From stoklund at 2pi.dk  Mon Apr 27 00:07:08 2009
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 27 Apr 2009 07:07:08 +0200
Subject: [llvm-commits] [PATCH] Add GR8_H register class to X86 backend
In-Reply-To: <EA2F88C0-9149-4867-8874-FBA4E75DAFC5@apple.com>
References: <74F36AB3-29C6-4FB0-8956-6F3CA337D62C@2pi.dk>
	<EA2F88C0-9149-4867-8874-FBA4E75DAFC5@apple.com>
Message-ID: <31D5DF3C-DC5D-474F-BE7F-C68E32D2DA1B@2pi.dk>


On 27/04/2009, at 02.37, Dan Gohman wrote:

> Thanks for pointing this out.  This looks right to me.  I'll apply the
> patch
> soon. Do you happen to have a testcase which shows the extra copies?

The coalescer is actually quite effective at eliminating the bad  
vregs, so I have not been able to find a difference when running  
normally. You can see the difference by disabling the coalescer:

	llc -join-liveintervals=0 < test/CodeGen/X86/h-registers-2.ll

Before applying this patch, an extra "movb %ah, %al" is inserted by  
LowerSubregs.

My other submitted patch, coalesce-phys-virt.patch, causes a bunch of  
test failures without this one.

Thanks,

/jakob
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From nicholas at mxc.ca  Mon Apr 27 00:09:44 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 27 Apr 2009 05:09:44 -0000
Subject: [llvm-commits] [llvm] r70185 -
	/llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp
Message-ID: <200904270509.n3R59iZK008740@zion.cs.uiuc.edu>

Author: nicholas
Date: Mon Apr 27 00:09:44 2009
New Revision: 70185

URL: http://llvm.org/viewvc/llvm-project?rev=70185&view=rev
Log:
Under unusual circumstances (jitting a function that causes the creation of
another stub, but then never calling the jitted function) can cause the JIT to
leave a stub in place. Judging by the comments this is a known deficiency, so
we're just not going to use AssertingVH for the StubToFunctionTy map.

Also shorten some lines longer than 80 columns.

This fixes the "make check" failure with ocaml on x86-64 linux.

Modified:
    llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp

Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp?rev=70185&r1=70184&r2=70185&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Mon Apr 27 00:09:44 2009
@@ -55,32 +55,35 @@
 //
 namespace {
   class JITResolverState {
+  public:
+    typedef std::map<AssertingVH<Function>, void*> FunctionToStubMapTy;
+    typedef std::map<void*, Function*> StubToFunctionMapTy;
+    typedef std::map<AssertingVH<GlobalValue>, void*> GlobalToIndirectSymMapTy;
   private:
     /// FunctionToStubMap - Keep track of the stub created for a particular
     /// function so that we can reuse them if necessary.
-    std::map<AssertingVH<Function>, void*> FunctionToStubMap;
+    FunctionToStubMapTy FunctionToStubMap;
 
     /// StubToFunctionMap - Keep track of the function that each stub
     /// corresponds to.
-    std::map<void*, AssertingVH<Function> > StubToFunctionMap;
+    StubToFunctionMapTy StubToFunctionMap;
 
     /// GlobalToIndirectSymMap - Keep track of the indirect symbol created for a
     /// particular GlobalVariable so that we can reuse them if necessary.
-    std::map<GlobalValue*, void*> GlobalToIndirectSymMap;
+    GlobalToIndirectSymMapTy GlobalToIndirectSymMap;
 
   public:
-    std::map<AssertingVH<Function>, void*>& getFunctionToStubMap(const MutexGuard& locked) {
+    FunctionToStubMapTy& getFunctionToStubMap(const MutexGuard& locked) {
       assert(locked.holds(TheJIT->lock));
       return FunctionToStubMap;
     }
 
-    std::map<void*, AssertingVH<Function> >& getStubToFunctionMap(const MutexGuard& locked) {
+    StubToFunctionMapTy& getStubToFunctionMap(const MutexGuard& locked) {
       assert(locked.holds(TheJIT->lock));
       return StubToFunctionMap;
     }
 
-    std::map<GlobalValue*, void*>&
-    getGlobalToIndirectSymMap(const MutexGuard& locked) {
+    GlobalToIndirectSymMapTy& getGlobalToIndirectSymMap(const MutexGuard& locked) {
       assert(locked.holds(TheJIT->lock));
       return GlobalToIndirectSymMap;
     }
@@ -89,6 +92,10 @@
   /// JITResolver - Keep track of, and resolve, call sites for functions that
   /// have not yet been compiled.
   class JITResolver {
+    typedef JITResolverState::FunctionToStubMapTy FunctionToStubMapTy;
+    typedef JITResolverState::StubToFunctionMapTy StubToFunctionMapTy;
+    typedef JITResolverState::GlobalToIndirectSymMapTy GlobalToIndirectSymMapTy;
+
     /// LazyResolverFn - The target lazy resolver function that we actually
     /// rewrite instructions to use.
     TargetJITInfo::LazyResolverFn LazyResolverFn;
@@ -276,18 +283,17 @@
                                     SmallVectorImpl<void*> &Ptrs) {
   MutexGuard locked(TheJIT->lock);
   
-  std::map<AssertingVH<Function>,void*> &FM =state.getFunctionToStubMap(locked);
-  std::map<GlobalValue*,void*> &GM = state.getGlobalToIndirectSymMap(locked);
+  FunctionToStubMapTy &FM = state.getFunctionToStubMap(locked);
+  GlobalToIndirectSymMapTy &GM = state.getGlobalToIndirectSymMap(locked);
   
-  for (std::map<AssertingVH<Function>,void*>::iterator i = FM.begin(),
-       e = FM.end(); i != e; ++i) {
+  for (FunctionToStubMapTy::iterator i = FM.begin(), e = FM.end(); i != e; ++i){
     Function *F = i->first;
     if (F->isDeclaration() && F->hasExternalLinkage()) {
       GVs.push_back(i->first);
       Ptrs.push_back(i->second);
     }
   }
-  for (std::map<GlobalValue*,void*>::iterator i = GM.begin(), e = GM.end();
+  for (GlobalToIndirectSymMapTy::iterator i = GM.begin(), e = GM.end();
        i != e; ++i) {
     GVs.push_back(i->first);
     Ptrs.push_back(i->second);
@@ -297,9 +303,9 @@
 GlobalValue *JITResolver::invalidateStub(void *Stub) {
   MutexGuard locked(TheJIT->lock);
   
-  std::map<AssertingVH<Function>,void*> &FM =state.getFunctionToStubMap(locked);
-  std::map<void*,AssertingVH<Function> > &SM=state.getStubToFunctionMap(locked);
-  std::map<GlobalValue*,void*> &GM = state.getGlobalToIndirectSymMap(locked);
+  FunctionToStubMapTy &FM = state.getFunctionToStubMap(locked);
+  StubToFunctionMapTy &SM = state.getStubToFunctionMap(locked);
+  GlobalToIndirectSymMapTy &GM = state.getGlobalToIndirectSymMap(locked);
   
   // Look up the cheap way first, to see if it's a function stub we are
   // invalidating.  If so, remove it from both the forward and reverse maps.
@@ -311,7 +317,7 @@
   }
   
   // Otherwise, it might be an indirect symbol stub.  Find it and remove it.
-  for (std::map<GlobalValue*,void*>::iterator i = GM.begin(), e = GM.end();
+  for (GlobalToIndirectSymMapTy::iterator i = GM.begin(), e = GM.end();
        i != e; ++i) {
     if (i->second != Stub)
       continue;
@@ -349,7 +355,7 @@
 
     // The address given to us for the stub may not be exactly right, it might be
     // a little bit after the stub.  As such, use upper_bound to find it.
-    std::map<void*, AssertingVH<Function> >::iterator I =
+    StubToFunctionMapTy::iterator I =
       JR.state.getStubToFunctionMap(locked).upper_bound(Stub);
     assert(I != JR.state.getStubToFunctionMap(locked).begin() &&
            "This is not a known stub!");




From wangmp at apple.com  Mon Apr 27 02:22:11 2009
From: wangmp at apple.com (Mon P Wang)
Date: Mon, 27 Apr 2009 07:22:11 -0000
Subject: [llvm-commits] [llvm] r70197 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.td
Message-ID: <200904270722.n3R7MCbB013330@zion.cs.uiuc.edu>

Author: wangmp
Date: Mon Apr 27 02:22:10 2009
New Revision: 70197

URL: http://llvm.org/viewvc/llvm-project?rev=70197&view=rev
Log:
Revised 68749 to allow matching of load/stores for address spaces < 256.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=70197&r1=70196&r2=70197&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Apr 27 02:22:10 2009
@@ -286,7 +286,7 @@
   LoadSDNode *LD = cast<LoadSDNode>(N);
   if (const Value *Src = LD->getSrcValue())
     if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() != 0)
+      if (PT->getAddressSpace() > 255)
         return false;
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::NON_EXTLOAD)
@@ -300,7 +300,7 @@
   LoadSDNode *LD = cast<LoadSDNode>(N);
   if (const Value *Src = LD->getSrcValue())
     if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() != 0)
+      if (PT->getAddressSpace() > 255)
         return false;
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::EXTLOAD)
@@ -312,7 +312,7 @@
   LoadSDNode *LD = cast<LoadSDNode>(N);
   if (const Value *Src = LD->getSrcValue())
     if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() != 0)
+      if (PT->getAddressSpace() > 255)
         return false;
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::NON_EXTLOAD)
@@ -326,7 +326,7 @@
   LoadSDNode *LD = cast<LoadSDNode>(N);
   if (const Value *Src = LD->getSrcValue())
     if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() != 0)
+      if (PT->getAddressSpace() > 255)
         return false;
   if (LD->isVolatile())
     return false;
@@ -348,14 +348,14 @@
 def loadi8  : PatFrag<(ops node:$ptr), (i8  (load node:$ptr)), [{
   if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
     if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() != 0)
+      if (PT->getAddressSpace() > 255)
         return false;
   return true;
 }]>;
 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
   if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
     if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() != 0)
+      if (PT->getAddressSpace() > 255)
         return false;
   return true;
 }]>;
@@ -363,21 +363,21 @@
 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
   if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
     if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() != 0)
+      if (PT->getAddressSpace() > 255)
         return false;
   return true;
 }]>;
 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
   if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
     if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() != 0)
+      if (PT->getAddressSpace() > 255)
         return false;
   return true;
 }]>;
 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
   if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
     if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() != 0)
+      if (PT->getAddressSpace() > 255)
         return false;
   return true;
 }]>;




From baldrick at free.fr  Mon Apr 27 03:52:58 2009
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 27 Apr 2009 10:52:58 +0200
Subject: [llvm-commits] [llvm] r70165 - in /llvm/trunk:
	docs/BitCodeFormat.html include/llvm/Bitcode/BitCodes.h
	include/llvm/Bitcode/BitstreamReader.h
	tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
In-Reply-To: <200904262221.n3QMLx0a028970@zion.cs.uiuc.edu>
References: <200904262221.n3QMLx0a028970@zion.cs.uiuc.edu>
Message-ID: <200904271052.58445.baldrick@free.fr>

> Add two new record types to the blockinfo block:
> BLOCKNAME and SETRECORDNAME.  This allows a bitcode
> file to be self describing with pretty names for 
> records and blocks in addition to numbers.  This
> enhances llvm-bcanalyzer to use this to print prettily.

Testcase?

Ciao,

Duncan.


From baldrick at free.fr  Mon Apr 27 06:21:46 2009
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 27 Apr 2009 11:21:46 -0000
Subject: [llvm-commits] [llvm] r70205 -
	/llvm/trunk/docs/GCCFEBuildInstrs.html
Message-ID: <200904271121.n3RBLlrV032630@zion.cs.uiuc.edu>

Author: baldrick
Date: Mon Apr 27 06:21:35 2009
New Revision: 70205

URL: http://llvm.org/viewvc/llvm-project?rev=70205&view=rev
Log:
Fix some confusion in the Ada f-e build instructions between
building without optimization and building with checking.

Modified:
    llvm/trunk/docs/GCCFEBuildInstrs.html

Modified: llvm/trunk/docs/GCCFEBuildInstrs.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GCCFEBuildInstrs.html?rev=70205&r1=70204&r2=70205&view=diff

==============================================================================
--- llvm/trunk/docs/GCCFEBuildInstrs.html (original)
+++ llvm/trunk/docs/GCCFEBuildInstrs.html Mon Apr 27 06:21:35 2009
@@ -157,29 +157,32 @@
   <li><p>Configure LLVM (here it is configured to install into <tt>/usr/local</tt>):</p>
 
 <pre class="doc_code">
-../llvm/configure --prefix=<b>/usr/local</b>
+../llvm/configure --prefix=<b>/usr/local</b> --enable-optimized --enable-assertions
 </pre>
 
       <p>If you have a multi-compiler setup and the C++ compiler is not the
       default, then you can configure like this:</p>
 
 <pre class="doc_code">
-CXX=<b>PATH_TO_C++_COMPILER</b> ../llvm/configure --prefix=<b>/usr/local</b>
+CXX=<b>PATH_TO_C++_COMPILER</b> ../llvm/configure --prefix=<b>/usr/local</b> --enable-optimized --enable-assertions
 </pre>
+
+      <p>To compile without checking (not recommended), replace
+      <tt>--enable-assertions</tt> with <tt>--disable-assertions</tt>.</p>
+
       </li>
 
-  <li><p>Build LLVM with checking enabled (use <tt>ENABLE_OPTIMIZED=1</tt> to
-         build without checking):</p>
+  <li><p>Build LLVM:</p>
 
 <pre class="doc_code">
-make ENABLE_OPTIMIZED=0
+make
 </pre>
       </li>
 
   <li><p>Install LLVM (optional):</p>
 
 <pre class="doc_code">
-make ENABLE_OPTIMIZED=0 install
+make install
 </pre>
       </li>
 
@@ -195,7 +198,8 @@
 
   <li><p>Configure llvm-gcc (here it is configured to install into <tt>/usr/local</tt>).
       The <tt>--enable-checking</tt> flag turns on sanity checks inside the compiler.
-      If you omit it then LLVM should be built with <tt>make ENABLE_OPTIMIZED=1</tt>.
+      To turn off these checks (not recommended), replace <tt>--enable-checking</tt>
+      with <tt>--disable-checking</tt>.
       Additional languages can be appended to the <tt>--enable-languages</tt> switch,
       for example <tt>--enable-languages=ada,c,c++</tt>.</p>
 




From gohman at apple.com  Mon Apr 27 10:08:45 2009
From: gohman at apple.com (Dan Gohman)
Date: Mon, 27 Apr 2009 15:08:45 -0000
Subject: [llvm-commits] [llvm] r70208 -
	/llvm/trunk/test/CodeGen/X86/2009-04-24.ll
Message-ID: <200904271508.n3RF8m98007543@zion.cs.uiuc.edu>

Author: djg
Date: Mon Apr 27 10:08:34 2009
New Revision: 70208

URL: http://llvm.org/viewvc/llvm-project?rev=70208&view=rev
Log:
Fix the syntax for a PR number in a test.

Modified:
    llvm/trunk/test/CodeGen/X86/2009-04-24.ll

Modified: llvm/trunk/test/CodeGen/X86/2009-04-24.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-24.ll?rev=70208&r1=70207&r2=70208&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-24.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-04-24.ll Mon Apr 27 10:08:34 2009
@@ -2,7 +2,7 @@
 ; RUN: grep {leal.*TLSGD.*___tls_get_addr} %t
 ; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=local -relocation-model=pic > %t2
 ; RUN: grep {leaq.*TLSGD.*__tls_get_addr} %t2
-; PR/4004
+; PR4004
 
 @i = thread_local global i32 15
 




From gohman at apple.com  Mon Apr 27 10:13:35 2009
From: gohman at apple.com (Dan Gohman)
Date: Mon, 27 Apr 2009 15:13:35 -0000
Subject: [llvm-commits] [llvm] r70209 - in /llvm/trunk/lib/Target/X86:
 X86Instr64bit.td X86InstrInfo.td
Message-ID: <200904271513.n3RFDa7h007692@zion.cs.uiuc.edu>

Author: djg
Date: Mon Apr 27 10:13:28 2009
New Revision: 70209

URL: http://llvm.org/viewvc/llvm-project?rev=70209&view=rev
Log:
Break up long multi-mnemonic strings into separate lines for readability.

Modified:
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=70209&r1=70208&r2=70209&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Mon Apr 27 10:13:28 2009
@@ -1313,7 +1313,11 @@
             XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
     Uses = [RSP] in
 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64imm:$sym),
-    ".byte\t0x66; leaq\t${sym:mem}(%rip), %rdi; .word\t0x6666; rex64;call\t__tls_get_addr at PLT",
+                   ".byte\t0x66; "
+                   "leaq\t${sym:mem}(%rip), %rdi; "
+                   ".word\t0x6666; "
+                   "rex64; "
+                   "call\t__tls_get_addr at PLT",
                   [(X86tlsaddr tglobaltlsaddr:$sym)]>,
                   Requires<[In64BitMode]>;
 
@@ -1328,14 +1332,16 @@
 
 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
-               "lock\n\tcmpxchgq\t$swap,$ptr",
+               "lock\n\t"
+               "cmpxchgq\t$swap,$ptr",
                [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
 }
 
 let Constraints = "$val = $dst" in {
 let Defs = [EFLAGS] in
 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
-               "lock\n\txadd\t$val, $ptr", 
+               "lock\n\t"
+               "xadd\t$val, $ptr",
                [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
                 TB, LOCK;
 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=70209&r1=70208&r2=70209&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Apr 27 10:13:28 2009
@@ -469,7 +469,8 @@
 // PIC base
 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
   def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
-                      "call\t$label\n\tpop{l}\t$reg", []>;
+                      "call\t$label\n\t"
+                      "pop{l}\t$reg", []>;
 
 //===----------------------------------------------------------------------===//
 //  Control Flow Instructions...
@@ -2986,7 +2987,8 @@
             XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
     Uses = [ESP, EBX] in
 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32imm:$sym),
-                  "leal\t${sym:mem}(,%ebx,1), %eax; call\t___tls_get_addr at PLT",
+                  "leal\t${sym:mem}(,%ebx,1), %eax; "
+                  "call\t___tls_get_addr at PLT",
                   [(X86tlsaddr tglobaltlsaddr:$sym)]>,
                   Requires<[In32BitMode]>;
 
@@ -3038,38 +3040,45 @@
 // Atomic compare and swap.
 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
-               "lock\n\tcmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
+               "lock\n\t"
+               "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
                [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
 }
 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
-               "lock\n\tcmpxchg8b\t$ptr",
+               "lock\n\t"
+               "cmpxchg8b\t$ptr",
                [(X86cas8 addr:$ptr)]>, TB, LOCK;
 }
 
 let Defs = [AX, EFLAGS], Uses = [AX] in {
 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
-               "lock\n\tcmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
+               "lock\n\t"
+               "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
                [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
 }
 let Defs = [AL, EFLAGS], Uses = [AL] in {
 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
-               "lock\n\tcmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
+               "lock\n\t"
+               "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
                [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
 }
 
 // Atomic exchange and add
 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
-               "lock\n\txadd{l}\t{$val, $ptr|$ptr, $val}", 
+               "lock\n\t"
+               "xadd{l}\t{$val, $ptr|$ptr, $val}",
                [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
                 TB, LOCK;
 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
-               "lock\n\txadd{w}\t{$val, $ptr|$ptr, $val}", 
+               "lock\n\t"
+               "xadd{w}\t{$val, $ptr|$ptr, $val}",
                [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
                 TB, OpSize, LOCK;
 def LXADD8  : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
-               "lock\n\txadd{b}\t{$val, $ptr|$ptr, $val}", 
+               "lock\n\t"
+               "xadd{b}\t{$val, $ptr|$ptr, $val}",
                [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
                 TB, LOCK;
 }




From gohman at apple.com  Mon Apr 27 11:33:27 2009
From: gohman at apple.com (Dan Gohman)
Date: Mon, 27 Apr 2009 16:33:27 -0000
Subject: [llvm-commits] [llvm] r70210 - in /llvm/trunk/lib/Target/X86:
 X86FastISel.cpp X86Instr64bit.td X86InstrInfo.cpp X86InstrInfo.td
 X86RegisterInfo.td
Message-ID: <200904271633.n3RGXU4M010445@zion.cs.uiuc.edu>

Author: djg
Date: Mon Apr 27 11:33:14 2009
New Revision: 70210

URL: http://llvm.org/viewvc/llvm-project?rev=70210&view=rev
Log:
Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,
GR32_ABCD, and GR64_ABCD, respectively, to help describe them.

Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=70210&r1=70209&r2=70210&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Mon Apr 27 11:33:14 2009
@@ -996,10 +996,10 @@
     // Unhandled operand.  Halt "fast" selection and bail.
     return false;
 
-  // First issue a copy to GR16_ or GR32_.
+  // First issue a copy to GR16_ABCD or GR32_ABCD.
   unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
   const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
-    ? X86::GR16_RegisterClass : X86::GR32_RegisterClass;
+    ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
   unsigned CopyReg = createResultReg(CopyRC);
   BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
 

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=70210&r1=70209&r2=70210&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Mon Apr 27 11:33:14 2009
@@ -1594,18 +1594,18 @@
           (SUBREG_TO_REG
             (i64 0),
             (MOVZX32_NOREXrr8
-              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_),
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
                               x86_subreg_8bit_hi)),
             x86_subreg_32bit)>;
 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
           (MOVZX32_NOREXrr8
-            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
                             x86_subreg_8bit_hi))>,
       Requires<[In64BitMode]>;
 def : Pat<(srl_su GR16:$src, (i8 8)),
           (EXTRACT_SUBREG
             (MOVZX32_NOREXrr8
-              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
                               x86_subreg_8bit_hi)),
             x86_subreg_16bit)>,
       Requires<[In64BitMode]>;
@@ -1614,18 +1614,18 @@
 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
           (MOV8mr_NOREX
             addr:$dst,
-            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_),
+            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
                             x86_subreg_8bit_hi))>;
 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
           (MOV8mr_NOREX
             addr:$dst,
-            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
                             x86_subreg_8bit_hi))>,
       Requires<[In64BitMode]>;
 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
           (MOV8mr_NOREX
             addr:$dst,
-            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
                             x86_subreg_8bit_hi))>,
       Requires<[In64BitMode]>;
 

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=70210&r1=70209&r2=70210&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Apr 27 11:33:14 2009
@@ -1681,13 +1681,13 @@
         Opc = X86::MOV8rr_NOREX;
       else
         Opc = X86::MOV8rr;
-    } else if (CommonRC == &X86::GR64_RegClass) {
+    } else if (CommonRC == &X86::GR64_ABCDRegClass) {
       Opc = X86::MOV64rr;
-    } else if (CommonRC == &X86::GR32_RegClass) {
+    } else if (CommonRC == &X86::GR32_ABCDRegClass) {
       Opc = X86::MOV32rr;
-    } else if (CommonRC == &X86::GR16_RegClass) {
+    } else if (CommonRC == &X86::GR16_ABCDRegClass) {
       Opc = X86::MOV16rr;
-    } else if (CommonRC == &X86::GR8_RegClass) {
+    } else if (CommonRC == &X86::GR8_ABCDRegClass) {
       Opc = X86::MOV8rr;
     } else if (CommonRC == &X86::GR64_NOREXRegClass) {
       Opc = X86::MOV64rr;
@@ -1802,13 +1802,13 @@
     Opc = X86::MOV16mr;
   } else if (RC == &X86::GR8RegClass) {
     Opc = X86::MOV8mr;
-  } else if (RC == &X86::GR64_RegClass) {
+  } else if (RC == &X86::GR64_ABCDRegClass) {
     Opc = X86::MOV64mr;
-  } else if (RC == &X86::GR32_RegClass) {
+  } else if (RC == &X86::GR32_ABCDRegClass) {
     Opc = X86::MOV32mr;
-  } else if (RC == &X86::GR16_RegClass) {
+  } else if (RC == &X86::GR16_ABCDRegClass) {
     Opc = X86::MOV16mr;
-  } else if (RC == &X86::GR8_RegClass) {
+  } else if (RC == &X86::GR8_ABCDRegClass) {
     Opc = X86::MOV8mr;
   } else if (RC == &X86::GR64_NOREXRegClass) {
     Opc = X86::MOV64mr;
@@ -1882,13 +1882,13 @@
     Opc = X86::MOV16rm;
   } else if (RC == &X86::GR8RegClass) {
     Opc = X86::MOV8rm;
-  } else if (RC == &X86::GR64_RegClass) {
+  } else if (RC == &X86::GR64_ABCDRegClass) {
     Opc = X86::MOV64rm;
-  } else if (RC == &X86::GR32_RegClass) {
+  } else if (RC == &X86::GR32_ABCDRegClass) {
     Opc = X86::MOV32rm;
-  } else if (RC == &X86::GR16_RegClass) {
+  } else if (RC == &X86::GR16_ABCDRegClass) {
     Opc = X86::MOV16rm;
-  } else if (RC == &X86::GR8_RegClass) {
+  } else if (RC == &X86::GR8_ABCDRegClass) {
     Opc = X86::MOV8rm;
   } else if (RC == &X86::GR64_NOREXRegClass) {
     Opc = X86::MOV64rm;

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=70210&r1=70209&r2=70210&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Apr 27 11:33:14 2009
@@ -3372,12 +3372,12 @@
           (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
 // r & (2^8-1) ==> movz
 def : Pat<(and GR32:$src1, 0xff),
-          (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_),
+          (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
                                       x86_subreg_8bit))>,
       Requires<[In32BitMode]>;
 // r & (2^8-1) ==> movz
 def : Pat<(and GR16:$src1, 0xff),
-          (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_),
+          (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
                                       x86_subreg_8bit))>,
       Requires<[In32BitMode]>;
 
@@ -3385,11 +3385,11 @@
 def : Pat<(sext_inreg GR32:$src, i16),
           (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
 def : Pat<(sext_inreg GR32:$src, i8),
-          (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+          (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
                                       x86_subreg_8bit))>,
       Requires<[In32BitMode]>;
 def : Pat<(sext_inreg GR16:$src, i8),
-          (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+          (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
                                       x86_subreg_8bit))>,
       Requires<[In32BitMode]>;
 
@@ -3397,32 +3397,32 @@
 def : Pat<(i16 (trunc GR32:$src)),
           (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
 def : Pat<(i8 (trunc GR32:$src)),
-          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
                           x86_subreg_8bit)>,
       Requires<[In32BitMode]>;
 def : Pat<(i8 (trunc GR16:$src)),
-          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
                           x86_subreg_8bit)>,
       Requires<[In32BitMode]>;
 
 // h-register tricks
 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
-          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
                           x86_subreg_8bit_hi)>,
       Requires<[In32BitMode]>;
 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
-          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
                           x86_subreg_8bit_hi)>,
       Requires<[In32BitMode]>;
 def : Pat<(srl_su GR16:$src, (i8 8)),
           (EXTRACT_SUBREG
             (MOVZX32rr8
-              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
                               x86_subreg_8bit_hi)),
             x86_subreg_16bit)>,
       Requires<[In32BitMode]>;
 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
-          (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+          (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
                                       x86_subreg_8bit_hi))>,
       Requires<[In32BitMode]>;
 

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=70210&r1=70209&r2=70210&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Mon Apr 27 11:33:14 2009
@@ -461,21 +461,21 @@
 }
 
 
-// GR8_, GR16_, GR32_, GR64_ - Subclasses of GR8, GR16, GR32, and GR64
-// which contain just the "a" "b", "c", and "d" registers. On x86-32,
-// GR16_ and GR32_ are classes for registers that support 8-bit subreg
-// operations. On x86-64, GR16_, GR32_, and GR64_ are classes for registers
-// that support 8-bit h-register operations.
-def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
+// GR8_ABCD, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of GR8, GR16, GR32,
+// and GR64 which contain just the "a" "b", "c", and "d" registers. On x86-32,
+// GR16_ABCD and GR32_ABCD are classes for registers that support 8-bit subreg
+// operations. On x86-64, GR16_ABCD, GR32_ABCD, and GR64_ABCD are classes for
+// registers that support 8-bit h-register operations.
+def GR8_ABCD : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
 }
-def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
-  let SubRegClassList = [GR8_, GR8_];
+def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
+  let SubRegClassList = [GR8_ABCD, GR8_ABCD];
 }
-def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
-  let SubRegClassList = [GR8_, GR8_, GR16_];
+def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
+  let SubRegClassList = [GR8_ABCD, GR8_ABCD, GR16_ABCD];
 }
-def GR64_ : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
-  let SubRegClassList = [GR8_, GR8_, GR16_, GR32_];
+def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
+  let SubRegClassList = [GR8_ABCD, GR8_ABCD, GR16_ABCD, GR32_ABCD];
 }
 
 // GR8_NOREX, GR16_NOREX, GR32_NOREX, GR64_NOREX - Subclasses of




From gohman at apple.com  Mon Apr 27 11:41:37 2009
From: gohman at apple.com (Dan Gohman)
Date: Mon, 27 Apr 2009 16:41:37 -0000
Subject: [llvm-commits] [llvm] r70211 - in /llvm/trunk/lib/Target/X86:
 X86InstrInfo.cpp X86InstrInfo.td X86RegisterInfo.td
Message-ID: <200904271641.n3RGfbf9010832@zion.cs.uiuc.edu>

Author: djg
Date: Mon Apr 27 11:41:36 2009
New Revision: 70211

URL: http://llvm.org/viewvc/llvm-project?rev=70211&view=rev
Log:
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these
to precisely describe the h-register subreg register classes.
Thanks to Jakob Stoklund Olesen for spotting this and for the
initial patch!

Also, make getStoreRegOpcode and getLoadRegOpcode aware of the
needs of h registers.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=70211&r1=70210&r2=70211&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Apr 27 11:41:36 2009
@@ -1645,7 +1645,7 @@
 
 /// isHReg - Test if the given register is a physical h register.
 static bool isHReg(unsigned Reg) {
-  return Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH;
+  return X86::GR8_ABCD_HRegClass.contains(Reg);
 }
 
 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
@@ -1674,7 +1674,7 @@
     } else if (CommonRC == &X86::GR16RegClass) {
       Opc = X86::MOV16rr;
     } else if (CommonRC == &X86::GR8RegClass) {
-      // Copying two or from a physical H register on x86-64 requires a NOREX
+      // Copying to or from a physical H register on x86-64 requires a NOREX
       // move.  Otherwise use a normal move.
       if ((isHReg(DestReg) || isHReg(SrcReg)) &&
           TM.getSubtarget<X86Subtarget>().is64Bit())
@@ -1687,8 +1687,13 @@
       Opc = X86::MOV32rr;
     } else if (CommonRC == &X86::GR16_ABCDRegClass) {
       Opc = X86::MOV16rr;
-    } else if (CommonRC == &X86::GR8_ABCDRegClass) {
+    } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
       Opc = X86::MOV8rr;
+    } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
+      if (TM.getSubtarget<X86Subtarget>().is64Bit())
+        Opc = X86::MOV8rr_NOREX;
+      else
+        Opc = X86::MOV8rr;
     } else if (CommonRC == &X86::GR64_NOREXRegClass) {
       Opc = X86::MOV64rr;
     } else if (CommonRC == &X86::GR32_NOREXRegClass) {
@@ -1791,8 +1796,10 @@
   return false;
 }
 
-static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
-                                  bool isStackAligned) {
+static unsigned getStoreRegOpcode(unsigned SrcReg,
+                                  const TargetRegisterClass *RC,
+                                  bool isStackAligned,
+                                  TargetMachine &TM) {
   unsigned Opc = 0;
   if (RC == &X86::GR64RegClass) {
     Opc = X86::MOV64mr;
@@ -1801,15 +1808,26 @@
   } else if (RC == &X86::GR16RegClass) {
     Opc = X86::MOV16mr;
   } else if (RC == &X86::GR8RegClass) {
-    Opc = X86::MOV8mr;
+    // Copying to or from a physical H register on x86-64 requires a NOREX
+    // move.  Otherwise use a normal move.
+    if (isHReg(SrcReg) &&
+        TM.getSubtarget<X86Subtarget>().is64Bit())
+      Opc = X86::MOV8mr_NOREX;
+    else
+      Opc = X86::MOV8mr;
   } else if (RC == &X86::GR64_ABCDRegClass) {
     Opc = X86::MOV64mr;
   } else if (RC == &X86::GR32_ABCDRegClass) {
     Opc = X86::MOV32mr;
   } else if (RC == &X86::GR16_ABCDRegClass) {
     Opc = X86::MOV16mr;
-  } else if (RC == &X86::GR8_ABCDRegClass) {
+  } else if (RC == &X86::GR8_ABCD_LRegClass) {
     Opc = X86::MOV8mr;
+  } else if (RC == &X86::GR8_ABCD_HRegClass) {
+    if (TM.getSubtarget<X86Subtarget>().is64Bit())
+      Opc = X86::MOV8mr_NOREX;
+    else
+      Opc = X86::MOV8mr;
   } else if (RC == &X86::GR64_NOREXRegClass) {
     Opc = X86::MOV64mr;
   } else if (RC == &X86::GR32_NOREXRegClass) {
@@ -1848,7 +1866,7 @@
   const MachineFunction &MF = *MBB.getParent();
   bool isAligned = (RI.getStackAlignment() >= 16) ||
     RI.needsStackRealignment(MF);
-  unsigned Opc = getStoreRegOpcode(RC, isAligned);
+  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
   DebugLoc DL = DebugLoc::getUnknownLoc();
   if (MI != MBB.end()) DL = MI->getDebugLoc();
   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
@@ -1862,7 +1880,7 @@
                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
   bool isAligned = (RI.getStackAlignment() >= 16) ||
     RI.needsStackRealignment(MF);
-  unsigned Opc = getStoreRegOpcode(RC, isAligned);
+  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
   DebugLoc DL = DebugLoc::getUnknownLoc();
   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
@@ -1871,8 +1889,10 @@
   NewMIs.push_back(MIB);
 }
 
-static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
-                                 bool isStackAligned) {
+static unsigned getLoadRegOpcode(unsigned DestReg,
+                                 const TargetRegisterClass *RC,
+                                 bool isStackAligned,
+                                 const TargetMachine &TM) {
   unsigned Opc = 0;
   if (RC == &X86::GR64RegClass) {
     Opc = X86::MOV64rm;
@@ -1881,15 +1901,26 @@
   } else if (RC == &X86::GR16RegClass) {
     Opc = X86::MOV16rm;
   } else if (RC == &X86::GR8RegClass) {
-    Opc = X86::MOV8rm;
+    // Copying to or from a physical H register on x86-64 requires a NOREX
+    // move.  Otherwise use a normal move.
+    if (isHReg(DestReg) &&
+        TM.getSubtarget<X86Subtarget>().is64Bit())
+      Opc = X86::MOV8rm_NOREX;
+    else
+      Opc = X86::MOV8rm;
   } else if (RC == &X86::GR64_ABCDRegClass) {
     Opc = X86::MOV64rm;
   } else if (RC == &X86::GR32_ABCDRegClass) {
     Opc = X86::MOV32rm;
   } else if (RC == &X86::GR16_ABCDRegClass) {
     Opc = X86::MOV16rm;
-  } else if (RC == &X86::GR8_ABCDRegClass) {
+  } else if (RC == &X86::GR8_ABCD_LRegClass) {
     Opc = X86::MOV8rm;
+  } else if (RC == &X86::GR8_ABCD_HRegClass) {
+    if (TM.getSubtarget<X86Subtarget>().is64Bit())
+      Opc = X86::MOV8rm_NOREX;
+    else
+      Opc = X86::MOV8rm;
   } else if (RC == &X86::GR64_NOREXRegClass) {
     Opc = X86::MOV64rm;
   } else if (RC == &X86::GR32_NOREXRegClass) {
@@ -1928,7 +1959,7 @@
   const MachineFunction &MF = *MBB.getParent();
   bool isAligned = (RI.getStackAlignment() >= 16) ||
     RI.needsStackRealignment(MF);
-  unsigned Opc = getLoadRegOpcode(RC, isAligned);
+  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
   DebugLoc DL = DebugLoc::getUnknownLoc();
   if (MI != MBB.end()) DL = MI->getDebugLoc();
   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
@@ -1940,7 +1971,7 @@
                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
   bool isAligned = (RI.getStackAlignment() >= 16) ||
     RI.needsStackRealignment(MF);
-  unsigned Opc = getLoadRegOpcode(RC, isAligned);
+  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
   DebugLoc DL = DebugLoc::getUnknownLoc();
   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
@@ -2455,9 +2486,8 @@
     MVT VT = *RC->vt_begin();
     bool isAligned = (RI.getStackAlignment() >= 16) ||
       RI.needsStackRealignment(MF);
-    Load = DAG.getTargetNode(getLoadRegOpcode(RC, isAligned), dl,
-                             VT, MVT::Other,
-                             &AddrOps[0], AddrOps.size());
+    Load = DAG.getTargetNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
+                             VT, MVT::Other, &AddrOps[0], AddrOps.size());
     NewNodes.push_back(Load);
   }
 
@@ -2489,8 +2519,10 @@
     AddrOps.push_back(Chain);
     bool isAligned = (RI.getStackAlignment() >= 16) ||
       RI.needsStackRealignment(MF);
-    SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, isAligned), dl,
-                                      MVT::Other, &AddrOps[0], AddrOps.size());
+    SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(0, DstRC,
+                                                        isAligned, TM),
+                                      dl, MVT::Other,
+                                      &AddrOps[0], AddrOps.size());
     NewNodes.push_back(Store);
   }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=70211&r1=70210&r2=70211&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Apr 27 11:41:36 2009
@@ -784,9 +784,9 @@
                 "mov{l}\t{$src, $dst|$dst, $src}",
                 [(store GR32:$src, addr:$dst)]>;
 
-// Versions of MOV8rr and MOV8mr that use i8mem_NOREX and GR8_NOREX so that they
-// can be used for copying and storing h registers, which can't be encoded when
-// a REX prefix is present.
+// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
+// that they can be used for copying and storing h registers, which can't be
+// encoded when a REX prefix is present.
 let neverHasSideEffects = 1 in
 def MOV8rr_NOREX : I<0x88, MRMDestReg,
                      (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
@@ -794,6 +794,10 @@
 def MOV8mr_NOREX : I<0x88, MRMDestMem,
                      (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
                      "mov{b}\t{$src, $dst|$dst, $src}  # NOREX", []>;
+let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
+def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
+                     (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
+                     "mov{b}\t{$src, $dst|$dst, $src}  # NOREX", []>;
 
 //===----------------------------------------------------------------------===//
 //  Fixed-Register Multiplication and Division Instructions...

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=70211&r1=70210&r2=70211&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Mon Apr 27 11:41:36 2009
@@ -461,21 +461,24 @@
 }
 
 
-// GR8_ABCD, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of GR8, GR16, GR32,
-// and GR64 which contain just the "a" "b", "c", and "d" registers. On x86-32,
-// GR16_ABCD and GR32_ABCD are classes for registers that support 8-bit subreg
-// operations. On x86-64, GR16_ABCD, GR32_ABCD, and GR64_ABCD are classes for
-// registers that support 8-bit h-register operations.
-def GR8_ABCD : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
+// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
+// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
+// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
+// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
+// and GR64_ABCD are classes for registers that support 8-bit h-register
+// operations.
+def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
+}
+def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]> {
 }
 def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
-  let SubRegClassList = [GR8_ABCD, GR8_ABCD];
+  let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H];
 }
 def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
-  let SubRegClassList = [GR8_ABCD, GR8_ABCD, GR16_ABCD];
+  let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD];
 }
 def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
-  let SubRegClassList = [GR8_ABCD, GR8_ABCD, GR16_ABCD, GR32_ABCD];
+  let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD];
 }
 
 // GR8_NOREX, GR16_NOREX, GR32_NOREX, GR64_NOREX - Subclasses of




From stoklund at 2pi.dk  Mon Apr 27 12:01:43 2009
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 27 Apr 2009 19:01:43 +0200
Subject: [llvm-commits] [PATCH] Annotate virtual registers with register
	class in debug output
Message-ID: <BA3F4AA9-1FCA-47C4-BD50-C13663E2FE69@2pi.dk>

I am using this patch when working on the Blackfin backend. Now that  
X86 is gaining a decent set of register classes, it might be generally  
useful.

It prints machine code like this:

	%reg1025GR32<def> = MOV32rr %ESI
	%reg1024GR64<def> = MOV64rr %RDI
	%reg1026GR32_ABCD<def> = MOV32rr %reg1025GR32
	%reg1027GR8_ABCD_H<def> = EXTRACT_SUBREG %reg1026GR32_ABCD, 2
	%reg1028GR32_NOREX<def> = MOVZX32_NOREXrr8 %reg1027GR8_ABCD_H
	%EAX<def> = MOV32rr %reg1028GR32_NOREX
	RET

What do you think? Too much clutter?

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From evan.cheng at apple.com  Mon Apr 27 12:35:21 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Apr 2009 17:35:21 -0000
Subject: [llvm-commits] [llvm] r70212 -
	/llvm/trunk/lib/CodeGen/LiveInterval.cpp
Message-ID: <200904271735.n3RHZLX5013201@zion.cs.uiuc.edu>

Author: evancheng
Date: Mon Apr 27 12:35:19 2009
New Revision: 70212

URL: http://llvm.org/viewvc/llvm-project?rev=70212&view=rev
Log:
Also delete last unused val#.

Modified:
    llvm/trunk/lib/CodeGen/LiveInterval.cpp

Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=70212&r1=70211&r2=70212&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Mon Apr 27 12:35:19 2009
@@ -629,6 +629,12 @@
       UnusedValNo = 0;
     }
   }
+
+  if (UnusedValNo) {
+    // Delete the last unused val#.
+    valnos.pop_back();
+    UnusedValNo->~VNInfo();
+  }
 }
 
 void LiveInterval::MergeInClobberRange(unsigned Start, unsigned End,




From evan.cheng at apple.com  Mon Apr 27 12:36:47 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Apr 2009 17:36:47 -0000
Subject: [llvm-commits] [llvm] r70213 - in /llvm/trunk:
 lib/CodeGen/LiveIntervalAnalysis.cpp
 test/CodeGen/X86/2009-04-27-LiveIntervalsAssert.ll
Message-ID: <200904271736.n3RHamOw013268@zion.cs.uiuc.edu>

Author: evancheng
Date: Mon Apr 27 12:36:47 2009
New Revision: 70213

URL: http://llvm.org/viewvc/llvm-project?rev=70213&view=rev
Log:
Fix PR4056. It's possible a physical register def is dead if its implicit use is deleted by two-address pass.

Added:
    llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert.ll
Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=70213&r1=70212&r2=70213&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Mon Apr 27 12:36:47 2009
@@ -627,8 +627,8 @@
   
   // The only case we should have a dead physreg here without a killing or
   // instruction where we know it's dead is if it is live-in to the function
-  // and never used.
-  assert(!CopyMI && "physreg was not killed in defining block!");
+  // and never used. Another possible case is the implicit use of the
+  // physical register has been deleted by two-address pass.
   end = start + 1;
 
 exit:

Added: llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert.ll?rev=70213&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert.ll Mon Apr 27 12:36:47 2009
@@ -0,0 +1,24 @@
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9
+; PR4056
+
+define void @int163(i32 %p_4, i32 %p_5) nounwind {
+entry:
+	%0 = tail call i32 @bar(i32 1) nounwind		; <i32> [#uses=2]
+	%1 = icmp sgt i32 %0, 7		; <i1> [#uses=1]
+	br i1 %1, label %foo.exit, label %bb.i
+
+bb.i:		; preds = %entry
+	%2 = lshr i32 1, %0		; <i32> [#uses=1]
+	%3 = icmp eq i32 %2, 0		; <i1> [#uses=1]
+	%4 = zext i1 %3 to i32		; <i32> [#uses=1]
+	%.p_5 = shl i32 %p_5, %4		; <i32> [#uses=1]
+	br label %foo.exit
+
+foo.exit:		; preds = %bb.i, %entry
+	%5 = phi i32 [ %.p_5, %bb.i ], [ %p_5, %entry ]		; <i32> [#uses=1]
+	%6 = icmp eq i32 %5, 0		; <i1> [#uses=0]
+	%7 = tail call i32 @bar(i32 %p_5) nounwind		; <i32> [#uses=0]
+	ret void
+}
+
+declare i32 @bar(i32)




From sabre at nondot.org  Mon Apr 27 12:59:34 2009
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 27 Apr 2009 17:59:34 -0000
Subject: [llvm-commits] [llvm] r70214 -
	/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
Message-ID: <200904271759.n3RHxYlY014086@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr 27 12:59:34 2009
New Revision: 70214

URL: http://llvm.org/viewvc/llvm-project?rev=70214&view=rev
Log:
clean up the output of llvm-bcanalyzer by using printf
instead of ostreams for formatting.

Modified:
    llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp

Modified: llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp?rev=70214&r1=70213&r2=70214&view=diff

==============================================================================
--- llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp (original)
+++ llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Mon Apr 27 12:59:34 2009
@@ -245,6 +245,9 @@
   }
 }
 
+struct PerRecordStats {
+  unsigned NumInstances;
+};
 
 struct PerBlockIDStats {
   /// NumInstances - This the number of times this block ID has been seen.
@@ -264,7 +267,7 @@
   unsigned NumRecords, NumAbbreviatedRecords;
   
   /// CodeFreq - Keep track of the number of times we see each code.
-  std::vector<unsigned> CodeFreq;
+  std::vector<PerRecordStats> CodeFreq;
   
   PerBlockIDStats()
     : NumInstances(0), NumBits(0),
@@ -375,7 +378,7 @@
       // Increment the # occurrences of this code.
       if (BlockStats.CodeFreq.size() <= Code)
         BlockStats.CodeFreq.resize(Code+1);
-      BlockStats.CodeFreq[Code]++;
+      BlockStats.CodeFreq[Code].NumInstances++;
       
       if (Dump) {
         std::cerr << Indent << "  <";
@@ -419,7 +422,11 @@
 }
 
 static void PrintSize(double Bits) {
-  std::cerr << Bits << "b/" << Bits/8 << "B/" << Bits/32 << "W";
+  fprintf(stderr, "%.2f/%.2fB/%lluW", Bits, Bits/8,(unsigned long long)Bits/32);
+}
+static void PrintSize(uint64_t Bits) {
+  fprintf(stderr, "%llub/%.2fB/%lluW", (unsigned long long)Bits,
+          (double)Bits/8, (unsigned long long)Bits/32);
 }
 
 
@@ -532,19 +539,21 @@
     if (!NoHistogram && !Stats.CodeFreq.empty()) {
       std::vector<std::pair<unsigned, unsigned> > FreqPairs;  // <freq,code>
       for (unsigned i = 0, e = Stats.CodeFreq.size(); i != e; ++i)
-        if (unsigned Freq = Stats.CodeFreq[i])
+        if (unsigned Freq = Stats.CodeFreq[i].NumInstances)
           FreqPairs.push_back(std::make_pair(Freq, i));
       std::stable_sort(FreqPairs.begin(), FreqPairs.end());
       std::reverse(FreqPairs.begin(), FreqPairs.end());
       
-      std::cerr << "\tCode Histogram:\n";
+      std::cerr << "\tRecord Histogram:\n";
+      fprintf(stderr, "\t\t  Count   Record Kind\n");
       for (unsigned i = 0, e = FreqPairs.size(); i != e; ++i) {
-        std::cerr << "\t\t" << FreqPairs[i].first << "\t";
+        fprintf(stderr, "\t\t%7d   ", FreqPairs[i].first);
+        
         if (const char *CodeName = 
               GetCodeName(FreqPairs[i].second, I->first, StreamFile))
-          std::cerr << CodeName << "\n";
+          fprintf(stderr, "%s\n", CodeName);
         else
-          std::cerr << "UnknownCode" << FreqPairs[i].second << "\n";
+          fprintf(stderr, "UnknownCode%d\n", FreqPairs[i].second);
       }
       std::cerr << "\n";
       




From sabre at nondot.org  Mon Apr 27 13:15:28 2009
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 27 Apr 2009 18:15:28 -0000
Subject: [llvm-commits] [llvm] r70215 -
	/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
Message-ID: <200904271815.n3RIFSmo014579@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr 27 13:15:27 2009
New Revision: 70215

URL: http://llvm.org/viewvc/llvm-project?rev=70215&view=rev
Log:
Print statistics for each record kind saying the number of bits
and % abbreviated.  For example:

	Record Histogram:
		  Count    # Bits   % Abv  Record Kind
		  25738   3424174  100.00  SM_SLOC_INSTANTIATION_ENTRY
		    814    562079  100.00  SM_SLOC_FILE_ENTRY
		    798     34110          SM_HEADER_FILE_INFO
		      3     91104  100.00  SM_SLOC_BUFFER_BLOB
		      3       498  100.00  SM_SLOC_BUFFER_ENTRY
		      1       465          SM_LINE_TABLE


Modified:
    llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp

Modified: llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp?rev=70215&r1=70214&r2=70215&view=diff

==============================================================================
--- llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp (original)
+++ llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Mon Apr 27 13:15:27 2009
@@ -247,6 +247,10 @@
 
 struct PerRecordStats {
   unsigned NumInstances;
+  unsigned NumAbbrev;
+  uint64_t TotalBits;
+  
+  PerRecordStats() : NumInstances(0), NumAbbrev(0), TotalBits(0) {}
 };
 
 struct PerBlockIDStats {
@@ -332,6 +336,8 @@
     if (Stream.AtEndOfStream())
       return Error("Premature end of bitstream");
 
+    uint64_t RecordStartBit = Stream.GetCurrentBitNo();
+    
     // Read the code for this record.
     unsigned AbbrevID = Stream.ReadCode();
     switch (AbbrevID) {
@@ -375,11 +381,17 @@
       unsigned BlobLen = 0;
       unsigned Code = Stream.ReadRecord(AbbrevID, Record, BlobStart, BlobLen);
 
+        
+        
       // Increment the # occurrences of this code.
       if (BlockStats.CodeFreq.size() <= Code)
         BlockStats.CodeFreq.resize(Code+1);
       BlockStats.CodeFreq[Code].NumInstances++;
-      
+      BlockStats.CodeFreq[Code].TotalBits +=
+        Stream.GetCurrentBitNo()-RecordStartBit;
+      if (AbbrevID != bitc::UNABBREV_RECORD)
+        BlockStats.CodeFreq[Code].NumAbbrev++;
+        
       if (Dump) {
         std::cerr << Indent << "  <";
         if (const char *CodeName =
@@ -545,9 +557,18 @@
       std::reverse(FreqPairs.begin(), FreqPairs.end());
       
       std::cerr << "\tRecord Histogram:\n";
-      fprintf(stderr, "\t\t  Count   Record Kind\n");
+      fprintf(stderr, "\t\t  Count    # Bits   %% Abv  Record Kind\n");
       for (unsigned i = 0, e = FreqPairs.size(); i != e; ++i) {
-        fprintf(stderr, "\t\t%7d   ", FreqPairs[i].first);
+        const PerRecordStats &RecStats = Stats.CodeFreq[FreqPairs[i].second];
+        
+        fprintf(stderr, "\t\t%7d %9llu ", RecStats.NumInstances,
+                RecStats.TotalBits);
+        
+        if (RecStats.NumAbbrev)
+          fprintf(stderr, "%7.2f  ",
+                  (double)RecStats.NumAbbrev/RecStats.NumInstances*100);
+        else
+          fprintf(stderr, "         ");
         
         if (const char *CodeName = 
               GetCodeName(FreqPairs[i].second, I->first, StreamFile))




From isanbard at gmail.com  Mon Apr 27 13:35:46 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 27 Apr 2009 18:35:46 -0000
Subject: [llvm-commits] [llvm] r70221 - /llvm/tags/Apple/llvmCore-2107.2/
Message-ID: <200904271835.n3RIZkxF015357@zion.cs.uiuc.edu>

Author: void
Date: Mon Apr 27 13:35:46 2009
New Revision: 70221

URL: http://llvm.org/viewvc/llvm-project?rev=70221&view=rev
Log:
Creating llvmCore-2107.2 from Dib.

Added:
    llvm/tags/Apple/llvmCore-2107.2/
      - copied from r70220, llvm/branches/Apple/Dib/



From isanbard at gmail.com  Mon Apr 27 13:36:28 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 27 Apr 2009 18:36:28 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r70222 -
	/llvm-gcc-4.2/tags/Apple/llvmgcc42-2107.2/
Message-ID: <200904271836.n3RIaSTG015386@zion.cs.uiuc.edu>

Author: void
Date: Mon Apr 27 13:36:28 2009
New Revision: 70222

URL: http://llvm.org/viewvc/llvm-project?rev=70222&view=rev
Log:
Creating llvmgcc42-2107.2 from Dib.

Added:
    llvm-gcc-4.2/tags/Apple/llvmgcc42-2107.2/
      - copied from r70215, llvm-gcc-4.2/branches/Apple/Dib/



From natebegeman at mac.com  Mon Apr 27 13:41:30 2009
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 27 Apr 2009 18:41:30 -0000
Subject: [llvm-commits] [llvm] r70225 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/
 lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/
 test/CodeGen/Generic/ test/CodeGen/X86/ utils/TableGen/
Message-ID: <200904271841.n3RIfW0N015595@zion.cs.uiuc.edu>

Author: sampo
Date: Mon Apr 27 13:41:29 2009
New Revision: 70225

URL: http://llvm.org/viewvc/llvm-project?rev=70225&view=rev
Log:
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.

PR2957

ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.


Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/include/llvm/Target/TargetLowering.h
    llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
    llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/lib/Target/X86/X86InstrMMX.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/Generic/vector-casts.ll
    llvm/trunk/test/CodeGen/X86/vec_clear.ll
    llvm/trunk/test/CodeGen/X86/vec_shuffle-10.ll
    llvm/trunk/test/CodeGen/X86/vec_shuffle-16.ll
    llvm/trunk/test/CodeGen/X86/vec_shuffle-30.ll
    llvm/trunk/test/CodeGen/X86/vec_shuffle-31.ll
    llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
    llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Apr 27 13:41:29 2009
@@ -353,6 +353,13 @@
   SDValue getConvertRndSat(MVT VT, DebugLoc dl, SDValue Val, SDValue DTy,
                            SDValue STy,
                            SDValue Rnd, SDValue Sat, ISD::CvtCode Code);
+  
+  /// getVectorShuffle - Return an ISD::VECTOR_SHUFFLE node.  The number of
+  /// elements in VT, which must be a vector type, must match the number of
+  /// mask elements NumElts.  A negative integer mask element is treated as
+  /// undefined.
+  SDValue getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, SDValue N2, 
+                           const int *MaskElts);
 
   /// getZeroExtendInReg - Return the expression required to zero extend the Op
   /// value assuming it was the smaller SrcTy value.

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Apr 27 13:41:29 2009
@@ -24,6 +24,7 @@
 #include "llvm/ADT/GraphTraits.h"
 #include "llvm/ADT/iterator.h"
 #include "llvm/ADT/ilist_node.h"
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
@@ -1703,6 +1704,41 @@
   }
 };
 
+class ShuffleVectorSDNode : public SDNode {
+  SDUse Ops[2];
+  int *Mask;
+protected:
+  friend class SelectionDAG;
+  ShuffleVectorSDNode(MVT VT, DebugLoc dl, SDValue N1, SDValue N2, int *M)
+    : SDNode(ISD::VECTOR_SHUFFLE, dl, getSDVTList(VT)), Mask(M) {
+    InitOperands(Ops, N1, N2);
+  }
+public:
+
+  void getMask(SmallVectorImpl<int> &M) const {
+    MVT VT = getValueType(0);
+    M.clear();
+    for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
+      M.push_back(Mask[i]);
+  }
+  int getMaskElt(unsigned Idx) const {
+    assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!");
+    return Mask[Idx];
+  }
+  
+  bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }
+  int  getSplatIndex() const { 
+    assert(isSplat() && "Cannot get splat index for non-splat!");
+    return Mask[0];
+  }
+  static bool isSplatMask(const int *Mask, MVT VT);
+
+  static bool classof(const ShuffleVectorSDNode *) { return true; }
+  static bool classof(const SDNode *N) {
+    return N->getOpcode() == ISD::VECTOR_SHUFFLE;
+  }
+};
+  
 class ConstantSDNode : public SDNode {
   const ConstantInt *Value;
   friend class SelectionDAG;
@@ -2084,7 +2120,7 @@
     return N->getOpcode() == ISD::CONDCODE;
   }
 };
-
+  
 /// CvtRndSatSDNode - NOTE: avoid using this node as this may disappear in the
 /// future and most targets don't support it.
 class CvtRndSatSDNode : public SDNode {

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Apr 27 13:41:29 2009
@@ -28,6 +28,7 @@
 #include "llvm/ADT/APFloat.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/DebugLoc.h"
 #include "llvm/Target/TargetMachine.h"
@@ -328,7 +329,7 @@
   /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
   /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
   /// are assumed to be legal.
-  virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const {
+  virtual bool isShuffleMaskLegal(SmallVectorImpl<int> &Mask, MVT VT) const {
     return true;
   }
 
@@ -336,9 +337,7 @@
   /// used by Targets can use this to indicate if there is a suitable
   /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
   /// pool entry.
-  virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
-                                      MVT EVT,
-                                      SelectionDAG &DAG) const {
+  virtual bool isVectorClearMaskLegal(SmallVectorImpl<int> &M, MVT VT) const {
     return false;
   }
 

Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Mon Apr 27 13:41:29 2009
@@ -51,15 +51,6 @@
   int BigOperandNum = BigOp;
 }
 
-/// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
-/// vector types, and that ThisOp is the result of 
-/// MVT::getIntVectorWithNumElements with the number of elements
-/// that ThisOp has.
-class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
-  : SDTypeConstraint<ThisOp> {
-  int OtherOpNum = OtherOp;
-}
-
 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
 /// type as the element type of OtherOp, which is a vector type.
 class SDTCisEltOfVec<int ThisOp, int OtherOp>
@@ -175,8 +166,8 @@
   SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
 ]>;
 
-def SDTVecShuffle : SDTypeProfile<1, 3, [
-  SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
+def SDTVecShuffle : SDTypeProfile<1, 2, [
+  SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
 ]>;
 def SDTVecExtract : SDTypeProfile<1, 2, [   // vector extract
   SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 27 13:41:29 2009
@@ -5102,7 +5102,21 @@
     return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
                        InVec.getValueType(), &Ops[0], Ops.size());
   }
+  // If the invec is an UNDEF and if EltNo is a constant, create a new 
+  // BUILD_VECTOR with undef elements and the inserted element.
+  if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 
+      isa<ConstantSDNode>(EltNo)) {
+    MVT VT = InVec.getValueType();
+    MVT EVT = VT.getVectorElementType();
+    unsigned NElts = VT.getVectorNumElements();
+    SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT));
 
+    unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
+    if (Elt < Ops.size())
+      Ops[Elt] = InVal;
+    return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
+                       InVec.getValueType(), &Ops[0], Ops.size());
+  }
   return SDValue();
 }
 
@@ -5164,9 +5178,8 @@
       // to examine the mask.
       if (BCNumEltsChanged)
         return SDValue();
-      unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2).
-                                          getOperand(Elt))->getZExtValue();
-      unsigned NumElems = InVec.getOperand(2).getNumOperands();
+      int Idx = cast<ShuffleVectorSDNode>(InVec)->getMaskElt(Elt);
+      int NumElems = InVec.getValueType().getVectorNumElements();
       InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
       if (InVec.getOpcode() == ISD::BIT_CONVERT)
         InVec = InVec.getOperand(0);
@@ -5213,7 +5226,6 @@
 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
   unsigned NumInScalars = N->getNumOperands();
   MVT VT = N->getValueType(0);
-  unsigned NumElts = VT.getVectorNumElements();
   MVT EltType = VT.getVectorElementType();
 
   // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
@@ -5256,56 +5268,36 @@
   }
 
   // If everything is good, we can make a shuffle operation.
-  MVT IndexVT = MVT::i32;
   if (VecIn1.getNode()) {
-    SmallVector<SDValue, 8> BuildVecIndices;
+    SmallVector<int, 8> Mask;
     for (unsigned i = 0; i != NumInScalars; ++i) {
       if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
-        BuildVecIndices.push_back(DAG.getUNDEF(IndexVT));
+        Mask.push_back(-1);
         continue;
       }
 
-      SDValue Extract = N->getOperand(i);
-
       // If extracting from the first vector, just use the index directly.
+      SDValue Extract = N->getOperand(i);
       SDValue ExtVal = Extract.getOperand(1);
       if (Extract.getOperand(0) == VecIn1) {
-        if (ExtVal.getValueType() == IndexVT)
-          BuildVecIndices.push_back(ExtVal);
-        else {
-          unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
-          BuildVecIndices.push_back(DAG.getConstant(Idx, IndexVT));
-        }
+        Mask.push_back(cast<ConstantSDNode>(ExtVal)->getZExtValue());
         continue;
       }
 
       // Otherwise, use InIdx + VecSize
       unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
-      BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, IndexVT));
+      Mask.push_back(Idx+NumInScalars);
     }
 
     // Add count and size info.
-    MVT BuildVecVT = MVT::getVectorVT(IndexVT, NumElts);
-    if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes)
+    if (!TLI.isTypeLegal(VT) && LegalTypes)
       return SDValue();
 
     // Return the new VECTOR_SHUFFLE node.
-    SDValue Ops[5];
+    SDValue Ops[2];
     Ops[0] = VecIn1;
-    if (VecIn2.getNode()) {
-      Ops[1] = VecIn2;
-    } else {
-      // Use an undef build_vector as input for the second operand.
-      std::vector<SDValue> UnOps(NumInScalars,
-                                 DAG.getUNDEF(EltType));
-      Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
-                           &UnOps[0], UnOps.size());
-      AddToWorkList(Ops[1].getNode());
-    }
-
-    Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), BuildVecVT,
-                         &BuildVecIndices[0], BuildVecIndices.size());
-    return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), VT, Ops, 3);
+    Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
+    return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
   }
 
   return SDValue();
@@ -5325,8 +5317,10 @@
 }
 
 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
-  SDValue ShufMask = N->getOperand(2);
-  unsigned NumElts = ShufMask.getNumOperands();
+  return SDValue();
+  
+  MVT VT = N->getValueType(0);
+  unsigned NumElts = VT.getVectorNumElements();
 
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
@@ -5334,60 +5328,13 @@
   assert(N0.getValueType().getVectorNumElements() == NumElts &&
         "Vector shuffle must be normalized in DAG");
 
-  // If the shuffle mask is an identity operation on the LHS, return the LHS.
-  bool isIdentity = true;
-  for (unsigned i = 0; i != NumElts; ++i) {
-    if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
-        cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) {
-      isIdentity = false;
-      break;
-    }
-  }
-  if (isIdentity) return N->getOperand(0);
-
-  // If the shuffle mask is an identity operation on the RHS, return the RHS.
-  isIdentity = true;
-  for (unsigned i = 0; i != NumElts; ++i) {
-    if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
-        cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() !=
-          i+NumElts) {
-      isIdentity = false;
-      break;
-    }
-  }
-  if (isIdentity) return N->getOperand(1);
-
-  // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
-  // needed at all.
-  bool isUnary = true;
-  bool isSplat = true;
-  int VecNum = -1;
-  unsigned BaseIdx = 0;
-  for (unsigned i = 0; i != NumElts; ++i)
-    if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
-      unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue();
-      int V = (Idx < NumElts) ? 0 : 1;
-      if (VecNum == -1) {
-        VecNum = V;
-        BaseIdx = Idx;
-      } else {
-        if (BaseIdx != Idx)
-          isSplat = false;
-        if (VecNum != V) {
-          isUnary = false;
-          break;
-        }
-      }
-    }
-
-  // Normalize unary shuffle so the RHS is undef.
-  if (isUnary && VecNum == 1)
-    std::swap(N0, N1);
+  // FIXME: implement canonicalizations from DAG.getVectorShuffle()
 
   // If it is a splat, check if the argument vector is a build_vector with
   // all scalar elements the same.
-  if (isSplat) {
+  if (cast<ShuffleVectorSDNode>(N)->isSplat()) {
     SDNode *V = N0.getNode();
+    
 
     // If this is a bit convert that changes the element type of the vector but
     // not the number of vector elements, look through it.  Be careful not to
@@ -5401,6 +5348,7 @@
 
     if (V->getOpcode() == ISD::BUILD_VECTOR) {
       unsigned NumElems = V->getNumOperands();
+      unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex();
       if (NumElems > BaseIdx) {
         SDValue Base;
         bool AllSame = true;
@@ -5425,38 +5373,6 @@
       }
     }
   }
-
-  // If it is a unary or the LHS and the RHS are the same node, turn the RHS
-  // into an undef.
-  if (isUnary || N0 == N1) {
-    // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
-    // first operand.
-    SmallVector<SDValue, 8> MappedOps;
-
-    for (unsigned i = 0; i != NumElts; ++i) {
-      if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
-          cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() <
-            NumElts) {
-        MappedOps.push_back(ShufMask.getOperand(i));
-      } else {
-        unsigned NewIdx =
-          cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() -
-          NumElts;
-        MappedOps.push_back(DAG.getConstant(NewIdx,
-                                        ShufMask.getOperand(i).getValueType()));
-      }
-    }
-
-    ShufMask = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
-                           ShufMask.getValueType(),
-                           &MappedOps[0], MappedOps.size());
-    AddToWorkList(ShufMask.getNode());
-    return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
-                       N->getValueType(0), N0,
-                       DAG.getUNDEF(N->getValueType(0)),
-                       ShufMask);
-  }
-
   return SDValue();
 }
 
@@ -5465,52 +5381,42 @@
 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
 ///      vector_shuffle V, Zero, <0, 4, 2, 4>
 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
+  MVT VT = N->getValueType(0);
+  DebugLoc dl = N->getDebugLoc();
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
   if (N->getOpcode() == ISD::AND) {
     if (RHS.getOpcode() == ISD::BIT_CONVERT)
       RHS = RHS.getOperand(0);
     if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
-      std::vector<SDValue> IdxOps;
-      unsigned NumOps = RHS.getNumOperands();
-      unsigned NumElts = NumOps;
+      SmallVector<int, 8> Indices;
+      unsigned NumElts = RHS.getNumOperands();
       for (unsigned i = 0; i != NumElts; ++i) {
         SDValue Elt = RHS.getOperand(i);
         if (!isa<ConstantSDNode>(Elt))
           return SDValue();
         else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
-          IdxOps.push_back(DAG.getIntPtrConstant(i));
+          Indices.push_back(i);
         else if (cast<ConstantSDNode>(Elt)->isNullValue())
-          IdxOps.push_back(DAG.getIntPtrConstant(NumElts));
+          Indices.push_back(NumElts);
         else
           return SDValue();
       }
 
       // Let's see if the target supports this vector_shuffle.
-      if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG))
+      MVT RVT = RHS.getValueType();
+      if (!TLI.isVectorClearMaskLegal(Indices, RVT))
         return SDValue();
 
       // Return the new VECTOR_SHUFFLE node.
-      MVT EVT = RHS.getValueType().getVectorElementType();
-      MVT VT = MVT::getVectorVT(EVT, NumElts);
-      MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
-      std::vector<SDValue> Ops;
-      LHS = DAG.getNode(ISD::BIT_CONVERT, LHS.getDebugLoc(), VT, LHS);
-      Ops.push_back(LHS);
-      AddToWorkList(LHS.getNode());
-      std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
-      Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
-                                VT, &ZeroOps[0], ZeroOps.size()));
-      Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
-                                MaskVT, &IdxOps[0], IdxOps.size()));
-      SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
-                                   VT, &Ops[0], Ops.size());
-
-      if (VT != N->getValueType(0))
-        Result = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
-                             N->getValueType(0), Result);
-
-      return Result;
+      MVT EVT = RVT.getVectorElementType();
+      SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
+                                     DAG.getConstant(0, EVT));
+      SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
+                                 RVT, &ZeroOps[0], ZeroOps.size());
+      LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS);
+      SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
+      return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf);
     }
   }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 27 13:41:29 2009
@@ -267,16 +267,10 @@
                             bool isVolatile, SDValue ValOp,
                             unsigned StWidth, DebugLoc dl);
 
-  /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
-  /// specified mask and type.  Targets can specify exactly which masks they
-  /// support and the code generator is tasked with not creating illegal masks.
-  ///
-  /// Note that this will also return true for shuffles that are promoted to a
-  /// different type.
-  ///
-  /// If this is a legal shuffle, this method returns the (possibly promoted)
-  /// build_vector Mask.  If it's not a legal shuffle, it returns null.
-  SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
+  /// promoteShuffle - Promote a shuffle mask of a vector VT to perform the
+  /// same shuffle on a vector of NVT.  Must not create an illegal shuffle mask.
+  SDValue promoteShuffle(MVT NVT, MVT VT, DebugLoc dl, SDValue N1, SDValue N2, 
+                         SmallVectorImpl<int> &Mask) const;
 
   bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
                                     SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
@@ -319,50 +313,35 @@
 };
 }
 
-/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
-/// specified mask and type.  Targets can specify exactly which masks they
-/// support and the code generator is tasked with not creating illegal masks.
-///
-/// Note that this will also return true for shuffles that are promoted to a
-/// different type.
-SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
-  switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
-  default: return 0;
-  case TargetLowering::Legal:
-  case TargetLowering::Custom:
-    break;
-  case TargetLowering::Promote: {
-    // If this is promoted to a different type, convert the shuffle mask and
-    // ask if it is legal in the promoted type!
-    MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
-    MVT EltVT = NVT.getVectorElementType();
-
-    // If we changed # elements, change the shuffle mask.
-    unsigned NumEltsGrowth =
-      NVT.getVectorNumElements() / VT.getVectorNumElements();
-    assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
-    if (NumEltsGrowth > 1) {
-      // Renumber the elements.
-      SmallVector<SDValue, 8> Ops;
-      for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
-        SDValue InOp = Mask.getOperand(i);
-        for (unsigned j = 0; j != NumEltsGrowth; ++j) {
-          if (InOp.getOpcode() == ISD::UNDEF)
-            Ops.push_back(DAG.getUNDEF(EltVT));
-          else {
-            unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
-            Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
-          }
-        }
-      }
-      Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(),
-                         NVT, &Ops[0], Ops.size());
+/// promoteShuffle - Promote a shuffle mask of a vector VT to perform the
+/// same shuffle on a vector of NVT.  Must not create an illegal shuffle mask.
+/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
+SDValue SelectionDAGLegalize::promoteShuffle(MVT NVT, MVT VT, DebugLoc dl, 
+                                             SDValue N1, SDValue N2,
+                                             SmallVectorImpl<int> &Mask) const {
+  MVT EltVT = NVT.getVectorElementType();
+  int NumMaskElts = VT.getVectorNumElements();
+  int NumDestElts = NVT.getVectorNumElements();
+  unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
+
+  assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
+
+  if (NumEltsGrowth == 1)
+    return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
+  
+  SmallVector<int, 8> NewMask;
+  for (int i = 0; i != NumMaskElts; ++i) {
+    int Idx = Mask[i];
+    for (unsigned j = 0; j != NumEltsGrowth; ++j) {
+      if (Idx < 0) 
+        NewMask.push_back(-1);
+      else
+        NewMask.push_back(Idx * NumEltsGrowth + j);
     }
-    VT = NVT;
-    break;
-  }
   }
-  return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
+  assert((int)NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
+  assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
+  return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
 }
 
 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
@@ -1652,25 +1631,15 @@
                                       Tmp1.getValueType(), Tmp2);
 
           unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
-          MVT ShufMaskVT =
-            MVT::getIntVectorWithNumElements(NumElts);
-          MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
-
           // We generate a shuffle of InVec and ScVec, so the shuffle mask
           // should be 0,1,2,3,4,5... with the appropriate element replaced with
           // elt 0 of the RHS.
-          SmallVector<SDValue, 8> ShufOps;
-          for (unsigned i = 0; i != NumElts; ++i) {
-            if (i != InsertPos->getZExtValue())
-              ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
-            else
-              ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
-          }
-          SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, ShufMaskVT,
-                                         &ShufOps[0], ShufOps.size());
-
-          Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Tmp1.getValueType(),
-                               Tmp1, ScVec, ShufMask);
+          SmallVector<int, 8> ShufOps;
+          for (unsigned i = 0; i != NumElts; ++i)
+            ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
+          
+          Result = DAG.getVectorShuffle(Tmp1.getValueType(), dl, Tmp1, ScVec,
+                                        &ShufOps[0]);
           Result = LegalizeOp(Result);
           break;
         }
@@ -1705,16 +1674,21 @@
       break;
     }
     break;
-  case ISD::VECTOR_SHUFFLE:
+  case ISD::VECTOR_SHUFFLE: {
     Tmp1 = LegalizeOp(Node->getOperand(0));   // Legalize the input vectors,
     Tmp2 = LegalizeOp(Node->getOperand(1));   // but not the shuffle mask.
-    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
+    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+    MVT VT = Result.getValueType();
+
+    // Copy the Mask to a local SmallVector for use wi
+    SmallVector<int, 8> Mask;
+    cast<ShuffleVectorSDNode>(Result)->getMask(Mask);
 
     // Allow targets to custom lower the SHUFFLEs they support.
-    switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, Result.getValueType())){
+    switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
     default: assert(0 && "Unknown operation action!");
     case TargetLowering::Legal:
-      assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
+      assert(TLI.isShuffleMaskLegal(Mask, VT) &&
              "vector shuffle should not be created if not legal!");
       break;
     case TargetLowering::Custom:
@@ -1725,26 +1699,21 @@
       }
       // FALLTHROUGH
     case TargetLowering::Expand: {
-      MVT VT = Node->getValueType(0);
       MVT EltVT = VT.getVectorElementType();
-      MVT PtrVT = TLI.getPointerTy();
-      SDValue Mask = Node->getOperand(2);
-      unsigned NumElems = Mask.getNumOperands();
+      int NumElems = VT.getVectorNumElements();
       SmallVector<SDValue, 8> Ops;
-      for (unsigned i = 0; i != NumElems; ++i) {
-        SDValue Arg = Mask.getOperand(i);
-        if (Arg.getOpcode() == ISD::UNDEF) {
+      for (int i = 0; i != NumElems; ++i) {
+        if (Mask[i] < 0) {
           Ops.push_back(DAG.getUNDEF(EltVT));
-        } else {
-          assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-          unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
-          if (Idx < NumElems)
-            Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
-                                      DAG.getConstant(Idx, PtrVT)));
-          else
-            Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2,
-                                      DAG.getConstant(Idx - NumElems, PtrVT)));
+          continue;
         }
+        int Idx = Mask[i];
+        if (Idx < NumElems)
+          Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
+                                    DAG.getIntPtrConstant(Idx)));
+        else
+          Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2,
+                                    DAG.getIntPtrConstant(Idx - NumElems)));
       }
       Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
       break;
@@ -1759,15 +1728,13 @@
       Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
 
       // Convert the shuffle mask to the right # elements.
-      Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
-      assert(Tmp3.getNode() && "Shuffle not legal?");
-      Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NVT, Tmp1, Tmp2, Tmp3);
+      Result = promoteShuffle(NVT, OVT, dl, Tmp1, Tmp2, Mask);
       Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
       break;
     }
     }
     break;
-
+  }
   case ISD::EXTRACT_VECTOR_ELT:
     Tmp1 = Node->getOperand(0);
     Tmp2 = LegalizeOp(Node->getOperand(1));
@@ -5490,6 +5457,7 @@
 
   // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
   // and use a bitmask instead of a list of elements.
+  // FIXME: this doesn't treat <0, u, 0, u> for example, as a splat.
   std::map<SDValue, std::vector<unsigned> > Values;
   Values[SplatValue].push_back(0);
   bool isConstant = true;
@@ -5546,21 +5514,17 @@
 
   if (SplatValue.getNode()) {   // Splat of one value?
     // Build the shuffle constant vector: <0, 0, 0, 0>
-    MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-    SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
-    std::vector<SDValue> ZeroVec(NumElems, Zero);
-    SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                    &ZeroVec[0], ZeroVec.size());
+    SmallVector<int, 8> ZeroVec(NumElems, 0);
 
     // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
-    if (isShuffleLegal(VT, SplatMask)) {
+    if (TLI.isShuffleMaskLegal(ZeroVec, Node->getValueType(0))) {
       // Get the splatted value into the low element of a vector register.
       SDValue LowValVec =
         DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, SplatValue);
 
       // Return shuffle(LowValVec, undef, <0,0,0,0>)
-      return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, LowValVec,
-                         DAG.getUNDEF(VT), SplatMask);
+      return DAG.getVectorShuffle(VT, dl, LowValVec, DAG.getUNDEF(VT),
+                                  &ZeroVec[0]);
     }
   }
 
@@ -5582,35 +5546,25 @@
       std::swap(Val1, Val2);
 
     // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
-    MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-    MVT MaskEltVT = MaskVT.getVectorElementType();
-    std::vector<SDValue> MaskVec(NumElems);
+    SmallVector<int, 8> ShuffleMask(NumElems, -1);
 
     // Set elements of the shuffle mask for Val1.
     std::vector<unsigned> &Val1Elts = Values[Val1];
     for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
-      MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
+      ShuffleMask[Val1Elts[i]] = 0;
 
     // Set elements of the shuffle mask for Val2.
     std::vector<unsigned> &Val2Elts = Values[Val2];
     for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
       if (Val2.getOpcode() != ISD::UNDEF)
-        MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
-      else
-        MaskVec[Val2Elts[i]] = DAG.getUNDEF(MaskEltVT);
-
-    SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                      &MaskVec[0], MaskVec.size());
+        ShuffleMask[Val2Elts[i]] = NumElems;
 
     // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
     if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, VT) &&
-        isShuffleLegal(VT, ShuffleMask)) {
+        TLI.isShuffleMaskLegal(ShuffleMask, VT)) {
       Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val1);
       Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val2);
-      SDValue Ops[] = { Val1, Val2, ShuffleMask };
-
-      // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
-      return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, Ops, 3);
+      return DAG.getVectorShuffle(VT, dl, Val1, Val2, &ShuffleMask[0]);
     }
   }
 
@@ -8066,36 +8020,19 @@
   case ISD::VECTOR_SHUFFLE: {
     SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
     SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
-    // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
-    // used as permutation array. We build the vector here instead of widening
-    // because we don't want to legalize and have it turned to something else.
-    SDValue PermOp = Node->getOperand(2);
-    SDValueVector NewOps;
-    MVT PVT = PermOp.getValueType().getVectorElementType();
+    ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Node);
+    SmallVector<int, 8> NewMask;
     for (unsigned i = 0; i < NumElts; ++i) {
-      if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
-        NewOps.push_back(PermOp.getOperand(i));
-      } else {
-        unsigned Idx =
-          cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
-        if (Idx < NumElts) {
-          NewOps.push_back(PermOp.getOperand(i));
-        }
-        else {
-          NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
-                                           PermOp.getOperand(i).getValueType()));
-        }
-      }
-    }
-    for (unsigned i = NumElts; i < NewNumElts; ++i) {
-      NewOps.push_back(DAG.getUNDEF(PVT));
+      int Idx = SVOp->getMaskElt(i);
+      if (Idx < (int)NumElts)
+        NewMask.push_back(Idx);
+      else
+        NewMask.push_back(Idx + NewNumElts - NumElts);
     }
-
-    SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl,
-                               MVT::getVectorVT(PVT, NewOps.size()),
-                               &NewOps[0], NewOps.size());
-
-    Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, Tmp1, Tmp2, Tmp3);
+    for (unsigned i = NumElts; i < NewNumElts; ++i)
+      NewMask.push_back(-1);
+    
+    Result = DAG.getVectorShuffle(WidenVT, dl, Tmp1, Tmp2, &NewMask[0]);
     break;
   }
   case ISD::LOAD: {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Mon Apr 27 13:41:29 2009
@@ -761,6 +761,7 @@
                                                   SDValue &Hi) {
   // The low and high parts of the original input give four input vectors.
   SDValue Inputs[4];
+  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
   DebugLoc dl = N->getDebugLoc();
   GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
   GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
@@ -772,10 +773,7 @@
   // If Lo or Hi uses elements from at most two of the four input vectors, then
   // express it as a vector shuffle of those two inputs.  Otherwise extract the
   // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
-  SDValue Mask = N->getOperand(2);
-  MVT IdxVT = Mask.getValueType().getVectorElementType();
-  SmallVector<SDValue, 16> Ops;
-  Ops.reserve(NewElts);
+  SmallVector<int, 16> Ops;
   for (unsigned High = 0; High < 2; ++High) {
     SDValue &Output = High ? Hi : Lo;
 
@@ -787,18 +785,15 @@
     unsigned FirstMaskIdx = High * NewElts;
     bool useBuildVector = false;
     for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
-      SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
-
       // The mask element.  This indexes into the input.
-      unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
-        -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
+      int Idx = SVN->getMaskElt(FirstMaskIdx + MaskOffset);
 
       // The input vector this mask element indexes into.
-      unsigned Input = Idx / NewElts;
+      unsigned Input = (unsigned)Idx / NewElts;
 
       if (Input >= array_lengthof(Inputs)) {
         // The mask element does not index into any input vector.
-        Ops.push_back(DAG.getUNDEF(IdxVT));
+        Ops.push_back(-1);
         continue;
       }
 
@@ -826,27 +821,24 @@
       }
 
       // Add the mask index for the new shuffle vector.
-      Ops.push_back(DAG.getConstant(Idx + OpNo * NewElts, IdxVT));
+      Ops.push_back(Idx + OpNo * NewElts);
     }
 
     if (useBuildVector) {
       MVT EltVT = NewVT.getVectorElementType();
-      Ops.clear();
+      SmallVector<SDValue, 16> SVOps;
 
       // Extract the input elements by hand.
       for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
-        SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
-
         // The mask element.  This indexes into the input.
-        unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
-          -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
+        int Idx = SVN->getMaskElt(FirstMaskIdx + MaskOffset);
 
         // The input vector this mask element indexes into.
-        unsigned Input = Idx / NewElts;
+        unsigned Input = (unsigned)Idx / NewElts;
 
         if (Input >= array_lengthof(Inputs)) {
           // The mask element is "undef" or indexes off the end of the input.
-          Ops.push_back(DAG.getUNDEF(EltVT));
+          SVOps.push_back(DAG.getUNDEF(EltVT));
           continue;
         }
 
@@ -854,25 +846,22 @@
         Idx -= Input * NewElts;
 
         // Extract the vector element by hand.
-        Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
-                                  Inputs[Input], DAG.getIntPtrConstant(Idx)));
+        SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
+                                    Inputs[Input], DAG.getIntPtrConstant(Idx)));
       }
 
       // Construct the Lo/Hi output using a BUILD_VECTOR.
-      Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, &Ops[0], Ops.size());
+      Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
     } else if (InputUsed[0] == -1U) {
       // No input vectors were used!  The result is undefined.
       Output = DAG.getUNDEF(NewVT);
     } else {
-      // At least one input vector was used.  Create a new shuffle vector.
-      SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl,
-                                    MVT::getVectorVT(IdxVT, Ops.size()),
-                                    &Ops[0], Ops.size());
       SDValue Op0 = Inputs[InputUsed[0]];
       // If only one input was used, use an undefined vector for the other.
       SDValue Op1 = InputUsed[1] == -1U ?
         DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
-      Output = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, Op0, Op1, NewMask);
+      // At least one input vector was used.  Create a new shuffle vector.
+      Output =  DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
     }
 
     Ops.clear();
@@ -1473,18 +1462,15 @@
 
       if (NumOperands == 2) {
         // Replace concat of two operands with a shuffle.
-        MVT PtrVT = TLI.getPointerTy();
-        SmallVector<SDValue, 16> MaskOps(WidenNumElts);
+        SmallVector<int, 16> MaskOps(WidenNumElts);
         for (unsigned i=0; i < WidenNumElts/2; ++i) {
-          MaskOps[i] = DAG.getConstant(i, PtrVT);
-          MaskOps[i+WidenNumElts/2] = DAG.getConstant(i+WidenNumElts, PtrVT);
+          MaskOps[i] = i;
+          MaskOps[i+WidenNumElts/2] = i+WidenNumElts;
         }
-        SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl,
-                                   MVT::getVectorVT(PtrVT, WidenNumElts),
-                                   &MaskOps[0], WidenNumElts);
-        return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT,
-                           GetWidenedVector(N->getOperand(0)),
-                           GetWidenedVector(N->getOperand(1)), Mask);
+        return DAG.getVectorShuffle(WidenVT, dl, 
+                                    GetWidenedVector(N->getOperand(0)),
+                                    GetWidenedVector(N->getOperand(1)),
+                                    &MaskOps[0]);
       }
     }
   }
@@ -1761,8 +1747,9 @@
 }
 
 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(SDNode *N) {
+  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
   MVT VT = N->getValueType(0);
-  unsigned NumElts = VT.getVectorNumElements();
+  int NumElts = VT.getVectorNumElements();
   DebugLoc dl = N->getDebugLoc();
 
   MVT WidenVT = TLI.getTypeToTransformTo(VT);
@@ -1772,28 +1759,17 @@
   SDValue InOp2 = GetWidenedVector(N->getOperand(1));
 
   // Adjust mask based on new input vector length.
-  SDValue Mask = N->getOperand(2);
-  SmallVector<SDValue, 16> MaskOps(WidenNumElts);
-  MVT IdxVT = Mask.getValueType().getVectorElementType();
-  for (unsigned i = 0; i < NumElts; ++i) {
-    SDValue Arg = Mask.getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF)
-      MaskOps[i] = Arg;
-    else {
-      unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
-      if (Idx < NumElts)
-        MaskOps[i] = Arg;
-      else
-        MaskOps[i] = DAG.getConstant(Idx - NumElts + WidenNumElts, IdxVT);
-    }
+  SmallVector<int, 16> NewMask;
+  for (int i = 0; i < NumElts; ++i) {
+    int Idx = SVN->getMaskElt(i);
+    if (Idx < NumElts)
+      NewMask.push_back(Idx);
+    else
+      NewMask.push_back(Idx - NumElts + WidenNumElts);
   }
   for (unsigned i = NumElts; i < WidenNumElts; ++i)
-    MaskOps[i] = DAG.getUNDEF(IdxVT);
-  SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl,
-                                MVT::getVectorVT(IdxVT, WidenNumElts),
-                                &MaskOps[0], WidenNumElts);
-
-  return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, InOp1, InOp2, NewMask);
+    NewMask.push_back(-1);
+  return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
 }
 
 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Apr 27 13:41:29 2009
@@ -456,6 +456,13 @@
     ID.AddInteger(AT->getRawSubclassData());
     break;
   }
+  case ISD::VECTOR_SHUFFLE: {
+    const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
+    for (unsigned i = 0, e = N->getValueType(0).getVectorNumElements(); 
+         i != e; ++i)
+      ID.AddInteger(SVN->getMaskElt(i));
+    break;
+  }
   } // end switch (N->getOpcode())
 }
 
@@ -765,9 +772,9 @@
     MVT EltVT = N->getValueType(0).getVectorElementType();
     for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I)
       assert((I->getValueType() == EltVT ||
-              (EltVT.isInteger() && I->getValueType().isInteger() &&
-               EltVT.bitsLE(I->getValueType()))) &&
-             "Wrong operand type!");
+             (EltVT.isInteger() && I->getValueType().isInteger() &&
+              EltVT.bitsLE(I->getValueType()))) &&
+            "Wrong operand type!");
     break;
   }
   }
@@ -1126,6 +1133,110 @@
   return SDValue(CondCodeNodes[Cond], 0);
 }
 
+static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) {
+  std::swap(N1, N2);
+  int NElts = M.size();
+  for (int i = 0; i != NElts; ++i) {
+    if (M[i] >= NElts)
+      M[i] -= NElts;
+    else if (M[i] >= 0)
+      M[i] += NElts;
+  }
+}
+
+SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, 
+                                       SDValue N2, const int *Mask) {
+  assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE");
+  assert(VT.isVector() && N1.getValueType().isVector() && 
+         "Vector Shuffle VTs must be a vectors");
+  assert(VT.getVectorElementType() == N1.getValueType().getVectorElementType()
+         && "Vector Shuffle VTs must have same element type");
+
+  // Canonicalize shuffle undef, undef -> undef
+  if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF)
+    return N1;
+
+  // Validate that all indices in Mask are within the range of the elements 
+  // input to the shuffle.
+  int NElts = VT.getVectorNumElements();
+  SmallVector<int, 8> MaskVec;
+  for (int i = 0; i != NElts; ++i) {
+    if (Mask[i] >= (NElts * 2)) {
+      assert(0 && "Index out of range");
+      return SDValue();
+    }
+    MaskVec.push_back(Mask[i]);
+  }
+  
+  // Canonicalize shuffle v, v -> v, undef
+  if (N1 == N2) {
+    N2 = getUNDEF(VT);
+    for (int i = 0; i != NElts; ++i)
+      if (MaskVec[i] >= NElts) MaskVec[i] -= NElts;
+  }
+  
+  // Canonicalize shuffle undef, v -> v, undef.  Commute the shuffle mask.
+  if (N1.getOpcode() == ISD::UNDEF)
+    commuteShuffle(N1, N2, MaskVec);
+  
+  // Canonicalize all index into lhs, -> shuffle lhs, undef
+  // Canonicalize all index into rhs, -> shuffle rhs, undef
+  bool AllLHS = true, AllRHS = true;
+  bool N2Undef = N2.getOpcode() == ISD::UNDEF;
+  for (int i = 0; i != NElts; ++i) {
+    if (MaskVec[i] >= NElts) {
+      if (N2Undef)
+        MaskVec[i] = -1;
+      else
+        AllLHS = false;
+    } else if (MaskVec[i] >= 0) {
+      AllRHS = false;
+    }
+  }
+  if (AllLHS && AllRHS)
+    return getUNDEF(VT);
+  if (AllLHS)
+    N2 = getUNDEF(VT);
+  if (AllRHS) {
+    N1 = getUNDEF(VT);
+    commuteShuffle(N1, N2, MaskVec);
+  }
+  
+  // If Identity shuffle, or all shuffle in to undef, return that node.
+  bool AllUndef = true;
+  bool Identity = true;
+  for (int i = 0; i < NElts; ++i) {
+    if (MaskVec[i] >= 0 && MaskVec[i] != i) Identity = false;
+    if (MaskVec[i] >= 0) AllUndef = false;
+  }
+  if (Identity)
+    return N1;
+  if (AllUndef)
+    return getUNDEF(VT);
+
+  FoldingSetNodeID ID;
+  SDValue Ops[2] = { N1, N2 };
+  AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2);
+  for (int i = 0; i != NElts; ++i)
+    ID.AddInteger(MaskVec[i]);
+  
+  void* IP = 0;
+  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+    return SDValue(E, 0);
+  
+  // Allocate the mask array for the node out of the BumpPtrAllocator, since
+  // SDNode doesn't have access to it.  This memory will be "leaked" when
+  // the node is deallocated, but recovered when the NodeAllocator is released.
+  int *MaskAlloc = OperandAllocator.Allocate<int>(NElts);
+  memcpy(MaskAlloc, &MaskVec[0], NElts * sizeof(int));
+  
+  ShuffleVectorSDNode *N = NodeAllocator.Allocate<ShuffleVectorSDNode>();
+  new (N) ShuffleVectorSDNode(VT, dl, N1, N2, MaskAlloc);
+  CSEMap.InsertNode(N, IP);
+  AllNodes.push_back(N);
+  return SDValue(N, 0);
+}
+
 SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl,
                                        SDValue Val, SDValue DTy,
                                        SDValue STy, SDValue Rnd, SDValue Sat,
@@ -2087,19 +2198,18 @@
 SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) {
   MVT VT = N->getValueType(0);
   DebugLoc dl = N->getDebugLoc();
-  SDValue PermMask = N->getOperand(2);
-  SDValue Idx = PermMask.getOperand(i);
-  if (Idx.getOpcode() == ISD::UNDEF)
+  const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
+  int Index = SVN->getMaskElt(i);
+  if (Index < 0)
     return getUNDEF(VT.getVectorElementType());
-  unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
-  unsigned NumElems = PermMask.getNumOperands();
+  int NumElems = VT.getVectorNumElements();
   SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
   Index %= NumElems;
 
   if (V.getOpcode() == ISD::BIT_CONVERT) {
     V = V.getOperand(0);
     MVT VVT = V.getValueType();
-    if (!VVT.isVector() || VVT.getVectorNumElements() != NumElems)
+    if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems)
       return SDValue();
   }
   if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
@@ -2794,12 +2904,7 @@
     }
     break;
   case ISD::VECTOR_SHUFFLE:
-    assert(N1.getValueType() == N2.getValueType() &&
-           N1.getValueType().isVector() &&
-           VT.isVector() && N3.getValueType().isVector() &&
-           N3.getOpcode() == ISD::BUILD_VECTOR &&
-           VT.getVectorNumElements() == N3.getNumOperands() &&
-           "Illegal VECTOR_SHUFFLE node!");
+    assert(0 && "should use getVectorShuffle constructor!");
     break;
   case ISD::BIT_CONVERT:
     // Fold bit_convert nodes from a type to themselves.
@@ -5323,14 +5428,15 @@
 
 void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
   if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) {
-    SDNode *Mask = getOperand(2).getNode();
+    const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(this);
     OS << "<";
-    for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) {
+    for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) {
+      int Idx = SVN->getMaskElt(i);
       if (i) OS << ",";
-      if (Mask->getOperand(i).getOpcode() == ISD::UNDEF)
+      if (Idx < 0)
         OS << "u";
       else
-        OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue();
+        OS << Idx;
     }
     OS << ">";
   }
@@ -5611,3 +5717,13 @@
   SplatBitSize = sz;
   return true;
 }
+
+bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) {
+  int Idx = -1;
+  for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
+    if (Idx < 0) Idx = Mask[i];
+    if (Mask[i] >= 0 && Mask[i] != Idx)
+      return false;
+  }
+  return true;
+}

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Apr 27 13:41:29 2009
@@ -870,8 +870,7 @@
     if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
       return N = DAG.getConstantFP(*CFP, VT);
 
-    if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
-        !V->getType()->isAggregateType())
+    if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
       return N = DAG.getUNDEF(VT);
 
     if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
@@ -925,14 +924,11 @@
       for (unsigned i = 0; i != NumElements; ++i)
         Ops.push_back(getValue(CP->getOperand(i)));
     } else {
-      assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
-             "Unknown vector constant!");
+      assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
       MVT EltVT = TLI.getValueType(VecTy->getElementType());
 
       SDValue Op;
-      if (isa<UndefValue>(C))
-        Op = DAG.getUNDEF(EltVT);
-      else if (EltVT.isFloatingPoint())
+      if (EltVT.isFloatingPoint())
         Op = DAG.getConstantFP(0, EltVT);
       else
         Op = DAG.getConstant(0, EltVT);
@@ -2435,37 +2431,42 @@
 
 // Utility for visitShuffleVector - Returns true if the mask is mask starting
 // from SIndx and increasing to the element length (undefs are allowed).
-static bool SequentialMask(SDValue Mask, unsigned SIndx) {
-  unsigned MaskNumElts = Mask.getNumOperands();
-  for (unsigned i = 0; i != MaskNumElts; ++i) {
-    if (Mask.getOperand(i).getOpcode() != ISD::UNDEF) {
-      unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
-      if (Idx != i + SIndx)
-        return false;
-    }
-  }
+static bool SequentialMask(SmallVectorImpl<int> &Mask, int SIndx) {
+  int MaskNumElts = Mask.size();
+  for (int i = 0; i != MaskNumElts; ++i)
+    if ((Mask[i] >= 0) && (Mask[i] != i + SIndx))
+      return false;
   return true;
 }
 
 void SelectionDAGLowering::visitShuffleVector(User &I) {
+  SmallVector<int, 8> Mask;
   SDValue Src1 = getValue(I.getOperand(0));
   SDValue Src2 = getValue(I.getOperand(1));
-  SDValue Mask = getValue(I.getOperand(2));
 
+  // Convert the ConstantVector mask operand into an array of ints, with -1
+  // representing undef values.
+  SmallVector<Constant*, 8> MaskElts;
+  cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
+  int MaskNumElts = MaskElts.size();
+  for (int i = 0; i != MaskNumElts; ++i) {
+    if (isa<UndefValue>(MaskElts[i]))
+      Mask.push_back(-1);
+    else
+      Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
+  }
+  
   MVT VT = TLI.getValueType(I.getType());
   MVT SrcVT = Src1.getValueType();
-  int MaskNumElts = Mask.getNumOperands();
   int SrcNumElts = SrcVT.getVectorNumElements();
 
   if (SrcNumElts == MaskNumElts) {
-    setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
-                             VT, Src1, Src2, Mask));
+    setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
+                                      &Mask[0]));
     return;
   }
 
   // Normalize the shuffle vector since mask and vector length don't match.
-  MVT MaskEltVT = Mask.getValueType().getVectorElementType();
-
   if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
     // Mask is longer than the source vectors and is a multiple of the source
     // vectors.  We can use concatenate vector to make the mask and vectors
@@ -2479,44 +2480,33 @@
 
     // Pad both vectors with undefs to make them the same length as the mask.
     unsigned NumConcat = MaskNumElts / SrcNumElts;
+    bool Src1U = Src1.getOpcode() == ISD::UNDEF;
+    bool Src2U = Src2.getOpcode() == ISD::UNDEF;
     SDValue UndefVal = DAG.getUNDEF(SrcVT);
 
-    SDValue* MOps1 = new SDValue[NumConcat];
-    SDValue* MOps2 = new SDValue[NumConcat];
+    SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
+    SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
     MOps1[0] = Src1;
     MOps2[0] = Src2;
-    for (unsigned i = 1; i != NumConcat; ++i) {
-      MOps1[i] = UndefVal;
-      MOps2[i] = UndefVal;
-    }
-    Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
-                       VT, MOps1, NumConcat);
-    Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
-                       VT, MOps2, NumConcat);
-
-    delete [] MOps1;
-    delete [] MOps2;
+    
+    Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 
+                                                  getCurDebugLoc(), VT, 
+                                                  &MOps1[0], NumConcat);
+    Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
+                                                  getCurDebugLoc(), VT, 
+                                                  &MOps2[0], NumConcat);
 
     // Readjust mask for new input vector length.
-    SmallVector<SDValue, 8> MappedOps;
+    SmallVector<int, 8> MappedOps;
     for (int i = 0; i != MaskNumElts; ++i) {
-      if (Mask.getOperand(i).getOpcode() == ISD::UNDEF) {
-        MappedOps.push_back(Mask.getOperand(i));
-      } else {
-        int Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
-        if (Idx < SrcNumElts)
-          MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
-        else
-          MappedOps.push_back(DAG.getConstant(Idx + MaskNumElts - SrcNumElts,
-                                              MaskEltVT));
-      }
+      int Idx = Mask[i];
+      if (Idx < SrcNumElts)
+        MappedOps.push_back(Idx);
+      else
+        MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
     }
-    Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
-                       Mask.getValueType(),
-                       &MappedOps[0], MappedOps.size());
-
-    setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
-                             VT, Src1, Src2, Mask));
+    setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 
+                                      &MappedOps[0]));
     return;
   }
 
@@ -2541,20 +2531,19 @@
     int MaxRange[2] = {-1, -1};
 
     for (int i = 0; i != MaskNumElts; ++i) {
-      SDValue Arg = Mask.getOperand(i);
-      if (Arg.getOpcode() != ISD::UNDEF) {
-        assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-        int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
-        int Input = 0;
-        if (Idx >= SrcNumElts) {
-          Input = 1;
-          Idx -= SrcNumElts;
-        }
-        if (Idx > MaxRange[Input])
-          MaxRange[Input] = Idx;
-        if (Idx < MinRange[Input])
-          MinRange[Input] = Idx;
-      }
+      int Idx = Mask[i];
+      int Input = 0;
+      if (Idx < 0)
+        continue;
+      
+      if (Idx >= SrcNumElts) {
+        Input = 1;
+        Idx -= SrcNumElts;
+      }
+      if (Idx > MaxRange[Input])
+        MaxRange[Input] = Idx;
+      if (Idx < MinRange[Input])
+        MinRange[Input] = Idx;
     }
 
     // Check if the access is smaller than the vector size and can we find
@@ -2596,26 +2585,18 @@
         }
       }
       // Calculate new mask.
-      SmallVector<SDValue, 8> MappedOps;
+      SmallVector<int, 8> MappedOps;
       for (int i = 0; i != MaskNumElts; ++i) {
-        SDValue Arg = Mask.getOperand(i);
-        if (Arg.getOpcode() == ISD::UNDEF) {
-          MappedOps.push_back(Arg);
-        } else {
-          int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
-          if (Idx < SrcNumElts)
-            MappedOps.push_back(DAG.getConstant(Idx - StartIdx[0], MaskEltVT));
-          else {
-            Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
-            MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
-          }
-        }
+        int Idx = Mask[i];
+        if (Idx < 0)
+          MappedOps.push_back(Idx);
+        else if (Idx < SrcNumElts)
+          MappedOps.push_back(Idx - StartIdx[0]);
+        else
+          MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
       }
-      Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
-                         Mask.getValueType(),
-                         &MappedOps[0], MappedOps.size());
-      setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
-                               VT, Src1, Src2, Mask));
+      setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
+                                        &MappedOps[0]));
       return;
     }
   }
@@ -2627,12 +2608,10 @@
   MVT PtrVT = TLI.getPointerTy();
   SmallVector<SDValue,8> Ops;
   for (int i = 0; i != MaskNumElts; ++i) {
-    SDValue Arg = Mask.getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF) {
+    if (Mask[i] < 0) {
       Ops.push_back(DAG.getUNDEF(EltVT));
     } else {
-      assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-      int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
+      int Idx = Mask[i];
       if (Idx < SrcNumElts)
         Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
                                   EltVT, Src1, DAG.getConstant(Idx, PtrVT)));

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Mon Apr 27 13:41:29 2009
@@ -1670,9 +1670,9 @@
 /// \note
 /// SPUISD::SHUFB is eventually selected as Cell's <i>shufb</i> instructions.
 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
+  const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
   SDValue V1 = Op.getOperand(0);
   SDValue V2 = Op.getOperand(1);
-  SDValue PermMask = Op.getOperand(2);
   DebugLoc dl = Op.getDebugLoc();
 
   if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
@@ -1703,39 +1703,40 @@
   } else
     assert(0 && "Unhandled vector type in LowerVECTOR_SHUFFLE");
 
-  for (unsigned i = 0; i != PermMask.getNumOperands(); ++i) {
-    if (PermMask.getOperand(i).getOpcode() != ISD::UNDEF) {
-      unsigned SrcElt = cast<ConstantSDNode > (PermMask.getOperand(i))->getZExtValue();
-
-      if (monotonic) {
-        if (SrcElt >= V2EltIdx0) {
-          if (1 >= (++EltsFromV2)) {
-            V2Elt = (V2EltIdx0 - SrcElt) << 2;
-          }
-        } else if (CurrElt != SrcElt) {
-          monotonic = false;
+  for (unsigned i = 0; i != MaxElts; ++i) {
+    if (SVN->getMaskElt(i) < 0)
+      continue;
+    
+    unsigned SrcElt = SVN->getMaskElt(i);
+
+    if (monotonic) {
+      if (SrcElt >= V2EltIdx0) {
+        if (1 >= (++EltsFromV2)) {
+          V2Elt = (V2EltIdx0 - SrcElt) << 2;
         }
-
-        ++CurrElt;
+      } else if (CurrElt != SrcElt) {
+        monotonic = false;
       }
 
-      if (rotate) {
-        if (PrevElt > 0 && SrcElt < MaxElts) {
-          if ((PrevElt == SrcElt - 1)
-              || (PrevElt == MaxElts - 1 && SrcElt == 0)) {
-            PrevElt = SrcElt;
-            if (SrcElt == 0)
-              V0Elt = i;
-          } else {
-            rotate = false;
-          }
-        } else if (PrevElt == 0) {
-          // First time through, need to keep track of previous element
+      ++CurrElt;
+    }
+
+    if (rotate) {
+      if (PrevElt > 0 && SrcElt < MaxElts) {
+        if ((PrevElt == SrcElt - 1)
+            || (PrevElt == MaxElts - 1 && SrcElt == 0)) {
           PrevElt = SrcElt;
+          if (SrcElt == 0)
+            V0Elt = i;
         } else {
-          // This isn't a rotation, takes elements from vector 2
           rotate = false;
         }
+      } else if (PrevElt == 0) {
+        // First time through, need to keep track of previous element
+        PrevElt = SrcElt;
+      } else {
+        // This isn't a rotation, takes elements from vector 2
+        rotate = false;
       }
     }
   }
@@ -1768,17 +1769,11 @@
     unsigned BytesPerElement = EltVT.getSizeInBits()/8;
 
     SmallVector<SDValue, 16> ResultMask;
-    for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
-      unsigned SrcElt;
-      if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
-        SrcElt = 0;
-      else
-        SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getZExtValue();
-
-      for (unsigned j = 0; j < BytesPerElement; ++j) {
-        ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
-                                             MVT::i8));
-      }
+    for (unsigned i = 0, e = MaxElts; i != e; ++i) {
+      unsigned SrcElt = SVN->getMaskElt(i) < 0 ? 0 : SVN->getMaskElt(i);
+
+      for (unsigned j = 0; j < BytesPerElement; ++j)
+        ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,MVT::i8));
     }
 
     SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 27 13:41:29 2009
@@ -456,22 +456,21 @@
 
 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode.  Return
 /// true if Op is undef or if it matches the specified value.
-static bool isConstantOrUndef(SDValue Op, unsigned Val) {
-  return Op.getOpcode() == ISD::UNDEF ||
-         cast<ConstantSDNode>(Op)->getZExtValue() == Val;
+static bool isConstantOrUndef(int Op, int Val) {
+  return Op < 0 || Op == Val;
 }
 
 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
 /// VPKUHUM instruction.
-bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
+bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
   if (!isUnary) {
     for (unsigned i = 0; i != 16; ++i)
-      if (!isConstantOrUndef(N->getOperand(i),  i*2+1))
+      if (!isConstantOrUndef(N->getMaskElt(i),  i*2+1))
         return false;
   } else {
     for (unsigned i = 0; i != 8; ++i)
-      if (!isConstantOrUndef(N->getOperand(i),  i*2+1) ||
-          !isConstantOrUndef(N->getOperand(i+8),  i*2+1))
+      if (!isConstantOrUndef(N->getMaskElt(i),    i*2+1) ||
+          !isConstantOrUndef(N->getMaskElt(i+8),  i*2+1))
         return false;
   }
   return true;
@@ -479,18 +478,18 @@
 
 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
 /// VPKUWUM instruction.
-bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
+bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
   if (!isUnary) {
     for (unsigned i = 0; i != 16; i += 2)
-      if (!isConstantOrUndef(N->getOperand(i  ),  i*2+2) ||
-          !isConstantOrUndef(N->getOperand(i+1),  i*2+3))
+      if (!isConstantOrUndef(N->getMaskElt(i  ),  i*2+2) ||
+          !isConstantOrUndef(N->getMaskElt(i+1),  i*2+3))
         return false;
   } else {
     for (unsigned i = 0; i != 8; i += 2)
-      if (!isConstantOrUndef(N->getOperand(i  ),  i*2+2) ||
-          !isConstantOrUndef(N->getOperand(i+1),  i*2+3) ||
-          !isConstantOrUndef(N->getOperand(i+8),  i*2+2) ||
-          !isConstantOrUndef(N->getOperand(i+9),  i*2+3))
+      if (!isConstantOrUndef(N->getMaskElt(i  ),  i*2+2) ||
+          !isConstantOrUndef(N->getMaskElt(i+1),  i*2+3) ||
+          !isConstantOrUndef(N->getMaskElt(i+8),  i*2+2) ||
+          !isConstantOrUndef(N->getMaskElt(i+9),  i*2+3))
         return false;
   }
   return true;
@@ -498,27 +497,28 @@
 
 /// isVMerge - Common function, used to match vmrg* shuffles.
 ///
-static bool isVMerge(SDNode *N, unsigned UnitSize,
+static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
                      unsigned LHSStart, unsigned RHSStart) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR &&
-         N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
+  assert(N->getValueType(0) == MVT::v16i8 &&
+         "PPC only supports shuffles by bytes!");
   assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
          "Unsupported merge size!");
 
   for (unsigned i = 0; i != 8/UnitSize; ++i)     // Step over units
     for (unsigned j = 0; j != UnitSize; ++j) {   // Step over bytes within unit
-      if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
+      if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
                              LHSStart+j+i*UnitSize) ||
-          !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
+          !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
                              RHSStart+j+i*UnitSize))
         return false;
     }
-      return true;
+  return true;
 }
 
 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
-bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
+bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 
+                             bool isUnary) {
   if (!isUnary)
     return isVMerge(N, UnitSize, 8, 24);
   return isVMerge(N, UnitSize, 8, 8);
@@ -526,7 +526,8 @@
 
 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
-bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
+bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 
+                             bool isUnary) {
   if (!isUnary)
     return isVMerge(N, UnitSize, 0, 16);
   return isVMerge(N, UnitSize, 0, 0);
@@ -536,91 +537,90 @@
 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
 /// amount, otherwise return -1.
 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR &&
-         N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
+  assert(N->getValueType(0) == MVT::v16i8 &&
+         "PPC only supports shuffles by bytes!");
+
+  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
+  
   // Find the first non-undef value in the shuffle mask.
   unsigned i;
-  for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
+  for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
     /*search*/;
 
   if (i == 16) return -1;  // all undef.
 
-  // Otherwise, check to see if the rest of the elements are consequtively
+  // Otherwise, check to see if the rest of the elements are consecutively
   // numbered from this value.
-  unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getZExtValue();
+  unsigned ShiftAmt = SVOp->getMaskElt(i);
   if (ShiftAmt < i) return -1;
   ShiftAmt -= i;
 
   if (!isUnary) {
-    // Check the rest of the elements to see if they are consequtive.
+    // Check the rest of the elements to see if they are consecutive.
     for (++i; i != 16; ++i)
-      if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
+      if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
         return -1;
   } else {
-    // Check the rest of the elements to see if they are consequtive.
+    // Check the rest of the elements to see if they are consecutive.
     for (++i; i != 16; ++i)
-      if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
+      if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
         return -1;
   }
-
   return ShiftAmt;
 }
 
 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a splat of a single element that is suitable for input to
 /// VSPLTB/VSPLTH/VSPLTW.
-bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR &&
-         N->getNumOperands() == 16 &&
+bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
+  assert(N->getValueType(0) == MVT::v16i8 &&
          (EltSize == 1 || EltSize == 2 || EltSize == 4));
 
   // This is a splat operation if each element of the permute is the same, and
   // if the value doesn't reference the second vector.
-  unsigned ElementBase = 0;
-  SDValue Elt = N->getOperand(0);
-  if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
-    ElementBase = EltV->getZExtValue();
-  else
-    return false;   // FIXME: Handle UNDEF elements too!
-
-  if (cast<ConstantSDNode>(Elt)->getZExtValue() >= 16)
+  unsigned ElementBase = N->getMaskElt(0);
+  
+  // FIXME: Handle UNDEF elements too!
+  if (ElementBase >= 16)
     return false;
 
-  // Check that they are consequtive.
-  for (unsigned i = 1; i != EltSize; ++i) {
-    if (!isa<ConstantSDNode>(N->getOperand(i)) ||
-        cast<ConstantSDNode>(N->getOperand(i))->getZExtValue() != i+ElementBase)
+  // Check that the indices are consecutive, in the case of a multi-byte element
+  // splatted with a v16i8 mask.
+  for (unsigned i = 1; i != EltSize; ++i)
+    if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
       return false;
-  }
 
-  assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
   for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
-    if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
-    assert(isa<ConstantSDNode>(N->getOperand(i)) &&
-           "Invalid VECTOR_SHUFFLE mask!");
+    if (N->getMaskElt(i) < 0) continue;
     for (unsigned j = 0; j != EltSize; ++j)
-      if (N->getOperand(i+j) != N->getOperand(j))
+      if (N->getMaskElt(i+j) != N->getMaskElt(j))
         return false;
   }
-
   return true;
 }
 
 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
 /// are -0.0.
 bool PPC::isAllNegativeZeroVector(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-  if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
-    if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
+  BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
+
+  APInt APVal, APUndef;
+  unsigned BitSize;
+  bool HasAnyUndefs;
+  
+  if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32))
+    if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
       return CFP->getValueAPF().isNegZero();
+
   return false;
 }
 
 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
-  assert(isSplatShuffleMask(N, EltSize));
-  return cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() / EltSize;
+  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
+  assert(isSplatShuffleMask(SVOp, EltSize));
+  return SVOp->getMaskElt(0) / EltSize;
 }
 
 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
@@ -3149,11 +3149,10 @@
   LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
   RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
 
-  SDValue Ops[16];
+  int Ops[16];
   for (unsigned i = 0; i != 16; ++i)
-    Ops[i] = DAG.getConstant(i+Amt, MVT::i8);
-  SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, LHS, RHS,
-                        DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops,16));
+    Ops[i] = i + Amt;
+  SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
   return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
 }
 
@@ -3354,7 +3353,7 @@
   OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
   OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
 
-  unsigned ShufIdxs[16];
+  int ShufIdxs[16];
   switch (OpNum) {
   default: assert(0 && "Unknown i32 permute!");
   case OP_VMRGHW:
@@ -3392,13 +3391,11 @@
   case OP_VSLDOI12:
     return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
   }
-  SDValue Ops[16];
-  for (unsigned i = 0; i != 16; ++i)
-    Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8);
-
-  return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, OpLHS.getValueType(),
-                     OpLHS, OpRHS,
-                     DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16));
+  MVT VT = OpLHS.getValueType();
+  OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS);
+  OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS);
+  SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
+  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
 }
 
 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE.  If this
@@ -3406,28 +3403,29 @@
 /// return the code it can be lowered into.  Worst case, it can always be
 /// lowered into a vperm.
 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
-                                                 SelectionDAG &DAG) {
+                                               SelectionDAG &DAG) {
   DebugLoc dl = Op.getDebugLoc();
   SDValue V1 = Op.getOperand(0);
   SDValue V2 = Op.getOperand(1);
-  SDValue PermMask = Op.getOperand(2);
+  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
+  MVT VT = Op.getValueType();
 
   // Cases that are handled by instructions that take permute immediates
   // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
   // selected by the instruction selector.
   if (V2.getOpcode() == ISD::UNDEF) {
-    if (PPC::isSplatShuffleMask(PermMask.getNode(), 1) ||
-        PPC::isSplatShuffleMask(PermMask.getNode(), 2) ||
-        PPC::isSplatShuffleMask(PermMask.getNode(), 4) ||
-        PPC::isVPKUWUMShuffleMask(PermMask.getNode(), true) ||
-        PPC::isVPKUHUMShuffleMask(PermMask.getNode(), true) ||
-        PPC::isVSLDOIShuffleMask(PermMask.getNode(), true) != -1 ||
-        PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, true) ||
-        PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, true) ||
-        PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, true) ||
-        PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, true) ||
-        PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, true) ||
-        PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, true)) {
+    if (PPC::isSplatShuffleMask(SVOp, 1) ||
+        PPC::isSplatShuffleMask(SVOp, 2) ||
+        PPC::isSplatShuffleMask(SVOp, 4) ||
+        PPC::isVPKUWUMShuffleMask(SVOp, true) ||
+        PPC::isVPKUHUMShuffleMask(SVOp, true) ||
+        PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
+        PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
+        PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
+        PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
+        PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
+        PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
+        PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
       return Op;
     }
   }
@@ -3435,29 +3433,31 @@
   // Altivec has a variety of "shuffle immediates" that take two vector inputs
   // and produce a fixed permutation.  If any of these match, do not lower to
   // VPERM.
-  if (PPC::isVPKUWUMShuffleMask(PermMask.getNode(), false) ||
-      PPC::isVPKUHUMShuffleMask(PermMask.getNode(), false) ||
-      PPC::isVSLDOIShuffleMask(PermMask.getNode(), false) != -1 ||
-      PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, false) ||
-      PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, false) ||
-      PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, false) ||
-      PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, false) ||
-      PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, false) ||
-      PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, false))
+  if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
+      PPC::isVPKUHUMShuffleMask(SVOp, false) ||
+      PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
+      PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
+      PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
+      PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
+      PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
+      PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
+      PPC::isVMRGHShuffleMask(SVOp, 4, false))
     return Op;
 
   // Check to see if this is a shuffle of 4-byte values.  If so, we can use our
   // perfect shuffle table to emit an optimal matching sequence.
+  SmallVector<int, 16> PermMask;
+  SVOp->getMask(PermMask);
+  
   unsigned PFIndexes[4];
   bool isFourElementShuffle = true;
   for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
     unsigned EltNo = 8;   // Start out undef.
     for (unsigned j = 0; j != 4; ++j) {  // Intra-element byte.
-      if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
+      if (PermMask[i*4+j] < 0)
         continue;   // Undef, ignore it.
 
-      unsigned ByteSource =
-        cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getZExtValue();
+      unsigned ByteSource = PermMask[i*4+j];
       if ((ByteSource & 3) != j) {
         isFourElementShuffle = false;
         break;
@@ -3509,12 +3509,8 @@
   unsigned BytesPerElement = EltVT.getSizeInBits()/8;
 
   SmallVector<SDValue, 16> ResultMask;
-  for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
-    unsigned SrcElt;
-    if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
-      SrcElt = 0;
-    else
-      SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getZExtValue();
+  for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
+    unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
 
     for (unsigned j = 0; j != BytesPerElement; ++j)
       ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
@@ -3704,13 +3700,12 @@
     OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
 
     // Merge the results together.
-    SDValue Ops[16];
+    int Ops[16];
     for (unsigned i = 0; i != 8; ++i) {
-      Ops[i*2  ] = DAG.getConstant(2*i+1, MVT::i8);
-      Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
+      Ops[i*2  ] = 2*i+1;
+      Ops[i*2+1] = 2*i+1+16;
     }
-    return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, EvenParts, OddParts,
-                       DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16));
+    return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
   } else {
     assert(0 && "Unknown mul to lower!");
     abort();

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Mon Apr 27 13:41:29 2009
@@ -175,19 +175,21 @@
   namespace PPC {
     /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
     /// VPKUHUM instruction.
-    bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary);
+    bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
     
     /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
     /// VPKUWUM instruction.
-    bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary);
+    bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
 
     /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
     /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
-    bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
+    bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
+                            bool isUnary);
 
     /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
     /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
-    bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
+    bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
+                            bool isUnary);
     
     /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
     /// amount, otherwise return -1.
@@ -196,7 +198,7 @@
     /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
     /// specifies a splat of a single element that is suitable for input to
     /// VSPLTB/VSPLTH/VSPLTW.
-    bool isSplatShuffleMask(SDNode *N, unsigned EltSize);
+    bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
     
     /// isAllNegativeZeroVector - Returns true if all elements of build_vector
     /// are -0.0.

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Mon Apr 27 13:41:29 2009
@@ -15,96 +15,118 @@
 // Altivec transformation functions and pattern fragments.
 //
 
-/// VPKUHUM_shuffle_mask/VPKUWUM_shuffle_mask - Return true if this is a valid
-/// shuffle mask for the VPKUHUM or VPKUWUM instructions.
-def VPKUHUM_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVPKUHUMShuffleMask(N, false);
+
+def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                              (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
 }]>;
-def VPKUWUM_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVPKUWUMShuffleMask(N, false);
+def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                              (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
 }]>;
-
-def VPKUHUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVPKUHUMShuffleMask(N, true);
+def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                                    (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
 }]>;
-def VPKUWUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVPKUWUMShuffleMask(N, true);
+def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                                    (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
 }]>;
 
 
-def VMRGLB_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVMRGLShuffleMask(N, 1, false);
+def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                             (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
 }]>;
-def VMRGLH_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVMRGLShuffleMask(N, 2, false);
+def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                             (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
 }]>;
-def VMRGLW_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVMRGLShuffleMask(N, 4, false);
+def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                             (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
 }]>;
-def VMRGHB_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVMRGHShuffleMask(N, 1, false);
+def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                             (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
 }]>;
-def VMRGHH_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVMRGHShuffleMask(N, 2, false);
+def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                             (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
 }]>;
-def VMRGHW_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVMRGHShuffleMask(N, 4, false);
+def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                             (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
 }]>;
 
-def VMRGLB_unary_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVMRGLShuffleMask(N, 1, true);
+
+def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                                   (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
 }]>;
-def VMRGLH_unary_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVMRGLShuffleMask(N, 2, true);
+def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                                   (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
 }]>;
-def VMRGLW_unary_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVMRGLShuffleMask(N, 4, true);
+def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                                   (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
 }]>;
-def VMRGHB_unary_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVMRGHShuffleMask(N, 1, true);
+def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                                   (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
 }]>;
-def VMRGHH_unary_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVMRGHShuffleMask(N, 2, true);
+def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                                   (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
 }]>;
-def VMRGHW_unary_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isVMRGHShuffleMask(N, 4, true);
+def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                                   (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
 }]>;
 
-def VSLDOI_get_imm : SDNodeXForm<build_vector, [{
+
+def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
   return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
 }]>;
-def VSLDOI_shuffle_mask :  PatLeaf<(build_vector), [{
+def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                             (vector_shuffle node:$lhs, node:$rhs), [{
   return PPC::isVSLDOIShuffleMask(N, false) != -1;
 }], VSLDOI_get_imm>;
 
+
 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
 /// vector_shuffle(X,undef,mask) by the dag combiner.
-def VSLDOI_unary_get_imm : SDNodeXForm<build_vector, [{
+def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
   return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
 }]>;
-def VSLDOI_unary_shuffle_mask :  PatLeaf<(build_vector), [{
+def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                                   (vector_shuffle node:$lhs, node:$rhs), [{
   return PPC::isVSLDOIShuffleMask(N, true) != -1;
 }], VSLDOI_unary_get_imm>;
 
 
 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
-def VSPLTB_get_imm : SDNodeXForm<build_vector, [{
+def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
   return getI32Imm(PPC::getVSPLTImmediate(N, 1));
 }]>;
-def VSPLTB_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isSplatShuffleMask(N, 1);
+def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                             (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
 }], VSPLTB_get_imm>;
-def VSPLTH_get_imm : SDNodeXForm<build_vector, [{
+def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
   return getI32Imm(PPC::getVSPLTImmediate(N, 2));
 }]>;
-def VSPLTH_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isSplatShuffleMask(N, 2);
+def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                             (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
 }], VSPLTH_get_imm>;
-def VSPLTW_get_imm : SDNodeXForm<build_vector, [{
+def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
   return getI32Imm(PPC::getVSPLTImmediate(N, 4));
 }]>;
-def VSPLTW_shuffle_mask : PatLeaf<(build_vector), [{
-  return PPC::isSplatShuffleMask(N, 4);
+def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
+                             (vector_shuffle node:$lhs, node:$rhs), [{
+  return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
 }], VSPLTW_get_imm>;
 
 
@@ -268,8 +290,7 @@
 def VSLDOI  : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH),
                        "vsldoi $vD, $vA, $vB, $SH", VecFP,
                        [(set VRRC:$vD, 
-                             (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB,
-                                             VSLDOI_shuffle_mask:$SH))]>;
+                         (vsldoi_shuffle:$SH (v16i8 VRRC:$vA), VRRC:$vB))]>;
 
 // VX-Form instructions.  AltiVec arithmetic ops.
 def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
@@ -345,28 +366,22 @@
 
 def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
                       "vmrghb $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
-                                             VRRC:$vB, VMRGHB_shuffle_mask))]>;
+                      [(set VRRC:$vD, (vmrghb_shuffle VRRC:$vA, VRRC:$vB))]>;
 def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
                       "vmrghh $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
-                                             VRRC:$vB, VMRGHH_shuffle_mask))]>;
+                      [(set VRRC:$vD, (vmrghh_shuffle VRRC:$vA, VRRC:$vB))]>;
 def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
                       "vmrghw $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
-                                             VRRC:$vB, VMRGHW_shuffle_mask))]>;
+                      [(set VRRC:$vD, (vmrghw_shuffle VRRC:$vA, VRRC:$vB))]>;
 def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
                       "vmrglb $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
-                                             VRRC:$vB, VMRGLB_shuffle_mask))]>;
+                      [(set VRRC:$vD, (vmrglb_shuffle VRRC:$vA, VRRC:$vB))]>;
 def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
                       "vmrglh $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
-                                             VRRC:$vB, VMRGLH_shuffle_mask))]>;
+                      [(set VRRC:$vD, (vmrglh_shuffle VRRC:$vA, VRRC:$vB))]>;
 def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
                       "vmrglw $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
-                                             VRRC:$vB, VMRGLW_shuffle_mask))]>;
+                      [(set VRRC:$vD, (vmrglw_shuffle VRRC:$vA, VRRC:$vB))]>;
 
 def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
 def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
@@ -440,16 +455,16 @@
 
 def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
                       "vspltb $vD, $vB, $UIMM", VecPerm,
-                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
-                                      VSPLTB_shuffle_mask:$UIMM))]>;
+                      [(set VRRC:$vD,
+                        (vspltb_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
 def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
                       "vsplth $vD, $vB, $UIMM", VecPerm,
-                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
-                                      VSPLTH_shuffle_mask:$UIMM))]>;
+                      [(set VRRC:$vD,
+                        (vsplth_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
 def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
                       "vspltw $vD, $vB, $UIMM", VecPerm,
-                      [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
-                                      VSPLTW_shuffle_mask:$UIMM))]>;
+                      [(set VRRC:$vD, 
+                        (vspltw_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
 
 def VSR    : VX1_Int< 708, "vsr"  , int_ppc_altivec_vsr>;
 def VSRO   : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
@@ -479,13 +494,13 @@
 def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
 def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
                        "vpkuhum $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
-                                             VRRC:$vB, VPKUHUM_shuffle_mask))]>;
+                       [(set VRRC:$vD,
+                         (vpkuhum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>;
 def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
 def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
                        "vpkuwum $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
-                                             VRRC:$vB, VPKUWUM_shuffle_mask))]>;
+                       [(set VRRC:$vD,
+                         (vpkuwum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>;
 def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
 
 // Vector Unpack.
@@ -603,25 +618,25 @@
 // Shuffles.
 
 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
-def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VSLDOI_unary_shuffle_mask:$in),
-        (VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_unary_shuffle_mask:$in)>;
-def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUWUM_unary_shuffle_mask:$in),
+def:Pat<(vsldoi_unary_shuffle:$in (v16i8 VRRC:$vA), undef),
+        (VSLDOI VRRC:$vA, VRRC:$vA, (VSLDOI_unary_get_imm VRRC:$in))>;
+def:Pat<(vpkuwum_unary_shuffle (v16i8 VRRC:$vA), undef),
         (VPKUWUM VRRC:$vA, VRRC:$vA)>;
-def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUHUM_unary_shuffle_mask:$in),
+def:Pat<(vpkuhum_unary_shuffle (v16i8 VRRC:$vA), undef),
         (VPKUHUM VRRC:$vA, VRRC:$vA)>;
 
 // Match vmrg*(x,x)
-def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLB_unary_shuffle_mask:$in),
+def:Pat<(vmrglb_unary_shuffle (v16i8 VRRC:$vA), undef),
         (VMRGLB VRRC:$vA, VRRC:$vA)>;
-def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLH_unary_shuffle_mask:$in),
+def:Pat<(vmrglh_unary_shuffle (v16i8 VRRC:$vA), undef),
         (VMRGLH VRRC:$vA, VRRC:$vA)>;
-def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLW_unary_shuffle_mask:$in),
+def:Pat<(vmrglw_unary_shuffle (v16i8 VRRC:$vA), undef),
         (VMRGLW VRRC:$vA, VRRC:$vA)>;
-def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHB_unary_shuffle_mask:$in),
+def:Pat<(vmrghb_unary_shuffle (v16i8 VRRC:$vA), undef),
         (VMRGHB VRRC:$vA, VRRC:$vA)>;
-def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHH_unary_shuffle_mask:$in),
+def:Pat<(vmrghh_unary_shuffle (v16i8 VRRC:$vA), undef),
         (VMRGHH VRRC:$vA, VRRC:$vA)>;
-def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHW_unary_shuffle_mask:$in),
+def:Pat<(vmrghw_unary_shuffle (v16i8 VRRC:$vA), undef),
         (VMRGHW VRRC:$vA, VRRC:$vA)>;
 
 // Logical Operations

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Apr 27 13:41:29 2009
@@ -45,7 +45,8 @@
 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
 
 // Forward declarations.
-static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl);
+static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
+                       SDValue V2);
 
 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
   : TargetLowering(TM) {
@@ -1667,9 +1668,7 @@
             // Special case: passing MMX values in XMM registers.
             Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
             Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
-            Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64,
-                              DAG.getUNDEF(MVT::v2i64), Arg,
-                              getMOVLMask(2, DAG, dl));
+            Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
             break;
           }
           }
@@ -2138,186 +2137,164 @@
   }
 }
 
-/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode.  Return
-/// true if Op is undef or if its value falls within the specified range (L, H].
-static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
-  if (Op.getOpcode() == ISD::UNDEF)
-    return true;
-
-  unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue();
-  return (Val >= Low && Val < Hi);
+/// isUndefOrInRange - Return true if Val is undef or if its value falls within
+/// the specified range (L, H].
+static bool isUndefOrInRange(int Val, int Low, int Hi) {
+  return (Val < 0) || (Val >= Low && Val < Hi);
 }
 
-/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode.  Return
-/// true if Op is undef or if its value equal to the specified value.
-static bool isUndefOrEqual(SDValue Op, unsigned Val) {
-  if (Op.getOpcode() == ISD::UNDEF)
+/// isUndefOrEqual - Val is either less than zero (undef) or equal to the
+/// specified value.
+static bool isUndefOrEqual(int Val, int CmpVal) {
+  if (Val < 0 || Val == CmpVal)
     return true;
-  return cast<ConstantSDNode>(Op)->getZExtValue() == Val;
+  return false;
 }
 
-/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
-/// specifies a shuffle of elements that is suitable for input to PSHUFD.
-bool X86::isPSHUFDMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-
-  if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
-    return false;
-
-  // Check if the value doesn't reference the second vector.
-  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
-    SDValue Arg = N->getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF) continue;
-    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-    if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e)
-      return false;
-  }
-
-  return true;
+/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
+/// is suitable for input to PSHUFD or PSHUFW.  That is, it doesn't reference
+/// the second operand.
+static bool isPSHUFDMask(SmallVectorImpl<int> &Mask, MVT VT) {
+  if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
+    return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
+  if (VT == MVT::v2f64 || VT == MVT::v2i64)
+    return (Mask[0] < 2 && Mask[1] < 2);
+  return false;
 }
 
-/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
-/// specifies a shuffle of elements that is suitable for input to PSHUFHW.
-bool X86::isPSHUFHWMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
+bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
+  SmallVector<int, 8> M; 
+  N->getMask(M);
+  return ::isPSHUFDMask(M, N->getValueType(0));
+}
 
-  if (N->getNumOperands() != 8)
+/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
+/// is suitable for input to PSHUFHW.
+static bool isPSHUFHWMask(SmallVectorImpl<int> &Mask, MVT VT) {
+  if (VT != MVT::v8i16)
     return false;
-
-  // Lower quadword copied in order.
-  for (unsigned i = 0; i != 4; ++i) {
-    SDValue Arg = N->getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF) continue;
-    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-    if (cast<ConstantSDNode>(Arg)->getZExtValue() != i)
+  
+  // Lower quadword copied in order or undef.
+  for (int i = 0; i != 4; ++i)
+    if (Mask[i] >= 0 && Mask[i] != i)
       return false;
-  }
-
+  
   // Upper quadword shuffled.
-  for (unsigned i = 4; i != 8; ++i) {
-    SDValue Arg = N->getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF) continue;
-    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-    unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
-    if (Val < 4 || Val > 7)
+  for (int i = 4; i != 8; ++i)
+    if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
       return false;
-  }
-
+  
   return true;
 }
 
-/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
-/// specifies a shuffle of elements that is suitable for input to PSHUFLW.
-bool X86::isPSHUFLWMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
+bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
+  SmallVector<int, 8> M; 
+  N->getMask(M);
+  return ::isPSHUFHWMask(M, N->getValueType(0));
+}
 
-  if (N->getNumOperands() != 8)
+/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
+/// is suitable for input to PSHUFLW.
+static bool isPSHUFLWMask(SmallVectorImpl<int> &Mask, MVT VT) {
+  if (VT != MVT::v8i16)
     return false;
-
+  
   // Upper quadword copied in order.
-  for (unsigned i = 4; i != 8; ++i)
-    if (!isUndefOrEqual(N->getOperand(i), i))
+  for (int i = 4; i != 8; ++i)
+    if (Mask[i] >= 0 && Mask[i] != i)
       return false;
-
+  
   // Lower quadword shuffled.
-  for (unsigned i = 0; i != 4; ++i)
-    if (!isUndefOrInRange(N->getOperand(i), 0, 4))
+  for (int i = 0; i != 4; ++i)
+    if (Mask[i] >= 4)
       return false;
-
+  
   return true;
 }
 
+bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
+  SmallVector<int, 8> M; 
+  N->getMask(M);
+  return ::isPSHUFLWMask(M, N->getValueType(0));
+}
+
 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
-template<class SDOperand>
-static bool isSHUFPMask(SDOperand *Elems, unsigned NumElems) {
-  if (NumElems != 2 && NumElems != 4) return false;
-
-  unsigned Half = NumElems / 2;
-  for (unsigned i = 0; i < Half; ++i)
-    if (!isUndefOrInRange(Elems[i], 0, NumElems))
+static bool isSHUFPMask(SmallVectorImpl<int> &Mask, MVT VT) {
+  int NumElems = VT.getVectorNumElements();
+  if (NumElems != 2 && NumElems != 4)
+    return false;
+  
+  int Half = NumElems / 2;
+  for (int i = 0; i < Half; ++i)
+    if (!isUndefOrInRange(Mask[i], 0, NumElems))
       return false;
-  for (unsigned i = Half; i < NumElems; ++i)
-    if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
+  for (int i = Half; i < NumElems; ++i)
+    if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
       return false;
-
+  
   return true;
 }
 
-bool X86::isSHUFPMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-  return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
+bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
+  SmallVector<int, 8> M;
+  N->getMask(M);
+  return ::isSHUFPMask(M, N->getValueType(0));
 }
 
 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
 /// half elements to come from vector 1 (which would equal the dest.) and
 /// the upper half to come from vector 2.
-template<class SDOperand>
-static bool isCommutedSHUFP(SDOperand *Ops, unsigned NumOps) {
-  if (NumOps != 2 && NumOps != 4) return false;
-
-  unsigned Half = NumOps / 2;
-  for (unsigned i = 0; i < Half; ++i)
-    if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
+static bool isCommutedSHUFPMask(SmallVectorImpl<int> &Mask, MVT VT) {
+  int NumElems = VT.getVectorNumElements();
+  
+  if (NumElems != 2 && NumElems != 4) 
+    return false;
+  
+  int Half = NumElems / 2;
+  for (int i = 0; i < Half; ++i)
+    if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
       return false;
-  for (unsigned i = Half; i < NumOps; ++i)
-    if (!isUndefOrInRange(Ops[i], 0, NumOps))
+  for (int i = Half; i < NumElems; ++i)
+    if (!isUndefOrInRange(Mask[i], 0, NumElems))
       return false;
   return true;
 }
 
-static bool isCommutedSHUFP(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-  return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
+static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
+  SmallVector<int, 8> M;
+  N->getMask(M);
+  return isCommutedSHUFPMask(M, N->getValueType(0));
 }
 
 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
-bool X86::isMOVHLPSMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-
-  if (N->getNumOperands() != 4)
+bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
+  if (N->getValueType(0).getVectorNumElements() != 4)
     return false;
 
   // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
-  return isUndefOrEqual(N->getOperand(0), 6) &&
-         isUndefOrEqual(N->getOperand(1), 7) &&
-         isUndefOrEqual(N->getOperand(2), 2) &&
-         isUndefOrEqual(N->getOperand(3), 3);
-}
-
-/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
-/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
-/// <2, 3, 2, 3>
-bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-
-  if (N->getNumOperands() != 4)
-    return false;
-
-  // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
-  return isUndefOrEqual(N->getOperand(0), 2) &&
-         isUndefOrEqual(N->getOperand(1), 3) &&
-         isUndefOrEqual(N->getOperand(2), 2) &&
-         isUndefOrEqual(N->getOperand(3), 3);
+  return isUndefOrEqual(N->getMaskElt(0), 6) &&
+         isUndefOrEqual(N->getMaskElt(1), 7) &&
+         isUndefOrEqual(N->getMaskElt(2), 2) &&
+         isUndefOrEqual(N->getMaskElt(3), 3);
 }
 
 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
-bool X86::isMOVLPMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
+bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
+  unsigned NumElems = N->getValueType(0).getVectorNumElements();
 
-  unsigned NumElems = N->getNumOperands();
   if (NumElems != 2 && NumElems != 4)
     return false;
 
   for (unsigned i = 0; i < NumElems/2; ++i)
-    if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
+    if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
       return false;
 
   for (unsigned i = NumElems/2; i < NumElems; ++i)
-    if (!isUndefOrEqual(N->getOperand(i), i))
+    if (!isUndefOrEqual(N->getMaskElt(i), i))
       return false;
 
   return true;
@@ -2326,37 +2303,49 @@
 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
 /// and MOVLHPS.
-bool X86::isMOVHPMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
+bool X86::isMOVHPMask(ShuffleVectorSDNode *N) {
+  unsigned NumElems = N->getValueType(0).getVectorNumElements();
 
-  unsigned NumElems = N->getNumOperands();
   if (NumElems != 2 && NumElems != 4)
     return false;
 
   for (unsigned i = 0; i < NumElems/2; ++i)
-    if (!isUndefOrEqual(N->getOperand(i), i))
+    if (!isUndefOrEqual(N->getMaskElt(i), i))
       return false;
 
-  for (unsigned i = 0; i < NumElems/2; ++i) {
-    SDValue Arg = N->getOperand(i + NumElems/2);
-    if (!isUndefOrEqual(Arg, i + NumElems))
+  for (unsigned i = 0; i < NumElems/2; ++i)
+    if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
       return false;
-  }
 
   return true;
 }
 
+/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
+/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
+/// <2, 3, 2, 3>
+bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
+  unsigned NumElems = N->getValueType(0).getVectorNumElements();
+  
+  if (NumElems != 4)
+    return false;
+  
+  return isUndefOrEqual(N->getMaskElt(0), 2) && 
+         isUndefOrEqual(N->getMaskElt(1), 3) &&
+         isUndefOrEqual(N->getMaskElt(2), 2) && 
+         isUndefOrEqual(N->getMaskElt(3), 3);
+}
+
 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
-template<class SDOperand>
-bool static isUNPCKLMask(SDOperand *Elts, unsigned NumElts,
+static bool isUNPCKLMask(SmallVectorImpl<int> &Mask, MVT VT,
                          bool V2IsSplat = false) {
+  int NumElts = VT.getVectorNumElements();
   if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
     return false;
-
-  for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
-    SDValue BitI  = Elts[i];
-    SDValue BitI1 = Elts[i+1];
+  
+  for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
+    int BitI  = Mask[i];
+    int BitI1 = Mask[i+1];
     if (!isUndefOrEqual(BitI, j))
       return false;
     if (V2IsSplat) {
@@ -2367,26 +2356,26 @@
         return false;
     }
   }
-
   return true;
 }
 
-bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-  return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
+bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
+  SmallVector<int, 8> M;
+  N->getMask(M);
+  return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
 }
 
 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
-template<class SDOperand>
-bool static isUNPCKHMask(SDOperand *Elts, unsigned NumElts,
+static bool isUNPCKHMask(SmallVectorImpl<int> &Mask, MVT VT, 
                          bool V2IsSplat = false) {
+  int NumElts = VT.getVectorNumElements();
   if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
     return false;
-
-  for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
-    SDValue BitI  = Elts[i];
-    SDValue BitI1 = Elts[i+1];
+  
+  for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
+    int BitI  = Mask[i];
+    int BitI1 = Mask[i+1];
     if (!isUndefOrEqual(BitI, j + NumElts/2))
       return false;
     if (V2IsSplat) {
@@ -2397,270 +2386,176 @@
         return false;
     }
   }
-
   return true;
 }
 
-bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-  return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
+bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
+  SmallVector<int, 8> M;
+  N->getMask(M);
+  return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
 }
 
 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
 /// <0, 0, 1, 1>
-bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-
-  unsigned NumElems = N->getNumOperands();
+static bool isUNPCKL_v_undef_Mask(SmallVectorImpl<int> &Mask, MVT VT) {
+  int NumElems = VT.getVectorNumElements();
   if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
     return false;
-
-  for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
-    SDValue BitI  = N->getOperand(i);
-    SDValue BitI1 = N->getOperand(i+1);
-
+  
+  for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
+    int BitI  = Mask[i];
+    int BitI1 = Mask[i+1];
     if (!isUndefOrEqual(BitI, j))
       return false;
     if (!isUndefOrEqual(BitI1, j))
       return false;
   }
-
   return true;
 }
 
+bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
+  SmallVector<int, 8> M;
+  N->getMask(M);
+  return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
+}
+
 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
 /// <2, 2, 3, 3>
-bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-
-  unsigned NumElems = N->getNumOperands();
+static bool isUNPCKH_v_undef_Mask(SmallVectorImpl<int> &Mask, MVT VT) {
+  int NumElems = VT.getVectorNumElements();
   if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
     return false;
-
-  for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
-    SDValue BitI  = N->getOperand(i);
-    SDValue BitI1 = N->getOperand(i + 1);
-
+  
+  for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
+    int BitI  = Mask[i];
+    int BitI1 = Mask[i+1];
     if (!isUndefOrEqual(BitI, j))
       return false;
     if (!isUndefOrEqual(BitI1, j))
       return false;
   }
-
   return true;
 }
 
+bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
+  SmallVector<int, 8> M;
+  N->getMask(M);
+  return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
+}
+
 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to MOVSS,
 /// MOVSD, and MOVD, i.e. setting the lowest element.
-template<class SDOperand>
-static bool isMOVLMask(SDOperand *Elts, unsigned NumElts) {
+static bool isMOVLMask(SmallVectorImpl<int> &Mask, MVT VT) {
+  int NumElts = VT.getVectorNumElements();
   if (NumElts != 2 && NumElts != 4)
     return false;
-
-  if (!isUndefOrEqual(Elts[0], NumElts))
+  
+  if (!isUndefOrEqual(Mask[0], NumElts))
     return false;
-
-  for (unsigned i = 1; i < NumElts; ++i) {
-    if (!isUndefOrEqual(Elts[i], i))
+  
+  for (int i = 1; i < NumElts; ++i)
+    if (!isUndefOrEqual(Mask[i], i))
       return false;
-  }
-
+  
   return true;
 }
 
-bool X86::isMOVLMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-  return ::isMOVLMask(N->op_begin(), N->getNumOperands());
+bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
+  SmallVector<int, 8> M;
+  N->getMask(M);
+  return ::isMOVLMask(M, N->getValueType(0));
 }
 
 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
 /// of what x86 movss want. X86 movs requires the lowest  element to be lowest
 /// element of vector 2 and the other elements to come from vector 1 in order.
-template<class SDOperand>
-static bool isCommutedMOVL(SDOperand *Ops, unsigned NumOps,
-                           bool V2IsSplat = false,
-                           bool V2IsUndef = false) {
+static bool isCommutedMOVLMask(SmallVectorImpl<int> &Mask, MVT VT,
+                               bool V2IsSplat = false, bool V2IsUndef = false) {
+  int NumOps = VT.getVectorNumElements();
   if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
     return false;
-
-  if (!isUndefOrEqual(Ops[0], 0))
+  
+  if (!isUndefOrEqual(Mask[0], 0))
     return false;
-
-  for (unsigned i = 1; i < NumOps; ++i) {
-    SDValue Arg = Ops[i];
-    if (!(isUndefOrEqual(Arg, i+NumOps) ||
-          (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
-          (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
+  
+  for (int i = 1; i < NumOps; ++i)
+    if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
+          (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
+          (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
       return false;
-  }
-
+  
   return true;
 }
 
-static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
+static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
                            bool V2IsUndef = false) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-  return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
-                        V2IsSplat, V2IsUndef);
+  SmallVector<int, 8> M;
+  N->getMask(M);
+  return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
 }
 
 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
-bool X86::isMOVSHDUPMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-
-  if (N->getNumOperands() != 4)
+bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
+  if (N->getValueType(0).getVectorNumElements() != 4)
     return false;
 
   // Expect 1, 1, 3, 3
   for (unsigned i = 0; i < 2; ++i) {
-    SDValue Arg = N->getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF) continue;
-    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-    unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
-    if (Val != 1) return false;
+    int Elt = N->getMaskElt(i);
+    if (Elt >= 0 && Elt != 1)
+      return false;
   }
 
   bool HasHi = false;
   for (unsigned i = 2; i < 4; ++i) {
-    SDValue Arg = N->getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF) continue;
-    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-    unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
-    if (Val != 3) return false;
-    HasHi = true;
+    int Elt = N->getMaskElt(i);
+    if (Elt >= 0 && Elt != 3)
+      return false;
+    if (Elt == 3)
+      HasHi = true;
   }
-
   // Don't use movshdup if it can be done with a shufps.
+  // FIXME: verify that matching u, u, 3, 3 is what we want.
   return HasHi;
 }
 
 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
-bool X86::isMOVSLDUPMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-
-  if (N->getNumOperands() != 4)
+bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
+  if (N->getValueType(0).getVectorNumElements() != 4)
     return false;
 
   // Expect 0, 0, 2, 2
-  for (unsigned i = 0; i < 2; ++i) {
-    SDValue Arg = N->getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF) continue;
-    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-    unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
-    if (Val != 0) return false;
-  }
+  for (unsigned i = 0; i < 2; ++i)
+    if (N->getMaskElt(i) > 0)
+      return false;
 
   bool HasHi = false;
   for (unsigned i = 2; i < 4; ++i) {
-    SDValue Arg = N->getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF) continue;
-    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-    unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
-    if (Val != 2) return false;
-    HasHi = true;
-  }
-
-  // Don't use movshdup if it can be done with a shufps.
-  return HasHi;
-}
-
-/// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
-/// specifies a identity operation on the LHS or RHS.
-static bool isIdentityMask(SDNode *N, bool RHS = false) {
-  unsigned NumElems = N->getNumOperands();
-  for (unsigned i = 0; i < NumElems; ++i)
-    if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
+    int Elt = N->getMaskElt(i);
+    if (Elt >= 0 && Elt != 2)
       return false;
-  return true;
-}
-
-/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
-/// a splat of a single element.
-static bool isSplatMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-
-  // This is a splat operation if each element of the permute is the same, and
-  // if the value doesn't reference the second vector.
-  unsigned NumElems = N->getNumOperands();
-  SDValue ElementBase;
-  unsigned i = 0;
-  for (; i != NumElems; ++i) {
-    SDValue Elt = N->getOperand(i);
-    if (isa<ConstantSDNode>(Elt)) {
-      ElementBase = Elt;
-      break;
-    }
-  }
-
-  if (!ElementBase.getNode())
-    return false;
-
-  for (; i != NumElems; ++i) {
-    SDValue Arg = N->getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF) continue;
-    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-    if (Arg != ElementBase) return false;
-  }
-
-  // Make sure it is a splat of the first vector operand.
-  return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems;
-}
-
-/// getSplatMaskEltNo - Given a splat mask, return the index to the element
-/// we want to splat.
-static SDValue getSplatMaskEltNo(SDNode *N) {
-  assert(isSplatMask(N) && "Not a splat mask");
-  unsigned NumElems = N->getNumOperands();
-  SDValue ElementBase;
-  unsigned i = 0;
-  for (; i != NumElems; ++i) {
-    SDValue Elt = N->getOperand(i);
-    if (isa<ConstantSDNode>(Elt))
-      return Elt;
+    if (Elt == 2)
+      HasHi = true;
   }
-  assert(0 && " No splat value found!");
-  return SDValue();
-}
-
-
-/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
-/// a splat of a single element and it's a 2 or 4 element mask.
-bool X86::isSplatMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-
-  // We can only splat 64-bit, and 32-bit quantities with a single instruction.
-  if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
-    return false;
-  return ::isSplatMask(N);
-}
-
-/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
-/// specifies a splat of zero element.
-bool X86::isSplatLoMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-
-  for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
-    if (!isUndefOrEqual(N->getOperand(i), 0))
-      return false;
-  return true;
+  // Don't use movsldup if it can be done with a shufps.
+  return HasHi;
 }
 
 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
-bool X86::isMOVDDUPMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-
-  unsigned e = N->getNumOperands() / 2;
-  for (unsigned i = 0; i < e; ++i)
-    if (!isUndefOrEqual(N->getOperand(i), i))
+bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
+  int e = N->getValueType(0).getVectorNumElements() / 2;
+  
+  for (int i = 0; i < e; ++i)
+    if (!isUndefOrEqual(N->getMaskElt(i), i))
       return false;
-  for (unsigned i = 0; i < e; ++i)
-    if (!isUndefOrEqual(N->getOperand(e+i), i))
+  for (int i = 0; i < e; ++i)
+    if (!isUndefOrEqual(N->getMaskElt(e+i), i))
       return false;
   return true;
 }
@@ -2669,20 +2564,19 @@
 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
 /// instructions.
 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
-  unsigned NumOperands = N->getNumOperands();
+  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
+  int NumOperands = SVOp->getValueType(0).getVectorNumElements();
+
   unsigned Shift = (NumOperands == 4) ? 2 : 1;
   unsigned Mask = 0;
-  for (unsigned i = 0; i < NumOperands; ++i) {
-    unsigned Val = 0;
-    SDValue Arg = N->getOperand(NumOperands-i-1);
-    if (Arg.getOpcode() != ISD::UNDEF)
-      Val = cast<ConstantSDNode>(Arg)->getZExtValue();
+  for (int i = 0; i < NumOperands; ++i) {
+    int Val = SVOp->getMaskElt(NumOperands-i-1);
+    if (Val < 0) Val = 0;
     if (Val >= NumOperands) Val -= NumOperands;
     Mask |= Val;
     if (i != NumOperands - 1)
       Mask <<= Shift;
   }
-
   return Mask;
 }
 
@@ -2690,19 +2584,16 @@
 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
 /// instructions.
 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
+  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
   unsigned Mask = 0;
   // 8 nodes, but we only care about the last 4.
   for (unsigned i = 7; i >= 4; --i) {
-    unsigned Val = 0;
-    SDValue Arg = N->getOperand(i);
-    if (Arg.getOpcode() != ISD::UNDEF) {
-      Val = cast<ConstantSDNode>(Arg)->getZExtValue();
+    int Val = SVOp->getMaskElt(i);
+    if (Val >= 0)
       Mask |= (Val - 4);
-    }
     if (i != 4)
       Mask <<= 2;
   }
-
   return Mask;
 }
 
@@ -2710,90 +2601,67 @@
 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
 /// instructions.
 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
+  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
   unsigned Mask = 0;
   // 8 nodes, but we only care about the first 4.
   for (int i = 3; i >= 0; --i) {
-    unsigned Val = 0;
-    SDValue Arg = N->getOperand(i);
-    if (Arg.getOpcode() != ISD::UNDEF)
-      Val = cast<ConstantSDNode>(Arg)->getZExtValue();
-    Mask |= Val;
+    int Val = SVOp->getMaskElt(i);
+    if (Val >= 0)
+      Mask |= Val;
     if (i != 0)
       Mask <<= 2;
   }
-
   return Mask;
 }
 
-/// CommuteVectorShuffle - Swap vector_shuffle operands as well as
-/// values in ther permute mask.
-static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
-                                      SDValue &V2, SDValue &Mask,
-                                      SelectionDAG &DAG) {
-  MVT VT = Op.getValueType();
-  MVT MaskVT = Mask.getValueType();
-  MVT EltVT = MaskVT.getVectorElementType();
-  unsigned NumElems = Mask.getNumOperands();
-  SmallVector<SDValue, 8> MaskVec;
-  DebugLoc dl = Op.getDebugLoc();
-
-  for (unsigned i = 0; i != NumElems; ++i) {
-    SDValue Arg = Mask.getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF) {
-      MaskVec.push_back(DAG.getUNDEF(EltVT));
-      continue;
-    }
-    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-    unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
-    if (Val < NumElems)
-      MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
+/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
+/// their permute mask.
+static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
+                                    SelectionDAG &DAG) {
+  MVT VT = SVOp->getValueType(0);
+  int NumElems = VT.getVectorNumElements();
+  SmallVector<int, 8> MaskVec;
+  
+  for (int i = 0; i != NumElems; ++i) {
+    int idx = SVOp->getMaskElt(i);
+    if (idx < 0)
+      MaskVec.push_back(idx);
+    else if (idx < NumElems)
+      MaskVec.push_back(idx + NumElems);
     else
-      MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
+      MaskVec.push_back(idx - NumElems);
   }
-
-  std::swap(V1, V2);
-  Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems);
-  return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask);
+  return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
+                              SVOp->getOperand(0), &MaskVec[0]);
 }
 
 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
 /// the two vector operands have swapped position.
-static
-SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG, DebugLoc dl) {
-  MVT MaskVT = Mask.getValueType();
-  MVT EltVT = MaskVT.getVectorElementType();
-  unsigned NumElems = Mask.getNumOperands();
-  SmallVector<SDValue, 8> MaskVec;
-  for (unsigned i = 0; i != NumElems; ++i) {
-    SDValue Arg = Mask.getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF) {
-      MaskVec.push_back(DAG.getUNDEF(EltVT));
+static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, MVT VT) {
+  int NumElems = VT.getVectorNumElements();
+  for (int i = 0; i != NumElems; ++i) {
+    int idx = Mask[i];
+    if (idx < 0)
       continue;
-    }
-    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-    unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
-    if (Val < NumElems)
-      MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
+    else if (idx < NumElems)
+      Mask[i] = idx + NumElems;
     else
-      MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
+      Mask[i] = idx - NumElems;
   }
-  return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems);
 }
 
-
 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
 /// match movhlps. The lower half elements should come from upper half of
 /// V1 (and in order), and the upper half elements should come from the upper
 /// half of V2 (and in order).
-static bool ShouldXformToMOVHLPS(SDNode *Mask) {
-  unsigned NumElems = Mask->getNumOperands();
-  if (NumElems != 4)
+static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
+  if (Op->getValueType(0).getVectorNumElements() != 4)
     return false;
   for (unsigned i = 0, e = 2; i != e; ++i)
-    if (!isUndefOrEqual(Mask->getOperand(i), i+2))
+    if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
       return false;
   for (unsigned i = 2; i != 4; ++i)
-    if (!isUndefOrEqual(Mask->getOperand(i), i+4))
+    if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
       return false;
   return true;
 }
@@ -2817,7 +2685,8 @@
 /// V1 (and in order), and the upper half elements should come from the upper
 /// half of V2 (and in order). And since V1 will become the source of the
 /// MOVLP, it must be either a vector load or a scalar load to vector.
-static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
+static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
+                               ShuffleVectorSDNode *Op) {
   if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
     return false;
   // Is V2 is a vector load, don't do this transformation. We will try to use
@@ -2825,14 +2694,15 @@
   if (ISD::isNON_EXTLoad(V2))
     return false;
 
-  unsigned NumElems = Mask->getNumOperands();
+  int NumElems = Op->getValueType(0).getVectorNumElements();
+  
   if (NumElems != 2 && NumElems != 4)
     return false;
-  for (unsigned i = 0, e = NumElems/2; i != e; ++i)
-    if (!isUndefOrEqual(Mask->getOperand(i), i))
+  for (int i = 0, e = NumElems/2; i != e; ++i)
+    if (!isUndefOrEqual(Op->getMaskElt(i), i))
       return false;
-  for (unsigned i = NumElems/2; i != NumElems; ++i)
-    if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
+  for (int i = NumElems/2; i != NumElems; ++i)
+    if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
       return false;
   return true;
 }
@@ -2850,29 +2720,6 @@
   return true;
 }
 
-/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
-/// to an undef.
-static bool isUndefShuffle(SDNode *N) {
-  if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
-    return false;
-
-  SDValue V1 = N->getOperand(0);
-  SDValue V2 = N->getOperand(1);
-  SDValue Mask = N->getOperand(2);
-  unsigned NumElems = Mask.getNumOperands();
-  for (unsigned i = 0; i != NumElems; ++i) {
-    SDValue Arg = Mask.getOperand(i);
-    if (Arg.getOpcode() != ISD::UNDEF) {
-      unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
-      if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
-        return false;
-      else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
-        return false;
-    }
-  }
-  return true;
-}
-
 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
 /// constant +0.0.
 static inline bool isZeroNode(SDValue Elt) {
@@ -2883,34 +2730,25 @@
 }
 
 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
-/// to an zero vector.
-static bool isZeroShuffle(SDNode *N) {
-  if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
-    return false;
-
+/// to an zero vector. 
+/// FIXME: move to dag combiner?
+static bool isZeroShuffle(ShuffleVectorSDNode *N) {
   SDValue V1 = N->getOperand(0);
   SDValue V2 = N->getOperand(1);
-  SDValue Mask = N->getOperand(2);
-  unsigned NumElems = Mask.getNumOperands();
-  for (unsigned i = 0; i != NumElems; ++i) {
-    SDValue Arg = Mask.getOperand(i);
-    if (Arg.getOpcode() == ISD::UNDEF)
-      continue;
-
-    unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
-    if (Idx < NumElems) {
-      unsigned Opc = V1.getNode()->getOpcode();
-      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
+  int NumElems = N->getValueType(0).getVectorNumElements();
+  for (int i = 0; i != NumElems; ++i) {
+    int Idx = N->getMaskElt(i);
+    if (Idx >= NumElems) {
+      unsigned Opc = V2.getOpcode();
+      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
         continue;
-      if (Opc != ISD::BUILD_VECTOR ||
-          !isZeroNode(V1.getNode()->getOperand(Idx)))
+      if (Opc != ISD::BUILD_VECTOR || !isZeroNode(V2.getOperand(Idx-NumElems)))
         return false;
-    } else if (Idx >= NumElems) {
-      unsigned Opc = V2.getNode()->getOpcode();
-      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
+    } else if (Idx >= 0) {
+      unsigned Opc = V1.getOpcode();
+      if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
         continue;
-      if (Opc != ISD::BUILD_VECTOR ||
-          !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
+      if (Opc != ISD::BUILD_VECTOR || !isZeroNode(V1.getOperand(Idx)))
         return false;
     }
   }
@@ -2958,127 +2796,92 @@
 
 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
 /// that point to V2 points to its first element.
-static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
-  assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
-
+static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
+  MVT VT = SVOp->getValueType(0);
+  int NumElems = VT.getVectorNumElements();
+  
   bool Changed = false;
-  SmallVector<SDValue, 8> MaskVec;
-  unsigned NumElems = Mask.getNumOperands();
-  for (unsigned i = 0; i != NumElems; ++i) {
-    SDValue Arg = Mask.getOperand(i);
-    if (Arg.getOpcode() != ISD::UNDEF) {
-      unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
-      if (Val > NumElems) {
-        Arg = DAG.getConstant(NumElems, Arg.getValueType());
-        Changed = true;
-      }
+  SmallVector<int, 8> MaskVec;
+  SVOp->getMask(MaskVec);
+  
+  for (int i = 0; i != NumElems; ++i) {
+    if (MaskVec[i] > NumElems) {
+      MaskVec[i] = NumElems;
+      Changed = true;
     }
-    MaskVec.push_back(Arg);
   }
-
   if (Changed)
-    Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(),
-                       Mask.getValueType(),
-                       &MaskVec[0], MaskVec.size());
-  return Mask;
+    return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
+                                SVOp->getOperand(1), &MaskVec[0]);
+  return SDValue(SVOp, 0);
 }
 
 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
 /// operation of specified width.
-static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl) {
-  MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-  MVT BaseVT = MaskVT.getVectorElementType();
-
-  SmallVector<SDValue, 8> MaskVec;
-  MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
+static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
+                       SDValue V2) {
+  unsigned NumElems = VT.getVectorNumElements();
+  SmallVector<int, 8> Mask;
+  Mask.push_back(NumElems);
   for (unsigned i = 1; i != NumElems; ++i)
-    MaskVec.push_back(DAG.getConstant(i, BaseVT));
-  return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                     &MaskVec[0], MaskVec.size());
+    Mask.push_back(i);
+  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
 }
 
-/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
-/// of specified width.
-static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG,
-                              DebugLoc dl) {
-  MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-  MVT BaseVT = MaskVT.getVectorElementType();
-  SmallVector<SDValue, 8> MaskVec;
+/// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
+static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
+                          SDValue V2) {
+  unsigned NumElems = VT.getVectorNumElements();
+  SmallVector<int, 8> Mask;
   for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
-    MaskVec.push_back(DAG.getConstant(i,            BaseVT));
-    MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
+    Mask.push_back(i);
+    Mask.push_back(i + NumElems);
   }
-  return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                     &MaskVec[0], MaskVec.size());
+  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
 }
 
-/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
-/// of specified width.
-static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG,
-                              DebugLoc dl) {
-  MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-  MVT BaseVT = MaskVT.getVectorElementType();
+/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
+static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
+                          SDValue V2) {
+  unsigned NumElems = VT.getVectorNumElements();
   unsigned Half = NumElems/2;
-  SmallVector<SDValue, 8> MaskVec;
+  SmallVector<int, 8> Mask;
   for (unsigned i = 0; i != Half; ++i) {
-    MaskVec.push_back(DAG.getConstant(i + Half,            BaseVT));
-    MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
+    Mask.push_back(i + Half);
+    Mask.push_back(i + NumElems + Half);
   }
-  return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                     &MaskVec[0], MaskVec.size());
-}
-
-/// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
-/// element #0 of a vector with the specified index, leaving the rest of the
-/// elements in place.
-static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
-                                   SelectionDAG &DAG, DebugLoc dl) {
-  MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-  MVT BaseVT = MaskVT.getVectorElementType();
-  SmallVector<SDValue, 8> MaskVec;
-  // Element #0 of the result gets the elt we are replacing.
-  MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
-  for (unsigned i = 1; i != NumElems; ++i)
-    MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
-  return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                     &MaskVec[0], MaskVec.size());
+  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
 }
 
 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
-static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
-  MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
-  MVT VT = Op.getValueType();
-  if (PVT == VT)
-    return Op;
-  SDValue V1 = Op.getOperand(0);
-  SDValue Mask = Op.getOperand(2);
-  unsigned MaskNumElems = Mask.getNumOperands();
-  unsigned NumElems = MaskNumElems;
-  DebugLoc dl = Op.getDebugLoc();
-  // Special handling of v4f32 -> v4i32.
-  if (VT != MVT::v4f32) {
-    // Find which element we want to splat.
-    SDNode* EltNoNode = getSplatMaskEltNo(Mask.getNode()).getNode();
-    unsigned EltNo = cast<ConstantSDNode>(EltNoNode)->getZExtValue();
-    // unpack elements to the correct location
-    while (NumElems > 4) {
-      if (EltNo < NumElems/2) {
-        Mask = getUnpacklMask(MaskNumElems, DAG, dl);
-      } else {
-        Mask = getUnpackhMask(MaskNumElems, DAG, dl);
-        EltNo -= NumElems/2;
-      }
-      V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1, Mask);
-      NumElems >>= 1;
+static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG, 
+                            bool HasSSE2) {
+  if (SV->getValueType(0).getVectorNumElements() <= 4)
+    return SDValue(SV, 0);
+  
+  MVT PVT = MVT::v4f32;
+  MVT VT = SV->getValueType(0);
+  DebugLoc dl = SV->getDebugLoc();
+  SDValue V1 = SV->getOperand(0);
+  int NumElems = VT.getVectorNumElements();
+  int EltNo = SV->getSplatIndex();
+
+  // unpack elements to the correct location
+  while (NumElems > 4) {
+    if (EltNo < NumElems/2) {
+      V1 = getUnpackl(DAG, dl, VT, V1, V1);
+    } else {
+      V1 = getUnpackh(DAG, dl, VT, V1, V1);
+      EltNo -= NumElems/2;
     }
-    SDValue Cst = DAG.getConstant(EltNo, MVT::i32);
-    Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
+    NumElems >>= 1;
   }
-
+  
+  // Perform the splat.
+  int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
   V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
-  SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1,
-                                  DAG.getUNDEF(PVT), Mask);
-  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle);
+  V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
+  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
 }
 
 /// isVectorLoad - Returns true if the node is a vector load, a scalar
@@ -3095,32 +2898,28 @@
 
 /// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
 ///
-static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask,
-                                   SelectionDAG &DAG, bool HasSSE3) {
+static SDValue CanonicalizeMovddup(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
+                                   bool HasSSE3) {
   // If we have sse3 and shuffle has more than one use or input is a load, then
   // use movddup. Otherwise, use movlhps.
-  bool UseMovddup = HasSSE3 && (!Op.hasOneUse() || isVectorLoad(V1));
+  SDValue V1 = SV->getOperand(0);
+  
+  bool UseMovddup = HasSSE3 && (!SV->hasOneUse() || isVectorLoad(V1));
   MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32;
-  MVT VT = Op.getValueType();
+  MVT VT = SV->getValueType(0);
   if (VT == PVT)
-    return Op;
-  DebugLoc dl = Op.getDebugLoc();
-  unsigned NumElems = PVT.getVectorNumElements();
-  if (NumElems == 2) {
-    SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
-    Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
+    return SDValue(SV, 0);
+  
+  DebugLoc dl = SV->getDebugLoc();
+  V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
+  if (PVT.getVectorNumElements() == 2) {
+    int Mask[2] = { 0, 0 };
+    V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), Mask);
   } else {
-    assert(NumElems == 4);
-    SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32);
-    SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32);
-    Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
-                       Cst0, Cst1, Cst0, Cst1);
+    int Mask[4] = { 0, 1, 0, 1 };
+    V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), Mask);
   }
-
-  V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
-  SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1,
-                                DAG.getUNDEF(PVT), Mask);
-  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle);
+  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
 }
 
 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
@@ -3130,39 +2929,31 @@
 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
                                              bool isZero, bool HasSSE2,
                                              SelectionDAG &DAG) {
-  DebugLoc dl = V2.getDebugLoc();
   MVT VT = V2.getValueType();
   SDValue V1 = isZero
-    ? getZeroVector(VT, HasSSE2, DAG, dl) : DAG.getUNDEF(VT);
-  unsigned NumElems = V2.getValueType().getVectorNumElements();
-  MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-  MVT EVT = MaskVT.getVectorElementType();
-  SmallVector<SDValue, 16> MaskVec;
+    ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
+  unsigned NumElems = VT.getVectorNumElements();
+  SmallVector<int, 16> MaskVec;
   for (unsigned i = 0; i != NumElems; ++i)
-    if (i == Idx)  // If this is the insertion idx, put the low elt of V2 here.
-      MaskVec.push_back(DAG.getConstant(NumElems, EVT));
-    else
-      MaskVec.push_back(DAG.getConstant(i, EVT));
-  SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                               &MaskVec[0], MaskVec.size());
-  return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask);
+    // If this is the insertion idx, put the low elt of V2 here.
+    MaskVec.push_back(i == Idx ? NumElems : i);
+  return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
 }
 
 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
 /// a shuffle that is zero.
 static
-unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
-                                  unsigned NumElems, bool Low,
-                                  SelectionDAG &DAG) {
+unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
+                                  bool Low, SelectionDAG &DAG) {
   unsigned NumZeros = 0;
-  for (unsigned i = 0; i < NumElems; ++i) {
+  for (int i = 0; i < NumElems; ++i) {
     unsigned Index = Low ? i : NumElems-i-1;
-    SDValue Idx = Mask.getOperand(Index);
-    if (Idx.getOpcode() == ISD::UNDEF) {
+    int Idx = SVOp->getMaskElt(Index);
+    if (Idx < 0) {
       ++NumZeros;
       continue;
     }
-    SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
+    SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
     if (Elt.getNode() && isZeroNode(Elt))
       ++NumZeros;
     else
@@ -3173,40 +2964,39 @@
 
 /// isVectorShift - Returns true if the shuffle can be implemented as a
 /// logical left or right shift of a vector.
-static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
+/// FIXME: split into pslldqi, psrldqi, palignr variants.
+static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
                           bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
-  unsigned NumElems = Mask.getNumOperands();
+  int NumElems = SVOp->getValueType(0).getVectorNumElements();
 
   isLeft = true;
-  unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
+  unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
   if (!NumZeros) {
     isLeft = false;
-    NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
+    NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
     if (!NumZeros)
       return false;
   }
-
   bool SeenV1 = false;
   bool SeenV2 = false;
-  for (unsigned i = NumZeros; i < NumElems; ++i) {
-    unsigned Val = isLeft ? (i - NumZeros) : i;
-    SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
-    if (Idx.getOpcode() == ISD::UNDEF)
+  for (int i = NumZeros; i < NumElems; ++i) {
+    int Val = isLeft ? (i - NumZeros) : i;
+    int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
+    if (Idx < 0)
       continue;
-    unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
-    if (Index < NumElems)
+    if (Idx < NumElems)
       SeenV1 = true;
     else {
-      Index -= NumElems;
+      Idx -= NumElems;
       SeenV2 = true;
     }
-    if (Index != Val)
+    if (Idx != Val)
       return false;
   }
   if (SeenV1 && SeenV2)
     return false;
 
-  ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
+  ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
   ShAmt = NumZeros;
   return true;
 }
@@ -3291,8 +3081,8 @@
 /// getVShift - Return a vector logical shift node.
 ///
 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
-                           unsigned NumBits, SelectionDAG &DAG,
-                           const TargetLowering &TLI, DebugLoc dl) {
+                         unsigned NumBits, SelectionDAG &DAG,
+                         const TargetLowering &TLI, DebugLoc dl) {
   bool isMMX = VT.getSizeInBits() == 64;
   MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
   unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
@@ -3377,11 +3167,13 @@
         // Now we have our 32-bit value zero extended in the low element of
         // a vector.  If Idx != 0, swizzle it into place.
         if (Idx != 0) {
-          SDValue Ops[] = {
-            Item, DAG.getUNDEF(Item.getValueType()),
-            getSwapEltZeroMask(VecElts, Idx, DAG, dl)
-          };
-          Item = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VecVT, Ops, 3);
+          SmallVector<int, 4> Mask;
+          Mask.push_back(Idx);
+          for (unsigned i = 1; i != VecElts; ++i)
+            Mask.push_back(i);
+          Item = DAG.getVectorShuffle(VecVT, dl, Item,
+                                      DAG.getUNDEF(Item.getValueType()), 
+                                      &Mask[0]);
         }
         return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
       }
@@ -3425,15 +3217,10 @@
       // Turn it into a shuffle of zero and zero-extended scalar to vector.
       Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
                                          Subtarget->hasSSE2(), DAG);
-      MVT MaskVT  = MVT::getIntVectorWithNumElements(NumElems);
-      MVT MaskEVT = MaskVT.getVectorElementType();
-      SmallVector<SDValue, 8> MaskVec;
+      SmallVector<int, 8> MaskVec;
       for (unsigned i = 0; i < NumElems; i++)
-        MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
-      SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                   &MaskVec[0], MaskVec.size());
-      return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, Item,
-                         DAG.getUNDEF(VT), Mask);
+        MaskVec.push_back(i == Idx ? 0 : 1);
+      return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
     }
   }
 
@@ -3491,54 +3278,53 @@
           V[i] = V[i*2];  // Must be a zero vector.
           break;
         case 1:
-          V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2+1], V[i*2],
-                             getMOVLMask(NumElems, DAG, dl));
+          V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
           break;
         case 2:
-          V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1],
-                             getMOVLMask(NumElems, DAG, dl));
+          V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
           break;
         case 3:
-          V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1],
-                             getUnpacklMask(NumElems, DAG, dl));
+          V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
           break;
       }
     }
 
-    MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-    MVT EVT = MaskVT.getVectorElementType();
-    SmallVector<SDValue, 8> MaskVec;
+    SmallVector<int, 8> MaskVec;
     bool Reverse = (NonZeros & 0x3) == 2;
     for (unsigned i = 0; i < 2; ++i)
-      if (Reverse)
-        MaskVec.push_back(DAG.getConstant(1-i, EVT));
-      else
-        MaskVec.push_back(DAG.getConstant(i, EVT));
+      MaskVec.push_back(Reverse ? 1-i : i);
     Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
     for (unsigned i = 0; i < 2; ++i)
-      if (Reverse)
-        MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
-      else
-        MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
-    SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                     &MaskVec[0], MaskVec.size());
-    return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[0], V[1], ShufMask);
+      MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
+    return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
   }
 
   if (Values.size() > 2) {
+    // If we have SSE 4.1, Expand into a number of inserts unless the number of
+    // values to be inserted is equal to the number of elements, in which case
+    // use the unpack code below in the hopes of matching the consecutive elts
+    // load merge pattern for shuffles. 
+    // FIXME: We could probably just check that here directly.
+    if (Values.size() < NumElems && VT.getSizeInBits() == 128 && 
+        getSubtarget()->hasSSE41()) {
+      V[0] = DAG.getUNDEF(VT);
+      for (unsigned i = 0; i < NumElems; ++i)
+        if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
+          V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
+                             Op.getOperand(i), DAG.getIntPtrConstant(i));
+      return V[0];
+    }
     // Expand into a number of unpckl*.
     // e.g. for v4f32
     //   Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
     //         : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
     //   Step 2: unpcklps X, Y ==>    <3, 2, 1, 0>
-    SDValue UnpckMask = getUnpacklMask(NumElems, DAG, dl);
     for (unsigned i = 0; i < NumElems; ++i)
       V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
     NumElems >>= 1;
     while (NumElems != 0) {
       for (unsigned i = 0; i < NumElems; ++i)
-        V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i], V[i + NumElems],
-                           UnpckMask);
+        V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
       NumElems >>= 1;
     }
     return V[0];
@@ -3553,11 +3339,11 @@
 // 3. [ssse3] 2 x pshufb + 1 x por
 // 4. [all]   mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
 static
-SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
-                                 SDValue PermMask, SelectionDAG &DAG,
-                                 X86TargetLowering &TLI, DebugLoc dl) {
-  SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
-                                   PermMask.getNode()->op_end());
+SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
+                                 SelectionDAG &DAG, X86TargetLowering &TLI) {
+  SDValue V1 = SVOp->getOperand(0);
+  SDValue V2 = SVOp->getOperand(1);
+  DebugLoc dl = SVOp->getDebugLoc();
   SmallVector<int, 8> MaskVals;
 
   // Determine if more than 1 of the words in each of the low and high quadwords
@@ -3568,9 +3354,7 @@
   BitVector InputQuads(4);
   for (unsigned i = 0; i < 8; ++i) {
     SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
-    SDValue Elt = MaskElts[i];
-    int EltIdx = Elt.getOpcode() == ISD::UNDEF ? -1 : 
-                 cast<ConstantSDNode>(Elt)->getZExtValue();
+    int EltIdx = SVOp->getMaskElt(i);
     MaskVals.push_back(EltIdx);
     if (EltIdx < 0) {
       ++Quad[0];
@@ -3623,14 +3407,12 @@
   // words from all 4 input quadwords.
   SDValue NewV;
   if (BestLoQuad >= 0 || BestHiQuad >= 0) {
-    SmallVector<SDValue,8> MaskV;
-    MaskV.push_back(DAG.getConstant(BestLoQuad < 0 ? 0 : BestLoQuad, MVT::i64));
-    MaskV.push_back(DAG.getConstant(BestHiQuad < 0 ? 1 : BestHiQuad, MVT::i64));
-    SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, &MaskV[0], 2);
-    
-    NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64,
-                     DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
-                     DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), Mask);
+    SmallVector<int, 8> MaskV;
+    MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
+    MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
+    NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 
+                  DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
+                  DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
     NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
 
     // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
@@ -3668,15 +3450,8 @@
     // If we've eliminated the use of V2, and the new mask is a pshuflw or
     // pshufhw, that's as cheap as it gets.  Return the new shuffle.
     if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
-      MaskV.clear();
-      for (unsigned i = 0; i != 8; ++i)
-        MaskV.push_back((MaskVals[i] < 0) ? DAG.getUNDEF(MVT::i16)
-                                          : DAG.getConstant(MaskVals[i],
-                                                            MVT::i16));
-      return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV, 
-                         DAG.getUNDEF(MVT::v8i16), 
-                         DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16,
-                                     &MaskV[0], 8));
+      return DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 
+                                  DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
     }
   }
   
@@ -3733,49 +3508,45 @@
   // and update MaskVals with new element order.
   BitVector InOrder(8);
   if (BestLoQuad >= 0) {
-    SmallVector<SDValue, 8> MaskV;
+    SmallVector<int, 8> MaskV;
     for (int i = 0; i != 4; ++i) {
       int idx = MaskVals[i];
       if (idx < 0) {
-        MaskV.push_back(DAG.getUNDEF(MVT::i16));
+        MaskV.push_back(-1);
         InOrder.set(i);
       } else if ((idx / 4) == BestLoQuad) {
-        MaskV.push_back(DAG.getConstant(idx & 3, MVT::i16));
+        MaskV.push_back(idx & 3);
         InOrder.set(i);
       } else {
-        MaskV.push_back(DAG.getUNDEF(MVT::i16));
+        MaskV.push_back(-1);
       }
     }
     for (unsigned i = 4; i != 8; ++i)
-      MaskV.push_back(DAG.getConstant(i, MVT::i16));
-    NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV,
-                       DAG.getUNDEF(MVT::v8i16),
-                       DAG.getNode(ISD::BUILD_VECTOR, dl,
-                                   MVT::v8i16, &MaskV[0], 8));
+      MaskV.push_back(i);
+    NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
+                                &MaskV[0]);
   }
   
   // If BestHi >= 0, generate a pshufhw to put the high elements in order,
   // and update MaskVals with the new element order.
   if (BestHiQuad >= 0) {
-    SmallVector<SDValue, 8> MaskV;
+    SmallVector<int, 8> MaskV;
     for (unsigned i = 0; i != 4; ++i)
-      MaskV.push_back(DAG.getConstant(i, MVT::i16));
+      MaskV.push_back(i);
     for (unsigned i = 4; i != 8; ++i) {
       int idx = MaskVals[i];
       if (idx < 0) {
-        MaskV.push_back(DAG.getUNDEF(MVT::i16));
+        MaskV.push_back(-1);
         InOrder.set(i);
       } else if ((idx / 4) == BestHiQuad) {
-        MaskV.push_back(DAG.getConstant((idx & 3) + 4, MVT::i16));
+        MaskV.push_back((idx & 3) + 4);
         InOrder.set(i);
       } else {
-        MaskV.push_back(DAG.getUNDEF(MVT::i16));
+        MaskV.push_back(-1);
       }
     }
-    NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV,
-                       DAG.getUNDEF(MVT::v8i16),
-                       DAG.getNode(ISD::BUILD_VECTOR, dl,
-                                   MVT::v8i16, &MaskV[0], 8));
+    NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
+                                &MaskV[0]);
   }
   
   // In case BestHi & BestLo were both -1, which means each quadword has a word
@@ -3811,12 +3582,13 @@
 // 2. [ssse3] 2 x pshufb + 1 x por
 // 3. [all]   v8i16 shuffle + N x pextrw + rotate + pinsrw
 static
-SDValue LowerVECTOR_SHUFFLEv16i8(SDValue V1, SDValue V2,
-                                 SDValue PermMask, SelectionDAG &DAG,
-                                 X86TargetLowering &TLI, DebugLoc dl) {
-  SmallVector<SDValue, 16> MaskElts(PermMask.getNode()->op_begin(),
-                                    PermMask.getNode()->op_end());
+SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
+                                 SelectionDAG &DAG, X86TargetLowering &TLI) {
+  SDValue V1 = SVOp->getOperand(0);
+  SDValue V2 = SVOp->getOperand(1);
+  DebugLoc dl = SVOp->getDebugLoc();
   SmallVector<int, 16> MaskVals;
+  SVOp->getMask(MaskVals);
   
   // If we have SSSE3, case 1 is generated when all result bytes come from
   // one of  the inputs.  Otherwise, case 2 is generated.  If no SSSE3 is 
@@ -3825,10 +3597,7 @@
   bool V1Only = true;
   bool V2Only = true;
   for (unsigned i = 0; i < 16; ++i) {
-    SDValue Elt = MaskElts[i];
-    int EltIdx = Elt.getOpcode() == ISD::UNDEF ? -1 : 
-                 cast<ConstantSDNode>(Elt)->getZExtValue();
-    MaskVals.push_back(EltIdx);
+    int EltIdx = MaskVals[i];
     if (EltIdx < 0)
       continue;
     if (EltIdx < 16)
@@ -3958,11 +3727,13 @@
 /// the right sequence. e.g.
 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
 static
-SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
-                                MVT VT,
-                                SDValue PermMask, SelectionDAG &DAG,
-                                TargetLowering &TLI, DebugLoc dl) {
-  unsigned NumElems = PermMask.getNumOperands();
+SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
+                                 SelectionDAG &DAG,
+                                 TargetLowering &TLI, DebugLoc dl) {
+  MVT VT = SVOp->getValueType(0);
+  SDValue V1 = SVOp->getOperand(0);
+  SDValue V2 = SVOp->getOperand(1);
+  unsigned NumElems = VT.getVectorNumElements();
   unsigned NewWidth = (NumElems == 4) ? 2 : 4;
   MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
   MVT MaskEltVT = MaskVT.getVectorElementType();
@@ -3981,38 +3752,35 @@
     else
       NewVT = MVT::v2f64;
   }
-  unsigned Scale = NumElems / NewWidth;
-  SmallVector<SDValue, 8> MaskVec;
+  int Scale = NumElems / NewWidth;
+  SmallVector<int, 8> MaskVec;
   for (unsigned i = 0; i < NumElems; i += Scale) {
-    unsigned StartIdx = ~0U;
-    for (unsigned j = 0; j < Scale; ++j) {
-      SDValue Elt = PermMask.getOperand(i+j);
-      if (Elt.getOpcode() == ISD::UNDEF)
+    int StartIdx = -1;
+    for (int j = 0; j < Scale; ++j) {
+      int EltIdx = SVOp->getMaskElt(i+j);
+      if (EltIdx < 0)
         continue;
-      unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
-      if (StartIdx == ~0U)
+      if (StartIdx == -1)
         StartIdx = EltIdx - (EltIdx % Scale);
       if (EltIdx != StartIdx + j)
         return SDValue();
     }
-    if (StartIdx == ~0U)
-      MaskVec.push_back(DAG.getUNDEF(MaskEltVT));
+    if (StartIdx == -1)
+      MaskVec.push_back(-1);
     else
-      MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
+      MaskVec.push_back(StartIdx / Scale);
   }
 
   V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
   V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
-  return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, V1, V2,
-                     DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                 &MaskVec[0], MaskVec.size()));
+  return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
 }
 
 /// getVZextMovL - Return a zero-extending vector move low node.
 ///
 static SDValue getVZextMovL(MVT VT, MVT OpVT,
-                              SDValue SrcOp, SelectionDAG &DAG,
-                              const X86Subtarget *Subtarget, DebugLoc dl) {
+                            SDValue SrcOp, SelectionDAG &DAG,
+                            const X86Subtarget *Subtarget, DebugLoc dl) {
   if (VT == MVT::v2f64 || VT == MVT::v4f32) {
     LoadSDNode *LD = NULL;
     if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
@@ -4046,31 +3814,34 @@
 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
 /// shuffles.
 static SDValue
-LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
-                          SDValue PermMask, MVT VT, SelectionDAG &DAG,
-                          DebugLoc dl) {
-  MVT MaskVT = PermMask.getValueType();
-  MVT MaskEVT = MaskVT.getVectorElementType();
+LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
+  SDValue V1 = SVOp->getOperand(0);
+  SDValue V2 = SVOp->getOperand(1);
+  DebugLoc dl = SVOp->getDebugLoc();
+  MVT VT = SVOp->getValueType(0);
+  
   SmallVector<std::pair<int, int>, 8> Locs;
   Locs.resize(4);
-  SmallVector<SDValue, 8> Mask1(4, DAG.getUNDEF(MaskEVT));
+  SmallVector<int, 8> Mask1(4U, -1);
+  SmallVector<int, 8> PermMask;
+  SVOp->getMask(PermMask);
+
   unsigned NumHi = 0;
   unsigned NumLo = 0;
   for (unsigned i = 0; i != 4; ++i) {
-    SDValue Elt = PermMask.getOperand(i);
-    if (Elt.getOpcode() == ISD::UNDEF) {
+    int Idx = PermMask[i];
+    if (Idx < 0) {
       Locs[i] = std::make_pair(-1, -1);
     } else {
-      unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
-      assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
-      if (Val < 4) {
+      assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
+      if (Idx < 4) {
         Locs[i] = std::make_pair(0, NumLo);
-        Mask1[NumLo] = Elt;
+        Mask1[NumLo] = Idx;
         NumLo++;
       } else {
         Locs[i] = std::make_pair(1, NumHi);
         if (2+NumHi < 4)
-          Mask1[2+NumHi] = Elt;
+          Mask1[2+NumHi] = Idx;
         NumHi++;
       }
     }
@@ -4081,24 +3852,21 @@
     // implemented with two shuffles. First shuffle gather the elements.
     // The second shuffle, which takes the first shuffle as both of its
     // vector operands, put the elements into the right order.
-    V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
-                     DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                 &Mask1[0], Mask1.size()));
+    V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
 
-    SmallVector<SDValue, 8> Mask2(4, DAG.getUNDEF(MaskEVT));
+    SmallVector<int, 8> Mask2(4U, -1);
+    
     for (unsigned i = 0; i != 4; ++i) {
       if (Locs[i].first == -1)
         continue;
       else {
         unsigned Idx = (i < 2) ? 0 : 4;
         Idx += Locs[i].first * 2 + Locs[i].second;
-        Mask2[i] = DAG.getConstant(Idx, MaskEVT);
+        Mask2[i] = Idx;
       }
     }
 
-    return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1,
-                       DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                   &Mask2[0], Mask2.size()));
+    return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
   } else if (NumLo == 3 || NumHi == 3) {
     // Otherwise, we must have three elements from one vector, call it X, and
     // one element from the other, call it Y.  First, use a shufps to build an
@@ -4109,60 +3877,51 @@
     // from X.
     if (NumHi == 3) {
       // Normalize it so the 3 elements come from V1.
-      PermMask = CommuteVectorShuffleMask(PermMask, DAG, dl);
+      CommuteVectorShuffleMask(PermMask, VT);
       std::swap(V1, V2);
     }
 
     // Find the element from V2.
     unsigned HiIndex;
     for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
-      SDValue Elt = PermMask.getOperand(HiIndex);
-      if (Elt.getOpcode() == ISD::UNDEF)
+      int Val = PermMask[HiIndex];
+      if (Val < 0)
         continue;
-      unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
       if (Val >= 4)
         break;
     }
 
-    Mask1[0] = PermMask.getOperand(HiIndex);
-    Mask1[1] = DAG.getUNDEF(MaskEVT);
-    Mask1[2] = PermMask.getOperand(HiIndex^1);
-    Mask1[3] = DAG.getUNDEF(MaskEVT);
-    V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
-                     DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &Mask1[0], 4));
+    Mask1[0] = PermMask[HiIndex];
+    Mask1[1] = -1;
+    Mask1[2] = PermMask[HiIndex^1];
+    Mask1[3] = -1;
+    V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
 
     if (HiIndex >= 2) {
-      Mask1[0] = PermMask.getOperand(0);
-      Mask1[1] = PermMask.getOperand(1);
-      Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
-      Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
-      return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
-                         DAG.getNode(ISD::BUILD_VECTOR, dl,
-                                     MaskVT, &Mask1[0], 4));
+      Mask1[0] = PermMask[0];
+      Mask1[1] = PermMask[1];
+      Mask1[2] = HiIndex & 1 ? 6 : 4;
+      Mask1[3] = HiIndex & 1 ? 4 : 6;
+      return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
     } else {
-      Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
-      Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
-      Mask1[2] = PermMask.getOperand(2);
-      Mask1[3] = PermMask.getOperand(3);
-      if (Mask1[2].getOpcode() != ISD::UNDEF)
-        Mask1[2] =
-          DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4,
-                          MaskEVT);
-      if (Mask1[3].getOpcode() != ISD::UNDEF)
-        Mask1[3] =
-          DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
-                          MaskEVT);
-      return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V2, V1,
-                         DAG.getNode(ISD::BUILD_VECTOR, dl,
-                                     MaskVT, &Mask1[0], 4));
+      Mask1[0] = HiIndex & 1 ? 2 : 0;
+      Mask1[1] = HiIndex & 1 ? 0 : 2;
+      Mask1[2] = PermMask[2];
+      Mask1[3] = PermMask[3];
+      if (Mask1[2] >= 0)
+        Mask1[2] += 4;
+      if (Mask1[3] >= 0)
+        Mask1[3] += 4;
+      return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
     }
   }
 
   // Break it into (shuffle shuffle_hi, shuffle_lo).
   Locs.clear();
-  SmallVector<SDValue,8> LoMask(4, DAG.getUNDEF(MaskEVT));
-  SmallVector<SDValue,8> HiMask(4, DAG.getUNDEF(MaskEVT));
-  SmallVector<SDValue,8> *MaskPtr = &LoMask;
+  SmallVector<int,8> LoMask(4U, -1);
+  SmallVector<int,8> HiMask(4U, -1);
+
+  SmallVector<int,8> *MaskPtr = &LoMask;
   unsigned MaskIdx = 0;
   unsigned LoIdx = 0;
   unsigned HiIdx = 2;
@@ -4173,84 +3932,67 @@
       LoIdx = 0;
       HiIdx = 2;
     }
-    SDValue Elt = PermMask.getOperand(i);
-    if (Elt.getOpcode() == ISD::UNDEF) {
+    int Idx = PermMask[i];
+    if (Idx < 0) {
       Locs[i] = std::make_pair(-1, -1);
-    } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) {
+    } else if (Idx < 4) {
       Locs[i] = std::make_pair(MaskIdx, LoIdx);
-      (*MaskPtr)[LoIdx] = Elt;
+      (*MaskPtr)[LoIdx] = Idx;
       LoIdx++;
     } else {
       Locs[i] = std::make_pair(MaskIdx, HiIdx);
-      (*MaskPtr)[HiIdx] = Elt;
+      (*MaskPtr)[HiIdx] = Idx;
       HiIdx++;
     }
   }
 
-  SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
-                                    DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                                &LoMask[0], LoMask.size()));
-  SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
-                                    DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                                &HiMask[0], HiMask.size()));
-  SmallVector<SDValue, 8> MaskOps;
+  SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
+  SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
+  SmallVector<int, 8> MaskOps;
   for (unsigned i = 0; i != 4; ++i) {
     if (Locs[i].first == -1) {
-      MaskOps.push_back(DAG.getUNDEF(MaskEVT));
+      MaskOps.push_back(-1);
     } else {
       unsigned Idx = Locs[i].first * 4 + Locs[i].second;
-      MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
+      MaskOps.push_back(Idx);
     }
   }
-  return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, LoShuffle, HiShuffle,
-                     DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                 &MaskOps[0], MaskOps.size()));
+  return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
 }
 
 SDValue
 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
+  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
   SDValue V1 = Op.getOperand(0);
   SDValue V2 = Op.getOperand(1);
-  SDValue PermMask = Op.getOperand(2);
   MVT VT = Op.getValueType();
   DebugLoc dl = Op.getDebugLoc();
-  unsigned NumElems = PermMask.getNumOperands();
+  unsigned NumElems = VT.getVectorNumElements();
   bool isMMX = VT.getSizeInBits() == 64;
   bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
   bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
   bool V1IsSplat = false;
   bool V2IsSplat = false;
 
-  // FIXME: Check for legal shuffle and return?
-  
-  if (isUndefShuffle(Op.getNode()))
-    return DAG.getUNDEF(VT);
-
-  if (isZeroShuffle(Op.getNode()))
+  if (isZeroShuffle(SVOp))
     return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
 
-  if (isIdentityMask(PermMask.getNode()))
-    return V1;
-  else if (isIdentityMask(PermMask.getNode(), true))
-    return V2;
-
   // Canonicalize movddup shuffles.
-  if (V2IsUndef && Subtarget->hasSSE2() &&
-      VT.getSizeInBits() == 128 &&
-      X86::isMOVDDUPMask(PermMask.getNode()))
-    return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3());
-
-  if (isSplatMask(PermMask.getNode())) {
-    if (isMMX || NumElems < 4) return Op;
-    // Promote it to a v4{if}32 splat.
-    return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
+  if (V2IsUndef && Subtarget->hasSSE2() && VT.getSizeInBits() == 128 &&
+      X86::isMOVDDUPMask(SVOp))
+    return CanonicalizeMovddup(SVOp, DAG, Subtarget->hasSSE3());
+
+  // Promote splats to v4f32.
+  if (SVOp->isSplat()) {
+    if (isMMX || NumElems < 4) 
+      return Op;
+    return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
   }
 
   // If the shuffle can be profitably rewritten as a narrower shuffle, then
   // do it!
   if (VT == MVT::v8i16 || VT == MVT::v16i8) {
-    SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG,
-                                            *this, dl);
+    SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
     if (NewOp.getNode())
       return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
                          LowerVECTOR_SHUFFLE(NewOp, DAG));
@@ -4258,32 +4000,29 @@
     // FIXME: Figure out a cleaner way to do this.
     // Try to make use of movq to zero out the top part.
     if (ISD::isBuildVectorAllZeros(V2.getNode())) {
-      SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
-                                                 DAG, *this, dl);
+      SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
       if (NewOp.getNode()) {
-        SDValue NewV1 = NewOp.getOperand(0);
-        SDValue NewV2 = NewOp.getOperand(1);
-        SDValue NewMask = NewOp.getOperand(2);
-        if (isCommutedMOVL(NewMask.getNode(), true, false)) {
-          NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
-          return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget,
-                              dl);
-        }
+        if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
+          return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
+                              DAG, Subtarget, dl);
       }
     } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
-      SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
-                                                DAG, *this, dl);
-      if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
+      SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
+      if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
         return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
-                             DAG, Subtarget, dl);
+                            DAG, Subtarget, dl);
     }
   }
-
+  
+  if (X86::isPSHUFDMask(SVOp))
+    return Op;
+  
   // Check if this can be converted into a logical shift.
   bool isLeft = false;
   unsigned ShAmt = 0;
   SDValue ShVal;
-  bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
+  bool isShift = getSubtarget()->hasSSE2() &&
+  isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
   if (isShift && ShVal.hasOneUse()) {
     // If the shifted value has multiple uses, it may be cheaper to use
     // v_set0 + movlhps or movhlps, etc.
@@ -4291,8 +4030,8 @@
     ShAmt *= EVT.getSizeInBits();
     return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
   }
-
-  if (X86::isMOVLMask(PermMask.getNode())) {
+  
+  if (X86::isMOVLMask(SVOp)) {
     if (V1IsUndef)
       return V2;
     if (ISD::isBuildVectorAllZeros(V1.getNode()))
@@ -4300,17 +4039,18 @@
     if (!isMMX)
       return Op;
   }
-
-  if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
-                 X86::isMOVSLDUPMask(PermMask.getNode()) ||
-                 X86::isMOVHLPSMask(PermMask.getNode()) ||
-                 X86::isMOVHPMask(PermMask.getNode()) ||
-                 X86::isMOVLPMask(PermMask.getNode())))
+  
+  // FIXME: fold these into legal mask.
+  if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
+                 X86::isMOVSLDUPMask(SVOp) ||
+                 X86::isMOVHLPSMask(SVOp) ||
+                 X86::isMOVHPMask(SVOp) ||
+                 X86::isMOVLPMask(SVOp)))
     return Op;
 
-  if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
-      ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
-    return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
+  if (ShouldXformToMOVHLPS(SVOp) ||
+      ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
+    return CommuteVectorShuffle(SVOp, DAG);
 
   if (isShift) {
     // No better options. Use a vshl / vsrl.
@@ -4318,7 +4058,7 @@
     ShAmt *= EVT.getSizeInBits();
     return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
   }
-
+  
   bool Commuted = false;
   // FIXME: This should also accept a bitcast of a splat?  Be careful, not
   // 1,1,1,1 -> v8i16 though.
@@ -4327,115 +4067,86 @@
 
   // Canonicalize the splat or undef, if present, to be on the RHS.
   if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
-    Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
+    Op = CommuteVectorShuffle(SVOp, DAG);
+    SVOp = cast<ShuffleVectorSDNode>(Op);
+    V1 = SVOp->getOperand(0);
+    V2 = SVOp->getOperand(1);
     std::swap(V1IsSplat, V2IsSplat);
     std::swap(V1IsUndef, V2IsUndef);
     Commuted = true;
   }
 
-  // FIXME: Figure out a cleaner way to do this.
-  if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
-    if (V2IsUndef) return V1;
-    Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
-    if (V2IsSplat) {
-      // V2 is a splat, so the mask may be malformed. That is, it may point
-      // to any V2 element. The instruction selectior won't like this. Get
-      // a corrected mask and commute to form a proper MOVS{S|D}.
-      SDValue NewMask = getMOVLMask(NumElems, DAG, dl);
-      if (NewMask.getNode() != PermMask.getNode())
-        Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
-    }
-    return Op;
+  if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
+    // Shuffling low element of v1 into undef, just return v1.
+    if (V2IsUndef) 
+      return V1;
+    // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
+    // the instruction selector will not match, so get a canonical MOVL with
+    // swapped operands to undo the commute.
+    return getMOVL(DAG, dl, VT, V2, V1);
   }
 
-  if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
-      X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
-      X86::isUNPCKLMask(PermMask.getNode()) ||
-      X86::isUNPCKHMask(PermMask.getNode()))
+  if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
+      X86::isUNPCKH_v_undef_Mask(SVOp) ||
+      X86::isUNPCKLMask(SVOp) ||
+      X86::isUNPCKHMask(SVOp))
     return Op;
 
   if (V2IsSplat) {
     // Normalize mask so all entries that point to V2 points to its first
     // element then try to match unpck{h|l} again. If match, return a
     // new vector_shuffle with the corrected mask.
-    SDValue NewMask = NormalizeMask(PermMask, DAG);
-    if (NewMask.getNode() != PermMask.getNode()) {
-      if (X86::isUNPCKLMask(NewMask.getNode(), true)) {
-        SDValue NewMask = getUnpacklMask(NumElems, DAG, dl);
-        return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
-      } else if (X86::isUNPCKHMask(NewMask.getNode(), true)) {
-        SDValue NewMask = getUnpackhMask(NumElems, DAG, dl);
-        return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
+    SDValue NewMask = NormalizeMask(SVOp, DAG);
+    ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
+    if (NSVOp != SVOp) {
+      if (X86::isUNPCKLMask(NSVOp, true)) {
+        return NewMask;
+      } else if (X86::isUNPCKHMask(NSVOp, true)) {
+        return NewMask;
       }
     }
   }
 
-  // Normalize the node to match x86 shuffle ops if needed
-  if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
-      Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
-
   if (Commuted) {
     // Commute is back and try unpck* again.
-    Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
-    if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
-        X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
-        X86::isUNPCKLMask(PermMask.getNode()) ||
-        X86::isUNPCKHMask(PermMask.getNode()))
-      return Op;
+    // FIXME: this seems wrong.
+    SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
+    ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
+    if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
+        X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
+        X86::isUNPCKLMask(NewSVOp) ||
+        X86::isUNPCKHMask(NewSVOp))
+      return NewOp;
   }
 
   // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
-  // Try PSHUF* first, then SHUFP*.
-  // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
-  // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
-  if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
-    if (V2.getOpcode() != ISD::UNDEF)
-      return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1,
-                         DAG.getUNDEF(VT), PermMask);
-    return Op;
-  }
-
-  if (!isMMX) {
-    if (Subtarget->hasSSE2() &&
-        (X86::isPSHUFDMask(PermMask.getNode()) ||
-         X86::isPSHUFHWMask(PermMask.getNode()) ||
-         X86::isPSHUFLWMask(PermMask.getNode()))) {
-      MVT RVT = VT;
-      if (VT == MVT::v4f32) {
-        RVT = MVT::v4i32;
-        Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT,
-                         DAG.getNode(ISD::BIT_CONVERT, dl, RVT, V1),
-                         DAG.getUNDEF(RVT), PermMask);
-      } else if (V2.getOpcode() != ISD::UNDEF)
-        Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT, V1,
-                         DAG.getUNDEF(RVT), PermMask);
-      if (RVT != VT)
-        Op = DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op);
-      return Op;
-    }
 
-    // Binary or unary shufps.
-    if (X86::isSHUFPMask(PermMask.getNode()) ||
-        (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
-      return Op;
-  }
+  // Normalize the node to match x86 shuffle ops if needed
+  if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
+    return CommuteVectorShuffle(SVOp, DAG);
 
+  // Check for legal shuffle and return?
+  SmallVector<int, 16> PermMask;
+  SVOp->getMask(PermMask);
+  if (isShuffleMaskLegal(PermMask, VT))
+    return Op;
+  
   // Handle v8i16 specifically since SSE can do byte extraction and insertion.
   if (VT == MVT::v8i16) {
-    SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this, dl);
+    SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
     if (NewOp.getNode())
       return NewOp;
   }
 
   if (VT == MVT::v16i8) {
-    SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(V1, V2, PermMask, DAG, *this, dl);
+    SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
     if (NewOp.getNode())
       return NewOp;
   }
   
   // Handle all 4 wide cases with a number of shuffles except for MMX.
   if (NumElems == 4 && !isMMX)
-    return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG, dl);
+    return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
 
   return SDValue();
 }
@@ -4529,22 +4240,12 @@
     unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
     if (Idx == 0)
       return Op;
+    
     // SHUFPS the element to the lowest double word, then movss.
-    MVT MaskVT = MVT::getIntVectorWithNumElements(4);
-    SmallVector<SDValue, 8> IdxVec;
-    IdxVec.
-      push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
-    IdxVec.
-      push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
-    IdxVec.
-      push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
-    IdxVec.
-      push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
-    SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                 &IdxVec[0], IdxVec.size());
-    SDValue Vec = Op.getOperand(0);
-    Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
-                      Vec, DAG.getUNDEF(Vec.getValueType()), Mask);
+    int Mask[4] = { Idx, -1, -1, -1 };
+    MVT VVT = Op.getOperand(0).getValueType();
+    SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 
+                                       DAG.getUNDEF(VVT), Mask);
     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
                        DAG.getIntPtrConstant(0));
   } else if (VT.getSizeInBits() == 64) {
@@ -4558,17 +4259,10 @@
     // UNPCKHPD the element to the lowest double word, then movsd.
     // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
     // to a f64mem, the whole operation is folded into a single MOVHPDmr.
-    MVT MaskVT = MVT::getIntVectorWithNumElements(2);
-    SmallVector<SDValue, 8> IdxVec;
-    IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
-    IdxVec.
-      push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
-    SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
-                                 &IdxVec[0], IdxVec.size());
-    SDValue Vec = Op.getOperand(0);
-    Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
-                      Vec, DAG.getUNDEF(Vec.getValueType()),
-                      Mask);
+    int Mask[2] = { 1, -1 };
+    MVT VVT = Op.getOperand(0).getValueType();
+    SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 
+                                       DAG.getUNDEF(VVT), Mask);
     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
                        DAG.getIntPtrConstant(0));
   }
@@ -5049,19 +4743,6 @@
   Constant *C1 = ConstantVector::get(CV1);
   SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
 
-  SmallVector<SDValue, 4> MaskVec;
-  MaskVec.push_back(DAG.getConstant(0, MVT::i32));
-  MaskVec.push_back(DAG.getConstant(4, MVT::i32));
-  MaskVec.push_back(DAG.getConstant(1, MVT::i32));
-  MaskVec.push_back(DAG.getConstant(5, MVT::i32));
-  SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
-                                   &MaskVec[0], MaskVec.size());
-  SmallVector<SDValue, 4> MaskVec2;
-  MaskVec2.push_back(DAG.getConstant(1, MVT::i32));
-  MaskVec2.push_back(DAG.getConstant(0, MVT::i32));
-  SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32,
-                                 &MaskVec2[0], MaskVec2.size());
-
   SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
                             DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
                                         Op.getOperand(0),
@@ -5070,13 +4751,11 @@
                             DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
                                         Op.getOperand(0),
                                         DAG.getIntPtrConstant(0)));
-  SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32,
-                                XR1, XR2, UnpcklMask);
+  SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
   SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
                               PseudoSourceValue::getConstantPool(), 0,
                               false, 16);
-  SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32,
-                               Unpck1, CLod0, UnpcklMask);
+  SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
   SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
   SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
                               PseudoSourceValue::getConstantPool(), 0,
@@ -5084,8 +4763,9 @@
   SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
 
   // Add the halves; easiest way is to swap them into another reg first.
-  SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2f64,
-                             Sub, Sub, ShufMask);
+  int ShufMask[2] = { 1, -1 };
+  SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
+                                      DAG.getUNDEF(MVT::v2f64), ShufMask);
   SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
                      DAG.getIntPtrConstant(0));
@@ -7237,34 +6917,37 @@
 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
 /// are assumed to be legal.
 bool
-X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
+X86TargetLowering::isShuffleMaskLegal(SmallVectorImpl<int> &M, MVT VT) const {
   // Only do shuffles on 128-bit vector types for now.
-  // FIXME: pshufb, blends
-  if (VT.getSizeInBits() == 64) return false;
-  return (Mask.getNode()->getNumOperands() <= 4 ||
-          isIdentityMask(Mask.getNode()) ||
-          isIdentityMask(Mask.getNode(), true) ||
-          isSplatMask(Mask.getNode())  ||
-          X86::isPSHUFHWMask(Mask.getNode()) ||
-          X86::isPSHUFLWMask(Mask.getNode()) ||
-          X86::isUNPCKLMask(Mask.getNode()) ||
-          X86::isUNPCKHMask(Mask.getNode()) ||
-          X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
-          X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
+  if (VT.getSizeInBits() == 64)
+    return false;
+
+  // FIXME: pshufb, blends, palignr, shifts.
+  return (VT.getVectorNumElements() == 2 ||
+          ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
+          isMOVLMask(M, VT) ||
+          isSHUFPMask(M, VT) ||
+          isPSHUFDMask(M, VT) ||
+          isPSHUFHWMask(M, VT) ||
+          isPSHUFLWMask(M, VT) ||
+          isUNPCKLMask(M, VT) ||
+          isUNPCKHMask(M, VT) ||
+          isUNPCKL_v_undef_Mask(M, VT) ||
+          isUNPCKH_v_undef_Mask(M, VT));
 }
 
 bool
-X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
-                                          MVT EVT, SelectionDAG &DAG) const {
-  unsigned NumElts = BVOps.size();
-  // Only do shuffles on 128-bit vector types for now.
-  if (EVT.getSizeInBits() * NumElts == 64) return false;
-  if (NumElts == 2) return true;
-  if (NumElts == 4) {
-    return (isMOVLMask(&BVOps[0], 4)  ||
-            isCommutedMOVL(&BVOps[0], 4, true) ||
-            isSHUFPMask(&BVOps[0], 4) ||
-            isCommutedSHUFP(&BVOps[0], 4));
+X86TargetLowering::isVectorClearMaskLegal(SmallVectorImpl<int> &Mask,
+                                          MVT VT) const {
+  unsigned NumElts = VT.getVectorNumElements();
+  // FIXME: This collection of masks seems suspect.
+  if (NumElts == 2)
+    return true;
+  if (NumElts == 4 && VT.getSizeInBits() == 128) {
+    return (isMOVLMask(Mask, VT)  ||
+            isCommutedMOVLMask(Mask, VT, true) ||
+            isSHUFPMask(Mask, VT) ||
+            isCommutedSHUFPMask(Mask, VT));
   }
   return false;
 }
@@ -7999,15 +7682,13 @@
   return false;
 }
 
-static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
-                                     unsigned NumElems, MVT EVT,
-                                     SDNode *&Base,
+static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
+                                     MVT EVT, SDNode *&Base,
                                      SelectionDAG &DAG, MachineFrameInfo *MFI,
                                      const TargetLowering &TLI) {
   Base = NULL;
   for (unsigned i = 0; i < NumElems; ++i) {
-    SDValue Idx = PermMask.getOperand(i);
-    if (Idx.getOpcode() == ISD::UNDEF) {
+    if (N->getMaskElt(i) < 0) {
       if (!Base)
         return false;
       continue;
@@ -8040,12 +7721,12 @@
 /// shuffle to be an appropriate build vector so it can take advantage of
 // performBuildVectorCombine.
 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
-                                       const TargetLowering &TLI) {
+                                     const TargetLowering &TLI) {
   DebugLoc dl = N->getDebugLoc();
   MVT VT = N->getValueType(0);
   MVT EVT = VT.getVectorElementType();
-  SDValue PermMask = N->getOperand(2);
-  unsigned NumElems = PermMask.getNumOperands();
+  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
+  unsigned NumElems = VT.getVectorNumElements();
 
   // For x86-32 machines, if we see an insert and then a shuffle in a v2i64
   // where the upper half is 0, it is advantageous to rewrite it as a build
@@ -8054,15 +7735,16 @@
     SDValue In[2];
     In[0] = N->getOperand(0);
     In[1] = N->getOperand(1);
-    unsigned Idx0 =cast<ConstantSDNode>(PermMask.getOperand(0))->getZExtValue();
-    unsigned Idx1 =cast<ConstantSDNode>(PermMask.getOperand(1))->getZExtValue();
-    if (In[0].getValueType().getVectorNumElements() == NumElems &&
+    int Idx0 = SVN->getMaskElt(0);
+    int Idx1 = SVN->getMaskElt(1);
+    // FIXME: can we take advantage of undef index?
+    if (Idx0 >= 0 && Idx1 >= 0 &&
         In[Idx0/2].getOpcode() == ISD::INSERT_VECTOR_ELT &&
         In[Idx1/2].getOpcode() == ISD::BUILD_VECTOR) {
       ConstantSDNode* InsertVecIdx =
                              dyn_cast<ConstantSDNode>(In[Idx0/2].getOperand(2));
       if (InsertVecIdx &&
-          InsertVecIdx->getZExtValue() == (Idx0 % 2) &&
+          InsertVecIdx->getZExtValue() == (unsigned)(Idx0 % 2) &&
           isZeroNode(In[Idx1/2].getOperand(Idx1 % 2))) {
         return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
                            In[Idx0/2].getOperand(1),
@@ -8074,8 +7756,7 @@
   // Try to combine a vector_shuffle into a 128-bit load.
   MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
   SDNode *Base = NULL;
-  if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
-                                DAG, MFI, TLI))
+  if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, Base, DAG, MFI, TLI))
     return SDValue();
 
   LoadSDNode *LD = cast<LoadSDNode>(Base);
@@ -8520,9 +8201,9 @@
       }
     }
   } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
-             isSplatMask(ShAmtOp.getOperand(2).getNode())) {
-      BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
-                              DAG.getIntPtrConstant(0));
+             cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
+    BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
+                            DAG.getIntPtrConstant(0));
   } else
     return SDValue();
 

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Apr 27 13:41:29 2009
@@ -230,7 +230,8 @@
 
       // VSHL, VSRL - Vector logical left / right shift.
       VSHL, VSRL,
-      
+
+      // CMPPD, CMPPS - Vector double/float comparison.
       // CMPPD, CMPPS - Vector double/float comparison.
       CMPPD, CMPPS,
       
@@ -251,80 +252,72 @@
   namespace X86 {
     /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
     /// specifies a shuffle of elements that is suitable for input to PSHUFD.
-    bool isPSHUFDMask(SDNode *N);
+    bool isPSHUFDMask(ShuffleVectorSDNode *N);
 
     /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
     /// specifies a shuffle of elements that is suitable for input to PSHUFD.
-    bool isPSHUFHWMask(SDNode *N);
+    bool isPSHUFHWMask(ShuffleVectorSDNode *N);
 
     /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
     /// specifies a shuffle of elements that is suitable for input to PSHUFD.
-    bool isPSHUFLWMask(SDNode *N);
+    bool isPSHUFLWMask(ShuffleVectorSDNode *N);
 
     /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
     /// specifies a shuffle of elements that is suitable for input to SHUFP*.
-    bool isSHUFPMask(SDNode *N);
+    bool isSHUFPMask(ShuffleVectorSDNode *N);
 
     /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
     /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
-    bool isMOVHLPSMask(SDNode *N);
+    bool isMOVHLPSMask(ShuffleVectorSDNode *N);
 
     /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
     /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
     /// <2, 3, 2, 3>
-    bool isMOVHLPS_v_undef_Mask(SDNode *N);
+    bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
 
     /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
-    /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
-    bool isMOVLPMask(SDNode *N);
+    /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
+    bool isMOVLPMask(ShuffleVectorSDNode *N);
 
     /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
-    /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
+    /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
     /// as well as MOVLHPS.
-    bool isMOVHPMask(SDNode *N);
+    bool isMOVHPMask(ShuffleVectorSDNode *N);
 
     /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
     /// specifies a shuffle of elements that is suitable for input to UNPCKL.
-    bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
+    bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
 
     /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
     /// specifies a shuffle of elements that is suitable for input to UNPCKH.
-    bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
+    bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
 
     /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
     /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
     /// <0, 0, 1, 1>
-    bool isUNPCKL_v_undef_Mask(SDNode *N);
+    bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
 
     /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
     /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
     /// <2, 2, 3, 3>
-    bool isUNPCKH_v_undef_Mask(SDNode *N);
+    bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
 
     /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
     /// specifies a shuffle of elements that is suitable for input to MOVSS,
     /// MOVSD, and MOVD, i.e. setting the lowest element.
-    bool isMOVLMask(SDNode *N);
+    bool isMOVLMask(ShuffleVectorSDNode *N);
 
     /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
     /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
-    bool isMOVSHDUPMask(SDNode *N);
+    bool isMOVSHDUPMask(ShuffleVectorSDNode *N);
 
     /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
     /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
-    bool isMOVSLDUPMask(SDNode *N);
-
-    /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
-    /// specifies a splat of a single element.
-    bool isSplatMask(SDNode *N);
-
-    /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
-    /// specifies a splat of zero element.
-    bool isSplatLoMask(SDNode *N);
+    bool isMOVSLDUPMask(ShuffleVectorSDNode *N);
 
     /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
     /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
-    bool isMOVDDUPMask(SDNode *N);
+    bool isMOVDDUPMask(ShuffleVectorSDNode *N);
 
     /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
     /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
@@ -477,14 +470,13 @@
     /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
     /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
     /// values are assumed to be legal.
-    virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const;
+    virtual bool isShuffleMaskLegal(SmallVectorImpl<int> &Mask, MVT VT) const;
 
     /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
     /// used by Targets can use this to indicate if there is a suitable
     /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
     /// pool entry.
-    virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
-                                        MVT EVT, SelectionDAG &DAG) const;
+    virtual bool isVectorClearMaskLegal(SmallVectorImpl<int> &M, MVT VT) const;
 
     /// ShouldShrinkFPConstant - If true, then instruction selection should
     /// seek to shrink the FP constant of the specified type to a smaller type

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Apr 27 13:41:29 2009
@@ -3821,6 +3821,7 @@
                     (implicit EFLAGS)),
           (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
 
+
 //===----------------------------------------------------------------------===//
 // Floating Point Stack Support
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Mon Apr 27 13:41:29 2009
@@ -30,33 +30,37 @@
 
 // MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
 // PSHUFW imm.
-def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
+def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
   return getI8Imm(X86::getShuffleSHUFImmediate(N));
 }]>;
 
 // Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
-def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isUNPCKHMask(N);
+def mmx_unpckh : PatFrag<(ops node:$lhs, node:$rhs),
+                         (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
 // Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
-def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isUNPCKLMask(N);
+def mmx_unpckl : PatFrag<(ops node:$lhs, node:$rhs),
+                         (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
 // Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
-def MMX_UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isUNPCKH_v_undef_Mask(N);
+def mmx_unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
+                               (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
 // Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
-def MMX_UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isUNPCKL_v_undef_Mask(N);
+def mmx_unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
+                               (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
-// Patterns for shuffling.
-def MMX_PSHUFW_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isPSHUFDMask(N);
+def mmx_pshufw : PatFrag<(ops node:$lhs, node:$rhs),
+                         (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
 }], MMX_SHUFFLE_get_shuf_imm>;
 
 //===----------------------------------------------------------------------===//
@@ -185,9 +189,8 @@
 def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
                            "movq2dq\t{$src, $dst|$dst, $src}",
           [(set VR128:$dst,
-                (v2i64 (vector_shuffle immAllZerosV,
-                        (v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src)))),
-                        MOVL_shuffle_mask)))]>;
+            (movl immAllZerosV,
+                  (v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src))))))]>;
 
 let neverHasSideEffects = 1 in
 def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMDestMem, (outs FR64:$dst), (ins VR64:$src),
@@ -319,86 +322,74 @@
                              (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
                              "punpckhbw\t{$src2, $dst|$dst, $src2}",
                              [(set VR64:$dst,
-                               (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
-                                      MMX_UNPCKH_shuffle_mask)))]>;
+                               (v8i8 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
   def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem, 
                              (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
                              "punpckhbw\t{$src2, $dst|$dst, $src2}",
                              [(set VR64:$dst,
-                               (v8i8 (vector_shuffle VR64:$src1,
-                                      (bc_v8i8 (load_mmx addr:$src2)),
-                                      MMX_UNPCKH_shuffle_mask)))]>;
+                               (v8i8 (mmx_unpckh VR64:$src1,
+                                      (bc_v8i8 (load_mmx addr:$src2)))))]>;
 
   def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg, 
                              (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
                              "punpckhwd\t{$src2, $dst|$dst, $src2}",
                              [(set VR64:$dst,
-                               (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
-                                       MMX_UNPCKH_shuffle_mask)))]>;
+                               (v4i16 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
   def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem, 
                              (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
                              "punpckhwd\t{$src2, $dst|$dst, $src2}",
                              [(set VR64:$dst,
-                               (v4i16 (vector_shuffle VR64:$src1,
-                                       (bc_v4i16 (load_mmx addr:$src2)),
-                                       MMX_UNPCKH_shuffle_mask)))]>;
+                               (v4i16 (mmx_unpckh VR64:$src1,
+                                       (bc_v4i16 (load_mmx addr:$src2)))))]>;
 
   def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg, 
                              (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
                              "punpckhdq\t{$src2, $dst|$dst, $src2}",
                              [(set VR64:$dst,
-                               (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
-                                       MMX_UNPCKH_shuffle_mask)))]>;
+                               (v2i32 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
   def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
                              (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
                              "punpckhdq\t{$src2, $dst|$dst, $src2}",
                              [(set VR64:$dst,
-                               (v2i32 (vector_shuffle VR64:$src1,
-                                       (bc_v2i32 (load_mmx addr:$src2)),
-                                       MMX_UNPCKH_shuffle_mask)))]>;
+                               (v2i32 (mmx_unpckh VR64:$src1,
+                                       (bc_v2i32 (load_mmx addr:$src2)))))]>;
 
   // Unpack Low Packed Data Instructions
   def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
                              (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
                              "punpcklbw\t{$src2, $dst|$dst, $src2}",
                              [(set VR64:$dst,
-                               (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
-                                      MMX_UNPCKL_shuffle_mask)))]>;
+                               (v8i8 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
   def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
                              (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
                              "punpcklbw\t{$src2, $dst|$dst, $src2}",
                              [(set VR64:$dst,
-                               (v8i8 (vector_shuffle VR64:$src1,
-                                      (bc_v8i8 (load_mmx addr:$src2)),
-                                      MMX_UNPCKL_shuffle_mask)))]>;
+                               (v8i8 (mmx_unpckl VR64:$src1,
+                                      (bc_v8i8 (load_mmx addr:$src2)))))]>;
 
   def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
                              (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
                              "punpcklwd\t{$src2, $dst|$dst, $src2}",
                              [(set VR64:$dst,
-                               (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
-                                       MMX_UNPCKL_shuffle_mask)))]>;
+                               (v4i16 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
   def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
                              (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
                              "punpcklwd\t{$src2, $dst|$dst, $src2}",
                              [(set VR64:$dst,
-                               (v4i16 (vector_shuffle VR64:$src1,
-                                       (bc_v4i16 (load_mmx addr:$src2)),
-                                       MMX_UNPCKL_shuffle_mask)))]>;
+                               (v4i16 (mmx_unpckl VR64:$src1,
+                                       (bc_v4i16 (load_mmx addr:$src2)))))]>;
 
   def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg, 
                              (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
                              "punpckldq\t{$src2, $dst|$dst, $src2}",
                              [(set VR64:$dst,
-                               (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
-                                       MMX_UNPCKL_shuffle_mask)))]>;
+                               (v2i32 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
   def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem, 
                              (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
                              "punpckldq\t{$src2, $dst|$dst, $src2}",
                              [(set VR64:$dst,
-                               (v2i32 (vector_shuffle VR64:$src1,
-                                       (bc_v2i32 (load_mmx addr:$src2)),
-                                       MMX_UNPCKL_shuffle_mask)))]>;
+                               (v2i32 (mmx_unpckl VR64:$src1,
+                                       (bc_v2i32 (load_mmx addr:$src2)))))]>;
 }
 
 // -- Pack Instructions
@@ -411,17 +402,13 @@
                           (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
                           "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
                           [(set VR64:$dst,
-                            (v4i16 (vector_shuffle
-                                    VR64:$src1, (undef),
-                                    MMX_PSHUFW_shuffle_mask:$src2)))]>;
+                            (v4i16 (mmx_pshufw:$src2 VR64:$src1, (undef))))]>;
 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
                           (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
                           "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
                           [(set VR64:$dst,
-                            (v4i16 (vector_shuffle
-                                    (bc_v4i16 (load_mmx addr:$src1)),
-                                    (undef),
-                                    MMX_PSHUFW_shuffle_mask:$src2)))]>;
+                            (mmx_pshufw:$src2 (bc_v4i16 (load_mmx addr:$src1)),
+                                              (undef)))]>;
 
 // -- Conversion Instructions
 let neverHasSideEffects = 1 in {
@@ -627,34 +614,27 @@
 
 // Patterns to perform canonical versions of vector shuffling.
 let AddedComplexity = 10 in {
-  def : Pat<(v8i8  (vector_shuffle VR64:$src, (undef),
-                    MMX_UNPCKL_v_undef_shuffle_mask)),
+  def : Pat<(v8i8  (mmx_unpckl_undef VR64:$src, (undef))),
             (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
-  def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
-                    MMX_UNPCKL_v_undef_shuffle_mask)),
+  def : Pat<(v4i16 (mmx_unpckl_undef VR64:$src, (undef))),
             (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
-  def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
-                    MMX_UNPCKL_v_undef_shuffle_mask)),
+  def : Pat<(v2i32 (mmx_unpckl_undef VR64:$src, (undef))),
             (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
 }
 
 let AddedComplexity = 10 in {
-  def : Pat<(v8i8  (vector_shuffle VR64:$src, (undef),
-                    MMX_UNPCKH_v_undef_shuffle_mask)),
+  def : Pat<(v8i8  (mmx_unpckh_undef VR64:$src, (undef))),
             (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
-  def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
-                    MMX_UNPCKH_v_undef_shuffle_mask)),
+  def : Pat<(v4i16 (mmx_unpckh_undef VR64:$src, (undef))),
             (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
-  def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
-                    MMX_UNPCKH_v_undef_shuffle_mask)),
+  def : Pat<(v2i32 (mmx_unpckh_undef VR64:$src, (undef))),
             (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
 }
 
 // Patterns to perform vector shuffling with a zeroed out vector.
 let AddedComplexity = 20 in {
-  def : Pat<(bc_v2i32 (vector_shuffle immAllZerosV,
-                       (v2i32 (scalar_to_vector (load_mmx addr:$src))),
-                       MMX_UNPCKL_shuffle_mask)),
+  def : Pat<(bc_v2i32 (mmx_unpckl immAllZerosV,
+                       (v2i32 (scalar_to_vector (load_mmx addr:$src))))),
             (MMX_PUNPCKLDQrm VR64:$src, VR64:$src)>;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Apr 27 13:41:29 2009
@@ -175,102 +175,107 @@
 
 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
 // SHUFP* etc. imm.
-def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
+def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
   return getI8Imm(X86::getShuffleSHUFImmediate(N));
 }]>;
 
 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to 
 // PSHUFHW imm.
-def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
+def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
   return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
 }]>;
 
 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to 
 // PSHUFLW imm.
-def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
+def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
   return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
 }]>;
 
-def SSE_splat_mask : PatLeaf<(build_vector), [{
-  return X86::isSplatMask(N);
-}], SHUFFLE_get_shuf_imm>;
-
-def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
-  return X86::isSplatLoMask(N);
+def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
+                       (vector_shuffle node:$lhs, node:$rhs), [{
+  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
+  return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
 }]>;
 
-def MOVDDUP_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isMOVDDUPMask(N);
+def movddup : PatFrag<(ops node:$lhs, node:$rhs),
+                      (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
-def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isMOVHLPSMask(N);
+def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
+                      (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
-def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isMOVHLPS_v_undef_Mask(N);
+def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
+                            (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
-def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isMOVHPMask(N);
+def movhp : PatFrag<(ops node:$lhs, node:$rhs),
+                    (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isMOVHPMask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
-def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isMOVLPMask(N);
+def movlp : PatFrag<(ops node:$lhs, node:$rhs),
+                    (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
-def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isMOVLMask(N);
+def movl : PatFrag<(ops node:$lhs, node:$rhs),
+                   (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
-def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isMOVSHDUPMask(N);
+def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
+                       (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
-def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isMOVSLDUPMask(N);
+def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
+                       (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
-def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isUNPCKLMask(N);
+def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
+                     (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
-def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isUNPCKHMask(N);
+def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
+                     (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
-def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isUNPCKL_v_undef_Mask(N);
+def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
+                           (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
-def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isUNPCKH_v_undef_Mask(N);
+def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
+                           (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
 }]>;
 
-def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isPSHUFDMask(N);
-}], SHUFFLE_get_shuf_imm>;
-
-def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isPSHUFHWMask(N);
-}], SHUFFLE_get_pshufhw_imm>;
-
-def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isPSHUFLWMask(N);
-}], SHUFFLE_get_pshuflw_imm>;
-
-def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isPSHUFDMask(N);
+def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
+                     (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
 }], SHUFFLE_get_shuf_imm>;
 
-def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isSHUFPMask(N);
+def shufp : PatFrag<(ops node:$lhs, node:$rhs),
+                    (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
 }], SHUFFLE_get_shuf_imm>;
 
-def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isSHUFPMask(N);
-}], SHUFFLE_get_shuf_imm>;
+def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
+                      (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
+}], SHUFFLE_get_pshufhw_imm>;
 
+def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
+                      (vector_shuffle node:$lhs, node:$rhs), [{
+  return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
+}], SHUFFLE_get_pshuflw_imm>;
 
 //===----------------------------------------------------------------------===//
 // SSE scalar FP Instructions
@@ -704,16 +709,14 @@
                        (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
                        "movlps\t{$src2, $dst|$dst, $src2}",
        [(set VR128:$dst, 
-             (v4f32 (vector_shuffle VR128:$src1,
-                     (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
-                     MOVLP_shuffle_mask)))]>;
+         (movlp VR128:$src1,
+                (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
     def MOVHPSrm : PSI<0x16, MRMSrcMem,
                        (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
                        "movhps\t{$src2, $dst|$dst, $src2}",
        [(set VR128:$dst, 
-             (v4f32 (vector_shuffle VR128:$src1,
-                     (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
-                     MOVHP_shuffle_mask)))]>;
+         (movhp VR128:$src1,
+                (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
   } // AddedComplexity
 } // Constraints = "$src1 = $dst"
 
@@ -728,29 +731,25 @@
 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
                    "movhps\t{$src, $dst|$dst, $src}",
                    [(store (f64 (vector_extract
-                                 (v2f64 (vector_shuffle
-                                         (bc_v2f64 (v4f32 VR128:$src)), (undef),
-                                         UNPCKH_shuffle_mask)), (iPTR 0))),
-                     addr:$dst)]>;
+                                 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
+                                         (undef)), (iPTR 0))), addr:$dst)]>;
 
 let Constraints = "$src1 = $dst" in {
 let AddedComplexity = 20 in {
 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                     "movlhps\t{$src2, $dst|$dst, $src2}",
                     [(set VR128:$dst,
-                      (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
-                              MOVHP_shuffle_mask)))]>;
+                      (v4f32 (movhp VR128:$src1, VR128:$src2)))]>;
 
 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                     "movhlps\t{$src2, $dst|$dst, $src2}",
                     [(set VR128:$dst,
-                      (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
-                              MOVHLPS_shuffle_mask)))]>;
+                      (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
 } // AddedComplexity
 } // Constraints = "$src1 = $dst"
 
 let AddedComplexity = 20 in
-def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), MOVDDUP_shuffle_mask)),
+def : Pat<(v4f32 (movddup VR128:$src, (undef))),
           (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
 
 
@@ -908,51 +907,41 @@
   let isConvertibleToThreeAddress = 1 in // Convert to pshufd
     def SHUFPSrri : PSIi8<0xC6, MRMSrcReg, 
                           (outs VR128:$dst), (ins VR128:$src1,
-                           VR128:$src2, i32i8imm:$src3),
+                           VR128:$src2, i8imm:$src3),
                           "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                           [(set VR128:$dst,
-                            (v4f32 (vector_shuffle
-                                    VR128:$src1, VR128:$src2,
-                                    SHUFP_shuffle_mask:$src3)))]>;
+                            (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
   def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem, 
                         (outs VR128:$dst), (ins VR128:$src1,
-                         f128mem:$src2, i32i8imm:$src3),
+                         f128mem:$src2, i8imm:$src3),
                         "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                         [(set VR128:$dst,
-                          (v4f32 (vector_shuffle
-                                  VR128:$src1, (memopv4f32 addr:$src2),
-                                  SHUFP_shuffle_mask:$src3)))]>;
+                          (v4f32 (shufp:$src3
+                                  VR128:$src1, (memopv4f32 addr:$src2))))]>;
 
   let AddedComplexity = 10 in {
     def UNPCKHPSrr : PSI<0x15, MRMSrcReg, 
                          (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                          "unpckhps\t{$src2, $dst|$dst, $src2}",
                          [(set VR128:$dst,
-                           (v4f32 (vector_shuffle
-                                   VR128:$src1, VR128:$src2,
-                                   UNPCKH_shuffle_mask)))]>;
+                           (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
     def UNPCKHPSrm : PSI<0x15, MRMSrcMem, 
                          (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
                          "unpckhps\t{$src2, $dst|$dst, $src2}",
                          [(set VR128:$dst,
-                           (v4f32 (vector_shuffle
-                                   VR128:$src1, (memopv4f32 addr:$src2),
-                                   UNPCKH_shuffle_mask)))]>;
+                           (v4f32 (unpckh VR128:$src1,
+                                          (memopv4f32 addr:$src2))))]>;
 
     def UNPCKLPSrr : PSI<0x14, MRMSrcReg, 
                          (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                          "unpcklps\t{$src2, $dst|$dst, $src2}",
                          [(set VR128:$dst,
-                           (v4f32 (vector_shuffle
-                                   VR128:$src1, VR128:$src2,
-                                   UNPCKL_shuffle_mask)))]>;
+                           (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
     def UNPCKLPSrm : PSI<0x14, MRMSrcMem, 
                          (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
                          "unpcklps\t{$src2, $dst|$dst, $src2}",
                          [(set VR128:$dst,
-                           (v4f32 (vector_shuffle
-                                   VR128:$src1, (memopv4f32 addr:$src2),
-                                   UNPCKL_shuffle_mask)))]>;
+                           (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
   } // AddedComplexity
 } // Constraints = "$src1 = $dst"
 
@@ -1044,8 +1033,7 @@
                        (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                        "movss\t{$src2, $dst|$dst, $src2}",
                        [(set VR128:$dst,
-                         (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
-                                 MOVL_shuffle_mask)))]>;
+                         (v4f32 (movl VR128:$src1, VR128:$src2)))]>;
 }
 
 // Move to lower bits of a VR128 and zeroing upper bits.
@@ -1451,16 +1439,14 @@
                        (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
                        "movlpd\t{$src2, $dst|$dst, $src2}",
                        [(set VR128:$dst, 
-                         (v2f64 (vector_shuffle VR128:$src1,
-                                 (scalar_to_vector (loadf64 addr:$src2)),
-                                 MOVLP_shuffle_mask)))]>;
+                         (v2f64 (movlp VR128:$src1,
+                                 (scalar_to_vector (loadf64 addr:$src2)))))]>;
     def MOVHPDrm : PDI<0x16, MRMSrcMem,
                        (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
                        "movhpd\t{$src2, $dst|$dst, $src2}",
                        [(set VR128:$dst, 
-                         (v2f64 (vector_shuffle VR128:$src1,
-                                 (scalar_to_vector (loadf64 addr:$src2)),
-                                 MOVHP_shuffle_mask)))]>;
+                         (v2f64 (movhp VR128:$src1,
+                                 (scalar_to_vector (loadf64 addr:$src2)))))]>;
   } // AddedComplexity
 } // Constraints = "$src1 = $dst"
 
@@ -1474,9 +1460,8 @@
 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
                    "movhpd\t{$src, $dst|$dst, $src}",
                    [(store (f64 (vector_extract
-                                 (v2f64 (vector_shuffle VR128:$src, (undef),
-                                         UNPCKH_shuffle_mask)), (iPTR 0))),
-                     addr:$dst)]>;
+                                 (v2f64 (unpckh VR128:$src, (undef))),
+                                 (iPTR 0))), addr:$dst)]>;
 
 // SSE2 instructions without OpSize prefix
 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
@@ -1744,48 +1729,39 @@
   def SHUFPDrri : PDIi8<0xC6, MRMSrcReg, 
                  (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
                  "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
-                 [(set VR128:$dst, (v2f64 (vector_shuffle
-                                           VR128:$src1, VR128:$src2,
-                                           SHUFP_shuffle_mask:$src3)))]>;
+                 [(set VR128:$dst,
+                   (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
   def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem, 
                         (outs VR128:$dst), (ins VR128:$src1,
                          f128mem:$src2, i8imm:$src3),
                         "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                         [(set VR128:$dst,
-                          (v2f64 (vector_shuffle
-                                  VR128:$src1, (memopv2f64 addr:$src2),
-                                  SHUFP_shuffle_mask:$src3)))]>;
+                          (v2f64 (shufp:$src3
+                                  VR128:$src1, (memopv2f64 addr:$src2))))]>;
 
   let AddedComplexity = 10 in {
     def UNPCKHPDrr : PDI<0x15, MRMSrcReg, 
                          (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                          "unpckhpd\t{$src2, $dst|$dst, $src2}",
                          [(set VR128:$dst,
-                           (v2f64 (vector_shuffle
-                                   VR128:$src1, VR128:$src2,
-                                   UNPCKH_shuffle_mask)))]>;
+                           (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
     def UNPCKHPDrm : PDI<0x15, MRMSrcMem, 
                          (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
                          "unpckhpd\t{$src2, $dst|$dst, $src2}",
                          [(set VR128:$dst,
-                           (v2f64 (vector_shuffle
-                                   VR128:$src1, (memopv2f64 addr:$src2),
-                                   UNPCKH_shuffle_mask)))]>;
+                           (v2f64 (unpckh VR128:$src1,
+                                          (memopv2f64 addr:$src2))))]>;
 
     def UNPCKLPDrr : PDI<0x14, MRMSrcReg, 
                          (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                          "unpcklpd\t{$src2, $dst|$dst, $src2}",
                          [(set VR128:$dst,
-                           (v2f64 (vector_shuffle
-                                   VR128:$src1, VR128:$src2,
-                                   UNPCKL_shuffle_mask)))]>;
+                           (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
     def UNPCKLPDrm : PDI<0x14, MRMSrcMem, 
                          (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
                          "unpcklpd\t{$src2, $dst|$dst, $src2}",
                          [(set VR128:$dst,
-                           (v2f64 (vector_shuffle
-                                   VR128:$src1, (memopv2f64 addr:$src2),
-                                   UNPCKL_shuffle_mask)))]>;
+                           (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
   } // AddedComplexity
 } // Constraints = "$src1 = $dst"
 
@@ -2043,49 +2019,43 @@
 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
                      (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
                      "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                     [(set VR128:$dst, (v4i32 (vector_shuffle
-                                               VR128:$src1, (undef),
-                                               PSHUFD_shuffle_mask:$src2)))]>;
+                     [(set VR128:$dst, (v4i32 (pshufd:$src2
+                                               VR128:$src1, (undef))))]>;
 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
                      (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
                      "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                     [(set VR128:$dst, (v4i32 (vector_shuffle
+                     [(set VR128:$dst, (v4i32 (pshufd:$src2
                                                (bc_v4i32(memopv2i64 addr:$src1)),
-                                               (undef),
-                                               PSHUFD_shuffle_mask:$src2)))]>;
+                                               (undef))))]>;
 
 // SSE2 with ImmT == Imm8 and XS prefix.
 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
                     (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
                     "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                    [(set VR128:$dst, (v8i16 (vector_shuffle
-                                              VR128:$src1, (undef),
-                                              PSHUFHW_shuffle_mask:$src2)))]>,
+                    [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
+                                                            (undef))))]>,
                 XS, Requires<[HasSSE2]>;
 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
                     (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
                     "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                    [(set VR128:$dst, (v8i16 (vector_shuffle
-                                              (bc_v8i16 (memopv2i64 addr:$src1)),
-                                              (undef),
-                                              PSHUFHW_shuffle_mask:$src2)))]>,
+                    [(set VR128:$dst, (v8i16 (pshufhw:$src2
+                                             (bc_v8i16 (memopv2i64 addr:$src1)),
+                                             (undef))))]>,
                 XS, Requires<[HasSSE2]>;
 
 // SSE2 with ImmT == Imm8 and XD prefix.
 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
-                    (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
+                    (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
                     "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                    [(set VR128:$dst, (v8i16 (vector_shuffle
-                                              VR128:$src1, (undef),
-                                              PSHUFLW_shuffle_mask:$src2)))]>,
+                    [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
+                                                            (undef))))]>,
                 XD, Requires<[HasSSE2]>;
 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
-                    (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
+                    (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
                     "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                    [(set VR128:$dst, (v8i16 (vector_shuffle
-                                              (bc_v8i16 (memopv2i64 addr:$src1)),
-                                              (undef),
-                                              PSHUFLW_shuffle_mask:$src2)))]>,
+                    [(set VR128:$dst, (v8i16 (pshuflw:$src2
+                                             (bc_v8i16 (memopv2i64 addr:$src1)),
+                                             (undef))))]>,
                 XD, Requires<[HasSSE2]>;
 
 
@@ -2094,107 +2064,91 @@
                         (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                         "punpcklbw\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
-                                  UNPCKL_shuffle_mask)))]>;
+                          (v16i8 (unpckl VR128:$src1, VR128:$src2)))]>;
   def PUNPCKLBWrm : PDI<0x60, MRMSrcMem, 
                         (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
                         "punpcklbw\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v16i8 (vector_shuffle VR128:$src1,
-                                  (bc_v16i8 (memopv2i64 addr:$src2)),
-                                  UNPCKL_shuffle_mask)))]>;
+                          (unpckl VR128:$src1,
+                                  (bc_v16i8 (memopv2i64 addr:$src2))))]>;
   def PUNPCKLWDrr : PDI<0x61, MRMSrcReg, 
                         (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                         "punpcklwd\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
-                                  UNPCKL_shuffle_mask)))]>;
+                          (v8i16 (unpckl VR128:$src1, VR128:$src2)))]>;
   def PUNPCKLWDrm : PDI<0x61, MRMSrcMem, 
                         (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
                         "punpcklwd\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v8i16 (vector_shuffle VR128:$src1,
-                                  (bc_v8i16 (memopv2i64 addr:$src2)),
-                                  UNPCKL_shuffle_mask)))]>;
+                          (unpckl VR128:$src1,
+                                  (bc_v8i16 (memopv2i64 addr:$src2))))]>;
   def PUNPCKLDQrr : PDI<0x62, MRMSrcReg, 
                         (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                         "punpckldq\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
-                                  UNPCKL_shuffle_mask)))]>;
+                          (v4i32 (unpckl VR128:$src1, VR128:$src2)))]>;
   def PUNPCKLDQrm : PDI<0x62, MRMSrcMem, 
                         (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
                         "punpckldq\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v4i32 (vector_shuffle VR128:$src1,
-                                  (bc_v4i32 (memopv2i64 addr:$src2)),
-                                  UNPCKL_shuffle_mask)))]>;
+                          (unpckl VR128:$src1,
+                                  (bc_v4i32 (memopv2i64 addr:$src2))))]>;
   def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg, 
                          (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                          "punpcklqdq\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
-                                  UNPCKL_shuffle_mask)))]>;
+                          (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
   def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem, 
                          (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
                          "punpcklqdq\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v2i64 (vector_shuffle VR128:$src1,
-                                  (memopv2i64 addr:$src2),
-                                  UNPCKL_shuffle_mask)))]>;
+                          (v2i64 (unpckl VR128:$src1,
+                                         (memopv2i64 addr:$src2))))]>;
   
   def PUNPCKHBWrr : PDI<0x68, MRMSrcReg, 
                         (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                         "punpckhbw\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
-                                  UNPCKH_shuffle_mask)))]>;
+                          (v16i8 (unpckh VR128:$src1, VR128:$src2)))]>;
   def PUNPCKHBWrm : PDI<0x68, MRMSrcMem, 
                         (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
                         "punpckhbw\t{$src2, $dst|$dst, $src2}",
-                        [(set VR128:$dst,
-                          (v16i8 (vector_shuffle VR128:$src1,
-                                  (bc_v16i8 (memopv2i64 addr:$src2)),
-                                  UNPCKH_shuffle_mask)))]>;
+                        [(set VR128:$dst, 
+                          (unpckh VR128:$src1, 
+                                  (bc_v16i8 (memopv2i64 addr:$src2))))]>;
   def PUNPCKHWDrr : PDI<0x69, MRMSrcReg, 
                         (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                         "punpckhwd\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
-                                  UNPCKH_shuffle_mask)))]>;
+                          (v8i16 (unpckh VR128:$src1, VR128:$src2)))]>;
   def PUNPCKHWDrm : PDI<0x69, MRMSrcMem, 
                         (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
                         "punpckhwd\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v8i16 (vector_shuffle VR128:$src1,
-                                  (bc_v8i16 (memopv2i64 addr:$src2)),
-                                  UNPCKH_shuffle_mask)))]>;
+                          (unpckh VR128:$src1,
+                                  (bc_v8i16 (memopv2i64 addr:$src2))))]>;
   def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg, 
                         (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                         "punpckhdq\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
-                                  UNPCKH_shuffle_mask)))]>;
+                          (v4i32 (unpckh VR128:$src1, VR128:$src2)))]>;
   def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem, 
                         (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
                         "punpckhdq\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v4i32 (vector_shuffle VR128:$src1,
-                                  (bc_v4i32 (memopv2i64 addr:$src2)),
-                                  UNPCKH_shuffle_mask)))]>;
+                          (unpckh VR128:$src1,
+                                  (bc_v4i32 (memopv2i64 addr:$src2))))]>;
   def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg, 
                          (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                          "punpckhqdq\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
-                                  UNPCKH_shuffle_mask)))]>;
+                          (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
   def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem, 
                         (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
                         "punpckhqdq\t{$src2, $dst|$dst, $src2}",
                         [(set VR128:$dst,
-                          (v2i64 (vector_shuffle VR128:$src1,
-                                  (memopv2i64 addr:$src2),
-                                  UNPCKH_shuffle_mask)))]>;
+                          (v2i64 (unpckh VR128:$src1,
+                                         (memopv2i64 addr:$src2))))]>;
 }
 
 // Extract / Insert
@@ -2357,8 +2311,7 @@
                        (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                        "movsd\t{$src2, $dst|$dst, $src2}",
                        [(set VR128:$dst,
-                         (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
-                                 MOVL_shuffle_mask)))]>;
+                         (v2f64 (movl VR128:$src1, VR128:$src2)))]>;
 }
 
 // Store / copy lower 64-bits of a XMM register.
@@ -2449,44 +2402,35 @@
 // Move Instructions
 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                       "movshdup\t{$src, $dst|$dst, $src}",
-                      [(set VR128:$dst, (v4f32 (vector_shuffle
-                                                VR128:$src, (undef),
-                                                MOVSHDUP_shuffle_mask)))]>;
+                      [(set VR128:$dst, (v4f32 (movshdup
+                                                VR128:$src, (undef))))]>;
 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
                       "movshdup\t{$src, $dst|$dst, $src}",
-                      [(set VR128:$dst, (v4f32 (vector_shuffle
-                                                (memopv4f32 addr:$src), (undef),
-                                                MOVSHDUP_shuffle_mask)))]>;
+                      [(set VR128:$dst, (movshdup
+                                         (memopv4f32 addr:$src), (undef)))]>;
 
 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                       "movsldup\t{$src, $dst|$dst, $src}",
-                      [(set VR128:$dst, (v4f32 (vector_shuffle
-                                                VR128:$src, (undef),
-                                                MOVSLDUP_shuffle_mask)))]>;
+                      [(set VR128:$dst, (v4f32 (movsldup
+                                                VR128:$src, (undef))))]>;
 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
                       "movsldup\t{$src, $dst|$dst, $src}",
-                      [(set VR128:$dst, (v4f32 (vector_shuffle
-                                                (memopv4f32 addr:$src), (undef),
-                                                MOVSLDUP_shuffle_mask)))]>;
+                      [(set VR128:$dst, (movsldup
+                                         (memopv4f32 addr:$src), (undef)))]>;
 
 def MOVDDUPrr  : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                       "movddup\t{$src, $dst|$dst, $src}",
-                      [(set VR128:$dst,
-                         (v2f64 (vector_shuffle VR128:$src, (undef),
-                                                MOVDDUP_shuffle_mask)))]>;
+                      [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
 def MOVDDUPrm  : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
                       "movddup\t{$src, $dst|$dst, $src}",
                     [(set VR128:$dst,
-                      (v2f64 (vector_shuffle
-                              (scalar_to_vector (loadf64 addr:$src)),
-                              (undef), MOVDDUP_shuffle_mask)))]>;
-
-def : Pat<(vector_shuffle
-             (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
-             (undef), MOVDDUP_shuffle_mask),
+                      (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
+                                      (undef))))]>;
+
+def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
+                   (undef)),
           (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
-def : Pat<(vector_shuffle
-            (memopv2f64 addr:$src), (undef), MOVDDUP_shuffle_mask),
+def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
           (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
 
 
@@ -2555,22 +2499,18 @@
 
 // vector_shuffle v1, <undef> <1, 1, 3, 3>
 let AddedComplexity = 15 in
-def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
-                  MOVSHDUP_shuffle_mask)),
+def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
           (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
 let AddedComplexity = 20 in
-def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
-                  MOVSHDUP_shuffle_mask)),
+def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
           (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
 
 // vector_shuffle v1, <undef> <0, 0, 2, 2>
 let AddedComplexity = 15 in
-  def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
-                    MOVSLDUP_shuffle_mask)),
+  def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
             (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
 let AddedComplexity = 20 in
-  def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
-                    MOVSLDUP_shuffle_mask)),
+  def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
             (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
 
 //===----------------------------------------------------------------------===//
@@ -2911,207 +2851,173 @@
 
 // Splat v2f64 / v2i64
 let AddedComplexity = 10 in {
-def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
+def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
           (UNPCKLPDrr VR128:$src, VR128:$src)>,   Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
+def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
           (UNPCKHPDrr VR128:$src, VR128:$src)>,   Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
+def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
           (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
+def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
           (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
 }
 
 // Special unary SHUFPSrri case.
-def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
-           SHUFP_unary_shuffle_mask:$sm)),
-          (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
+def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
+          (SHUFPSrri VR128:$src1, VR128:$src1,
+                     (SHUFFLE_get_shuf_imm VR128:$src3))>,
       Requires<[HasSSE1]>;
+let AddedComplexity = 5 in
+def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
+          (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
+      Requires<[HasSSE2]>;
+// Special unary SHUFPDrri case.
+def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
+          (SHUFPDrri VR128:$src1, VR128:$src1, 
+                     (SHUFFLE_get_shuf_imm VR128:$src3))>,
+      Requires<[HasSSE2]>;
 // Special unary SHUFPDrri case.
-def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
-           SHUFP_unary_shuffle_mask:$sm)),
-          (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
+def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
+          (SHUFPDrri VR128:$src1, VR128:$src1, 
+                     (SHUFFLE_get_shuf_imm VR128:$src3))>,
       Requires<[HasSSE2]>;
 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
-def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
-           SHUFP_unary_shuffle_mask:$sm),
-          (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
+def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
+          (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
       Requires<[HasSSE2]>;
 
 // Special binary v4i32 shuffle cases with SHUFPS.
-def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
-           PSHUFD_binary_shuffle_mask:$sm)),
-          (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
+def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
+          (SHUFPSrri VR128:$src1, VR128:$src2, 
+                     (SHUFFLE_get_shuf_imm VR128:$src3))>,
            Requires<[HasSSE2]>;
-def : Pat<(v4i32 (vector_shuffle VR128:$src1,
-           (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
-          (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
+def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
+          (SHUFPSrmi VR128:$src1, addr:$src2, 
+                    (SHUFFLE_get_shuf_imm VR128:$src3))>,
            Requires<[HasSSE2]>;
 // Special binary v2i64 shuffle cases using SHUFPDrri.
-def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
-                 SHUFP_shuffle_mask:$sm)),
-          (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
+def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
+          (SHUFPDrri VR128:$src1, VR128:$src2, 
+                     (SHUFFLE_get_shuf_imm VR128:$src3))>,
           Requires<[HasSSE2]>;
-// Special unary SHUFPDrri case.
-def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
-                  SHUFP_unary_shuffle_mask:$sm)),
-          (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
-      Requires<[HasSSE2]>;
 
 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
 let AddedComplexity = 15 in {
-def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
-                                 UNPCKL_v_undef_shuffle_mask:$sm)),
-          (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
+def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
+          (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
           Requires<[OptForSpeed, HasSSE2]>;
-def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
-                                 UNPCKL_v_undef_shuffle_mask:$sm)),
-          (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
+def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
+          (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
           Requires<[OptForSpeed, HasSSE2]>;
 }
 let AddedComplexity = 10 in {
-def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
-                  UNPCKL_v_undef_shuffle_mask)),
+def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
           (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
-def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
-                  UNPCKL_v_undef_shuffle_mask)),
+def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
           (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
-def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
-                  UNPCKL_v_undef_shuffle_mask)),
+def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
           (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
-def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
-                  UNPCKL_v_undef_shuffle_mask)),
+def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
           (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
 }
 
 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
 let AddedComplexity = 15 in {
-def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
-                 UNPCKH_v_undef_shuffle_mask:$sm)),
-          (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
+def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
+          (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
           Requires<[OptForSpeed, HasSSE2]>;
-def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
-                 UNPCKH_v_undef_shuffle_mask:$sm)),
-          (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
+def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
+          (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
           Requires<[OptForSpeed, HasSSE2]>;
 }
 let AddedComplexity = 10 in {
-def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
-                  UNPCKH_v_undef_shuffle_mask)),
+def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
           (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
-def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
-                  UNPCKH_v_undef_shuffle_mask)),
+def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
           (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
-def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
-                  UNPCKH_v_undef_shuffle_mask)),
+def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
           (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
-def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
-                  UNPCKH_v_undef_shuffle_mask)),
+def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
           (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
 }
 
 let AddedComplexity = 20 in {
 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
-def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
-                  MOVHP_shuffle_mask)),
+def : Pat<(v4i32 (movhp VR128:$src1, VR128:$src2)),
           (MOVLHPSrr VR128:$src1, VR128:$src2)>;
 
 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
-def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
-                  MOVHLPS_shuffle_mask)),
+def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
           (MOVHLPSrr VR128:$src1, VR128:$src2)>;
 
 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
-def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
-                  MOVHLPS_v_undef_shuffle_mask)),
+def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
           (MOVHLPSrr VR128:$src1, VR128:$src1)>;
-def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
-                  MOVHLPS_v_undef_shuffle_mask)),
+def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
           (MOVHLPSrr VR128:$src1, VR128:$src1)>;
 }
 
 let AddedComplexity = 20 in {
 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
-def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
-                  MOVLP_shuffle_mask)),
+def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
           (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
-                  MOVLP_shuffle_mask)),
+def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
           (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
-def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
-                  MOVHP_shuffle_mask)),
+def : Pat<(v4f32 (movhp VR128:$src1, (load addr:$src2))),
           (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
-                  MOVHP_shuffle_mask)),
+def : Pat<(v2f64 (movhp VR128:$src1, (load addr:$src2))),
           (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
 
-def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
-                  MOVLP_shuffle_mask)),
+def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
           (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
-def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
-                  MOVLP_shuffle_mask)),
+def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
           (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
-def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
-                  MOVHP_shuffle_mask)),
+def : Pat<(v4i32 (movhp VR128:$src1, (load addr:$src2))),
           (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
-                  MOVHP_shuffle_mask)),
+def : Pat<(v2i64 (movhp VR128:$src1, (load addr:$src2))),
           (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
 }
 
 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
-def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2,
-                         MOVLP_shuffle_mask)), addr:$src1),
+def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
           (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2,
-                         MOVLP_shuffle_mask)), addr:$src1),
+def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
           (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
-def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2,
-                         MOVHP_shuffle_mask)), addr:$src1),
+def : Pat<(store (v4f32 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
           (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2,
-                         MOVHP_shuffle_mask)), addr:$src1),
+def : Pat<(store (v2f64 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
           (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
 
-def : Pat<(store (v4i32 (vector_shuffle
-                         (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2,
-                         MOVLP_shuffle_mask)), addr:$src1),
+def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
+                 addr:$src1),
           (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2,
-                         MOVLP_shuffle_mask)), addr:$src1),
+def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
           (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
-def : Pat<(store (v4i32 (vector_shuffle
-                         (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2,
-                         MOVHP_shuffle_mask)), addr:$src1),
+def : Pat<(store (v4i32 (movhp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
+                 addr:$src1),
           (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2,
-                         MOVHP_shuffle_mask)), addr:$src1),
+def : Pat<(store (v2i64 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
           (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
 
 
 let AddedComplexity = 15 in {
 // Setting the lowest element in the vector.
-def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
-                  MOVL_shuffle_mask)),
+def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
           (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
-def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
-                  MOVL_shuffle_mask)),
+def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
           (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
 
 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
-def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
-                  MOVLP_shuffle_mask)),
+def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
           (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
-def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
-                  MOVLP_shuffle_mask)),
+def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
           (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
 }
 
 // Set lowest element and zero upper elements.
 let AddedComplexity = 15 in
-def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
-           MOVL_shuffle_mask)),
+def : Pat<(v2f64 (movl immAllZerosV_bc, VR128:$src)),
           (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
           (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;

Modified: llvm/trunk/test/CodeGen/Generic/vector-casts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/vector-casts.ll?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/vector-casts.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/vector-casts.ll Mon Apr 27 13:41:29 2009
@@ -1,45 +1,9 @@
 ; RUN: llvm-as < %s | llc
 ; PR2671
 
-define void @a(<2 x double>* %p, <2 x i8>* %q) {
-        %t = load <2 x double>* %p
-	%r = fptosi <2 x double> %t to <2 x i8>
-        store <2 x i8> %r, <2 x i8>* %q
-	ret void
-}
-define void @b(<2 x double>* %p, <2 x i8>* %q) {
-        %t = load <2 x double>* %p
-	%r = fptoui <2 x double> %t to <2 x i8>
-        store <2 x i8> %r, <2 x i8>* %q
-	ret void
-}
-define void @c(<2 x i8>* %p, <2 x double>* %q) {
-        %t = load <2 x i8>* %p
-	%r = sitofp <2 x i8> %t to <2 x double>
-        store <2 x double> %r, <2 x double>* %q
-	ret void
-}
-define void @d(<2 x i8>* %p, <2 x double>* %q) {
-        %t = load <2 x i8>* %p
-	%r = uitofp <2 x i8> %t to <2 x double>
-        store <2 x double> %r, <2 x double>* %q
-	ret void
-}
-define void @e(<2 x i8>* %p, <2 x i16>* %q) {
-        %t = load <2 x i8>* %p
-	%r = sext <2 x i8> %t to <2 x i16>
-        store <2 x i16> %r, <2 x i16>* %q
-	ret void
-}
-define void @f(<2 x i8>* %p, <2 x i16>* %q) {
-        %t = load <2 x i8>* %p
-	%r = zext <2 x i8> %t to <2 x i16>
-        store <2 x i16> %r, <2 x i16>* %q
-	ret void
-}
 define void @g(<2 x i16>* %p, <2 x i8>* %q) {
-        %t = load <2 x i16>* %p
-	%r = trunc <2 x i16> %t to <2 x i8>
-        store <2 x i8> %r, <2 x i8>* %q
-	ret void
+  %t = load <2 x i16>* %p
+  %r = trunc <2 x i16> %t to <2 x i8>
+  store <2 x i8> %r, <2 x i8>* %q
+  ret void
 }

Modified: llvm/trunk/test/CodeGen/X86/vec_clear.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_clear.ll?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_clear.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_clear.ll Mon Apr 27 13:41:29 2009
@@ -1,5 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | not grep and
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | grep psrldq
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -o %t -f
+; RUN: not grep and %t
+; RUN: not grep psrldq %t
+; RUN: grep xorps %t
 
 define <4 x float> @test(<4 x float>* %v1) nounwind {
         %tmp = load <4 x float>* %v1            ; <<4 x float>> [#uses=1]

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-10.ll?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-10.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-10.ll Mon Apr 27 13:41:29 2009
@@ -1,9 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | \
-; RUN:   grep unpcklps | count 1
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | \
-; RUN:   grep unpckhps | count 1
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | \
-; RUN:   not grep {sub.*esp}
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t -f
+; RUN: grep unpcklps %t | count 1
+; RUN: grep pshufd   %t | count 1
+; RUN: not grep {sub.*esp} %t
 
 define void @test(<4 x float>* %res, <4 x float>* %A, <4 x float>* %B) {
 	%tmp = load <4 x float>* %B		; <<4 x float>> [#uses=2]

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-16.ll?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-16.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-16.ll Mon Apr 27 13:41:29 2009
@@ -1,8 +1,10 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,-sse2 | grep shufps | count 4
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,-sse2 -mtriple=i386-apple-darwin | grep mov | count 2
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufd | count 4
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep shufps
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | not grep mov
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,-sse2 -mtriple=i386-apple-darwin -o %t -f
+; RUN: grep shufps %t | count 4
+; RUN: grep movaps %t | count 2
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -o %t -f
+; RUN: grep pshufd %t | count 4
+; RUN: not grep shufps %t
+; RUN: not grep mov %t
 
 define <4 x float> @t1(<4 x float> %a, <4 x float> %b) nounwind  {
         %tmp1 = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-30.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-30.ll?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-30.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-30.ll Mon Apr 27 13:41:29 2009
@@ -1,8 +1,7 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -disable-mmx -o %t -f
 ; RUN: grep pshufhw %t | grep 161 | count 1
-; RUN: grep pslldq %t | count 1
-
-
+; RUN: grep shufps %t | count 1
+; RUN: not grep pslldq %t
 
 ; Test case when creating pshufhw, we incorrectly set the higher order bit
 ; for an undef,
@@ -20,4 +19,4 @@
   %0 = shufflevector <4 x i32> %in, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> < i32 undef, i32 5, i32 undef, i32 2>
   store <4 x i32> %0, <4 x i32>* %dest
   ret void
-}       
\ No newline at end of file
+}

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-31.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-31.ll?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-31.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-31.ll Mon Apr 27 13:41:29 2009
@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah -o %t -f
 ; RUN: grep pextrw %t | count 1
-; RUN: grep punpcklqdq %t | count 1
+; RUN: grep movlhps %t | count 1
 ; RUN: grep pshufhw %t | count 1
 ; RUN: grep pinsrw %t | count 1
 ; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 -o %t -f

Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Mon Apr 27 13:41:29 2009
@@ -194,10 +194,6 @@
     ConstraintType = SDTCisOpSmallerThanOp;
     x.SDTCisOpSmallerThanOp_Info.BigOperandNum = 
       R->getValueAsInt("BigOperandNum");
-  } else if (R->isSubClassOf("SDTCisIntVectorOfSameSize")) {
-    ConstraintType = SDTCisIntVectorOfSameSize;
-    x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum =
-      R->getValueAsInt("OtherOpNum");
   } else if (R->isSubClassOf("SDTCisEltOfVec")) {
     ConstraintType = SDTCisEltOfVec;
     x.SDTCisEltOfVec_Info.OtherOperandNum =
@@ -365,23 +361,9 @@
     }    
     return MadeChange;
   }
-  case SDTCisIntVectorOfSameSize: {
-    TreePatternNode *OtherOperand =
-      getOperandNum(x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum,
-                    N, NumResults);
-    if (OtherOperand->hasTypeSet()) {
-      if (!isVector(OtherOperand->getTypeNum(0)))
-        TP.error(N->getOperator()->getName() + " VT operand must be a vector!");
-      MVT IVT = OtherOperand->getTypeNum(0);
-      unsigned NumElements = IVT.getVectorNumElements();
-      IVT = MVT::getIntVectorWithNumElements(NumElements);
-      return NodeToApply->UpdateNodeType(IVT.getSimpleVT(), TP);
-    }
-    return false;
-  }
   case SDTCisEltOfVec: {
     TreePatternNode *OtherOperand =
-      getOperandNum(x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum,
+      getOperandNum(x.SDTCisEltOfVec_Info.OtherOperandNum,
                     N, NumResults);
     if (OtherOperand->hasTypeSet()) {
       if (!isVector(OtherOperand->getTypeNum(0)))
@@ -925,25 +907,6 @@
     if (NI.getNumResults() == 0)
       MadeChange |= UpdateNodeType(MVT::isVoid, TP);
     
-    // If this is a vector_shuffle operation, apply types to the build_vector
-    // operation.  The types of the integers don't matter, but this ensures they
-    // won't get checked.
-    if (getOperator()->getName() == "vector_shuffle" &&
-        getChild(2)->getOperator()->getName() == "build_vector") {
-      TreePatternNode *BV = getChild(2);
-      const std::vector<MVT::SimpleValueType> &LegalVTs
-        = CDP.getTargetInfo().getLegalValueTypes();
-      MVT::SimpleValueType LegalIntVT = MVT::Other;
-      for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
-        if (isInteger(LegalVTs[i]) && !isVector(LegalVTs[i])) {
-          LegalIntVT = LegalVTs[i];
-          break;
-        }
-      assert(LegalIntVT != MVT::Other && "No legal integer VT?");
-            
-      for (unsigned i = 0, e = BV->getNumChildren(); i != e; ++i)
-        MadeChange |= BV->getChild(i)->UpdateNodeType(LegalIntVT, TP);
-    }
     return MadeChange;  
   } else if (getOperator()->isSubClassOf("Instruction")) {
     const DAGInstruction &Inst = CDP.getInstruction(getOperator());
@@ -2086,7 +2049,7 @@
       IterateInference |= Result->getTree(0)->
         UpdateNodeType(Pattern->getTree(0)->getExtTypes(), *Result);
     } while (IterateInference);
-
+    
     // Verify that we inferred enough types that we can do something with the
     // pattern and result.  If these fire the user has to add type casts.
     if (!InferredAllPatternTypes)

Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=70225&r1=70224&r2=70225&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Mon Apr 27 13:41:29 2009
@@ -62,8 +62,7 @@
   unsigned OperandNo;   // The operand # this constraint applies to.
   enum { 
     SDTCisVT, SDTCisPtrTy, SDTCisInt, SDTCisFP, SDTCisSameAs, 
-    SDTCisVTSmallerThanOp, SDTCisOpSmallerThanOp, SDTCisIntVectorOfSameSize,
-    SDTCisEltOfVec
+    SDTCisVTSmallerThanOp, SDTCisOpSmallerThanOp, SDTCisEltOfVec
   } ConstraintType;
   
   union {   // The discriminated union.
@@ -81,9 +80,6 @@
     } SDTCisOpSmallerThanOp_Info;
     struct {
       unsigned OtherOperandNum;
-    } SDTCisIntVectorOfSameSize_Info;
-    struct {
-      unsigned OtherOperandNum;
     } SDTCisEltOfVec_Info;
   } x;
 




From natebegeman at mac.com  Mon Apr 27 13:42:40 2009
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 27 Apr 2009 18:42:40 -0000
Subject: [llvm-commits] [llvm] r70226 -
	/llvm/trunk/test/CodeGen/Generic/vector-casts.ll
Message-ID: <200904271842.n3RIgfiN015634@zion.cs.uiuc.edu>

Author: sampo
Date: Mon Apr 27 13:42:40 2009
New Revision: 70226

URL: http://llvm.org/viewvc/llvm-project?rev=70226&view=rev
Log:
Revert accidental testcase reduction

Modified:
    llvm/trunk/test/CodeGen/Generic/vector-casts.ll

Modified: llvm/trunk/test/CodeGen/Generic/vector-casts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/vector-casts.ll?rev=70226&r1=70225&r2=70226&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/vector-casts.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/vector-casts.ll Mon Apr 27 13:42:40 2009
@@ -1,9 +1,45 @@
 ; RUN: llvm-as < %s | llc
 ; PR2671
 
+define void @a(<2 x double>* %p, <2 x i8>* %q) {
+        %t = load <2 x double>* %p
+	%r = fptosi <2 x double> %t to <2 x i8>
+        store <2 x i8> %r, <2 x i8>* %q
+	ret void
+}
+define void @b(<2 x double>* %p, <2 x i8>* %q) {
+        %t = load <2 x double>* %p
+	%r = fptoui <2 x double> %t to <2 x i8>
+        store <2 x i8> %r, <2 x i8>* %q
+	ret void
+}
+define void @c(<2 x i8>* %p, <2 x double>* %q) {
+        %t = load <2 x i8>* %p
+	%r = sitofp <2 x i8> %t to <2 x double>
+        store <2 x double> %r, <2 x double>* %q
+	ret void
+}
+define void @d(<2 x i8>* %p, <2 x double>* %q) {
+        %t = load <2 x i8>* %p
+	%r = uitofp <2 x i8> %t to <2 x double>
+        store <2 x double> %r, <2 x double>* %q
+	ret void
+}
+define void @e(<2 x i8>* %p, <2 x i16>* %q) {
+        %t = load <2 x i8>* %p
+	%r = sext <2 x i8> %t to <2 x i16>
+        store <2 x i16> %r, <2 x i16>* %q
+	ret void
+}
+define void @f(<2 x i8>* %p, <2 x i16>* %q) {
+        %t = load <2 x i8>* %p
+	%r = zext <2 x i8> %t to <2 x i16>
+        store <2 x i16> %r, <2 x i16>* %q
+	ret void
+}
 define void @g(<2 x i16>* %p, <2 x i8>* %q) {
-  %t = load <2 x i16>* %p
-  %r = trunc <2 x i16> %t to <2 x i8>
-  store <2 x i8> %r, <2 x i8>* %q
-  ret void
+        %t = load <2 x i16>* %p
+	%r = trunc <2 x i16> %t to <2 x i8>
+        store <2 x i8> %r, <2 x i8>* %q
+	ret void
 }




From dalej at apple.com  Mon Apr 27 14:13:44 2009
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 27 Apr 2009 19:13:44 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r70231 -
	/llvm-gcc-4.2/trunk/gcc/objc/objc-act.c
Message-ID: <200904271913.n3RJDic7016626@zion.cs.uiuc.edu>

Author: johannes
Date: Mon Apr 27 14:13:43 2009
New Revision: 70231

URL: http://llvm.org/viewvc/llvm-project?rev=70231&view=rev
Log:
Fix a layout difference with gcc.  6817146.


Modified:
    llvm-gcc-4.2/trunk/gcc/objc/objc-act.c

Modified: llvm-gcc-4.2/trunk/gcc/objc/objc-act.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/objc/objc-act.c?rev=70231&r1=70230&r2=70231&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/objc/objc-act.c (original)
+++ llvm-gcc-4.2/trunk/gcc/objc/objc-act.c Mon Apr 27 14:13:43 2009
@@ -1018,6 +1018,23 @@
   objc_method_optional_flag = 0;
 }
 
+#ifdef ENABLE_LLVM
+/* Return size in bits this class occupies when used as a base class. */
+static int realClassSize(tree class)
+{
+  unsigned int instanceSize = 0;
+  tree field = TYPE_FIELDS (class);
+  while (field && TREE_CHAIN (field)
+         && TREE_CODE (TREE_CHAIN (field)) == FIELD_DECL)
+    field = TREE_CHAIN (field);
+  
+  if (field && TREE_CODE (field) == FIELD_DECL)
+    instanceSize = int_byte_position (field) * BITS_PER_UNIT + 
+                          tree_low_cst (DECL_SIZE (field), 0);
+  return instanceSize;
+}
+#endif
+
 void
 objc_start_class_implementation (tree class, tree super_class)
 {
@@ -1044,18 +1061,24 @@
               /* If we have an embedded base class, and its size doesn't match the
                  size in the field node, that's because ivars were added to the base
                  class after the field node was built.  We need to update the field
-                 node and re-layout the outer record. */
+                 node and re-layout the outer record. 
+                 Note that we can't rely on the size in the TYPE_SIZE node of
+                 the embedded base class type, it is wrong for some cases
+                 involving bitfields (!) */
               if (DECL_ARTIFICIAL (field) && !DECL_NAME (field)
                   && TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE
-                  && DECL_SIZE (field) && TYPE_SIZE(TREE_TYPE(field))
-                  && TREE_CODE (DECL_SIZE (field)) == INTEGER_CST
-                  && TREE_CODE (TYPE_SIZE (TREE_TYPE (field))) == INTEGER_CST
-                  && TREE_INT_CST_LOW (DECL_SIZE (field))
-                     != TREE_INT_CST_LOW (TYPE_SIZE (TREE_TYPE (field))))
+                  && DECL_SIZE (field) 
+                  && TREE_CODE (DECL_SIZE (field)) == INTEGER_CST)
                 {
-                  DECL_SIZE (field) = TYPE_SIZE (TREE_TYPE (field));
-                  DECL_SIZE_UNIT (field) = TYPE_SIZE_UNIT (TREE_TYPE (field));
-                  changed = true;
+                  unsigned int realSize = realClassSize(TREE_TYPE(field));
+                  if (realSize && 
+                      TREE_INT_CST_LOW (DECL_SIZE (field)) != realSize)
+                  {
+                    DECL_SIZE (field) = build_int_cst(bitsizetype, realSize);
+                    DECL_SIZE_UNIT (field) = 
+                        build_int_cst(sizetype, realSize / BITS_PER_UNIT);
+                    changed = true;
+                  }
                 }
             }
           if (changed) 




From dalej at apple.com  Mon Apr 27 14:15:09 2009
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 27 Apr 2009 19:15:09 -0000
Subject: [llvm-commits] [llvm] r70233 -
	/llvm/trunk/test/FrontendObjC/2009-04-27-bitfield-vs-ivar.m
Message-ID: <200904271915.n3RJF9Zb016689@zion.cs.uiuc.edu>

Author: johannes
Date: Mon Apr 27 14:15:09 2009
New Revision: 70233

URL: http://llvm.org/viewvc/llvm-project?rev=70233&view=rev
Log:
Test for (llvm-gcc) 70231.


Added:
    llvm/trunk/test/FrontendObjC/2009-04-27-bitfield-vs-ivar.m

Added: llvm/trunk/test/FrontendObjC/2009-04-27-bitfield-vs-ivar.m
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendObjC/2009-04-27-bitfield-vs-ivar.m?rev=70233&view=auto

==============================================================================
--- llvm/trunk/test/FrontendObjC/2009-04-27-bitfield-vs-ivar.m (added)
+++ llvm/trunk/test/FrontendObjC/2009-04-27-bitfield-vs-ivar.m Mon Apr 27 14:15:09 2009
@@ -0,0 +1,44 @@
+// RUN: %llvmgcc -S -x objective-c -m64 -fobjc-abi-version=2 %s -o %t
+// RUN: grep {OBJC_CLASS_RO_\\\$_I4} %t | grep {i32 0, i32 1, i32 2, i32 0}
+// RUN: grep {OBJC_CLASS_RO_\\\$_I2} %t | grep {i32 0, i32 1, i32 1, i32 0}
+// RUN: grep {OBJC_CLASS_RO_\\\$_I5} %t | grep {i32 0, i32 0, i32 0, i32 0}
+// XTARGETS: darwin
+
+// Test instance variable sizing when base class ends in bitfield
+ at interface I3 {
+  unsigned int _iv2 :1;
+}
+ at end
+
+ at interface I4 : I3 {
+  char _iv4;
+}
+ at end
+
+// Test case with no instance variables in derived class
+ at interface I1 {
+  unsigned int _iv2 :1;
+}
+ at end
+
+ at interface I2 : I1 {
+}
+ at end
+
+// Test case with no instance variables anywhere
+ at interface I6 {
+}
+ at end
+
+ at interface I5 : I6 {
+}
+ at end
+
+ at implementation I4
+ at end
+
+ at implementation I2
+ at end
+
+ at implementation I5
+ at end




From baldrick at free.fr  Mon Apr 27 14:33:05 2009
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 27 Apr 2009 19:33:05 -0000
Subject: [llvm-commits] [llvm] r70234 - in
 /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp LegalizeTypes.cpp
 LegalizeTypes.h LegalizeVectorTypes.cpp
Message-ID: <200904271933.n3RJX59P017484@zion.cs.uiuc.edu>

Author: baldrick
Date: Mon Apr 27 14:33:03 2009
New Revision: 70234

URL: http://llvm.org/viewvc/llvm-project?rev=70234&view=rev
Log:
Now that PR2957 is resolved, remove a bunch of
no-longer needed workarounds.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70234&r1=70233&r2=70234&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 27 14:33:03 2009
@@ -489,10 +489,8 @@
   // If the type legalizer was run then we should never see any illegal result
   // types here except for target constants (the type legalizer does not touch
   // those) or for build vector used as a mask for a vector shuffle.
-  // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
   assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
-          IsLegalizingCallArgs || Op.getOpcode() == ISD::TargetConstant ||
-          Op.getOpcode() == ISD::BUILD_VECTOR) &&
+          IsLegalizingCallArgs || Op.getOpcode() == ISD::TargetConstant) &&
          "Illegal type introduced after type legalization?");
   switch (getTypeAction(VT)) {
   default: assert(0 && "Bad type action!");

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=70234&r1=70233&r2=70234&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Mon Apr 27 14:33:03 2009
@@ -116,11 +116,8 @@
           cerr << "Unprocessed value in a map!";
           Failed = true;
         }
-      } else if (isTypeLegal(Res.getValueType()) || IgnoreNodeResults(I)) {
-        // FIXME: Because of PR2957, the build vector can be placed on this
-        // list but if the associated vector shuffle is split, the build vector
-        // can also be split so we allow this to go through for now.
-        if (Mapped > 1 && Res.getOpcode() != ISD::BUILD_VECTOR) {
+      } else if (isTypeLegal(Res.getValueType())) {
+        if (Mapped > 1) {
           cerr << "Value with legal type was transformed!";
           Failed = true;
         }
@@ -266,13 +263,6 @@
       if (IgnoreNodeResults(N->getOperand(i).getNode()))
         continue;
 
-      if (N->getOpcode() == ISD::VECTOR_SHUFFLE && i == 2) {
-        // The shuffle mask doesn't need to be a legal vector type.
-        // FIXME: We can remove this once we fix PR2957.
-        SetIgnoredNodeResult(N->getOperand(2).getNode());
-        continue;
-      }
-
       MVT OpVT = N->getOperand(i).getValueType();
       switch (getTypeAction(OpVT)) {
       default:
@@ -842,10 +832,6 @@
   OpEntry = Result;
 }
 
-// Set to ignore result
-void DAGTypeLegalizer::SetIgnoredNodeResult(SDNode* N) {
-  IgnoredNodesResultsSet.insert(N);
-}
 
 //===----------------------------------------------------------------------===//
 // Utilities.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=70234&r1=70233&r2=70234&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Apr 27 14:33:03 2009
@@ -114,16 +114,10 @@
   }
 
   /// IgnoreNodeResults - Pretend all of this node's results are legal.
-  /// FIXME: Remove once PR2957 is done.
   bool IgnoreNodeResults(SDNode *N) const {
-    return N->getOpcode() == ISD::TargetConstant ||
-           IgnoredNodesResultsSet.count(N);
+    return N->getOpcode() == ISD::TargetConstant;
   }
 
-  /// IgnoredNode - Set of nodes whose result don't need to be legal.
-  /// FIXME: Remove once PR2957 is done.
-  DenseSet<SDNode*> IgnoredNodesResultsSet;
-
   /// PromotedIntegers - For integer nodes that are below legal width, this map
   /// indicates what promoted value to use.
   DenseMap<SDValue, SDValue> PromotedIntegers;
@@ -202,7 +196,6 @@
   SDValue PromoteTargetBoolean(SDValue Bool, MVT VT);
   void ReplaceValueWith(SDValue From, SDValue To);
   void ReplaceValueWithHelper(SDValue From, SDValue To);
-  void SetIgnoredNodeResult(SDNode* N);
   void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
   void SplitInteger(SDValue Op, MVT LoVT, MVT HiVT,
                     SDValue &Lo, SDValue &Hi);
@@ -577,7 +570,6 @@
   SDValue SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
   SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
   SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
-  SDValue SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo);
 
   //===--------------------------------------------------------------------===//
   // Vector Widening Support: LegalizeVectorTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=70234&r1=70233&r2=70234&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Mon Apr 27 14:33:03 2009
@@ -910,7 +910,6 @@
     case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
     case ISD::STORE:             Res = SplitVecOp_STORE(cast<StoreSDNode>(N),
                                                         OpNo); break;
-    case ISD::VECTOR_SHUFFLE:    Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break;
 
     case ISD::CTTZ:
     case ISD::CTLZ:
@@ -1073,67 +1072,6 @@
   return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
 }
 
-SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
-  assert(OpNo == 2 && "Shuffle source type differs from result type?");
-  SDValue Mask = N->getOperand(2);
-  DebugLoc dl = N->getDebugLoc();
-  unsigned MaskLength = Mask.getValueType().getVectorNumElements();
-  unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
-  unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
-
-  // Look for a legal vector type to place the mask values in.
-  // Note that there may not be *any* legal vector-of-integer
-  // type for which the element type is legal!
-  for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
-       EltVT <= MVT::LAST_INTEGER_VALUETYPE;
-       // Integer values types are consecutively numbered.  Exploit this.
-       EltVT = MVT::SimpleValueType(EltVT + 1)) {
-
-    // Is the element type big enough to hold the values?
-    if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
-      // Nope.
-      continue;
-
-    // Is the vector type legal?
-    MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
-    if (!isTypeLegal(VecVT))
-      // Nope.
-      continue;
-
-    // If the element type is not legal, find a larger legal type to use for
-    // the BUILD_VECTOR operands.  This is an ugly hack, but seems to work!
-    // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
-    // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
-    for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
-         // Integer values types are consecutively numbered.  Exploit this.
-         OpVT = MVT::SimpleValueType(OpVT + 1)) {
-      if (!isTypeLegal(OpVT))
-        continue;
-
-      // Success!  Rebuild the vector using the legal types.
-      SmallVector<SDValue, 16> Ops(MaskLength);
-      for (unsigned i = 0; i < MaskLength; ++i) {
-        SDValue Arg = Mask.getOperand(i);
-        if (Arg.getOpcode() == ISD::UNDEF) {
-          Ops[i] = DAG.getUNDEF(OpVT);
-        } else {
-          uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
-          Ops[i] = DAG.getConstant(Idx, OpVT);
-        }
-      }
-      return DAG.UpdateNodeOperands(SDValue(N,0),
-                                    N->getOperand(0), N->getOperand(1),
-                                    DAG.getNode(ISD::BUILD_VECTOR, dl,
-                                                VecVT, &Ops[0], Ops.size()));
-    }
-
-    // Continuing is pointless - failure is certain.
-    break;
-  }
-  assert(false && "Failed to find an appropriate mask type!");
-  return SDValue(N, 0);
-}
-
 
 //===----------------------------------------------------------------------===//
 //  Result Vector Widening




From resistor at mac.com  Mon Apr 27 14:55:47 2009
From: resistor at mac.com (Owen Anderson)
Date: Mon, 27 Apr 2009 19:55:47 -0000
Subject: [llvm-commits] [llvm] r70238 -
	/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
Message-ID: <200904271955.n3RJtl0i018527@zion.cs.uiuc.edu>

Author: resistor
Date: Mon Apr 27 14:55:47 2009
New Revision: 70238

URL: http://llvm.org/viewvc/llvm-project?rev=70238&view=rev
Log:
Don't skip the CopyMI when removing kill markers.
This should have no effect on generated code, but makes the intermediate state
of the coalescer more sane.

Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=70238&r1=70237&r2=70238&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon Apr 27 14:55:47 2009
@@ -772,8 +772,6 @@
     if (UseMO.isKill()) {
       MachineInstr *UseMI = UseMO.getParent();
       unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
-      if (JoinedCopies.count(UseMI))
-        continue;
       const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
       if (!UI || !LI.isKill(UI->valno, UseIdx+1))
         UseMO.setIsKill(false);




From sabre at nondot.org  Mon Apr 27 15:04:09 2009
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 27 Apr 2009 20:04:09 -0000
Subject: [llvm-commits] [llvm] r70239 - in /llvm/trunk:
 include/llvm/Bitcode/BitstreamReader.h
 tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
Message-ID: <200904272004.n3RK495X018801@zion.cs.uiuc.edu>

Author: lattner
Date: Mon Apr 27 15:04:08 2009
New Revision: 70239

URL: http://llvm.org/viewvc/llvm-project?rev=70239&view=rev
Log:
give bitstreamreader an API to ignore names for blocks/records,
only llvm-bcanalyzer wants this info.

Modified:
    llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
    llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamReader.h?rev=70239&r1=70238&r2=70239&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamReader.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamReader.h Mon Apr 27 15:04:08 2009
@@ -41,11 +41,19 @@
   
   std::vector<BlockInfo> BlockInfoRecords;
 
+  /// IgnoreBlockInfoNames - This is set to true if we don't care about the
+  /// block/record name information in the BlockInfo block. Only llvm-bcanalyzer
+  /// uses this.
+  bool IgnoreBlockInfoNames;
+  
+  BitstreamReader(const BitstreamReader&);  // NOT IMPLEMENTED
+  void operator=(const BitstreamReader&);  // NOT IMPLEMENTED
 public:
-  BitstreamReader() : FirstChar(0), LastChar(0) {
+  BitstreamReader() : FirstChar(0), LastChar(0), IgnoreBlockInfoNames(true) {
   }
 
   BitstreamReader(const unsigned char *Start, const unsigned char *End) {
+    IgnoreBlockInfoNames = true;
     init(Start, End);
   }
 
@@ -70,6 +78,11 @@
   const unsigned char *getFirstChar() const { return FirstChar; }
   const unsigned char *getLastChar() const { return LastChar; }
 
+  /// CollectBlockInfoNames - This is called by clients that want block/record
+  /// name information.
+  void CollectBlockInfoNames() { IgnoreBlockInfoNames = false; }
+  bool isIgnoringBlockInfoNames() { return IgnoreBlockInfoNames; }
+  
   //===--------------------------------------------------------------------===//
   // Block Manipulation
   //===--------------------------------------------------------------------===//
@@ -598,6 +611,7 @@
         break;
       case bitc::BLOCKINFO_CODE_BLOCKNAME: {
         if (!CurBlockInfo) return true;
+        if (BitStream->isIgnoringBlockInfoNames()) break;  // Ignore name.
         std::string Name;
         for (unsigned i = 0, e = Record.size(); i != e; ++i)
           Name += (char)Record[i];
@@ -606,6 +620,7 @@
       }
       case bitc::BLOCKINFO_CODE_SETRECORDNAME: {
         if (!CurBlockInfo) return true;
+        if (BitStream->isIgnoringBlockInfoNames()) break;  // Ignore name.
         std::string Name;
         for (unsigned i = 1, e = Record.size(); i != e; ++i)
           Name += (char)Record[i];

Modified: llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp?rev=70239&r1=70238&r2=70239&view=diff

==============================================================================
--- llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp (original)
+++ llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Mon Apr 27 15:04:08 2009
@@ -464,6 +464,7 @@
   
   BitstreamReader StreamFile(BufPtr, EndBufPtr);
   BitstreamCursor Stream(StreamFile);
+  StreamFile.CollectBlockInfoNames();
   
   // Read the stream signature.
   char Signature[6];




From evan.cheng at apple.com  Mon Apr 27 15:14:52 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Apr 2009 13:14:52 -0700
Subject: [llvm-commits] [llvm] r70238 -
	/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
In-Reply-To: <200904271955.n3RJtl0i018527@zion.cs.uiuc.edu>
References: <200904271955.n3RJtl0i018527@zion.cs.uiuc.edu>
Message-ID: <64806CD5-0FAE-4E0B-A1D4-E2AD98440A0B@apple.com>


On Apr 27, 2009, at 12:55 PM, Owen Anderson wrote:

> Author: resistor
> Date: Mon Apr 27 14:55:47 2009
> New Revision: 70238
>
> URL: http://llvm.org/viewvc/llvm-project?rev=70238&view=rev
> Log:
> Don't skip the CopyMI when removing kill markers.
> This should have no effect on generated code, but makes the  
> intermediate state
> of the coalescer more sane.

Please be sure about this. I assume you ran lots of tests? One of the  
possible fallout of something like this is it breaks ARM (which uses  
scavenger). It would be nice if we can just run it as a verification  
pass.

Evan

>
>
> Modified:
>    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=70238&r1=70237&r2=70238&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon Apr 27  
> 14:55:47 2009
> @@ -772,8 +772,6 @@
>     if (UseMO.isKill()) {
>       MachineInstr *UseMI = UseMO.getParent();
>       unsigned UseIdx = li_->getUseIndex(li_- 
> >getInstructionIndex(UseMI));
> -      if (JoinedCopies.count(UseMI))
> -        continue;
>       const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
>       if (!UI || !LI.isKill(UI->valno, UseIdx+1))
>         UseMO.setIsKill(false);
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Mon Apr 27 15:15:16 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Apr 2009 13:15:16 -0700
Subject: [llvm-commits] [PATCH] Annotate virtual registers with
	register	class in debug output
In-Reply-To: <BA3F4AA9-1FCA-47C4-BD50-C13663E2FE69@2pi.dk>
References: <BA3F4AA9-1FCA-47C4-BD50-C13663E2FE69@2pi.dk>
Message-ID: <CD06DBA4-8B2A-4BD5-AA0B-C3640BB7C3CD@apple.com>

I think it's too much clutter. :-(

Evan

On Apr 27, 2009, at 10:01 AM, Jakob Stoklund Olesen wrote:

> I am using this patch when working on the Blackfin backend. Now that  
> X86 is gaining a decent set of register classes, it might be  
> generally useful.
>
> It prints machine code like this:
>
> 	%reg1025GR32<def> = MOV32rr %ESI
> 	%reg1024GR64<def> = MOV64rr %RDI
> 	%reg1026GR32_ABCD<def> = MOV32rr %reg1025GR32
> 	%reg1027GR8_ABCD_H<def> = EXTRACT_SUBREG %reg1026GR32_ABCD, 2
> 	%reg1028GR32_NOREX<def> = MOVZX32_NOREXrr8 %reg1027GR8_ABCD_H
> 	%EAX<def> = MOV32rr %reg1028GR32_NOREX
> 	RET
>
> What do you think? Too much clutter?
>
> <regclass-print.patch>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From gohman at apple.com  Mon Apr 27 15:16:15 2009
From: gohman at apple.com (Dan Gohman)
Date: Mon, 27 Apr 2009 20:16:15 -0000
Subject: [llvm-commits] [llvm] r70241 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/CodeGen/X86/masked-iv-safe.ll
 test/CodeGen/X86/masked-iv-unsafe.ll
 test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-1.ll
Message-ID: <200904272016.n3RKGFWt019147@zion.cs.uiuc.edu>

Author: djg
Date: Mon Apr 27 15:16:15 2009
New Revision: 70241

URL: http://llvm.org/viewvc/llvm-project?rev=70241&view=rev
Log:
Teach getZeroExtendExpr and getSignExtendExpr to use trip-count
information to simplify [sz]ext({a,+,b}) to {zext(a),+,[zs]ext(b)},
as appropriate.

These functions and the trip count code each call into the other, so
this requires careful handling to avoid infinite recursion. During
the initial trip count computation, conservative SCEVs are used,
which are subsequently discarded once the trip count is actually
known.

Among other benefits, this change lets LSR automatically eliminate
some unnecessary zext-inreg and sext-inreg operation where the
operand is an induction variable.

Added:
    llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll
    llvm/trunk/test/CodeGen/X86/masked-iv-unsafe.ll
Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp
    llvm/trunk/test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-1.ll

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=70241&r1=70240&r2=70241&view=diff

==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Apr 27 15:16:15 2009
@@ -701,17 +701,81 @@
   if (SCEVZeroExtendExpr *SZ = dyn_cast<SCEVZeroExtendExpr>(Op))
     return getZeroExtendExpr(SZ->getOperand(), Ty);
 
-  // FIXME: If the input value is a chrec scev, and we can prove that the value
+  // If the input value is a chrec scev, and we can prove that the value
   // did not overflow the old, smaller, value, we can zero extend all of the
-  // operands (often constants).  This would allow analysis of something like
+  // operands (often constants).  This allows analysis of something like
   // this:  for (unsigned char X = 0; X < 100; ++X) { int Y = X; }
+  if (SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(Op))
+    if (AR->isAffine()) {
+      // Check whether the backedge-taken count is SCEVCouldNotCompute.
+      // Note that this serves two purposes: It filters out loops that are
+      // simply not analyzable, and it covers the case where this code is
+      // being called from within backedge-taken count analysis, such that
+      // attempting to ask for the backedge-taken count would likely result
+      // in infinite recursion. In the later case, the analysis code will
+      // cope with a conservative value, and it will take care to purge
+      // that value once it has finished.
+      SCEVHandle BECount = getBackedgeTakenCount(AR->getLoop());
+      if (!isa<SCEVCouldNotCompute>(BECount)) {
+        // Compute the extent of AR and divide it by the step value. This is
+        // used to determine if it's safe to extend the stride value.
+        SCEVHandle Start = AR->getStart();
+        SCEVHandle Step = AR->getStepRecurrence(*this);
+
+        // Check whether the backedge-taken count can be losslessly casted to
+        // the addrec's type. The count is always unsigned.
+        SCEVHandle CastedBECount =
+          getTruncateOrZeroExtend(BECount, Start->getType());
+        if (BECount ==
+            getTruncateOrZeroExtend(CastedBECount, BECount->getType())) {
+          const Type *WideTy =
+            IntegerType::get(getTypeSizeInBits(Start->getType()) * 2);
+          SCEVHandle ZMul =
+            getMulExpr(CastedBECount,
+                       getTruncateOrZeroExtend(Step, Start->getType()));
+          // Check whether Start+Step*BECount has no unsigned overflow.
+          if (getZeroExtendExpr(ZMul, WideTy) ==
+              getMulExpr(getZeroExtendExpr(CastedBECount, WideTy),
+                         getZeroExtendExpr(Step, WideTy))) {
+            SCEVHandle Add = getAddExpr(Start, ZMul);
+            if (getZeroExtendExpr(Add, WideTy) ==
+                getAddExpr(getZeroExtendExpr(Start, WideTy),
+                           getZeroExtendExpr(ZMul, WideTy)))
+              // Return the expression with the addrec on the outside.
+              return getAddRecExpr(getZeroExtendExpr(Start, Ty),
+                                   getZeroExtendExpr(Step, Ty),
+                                   AR->getLoop());
+          }
+
+          // Similar to above, only this time treat the step value as signed.
+          // This covers loops that count down.
+          SCEVHandle SMul =
+            getMulExpr(CastedBECount,
+                       getTruncateOrSignExtend(Step, Start->getType()));
+          // Check whether Start+Step*BECount has no unsigned overflow.
+          if (getSignExtendExpr(SMul, WideTy) ==
+              getMulExpr(getZeroExtendExpr(CastedBECount, WideTy),
+                         getSignExtendExpr(Step, WideTy))) {
+            SCEVHandle Add = getAddExpr(Start, SMul);
+            if (getZeroExtendExpr(Add, WideTy) ==
+                getAddExpr(getZeroExtendExpr(Start, WideTy),
+                           getSignExtendExpr(SMul, WideTy)))
+              // Return the expression with the addrec on the outside.
+              return getAddRecExpr(getZeroExtendExpr(Start, Ty),
+                                   getSignExtendExpr(Step, Ty),
+                                   AR->getLoop());
+          }
+        }
+      }
+    }
 
   SCEVZeroExtendExpr *&Result = (*SCEVZeroExtends)[std::make_pair(Op, Ty)];
   if (Result == 0) Result = new SCEVZeroExtendExpr(Op, Ty);
   return Result;
 }
 
-SCEVHandle ScalarEvolution::getSignExtendExpr(const SCEVHandle &Op, const Type *Ty) {
+SCEVHandle ScalarEvolution::getSignExtendExpr(const SCEVHandle &Op,
+                                              const Type *Ty) {
   assert(getTypeSizeInBits(Op->getType()) < getTypeSizeInBits(Ty) &&
          "This is not an extending conversion!");
 
@@ -726,10 +790,54 @@
   if (SCEVSignExtendExpr *SS = dyn_cast<SCEVSignExtendExpr>(Op))
     return getSignExtendExpr(SS->getOperand(), Ty);
 
-  // FIXME: If the input value is a chrec scev, and we can prove that the value
+  // If the input value is a chrec scev, and we can prove that the value
   // did not overflow the old, smaller, value, we can sign extend all of the
-  // operands (often constants).  This would allow analysis of something like
+  // operands (often constants).  This allows analysis of something like
   // this:  for (signed char X = 0; X < 100; ++X) { int Y = X; }
+  if (SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(Op))
+    if (AR->isAffine()) {
+      // Check whether the backedge-taken count is SCEVCouldNotCompute.
+      // Note that this serves two purposes: It filters out loops that are
+      // simply not analyzable, and it covers the case where this code is
+      // being called from within backedge-taken count analysis, such that
+      // attempting to ask for the backedge-taken count would likely result
+      // in infinite recursion. In the later case, the analysis code will
+      // cope with a conservative value, and it will take care to purge
+      // that value once it has finished.
+      SCEVHandle BECount = getBackedgeTakenCount(AR->getLoop());
+      if (!isa<SCEVCouldNotCompute>(BECount)) {
+        // Compute the extent of AR and divide it by the step value. This is
+        // used to determine if it's safe to extend the stride value.
+        SCEVHandle Start = AR->getStart();
+        SCEVHandle Step = AR->getStepRecurrence(*this);
+
+        // Check whether the backedge-taken count can be losslessly casted to
+        // the addrec's type. The count is always unsigned.
+        SCEVHandle CastedBECount =
+          getTruncateOrZeroExtend(BECount, Start->getType());
+        if (BECount ==
+            getTruncateOrZeroExtend(CastedBECount, BECount->getType())) {
+          const Type *WideTy =
+            IntegerType::get(getTypeSizeInBits(Start->getType()) * 2);
+          SCEVHandle SMul =
+            getMulExpr(CastedBECount,
+                       getTruncateOrSignExtend(Step, Start->getType()));
+          // Check whether Start+Step*BECount has no signed overflow.
+          if (getSignExtendExpr(SMul, WideTy) ==
+              getMulExpr(getSignExtendExpr(CastedBECount, WideTy),
+                         getSignExtendExpr(Step, WideTy))) {
+            SCEVHandle Add = getAddExpr(Start, SMul);
+            if (getSignExtendExpr(Add, WideTy) ==
+                getAddExpr(getSignExtendExpr(Start, WideTy),
+                           getSignExtendExpr(SMul, WideTy)))
+              // Return the expression with the addrec on the outside.
+              return getAddRecExpr(getSignExtendExpr(Start, Ty),
+                                   getSignExtendExpr(Step, Ty),
+                                   AR->getLoop());
+          }
+        }
+      }
+    }
 
   SCEVSignExtendExpr *&Result = (*SCEVSignExtends)[std::make_pair(Op, Ty)];
   if (Result == 0) Result = new SCEVSignExtendExpr(Op, Ty);
@@ -1962,20 +2070,36 @@
 /// hasLoopInvariantBackedgeTakenCount).
 ///
 SCEVHandle ScalarEvolution::getBackedgeTakenCount(const Loop *L) {
-  std::map<const Loop*, SCEVHandle>::iterator I = BackedgeTakenCounts.find(L);
-  if (I == BackedgeTakenCounts.end()) {
+  // Initially insert a CouldNotCompute for this loop. If the insertion
+  // succeeds, procede to actually compute a backedge-taken count and
+  // update the value. The temporary CouldNotCompute value tells SCEV
+  // code elsewhere that it shouldn't attempt to request a new
+  // backedge-taken count, which could result in infinite recursion.
+  std::pair<std::map<const Loop*, SCEVHandle>::iterator, bool> Pair =
+    BackedgeTakenCounts.insert(std::make_pair(L, getCouldNotCompute()));
+  if (Pair.second) {
     SCEVHandle ItCount = ComputeBackedgeTakenCount(L);
-    I = BackedgeTakenCounts.insert(std::make_pair(L, ItCount)).first;
     if (ItCount != UnknownValue) {
       assert(ItCount->isLoopInvariant(L) &&
              "Computed trip count isn't loop invariant for loop!");
       ++NumTripCountsComputed;
+
+      // Now that we know the trip count for this loop, forget any
+      // existing SCEV values for PHI nodes in this loop since they
+      // are only conservative estimates made without the benefit
+      // of trip count information.
+      for (BasicBlock::iterator I = L->getHeader()->begin();
+           PHINode *PN = dyn_cast<PHINode>(I); ++I)
+        deleteValueFromRecords(PN);
+
+      // Update the value in the map.
+      Pair.first->second = ItCount;
     } else if (isa<PHINode>(L->getHeader()->begin())) {
       // Only count loops that have phi nodes as not being computable.
       ++NumTripCountsNotComputed;
     }
   }
-  return I->second;
+  return Pair.first->second;
 }
 
 /// forgetLoopBackedgeTakenCount - This method should be called by the

Added: llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll?rev=70241&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll (added)
+++ llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll Mon Apr 27 15:16:15 2009
@@ -0,0 +1,244 @@
+; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: not grep and %t
+; RUN: not grep movz %t
+; RUN: not grep sar %t
+; RUN: not grep shl %t
+; RUN: grep add %t | count 6
+; RUN: grep inc %t | count 4
+; RUN: grep dec %t | count 2
+; RUN: grep lea %t | count 2
+
+; Optimize away zext-inreg and sext-inreg on the loop induction
+; variable using trip-count information.
+
+define void @count_up(double* %d, i64 %n) nounwind {
+entry:
+	br label %loop
+
+loop:
+	%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+	%indvar.i8 = and i64 %indvar, 255
+	%t0 = getelementptr double* %d, i64 %indvar.i8
+	%t1 = load double* %t0
+	%t2 = mul double %t1, 0.1
+	store double %t2, double* %t0
+	%indvar.i24 = and i64 %indvar, 16777215
+	%t3 = getelementptr double* %d, i64 %indvar.i24
+	%t4 = load double* %t3
+	%t5 = mul double %t4, 2.3
+	store double %t5, double* %t3
+	%t6 = getelementptr double* %d, i64 %indvar
+	%t7 = load double* %t6
+	%t8 = mul double %t7, 4.5
+	store double %t8, double* %t6
+	%indvar.next = add i64 %indvar, 1
+	%exitcond = icmp eq i64 %indvar.next, 10
+	br i1 %exitcond, label %return, label %loop
+
+return:
+	ret void
+}
+
+define void @count_down(double* %d, i64 %n) nounwind {
+entry:
+	br label %loop
+
+loop:
+	%indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+	%indvar.i8 = and i64 %indvar, 255
+	%t0 = getelementptr double* %d, i64 %indvar.i8
+	%t1 = load double* %t0
+	%t2 = mul double %t1, 0.1
+	store double %t2, double* %t0
+	%indvar.i24 = and i64 %indvar, 16777215
+	%t3 = getelementptr double* %d, i64 %indvar.i24
+	%t4 = load double* %t3
+	%t5 = mul double %t4, 2.3
+	store double %t5, double* %t3
+	%t6 = getelementptr double* %d, i64 %indvar
+	%t7 = load double* %t6
+	%t8 = mul double %t7, 4.5
+	store double %t8, double* %t6
+	%indvar.next = sub i64 %indvar, 1
+	%exitcond = icmp eq i64 %indvar.next, 0
+	br i1 %exitcond, label %return, label %loop
+
+return:
+	ret void
+}
+
+define void @count_up_signed(double* %d, i64 %n) nounwind {
+entry:
+	br label %loop
+
+loop:
+	%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+        %s0 = shl i64 %indvar, 8
+	%indvar.i8 = ashr i64 %s0, 8
+	%t0 = getelementptr double* %d, i64 %indvar.i8
+	%t1 = load double* %t0
+	%t2 = mul double %t1, 0.1
+	store double %t2, double* %t0
+	%s1 = shl i64 %indvar, 24
+	%indvar.i24 = ashr i64 %s1, 24
+	%t3 = getelementptr double* %d, i64 %indvar.i24
+	%t4 = load double* %t3
+	%t5 = mul double %t4, 2.3
+	store double %t5, double* %t3
+	%t6 = getelementptr double* %d, i64 %indvar
+	%t7 = load double* %t6
+	%t8 = mul double %t7, 4.5
+	store double %t8, double* %t6
+	%indvar.next = add i64 %indvar, 1
+	%exitcond = icmp eq i64 %indvar.next, 10
+	br i1 %exitcond, label %return, label %loop
+
+return:
+	ret void
+}
+
+define void @count_down_signed(double* %d, i64 %n) nounwind {
+entry:
+	br label %loop
+
+loop:
+	%indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+        %s0 = shl i64 %indvar, 8
+	%indvar.i8 = ashr i64 %s0, 8
+	%t0 = getelementptr double* %d, i64 %indvar.i8
+	%t1 = load double* %t0
+	%t2 = mul double %t1, 0.1
+	store double %t2, double* %t0
+	%s1 = shl i64 %indvar, 24
+	%indvar.i24 = ashr i64 %s1, 24
+	%t3 = getelementptr double* %d, i64 %indvar.i24
+	%t4 = load double* %t3
+	%t5 = mul double %t4, 2.3
+	store double %t5, double* %t3
+	%t6 = getelementptr double* %d, i64 %indvar
+	%t7 = load double* %t6
+	%t8 = mul double %t7, 4.5
+	store double %t8, double* %t6
+	%indvar.next = sub i64 %indvar, 1
+	%exitcond = icmp eq i64 %indvar.next, 0
+	br i1 %exitcond, label %return, label %loop
+
+return:
+	ret void
+}
+
+define void @another_count_up(double* %d, i64 %n) nounwind {
+entry:
+	br label %loop
+
+loop:
+	%indvar = phi i64 [ 18446744073709551615, %entry ], [ %indvar.next, %loop ]
+	%indvar.i8 = and i64 %indvar, 255
+	%t0 = getelementptr double* %d, i64 %indvar.i8
+	%t1 = load double* %t0
+	%t2 = mul double %t1, 0.1
+	store double %t2, double* %t0
+	%indvar.i24 = and i64 %indvar, 16777215
+	%t3 = getelementptr double* %d, i64 %indvar.i24
+	%t4 = load double* %t3
+	%t5 = mul double %t4, 2.3
+	store double %t5, double* %t3
+	%t6 = getelementptr double* %d, i64 %indvar
+	%t7 = load double* %t6
+	%t8 = mul double %t7, 4.5
+	store double %t8, double* %t6
+	%indvar.next = add i64 %indvar, 1
+	%exitcond = icmp eq i64 %indvar.next, 0
+	br i1 %exitcond, label %return, label %loop
+
+return:
+	ret void
+}
+
+define void @another_count_down(double* %d, i64 %n) nounwind {
+entry:
+	br label %loop
+
+loop:
+	%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+	%indvar.i8 = and i64 %indvar, 255
+	%t0 = getelementptr double* %d, i64 %indvar.i8
+	%t1 = load double* %t0
+	%t2 = mul double %t1, 0.1
+	store double %t2, double* %t0
+	%indvar.i24 = and i64 %indvar, 16777215
+	%t3 = getelementptr double* %d, i64 %indvar.i24
+	%t4 = load double* %t3
+	%t5 = mul double %t4, 2.3
+	store double %t5, double* %t3
+	%t6 = getelementptr double* %d, i64 %indvar
+	%t7 = load double* %t6
+	%t8 = mul double %t7, 4.5
+	store double %t8, double* %t6
+	%indvar.next = sub i64 %indvar, 1
+	%exitcond = icmp eq i64 %indvar.next, 18446744073709551615
+	br i1 %exitcond, label %return, label %loop
+
+return:
+	ret void
+}
+
+define void @another_count_up_signed(double* %d, i64 %n) nounwind {
+entry:
+	br label %loop
+
+loop:
+	%indvar = phi i64 [ 18446744073709551615, %entry ], [ %indvar.next, %loop ]
+        %s0 = shl i64 %indvar, 8
+	%indvar.i8 = ashr i64 %s0, 8
+	%t0 = getelementptr double* %d, i64 %indvar.i8
+	%t1 = load double* %t0
+	%t2 = mul double %t1, 0.1
+	store double %t2, double* %t0
+	%s1 = shl i64 %indvar, 24
+	%indvar.i24 = ashr i64 %s1, 24
+	%t3 = getelementptr double* %d, i64 %indvar.i24
+	%t4 = load double* %t3
+	%t5 = mul double %t4, 2.3
+	store double %t5, double* %t3
+	%t6 = getelementptr double* %d, i64 %indvar
+	%t7 = load double* %t6
+	%t8 = mul double %t7, 4.5
+	store double %t8, double* %t6
+	%indvar.next = add i64 %indvar, 1
+	%exitcond = icmp eq i64 %indvar.next, 0
+	br i1 %exitcond, label %return, label %loop
+
+return:
+	ret void
+}
+
+define void @another_count_down_signed(double* %d, i64 %n) nounwind {
+entry:
+	br label %loop
+
+loop:
+	%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+        %s0 = shl i64 %indvar, 8
+	%indvar.i8 = ashr i64 %s0, 8
+	%t0 = getelementptr double* %d, i64 %indvar.i8
+	%t1 = load double* %t0
+	%t2 = mul double %t1, 0.1
+	store double %t2, double* %t0
+	%s1 = shl i64 %indvar, 24
+	%indvar.i24 = ashr i64 %s1, 24
+	%t3 = getelementptr double* %d, i64 %indvar.i24
+	%t4 = load double* %t3
+	%t5 = mul double %t4, 2.3
+	store double %t5, double* %t3
+	%t6 = getelementptr double* %d, i64 %indvar
+	%t7 = load double* %t6
+	%t8 = mul double %t7, 4.5
+	store double %t8, double* %t6
+	%indvar.next = sub i64 %indvar, 1
+	%exitcond = icmp eq i64 %indvar.next, 18446744073709551615
+	br i1 %exitcond, label %return, label %loop
+
+return:
+	ret void
+}

Added: llvm/trunk/test/CodeGen/X86/masked-iv-unsafe.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/masked-iv-unsafe.ll?rev=70241&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/masked-iv-unsafe.ll (added)
+++ llvm/trunk/test/CodeGen/X86/masked-iv-unsafe.ll Mon Apr 27 15:16:15 2009
@@ -0,0 +1,386 @@
+; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: grep and %t | count 6
+; RUN: grep movzb %t | count 6
+; RUN: grep sar %t | count 12
+
+; Don't optimize away zext-inreg and sext-inreg on the loop induction
+; variable, because it isn't safe to do so in these cases.
+
+define void @count_up(double* %d, i64 %n) nounwind {
+entry:
+	br label %loop
+
+loop:
+	%indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+	%indvar.i8 = and i64 %indvar, 255
+	%t0 = getelementptr double* %d, i64 %indvar.i8
+	%t1 = load double* %t0
+	%t2 = mul double %t1, 0.1
+	store double %t2, double* %t0
+	%indvar.i24 = and i64 %indvar, 16777215
+	%t3 = getelementptr double* %d, i64 %indvar.i24
+	%t4 = load double* %t3
+	%t5 = mul double %t4, 2.3
+	store double %t5, double* %t3
+	%t6 = getelementptr double* %d, i64 %indvar
+	%t7 = load double* %t6
+	%t8 = mul double %t7, 4.5
+	store double %t8, double* %t6
+	%indvar.next = add i64 %indvar, 1
+	%exitcond = icmp eq i64 %indvar.next, 0
+	br i1 %exitcond, label %return, label %loop
+
+return:
+	ret void
+}
+
+define void @count_down(double* %d, i64 %n) nounwind {
+entry:
+	br label %loop
+
+loop:
+	%indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+	%indvar.i8 = and i64 %indvar, 255
+	%t0 = getelementptr double* %d, i64 %indvar.i8
+	%t1 = load double* %t0
+	%t2 = mul double %t1, 0.1
+	store double %t2, double* %t0
+	%indvar.i24 = and i64 %indvar, 16777215
+	%t3 = getelementptr double* %d, i64 %indvar.i24
+	%t4 = load double* %t3
+	%t5 = mul double %t4, 2.3
+	store double %t5, double* %t3
+	%t6 = getelementptr double* %d, i64 %indvar
+	%t7 = load double* %t6
+	%t8 = mul double %t7, 4.5
+	store double %t8, double* %t6
+	%indvar.next = sub i64 %indvar, 1
+	%exitcond = icmp eq i64 %indvar.next, 20
+	br i1 %exitcond, label %return, label %loop
+
+return:
+	ret void
+}
+
+define void @count_up_signed(double* %d, i64 %n) nounwind {
+entry:
+	br label %loop
+
+loop:
+	%indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+        %s0 = shl i64 %indvar, 8
+	%indvar.i8 = ashr i64 %s0, 8
+	%t0 = getelementptr double* %d, i64 %indvar.i8
+	%t1 = load double* %t0
+	%t2 = mul double %t1, 0.1
+	store double %t2, double* %t0
+	%s1 = shl i64 %indvar, 24
+	%indvar.i24 = ashr i64 %s1, 24
+	%t3 = getelementptr double* %d, i64 %indvar.i24
+	%t4 = load double* %t3
+	%t5 = mul double %t4, 2.3
+	store double %t5, double* %t3
+	%t6 = getelementptr double* %d, i64 %indvar
+	%t7 = load double* %t6
+	%t8 = mul double %t7, 4.5
+	store double %t8, double* %t6
+	%indvar.next = add i64 %indvar, 1
+	%exitcond = icmp eq i64 %indvar.next, 0
+	br i1 %exitcond, label %return, label %loop
+
+return:
+	ret void
+}
+
+define void @count_down_signed(double* %d, i64 %n) nounwind {
+entry:
+	br label %loop
+
+loop:
+	%indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+        %s0 = shl i64 %indvar, 8
+	%indvar.i8 = ashr i64 %s0, 8
+	%t0 = getelementptr double* %d, i64 %indvar.i8
+	%t1 = load double* %t0
+	%t2 = mul double %t1, 0.1
+	store double %t2, double* %t0
+	%s1 = shl i64 %indvar, 24
+	%indvar.i24 = ashr i64 %s1, 24
+	%t3 = getelementptr double* %d, i64 %indvar.i24
+	%t4 = load double* %t3
+	%t5 = mul double %t4, 2.3
+	store double %t5, double* %t3
+	%t6 = getelementptr double* %d, i64 %indvar
+	%t7 = load double* %t6
+	%t8 = mul double %t7, 4.5
+	store double %t8, double* %t6
+	%indvar.next = sub i64 %indvar, 1
+	%exitcond = icmp eq i64 %indvar.next, 20
+	br i1 %exitcond, label %return, label %loop
+
+return:
+	ret void
+}
+
+define void @another_count_up(double* %d, i64 %n) nounwind {
+entry:
+        br label %loop
+
+loop:
+        %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+        %indvar.i8 = and i64 %indvar, 255
+        %t0 = getelementptr double* %d, i64 %indvar.i8
+        %t1 = load double* %t0
+        %t2 = mul double %t1, 0.1
+        store double %t2, double* %t0
+        %indvar.i24 = and i64 %indvar, 16777215
+        %t3 = getelementptr double* %d, i64 %indvar.i24
+        %t4 = load double* %t3
+        %t5 = mul double %t4, 2.3
+        store double %t5, double* %t3
+        %t6 = getelementptr double* %d, i64 %indvar
+        %t7 = load double* %t6
+        %t8 = mul double %t7, 4.5
+        store double %t8, double* %t6
+        %indvar.next = add i64 %indvar, 1
+        %exitcond = icmp eq i64 %indvar.next, %n
+        br i1 %exitcond, label %return, label %loop
+
+return:
+        ret void
+}
+
+define void @another_count_down(double* %d, i64 %n) nounwind {
+entry:
+        br label %loop
+
+loop:
+        %indvar = phi i64 [ %n, %entry ], [ %indvar.next, %loop ]
+        %indvar.i8 = and i64 %indvar, 255
+        %t0 = getelementptr double* %d, i64 %indvar.i8
+        %t1 = load double* %t0
+        %t2 = mul double %t1, 0.1
+        store double %t2, double* %t0
+        %indvar.i24 = and i64 %indvar, 16777215
+        %t3 = getelementptr double* %d, i64 %indvar.i24
+        %t4 = load double* %t3
+        %t5 = mul double %t4, 2.3
+        store double %t5, double* %t3
+        %t6 = getelementptr double* %d, i64 %indvar
+        %t7 = load double* %t6
+        %t8 = mul double %t7, 4.5
+        store double %t8, double* %t6
+        %indvar.next = sub i64 %indvar, 1
+        %exitcond = icmp eq i64 %indvar.next, 10
+        br i1 %exitcond, label %return, label %loop
+
+return:
+        ret void
+}
+
+define void @another_count_up_signed(double* %d, i64 %n) nounwind {
+entry:
+        br label %loop
+
+loop:
+        %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+        %s0 = shl i64 %indvar, 8
+        %indvar.i8 = ashr i64 %s0, 8
+        %t0 = getelementptr double* %d, i64 %indvar.i8
+        %t1 = load double* %t0
+        %t2 = mul double %t1, 0.1
+        store double %t2, double* %t0
+        %s1 = shl i64 %indvar, 24
+        %indvar.i24 = ashr i64 %s1, 24
+        %t3 = getelementptr double* %d, i64 %indvar.i24
+        %t4 = load double* %t3
+        %t5 = mul double %t4, 2.3
+        store double %t5, double* %t3
+        %t6 = getelementptr double* %d, i64 %indvar
+        %t7 = load double* %t6
+        %t8 = mul double %t7, 4.5
+        store double %t8, double* %t6
+        %indvar.next = add i64 %indvar, 1
+        %exitcond = icmp eq i64 %indvar.next, %n
+        br i1 %exitcond, label %return, label %loop
+
+return:
+        ret void
+}
+
+define void @another_count_down_signed(double* %d, i64 %n) nounwind {
+entry:
+        br label %loop
+
+loop:
+        %indvar = phi i64 [ %n, %entry ], [ %indvar.next, %loop ]
+        %s0 = shl i64 %indvar, 8
+        %indvar.i8 = ashr i64 %s0, 8
+        %t0 = getelementptr double* %d, i64 %indvar.i8
+        %t1 = load double* %t0
+        %t2 = mul double %t1, 0.1
+        store double %t2, double* %t0
+        %s1 = shl i64 %indvar, 24
+        %indvar.i24 = ashr i64 %s1, 24
+        %t3 = getelementptr double* %d, i64 %indvar.i24
+        %t4 = load double* %t3
+        %t5 = mul double %t4, 2.3
+        store double %t5, double* %t3
+        %t6 = getelementptr double* %d, i64 %indvar
+        %t7 = load double* %t6
+        %t8 = mul double %t7, 4.5
+        store double %t8, double* %t6
+        %indvar.next = sub i64 %indvar, 1
+        %exitcond = icmp eq i64 %indvar.next, 10
+        br i1 %exitcond, label %return, label %loop
+
+return:
+        ret void
+}
+
+define void @yet_another_count_down(double* %d, i64 %n) nounwind {
+entry:
+	br label %loop
+
+loop:
+	%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+	%indvar.i8 = and i64 %indvar, 255
+	%t0 = getelementptr double* %d, i64 %indvar.i8
+	%t1 = load double* %t0
+	%t2 = mul double %t1, 0.1
+	store double %t2, double* %t0
+	%indvar.i24 = and i64 %indvar, 16777215
+	%t3 = getelementptr double* %d, i64 %indvar.i24
+	%t4 = load double* %t3
+	%t5 = mul double %t4, 2.3
+	store double %t5, double* %t3
+	%t6 = getelementptr double* %d, i64 %indvar
+	%t7 = load double* %t6
+	%t8 = mul double %t7, 4.5
+	store double %t8, double* %t6
+	%indvar.next = sub i64 %indvar, 1
+	%exitcond = icmp eq i64 %indvar.next, 18446744073709551615
+	br i1 %exitcond, label %return, label %loop
+
+return:
+	ret void
+}
+
+define void @yet_another_count_up(double* %d, i64 %n) nounwind {
+entry:
+        br label %loop
+
+loop:
+        %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+        %indvar.i8 = and i64 %indvar, 255
+        %t0 = getelementptr double* %d, i64 %indvar.i8
+        %t1 = load double* %t0
+        %t2 = mul double %t1, 0.1
+        store double %t2, double* %t0
+        %indvar.i24 = and i64 %indvar, 16777215
+        %t3 = getelementptr double* %d, i64 %indvar.i24
+        %t4 = load double* %t3
+        %t5 = mul double %t4, 2.3
+        store double %t5, double* %t3
+        %t6 = getelementptr double* %d, i64 %indvar
+        %t7 = load double* %t6
+        %t8 = mul double %t7, 4.5
+        store double %t8, double* %t6
+        %indvar.next = add i64 %indvar, 3
+        %exitcond = icmp eq i64 %indvar.next, 10
+        br i1 %exitcond, label %return, label %loop
+
+return:
+        ret void
+}
+
+define void @still_another_count_down(double* %d, i64 %n) nounwind {
+entry:
+        br label %loop
+
+loop:
+        %indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+        %indvar.i8 = and i64 %indvar, 255
+        %t0 = getelementptr double* %d, i64 %indvar.i8
+        %t1 = load double* %t0
+        %t2 = mul double %t1, 0.1
+        store double %t2, double* %t0
+        %indvar.i24 = and i64 %indvar, 16777215
+        %t3 = getelementptr double* %d, i64 %indvar.i24
+        %t4 = load double* %t3
+        %t5 = mul double %t4, 2.3
+        store double %t5, double* %t3
+        %t6 = getelementptr double* %d, i64 %indvar
+        %t7 = load double* %t6
+        %t8 = mul double %t7, 4.5
+        store double %t8, double* %t6
+        %indvar.next = sub i64 %indvar, 3
+        %exitcond = icmp eq i64 %indvar.next, 0
+        br i1 %exitcond, label %return, label %loop
+
+return:
+        ret void
+}
+
+define void @yet_another_count_up_signed(double* %d, i64 %n) nounwind {
+entry:
+        br label %loop
+
+loop:
+        %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+        %s0 = shl i64 %indvar, 8
+        %indvar.i8 = ashr i64 %s0, 8
+        %t0 = getelementptr double* %d, i64 %indvar.i8
+        %t1 = load double* %t0
+        %t2 = mul double %t1, 0.1
+        store double %t2, double* %t0
+        %s1 = shl i64 %indvar, 24
+        %indvar.i24 = ashr i64 %s1, 24
+        %t3 = getelementptr double* %d, i64 %indvar.i24
+        %t4 = load double* %t3
+        %t5 = mul double %t4, 2.3
+        store double %t5, double* %t3
+        %t6 = getelementptr double* %d, i64 %indvar
+        %t7 = load double* %t6
+        %t8 = mul double %t7, 4.5
+        store double %t8, double* %t6
+        %indvar.next = add i64 %indvar, 3
+        %exitcond = icmp eq i64 %indvar.next, 10
+        br i1 %exitcond, label %return, label %loop
+
+return:
+        ret void
+}
+
+define void @yet_another_count_down_signed(double* %d, i64 %n) nounwind {
+entry:
+        br label %loop
+
+loop:
+        %indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+        %s0 = shl i64 %indvar, 8
+        %indvar.i8 = ashr i64 %s0, 8
+        %t0 = getelementptr double* %d, i64 %indvar.i8
+        %t1 = load double* %t0
+        %t2 = mul double %t1, 0.1
+        store double %t2, double* %t0
+        %s1 = shl i64 %indvar, 24
+        %indvar.i24 = ashr i64 %s1, 24
+        %t3 = getelementptr double* %d, i64 %indvar.i24
+        %t4 = load double* %t3
+        %t5 = mul double %t4, 2.3
+        store double %t5, double* %t3
+        %t6 = getelementptr double* %d, i64 %indvar
+        %t7 = load double* %t6
+        %t8 = mul double %t7, 4.5
+        store double %t8, double* %t6
+        %indvar.next = sub i64 %indvar, 3
+        %exitcond = icmp eq i64 %indvar.next, 0
+        br i1 %exitcond, label %return, label %loop
+
+return:
+        ret void
+}
+
+
+

Modified: llvm/trunk/test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-1.ll?rev=70241&r1=70240&r2=70241&view=diff

==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-1.ll (original)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-1.ll Mon Apr 27 15:16:15 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc --x86-asm-syntax=att | grep {cmpl	\$8}
+; RUN: llvm-as < %s | llc --x86-asm-syntax=att | grep {cmpq	\$8}
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-apple-darwin9"
 
@@ -6,7 +6,7 @@
 ; happens after the relevant use, so the comparison stride can be
 ; easily changed.
 
-define void @foo() {
+define void @foo() nounwind {
 entry:
 	br label %loop
 
@@ -14,9 +14,11 @@
 	%indvar = phi i32 [ 0, %entry ], [ %i.2.0.us1534, %loop ]		; <i32> [#uses=1]
 	%i.2.0.us1534 = add i32 %indvar, 1		; <i32> [#uses=3]
 	%tmp628.us1540 = shl i32 %i.2.0.us1534, 1		; <i32> [#uses=1]
-	%tmp645646647.us1547 = sext i32 %tmp628.us1540 to i64		; <i64> [#uses=0]
+	%tmp645646647.us1547 = sext i32 %tmp628.us1540 to i64		; <i64> [#uses=1]
+	store i64 %tmp645646647.us1547, i64* null
 	%tmp611.us1535 = icmp eq i32 %i.2.0.us1534, 4		; <i1> [#uses=2]
-	%tmp623.us1538 = select i1 %tmp611.us1535, i32 6, i32 0		; <i32> [#uses=0]
+	%tmp623.us1538 = select i1 %tmp611.us1535, i32 6, i32 0		; <i32> [#uses=1]
+	store i32 %tmp623.us1538, i32* null
 	br i1 %tmp611.us1535, label %exit, label %loop
 
 exit:




From evan.cheng at apple.com  Mon Apr 27 15:17:30 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Apr 2009 13:17:30 -0700
Subject: [llvm-commits] [PATCH] Prevent illegal joins of physical
	and	virtual registers
In-Reply-To: <E168324F-D0A8-4711-8D01-641C48E146E0@2pi.dk>
References: <E168324F-D0A8-4711-8D01-641C48E146E0@2pi.dk>
Message-ID: <BBAEC134-C1DB-43CB-B311-B7C5EF1173DD@apple.com>

Looks good. Please commit.

Thanks,

Evan

On Apr 26, 2009, at 8:21 AM, Jakob Stoklund Olesen wrote:

> This is my second attempt at verifying register classes when  
> coalescing physical and virtual registers. The first attempt  
> completely missed the issue of subregisters being joined.
>
> I have attached two patches:
>
> targetregclass.patch: Change the static function  
> getSubRegisterRegClass in ScheduleDagSDNodesEmit.cpp to a method on  
> TargetRegisterClass. The method is needed by the next patch.
>
> coalesce-phys-virt.patch: Verify register classes when joining  
> physical and virtual registers. This time take into account all the  
> weird subreg combinations that are possible.
>
> Please note that this patch causes a number of failures in the  
> CodeGen/X86 test suite. That is because X86RegisterInfo.td contains  
> inconsistent information about subregister classes. I am submitting  
> a patch to the X86 backend that fixes this.
>
> With the X86 patch, this patch passes "make check".
>
> <coalesce-phys-virt.patch><targetregclass- 
> subreg.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From jyasskin at google.com  Mon Apr 27 15:32:07 2009
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Mon, 27 Apr 2009 20:32:07 -0000
Subject: [llvm-commits] [llvm] r70243 - in /llvm/trunk:
 include/llvm/Support/ValueHandle.h unittests/Support/ValueHandleTest.cpp
Message-ID: <200904272032.n3RKW8tn019785@zion.cs.uiuc.edu>

Author: jyasskin
Date: Mon Apr 27 15:32:07 2009
New Revision: 70243

URL: http://llvm.org/viewvc/llvm-project?rev=70243&view=rev
Log:
Add tests for WeakVH and AssertingVH.  These pointed out that the overloads for
the comparison operators were not only unnecessary in the presence of the
implicit conversion; they caused ambiguous overload errors. So I deleted them.

Added:
    llvm/trunk/unittests/Support/ValueHandleTest.cpp
Modified:
    llvm/trunk/include/llvm/Support/ValueHandle.h

Modified: llvm/trunk/include/llvm/Support/ValueHandle.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ValueHandle.h?rev=70243&r1=70242&r2=70243&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/ValueHandle.h (original)
+++ llvm/trunk/include/llvm/Support/ValueHandle.h Mon Apr 27 15:32:07 2009
@@ -39,7 +39,7 @@
 class ValueHandleBase {
   friend class Value;
 protected:
-  /// HandleBaseKind - This indicates what base class the handle actually is.
+  /// HandleBaseKind - This indicates what sub class the handle actually is.
   /// This is to avoid having a vtable for the light-weight handle pointers. The
   /// fully generally Callback version does have a vtable.
   enum HandleBaseKind {
@@ -87,20 +87,7 @@
   
   Value *operator->() const { return getValPtr(); }
   Value &operator*() const { return *getValPtr(); }
-  
-  bool operator==(const Value *RHS) const { return VP == RHS; }
-  bool operator==(const ValueHandleBase &RHS) const { return VP == RHS.VP; }
-  bool operator!=(const Value *RHS) const { return VP != RHS; }
-  bool operator!=(const ValueHandleBase &RHS) const { return VP != RHS.VP; }
-  bool operator<(const Value *RHS) const { return VP < RHS; }
-  bool operator<(const ValueHandleBase &RHS) const { return VP < RHS.VP; }
-  bool operator>(const Value *RHS) const { return VP > RHS; }
-  bool operator>(const ValueHandleBase &RHS) const { return VP > RHS.VP; }
-  bool operator<=(const Value *RHS) const { return VP <= RHS; }
-  bool operator<=(const ValueHandleBase &RHS) const { return VP <= RHS.VP; }
-  bool operator>=(const Value *RHS) const { return VP >= RHS; }
-  bool operator>=(const ValueHandleBase &RHS) const { return VP >= RHS.VP; }
-  
+
 protected:
   Value *getValPtr() const { return VP; }
 private:
@@ -198,33 +185,6 @@
 
   ValueTy *operator->() const { return getValPtr(); }
   ValueTy &operator*() const { return *getValPtr(); }
-
-  // Duplicate these from the base class so that they work when assertions are
-  // off.
-  bool operator==(const Value *RHS) const { return getValPtr() == RHS; }
-  bool operator!=(const Value *RHS) const { return getValPtr() != RHS; }
-  bool operator<(const Value *RHS) const { return getValPtr() < RHS; }
-  bool operator>(const Value *RHS) const { return getValPtr() > RHS; }
-  bool operator<=(const Value *RHS) const { return getValPtr() <= RHS; }
-  bool operator>=(const Value *RHS) const { return getValPtr() >= RHS; }
-  bool operator==(const AssertingVH &RHS) const {
-    return getValPtr() == RHS.getValPtr();
-  }
-  bool operator!=(const AssertingVH &RHS) const {
-    return getValPtr() != RHS.getValPtr();
-  }
-  bool operator<(const AssertingVH &RHS) const {
-    return getValPtr() < RHS.getValPtr();
-  }
-  bool operator>(const AssertingVH &RHS) const {
-    return getValPtr() > RHS.getValPtr();
-  }
-  bool operator<=(const AssertingVH &RHS) const {
-    return getValPtr() <= RHS.getValPtr();
-  }
-  bool operator>=(const AssertingVH &RHS) const {
-    return getValPtr() >= RHS.getValPtr();
-  }
 };
 
 } // End llvm namespace

Added: llvm/trunk/unittests/Support/ValueHandleTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/ValueHandleTest.cpp?rev=70243&view=auto

==============================================================================
--- llvm/trunk/unittests/Support/ValueHandleTest.cpp (added)
+++ llvm/trunk/unittests/Support/ValueHandleTest.cpp Mon Apr 27 15:32:07 2009
@@ -0,0 +1,181 @@
+//===- llvm/unittest/Support/ValueHandleTest.cpp - ValueHandle tests --------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/ValueHandle.h"
+
+#include "llvm/Constants.h"
+#include "llvm/Instructions.h"
+
+#include "gtest/gtest.h"
+
+#include <memory>
+
+using namespace llvm;
+
+namespace {
+
+class ValueHandle : public testing::Test {
+protected:
+  Constant *ConstantV;
+  std::auto_ptr<BitCastInst> BitcastV;
+
+  ValueHandle() : ConstantV(ConstantInt::get(Type::Int32Ty, 0)),
+                  BitcastV(new BitCastInst(ConstantV, Type::Int32Ty)) {
+  }
+};
+
+TEST_F(ValueHandle, WeakVH_BasicOperation) {
+  WeakVH WVH(BitcastV.get());
+  EXPECT_EQ(BitcastV.get(), WVH);
+  WVH = ConstantV;
+  EXPECT_EQ(ConstantV, WVH);
+
+  // Make sure I can call a method on the underlying Value.  It
+  // doesn't matter which method.
+  EXPECT_EQ(Type::Int32Ty, WVH->getType());
+  EXPECT_EQ(Type::Int32Ty, (*WVH).getType());
+}
+
+TEST_F(ValueHandle, WeakVH_Comparisons) {
+  WeakVH BitcastWVH(BitcastV.get());
+  WeakVH ConstantWVH(ConstantV);
+
+  EXPECT_TRUE(BitcastWVH == BitcastWVH);
+  EXPECT_TRUE(BitcastV.get() == BitcastWVH);
+  EXPECT_TRUE(BitcastWVH == BitcastV.get());
+  EXPECT_FALSE(BitcastWVH == ConstantWVH);
+
+  EXPECT_TRUE(BitcastWVH != ConstantWVH);
+  EXPECT_TRUE(BitcastV.get() != ConstantWVH);
+  EXPECT_TRUE(BitcastWVH != ConstantV);
+  EXPECT_FALSE(BitcastWVH != BitcastWVH);
+
+  // Cast to Value* so comparisons work.
+  Value *BV = BitcastV.get();
+  Value *CV = ConstantV;
+  EXPECT_EQ(BV < CV, BitcastWVH < ConstantWVH);
+  EXPECT_EQ(BV <= CV, BitcastWVH <= ConstantWVH);
+  EXPECT_EQ(BV > CV, BitcastWVH > ConstantWVH);
+  EXPECT_EQ(BV >= CV, BitcastWVH >= ConstantWVH);
+
+  EXPECT_EQ(BV < CV, BitcastV.get() < ConstantWVH);
+  EXPECT_EQ(BV <= CV, BitcastV.get() <= ConstantWVH);
+  EXPECT_EQ(BV > CV, BitcastV.get() > ConstantWVH);
+  EXPECT_EQ(BV >= CV, BitcastV.get() >= ConstantWVH);
+
+  EXPECT_EQ(BV < CV, BitcastWVH < ConstantV);
+  EXPECT_EQ(BV <= CV, BitcastWVH <= ConstantV);
+  EXPECT_EQ(BV > CV, BitcastWVH > ConstantV);
+  EXPECT_EQ(BV >= CV, BitcastWVH >= ConstantV);
+}
+
+TEST_F(ValueHandle, WeakVH_FollowsRAUW) {
+  WeakVH WVH(BitcastV.get());
+  WeakVH WVH_Copy(WVH);
+  WeakVH WVH_Recreated(BitcastV.get());
+  BitcastV->replaceAllUsesWith(ConstantV);
+  EXPECT_EQ(ConstantV, WVH);
+  EXPECT_EQ(ConstantV, WVH_Copy);
+  EXPECT_EQ(ConstantV, WVH_Recreated);
+}
+
+TEST_F(ValueHandle, WeakVH_NullOnDeletion) {
+  WeakVH WVH(BitcastV.get());
+  WeakVH WVH_Copy(WVH);
+  WeakVH WVH_Recreated(BitcastV.get());
+  BitcastV.reset();
+  Value *null_value = NULL;
+  EXPECT_EQ(null_value, WVH);
+  EXPECT_EQ(null_value, WVH_Copy);
+  EXPECT_EQ(null_value, WVH_Recreated);
+}
+
+
+TEST_F(ValueHandle, AssertingVH_BasicOperation) {
+  AssertingVH<CastInst> AVH(BitcastV.get());
+  CastInst *implicit_to_exact_type = AVH;
+  implicit_to_exact_type = implicit_to_exact_type;  // Avoid warning.
+
+  AssertingVH<Value> GenericAVH(BitcastV.get());
+  EXPECT_EQ(BitcastV.get(), GenericAVH);
+  GenericAVH = ConstantV;
+  EXPECT_EQ(ConstantV, GenericAVH);
+
+  // Make sure I can call a method on the underlying CastInst.  It
+  // doesn't matter which method.
+  EXPECT_FALSE(AVH->mayWriteToMemory());
+  EXPECT_FALSE((*AVH).mayWriteToMemory());
+}
+
+TEST_F(ValueHandle, AssertingVH_Comparisons) {
+  AssertingVH<Value> BitcastAVH(BitcastV.get());
+  AssertingVH<Value> ConstantAVH(ConstantV);
+
+  EXPECT_TRUE(BitcastAVH == BitcastAVH);
+  EXPECT_TRUE(BitcastV.get() == BitcastAVH);
+  EXPECT_TRUE(BitcastAVH == BitcastV.get());
+  EXPECT_FALSE(BitcastAVH == ConstantAVH);
+
+  EXPECT_TRUE(BitcastAVH != ConstantAVH);
+  EXPECT_TRUE(BitcastV.get() != ConstantAVH);
+  EXPECT_TRUE(BitcastAVH != ConstantV);
+  EXPECT_FALSE(BitcastAVH != BitcastAVH);
+
+  // Cast to Value* so comparisons work.
+  Value *BV = BitcastV.get();
+  Value *CV = ConstantV;
+  EXPECT_EQ(BV < CV, BitcastAVH < ConstantAVH);
+  EXPECT_EQ(BV <= CV, BitcastAVH <= ConstantAVH);
+  EXPECT_EQ(BV > CV, BitcastAVH > ConstantAVH);
+  EXPECT_EQ(BV >= CV, BitcastAVH >= ConstantAVH);
+
+  EXPECT_EQ(BV < CV, BitcastV.get() < ConstantAVH);
+  EXPECT_EQ(BV <= CV, BitcastV.get() <= ConstantAVH);
+  EXPECT_EQ(BV > CV, BitcastV.get() > ConstantAVH);
+  EXPECT_EQ(BV >= CV, BitcastV.get() >= ConstantAVH);
+
+  EXPECT_EQ(BV < CV, BitcastAVH < ConstantV);
+  EXPECT_EQ(BV <= CV, BitcastAVH <= ConstantV);
+  EXPECT_EQ(BV > CV, BitcastAVH > ConstantV);
+  EXPECT_EQ(BV >= CV, BitcastAVH >= ConstantV);
+}
+
+TEST_F(ValueHandle, AssertingVH_DoesNotFollowRAUW) {
+  AssertingVH<Value> AVH(BitcastV.get());
+  BitcastV->replaceAllUsesWith(ConstantV);
+  EXPECT_EQ(BitcastV.get(), AVH);
+}
+
+#ifdef NDEBUG
+
+TEST_F(ValueHandle, AssertingVH_ReducesToPointer) {
+  EXPECT_EQ(sizeof(CastInst *), sizeof(AssertingVH<CastInst>));
+}
+
+#else  // !NDEBUG
+
+#ifdef GTEST_HAS_DEATH_TEST
+
+TEST_F(ValueHandle, AssertingVH_Asserts) {
+  AssertingVH<Value> AVH(BitcastV.get());
+  EXPECT_DEATH({BitcastV.reset();},
+               "An asserting value handle still pointed to this value!");
+  AssertingVH<Value> Copy(AVH);
+  AVH = NULL;
+  EXPECT_DEATH({BitcastV.reset();},
+               "An asserting value handle still pointed to this value!");
+  Copy = NULL;
+  BitcastV.reset();
+}
+
+#endif  // GTEST_HAS_DEATH_TEST
+
+#endif  // NDEBUG
+
+}




From jyasskin at google.com  Mon Apr 27 15:33:54 2009
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Mon, 27 Apr 2009 13:33:54 -0700
Subject: [llvm-commits] Tests for WeakVH and AssertingVH
In-Reply-To: <19F86ABC-29C0-406C-A6A6-EC781E54887C@apple.com>
References: <bb55930e0904262131t2a3d25b8jca0b8ca7869ef994@mail.gmail.com>
	<19F86ABC-29C0-406C-A6A6-EC781E54887C@apple.com>
Message-ID: <bb55930e0904271333t463603cyf526fa3aac2243af@mail.gmail.com>

On Sun, Apr 26, 2009 at 9:36 PM, Chris Lattner <clattner at apple.com> wrote:
>
> On Apr 26, 2009, at 9:31 PM, Jeffrey Yasskin wrote:
>
>> In preparation for writing CallbackVH, I figured it'd be nice for
>> WeakVH and AssertingVH to have tests. These pointed out that the
>> overloads for the comparison operators were not only unnecessary in
>> the presence of the implicit conversion; they caused ambiguous
>> overload errors. So I deleted them.
>
> Looks good, please commit!

Thanks! Committed as r70243:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090427/076774.html.


From jyasskin at google.com  Mon Apr 27 15:35:07 2009
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Mon, 27 Apr 2009 13:35:07 -0700
Subject: [llvm-commits] TypeBuilder helper class
In-Reply-To: <C00C39E7-7CB2-4553-A6E9-F3E457F3F1D6@apple.com>
References: <bb55930e0904021137i3199acb6j3108bc4c2819d9c5@mail.gmail.com>
	<bb55930e0904090940o5686c16er9f8f87e9ca302ed5@mail.gmail.com>
	<5F5A9B7F-1967-4D07-9D74-20466088C123@apple.com>
	<bb55930e0904121716j19c85efdxbadff2f727315df4@mail.gmail.com>
	<C00C39E7-7CB2-4553-A6E9-F3E457F3F1D6@apple.com>
Message-ID: <bb55930e0904271335s72903cd6reddea56beb20070e@mail.gmail.com>

On Sat, Apr 25, 2009 at 3:15 PM, Chris Lattner <clattner at apple.com> wrote:
>
> On Apr 12, 2009, at 5:16 PM, Jeffrey Yasskin wrote:
>
>> On Thu, Apr 9, 2009 at 11:38 PM, Chris Lattner <clattner at apple.com>
>> wrote:
>>>
>>> On Apr 9, 2009, at 9:40 AM, Jeffrey Yasskin wrote:
>>>
>>>>
>>>> I think I see how to define TypeBuilder<typename T, bool
>>>> restrict_to_cross_compilable_types> so that TypeBuilder<size_t,
>>>> true>
>>>> fails to compile but TypeBuilder<sometype<64>, false> succeeds,
>>>> without duplicating code. Could you confirm that that's along the
>>>> lines of what you want implemented before I waste time implementing
>>>> it? Also, what's the right spelling for "sometype"? I'd vote for
>>>> llvm::types::i<N> or something similar.
>>>>
>>>
>>> Sounds great to me!
>>
>> Ok, here's the new version. I'm not entirely happy with using a bool
>> for this decision since it makes user code harder to read. I could use
>> an enum or distinct subtypes, but then I'd need names. "Host" seems to
>> work for the version that accepts types like 'size_t', but
>> "CrossCompilable" seems too long for the version that doesn't.
>> Thoughts?
>
> This looks great! ?Can you please add some mention of this to the
> programmer's manual?
> http://llvm.org/docs/ProgrammersManual.html
>
> Perhaps a "how to create types" entry in the "Helpful Hints for Common
> Operations" section.

Will do, probably on Wednesday.

> Applied here:
> http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090420/076704.html
>
> Thanks Jeffrey!



From gohman at apple.com  Mon Apr 27 15:35:33 2009
From: gohman at apple.com (Dan Gohman)
Date: Mon, 27 Apr 2009 20:35:33 -0000
Subject: [llvm-commits] [llvm] r70244 - in /llvm/trunk:
 lib/Transforms/Scalar/LoopStrengthReduce.cpp
 test/CodeGen/X86/change-compare-stride-0.ll
 test/CodeGen/X86/change-compare-stride-1.ll
Message-ID: <200904272035.n3RKZXPK019887@zion.cs.uiuc.edu>

Author: djg
Date: Mon Apr 27 15:35:32 2009
New Revision: 70244

URL: http://llvm.org/viewvc/llvm-project?rev=70244&view=rev
Log:
Permit ChangeCompareStride to rewrite a comparison when the factor
between the comparison's iv stride and the candidate stride is
exactly -1.

Added:
    llvm/trunk/test/CodeGen/X86/change-compare-stride-0.ll
    llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=70244&r1=70243&r2=70244&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Mon Apr 27 15:35:32 2009
@@ -2028,7 +2028,9 @@
       if (!isa<SCEVConstant>(SI->first))
         continue;
       int64_t SSInt = cast<SCEVConstant>(SI->first)->getValue()->getSExtValue();
-      if (abs(SSInt) <= abs(CmpSSInt) || (SSInt % CmpSSInt) != 0)
+      if (SSInt == CmpSSInt ||
+          abs(SSInt) < abs(CmpSSInt) ||
+          (SSInt % CmpSSInt) != 0)
         continue;
 
       Scale = SSInt / CmpSSInt;

Added: llvm/trunk/test/CodeGen/X86/change-compare-stride-0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/change-compare-stride-0.ll?rev=70244&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/change-compare-stride-0.ll (added)
+++ llvm/trunk/test/CodeGen/X86/change-compare-stride-0.ll Mon Apr 27 15:35:32 2009
@@ -0,0 +1,77 @@
+; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: grep {cmpl	\$4294966818,} %t
+; RUN: not grep inc %t
+; RUN: not grep {leal	1(} %t
+; RUN: not grep {leal	-1(} %t
+; RUN: grep dec %t | count 1
+
+define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind {
+bb4.thread:
+	br label %bb2.outer
+
+bb2.outer:		; preds = %bb4, %bb4.thread
+	%indvar18 = phi i32 [ 0, %bb4.thread ], [ %indvar.next28, %bb4 ]		; <i32> [#uses=3]
+	%tmp34 = mul i32 %indvar18, 65535		; <i32> [#uses=1]
+	%i.0.reg2mem.0.ph = add i32 %tmp34, 639		; <i32> [#uses=1]
+	%0 = and i32 %i.0.reg2mem.0.ph, 65535		; <i32> [#uses=1]
+	%1 = mul i32 %0, 480		; <i32> [#uses=1]
+	%tmp20 = mul i32 %indvar18, -478		; <i32> [#uses=1]
+	br label %bb2
+
+bb2:		; preds = %bb2, %bb2.outer
+	%indvar = phi i32 [ 0, %bb2.outer ], [ %indvar.next, %bb2 ]		; <i32> [#uses=3]
+	%ctg2 = getelementptr i8* %out, i32 %tmp20		; <i8*> [#uses=1]
+	%tmp21 = ptrtoint i8* %ctg2 to i32		; <i32> [#uses=1]
+	%tmp23 = sub i32 %tmp21, %indvar		; <i32> [#uses=1]
+	%out_addr.0.reg2mem.0 = inttoptr i32 %tmp23 to i8*		; <i8*> [#uses=1]
+	%tmp25 = mul i32 %indvar, 65535		; <i32> [#uses=1]
+	%j.0.reg2mem.0 = add i32 %tmp25, 479		; <i32> [#uses=1]
+	%2 = and i32 %j.0.reg2mem.0, 65535		; <i32> [#uses=1]
+	%3 = add i32 %1, %2		; <i32> [#uses=9]
+	%4 = add i32 %3, -481		; <i32> [#uses=1]
+	%5 = getelementptr i8* %in, i32 %4		; <i8*> [#uses=1]
+	%6 = load i8* %5, align 1		; <i8> [#uses=1]
+	%7 = add i32 %3, -480		; <i32> [#uses=1]
+	%8 = getelementptr i8* %in, i32 %7		; <i8*> [#uses=1]
+	%9 = load i8* %8, align 1		; <i8> [#uses=1]
+	%10 = add i32 %3, -479		; <i32> [#uses=1]
+	%11 = getelementptr i8* %in, i32 %10		; <i8*> [#uses=1]
+	%12 = load i8* %11, align 1		; <i8> [#uses=1]
+	%13 = add i32 %3, -1		; <i32> [#uses=1]
+	%14 = getelementptr i8* %in, i32 %13		; <i8*> [#uses=1]
+	%15 = load i8* %14, align 1		; <i8> [#uses=1]
+	%16 = getelementptr i8* %in, i32 %3		; <i8*> [#uses=1]
+	%17 = load i8* %16, align 1		; <i8> [#uses=1]
+	%18 = add i32 %3, 1		; <i32> [#uses=1]
+	%19 = getelementptr i8* %in, i32 %18		; <i8*> [#uses=1]
+	%20 = load i8* %19, align 1		; <i8> [#uses=1]
+	%21 = add i32 %3, 481		; <i32> [#uses=1]
+	%22 = getelementptr i8* %in, i32 %21		; <i8*> [#uses=1]
+	%23 = load i8* %22, align 1		; <i8> [#uses=1]
+	%24 = add i32 %3, 480		; <i32> [#uses=1]
+	%25 = getelementptr i8* %in, i32 %24		; <i8*> [#uses=1]
+	%26 = load i8* %25, align 1		; <i8> [#uses=1]
+	%27 = add i32 %3, 479		; <i32> [#uses=1]
+	%28 = getelementptr i8* %in, i32 %27		; <i8*> [#uses=1]
+	%29 = load i8* %28, align 1		; <i8> [#uses=1]
+	%30 = add i8 %9, %6		; <i8> [#uses=1]
+	%31 = add i8 %30, %12		; <i8> [#uses=1]
+	%32 = add i8 %31, %15		; <i8> [#uses=1]
+	%33 = add i8 %32, %17		; <i8> [#uses=1]
+	%34 = add i8 %33, %20		; <i8> [#uses=1]
+	%35 = add i8 %34, %23		; <i8> [#uses=1]
+	%36 = add i8 %35, %26		; <i8> [#uses=1]
+	%37 = add i8 %36, %29		; <i8> [#uses=1]
+	store i8 %37, i8* %out_addr.0.reg2mem.0, align 1
+	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=2]
+	%exitcond = icmp eq i32 %indvar.next, 478		; <i1> [#uses=1]
+	br i1 %exitcond, label %bb4, label %bb2
+
+bb4:		; preds = %bb2
+	%indvar.next28 = add i32 %indvar18, 1		; <i32> [#uses=2]
+	%exitcond29 = icmp eq i32 %indvar.next28, 638		; <i1> [#uses=1]
+	br i1 %exitcond29, label %return, label %bb2.outer
+
+return:		; preds = %bb4
+	ret void
+}

Added: llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll?rev=70244&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll (added)
+++ llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll Mon Apr 27 15:35:32 2009
@@ -0,0 +1,86 @@
+; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: grep {cmpq	\$-478,} %t
+; RUN: not grep inc %t
+; RUN: not grep {leal	1(} %t
+; RUN: not grep {leal	-1(} %t
+; RUN: grep dec %t | count 1
+
+define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind {
+bb4.thread:
+	br label %bb2.outer
+
+bb2.outer:		; preds = %bb4, %bb4.thread
+	%indvar19 = phi i64 [ 0, %bb4.thread ], [ %indvar.next29, %bb4 ]		; <i64> [#uses=3]
+	%indvar31 = trunc i64 %indvar19 to i16		; <i16> [#uses=1]
+	%i.0.reg2mem.0.ph = sub i16 639, %indvar31		; <i16> [#uses=1]
+	%0 = zext i16 %i.0.reg2mem.0.ph to i32		; <i32> [#uses=1]
+	%1 = mul i32 %0, 480		; <i32> [#uses=1]
+	%tmp21 = mul i64 %indvar19, -478		; <i64> [#uses=1]
+	br label %bb2
+
+bb2:		; preds = %bb2, %bb2.outer
+	%indvar = phi i64 [ 0, %bb2.outer ], [ %indvar.next, %bb2 ]		; <i64> [#uses=3]
+	%indvar16 = trunc i64 %indvar to i16		; <i16> [#uses=1]
+	%ctg2 = getelementptr i8* %out, i64 %tmp21		; <i8*> [#uses=1]
+	%tmp22 = ptrtoint i8* %ctg2 to i64		; <i64> [#uses=1]
+	%tmp24 = sub i64 %tmp22, %indvar		; <i64> [#uses=1]
+	%out_addr.0.reg2mem.0 = inttoptr i64 %tmp24 to i8*		; <i8*> [#uses=1]
+	%j.0.reg2mem.0 = sub i16 479, %indvar16		; <i16> [#uses=1]
+	%2 = zext i16 %j.0.reg2mem.0 to i32		; <i32> [#uses=1]
+	%3 = add i32 %1, %2		; <i32> [#uses=9]
+	%4 = add i32 %3, -481		; <i32> [#uses=1]
+	%5 = zext i32 %4 to i64		; <i64> [#uses=1]
+	%6 = getelementptr i8* %in, i64 %5		; <i8*> [#uses=1]
+	%7 = load i8* %6, align 1		; <i8> [#uses=1]
+	%8 = add i32 %3, -480		; <i32> [#uses=1]
+	%9 = zext i32 %8 to i64		; <i64> [#uses=1]
+	%10 = getelementptr i8* %in, i64 %9		; <i8*> [#uses=1]
+	%11 = load i8* %10, align 1		; <i8> [#uses=1]
+	%12 = add i32 %3, -479		; <i32> [#uses=1]
+	%13 = zext i32 %12 to i64		; <i64> [#uses=1]
+	%14 = getelementptr i8* %in, i64 %13		; <i8*> [#uses=1]
+	%15 = load i8* %14, align 1		; <i8> [#uses=1]
+	%16 = add i32 %3, -1		; <i32> [#uses=1]
+	%17 = zext i32 %16 to i64		; <i64> [#uses=1]
+	%18 = getelementptr i8* %in, i64 %17		; <i8*> [#uses=1]
+	%19 = load i8* %18, align 1		; <i8> [#uses=1]
+	%20 = zext i32 %3 to i64		; <i64> [#uses=1]
+	%21 = getelementptr i8* %in, i64 %20		; <i8*> [#uses=1]
+	%22 = load i8* %21, align 1		; <i8> [#uses=1]
+	%23 = add i32 %3, 1		; <i32> [#uses=1]
+	%24 = zext i32 %23 to i64		; <i64> [#uses=1]
+	%25 = getelementptr i8* %in, i64 %24		; <i8*> [#uses=1]
+	%26 = load i8* %25, align 1		; <i8> [#uses=1]
+	%27 = add i32 %3, 481		; <i32> [#uses=1]
+	%28 = zext i32 %27 to i64		; <i64> [#uses=1]
+	%29 = getelementptr i8* %in, i64 %28		; <i8*> [#uses=1]
+	%30 = load i8* %29, align 1		; <i8> [#uses=1]
+	%31 = add i32 %3, 480		; <i32> [#uses=1]
+	%32 = zext i32 %31 to i64		; <i64> [#uses=1]
+	%33 = getelementptr i8* %in, i64 %32		; <i8*> [#uses=1]
+	%34 = load i8* %33, align 1		; <i8> [#uses=1]
+	%35 = add i32 %3, 479		; <i32> [#uses=1]
+	%36 = zext i32 %35 to i64		; <i64> [#uses=1]
+	%37 = getelementptr i8* %in, i64 %36		; <i8*> [#uses=1]
+	%38 = load i8* %37, align 1		; <i8> [#uses=1]
+	%39 = add i8 %11, %7		; <i8> [#uses=1]
+	%40 = add i8 %39, %15		; <i8> [#uses=1]
+	%41 = add i8 %40, %19		; <i8> [#uses=1]
+	%42 = add i8 %41, %22		; <i8> [#uses=1]
+	%43 = add i8 %42, %26		; <i8> [#uses=1]
+	%44 = add i8 %43, %30		; <i8> [#uses=1]
+	%45 = add i8 %44, %34		; <i8> [#uses=1]
+	%46 = add i8 %45, %38		; <i8> [#uses=1]
+	store i8 %46, i8* %out_addr.0.reg2mem.0, align 1
+	%indvar.next = add i64 %indvar, 1		; <i64> [#uses=2]
+	%exitcond = icmp eq i64 %indvar.next, 478		; <i1> [#uses=1]
+	br i1 %exitcond, label %bb4, label %bb2
+
+bb4:		; preds = %bb2
+	%indvar.next29 = add i64 %indvar19, 1		; <i64> [#uses=2]
+	%exitcond30 = icmp eq i64 %indvar.next29, 638		; <i1> [#uses=1]
+	br i1 %exitcond30, label %return, label %bb2.outer
+
+return:		; preds = %bb4
+	ret void
+}




From evan.cheng at apple.com  Mon Apr 27 15:42:46 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Apr 2009 20:42:46 -0000
Subject: [llvm-commits] [llvm] r70245 - in /llvm/trunk:
 lib/CodeGen/LiveIntervalAnalysis.cpp
 test/CodeGen/X86/2009-04-27-LiveIntervalsBug.ll
Message-ID: <200904272042.n3RKgk0P020110@zion.cs.uiuc.edu>

Author: evancheng
Date: Mon Apr 27 15:42:46 2009
New Revision: 70245

URL: http://llvm.org/viewvc/llvm-project?rev=70245&view=rev
Log:
Fix PR4076. Correctly create live interval of physical register with two-address update.

Added:
    llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsBug.ll
Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=70245&r1=70244&r2=70245&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Mon Apr 27 15:42:46 2009
@@ -612,14 +612,24 @@
       DOUT << " killed";
       end = getUseIndex(baseIndex) + 1;
       goto exit;
-    } else if (mi->modifiesRegister(interval.reg, tri_)) {
-      // Another instruction redefines the register before it is ever read.
-      // Then the register is essentially dead at the instruction that defines
-      // it. Hence its interval is:
-      // [defSlot(def), defSlot(def)+1)
-      DOUT << " dead";
-      end = start + 1;
-      goto exit;
+    } else {
+      int DefIdx = mi->findRegisterDefOperandIdx(interval.reg, false, tri_);
+      if (DefIdx != -1) {
+        if (mi->isRegTiedToUseOperand(DefIdx)) {
+          // Two-address instruction.
+          end = getDefIndex(baseIndex);
+          if (mi->getOperand(DefIdx).isEarlyClobber())
+            end = getUseIndex(baseIndex);
+        } else {
+          // Another instruction redefines the register before it is ever read.
+          // Then the register is essentially dead at the instruction that defines
+          // it. Hence its interval is:
+          // [defSlot(def), defSlot(def)+1)
+          DOUT << " dead";
+          end = start + 1;
+        }
+        goto exit;
+      }
     }
     
     baseIndex += InstrSlots::NUM;
@@ -663,14 +673,14 @@
         MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG ||
         tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
       CopyMI = MI;
-    handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, 
+    handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
                               getOrCreateInterval(MO.getReg()), CopyMI);
     // Def of a register also defines its sub-registers.
     for (const unsigned* AS = tri_->getSubRegisters(MO.getReg()); *AS; ++AS)
       // If MI also modifies the sub-register explicitly, avoid processing it
       // more than once. Do not pass in TRI here so it checks for exact match.
       if (!MI->modifiesRegister(*AS))
-        handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, 
+        handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
                                   getOrCreateInterval(*AS), 0);
   }
 }

Added: llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsBug.ll?rev=70245&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsBug.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsBug.ll Mon Apr 27 15:42:46 2009
@@ -0,0 +1,165 @@
+; RUN: llvm-as < %s | llc -mtriple=i386-unknown-linux-gnu | grep cmpxchgl | not grep eax
+; PR4076
+
+	type { i8, i8, i8 }		; type %0
+	type { i32, i8** }		; type %1
+	type { %3* }		; type %2
+	type { %4 }		; type %3
+	type { %5 }		; type %4
+	type { %6, i32, %7 }		; type %5
+	type { i8* }		; type %6
+	type { i32, [12 x i8] }		; type %7
+	type { %9 }		; type %8
+	type { %10, %11*, i8 }		; type %9
+	type { %11* }		; type %10
+	type { i32, %6, i8*, %12, %13*, i8, i32, %28, %29, i32, %30, i32, i32, i32, i8*, i8*, i8, i8 }		; type %11
+	type { %13* }		; type %12
+	type { %14, i32, %13*, %21 }		; type %13
+	type { %15, %16 }		; type %14
+	type { i32 (...)** }		; type %15
+	type { %17, i8* (i32)*, void (i8*)*, i8 }		; type %16
+	type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %18 }		; type %17
+	type { %19* }		; type %18
+	type { i32, %20**, i32, %20**, i8** }		; type %19
+	type { i32 (...)**, i32 }		; type %20
+	type { %22, %25*, i8, i8, %17*, %26*, %27*, %27* }		; type %21
+	type { i32 (...)**, i32, i32, i32, i32, i32, %23*, %24, [8 x %24], i32, %24*, %18 }		; type %22
+	type { %23*, void (i32, %22*, i32)*, i32, i32 }		; type %23
+	type { i8*, i32 }		; type %24
+	type { i32 (...)**, %21 }		; type %25
+	type { %20, i32*, i8, i32*, i32*, i16*, i8, [256 x i8], [256 x i8], i8 }		; type %26
+	type { %20 }		; type %27
+	type { void (%9*)*, i32 }		; type %28
+	type { %15* }		; type %29
+	type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8* }		; type %30
+ at AtomicOps_Internalx86CPUFeatures = external global %0		; <%0*> [#uses=1]
+internal constant [19 x i8] c"xxxxxxxxxxxxxxxxxx\00"		; <[19 x i8]*>:0 [#uses=1]
+internal constant [47 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\00"		; <[47 x i8]*>:1 [#uses=1]
+
+define i8** @func6(i8 zeroext, i32, i32, %1*) nounwind {
+; <label>:4
+	%5 = alloca i32, align 4		; <i32*> [#uses=2]
+	%6 = alloca i32, align 4		; <i32*> [#uses=2]
+	%7 = alloca %2, align 8		; <%2*> [#uses=3]
+	%8 = alloca %8, align 8		; <%8*> [#uses=2]
+	br label %17
+
+; <label>:9		; preds = %17
+	%10 = getelementptr %1* %3, i32 %19, i32 0		; <i32*> [#uses=1]
+	%11 = load i32* %10, align 4		; <i32> [#uses=1]
+	%12 = icmp eq i32 %11, %2		; <i1> [#uses=1]
+	br i1 %12, label %13, label %16
+
+; <label>:13		; preds = %9
+	%14 = getelementptr %1* %3, i32 %19, i32 1		; <i8***> [#uses=1]
+	%15 = load i8*** %14, align 4		; <i8**> [#uses=1]
+	ret i8** %15
+
+; <label>:16		; preds = %9
+	%indvar.next13 = add i32 %18, 1		; <i32> [#uses=1]
+	br label %17
+
+; <label>:17		; preds = %16, %4
+	%18 = phi i32 [ 0, %4 ], [ %indvar.next13, %16 ]		; <i32> [#uses=2]
+	%19 = add i32 %18, %1		; <i32> [#uses=3]
+	%20 = icmp sgt i32 %19, 3		; <i1> [#uses=1]
+	br i1 %20, label %21, label %9
+
+; <label>:21		; preds = %17
+	call void @func5()
+	%22 = getelementptr %1* %3, i32 0, i32 0		; <i32*> [#uses=1]
+	%23 = load i32* %22, align 4		; <i32> [#uses=1]
+	%24 = icmp eq i32 %23, 0		; <i1> [#uses=1]
+	br i1 %24, label %._crit_edge, label %._crit_edge1
+
+._crit_edge1:		; preds = %._crit_edge1, %21
+	%25 = phi i32 [ 0, %21 ], [ %26, %._crit_edge1 ]		; <i32> [#uses=1]
+	%26 = add i32 %25, 1		; <i32> [#uses=4]
+	%27 = getelementptr %1* %3, i32 %26, i32 0		; <i32*> [#uses=1]
+	%28 = load i32* %27, align 4		; <i32> [#uses=1]
+	%29 = icmp ne i32 %28, 0		; <i1> [#uses=1]
+	%30 = icmp ne i32 %26, 4		; <i1> [#uses=1]
+	%31 = and i1 %29, %30		; <i1> [#uses=1]
+	br i1 %31, label %._crit_edge1, label %._crit_edge
+
+._crit_edge:		; preds = %._crit_edge1, %21
+	%32 = phi i32 [ 0, %21 ], [ %26, %._crit_edge1 ]		; <i32> [#uses=3]
+	%33 = call i8* @pthread_getspecific(i32 0) nounwind		; <i8*> [#uses=2]
+	%34 = icmp ne i8* %33, null		; <i1> [#uses=1]
+	%35 = icmp eq i8 %0, 0		; <i1> [#uses=1]
+	%36 = or i1 %34, %35		; <i1> [#uses=1]
+	br i1 %36, label %._crit_edge4, label %37
+
+; <label>:37		; preds = %._crit_edge
+	%38 = call i8* @func2(i32 2048)		; <i8*> [#uses=4]
+	call void @llvm.memset.i32(i8* %38, i8 0, i32 2048, i32 4)
+	%39 = call i32 @pthread_setspecific(i32 0, i8* %38) nounwind		; <i32> [#uses=2]
+	store i32 %39, i32* %5
+	store i32 0, i32* %6
+	%40 = icmp eq i32 %39, 0		; <i1> [#uses=1]
+	br i1 %40, label %41, label %43
+
+; <label>:41		; preds = %37
+	%42 = getelementptr %2* %7, i32 0, i32 0		; <%3**> [#uses=1]
+	store %3* null, %3** %42, align 8
+	br label %._crit_edge4
+
+; <label>:43		; preds = %37
+	%44 = call %3* @func1(i32* %5, i32* %6, i8* getelementptr ([47 x i8]* @1, i32 0, i32 0))		; <%3*> [#uses=2]
+	%45 = getelementptr %2* %7, i32 0, i32 0		; <%3**> [#uses=1]
+	store %3* %44, %3** %45, align 8
+	%46 = icmp eq %3* %44, null		; <i1> [#uses=1]
+	br i1 %46, label %._crit_edge4, label %47
+
+; <label>:47		; preds = %43
+	call void @func4(%8* %8, i8* getelementptr ([19 x i8]* @0, i32 0, i32 0), i32 165, %2* %7)
+	call void @func3(%8* %8) noreturn
+	unreachable
+
+._crit_edge4:		; preds = %43, %41, %._crit_edge
+	%48 = phi i8* [ %38, %41 ], [ %33, %._crit_edge ], [ %38, %43 ]		; <i8*> [#uses=2]
+	%49 = bitcast i8* %48 to i8**		; <i8**> [#uses=3]
+	%50 = icmp ne i8* %48, null		; <i1> [#uses=1]
+	%51 = icmp slt i32 %32, 4		; <i1> [#uses=1]
+	%52 = and i1 %50, %51		; <i1> [#uses=1]
+	br i1 %52, label %53, label %._crit_edge6
+
+; <label>:53		; preds = %._crit_edge4
+	%54 = getelementptr %1* %3, i32 %32, i32 0		; <i32*> [#uses=1]
+	%55 = call i32 asm sideeffect "lock; cmpxchgl $1,$2", "={ax},q,*m,0,~{dirflag},~{fpsr},~{flags},~{memory}"(i32 %2, i32* %54, i32 0) nounwind		; <i32> [#uses=1]
+	%56 = load i8* getelementptr (%0* @AtomicOps_Internalx86CPUFeatures, i32 0, i32 0), align 8		; <i8> [#uses=1]
+	%57 = icmp eq i8 %56, 0		; <i1> [#uses=1]
+	br i1 %57, label %._crit_edge7, label %58
+
+; <label>:58		; preds = %53
+	call void asm sideeffect "lfence", "~{dirflag},~{fpsr},~{flags},~{memory}"() nounwind
+	br label %._crit_edge7
+
+._crit_edge7:		; preds = %58, %53
+	%59 = icmp eq i32 %55, 0		; <i1> [#uses=1]
+	br i1 %59, label %60, label %._crit_edge6
+
+._crit_edge6:		; preds = %._crit_edge7, %._crit_edge4
+	ret i8** %49
+
+; <label>:60		; preds = %._crit_edge7
+	%61 = getelementptr %1* %3, i32 %32, i32 1		; <i8***> [#uses=1]
+	store i8** %49, i8*** %61, align 4
+	ret i8** %49
+}
+
+declare %3* @func1(i32* nocapture, i32* nocapture, i8*)
+
+declare void @func5()
+
+declare void @func4(%8*, i8*, i32, %2*)
+
+declare void @func3(%8*) noreturn
+
+declare i8* @pthread_getspecific(i32) nounwind
+
+declare i8* @func2(i32)
+
+declare void @llvm.memset.i32(i8* nocapture, i8, i32, i32) nounwind
+
+declare i32 @pthread_setspecific(i32, i8*) nounwind




From dalej at apple.com  Mon Apr 27 16:03:15 2009
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 27 Apr 2009 21:03:15 -0000
Subject: [llvm-commits] [llvm] r70247 - in /llvm/trunk:
 lib/Transforms/Scalar/IndVarSimplify.cpp
 test/Transforms/IndVarSimplify/2009-04-27-Floating.ll
Message-ID: <200904272103.n3RL3Fs0021007@zion.cs.uiuc.edu>

Author: johannes
Date: Mon Apr 27 16:03:15 2009
New Revision: 70247

URL: http://llvm.org/viewvc/llvm-project?rev=70247&view=rev
Log:
Fix PR 4086, a bug in FP IV elimination.


Added:
    llvm/trunk/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=70247&r1=70246&r2=70247&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Mon Apr 27 16:03:15 2009
@@ -1037,9 +1037,11 @@
                                             Incr->getName()+".int", Incr);
   NewPHI->addIncoming(NewAdd, PH->getIncomingBlock(BackEdge));
 
+  // The back edge is edge 1 of newPHI, whatever it may have been in the
+  // original PHI.
   ConstantInt *NewEV = ConstantInt::get(Type::Int32Ty, intEV);
-  Value *LHS = (EVIndex == 1 ? NewPHI->getIncomingValue(BackEdge) : NewEV);
-  Value *RHS = (EVIndex == 1 ? NewEV : NewPHI->getIncomingValue(BackEdge));
+  Value *LHS = (EVIndex == 1 ? NewPHI->getIncomingValue(1) : NewEV);
+  Value *RHS = (EVIndex == 1 ? NewEV : NewPHI->getIncomingValue(1));
   ICmpInst *NewEC = new ICmpInst(NewPred, LHS, RHS, EC->getNameStart(),
                                  EC->getParent()->getTerminator());
 

Added: llvm/trunk/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll?rev=70247&view=auto

==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll (added)
+++ llvm/trunk/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll Mon Apr 27 16:03:15 2009
@@ -0,0 +1,18 @@
+; RUN: llvm-as < %s | opt -indvars | llvm-dis | grep icmp | grep next
+; PR4086
+declare void @foo()
+
+define void @test() {
+entry:
+        br label %loop_body
+
+loop_body:              
+        %i = phi float [ %nexti, %loop_body ], [ 0.0, %entry ]          
+        tail call void @foo()
+        %nexti = add float %i, 1.0              
+        %less = fcmp olt float %nexti, 2.0              
+        br i1 %less, label %loop_body, label %done
+
+done:           
+        ret void
+}




From isanbard at gmail.com  Mon Apr 27 16:58:49 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 27 Apr 2009 21:58:49 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r70258 -
	/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Message-ID: <200904272158.n3RLwng7022916@zion.cs.uiuc.edu>

Author: void
Date: Mon Apr 27 16:58:49 2009
New Revision: 70258

URL: http://llvm.org/viewvc/llvm-project?rev=70258&view=rev
Log:
Set the linkage type for the new GV as well.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=70258&r1=70257&r2=70258&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Mon Apr 27 16:58:49 2009
@@ -1200,6 +1200,7 @@
     NGV->setVisibility(GV->getVisibility());
     NGV->setSection(GV->getSection());
     NGV->setAlignment(GV->getAlignment());
+    NGV->setLinkage(GV->getLinkage());
     GV->replaceAllUsesWith(TheFolder->CreateBitCast(NGV, GV->getType()));
     changeLLVMConstant(GV, NGV);
     delete GV;




From resistor at mac.com  Mon Apr 27 16:59:58 2009
From: resistor at mac.com (Owen Anderson)
Date: Mon, 27 Apr 2009 14:59:58 -0700
Subject: [llvm-commits] [llvm] r70238 -
 /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
In-Reply-To: <64806CD5-0FAE-4E0B-A1D4-E2AD98440A0B@apple.com>
References: <200904271955.n3RJtl0i018527@zion.cs.uiuc.edu>
	<64806CD5-0FAE-4E0B-A1D4-E2AD98440A0B@apple.com>
Message-ID: <6202AFEC-0AF6-4DF5-AC59-46E965863386@mac.com>


On Apr 27, 2009, at 1:14 PM, Evan Cheng wrote:
> On Apr 27, 2009, at 12:55 PM, Owen Anderson wrote:
>
>> Author: resistor
>> Date: Mon Apr 27 14:55:47 2009
>> New Revision: 70238
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=70238&view=rev
>> Log:
>> Don't skip the CopyMI when removing kill markers.
>> This should have no effect on generated code, but makes the
>> intermediate state
>> of the coalescer more sane.
>
> Please be sure about this. I assume you ran lots of tests? One of the
> possible fallout of something like this is it breaks ARM (which uses
> scavenger). It would be nice if we can just run it as a verification
> pass.


It passed everything I could throw at it, but I don't have an ARM  
system to test it on.

--Owen


From isanbard at gmail.com  Mon Apr 27 17:02:54 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 27 Apr 2009 22:02:54 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r70260 - in /llvm-gcc-4.2/trunk/gcc:
 objc/ChangeLog.apple objc/objc-act.c testsuite/ChangeLog.apple
 testsuite/objc.dg/image-info-1.m
Message-ID: <200904272202.n3RM2suZ023096@zion.cs.uiuc.edu>

Author: void
Date: Mon Apr 27 17:02:54 2009
New Revision: 70260

URL: http://llvm.org/viewvc/llvm-project?rev=70260&view=rev
Log:
Merge Apple's gcc r155737 into llvm-gcc:

2009-04-20 Fariborz Jahanian <fjahanian at apple.com> 
        Radar 6803342
        * objc-act.c (generate_objc_image_info): Set the imfo_info
        flag to 16 (1<<4) when in objc2, setter/getter issues error
        on use of super class synthsized ivar.

Added:
    llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/image-info-1.m
Modified:
    llvm-gcc-4.2/trunk/gcc/objc/ChangeLog.apple
    llvm-gcc-4.2/trunk/gcc/objc/objc-act.c
    llvm-gcc-4.2/trunk/gcc/testsuite/ChangeLog.apple

Modified: llvm-gcc-4.2/trunk/gcc/objc/ChangeLog.apple
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/objc/ChangeLog.apple?rev=70260&r1=70259&r2=70260&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/objc/ChangeLog.apple (original)
+++ llvm-gcc-4.2/trunk/gcc/objc/ChangeLog.apple Mon Apr 27 17:02:54 2009
@@ -1,3 +1,9 @@
+2009-04-20 Fariborz Jahanian <fjahanian at apple.com> 
+        Radar 6803342
+        * objc-act.c (generate_objc_image_info): Set the imfo_info
+        flag to 16 (1<<4) when in objc2, setter/getter issues error
+        on use of super class synthsized ivar.
+
 2009-01-07  Fariborz Jahanian <fjahanian at apple.com>
 
         Radar 6379842

Modified: llvm-gcc-4.2/trunk/gcc/objc/objc-act.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/objc/objc-act.c?rev=70260&r1=70259&r2=70260&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/objc/objc-act.c (original)
+++ llvm-gcc-4.2/trunk/gcc/objc/objc-act.c Mon Apr 27 17:02:54 2009
@@ -9913,9 +9913,11 @@
       DECL_ALIGN(decl) = 32;
       DECL_USER_ALIGN(decl) = 1;
 #endif
+      /* LLVM LOCAL end */
 
       finish_var_decl (decl, initlist);
 
+      /* LLVM LOCAL begin */
 #ifdef ENABLE_LLVM
       /* At -O0, we may have emitted references to the decl earlier. */
       if (!optimize)
@@ -11149,8 +11151,10 @@
 
       /* Set offset.  */
       /* LLVM LOCAL - begin make initializer size match type size */
+#ifdef ENABLE_LLVM
       ivar = tree_cons (NULL_TREE, convert (integer_type_node,
                                             byte_position (field_decl)), ivar);
+#endif
       /* LLVM LOCAL - end make initializer size match type size */
       initlist = tree_cons (NULL_TREE,
 			    objc_build_constructor (type, nreverse (ivar)),
@@ -18402,11 +18406,11 @@
 			   get_arg_type_list (METHOD_SEL_NAME (method), method, METHOD_DEF, 0));
   /* APPLE LOCAL radar 5839812 - location for synthesized methods  */
   objc_start_function (method_id, meth_type, NULL_TREE, parmlist, method);
-/* LLVM LOCAL begin prevent llvm from adding leading _ */
+  /* LLVM LOCAL begin prevent llvm from adding leading _ */
 #ifdef ENABLE_LLVM
   set_user_assembler_name(current_function_decl, buf);
 #endif
-/* LLVM LOCAL end prevent llvm from adding leading _ */
+  /* LLVM LOCAL end prevent llvm from adding leading _ */
 
   /* Set self_decl from the first argument.  */
   self_decl = DECL_ARGUMENTS (current_function_decl);
@@ -19285,13 +19289,13 @@
   DECL_INITIAL (decl) = exp;
   TREE_STATIC (decl) = 1;
   TREE_USED (decl) = 1;
-/* LLVM LOCAL begin */
+  /* LLVM LOCAL begin */
 #ifdef ENABLE_LLVM
   /* This decl's name is special. Ask llvm to not add leading underscore by 
      setting it as a user supplied asm name.  */
   set_user_assembler_name(decl, string);
 #endif
-/* LLVM LOCAL end */
+  /* LLVM LOCAL end */
   /* Force the output of the decl as this forces the reference of the class.  */
   mark_decl_referenced (decl);
 
@@ -19331,7 +19335,7 @@
       /* Do the same for categories.  Even though no references to
          these symbols are generated automatically by the compiler, it
          gives you a handle to pull them into an archive by hand.  */
-/* LLVM LOCAL begin */
+      /* LLVM LOCAL begin */
 #ifdef ENABLE_LLVM
       /* The * is a sentinel for gcc's back end, but is not wanted by llvm. */
       sprintf (string, "%sobjc_category_name_%s_%s",
@@ -19340,7 +19344,7 @@
       sprintf (string, "*%sobjc_category_name_%s_%s",
                (flag_next_runtime ? "." : "__"), class_name, class_super_name);
 #endif
-/* LLVM LOCAL end */
+      /* LLVM LOCAL end */
     }
   else
     return;
@@ -19400,6 +19404,10 @@
   if (flag_objc_gc_only)
     flags |= 6;
   /* APPLE LOCAL end radar 4810609 */
+  /* APPLE LOCAL begin radar 6803242 */
+  if (flag_objc_abi == 2)
+    flags |= 16;
+  /* APPLE LOCAL end radar 6803242 */
 
   /* APPLE LOCAL begin radar 4810587 */
   /* LLVM LOCAL begin */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/ChangeLog.apple
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/ChangeLog.apple?rev=70260&r1=70259&r2=70260&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/ChangeLog.apple (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/ChangeLog.apple Mon Apr 27 17:02:54 2009
@@ -1,3 +1,17 @@
+2009-04-20  Fariborz Jahanian <fjahanian at apple.com>
+
+        Radar 6803242
+        *  image-info-1.m: Add
+
+2009-04-13  Stuart Hastings  <stuart at apple.com>
+
+	* g++.apple/675506.C: Added "-Os -m32".
+
+2009-04-06  Stuart Hastings  <stuart at apple.com>
+
+	Radar 6755006
+	* g++.apple/675506.C: New.
+
 2009-03-24  Stuart Hastings  <stuart at apple.com>
 
 	gcc.apple/5774346.c: Add -maltivec.

Added: llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/image-info-1.m
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/image-info-1.m?rev=70260&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/image-info-1.m (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/image-info-1.m Mon Apr 27 17:02:54 2009
@@ -0,0 +1,9 @@
+/* APPLE LOCAL file radar 6803242 */
+/* { dg-do compile { target powerpc*-*-darwin* i?86*-*-darwin* } } */
+/* { dg-options "-mmacosx-version-min=10.5 -m64" } */
+
+ at interface INTF
+ at end
+ at implementation  INTF
+ at end
+/* { dg-final { scan-assembler "L_OBJC_IMAGE_INFO:\n\t.long\t0\n\t.long\t16" } } */




From gohman at apple.com  Mon Apr 27 17:12:34 2009
From: gohman at apple.com (Dan Gohman)
Date: Mon, 27 Apr 2009 22:12:34 -0000
Subject: [llvm-commits] [llvm] r70262 -
	/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
Message-ID: <200904272212.n3RMCYVA023412@zion.cs.uiuc.edu>

Author: djg
Date: Mon Apr 27 17:12:34 2009
New Revision: 70262

URL: http://llvm.org/viewvc/llvm-project?rev=70262&view=rev
Log:
Remove an obsolete comment.

Modified:
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=70262&r1=70261&r2=70262&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Mon Apr 27 17:12:34 2009
@@ -370,11 +370,9 @@
   return Ty;
 }
 
-/// TestOrigIVForWrap - Analyze the original induction variable
-/// that controls the loop's iteration to determine whether it
-/// would ever undergo signed or unsigned overflow. Also, check
-/// whether an induction variable in the same type that starts
-/// at 0 would undergo signed overflow.
+/// TestOrigIVForWrap - Analyze the original induction variable that
+/// controls the loop's iteration to determine whether it would ever
+/// undergo signed or unsigned overflow.
 ///
 /// In addition to setting the NoSignedWrap and NoUnsignedWrap
 /// variables to true when appropriate (they are not set to false here),




From isanbard at gmail.com  Mon Apr 27 19:21:35 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 28 Apr 2009 00:21:35 -0000
Subject: [llvm-commits] [test-suite] r70271 -
	/test-suite/trunk/Makefile.programs
Message-ID: <200904280021.n3S0La5m027556@zion.cs.uiuc.edu>

Author: void
Date: Mon Apr 27 19:21:35 2009
New Revision: 70271

URL: http://llvm.org/viewvc/llvm-project?rev=70271&view=rev
Log:
Change the '-fast' flag to '-O0' to coincide with the llc flag change.

Modified:
    test-suite/trunk/Makefile.programs

Modified: test-suite/trunk/Makefile.programs
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=70271&r1=70270&r2=70271&view=diff

==============================================================================
--- test-suite/trunk/Makefile.programs (original)
+++ test-suite/trunk/Makefile.programs Mon Apr 27 19:21:35 2009
@@ -211,7 +211,7 @@
 endif#DISABLE_DIFFS
 
 ifeq ($(ARCH),PowerPC)
-LLCBETAOPTION := -regalloc=local -fast
+LLCBETAOPTION := -regalloc=local -O0
 #--enable-ppc-preinc
 #-aggressive-remat
 #--enable-tail-merge
@@ -237,9 +237,9 @@
 #-schedule-livein-copies
 #-new-coalescer-heuristic=true
 #-tailcallopt
-#-regalloc=local -fast
+#-regalloc=local -O0
 #-disable-fp-elim
-#-regalloc=bigblock -fast
+#-regalloc=bigblock -O0
 endif
 ifeq ($(ARCH),Sparc)
 LLCBETAOPTION := -enable-sparc-v9-insts




From isanbard at gmail.com  Mon Apr 27 19:21:34 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 28 Apr 2009 00:21:34 -0000
Subject: [llvm-commits] [llvm] r70270 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/
 lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/
 lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Alpha/AsmPrinter/
 lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CellSPU/AsmPrinter/
 lib/Target/CppBackend/ lib/Target/IA64/ lib/Target/IA64/AsmPrinter/
 lib/Target/MSIL/ lib/Target/Mips/ lib/Target/Mips/AsmPrinter/
 lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/PowerPC/AsmPrinter/
 lib/Target...
Message-ID: <200904280021.n3S0LdXU027640@zion.cs.uiuc.edu>

Author: void
Date: Mon Apr 27 19:21:31 2009
New Revision: 70270

URL: http://llvm.org/viewvc/llvm-project?rev=70270&view=rev
Log:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...

Modified:
    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
    llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
    llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
    llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
    llvm/trunk/include/llvm/Target/TargetMachine.h
    llvm/trunk/include/llvm/Target/TargetOptions.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/lib/Target/ARM/ARM.h
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/Alpha/Alpha.h
    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
    llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
    llvm/trunk/lib/Target/CBackend/CBackend.cpp
    llvm/trunk/lib/Target/CBackend/CTargetMachine.h
    llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
    llvm/trunk/lib/Target/CellSPU/SPU.h
    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
    llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
    llvm/trunk/lib/Target/IA64/IA64.h
    llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
    llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
    llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
    llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
    llvm/trunk/lib/Target/Mips/Mips.h
    llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
    llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
    llvm/trunk/lib/Target/PIC16/PIC16.h
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
    llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
    llvm/trunk/lib/Target/PowerPC/PPC.h
    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
    llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
    llvm/trunk/lib/Target/Sparc/Sparc.h
    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
    llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
    llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
    llvm/trunk/lib/Target/X86/X86.h
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.h
    llvm/trunk/lib/Target/XCore/XCore.h
    llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
    llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
    llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
    llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
    llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
    llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
    llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
    llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
    llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
    llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
    llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
    llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
    llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
    llvm/trunk/test/CodeGen/X86/pr1489.ll
    llvm/trunk/test/CodeGen/X86/volatile.ll
    llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
    llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
    llvm/trunk/test/DebugInfo/deaddebuglabel.ll
    llvm/trunk/test/DebugInfo/forwardDecl.ll
    llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
    llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
    llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
    llvm/trunk/tools/llc/llc.cpp
    llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Mon Apr 27 19:21:31 2009
@@ -65,8 +65,8 @@
     // Necessary for external weak linkage support
     std::set<const GlobalValue*> ExtWeakSymbols;
 
-    /// Fast - Generating code via fast instruction selection.
-    bool Fast;
+    /// OptLevel - Generating code at a specific optimization level.
+    unsigned OptLevel;
   public:
     /// Output stream on which we're printing assembly code.
     ///
@@ -110,8 +110,8 @@
     bool VerboseAsm;
 
   protected:
-    AsmPrinter(raw_ostream &o, TargetMachine &TM,
-               const TargetAsmInfo *T, bool F, bool V);
+    explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
+                        const TargetAsmInfo *T, unsigned OL, bool V);
     
   public:
     virtual ~AsmPrinter();

Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Mon Apr 27 19:21:31 2009
@@ -81,7 +81,7 @@
   void EndFunction(MachineFunction *MF);
 
   /// ValidDebugInfo - Return true if V represents valid debug info value.
-  bool ValidDebugInfo(Value *V, bool FastISel);
+  bool ValidDebugInfo(Value *V, unsigned OptLevel);
 
   /// RecordSourceLine - Register a source line with debug info. Returns a
   /// unique label ID used to generate a label and provide correspondence to

Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Mon Apr 27 19:21:31 2009
@@ -42,11 +42,11 @@
       llvm::linkOcamlGC();
       llvm::linkShadowStackGC();
       
-      (void) llvm::createBURRListDAGScheduler(NULL, false);
-      (void) llvm::createTDRRListDAGScheduler(NULL, false);
-      (void) llvm::createTDListDAGScheduler(NULL, false);
-      (void) llvm::createFastDAGScheduler(NULL, false);
-      (void) llvm::createDefaultScheduler(NULL, false);
+      (void) llvm::createBURRListDAGScheduler(NULL, 3);
+      (void) llvm::createTDRRListDAGScheduler(NULL, 3);
+      (void) llvm::createTDListDAGScheduler(NULL, 3);
+      (void) llvm::createFastDAGScheduler(NULL, 3);
+      (void) llvm::createDefaultScheduler(NULL, 3);
 
     }
   } ForceCodegenLinking; // Force link by creating a global definition.

Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Mon Apr 27 19:21:31 2009
@@ -32,7 +32,7 @@
 
 class RegisterScheduler : public MachinePassRegistryNode {
 public:
-  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, bool);
+  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned);
 
   static MachinePassRegistry Registry;
 
@@ -64,27 +64,27 @@
 /// createBURRListDAGScheduler - This creates a bottom up register usage
 /// reduction list scheduler.
 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
-                                               bool Fast);
+                                               unsigned OptLevel);
 
 /// createTDRRListDAGScheduler - This creates a top down register usage
 /// reduction list scheduler.
 ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
-                                               bool Fast);
+                                               unsigned OptLevel);
 
 /// createTDListDAGScheduler - This creates a top-down list scheduler with
 /// a hazard recognizer.
 ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
-                                             bool Fast);
+                                             unsigned OptLevel);
 
 /// createFastDAGScheduler - This creates a "fast" scheduler.
 ///
 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
-                                           bool Fast);
+                                           unsigned OptLevel);
 
 /// createDefaultScheduler - This creates an instruction scheduler appropriate
 /// for the target.
 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
-                                           bool Fast);
+                                           unsigned OptLevel);
 
 } // end namespace llvm
 

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Apr 27 19:21:31 2009
@@ -202,7 +202,7 @@
   /// certain types of nodes together, or eliminating superfluous nodes.  The
   /// Level argument controls whether Combine is allowed to produce nodes and
   /// types that are illegal on the target.
-  void Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast);
+  void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned OptLevel);
 
   /// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that
   /// only uses types natively supported by the target.  Returns "true" if it
@@ -218,7 +218,7 @@
   ///
   /// Note that this is an involved process that may invalidate pointers into
   /// the graph.
-  void Legalize(bool TypesNeedLegalizing, bool Fast);
+  void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
 
   /// RemoveDeadNodes - This method deletes all unreachable nodes in the
   /// SelectionDAG.

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Mon Apr 27 19:21:31 2009
@@ -51,10 +51,10 @@
   MachineBasicBlock *BB;
   AliasAnalysis *AA;
   GCFunctionInfo *GFI;
-  bool Fast;
+  unsigned OptLevel;
   static char ID;
 
-  explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
+  explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
   virtual ~SelectionDAGISel();
   
   TargetLowering &getTargetLowering() { return TLI; }

Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
+++ llvm/trunk/include/llvm/Target/TargetMachine.h Mon Apr 27 19:21:31 2009
@@ -213,7 +213,7 @@
   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
                                                raw_ostream &,
                                                CodeGenFileType,
-                                               bool /*Fast*/) {
+                                               unsigned /* OptLevel */) {
     return FileModel::None;
   }
 
@@ -222,7 +222,8 @@
   /// used to finish up adding passes to emit the file, if necessary.
   ///
   virtual bool addPassesToEmitFileFinish(PassManagerBase &,
-                                         MachineCodeEmitter *, bool /*Fast*/) {
+                                         MachineCodeEmitter *,
+                                         unsigned /* OptLevel */) {
     return true;
   }
  
@@ -234,7 +235,7 @@
   ///
   virtual bool addPassesToEmitMachineCode(PassManagerBase &,
                                           MachineCodeEmitter &,
-                                          bool /*Fast*/) {
+                                          unsigned /* OptLevel */) {
     return true;
   }
 
@@ -243,7 +244,8 @@
   /// use this.
   virtual bool WantsWholeFile() const { return false; }
   virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
-                                        CodeGenFileType, bool /*Fast*/) {
+                                        CodeGenFileType,
+                                        unsigned /* OptLevel */) {
     return true;
   }
 };
@@ -258,16 +260,16 @@
   /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
   /// both emitting to assembly files or machine code output.
   ///
-  bool addCommonCodeGenPasses(PassManagerBase &, bool /*Fast*/);
+  bool addCommonCodeGenPasses(PassManagerBase &, unsigned /* OptLevel */);
 
 public:
   
   /// addPassesToEmitFile - Add passes to the specified pass manager to get the
   /// specified file emitted.  Typically this will involve several steps of code
-  /// generation.  If Fast is set to true, the code generator should emit code
-  /// as fast as possible, though the generated code may be less efficient.
-  /// This method should return FileModel::Error if emission of this file type
-  /// is not supported.
+  /// generation.  If OptLevel is 0, the code generator should emit code as fast
+  /// as possible, though the generated code may be less efficient.  This method
+  /// should return FileModel::Error if emission of this file type is not
+  /// supported.
   ///
   /// The default implementation of this method adds components from the
   /// LLVM retargetable code generator, invoking the methods below to get
@@ -276,14 +278,15 @@
   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
                                                raw_ostream &Out,
                                                CodeGenFileType FileType,
-                                               bool Fast);
+                                               unsigned OptLevel);
   
   /// addPassesToEmitFileFinish - If the passes to emit the specified file had
   /// to be split up (e.g., to add an object writer pass), this method can be
   /// used to finish up adding passes to emit the file, if necessary.
   ///
   virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
-                                         MachineCodeEmitter *MCE, bool Fast);
+                                         MachineCodeEmitter *MCE,
+                                         unsigned OptLevel);
  
   /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
   /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
@@ -292,21 +295,22 @@
   /// not supported.
   ///
   virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
-                                          MachineCodeEmitter &MCE, bool Fast);
+                                          MachineCodeEmitter &MCE,
+                                          unsigned OptLevel);
   
   /// Target-Independent Code Generator Pass Configuration Options.
   
   /// addInstSelector - This method should add any "last minute" LLVM->LLVM
   /// passes, then install an instruction selector pass, which converts from
   /// LLVM code to machine instructions.
-  virtual bool addInstSelector(PassManagerBase &, bool /*Fast*/) {
+  virtual bool addInstSelector(PassManagerBase &, unsigned /* OptLevel */) {
     return true;
   }
 
   /// addPreRegAllocPasses - This method may be implemented by targets that want
   /// to run passes immediately before register allocation. This should return
   /// true if -print-machineinstrs should print after these passes.
-  virtual bool addPreRegAlloc(PassManagerBase &, bool /*Fast*/) {
+  virtual bool addPreRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
     return false;
   }
 
@@ -314,14 +318,14 @@
   /// want to run passes after register allocation but before prolog-epilog
   /// insertion.  This should return true if -print-machineinstrs should print
   /// after these passes.
-  virtual bool addPostRegAlloc(PassManagerBase &, bool /*Fast*/) {
+  virtual bool addPostRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
     return false;
   }
   
   /// addPreEmitPass - This pass may be implemented by targets that want to run
   /// passes immediately before machine code is emitted.  This should return
   /// true if -print-machineinstrs should print out the code after the passes.
-  virtual bool addPreEmitPass(PassManagerBase &, bool /*Fast*/) {
+  virtual bool addPreEmitPass(PassManagerBase &, unsigned /* OptLevel */) {
     return false;
   }
   
@@ -329,7 +333,7 @@
   /// addAssemblyEmitter - This pass should be overridden by the target to add
   /// the asmprinter, if asm emission is supported.  If this is not supported,
   /// 'true' should be returned.
-  virtual bool addAssemblyEmitter(PassManagerBase &, bool /*Fast*/,
+  virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /* OptLevel */,
                                   bool /* VerboseAsmDefault */, raw_ostream &) {
     return true;
   }
@@ -337,7 +341,7 @@
   /// addCodeEmitter - This pass should be overridden by the target to add a
   /// code emitter, if supported.  If this is not supported, 'true' should be
   /// returned. If DumpAsm is true, the generated assembly is printed to cerr.
-  virtual bool addCodeEmitter(PassManagerBase &, bool /*Fast*/,
+  virtual bool addCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
                               bool /*DumpAsm*/, MachineCodeEmitter &) {
     return true;
   }
@@ -346,7 +350,7 @@
   /// a code emitter (without setting flags), if supported.  If this is not
   /// supported, 'true' should be returned.  If DumpAsm is true, the generated
   /// assembly is printed to cerr.
-  virtual bool addSimpleCodeEmitter(PassManagerBase &, bool /*Fast*/,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
                                     bool /*DumpAsm*/, MachineCodeEmitter &) {
     return true;
   }

Modified: llvm/trunk/include/llvm/Target/TargetOptions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOptions.h (original)
+++ llvm/trunk/include/llvm/Target/TargetOptions.h Mon Apr 27 19:21:31 2009
@@ -108,7 +108,7 @@
   /// generated.
   extern bool DisableJumpTables;
 
-  /// FastISel - This flag enables fast-path instruction selection
+  /// EnableFastISel - This flag enables fast-path instruction selection
   /// which trades away generated code quality in favor of reducing
   /// compile time.
   extern bool EnableFastISel;

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon Apr 27 19:21:31 2009
@@ -42,8 +42,8 @@
 
 char AsmPrinter::ID = 0;
 AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
-                       const TargetAsmInfo *T, bool F, bool VDef)
-  : MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o),
+                       const TargetAsmInfo *T, unsigned OL, bool VDef)
+  : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
     TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
     IsInTextSection(false)
 {

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Mon Apr 27 19:21:31 2009
@@ -3351,7 +3351,7 @@
   }
 
   /// ValidDebugInfo - Return true if V represents valid debug info value.
-  bool ValidDebugInfo(Value *V, bool FastISel) {
+  bool ValidDebugInfo(Value *V, unsigned OptLevel) {
     if (!V)
       return false;
 
@@ -3393,7 +3393,7 @@
     case DW_TAG_lexical_block:
       /// FIXME. This interfers with the qualitfy of generated code when 
       /// during optimization.
-      if (FastISel == false)
+      if (OptLevel != 0)
         return false;
     default:
       break;
@@ -4730,8 +4730,8 @@
 }
 
 /// ValidDebugInfo - Return true if V represents valid debug info value.
-bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) {
-  return DD && DD->ValidDebugInfo(V, FastISel);
+bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
+  return DD && DD->ValidDebugInfo(V, OptLevel);
 }
 
 /// RecordSourceLine - Records location information and associates it with a 

Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Mon Apr 27 19:21:31 2009
@@ -55,9 +55,9 @@
 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                        raw_ostream &Out,
                                        CodeGenFileType FileType,
-                                       bool Fast) {
+                                       unsigned OptLevel) {
   // Add common CodeGen passes.
-  if (addCommonCodeGenPasses(PM, Fast))
+  if (addCommonCodeGenPasses(PM, OptLevel))
     return FileModel::Error;
 
   // Fold redundant debug labels.
@@ -66,17 +66,17 @@
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
+  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (!Fast)
+  if (OptLevel != 0)
     PM.add(createLoopAlignerPass());
 
   switch (FileType) {
   default:
     break;
   case TargetMachine::AssemblyFile:
-    if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(), Out))
+    if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
       return FileModel::Error;
     return FileModel::AsmFile;
   case TargetMachine::ObjectFile:
@@ -94,9 +94,9 @@
 /// finish up adding passes to emit the file, if necessary.
 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
                                                   MachineCodeEmitter *MCE,
-                                                  bool Fast) {
+                                                  unsigned OptLevel) {
   if (MCE)
-    addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
+    addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
 
   PM.add(createGCInfoDeleter());
 
@@ -114,15 +114,15 @@
 ///
 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
                                                    MachineCodeEmitter &MCE,
-                                                   bool Fast) {
+                                                   unsigned OptLevel) {
   // Add common CodeGen passes.
-  if (addCommonCodeGenPasses(PM, Fast))
+  if (addCommonCodeGenPasses(PM, OptLevel))
     return true;
 
-  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
+  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
+  addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
 
   PM.add(createGCInfoDeleter());
 
@@ -135,11 +135,12 @@
 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
 /// both emitting to assembly files or machine code output.
 ///
-bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
+bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
+                                               unsigned OptLevel) {
   // Standard LLVM-Level Passes.
 
   // Run loop strength reduction before anything else.
-  if (!Fast) {
+  if (OptLevel != 0) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     if (PrintLSR)
       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
@@ -153,7 +154,7 @@
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
-  if (!Fast)
+  if (OptLevel != 0)
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
   PM.add(createStackProtectorPass(getTargetLowering()));
@@ -167,38 +168,38 @@
 
   // Enable FastISel with -fast, but allow that to be overridden.
   if (EnableFastISelOption == cl::BOU_TRUE ||
-      (Fast && EnableFastISelOption != cl::BOU_FALSE))
+      (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
     EnableFastISel = true;
 
   // Ask the target for an isel.
-  if (addInstSelector(PM, Fast))
+  if (addInstSelector(PM, OptLevel))
     return true;
 
   // Print the instruction selected machine code...
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (!Fast) {
+  if (OptLevel != 0) {
     PM.add(createMachineLICMPass());
     PM.add(createMachineSinkingPass());
   }
 
   // Run pre-ra passes.
-  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
+  if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Perform register allocation.
   PM.add(createRegisterAllocator());
 
   // Perform stack slot coloring.
-  if (!Fast)
+  if (OptLevel != 0)
     PM.add(createStackSlotColoringPass());
 
   if (PrintMachineCode)  // Print the register-allocated code
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Run post-ra passes.
-  if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
+  if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   if (PrintMachineCode)
@@ -216,7 +217,7 @@
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Second pass scheduler.
-  if (!Fast && !DisablePostRAScheduler) {
+  if (OptLevel != 0 && !DisablePostRAScheduler) {
     PM.add(createPostRAScheduler());
 
     if (PrintMachineCode)
@@ -224,7 +225,7 @@
   }
 
   // Branch folding must be run after regalloc and prolog/epilog insertion.
-  if (!Fast)
+  if (OptLevel != 0)
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 
   if (PrintMachineCode)

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 27 19:21:31 2009
@@ -57,9 +57,9 @@
     SelectionDAG &DAG;
     const TargetLowering &TLI;
     CombineLevel Level;
+    unsigned OptLevel;
     bool LegalOperations;
     bool LegalTypes;
-    bool Fast;
 
     // Worklist of all of the nodes that need to be simplified.
     std::vector<SDNode*> WorkList;
@@ -254,13 +254,13 @@
     }
 
 public:
-    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
+    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
       : DAG(D),
         TLI(D.getTargetLoweringInfo()),
         Level(Unrestricted),
+        OptLevel(OL),
         LegalOperations(false),
         LegalTypes(false),
-        Fast(fast),
         AA(A) {}
 
     /// Run - runs the dag combiner on all nodes in the work list
@@ -4784,7 +4784,7 @@
   SDValue Ptr   = LD->getBasePtr();
 
   // Try to infer better alignment information than the load already has.
-  if (!Fast && LD->isUnindexed()) {
+  if (OptLevel != 0 && LD->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > LD->getAlignment())
         return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
@@ -4904,7 +4904,7 @@
   SDValue Ptr   = ST->getBasePtr();
 
   // Try to infer better alignment information than the store already has.
-  if (!Fast && ST->isUnindexed()) {
+  if (OptLevel != 0 && ST->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > ST->getAlignment())
         return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
@@ -6084,8 +6084,9 @@
 
 // SelectionDAG::Combine - This is the entry point for the file.
 //
-void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) {
+void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
+                           unsigned OptLevel) {
   /// run - This is the main entry point to this class.
   ///
-  DAGCombiner(*this, AA, Fast).Run(Level);
+  DAGCombiner(*this, AA, OptLevel).Run(Level);
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Apr 27 19:21:31 2009
@@ -327,7 +327,7 @@
   default: break;
   case Intrinsic::dbg_stoppoint: {
     DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
-    if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) {
+    if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
       DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
       std::string Dir, FN;
       unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
@@ -344,7 +344,7 @@
   }
   case Intrinsic::dbg_region_start: {
     DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
-    if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) {
+    if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
       unsigned ID = 
         DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
@@ -354,7 +354,7 @@
   }
   case Intrinsic::dbg_region_end: {
     DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
-    if (DW && DW->ValidDebugInfo(REI->getContext(), true)) {
+    if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
      unsigned ID = 0;
      DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
      if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
@@ -380,7 +380,7 @@
     DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
     Value *SP = FSI->getSubprogram();
 
-    if (DW->ValidDebugInfo(SP, true)) {
+    if (DW->ValidDebugInfo(SP, 0)) {
       // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
       // (most?) gdb expects.
       DebugLoc PrevLoc = DL;
@@ -425,7 +425,7 @@
   case Intrinsic::dbg_declare: {
     DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
     Value *Variable = DI->getVariable();
-    if (DW && DW->ValidDebugInfo(Variable, true)) {
+    if (DW && DW->ValidDebugInfo(Variable, 0)) {
       // Determine the address of the declared object.
       Value *Address = DI->getAddress();
       if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 27 19:21:31 2009
@@ -55,8 +55,8 @@
 class VISIBILITY_HIDDEN SelectionDAGLegalize {
   TargetLowering &TLI;
   SelectionDAG &DAG;
+  unsigned OptLevel;
   bool TypesNeedLegalizing;
-  bool Fast;
 
   // Libcall insertion helpers.
 
@@ -139,7 +139,7 @@
 
 public:
   explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
-                                bool fast);
+                                unsigned ol);
 
   /// getTypeAction - Return how we should legalize values of this type, either
   /// it is already legal or we need to expand it into multiple registers of
@@ -345,9 +345,9 @@
 }
 
 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
-                                           bool types, bool fast)
-  : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
-    Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
+                                           bool types, unsigned ol)
+  : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
+    TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) {
   assert(MVT::LAST_VALUETYPE <= 32 &&
          "Too many value types for ValueTypeActions to hold!");
 }
@@ -1271,7 +1271,7 @@
         unsigned Line = DSP->getLine();
         unsigned Col = DSP->getColumn();
 
-        if (Fast) {
+        if (OptLevel == 0) {
           // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
           // won't hurt anything.
           if (useDEBUG_LOC) {
@@ -8566,9 +8566,9 @@
 
 // SelectionDAG::Legalize - This is the entry point for the file.
 //
-void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
+void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) {
   /// run - This is the main entry point to this class.
   ///
-  SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG();
+  SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG();
 }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Mon Apr 27 19:21:31 2009
@@ -630,6 +630,6 @@
 //===----------------------------------------------------------------------===//
 
 llvm::ScheduleDAGSDNodes *
-llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
+llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
   return new ScheduleDAGFast(*IS->MF);
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon Apr 27 19:21:31 2009
@@ -261,7 +261,7 @@
 /// new hazard recognizer. This scheduler takes ownership of the hazard
 /// recognizer and deletes it when done.
 ScheduleDAGSDNodes *
-llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) {
+llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
   return new ScheduleDAGList(*IS->MF,
                              new LatencyPriorityQueue(),
                              IS->CreateTargetHazardRecognizer());

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Apr 27 19:21:31 2009
@@ -1505,7 +1505,7 @@
 //===----------------------------------------------------------------------===//
 
 llvm::ScheduleDAGSDNodes *
-llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
+llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
   const TargetMachine &TM = IS->TM;
   const TargetInstrInfo *TII = TM.getInstrInfo();
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
@@ -1519,7 +1519,7 @@
 }
 
 llvm::ScheduleDAGSDNodes *
-llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
+llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
   const TargetMachine &TM = IS->TM;
   const TargetInstrInfo *TII = TM.getInstrInfo();
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Apr 27 19:21:31 2009
@@ -3910,9 +3910,9 @@
   case Intrinsic::dbg_stoppoint: {
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
-    if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
+    if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
       MachineFunction &MF = DAG.getMachineFunction();
-      if (Fast)
+      if (OptLevel == 0)
         DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
                                         SPI.getLine(),
                                         SPI.getColumn(),
@@ -3930,7 +3930,8 @@
   case Intrinsic::dbg_region_start: {
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
-    if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
+
+    if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) {
       unsigned LabelID =
         DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
       DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
@@ -3942,8 +3943,8 @@
   case Intrinsic::dbg_region_end: {
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
-    if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
 
+    if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) {
       MachineFunction &MF = DAG.getMachineFunction();
       DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
       std::string SPName;
@@ -3952,7 +3953,7 @@
           && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
           // This is end of inlined function. Debugging information for
           // inlined function is not handled yet (only supported by FastISel).
-        if (Fast) {
+        if (OptLevel == 0) {
           unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
           if (ID != 0)
             // Returned ID is 0 if this is unbalanced "end of inlined
@@ -3978,9 +3979,9 @@
     if (!DW) return 0;
     DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
     Value *SP = FSI.getSubprogram();
-    if (SP && DW->ValidDebugInfo(SP, Fast)) {
-        MachineFunction &MF = DAG.getMachineFunction();
-      if (Fast) {
+    if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
+      MachineFunction &MF = DAG.getMachineFunction();
+      if (OptLevel == 0) {
         // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
         // (most?) gdb expects.
         DebugLoc PrevLoc = CurDebugLoc;
@@ -4051,11 +4052,11 @@
     return 0;
   }
   case Intrinsic::dbg_declare: {
-    if (Fast) {
+    if (OptLevel == 0) {
       DwarfWriter *DW = DAG.getDwarfWriter();
       DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
       Value *Variable = DI.getVariable();
-      if (DW && DW->ValidDebugInfo(Variable, Fast))
+      if (DW && DW->ValidDebugInfo(Variable, OptLevel))
         DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
                                 getValue(DI.getAddress()), getValue(Variable)));
     } else {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Mon Apr 27 19:21:31 2009
@@ -355,17 +355,17 @@
   ///
   FunctionLoweringInfo &FuncInfo;
 
-  /// Fast - We are in -fast mode.
+  /// OptLevel - What optimization level we're generating code for.
   /// 
-  bool Fast;
+  unsigned OptLevel;
   
   /// GFI - Garbage collection metadata for the function.
   GCFunctionInfo *GFI;
 
   SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
-                       FunctionLoweringInfo &funcinfo, bool fast)
+                       FunctionLoweringInfo &funcinfo, unsigned ol)
     : CurDebugLoc(DebugLoc::getUnknownLoc()), 
-      TLI(tli), DAG(dag), FuncInfo(funcinfo), Fast(fast) {
+      TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
   }
 
   void init(GCFunctionInfo *gfi, AliasAnalysis &aa);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 27 19:21:31 2009
@@ -136,16 +136,16 @@
   /// createDefaultScheduler - This creates an instruction scheduler appropriate
   /// for the target.
   ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
-                                             bool Fast) {
+                                             unsigned OptLevel) {
     const TargetLowering &TLI = IS->getTargetLowering();
 
-    if (Fast)
-      return createFastDAGScheduler(IS, Fast);
+    if (OptLevel == 0)
+      return createFastDAGScheduler(IS, OptLevel);
     if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
-      return createTDListDAGScheduler(IS, Fast);
+      return createTDListDAGScheduler(IS, OptLevel);
     assert(TLI.getSchedulingPreference() ==
          TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
-    return createBURRListDAGScheduler(IS, Fast);
+    return createBURRListDAGScheduler(IS, OptLevel);
   }
 }
 
@@ -262,13 +262,13 @@
 // SelectionDAGISel code
 //===----------------------------------------------------------------------===//
 
-SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
+SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
   FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
   FuncInfo(new FunctionLoweringInfo(TLI)),
   CurDAG(new SelectionDAG(TLI, *FuncInfo)),
-  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)),
+  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)),
   GFI(),
-  Fast(fast),
+  OptLevel(OL),
   DAGSize(0)
 {}
 
@@ -576,9 +576,9 @@
   // Run the DAG combiner in pre-legalize mode.
   if (TimePassesIsEnabled) {
     NamedRegionTimer T("DAG Combining 1", GroupName);
-    CurDAG->Combine(Unrestricted, *AA, Fast);
+    CurDAG->Combine(Unrestricted, *AA, OptLevel);
   } else {
-    CurDAG->Combine(Unrestricted, *AA, Fast);
+    CurDAG->Combine(Unrestricted, *AA, OptLevel);
   }
   
   DOUT << "Optimized lowered selection DAG:\n";
@@ -608,9 +608,9 @@
       // Run the DAG combiner in post-type-legalize mode.
       if (TimePassesIsEnabled) {
         NamedRegionTimer T("DAG Combining after legalize types", GroupName);
-        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
+        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
       } else {
-        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
+        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
       }
 
       DOUT << "Optimized type-legalized selection DAG:\n";
@@ -622,9 +622,9 @@
 
   if (TimePassesIsEnabled) {
     NamedRegionTimer T("DAG Legalization", GroupName);
-    CurDAG->Legalize(DisableLegalizeTypes, Fast);
+    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
   } else {
-    CurDAG->Legalize(DisableLegalizeTypes, Fast);
+    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
   }
   
   DOUT << "Legalized selection DAG:\n";
@@ -635,9 +635,9 @@
   // Run the DAG combiner in post-legalize mode.
   if (TimePassesIsEnabled) {
     NamedRegionTimer T("DAG Combining 2", GroupName);
-    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
+    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
   } else {
-    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
+    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
   }
   
   DOUT << "Optimized legalized selection DAG:\n";
@@ -645,7 +645,7 @@
 
   if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
   
-  if (!Fast)
+  if (OptLevel != 0)
     ComputeLiveOutVRegInfo();
 
   // Third, instruction select all of the operations to machine code, adding the
@@ -1082,7 +1082,7 @@
     RegisterScheduler::setDefault(Ctor);
   }
   
-  return Ctor(this, Fast);
+  return Ctor(this, OptLevel);
 }
 
 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {

Modified: llvm/trunk/lib/Target/ARM/ARM.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.h (original)
+++ llvm/trunk/lib/Target/ARM/ARM.h Mon Apr 27 19:21:31 2009
@@ -91,7 +91,7 @@
 FunctionPass *createARMISelDag(ARMTargetMachine &TM);
 FunctionPass *createARMCodePrinterPass(raw_ostream &O,
                                        ARMTargetMachine &TM,
-                                       bool Fast, bool Verbose);
+                                       unsigned OptLevel, bool Verbose);
 FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
                                        MachineCodeEmitter &MCE);
 FunctionPass *createARMLoadStoreOptimizationPass();

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Mon Apr 27 19:21:31 2009
@@ -138,35 +138,37 @@
 
 
 // Pass Pipeline Configuration
-bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
   PM.add(createARMISelDag(*this));
   return false;
 }
 
-bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
+bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
   // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
-  if (!Fast && !DisableLdStOpti && !Subtarget.isThumb())
+  if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
     PM.add(createARMLoadStoreOptimizationPass());
 
-  if (!Fast && !DisableIfConversion && !Subtarget.isThumb())
+  if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
     PM.add(createIfConverterPass());
 
   PM.add(createARMConstantIslandPass());
   return true;
 }
 
-bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
-                                          bool Verbose, raw_ostream &Out) {
+bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                          unsigned OptLevel,
+                                          bool Verbose,
+                                          raw_ostream &Out) {
   // Output assembly language.
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
   if (AsmPrinterCtor)
-    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
+    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
 
   return false;
 }
 
 
-bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
+bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // FIXME: Move this to TargetJITInfo!
   if (DefRelocModel == Reloc::Default)
@@ -177,20 +179,22 @@
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
   }
 
   return false;
 }
 
-bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
-                                        bool DumpAsm, MachineCodeEmitter &MCE) {
+bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+                                            unsigned OptLevel,
+                                            bool DumpAsm,
+                                            MachineCodeEmitter &MCE) {
   // Machine code emitter pass for ARM.
   PM.add(createARMCodeEmitterPass(*this, MCE));
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
   }
 
   return false;

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Mon Apr 27 19:21:31 2009
@@ -41,7 +41,7 @@
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             ARMTargetMachine &tm,
-                                            bool fast, bool verbose);
+                                            unsigned OptLevel, bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -69,13 +69,13 @@
   virtual const TargetAsmInfo *createTargetAsmInfo() const;
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
 };
 

Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Mon Apr 27 19:21:31 2009
@@ -80,9 +80,9 @@
     /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
     bool InCPMode;
   public:
-    ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                  const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
+    explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                           const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
         InCPMode(false) {
       Subtarget = &TM.getSubtarget<ARMSubtarget>();
     }
@@ -1061,8 +1061,8 @@
 ///
 FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
                                              ARMTargetMachine &tm,
-                                             bool fast, bool verbose) {
-  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                             unsigned OptLevel, bool verbose) {
+  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 
 namespace {

Modified: llvm/trunk/lib/Target/Alpha/Alpha.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/Alpha.h (original)
+++ llvm/trunk/lib/Target/Alpha/Alpha.h Mon Apr 27 19:21:31 2009
@@ -26,7 +26,7 @@
   FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
   FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
                                            TargetMachine &TM,
-                                           bool Fast, bool Verbose);
+                                           unsigned OptLevel, bool Verbose);
   FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
   FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
                                            MachineCodeEmitter &MCE);

Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Mon Apr 27 19:21:31 2009
@@ -76,31 +76,34 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
+                                         unsigned OptLevel) {
   PM.add(createAlphaISelDag(*this));
   return false;
 }
-bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
+bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
+                                        unsigned OptLevel) {
   // Must run branch selection immediately preceding the asm printer
   PM.add(createAlphaBranchSelectionPass());
   return false;
 }
-bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
+bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                            unsigned OptLevel,
                                             bool Verbose,
                                             raw_ostream &Out) {
   PM.add(createAlphaLLRPPass(*this));
-  PM.add(createAlphaCodePrinterPass(Out, *this, Fast, Verbose));
+  PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }
-bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                         bool DumpAsm, MachineCodeEmitter &MCE) {
   PM.add(createAlphaCodeEmitterPass(*this, MCE));
   if (DumpAsm)
-    PM.add(createAlphaCodePrinterPass(errs(), *this, Fast, true));
+    PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel, true));
   return false;
 }
 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
-                                              bool Fast, bool DumpAsm,
+                                              unsigned OptLevel, bool DumpAsm,
                                               MachineCodeEmitter &MCE) {
-  return addCodeEmitter(PM, Fast, DumpAsm, MCE);
+  return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
 }

Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Mon Apr 27 19:21:31 2009
@@ -58,13 +58,13 @@
   static unsigned getModuleMatchQuality(const Module &M);
   
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
 };
 

Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Mon Apr 27 19:21:31 2009
@@ -36,9 +36,9 @@
     /// Unique incrementer for label values for referencing Global values.
     ///
 
-    AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
-                    const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(o, tm, T, F, V) {}
+    explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
+                             const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(o, tm, T, OL, V) {}
 
     virtual const char *getPassName() const {
       return "Alpha Assembly Printer";
@@ -68,8 +68,9 @@
 ///
 FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
                                                TargetMachine &tm,
-                                               bool fast, bool verbose) {
-  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                               unsigned OptLevel,
+                                               bool verbose) {
+  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 
 #include "AlphaGenAsmWriter.inc"

Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
+++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Apr 27 19:21:31 2009
@@ -3587,7 +3587,7 @@
 bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
                                               raw_ostream &o,
                                               CodeGenFileType FileType,
-                                              bool Fast) {
+                                              unsigned OptLevel) {
   if (FileType != TargetMachine::AssemblyFile) return true;
 
   PM.add(createGCLoweringPass());

Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Mon Apr 27 19:21:31 2009
@@ -27,7 +27,8 @@
 
   virtual bool WantsWholeFile() const { return true; }
   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
-                                        CodeGenFileType FileType, bool Fast);
+                                        CodeGenFileType FileType,
+                                        unsigned OptLevel);
 
   // This class always works, but must be requested explicitly on 
   // llc command line.

Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Mon Apr 27 19:21:31 2009
@@ -48,9 +48,9 @@
   class VISIBILITY_HIDDEN SPUAsmPrinter : public AsmPrinter {
     std::set<std::string> FnStubs, GVStubs;
   public:
-    SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                  const TargetAsmInfo *T, bool F, bool V) :
-      AsmPrinter(O, TM, T, F, V) {}
+    explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                           const TargetAsmInfo *T, unsigned OL, bool V) :
+      AsmPrinter(O, TM, T, OL, V) {}
 
     virtual const char *getPassName() const {
       return "STI CBEA SPU Assembly Printer";
@@ -615,6 +615,6 @@
 ///
 FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
                                             SPUTargetMachine &tm,
-                                            bool fast, bool verbose) {
-  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                            unsigned OptLevel, bool verbose) {
+  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }

Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPU.h Mon Apr 27 19:21:31 2009
@@ -25,7 +25,7 @@
   FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
   FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
                                         SPUTargetMachine &tm,
-                                        bool fast, bool verbose);
+                                        unsigned OptLevel, bool verbose);
 
   /*--== Utility functions/predicates/etc used all over the place: --==*/
   //! Predicate test for a signed 10-bit value

Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Mon Apr 27 19:21:31 2009
@@ -81,15 +81,17 @@
 //===----------------------------------------------------------------------===//
 
 bool
-SPUTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast)
+SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel)
 {
   // Install an instruction selector.
   PM.add(createSPUISelDag(*this));
   return false;
 }
 
-bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
-                                          bool Verbose, raw_ostream &Out) {
-  PM.add(createSPUAsmPrinterPass(Out, *this, Fast, Verbose));
+bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                          unsigned OptLevel,
+                                          bool Verbose,
+                                          raw_ostream &Out) {
+  PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }

Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Mon Apr 27 19:21:31 2009
@@ -83,9 +83,9 @@
   }
   
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool /*Fast*/);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool /*Fast*/, 
-                                  bool /*Verbose*/, raw_ostream &Out);
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+                                  bool Verbose, raw_ostream &Out);
 };
 
 } // end namespace llvm

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Mon Apr 27 19:21:31 2009
@@ -1995,7 +1995,7 @@
 bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
                                                 raw_ostream &o,
                                                 CodeGenFileType FileType,
-                                                bool Fast) {
+                                                unsigned OptLevel) {
   if (FileType != TargetMachine::AssemblyFile) return true;
   PM.add(new CppWriter(o));
   return false;

Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Mon Apr 27 19:21:31 2009
@@ -29,7 +29,8 @@
 
   virtual bool WantsWholeFile() const { return true; }
   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
-                                        CodeGenFileType FileType, bool Fast);
+                                        CodeGenFileType FileType,
+                                        unsigned OptLevel);
 
   // This class always works, but shouldn't be the default in most cases.
   static unsigned getModuleMatchQuality(const Module &M) { return 1; }

Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Mon Apr 27 19:21:31 2009
@@ -37,9 +37,9 @@
   class IA64AsmPrinter : public AsmPrinter {
     std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
   public:
-    IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
-                   const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V) {}
+    explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
+                            const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V) {}
 
     virtual const char *getPassName() const {
       return "IA64 Assembly Printer";
@@ -370,6 +370,7 @@
 ///
 FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
                                               IA64TargetMachine &tm,
-                                              bool fast, bool verbose) {
-  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                              unsigned OptLevel,
+                                              bool verbose) {
+  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }

Modified: llvm/trunk/lib/Target/IA64/IA64.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64.h Mon Apr 27 19:21:31 2009
@@ -37,7 +37,7 @@
 ///
 FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
                                         IA64TargetMachine &tm,
-                                        bool fast, bool verbose);
+                                        unsigned OptLevel, bool verbose);
 
 } // End llvm namespace
 

Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Mon Apr 27 19:21:31 2009
@@ -72,19 +72,21 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLEvel){
   PM.add(createIA64DAGToDAGInstructionSelector(*this));
   return false;
 }
 
-bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
+bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
   // Make sure everything is bundled happily
   PM.add(createIA64BundlingPass(*this));
   return true;
 }
-bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
-                                           bool Verbose, raw_ostream &Out) {
-  PM.add(createIA64CodePrinterPass(Out, *this, Fast, Verbose));
+bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                           unsigned OptLevel,
+                                           bool Verbose,
+                                           raw_ostream &Out) {
+  PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }
 

Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64TargetMachine.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.h Mon Apr 27 19:21:31 2009
@@ -51,9 +51,9 @@
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                                   bool Verbose, raw_ostream &Out);
 };
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
+++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Mon Apr 27 19:21:31 2009
@@ -35,7 +35,8 @@
 
     virtual bool WantsWholeFile() const { return true; }
     virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
-                                         CodeGenFileType FileType, bool Fast);
+                                          CodeGenFileType FileType,
+                                          unsigned OptLevel);
 
     // This class always works, but shouldn't be the default in most cases.
     static unsigned getModuleMatchQuality(const Module &M) { return 1; }
@@ -1662,7 +1663,8 @@
 //===----------------------------------------------------------------------===//
 
 bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o,
-                                          CodeGenFileType FileType, bool Fast)
+                                          CodeGenFileType FileType,
+                                          unsigned OptLevel)
 {
   if (FileType != TargetMachine::AssemblyFile) return true;
   MSILWriter* Writer = new MSILWriter(o);

Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Mon Apr 27 19:21:31 2009
@@ -49,9 +49,9 @@
   class VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
     const MipsSubtarget *Subtarget;
   public:
-    MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM, 
-                   const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V) {
+    explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM, 
+                            const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V) {
       Subtarget = &TM.getSubtarget<MipsSubtarget>();
     }
 
@@ -91,8 +91,8 @@
 /// regardless of whether the function is in SSA form.
 FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
                                               MipsTargetMachine &tm,
-                                              bool fast, bool verbose) {
-  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                              unsigned OptLevel, bool verbose) {
+  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/Mips/Mips.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.h (original)
+++ llvm/trunk/lib/Target/Mips/Mips.h Mon Apr 27 19:21:31 2009
@@ -25,7 +25,7 @@
   FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
   FunctionPass *createMipsCodePrinterPass(raw_ostream &OS, 
                                           MipsTargetMachine &TM,
-                                          bool Fast, bool Verbose);
+                                          unsigned OptLevel, bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for Mips registers.  This defines a mapping from

Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Mon Apr 27 19:21:31 2009
@@ -105,7 +105,7 @@
 // Install an instruction selector pass using 
 // the ISelDag to gen Mips code.
 bool MipsTargetMachine::
-addInstSelector(PassManagerBase &PM, bool Fast) 
+addInstSelector(PassManagerBase &PM, unsigned OptLevel) 
 {
   PM.add(createMipsISelDag(*this));
   return false;
@@ -115,7 +115,7 @@
 // machine code is emitted. return true if -print-machineinstrs should 
 // print out the code after the passes.
 bool MipsTargetMachine::
-addPreEmitPass(PassManagerBase &PM, bool Fast) 
+addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) 
 {
   PM.add(createMipsDelaySlotFillerPass(*this));
   return true;
@@ -124,10 +124,10 @@
 // Implements the AssemblyEmitter for the target. Must return
 // true if AssemblyEmitter is supported
 bool MipsTargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                    bool Verbose, raw_ostream &Out) 
 {
   // Output assembly language.
-  PM.add(createMipsCodePrinterPass(Out, *this, Fast, Verbose));
+  PM.add(createMipsCodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }

Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Mon Apr 27 19:21:31 2009
@@ -57,9 +57,9 @@
     static unsigned getModuleMatchQuality(const Module &M);
 
     // Pass Pipeline Configuration
-    virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-    virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
-    virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+    virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+    virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
+    virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
                                     bool Verbose, raw_ostream &Out);
   };
 

Modified: llvm/trunk/lib/Target/PIC16/PIC16.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16.h Mon Apr 27 19:21:31 2009
@@ -75,7 +75,7 @@
   FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
   FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS, 
                                            PIC16TargetMachine &TM,
-                                           bool Fast, bool Verbose);
+                                           unsigned OptLevel, bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for PIC16 registers.  This defines a mapping from

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Mon Apr 27 19:21:31 2009
@@ -161,8 +161,9 @@
 ///
 FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
                                                PIC16TargetMachine &tm,
-                                               bool fast, bool verbose) {
-  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                               unsigned OptLevel,
+                                               bool verbose) {
+  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 
 void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Mon Apr 27 19:21:31 2009
@@ -24,9 +24,9 @@
 
 namespace llvm {
   struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
-  PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
-                    const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V) {
+    explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
+                             const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V) {
       CurBank = "";
       FunctionLabelBegin = '@';
       IsRomData = false;

Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Mon Apr 27 19:21:31 2009
@@ -55,17 +55,18 @@
   return new PIC16TargetAsmInfo(*this);
 }
 
-bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
+                                         unsigned OptLevel) {
   // Install an instruction selector.
   PM.add(createPIC16ISelDag(*this));
   return false;
 }
 
 bool PIC16TargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, bool Fast, bool Verbose,
+addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose,
                    raw_ostream &Out) {
   // Output assembly language.
-  PM.add(createPIC16CodePrinterPass(Out, *this, Fast, Verbose));
+  PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }
 

Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h Mon Apr 27 19:21:31 2009
@@ -57,8 +57,8 @@
     return const_cast<PIC16TargetLowering*>(&TLInfo); 
   }
 
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
                                   bool Verbose, raw_ostream &Out);
 }; // PIC16TargetMachine.
 

Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Mon Apr 27 19:21:31 2009
@@ -54,9 +54,9 @@
     StringSet<> FnStubs, GVStubs, HiddenGVStubs;
     const PPCSubtarget &Subtarget;
   public:
-    PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                  const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V),
+    explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                           const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V),
         Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
 
     virtual const char *getPassName() const {
@@ -297,9 +297,9 @@
     DwarfWriter *DW;
     MachineModuleInfo *MMI;
   public:
-    PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
-                       const TargetAsmInfo *T, bool F, bool V)
-      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
+    explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
+                                const TargetAsmInfo *T, unsigned OL, bool V)
+      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
 
     virtual const char *getPassName() const {
       return "Linux PPC Assembly Printer";
@@ -326,9 +326,9 @@
     MachineModuleInfo *MMI;
     raw_ostream &OS;
   public:
-    PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
-                        const TargetAsmInfo *T, bool F, bool V)
-      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0), OS(O) {}
+    explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
+                                 const TargetAsmInfo *T, unsigned OL, bool V)
+      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
 
     virtual const char *getPassName() const {
       return "Darwin PPC Assembly Printer";
@@ -1176,13 +1176,15 @@
 ///
 FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
                                             PPCTargetMachine &tm,
-                                            bool fast, bool verbose) {
+                                            unsigned OptLevel, bool verbose) {
   const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
 
   if (Subtarget->isDarwin()) {
-    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
+                                   OptLevel, verbose);
   } else {
-    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
+                                  OptLevel, verbose);
   }
 }
 

Modified: llvm/trunk/lib/Target/PowerPC/PPC.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPC.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPC.h Mon Apr 27 19:21:31 2009
@@ -28,7 +28,7 @@
 FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
 FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
                                       PPCTargetMachine &TM,
-                                      bool Fast, bool Verbose);
+                                      unsigned OptLevel, bool Verbose);
 FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
                                        MachineCodeEmitter &MCE);
 } // end namespace llvm;

Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Apr 27 19:21:31 2009
@@ -129,29 +129,31 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
   // Install an instruction selector.
   PM.add(createPPCISelDag(*this));
   return false;
 }
 
-bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
+bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
   
   // Must run branch selection immediately preceding the asm printer.
   PM.add(createPPCBranchSelectionPass());
   return false;
 }
 
-bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
-                                          bool Verbose, raw_ostream &Out) {
+bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                          unsigned OptLevel,
+                                          bool Verbose,
+                                          raw_ostream &Out) {
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
   if (AsmPrinterCtor)
-    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
+    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
 
   return false;
 }
 
-bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
+bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
   // FIXME: This should be moved to TargetJITInfo!!
@@ -176,20 +178,20 @@
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
   }
 
   return false;
 }
 
-bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                             bool DumpAsm, MachineCodeEmitter &MCE) {
   // Machine code emitter pass for PowerPC.
   PM.add(createPPCCodeEmitterPass(*this, MCE));
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
   }
 
   return false;

Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Mon Apr 27 19:21:31 2009
@@ -46,7 +46,7 @@
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             PPCTargetMachine &tm, 
-                                            bool fast, bool verbose);
+                                            unsigned OptLevel, bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -76,13 +76,13 @@
   }
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
   virtual bool getEnableTailMergeDefault() const;
 };

Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp Mon Apr 27 19:21:31 2009
@@ -48,9 +48,9 @@
     typedef std::map<const Value *, unsigned> ValueMapTy;
     ValueMapTy NumberForBB;
   public:
-    SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                    const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V) {}
+    explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                             const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V) {}
 
     virtual const char *getPassName() const {
       return "Sparc Assembly Printer";
@@ -82,8 +82,9 @@
 ///
 FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
                                                TargetMachine &tm,
-                                               bool fast, bool verbose) {
-  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                               unsigned OptLevel,
+                                               bool verbose) {
+  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 
 /// runOnMachineFunction - This uses the printInstruction()

Modified: llvm/trunk/lib/Target/Sparc/Sparc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/Sparc.h (original)
+++ llvm/trunk/lib/Target/Sparc/Sparc.h Mon Apr 27 19:21:31 2009
@@ -25,7 +25,7 @@
 
   FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
   FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM,
-                                           bool Fast, bool Verbose);
+                                           unsigned OptLevel, bool Verbose);
   FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
   FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
 } // end namespace llvm;

Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Mon Apr 27 19:21:31 2009
@@ -68,7 +68,8 @@
 #endif
 }
 
-bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
+                                         unsigned OptLevel) {
   PM.add(createSparcISelDag(*this));
   return false;
 }
@@ -76,15 +77,17 @@
 /// addPreEmitPass - This pass may be implemented by targets that want to run
 /// passes immediately before machine code is emitted.  This should return
 /// true if -print-machineinstrs should print out the code after the passes.
-bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
+bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel){
   PM.add(createSparcFPMoverPass(*this));
   PM.add(createSparcDelaySlotFillerPass(*this));
   return true;
 }
 
-bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
-                                            bool Verbose, raw_ostream &Out) {
+bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                            unsigned OptLevel,
+                                            bool Verbose,
+                                            raw_ostream &Out) {
   // Output assembly language.
-  PM.add(createSparcCodePrinterPass(Out, *this, Fast, Verbose));
+  PM.add(createSparcCodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }

Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Mon Apr 27 19:21:31 2009
@@ -51,9 +51,9 @@
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                                   bool Verbose, raw_ostream &Out);
 };
 

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Mon Apr 27 19:21:31 2009
@@ -33,9 +33,9 @@
   MachineModuleInfo *MMI;
   const X86Subtarget *Subtarget;
  public:
-  X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
-                   const TargetAsmInfo *T, bool F, bool V)
-    : AsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {
+  explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
+                            const TargetAsmInfo *T, unsigned OL, bool V)
+    : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
     Subtarget = &TM.getSubtarget<X86Subtarget>();
   }
 

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Mon Apr 27 19:21:31 2009
@@ -25,13 +25,15 @@
 ///
 FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
                                              X86TargetMachine &tm,
-                                             bool fast, bool verbose) {
+                                             unsigned OptLevel, bool verbose) {
   const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
 
   if (Subtarget->isFlavorIntel()) {
-    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(),
+                                  OptLevel, verbose);
   } else {
-    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(),
+                                OptLevel, verbose);
   }
 }
 

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h Mon Apr 27 19:21:31 2009
@@ -25,9 +25,9 @@
 namespace llvm {
 
 struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
-  X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
-                     const TargetAsmInfo *T, bool F, bool V)
-    : AsmPrinter(O, TM, T, F, V) {}
+  explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
+                              const TargetAsmInfo *T, unsigned OL, bool V)
+    : AsmPrinter(O, TM, T, OL, V) {}
 
   virtual const char *getPassName() const {
     return "X86 Intel-Style Assembly Printer";

Modified: llvm/trunk/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86.h (original)
+++ llvm/trunk/lib/Target/X86/X86.h Mon Apr 27 19:21:31 2009
@@ -25,7 +25,7 @@
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *createX86ISelDag(X86TargetMachine &TM, bool Fast);
+FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned OptSize);
 
 /// createX86FloatingPointStackifierPass - This function returns a pass which
 /// converts floating point register references and pseudo instructions into
@@ -44,7 +44,7 @@
 ///
 FunctionPass *createX86CodePrinterPass(raw_ostream &o,
                                        X86TargetMachine &tm,
-                                       bool fast, bool Verbose);
+                                       unsigned OptLevel, bool Verbose);
 
 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
 /// to the specified MCE object.

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Apr 27 19:21:31 2009
@@ -134,8 +134,8 @@
     bool OptForSize;
 
   public:
-    X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
-      : SelectionDAGISel(tm, fast),
+    explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
+      : SelectionDAGISel(tm, OptLevel),
         TM(tm), X86Lowering(*TM.getTargetLowering()),
         Subtarget(&TM.getSubtarget<X86Subtarget>()),
         OptForSize(false) {}
@@ -306,7 +306,7 @@
 
 bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
                                                  SDNode *Root) const {
-  if (Fast) return false;
+  if (OptLevel == 0) return false;
 
   if (U == Root)
     switch (U->getOpcode()) {
@@ -512,7 +512,7 @@
 
 
 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
-/// This is only run if not in -fast mode (aka -O0).
+/// This is only run if not in -O0 mode.
 /// This allows the instruction selector to pick more read-modify-write
 /// instructions. This is a common case:
 ///
@@ -714,10 +714,10 @@
   OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
 
   DEBUG(BB->dump());
-  if (!Fast)
+  if (OptLevel != 0)
     PreprocessForRMW();
 
-  // FIXME: This should only happen when not -fast.
+  // FIXME: This should only happen when not compiled with -O0.
   PreprocessForFPConvert();
 
   // Codegen the basic block.
@@ -1744,6 +1744,6 @@
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
-  return new X86DAGToDAGISel(TM, Fast);
+FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned OptLevel) {
+  return new X86DAGToDAGISel(TM, OptLevel);
 }

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Apr 27 19:21:31 2009
@@ -180,9 +180,9 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool X86TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
   // Install an instruction selector.
-  PM.add(createX86ISelDag(*this, Fast));
+  PM.add(createX86ISelDag(*this, OptLevel));
 
   // If we're using Fast-ISel, clean up the mess.
   if (EnableFastISel)
@@ -194,27 +194,29 @@
   return false;
 }
 
-bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, bool Fast) {
+bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
   // Calculate and set max stack object alignment early, so we can decide
   // whether we will need stack realignment (and thus FP).
   PM.add(createX86MaxStackAlignmentCalculatorPass());
   return false;  // -print-machineinstr shouldn't print after this.
 }
 
-bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, bool Fast) {
+bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
   PM.add(createX86FloatingPointStackifierPass());
   return true;  // -print-machineinstr should print after this.
 }
 
-bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
-                                          bool Verbose, raw_ostream &Out) {
+bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                          unsigned OptLevel,
+                                          bool Verbose,
+                                          raw_ostream &Out) {
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
   if (AsmPrinterCtor)
-    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
+    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
   return false;
 }
 
-bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
+bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // FIXME: Move this to TargetJITInfo!
   // On Darwin, do not override 64-bit setting made in X86TargetMachine().
@@ -236,19 +238,20 @@
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
   }
 
   return false;
 }
 
-bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
-                                        bool DumpAsm, MachineCodeEmitter &MCE) {
+bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+                                            unsigned OptLevel, bool DumpAsm,
+                                            MachineCodeEmitter &MCE) {
   PM.add(createX86CodeEmitterPass(*this, MCE));
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
   }
 
   return false;

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Mon Apr 27 19:21:31 2009
@@ -45,7 +45,7 @@
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             X86TargetMachine &tm,
-                                            bool fast, bool verbose);
+                                            unsigned OptLevel, bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -74,14 +74,14 @@
   }
 
   // Set up the pass pipeline.
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addPreRegAlloc(PassManagerBase &PM, bool Fast);
-  virtual bool addPostRegAlloc(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
 
   /// symbolicAddressesAreRIPRel - Return true if symbolic addresses are

Modified: llvm/trunk/lib/Target/XCore/XCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCore.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCore.h (original)
+++ llvm/trunk/lib/Target/XCore/XCore.h Mon Apr 27 19:21:31 2009
@@ -24,7 +24,7 @@
   FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
   FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
                                            XCoreTargetMachine &TM,
-                                           bool Fast, bool Verbose);
+                                           unsigned OptLevel, bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for XCore registers.  This defines a mapping from

Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Mon Apr 27 19:21:31 2009
@@ -58,8 +58,8 @@
     const XCoreSubtarget &Subtarget;
   public:
     XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
-                    const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V), DW(0),
+                    const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V), DW(0),
         Subtarget(*TM.getSubtargetImpl()) {}
 
     virtual const char *getPassName() const {
@@ -105,8 +105,9 @@
 ///
 FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
                                                XCoreTargetMachine &tm,
-                                               bool fast, bool verbose) {
-  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                               unsigned OptLevel,
+                                               bool verbose) {
+  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 
 // PrintEscapedString - Print each character of the specified string, escaping

Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Mon Apr 27 19:21:31 2009
@@ -55,14 +55,17 @@
   return 0;
 }
 
-bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
+                                         unsigned OptLevel) {
   PM.add(createXCoreISelDag(*this));
   return false;
 }
 
-bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
-                                            bool Verbose, raw_ostream &Out) {
+bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                            unsigned OptLevel,
+                                            bool Verbose,
+                                            raw_ostream &Out) {
   // Output assembly language.
-  PM.add(createXCoreCodePrinterPass(Out, *this, Fast, Verbose));
+  PM.add(createXCoreCodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }

Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Mon Apr 27 19:21:31 2009
@@ -52,8 +52,8 @@
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                                   bool Verbose, raw_ostream &Out);
 };
 

Modified: llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll Mon Apr 27 19:21:31 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast
+; RUN: llvm-as < %s | llc -O0
 
 define float @test(i32 %tmp12771278) {
         switch i32 %tmp12771278, label %bb1279 [

Modified: llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll Mon Apr 27 19:21:31 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast
+; RUN: llvm-as < %s | llc -O0
 	
 %struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32 }
 @cl_pf_opts = external global %struct.cl_perfunc_opts		; <%struct.cl_perfunc_opts*> [#uses=2]

Modified: llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll Mon Apr 27 19:21:31 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast
+; RUN: llvm-as < %s | llc -O0
 ; PR 1323
 
 ; ModuleID = 'test.bc'

Modified: llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll Mon Apr 27 19:21:31 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -fast -relocation-model=pic -o -
+; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o -
 ; PR1638
 
 @.str242 = external constant [3 x i8]		; <[3 x i8]*> [#uses=1]

Modified: llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll Mon Apr 27 19:21:31 2009
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -fast -regalloc=local
+; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local
 
 	%struct.CGPoint = type { double, double }
 	%struct.NSArray = type { %struct.NSObject }

Modified: llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll Mon Apr 27 19:21:31 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -fast -fast-isel=false | grep mov | count 5
+; RUN: llvm-as < %s | llc -march=x86 -O0 -fast-isel=false | grep mov | count 5
 ; PR2343
 
 	%llvm.dbg.anchor.type = type { i32, i32 }

Modified: llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll Mon Apr 27 19:21:31 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0
 
 define fastcc void @optimize_bit_field() nounwind {
 bb4:

Modified: llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll Mon Apr 27 19:21:31 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast -regalloc=local | not grep sil
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil
 ; rdar://6787136
 
 	%struct.X = type { i8, [32 x i8] }

Modified: llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/add-with-overflow.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/add-with-overflow.ll (original)
+++ llvm/trunk/test/CodeGen/X86/add-with-overflow.ll Mon Apr 27 19:21:31 2009
@@ -1,7 +1,7 @@
 ; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 2
 ; RUN: llvm-as < %s | llc -march=x86 | grep {jb} | count 2
-; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jo} | count 2
-; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jb} | count 2
+; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jo} | count 2
+; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jb} | count 2
 
 @ok = internal constant [4 x i8] c"%d\0A\00"
 @no = internal constant [4 x i8] c"no\0A\00"

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll Mon Apr 27 19:21:31 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -fast
+; RUN: llvm-as < %s | llc -march=x86 -O0
 
 ; This file is for regression tests for cases where FastISel needs
 ; to gracefully bail out and let SelectionDAGISel take over.

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll Mon Apr 27 19:21:31 2009
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -fast | grep movslq
-; RUN: llvm-as < %s | llc -march=x86 -fast
+; RUN: llvm-as < %s | llc -march=x86-64 -O0 | grep movslq
+; RUN: llvm-as < %s | llc -march=x86 -O0
 ; PR3181
 
 ; GEP indices are interpreted as signed integers, so they

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll Mon Apr 27 19:21:31 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -fast | grep {sarl	\$80, %eax}
+; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {sarl	\$80, %eax}
 ; PR3242
 
 define i32 @foo(i32 %x) nounwind {

Modified: llvm/trunk/test/CodeGen/X86/pr1489.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr1489.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr1489.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr1489.ll Mon Apr 27 19:21:31 2009
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 1082126238 | count 3
-; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 3058016715 | count 1
+; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 1082126238 | count 3
+; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 3058016715 | count 1
 ;; magic constants are 3.999f and half of 3.999
 ; ModuleID = '1489.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"

Modified: llvm/trunk/test/CodeGen/X86/volatile.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/volatile.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/volatile.ll (original)
+++ llvm/trunk/test/CodeGen/X86/volatile.ll Mon Apr 27 19:21:31 2009
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 | grep movsd | count 5
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -fast | grep movsd | count 5
+; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -O0 | grep movsd | count 5
 
 @x = external global double
 

Modified: llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll (original)
+++ llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll Mon Apr 27 19:21:31 2009
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc
-; RUN: llvm-as < %s | llc -fast
+; RUN: llvm-as < %s | llc -O0
 	%llvm.dbg.anchor.type = type { i32, i32 }
 	%llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 }
 	%llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8* }

Modified: llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-30-Method.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/2009-01-30-Method.ll (original)
+++ llvm/trunk/test/DebugInfo/2009-01-30-Method.ll Mon Apr 27 19:21:31 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast | grep "\\"foo" | count 3
+; RUN: llvm-as < %s | llc -O0 | grep "\\"foo" | count 3
 ; 1 declaration, 1 definition and 1 pubnames entry.
 target triple = "i386-apple-darwin*"
 	%llvm.dbg.anchor.type = type { i32, i32 }

Modified: llvm/trunk/test/DebugInfo/deaddebuglabel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/deaddebuglabel.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/deaddebuglabel.ll (original)
+++ llvm/trunk/test/DebugInfo/deaddebuglabel.ll Mon Apr 27 19:21:31 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast | grep "label" | count 8
+; RUN: llvm-as < %s | llc -O0 | grep "label" | count 8
 ; PR2614
 ; XFAIL: *
 

Modified: llvm/trunk/test/DebugInfo/forwardDecl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/forwardDecl.ll?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/forwardDecl.ll (original)
+++ llvm/trunk/test/DebugInfo/forwardDecl.ll Mon Apr 27 19:21:31 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast | %prcontext ST 1 | grep 0x1 | count 1
+; RUN: llvm-as < %s | llc -O0 | %prcontext ST 1 | grep 0x1 | count 1
 
 target triple = "i386-apple-darwin9.6"
 	%llvm.dbg.anchor.type = type { i32, i32 }

Modified: llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-06-StackTrace.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp Mon Apr 27 19:21:31 2009
@@ -1,7 +1,7 @@
 // This is a regression test on debug info to make sure that we can get a
 // meaningful stack trace from a C++ program.
 // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
-// RUN:    llc --disable-fp-elim -o %t.s -f -fast -relocation-model=pic
+// RUN:    llc --disable-fp-elim -o %t.s -f -O0 -relocation-model=pic
 // RUN: %compile_c %t.s -o %t.o
 // RUN: %link %t.o -o %t.exe
 // RUN: echo {break DeepStack::deepest\nrun 17\nwhere\n} > %t.in 

Modified: llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-30-Pubnames.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp Mon Apr 27 19:21:31 2009
@@ -1,7 +1,7 @@
 // This is a regression test on debug info to make sure that we can access 
 // qualified global names.
 // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
-// RUN:   llc --disable-fp-elim -o %t.s -f -fast
+// RUN:   llc --disable-fp-elim -o %t.s -f -O0
 // RUN: %compile_c %t.s -o %t.o
 // RUN: %link %t.o -o %t.exe
 // RUN: %llvmdsymutil %t.exe 

Modified: llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-04-21-DtorNames-dbg.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp Mon Apr 27 19:21:31 2009
@@ -1,4 +1,4 @@
-// RUN: %llvmgcc -c -g %s -o - | llc -fast -f -o %t.s
+// RUN: %llvmgcc -c -g %s -o - | llc -O0 -f -o %t.s
 // RUN: %compile_c %t.s -o %t.o
 // PR4025
 

Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Mon Apr 27 19:21:31 2009
@@ -55,8 +55,13 @@
 
 static cl::opt<bool> Force("f", cl::desc("Overwrite output files"));
 
-static cl::opt<bool> Fast("fast",
-      cl::desc("Generate code quickly, potentially sacrificing code quality"));
+// Determine optimization level. Level -O0 is equivalent to "fast" code gen.
+static cl::opt<unsigned>
+OptLevel("O",
+         cl::desc("Optimization level. Similar to llvm-gcc -O. (default: -O3)"),
+         cl::Prefix,
+         cl::ZeroOrMore,
+         cl::init(3));
 
 static cl::opt<std::string>
 TargetTriple("mtriple", cl::desc("Override target triple for module"));
@@ -257,7 +262,7 @@
       PM.add(createVerifierPass());
 
     // Ask the target to add backend passes as necessary.
-    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, Fast)) {
+    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OptLevel)) {
       std::cerr << argv[0] << ": target does not support generation of this"
                 << " file type!\n";
       if (Out != &outs()) delete Out;
@@ -283,7 +288,7 @@
     // Override default to generate verbose assembly.
     Target.setAsmVerbosityDefault(true);
 
-    switch (Target.addPassesToEmitFile(Passes, *Out, FileType, Fast)) {
+    switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OptLevel)) {
     default:
       assert(0 && "Invalid file model!");
       return 1;
@@ -304,7 +309,7 @@
       break;
     }
 
-    if (Target.addPassesToEmitFileFinish(Passes, MCE, Fast)) {
+    if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) {
       std::cerr << argv[0] << ": target does not support generation of this"
                 << " file type!\n";
       if (Out != &outs()) delete Out;

Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Mon Apr 27 19:21:31 2009
@@ -650,7 +650,7 @@
   O << "\";\n\n";
 
   O << "  if (TAI->doesSupportDebugInformation() &&\n"
-    << "      DW->ShouldEmitDwarfDebug() && !Fast) {\n"
+    << "      DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n"
     << "    DebugLoc CurDL = MI->getDebugLoc();\n\n"
     << "    if (!CurDL.isUnknown()) {\n"
     << "      static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n"

Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=70270&r1=70269&r2=70270&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Apr 27 19:21:31 2009
@@ -465,7 +465,7 @@
       NumInputRootOps = N->getNumChildren();
 
       if (DisablePatternForFastISel(N, CGP))
-        emitCheck("!Fast");
+        emitCheck("OptLevel != 0");
 
       emitCheck(PredicateCheck);
     }




From evan.cheng at apple.com  Mon Apr 27 19:30:25 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Apr 2009 17:30:25 -0700
Subject: [llvm-commits] [llvm] r70270 - in /llvm/trunk:
	include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/
	lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/
	lib/Target/Alpha/AsmPrinter/ lib/Target/CBackend/
	lib/Target/CellSPU/ lib/Target/CellSPU/AsmPrinter/
	lib/Target/CppBackend/ lib/Target/IA64/
	lib/Target/IA64/AsmPrinter/ lib/Target/MSIL/ lib/Target/Mips/
	lib/Target/Mips/AsmPrinter/ lib/Target/PIC16/
	lib/Target/PowerPC/ lib/Target/PowerPC/AsmPrinter/ lib/Target...
In-Reply-To: <200904280021.n3S0LdXU027640@zion.cs.uiuc.edu>
References: <200904280021.n3S0LdXU027640@zion.cs.uiuc.edu>
Message-ID: <F4CEA21C-BE09-4BC0-B05F-ADC60A5397BC@apple.com>

Thanks. How about libLTO?

Also, JIT (calls to TM.addPassesToEmitMachineCode and lli.cpp) has to  
be changed as well.

Evan

On Apr 27, 2009, at 5:21 PM, Bill Wendling wrote:

> Author: void
> Date: Mon Apr 27 19:21:31 2009
> New Revision: 70270
>
> URL: http://llvm.org/viewvc/llvm-project?rev=70270&view=rev
> Log:
> Massive check in. This changes the "-fast" flag to "-O#" in llc. If  
> you want to
> use the old behavior, the flag is -O0. This change allows for finer- 
> grained
> control over which optimizations are run at different -O levels.
>
> Most of this work was pretty mechanical. The majority of the fixes  
> came from
> verifying that a "fast" variable wasn't used anymore. The JIT still  
> uses a
> "Fast" flag. I'm not 100% sure if it's necessary to change it there...
>
> Modified:
>    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
>    llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
>    llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>    llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
>    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
>    llvm/trunk/include/llvm/Target/TargetMachine.h
>    llvm/trunk/include/llvm/Target/TargetOptions.h
>    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
>    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
>    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>    llvm/trunk/lib/Target/ARM/ARM.h
>    llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
>    llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
>    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>    llvm/trunk/lib/Target/Alpha/Alpha.h
>    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
>    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
>    llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>    llvm/trunk/lib/Target/CBackend/CBackend.cpp
>    llvm/trunk/lib/Target/CBackend/CTargetMachine.h
>    llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>    llvm/trunk/lib/Target/CellSPU/SPU.h
>    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
>    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
>    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
>    llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
>    llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>    llvm/trunk/lib/Target/IA64/IA64.h
>    llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
>    llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
>    llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
>    llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>    llvm/trunk/lib/Target/Mips/Mips.h
>    llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
>    llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
>    llvm/trunk/lib/Target/PIC16/PIC16.h
>    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
>    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
>    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
>    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
>    llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>    llvm/trunk/lib/Target/PowerPC/PPC.h
>    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
>    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
>    llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
>    llvm/trunk/lib/Target/Sparc/Sparc.h
>    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
>    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
>    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
>    llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
>    llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
>    llvm/trunk/lib/Target/X86/X86.h
>    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
>    llvm/trunk/lib/Target/X86/X86TargetMachine.h
>    llvm/trunk/lib/Target/XCore/XCore.h
>    llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
>    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
>    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
>    llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
>    llvm/trunk/test/CodeGen/Generic/2006-06-13- 
> ComputeMaskedBitsCrash.ll
>    llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
>    llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
>    llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
>    llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
>    llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
>    llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
>    llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
>    llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
>    llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
>    llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
>    llvm/trunk/test/CodeGen/X86/pr1489.ll
>    llvm/trunk/test/CodeGen/X86/volatile.ll
>    llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
>    llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
>    llvm/trunk/test/DebugInfo/deaddebuglabel.ll
>    llvm/trunk/test/DebugInfo/forwardDecl.ll
>    llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
>    llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
>    llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
>    llvm/trunk/tools/llc/llc.cpp
>    llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
>    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Mon Apr 27 19:21:31  
> 2009
> @@ -65,8 +65,8 @@
>     // Necessary for external weak linkage support
>     std::set<const GlobalValue*> ExtWeakSymbols;
>
> -    /// Fast - Generating code via fast instruction selection.
> -    bool Fast;
> +    /// OptLevel - Generating code at a specific optimization level.
> +    unsigned OptLevel;
>   public:
>     /// Output stream on which we're printing assembly code.
>     ///
> @@ -110,8 +110,8 @@
>     bool VerboseAsm;
>
>   protected:
> -    AsmPrinter(raw_ostream &o, TargetMachine &TM,
> -               const TargetAsmInfo *T, bool F, bool V);
> +    explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
> +                        const TargetAsmInfo *T, unsigned OL, bool V);
>
>   public:
>     virtual ~AsmPrinter();
>
> Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Mon Apr 27  
> 19:21:31 2009
> @@ -81,7 +81,7 @@
>   void EndFunction(MachineFunction *MF);
>
>   /// ValidDebugInfo - Return true if V represents valid debug info  
> value.
> -  bool ValidDebugInfo(Value *V, bool FastISel);
> +  bool ValidDebugInfo(Value *V, unsigned OptLevel);
>
>   /// RecordSourceLine - Register a source line with debug info.  
> Returns a
>   /// unique label ID used to generate a label and provide  
> correspondence to
>
> Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h  
> (original)
> +++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Mon  
> Apr 27 19:21:31 2009
> @@ -42,11 +42,11 @@
>       llvm::linkOcamlGC();
>       llvm::linkShadowStackGC();
>
> -      (void) llvm::createBURRListDAGScheduler(NULL, false);
> -      (void) llvm::createTDRRListDAGScheduler(NULL, false);
> -      (void) llvm::createTDListDAGScheduler(NULL, false);
> -      (void) llvm::createFastDAGScheduler(NULL, false);
> -      (void) llvm::createDefaultScheduler(NULL, false);
> +      (void) llvm::createBURRListDAGScheduler(NULL, 3);
> +      (void) llvm::createTDRRListDAGScheduler(NULL, 3);
> +      (void) llvm::createTDListDAGScheduler(NULL, 3);
> +      (void) llvm::createFastDAGScheduler(NULL, 3);
> +      (void) llvm::createDefaultScheduler(NULL, 3);
>
>     }
>   } ForceCodegenLinking; // Force link by creating a global  
> definition.
>
> Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Mon Apr 27  
> 19:21:31 2009
> @@ -32,7 +32,7 @@
>
> class RegisterScheduler : public MachinePassRegistryNode {
> public:
> -  typedef ScheduleDAGSDNodes *(*FunctionPassCtor) 
> (SelectionDAGISel*, bool);
> +  typedef ScheduleDAGSDNodes *(*FunctionPassCtor) 
> (SelectionDAGISel*, unsigned);
>
>   static MachinePassRegistry Registry;
>
> @@ -64,27 +64,27 @@
> /// createBURRListDAGScheduler - This creates a bottom up register  
> usage
> /// reduction list scheduler.
> ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
> -                                               bool Fast);
> +                                               unsigned OptLevel);
>
> /// createTDRRListDAGScheduler - This creates a top down register  
> usage
> /// reduction list scheduler.
> ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
> -                                               bool Fast);
> +                                               unsigned OptLevel);
>
> /// createTDListDAGScheduler - This creates a top-down list  
> scheduler with
> /// a hazard recognizer.
> ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
> -                                             bool Fast);
> +                                             unsigned OptLevel);
>
> /// createFastDAGScheduler - This creates a "fast" scheduler.
> ///
> ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
> -                                           bool Fast);
> +                                           unsigned OptLevel);
>
> /// createDefaultScheduler - This creates an instruction scheduler  
> appropriate
> /// for the target.
> ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
> -                                           bool Fast);
> +                                           unsigned OptLevel);
>
> } // end namespace llvm
>
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Apr 27  
> 19:21:31 2009
> @@ -202,7 +202,7 @@
>   /// certain types of nodes together, or eliminating superfluous  
> nodes.  The
>   /// Level argument controls whether Combine is allowed to produce  
> nodes and
>   /// types that are illegal on the target.
> -  void Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast);
> +  void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned  
> OptLevel);
>
>   /// LegalizeTypes - This transforms the SelectionDAG into a  
> SelectionDAG that
>   /// only uses types natively supported by the target.  Returns  
> "true" if it
> @@ -218,7 +218,7 @@
>   ///
>   /// Note that this is an involved process that may invalidate  
> pointers into
>   /// the graph.
> -  void Legalize(bool TypesNeedLegalizing, bool Fast);
> +  void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
>
>   /// RemoveDeadNodes - This method deletes all unreachable nodes in  
> the
>   /// SelectionDAG.
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Mon Apr 27  
> 19:21:31 2009
> @@ -51,10 +51,10 @@
>   MachineBasicBlock *BB;
>   AliasAnalysis *AA;
>   GCFunctionInfo *GFI;
> -  bool Fast;
> +  unsigned OptLevel;
>   static char ID;
>
> -  explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
> +  explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
>   virtual ~SelectionDAGISel();
>
>   TargetLowering &getTargetLowering() { return TLI; }
>
> Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetMachine.h Mon Apr 27  
> 19:21:31 2009
> @@ -213,7 +213,7 @@
>   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
>                                                raw_ostream &,
>                                                CodeGenFileType,
> -                                               bool /*Fast*/) {
> +                                               unsigned /* OptLevel  
> */) {
>     return FileModel::None;
>   }
>
> @@ -222,7 +222,8 @@
>   /// used to finish up adding passes to emit the file, if necessary.
>   ///
>   virtual bool addPassesToEmitFileFinish(PassManagerBase &,
> -                                         MachineCodeEmitter *,  
> bool /*Fast*/) {
> +                                         MachineCodeEmitter *,
> +                                         unsigned /* OptLevel */) {
>     return true;
>   }
>
> @@ -234,7 +235,7 @@
>   ///
>   virtual bool addPassesToEmitMachineCode(PassManagerBase &,
>                                           MachineCodeEmitter &,
> -                                          bool /*Fast*/) {
> +                                          unsigned /* OptLevel */) {
>     return true;
>   }
>
> @@ -243,7 +244,8 @@
>   /// use this.
>   virtual bool WantsWholeFile() const { return false; }
>   virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
> -                                        CodeGenFileType, bool / 
> *Fast*/) {
> +                                        CodeGenFileType,
> +                                        unsigned /* OptLevel */) {
>     return true;
>   }
> };
> @@ -258,16 +260,16 @@
>   /// addCommonCodeGenPasses - Add standard LLVM codegen passes used  
> for
>   /// both emitting to assembly files or machine code output.
>   ///
> -  bool addCommonCodeGenPasses(PassManagerBase &, bool /*Fast*/);
> +  bool addCommonCodeGenPasses(PassManagerBase &, unsigned /*  
> OptLevel */);
>
> public:
>
>   /// addPassesToEmitFile - Add passes to the specified pass manager  
> to get the
>   /// specified file emitted.  Typically this will involve several  
> steps of code
> -  /// generation.  If Fast is set to true, the code generator  
> should emit code
> -  /// as fast as possible, though the generated code may be less  
> efficient.
> -  /// This method should return FileModel::Error if emission of  
> this file type
> -  /// is not supported.
> +  /// generation.  If OptLevel is 0, the code generator should emit  
> code as fast
> +  /// as possible, though the generated code may be less  
> efficient.  This method
> +  /// should return FileModel::Error if emission of this file type  
> is not
> +  /// supported.
>   ///
>   /// The default implementation of this method adds components from  
> the
>   /// LLVM retargetable code generator, invoking the methods below  
> to get
> @@ -276,14 +278,15 @@
>   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
>                                                raw_ostream &Out,
>                                                CodeGenFileType  
> FileType,
> -                                               bool Fast);
> +                                               unsigned OptLevel);
>
>   /// addPassesToEmitFileFinish - If the passes to emit the  
> specified file had
>   /// to be split up (e.g., to add an object writer pass), this  
> method can be
>   /// used to finish up adding passes to emit the file, if necessary.
>   ///
>   virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
> -                                         MachineCodeEmitter *MCE,  
> bool Fast);
> +                                         MachineCodeEmitter *MCE,
> +                                         unsigned OptLevel);
>
>   /// addPassesToEmitMachineCode - Add passes to the specified pass  
> manager to
>   /// get machine code emitted.  This uses a MachineCodeEmitter  
> object to handle
> @@ -292,21 +295,22 @@
>   /// not supported.
>   ///
>   virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
> -                                          MachineCodeEmitter &MCE,  
> bool Fast);
> +                                          MachineCodeEmitter &MCE,
> +                                          unsigned OptLevel);
>
>   /// Target-Independent Code Generator Pass Configuration Options.
>
>   /// addInstSelector - This method should add any "last minute"  
> LLVM->LLVM
>   /// passes, then install an instruction selector pass, which  
> converts from
>   /// LLVM code to machine instructions.
> -  virtual bool addInstSelector(PassManagerBase &, bool /*Fast*/) {
> +  virtual bool addInstSelector(PassManagerBase &, unsigned /*  
> OptLevel */) {
>     return true;
>   }
>
>   /// addPreRegAllocPasses - This method may be implemented by  
> targets that want
>   /// to run passes immediately before register allocation. This  
> should return
>   /// true if -print-machineinstrs should print after these passes.
> -  virtual bool addPreRegAlloc(PassManagerBase &, bool /*Fast*/) {
> +  virtual bool addPreRegAlloc(PassManagerBase &, unsigned /*  
> OptLevel */) {
>     return false;
>   }
>
> @@ -314,14 +318,14 @@
>   /// want to run passes after register allocation but before prolog- 
> epilog
>   /// insertion.  This should return true if -print-machineinstrs  
> should print
>   /// after these passes.
> -  virtual bool addPostRegAlloc(PassManagerBase &, bool /*Fast*/) {
> +  virtual bool addPostRegAlloc(PassManagerBase &, unsigned /*  
> OptLevel */) {
>     return false;
>   }
>
>   /// addPreEmitPass - This pass may be implemented by targets that  
> want to run
>   /// passes immediately before machine code is emitted.  This  
> should return
>   /// true if -print-machineinstrs should print out the code after  
> the passes.
> -  virtual bool addPreEmitPass(PassManagerBase &, bool /*Fast*/) {
> +  virtual bool addPreEmitPass(PassManagerBase &, unsigned /*  
> OptLevel */) {
>     return false;
>   }
>
> @@ -329,7 +333,7 @@
>   /// addAssemblyEmitter - This pass should be overridden by the  
> target to add
>   /// the asmprinter, if asm emission is supported.  If this is not  
> supported,
>   /// 'true' should be returned.
> -  virtual bool addAssemblyEmitter(PassManagerBase &, bool /*Fast*/,
> +  virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /*  
> OptLevel */,
>                                   bool /* VerboseAsmDefault */,  
> raw_ostream &) {
>     return true;
>   }
> @@ -337,7 +341,7 @@
>   /// addCodeEmitter - This pass should be overridden by the target  
> to add a
>   /// code emitter, if supported.  If this is not supported, 'true'  
> should be
>   /// returned. If DumpAsm is true, the generated assembly is  
> printed to cerr.
> -  virtual bool addCodeEmitter(PassManagerBase &, bool /*Fast*/,
> +  virtual bool addCodeEmitter(PassManagerBase &, unsigned /*  
> OptLevel */,
>                               bool /*DumpAsm*/, MachineCodeEmitter  
> &) {
>     return true;
>   }
> @@ -346,7 +350,7 @@
>   /// a code emitter (without setting flags), if supported.  If this  
> is not
>   /// supported, 'true' should be returned.  If DumpAsm is true, the  
> generated
>   /// assembly is printed to cerr.
> -  virtual bool addSimpleCodeEmitter(PassManagerBase &, bool /*Fast*/,
> +  virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /*  
> OptLevel */,
>                                     bool /*DumpAsm*/,  
> MachineCodeEmitter &) {
>     return true;
>   }
>
> Modified: llvm/trunk/include/llvm/Target/TargetOptions.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/Target/TargetOptions.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetOptions.h Mon Apr 27  
> 19:21:31 2009
> @@ -108,7 +108,7 @@
>   /// generated.
>   extern bool DisableJumpTables;
>
> -  /// FastISel - This flag enables fast-path instruction selection
> +  /// EnableFastISel - This flag enables fast-path instruction  
> selection
>   /// which trades away generated code quality in favor of reducing
>   /// compile time.
>   extern bool EnableFastISel;
>
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -42,8 +42,8 @@
>
> char AsmPrinter::ID = 0;
> AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
> -                       const TargetAsmInfo *T, bool F, bool VDef)
> -  : MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o),
> +                       const TargetAsmInfo *T, unsigned OL, bool  
> VDef)
> +  : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
>     TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
>     IsInTextSection(false)
> {
>
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -3351,7 +3351,7 @@
>   }
>
>   /// ValidDebugInfo - Return true if V represents valid debug info  
> value.
> -  bool ValidDebugInfo(Value *V, bool FastISel) {
> +  bool ValidDebugInfo(Value *V, unsigned OptLevel) {
>     if (!V)
>       return false;
>
> @@ -3393,7 +3393,7 @@
>     case DW_TAG_lexical_block:
>       /// FIXME. This interfers with the qualitfy of generated code  
> when
>       /// during optimization.
> -      if (FastISel == false)
> +      if (OptLevel != 0)
>         return false;
>     default:
>       break;
> @@ -4730,8 +4730,8 @@
> }
>
> /// ValidDebugInfo - Return true if V represents valid debug info  
> value.
> -bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) {
> -  return DD && DD->ValidDebugInfo(V, FastISel);
> +bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
> +  return DD && DD->ValidDebugInfo(V, OptLevel);
> }
>
> /// RecordSourceLine - Records location information and associates  
> it with a
>
> Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Mon Apr 27 19:21:31  
> 2009
> @@ -55,9 +55,9 @@
> LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
>                                        raw_ostream &Out,
>                                        CodeGenFileType FileType,
> -                                       bool Fast) {
> +                                       unsigned OptLevel) {
>   // Add common CodeGen passes.
> -  if (addCommonCodeGenPasses(PM, Fast))
> +  if (addCommonCodeGenPasses(PM, OptLevel))
>     return FileModel::Error;
>
>   // Fold redundant debug labels.
> @@ -66,17 +66,17 @@
>   if (PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
> -  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
> +  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
> -  if (!Fast)
> +  if (OptLevel != 0)
>     PM.add(createLoopAlignerPass());
>
>   switch (FileType) {
>   default:
>     break;
>   case TargetMachine::AssemblyFile:
> -    if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(), Out))
> +    if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(),  
> Out))
>       return FileModel::Error;
>     return FileModel::AsmFile;
>   case TargetMachine::ObjectFile:
> @@ -94,9 +94,9 @@
> /// finish up adding passes to emit the file, if necessary.
> bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
>                                                   MachineCodeEmitter  
> *MCE,
> -                                                  bool Fast) {
> +                                                  unsigned  
> OptLevel) {
>   if (MCE)
> -    addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
> +    addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
>
>   PM.add(createGCInfoDeleter());
>
> @@ -114,15 +114,15 @@
> ///
> bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase  
> &PM,
>                                                     
> MachineCodeEmitter &MCE,
> -                                                   bool Fast) {
> +                                                   unsigned  
> OptLevel) {
>   // Add common CodeGen passes.
> -  if (addCommonCodeGenPasses(PM, Fast))
> +  if (addCommonCodeGenPasses(PM, OptLevel))
>     return true;
>
> -  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
> +  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
> -  addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
> +  addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
>
>   PM.add(createGCInfoDeleter());
>
> @@ -135,11 +135,12 @@
> /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
> /// both emitting to assembly files or machine code output.
> ///
> -bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,  
> bool Fast) {
> +bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
> +                                               unsigned OptLevel) {
>   // Standard LLVM-Level Passes.
>
>   // Run loop strength reduction before anything else.
> -  if (!Fast) {
> +  if (OptLevel != 0) {
>     PM.add(createLoopStrengthReducePass(getTargetLowering()));
>     if (PrintLSR)
>       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n",  
> &errs()));
> @@ -153,7 +154,7 @@
>   // Make sure that no unreachable blocks are instruction selected.
>   PM.add(createUnreachableBlockEliminationPass());
>
> -  if (!Fast)
> +  if (OptLevel != 0)
>     PM.add(createCodeGenPreparePass(getTargetLowering()));
>
>   PM.add(createStackProtectorPass(getTargetLowering()));
> @@ -167,38 +168,38 @@
>
>   // Enable FastISel with -fast, but allow that to be overridden.
>   if (EnableFastISelOption == cl::BOU_TRUE ||
> -      (Fast && EnableFastISelOption != cl::BOU_FALSE))
> +      (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
>     EnableFastISel = true;
>
>   // Ask the target for an isel.
> -  if (addInstSelector(PM, Fast))
> +  if (addInstSelector(PM, OptLevel))
>     return true;
>
>   // Print the instruction selected machine code...
>   if (PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
> -  if (!Fast) {
> +  if (OptLevel != 0) {
>     PM.add(createMachineLICMPass());
>     PM.add(createMachineSinkingPass());
>   }
>
>   // Run pre-ra passes.
> -  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
> +  if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
>   // Perform register allocation.
>   PM.add(createRegisterAllocator());
>
>   // Perform stack slot coloring.
> -  if (!Fast)
> +  if (OptLevel != 0)
>     PM.add(createStackSlotColoringPass());
>
>   if (PrintMachineCode)  // Print the register-allocated code
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
>   // Run post-ra passes.
> -  if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
> +  if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
>   if (PrintMachineCode)
> @@ -216,7 +217,7 @@
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
>   // Second pass scheduler.
> -  if (!Fast && !DisablePostRAScheduler) {
> +  if (OptLevel != 0 && !DisablePostRAScheduler) {
>     PM.add(createPostRAScheduler());
>
>     if (PrintMachineCode)
> @@ -224,7 +225,7 @@
>   }
>
>   // Branch folding must be run after regalloc and prolog/epilog  
> insertion.
> -  if (!Fast)
> +  if (OptLevel != 0)
>     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
>
>   if (PrintMachineCode)
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -57,9 +57,9 @@
>     SelectionDAG &DAG;
>     const TargetLowering &TLI;
>     CombineLevel Level;
> +    unsigned OptLevel;
>     bool LegalOperations;
>     bool LegalTypes;
> -    bool Fast;
>
>     // Worklist of all of the nodes that need to be simplified.
>     std::vector<SDNode*> WorkList;
> @@ -254,13 +254,13 @@
>     }
>
> public:
> -    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
> +    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
>       : DAG(D),
>         TLI(D.getTargetLoweringInfo()),
>         Level(Unrestricted),
> +        OptLevel(OL),
>         LegalOperations(false),
>         LegalTypes(false),
> -        Fast(fast),
>         AA(A) {}
>
>     /// Run - runs the dag combiner on all nodes in the work list
> @@ -4784,7 +4784,7 @@
>   SDValue Ptr   = LD->getBasePtr();
>
>   // Try to infer better alignment information than the load already  
> has.
> -  if (!Fast && LD->isUnindexed()) {
> +  if (OptLevel != 0 && LD->isUnindexed()) {
>     if (unsigned Align = InferAlignment(Ptr, DAG)) {
>       if (Align > LD->getAlignment())
>         return DAG.getExtLoad(LD->getExtensionType(), N- 
> >getDebugLoc(),
> @@ -4904,7 +4904,7 @@
>   SDValue Ptr   = ST->getBasePtr();
>
>   // Try to infer better alignment information than the store  
> already has.
> -  if (!Fast && ST->isUnindexed()) {
> +  if (OptLevel != 0 && ST->isUnindexed()) {
>     if (unsigned Align = InferAlignment(Ptr, DAG)) {
>       if (Align > ST->getAlignment())
>         return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
> @@ -6084,8 +6084,9 @@
>
> // SelectionDAG::Combine - This is the entry point for the file.
> //
> -void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,  
> bool Fast) {
> +void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
> +                           unsigned OptLevel) {
>   /// run - This is the main entry point to this class.
>   ///
> -  DAGCombiner(*this, AA, Fast).Run(Level);
> +  DAGCombiner(*this, AA, OptLevel).Run(Level);
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -327,7 +327,7 @@
>   default: break;
>   case Intrinsic::dbg_stoppoint: {
>     DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
> -    if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) {
> +    if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
>       DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
>       std::string Dir, FN;
>       unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
> @@ -344,7 +344,7 @@
>   }
>   case Intrinsic::dbg_region_start: {
>     DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
> -    if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) {
> +    if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
>       unsigned ID =
>         DW->RecordRegionStart(cast<GlobalVariable>(RSI- 
> >getContext()));
>       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
> @@ -354,7 +354,7 @@
>   }
>   case Intrinsic::dbg_region_end: {
>     DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
> -    if (DW && DW->ValidDebugInfo(REI->getContext(), true)) {
> +    if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
>      unsigned ID = 0;
>      DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
>      if (!Subprogram.isNull() && ! 
> Subprogram.describes(MF.getFunction())) {
> @@ -380,7 +380,7 @@
>     DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
>     Value *SP = FSI->getSubprogram();
>
> -    if (DW->ValidDebugInfo(SP, true)) {
> +    if (DW->ValidDebugInfo(SP, 0)) {
>       // llvm.dbg.func.start implicitly defines a dbg_stoppoint  
> which is what
>       // (most?) gdb expects.
>       DebugLoc PrevLoc = DL;
> @@ -425,7 +425,7 @@
>   case Intrinsic::dbg_declare: {
>     DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
>     Value *Variable = DI->getVariable();
> -    if (DW && DW->ValidDebugInfo(Variable, true)) {
> +    if (DW && DW->ValidDebugInfo(Variable, 0)) {
>       // Determine the address of the declared object.
>       Value *Address = DI->getAddress();
>       if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -55,8 +55,8 @@
> class VISIBILITY_HIDDEN SelectionDAGLegalize {
>   TargetLowering &TLI;
>   SelectionDAG &DAG;
> +  unsigned OptLevel;
>   bool TypesNeedLegalizing;
> -  bool Fast;
>
>   // Libcall insertion helpers.
>
> @@ -139,7 +139,7 @@
>
> public:
>   explicit SelectionDAGLegalize(SelectionDAG &DAG, bool  
> TypesNeedLegalizing,
> -                                bool fast);
> +                                unsigned ol);
>
>   /// getTypeAction - Return how we should legalize values of this  
> type, either
>   /// it is already legal or we need to expand it into multiple  
> registers of
> @@ -345,9 +345,9 @@
> }
>
> SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
> -                                           bool types, bool fast)
> -  : TLI(dag.getTargetLoweringInfo()), DAG(dag),  
> TypesNeedLegalizing(types),
> -    Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
> +                                           bool types, unsigned ol)
> +  : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
> +    TypesNeedLegalizing(types),  
> ValueTypeActions(TLI.getValueTypeActions()) {
>   assert(MVT::LAST_VALUETYPE <= 32 &&
>          "Too many value types for ValueTypeActions to hold!");
> }
> @@ -1271,7 +1271,7 @@
>         unsigned Line = DSP->getLine();
>         unsigned Col = DSP->getColumn();
>
> -        if (Fast) {
> +        if (OptLevel == 0) {
>           // A bit self-referential to have DebugLoc on Debug_Loc  
> nodes, but it
>           // won't hurt anything.
>           if (useDEBUG_LOC) {
> @@ -8566,9 +8566,9 @@
>
> // SelectionDAG::Legalize - This is the entry point for the file.
> //
> -void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
> +void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned  
> OptLevel) {
>   /// run - This is the main entry point to this class.
>   ///
> -  SelectionDAGLegalize(*this, TypesNeedLegalizing,  
> Fast).LegalizeDAG();
> +  SelectionDAGLegalize(*this, TypesNeedLegalizing,  
> OptLevel).LegalizeDAG();
> }
>
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Mon Apr  
> 27 19:21:31 2009
> @@ -630,6 +630,6 @@
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> llvm::ScheduleDAGSDNodes *
> -llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
> +llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
>   return new ScheduleDAGFast(*IS->MF);
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon Apr  
> 27 19:21:31 2009
> @@ -261,7 +261,7 @@
> /// new hazard recognizer. This scheduler takes ownership of the  
> hazard
> /// recognizer and deletes it when done.
> ScheduleDAGSDNodes *
> -llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) {
> +llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>   return new ScheduleDAGList(*IS->MF,
>                              new LatencyPriorityQueue(),
>                              IS->CreateTargetHazardRecognizer());
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon  
> Apr 27 19:21:31 2009
> @@ -1505,7 +1505,7 @@
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> llvm::ScheduleDAGSDNodes *
> -llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
> +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>   const TargetMachine &TM = IS->TM;
>   const TargetInstrInfo *TII = TM.getInstrInfo();
>   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
> @@ -1519,7 +1519,7 @@
> }
>
> llvm::ScheduleDAGSDNodes *
> -llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
> +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>   const TargetMachine &TM = IS->TM;
>   const TargetInstrInfo *TII = TM.getInstrInfo();
>   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon  
> Apr 27 19:21:31 2009
> @@ -3910,9 +3910,9 @@
>   case Intrinsic::dbg_stoppoint: {
>     DwarfWriter *DW = DAG.getDwarfWriter();
>     DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
> -    if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
> +    if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
>       MachineFunction &MF = DAG.getMachineFunction();
> -      if (Fast)
> +      if (OptLevel == 0)
>         DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
>                                         SPI.getLine(),
>                                         SPI.getColumn(),
> @@ -3930,7 +3930,8 @@
>   case Intrinsic::dbg_region_start: {
>     DwarfWriter *DW = DAG.getDwarfWriter();
>     DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
> -    if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
> +
> +    if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) {
>       unsigned LabelID =
>         DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
>       DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
> @@ -3942,8 +3943,8 @@
>   case Intrinsic::dbg_region_end: {
>     DwarfWriter *DW = DAG.getDwarfWriter();
>     DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
> -    if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
>
> +    if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) {
>       MachineFunction &MF = DAG.getMachineFunction();
>       DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
>       std::string SPName;
> @@ -3952,7 +3953,7 @@
>           && strcmp(SPName.c_str(), MF.getFunction()- 
> >getNameStart())) {
>           // This is end of inlined function. Debugging information  
> for
>           // inlined function is not handled yet (only supported by  
> FastISel).
> -        if (Fast) {
> +        if (OptLevel == 0) {
>           unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
>           if (ID != 0)
>             // Returned ID is 0 if this is unbalanced "end of inlined
> @@ -3978,9 +3979,9 @@
>     if (!DW) return 0;
>     DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
>     Value *SP = FSI.getSubprogram();
> -    if (SP && DW->ValidDebugInfo(SP, Fast)) {
> -        MachineFunction &MF = DAG.getMachineFunction();
> -      if (Fast) {
> +    if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
> +      MachineFunction &MF = DAG.getMachineFunction();
> +      if (OptLevel == 0) {
>         // llvm.dbg.func.start implicitly defines a dbg_stoppoint  
> which is what
>         // (most?) gdb expects.
>         DebugLoc PrevLoc = CurDebugLoc;
> @@ -4051,11 +4052,11 @@
>     return 0;
>   }
>   case Intrinsic::dbg_declare: {
> -    if (Fast) {
> +    if (OptLevel == 0) {
>       DwarfWriter *DW = DAG.getDwarfWriter();
>       DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
>       Value *Variable = DI.getVariable();
> -      if (DW && DW->ValidDebugInfo(Variable, Fast))
> +      if (DW && DW->ValidDebugInfo(Variable, OptLevel))
>         DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other,  
> getRoot(),
>                                 getValue(DI.getAddress()),  
> getValue(Variable)));
>     } else {
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Mon Apr  
> 27 19:21:31 2009
> @@ -355,17 +355,17 @@
>   ///
>   FunctionLoweringInfo &FuncInfo;
>
> -  /// Fast - We are in -fast mode.
> +  /// OptLevel - What optimization level we're generating code for.
>   ///
> -  bool Fast;
> +  unsigned OptLevel;
>
>   /// GFI - Garbage collection metadata for the function.
>   GCFunctionInfo *GFI;
>
>   SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
> -                       FunctionLoweringInfo &funcinfo, bool fast)
> +                       FunctionLoweringInfo &funcinfo, unsigned ol)
>     : CurDebugLoc(DebugLoc::getUnknownLoc()),
> -      TLI(tli), DAG(dag), FuncInfo(funcinfo), Fast(fast) {
> +      TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
>   }
>
>   void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr  
> 27 19:21:31 2009
> @@ -136,16 +136,16 @@
>   /// createDefaultScheduler - This creates an instruction scheduler  
> appropriate
>   /// for the target.
>   ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
> -                                             bool Fast) {
> +                                             unsigned OptLevel) {
>     const TargetLowering &TLI = IS->getTargetLowering();
>
> -    if (Fast)
> -      return createFastDAGScheduler(IS, Fast);
> +    if (OptLevel == 0)
> +      return createFastDAGScheduler(IS, OptLevel);
>     if (TLI.getSchedulingPreference() ==  
> TargetLowering::SchedulingForLatency)
> -      return createTDListDAGScheduler(IS, Fast);
> +      return createTDListDAGScheduler(IS, OptLevel);
>     assert(TLI.getSchedulingPreference() ==
>          TargetLowering::SchedulingForRegPressure && "Unknown sched  
> type!");
> -    return createBURRListDAGScheduler(IS, Fast);
> +    return createBURRListDAGScheduler(IS, OptLevel);
>   }
> }
>
> @@ -262,13 +262,13 @@
> // SelectionDAGISel code
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> -SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
> +SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
>   FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
>   FuncInfo(new FunctionLoweringInfo(TLI)),
>   CurDAG(new SelectionDAG(TLI, *FuncInfo)),
> -  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)),
> +  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)),
>   GFI(),
> -  Fast(fast),
> +  OptLevel(OL),
>   DAGSize(0)
> {}
>
> @@ -576,9 +576,9 @@
>   // Run the DAG combiner in pre-legalize mode.
>   if (TimePassesIsEnabled) {
>     NamedRegionTimer T("DAG Combining 1", GroupName);
> -    CurDAG->Combine(Unrestricted, *AA, Fast);
> +    CurDAG->Combine(Unrestricted, *AA, OptLevel);
>   } else {
> -    CurDAG->Combine(Unrestricted, *AA, Fast);
> +    CurDAG->Combine(Unrestricted, *AA, OptLevel);
>   }
>
>   DOUT << "Optimized lowered selection DAG:\n";
> @@ -608,9 +608,9 @@
>       // Run the DAG combiner in post-type-legalize mode.
>       if (TimePassesIsEnabled) {
>         NamedRegionTimer T("DAG Combining after legalize types",  
> GroupName);
> -        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
> +        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
>       } else {
> -        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
> +        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
>       }
>
>       DOUT << "Optimized type-legalized selection DAG:\n";
> @@ -622,9 +622,9 @@
>
>   if (TimePassesIsEnabled) {
>     NamedRegionTimer T("DAG Legalization", GroupName);
> -    CurDAG->Legalize(DisableLegalizeTypes, Fast);
> +    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
>   } else {
> -    CurDAG->Legalize(DisableLegalizeTypes, Fast);
> +    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
>   }
>
>   DOUT << "Legalized selection DAG:\n";
> @@ -635,9 +635,9 @@
>   // Run the DAG combiner in post-legalize mode.
>   if (TimePassesIsEnabled) {
>     NamedRegionTimer T("DAG Combining 2", GroupName);
> -    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
> +    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
>   } else {
> -    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
> +    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
>   }
>
>   DOUT << "Optimized legalized selection DAG:\n";
> @@ -645,7 +645,7 @@
>
>   if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
>
> -  if (!Fast)
> +  if (OptLevel != 0)
>     ComputeLiveOutVRegInfo();
>
>   // Third, instruction select all of the operations to machine  
> code, adding the
> @@ -1082,7 +1082,7 @@
>     RegisterScheduler::setDefault(Ctor);
>   }
>
> -  return Ctor(this, Fast);
> +  return Ctor(this, OptLevel);
> }
>
> ScheduleHazardRecognizer  
> *SelectionDAGISel::CreateTargetHazardRecognizer() {
>
> Modified: llvm/trunk/lib/Target/ARM/ARM.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARM.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARM.h Mon Apr 27 19:21:31 2009
> @@ -91,7 +91,7 @@
> FunctionPass *createARMISelDag(ARMTargetMachine &TM);
> FunctionPass *createARMCodePrinterPass(raw_ostream &O,
>                                        ARMTargetMachine &TM,
> -                                       bool Fast, bool Verbose);
> +                                       unsigned OptLevel, bool  
> Verbose);
> FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
>                                        MachineCodeEmitter &MCE);
> FunctionPass *createARMLoadStoreOptimizationPass();
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -138,35 +138,37 @@
>
>
> // Pass Pipeline Configuration
> -bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,  
> unsigned OptLevel) {
>   PM.add(createARMISelDag(*this));
>   return false;
> }
>
> -bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, bool  
> Fast) {
> +bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel) {
>   // FIXME: temporarily disabling load / store optimization pass for  
> Thumb mode.
> -  if (!Fast && !DisableLdStOpti && !Subtarget.isThumb())
> +  if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
>     PM.add(createARMLoadStoreOptimizationPass());
>
> -  if (!Fast && !DisableIfConversion && !Subtarget.isThumb())
> +  if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
>     PM.add(createIfConverterPass());
>
>   PM.add(createARMConstantIslandPass());
>   return true;
> }
>
> -bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool  
> Fast,
> -                                          bool Verbose, raw_ostream  
> &Out) {
> +bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                          unsigned OptLevel,
> +                                          bool Verbose,
> +                                          raw_ostream &Out) {
>   // Output assembly language.
>   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>   if (AsmPrinterCtor)
> -    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
> +    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>
>   return false;
> }
>
>
> -bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
> +bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                       bool DumpAsm,  
> MachineCodeEmitter &MCE) {
>   // FIXME: Move this to TargetJITInfo!
>   if (DefRelocModel == Reloc::Default)
> @@ -177,20 +179,22 @@
>   if (DumpAsm) {
>     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>     if (AsmPrinterCtor)
> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>   }
>
>   return false;
> }
>
> -bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,  
> bool Fast,
> -                                        bool DumpAsm,  
> MachineCodeEmitter &MCE) {
> +bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
> +                                            unsigned OptLevel,
> +                                            bool DumpAsm,
> +                                            MachineCodeEmitter  
> &MCE) {
>   // Machine code emitter pass for ARM.
>   PM.add(createARMCodeEmitterPass(*this, MCE));
>   if (DumpAsm) {
>     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>     if (AsmPrinterCtor)
> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>   }
>
>   return false;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Mon Apr 27 19:21:31  
> 2009
> @@ -41,7 +41,7 @@
>   // set this functions to ctor pointer at startup time if they are  
> linked in.
>   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>                                             ARMTargetMachine &tm,
> -                                            bool fast, bool verbose);
> +                                            unsigned OptLevel, bool  
> verbose);
>   static AsmPrinterCtorFn AsmPrinterCtor;
>
> public:
> @@ -69,13 +69,13 @@
>   virtual const TargetAsmInfo *createTargetAsmInfo() const;
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
>                               bool DumpAsm, MachineCodeEmitter &MCE);
> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                     bool DumpAsm, MachineCodeEmitter  
> &MCE);
> };
>
>
> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Mon Apr  
> 27 19:21:31 2009
> @@ -80,9 +80,9 @@
>     /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
>     bool InCPMode;
>   public:
> -    ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                  const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V), DW(0), MMI(NULL), AFI(NULL),  
> MCP(NULL),
> +    explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
> +                           const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL),  
> MCP(NULL),
>         InCPMode(false) {
>       Subtarget = &TM.getSubtarget<ARMSubtarget>();
>     }
> @@ -1061,8 +1061,8 @@
> ///
> FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
>                                              ARMTargetMachine &tm,
> -                                             bool fast, bool  
> verbose) {
> -  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                             unsigned OptLevel,  
> bool verbose) {
> +  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,  
> verbose);
> }
>
> namespace {
>
> Modified: llvm/trunk/lib/Target/Alpha/Alpha.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/Alpha.h (original)
> +++ llvm/trunk/lib/Target/Alpha/Alpha.h Mon Apr 27 19:21:31 2009
> @@ -26,7 +26,7 @@
>   FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
>   FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
>                                            TargetMachine &TM,
> -                                           bool Fast, bool Verbose);
> +                                           unsigned OptLevel, bool  
> Verbose);
>   FunctionPass *createAlphaPatternInstructionSelector(TargetMachine  
> &TM);
>   FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
>                                            MachineCodeEmitter &MCE);
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -76,31 +76,34 @@
> // Pass Pipeline Configuration
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> -bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
> +                                         unsigned OptLevel) {
>   PM.add(createAlphaISelDag(*this));
>   return false;
> }
> -bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, bool  
> Fast) {
> +bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
> +                                        unsigned OptLevel) {
>   // Must run branch selection immediately preceding the asm printer
>   PM.add(createAlphaBranchSelectionPass());
>   return false;
> }
> -bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,  
> bool Fast,
> +bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                            unsigned OptLevel,
>                                             bool Verbose,
>                                             raw_ostream &Out) {
>   PM.add(createAlphaLLRPPass(*this));
> -  PM.add(createAlphaCodePrinterPass(Out, *this, Fast, Verbose));
> +  PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
> -bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, bool  
> Fast,
> +bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,  
> unsigned OptLevel,
>                                         bool DumpAsm,  
> MachineCodeEmitter &MCE) {
>   PM.add(createAlphaCodeEmitterPass(*this, MCE));
>   if (DumpAsm)
> -    PM.add(createAlphaCodePrinterPass(errs(), *this, Fast, true));
> +    PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel,  
> true));
>   return false;
> }
> bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
> -                                              bool Fast, bool  
> DumpAsm,
> +                                              unsigned OptLevel,  
> bool DumpAsm,
>                                               MachineCodeEmitter  
> &MCE) {
> -  return addCodeEmitter(PM, Fast, DumpAsm, MCE);
> +  return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
> }
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Mon Apr 27  
> 19:21:31 2009
> @@ -58,13 +58,13 @@
>   static unsigned getModuleMatchQuality(const Module &M);
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
>                               bool DumpAsm, MachineCodeEmitter &MCE);
> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                     bool DumpAsm, MachineCodeEmitter  
> &MCE);
> };
>
>
> Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Mon  
> Apr 27 19:21:31 2009
> @@ -36,9 +36,9 @@
>     /// Unique incrementer for label values for referencing Global  
> values.
>     ///
>
> -    AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
> -                    const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(o, tm, T, F, V) {}
> +    explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
> +                             const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(o, tm, T, OL, V) {}
>
>     virtual const char *getPassName() const {
>       return "Alpha Assembly Printer";
> @@ -68,8 +68,9 @@
> ///
> FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
>                                                TargetMachine &tm,
> -                                               bool fast, bool  
> verbose) {
> -  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                               unsigned OptLevel,
> +                                               bool verbose) {
> +  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> OptLevel, verbose);
> }
>
> #include "AlphaGenAsmWriter.inc"
>
> Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
> +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Apr 27 19:21:31  
> 2009
> @@ -3587,7 +3587,7 @@
> bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>                                               raw_ostream &o,
>                                               CodeGenFileType  
> FileType,
> -                                              bool Fast) {
> +                                              unsigned OptLevel) {
>   if (FileType != TargetMachine::AssemblyFile) return true;
>
>   PM.add(createGCLoweringPass());
>
> Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Mon Apr 27  
> 19:21:31 2009
> @@ -27,7 +27,8 @@
>
>   virtual bool WantsWholeFile() const { return true; }
>   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream  
> &Out,
> -                                        CodeGenFileType FileType,  
> bool Fast);
> +                                        CodeGenFileType FileType,
> +                                        unsigned OptLevel);
>
>   // This class always works, but must be requested explicitly on
>   // llc command line.
>
> Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Mon  
> Apr 27 19:21:31 2009
> @@ -48,9 +48,9 @@
>   class VISIBILITY_HIDDEN SPUAsmPrinter : public AsmPrinter {
>     std::set<std::string> FnStubs, GVStubs;
>   public:
> -    SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                  const TargetAsmInfo *T, bool F, bool V) :
> -      AsmPrinter(O, TM, T, F, V) {}
> +    explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
> +                           const TargetAsmInfo *T, unsigned OL,  
> bool V) :
> +      AsmPrinter(O, TM, T, OL, V) {}
>
>     virtual const char *getPassName() const {
>       return "STI CBEA SPU Assembly Printer";
> @@ -615,6 +615,6 @@
> ///
> FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
>                                             SPUTargetMachine &tm,
> -                                            bool fast, bool  
> verbose) {
> -  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                            unsigned OptLevel, bool  
> verbose) {
> +  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> OptLevel, verbose);
> }
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPU.h Mon Apr 27 19:21:31 2009
> @@ -25,7 +25,7 @@
>   FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
>   FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
>                                         SPUTargetMachine &tm,
> -                                        bool fast, bool verbose);
> +                                        unsigned OptLevel, bool  
> verbose);
>
>   /*--== Utility functions/predicates/etc used all over the place: -- 
> ==*/
>   //! Predicate test for a signed 10-bit value
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -81,15 +81,17 @@
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> bool
> -SPUTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast)
> +SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel)
> {
>   // Install an instruction selector.
>   PM.add(createSPUISelDag(*this));
>   return false;
> }
>
> -bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool  
> Fast,
> -                                          bool Verbose, raw_ostream  
> &Out) {
> -  PM.add(createSPUAsmPrinterPass(Out, *this, Fast, Verbose));
> +bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                          unsigned OptLevel,
> +                                          bool Verbose,
> +                                          raw_ostream &Out) {
> +  PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Mon Apr 27  
> 19:21:31 2009
> @@ -83,9 +83,9 @@
>   }
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool /*Fast*/);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool /*Fast*/,
> -                                  bool /*Verbose*/, raw_ostream  
> &Out);
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
> +                                  bool Verbose, raw_ostream &Out);
> };
>
> } // end namespace llvm
>
> Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
> +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -1995,7 +1995,7 @@
> bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>                                                 raw_ostream &o,
>                                                 CodeGenFileType  
> FileType,
> -                                                bool Fast) {
> +                                                unsigned OptLevel) {
>   if (FileType != TargetMachine::AssemblyFile) return true;
>   PM.add(new CppWriter(o));
>   return false;
>
> Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Mon Apr 27  
> 19:21:31 2009
> @@ -29,7 +29,8 @@
>
>   virtual bool WantsWholeFile() const { return true; }
>   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream  
> &Out,
> -                                        CodeGenFileType FileType,  
> bool Fast);
> +                                        CodeGenFileType FileType,
> +                                        unsigned OptLevel);
>
>   // This class always works, but shouldn't be the default in most  
> cases.
>   static unsigned getModuleMatchQuality(const Module &M) { return 1; }
>
> Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Mon Apr  
> 27 19:21:31 2009
> @@ -37,9 +37,9 @@
>   class IA64AsmPrinter : public AsmPrinter {
>     std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
>   public:
> -    IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                   const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V) {}
> +    explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
> +                            const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(O, TM, T, OL, V) {}
>
>     virtual const char *getPassName() const {
>       return "IA64 Assembly Printer";
> @@ -370,6 +370,7 @@
> ///
> FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
>                                               IA64TargetMachine &tm,
> -                                              bool fast, bool  
> verbose) {
> -  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                              unsigned OptLevel,
> +                                              bool verbose) {
> +  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,  
> verbose);
> }
>
> Modified: llvm/trunk/lib/Target/IA64/IA64.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64.h (original)
> +++ llvm/trunk/lib/Target/IA64/IA64.h Mon Apr 27 19:21:31 2009
> @@ -37,7 +37,7 @@
> ///
> FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
>                                         IA64TargetMachine &tm,
> -                                        bool fast, bool verbose);
> +                                        unsigned OptLevel, bool  
> verbose);
>
> } // End llvm namespace
>
>
> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -72,19 +72,21 @@
> // Pass Pipeline Configuration
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> -bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,  
> unsigned OptLEvel){
>   PM.add(createIA64DAGToDAGInstructionSelector(*this));
>   return false;
> }
>
> -bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, bool  
> Fast) {
> +bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,  
> unsigned OptLevel) {
>   // Make sure everything is bundled happily
>   PM.add(createIA64BundlingPass(*this));
>   return true;
> }
> -bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,  
> bool Fast,
> -                                           bool Verbose,  
> raw_ostream &Out) {
> -  PM.add(createIA64CodePrinterPass(Out, *this, Fast, Verbose));
> +bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                           unsigned OptLevel,
> +                                           bool Verbose,
> +                                           raw_ostream &Out) {
> +  PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
>
> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.h Mon Apr 27  
> 19:21:31 2009
> @@ -51,9 +51,9 @@
>   static unsigned getModuleMatchQuality(const Module &M);
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> };
> } // End llvm namespace
>
> Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
> +++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Mon Apr 27 19:21:31 2009
> @@ -35,7 +35,8 @@
>
>     virtual bool WantsWholeFile() const { return true; }
>     virtual bool addPassesToEmitWholeFile(PassManager &PM,  
> raw_ostream &Out,
> -                                         CodeGenFileType FileType,  
> bool Fast);
> +                                          CodeGenFileType FileType,
> +                                          unsigned OptLevel);
>
>     // This class always works, but shouldn't be the default in most  
> cases.
>     static unsigned getModuleMatchQuality(const Module &M) { return  
> 1; }
> @@ -1662,7 +1663,8 @@
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM,  
> raw_ostream &o,
> -                                          CodeGenFileType FileType,  
> bool Fast)
> +                                          CodeGenFileType FileType,
> +                                          unsigned OptLevel)
> {
>   if (FileType != TargetMachine::AssemblyFile) return true;
>   MSILWriter* Writer = new MSILWriter(o);
>
> Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Mon Apr  
> 27 19:21:31 2009
> @@ -49,9 +49,9 @@
>   class VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
>     const MipsSubtarget *Subtarget;
>   public:
> -    MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
> -                   const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V) {
> +    explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
> +                            const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(O, TM, T, OL, V) {
>       Subtarget = &TM.getSubtarget<MipsSubtarget>();
>     }
>
> @@ -91,8 +91,8 @@
> /// regardless of whether the function is in SSA form.
> FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
>                                               MipsTargetMachine &tm,
> -                                              bool fast, bool  
> verbose) {
> -  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                              unsigned OptLevel,  
> bool verbose) {
> +  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,  
> verbose);
> }
>
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> Modified: llvm/trunk/lib/Target/Mips/Mips.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/Mips.h (original)
> +++ llvm/trunk/lib/Target/Mips/Mips.h Mon Apr 27 19:21:31 2009
> @@ -25,7 +25,7 @@
>   FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
>   FunctionPass *createMipsCodePrinterPass(raw_ostream &OS,
>                                           MipsTargetMachine &TM,
> -                                          bool Fast, bool Verbose);
> +                                          unsigned OptLevel, bool  
> Verbose);
> } // end namespace llvm;
>
> // Defines symbolic names for Mips registers.  This defines a  
> mapping from
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -105,7 +105,7 @@
> // Install an instruction selector pass using
> // the ISelDag to gen Mips code.
> bool MipsTargetMachine::
> -addInstSelector(PassManagerBase &PM, bool Fast)
> +addInstSelector(PassManagerBase &PM, unsigned OptLevel)
> {
>   PM.add(createMipsISelDag(*this));
>   return false;
> @@ -115,7 +115,7 @@
> // machine code is emitted. return true if -print-machineinstrs should
> // print out the code after the passes.
> bool MipsTargetMachine::
> -addPreEmitPass(PassManagerBase &PM, bool Fast)
> +addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
> {
>   PM.add(createMipsDelaySlotFillerPass(*this));
>   return true;
> @@ -124,10 +124,10 @@
> // Implements the AssemblyEmitter for the target. Must return
> // true if AssemblyEmitter is supported
> bool MipsTargetMachine::
> -addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
>                    bool Verbose, raw_ostream &Out)
> {
>   // Output assembly language.
> -  PM.add(createMipsCodePrinterPass(Out, *this, Fast, Verbose));
> +  PM.add(createMipsCodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Mon Apr 27  
> 19:21:31 2009
> @@ -57,9 +57,9 @@
>     static unsigned getModuleMatchQuality(const Module &M);
>
>     // Pass Pipeline Configuration
> -    virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -    virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
> -    virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +    virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +    virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> +    virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                     bool Verbose, raw_ostream &Out);
>   };
>
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16.h Mon Apr 27 19:21:31 2009
> @@ -75,7 +75,7 @@
>   FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
>   FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
>                                            PIC16TargetMachine &TM,
> -                                           bool Fast, bool Verbose);
> +                                           unsigned OptLevel, bool  
> Verbose);
> } // end namespace llvm;
>
> // Defines symbolic names for PIC16 registers.  This defines a  
> mapping from
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -161,8 +161,9 @@
> ///
> FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
>                                                PIC16TargetMachine &tm,
> -                                               bool fast, bool  
> verbose) {
> -  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                               unsigned OptLevel,
> +                                               bool verbose) {
> +  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> OptLevel, verbose);
> }
>
> void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int  
> opNum) {
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Mon Apr 27  
> 19:21:31 2009
> @@ -24,9 +24,9 @@
>
> namespace llvm {
>   struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
> -  PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
> -                    const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V) {
> +    explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
> +                             const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(O, TM, T, OL, V) {
>       CurBank = "";
>       FunctionLabelBegin = '@';
>       IsRomData = false;
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -55,17 +55,18 @@
>   return new PIC16TargetAsmInfo(*this);
> }
>
> -bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
> +                                         unsigned OptLevel) {
>   // Install an instruction selector.
>   PM.add(createPIC16ISelDag(*this));
>   return false;
> }
>
> bool PIC16TargetMachine::
> -addAssemblyEmitter(PassManagerBase &PM, bool Fast, bool Verbose,
> +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool  
> Verbose,
>                    raw_ostream &Out) {
>   // Output assembly language.
> -  PM.add(createPIC16CodePrinterPass(Out, *this, Fast, Verbose));
> +  PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h Mon Apr 27  
> 19:21:31 2009
> @@ -57,8 +57,8 @@
>     return const_cast<PIC16TargetLowering*>(&TLInfo);
>   }
>
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> }; // PIC16TargetMachine.
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Mon  
> Apr 27 19:21:31 2009
> @@ -54,9 +54,9 @@
>     StringSet<> FnStubs, GVStubs, HiddenGVStubs;
>     const PPCSubtarget &Subtarget;
>   public:
> -    PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                  const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V),
> +    explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
> +                           const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(O, TM, T, OL, V),
>         Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
>
>     virtual const char *getPassName() const {
> @@ -297,9 +297,9 @@
>     DwarfWriter *DW;
>     MachineModuleInfo *MMI;
>   public:
> -    PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
> -                       const TargetAsmInfo *T, bool F, bool V)
> -      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
> +    explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
> +                                const TargetAsmInfo *T, unsigned  
> OL, bool V)
> +      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
>
>     virtual const char *getPassName() const {
>       return "Linux PPC Assembly Printer";
> @@ -326,9 +326,9 @@
>     MachineModuleInfo *MMI;
>     raw_ostream &OS;
>   public:
> -    PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
> -                        const TargetAsmInfo *T, bool F, bool V)
> -      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0), OS(O) {}
> +    explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine  
> &TM,
> +                                 const TargetAsmInfo *T, unsigned  
> OL, bool V)
> +      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
>
>     virtual const char *getPassName() const {
>       return "Darwin PPC Assembly Printer";
> @@ -1176,13 +1176,15 @@
> ///
> FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
>                                             PPCTargetMachine &tm,
> -                                            bool fast, bool  
> verbose) {
> +                                            unsigned OptLevel, bool  
> verbose) {
>   const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
>
>   if (Subtarget->isDarwin()) {
> -    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> fast, verbose);
> +    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
> +                                   OptLevel, verbose);
>   } else {
> -    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> fast, verbose);
> +    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
> +                                  OptLevel, verbose);
>   }
> }
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPC.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPC.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPC.h Mon Apr 27 19:21:31 2009
> @@ -28,7 +28,7 @@
> FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
> FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
>                                       PPCTargetMachine &TM,
> -                                      bool Fast, bool Verbose);
> +                                      unsigned OptLevel, bool  
> Verbose);
> FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
>                                        MachineCodeEmitter &MCE);
> } // end namespace llvm;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -129,29 +129,31 @@
> // Pass Pipeline Configuration
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> -bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,  
> unsigned OptLevel) {
>   // Install an instruction selector.
>   PM.add(createPPCISelDag(*this));
>   return false;
> }
>
> -bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool  
> Fast) {
> +bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel) {
>
>   // Must run branch selection immediately preceding the asm printer.
>   PM.add(createPPCBranchSelectionPass());
>   return false;
> }
>
> -bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool  
> Fast,
> -                                          bool Verbose, raw_ostream  
> &Out) {
> +bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                          unsigned OptLevel,
> +                                          bool Verbose,
> +                                          raw_ostream &Out) {
>   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>   if (AsmPrinterCtor)
> -    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
> +    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>
>   return false;
> }
>
> -bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
> +bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                       bool DumpAsm,  
> MachineCodeEmitter &MCE) {
>   // The JIT should use the static relocation model in ppc32 mode,  
> PIC in ppc64.
>   // FIXME: This should be moved to TargetJITInfo!!
> @@ -176,20 +178,20 @@
>   if (DumpAsm) {
>     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>     if (AsmPrinterCtor)
> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>   }
>
>   return false;
> }
>
> -bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,  
> bool Fast,
> +bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,  
> unsigned OptLevel,
>                                             bool DumpAsm,  
> MachineCodeEmitter &MCE) {
>   // Machine code emitter pass for PowerPC.
>   PM.add(createPPCCodeEmitterPass(*this, MCE));
>   if (DumpAsm) {
>     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>     if (AsmPrinterCtor)
> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>   }
>
>   return false;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Mon Apr 27  
> 19:21:31 2009
> @@ -46,7 +46,7 @@
>   // set this functions to ctor pointer at startup time if they are  
> linked in.
>   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>                                             PPCTargetMachine &tm,
> -                                            bool fast, bool verbose);
> +                                            unsigned OptLevel, bool  
> verbose);
>   static AsmPrinterCtorFn AsmPrinterCtor;
>
> public:
> @@ -76,13 +76,13 @@
>   }
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
>                               bool DumpAsm, MachineCodeEmitter &MCE);
> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                     bool DumpAsm, MachineCodeEmitter  
> &MCE);
>   virtual bool getEnableTailMergeDefault() const;
> };
>
> Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp Mon  
> Apr 27 19:21:31 2009
> @@ -48,9 +48,9 @@
>     typedef std::map<const Value *, unsigned> ValueMapTy;
>     ValueMapTy NumberForBB;
>   public:
> -    SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                    const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V) {}
> +    explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
> +                             const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(O, TM, T, OL, V) {}
>
>     virtual const char *getPassName() const {
>       return "Sparc Assembly Printer";
> @@ -82,8 +82,9 @@
> ///
> FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
>                                                TargetMachine &tm,
> -                                               bool fast, bool  
> verbose) {
> -  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                               unsigned OptLevel,
> +                                               bool verbose) {
> +  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> OptLevel, verbose);
> }
>
> /// runOnMachineFunction - This uses the printInstruction()
>
> Modified: llvm/trunk/lib/Target/Sparc/Sparc.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/Sparc.h (original)
> +++ llvm/trunk/lib/Target/Sparc/Sparc.h Mon Apr 27 19:21:31 2009
> @@ -25,7 +25,7 @@
>
>   FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
>   FunctionPass *createSparcCodePrinterPass(raw_ostream &OS,  
> TargetMachine &TM,
> -                                           bool Fast, bool Verbose);
> +                                           unsigned OptLevel, bool  
> Verbose);
>   FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
>   FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
> } // end namespace llvm;
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -68,7 +68,8 @@
> #endif
> }
>
> -bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
> +                                         unsigned OptLevel) {
>   PM.add(createSparcISelDag(*this));
>   return false;
> }
> @@ -76,15 +77,17 @@
> /// addPreEmitPass - This pass may be implemented by targets that  
> want to run
> /// passes immediately before machine code is emitted.  This should  
> return
> /// true if -print-machineinstrs should print out the code after the  
> passes.
> -bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, bool  
> Fast) {
> +bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,  
> unsigned OptLevel){
>   PM.add(createSparcFPMoverPass(*this));
>   PM.add(createSparcDelaySlotFillerPass(*this));
>   return true;
> }
>
> -bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,  
> bool Fast,
> -                                            bool Verbose,  
> raw_ostream &Out) {
> +bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                            unsigned OptLevel,
> +                                            bool Verbose,
> +                                            raw_ostream &Out) {
>   // Output assembly language.
> -  PM.add(createSparcCodePrinterPass(Out, *this, Fast, Verbose));
> +  PM.add(createSparcCodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Mon Apr 27  
> 19:21:31 2009
> @@ -51,9 +51,9 @@
>   static unsigned getModuleMatchQuality(const Module &M);
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> };
>
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Mon Apr  
> 27 19:21:31 2009
> @@ -33,9 +33,9 @@
>   MachineModuleInfo *MMI;
>   const X86Subtarget *Subtarget;
>  public:
> -  X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
> -                   const TargetAsmInfo *T, bool F, bool V)
> -    : AsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {
> +  explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
> +                            const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +    : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
>     Subtarget = &TM.getSubtarget<X86Subtarget>();
>   }
>
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Mon Apr  
> 27 19:21:31 2009
> @@ -25,13 +25,15 @@
> ///
> FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
>                                              X86TargetMachine &tm,
> -                                             bool fast, bool  
> verbose) {
> +                                             unsigned OptLevel,  
> bool verbose) {
>   const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
>
>   if (Subtarget->isFlavorIntel()) {
> -    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> fast, verbose);
> +    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(),
> +                                  OptLevel, verbose);
>   } else {
> -    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(),
> +                                OptLevel, verbose);
>   }
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h  
> (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h Mon  
> Apr 27 19:21:31 2009
> @@ -25,9 +25,9 @@
> namespace llvm {
>
> struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
> -  X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
> -                     const TargetAsmInfo *T, bool F, bool V)
> -    : AsmPrinter(O, TM, T, F, V) {}
> +  explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
> +                              const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +    : AsmPrinter(O, TM, T, OL, V) {}
>
>   virtual const char *getPassName() const {
>     return "X86 Intel-Style Assembly Printer";
>
> Modified: llvm/trunk/lib/Target/X86/X86.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86.h (original)
> +++ llvm/trunk/lib/Target/X86/X86.h Mon Apr 27 19:21:31 2009
> @@ -25,7 +25,7 @@
> /// createX86ISelDag - This pass converts a legalized DAG into a
> /// X86-specific DAG, ready for instruction scheduling.
> ///
> -FunctionPass *createX86ISelDag(X86TargetMachine &TM, bool Fast);
> +FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned  
> OptSize);
>
> /// createX86FloatingPointStackifierPass - This function returns a  
> pass which
> /// converts floating point register references and pseudo  
> instructions into
> @@ -44,7 +44,7 @@
> ///
> FunctionPass *createX86CodePrinterPass(raw_ostream &o,
>                                        X86TargetMachine &tm,
> -                                       bool fast, bool Verbose);
> +                                       unsigned OptLevel, bool  
> Verbose);
>
> /// createX86CodeEmitterPass - Return a pass that emits the  
> collected X86 code
> /// to the specified MCE object.
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -134,8 +134,8 @@
>     bool OptForSize;
>
>   public:
> -    X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
> -      : SelectionDAGISel(tm, fast),
> +    explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
> +      : SelectionDAGISel(tm, OptLevel),
>         TM(tm), X86Lowering(*TM.getTargetLowering()),
>         Subtarget(&TM.getSubtarget<X86Subtarget>()),
>         OptForSize(false) {}
> @@ -306,7 +306,7 @@
>
> bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
>                                                  SDNode *Root) const {
> -  if (Fast) return false;
> +  if (OptLevel == 0) return false;
>
>   if (U == Root)
>     switch (U->getOpcode()) {
> @@ -512,7 +512,7 @@
>
>
> /// PreprocessForRMW - Preprocess the DAG to make instruction  
> selection better.
> -/// This is only run if not in -fast mode (aka -O0).
> +/// This is only run if not in -O0 mode.
> /// This allows the instruction selector to pick more read-modify- 
> write
> /// instructions. This is a common case:
> ///
> @@ -714,10 +714,10 @@
>   OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
>
>   DEBUG(BB->dump());
> -  if (!Fast)
> +  if (OptLevel != 0)
>     PreprocessForRMW();
>
> -  // FIXME: This should only happen when not -fast.
> +  // FIXME: This should only happen when not compiled with -O0.
>   PreprocessForFPConvert();
>
>   // Codegen the basic block.
> @@ -1744,6 +1744,6 @@
> /// createX86ISelDag - This pass converts a legalized DAG into a
> /// X86-specific DAG, ready for instruction scheduling.
> ///
> -FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool  
> Fast) {
> -  return new X86DAGToDAGISel(TM, Fast);
> +FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned  
> OptLevel) {
> +  return new X86DAGToDAGISel(TM, OptLevel);
> }
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -180,9 +180,9 @@
> // Pass Pipeline Configuration
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> -bool X86TargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool X86TargetMachine::addInstSelector(PassManagerBase &PM,  
> unsigned OptLevel) {
>   // Install an instruction selector.
> -  PM.add(createX86ISelDag(*this, Fast));
> +  PM.add(createX86ISelDag(*this, OptLevel));
>
>   // If we're using Fast-ISel, clean up the mess.
>   if (EnableFastISel)
> @@ -194,27 +194,29 @@
>   return false;
> }
>
> -bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, bool  
> Fast) {
> +bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned  
> OptLevel) {
>   // Calculate and set max stack object alignment early, so we can  
> decide
>   // whether we will need stack realignment (and thus FP).
>   PM.add(createX86MaxStackAlignmentCalculatorPass());
>   return false;  // -print-machineinstr shouldn't print after this.
> }
>
> -bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, bool  
> Fast) {
> +bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,  
> unsigned OptLevel) {
>   PM.add(createX86FloatingPointStackifierPass());
>   return true;  // -print-machineinstr should print after this.
> }
>
> -bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool  
> Fast,
> -                                          bool Verbose, raw_ostream  
> &Out) {
> +bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                          unsigned OptLevel,
> +                                          bool Verbose,
> +                                          raw_ostream &Out) {
>   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>   if (AsmPrinterCtor)
> -    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
> +    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
> -bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
> +bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                       bool DumpAsm,  
> MachineCodeEmitter &MCE) {
>   // FIXME: Move this to TargetJITInfo!
>   // On Darwin, do not override 64-bit setting made in  
> X86TargetMachine().
> @@ -236,19 +238,20 @@
>   if (DumpAsm) {
>     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>     if (AsmPrinterCtor)
> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>   }
>
>   return false;
> }
>
> -bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,  
> bool Fast,
> -                                        bool DumpAsm,  
> MachineCodeEmitter &MCE) {
> +bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
> +                                            unsigned OptLevel, bool  
> DumpAsm,
> +                                            MachineCodeEmitter  
> &MCE) {
>   PM.add(createX86CodeEmitterPass(*this, MCE));
>   if (DumpAsm) {
>     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>     if (AsmPrinterCtor)
> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>   }
>
>   return false;
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Mon Apr 27 19:21:31  
> 2009
> @@ -45,7 +45,7 @@
>   // set this functions to ctor pointer at startup time if they are  
> linked in.
>   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>                                             X86TargetMachine &tm,
> -                                            bool fast, bool verbose);
> +                                            unsigned OptLevel, bool  
> verbose);
>   static AsmPrinterCtorFn AsmPrinterCtor;
>
> public:
> @@ -74,14 +74,14 @@
>   }
>
>   // Set up the pass pipeline.
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addPreRegAlloc(PassManagerBase &PM, bool Fast);
> -  virtual bool addPostRegAlloc(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
>                               bool DumpAsm, MachineCodeEmitter &MCE);
> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                     bool DumpAsm, MachineCodeEmitter  
> &MCE);
>
>   /// symbolicAddressesAreRIPRel - Return true if symbolic addresses  
> are
>
> Modified: llvm/trunk/lib/Target/XCore/XCore.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCore.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/XCore/XCore.h (original)
> +++ llvm/trunk/lib/Target/XCore/XCore.h Mon Apr 27 19:21:31 2009
> @@ -24,7 +24,7 @@
>   FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
>   FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
>                                            XCoreTargetMachine &TM,
> -                                           bool Fast, bool Verbose);
> +                                           unsigned OptLevel, bool  
> Verbose);
> } // end namespace llvm;
>
> // Defines symbolic names for XCore registers.  This defines a  
> mapping from
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -58,8 +58,8 @@
>     const XCoreSubtarget &Subtarget;
>   public:
>     XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
> -                    const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V), DW(0),
> +                    const TargetAsmInfo *T, unsigned OL, bool V)
> +      : AsmPrinter(O, TM, T, OL, V), DW(0),
>         Subtarget(*TM.getSubtargetImpl()) {}
>
>     virtual const char *getPassName() const {
> @@ -105,8 +105,9 @@
> ///
> FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
>                                                XCoreTargetMachine &tm,
> -                                               bool fast, bool  
> verbose) {
> -  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                               unsigned OptLevel,
> +                                               bool verbose) {
> +  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> OptLevel, verbose);
> }
>
> // PrintEscapedString - Print each character of the specified  
> string, escaping
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -55,14 +55,17 @@
>   return 0;
> }
>
> -bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
> +                                         unsigned OptLevel) {
>   PM.add(createXCoreISelDag(*this));
>   return false;
> }
>
> -bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,  
> bool Fast,
> -                                            bool Verbose,  
> raw_ostream &Out) {
> +bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                            unsigned OptLevel,
> +                                            bool Verbose,
> +                                            raw_ostream &Out) {
>   // Output assembly language.
> -  PM.add(createXCoreCodePrinterPass(Out, *this, Fast, Verbose));
> +  PM.add(createXCoreCodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Mon Apr 27  
> 19:21:31 2009
> @@ -52,8 +52,8 @@
>   static unsigned getModuleMatchQuality(const Module &M);
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> };
>
>
> Modified: llvm/trunk/test/CodeGen/Generic/2006-06-12- 
> LowerSwitchCrash.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll  
> (original)
> +++ llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll  
> Mon Apr 27 19:21:31 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -fast
> +; RUN: llvm-as < %s | llc -O0
>
> define float @test(i32 %tmp12771278) {
>         switch i32 %tmp12771278, label %bb1279 [
>
> Modified: llvm/trunk/test/CodeGen/Generic/2006-06-13- 
> ComputeMaskedBitsCrash.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/Generic/2006-06-13- 
> ComputeMaskedBitsCrash.ll (original)
> +++ llvm/trunk/test/CodeGen/Generic/2006-06-13- 
> ComputeMaskedBitsCrash.ll Mon Apr 27 19:21:31 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -fast
> +; RUN: llvm-as < %s | llc -O0
> 	
> %struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8,  
> i8, i8, i8, i32, i32, i32, i32, i32, i32, i32 }
> @cl_pf_opts = external global %struct.cl_perfunc_opts		; < 
> %struct.cl_perfunc_opts*> [#uses=2]
>
> Modified: llvm/trunk/test/CodeGen/Generic/2007-04-13- 
> SwitchLowerBadPhi.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll  
> (original)
> +++ llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll  
> Mon Apr 27 19:21:31 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -fast
> +; RUN: llvm-as < %s | llc -O0
> ; PR 1323
>
> ; ModuleID = 'test.bc'
>
> Modified: llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll Mon Apr 27  
> 19:21:31 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -fast - 
> relocation-model=pic -o -
> +; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -O0 - 
> relocation-model=pic -o -
> ; PR1638
>
> @.str242 = external constant [3 x i8]		; <[3 x i8]*> [#uses=1]
>
> Modified: llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll  
> (original)
> +++ llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll Mon  
> Apr 27 19:21:31 2009
> @@ -1,5 +1,5 @@
> ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin
> -; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation- 
> model=pic -disable-fp-elim -fast -regalloc=local
> +; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation- 
> model=pic -disable-fp-elim -O0 -regalloc=local
>
> 	%struct.CGPoint = type { double, double }
> 	%struct.NSArray = type { %struct.NSObject }
>
> Modified: llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll Mon Apr  
> 27 19:21:31 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -march=x86 -fast -fast-isel=false | grep  
> mov | count 5
> +; RUN: llvm-as < %s | llc -march=x86 -O0 -fast-isel=false | grep  
> mov | count 5
> ; PR2343
>
> 	%llvm.dbg.anchor.type = type { i32, i32 }
>
> Modified: llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll Mon Apr  
> 27 19:21:31 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast
> +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0
>
> define fastcc void @optimize_bit_field() nounwind {
> bb4:
>
> Modified: llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll Mon Apr 27  
> 19:21:31 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast - 
> regalloc=local | not grep sil
> +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0 - 
> regalloc=local | not grep sil
> ; rdar://6787136
>
> 	%struct.X = type { i8, [32 x i8] }
>
> Modified: llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/add-with-overflow.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/add-with-overflow.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/add-with-overflow.ll Mon Apr 27  
> 19:21:31 2009
> @@ -1,7 +1,7 @@
> ; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 2
> ; RUN: llvm-as < %s | llc -march=x86 | grep {jb} | count 2
> -; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jo} | count 2
> -; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jb} | count 2
> +; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jo} | count 2
> +; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jb} | count 2
>
> @ok = internal constant [4 x i8] c"%d\0A\00"
> @no = internal constant [4 x i8] c"no\0A\00"
>
> Modified: llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll Mon Apr 27  
> 19:21:31 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -march=x86 -fast
> +; RUN: llvm-as < %s | llc -march=x86 -O0
>
> ; This file is for regression tests for cases where FastISel needs
> ; to gracefully bail out and let SelectionDAGISel take over.
>
> Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll Mon Apr 27  
> 19:21:31 2009
> @@ -1,5 +1,5 @@
> -; RUN: llvm-as < %s | llc -march=x86-64 -fast | grep movslq
> -; RUN: llvm-as < %s | llc -march=x86 -fast
> +; RUN: llvm-as < %s | llc -march=x86-64 -O0 | grep movslq
> +; RUN: llvm-as < %s | llc -march=x86 -O0
> ; PR3181
>
> ; GEP indices are interpreted as signed integers, so they
>
> Modified: llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll Mon Apr 27  
> 19:21:31 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -march=x86 -fast | grep {sarl	\$80, %eax}
> +; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {sarl	\$80, %eax}
> ; PR3242
>
> define i32 @foo(i32 %x) nounwind {
>
> Modified: llvm/trunk/test/CodeGen/X86/pr1489.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr1489.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/pr1489.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/pr1489.ll Mon Apr 27 19:21:31 2009
> @@ -1,5 +1,5 @@
> -; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep  
> 1082126238 | count 3
> -; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep  
> 3058016715 | count 1
> +; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep  
> 1082126238 | count 3
> +; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep  
> 3058016715 | count 1
> ;; magic constants are 3.999f and half of 3.999
> ; ModuleID = '1489.c'
> target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32- 
> i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
>
> Modified: llvm/trunk/test/CodeGen/X86/volatile.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/volatile.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/volatile.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/volatile.ll Mon Apr 27 19:21:31 2009
> @@ -1,5 +1,5 @@
> ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 | grep movsd |  
> count 5
> -; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -fast | grep movsd  
> | count 5
> +; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -O0 | grep movsd |  
> count 5
>
> @x = external global double
>
>
> Modified: llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll  
> (original)
> +++ llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll Mon Apr  
> 27 19:21:31 2009
> @@ -1,5 +1,5 @@
> ; RUN: llvm-as < %s | llc
> -; RUN: llvm-as < %s | llc -fast
> +; RUN: llvm-as < %s | llc -O0
> 	%llvm.dbg.anchor.type = type { i32, i32 }
> 	%llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64,  
> i64, i64, i32, i32 }
> 	%llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8* }
>
> Modified: llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-30-Method.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/DebugInfo/2009-01-30-Method.ll (original)
> +++ llvm/trunk/test/DebugInfo/2009-01-30-Method.ll Mon Apr 27  
> 19:21:31 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -fast | grep "\\"foo" | count 3
> +; RUN: llvm-as < %s | llc -O0 | grep "\\"foo" | count 3
> ; 1 declaration, 1 definition and 1 pubnames entry.
> target triple = "i386-apple-darwin*"
> 	%llvm.dbg.anchor.type = type { i32, i32 }
>
> Modified: llvm/trunk/test/DebugInfo/deaddebuglabel.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/deaddebuglabel.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/DebugInfo/deaddebuglabel.ll (original)
> +++ llvm/trunk/test/DebugInfo/deaddebuglabel.ll Mon Apr 27 19:21:31  
> 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -fast | grep "label" | count 8
> +; RUN: llvm-as < %s | llc -O0 | grep "label" | count 8
> ; PR2614
> ; XFAIL: *
>
>
> Modified: llvm/trunk/test/DebugInfo/forwardDecl.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/forwardDecl.ll?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/DebugInfo/forwardDecl.ll (original)
> +++ llvm/trunk/test/DebugInfo/forwardDecl.ll Mon Apr 27 19:21:31 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -fast | %prcontext ST 1 | grep 0x1 |  
> count 1
> +; RUN: llvm-as < %s | llc -O0 | %prcontext ST 1 | grep 0x1 | count 1
>
> target triple = "i386-apple-darwin9.6"
> 	%llvm.dbg.anchor.type = type { i32, i32 }
>
> Modified: llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-06-StackTrace.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp (original)
> +++ llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -1,7 +1,7 @@
> // This is a regression test on debug info to make sure that we can  
> get a
> // meaningful stack trace from a C++ program.
> // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
> -// RUN:    llc --disable-fp-elim -o %t.s -f -fast -relocation- 
> model=pic
> +// RUN:    llc --disable-fp-elim -o %t.s -f -O0 -relocation-model=pic
> // RUN: %compile_c %t.s -o %t.o
> // RUN: %link %t.o -o %t.exe
> // RUN: echo {break DeepStack::deepest\nrun 17\nwhere\n} > %t.in
>
> Modified: llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-30-Pubnames.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp (original)
> +++ llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -1,7 +1,7 @@
> // This is a regression test on debug info to make sure that we can  
> access
> // qualified global names.
> // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
> -// RUN:   llc --disable-fp-elim -o %t.s -f -fast
> +// RUN:   llc --disable-fp-elim -o %t.s -f -O0
> // RUN: %compile_c %t.s -o %t.o
> // RUN: %link %t.o -o %t.exe
> // RUN: %llvmdsymutil %t.exe
>
> Modified: llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-04-21-DtorNames-dbg.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp  
> (original)
> +++ llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp Mon Apr  
> 27 19:21:31 2009
> @@ -1,4 +1,4 @@
> -// RUN: %llvmgcc -c -g %s -o - | llc -fast -f -o %t.s
> +// RUN: %llvmgcc -c -g %s -o - | llc -O0 -f -o %t.s
> // RUN: %compile_c %t.s -o %t.o
> // PR4025
>
>
> Modified: llvm/trunk/tools/llc/llc.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/tools/llc/llc.cpp (original)
> +++ llvm/trunk/tools/llc/llc.cpp Mon Apr 27 19:21:31 2009
> @@ -55,8 +55,13 @@
>
> static cl::opt<bool> Force("f", cl::desc("Overwrite output files"));
>
> -static cl::opt<bool> Fast("fast",
> -      cl::desc("Generate code quickly, potentially sacrificing code  
> quality"));
> +// Determine optimization level. Level -O0 is equivalent to "fast"  
> code gen.
> +static cl::opt<unsigned>
> +OptLevel("O",
> +         cl::desc("Optimization level. Similar to llvm-gcc -O.  
> (default: -O3)"),
> +         cl::Prefix,
> +         cl::ZeroOrMore,
> +         cl::init(3));
>
> static cl::opt<std::string>
> TargetTriple("mtriple", cl::desc("Override target triple for  
> module"));
> @@ -257,7 +262,7 @@
>       PM.add(createVerifierPass());
>
>     // Ask the target to add backend passes as necessary.
> -    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, Fast)) {
> +    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType,  
> OptLevel)) {
>       std::cerr << argv[0] << ": target does not support generation  
> of this"
>                 << " file type!\n";
>       if (Out != &outs()) delete Out;
> @@ -283,7 +288,7 @@
>     // Override default to generate verbose assembly.
>     Target.setAsmVerbosityDefault(true);
>
> -    switch (Target.addPassesToEmitFile(Passes, *Out, FileType,  
> Fast)) {
> +    switch (Target.addPassesToEmitFile(Passes, *Out, FileType,  
> OptLevel)) {
>     default:
>       assert(0 && "Invalid file model!");
>       return 1;
> @@ -304,7 +309,7 @@
>       break;
>     }
>
> -    if (Target.addPassesToEmitFileFinish(Passes, MCE, Fast)) {
> +    if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) {
>       std::cerr << argv[0] << ": target does not support generation  
> of this"
>                 << " file type!\n";
>       if (Out != &outs()) delete Out;
>
> Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Mon Apr 27  
> 19:21:31 2009
> @@ -650,7 +650,7 @@
>   O << "\";\n\n";
>
>   O << "  if (TAI->doesSupportDebugInformation() &&\n"
> -    << "      DW->ShouldEmitDwarfDebug() && !Fast) {\n"
> +    << "      DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n"
>     << "    DebugLoc CurDL = MI->getDebugLoc();\n\n"
>     << "    if (!CurDL.isUnknown()) {\n"
>     << "      static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n"
>
> Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Apr 27 19:21:31  
> 2009
> @@ -465,7 +465,7 @@
>       NumInputRootOps = N->getNumChildren();
>
>       if (DisablePatternForFastISel(N, CGP))
> -        emitCheck("!Fast");
> +        emitCheck("OptLevel != 0");
>
>       emitCheck(PredicateCheck);
>     }
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Mon Apr 27 19:32:20 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Apr 2009 17:32:20 -0700
Subject: [llvm-commits] [llvm] r70270 - in /llvm/trunk:
	include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/	lib/Target/ARM/
	lib/Target/ARM/AsmPrinter/
	lib/Target/Alpha/	lib/Target/Alpha/AsmPrinter/
	lib/Target/CBackend/	lib/Target/CellSPU/
	lib/Target/CellSPU/AsmPrinter/ lib/Target/CppBackend/
	lib/Target/IA64/	lib/Target/IA64/AsmPrinter/ lib/Target/MSIL/
	lib/Target/Mips/	lib/Target/Mips/AsmPrinter/
	lib/Target/PIC16/	lib/Target/PowerPC/
	lib/Target/PowerPC/AsmPrinter/ lib/Target...
In-Reply-To: <F4CEA21C-BE09-4BC0-B05F-ADC60A5397BC@apple.com>
References: <200904280021.n3S0LdXU027640@zion.cs.uiuc.edu>
	<F4CEA21C-BE09-4BC0-B05F-ADC60A5397BC@apple.com>
Message-ID: <DD11DD66-238F-40E7-BE34-71AFB0BB9227@apple.com>

Also llvmgcc changes?

Evan

On Apr 27, 2009, at 5:30 PM, Evan Cheng wrote:

> Thanks. How about libLTO?
>
> Also, JIT (calls to TM.addPassesToEmitMachineCode and lli.cpp) has to
> be changed as well.
>
> Evan
>
> On Apr 27, 2009, at 5:21 PM, Bill Wendling wrote:
>
>> Author: void
>> Date: Mon Apr 27 19:21:31 2009
>> New Revision: 70270
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=70270&view=rev
>> Log:
>> Massive check in. This changes the "-fast" flag to "-O#" in llc. If
>> you want to
>> use the old behavior, the flag is -O0. This change allows for finer-
>> grained
>> control over which optimizations are run at different -O levels.
>>
>> Most of this work was pretty mechanical. The majority of the fixes
>> came from
>> verifying that a "fast" variable wasn't used anymore. The JIT still
>> uses a
>> "Fast" flag. I'm not 100% sure if it's necessary to change it  
>> there...
>>
>> Modified:
>>   llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
>>   llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
>>   llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>>   llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
>>   llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>>   llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
>>   llvm/trunk/include/llvm/Target/TargetMachine.h
>>   llvm/trunk/include/llvm/Target/TargetOptions.h
>>   llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
>>   llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
>>   llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>>   llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>>   llvm/trunk/lib/Target/ARM/ARM.h
>>   llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
>>   llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
>>   llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>>   llvm/trunk/lib/Target/Alpha/Alpha.h
>>   llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
>>   llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
>>   llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>>   llvm/trunk/lib/Target/CBackend/CBackend.cpp
>>   llvm/trunk/lib/Target/CBackend/CTargetMachine.h
>>   llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>>   llvm/trunk/lib/Target/CellSPU/SPU.h
>>   llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
>>   llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
>>   llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
>>   llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
>>   llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>>   llvm/trunk/lib/Target/IA64/IA64.h
>>   llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
>>   llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
>>   llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
>>   llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>>   llvm/trunk/lib/Target/Mips/Mips.h
>>   llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
>>   llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
>>   llvm/trunk/lib/Target/PIC16/PIC16.h
>>   llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
>>   llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
>>   llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
>>   llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
>>   llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>>   llvm/trunk/lib/Target/PowerPC/PPC.h
>>   llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
>>   llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
>>   llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
>>   llvm/trunk/lib/Target/Sparc/Sparc.h
>>   llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
>>   llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
>>   llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
>>   llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
>>   llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
>>   llvm/trunk/lib/Target/X86/X86.h
>>   llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>>   llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
>>   llvm/trunk/lib/Target/X86/X86TargetMachine.h
>>   llvm/trunk/lib/Target/XCore/XCore.h
>>   llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
>>   llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
>>   llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
>>   llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
>>   llvm/trunk/test/CodeGen/Generic/2006-06-13-
>> ComputeMaskedBitsCrash.ll
>>   llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
>>   llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
>>   llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
>>   llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
>>   llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
>>   llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
>>   llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
>>   llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
>>   llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
>>   llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
>>   llvm/trunk/test/CodeGen/X86/pr1489.ll
>>   llvm/trunk/test/CodeGen/X86/volatile.ll
>>   llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
>>   llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
>>   llvm/trunk/test/DebugInfo/deaddebuglabel.ll
>>   llvm/trunk/test/DebugInfo/forwardDecl.ll
>>   llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
>>   llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
>>   llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
>>   llvm/trunk/tools/llc/llc.cpp
>>   llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
>>   llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Mon Apr 27 19:21:31
>> 2009
>> @@ -65,8 +65,8 @@
>>    // Necessary for external weak linkage support
>>    std::set<const GlobalValue*> ExtWeakSymbols;
>>
>> -    /// Fast - Generating code via fast instruction selection.
>> -    bool Fast;
>> +    /// OptLevel - Generating code at a specific optimization level.
>> +    unsigned OptLevel;
>>  public:
>>    /// Output stream on which we're printing assembly code.
>>    ///
>> @@ -110,8 +110,8 @@
>>    bool VerboseAsm;
>>
>>  protected:
>> -    AsmPrinter(raw_ostream &o, TargetMachine &TM,
>> -               const TargetAsmInfo *T, bool F, bool V);
>> +    explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
>> +                        const TargetAsmInfo *T, unsigned OL, bool  
>> V);
>>
>>  public:
>>    virtual ~AsmPrinter();
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Mon Apr 27
>> 19:21:31 2009
>> @@ -81,7 +81,7 @@
>>  void EndFunction(MachineFunction *MF);
>>
>>  /// ValidDebugInfo - Return true if V represents valid debug info
>> value.
>> -  bool ValidDebugInfo(Value *V, bool FastISel);
>> +  bool ValidDebugInfo(Value *V, unsigned OptLevel);
>>
>>  /// RecordSourceLine - Register a source line with debug info.
>> Returns a
>>  /// unique label ID used to generate a label and provide
>> correspondence to
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>> (original)
>> +++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Mon
>> Apr 27 19:21:31 2009
>> @@ -42,11 +42,11 @@
>>      llvm::linkOcamlGC();
>>      llvm::linkShadowStackGC();
>>
>> -      (void) llvm::createBURRListDAGScheduler(NULL, false);
>> -      (void) llvm::createTDRRListDAGScheduler(NULL, false);
>> -      (void) llvm::createTDListDAGScheduler(NULL, false);
>> -      (void) llvm::createFastDAGScheduler(NULL, false);
>> -      (void) llvm::createDefaultScheduler(NULL, false);
>> +      (void) llvm::createBURRListDAGScheduler(NULL, 3);
>> +      (void) llvm::createTDRRListDAGScheduler(NULL, 3);
>> +      (void) llvm::createTDListDAGScheduler(NULL, 3);
>> +      (void) llvm::createFastDAGScheduler(NULL, 3);
>> +      (void) llvm::createDefaultScheduler(NULL, 3);
>>
>>    }
>>  } ForceCodegenLinking; // Force link by creating a global
>> definition.
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Mon Apr 27
>> 19:21:31 2009
>> @@ -32,7 +32,7 @@
>>
>> class RegisterScheduler : public MachinePassRegistryNode {
>> public:
>> -  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)
>> (SelectionDAGISel*, bool);
>> +  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)
>> (SelectionDAGISel*, unsigned);
>>
>>  static MachinePassRegistry Registry;
>>
>> @@ -64,27 +64,27 @@
>> /// createBURRListDAGScheduler - This creates a bottom up register
>> usage
>> /// reduction list scheduler.
>> ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
>> -                                               bool Fast);
>> +                                               unsigned OptLevel);
>>
>> /// createTDRRListDAGScheduler - This creates a top down register
>> usage
>> /// reduction list scheduler.
>> ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
>> -                                               bool Fast);
>> +                                               unsigned OptLevel);
>>
>> /// createTDListDAGScheduler - This creates a top-down list
>> scheduler with
>> /// a hazard recognizer.
>> ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
>> -                                             bool Fast);
>> +                                             unsigned OptLevel);
>>
>> /// createFastDAGScheduler - This creates a "fast" scheduler.
>> ///
>> ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
>> -                                           bool Fast);
>> +                                           unsigned OptLevel);
>>
>> /// createDefaultScheduler - This creates an instruction scheduler
>> appropriate
>> /// for the target.
>> ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
>> -                                           bool Fast);
>> +                                           unsigned OptLevel);
>>
>> } // end namespace llvm
>>
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Apr 27
>> 19:21:31 2009
>> @@ -202,7 +202,7 @@
>>  /// certain types of nodes together, or eliminating superfluous
>> nodes.  The
>>  /// Level argument controls whether Combine is allowed to produce
>> nodes and
>>  /// types that are illegal on the target.
>> -  void Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast);
>> +  void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned
>> OptLevel);
>>
>>  /// LegalizeTypes - This transforms the SelectionDAG into a
>> SelectionDAG that
>>  /// only uses types natively supported by the target.  Returns
>> "true" if it
>> @@ -218,7 +218,7 @@
>>  ///
>>  /// Note that this is an involved process that may invalidate
>> pointers into
>>  /// the graph.
>> -  void Legalize(bool TypesNeedLegalizing, bool Fast);
>> +  void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
>>
>>  /// RemoveDeadNodes - This method deletes all unreachable nodes in
>> the
>>  /// SelectionDAG.
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Mon Apr 27
>> 19:21:31 2009
>> @@ -51,10 +51,10 @@
>>  MachineBasicBlock *BB;
>>  AliasAnalysis *AA;
>>  GCFunctionInfo *GFI;
>> -  bool Fast;
>> +  unsigned OptLevel;
>>  static char ID;
>>
>> -  explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
>> +  explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
>>  virtual ~SelectionDAGISel();
>>
>>  TargetLowering &getTargetLowering() { return TLI; }
>>
>> Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
>> +++ llvm/trunk/include/llvm/Target/TargetMachine.h Mon Apr 27
>> 19:21:31 2009
>> @@ -213,7 +213,7 @@
>>  virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
>>                                               raw_ostream &,
>>                                               CodeGenFileType,
>> -                                               bool /*Fast*/) {
>> +                                               unsigned /* OptLevel
>> */) {
>>    return FileModel::None;
>>  }
>>
>> @@ -222,7 +222,8 @@
>>  /// used to finish up adding passes to emit the file, if necessary.
>>  ///
>>  virtual bool addPassesToEmitFileFinish(PassManagerBase &,
>> -                                         MachineCodeEmitter *,
>> bool /*Fast*/) {
>> +                                         MachineCodeEmitter *,
>> +                                         unsigned /* OptLevel */) {
>>    return true;
>>  }
>>
>> @@ -234,7 +235,7 @@
>>  ///
>>  virtual bool addPassesToEmitMachineCode(PassManagerBase &,
>>                                          MachineCodeEmitter &,
>> -                                          bool /*Fast*/) {
>> +                                          unsigned /* OptLevel */) {
>>    return true;
>>  }
>>
>> @@ -243,7 +244,8 @@
>>  /// use this.
>>  virtual bool WantsWholeFile() const { return false; }
>>  virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
>> -                                        CodeGenFileType, bool /
>> *Fast*/) {
>> +                                        CodeGenFileType,
>> +                                        unsigned /* OptLevel */) {
>>    return true;
>>  }
>> };
>> @@ -258,16 +260,16 @@
>>  /// addCommonCodeGenPasses - Add standard LLVM codegen passes used
>> for
>>  /// both emitting to assembly files or machine code output.
>>  ///
>> -  bool addCommonCodeGenPasses(PassManagerBase &, bool /*Fast*/);
>> +  bool addCommonCodeGenPasses(PassManagerBase &, unsigned /*
>> OptLevel */);
>>
>> public:
>>
>>  /// addPassesToEmitFile - Add passes to the specified pass manager
>> to get the
>>  /// specified file emitted.  Typically this will involve several
>> steps of code
>> -  /// generation.  If Fast is set to true, the code generator
>> should emit code
>> -  /// as fast as possible, though the generated code may be less
>> efficient.
>> -  /// This method should return FileModel::Error if emission of
>> this file type
>> -  /// is not supported.
>> +  /// generation.  If OptLevel is 0, the code generator should emit
>> code as fast
>> +  /// as possible, though the generated code may be less
>> efficient.  This method
>> +  /// should return FileModel::Error if emission of this file type
>> is not
>> +  /// supported.
>>  ///
>>  /// The default implementation of this method adds components from
>> the
>>  /// LLVM retargetable code generator, invoking the methods below
>> to get
>> @@ -276,14 +278,15 @@
>>  virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
>>                                               raw_ostream &Out,
>>                                               CodeGenFileType
>> FileType,
>> -                                               bool Fast);
>> +                                               unsigned OptLevel);
>>
>>  /// addPassesToEmitFileFinish - If the passes to emit the
>> specified file had
>>  /// to be split up (e.g., to add an object writer pass), this
>> method can be
>>  /// used to finish up adding passes to emit the file, if necessary.
>>  ///
>>  virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
>> -                                         MachineCodeEmitter *MCE,
>> bool Fast);
>> +                                         MachineCodeEmitter *MCE,
>> +                                         unsigned OptLevel);
>>
>>  /// addPassesToEmitMachineCode - Add passes to the specified pass
>> manager to
>>  /// get machine code emitted.  This uses a MachineCodeEmitter
>> object to handle
>> @@ -292,21 +295,22 @@
>>  /// not supported.
>>  ///
>>  virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
>> -                                          MachineCodeEmitter &MCE,
>> bool Fast);
>> +                                          MachineCodeEmitter &MCE,
>> +                                          unsigned OptLevel);
>>
>>  /// Target-Independent Code Generator Pass Configuration Options.
>>
>>  /// addInstSelector - This method should add any "last minute"
>> LLVM->LLVM
>>  /// passes, then install an instruction selector pass, which
>> converts from
>>  /// LLVM code to machine instructions.
>> -  virtual bool addInstSelector(PassManagerBase &, bool /*Fast*/) {
>> +  virtual bool addInstSelector(PassManagerBase &, unsigned /*
>> OptLevel */) {
>>    return true;
>>  }
>>
>>  /// addPreRegAllocPasses - This method may be implemented by
>> targets that want
>>  /// to run passes immediately before register allocation. This
>> should return
>>  /// true if -print-machineinstrs should print after these passes.
>> -  virtual bool addPreRegAlloc(PassManagerBase &, bool /*Fast*/) {
>> +  virtual bool addPreRegAlloc(PassManagerBase &, unsigned /*
>> OptLevel */) {
>>    return false;
>>  }
>>
>> @@ -314,14 +318,14 @@
>>  /// want to run passes after register allocation but before prolog-
>> epilog
>>  /// insertion.  This should return true if -print-machineinstrs
>> should print
>>  /// after these passes.
>> -  virtual bool addPostRegAlloc(PassManagerBase &, bool /*Fast*/) {
>> +  virtual bool addPostRegAlloc(PassManagerBase &, unsigned /*
>> OptLevel */) {
>>    return false;
>>  }
>>
>>  /// addPreEmitPass - This pass may be implemented by targets that
>> want to run
>>  /// passes immediately before machine code is emitted.  This
>> should return
>>  /// true if -print-machineinstrs should print out the code after
>> the passes.
>> -  virtual bool addPreEmitPass(PassManagerBase &, bool /*Fast*/) {
>> +  virtual bool addPreEmitPass(PassManagerBase &, unsigned /*
>> OptLevel */) {
>>    return false;
>>  }
>>
>> @@ -329,7 +333,7 @@
>>  /// addAssemblyEmitter - This pass should be overridden by the
>> target to add
>>  /// the asmprinter, if asm emission is supported.  If this is not
>> supported,
>>  /// 'true' should be returned.
>> -  virtual bool addAssemblyEmitter(PassManagerBase &, bool /*Fast*/,
>> +  virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /*
>> OptLevel */,
>>                                  bool /* VerboseAsmDefault */,
>> raw_ostream &) {
>>    return true;
>>  }
>> @@ -337,7 +341,7 @@
>>  /// addCodeEmitter - This pass should be overridden by the target
>> to add a
>>  /// code emitter, if supported.  If this is not supported, 'true'
>> should be
>>  /// returned. If DumpAsm is true, the generated assembly is
>> printed to cerr.
>> -  virtual bool addCodeEmitter(PassManagerBase &, bool /*Fast*/,
>> +  virtual bool addCodeEmitter(PassManagerBase &, unsigned /*
>> OptLevel */,
>>                              bool /*DumpAsm*/, MachineCodeEmitter
>> &) {
>>    return true;
>>  }
>> @@ -346,7 +350,7 @@
>>  /// a code emitter (without setting flags), if supported.  If this
>> is not
>>  /// supported, 'true' should be returned.  If DumpAsm is true, the
>> generated
>>  /// assembly is printed to cerr.
>> -  virtual bool addSimpleCodeEmitter(PassManagerBase &, bool / 
>> *Fast*/,
>> +  virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /*
>> OptLevel */,
>>                                    bool /*DumpAsm*/,
>> MachineCodeEmitter &) {
>>    return true;
>>  }
>>
>> Modified: llvm/trunk/include/llvm/Target/TargetOptions.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/Target/TargetOptions.h (original)
>> +++ llvm/trunk/include/llvm/Target/TargetOptions.h Mon Apr 27
>> 19:21:31 2009
>> @@ -108,7 +108,7 @@
>>  /// generated.
>>  extern bool DisableJumpTables;
>>
>> -  /// FastISel - This flag enables fast-path instruction selection
>> +  /// EnableFastISel - This flag enables fast-path instruction
>> selection
>>  /// which trades away generated code quality in favor of reducing
>>  /// compile time.
>>  extern bool EnableFastISel;
>>
>> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -42,8 +42,8 @@
>>
>> char AsmPrinter::ID = 0;
>> AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
>> -                       const TargetAsmInfo *T, bool F, bool VDef)
>> -  : MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o),
>> +                       const TargetAsmInfo *T, unsigned OL, bool
>> VDef)
>> +  : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
>>    TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
>>    IsInTextSection(false)
>> {
>>
>> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -3351,7 +3351,7 @@
>>  }
>>
>>  /// ValidDebugInfo - Return true if V represents valid debug info
>> value.
>> -  bool ValidDebugInfo(Value *V, bool FastISel) {
>> +  bool ValidDebugInfo(Value *V, unsigned OptLevel) {
>>    if (!V)
>>      return false;
>>
>> @@ -3393,7 +3393,7 @@
>>    case DW_TAG_lexical_block:
>>      /// FIXME. This interfers with the qualitfy of generated code
>> when
>>      /// during optimization.
>> -      if (FastISel == false)
>> +      if (OptLevel != 0)
>>        return false;
>>    default:
>>      break;
>> @@ -4730,8 +4730,8 @@
>> }
>>
>> /// ValidDebugInfo - Return true if V represents valid debug info
>> value.
>> -bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) {
>> -  return DD && DD->ValidDebugInfo(V, FastISel);
>> +bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
>> +  return DD && DD->ValidDebugInfo(V, OptLevel);
>> }
>>
>> /// RecordSourceLine - Records location information and associates
>> it with a
>>
>> Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Mon Apr 27 19:21:31
>> 2009
>> @@ -55,9 +55,9 @@
>> LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
>>                                       raw_ostream &Out,
>>                                       CodeGenFileType FileType,
>> -                                       bool Fast) {
>> +                                       unsigned OptLevel) {
>>  // Add common CodeGen passes.
>> -  if (addCommonCodeGenPasses(PM, Fast))
>> +  if (addCommonCodeGenPasses(PM, OptLevel))
>>    return FileModel::Error;
>>
>>  // Fold redundant debug labels.
>> @@ -66,17 +66,17 @@
>>  if (PrintMachineCode)
>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>
>> -  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
>> +  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>
>> -  if (!Fast)
>> +  if (OptLevel != 0)
>>    PM.add(createLoopAlignerPass());
>>
>>  switch (FileType) {
>>  default:
>>    break;
>>  case TargetMachine::AssemblyFile:
>> -    if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(), Out))
>> +    if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(),
>> Out))
>>      return FileModel::Error;
>>    return FileModel::AsmFile;
>>  case TargetMachine::ObjectFile:
>> @@ -94,9 +94,9 @@
>> /// finish up adding passes to emit the file, if necessary.
>> bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase  
>> &PM,
>>                                                  MachineCodeEmitter
>> *MCE,
>> -                                                  bool Fast) {
>> +                                                  unsigned
>> OptLevel) {
>>  if (MCE)
>> -    addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
>> +    addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
>>
>>  PM.add(createGCInfoDeleter());
>>
>> @@ -114,15 +114,15 @@
>> ///
>> bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase
>> &PM,
>>
>> MachineCodeEmitter &MCE,
>> -                                                   bool Fast) {
>> +                                                   unsigned
>> OptLevel) {
>>  // Add common CodeGen passes.
>> -  if (addCommonCodeGenPasses(PM, Fast))
>> +  if (addCommonCodeGenPasses(PM, OptLevel))
>>    return true;
>>
>> -  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
>> +  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>
>> -  addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
>> +  addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
>>
>>  PM.add(createGCInfoDeleter());
>>
>> @@ -135,11 +135,12 @@
>> /// addCommonCodeGenPasses - Add standard LLVM codegen passes used  
>> for
>> /// both emitting to assembly files or machine code output.
>> ///
>> -bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
>> bool Fast) {
>> +bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
>> +                                               unsigned OptLevel) {
>>  // Standard LLVM-Level Passes.
>>
>>  // Run loop strength reduction before anything else.
>> -  if (!Fast) {
>> +  if (OptLevel != 0) {
>>    PM.add(createLoopStrengthReducePass(getTargetLowering()));
>>    if (PrintLSR)
>>      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n",
>> &errs()));
>> @@ -153,7 +154,7 @@
>>  // Make sure that no unreachable blocks are instruction selected.
>>  PM.add(createUnreachableBlockEliminationPass());
>>
>> -  if (!Fast)
>> +  if (OptLevel != 0)
>>    PM.add(createCodeGenPreparePass(getTargetLowering()));
>>
>>  PM.add(createStackProtectorPass(getTargetLowering()));
>> @@ -167,38 +168,38 @@
>>
>>  // Enable FastISel with -fast, but allow that to be overridden.
>>  if (EnableFastISelOption == cl::BOU_TRUE ||
>> -      (Fast && EnableFastISelOption != cl::BOU_FALSE))
>> +      (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
>>    EnableFastISel = true;
>>
>>  // Ask the target for an isel.
>> -  if (addInstSelector(PM, Fast))
>> +  if (addInstSelector(PM, OptLevel))
>>    return true;
>>
>>  // Print the instruction selected machine code...
>>  if (PrintMachineCode)
>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>
>> -  if (!Fast) {
>> +  if (OptLevel != 0) {
>>    PM.add(createMachineLICMPass());
>>    PM.add(createMachineSinkingPass());
>>  }
>>
>>  // Run pre-ra passes.
>> -  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
>> +  if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>
>>  // Perform register allocation.
>>  PM.add(createRegisterAllocator());
>>
>>  // Perform stack slot coloring.
>> -  if (!Fast)
>> +  if (OptLevel != 0)
>>    PM.add(createStackSlotColoringPass());
>>
>>  if (PrintMachineCode)  // Print the register-allocated code
>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>
>>  // Run post-ra passes.
>> -  if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
>> +  if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>
>>  if (PrintMachineCode)
>> @@ -216,7 +217,7 @@
>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>
>>  // Second pass scheduler.
>> -  if (!Fast && !DisablePostRAScheduler) {
>> +  if (OptLevel != 0 && !DisablePostRAScheduler) {
>>    PM.add(createPostRAScheduler());
>>
>>    if (PrintMachineCode)
>> @@ -224,7 +225,7 @@
>>  }
>>
>>  // Branch folding must be run after regalloc and prolog/epilog
>> insertion.
>> -  if (!Fast)
>> +  if (OptLevel != 0)
>>    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
>>
>>  if (PrintMachineCode)
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -57,9 +57,9 @@
>>    SelectionDAG &DAG;
>>    const TargetLowering &TLI;
>>    CombineLevel Level;
>> +    unsigned OptLevel;
>>    bool LegalOperations;
>>    bool LegalTypes;
>> -    bool Fast;
>>
>>    // Worklist of all of the nodes that need to be simplified.
>>    std::vector<SDNode*> WorkList;
>> @@ -254,13 +254,13 @@
>>    }
>>
>> public:
>> -    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
>> +    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
>>      : DAG(D),
>>        TLI(D.getTargetLoweringInfo()),
>>        Level(Unrestricted),
>> +        OptLevel(OL),
>>        LegalOperations(false),
>>        LegalTypes(false),
>> -        Fast(fast),
>>        AA(A) {}
>>
>>    /// Run - runs the dag combiner on all nodes in the work list
>> @@ -4784,7 +4784,7 @@
>>  SDValue Ptr   = LD->getBasePtr();
>>
>>  // Try to infer better alignment information than the load already
>> has.
>> -  if (!Fast && LD->isUnindexed()) {
>> +  if (OptLevel != 0 && LD->isUnindexed()) {
>>    if (unsigned Align = InferAlignment(Ptr, DAG)) {
>>      if (Align > LD->getAlignment())
>>        return DAG.getExtLoad(LD->getExtensionType(), N-
>>> getDebugLoc(),
>> @@ -4904,7 +4904,7 @@
>>  SDValue Ptr   = ST->getBasePtr();
>>
>>  // Try to infer better alignment information than the store
>> already has.
>> -  if (!Fast && ST->isUnindexed()) {
>> +  if (OptLevel != 0 && ST->isUnindexed()) {
>>    if (unsigned Align = InferAlignment(Ptr, DAG)) {
>>      if (Align > ST->getAlignment())
>>        return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
>> @@ -6084,8 +6084,9 @@
>>
>> // SelectionDAG::Combine - This is the entry point for the file.
>> //
>> -void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
>> bool Fast) {
>> +void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
>> +                           unsigned OptLevel) {
>>  /// run - This is the main entry point to this class.
>>  ///
>> -  DAGCombiner(*this, AA, Fast).Run(Level);
>> +  DAGCombiner(*this, AA, OptLevel).Run(Level);
>> }
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -327,7 +327,7 @@
>>  default: break;
>>  case Intrinsic::dbg_stoppoint: {
>>    DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
>> -    if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) {
>> +    if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
>>      DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
>>      std::string Dir, FN;
>>      unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
>> @@ -344,7 +344,7 @@
>>  }
>>  case Intrinsic::dbg_region_start: {
>>    DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
>> -    if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) {
>> +    if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
>>      unsigned ID =
>>        DW->RecordRegionStart(cast<GlobalVariable>(RSI-
>>> getContext()));
>>      const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
>> @@ -354,7 +354,7 @@
>>  }
>>  case Intrinsic::dbg_region_end: {
>>    DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
>> -    if (DW && DW->ValidDebugInfo(REI->getContext(), true)) {
>> +    if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
>>     unsigned ID = 0;
>>     DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
>>     if (!Subprogram.isNull() && !
>> Subprogram.describes(MF.getFunction())) {
>> @@ -380,7 +380,7 @@
>>    DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
>>    Value *SP = FSI->getSubprogram();
>>
>> -    if (DW->ValidDebugInfo(SP, true)) {
>> +    if (DW->ValidDebugInfo(SP, 0)) {
>>      // llvm.dbg.func.start implicitly defines a dbg_stoppoint
>> which is what
>>      // (most?) gdb expects.
>>      DebugLoc PrevLoc = DL;
>> @@ -425,7 +425,7 @@
>>  case Intrinsic::dbg_declare: {
>>    DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
>>    Value *Variable = DI->getVariable();
>> -    if (DW && DW->ValidDebugInfo(Variable, true)) {
>> +    if (DW && DW->ValidDebugInfo(Variable, 0)) {
>>      // Determine the address of the declared object.
>>      Value *Address = DI->getAddress();
>>      if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -55,8 +55,8 @@
>> class VISIBILITY_HIDDEN SelectionDAGLegalize {
>>  TargetLowering &TLI;
>>  SelectionDAG &DAG;
>> +  unsigned OptLevel;
>>  bool TypesNeedLegalizing;
>> -  bool Fast;
>>
>>  // Libcall insertion helpers.
>>
>> @@ -139,7 +139,7 @@
>>
>> public:
>>  explicit SelectionDAGLegalize(SelectionDAG &DAG, bool
>> TypesNeedLegalizing,
>> -                                bool fast);
>> +                                unsigned ol);
>>
>>  /// getTypeAction - Return how we should legalize values of this
>> type, either
>>  /// it is already legal or we need to expand it into multiple
>> registers of
>> @@ -345,9 +345,9 @@
>> }
>>
>> SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
>> -                                           bool types, bool fast)
>> -  : TLI(dag.getTargetLoweringInfo()), DAG(dag),
>> TypesNeedLegalizing(types),
>> -    Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
>> +                                           bool types, unsigned ol)
>> +  : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
>> +    TypesNeedLegalizing(types),
>> ValueTypeActions(TLI.getValueTypeActions()) {
>>  assert(MVT::LAST_VALUETYPE <= 32 &&
>>         "Too many value types for ValueTypeActions to hold!");
>> }
>> @@ -1271,7 +1271,7 @@
>>        unsigned Line = DSP->getLine();
>>        unsigned Col = DSP->getColumn();
>>
>> -        if (Fast) {
>> +        if (OptLevel == 0) {
>>          // A bit self-referential to have DebugLoc on Debug_Loc
>> nodes, but it
>>          // won't hurt anything.
>>          if (useDEBUG_LOC) {
>> @@ -8566,9 +8566,9 @@
>>
>> // SelectionDAG::Legalize - This is the entry point for the file.
>> //
>> -void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
>> +void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned
>> OptLevel) {
>>  /// run - This is the main entry point to this class.
>>  ///
>> -  SelectionDAGLegalize(*this, TypesNeedLegalizing,
>> Fast).LegalizeDAG();
>> +  SelectionDAGLegalize(*this, TypesNeedLegalizing,
>> OptLevel).LegalizeDAG();
>> }
>>
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp  
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Mon Apr
>> 27 19:21:31 2009
>> @@ -630,6 +630,6 @@
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> llvm::ScheduleDAGSDNodes *
>> -llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
>> +llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>  return new ScheduleDAGFast(*IS->MF);
>> }
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp  
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon Apr
>> 27 19:21:31 2009
>> @@ -261,7 +261,7 @@
>> /// new hazard recognizer. This scheduler takes ownership of the
>> hazard
>> /// recognizer and deletes it when done.
>> ScheduleDAGSDNodes *
>> -llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) {
>> +llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>  return new ScheduleDAGList(*IS->MF,
>>                             new LatencyPriorityQueue(),
>>                             IS->CreateTargetHazardRecognizer());
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon
>> Apr 27 19:21:31 2009
>> @@ -1505,7 +1505,7 @@
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> llvm::ScheduleDAGSDNodes *
>> -llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
>> +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>  const TargetMachine &TM = IS->TM;
>>  const TargetInstrInfo *TII = TM.getInstrInfo();
>>  const TargetRegisterInfo *TRI = TM.getRegisterInfo();
>> @@ -1519,7 +1519,7 @@
>> }
>>
>> llvm::ScheduleDAGSDNodes *
>> -llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
>> +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>  const TargetMachine &TM = IS->TM;
>>  const TargetInstrInfo *TII = TM.getInstrInfo();
>>  const TargetRegisterInfo *TRI = TM.getRegisterInfo();
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon
>> Apr 27 19:21:31 2009
>> @@ -3910,9 +3910,9 @@
>>  case Intrinsic::dbg_stoppoint: {
>>    DwarfWriter *DW = DAG.getDwarfWriter();
>>    DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
>> -    if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
>> +    if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
>>      MachineFunction &MF = DAG.getMachineFunction();
>> -      if (Fast)
>> +      if (OptLevel == 0)
>>        DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
>>                                        SPI.getLine(),
>>                                        SPI.getColumn(),
>> @@ -3930,7 +3930,8 @@
>>  case Intrinsic::dbg_region_start: {
>>    DwarfWriter *DW = DAG.getDwarfWriter();
>>    DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
>> -    if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
>> +
>> +    if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) {
>>      unsigned LabelID =
>>        DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
>>      DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
>> @@ -3942,8 +3943,8 @@
>>  case Intrinsic::dbg_region_end: {
>>    DwarfWriter *DW = DAG.getDwarfWriter();
>>    DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
>> -    if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
>>
>> +    if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) {
>>      MachineFunction &MF = DAG.getMachineFunction();
>>      DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
>>      std::string SPName;
>> @@ -3952,7 +3953,7 @@
>>          && strcmp(SPName.c_str(), MF.getFunction()-
>>> getNameStart())) {
>>          // This is end of inlined function. Debugging information
>> for
>>          // inlined function is not handled yet (only supported by
>> FastISel).
>> -        if (Fast) {
>> +        if (OptLevel == 0) {
>>          unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
>>          if (ID != 0)
>>            // Returned ID is 0 if this is unbalanced "end of inlined
>> @@ -3978,9 +3979,9 @@
>>    if (!DW) return 0;
>>    DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
>>    Value *SP = FSI.getSubprogram();
>> -    if (SP && DW->ValidDebugInfo(SP, Fast)) {
>> -        MachineFunction &MF = DAG.getMachineFunction();
>> -      if (Fast) {
>> +    if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
>> +      MachineFunction &MF = DAG.getMachineFunction();
>> +      if (OptLevel == 0) {
>>        // llvm.dbg.func.start implicitly defines a dbg_stoppoint
>> which is what
>>        // (most?) gdb expects.
>>        DebugLoc PrevLoc = CurDebugLoc;
>> @@ -4051,11 +4052,11 @@
>>    return 0;
>>  }
>>  case Intrinsic::dbg_declare: {
>> -    if (Fast) {
>> +    if (OptLevel == 0) {
>>      DwarfWriter *DW = DAG.getDwarfWriter();
>>      DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
>>      Value *Variable = DI.getVariable();
>> -      if (DW && DW->ValidDebugInfo(Variable, Fast))
>> +      if (DW && DW->ValidDebugInfo(Variable, OptLevel))
>>        DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other,
>> getRoot(),
>>                                getValue(DI.getAddress()),
>> getValue(Variable)));
>>    } else {
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h  
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Mon Apr
>> 27 19:21:31 2009
>> @@ -355,17 +355,17 @@
>>  ///
>>  FunctionLoweringInfo &FuncInfo;
>>
>> -  /// Fast - We are in -fast mode.
>> +  /// OptLevel - What optimization level we're generating code for.
>>  ///
>> -  bool Fast;
>> +  unsigned OptLevel;
>>
>>  /// GFI - Garbage collection metadata for the function.
>>  GCFunctionInfo *GFI;
>>
>>  SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
>> -                       FunctionLoweringInfo &funcinfo, bool fast)
>> +                       FunctionLoweringInfo &funcinfo, unsigned ol)
>>    : CurDebugLoc(DebugLoc::getUnknownLoc()),
>> -      TLI(tli), DAG(dag), FuncInfo(funcinfo), Fast(fast) {
>> +      TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
>>  }
>>
>>  void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr
>> 27 19:21:31 2009
>> @@ -136,16 +136,16 @@
>>  /// createDefaultScheduler - This creates an instruction scheduler
>> appropriate
>>  /// for the target.
>>  ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
>> -                                             bool Fast) {
>> +                                             unsigned OptLevel) {
>>    const TargetLowering &TLI = IS->getTargetLowering();
>>
>> -    if (Fast)
>> -      return createFastDAGScheduler(IS, Fast);
>> +    if (OptLevel == 0)
>> +      return createFastDAGScheduler(IS, OptLevel);
>>    if (TLI.getSchedulingPreference() ==
>> TargetLowering::SchedulingForLatency)
>> -      return createTDListDAGScheduler(IS, Fast);
>> +      return createTDListDAGScheduler(IS, OptLevel);
>>    assert(TLI.getSchedulingPreference() ==
>>         TargetLowering::SchedulingForRegPressure && "Unknown sched
>> type!");
>> -    return createBURRListDAGScheduler(IS, Fast);
>> +    return createBURRListDAGScheduler(IS, OptLevel);
>>  }
>> }
>>
>> @@ -262,13 +262,13 @@
>> // SelectionDAGISel code
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> -SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
>> +SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
>>  FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
>>  FuncInfo(new FunctionLoweringInfo(TLI)),
>>  CurDAG(new SelectionDAG(TLI, *FuncInfo)),
>> -  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)),
>> +  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)),
>>  GFI(),
>> -  Fast(fast),
>> +  OptLevel(OL),
>>  DAGSize(0)
>> {}
>>
>> @@ -576,9 +576,9 @@
>>  // Run the DAG combiner in pre-legalize mode.
>>  if (TimePassesIsEnabled) {
>>    NamedRegionTimer T("DAG Combining 1", GroupName);
>> -    CurDAG->Combine(Unrestricted, *AA, Fast);
>> +    CurDAG->Combine(Unrestricted, *AA, OptLevel);
>>  } else {
>> -    CurDAG->Combine(Unrestricted, *AA, Fast);
>> +    CurDAG->Combine(Unrestricted, *AA, OptLevel);
>>  }
>>
>>  DOUT << "Optimized lowered selection DAG:\n";
>> @@ -608,9 +608,9 @@
>>      // Run the DAG combiner in post-type-legalize mode.
>>      if (TimePassesIsEnabled) {
>>        NamedRegionTimer T("DAG Combining after legalize types",
>> GroupName);
>> -        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
>> +        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
>>      } else {
>> -        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
>> +        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
>>      }
>>
>>      DOUT << "Optimized type-legalized selection DAG:\n";
>> @@ -622,9 +622,9 @@
>>
>>  if (TimePassesIsEnabled) {
>>    NamedRegionTimer T("DAG Legalization", GroupName);
>> -    CurDAG->Legalize(DisableLegalizeTypes, Fast);
>> +    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
>>  } else {
>> -    CurDAG->Legalize(DisableLegalizeTypes, Fast);
>> +    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
>>  }
>>
>>  DOUT << "Legalized selection DAG:\n";
>> @@ -635,9 +635,9 @@
>>  // Run the DAG combiner in post-legalize mode.
>>  if (TimePassesIsEnabled) {
>>    NamedRegionTimer T("DAG Combining 2", GroupName);
>> -    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
>> +    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
>>  } else {
>> -    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
>> +    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
>>  }
>>
>>  DOUT << "Optimized legalized selection DAG:\n";
>> @@ -645,7 +645,7 @@
>>
>>  if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
>>
>> -  if (!Fast)
>> +  if (OptLevel != 0)
>>    ComputeLiveOutVRegInfo();
>>
>>  // Third, instruction select all of the operations to machine
>> code, adding the
>> @@ -1082,7 +1082,7 @@
>>    RegisterScheduler::setDefault(Ctor);
>>  }
>>
>> -  return Ctor(this, Fast);
>> +  return Ctor(this, OptLevel);
>> }
>>
>> ScheduleHazardRecognizer
>> *SelectionDAGISel::CreateTargetHazardRecognizer() {
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARM.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARM.h (original)
>> +++ llvm/trunk/lib/Target/ARM/ARM.h Mon Apr 27 19:21:31 2009
>> @@ -91,7 +91,7 @@
>> FunctionPass *createARMISelDag(ARMTargetMachine &TM);
>> FunctionPass *createARMCodePrinterPass(raw_ostream &O,
>>                                       ARMTargetMachine &TM,
>> -                                       bool Fast, bool Verbose);
>> +                                       unsigned OptLevel, bool
>> Verbose);
>> FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
>>                                       MachineCodeEmitter &MCE);
>> FunctionPass *createARMLoadStoreOptimizationPass();
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -138,35 +138,37 @@
>>
>>
>> // Pass Pipeline Configuration
>> -bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, bool
>> Fast) {
>> +bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
>> unsigned OptLevel) {
>>  PM.add(createARMISelDag(*this));
>>  return false;
>> }
>>
>> -bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>> Fast) {
>> +bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned
>> OptLevel) {
>>  // FIXME: temporarily disabling load / store optimization pass for
>> Thumb mode.
>> -  if (!Fast && !DisableLdStOpti && !Subtarget.isThumb())
>> +  if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
>>    PM.add(createARMLoadStoreOptimizationPass());
>>
>> -  if (!Fast && !DisableIfConversion && !Subtarget.isThumb())
>> +  if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
>>    PM.add(createIfConverterPass());
>>
>>  PM.add(createARMConstantIslandPass());
>>  return true;
>> }
>>
>> -bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool
>> Fast,
>> -                                          bool Verbose, raw_ostream
>> &Out) {
>> +bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>> +                                          unsigned OptLevel,
>> +                                          bool Verbose,
>> +                                          raw_ostream &Out) {
>>  // Output assembly language.
>>  assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>  if (AsmPrinterCtor)
>> -    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
>> +    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>>
>>  return false;
>> }
>>
>>
>> -bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, bool  
>> Fast,
>> +bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                      bool DumpAsm,
>> MachineCodeEmitter &MCE) {
>>  // FIXME: Move this to TargetJITInfo!
>>  if (DefRelocModel == Reloc::Default)
>> @@ -177,20 +179,22 @@
>>  if (DumpAsm) {
>>    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>    if (AsmPrinterCtor)
>> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>  }
>>
>>  return false;
>> }
>>
>> -bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>> bool Fast,
>> -                                        bool DumpAsm,
>> MachineCodeEmitter &MCE) {
>> +bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>> +                                            unsigned OptLevel,
>> +                                            bool DumpAsm,
>> +                                            MachineCodeEmitter
>> &MCE) {
>>  // Machine code emitter pass for ARM.
>>  PM.add(createARMCodeEmitterPass(*this, MCE));
>>  if (DumpAsm) {
>>    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>    if (AsmPrinterCtor)
>> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>  }
>>
>>  return false;
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Mon Apr 27 19:21:31
>> 2009
>> @@ -41,7 +41,7 @@
>>  // set this functions to ctor pointer at startup time if they are
>> linked in.
>>  typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>>                                            ARMTargetMachine &tm,
>> -                                            bool fast, bool  
>> verbose);
>> +                                            unsigned OptLevel, bool
>> verbose);
>>  static AsmPrinterCtorFn AsmPrinterCtor;
>>
>> public:
>> @@ -69,13 +69,13 @@
>>  virtual const TargetAsmInfo *createTargetAsmInfo() const;
>>
>>  // Pass Pipeline Configuration
>> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                  bool Verbose, raw_ostream &Out);
>> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned  
>> OptLevel,
>>                              bool DumpAsm, MachineCodeEmitter &MCE);
>> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                    bool DumpAsm, MachineCodeEmitter
>> &MCE);
>> };
>>
>>
>> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Mon Apr
>> 27 19:21:31 2009
>> @@ -80,9 +80,9 @@
>>    /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
>>    bool InCPMode;
>>  public:
>> -    ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
>> -                  const TargetAsmInfo *T, bool F, bool V)
>> -      : AsmPrinter(O, TM, T, F, V), DW(0), MMI(NULL), AFI(NULL),
>> MCP(NULL),
>> +    explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
>> +                           const TargetAsmInfo *T, unsigned OL,
>> bool V)
>> +      : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL),
>> MCP(NULL),
>>        InCPMode(false) {
>>      Subtarget = &TM.getSubtarget<ARMSubtarget>();
>>    }
>> @@ -1061,8 +1061,8 @@
>> ///
>> FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
>>                                             ARMTargetMachine &tm,
>> -                                             bool fast, bool
>> verbose) {
>> -  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>> verbose);
>> +                                             unsigned OptLevel,
>> bool verbose) {
>> +  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
>> verbose);
>> }
>>
>> namespace {
>>
>> Modified: llvm/trunk/lib/Target/Alpha/Alpha.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Alpha/Alpha.h (original)
>> +++ llvm/trunk/lib/Target/Alpha/Alpha.h Mon Apr 27 19:21:31 2009
>> @@ -26,7 +26,7 @@
>>  FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
>>  FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
>>                                           TargetMachine &TM,
>> -                                           bool Fast, bool Verbose);
>> +                                           unsigned OptLevel, bool
>> Verbose);
>>  FunctionPass *createAlphaPatternInstructionSelector(TargetMachine
>> &TM);
>>  FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
>>                                           MachineCodeEmitter &MCE);
>>
>> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
>> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -76,31 +76,34 @@
>> // Pass Pipeline Configuration
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> -bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, bool
>> Fast) {
>> +bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
>> +                                         unsigned OptLevel) {
>>  PM.add(createAlphaISelDag(*this));
>>  return false;
>> }
>> -bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>> Fast) {
>> +bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
>> +                                        unsigned OptLevel) {
>>  // Must run branch selection immediately preceding the asm printer
>>  PM.add(createAlphaBranchSelectionPass());
>>  return false;
>> }
>> -bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>> bool Fast,
>> +bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>> +                                            unsigned OptLevel,
>>                                            bool Verbose,
>>                                            raw_ostream &Out) {
>>  PM.add(createAlphaLLRPPass(*this));
>> -  PM.add(createAlphaCodePrinterPass(Out, *this, Fast, Verbose));
>> +  PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
>>  return false;
>> }
>> -bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, bool
>> Fast,
>> +bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
>> unsigned OptLevel,
>>                                        bool DumpAsm,
>> MachineCodeEmitter &MCE) {
>>  PM.add(createAlphaCodeEmitterPass(*this, MCE));
>>  if (DumpAsm)
>> -    PM.add(createAlphaCodePrinterPass(errs(), *this, Fast, true));
>> +    PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel,
>> true));
>>  return false;
>> }
>> bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>> -                                              bool Fast, bool
>> DumpAsm,
>> +                                              unsigned OptLevel,
>> bool DumpAsm,
>>                                              MachineCodeEmitter
>> &MCE) {
>> -  return addCodeEmitter(PM, Fast, DumpAsm, MCE);
>> +  return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
>> }
>>
>> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original)
>> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Mon Apr 27
>> 19:21:31 2009
>> @@ -58,13 +58,13 @@
>>  static unsigned getModuleMatchQuality(const Module &M);
>>
>>  // Pass Pipeline Configuration
>> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                  bool Verbose, raw_ostream &Out);
>> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned  
>> OptLevel,
>>                              bool DumpAsm, MachineCodeEmitter &MCE);
>> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                    bool DumpAsm, MachineCodeEmitter
>> &MCE);
>> };
>>
>>
>> Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Mon
>> Apr 27 19:21:31 2009
>> @@ -36,9 +36,9 @@
>>    /// Unique incrementer for label values for referencing Global
>> values.
>>    ///
>>
>> -    AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
>> -                    const TargetAsmInfo *T, bool F, bool V)
>> -      : AsmPrinter(o, tm, T, F, V) {}
>> +    explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
>> +                             const TargetAsmInfo *T, unsigned OL,
>> bool V)
>> +      : AsmPrinter(o, tm, T, OL, V) {}
>>
>>    virtual const char *getPassName() const {
>>      return "Alpha Assembly Printer";
>> @@ -68,8 +68,9 @@
>> ///
>> FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
>>                                               TargetMachine &tm,
>> -                                               bool fast, bool
>> verbose) {
>> -  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>> verbose);
>> +                                               unsigned OptLevel,
>> +                                               bool verbose) {
>> +  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>> OptLevel, verbose);
>> }
>>
>> #include "AlphaGenAsmWriter.inc"
>>
>> Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
>> +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Apr 27 19:21:31
>> 2009
>> @@ -3587,7 +3587,7 @@
>> bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>>                                              raw_ostream &o,
>>                                              CodeGenFileType
>> FileType,
>> -                                              bool Fast) {
>> +                                              unsigned OptLevel) {
>>  if (FileType != TargetMachine::AssemblyFile) return true;
>>
>>  PM.add(createGCLoweringPass());
>>
>> Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
>> +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Mon Apr 27
>> 19:21:31 2009
>> @@ -27,7 +27,8 @@
>>
>>  virtual bool WantsWholeFile() const { return true; }
>>  virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream
>> &Out,
>> -                                        CodeGenFileType FileType,
>> bool Fast);
>> +                                        CodeGenFileType FileType,
>> +                                        unsigned OptLevel);
>>
>>  // This class always works, but must be requested explicitly on
>>  // llc command line.
>>
>> Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Mon
>> Apr 27 19:21:31 2009
>> @@ -48,9 +48,9 @@
>>  class VISIBILITY_HIDDEN SPUAsmPrinter : public AsmPrinter {
>>    std::set<std::string> FnStubs, GVStubs;
>>  public:
>> -    SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
>> -                  const TargetAsmInfo *T, bool F, bool V) :
>> -      AsmPrinter(O, TM, T, F, V) {}
>> +    explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
>> +                           const TargetAsmInfo *T, unsigned OL,
>> bool V) :
>> +      AsmPrinter(O, TM, T, OL, V) {}
>>
>>    virtual const char *getPassName() const {
>>      return "STI CBEA SPU Assembly Printer";
>> @@ -615,6 +615,6 @@
>> ///
>> FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
>>                                            SPUTargetMachine &tm,
>> -                                            bool fast, bool
>> verbose) {
>> -  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>> verbose);
>> +                                            unsigned OptLevel, bool
>> verbose) {
>> +  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>> OptLevel, verbose);
>> }
>>
>> Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
>> +++ llvm/trunk/lib/Target/CellSPU/SPU.h Mon Apr 27 19:21:31 2009
>> @@ -25,7 +25,7 @@
>>  FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
>>  FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
>>                                        SPUTargetMachine &tm,
>> -                                        bool fast, bool verbose);
>> +                                        unsigned OptLevel, bool
>> verbose);
>>
>>  /*--== Utility functions/predicates/etc used all over the place: --
>> ==*/
>>  //! Predicate test for a signed 10-bit value
>>
>> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
>> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -81,15 +81,17 @@
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> bool
>> -SPUTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast)
>> +SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned
>> OptLevel)
>> {
>>  // Install an instruction selector.
>>  PM.add(createSPUISelDag(*this));
>>  return false;
>> }
>>
>> -bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool
>> Fast,
>> -                                          bool Verbose, raw_ostream
>> &Out) {
>> -  PM.add(createSPUAsmPrinterPass(Out, *this, Fast, Verbose));
>> +bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>> +                                          unsigned OptLevel,
>> +                                          bool Verbose,
>> +                                          raw_ostream &Out) {
>> +  PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
>>  return false;
>> }
>>
>> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original)
>> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Mon Apr 27
>> 19:21:31 2009
>> @@ -83,9 +83,9 @@
>>  }
>>
>>  // Pass Pipeline Configuration
>> -  virtual bool addInstSelector(PassManagerBase &PM, bool /*Fast*/);
>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool / 
>> *Fast*/,
>> -                                  bool /*Verbose*/, raw_ostream
>> &Out);
>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>> +                                  bool Verbose, raw_ostream &Out);
>> };
>>
>> } // end namespace llvm
>>
>> Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
>> +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -1995,7 +1995,7 @@
>> bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>>                                                raw_ostream &o,
>>                                                CodeGenFileType
>> FileType,
>> -                                                bool Fast) {
>> +                                                unsigned OptLevel) {
>>  if (FileType != TargetMachine::AssemblyFile) return true;
>>  PM.add(new CppWriter(o));
>>  return false;
>>
>> Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
>> +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Mon Apr 27
>> 19:21:31 2009
>> @@ -29,7 +29,8 @@
>>
>>  virtual bool WantsWholeFile() const { return true; }
>>  virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream
>> &Out,
>> -                                        CodeGenFileType FileType,
>> bool Fast);
>> +                                        CodeGenFileType FileType,
>> +                                        unsigned OptLevel);
>>
>>  // This class always works, but shouldn't be the default in most
>> cases.
>>  static unsigned getModuleMatchQuality(const Module &M) { return 1; }
>>
>> Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Mon Apr
>> 27 19:21:31 2009
>> @@ -37,9 +37,9 @@
>>  class IA64AsmPrinter : public AsmPrinter {
>>    std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
>>  public:
>> -    IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
>> -                   const TargetAsmInfo *T, bool F, bool V)
>> -      : AsmPrinter(O, TM, T, F, V) {}
>> +    explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
>> +                            const TargetAsmInfo *T, unsigned OL,
>> bool V)
>> +      : AsmPrinter(O, TM, T, OL, V) {}
>>
>>    virtual const char *getPassName() const {
>>      return "IA64 Assembly Printer";
>> @@ -370,6 +370,7 @@
>> ///
>> FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
>>                                              IA64TargetMachine &tm,
>> -                                              bool fast, bool
>> verbose) {
>> -  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>> verbose);
>> +                                              unsigned OptLevel,
>> +                                              bool verbose) {
>> +  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
>> verbose);
>> }
>>
>> Modified: llvm/trunk/lib/Target/IA64/IA64.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/IA64/IA64.h (original)
>> +++ llvm/trunk/lib/Target/IA64/IA64.h Mon Apr 27 19:21:31 2009
>> @@ -37,7 +37,7 @@
>> ///
>> FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
>>                                        IA64TargetMachine &tm,
>> -                                        bool fast, bool verbose);
>> +                                        unsigned OptLevel, bool
>> verbose);
>>
>> } // End llvm namespace
>>
>>
>> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original)
>> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -72,19 +72,21 @@
>> // Pass Pipeline Configuration
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> -bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, bool
>> Fast) {
>> +bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,
>> unsigned OptLEvel){
>>  PM.add(createIA64DAGToDAGInstructionSelector(*this));
>>  return false;
>> }
>>
>> -bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>> Fast) {
>> +bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,
>> unsigned OptLevel) {
>>  // Make sure everything is bundled happily
>>  PM.add(createIA64BundlingPass(*this));
>>  return true;
>> }
>> -bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>> bool Fast,
>> -                                           bool Verbose,
>> raw_ostream &Out) {
>> -  PM.add(createIA64CodePrinterPass(Out, *this, Fast, Verbose));
>> +bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>> +                                           unsigned OptLevel,
>> +                                           bool Verbose,
>> +                                           raw_ostream &Out) {
>> +  PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
>>  return false;
>> }
>>
>>
>> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.h (original)
>> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.h Mon Apr 27
>> 19:21:31 2009
>> @@ -51,9 +51,9 @@
>>  static unsigned getModuleMatchQuality(const Module &M);
>>
>>  // Pass Pipeline Configuration
>> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                  bool Verbose, raw_ostream &Out);
>> };
>> } // End llvm namespace
>>
>> Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
>> +++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Mon Apr 27 19:21:31  
>> 2009
>> @@ -35,7 +35,8 @@
>>
>>    virtual bool WantsWholeFile() const { return true; }
>>    virtual bool addPassesToEmitWholeFile(PassManager &PM,
>> raw_ostream &Out,
>> -                                         CodeGenFileType FileType,
>> bool Fast);
>> +                                          CodeGenFileType FileType,
>> +                                          unsigned OptLevel);
>>
>>    // This class always works, but shouldn't be the default in most
>> cases.
>>    static unsigned getModuleMatchQuality(const Module &M) { return
>> 1; }
>> @@ -1662,7 +1663,8 @@
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM,
>> raw_ostream &o,
>> -                                          CodeGenFileType FileType,
>> bool Fast)
>> +                                          CodeGenFileType FileType,
>> +                                          unsigned OptLevel)
>> {
>>  if (FileType != TargetMachine::AssemblyFile) return true;
>>  MSILWriter* Writer = new MSILWriter(o);
>>
>> Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Mon Apr
>> 27 19:21:31 2009
>> @@ -49,9 +49,9 @@
>>  class VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
>>    const MipsSubtarget *Subtarget;
>>  public:
>> -    MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
>> -                   const TargetAsmInfo *T, bool F, bool V)
>> -      : AsmPrinter(O, TM, T, F, V) {
>> +    explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
>> +                            const TargetAsmInfo *T, unsigned OL,
>> bool V)
>> +      : AsmPrinter(O, TM, T, OL, V) {
>>      Subtarget = &TM.getSubtarget<MipsSubtarget>();
>>    }
>>
>> @@ -91,8 +91,8 @@
>> /// regardless of whether the function is in SSA form.
>> FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
>>                                              MipsTargetMachine &tm,
>> -                                              bool fast, bool
>> verbose) {
>> -  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>> verbose);
>> +                                              unsigned OptLevel,
>> bool verbose) {
>> +  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
>> verbose);
>> }
>>
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> Modified: llvm/trunk/lib/Target/Mips/Mips.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Mips/Mips.h (original)
>> +++ llvm/trunk/lib/Target/Mips/Mips.h Mon Apr 27 19:21:31 2009
>> @@ -25,7 +25,7 @@
>>  FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
>>  FunctionPass *createMipsCodePrinterPass(raw_ostream &OS,
>>                                          MipsTargetMachine &TM,
>> -                                          bool Fast, bool Verbose);
>> +                                          unsigned OptLevel, bool
>> Verbose);
>> } // end namespace llvm;
>>
>> // Defines symbolic names for Mips registers.  This defines a
>> mapping from
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -105,7 +105,7 @@
>> // Install an instruction selector pass using
>> // the ISelDag to gen Mips code.
>> bool MipsTargetMachine::
>> -addInstSelector(PassManagerBase &PM, bool Fast)
>> +addInstSelector(PassManagerBase &PM, unsigned OptLevel)
>> {
>>  PM.add(createMipsISelDag(*this));
>>  return false;
>> @@ -115,7 +115,7 @@
>> // machine code is emitted. return true if -print-machineinstrs  
>> should
>> // print out the code after the passes.
>> bool MipsTargetMachine::
>> -addPreEmitPass(PassManagerBase &PM, bool Fast)
>> +addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
>> {
>>  PM.add(createMipsDelaySlotFillerPass(*this));
>>  return true;
>> @@ -124,10 +124,10 @@
>> // Implements the AssemblyEmitter for the target. Must return
>> // true if AssemblyEmitter is supported
>> bool MipsTargetMachine::
>> -addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>> +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
>>                   bool Verbose, raw_ostream &Out)
>> {
>>  // Output assembly language.
>> -  PM.add(createMipsCodePrinterPass(Out, *this, Fast, Verbose));
>> +  PM.add(createMipsCodePrinterPass(Out, *this, OptLevel, Verbose));
>>  return false;
>> }
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Mon Apr 27
>> 19:21:31 2009
>> @@ -57,9 +57,9 @@
>>    static unsigned getModuleMatchQuality(const Module &M);
>>
>>    // Pass Pipeline Configuration
>> -    virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>> -    virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>> -    virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>> +    virtual bool addInstSelector(PassManagerBase &PM, unsigned
>> OptLevel);
>> +    virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>> OptLevel);
>> +    virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                    bool Verbose, raw_ostream &Out);
>>  };
>>
>>
>> Modified: llvm/trunk/lib/Target/PIC16/PIC16.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/PIC16/PIC16.h (original)
>> +++ llvm/trunk/lib/Target/PIC16/PIC16.h Mon Apr 27 19:21:31 2009
>> @@ -75,7 +75,7 @@
>>  FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
>>  FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
>>                                           PIC16TargetMachine &TM,
>> -                                           bool Fast, bool Verbose);
>> +                                           unsigned OptLevel, bool
>> Verbose);
>> } // end namespace llvm;
>>
>> // Defines symbolic names for PIC16 registers.  This defines a
>> mapping from
>>
>> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -161,8 +161,9 @@
>> ///
>> FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
>>                                               PIC16TargetMachine &tm,
>> -                                               bool fast, bool
>> verbose) {
>> -  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>> verbose);
>> +                                               unsigned OptLevel,
>> +                                               bool verbose) {
>> +  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(),
>> OptLevel, verbose);
>> }
>>
>> void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int
>> opNum) {
>>
>> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
>> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Mon Apr 27
>> 19:21:31 2009
>> @@ -24,9 +24,9 @@
>>
>> namespace llvm {
>>  struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
>> -  PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
>> -                    const TargetAsmInfo *T, bool F, bool V)
>> -      : AsmPrinter(O, TM, T, F, V) {
>> +    explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
>> +                             const TargetAsmInfo *T, unsigned OL,
>> bool V)
>> +      : AsmPrinter(O, TM, T, OL, V) {
>>      CurBank = "";
>>      FunctionLabelBegin = '@';
>>      IsRomData = false;
>>
>> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original)
>> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -55,17 +55,18 @@
>>  return new PIC16TargetAsmInfo(*this);
>> }
>>
>> -bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool
>> Fast) {
>> +bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
>> +                                         unsigned OptLevel) {
>>  // Install an instruction selector.
>>  PM.add(createPIC16ISelDag(*this));
>>  return false;
>> }
>>
>> bool PIC16TargetMachine::
>> -addAssemblyEmitter(PassManagerBase &PM, bool Fast, bool Verbose,
>> +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool
>> Verbose,
>>                   raw_ostream &Out) {
>>  // Output assembly language.
>> -  PM.add(createPIC16CodePrinterPass(Out, *this, Fast, Verbose));
>> +  PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
>>  return false;
>> }
>>
>>
>> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h (original)
>> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h Mon Apr 27
>> 19:21:31 2009
>> @@ -57,8 +57,8 @@
>>    return const_cast<PIC16TargetLowering*>(&TLInfo);
>>  }
>>
>> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                  bool Verbose, raw_ostream &Out);
>> }; // PIC16TargetMachine.
>>
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Mon
>> Apr 27 19:21:31 2009
>> @@ -54,9 +54,9 @@
>>    StringSet<> FnStubs, GVStubs, HiddenGVStubs;
>>    const PPCSubtarget &Subtarget;
>>  public:
>> -    PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
>> -                  const TargetAsmInfo *T, bool F, bool V)
>> -      : AsmPrinter(O, TM, T, F, V),
>> +    explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
>> +                           const TargetAsmInfo *T, unsigned OL,
>> bool V)
>> +      : AsmPrinter(O, TM, T, OL, V),
>>        Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
>>
>>    virtual const char *getPassName() const {
>> @@ -297,9 +297,9 @@
>>    DwarfWriter *DW;
>>    MachineModuleInfo *MMI;
>>  public:
>> -    PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
>> -                       const TargetAsmInfo *T, bool F, bool V)
>> -      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
>> +    explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine  
>> &TM,
>> +                                const TargetAsmInfo *T, unsigned
>> OL, bool V)
>> +      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
>>
>>    virtual const char *getPassName() const {
>>      return "Linux PPC Assembly Printer";
>> @@ -326,9 +326,9 @@
>>    MachineModuleInfo *MMI;
>>    raw_ostream &OS;
>>  public:
>> -    PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
>> -                        const TargetAsmInfo *T, bool F, bool V)
>> -      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0), OS(O) {}
>> +    explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine
>> &TM,
>> +                                 const TargetAsmInfo *T, unsigned
>> OL, bool V)
>> +      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
>>
>>    virtual const char *getPassName() const {
>>      return "Darwin PPC Assembly Printer";
>> @@ -1176,13 +1176,15 @@
>> ///
>> FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
>>                                            PPCTargetMachine &tm,
>> -                                            bool fast, bool
>> verbose) {
>> +                                            unsigned OptLevel, bool
>> verbose) {
>>  const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
>>
>>  if (Subtarget->isDarwin()) {
>> -    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>> fast, verbose);
>> +    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>> +                                   OptLevel, verbose);
>>  } else {
>> -    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>> fast, verbose);
>> +    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>> +                                  OptLevel, verbose);
>>  }
>> }
>>
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPC.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/PowerPC/PPC.h (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPC.h Mon Apr 27 19:21:31 2009
>> @@ -28,7 +28,7 @@
>> FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
>> FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
>>                                      PPCTargetMachine &TM,
>> -                                      bool Fast, bool Verbose);
>> +                                      unsigned OptLevel, bool
>> Verbose);
>> FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
>>                                       MachineCodeEmitter &MCE);
>> } // end namespace llvm;
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -129,29 +129,31 @@
>> // Pass Pipeline Configuration
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> -bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool
>> Fast) {
>> +bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
>> unsigned OptLevel) {
>>  // Install an instruction selector.
>>  PM.add(createPPCISelDag(*this));
>>  return false;
>> }
>>
>> -bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>> Fast) {
>> +bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned
>> OptLevel) {
>>
>>  // Must run branch selection immediately preceding the asm printer.
>>  PM.add(createPPCBranchSelectionPass());
>>  return false;
>> }
>>
>> -bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool
>> Fast,
>> -                                          bool Verbose, raw_ostream
>> &Out) {
>> +bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>> +                                          unsigned OptLevel,
>> +                                          bool Verbose,
>> +                                          raw_ostream &Out) {
>>  assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>  if (AsmPrinterCtor)
>> -    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
>> +    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>>
>>  return false;
>> }
>>
>> -bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool  
>> Fast,
>> +bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                      bool DumpAsm,
>> MachineCodeEmitter &MCE) {
>>  // The JIT should use the static relocation model in ppc32 mode,
>> PIC in ppc64.
>>  // FIXME: This should be moved to TargetJITInfo!!
>> @@ -176,20 +178,20 @@
>>  if (DumpAsm) {
>>    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>    if (AsmPrinterCtor)
>> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>  }
>>
>>  return false;
>> }
>>
>> -bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>> bool Fast,
>> +bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>> unsigned OptLevel,
>>                                            bool DumpAsm,
>> MachineCodeEmitter &MCE) {
>>  // Machine code emitter pass for PowerPC.
>>  PM.add(createPPCCodeEmitterPass(*this, MCE));
>>  if (DumpAsm) {
>>    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>    if (AsmPrinterCtor)
>> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>  }
>>
>>  return false;
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Mon Apr 27
>> 19:21:31 2009
>> @@ -46,7 +46,7 @@
>>  // set this functions to ctor pointer at startup time if they are
>> linked in.
>>  typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>>                                            PPCTargetMachine &tm,
>> -                                            bool fast, bool  
>> verbose);
>> +                                            unsigned OptLevel, bool
>> verbose);
>>  static AsmPrinterCtorFn AsmPrinterCtor;
>>
>> public:
>> @@ -76,13 +76,13 @@
>>  }
>>
>>  // Pass Pipeline Configuration
>> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                  bool Verbose, raw_ostream &Out);
>> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned  
>> OptLevel,
>>                              bool DumpAsm, MachineCodeEmitter &MCE);
>> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                    bool DumpAsm, MachineCodeEmitter
>> &MCE);
>>  virtual bool getEnableTailMergeDefault() const;
>> };
>>
>> Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp Mon
>> Apr 27 19:21:31 2009
>> @@ -48,9 +48,9 @@
>>    typedef std::map<const Value *, unsigned> ValueMapTy;
>>    ValueMapTy NumberForBB;
>>  public:
>> -    SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
>> -                    const TargetAsmInfo *T, bool F, bool V)
>> -      : AsmPrinter(O, TM, T, F, V) {}
>> +    explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
>> +                             const TargetAsmInfo *T, unsigned OL,
>> bool V)
>> +      : AsmPrinter(O, TM, T, OL, V) {}
>>
>>    virtual const char *getPassName() const {
>>      return "Sparc Assembly Printer";
>> @@ -82,8 +82,9 @@
>> ///
>> FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
>>                                               TargetMachine &tm,
>> -                                               bool fast, bool
>> verbose) {
>> -  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>> verbose);
>> +                                               unsigned OptLevel,
>> +                                               bool verbose) {
>> +  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>> OptLevel, verbose);
>> }
>>
>> /// runOnMachineFunction - This uses the printInstruction()
>>
>> Modified: llvm/trunk/lib/Target/Sparc/Sparc.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Sparc/Sparc.h (original)
>> +++ llvm/trunk/lib/Target/Sparc/Sparc.h Mon Apr 27 19:21:31 2009
>> @@ -25,7 +25,7 @@
>>
>>  FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
>>  FunctionPass *createSparcCodePrinterPass(raw_ostream &OS,
>> TargetMachine &TM,
>> -                                           bool Fast, bool Verbose);
>> +                                           unsigned OptLevel, bool
>> Verbose);
>>  FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
>>  FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
>> } // end namespace llvm;
>>
>> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)
>> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -68,7 +68,8 @@
>> #endif
>> }
>>
>> -bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, bool
>> Fast) {
>> +bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
>> +                                         unsigned OptLevel) {
>>  PM.add(createSparcISelDag(*this));
>>  return false;
>> }
>> @@ -76,15 +77,17 @@
>> /// addPreEmitPass - This pass may be implemented by targets that
>> want to run
>> /// passes immediately before machine code is emitted.  This should
>> return
>> /// true if -print-machineinstrs should print out the code after the
>> passes.
>> -bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>> Fast) {
>> +bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
>> unsigned OptLevel){
>>  PM.add(createSparcFPMoverPass(*this));
>>  PM.add(createSparcDelaySlotFillerPass(*this));
>>  return true;
>> }
>>
>> -bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>> bool Fast,
>> -                                            bool Verbose,
>> raw_ostream &Out) {
>> +bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>> +                                            unsigned OptLevel,
>> +                                            bool Verbose,
>> +                                            raw_ostream &Out) {
>>  // Output assembly language.
>> -  PM.add(createSparcCodePrinterPass(Out, *this, Fast, Verbose));
>> +  PM.add(createSparcCodePrinterPass(Out, *this, OptLevel, Verbose));
>>  return false;
>> }
>>
>> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original)
>> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Mon Apr 27
>> 19:21:31 2009
>> @@ -51,9 +51,9 @@
>>  static unsigned getModuleMatchQuality(const Module &M);
>>
>>  // Pass Pipeline Configuration
>> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                  bool Verbose, raw_ostream &Out);
>> };
>>
>>
>> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h  
>> (original)
>> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Mon Apr
>> 27 19:21:31 2009
>> @@ -33,9 +33,9 @@
>>  MachineModuleInfo *MMI;
>>  const X86Subtarget *Subtarget;
>> public:
>> -  X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
>> -                   const TargetAsmInfo *T, bool F, bool V)
>> -    : AsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {
>> +  explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
>> +                            const TargetAsmInfo *T, unsigned OL,
>> bool V)
>> +    : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
>>    Subtarget = &TM.getSubtarget<X86Subtarget>();
>>  }
>>
>>
>> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Mon Apr
>> 27 19:21:31 2009
>> @@ -25,13 +25,15 @@
>> ///
>> FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
>>                                             X86TargetMachine &tm,
>> -                                             bool fast, bool
>> verbose) {
>> +                                             unsigned OptLevel,
>> bool verbose) {
>>  const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
>>
>>  if (Subtarget->isFlavorIntel()) {
>> -    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>> fast, verbose);
>> +    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>> +                                  OptLevel, verbose);
>>  } else {
>> -    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>> verbose);
>> +    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>> +                                OptLevel, verbose);
>>  }
>> }
>>
>>
>> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
>> (original)
>> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h Mon
>> Apr 27 19:21:31 2009
>> @@ -25,9 +25,9 @@
>> namespace llvm {
>>
>> struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
>> -  X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
>> -                     const TargetAsmInfo *T, bool F, bool V)
>> -    : AsmPrinter(O, TM, T, F, V) {}
>> +  explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
>> +                              const TargetAsmInfo *T, unsigned OL,
>> bool V)
>> +    : AsmPrinter(O, TM, T, OL, V) {}
>>
>>  virtual const char *getPassName() const {
>>    return "X86 Intel-Style Assembly Printer";
>>
>> Modified: llvm/trunk/lib/Target/X86/X86.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/X86.h (original)
>> +++ llvm/trunk/lib/Target/X86/X86.h Mon Apr 27 19:21:31 2009
>> @@ -25,7 +25,7 @@
>> /// createX86ISelDag - This pass converts a legalized DAG into a
>> /// X86-specific DAG, ready for instruction scheduling.
>> ///
>> -FunctionPass *createX86ISelDag(X86TargetMachine &TM, bool Fast);
>> +FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned
>> OptSize);
>>
>> /// createX86FloatingPointStackifierPass - This function returns a
>> pass which
>> /// converts floating point register references and pseudo
>> instructions into
>> @@ -44,7 +44,7 @@
>> ///
>> FunctionPass *createX86CodePrinterPass(raw_ostream &o,
>>                                       X86TargetMachine &tm,
>> -                                       bool fast, bool Verbose);
>> +                                       unsigned OptLevel, bool
>> Verbose);
>>
>> /// createX86CodeEmitterPass - Return a pass that emits the
>> collected X86 code
>> /// to the specified MCE object.
>>
>> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -134,8 +134,8 @@
>>    bool OptForSize;
>>
>>  public:
>> -    X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
>> -      : SelectionDAGISel(tm, fast),
>> +    explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned  
>> OptLevel)
>> +      : SelectionDAGISel(tm, OptLevel),
>>        TM(tm), X86Lowering(*TM.getTargetLowering()),
>>        Subtarget(&TM.getSubtarget<X86Subtarget>()),
>>        OptForSize(false) {}
>> @@ -306,7 +306,7 @@
>>
>> bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode  
>> *U,
>>                                                 SDNode *Root) const {
>> -  if (Fast) return false;
>> +  if (OptLevel == 0) return false;
>>
>>  if (U == Root)
>>    switch (U->getOpcode()) {
>> @@ -512,7 +512,7 @@
>>
>>
>> /// PreprocessForRMW - Preprocess the DAG to make instruction
>> selection better.
>> -/// This is only run if not in -fast mode (aka -O0).
>> +/// This is only run if not in -O0 mode.
>> /// This allows the instruction selector to pick more read-modify-
>> write
>> /// instructions. This is a common case:
>> ///
>> @@ -714,10 +714,10 @@
>>  OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
>>
>>  DEBUG(BB->dump());
>> -  if (!Fast)
>> +  if (OptLevel != 0)
>>    PreprocessForRMW();
>>
>> -  // FIXME: This should only happen when not -fast.
>> +  // FIXME: This should only happen when not compiled with -O0.
>>  PreprocessForFPConvert();
>>
>>  // Codegen the basic block.
>> @@ -1744,6 +1744,6 @@
>> /// createX86ISelDag - This pass converts a legalized DAG into a
>> /// X86-specific DAG, ready for instruction scheduling.
>> ///
>> -FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool
>> Fast) {
>> -  return new X86DAGToDAGISel(TM, Fast);
>> +FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned
>> OptLevel) {
>> +  return new X86DAGToDAGISel(TM, OptLevel);
>> }
>>
>> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -180,9 +180,9 @@
>> // Pass Pipeline Configuration
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> -bool X86TargetMachine::addInstSelector(PassManagerBase &PM, bool
>> Fast) {
>> +bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
>> unsigned OptLevel) {
>>  // Install an instruction selector.
>> -  PM.add(createX86ISelDag(*this, Fast));
>> +  PM.add(createX86ISelDag(*this, OptLevel));
>>
>>  // If we're using Fast-ISel, clean up the mess.
>>  if (EnableFastISel)
>> @@ -194,27 +194,29 @@
>>  return false;
>> }
>>
>> -bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, bool
>> Fast) {
>> +bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned
>> OptLevel) {
>>  // Calculate and set max stack object alignment early, so we can
>> decide
>>  // whether we will need stack realignment (and thus FP).
>>  PM.add(createX86MaxStackAlignmentCalculatorPass());
>>  return false;  // -print-machineinstr shouldn't print after this.
>> }
>>
>> -bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, bool
>> Fast) {
>> +bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
>> unsigned OptLevel) {
>>  PM.add(createX86FloatingPointStackifierPass());
>>  return true;  // -print-machineinstr should print after this.
>> }
>>
>> -bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool
>> Fast,
>> -                                          bool Verbose, raw_ostream
>> &Out) {
>> +bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>> +                                          unsigned OptLevel,
>> +                                          bool Verbose,
>> +                                          raw_ostream &Out) {
>>  assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>  if (AsmPrinterCtor)
>> -    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
>> +    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>>  return false;
>> }
>>
>> -bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool  
>> Fast,
>> +bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                      bool DumpAsm,
>> MachineCodeEmitter &MCE) {
>>  // FIXME: Move this to TargetJITInfo!
>>  // On Darwin, do not override 64-bit setting made in
>> X86TargetMachine().
>> @@ -236,19 +238,20 @@
>>  if (DumpAsm) {
>>    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>    if (AsmPrinterCtor)
>> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>  }
>>
>>  return false;
>> }
>>
>> -bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>> bool Fast,
>> -                                        bool DumpAsm,
>> MachineCodeEmitter &MCE) {
>> +bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>> +                                            unsigned OptLevel, bool
>> DumpAsm,
>> +                                            MachineCodeEmitter
>> &MCE) {
>>  PM.add(createX86CodeEmitterPass(*this, MCE));
>>  if (DumpAsm) {
>>    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>    if (AsmPrinterCtor)
>> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>  }
>>
>>  return false;
>>
>> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
>> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Mon Apr 27 19:21:31
>> 2009
>> @@ -45,7 +45,7 @@
>>  // set this functions to ctor pointer at startup time if they are
>> linked in.
>>  typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>>                                            X86TargetMachine &tm,
>> -                                            bool fast, bool  
>> verbose);
>> +                                            unsigned OptLevel, bool
>> verbose);
>>  static AsmPrinterCtorFn AsmPrinterCtor;
>>
>> public:
>> @@ -74,14 +74,14 @@
>>  }
>>
>>  // Set up the pass pipeline.
>> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>> -  virtual bool addPreRegAlloc(PassManagerBase &PM, bool Fast);
>> -  virtual bool addPostRegAlloc(PassManagerBase &PM, bool Fast);
>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                  bool Verbose, raw_ostream &Out);
>> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned  
>> OptLevel,
>>                              bool DumpAsm, MachineCodeEmitter &MCE);
>> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                    bool DumpAsm, MachineCodeEmitter
>> &MCE);
>>
>>  /// symbolicAddressesAreRIPRel - Return true if symbolic addresses
>> are
>>
>> Modified: llvm/trunk/lib/Target/XCore/XCore.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCore.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/XCore/XCore.h (original)
>> +++ llvm/trunk/lib/Target/XCore/XCore.h Mon Apr 27 19:21:31 2009
>> @@ -24,7 +24,7 @@
>>  FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
>>  FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
>>                                           XCoreTargetMachine &TM,
>> -                                           bool Fast, bool Verbose);
>> +                                           unsigned OptLevel, bool
>> Verbose);
>> } // end namespace llvm;
>>
>> // Defines symbolic names for XCore registers.  This defines a
>> mapping from
>>
>> Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -58,8 +58,8 @@
>>    const XCoreSubtarget &Subtarget;
>>  public:
>>    XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
>> -                    const TargetAsmInfo *T, bool F, bool V)
>> -      : AsmPrinter(O, TM, T, F, V), DW(0),
>> +                    const TargetAsmInfo *T, unsigned OL, bool V)
>> +      : AsmPrinter(O, TM, T, OL, V), DW(0),
>>        Subtarget(*TM.getSubtargetImpl()) {}
>>
>>    virtual const char *getPassName() const {
>> @@ -105,8 +105,9 @@
>> ///
>> FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
>>                                               XCoreTargetMachine &tm,
>> -                                               bool fast, bool
>> verbose) {
>> -  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>> verbose);
>> +                                               unsigned OptLevel,
>> +                                               bool verbose) {
>> +  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>> OptLevel, verbose);
>> }
>>
>> // PrintEscapedString - Print each character of the specified
>> string, escaping
>>
>> Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original)
>> +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -55,14 +55,17 @@
>>  return 0;
>> }
>>
>> -bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, bool
>> Fast) {
>> +bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
>> +                                         unsigned OptLevel) {
>>  PM.add(createXCoreISelDag(*this));
>>  return false;
>> }
>>
>> -bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>> bool Fast,
>> -                                            bool Verbose,
>> raw_ostream &Out) {
>> +bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>> +                                            unsigned OptLevel,
>> +                                            bool Verbose,
>> +                                            raw_ostream &Out) {
>>  // Output assembly language.
>> -  PM.add(createXCoreCodePrinterPass(Out, *this, Fast, Verbose));
>> +  PM.add(createXCoreCodePrinterPass(Out, *this, OptLevel, Verbose));
>>  return false;
>> }
>>
>> Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original)
>> +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Mon Apr 27
>> 19:21:31 2009
>> @@ -52,8 +52,8 @@
>>  static unsigned getModuleMatchQuality(const Module &M);
>>
>>  // Pass Pipeline Configuration
>> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>> OptLevel);
>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>> OptLevel,
>>                                  bool Verbose, raw_ostream &Out);
>> };
>>
>>
>> Modified: llvm/trunk/test/CodeGen/Generic/2006-06-12-
>> LowerSwitchCrash.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
>> (original)
>> +++ llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
>> Mon Apr 27 19:21:31 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llvm-as < %s | llc -fast
>> +; RUN: llvm-as < %s | llc -O0
>>
>> define float @test(i32 %tmp12771278) {
>>        switch i32 %tmp12771278, label %bb1279 [
>>
>> Modified: llvm/trunk/test/CodeGen/Generic/2006-06-13-
>> ComputeMaskedBitsCrash.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/Generic/2006-06-13-
>> ComputeMaskedBitsCrash.ll (original)
>> +++ llvm/trunk/test/CodeGen/Generic/2006-06-13-
>> ComputeMaskedBitsCrash.ll Mon Apr 27 19:21:31 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llvm-as < %s | llc -fast
>> +; RUN: llvm-as < %s | llc -O0
>> 	
>> %struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8,
>> i8, i8, i8, i32, i32, i32, i32, i32, i32, i32 }
>> @cl_pf_opts = external global %struct.cl_perfunc_opts		; <
>> %struct.cl_perfunc_opts*> [#uses=2]
>>
>> Modified: llvm/trunk/test/CodeGen/Generic/2007-04-13-
>> SwitchLowerBadPhi.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
>> (original)
>> +++ llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
>> Mon Apr 27 19:21:31 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llvm-as < %s | llc -fast
>> +; RUN: llvm-as < %s | llc -O0
>> ; PR 1323
>>
>> ; ModuleID = 'test.bc'
>>
>> Modified: llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll (original)
>> +++ llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll Mon Apr 27
>> 19:21:31 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -fast -
>> relocation-model=pic -o -
>> +; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -O0 -
>> relocation-model=pic -o -
>> ; PR1638
>>
>> @.str242 = external constant [3 x i8]		; <[3 x i8]*> [#uses=1]
>>
>> Modified: llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
>> (original)
>> +++ llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll Mon
>> Apr 27 19:21:31 2009
>> @@ -1,5 +1,5 @@
>> ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin
>> -; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-
>> model=pic -disable-fp-elim -fast -regalloc=local
>> +; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-
>> model=pic -disable-fp-elim -O0 -regalloc=local
>>
>> 	%struct.CGPoint = type { double, double }
>> 	%struct.NSArray = type { %struct.NSObject }
>>
>> Modified: llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll Mon Apr
>> 27 19:21:31 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llvm-as < %s | llc -march=x86 -fast -fast-isel=false | grep
>> mov | count 5
>> +; RUN: llvm-as < %s | llc -march=x86 -O0 -fast-isel=false | grep
>> mov | count 5
>> ; PR2343
>>
>> 	%llvm.dbg.anchor.type = type { i32, i32 }
>>
>> Modified: llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll  
>> (original)
>> +++ llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll Mon Apr
>> 27 19:21:31 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast
>> +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0
>>
>> define fastcc void @optimize_bit_field() nounwind {
>> bb4:
>>
>> Modified: llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll Mon Apr 27
>> 19:21:31 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast -
>> regalloc=local | not grep sil
>> +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0 -
>> regalloc=local | not grep sil
>> ; rdar://6787136
>>
>> 	%struct.X = type { i8, [32 x i8] }
>>
>> Modified: llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/add-with-overflow.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/X86/add-with-overflow.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/add-with-overflow.ll Mon Apr 27
>> 19:21:31 2009
>> @@ -1,7 +1,7 @@
>> ; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 2
>> ; RUN: llvm-as < %s | llc -march=x86 | grep {jb} | count 2
>> -; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jo} | count 2
>> -; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jb} | count 2
>> +; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jo} | count 2
>> +; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jb} | count 2
>>
>> @ok = internal constant [4 x i8] c"%d\0A\00"
>> @no = internal constant [4 x i8] c"no\0A\00"
>>
>> Modified: llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll Mon Apr 27
>> 19:21:31 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llvm-as < %s | llc -march=x86 -fast
>> +; RUN: llvm-as < %s | llc -march=x86 -O0
>>
>> ; This file is for regression tests for cases where FastISel needs
>> ; to gracefully bail out and let SelectionDAGISel take over.
>>
>> Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll Mon Apr 27
>> 19:21:31 2009
>> @@ -1,5 +1,5 @@
>> -; RUN: llvm-as < %s | llc -march=x86-64 -fast | grep movslq
>> -; RUN: llvm-as < %s | llc -march=x86 -fast
>> +; RUN: llvm-as < %s | llc -march=x86-64 -O0 | grep movslq
>> +; RUN: llvm-as < %s | llc -march=x86 -O0
>> ; PR3181
>>
>> ; GEP indices are interpreted as signed integers, so they
>>
>> Modified: llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll Mon Apr 27
>> 19:21:31 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llvm-as < %s | llc -march=x86 -fast | grep {sarl	\$80, %eax}
>> +; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {sarl	\$80, %eax}
>> ; PR3242
>>
>> define i32 @foo(i32 %x) nounwind {
>>
>> Modified: llvm/trunk/test/CodeGen/X86/pr1489.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr1489.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/X86/pr1489.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/pr1489.ll Mon Apr 27 19:21:31 2009
>> @@ -1,5 +1,5 @@
>> -; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep
>> 1082126238 | count 3
>> -; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep
>> 3058016715 | count 1
>> +; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep
>> 1082126238 | count 3
>> +; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep
>> 3058016715 | count 1
>> ;; magic constants are 3.999f and half of 3.999
>> ; ModuleID = '1489.c'
>> target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-
>> i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
>>
>> Modified: llvm/trunk/test/CodeGen/X86/volatile.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/volatile.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/X86/volatile.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/volatile.ll Mon Apr 27 19:21:31 2009
>> @@ -1,5 +1,5 @@
>> ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 | grep movsd |
>> count 5
>> -; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -fast | grep movsd
>> | count 5
>> +; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -O0 | grep movsd |
>> count 5
>>
>> @x = external global double
>>
>>
>> Modified: llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
>> (original)
>> +++ llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll Mon Apr
>> 27 19:21:31 2009
>> @@ -1,5 +1,5 @@
>> ; RUN: llvm-as < %s | llc
>> -; RUN: llvm-as < %s | llc -fast
>> +; RUN: llvm-as < %s | llc -O0
>> 	%llvm.dbg.anchor.type = type { i32, i32 }
>> 	%llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64,
>> i64, i64, i32, i32 }
>> 	%llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8* }
>>
>> Modified: llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-30-Method.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/DebugInfo/2009-01-30-Method.ll (original)
>> +++ llvm/trunk/test/DebugInfo/2009-01-30-Method.ll Mon Apr 27
>> 19:21:31 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llvm-as < %s | llc -fast | grep "\\"foo" | count 3
>> +; RUN: llvm-as < %s | llc -O0 | grep "\\"foo" | count 3
>> ; 1 declaration, 1 definition and 1 pubnames entry.
>> target triple = "i386-apple-darwin*"
>> 	%llvm.dbg.anchor.type = type { i32, i32 }
>>
>> Modified: llvm/trunk/test/DebugInfo/deaddebuglabel.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/deaddebuglabel.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/DebugInfo/deaddebuglabel.ll (original)
>> +++ llvm/trunk/test/DebugInfo/deaddebuglabel.ll Mon Apr 27 19:21:31
>> 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llvm-as < %s | llc -fast | grep "label" | count 8
>> +; RUN: llvm-as < %s | llc -O0 | grep "label" | count 8
>> ; PR2614
>> ; XFAIL: *
>>
>>
>> Modified: llvm/trunk/test/DebugInfo/forwardDecl.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/forwardDecl.ll?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/DebugInfo/forwardDecl.ll (original)
>> +++ llvm/trunk/test/DebugInfo/forwardDecl.ll Mon Apr 27 19:21:31 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llvm-as < %s | llc -fast | %prcontext ST 1 | grep 0x1 |
>> count 1
>> +; RUN: llvm-as < %s | llc -O0 | %prcontext ST 1 | grep 0x1 | count 1
>>
>> target triple = "i386-apple-darwin9.6"
>> 	%llvm.dbg.anchor.type = type { i32, i32 }
>>
>> Modified: llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-06-StackTrace.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp (original)
>> +++ llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -1,7 +1,7 @@
>> // This is a regression test on debug info to make sure that we can
>> get a
>> // meaningful stack trace from a C++ program.
>> // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
>> -// RUN:    llc --disable-fp-elim -o %t.s -f -fast -relocation-
>> model=pic
>> +// RUN:    llc --disable-fp-elim -o %t.s -f -O0 -relocation- 
>> model=pic
>> // RUN: %compile_c %t.s -o %t.o
>> // RUN: %link %t.o -o %t.exe
>> // RUN: echo {break DeepStack::deepest\nrun 17\nwhere\n} > %t.in
>>
>> Modified: llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-30-Pubnames.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp (original)
>> +++ llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -1,7 +1,7 @@
>> // This is a regression test on debug info to make sure that we can
>> access
>> // qualified global names.
>> // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
>> -// RUN:   llc --disable-fp-elim -o %t.s -f -fast
>> +// RUN:   llc --disable-fp-elim -o %t.s -f -O0
>> // RUN: %compile_c %t.s -o %t.o
>> // RUN: %link %t.o -o %t.exe
>> // RUN: %llvmdsymutil %t.exe
>>
>> Modified: llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-04-21-DtorNames-dbg.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
>> (original)
>> +++ llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp Mon Apr
>> 27 19:21:31 2009
>> @@ -1,4 +1,4 @@
>> -// RUN: %llvmgcc -c -g %s -o - | llc -fast -f -o %t.s
>> +// RUN: %llvmgcc -c -g %s -o - | llc -O0 -f -o %t.s
>> // RUN: %compile_c %t.s -o %t.o
>> // PR4025
>>
>>
>> Modified: llvm/trunk/tools/llc/llc.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/tools/llc/llc.cpp (original)
>> +++ llvm/trunk/tools/llc/llc.cpp Mon Apr 27 19:21:31 2009
>> @@ -55,8 +55,13 @@
>>
>> static cl::opt<bool> Force("f", cl::desc("Overwrite output files"));
>>
>> -static cl::opt<bool> Fast("fast",
>> -      cl::desc("Generate code quickly, potentially sacrificing code
>> quality"));
>> +// Determine optimization level. Level -O0 is equivalent to "fast"
>> code gen.
>> +static cl::opt<unsigned>
>> +OptLevel("O",
>> +         cl::desc("Optimization level. Similar to llvm-gcc -O.
>> (default: -O3)"),
>> +         cl::Prefix,
>> +         cl::ZeroOrMore,
>> +         cl::init(3));
>>
>> static cl::opt<std::string>
>> TargetTriple("mtriple", cl::desc("Override target triple for
>> module"));
>> @@ -257,7 +262,7 @@
>>      PM.add(createVerifierPass());
>>
>>    // Ask the target to add backend passes as necessary.
>> -    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, Fast)) {
>> +    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType,
>> OptLevel)) {
>>      std::cerr << argv[0] << ": target does not support generation
>> of this"
>>                << " file type!\n";
>>      if (Out != &outs()) delete Out;
>> @@ -283,7 +288,7 @@
>>    // Override default to generate verbose assembly.
>>    Target.setAsmVerbosityDefault(true);
>>
>> -    switch (Target.addPassesToEmitFile(Passes, *Out, FileType,
>> Fast)) {
>> +    switch (Target.addPassesToEmitFile(Passes, *Out, FileType,
>> OptLevel)) {
>>    default:
>>      assert(0 && "Invalid file model!");
>>      return 1;
>> @@ -304,7 +309,7 @@
>>      break;
>>    }
>>
>> -    if (Target.addPassesToEmitFileFinish(Passes, MCE, Fast)) {
>> +    if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) {
>>      std::cerr << argv[0] << ": target does not support generation
>> of this"
>>                << " file type!\n";
>>      if (Out != &outs()) delete Out;
>>
>> Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original)
>> +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Mon Apr 27
>> 19:21:31 2009
>> @@ -650,7 +650,7 @@
>>  O << "\";\n\n";
>>
>>  O << "  if (TAI->doesSupportDebugInformation() &&\n"
>> -    << "      DW->ShouldEmitDwarfDebug() && !Fast) {\n"
>> +    << "      DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n"
>>    << "    DebugLoc CurDL = MI->getDebugLoc();\n\n"
>>    << "    if (!CurDL.isUnknown()) {\n"
>>    << "      static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n"
>>
>> Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
>> +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Apr 27 19:21:31
>> 2009
>> @@ -465,7 +465,7 @@
>>      NumInputRootOps = N->getNumChildren();
>>
>>      if (DisablePatternForFastISel(N, CGP))
>> -        emitCheck("!Fast");
>> +        emitCheck("OptLevel != 0");
>>
>>      emitCheck(PredicateCheck);
>>    }
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From isanbard at gmail.com  Mon Apr 27 19:34:01 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 27 Apr 2009 17:34:01 -0700
Subject: [llvm-commits] [llvm] r70270 - in /llvm/trunk:
	include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/
	lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/
	lib/Target/Alpha/AsmPrinter/ lib
Message-ID: <16e5fdf90904271734s62127641nd68249a7fc89bd5e@mail.gmail.com>

There weren't any llvmgcc changes that I could see. I.e., I couldn't
see where it was passing -fast...

-bw

On Mon, Apr 27, 2009 at 5:32 PM, Evan Cheng <evan.cheng at apple.com> wrote:
> Also llvmgcc changes?
>
> Evan
>
> On Apr 27, 2009, at 5:30 PM, Evan Cheng wrote:
>
>> Thanks. How about libLTO?
>>
>> Also, JIT (calls to TM.addPassesToEmitMachineCode and lli.cpp) has to
>> be changed as well.
>>
>> Evan
>>
>> On Apr 27, 2009, at 5:21 PM, Bill Wendling wrote:
>>
>>> Author: void
>>> Date: Mon Apr 27 19:21:31 2009
>>> New Revision: 70270
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=70270&view=rev
>>> Log:
>>> Massive check in. This changes the "-fast" flag to "-O#" in llc. If
>>> you want to
>>> use the old behavior, the flag is -O0. This change allows for finer-
>>> grained
>>> control over which optimizations are run at different -O levels.
>>>
>>> Most of this work was pretty mechanical. The majority of the fixes
>>> came from
>>> verifying that a "fast" variable wasn't used anymore. The JIT still
>>> uses a
>>> "Fast" flag. I'm not 100% sure if it's necessary to change it
>>> there...
>>>
>>> Modified:
>>> ? llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
>>> ? llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
>>> ? llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>>> ? llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
>>> ? llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>>> ? llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
>>> ? llvm/trunk/include/llvm/Target/TargetMachine.h
>>> ? llvm/trunk/include/llvm/Target/TargetOptions.h
>>> ? llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
>>> ? llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
>>> ? llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>>> ? llvm/trunk/lib/Target/ARM/ARM.h
>>> ? llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
>>> ? llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
>>> ? llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>>> ? llvm/trunk/lib/Target/Alpha/Alpha.h
>>> ? llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
>>> ? llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
>>> ? llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>>> ? llvm/trunk/lib/Target/CBackend/CBackend.cpp
>>> ? llvm/trunk/lib/Target/CBackend/CTargetMachine.h
>>> ? llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>>> ? llvm/trunk/lib/Target/CellSPU/SPU.h
>>> ? llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
>>> ? llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
>>> ? llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
>>> ? llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
>>> ? llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>>> ? llvm/trunk/lib/Target/IA64/IA64.h
>>> ? llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
>>> ? llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
>>> ? llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
>>> ? llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>>> ? llvm/trunk/lib/Target/Mips/Mips.h
>>> ? llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
>>> ? llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
>>> ? llvm/trunk/lib/Target/PIC16/PIC16.h
>>> ? llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
>>> ? llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
>>> ? llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
>>> ? llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
>>> ? llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>>> ? llvm/trunk/lib/Target/PowerPC/PPC.h
>>> ? llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
>>> ? llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
>>> ? llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
>>> ? llvm/trunk/lib/Target/Sparc/Sparc.h
>>> ? llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
>>> ? llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
>>> ? llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
>>> ? llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
>>> ? llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
>>> ? llvm/trunk/lib/Target/X86/X86.h
>>> ? llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>>> ? llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
>>> ? llvm/trunk/lib/Target/X86/X86TargetMachine.h
>>> ? llvm/trunk/lib/Target/XCore/XCore.h
>>> ? llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
>>> ? llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
>>> ? llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
>>> ? llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
>>> ? llvm/trunk/test/CodeGen/Generic/2006-06-13-
>>> ComputeMaskedBitsCrash.ll
>>> ? llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
>>> ? llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
>>> ? llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
>>> ? llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
>>> ? llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
>>> ? llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
>>> ? llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
>>> ? llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
>>> ? llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
>>> ? llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
>>> ? llvm/trunk/test/CodeGen/X86/pr1489.ll
>>> ? llvm/trunk/test/CodeGen/X86/volatile.ll
>>> ? llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
>>> ? llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
>>> ? llvm/trunk/test/DebugInfo/deaddebuglabel.ll
>>> ? llvm/trunk/test/DebugInfo/forwardDecl.ll
>>> ? llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
>>> ? llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
>>> ? llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
>>> ? llvm/trunk/tools/llc/llc.cpp
>>> ? llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
>>> ? llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Mon Apr 27 19:21:31
>>> 2009
>>> @@ -65,8 +65,8 @@
>>> ? ?// Necessary for external weak linkage support
>>> ? ?std::set<const GlobalValue*> ExtWeakSymbols;
>>>
>>> - ? ?/// Fast - Generating code via fast instruction selection.
>>> - ? ?bool Fast;
>>> + ? ?/// OptLevel - Generating code at a specific optimization level.
>>> + ? ?unsigned OptLevel;
>>> ?public:
>>> ? ?/// Output stream on which we're printing assembly code.
>>> ? ?///
>>> @@ -110,8 +110,8 @@
>>> ? ?bool VerboseAsm;
>>>
>>> ?protected:
>>> - ? ?AsmPrinter(raw_ostream &o, TargetMachine &TM,
>>> - ? ? ? ? ? ? ? const TargetAsmInfo *T, bool F, bool V);
>>> + ? ?explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ?const TargetAsmInfo *T, unsigned OL, bool
>>> V);
>>>
>>> ?public:
>>> ? ?virtual ~AsmPrinter();
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -81,7 +81,7 @@
>>> ?void EndFunction(MachineFunction *MF);
>>>
>>> ?/// ValidDebugInfo - Return true if V represents valid debug info
>>> value.
>>> - ?bool ValidDebugInfo(Value *V, bool FastISel);
>>> + ?bool ValidDebugInfo(Value *V, unsigned OptLevel);
>>>
>>> ?/// RecordSourceLine - Register a source line with debug info.
>>> Returns a
>>> ?/// unique label ID used to generate a label and provide
>>> correspondence to
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>>> (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Mon
>>> Apr 27 19:21:31 2009
>>> @@ -42,11 +42,11 @@
>>> ? ? ?llvm::linkOcamlGC();
>>> ? ? ?llvm::linkShadowStackGC();
>>>
>>> - ? ? ?(void) llvm::createBURRListDAGScheduler(NULL, false);
>>> - ? ? ?(void) llvm::createTDRRListDAGScheduler(NULL, false);
>>> - ? ? ?(void) llvm::createTDListDAGScheduler(NULL, false);
>>> - ? ? ?(void) llvm::createFastDAGScheduler(NULL, false);
>>> - ? ? ?(void) llvm::createDefaultScheduler(NULL, false);
>>> + ? ? ?(void) llvm::createBURRListDAGScheduler(NULL, 3);
>>> + ? ? ?(void) llvm::createTDRRListDAGScheduler(NULL, 3);
>>> + ? ? ?(void) llvm::createTDListDAGScheduler(NULL, 3);
>>> + ? ? ?(void) llvm::createFastDAGScheduler(NULL, 3);
>>> + ? ? ?(void) llvm::createDefaultScheduler(NULL, 3);
>>>
>>> ? ?}
>>> ?} ForceCodegenLinking; // Force link by creating a global
>>> definition.
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -32,7 +32,7 @@
>>>
>>> class RegisterScheduler : public MachinePassRegistryNode {
>>> public:
>>> - ?typedef ScheduleDAGSDNodes *(*FunctionPassCtor)
>>> (SelectionDAGISel*, bool);
>>> + ?typedef ScheduleDAGSDNodes *(*FunctionPassCtor)
>>> (SelectionDAGISel*, unsigned);
>>>
>>> ?static MachinePassRegistry Registry;
>>>
>>> @@ -64,27 +64,27 @@
>>> /// createBURRListDAGScheduler - This creates a bottom up register
>>> usage
>>> /// reduction list scheduler.
>>> ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Fast);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel);
>>>
>>> /// createTDRRListDAGScheduler - This creates a top down register
>>> usage
>>> /// reduction list scheduler.
>>> ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Fast);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel);
>>>
>>> /// createTDListDAGScheduler - This creates a top-down list
>>> scheduler with
>>> /// a hazard recognizer.
>>> ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Fast);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel);
>>>
>>> /// createFastDAGScheduler - This creates a "fast" scheduler.
>>> ///
>>> ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Fast);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel);
>>>
>>> /// createDefaultScheduler - This creates an instruction scheduler
>>> appropriate
>>> /// for the target.
>>> ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Fast);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel);
>>>
>>> } // end namespace llvm
>>>
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -202,7 +202,7 @@
>>> ?/// certain types of nodes together, or eliminating superfluous
>>> nodes. ?The
>>> ?/// Level argument controls whether Combine is allowed to produce
>>> nodes and
>>> ?/// types that are illegal on the target.
>>> - ?void Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast);
>>> + ?void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned
>>> OptLevel);
>>>
>>> ?/// LegalizeTypes - This transforms the SelectionDAG into a
>>> SelectionDAG that
>>> ?/// only uses types natively supported by the target. ?Returns
>>> "true" if it
>>> @@ -218,7 +218,7 @@
>>> ?///
>>> ?/// Note that this is an involved process that may invalidate
>>> pointers into
>>> ?/// the graph.
>>> - ?void Legalize(bool TypesNeedLegalizing, bool Fast);
>>> + ?void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
>>>
>>> ?/// RemoveDeadNodes - This method deletes all unreachable nodes in
>>> the
>>> ?/// SelectionDAG.
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -51,10 +51,10 @@
>>> ?MachineBasicBlock *BB;
>>> ?AliasAnalysis *AA;
>>> ?GCFunctionInfo *GFI;
>>> - ?bool Fast;
>>> + ?unsigned OptLevel;
>>> ?static char ID;
>>>
>>> - ?explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
>>> + ?explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
>>> ?virtual ~SelectionDAGISel();
>>>
>>> ?TargetLowering &getTargetLowering() { return TLI; }
>>>
>>> Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
>>> +++ llvm/trunk/include/llvm/Target/TargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -213,7 +213,7 @@
>>> ?virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? raw_ostream &,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CodeGenFileType,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool /*Fast*/) {
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned /* OptLevel
>>> */) {
>>> ? ?return FileModel::None;
>>> ?}
>>>
>>> @@ -222,7 +222,8 @@
>>> ?/// used to finish up adding passes to emit the file, if necessary.
>>> ?///
>>> ?virtual bool addPassesToEmitFileFinish(PassManagerBase &,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineCodeEmitter *,
>>> bool /*Fast*/) {
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineCodeEmitter *,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned /* OptLevel */) {
>>> ? ?return true;
>>> ?}
>>>
>>> @@ -234,7 +235,7 @@
>>> ?///
>>> ?virtual bool addPassesToEmitMachineCode(PassManagerBase &,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineCodeEmitter &,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool /*Fast*/) {
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned /* OptLevel */) {
>>> ? ?return true;
>>> ?}
>>>
>>> @@ -243,7 +244,8 @@
>>> ?/// use this.
>>> ?virtual bool WantsWholeFile() const { return false; }
>>> ?virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CodeGenFileType, bool /
>>> *Fast*/) {
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CodeGenFileType,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned /* OptLevel */) {
>>> ? ?return true;
>>> ?}
>>> };
>>> @@ -258,16 +260,16 @@
>>> ?/// addCommonCodeGenPasses - Add standard LLVM codegen passes used
>>> for
>>> ?/// both emitting to assembly files or machine code output.
>>> ?///
>>> - ?bool addCommonCodeGenPasses(PassManagerBase &, bool /*Fast*/);
>>> + ?bool addCommonCodeGenPasses(PassManagerBase &, unsigned /*
>>> OptLevel */);
>>>
>>> public:
>>>
>>> ?/// addPassesToEmitFile - Add passes to the specified pass manager
>>> to get the
>>> ?/// specified file emitted. ?Typically this will involve several
>>> steps of code
>>> - ?/// generation. ?If Fast is set to true, the code generator
>>> should emit code
>>> - ?/// as fast as possible, though the generated code may be less
>>> efficient.
>>> - ?/// This method should return FileModel::Error if emission of
>>> this file type
>>> - ?/// is not supported.
>>> + ?/// generation. ?If OptLevel is 0, the code generator should emit
>>> code as fast
>>> + ?/// as possible, though the generated code may be less
>>> efficient. ?This method
>>> + ?/// should return FileModel::Error if emission of this file type
>>> is not
>>> + ?/// supported.
>>> ?///
>>> ?/// The default implementation of this method adds components from
>>> the
>>> ?/// LLVM retargetable code generator, invoking the methods below
>>> to get
>>> @@ -276,14 +278,15 @@
>>> ?virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? raw_ostream &Out,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CodeGenFileType
>>> FileType,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Fast);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel);
>>>
>>> ?/// addPassesToEmitFileFinish - If the passes to emit the
>>> specified file had
>>> ?/// to be split up (e.g., to add an object writer pass), this
>>> method can be
>>> ?/// used to finish up adding passes to emit the file, if necessary.
>>> ?///
>>> ?virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineCodeEmitter *MCE,
>>> bool Fast);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineCodeEmitter *MCE,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel);
>>>
>>> ?/// addPassesToEmitMachineCode - Add passes to the specified pass
>>> manager to
>>> ?/// get machine code emitted. ?This uses a MachineCodeEmitter
>>> object to handle
>>> @@ -292,21 +295,22 @@
>>> ?/// not supported.
>>> ?///
>>> ?virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineCodeEmitter &MCE,
>>> bool Fast);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineCodeEmitter &MCE,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel);
>>>
>>> ?/// Target-Independent Code Generator Pass Configuration Options.
>>>
>>> ?/// addInstSelector - This method should add any "last minute"
>>> LLVM->LLVM
>>> ?/// passes, then install an instruction selector pass, which
>>> converts from
>>> ?/// LLVM code to machine instructions.
>>> - ?virtual bool addInstSelector(PassManagerBase &, bool /*Fast*/) {
>>> + ?virtual bool addInstSelector(PassManagerBase &, unsigned /*
>>> OptLevel */) {
>>> ? ?return true;
>>> ?}
>>>
>>> ?/// addPreRegAllocPasses - This method may be implemented by
>>> targets that want
>>> ?/// to run passes immediately before register allocation. This
>>> should return
>>> ?/// true if -print-machineinstrs should print after these passes.
>>> - ?virtual bool addPreRegAlloc(PassManagerBase &, bool /*Fast*/) {
>>> + ?virtual bool addPreRegAlloc(PassManagerBase &, unsigned /*
>>> OptLevel */) {
>>> ? ?return false;
>>> ?}
>>>
>>> @@ -314,14 +318,14 @@
>>> ?/// want to run passes after register allocation but before prolog-
>>> epilog
>>> ?/// insertion. ?This should return true if -print-machineinstrs
>>> should print
>>> ?/// after these passes.
>>> - ?virtual bool addPostRegAlloc(PassManagerBase &, bool /*Fast*/) {
>>> + ?virtual bool addPostRegAlloc(PassManagerBase &, unsigned /*
>>> OptLevel */) {
>>> ? ?return false;
>>> ?}
>>>
>>> ?/// addPreEmitPass - This pass may be implemented by targets that
>>> want to run
>>> ?/// passes immediately before machine code is emitted. ?This
>>> should return
>>> ?/// true if -print-machineinstrs should print out the code after
>>> the passes.
>>> - ?virtual bool addPreEmitPass(PassManagerBase &, bool /*Fast*/) {
>>> + ?virtual bool addPreEmitPass(PassManagerBase &, unsigned /*
>>> OptLevel */) {
>>> ? ?return false;
>>> ?}
>>>
>>> @@ -329,7 +333,7 @@
>>> ?/// addAssemblyEmitter - This pass should be overridden by the
>>> target to add
>>> ?/// the asmprinter, if asm emission is supported. ?If this is not
>>> supported,
>>> ?/// 'true' should be returned.
>>> - ?virtual bool addAssemblyEmitter(PassManagerBase &, bool /*Fast*/,
>>> + ?virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /*
>>> OptLevel */,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool /* VerboseAsmDefault */,
>>> raw_ostream &) {
>>> ? ?return true;
>>> ?}
>>> @@ -337,7 +341,7 @@
>>> ?/// addCodeEmitter - This pass should be overridden by the target
>>> to add a
>>> ?/// code emitter, if supported. ?If this is not supported, 'true'
>>> should be
>>> ?/// returned. If DumpAsm is true, the generated assembly is
>>> printed to cerr.
>>> - ?virtual bool addCodeEmitter(PassManagerBase &, bool /*Fast*/,
>>> + ?virtual bool addCodeEmitter(PassManagerBase &, unsigned /*
>>> OptLevel */,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool /*DumpAsm*/, MachineCodeEmitter
>>> &) {
>>> ? ?return true;
>>> ?}
>>> @@ -346,7 +350,7 @@
>>> ?/// a code emitter (without setting flags), if supported. ?If this
>>> is not
>>> ?/// supported, 'true' should be returned. ?If DumpAsm is true, the
>>> generated
>>> ?/// assembly is printed to cerr.
>>> - ?virtual bool addSimpleCodeEmitter(PassManagerBase &, bool /
>>> *Fast*/,
>>> + ?virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /*
>>> OptLevel */,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool /*DumpAsm*/,
>>> MachineCodeEmitter &) {
>>> ? ?return true;
>>> ?}
>>>
>>> Modified: llvm/trunk/include/llvm/Target/TargetOptions.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/include/llvm/Target/TargetOptions.h (original)
>>> +++ llvm/trunk/include/llvm/Target/TargetOptions.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -108,7 +108,7 @@
>>> ?/// generated.
>>> ?extern bool DisableJumpTables;
>>>
>>> - ?/// FastISel - This flag enables fast-path instruction selection
>>> + ?/// EnableFastISel - This flag enables fast-path instruction
>>> selection
>>> ?/// which trades away generated code quality in favor of reducing
>>> ?/// compile time.
>>> ?extern bool EnableFastISel;
>>>
>>> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -42,8 +42,8 @@
>>>
>>> char AsmPrinter::ID = 0;
>>> AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
>>> - ? ? ? ? ? ? ? ? ? ? ? const TargetAsmInfo *T, bool F, bool VDef)
>>> - ?: MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o),
>>> + ? ? ? ? ? ? ? ? ? ? ? const TargetAsmInfo *T, unsigned OL, bool
>>> VDef)
>>> + ?: MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
>>> ? ?TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
>>> ? ?IsInTextSection(false)
>>> {
>>>
>>> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -3351,7 +3351,7 @@
>>> ?}
>>>
>>> ?/// ValidDebugInfo - Return true if V represents valid debug info
>>> value.
>>> - ?bool ValidDebugInfo(Value *V, bool FastISel) {
>>> + ?bool ValidDebugInfo(Value *V, unsigned OptLevel) {
>>> ? ?if (!V)
>>> ? ? ?return false;
>>>
>>> @@ -3393,7 +3393,7 @@
>>> ? ?case DW_TAG_lexical_block:
>>> ? ? ?/// FIXME. This interfers with the qualitfy of generated code
>>> when
>>> ? ? ?/// during optimization.
>>> - ? ? ?if (FastISel == false)
>>> + ? ? ?if (OptLevel != 0)
>>> ? ? ? ?return false;
>>> ? ?default:
>>> ? ? ?break;
>>> @@ -4730,8 +4730,8 @@
>>> }
>>>
>>> /// ValidDebugInfo - Return true if V represents valid debug info
>>> value.
>>> -bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) {
>>> - ?return DD && DD->ValidDebugInfo(V, FastISel);
>>> +bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
>>> + ?return DD && DD->ValidDebugInfo(V, OptLevel);
>>> }
>>>
>>> /// RecordSourceLine - Records location information and associates
>>> it with a
>>>
>>> Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Mon Apr 27 19:21:31
>>> 2009
>>> @@ -55,9 +55,9 @@
>>> LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? raw_ostream &Out,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CodeGenFileType FileType,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Fast) {
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel) {
>>> ?// Add common CodeGen passes.
>>> - ?if (addCommonCodeGenPasses(PM, Fast))
>>> + ?if (addCommonCodeGenPasses(PM, OptLevel))
>>> ? ?return FileModel::Error;
>>>
>>> ?// Fold redundant debug labels.
>>> @@ -66,17 +66,17 @@
>>> ?if (PrintMachineCode)
>>> ? ?PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> - ?if (addPreEmitPass(PM, Fast) && PrintMachineCode)
>>> + ?if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
>>> ? ?PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> - ?if (!Fast)
>>> + ?if (OptLevel != 0)
>>> ? ?PM.add(createLoopAlignerPass());
>>>
>>> ?switch (FileType) {
>>> ?default:
>>> ? ?break;
>>> ?case TargetMachine::AssemblyFile:
>>> - ? ?if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(), Out))
>>> + ? ?if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(),
>>> Out))
>>> ? ? ?return FileModel::Error;
>>> ? ?return FileModel::AsmFile;
>>> ?case TargetMachine::ObjectFile:
>>> @@ -94,9 +94,9 @@
>>> /// finish up adding passes to emit the file, if necessary.
>>> bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase
>>> &PM,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineCodeEmitter
>>> *MCE,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Fast) {
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned
>>> OptLevel) {
>>> ?if (MCE)
>>> - ? ?addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
>>> + ? ?addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
>>>
>>> ?PM.add(createGCInfoDeleter());
>>>
>>> @@ -114,15 +114,15 @@
>>> ///
>>> bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase
>>> &PM,
>>>
>>> MachineCodeEmitter &MCE,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Fast) {
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned
>>> OptLevel) {
>>> ?// Add common CodeGen passes.
>>> - ?if (addCommonCodeGenPasses(PM, Fast))
>>> + ?if (addCommonCodeGenPasses(PM, OptLevel))
>>> ? ?return true;
>>>
>>> - ?if (addPreEmitPass(PM, Fast) && PrintMachineCode)
>>> + ?if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
>>> ? ?PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> - ?addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
>>> + ?addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
>>>
>>> ?PM.add(createGCInfoDeleter());
>>>
>>> @@ -135,11 +135,12 @@
>>> /// addCommonCodeGenPasses - Add standard LLVM codegen passes used
>>> for
>>> /// both emitting to assembly files or machine code output.
>>> ///
>>> -bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
>>> bool Fast) {
>>> +bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel) {
>>> ?// Standard LLVM-Level Passes.
>>>
>>> ?// Run loop strength reduction before anything else.
>>> - ?if (!Fast) {
>>> + ?if (OptLevel != 0) {
>>> ? ?PM.add(createLoopStrengthReducePass(getTargetLowering()));
>>> ? ?if (PrintLSR)
>>> ? ? ?PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n",
>>> &errs()));
>>> @@ -153,7 +154,7 @@
>>> ?// Make sure that no unreachable blocks are instruction selected.
>>> ?PM.add(createUnreachableBlockEliminationPass());
>>>
>>> - ?if (!Fast)
>>> + ?if (OptLevel != 0)
>>> ? ?PM.add(createCodeGenPreparePass(getTargetLowering()));
>>>
>>> ?PM.add(createStackProtectorPass(getTargetLowering()));
>>> @@ -167,38 +168,38 @@
>>>
>>> ?// Enable FastISel with -fast, but allow that to be overridden.
>>> ?if (EnableFastISelOption == cl::BOU_TRUE ||
>>> - ? ? ?(Fast && EnableFastISelOption != cl::BOU_FALSE))
>>> + ? ? ?(OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
>>> ? ?EnableFastISel = true;
>>>
>>> ?// Ask the target for an isel.
>>> - ?if (addInstSelector(PM, Fast))
>>> + ?if (addInstSelector(PM, OptLevel))
>>> ? ?return true;
>>>
>>> ?// Print the instruction selected machine code...
>>> ?if (PrintMachineCode)
>>> ? ?PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> - ?if (!Fast) {
>>> + ?if (OptLevel != 0) {
>>> ? ?PM.add(createMachineLICMPass());
>>> ? ?PM.add(createMachineSinkingPass());
>>> ?}
>>>
>>> ?// Run pre-ra passes.
>>> - ?if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
>>> + ?if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
>>> ? ?PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> ?// Perform register allocation.
>>> ?PM.add(createRegisterAllocator());
>>>
>>> ?// Perform stack slot coloring.
>>> - ?if (!Fast)
>>> + ?if (OptLevel != 0)
>>> ? ?PM.add(createStackSlotColoringPass());
>>>
>>> ?if (PrintMachineCode) ?// Print the register-allocated code
>>> ? ?PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> ?// Run post-ra passes.
>>> - ?if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
>>> + ?if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
>>> ? ?PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> ?if (PrintMachineCode)
>>> @@ -216,7 +217,7 @@
>>> ? ?PM.add(createMachineFunctionPrinterPass(cerr));
>>>
>>> ?// Second pass scheduler.
>>> - ?if (!Fast && !DisablePostRAScheduler) {
>>> + ?if (OptLevel != 0 && !DisablePostRAScheduler) {
>>> ? ?PM.add(createPostRAScheduler());
>>>
>>> ? ?if (PrintMachineCode)
>>> @@ -224,7 +225,7 @@
>>> ?}
>>>
>>> ?// Branch folding must be run after regalloc and prolog/epilog
>>> insertion.
>>> - ?if (!Fast)
>>> + ?if (OptLevel != 0)
>>> ? ?PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
>>>
>>> ?if (PrintMachineCode)
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -57,9 +57,9 @@
>>> ? ?SelectionDAG &DAG;
>>> ? ?const TargetLowering &TLI;
>>> ? ?CombineLevel Level;
>>> + ? ?unsigned OptLevel;
>>> ? ?bool LegalOperations;
>>> ? ?bool LegalTypes;
>>> - ? ?bool Fast;
>>>
>>> ? ?// Worklist of all of the nodes that need to be simplified.
>>> ? ?std::vector<SDNode*> WorkList;
>>> @@ -254,13 +254,13 @@
>>> ? ?}
>>>
>>> public:
>>> - ? ?DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
>>> + ? ?DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
>>> ? ? ?: DAG(D),
>>> ? ? ? ?TLI(D.getTargetLoweringInfo()),
>>> ? ? ? ?Level(Unrestricted),
>>> + ? ? ? ?OptLevel(OL),
>>> ? ? ? ?LegalOperations(false),
>>> ? ? ? ?LegalTypes(false),
>>> - ? ? ? ?Fast(fast),
>>> ? ? ? ?AA(A) {}
>>>
>>> ? ?/// Run - runs the dag combiner on all nodes in the work list
>>> @@ -4784,7 +4784,7 @@
>>> ?SDValue Ptr ? = LD->getBasePtr();
>>>
>>> ?// Try to infer better alignment information than the load already
>>> has.
>>> - ?if (!Fast && LD->isUnindexed()) {
>>> + ?if (OptLevel != 0 && LD->isUnindexed()) {
>>> ? ?if (unsigned Align = InferAlignment(Ptr, DAG)) {
>>> ? ? ?if (Align > LD->getAlignment())
>>> ? ? ? ?return DAG.getExtLoad(LD->getExtensionType(), N-
>>>> getDebugLoc(),
>>> @@ -4904,7 +4904,7 @@
>>> ?SDValue Ptr ? = ST->getBasePtr();
>>>
>>> ?// Try to infer better alignment information than the store
>>> already has.
>>> - ?if (!Fast && ST->isUnindexed()) {
>>> + ?if (OptLevel != 0 && ST->isUnindexed()) {
>>> ? ?if (unsigned Align = InferAlignment(Ptr, DAG)) {
>>> ? ? ?if (Align > ST->getAlignment())
>>> ? ? ? ?return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
>>> @@ -6084,8 +6084,9 @@
>>>
>>> // SelectionDAG::Combine - This is the entry point for the file.
>>> //
>>> -void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
>>> bool Fast) {
>>> +void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel) {
>>> ?/// run - This is the main entry point to this class.
>>> ?///
>>> - ?DAGCombiner(*this, AA, Fast).Run(Level);
>>> + ?DAGCombiner(*this, AA, OptLevel).Run(Level);
>>> }
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -327,7 +327,7 @@
>>> ?default: break;
>>> ?case Intrinsic::dbg_stoppoint: {
>>> ? ?DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
>>> - ? ?if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) {
>>> + ? ?if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
>>> ? ? ?DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
>>> ? ? ?std::string Dir, FN;
>>> ? ? ?unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
>>> @@ -344,7 +344,7 @@
>>> ?}
>>> ?case Intrinsic::dbg_region_start: {
>>> ? ?DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
>>> - ? ?if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) {
>>> + ? ?if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
>>> ? ? ?unsigned ID =
>>> ? ? ? ?DW->RecordRegionStart(cast<GlobalVariable>(RSI-
>>>> getContext()));
>>> ? ? ?const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
>>> @@ -354,7 +354,7 @@
>>> ?}
>>> ?case Intrinsic::dbg_region_end: {
>>> ? ?DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
>>> - ? ?if (DW && DW->ValidDebugInfo(REI->getContext(), true)) {
>>> + ? ?if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
>>> ? ? unsigned ID = 0;
>>> ? ? DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
>>> ? ? if (!Subprogram.isNull() && !
>>> Subprogram.describes(MF.getFunction())) {
>>> @@ -380,7 +380,7 @@
>>> ? ?DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
>>> ? ?Value *SP = FSI->getSubprogram();
>>>
>>> - ? ?if (DW->ValidDebugInfo(SP, true)) {
>>> + ? ?if (DW->ValidDebugInfo(SP, 0)) {
>>> ? ? ?// llvm.dbg.func.start implicitly defines a dbg_stoppoint
>>> which is what
>>> ? ? ?// (most?) gdb expects.
>>> ? ? ?DebugLoc PrevLoc = DL;
>>> @@ -425,7 +425,7 @@
>>> ?case Intrinsic::dbg_declare: {
>>> ? ?DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
>>> ? ?Value *Variable = DI->getVariable();
>>> - ? ?if (DW && DW->ValidDebugInfo(Variable, true)) {
>>> + ? ?if (DW && DW->ValidDebugInfo(Variable, 0)) {
>>> ? ? ?// Determine the address of the declared object.
>>> ? ? ?Value *Address = DI->getAddress();
>>> ? ? ?if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -55,8 +55,8 @@
>>> class VISIBILITY_HIDDEN SelectionDAGLegalize {
>>> ?TargetLowering &TLI;
>>> ?SelectionDAG &DAG;
>>> + ?unsigned OptLevel;
>>> ?bool TypesNeedLegalizing;
>>> - ?bool Fast;
>>>
>>> ?// Libcall insertion helpers.
>>>
>>> @@ -139,7 +139,7 @@
>>>
>>> public:
>>> ?explicit SelectionDAGLegalize(SelectionDAG &DAG, bool
>>> TypesNeedLegalizing,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool fast);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned ol);
>>>
>>> ?/// getTypeAction - Return how we should legalize values of this
>>> type, either
>>> ?/// it is already legal or we need to expand it into multiple
>>> registers of
>>> @@ -345,9 +345,9 @@
>>> }
>>>
>>> SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool types, bool fast)
>>> - ?: TLI(dag.getTargetLoweringInfo()), DAG(dag),
>>> TypesNeedLegalizing(types),
>>> - ? ?Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool types, unsigned ol)
>>> + ?: TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
>>> + ? ?TypesNeedLegalizing(types),
>>> ValueTypeActions(TLI.getValueTypeActions()) {
>>> ?assert(MVT::LAST_VALUETYPE <= 32 &&
>>> ? ? ? ? "Too many value types for ValueTypeActions to hold!");
>>> }
>>> @@ -1271,7 +1271,7 @@
>>> ? ? ? ?unsigned Line = DSP->getLine();
>>> ? ? ? ?unsigned Col = DSP->getColumn();
>>>
>>> - ? ? ? ?if (Fast) {
>>> + ? ? ? ?if (OptLevel == 0) {
>>> ? ? ? ? ?// A bit self-referential to have DebugLoc on Debug_Loc
>>> nodes, but it
>>> ? ? ? ? ?// won't hurt anything.
>>> ? ? ? ? ?if (useDEBUG_LOC) {
>>> @@ -8566,9 +8566,9 @@
>>>
>>> // SelectionDAG::Legalize - This is the entry point for the file.
>>> //
>>> -void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
>>> +void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned
>>> OptLevel) {
>>> ?/// run - This is the main entry point to this class.
>>> ?///
>>> - ?SelectionDAGLegalize(*this, TypesNeedLegalizing,
>>> Fast).LegalizeDAG();
>>> + ?SelectionDAGLegalize(*this, TypesNeedLegalizing,
>>> OptLevel).LegalizeDAG();
>>> }
>>>
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>>> (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Mon Apr
>>> 27 19:21:31 2009
>>> @@ -630,6 +630,6 @@
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> llvm::ScheduleDAGSDNodes *
>>> -llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
>>> +llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>> ?return new ScheduleDAGFast(*IS->MF);
>>> }
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>>> (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon Apr
>>> 27 19:21:31 2009
>>> @@ -261,7 +261,7 @@
>>> /// new hazard recognizer. This scheduler takes ownership of the
>>> hazard
>>> /// recognizer and deletes it when done.
>>> ScheduleDAGSDNodes *
>>> -llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) {
>>> +llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>> ?return new ScheduleDAGList(*IS->MF,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? new LatencyPriorityQueue(),
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? IS->CreateTargetHazardRecognizer());
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>> (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon
>>> Apr 27 19:21:31 2009
>>> @@ -1505,7 +1505,7 @@
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> llvm::ScheduleDAGSDNodes *
>>> -llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
>>> +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>> ?const TargetMachine &TM = IS->TM;
>>> ?const TargetInstrInfo *TII = TM.getInstrInfo();
>>> ?const TargetRegisterInfo *TRI = TM.getRegisterInfo();
>>> @@ -1519,7 +1519,7 @@
>>> }
>>>
>>> llvm::ScheduleDAGSDNodes *
>>> -llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
>>> +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>> ?const TargetMachine &TM = IS->TM;
>>> ?const TargetInstrInfo *TII = TM.getInstrInfo();
>>> ?const TargetRegisterInfo *TRI = TM.getRegisterInfo();
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>>> (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon
>>> Apr 27 19:21:31 2009
>>> @@ -3910,9 +3910,9 @@
>>> ?case Intrinsic::dbg_stoppoint: {
>>> ? ?DwarfWriter *DW = DAG.getDwarfWriter();
>>> ? ?DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
>>> - ? ?if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
>>> + ? ?if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
>>> ? ? ?MachineFunction &MF = DAG.getMachineFunction();
>>> - ? ? ?if (Fast)
>>> + ? ? ?if (OptLevel == 0)
>>> ? ? ? ?DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SPI.getLine(),
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SPI.getColumn(),
>>> @@ -3930,7 +3930,8 @@
>>> ?case Intrinsic::dbg_region_start: {
>>> ? ?DwarfWriter *DW = DAG.getDwarfWriter();
>>> ? ?DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
>>> - ? ?if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
>>> +
>>> + ? ?if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) {
>>> ? ? ?unsigned LabelID =
>>> ? ? ? ?DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
>>> ? ? ?DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
>>> @@ -3942,8 +3943,8 @@
>>> ?case Intrinsic::dbg_region_end: {
>>> ? ?DwarfWriter *DW = DAG.getDwarfWriter();
>>> ? ?DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
>>> - ? ?if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
>>>
>>> + ? ?if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) {
>>> ? ? ?MachineFunction &MF = DAG.getMachineFunction();
>>> ? ? ?DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
>>> ? ? ?std::string SPName;
>>> @@ -3952,7 +3953,7 @@
>>> ? ? ? ? ?&& strcmp(SPName.c_str(), MF.getFunction()-
>>>> getNameStart())) {
>>> ? ? ? ? ?// This is end of inlined function. Debugging information
>>> for
>>> ? ? ? ? ?// inlined function is not handled yet (only supported by
>>> FastISel).
>>> - ? ? ? ?if (Fast) {
>>> + ? ? ? ?if (OptLevel == 0) {
>>> ? ? ? ? ?unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
>>> ? ? ? ? ?if (ID != 0)
>>> ? ? ? ? ? ?// Returned ID is 0 if this is unbalanced "end of inlined
>>> @@ -3978,9 +3979,9 @@
>>> ? ?if (!DW) return 0;
>>> ? ?DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
>>> ? ?Value *SP = FSI.getSubprogram();
>>> - ? ?if (SP && DW->ValidDebugInfo(SP, Fast)) {
>>> - ? ? ? ?MachineFunction &MF = DAG.getMachineFunction();
>>> - ? ? ?if (Fast) {
>>> + ? ?if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
>>> + ? ? ?MachineFunction &MF = DAG.getMachineFunction();
>>> + ? ? ?if (OptLevel == 0) {
>>> ? ? ? ?// llvm.dbg.func.start implicitly defines a dbg_stoppoint
>>> which is what
>>> ? ? ? ?// (most?) gdb expects.
>>> ? ? ? ?DebugLoc PrevLoc = CurDebugLoc;
>>> @@ -4051,11 +4052,11 @@
>>> ? ?return 0;
>>> ?}
>>> ?case Intrinsic::dbg_declare: {
>>> - ? ?if (Fast) {
>>> + ? ?if (OptLevel == 0) {
>>> ? ? ?DwarfWriter *DW = DAG.getDwarfWriter();
>>> ? ? ?DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
>>> ? ? ?Value *Variable = DI.getVariable();
>>> - ? ? ?if (DW && DW->ValidDebugInfo(Variable, Fast))
>>> + ? ? ?if (DW && DW->ValidDebugInfo(Variable, OptLevel))
>>> ? ? ? ?DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other,
>>> getRoot(),
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?getValue(DI.getAddress()),
>>> getValue(Variable)));
>>> ? ?} else {
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>>> (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Mon Apr
>>> 27 19:21:31 2009
>>> @@ -355,17 +355,17 @@
>>> ?///
>>> ?FunctionLoweringInfo &FuncInfo;
>>>
>>> - ?/// Fast - We are in -fast mode.
>>> + ?/// OptLevel - What optimization level we're generating code for.
>>> ?///
>>> - ?bool Fast;
>>> + ?unsigned OptLevel;
>>>
>>> ?/// GFI - Garbage collection metadata for the function.
>>> ?GCFunctionInfo *GFI;
>>>
>>> ?SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
>>> - ? ? ? ? ? ? ? ? ? ? ? FunctionLoweringInfo &funcinfo, bool fast)
>>> + ? ? ? ? ? ? ? ? ? ? ? FunctionLoweringInfo &funcinfo, unsigned ol)
>>> ? ?: CurDebugLoc(DebugLoc::getUnknownLoc()),
>>> - ? ? ?TLI(tli), DAG(dag), FuncInfo(funcinfo), Fast(fast) {
>>> + ? ? ?TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
>>> ?}
>>>
>>> ?void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>>> (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr
>>> 27 19:21:31 2009
>>> @@ -136,16 +136,16 @@
>>> ?/// createDefaultScheduler - This creates an instruction scheduler
>>> appropriate
>>> ?/// for the target.
>>> ?ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Fast) {
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel) {
>>> ? ?const TargetLowering &TLI = IS->getTargetLowering();
>>>
>>> - ? ?if (Fast)
>>> - ? ? ?return createFastDAGScheduler(IS, Fast);
>>> + ? ?if (OptLevel == 0)
>>> + ? ? ?return createFastDAGScheduler(IS, OptLevel);
>>> ? ?if (TLI.getSchedulingPreference() ==
>>> TargetLowering::SchedulingForLatency)
>>> - ? ? ?return createTDListDAGScheduler(IS, Fast);
>>> + ? ? ?return createTDListDAGScheduler(IS, OptLevel);
>>> ? ?assert(TLI.getSchedulingPreference() ==
>>> ? ? ? ? TargetLowering::SchedulingForRegPressure && "Unknown sched
>>> type!");
>>> - ? ?return createBURRListDAGScheduler(IS, Fast);
>>> + ? ?return createBURRListDAGScheduler(IS, OptLevel);
>>> ?}
>>> }
>>>
>>> @@ -262,13 +262,13 @@
>>> // SelectionDAGISel code
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> -SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
>>> +SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
>>> ?FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
>>> ?FuncInfo(new FunctionLoweringInfo(TLI)),
>>> ?CurDAG(new SelectionDAG(TLI, *FuncInfo)),
>>> - ?SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)),
>>> + ?SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)),
>>> ?GFI(),
>>> - ?Fast(fast),
>>> + ?OptLevel(OL),
>>> ?DAGSize(0)
>>> {}
>>>
>>> @@ -576,9 +576,9 @@
>>> ?// Run the DAG combiner in pre-legalize mode.
>>> ?if (TimePassesIsEnabled) {
>>> ? ?NamedRegionTimer T("DAG Combining 1", GroupName);
>>> - ? ?CurDAG->Combine(Unrestricted, *AA, Fast);
>>> + ? ?CurDAG->Combine(Unrestricted, *AA, OptLevel);
>>> ?} else {
>>> - ? ?CurDAG->Combine(Unrestricted, *AA, Fast);
>>> + ? ?CurDAG->Combine(Unrestricted, *AA, OptLevel);
>>> ?}
>>>
>>> ?DOUT << "Optimized lowered selection DAG:\n";
>>> @@ -608,9 +608,9 @@
>>> ? ? ?// Run the DAG combiner in post-type-legalize mode.
>>> ? ? ?if (TimePassesIsEnabled) {
>>> ? ? ? ?NamedRegionTimer T("DAG Combining after legalize types",
>>> GroupName);
>>> - ? ? ? ?CurDAG->Combine(NoIllegalTypes, *AA, Fast);
>>> + ? ? ? ?CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
>>> ? ? ?} else {
>>> - ? ? ? ?CurDAG->Combine(NoIllegalTypes, *AA, Fast);
>>> + ? ? ? ?CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
>>> ? ? ?}
>>>
>>> ? ? ?DOUT << "Optimized type-legalized selection DAG:\n";
>>> @@ -622,9 +622,9 @@
>>>
>>> ?if (TimePassesIsEnabled) {
>>> ? ?NamedRegionTimer T("DAG Legalization", GroupName);
>>> - ? ?CurDAG->Legalize(DisableLegalizeTypes, Fast);
>>> + ? ?CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
>>> ?} else {
>>> - ? ?CurDAG->Legalize(DisableLegalizeTypes, Fast);
>>> + ? ?CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
>>> ?}
>>>
>>> ?DOUT << "Legalized selection DAG:\n";
>>> @@ -635,9 +635,9 @@
>>> ?// Run the DAG combiner in post-legalize mode.
>>> ?if (TimePassesIsEnabled) {
>>> ? ?NamedRegionTimer T("DAG Combining 2", GroupName);
>>> - ? ?CurDAG->Combine(NoIllegalOperations, *AA, Fast);
>>> + ? ?CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
>>> ?} else {
>>> - ? ?CurDAG->Combine(NoIllegalOperations, *AA, Fast);
>>> + ? ?CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
>>> ?}
>>>
>>> ?DOUT << "Optimized legalized selection DAG:\n";
>>> @@ -645,7 +645,7 @@
>>>
>>> ?if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
>>>
>>> - ?if (!Fast)
>>> + ?if (OptLevel != 0)
>>> ? ?ComputeLiveOutVRegInfo();
>>>
>>> ?// Third, instruction select all of the operations to machine
>>> code, adding the
>>> @@ -1082,7 +1082,7 @@
>>> ? ?RegisterScheduler::setDefault(Ctor);
>>> ?}
>>>
>>> - ?return Ctor(this, Fast);
>>> + ?return Ctor(this, OptLevel);
>>> }
>>>
>>> ScheduleHazardRecognizer
>>> *SelectionDAGISel::CreateTargetHazardRecognizer() {
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/ARM.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARM.h (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARM.h Mon Apr 27 19:21:31 2009
>>> @@ -91,7 +91,7 @@
>>> FunctionPass *createARMISelDag(ARMTargetMachine &TM);
>>> FunctionPass *createARMCodePrinterPass(raw_ostream &O,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMTargetMachine &TM,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Fast, bool Verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel, bool
>>> Verbose);
>>> FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineCodeEmitter &MCE);
>>> FunctionPass *createARMLoadStoreOptimizationPass();
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -138,35 +138,37 @@
>>>
>>>
>>> // Pass Pipeline Configuration
>>> -bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
>>> unsigned OptLevel) {
>>> ?PM.add(createARMISelDag(*this));
>>> ?return false;
>>> }
>>>
>>> -bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel) {
>>> ?// FIXME: temporarily disabling load / store optimization pass for
>>> Thumb mode.
>>> - ?if (!Fast && !DisableLdStOpti && !Subtarget.isThumb())
>>> + ?if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
>>> ? ?PM.add(createARMLoadStoreOptimizationPass());
>>>
>>> - ?if (!Fast && !DisableIfConversion && !Subtarget.isThumb())
>>> + ?if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
>>> ? ?PM.add(createIfConverterPass());
>>>
>>> ?PM.add(createARMConstantIslandPass());
>>> ?return true;
>>> }
>>>
>>> -bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool
>>> Fast,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose, raw_ostream
>>> &Out) {
>>> +bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &Out) {
>>> ?// Output assembly language.
>>> ?assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>> ?if (AsmPrinterCtor)
>>> - ? ?PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
>>> + ? ?PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>>>
>>> ?return false;
>>> }
>>>
>>>
>>> -bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, bool
>>> Fast,
>>> +bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool DumpAsm,
>>> MachineCodeEmitter &MCE) {
>>> ?// FIXME: Move this to TargetJITInfo!
>>> ?if (DefRelocModel == Reloc::Default)
>>> @@ -177,20 +179,22 @@
>>> ?if (DumpAsm) {
>>> ? ?assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>> ? ?if (AsmPrinterCtor)
>>> - ? ? ?PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>>> + ? ? ?PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>> ?}
>>>
>>> ?return false;
>>> }
>>>
>>> -bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>> bool Fast,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool DumpAsm,
>>> MachineCodeEmitter &MCE) {
>>> +bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool DumpAsm,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineCodeEmitter
>>> &MCE) {
>>> ?// Machine code emitter pass for ARM.
>>> ?PM.add(createARMCodeEmitterPass(*this, MCE));
>>> ?if (DumpAsm) {
>>> ? ?assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>> ? ?if (AsmPrinterCtor)
>>> - ? ? ?PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>>> + ? ? ?PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>> ?}
>>>
>>> ?return false;
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Mon Apr 27 19:21:31
>>> 2009
>>> @@ -41,7 +41,7 @@
>>> ?// set this functions to ctor pointer at startup time if they are
>>> linked in.
>>> ?typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ARMTargetMachine &tm,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool fast, bool
>>> verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel, bool
>>> verbose);
>>> ?static AsmPrinterCtorFn AsmPrinterCtor;
>>>
>>> public:
>>> @@ -69,13 +69,13 @@
>>> ?virtual const TargetAsmInfo *createTargetAsmInfo() const;
>>>
>>> ?// Pass Pipeline Configuration
>>> - ?virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>> - ?virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>> - ?virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> + ?virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + ?virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + ?virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose, raw_ostream &Out);
>>> - ?virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
>>> + ?virtual bool addCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool DumpAsm, MachineCodeEmitter &MCE);
>>> - ?virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
>>> + ?virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool DumpAsm, MachineCodeEmitter
>>> &MCE);
>>> };
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Mon Apr
>>> 27 19:21:31 2009
>>> @@ -80,9 +80,9 @@
>>> ? ?/// True if asm printer is printing a series of CONSTPOOL_ENTRY.
>>> ? ?bool InCPMode;
>>> ?public:
>>> - ? ?ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> - ? ? ? ? ? ? ? ? ?const TargetAsmInfo *T, bool F, bool V)
>>> - ? ? ?: AsmPrinter(O, TM, T, F, V), DW(0), MMI(NULL), AFI(NULL),
>>> MCP(NULL),
>>> + ? ?explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? const TargetAsmInfo *T, unsigned OL,
>>> bool V)
>>> + ? ? ?: AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL),
>>> MCP(NULL),
>>> ? ? ? ?InCPMode(false) {
>>> ? ? ?Subtarget = &TM.getSubtarget<ARMSubtarget>();
>>> ? ?}
>>> @@ -1061,8 +1061,8 @@
>>> ///
>>> FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMTargetMachine &tm,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool fast, bool
>>> verbose) {
>>> - ?return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>> verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel,
>>> bool verbose) {
>>> + ?return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
>>> verbose);
>>> }
>>>
>>> namespace {
>>>
>>> Modified: llvm/trunk/lib/Target/Alpha/Alpha.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Alpha/Alpha.h (original)
>>> +++ llvm/trunk/lib/Target/Alpha/Alpha.h Mon Apr 27 19:21:31 2009
>>> @@ -26,7 +26,7 @@
>>> ?FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
>>> ?FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TargetMachine &TM,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Fast, bool Verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel, bool
>>> Verbose);
>>> ?FunctionPass *createAlphaPatternInstructionSelector(TargetMachine
>>> &TM);
>>> ?FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineCodeEmitter &MCE);
>>>
>>> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -76,31 +76,34 @@
>>> // Pass Pipeline Configuration
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> -bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel) {
>>> ?PM.add(createAlphaISelDag(*this));
>>> ?return false;
>>> }
>>> -bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel) {
>>> ?// Must run branch selection immediately preceding the asm printer
>>> ?PM.add(createAlphaBranchSelectionPass());
>>> ?return false;
>>> }
>>> -bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> bool Fast,
>>> +bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &Out) {
>>> ?PM.add(createAlphaLLRPPass(*this));
>>> - ?PM.add(createAlphaCodePrinterPass(Out, *this, Fast, Verbose));
>>> + ?PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
>>> ?return false;
>>> }
>>> -bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, bool
>>> Fast,
>>> +bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
>>> unsigned OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool DumpAsm,
>>> MachineCodeEmitter &MCE) {
>>> ?PM.add(createAlphaCodeEmitterPass(*this, MCE));
>>> ?if (DumpAsm)
>>> - ? ?PM.add(createAlphaCodePrinterPass(errs(), *this, Fast, true));
>>> + ? ?PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel,
>>> true));
>>> ?return false;
>>> }
>>> bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Fast, bool
>>> DumpAsm,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel,
>>> bool DumpAsm,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineCodeEmitter
>>> &MCE) {
>>> - ?return addCodeEmitter(PM, Fast, DumpAsm, MCE);
>>> + ?return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
>>> }
>>>
>>> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -58,13 +58,13 @@
>>> ?static unsigned getModuleMatchQuality(const Module &M);
>>>
>>> ?// Pass Pipeline Configuration
>>> - ?virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>> - ?virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>> - ?virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> + ?virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + ?virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + ?virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose, raw_ostream &Out);
>>> - ?virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
>>> + ?virtual bool addCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool DumpAsm, MachineCodeEmitter &MCE);
>>> - ?virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
>>> + ?virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool DumpAsm, MachineCodeEmitter
>>> &MCE);
>>> };
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Mon
>>> Apr 27 19:21:31 2009
>>> @@ -36,9 +36,9 @@
>>> ? ?/// Unique incrementer for label values for referencing Global
>>> values.
>>> ? ?///
>>>
>>> - ? ?AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
>>> - ? ? ? ? ? ? ? ? ? ?const TargetAsmInfo *T, bool F, bool V)
>>> - ? ? ?: AsmPrinter(o, tm, T, F, V) {}
>>> + ? ?explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? const TargetAsmInfo *T, unsigned OL,
>>> bool V)
>>> + ? ? ?: AsmPrinter(o, tm, T, OL, V) {}
>>>
>>> ? ?virtual const char *getPassName() const {
>>> ? ? ?return "Alpha Assembly Printer";
>>> @@ -68,8 +68,9 @@
>>> ///
>>> FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TargetMachine &tm,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool fast, bool
>>> verbose) {
>>> - ?return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>> verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool verbose) {
>>> + ?return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> OptLevel, verbose);
>>> }
>>>
>>> #include "AlphaGenAsmWriter.inc"
>>>
>>> Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
>>> +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Apr 27 19:21:31
>>> 2009
>>> @@ -3587,7 +3587,7 @@
>>> bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &o,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CodeGenFileType
>>> FileType,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Fast) {
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel) {
>>> ?if (FileType != TargetMachine::AssemblyFile) return true;
>>>
>>> ?PM.add(createGCLoweringPass());
>>>
>>> Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -27,7 +27,8 @@
>>>
>>> ?virtual bool WantsWholeFile() const { return true; }
>>> ?virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream
>>> &Out,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CodeGenFileType FileType,
>>> bool Fast);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CodeGenFileType FileType,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel);
>>>
>>> ?// This class always works, but must be requested explicitly on
>>> ?// llc command line.
>>>
>>> Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Mon
>>> Apr 27 19:21:31 2009
>>> @@ -48,9 +48,9 @@
>>> ?class VISIBILITY_HIDDEN SPUAsmPrinter : public AsmPrinter {
>>> ? ?std::set<std::string> FnStubs, GVStubs;
>>> ?public:
>>> - ? ?SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> - ? ? ? ? ? ? ? ? ?const TargetAsmInfo *T, bool F, bool V) :
>>> - ? ? ?AsmPrinter(O, TM, T, F, V) {}
>>> + ? ?explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? const TargetAsmInfo *T, unsigned OL,
>>> bool V) :
>>> + ? ? ?AsmPrinter(O, TM, T, OL, V) {}
>>>
>>> ? ?virtual const char *getPassName() const {
>>> ? ? ?return "STI CBEA SPU Assembly Printer";
>>> @@ -615,6 +615,6 @@
>>> ///
>>> FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SPUTargetMachine &tm,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool fast, bool
>>> verbose) {
>>> - ?return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>> verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel, bool
>>> verbose) {
>>> + ?return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> OptLevel, verbose);
>>> }
>>>
>>> Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
>>> +++ llvm/trunk/lib/Target/CellSPU/SPU.h Mon Apr 27 19:21:31 2009
>>> @@ -25,7 +25,7 @@
>>> ?FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
>>> ?FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SPUTargetMachine &tm,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool fast, bool verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel, bool
>>> verbose);
>>>
>>> ?/*--== Utility functions/predicates/etc used all over the place: --
>>> ==*/
>>> ?//! Predicate test for a signed 10-bit value
>>>
>>> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -81,15 +81,17 @@
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> bool
>>> -SPUTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast)
>>> +SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel)
>>> {
>>> ?// Install an instruction selector.
>>> ?PM.add(createSPUISelDag(*this));
>>> ?return false;
>>> }
>>>
>>> -bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool
>>> Fast,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose, raw_ostream
>>> &Out) {
>>> - ?PM.add(createSPUAsmPrinterPass(Out, *this, Fast, Verbose));
>>> +bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &Out) {
>>> + ?PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
>>> ?return false;
>>> }
>>>
>>> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -83,9 +83,9 @@
>>> ?}
>>>
>>> ?// Pass Pipeline Configuration
>>> - ?virtual bool addInstSelector(PassManagerBase &PM, bool /*Fast*/);
>>> - ?virtual bool addAssemblyEmitter(PassManagerBase &PM, bool /
>>> *Fast*/,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool /*Verbose*/, raw_ostream
>>> &Out);
>>> + ?virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + ?virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose, raw_ostream &Out);
>>> };
>>>
>>> } // end namespace llvm
>>>
>>> Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
>>> +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -1995,7 +1995,7 @@
>>> bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &o,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CodeGenFileType
>>> FileType,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Fast) {
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel) {
>>> ?if (FileType != TargetMachine::AssemblyFile) return true;
>>> ?PM.add(new CppWriter(o));
>>> ?return false;
>>>
>>> Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -29,7 +29,8 @@
>>>
>>> ?virtual bool WantsWholeFile() const { return true; }
>>> ?virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream
>>> &Out,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CodeGenFileType FileType,
>>> bool Fast);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CodeGenFileType FileType,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel);
>>>
>>> ?// This class always works, but shouldn't be the default in most
>>> cases.
>>> ?static unsigned getModuleMatchQuality(const Module &M) { return 1; }
>>>
>>> Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Mon Apr
>>> 27 19:21:31 2009
>>> @@ -37,9 +37,9 @@
>>> ?class IA64AsmPrinter : public AsmPrinter {
>>> ? ?std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
>>> ?public:
>>> - ? ?IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> - ? ? ? ? ? ? ? ? ? const TargetAsmInfo *T, bool F, bool V)
>>> - ? ? ?: AsmPrinter(O, TM, T, F, V) {}
>>> + ? ?explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ?const TargetAsmInfo *T, unsigned OL,
>>> bool V)
>>> + ? ? ?: AsmPrinter(O, TM, T, OL, V) {}
>>>
>>> ? ?virtual const char *getPassName() const {
>>> ? ? ?return "IA64 Assembly Printer";
>>> @@ -370,6 +370,7 @@
>>> ///
>>> FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?IA64TargetMachine &tm,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool fast, bool
>>> verbose) {
>>> - ?return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>> verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool verbose) {
>>> + ?return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
>>> verbose);
>>> }
>>>
>>> Modified: llvm/trunk/lib/Target/IA64/IA64.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/IA64/IA64.h (original)
>>> +++ llvm/trunk/lib/Target/IA64/IA64.h Mon Apr 27 19:21:31 2009
>>> @@ -37,7 +37,7 @@
>>> ///
>>> FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?IA64TargetMachine &tm,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool fast, bool verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel, bool
>>> verbose);
>>>
>>> } // End llvm namespace
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -72,19 +72,21 @@
>>> // Pass Pipeline Configuration
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> -bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,
>>> unsigned OptLEvel){
>>> ?PM.add(createIA64DAGToDAGInstructionSelector(*this));
>>> ?return false;
>>> }
>>>
>>> -bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,
>>> unsigned OptLevel) {
>>> ?// Make sure everything is bundled happily
>>> ?PM.add(createIA64BundlingPass(*this));
>>> ?return true;
>>> }
>>> -bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> bool Fast,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Verbose,
>>> raw_ostream &Out) {
>>> - ?PM.add(createIA64CodePrinterPass(Out, *this, Fast, Verbose));
>>> +bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Verbose,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? raw_ostream &Out) {
>>> + ?PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
>>> ?return false;
>>> }
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -51,9 +51,9 @@
>>> ?static unsigned getModuleMatchQuality(const Module &M);
>>>
>>> ?// Pass Pipeline Configuration
>>> - ?virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>> - ?virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>> - ?virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> + ?virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + ?virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + ?virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose, raw_ostream &Out);
>>> };
>>> } // End llvm namespace
>>>
>>> Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
>>> +++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Mon Apr 27 19:21:31
>>> 2009
>>> @@ -35,7 +35,8 @@
>>>
>>> ? ?virtual bool WantsWholeFile() const { return true; }
>>> ? ?virtual bool addPassesToEmitWholeFile(PassManager &PM,
>>> raw_ostream &Out,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CodeGenFileType FileType,
>>> bool Fast);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CodeGenFileType FileType,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel);
>>>
>>> ? ?// This class always works, but shouldn't be the default in most
>>> cases.
>>> ? ?static unsigned getModuleMatchQuality(const Module &M) { return
>>> 1; }
>>> @@ -1662,7 +1663,8 @@
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM,
>>> raw_ostream &o,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CodeGenFileType FileType,
>>> bool Fast)
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CodeGenFileType FileType,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel)
>>> {
>>> ?if (FileType != TargetMachine::AssemblyFile) return true;
>>> ?MSILWriter* Writer = new MSILWriter(o);
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Mon Apr
>>> 27 19:21:31 2009
>>> @@ -49,9 +49,9 @@
>>> ?class VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
>>> ? ?const MipsSubtarget *Subtarget;
>>> ?public:
>>> - ? ?MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
>>> - ? ? ? ? ? ? ? ? ? const TargetAsmInfo *T, bool F, bool V)
>>> - ? ? ?: AsmPrinter(O, TM, T, F, V) {
>>> + ? ?explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ?const TargetAsmInfo *T, unsigned OL,
>>> bool V)
>>> + ? ? ?: AsmPrinter(O, TM, T, OL, V) {
>>> ? ? ?Subtarget = &TM.getSubtarget<MipsSubtarget>();
>>> ? ?}
>>>
>>> @@ -91,8 +91,8 @@
>>> /// regardless of whether the function is in SSA form.
>>> FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MipsTargetMachine &tm,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool fast, bool
>>> verbose) {
>>> - ?return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>> verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel,
>>> bool verbose) {
>>> + ?return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
>>> verbose);
>>> }
>>>
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/Mips.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Mips/Mips.h (original)
>>> +++ llvm/trunk/lib/Target/Mips/Mips.h Mon Apr 27 19:21:31 2009
>>> @@ -25,7 +25,7 @@
>>> ?FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
>>> ?FunctionPass *createMipsCodePrinterPass(raw_ostream &OS,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MipsTargetMachine &TM,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Fast, bool Verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel, bool
>>> Verbose);
>>> } // end namespace llvm;
>>>
>>> // Defines symbolic names for Mips registers. ?This defines a
>>> mapping from
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -105,7 +105,7 @@
>>> // Install an instruction selector pass using
>>> // the ISelDag to gen Mips code.
>>> bool MipsTargetMachine::
>>> -addInstSelector(PassManagerBase &PM, bool Fast)
>>> +addInstSelector(PassManagerBase &PM, unsigned OptLevel)
>>> {
>>> ?PM.add(createMipsISelDag(*this));
>>> ?return false;
>>> @@ -115,7 +115,7 @@
>>> // machine code is emitted. return true if -print-machineinstrs
>>> should
>>> // print out the code after the passes.
>>> bool MipsTargetMachine::
>>> -addPreEmitPass(PassManagerBase &PM, bool Fast)
>>> +addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
>>> {
>>> ?PM.add(createMipsDelaySlotFillerPass(*this));
>>> ?return true;
>>> @@ -124,10 +124,10 @@
>>> // Implements the AssemblyEmitter for the target. Must return
>>> // true if AssemblyEmitter is supported
>>> bool MipsTargetMachine::
>>> -addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
>>> ? ? ? ? ? ? ? ? ? bool Verbose, raw_ostream &Out)
>>> {
>>> ?// Output assembly language.
>>> - ?PM.add(createMipsCodePrinterPass(Out, *this, Fast, Verbose));
>>> + ?PM.add(createMipsCodePrinterPass(Out, *this, OptLevel, Verbose));
>>> ?return false;
>>> }
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -57,9 +57,9 @@
>>> ? ?static unsigned getModuleMatchQuality(const Module &M);
>>>
>>> ? ?// Pass Pipeline Configuration
>>> - ? ?virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>> - ? ?virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>> - ? ?virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> + ? ?virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + ? ?virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + ? ?virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose, raw_ostream &Out);
>>> ?};
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PIC16/PIC16.h (original)
>>> +++ llvm/trunk/lib/Target/PIC16/PIC16.h Mon Apr 27 19:21:31 2009
>>> @@ -75,7 +75,7 @@
>>> ?FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
>>> ?FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? PIC16TargetMachine &TM,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool Fast, bool Verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel, bool
>>> Verbose);
>>> } // end namespace llvm;
>>>
>>> // Defines symbolic names for PIC16 registers. ?This defines a
>>> mapping from
>>>
>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
>>> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -161,8 +161,9 @@
>>> ///
>>> FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? PIC16TargetMachine &tm,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool fast, bool
>>> verbose) {
>>> - ?return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>> verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool verbose) {
>>> + ?return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> OptLevel, verbose);
>>> }
>>>
>>> void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int
>>> opNum) {
>>>
>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
>>> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -24,9 +24,9 @@
>>>
>>> namespace llvm {
>>> ?struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
>>> - ?PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
>>> - ? ? ? ? ? ? ? ? ? ?const TargetAsmInfo *T, bool F, bool V)
>>> - ? ? ?: AsmPrinter(O, TM, T, F, V) {
>>> + ? ?explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? const TargetAsmInfo *T, unsigned OL,
>>> bool V)
>>> + ? ? ?: AsmPrinter(O, TM, T, OL, V) {
>>> ? ? ?CurBank = "";
>>> ? ? ?FunctionLabelBegin = '@';
>>> ? ? ?IsRomData = false;
>>>
>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -55,17 +55,18 @@
>>> ?return new PIC16TargetAsmInfo(*this);
>>> }
>>>
>>> -bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptLevel) {
>>> ?// Install an instruction selector.
>>> ?PM.add(createPIC16ISelDag(*this));
>>> ?return false;
>>> }
>>>
>>> bool PIC16TargetMachine::
>>> -addAssemblyEmitter(PassManagerBase &PM, bool Fast, bool Verbose,
>>> +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool
>>> Verbose,
>>> ? ? ? ? ? ? ? ? ? raw_ostream &Out) {
>>> ?// Output assembly language.
>>> - ?PM.add(createPIC16CodePrinterPass(Out, *this, Fast, Verbose));
>>> + ?PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
>>> ?return false;
>>> }
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -57,8 +57,8 @@
>>> ? ?return const_cast<PIC16TargetLowering*>(&TLInfo);
>>> ?}
>>>
>>> - ?virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>> - ?virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> + ?virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + ?virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose, raw_ostream &Out);
>>> }; // PIC16TargetMachine.
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Mon
>>> Apr 27 19:21:31 2009
>>> @@ -54,9 +54,9 @@
>>> ? ?StringSet<> FnStubs, GVStubs, HiddenGVStubs;
>>> ? ?const PPCSubtarget &Subtarget;
>>> ?public:
>>> - ? ?PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> - ? ? ? ? ? ? ? ? ?const TargetAsmInfo *T, bool F, bool V)
>>> - ? ? ?: AsmPrinter(O, TM, T, F, V),
>>> + ? ?explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? const TargetAsmInfo *T, unsigned OL,
>>> bool V)
>>> + ? ? ?: AsmPrinter(O, TM, T, OL, V),
>>> ? ? ? ?Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
>>>
>>> ? ?virtual const char *getPassName() const {
>>> @@ -297,9 +297,9 @@
>>> ? ?DwarfWriter *DW;
>>> ? ?MachineModuleInfo *MMI;
>>> ?public:
>>> - ? ?PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
>>> - ? ? ? ? ? ? ? ? ? ? ? const TargetAsmInfo *T, bool F, bool V)
>>> - ? ? ?: PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
>>> + ? ?explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine
>>> &TM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const TargetAsmInfo *T, unsigned
>>> OL, bool V)
>>> + ? ? ?: PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
>>>
>>> ? ?virtual const char *getPassName() const {
>>> ? ? ?return "Linux PPC Assembly Printer";
>>> @@ -326,9 +326,9 @@
>>> ? ?MachineModuleInfo *MMI;
>>> ? ?raw_ostream &OS;
>>> ?public:
>>> - ? ?PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
>>> - ? ? ? ? ? ? ? ? ? ? ? ?const TargetAsmInfo *T, bool F, bool V)
>>> - ? ? ?: PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0), OS(O) {}
>>> + ? ?explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine
>>> &TM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const TargetAsmInfo *T, unsigned
>>> OL, bool V)
>>> + ? ? ?: PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
>>>
>>> ? ?virtual const char *getPassName() const {
>>> ? ? ?return "Darwin PPC Assembly Printer";
>>> @@ -1176,13 +1176,15 @@
>>> ///
>>> FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?PPCTargetMachine &tm,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool fast, bool
>>> verbose) {
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel, bool
>>> verbose) {
>>> ?const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
>>>
>>> ?if (Subtarget->isDarwin()) {
>>> - ? ?return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> fast, verbose);
>>> + ? ?return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? OptLevel, verbose);
>>> ?} else {
>>> - ? ?return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> fast, verbose);
>>> + ? ?return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?OptLevel, verbose);
>>> ?}
>>> }
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/PowerPC/PPC.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PowerPC/PPC.h (original)
>>> +++ llvm/trunk/lib/Target/PowerPC/PPC.h Mon Apr 27 19:21:31 2009
>>> @@ -28,7 +28,7 @@
>>> FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
>>> FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?PPCTargetMachine &TM,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Fast, bool Verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel, bool
>>> Verbose);
>>> FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineCodeEmitter &MCE);
>>> } // end namespace llvm;
>>>
>>> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
>>> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Apr 27
>>> 19:21:31 2009
>>> @@ -129,29 +129,31 @@
>>> // Pass Pipeline Configuration
>>> //
>>> =
>>> =
>>> =
>>> ----------------------------------------------------------------------=
>>> ==//
>>>
>>> -bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
>>> unsigned OptLevel) {
>>> ?// Install an instruction selector.
>>> ?PM.add(createPPCISelDag(*this));
>>> ?return false;
>>> }
>>>
>>> -bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>>> Fast) {
>>> +bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel) {
>>>
>>> ?// Must run branch selection immediately preceding the asm printer.
>>> ?PM.add(createPPCBranchSelectionPass());
>>> ?return false;
>>> }
>>>
>>> -bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool
>>> Fast,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose, raw_ostream
>>> &Out) {
>>> +bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &Out) {
>>> ?assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>> ?if (AsmPrinterCtor)
>>> - ? ?PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
>>> + ? ?PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>>>
>>> ?return false;
>>> }
>>>
>>> -bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool
>>> Fast,
>>> +bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool DumpAsm,
>>> MachineCodeEmitter &MCE) {
>>> ?// The JIT should use the static relocation model in ppc32 mode,
>>> PIC in ppc64.
>>> ?// FIXME: This should be moved to TargetJITInfo!!
>>> @@ -176,20 +178,20 @@
>>> ?if (DumpAsm) {
>>> ? ?assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>> ? ?if (AsmPrinterCtor)
>>> - ? ? ?PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>>> + ? ? ?PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>> ?}
>>>
>>> ?return false;
>>> }
>>>
>>> -bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>> bool Fast,
>>> +bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>> unsigned OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool DumpAsm,
>>> MachineCodeEmitter &MCE) {
>>> ?// Machine code emitter pass for PowerPC.
>>> ?PM.add(createPPCCodeEmitterPass(*this, MCE));
>>> ?if (DumpAsm) {
>>> ? ?assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>> ? ?if (AsmPrinterCtor)
>>> - ? ? ?PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>>> + ? ? ?PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>> ?}
>>>
>>> ?return false;
>>>
>>> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =====================================================================
>>> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
>>> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Mon Apr 27
>>> 19:21:31 2009
>>> @@ -46,7 +46,7 @@
>>> ?// set this functions to ctor pointer at startup time if they are
>>> linked in.
>>> ?typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?PPCTargetMachine &tm,
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool fast, bool
>>> verbose);
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned OptLevel, bool
>>> verbose);
>>> ?static AsmPrinterCtorFn AsmPrinterCtor;
>>>
>>> public:
>>> @@ -76,13 +76,13 @@
>>> ?}
>>>
>>> ?// Pass Pipeline Configuration
>>> - ?virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>> - ?virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>> - ?virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>> + ?virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + ?virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>> OptLevel);
>>> + ?virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool Verbose, raw_ostream &Out);
>>> - ?virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
>>> + ?virtual bool addCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool DumpAsm, MachineCodeEmitter &MCE);
>>> - ?virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
>>> + ?virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
>>> OptLevel,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool DumpAsm, MachineCodeEmitter
>>> &MCE);
>>> ?virtual bool getEnableTailMergeDefault() const;
>>> };
>>>
>>> Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =========================================
> ...
>
> [Message clipped]



From isanbard at gmail.com  Mon Apr 27 19:34:30 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 27 Apr 2009 17:34:30 -0700
Subject: [llvm-commits] [llvm] r70270 - in /llvm/trunk:
	include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/
	lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/
	lib/Target/Alpha/AsmPrinter/ lib
Message-ID: <16e5fdf90904271734p55bec367x2ac177c7687de257@mail.gmail.com>

On Mon, Apr 27, 2009 at 5:30 PM, Evan Cheng <evan.cheng at apple.com> wrote:
> Thanks. How about libLTO?
>
> Also, JIT (calls to TM.addPassesToEmitMachineCode and lli.cpp) has to
> be changed as well.
>
I'll check these out...

-bw


From evan.cheng at apple.com  Mon Apr 27 19:41:23 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Apr 2009 17:41:23 -0700
Subject: [llvm-commits] [llvm] r70270 - in /llvm/trunk:
	include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/	lib/Target/ARM/
	lib/Target/ARM/AsmPrinter/
	lib/Target/Alpha/	lib/Target/Alpha/AsmPrinter/ lib
In-Reply-To: <16e5fdf90904271734s62127641nd68249a7fc89bd5e@mail.gmail.com>
References: <16e5fdf90904271734s62127641nd68249a7fc89bd5e@mail.gmail.com>
Message-ID: <82A0CF48-6036-44BE-BD13-470433643A46@apple.com>


On Apr 27, 2009, at 5:34 PM, Bill Wendling wrote:

> There weren't any llvmgcc changes that I could see. I.e., I couldn't
> see where it was passing -fast...

Look for addPassesToEmitFile in llvm-backend.cpp

Evan

>
>
> -bw
>
> On Mon, Apr 27, 2009 at 5:32 PM, Evan Cheng <evan.cheng at apple.com>  
> wrote:
>> Also llvmgcc changes?
>>
>> Evan
>>
>> On Apr 27, 2009, at 5:30 PM, Evan Cheng wrote:
>>
>>> Thanks. How about libLTO?
>>>
>>> Also, JIT (calls to TM.addPassesToEmitMachineCode and lli.cpp) has  
>>> to
>>> be changed as well.
>>>
>>> Evan
>>>
>>> On Apr 27, 2009, at 5:21 PM, Bill Wendling wrote:
>>>
>>>> Author: void
>>>> Date: Mon Apr 27 19:21:31 2009
>>>> New Revision: 70270
>>>>
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=70270&view=rev
>>>> Log:
>>>> Massive check in. This changes the "-fast" flag to "-O#" in llc. If
>>>> you want to
>>>> use the old behavior, the flag is -O0. This change allows for  
>>>> finer-
>>>> grained
>>>> control over which optimizations are run at different -O levels.
>>>>
>>>> Most of this work was pretty mechanical. The majority of the fixes
>>>> came from
>>>> verifying that a "fast" variable wasn't used anymore. The JIT still
>>>> uses a
>>>> "Fast" flag. I'm not 100% sure if it's necessary to change it
>>>> there...
>>>>
>>>> Modified:
>>>>   llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
>>>>   llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
>>>>   llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>>>>   llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
>>>>   llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>>>>   llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
>>>>   llvm/trunk/include/llvm/Target/TargetMachine.h
>>>>   llvm/trunk/include/llvm/Target/TargetOptions.h
>>>>   llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
>>>>   llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
>>>>   llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>>>>   llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>>>   llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>>>>   llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>>>>   llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>>>>   llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>>>>   llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>>>   llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>>>>   llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>>>>   llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>>>>   llvm/trunk/lib/Target/ARM/ARM.h
>>>>   llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
>>>>   llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
>>>>   llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>>>>   llvm/trunk/lib/Target/Alpha/Alpha.h
>>>>   llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
>>>>   llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
>>>>   llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>>>>   llvm/trunk/lib/Target/CBackend/CBackend.cpp
>>>>   llvm/trunk/lib/Target/CBackend/CTargetMachine.h
>>>>   llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>>>>   llvm/trunk/lib/Target/CellSPU/SPU.h
>>>>   llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
>>>>   llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
>>>>   llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
>>>>   llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
>>>>   llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>>>>   llvm/trunk/lib/Target/IA64/IA64.h
>>>>   llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
>>>>   llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
>>>>   llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
>>>>   llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>>>>   llvm/trunk/lib/Target/Mips/Mips.h
>>>>   llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
>>>>   llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
>>>>   llvm/trunk/lib/Target/PIC16/PIC16.h
>>>>   llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
>>>>   llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
>>>>   llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
>>>>   llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
>>>>   llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>>>>   llvm/trunk/lib/Target/PowerPC/PPC.h
>>>>   llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
>>>>   llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
>>>>   llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
>>>>   llvm/trunk/lib/Target/Sparc/Sparc.h
>>>>   llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
>>>>   llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
>>>>   llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
>>>>   llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
>>>>   llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
>>>>   llvm/trunk/lib/Target/X86/X86.h
>>>>   llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>>>>   llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
>>>>   llvm/trunk/lib/Target/X86/X86TargetMachine.h
>>>>   llvm/trunk/lib/Target/XCore/XCore.h
>>>>   llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
>>>>   llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
>>>>   llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
>>>>   llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
>>>>   llvm/trunk/test/CodeGen/Generic/2006-06-13-
>>>> ComputeMaskedBitsCrash.ll
>>>>   llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
>>>>   llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
>>>>   llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
>>>>   llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
>>>>   llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
>>>>   llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
>>>>   llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
>>>>   llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
>>>>   llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
>>>>   llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
>>>>   llvm/trunk/test/CodeGen/X86/pr1489.ll
>>>>   llvm/trunk/test/CodeGen/X86/volatile.ll
>>>>   llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
>>>>   llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
>>>>   llvm/trunk/test/DebugInfo/deaddebuglabel.ll
>>>>   llvm/trunk/test/DebugInfo/forwardDecl.ll
>>>>   llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
>>>>   llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
>>>>   llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
>>>>   llvm/trunk/tools/llc/llc.cpp
>>>>   llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
>>>>   llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>>>>
>>>> Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
>>>> +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Mon Apr 27  
>>>> 19:21:31
>>>> 2009
>>>> @@ -65,8 +65,8 @@
>>>>    // Necessary for external weak linkage support
>>>>    std::set<const GlobalValue*> ExtWeakSymbols;
>>>>
>>>> -    /// Fast - Generating code via fast instruction selection.
>>>> -    bool Fast;
>>>> +    /// OptLevel - Generating code at a specific optimization  
>>>> level.
>>>> +    unsigned OptLevel;
>>>>  public:
>>>>    /// Output stream on which we're printing assembly code.
>>>>    ///
>>>> @@ -110,8 +110,8 @@
>>>>    bool VerboseAsm;
>>>>
>>>>  protected:
>>>> -    AsmPrinter(raw_ostream &o, TargetMachine &TM,
>>>> -               const TargetAsmInfo *T, bool F, bool V);
>>>> +    explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
>>>> +                        const TargetAsmInfo *T, unsigned OL, bool
>>>> V);
>>>>
>>>>  public:
>>>>    virtual ~AsmPrinter();
>>>>
>>>> Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
>>>> +++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -81,7 +81,7 @@
>>>>  void EndFunction(MachineFunction *MF);
>>>>
>>>>  /// ValidDebugInfo - Return true if V represents valid debug info
>>>> value.
>>>> -  bool ValidDebugInfo(Value *V, bool FastISel);
>>>> +  bool ValidDebugInfo(Value *V, unsigned OptLevel);
>>>>
>>>>  /// RecordSourceLine - Register a source line with debug info.
>>>> Returns a
>>>>  /// unique label ID used to generate a label and provide
>>>> correspondence to
>>>>
>>>> Modified: llvm/trunk/include/llvm/CodeGen/ 
>>>> LinkAllCodegenComponents.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>>>> (original)
>>>> +++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Mon
>>>> Apr 27 19:21:31 2009
>>>> @@ -42,11 +42,11 @@
>>>>      llvm::linkOcamlGC();
>>>>      llvm::linkShadowStackGC();
>>>>
>>>> -      (void) llvm::createBURRListDAGScheduler(NULL, false);
>>>> -      (void) llvm::createTDRRListDAGScheduler(NULL, false);
>>>> -      (void) llvm::createTDListDAGScheduler(NULL, false);
>>>> -      (void) llvm::createFastDAGScheduler(NULL, false);
>>>> -      (void) llvm::createDefaultScheduler(NULL, false);
>>>> +      (void) llvm::createBURRListDAGScheduler(NULL, 3);
>>>> +      (void) llvm::createTDRRListDAGScheduler(NULL, 3);
>>>> +      (void) llvm::createTDListDAGScheduler(NULL, 3);
>>>> +      (void) llvm::createFastDAGScheduler(NULL, 3);
>>>> +      (void) llvm::createDefaultScheduler(NULL, 3);
>>>>
>>>>    }
>>>>  } ForceCodegenLinking; // Force link by creating a global
>>>> definition.
>>>>
>>>> Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original)
>>>> +++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -32,7 +32,7 @@
>>>>
>>>> class RegisterScheduler : public MachinePassRegistryNode {
>>>> public:
>>>> -  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)
>>>> (SelectionDAGISel*, bool);
>>>> +  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)
>>>> (SelectionDAGISel*, unsigned);
>>>>
>>>>  static MachinePassRegistry Registry;
>>>>
>>>> @@ -64,27 +64,27 @@
>>>> /// createBURRListDAGScheduler - This creates a bottom up register
>>>> usage
>>>> /// reduction list scheduler.
>>>> ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel  
>>>> *IS,
>>>> -                                               bool Fast);
>>>> +                                               unsigned OptLevel);
>>>>
>>>> /// createTDRRListDAGScheduler - This creates a top down register
>>>> usage
>>>> /// reduction list scheduler.
>>>> ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel  
>>>> *IS,
>>>> -                                               bool Fast);
>>>> +                                               unsigned OptLevel);
>>>>
>>>> /// createTDListDAGScheduler - This creates a top-down list
>>>> scheduler with
>>>> /// a hazard recognizer.
>>>> ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
>>>> -                                             bool Fast);
>>>> +                                             unsigned OptLevel);
>>>>
>>>> /// createFastDAGScheduler - This creates a "fast" scheduler.
>>>> ///
>>>> ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
>>>> -                                           bool Fast);
>>>> +                                           unsigned OptLevel);
>>>>
>>>> /// createDefaultScheduler - This creates an instruction scheduler
>>>> appropriate
>>>> /// for the target.
>>>> ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
>>>> -                                           bool Fast);
>>>> +                                           unsigned OptLevel);
>>>>
>>>> } // end namespace llvm
>>>>
>>>>
>>>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
>>>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -202,7 +202,7 @@
>>>>  /// certain types of nodes together, or eliminating superfluous
>>>> nodes.  The
>>>>  /// Level argument controls whether Combine is allowed to produce
>>>> nodes and
>>>>  /// types that are illegal on the target.
>>>> -  void Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast);
>>>> +  void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned
>>>> OptLevel);
>>>>
>>>>  /// LegalizeTypes - This transforms the SelectionDAG into a
>>>> SelectionDAG that
>>>>  /// only uses types natively supported by the target.  Returns
>>>> "true" if it
>>>> @@ -218,7 +218,7 @@
>>>>  ///
>>>>  /// Note that this is an involved process that may invalidate
>>>> pointers into
>>>>  /// the graph.
>>>> -  void Legalize(bool TypesNeedLegalizing, bool Fast);
>>>> +  void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
>>>>
>>>>  /// RemoveDeadNodes - This method deletes all unreachable nodes in
>>>> the
>>>>  /// SelectionDAG.
>>>>
>>>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
>>>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -51,10 +51,10 @@
>>>>  MachineBasicBlock *BB;
>>>>  AliasAnalysis *AA;
>>>>  GCFunctionInfo *GFI;
>>>> -  bool Fast;
>>>> +  unsigned OptLevel;
>>>>  static char ID;
>>>>
>>>> -  explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
>>>> +  explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
>>>>  virtual ~SelectionDAGISel();
>>>>
>>>>  TargetLowering &getTargetLowering() { return TLI; }
>>>>
>>>> Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
>>>> +++ llvm/trunk/include/llvm/Target/TargetMachine.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -213,7 +213,7 @@
>>>>  virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
>>>>                                               raw_ostream &,
>>>>                                               CodeGenFileType,
>>>> -                                               bool /*Fast*/) {
>>>> +                                               unsigned /*  
>>>> OptLevel
>>>> */) {
>>>>    return FileModel::None;
>>>>  }
>>>>
>>>> @@ -222,7 +222,8 @@
>>>>  /// used to finish up adding passes to emit the file, if  
>>>> necessary.
>>>>  ///
>>>>  virtual bool addPassesToEmitFileFinish(PassManagerBase &,
>>>> -                                         MachineCodeEmitter *,
>>>> bool /*Fast*/) {
>>>> +                                         MachineCodeEmitter *,
>>>> +                                         unsigned /* OptLevel  
>>>> */) {
>>>>    return true;
>>>>  }
>>>>
>>>> @@ -234,7 +235,7 @@
>>>>  ///
>>>>  virtual bool addPassesToEmitMachineCode(PassManagerBase &,
>>>>                                          MachineCodeEmitter &,
>>>> -                                          bool /*Fast*/) {
>>>> +                                          unsigned /* OptLevel  
>>>> */) {
>>>>    return true;
>>>>  }
>>>>
>>>> @@ -243,7 +244,8 @@
>>>>  /// use this.
>>>>  virtual bool WantsWholeFile() const { return false; }
>>>>  virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream  
>>>> &,
>>>> -                                        CodeGenFileType, bool /
>>>> *Fast*/) {
>>>> +                                        CodeGenFileType,
>>>> +                                        unsigned /* OptLevel */) {
>>>>    return true;
>>>>  }
>>>> };
>>>> @@ -258,16 +260,16 @@
>>>>  /// addCommonCodeGenPasses - Add standard LLVM codegen passes used
>>>> for
>>>>  /// both emitting to assembly files or machine code output.
>>>>  ///
>>>> -  bool addCommonCodeGenPasses(PassManagerBase &, bool /*Fast*/);
>>>> +  bool addCommonCodeGenPasses(PassManagerBase &, unsigned /*
>>>> OptLevel */);
>>>>
>>>> public:
>>>>
>>>>  /// addPassesToEmitFile - Add passes to the specified pass manager
>>>> to get the
>>>>  /// specified file emitted.  Typically this will involve several
>>>> steps of code
>>>> -  /// generation.  If Fast is set to true, the code generator
>>>> should emit code
>>>> -  /// as fast as possible, though the generated code may be less
>>>> efficient.
>>>> -  /// This method should return FileModel::Error if emission of
>>>> this file type
>>>> -  /// is not supported.
>>>> +  /// generation.  If OptLevel is 0, the code generator should  
>>>> emit
>>>> code as fast
>>>> +  /// as possible, though the generated code may be less
>>>> efficient.  This method
>>>> +  /// should return FileModel::Error if emission of this file type
>>>> is not
>>>> +  /// supported.
>>>>  ///
>>>>  /// The default implementation of this method adds components from
>>>> the
>>>>  /// LLVM retargetable code generator, invoking the methods below
>>>> to get
>>>> @@ -276,14 +278,15 @@
>>>>  virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
>>>>                                               raw_ostream &Out,
>>>>                                               CodeGenFileType
>>>> FileType,
>>>> -                                               bool Fast);
>>>> +                                               unsigned OptLevel);
>>>>
>>>>  /// addPassesToEmitFileFinish - If the passes to emit the
>>>> specified file had
>>>>  /// to be split up (e.g., to add an object writer pass), this
>>>> method can be
>>>>  /// used to finish up adding passes to emit the file, if  
>>>> necessary.
>>>>  ///
>>>>  virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
>>>> -                                         MachineCodeEmitter *MCE,
>>>> bool Fast);
>>>> +                                         MachineCodeEmitter *MCE,
>>>> +                                         unsigned OptLevel);
>>>>
>>>>  /// addPassesToEmitMachineCode - Add passes to the specified pass
>>>> manager to
>>>>  /// get machine code emitted.  This uses a MachineCodeEmitter
>>>> object to handle
>>>> @@ -292,21 +295,22 @@
>>>>  /// not supported.
>>>>  ///
>>>>  virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
>>>> -                                          MachineCodeEmitter &MCE,
>>>> bool Fast);
>>>> +                                          MachineCodeEmitter &MCE,
>>>> +                                          unsigned OptLevel);
>>>>
>>>>  /// Target-Independent Code Generator Pass Configuration Options.
>>>>
>>>>  /// addInstSelector - This method should add any "last minute"
>>>> LLVM->LLVM
>>>>  /// passes, then install an instruction selector pass, which
>>>> converts from
>>>>  /// LLVM code to machine instructions.
>>>> -  virtual bool addInstSelector(PassManagerBase &, bool /*Fast*/) {
>>>> +  virtual bool addInstSelector(PassManagerBase &, unsigned /*
>>>> OptLevel */) {
>>>>    return true;
>>>>  }
>>>>
>>>>  /// addPreRegAllocPasses - This method may be implemented by
>>>> targets that want
>>>>  /// to run passes immediately before register allocation. This
>>>> should return
>>>>  /// true if -print-machineinstrs should print after these passes.
>>>> -  virtual bool addPreRegAlloc(PassManagerBase &, bool /*Fast*/) {
>>>> +  virtual bool addPreRegAlloc(PassManagerBase &, unsigned /*
>>>> OptLevel */) {
>>>>    return false;
>>>>  }
>>>>
>>>> @@ -314,14 +318,14 @@
>>>>  /// want to run passes after register allocation but before  
>>>> prolog-
>>>> epilog
>>>>  /// insertion.  This should return true if -print-machineinstrs
>>>> should print
>>>>  /// after these passes.
>>>> -  virtual bool addPostRegAlloc(PassManagerBase &, bool /*Fast*/) {
>>>> +  virtual bool addPostRegAlloc(PassManagerBase &, unsigned /*
>>>> OptLevel */) {
>>>>    return false;
>>>>  }
>>>>
>>>>  /// addPreEmitPass - This pass may be implemented by targets that
>>>> want to run
>>>>  /// passes immediately before machine code is emitted.  This
>>>> should return
>>>>  /// true if -print-machineinstrs should print out the code after
>>>> the passes.
>>>> -  virtual bool addPreEmitPass(PassManagerBase &, bool /*Fast*/) {
>>>> +  virtual bool addPreEmitPass(PassManagerBase &, unsigned /*
>>>> OptLevel */) {
>>>>    return false;
>>>>  }
>>>>
>>>> @@ -329,7 +333,7 @@
>>>>  /// addAssemblyEmitter - This pass should be overridden by the
>>>> target to add
>>>>  /// the asmprinter, if asm emission is supported.  If this is not
>>>> supported,
>>>>  /// 'true' should be returned.
>>>> -  virtual bool addAssemblyEmitter(PassManagerBase &, bool / 
>>>> *Fast*/,
>>>> +  virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /*
>>>> OptLevel */,
>>>>                                  bool /* VerboseAsmDefault */,
>>>> raw_ostream &) {
>>>>    return true;
>>>>  }
>>>> @@ -337,7 +341,7 @@
>>>>  /// addCodeEmitter - This pass should be overridden by the target
>>>> to add a
>>>>  /// code emitter, if supported.  If this is not supported, 'true'
>>>> should be
>>>>  /// returned. If DumpAsm is true, the generated assembly is
>>>> printed to cerr.
>>>> -  virtual bool addCodeEmitter(PassManagerBase &, bool /*Fast*/,
>>>> +  virtual bool addCodeEmitter(PassManagerBase &, unsigned /*
>>>> OptLevel */,
>>>>                              bool /*DumpAsm*/, MachineCodeEmitter
>>>> &) {
>>>>    return true;
>>>>  }
>>>> @@ -346,7 +350,7 @@
>>>>  /// a code emitter (without setting flags), if supported.  If this
>>>> is not
>>>>  /// supported, 'true' should be returned.  If DumpAsm is true, the
>>>> generated
>>>>  /// assembly is printed to cerr.
>>>> -  virtual bool addSimpleCodeEmitter(PassManagerBase &, bool /
>>>> *Fast*/,
>>>> +  virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /*
>>>> OptLevel */,
>>>>                                    bool /*DumpAsm*/,
>>>> MachineCodeEmitter &) {
>>>>    return true;
>>>>  }
>>>>
>>>> Modified: llvm/trunk/include/llvm/Target/TargetOptions.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/include/llvm/Target/TargetOptions.h (original)
>>>> +++ llvm/trunk/include/llvm/Target/TargetOptions.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -108,7 +108,7 @@
>>>>  /// generated.
>>>>  extern bool DisableJumpTables;
>>>>
>>>> -  /// FastISel - This flag enables fast-path instruction selection
>>>> +  /// EnableFastISel - This flag enables fast-path instruction
>>>> selection
>>>>  /// which trades away generated code quality in favor of reducing
>>>>  /// compile time.
>>>>  extern bool EnableFastISel;
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
>>>> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -42,8 +42,8 @@
>>>>
>>>> char AsmPrinter::ID = 0;
>>>> AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
>>>> -                       const TargetAsmInfo *T, bool F, bool VDef)
>>>> -  : MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o),
>>>> +                       const TargetAsmInfo *T, unsigned OL, bool
>>>> VDef)
>>>> +  : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL),  
>>>> O(o),
>>>>    TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
>>>>    IsInTextSection(false)
>>>> {
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
>>>> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -3351,7 +3351,7 @@
>>>>  }
>>>>
>>>>  /// ValidDebugInfo - Return true if V represents valid debug info
>>>> value.
>>>> -  bool ValidDebugInfo(Value *V, bool FastISel) {
>>>> +  bool ValidDebugInfo(Value *V, unsigned OptLevel) {
>>>>    if (!V)
>>>>      return false;
>>>>
>>>> @@ -3393,7 +3393,7 @@
>>>>    case DW_TAG_lexical_block:
>>>>      /// FIXME. This interfers with the qualitfy of generated code
>>>> when
>>>>      /// during optimization.
>>>> -      if (FastISel == false)
>>>> +      if (OptLevel != 0)
>>>>        return false;
>>>>    default:
>>>>      break;
>>>> @@ -4730,8 +4730,8 @@
>>>> }
>>>>
>>>> /// ValidDebugInfo - Return true if V represents valid debug info
>>>> value.
>>>> -bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) {
>>>> -  return DD && DD->ValidDebugInfo(V, FastISel);
>>>> +bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
>>>> +  return DD && DD->ValidDebugInfo(V, OptLevel);
>>>> }
>>>>
>>>> /// RecordSourceLine - Records location information and associates
>>>> it with a
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
>>>> +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Mon Apr 27  
>>>> 19:21:31
>>>> 2009
>>>> @@ -55,9 +55,9 @@
>>>> LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
>>>>                                       raw_ostream &Out,
>>>>                                       CodeGenFileType FileType,
>>>> -                                       bool Fast) {
>>>> +                                       unsigned OptLevel) {
>>>>  // Add common CodeGen passes.
>>>> -  if (addCommonCodeGenPasses(PM, Fast))
>>>> +  if (addCommonCodeGenPasses(PM, OptLevel))
>>>>    return FileModel::Error;
>>>>
>>>>  // Fold redundant debug labels.
>>>> @@ -66,17 +66,17 @@
>>>>  if (PrintMachineCode)
>>>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>>>
>>>> -  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
>>>> +  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
>>>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>>>
>>>> -  if (!Fast)
>>>> +  if (OptLevel != 0)
>>>>    PM.add(createLoopAlignerPass());
>>>>
>>>>  switch (FileType) {
>>>>  default:
>>>>    break;
>>>>  case TargetMachine::AssemblyFile:
>>>> -    if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(),  
>>>> Out))
>>>> +    if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(),
>>>> Out))
>>>>      return FileModel::Error;
>>>>    return FileModel::AsmFile;
>>>>  case TargetMachine::ObjectFile:
>>>> @@ -94,9 +94,9 @@
>>>> /// finish up adding passes to emit the file, if necessary.
>>>> bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase
>>>> &PM,
>>>>                                                  MachineCodeEmitter
>>>> *MCE,
>>>> -                                                  bool Fast) {
>>>> +                                                  unsigned
>>>> OptLevel) {
>>>>  if (MCE)
>>>> -    addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
>>>> +    addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
>>>>
>>>>  PM.add(createGCInfoDeleter());
>>>>
>>>> @@ -114,15 +114,15 @@
>>>> ///
>>>> bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase
>>>> &PM,
>>>>
>>>> MachineCodeEmitter &MCE,
>>>> -                                                   bool Fast) {
>>>> +                                                   unsigned
>>>> OptLevel) {
>>>>  // Add common CodeGen passes.
>>>> -  if (addCommonCodeGenPasses(PM, Fast))
>>>> +  if (addCommonCodeGenPasses(PM, OptLevel))
>>>>    return true;
>>>>
>>>> -  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
>>>> +  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
>>>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>>>
>>>> -  addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
>>>> +  addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
>>>>
>>>>  PM.add(createGCInfoDeleter());
>>>>
>>>> @@ -135,11 +135,12 @@
>>>> /// addCommonCodeGenPasses - Add standard LLVM codegen passes used
>>>> for
>>>> /// both emitting to assembly files or machine code output.
>>>> ///
>>>> -bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase  
>>>> &PM,
>>>> bool Fast) {
>>>> +bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase  
>>>> &PM,
>>>> +                                               unsigned  
>>>> OptLevel) {
>>>>  // Standard LLVM-Level Passes.
>>>>
>>>>  // Run loop strength reduction before anything else.
>>>> -  if (!Fast) {
>>>> +  if (OptLevel != 0) {
>>>>    PM.add(createLoopStrengthReducePass(getTargetLowering()));
>>>>    if (PrintLSR)
>>>>      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n",
>>>> &errs()));
>>>> @@ -153,7 +154,7 @@
>>>>  // Make sure that no unreachable blocks are instruction selected.
>>>>  PM.add(createUnreachableBlockEliminationPass());
>>>>
>>>> -  if (!Fast)
>>>> +  if (OptLevel != 0)
>>>>    PM.add(createCodeGenPreparePass(getTargetLowering()));
>>>>
>>>>  PM.add(createStackProtectorPass(getTargetLowering()));
>>>> @@ -167,38 +168,38 @@
>>>>
>>>>  // Enable FastISel with -fast, but allow that to be overridden.
>>>>  if (EnableFastISelOption == cl::BOU_TRUE ||
>>>> -      (Fast && EnableFastISelOption != cl::BOU_FALSE))
>>>> +      (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
>>>>    EnableFastISel = true;
>>>>
>>>>  // Ask the target for an isel.
>>>> -  if (addInstSelector(PM, Fast))
>>>> +  if (addInstSelector(PM, OptLevel))
>>>>    return true;
>>>>
>>>>  // Print the instruction selected machine code...
>>>>  if (PrintMachineCode)
>>>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>>>
>>>> -  if (!Fast) {
>>>> +  if (OptLevel != 0) {
>>>>    PM.add(createMachineLICMPass());
>>>>    PM.add(createMachineSinkingPass());
>>>>  }
>>>>
>>>>  // Run pre-ra passes.
>>>> -  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
>>>> +  if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
>>>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>>>
>>>>  // Perform register allocation.
>>>>  PM.add(createRegisterAllocator());
>>>>
>>>>  // Perform stack slot coloring.
>>>> -  if (!Fast)
>>>> +  if (OptLevel != 0)
>>>>    PM.add(createStackSlotColoringPass());
>>>>
>>>>  if (PrintMachineCode)  // Print the register-allocated code
>>>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>>>
>>>>  // Run post-ra passes.
>>>> -  if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
>>>> +  if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
>>>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>>>
>>>>  if (PrintMachineCode)
>>>> @@ -216,7 +217,7 @@
>>>>    PM.add(createMachineFunctionPrinterPass(cerr));
>>>>
>>>>  // Second pass scheduler.
>>>> -  if (!Fast && !DisablePostRAScheduler) {
>>>> +  if (OptLevel != 0 && !DisablePostRAScheduler) {
>>>>    PM.add(createPostRAScheduler());
>>>>
>>>>    if (PrintMachineCode)
>>>> @@ -224,7 +225,7 @@
>>>>  }
>>>>
>>>>  // Branch folding must be run after regalloc and prolog/epilog
>>>> insertion.
>>>> -  if (!Fast)
>>>> +  if (OptLevel != 0)
>>>>    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
>>>>
>>>>  if (PrintMachineCode)
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -57,9 +57,9 @@
>>>>    SelectionDAG &DAG;
>>>>    const TargetLowering &TLI;
>>>>    CombineLevel Level;
>>>> +    unsigned OptLevel;
>>>>    bool LegalOperations;
>>>>    bool LegalTypes;
>>>> -    bool Fast;
>>>>
>>>>    // Worklist of all of the nodes that need to be simplified.
>>>>    std::vector<SDNode*> WorkList;
>>>> @@ -254,13 +254,13 @@
>>>>    }
>>>>
>>>> public:
>>>> -    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
>>>> +    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
>>>>      : DAG(D),
>>>>        TLI(D.getTargetLoweringInfo()),
>>>>        Level(Unrestricted),
>>>> +        OptLevel(OL),
>>>>        LegalOperations(false),
>>>>        LegalTypes(false),
>>>> -        Fast(fast),
>>>>        AA(A) {}
>>>>
>>>>    /// Run - runs the dag combiner on all nodes in the work list
>>>> @@ -4784,7 +4784,7 @@
>>>>  SDValue Ptr   = LD->getBasePtr();
>>>>
>>>>  // Try to infer better alignment information than the load already
>>>> has.
>>>> -  if (!Fast && LD->isUnindexed()) {
>>>> +  if (OptLevel != 0 && LD->isUnindexed()) {
>>>>    if (unsigned Align = InferAlignment(Ptr, DAG)) {
>>>>      if (Align > LD->getAlignment())
>>>>        return DAG.getExtLoad(LD->getExtensionType(), N-
>>>>> getDebugLoc(),
>>>> @@ -4904,7 +4904,7 @@
>>>>  SDValue Ptr   = ST->getBasePtr();
>>>>
>>>>  // Try to infer better alignment information than the store
>>>> already has.
>>>> -  if (!Fast && ST->isUnindexed()) {
>>>> +  if (OptLevel != 0 && ST->isUnindexed()) {
>>>>    if (unsigned Align = InferAlignment(Ptr, DAG)) {
>>>>      if (Align > ST->getAlignment())
>>>>        return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
>>>> @@ -6084,8 +6084,9 @@
>>>>
>>>> // SelectionDAG::Combine - This is the entry point for the file.
>>>> //
>>>> -void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
>>>> bool Fast) {
>>>> +void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
>>>> +                           unsigned OptLevel) {
>>>>  /// run - This is the main entry point to this class.
>>>>  ///
>>>> -  DAGCombiner(*this, AA, Fast).Run(Level);
>>>> +  DAGCombiner(*this, AA, OptLevel).Run(Level);
>>>> }
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -327,7 +327,7 @@
>>>>  default: break;
>>>>  case Intrinsic::dbg_stoppoint: {
>>>>    DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
>>>> -    if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) {
>>>> +    if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
>>>>      DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
>>>>      std::string Dir, FN;
>>>>      unsigned SrcFile = DW- 
>>>> >getOrCreateSourceID(CU.getDirectory(Dir),
>>>> @@ -344,7 +344,7 @@
>>>>  }
>>>>  case Intrinsic::dbg_region_start: {
>>>>    DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
>>>> -    if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) {
>>>> +    if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
>>>>      unsigned ID =
>>>>        DW->RecordRegionStart(cast<GlobalVariable>(RSI-
>>>>> getContext()));
>>>>      const TargetInstrDesc &II =  
>>>> TII.get(TargetInstrInfo::DBG_LABEL);
>>>> @@ -354,7 +354,7 @@
>>>>  }
>>>>  case Intrinsic::dbg_region_end: {
>>>>    DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
>>>> -    if (DW && DW->ValidDebugInfo(REI->getContext(), true)) {
>>>> +    if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
>>>>     unsigned ID = 0;
>>>>     DISubprogram Subprogram(cast<GlobalVariable>(REI- 
>>>> >getContext()));
>>>>     if (!Subprogram.isNull() && !
>>>> Subprogram.describes(MF.getFunction())) {
>>>> @@ -380,7 +380,7 @@
>>>>    DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
>>>>    Value *SP = FSI->getSubprogram();
>>>>
>>>> -    if (DW->ValidDebugInfo(SP, true)) {
>>>> +    if (DW->ValidDebugInfo(SP, 0)) {
>>>>      // llvm.dbg.func.start implicitly defines a dbg_stoppoint
>>>> which is what
>>>>      // (most?) gdb expects.
>>>>      DebugLoc PrevLoc = DL;
>>>> @@ -425,7 +425,7 @@
>>>>  case Intrinsic::dbg_declare: {
>>>>    DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
>>>>    Value *Variable = DI->getVariable();
>>>> -    if (DW && DW->ValidDebugInfo(Variable, true)) {
>>>> +    if (DW && DW->ValidDebugInfo(Variable, 0)) {
>>>>      // Determine the address of the declared object.
>>>>      Value *Address = DI->getAddress();
>>>>      if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -55,8 +55,8 @@
>>>> class VISIBILITY_HIDDEN SelectionDAGLegalize {
>>>>  TargetLowering &TLI;
>>>>  SelectionDAG &DAG;
>>>> +  unsigned OptLevel;
>>>>  bool TypesNeedLegalizing;
>>>> -  bool Fast;
>>>>
>>>>  // Libcall insertion helpers.
>>>>
>>>> @@ -139,7 +139,7 @@
>>>>
>>>> public:
>>>>  explicit SelectionDAGLegalize(SelectionDAG &DAG, bool
>>>> TypesNeedLegalizing,
>>>> -                                bool fast);
>>>> +                                unsigned ol);
>>>>
>>>>  /// getTypeAction - Return how we should legalize values of this
>>>> type, either
>>>>  /// it is already legal or we need to expand it into multiple
>>>> registers of
>>>> @@ -345,9 +345,9 @@
>>>> }
>>>>
>>>> SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
>>>> -                                           bool types, bool fast)
>>>> -  : TLI(dag.getTargetLoweringInfo()), DAG(dag),
>>>> TypesNeedLegalizing(types),
>>>> -    Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
>>>> +                                           bool types, unsigned  
>>>> ol)
>>>> +  : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
>>>> +    TypesNeedLegalizing(types),
>>>> ValueTypeActions(TLI.getValueTypeActions()) {
>>>>  assert(MVT::LAST_VALUETYPE <= 32 &&
>>>>         "Too many value types for ValueTypeActions to hold!");
>>>> }
>>>> @@ -1271,7 +1271,7 @@
>>>>        unsigned Line = DSP->getLine();
>>>>        unsigned Col = DSP->getColumn();
>>>>
>>>> -        if (Fast) {
>>>> +        if (OptLevel == 0) {
>>>>          // A bit self-referential to have DebugLoc on Debug_Loc
>>>> nodes, but it
>>>>          // won't hurt anything.
>>>>          if (useDEBUG_LOC) {
>>>> @@ -8566,9 +8566,9 @@
>>>>
>>>> // SelectionDAG::Legalize - This is the entry point for the file.
>>>> //
>>>> -void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
>>>> +void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned
>>>> OptLevel) {
>>>>  /// run - This is the main entry point to this class.
>>>>  ///
>>>> -  SelectionDAGLegalize(*this, TypesNeedLegalizing,
>>>> Fast).LegalizeDAG();
>>>> +  SelectionDAGLegalize(*this, TypesNeedLegalizing,
>>>> OptLevel).LegalizeDAG();
>>>> }
>>>>
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>>>> (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Mon Apr
>>>> 27 19:21:31 2009
>>>> @@ -630,6 +630,6 @@
>>>> //
>>>> =
>>>> =
>>>> =
>>>> ----------------------------------------------------------------------=
>>>> ==//
>>>>
>>>> llvm::ScheduleDAGSDNodes *
>>>> -llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
>>>> +llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>>>  return new ScheduleDAGFast(*IS->MF);
>>>> }
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>>>> (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon Apr
>>>> 27 19:21:31 2009
>>>> @@ -261,7 +261,7 @@
>>>> /// new hazard recognizer. This scheduler takes ownership of the
>>>> hazard
>>>> /// recognizer and deletes it when done.
>>>> ScheduleDAGSDNodes *
>>>> -llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) {
>>>> +llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>>>  return new ScheduleDAGList(*IS->MF,
>>>>                             new LatencyPriorityQueue(),
>>>>                             IS->CreateTargetHazardRecognizer());
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>>> (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon
>>>> Apr 27 19:21:31 2009
>>>> @@ -1505,7 +1505,7 @@
>>>> //
>>>> =
>>>> =
>>>> =
>>>> ----------------------------------------------------------------------=
>>>> ==//
>>>>
>>>> llvm::ScheduleDAGSDNodes *
>>>> -llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
>>>> +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>>>  const TargetMachine &TM = IS->TM;
>>>>  const TargetInstrInfo *TII = TM.getInstrInfo();
>>>>  const TargetRegisterInfo *TRI = TM.getRegisterInfo();
>>>> @@ -1519,7 +1519,7 @@
>>>> }
>>>>
>>>> llvm::ScheduleDAGSDNodes *
>>>> -llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
>>>> +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>>>>  const TargetMachine &TM = IS->TM;
>>>>  const TargetInstrInfo *TII = TM.getInstrInfo();
>>>>  const TargetRegisterInfo *TRI = TM.getRegisterInfo();
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>>>> (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon
>>>> Apr 27 19:21:31 2009
>>>> @@ -3910,9 +3910,9 @@
>>>>  case Intrinsic::dbg_stoppoint: {
>>>>    DwarfWriter *DW = DAG.getDwarfWriter();
>>>>    DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
>>>> -    if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
>>>> +    if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
>>>>      MachineFunction &MF = DAG.getMachineFunction();
>>>> -      if (Fast)
>>>> +      if (OptLevel == 0)
>>>>        DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
>>>>                                        SPI.getLine(),
>>>>                                        SPI.getColumn(),
>>>> @@ -3930,7 +3930,8 @@
>>>>  case Intrinsic::dbg_region_start: {
>>>>    DwarfWriter *DW = DAG.getDwarfWriter();
>>>>    DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
>>>> -    if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
>>>> +
>>>> +    if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) {
>>>>      unsigned LabelID =
>>>>        DW- 
>>>> >RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
>>>>      DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
>>>> @@ -3942,8 +3943,8 @@
>>>>  case Intrinsic::dbg_region_end: {
>>>>    DwarfWriter *DW = DAG.getDwarfWriter();
>>>>    DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
>>>> -    if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
>>>>
>>>> +    if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) {
>>>>      MachineFunction &MF = DAG.getMachineFunction();
>>>>      DISubprogram  
>>>> Subprogram(cast<GlobalVariable>(REI.getContext()));
>>>>      std::string SPName;
>>>> @@ -3952,7 +3953,7 @@
>>>>          && strcmp(SPName.c_str(), MF.getFunction()-
>>>>> getNameStart())) {
>>>>          // This is end of inlined function. Debugging information
>>>> for
>>>>          // inlined function is not handled yet (only supported by
>>>> FastISel).
>>>> -        if (Fast) {
>>>> +        if (OptLevel == 0) {
>>>>          unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
>>>>          if (ID != 0)
>>>>            // Returned ID is 0 if this is unbalanced "end of  
>>>> inlined
>>>> @@ -3978,9 +3979,9 @@
>>>>    if (!DW) return 0;
>>>>    DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
>>>>    Value *SP = FSI.getSubprogram();
>>>> -    if (SP && DW->ValidDebugInfo(SP, Fast)) {
>>>> -        MachineFunction &MF = DAG.getMachineFunction();
>>>> -      if (Fast) {
>>>> +    if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
>>>> +      MachineFunction &MF = DAG.getMachineFunction();
>>>> +      if (OptLevel == 0) {
>>>>        // llvm.dbg.func.start implicitly defines a dbg_stoppoint
>>>> which is what
>>>>        // (most?) gdb expects.
>>>>        DebugLoc PrevLoc = CurDebugLoc;
>>>> @@ -4051,11 +4052,11 @@
>>>>    return 0;
>>>>  }
>>>>  case Intrinsic::dbg_declare: {
>>>> -    if (Fast) {
>>>> +    if (OptLevel == 0) {
>>>>      DwarfWriter *DW = DAG.getDwarfWriter();
>>>>      DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
>>>>      Value *Variable = DI.getVariable();
>>>> -      if (DW && DW->ValidDebugInfo(Variable, Fast))
>>>> +      if (DW && DW->ValidDebugInfo(Variable, OptLevel))
>>>>        DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other,
>>>> getRoot(),
>>>>                                getValue(DI.getAddress()),
>>>> getValue(Variable)));
>>>>    } else {
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>>>> (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Mon Apr
>>>> 27 19:21:31 2009
>>>> @@ -355,17 +355,17 @@
>>>>  ///
>>>>  FunctionLoweringInfo &FuncInfo;
>>>>
>>>> -  /// Fast - We are in -fast mode.
>>>> +  /// OptLevel - What optimization level we're generating code  
>>>> for.
>>>>  ///
>>>> -  bool Fast;
>>>> +  unsigned OptLevel;
>>>>
>>>>  /// GFI - Garbage collection metadata for the function.
>>>>  GCFunctionInfo *GFI;
>>>>
>>>>  SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
>>>> -                       FunctionLoweringInfo &funcinfo, bool fast)
>>>> +                       FunctionLoweringInfo &funcinfo, unsigned  
>>>> ol)
>>>>    : CurDebugLoc(DebugLoc::getUnknownLoc()),
>>>> -      TLI(tli), DAG(dag), FuncInfo(funcinfo), Fast(fast) {
>>>> +      TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
>>>>  }
>>>>
>>>>  void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>>>> (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon  
>>>> Apr
>>>> 27 19:21:31 2009
>>>> @@ -136,16 +136,16 @@
>>>>  /// createDefaultScheduler - This creates an instruction scheduler
>>>> appropriate
>>>>  /// for the target.
>>>>  ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
>>>> -                                             bool Fast) {
>>>> +                                             unsigned OptLevel) {
>>>>    const TargetLowering &TLI = IS->getTargetLowering();
>>>>
>>>> -    if (Fast)
>>>> -      return createFastDAGScheduler(IS, Fast);
>>>> +    if (OptLevel == 0)
>>>> +      return createFastDAGScheduler(IS, OptLevel);
>>>>    if (TLI.getSchedulingPreference() ==
>>>> TargetLowering::SchedulingForLatency)
>>>> -      return createTDListDAGScheduler(IS, Fast);
>>>> +      return createTDListDAGScheduler(IS, OptLevel);
>>>>    assert(TLI.getSchedulingPreference() ==
>>>>         TargetLowering::SchedulingForRegPressure && "Unknown sched
>>>> type!");
>>>> -    return createBURRListDAGScheduler(IS, Fast);
>>>> +    return createBURRListDAGScheduler(IS, OptLevel);
>>>>  }
>>>> }
>>>>
>>>> @@ -262,13 +262,13 @@
>>>> // SelectionDAGISel code
>>>> //
>>>> =
>>>> =
>>>> =
>>>> ----------------------------------------------------------------------=
>>>> ==//
>>>>
>>>> -SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
>>>> +SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned  
>>>> OL) :
>>>>  FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
>>>>  FuncInfo(new FunctionLoweringInfo(TLI)),
>>>>  CurDAG(new SelectionDAG(TLI, *FuncInfo)),
>>>> -  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)),
>>>> +  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)),
>>>>  GFI(),
>>>> -  Fast(fast),
>>>> +  OptLevel(OL),
>>>>  DAGSize(0)
>>>> {}
>>>>
>>>> @@ -576,9 +576,9 @@
>>>>  // Run the DAG combiner in pre-legalize mode.
>>>>  if (TimePassesIsEnabled) {
>>>>    NamedRegionTimer T("DAG Combining 1", GroupName);
>>>> -    CurDAG->Combine(Unrestricted, *AA, Fast);
>>>> +    CurDAG->Combine(Unrestricted, *AA, OptLevel);
>>>>  } else {
>>>> -    CurDAG->Combine(Unrestricted, *AA, Fast);
>>>> +    CurDAG->Combine(Unrestricted, *AA, OptLevel);
>>>>  }
>>>>
>>>>  DOUT << "Optimized lowered selection DAG:\n";
>>>> @@ -608,9 +608,9 @@
>>>>      // Run the DAG combiner in post-type-legalize mode.
>>>>      if (TimePassesIsEnabled) {
>>>>        NamedRegionTimer T("DAG Combining after legalize types",
>>>> GroupName);
>>>> -        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
>>>> +        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
>>>>      } else {
>>>> -        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
>>>> +        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
>>>>      }
>>>>
>>>>      DOUT << "Optimized type-legalized selection DAG:\n";
>>>> @@ -622,9 +622,9 @@
>>>>
>>>>  if (TimePassesIsEnabled) {
>>>>    NamedRegionTimer T("DAG Legalization", GroupName);
>>>> -    CurDAG->Legalize(DisableLegalizeTypes, Fast);
>>>> +    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
>>>>  } else {
>>>> -    CurDAG->Legalize(DisableLegalizeTypes, Fast);
>>>> +    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
>>>>  }
>>>>
>>>>  DOUT << "Legalized selection DAG:\n";
>>>> @@ -635,9 +635,9 @@
>>>>  // Run the DAG combiner in post-legalize mode.
>>>>  if (TimePassesIsEnabled) {
>>>>    NamedRegionTimer T("DAG Combining 2", GroupName);
>>>> -    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
>>>> +    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
>>>>  } else {
>>>> -    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
>>>> +    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
>>>>  }
>>>>
>>>>  DOUT << "Optimized legalized selection DAG:\n";
>>>> @@ -645,7 +645,7 @@
>>>>
>>>>  if (ViewISelDAGs) CurDAG->viewGraph("isel input for " +  
>>>> BlockName);
>>>>
>>>> -  if (!Fast)
>>>> +  if (OptLevel != 0)
>>>>    ComputeLiveOutVRegInfo();
>>>>
>>>>  // Third, instruction select all of the operations to machine
>>>> code, adding the
>>>> @@ -1082,7 +1082,7 @@
>>>>    RegisterScheduler::setDefault(Ctor);
>>>>  }
>>>>
>>>> -  return Ctor(this, Fast);
>>>> +  return Ctor(this, OptLevel);
>>>> }
>>>>
>>>> ScheduleHazardRecognizer
>>>> *SelectionDAGISel::CreateTargetHazardRecognizer() {
>>>>
>>>> Modified: llvm/trunk/lib/Target/ARM/ARM.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/ARM/ARM.h (original)
>>>> +++ llvm/trunk/lib/Target/ARM/ARM.h Mon Apr 27 19:21:31 2009
>>>> @@ -91,7 +91,7 @@
>>>> FunctionPass *createARMISelDag(ARMTargetMachine &TM);
>>>> FunctionPass *createARMCodePrinterPass(raw_ostream &O,
>>>>                                       ARMTargetMachine &TM,
>>>> -                                       bool Fast, bool Verbose);
>>>> +                                       unsigned OptLevel, bool
>>>> Verbose);
>>>> FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
>>>>                                       MachineCodeEmitter &MCE);
>>>> FunctionPass *createARMLoadStoreOptimizationPass();
>>>>
>>>> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
>>>> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -138,35 +138,37 @@
>>>>
>>>>
>>>> // Pass Pipeline Configuration
>>>> -bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, bool
>>>> Fast) {
>>>> +bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
>>>> unsigned OptLevel) {
>>>>  PM.add(createARMISelDag(*this));
>>>>  return false;
>>>> }
>>>>
>>>> -bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>>>> Fast) {
>>>> +bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM,  
>>>> unsigned
>>>> OptLevel) {
>>>>  // FIXME: temporarily disabling load / store optimization pass for
>>>> Thumb mode.
>>>> -  if (!Fast && !DisableLdStOpti && !Subtarget.isThumb())
>>>> +  if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
>>>>    PM.add(createARMLoadStoreOptimizationPass());
>>>>
>>>> -  if (!Fast && !DisableIfConversion && !Subtarget.isThumb())
>>>> +  if (OptLevel != 0 && !DisableIfConversion && ! 
>>>> Subtarget.isThumb())
>>>>    PM.add(createIfConverterPass());
>>>>
>>>>  PM.add(createARMConstantIslandPass());
>>>>  return true;
>>>> }
>>>>
>>>> -bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,  
>>>> bool
>>>> Fast,
>>>> -                                          bool Verbose,  
>>>> raw_ostream
>>>> &Out) {
>>>> +bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>>> +                                          unsigned OptLevel,
>>>> +                                          bool Verbose,
>>>> +                                          raw_ostream &Out) {
>>>>  // Output assembly language.
>>>>  assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>>>  if (AsmPrinterCtor)
>>>> -    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
>>>> +    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>>>>
>>>>  return false;
>>>> }
>>>>
>>>>
>>>> -bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, bool
>>>> Fast,
>>>> +bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM,  
>>>> unsigned
>>>> OptLevel,
>>>>                                      bool DumpAsm,
>>>> MachineCodeEmitter &MCE) {
>>>>  // FIXME: Move this to TargetJITInfo!
>>>>  if (DefRelocModel == Reloc::Default)
>>>> @@ -177,20 +179,22 @@
>>>>  if (DumpAsm) {
>>>>    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>>>    if (AsmPrinterCtor)
>>>> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>>>> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>>>  }
>>>>
>>>>  return false;
>>>> }
>>>>
>>>> -bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>>> bool Fast,
>>>> -                                        bool DumpAsm,
>>>> MachineCodeEmitter &MCE) {
>>>> +bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>>> +                                            unsigned OptLevel,
>>>> +                                            bool DumpAsm,
>>>> +                                            MachineCodeEmitter
>>>> &MCE) {
>>>>  // Machine code emitter pass for ARM.
>>>>  PM.add(createARMCodeEmitterPass(*this, MCE));
>>>>  if (DumpAsm) {
>>>>    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>>>    if (AsmPrinterCtor)
>>>> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>>>> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>>>  }
>>>>
>>>>  return false;
>>>>
>>>> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
>>>> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Mon Apr 27  
>>>> 19:21:31
>>>> 2009
>>>> @@ -41,7 +41,7 @@
>>>>  // set this functions to ctor pointer at startup time if they are
>>>> linked in.
>>>>  typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>>>>                                            ARMTargetMachine &tm,
>>>> -                                            bool fast, bool
>>>> verbose);
>>>> +                                            unsigned OptLevel,  
>>>> bool
>>>> verbose);
>>>>  static AsmPrinterCtorFn AsmPrinterCtor;
>>>>
>>>> public:
>>>> @@ -69,13 +69,13 @@
>>>>  virtual const TargetAsmInfo *createTargetAsmInfo() const;
>>>>
>>>>  // Pass Pipeline Configuration
>>>> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>>> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>>> OptLevel);
>>>> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>>> OptLevel);
>>>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>>> OptLevel,
>>>>                                  bool Verbose, raw_ostream &Out);
>>>> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
>>>> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned
>>>> OptLevel,
>>>>                              bool DumpAsm, MachineCodeEmitter  
>>>> &MCE);
>>>> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool  
>>>> Fast,
>>>> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
>>>> OptLevel,
>>>>                                    bool DumpAsm, MachineCodeEmitter
>>>> &MCE);
>>>> };
>>>>
>>>>
>>>> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp  
>>>> (original)
>>>> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Mon Apr
>>>> 27 19:21:31 2009
>>>> @@ -80,9 +80,9 @@
>>>>    /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
>>>>    bool InCPMode;
>>>>  public:
>>>> -    ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>>> -                  const TargetAsmInfo *T, bool F, bool V)
>>>> -      : AsmPrinter(O, TM, T, F, V), DW(0), MMI(NULL), AFI(NULL),
>>>> MCP(NULL),
>>>> +    explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>>> +                           const TargetAsmInfo *T, unsigned OL,
>>>> bool V)
>>>> +      : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL),
>>>> MCP(NULL),
>>>>        InCPMode(false) {
>>>>      Subtarget = &TM.getSubtarget<ARMSubtarget>();
>>>>    }
>>>> @@ -1061,8 +1061,8 @@
>>>> ///
>>>> FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
>>>>                                             ARMTargetMachine &tm,
>>>> -                                             bool fast, bool
>>>> verbose) {
>>>> -  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>>> verbose);
>>>> +                                             unsigned OptLevel,
>>>> bool verbose) {
>>>> +  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,
>>>> verbose);
>>>> }
>>>>
>>>> namespace {
>>>>
>>>> Modified: llvm/trunk/lib/Target/Alpha/Alpha.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/Alpha/Alpha.h (original)
>>>> +++ llvm/trunk/lib/Target/Alpha/Alpha.h Mon Apr 27 19:21:31 2009
>>>> @@ -26,7 +26,7 @@
>>>>  FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
>>>>  FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
>>>>                                           TargetMachine &TM,
>>>> -                                           bool Fast, bool  
>>>> Verbose);
>>>> +                                           unsigned OptLevel, bool
>>>> Verbose);
>>>>  FunctionPass *createAlphaPatternInstructionSelector(TargetMachine
>>>> &TM);
>>>>  FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
>>>>                                           MachineCodeEmitter &MCE);
>>>>
>>>> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
>>>> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -76,31 +76,34 @@
>>>> // Pass Pipeline Configuration
>>>> //
>>>> =
>>>> =
>>>> =
>>>> ----------------------------------------------------------------------=
>>>> ==//
>>>>
>>>> -bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, bool
>>>> Fast) {
>>>> +bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
>>>> +                                         unsigned OptLevel) {
>>>>  PM.add(createAlphaISelDag(*this));
>>>>  return false;
>>>> }
>>>> -bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>>>> Fast) {
>>>> +bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
>>>> +                                        unsigned OptLevel) {
>>>>  // Must run branch selection immediately preceding the asm printer
>>>>  PM.add(createAlphaBranchSelectionPass());
>>>>  return false;
>>>> }
>>>> -bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>>> bool Fast,
>>>> +bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>>> +                                            unsigned OptLevel,
>>>>                                            bool Verbose,
>>>>                                            raw_ostream &Out) {
>>>>  PM.add(createAlphaLLRPPass(*this));
>>>> -  PM.add(createAlphaCodePrinterPass(Out, *this, Fast, Verbose));
>>>> +  PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel,  
>>>> Verbose));
>>>>  return false;
>>>> }
>>>> -bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, bool
>>>> Fast,
>>>> +bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
>>>> unsigned OptLevel,
>>>>                                        bool DumpAsm,
>>>> MachineCodeEmitter &MCE) {
>>>>  PM.add(createAlphaCodeEmitterPass(*this, MCE));
>>>>  if (DumpAsm)
>>>> -    PM.add(createAlphaCodePrinterPass(errs(), *this, Fast, true));
>>>> +    PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel,
>>>> true));
>>>>  return false;
>>>> }
>>>> bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>>> -                                              bool Fast, bool
>>>> DumpAsm,
>>>> +                                              unsigned OptLevel,
>>>> bool DumpAsm,
>>>>                                              MachineCodeEmitter
>>>> &MCE) {
>>>> -  return addCodeEmitter(PM, Fast, DumpAsm, MCE);
>>>> +  return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
>>>> }
>>>>
>>>> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original)
>>>> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -58,13 +58,13 @@
>>>>  static unsigned getModuleMatchQuality(const Module &M);
>>>>
>>>>  // Pass Pipeline Configuration
>>>> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>>> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>>> OptLevel);
>>>> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>>> OptLevel);
>>>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>>> OptLevel,
>>>>                                  bool Verbose, raw_ostream &Out);
>>>> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
>>>> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned
>>>> OptLevel,
>>>>                              bool DumpAsm, MachineCodeEmitter  
>>>> &MCE);
>>>> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool  
>>>> Fast,
>>>> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
>>>> OptLevel,
>>>>                                    bool DumpAsm, MachineCodeEmitter
>>>> &MCE);
>>>> };
>>>>
>>>>
>>>> Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/ 
>>>> AlphaAsmPrinter.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>>>> (original)
>>>> +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Mon
>>>> Apr 27 19:21:31 2009
>>>> @@ -36,9 +36,9 @@
>>>>    /// Unique incrementer for label values for referencing Global
>>>> values.
>>>>    ///
>>>>
>>>> -    AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
>>>> -                    const TargetAsmInfo *T, bool F, bool V)
>>>> -      : AsmPrinter(o, tm, T, F, V) {}
>>>> +    explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
>>>> +                             const TargetAsmInfo *T, unsigned OL,
>>>> bool V)
>>>> +      : AsmPrinter(o, tm, T, OL, V) {}
>>>>
>>>>    virtual const char *getPassName() const {
>>>>      return "Alpha Assembly Printer";
>>>> @@ -68,8 +68,9 @@
>>>> ///
>>>> FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
>>>>                                               TargetMachine &tm,
>>>> -                                               bool fast, bool
>>>> verbose) {
>>>> -  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>>> verbose);
>>>> +                                               unsigned OptLevel,
>>>> +                                               bool verbose) {
>>>> +  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>>> OptLevel, verbose);
>>>> }
>>>>
>>>> #include "AlphaGenAsmWriter.inc"
>>>>
>>>> Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
>>>> +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Apr 27 19:21:31
>>>> 2009
>>>> @@ -3587,7 +3587,7 @@
>>>> bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>>>>                                              raw_ostream &o,
>>>>                                              CodeGenFileType
>>>> FileType,
>>>> -                                              bool Fast) {
>>>> +                                              unsigned OptLevel) {
>>>>  if (FileType != TargetMachine::AssemblyFile) return true;
>>>>
>>>>  PM.add(createGCLoweringPass());
>>>>
>>>> Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
>>>> +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -27,7 +27,8 @@
>>>>
>>>>  virtual bool WantsWholeFile() const { return true; }
>>>>  virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream
>>>> &Out,
>>>> -                                        CodeGenFileType FileType,
>>>> bool Fast);
>>>> +                                        CodeGenFileType FileType,
>>>> +                                        unsigned OptLevel);
>>>>
>>>>  // This class always works, but must be requested explicitly on
>>>>  // llc command line.
>>>>
>>>> Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/ 
>>>> SPUAsmPrinter.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>>>> (original)
>>>> +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Mon
>>>> Apr 27 19:21:31 2009
>>>> @@ -48,9 +48,9 @@
>>>>  class VISIBILITY_HIDDEN SPUAsmPrinter : public AsmPrinter {
>>>>    std::set<std::string> FnStubs, GVStubs;
>>>>  public:
>>>> -    SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>>> -                  const TargetAsmInfo *T, bool F, bool V) :
>>>> -      AsmPrinter(O, TM, T, F, V) {}
>>>> +    explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>>> +                           const TargetAsmInfo *T, unsigned OL,
>>>> bool V) :
>>>> +      AsmPrinter(O, TM, T, OL, V) {}
>>>>
>>>>    virtual const char *getPassName() const {
>>>>      return "STI CBEA SPU Assembly Printer";
>>>> @@ -615,6 +615,6 @@
>>>> ///
>>>> FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
>>>>                                            SPUTargetMachine &tm,
>>>> -                                            bool fast, bool
>>>> verbose) {
>>>> -  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>>> verbose);
>>>> +                                            unsigned OptLevel,  
>>>> bool
>>>> verbose) {
>>>> +  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>>> OptLevel, verbose);
>>>> }
>>>>
>>>> Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
>>>> +++ llvm/trunk/lib/Target/CellSPU/SPU.h Mon Apr 27 19:21:31 2009
>>>> @@ -25,7 +25,7 @@
>>>>  FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
>>>>  FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
>>>>                                        SPUTargetMachine &tm,
>>>> -                                        bool fast, bool verbose);
>>>> +                                        unsigned OptLevel, bool
>>>> verbose);
>>>>
>>>>  /*--== Utility functions/predicates/etc used all over the place:  
>>>> --
>>>> ==*/
>>>>  //! Predicate test for a signed 10-bit value
>>>>
>>>> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
>>>> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -81,15 +81,17 @@
>>>> //
>>>> =
>>>> =
>>>> =
>>>> ----------------------------------------------------------------------=
>>>> ==//
>>>>
>>>> bool
>>>> -SPUTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast)
>>>> +SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned
>>>> OptLevel)
>>>> {
>>>>  // Install an instruction selector.
>>>>  PM.add(createSPUISelDag(*this));
>>>>  return false;
>>>> }
>>>>
>>>> -bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,  
>>>> bool
>>>> Fast,
>>>> -                                          bool Verbose,  
>>>> raw_ostream
>>>> &Out) {
>>>> -  PM.add(createSPUAsmPrinterPass(Out, *this, Fast, Verbose));
>>>> +bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>>> +                                          unsigned OptLevel,
>>>> +                                          bool Verbose,
>>>> +                                          raw_ostream &Out) {
>>>> +  PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
>>>>  return false;
>>>> }
>>>>
>>>> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original)
>>>> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -83,9 +83,9 @@
>>>>  }
>>>>
>>>>  // Pass Pipeline Configuration
>>>> -  virtual bool addInstSelector(PassManagerBase &PM, bool / 
>>>> *Fast*/);
>>>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool /
>>>> *Fast*/,
>>>> -                                  bool /*Verbose*/, raw_ostream
>>>> &Out);
>>>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>>> OptLevel);
>>>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>>> OptLevel,
>>>> +                                  bool Verbose, raw_ostream &Out);
>>>> };
>>>>
>>>> } // end namespace llvm
>>>>
>>>> Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
>>>> +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -1995,7 +1995,7 @@
>>>> bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>>>>                                                raw_ostream &o,
>>>>                                                CodeGenFileType
>>>> FileType,
>>>> -                                                bool Fast) {
>>>> +                                                unsigned  
>>>> OptLevel) {
>>>>  if (FileType != TargetMachine::AssemblyFile) return true;
>>>>  PM.add(new CppWriter(o));
>>>>  return false;
>>>>
>>>> Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
>>>> +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -29,7 +29,8 @@
>>>>
>>>>  virtual bool WantsWholeFile() const { return true; }
>>>>  virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream
>>>> &Out,
>>>> -                                        CodeGenFileType FileType,
>>>> bool Fast);
>>>> +                                        CodeGenFileType FileType,
>>>> +                                        unsigned OptLevel);
>>>>
>>>>  // This class always works, but shouldn't be the default in most
>>>> cases.
>>>>  static unsigned getModuleMatchQuality(const Module &M) { return  
>>>> 1; }
>>>>
>>>> Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>>>> (original)
>>>> +++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Mon  
>>>> Apr
>>>> 27 19:21:31 2009
>>>> @@ -37,9 +37,9 @@
>>>>  class IA64AsmPrinter : public AsmPrinter {
>>>>    std::set<std::string> ExternalFunctionNames,  
>>>> ExternalObjectNames;
>>>>  public:
>>>> -    IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
>>>> -                   const TargetAsmInfo *T, bool F, bool V)
>>>> -      : AsmPrinter(O, TM, T, F, V) {}
>>>> +    explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
>>>> +                            const TargetAsmInfo *T, unsigned OL,
>>>> bool V)
>>>> +      : AsmPrinter(O, TM, T, OL, V) {}
>>>>
>>>>    virtual const char *getPassName() const {
>>>>      return "IA64 Assembly Printer";
>>>> @@ -370,6 +370,7 @@
>>>> ///
>>>> FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
>>>>                                              IA64TargetMachine &tm,
>>>> -                                              bool fast, bool
>>>> verbose) {
>>>> -  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>>> verbose);
>>>> +                                              unsigned OptLevel,
>>>> +                                              bool verbose) {
>>>> +  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(),  
>>>> OptLevel,
>>>> verbose);
>>>> }
>>>>
>>>> Modified: llvm/trunk/lib/Target/IA64/IA64.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/IA64/IA64.h (original)
>>>> +++ llvm/trunk/lib/Target/IA64/IA64.h Mon Apr 27 19:21:31 2009
>>>> @@ -37,7 +37,7 @@
>>>> ///
>>>> FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
>>>>                                        IA64TargetMachine &tm,
>>>> -                                        bool fast, bool verbose);
>>>> +                                        unsigned OptLevel, bool
>>>> verbose);
>>>>
>>>> } // End llvm namespace
>>>>
>>>>
>>>> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original)
>>>> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -72,19 +72,21 @@
>>>> // Pass Pipeline Configuration
>>>> //
>>>> =
>>>> =
>>>> =
>>>> ----------------------------------------------------------------------=
>>>> ==//
>>>>
>>>> -bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, bool
>>>> Fast) {
>>>> +bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,
>>>> unsigned OptLEvel){
>>>>  PM.add(createIA64DAGToDAGInstructionSelector(*this));
>>>>  return false;
>>>> }
>>>>
>>>> -bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>>>> Fast) {
>>>> +bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,
>>>> unsigned OptLevel) {
>>>>  // Make sure everything is bundled happily
>>>>  PM.add(createIA64BundlingPass(*this));
>>>>  return true;
>>>> }
>>>> -bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>>> bool Fast,
>>>> -                                           bool Verbose,
>>>> raw_ostream &Out) {
>>>> -  PM.add(createIA64CodePrinterPass(Out, *this, Fast, Verbose));
>>>> +bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>>> +                                           unsigned OptLevel,
>>>> +                                           bool Verbose,
>>>> +                                           raw_ostream &Out) {
>>>> +  PM.add(createIA64CodePrinterPass(Out, *this, OptLevel,  
>>>> Verbose));
>>>>  return false;
>>>> }
>>>>
>>>>
>>>> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.h (original)
>>>> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -51,9 +51,9 @@
>>>>  static unsigned getModuleMatchQuality(const Module &M);
>>>>
>>>>  // Pass Pipeline Configuration
>>>> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>>> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>>> OptLevel);
>>>> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>>> OptLevel);
>>>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>>> OptLevel,
>>>>                                  bool Verbose, raw_ostream &Out);
>>>> };
>>>> } // End llvm namespace
>>>>
>>>> Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
>>>> +++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Mon Apr 27 19:21:31
>>>> 2009
>>>> @@ -35,7 +35,8 @@
>>>>
>>>>    virtual bool WantsWholeFile() const { return true; }
>>>>    virtual bool addPassesToEmitWholeFile(PassManager &PM,
>>>> raw_ostream &Out,
>>>> -                                         CodeGenFileType FileType,
>>>> bool Fast);
>>>> +                                          CodeGenFileType  
>>>> FileType,
>>>> +                                          unsigned OptLevel);
>>>>
>>>>    // This class always works, but shouldn't be the default in most
>>>> cases.
>>>>    static unsigned getModuleMatchQuality(const Module &M) { return
>>>> 1; }
>>>> @@ -1662,7 +1663,8 @@
>>>> //
>>>> =
>>>> =
>>>> =
>>>> ----------------------------------------------------------------------=
>>>> ==//
>>>>
>>>> bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM,
>>>> raw_ostream &o,
>>>> -                                          CodeGenFileType  
>>>> FileType,
>>>> bool Fast)
>>>> +                                          CodeGenFileType  
>>>> FileType,
>>>> +                                          unsigned OptLevel)
>>>> {
>>>>  if (FileType != TargetMachine::AssemblyFile) return true;
>>>>  MSILWriter* Writer = new MSILWriter(o);
>>>>
>>>> Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>>>> (original)
>>>> +++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Mon  
>>>> Apr
>>>> 27 19:21:31 2009
>>>> @@ -49,9 +49,9 @@
>>>>  class VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
>>>>    const MipsSubtarget *Subtarget;
>>>>  public:
>>>> -    MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
>>>> -                   const TargetAsmInfo *T, bool F, bool V)
>>>> -      : AsmPrinter(O, TM, T, F, V) {
>>>> +    explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
>>>> +                            const TargetAsmInfo *T, unsigned OL,
>>>> bool V)
>>>> +      : AsmPrinter(O, TM, T, OL, V) {
>>>>      Subtarget = &TM.getSubtarget<MipsSubtarget>();
>>>>    }
>>>>
>>>> @@ -91,8 +91,8 @@
>>>> /// regardless of whether the function is in SSA form.
>>>> FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
>>>>                                              MipsTargetMachine &tm,
>>>> -                                              bool fast, bool
>>>> verbose) {
>>>> -  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>>> verbose);
>>>> +                                              unsigned OptLevel,
>>>> bool verbose) {
>>>> +  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
>>>> OptLevel,
>>>> verbose);
>>>> }
>>>>
>>>> //
>>>> =
>>>> =
>>>> =
>>>> ----------------------------------------------------------------------=
>>>> ==//
>>>>
>>>> Modified: llvm/trunk/lib/Target/Mips/Mips.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/Mips/Mips.h (original)
>>>> +++ llvm/trunk/lib/Target/Mips/Mips.h Mon Apr 27 19:21:31 2009
>>>> @@ -25,7 +25,7 @@
>>>>  FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine  
>>>> &TM);
>>>>  FunctionPass *createMipsCodePrinterPass(raw_ostream &OS,
>>>>                                          MipsTargetMachine &TM,
>>>> -                                          bool Fast, bool  
>>>> Verbose);
>>>> +                                          unsigned OptLevel, bool
>>>> Verbose);
>>>> } // end namespace llvm;
>>>>
>>>> // Defines symbolic names for Mips registers.  This defines a
>>>> mapping from
>>>>
>>>> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
>>>> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -105,7 +105,7 @@
>>>> // Install an instruction selector pass using
>>>> // the ISelDag to gen Mips code.
>>>> bool MipsTargetMachine::
>>>> -addInstSelector(PassManagerBase &PM, bool Fast)
>>>> +addInstSelector(PassManagerBase &PM, unsigned OptLevel)
>>>> {
>>>>  PM.add(createMipsISelDag(*this));
>>>>  return false;
>>>> @@ -115,7 +115,7 @@
>>>> // machine code is emitted. return true if -print-machineinstrs
>>>> should
>>>> // print out the code after the passes.
>>>> bool MipsTargetMachine::
>>>> -addPreEmitPass(PassManagerBase &PM, bool Fast)
>>>> +addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
>>>> {
>>>>  PM.add(createMipsDelaySlotFillerPass(*this));
>>>>  return true;
>>>> @@ -124,10 +124,10 @@
>>>> // Implements the AssemblyEmitter for the target. Must return
>>>> // true if AssemblyEmitter is supported
>>>> bool MipsTargetMachine::
>>>> -addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>>> +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
>>>>                   bool Verbose, raw_ostream &Out)
>>>> {
>>>>  // Output assembly language.
>>>> -  PM.add(createMipsCodePrinterPass(Out, *this, Fast, Verbose));
>>>> +  PM.add(createMipsCodePrinterPass(Out, *this, OptLevel,  
>>>> Verbose));
>>>>  return false;
>>>> }
>>>>
>>>> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
>>>> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -57,9 +57,9 @@
>>>>    static unsigned getModuleMatchQuality(const Module &M);
>>>>
>>>>    // Pass Pipeline Configuration
>>>> -    virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>>> -    virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>>> -    virtual bool addAssemblyEmitter(PassManagerBase &PM, bool  
>>>> Fast,
>>>> +    virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>>> OptLevel);
>>>> +    virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>>> OptLevel);
>>>> +    virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>>> OptLevel,
>>>>                                    bool Verbose, raw_ostream &Out);
>>>>  };
>>>>
>>>>
>>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/PIC16/PIC16.h (original)
>>>> +++ llvm/trunk/lib/Target/PIC16/PIC16.h Mon Apr 27 19:21:31 2009
>>>> @@ -75,7 +75,7 @@
>>>>  FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
>>>>  FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
>>>>                                           PIC16TargetMachine &TM,
>>>> -                                           bool Fast, bool  
>>>> Verbose);
>>>> +                                           unsigned OptLevel, bool
>>>> Verbose);
>>>> } // end namespace llvm;
>>>>
>>>> // Defines symbolic names for PIC16 registers.  This defines a
>>>> mapping from
>>>>
>>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
>>>> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -161,8 +161,9 @@
>>>> ///
>>>> FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
>>>>                                               PIC16TargetMachine  
>>>> &tm,
>>>> -                                               bool fast, bool
>>>> verbose) {
>>>> -  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,
>>>> verbose);
>>>> +                                               unsigned OptLevel,
>>>> +                                               bool verbose) {
>>>> +  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>>> OptLevel, verbose);
>>>> }
>>>>
>>>> void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int
>>>> opNum) {
>>>>
>>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
>>>> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -24,9 +24,9 @@
>>>>
>>>> namespace llvm {
>>>>  struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
>>>> -  PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
>>>> -                    const TargetAsmInfo *T, bool F, bool V)
>>>> -      : AsmPrinter(O, TM, T, F, V) {
>>>> +    explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine  
>>>> &TM,
>>>> +                             const TargetAsmInfo *T, unsigned OL,
>>>> bool V)
>>>> +      : AsmPrinter(O, TM, T, OL, V) {
>>>>      CurBank = "";
>>>>      FunctionLabelBegin = '@';
>>>>      IsRomData = false;
>>>>
>>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original)
>>>> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -55,17 +55,18 @@
>>>>  return new PIC16TargetAsmInfo(*this);
>>>> }
>>>>
>>>> -bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool
>>>> Fast) {
>>>> +bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
>>>> +                                         unsigned OptLevel) {
>>>>  // Install an instruction selector.
>>>>  PM.add(createPIC16ISelDag(*this));
>>>>  return false;
>>>> }
>>>>
>>>> bool PIC16TargetMachine::
>>>> -addAssemblyEmitter(PassManagerBase &PM, bool Fast, bool Verbose,
>>>> +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool
>>>> Verbose,
>>>>                   raw_ostream &Out) {
>>>>  // Output assembly language.
>>>> -  PM.add(createPIC16CodePrinterPass(Out, *this, Fast, Verbose));
>>>> +  PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel,  
>>>> Verbose));
>>>>  return false;
>>>> }
>>>>
>>>>
>>>> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h (original)
>>>> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -57,8 +57,8 @@
>>>>    return const_cast<PIC16TargetLowering*>(&TLInfo);
>>>>  }
>>>>
>>>> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>>> OptLevel);
>>>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>>> OptLevel,
>>>>                                  bool Verbose, raw_ostream &Out);
>>>> }; // PIC16TargetMachine.
>>>>
>>>>
>>>> Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/ 
>>>> PPCAsmPrinter.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>>>> (original)
>>>> +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Mon
>>>> Apr 27 19:21:31 2009
>>>> @@ -54,9 +54,9 @@
>>>>    StringSet<> FnStubs, GVStubs, HiddenGVStubs;
>>>>    const PPCSubtarget &Subtarget;
>>>>  public:
>>>> -    PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>>> -                  const TargetAsmInfo *T, bool F, bool V)
>>>> -      : AsmPrinter(O, TM, T, F, V),
>>>> +    explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
>>>> +                           const TargetAsmInfo *T, unsigned OL,
>>>> bool V)
>>>> +      : AsmPrinter(O, TM, T, OL, V),
>>>>        Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
>>>>
>>>>    virtual const char *getPassName() const {
>>>> @@ -297,9 +297,9 @@
>>>>    DwarfWriter *DW;
>>>>    MachineModuleInfo *MMI;
>>>>  public:
>>>> -    PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
>>>> -                       const TargetAsmInfo *T, bool F, bool V)
>>>> -      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
>>>> +    explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine
>>>> &TM,
>>>> +                                const TargetAsmInfo *T, unsigned
>>>> OL, bool V)
>>>> +      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
>>>>
>>>>    virtual const char *getPassName() const {
>>>>      return "Linux PPC Assembly Printer";
>>>> @@ -326,9 +326,9 @@
>>>>    MachineModuleInfo *MMI;
>>>>    raw_ostream &OS;
>>>>  public:
>>>> -    PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
>>>> -                        const TargetAsmInfo *T, bool F, bool V)
>>>> -      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0), OS(O) {}
>>>> +    explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine
>>>> &TM,
>>>> +                                 const TargetAsmInfo *T, unsigned
>>>> OL, bool V)
>>>> +      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
>>>>
>>>>    virtual const char *getPassName() const {
>>>>      return "Darwin PPC Assembly Printer";
>>>> @@ -1176,13 +1176,15 @@
>>>> ///
>>>> FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
>>>>                                            PPCTargetMachine &tm,
>>>> -                                            bool fast, bool
>>>> verbose) {
>>>> +                                            unsigned OptLevel,  
>>>> bool
>>>> verbose) {
>>>>  const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
>>>>
>>>>  if (Subtarget->isDarwin()) {
>>>> -    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>>> fast, verbose);
>>>> +    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>>> +                                   OptLevel, verbose);
>>>>  } else {
>>>> -    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>>> fast, verbose);
>>>> +    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
>>>> +                                  OptLevel, verbose);
>>>>  }
>>>> }
>>>>
>>>>
>>>> Modified: llvm/trunk/lib/Target/PowerPC/PPC.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/PowerPC/PPC.h (original)
>>>> +++ llvm/trunk/lib/Target/PowerPC/PPC.h Mon Apr 27 19:21:31 2009
>>>> @@ -28,7 +28,7 @@
>>>> FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
>>>> FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
>>>>                                      PPCTargetMachine &TM,
>>>> -                                      bool Fast, bool Verbose);
>>>> +                                      unsigned OptLevel, bool
>>>> Verbose);
>>>> FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
>>>>                                       MachineCodeEmitter &MCE);
>>>> } // end namespace llvm;
>>>>
>>>> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
>>>> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -129,29 +129,31 @@
>>>> // Pass Pipeline Configuration
>>>> //
>>>> =
>>>> =
>>>> =
>>>> ----------------------------------------------------------------------=
>>>> ==//
>>>>
>>>> -bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool
>>>> Fast) {
>>>> +bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
>>>> unsigned OptLevel) {
>>>>  // Install an instruction selector.
>>>>  PM.add(createPPCISelDag(*this));
>>>>  return false;
>>>> }
>>>>
>>>> -bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool
>>>> Fast) {
>>>> +bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,  
>>>> unsigned
>>>> OptLevel) {
>>>>
>>>>  // Must run branch selection immediately preceding the asm  
>>>> printer.
>>>>  PM.add(createPPCBranchSelectionPass());
>>>>  return false;
>>>> }
>>>>
>>>> -bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,  
>>>> bool
>>>> Fast,
>>>> -                                          bool Verbose,  
>>>> raw_ostream
>>>> &Out) {
>>>> +bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
>>>> +                                          unsigned OptLevel,
>>>> +                                          bool Verbose,
>>>> +                                          raw_ostream &Out) {
>>>>  assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>>>  if (AsmPrinterCtor)
>>>> -    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
>>>> +    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>>>>
>>>>  return false;
>>>> }
>>>>
>>>> -bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool
>>>> Fast,
>>>> +bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,  
>>>> unsigned
>>>> OptLevel,
>>>>                                      bool DumpAsm,
>>>> MachineCodeEmitter &MCE) {
>>>>  // The JIT should use the static relocation model in ppc32 mode,
>>>> PIC in ppc64.
>>>>  // FIXME: This should be moved to TargetJITInfo!!
>>>> @@ -176,20 +178,20 @@
>>>>  if (DumpAsm) {
>>>>    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>>>    if (AsmPrinterCtor)
>>>> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>>>> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>>>  }
>>>>
>>>>  return false;
>>>> }
>>>>
>>>> -bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>>> bool Fast,
>>>> +bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
>>>> unsigned OptLevel,
>>>>                                            bool DumpAsm,
>>>> MachineCodeEmitter &MCE) {
>>>>  // Machine code emitter pass for PowerPC.
>>>>  PM.add(createPPCCodeEmitterPass(*this, MCE));
>>>>  if (DumpAsm) {
>>>>    assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>>>>    if (AsmPrinterCtor)
>>>> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
>>>> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>>>>  }
>>>>
>>>>  return false;
>>>>
>>>> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> = 
>>>> = 
>>>> ===================================================================
>>>> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
>>>> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Mon Apr 27
>>>> 19:21:31 2009
>>>> @@ -46,7 +46,7 @@
>>>>  // set this functions to ctor pointer at startup time if they are
>>>> linked in.
>>>>  typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>>>>                                            PPCTargetMachine &tm,
>>>> -                                            bool fast, bool
>>>> verbose);
>>>> +                                            unsigned OptLevel,  
>>>> bool
>>>> verbose);
>>>>  static AsmPrinterCtorFn AsmPrinterCtor;
>>>>
>>>> public:
>>>> @@ -76,13 +76,13 @@
>>>>  }
>>>>
>>>>  // Pass Pipeline Configuration
>>>> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
>>>> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
>>>> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
>>>> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned
>>>> OptLevel);
>>>> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned
>>>> OptLevel);
>>>> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned
>>>> OptLevel,
>>>>                                  bool Verbose, raw_ostream &Out);
>>>> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
>>>> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned
>>>> OptLevel,
>>>>                              bool DumpAsm, MachineCodeEmitter  
>>>> &MCE);
>>>> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool  
>>>> Fast,
>>>> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned
>>>> OptLevel,
>>>>                                    bool DumpAsm, MachineCodeEmitter
>>>> &MCE);
>>>>  virtual bool getEnableTailMergeDefault() const;
>>>> };
>>>>
>>>> Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/ 
>>>> SparcAsmPrinter.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=70270&r1=70269&r2=70270&view=diff
>>>>
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =
>>>> =========================================
>> ...
>>
>> [Message clipped]
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From clattner at apple.com  Mon Apr 27 19:54:16 2009
From: clattner at apple.com (Chris Lattner)
Date: Mon, 27 Apr 2009 17:54:16 -0700
Subject: [llvm-commits] [llvm] r70165 - in /llvm/trunk:
	docs/BitCodeFormat.html include/llvm/Bitcode/BitCodes.h
	include/llvm/Bitcode/BitstreamReader.h
	tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
In-Reply-To: <200904271052.58445.baldrick@free.fr>
References: <200904262221.n3QMLx0a028970@zion.cs.uiuc.edu>
	<200904271052.58445.baldrick@free.fr>
Message-ID: <A412F391-5D07-47B0-962E-9F4C070D3641@apple.com>


On Apr 27, 2009, at 1:52 AM, Duncan Sands wrote:

>> Add two new record types to the blockinfo block:
>> BLOCKNAME and SETRECORDNAME.  This allows a bitcode
>> file to be self describing with pretty names for
>> records and blocks in addition to numbers.  This
>> enhances llvm-bcanalyzer to use this to print prettily.
>
> Testcase?

Clang uses this.  LLVM IR doesn't need this because llvm-bcanalyzer is  
hard coded to know about all of its records etc.

-Chris


From isanbard at gmail.com  Mon Apr 27 20:04:55 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 28 Apr 2009 01:04:55 -0000
Subject: [llvm-commits] [llvm] r70275 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/
 lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/
 lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Alpha/AsmPrinter/
 lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CellSPU/AsmPrinter/
 lib/Target/CppBackend/ lib/Target/IA64/ lib/Target/IA64/AsmPrinter/
 lib/Target/MSIL/ lib/Target/Mips/ lib/Target/Mips/AsmPrinter/
 lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/PowerPC/AsmPrinter/
 lib/Target...
Message-ID: <200904280104.n3S14wP3029289@zion.cs.uiuc.edu>

Author: void
Date: Mon Apr 27 20:04:53 2009
New Revision: 70275

URL: http://llvm.org/viewvc/llvm-project?rev=70275&view=rev
Log:
r70270 isn't ready yet. Back this out. Sorry for the noise.

Modified:
    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
    llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
    llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
    llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
    llvm/trunk/include/llvm/Target/TargetMachine.h
    llvm/trunk/include/llvm/Target/TargetOptions.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/lib/Target/ARM/ARM.h
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/Alpha/Alpha.h
    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
    llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
    llvm/trunk/lib/Target/CBackend/CBackend.cpp
    llvm/trunk/lib/Target/CBackend/CTargetMachine.h
    llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
    llvm/trunk/lib/Target/CellSPU/SPU.h
    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
    llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
    llvm/trunk/lib/Target/IA64/IA64.h
    llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
    llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
    llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
    llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
    llvm/trunk/lib/Target/Mips/Mips.h
    llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
    llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
    llvm/trunk/lib/Target/PIC16/PIC16.h
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
    llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
    llvm/trunk/lib/Target/PowerPC/PPC.h
    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
    llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
    llvm/trunk/lib/Target/Sparc/Sparc.h
    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
    llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
    llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
    llvm/trunk/lib/Target/X86/X86.h
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.h
    llvm/trunk/lib/Target/XCore/XCore.h
    llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
    llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
    llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
    llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
    llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
    llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
    llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
    llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
    llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
    llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
    llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
    llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
    llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
    llvm/trunk/test/CodeGen/X86/pr1489.ll
    llvm/trunk/test/CodeGen/X86/volatile.ll
    llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
    llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
    llvm/trunk/test/DebugInfo/deaddebuglabel.ll
    llvm/trunk/test/DebugInfo/forwardDecl.ll
    llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
    llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
    llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
    llvm/trunk/tools/llc/llc.cpp
    llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Mon Apr 27 20:04:53 2009
@@ -65,8 +65,8 @@
     // Necessary for external weak linkage support
     std::set<const GlobalValue*> ExtWeakSymbols;
 
-    /// OptLevel - Generating code at a specific optimization level.
-    unsigned OptLevel;
+    /// Fast - Generating code via fast instruction selection.
+    bool Fast;
   public:
     /// Output stream on which we're printing assembly code.
     ///
@@ -110,8 +110,8 @@
     bool VerboseAsm;
 
   protected:
-    explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
-                        const TargetAsmInfo *T, unsigned OL, bool V);
+    AsmPrinter(raw_ostream &o, TargetMachine &TM,
+               const TargetAsmInfo *T, bool F, bool V);
     
   public:
     virtual ~AsmPrinter();

Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Mon Apr 27 20:04:53 2009
@@ -81,7 +81,7 @@
   void EndFunction(MachineFunction *MF);
 
   /// ValidDebugInfo - Return true if V represents valid debug info value.
-  bool ValidDebugInfo(Value *V, unsigned OptLevel);
+  bool ValidDebugInfo(Value *V, bool FastISel);
 
   /// RecordSourceLine - Register a source line with debug info. Returns a
   /// unique label ID used to generate a label and provide correspondence to

Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Mon Apr 27 20:04:53 2009
@@ -42,11 +42,11 @@
       llvm::linkOcamlGC();
       llvm::linkShadowStackGC();
       
-      (void) llvm::createBURRListDAGScheduler(NULL, 3);
-      (void) llvm::createTDRRListDAGScheduler(NULL, 3);
-      (void) llvm::createTDListDAGScheduler(NULL, 3);
-      (void) llvm::createFastDAGScheduler(NULL, 3);
-      (void) llvm::createDefaultScheduler(NULL, 3);
+      (void) llvm::createBURRListDAGScheduler(NULL, false);
+      (void) llvm::createTDRRListDAGScheduler(NULL, false);
+      (void) llvm::createTDListDAGScheduler(NULL, false);
+      (void) llvm::createFastDAGScheduler(NULL, false);
+      (void) llvm::createDefaultScheduler(NULL, false);
 
     }
   } ForceCodegenLinking; // Force link by creating a global definition.

Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Mon Apr 27 20:04:53 2009
@@ -32,7 +32,7 @@
 
 class RegisterScheduler : public MachinePassRegistryNode {
 public:
-  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned);
+  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, bool);
 
   static MachinePassRegistry Registry;
 
@@ -64,27 +64,27 @@
 /// createBURRListDAGScheduler - This creates a bottom up register usage
 /// reduction list scheduler.
 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
-                                               unsigned OptLevel);
+                                               bool Fast);
 
 /// createTDRRListDAGScheduler - This creates a top down register usage
 /// reduction list scheduler.
 ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
-                                               unsigned OptLevel);
+                                               bool Fast);
 
 /// createTDListDAGScheduler - This creates a top-down list scheduler with
 /// a hazard recognizer.
 ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
-                                             unsigned OptLevel);
+                                             bool Fast);
 
 /// createFastDAGScheduler - This creates a "fast" scheduler.
 ///
 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
-                                           unsigned OptLevel);
+                                           bool Fast);
 
 /// createDefaultScheduler - This creates an instruction scheduler appropriate
 /// for the target.
 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
-                                           unsigned OptLevel);
+                                           bool Fast);
 
 } // end namespace llvm
 

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Apr 27 20:04:53 2009
@@ -202,7 +202,7 @@
   /// certain types of nodes together, or eliminating superfluous nodes.  The
   /// Level argument controls whether Combine is allowed to produce nodes and
   /// types that are illegal on the target.
-  void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned OptLevel);
+  void Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast);
 
   /// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that
   /// only uses types natively supported by the target.  Returns "true" if it
@@ -218,7 +218,7 @@
   ///
   /// Note that this is an involved process that may invalidate pointers into
   /// the graph.
-  void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
+  void Legalize(bool TypesNeedLegalizing, bool Fast);
 
   /// RemoveDeadNodes - This method deletes all unreachable nodes in the
   /// SelectionDAG.

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Mon Apr 27 20:04:53 2009
@@ -51,10 +51,10 @@
   MachineBasicBlock *BB;
   AliasAnalysis *AA;
   GCFunctionInfo *GFI;
-  unsigned OptLevel;
+  bool Fast;
   static char ID;
 
-  explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
+  explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
   virtual ~SelectionDAGISel();
   
   TargetLowering &getTargetLowering() { return TLI; }

Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
+++ llvm/trunk/include/llvm/Target/TargetMachine.h Mon Apr 27 20:04:53 2009
@@ -213,7 +213,7 @@
   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
                                                raw_ostream &,
                                                CodeGenFileType,
-                                               unsigned /* OptLevel */) {
+                                               bool /*Fast*/) {
     return FileModel::None;
   }
 
@@ -222,8 +222,7 @@
   /// used to finish up adding passes to emit the file, if necessary.
   ///
   virtual bool addPassesToEmitFileFinish(PassManagerBase &,
-                                         MachineCodeEmitter *,
-                                         unsigned /* OptLevel */) {
+                                         MachineCodeEmitter *, bool /*Fast*/) {
     return true;
   }
  
@@ -235,7 +234,7 @@
   ///
   virtual bool addPassesToEmitMachineCode(PassManagerBase &,
                                           MachineCodeEmitter &,
-                                          unsigned /* OptLevel */) {
+                                          bool /*Fast*/) {
     return true;
   }
 
@@ -244,8 +243,7 @@
   /// use this.
   virtual bool WantsWholeFile() const { return false; }
   virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
-                                        CodeGenFileType,
-                                        unsigned /* OptLevel */) {
+                                        CodeGenFileType, bool /*Fast*/) {
     return true;
   }
 };
@@ -260,16 +258,16 @@
   /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
   /// both emitting to assembly files or machine code output.
   ///
-  bool addCommonCodeGenPasses(PassManagerBase &, unsigned /* OptLevel */);
+  bool addCommonCodeGenPasses(PassManagerBase &, bool /*Fast*/);
 
 public:
   
   /// addPassesToEmitFile - Add passes to the specified pass manager to get the
   /// specified file emitted.  Typically this will involve several steps of code
-  /// generation.  If OptLevel is 0, the code generator should emit code as fast
-  /// as possible, though the generated code may be less efficient.  This method
-  /// should return FileModel::Error if emission of this file type is not
-  /// supported.
+  /// generation.  If Fast is set to true, the code generator should emit code
+  /// as fast as possible, though the generated code may be less efficient.
+  /// This method should return FileModel::Error if emission of this file type
+  /// is not supported.
   ///
   /// The default implementation of this method adds components from the
   /// LLVM retargetable code generator, invoking the methods below to get
@@ -278,15 +276,14 @@
   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
                                                raw_ostream &Out,
                                                CodeGenFileType FileType,
-                                               unsigned OptLevel);
+                                               bool Fast);
   
   /// addPassesToEmitFileFinish - If the passes to emit the specified file had
   /// to be split up (e.g., to add an object writer pass), this method can be
   /// used to finish up adding passes to emit the file, if necessary.
   ///
   virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
-                                         MachineCodeEmitter *MCE,
-                                         unsigned OptLevel);
+                                         MachineCodeEmitter *MCE, bool Fast);
  
   /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
   /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
@@ -295,22 +292,21 @@
   /// not supported.
   ///
   virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
-                                          MachineCodeEmitter &MCE,
-                                          unsigned OptLevel);
+                                          MachineCodeEmitter &MCE, bool Fast);
   
   /// Target-Independent Code Generator Pass Configuration Options.
   
   /// addInstSelector - This method should add any "last minute" LLVM->LLVM
   /// passes, then install an instruction selector pass, which converts from
   /// LLVM code to machine instructions.
-  virtual bool addInstSelector(PassManagerBase &, unsigned /* OptLevel */) {
+  virtual bool addInstSelector(PassManagerBase &, bool /*Fast*/) {
     return true;
   }
 
   /// addPreRegAllocPasses - This method may be implemented by targets that want
   /// to run passes immediately before register allocation. This should return
   /// true if -print-machineinstrs should print after these passes.
-  virtual bool addPreRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
+  virtual bool addPreRegAlloc(PassManagerBase &, bool /*Fast*/) {
     return false;
   }
 
@@ -318,14 +314,14 @@
   /// want to run passes after register allocation but before prolog-epilog
   /// insertion.  This should return true if -print-machineinstrs should print
   /// after these passes.
-  virtual bool addPostRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
+  virtual bool addPostRegAlloc(PassManagerBase &, bool /*Fast*/) {
     return false;
   }
   
   /// addPreEmitPass - This pass may be implemented by targets that want to run
   /// passes immediately before machine code is emitted.  This should return
   /// true if -print-machineinstrs should print out the code after the passes.
-  virtual bool addPreEmitPass(PassManagerBase &, unsigned /* OptLevel */) {
+  virtual bool addPreEmitPass(PassManagerBase &, bool /*Fast*/) {
     return false;
   }
   
@@ -333,7 +329,7 @@
   /// addAssemblyEmitter - This pass should be overridden by the target to add
   /// the asmprinter, if asm emission is supported.  If this is not supported,
   /// 'true' should be returned.
-  virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /* OptLevel */,
+  virtual bool addAssemblyEmitter(PassManagerBase &, bool /*Fast*/,
                                   bool /* VerboseAsmDefault */, raw_ostream &) {
     return true;
   }
@@ -341,7 +337,7 @@
   /// addCodeEmitter - This pass should be overridden by the target to add a
   /// code emitter, if supported.  If this is not supported, 'true' should be
   /// returned. If DumpAsm is true, the generated assembly is printed to cerr.
-  virtual bool addCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
+  virtual bool addCodeEmitter(PassManagerBase &, bool /*Fast*/,
                               bool /*DumpAsm*/, MachineCodeEmitter &) {
     return true;
   }
@@ -350,7 +346,7 @@
   /// a code emitter (without setting flags), if supported.  If this is not
   /// supported, 'true' should be returned.  If DumpAsm is true, the generated
   /// assembly is printed to cerr.
-  virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &, bool /*Fast*/,
                                     bool /*DumpAsm*/, MachineCodeEmitter &) {
     return true;
   }

Modified: llvm/trunk/include/llvm/Target/TargetOptions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOptions.h (original)
+++ llvm/trunk/include/llvm/Target/TargetOptions.h Mon Apr 27 20:04:53 2009
@@ -108,7 +108,7 @@
   /// generated.
   extern bool DisableJumpTables;
 
-  /// EnableFastISel - This flag enables fast-path instruction selection
+  /// FastISel - This flag enables fast-path instruction selection
   /// which trades away generated code quality in favor of reducing
   /// compile time.
   extern bool EnableFastISel;

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon Apr 27 20:04:53 2009
@@ -42,8 +42,8 @@
 
 char AsmPrinter::ID = 0;
 AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
-                       const TargetAsmInfo *T, unsigned OL, bool VDef)
-  : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
+                       const TargetAsmInfo *T, bool F, bool VDef)
+  : MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o),
     TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
     IsInTextSection(false)
 {

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Mon Apr 27 20:04:53 2009
@@ -3351,7 +3351,7 @@
   }
 
   /// ValidDebugInfo - Return true if V represents valid debug info value.
-  bool ValidDebugInfo(Value *V, unsigned OptLevel) {
+  bool ValidDebugInfo(Value *V, bool FastISel) {
     if (!V)
       return false;
 
@@ -3393,7 +3393,7 @@
     case DW_TAG_lexical_block:
       /// FIXME. This interfers with the qualitfy of generated code when 
       /// during optimization.
-      if (OptLevel != 0)
+      if (FastISel == false)
         return false;
     default:
       break;
@@ -3574,6 +3574,7 @@
       return 0;
 
     SmallVector<DbgScope *, 2> &Scopes = I->second;
+    if (Scopes.empty()) return 0;
     DbgScope *Scope = Scopes.back(); Scopes.pop_back();
     unsigned ID = MMI->NextLabelID();
     MMI->RecordUsedDbgLabel(ID);
@@ -4730,8 +4731,8 @@
 }
 
 /// ValidDebugInfo - Return true if V represents valid debug info value.
-bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
-  return DD && DD->ValidDebugInfo(V, OptLevel);
+bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) {
+  return DD && DD->ValidDebugInfo(V, FastISel);
 }
 
 /// RecordSourceLine - Records location information and associates it with a 

Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Mon Apr 27 20:04:53 2009
@@ -55,9 +55,9 @@
 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                        raw_ostream &Out,
                                        CodeGenFileType FileType,
-                                       unsigned OptLevel) {
+                                       bool Fast) {
   // Add common CodeGen passes.
-  if (addCommonCodeGenPasses(PM, OptLevel))
+  if (addCommonCodeGenPasses(PM, Fast))
     return FileModel::Error;
 
   // Fold redundant debug labels.
@@ -66,17 +66,17 @@
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
+  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (OptLevel != 0)
+  if (!Fast)
     PM.add(createLoopAlignerPass());
 
   switch (FileType) {
   default:
     break;
   case TargetMachine::AssemblyFile:
-    if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
+    if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(), Out))
       return FileModel::Error;
     return FileModel::AsmFile;
   case TargetMachine::ObjectFile:
@@ -94,9 +94,9 @@
 /// finish up adding passes to emit the file, if necessary.
 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
                                                   MachineCodeEmitter *MCE,
-                                                  unsigned OptLevel) {
+                                                  bool Fast) {
   if (MCE)
-    addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
+    addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
 
   PM.add(createGCInfoDeleter());
 
@@ -114,15 +114,15 @@
 ///
 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
                                                    MachineCodeEmitter &MCE,
-                                                   unsigned OptLevel) {
+                                                   bool Fast) {
   // Add common CodeGen passes.
-  if (addCommonCodeGenPasses(PM, OptLevel))
+  if (addCommonCodeGenPasses(PM, Fast))
     return true;
 
-  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
+  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
+  addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
 
   PM.add(createGCInfoDeleter());
 
@@ -135,12 +135,11 @@
 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
 /// both emitting to assembly files or machine code output.
 ///
-bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
-                                               unsigned OptLevel) {
+bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
   // Standard LLVM-Level Passes.
 
   // Run loop strength reduction before anything else.
-  if (OptLevel != 0) {
+  if (!Fast) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     if (PrintLSR)
       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
@@ -154,7 +153,7 @@
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
-  if (OptLevel != 0)
+  if (!Fast)
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
   PM.add(createStackProtectorPass(getTargetLowering()));
@@ -168,38 +167,38 @@
 
   // Enable FastISel with -fast, but allow that to be overridden.
   if (EnableFastISelOption == cl::BOU_TRUE ||
-      (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
+      (Fast && EnableFastISelOption != cl::BOU_FALSE))
     EnableFastISel = true;
 
   // Ask the target for an isel.
-  if (addInstSelector(PM, OptLevel))
+  if (addInstSelector(PM, Fast))
     return true;
 
   // Print the instruction selected machine code...
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (OptLevel != 0) {
+  if (!Fast) {
     PM.add(createMachineLICMPass());
     PM.add(createMachineSinkingPass());
   }
 
   // Run pre-ra passes.
-  if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
+  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Perform register allocation.
   PM.add(createRegisterAllocator());
 
   // Perform stack slot coloring.
-  if (OptLevel != 0)
+  if (!Fast)
     PM.add(createStackSlotColoringPass());
 
   if (PrintMachineCode)  // Print the register-allocated code
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Run post-ra passes.
-  if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
+  if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   if (PrintMachineCode)
@@ -217,7 +216,7 @@
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Second pass scheduler.
-  if (OptLevel != 0 && !DisablePostRAScheduler) {
+  if (!Fast && !DisablePostRAScheduler) {
     PM.add(createPostRAScheduler());
 
     if (PrintMachineCode)
@@ -225,7 +224,7 @@
   }
 
   // Branch folding must be run after regalloc and prolog/epilog insertion.
-  if (OptLevel != 0)
+  if (!Fast)
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 
   if (PrintMachineCode)

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 27 20:04:53 2009
@@ -57,9 +57,9 @@
     SelectionDAG &DAG;
     const TargetLowering &TLI;
     CombineLevel Level;
-    unsigned OptLevel;
     bool LegalOperations;
     bool LegalTypes;
+    bool Fast;
 
     // Worklist of all of the nodes that need to be simplified.
     std::vector<SDNode*> WorkList;
@@ -254,13 +254,13 @@
     }
 
 public:
-    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
+    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
       : DAG(D),
         TLI(D.getTargetLoweringInfo()),
         Level(Unrestricted),
-        OptLevel(OL),
         LegalOperations(false),
         LegalTypes(false),
+        Fast(fast),
         AA(A) {}
 
     /// Run - runs the dag combiner on all nodes in the work list
@@ -4784,7 +4784,7 @@
   SDValue Ptr   = LD->getBasePtr();
 
   // Try to infer better alignment information than the load already has.
-  if (OptLevel != 0 && LD->isUnindexed()) {
+  if (!Fast && LD->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > LD->getAlignment())
         return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
@@ -4904,7 +4904,7 @@
   SDValue Ptr   = ST->getBasePtr();
 
   // Try to infer better alignment information than the store already has.
-  if (OptLevel != 0 && ST->isUnindexed()) {
+  if (!Fast && ST->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > ST->getAlignment())
         return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
@@ -6084,9 +6084,8 @@
 
 // SelectionDAG::Combine - This is the entry point for the file.
 //
-void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
-                           unsigned OptLevel) {
+void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) {
   /// run - This is the main entry point to this class.
   ///
-  DAGCombiner(*this, AA, OptLevel).Run(Level);
+  DAGCombiner(*this, AA, Fast).Run(Level);
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Apr 27 20:04:53 2009
@@ -327,7 +327,7 @@
   default: break;
   case Intrinsic::dbg_stoppoint: {
     DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
-    if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
+    if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) {
       DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
       std::string Dir, FN;
       unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
@@ -344,7 +344,7 @@
   }
   case Intrinsic::dbg_region_start: {
     DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
-    if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
+    if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) {
       unsigned ID = 
         DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
@@ -354,7 +354,7 @@
   }
   case Intrinsic::dbg_region_end: {
     DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
-    if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
+    if (DW && DW->ValidDebugInfo(REI->getContext(), true)) {
      unsigned ID = 0;
      DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
      if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
@@ -380,7 +380,7 @@
     DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
     Value *SP = FSI->getSubprogram();
 
-    if (DW->ValidDebugInfo(SP, 0)) {
+    if (DW->ValidDebugInfo(SP, true)) {
       // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
       // (most?) gdb expects.
       DebugLoc PrevLoc = DL;
@@ -425,7 +425,7 @@
   case Intrinsic::dbg_declare: {
     DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
     Value *Variable = DI->getVariable();
-    if (DW && DW->ValidDebugInfo(Variable, 0)) {
+    if (DW && DW->ValidDebugInfo(Variable, true)) {
       // Determine the address of the declared object.
       Value *Address = DI->getAddress();
       if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 27 20:04:53 2009
@@ -55,8 +55,8 @@
 class VISIBILITY_HIDDEN SelectionDAGLegalize {
   TargetLowering &TLI;
   SelectionDAG &DAG;
-  unsigned OptLevel;
   bool TypesNeedLegalizing;
+  bool Fast;
 
   // Libcall insertion helpers.
 
@@ -139,7 +139,7 @@
 
 public:
   explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
-                                unsigned ol);
+                                bool fast);
 
   /// getTypeAction - Return how we should legalize values of this type, either
   /// it is already legal or we need to expand it into multiple registers of
@@ -345,9 +345,9 @@
 }
 
 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
-                                           bool types, unsigned ol)
-  : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
-    TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) {
+                                           bool types, bool fast)
+  : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
+    Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
   assert(MVT::LAST_VALUETYPE <= 32 &&
          "Too many value types for ValueTypeActions to hold!");
 }
@@ -1271,7 +1271,7 @@
         unsigned Line = DSP->getLine();
         unsigned Col = DSP->getColumn();
 
-        if (OptLevel == 0) {
+        if (Fast) {
           // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
           // won't hurt anything.
           if (useDEBUG_LOC) {
@@ -8566,9 +8566,9 @@
 
 // SelectionDAG::Legalize - This is the entry point for the file.
 //
-void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) {
+void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
   /// run - This is the main entry point to this class.
   ///
-  SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG();
+  SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG();
 }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Mon Apr 27 20:04:53 2009
@@ -630,6 +630,6 @@
 //===----------------------------------------------------------------------===//
 
 llvm::ScheduleDAGSDNodes *
-llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
   return new ScheduleDAGFast(*IS->MF);
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon Apr 27 20:04:53 2009
@@ -261,7 +261,7 @@
 /// new hazard recognizer. This scheduler takes ownership of the hazard
 /// recognizer and deletes it when done.
 ScheduleDAGSDNodes *
-llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) {
   return new ScheduleDAGList(*IS->MF,
                              new LatencyPriorityQueue(),
                              IS->CreateTargetHazardRecognizer());

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Apr 27 20:04:53 2009
@@ -1505,7 +1505,7 @@
 //===----------------------------------------------------------------------===//
 
 llvm::ScheduleDAGSDNodes *
-llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
   const TargetMachine &TM = IS->TM;
   const TargetInstrInfo *TII = TM.getInstrInfo();
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
@@ -1519,7 +1519,7 @@
 }
 
 llvm::ScheduleDAGSDNodes *
-llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
   const TargetMachine &TM = IS->TM;
   const TargetInstrInfo *TII = TM.getInstrInfo();
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Apr 27 20:04:53 2009
@@ -3910,9 +3910,9 @@
   case Intrinsic::dbg_stoppoint: {
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
-    if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
+    if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
       MachineFunction &MF = DAG.getMachineFunction();
-      if (OptLevel == 0)
+      if (Fast)
         DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
                                         SPI.getLine(),
                                         SPI.getColumn(),
@@ -3930,8 +3930,7 @@
   case Intrinsic::dbg_region_start: {
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
-
-    if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) {
+    if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
       unsigned LabelID =
         DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
       DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
@@ -3943,8 +3942,8 @@
   case Intrinsic::dbg_region_end: {
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
+    if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
 
-    if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) {
       MachineFunction &MF = DAG.getMachineFunction();
       DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
       std::string SPName;
@@ -3953,7 +3952,7 @@
           && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
           // This is end of inlined function. Debugging information for
           // inlined function is not handled yet (only supported by FastISel).
-        if (OptLevel == 0) {
+        if (Fast) {
           unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
           if (ID != 0)
             // Returned ID is 0 if this is unbalanced "end of inlined
@@ -3979,9 +3978,9 @@
     if (!DW) return 0;
     DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
     Value *SP = FSI.getSubprogram();
-    if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
-      MachineFunction &MF = DAG.getMachineFunction();
-      if (OptLevel == 0) {
+    if (SP && DW->ValidDebugInfo(SP, Fast)) {
+        MachineFunction &MF = DAG.getMachineFunction();
+      if (Fast) {
         // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
         // (most?) gdb expects.
         DebugLoc PrevLoc = CurDebugLoc;
@@ -4052,11 +4051,11 @@
     return 0;
   }
   case Intrinsic::dbg_declare: {
-    if (OptLevel == 0) {
+    if (Fast) {
       DwarfWriter *DW = DAG.getDwarfWriter();
       DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
       Value *Variable = DI.getVariable();
-      if (DW && DW->ValidDebugInfo(Variable, OptLevel))
+      if (DW && DW->ValidDebugInfo(Variable, Fast))
         DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
                                 getValue(DI.getAddress()), getValue(Variable)));
     } else {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Mon Apr 27 20:04:53 2009
@@ -355,17 +355,17 @@
   ///
   FunctionLoweringInfo &FuncInfo;
 
-  /// OptLevel - What optimization level we're generating code for.
+  /// Fast - We are in -fast mode.
   /// 
-  unsigned OptLevel;
+  bool Fast;
   
   /// GFI - Garbage collection metadata for the function.
   GCFunctionInfo *GFI;
 
   SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
-                       FunctionLoweringInfo &funcinfo, unsigned ol)
+                       FunctionLoweringInfo &funcinfo, bool fast)
     : CurDebugLoc(DebugLoc::getUnknownLoc()), 
-      TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
+      TLI(tli), DAG(dag), FuncInfo(funcinfo), Fast(fast) {
   }
 
   void init(GCFunctionInfo *gfi, AliasAnalysis &aa);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 27 20:04:53 2009
@@ -136,16 +136,16 @@
   /// createDefaultScheduler - This creates an instruction scheduler appropriate
   /// for the target.
   ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
-                                             unsigned OptLevel) {
+                                             bool Fast) {
     const TargetLowering &TLI = IS->getTargetLowering();
 
-    if (OptLevel == 0)
-      return createFastDAGScheduler(IS, OptLevel);
+    if (Fast)
+      return createFastDAGScheduler(IS, Fast);
     if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
-      return createTDListDAGScheduler(IS, OptLevel);
+      return createTDListDAGScheduler(IS, Fast);
     assert(TLI.getSchedulingPreference() ==
          TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
-    return createBURRListDAGScheduler(IS, OptLevel);
+    return createBURRListDAGScheduler(IS, Fast);
   }
 }
 
@@ -262,13 +262,13 @@
 // SelectionDAGISel code
 //===----------------------------------------------------------------------===//
 
-SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
+SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
   FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
   FuncInfo(new FunctionLoweringInfo(TLI)),
   CurDAG(new SelectionDAG(TLI, *FuncInfo)),
-  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)),
+  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)),
   GFI(),
-  OptLevel(OL),
+  Fast(fast),
   DAGSize(0)
 {}
 
@@ -576,9 +576,9 @@
   // Run the DAG combiner in pre-legalize mode.
   if (TimePassesIsEnabled) {
     NamedRegionTimer T("DAG Combining 1", GroupName);
-    CurDAG->Combine(Unrestricted, *AA, OptLevel);
+    CurDAG->Combine(Unrestricted, *AA, Fast);
   } else {
-    CurDAG->Combine(Unrestricted, *AA, OptLevel);
+    CurDAG->Combine(Unrestricted, *AA, Fast);
   }
   
   DOUT << "Optimized lowered selection DAG:\n";
@@ -608,9 +608,9 @@
       // Run the DAG combiner in post-type-legalize mode.
       if (TimePassesIsEnabled) {
         NamedRegionTimer T("DAG Combining after legalize types", GroupName);
-        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
+        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
       } else {
-        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
+        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
       }
 
       DOUT << "Optimized type-legalized selection DAG:\n";
@@ -622,9 +622,9 @@
 
   if (TimePassesIsEnabled) {
     NamedRegionTimer T("DAG Legalization", GroupName);
-    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
+    CurDAG->Legalize(DisableLegalizeTypes, Fast);
   } else {
-    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
+    CurDAG->Legalize(DisableLegalizeTypes, Fast);
   }
   
   DOUT << "Legalized selection DAG:\n";
@@ -635,9 +635,9 @@
   // Run the DAG combiner in post-legalize mode.
   if (TimePassesIsEnabled) {
     NamedRegionTimer T("DAG Combining 2", GroupName);
-    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
+    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
   } else {
-    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
+    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
   }
   
   DOUT << "Optimized legalized selection DAG:\n";
@@ -645,7 +645,7 @@
 
   if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
   
-  if (OptLevel != 0)
+  if (!Fast)
     ComputeLiveOutVRegInfo();
 
   // Third, instruction select all of the operations to machine code, adding the
@@ -1082,7 +1082,7 @@
     RegisterScheduler::setDefault(Ctor);
   }
   
-  return Ctor(this, OptLevel);
+  return Ctor(this, Fast);
 }
 
 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {

Modified: llvm/trunk/lib/Target/ARM/ARM.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.h (original)
+++ llvm/trunk/lib/Target/ARM/ARM.h Mon Apr 27 20:04:53 2009
@@ -91,7 +91,7 @@
 FunctionPass *createARMISelDag(ARMTargetMachine &TM);
 FunctionPass *createARMCodePrinterPass(raw_ostream &O,
                                        ARMTargetMachine &TM,
-                                       unsigned OptLevel, bool Verbose);
+                                       bool Fast, bool Verbose);
 FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
                                        MachineCodeEmitter &MCE);
 FunctionPass *createARMLoadStoreOptimizationPass();

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Mon Apr 27 20:04:53 2009
@@ -138,37 +138,35 @@
 
 
 // Pass Pipeline Configuration
-bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   PM.add(createARMISelDag(*this));
   return false;
 }
 
-bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
+bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
   // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
-  if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
+  if (!Fast && !DisableLdStOpti && !Subtarget.isThumb())
     PM.add(createARMLoadStoreOptimizationPass());
 
-  if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
+  if (!Fast && !DisableIfConversion && !Subtarget.isThumb())
     PM.add(createIfConverterPass());
 
   PM.add(createARMConstantIslandPass());
   return true;
 }
 
-bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                          unsigned OptLevel,
-                                          bool Verbose,
-                                          raw_ostream &Out) {
+bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
+                                          bool Verbose, raw_ostream &Out) {
   // Output assembly language.
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
   if (AsmPrinterCtor)
-    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
+    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
 
   return false;
 }
 
 
-bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // FIXME: Move this to TargetJITInfo!
   if (DefRelocModel == Reloc::Default)
@@ -179,22 +177,20 @@
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
   }
 
   return false;
 }
 
-bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel,
-                                            bool DumpAsm,
-                                            MachineCodeEmitter &MCE) {
+bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+                                        bool DumpAsm, MachineCodeEmitter &MCE) {
   // Machine code emitter pass for ARM.
   PM.add(createARMCodeEmitterPass(*this, MCE));
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
   }
 
   return false;

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Mon Apr 27 20:04:53 2009
@@ -41,7 +41,7 @@
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             ARMTargetMachine &tm,
-                                            unsigned OptLevel, bool verbose);
+                                            bool fast, bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -69,13 +69,13 @@
   virtual const TargetAsmInfo *createTargetAsmInfo() const;
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
 };
 

Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Mon Apr 27 20:04:53 2009
@@ -80,9 +80,9 @@
     /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
     bool InCPMode;
   public:
-    explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                           const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
+    ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                  const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
         InCPMode(false) {
       Subtarget = &TM.getSubtarget<ARMSubtarget>();
     }
@@ -1061,8 +1061,8 @@
 ///
 FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
                                              ARMTargetMachine &tm,
-                                             unsigned OptLevel, bool verbose) {
-  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                             bool fast, bool verbose) {
+  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }
 
 namespace {

Modified: llvm/trunk/lib/Target/Alpha/Alpha.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/Alpha.h (original)
+++ llvm/trunk/lib/Target/Alpha/Alpha.h Mon Apr 27 20:04:53 2009
@@ -26,7 +26,7 @@
   FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
   FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
                                            TargetMachine &TM,
-                                           unsigned OptLevel, bool Verbose);
+                                           bool Fast, bool Verbose);
   FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
   FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
                                            MachineCodeEmitter &MCE);

Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Mon Apr 27 20:04:53 2009
@@ -76,34 +76,31 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
-                                         unsigned OptLevel) {
+bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   PM.add(createAlphaISelDag(*this));
   return false;
 }
-bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
-                                        unsigned OptLevel) {
+bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
   // Must run branch selection immediately preceding the asm printer
   PM.add(createAlphaBranchSelectionPass());
   return false;
 }
-bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel,
+bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
                                             bool Verbose,
                                             raw_ostream &Out) {
   PM.add(createAlphaLLRPPass(*this));
-  PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
+  PM.add(createAlphaCodePrinterPass(Out, *this, Fast, Verbose));
   return false;
 }
-bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
                                         bool DumpAsm, MachineCodeEmitter &MCE) {
   PM.add(createAlphaCodeEmitterPass(*this, MCE));
   if (DumpAsm)
-    PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel, true));
+    PM.add(createAlphaCodePrinterPass(errs(), *this, Fast, true));
   return false;
 }
 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
-                                              unsigned OptLevel, bool DumpAsm,
+                                              bool Fast, bool DumpAsm,
                                               MachineCodeEmitter &MCE) {
-  return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
+  return addCodeEmitter(PM, Fast, DumpAsm, MCE);
 }

Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Mon Apr 27 20:04:53 2009
@@ -58,13 +58,13 @@
   static unsigned getModuleMatchQuality(const Module &M);
   
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
 };
 

Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Mon Apr 27 20:04:53 2009
@@ -36,9 +36,9 @@
     /// Unique incrementer for label values for referencing Global values.
     ///
 
-    explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
-                             const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(o, tm, T, OL, V) {}
+    AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
+                    const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(o, tm, T, F, V) {}
 
     virtual const char *getPassName() const {
       return "Alpha Assembly Printer";
@@ -68,9 +68,8 @@
 ///
 FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
                                                TargetMachine &tm,
-                                               unsigned OptLevel,
-                                               bool verbose) {
-  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                               bool fast, bool verbose) {
+  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }
 
 #include "AlphaGenAsmWriter.inc"

Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
+++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Apr 27 20:04:53 2009
@@ -3587,7 +3587,7 @@
 bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
                                               raw_ostream &o,
                                               CodeGenFileType FileType,
-                                              unsigned OptLevel) {
+                                              bool Fast) {
   if (FileType != TargetMachine::AssemblyFile) return true;
 
   PM.add(createGCLoweringPass());

Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Mon Apr 27 20:04:53 2009
@@ -27,8 +27,7 @@
 
   virtual bool WantsWholeFile() const { return true; }
   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
-                                        CodeGenFileType FileType,
-                                        unsigned OptLevel);
+                                        CodeGenFileType FileType, bool Fast);
 
   // This class always works, but must be requested explicitly on 
   // llc command line.

Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Mon Apr 27 20:04:53 2009
@@ -48,9 +48,9 @@
   class VISIBILITY_HIDDEN SPUAsmPrinter : public AsmPrinter {
     std::set<std::string> FnStubs, GVStubs;
   public:
-    explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                           const TargetAsmInfo *T, unsigned OL, bool V) :
-      AsmPrinter(O, TM, T, OL, V) {}
+    SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                  const TargetAsmInfo *T, bool F, bool V) :
+      AsmPrinter(O, TM, T, F, V) {}
 
     virtual const char *getPassName() const {
       return "STI CBEA SPU Assembly Printer";
@@ -615,6 +615,6 @@
 ///
 FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
                                             SPUTargetMachine &tm,
-                                            unsigned OptLevel, bool verbose) {
-  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                            bool fast, bool verbose) {
+  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }

Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPU.h Mon Apr 27 20:04:53 2009
@@ -25,7 +25,7 @@
   FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
   FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
                                         SPUTargetMachine &tm,
-                                        unsigned OptLevel, bool verbose);
+                                        bool fast, bool verbose);
 
   /*--== Utility functions/predicates/etc used all over the place: --==*/
   //! Predicate test for a signed 10-bit value

Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Mon Apr 27 20:04:53 2009
@@ -81,17 +81,15 @@
 //===----------------------------------------------------------------------===//
 
 bool
-SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel)
+SPUTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast)
 {
   // Install an instruction selector.
   PM.add(createSPUISelDag(*this));
   return false;
 }
 
-bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                          unsigned OptLevel,
-                                          bool Verbose,
-                                          raw_ostream &Out) {
-  PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
+bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+                                          bool Verbose, raw_ostream &Out) {
+  PM.add(createSPUAsmPrinterPass(Out, *this, Fast, Verbose));
   return false;
 }

Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Mon Apr 27 20:04:53 2009
@@ -83,9 +83,9 @@
   }
   
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
-                                  bool Verbose, raw_ostream &Out);
+  virtual bool addInstSelector(PassManagerBase &PM, bool /*Fast*/);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool /*Fast*/, 
+                                  bool /*Verbose*/, raw_ostream &Out);
 };
 
 } // end namespace llvm

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Mon Apr 27 20:04:53 2009
@@ -1995,7 +1995,7 @@
 bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
                                                 raw_ostream &o,
                                                 CodeGenFileType FileType,
-                                                unsigned OptLevel) {
+                                                bool Fast) {
   if (FileType != TargetMachine::AssemblyFile) return true;
   PM.add(new CppWriter(o));
   return false;

Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Mon Apr 27 20:04:53 2009
@@ -29,8 +29,7 @@
 
   virtual bool WantsWholeFile() const { return true; }
   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
-                                        CodeGenFileType FileType,
-                                        unsigned OptLevel);
+                                        CodeGenFileType FileType, bool Fast);
 
   // This class always works, but shouldn't be the default in most cases.
   static unsigned getModuleMatchQuality(const Module &M) { return 1; }

Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Mon Apr 27 20:04:53 2009
@@ -37,9 +37,9 @@
   class IA64AsmPrinter : public AsmPrinter {
     std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
   public:
-    explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
-                            const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V) {}
+    IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
+                   const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V) {}
 
     virtual const char *getPassName() const {
       return "IA64 Assembly Printer";
@@ -370,7 +370,6 @@
 ///
 FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
                                               IA64TargetMachine &tm,
-                                              unsigned OptLevel,
-                                              bool verbose) {
-  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                              bool fast, bool verbose) {
+  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }

Modified: llvm/trunk/lib/Target/IA64/IA64.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64.h Mon Apr 27 20:04:53 2009
@@ -37,7 +37,7 @@
 ///
 FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
                                         IA64TargetMachine &tm,
-                                        unsigned OptLevel, bool verbose);
+                                        bool fast, bool verbose);
 
 } // End llvm namespace
 

Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Mon Apr 27 20:04:53 2009
@@ -72,21 +72,19 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLEvel){
+bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   PM.add(createIA64DAGToDAGInstructionSelector(*this));
   return false;
 }
 
-bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
+bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
   // Make sure everything is bundled happily
   PM.add(createIA64BundlingPass(*this));
   return true;
 }
-bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                           unsigned OptLevel,
-                                           bool Verbose,
-                                           raw_ostream &Out) {
-  PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
+bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+                                           bool Verbose, raw_ostream &Out) {
+  PM.add(createIA64CodePrinterPass(Out, *this, Fast, Verbose));
   return false;
 }
 

Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64TargetMachine.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.h Mon Apr 27 20:04:53 2009
@@ -51,9 +51,9 @@
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                   bool Verbose, raw_ostream &Out);
 };
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
+++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Mon Apr 27 20:04:53 2009
@@ -35,8 +35,7 @@
 
     virtual bool WantsWholeFile() const { return true; }
     virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
-                                          CodeGenFileType FileType,
-                                          unsigned OptLevel);
+                                         CodeGenFileType FileType, bool Fast);
 
     // This class always works, but shouldn't be the default in most cases.
     static unsigned getModuleMatchQuality(const Module &M) { return 1; }
@@ -1663,8 +1662,7 @@
 //===----------------------------------------------------------------------===//
 
 bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o,
-                                          CodeGenFileType FileType,
-                                          unsigned OptLevel)
+                                          CodeGenFileType FileType, bool Fast)
 {
   if (FileType != TargetMachine::AssemblyFile) return true;
   MSILWriter* Writer = new MSILWriter(o);

Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Mon Apr 27 20:04:53 2009
@@ -49,9 +49,9 @@
   class VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
     const MipsSubtarget *Subtarget;
   public:
-    explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM, 
-                            const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V) {
+    MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM, 
+                   const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V) {
       Subtarget = &TM.getSubtarget<MipsSubtarget>();
     }
 
@@ -91,8 +91,8 @@
 /// regardless of whether the function is in SSA form.
 FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
                                               MipsTargetMachine &tm,
-                                              unsigned OptLevel, bool verbose) {
-  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                              bool fast, bool verbose) {
+  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/Mips/Mips.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.h (original)
+++ llvm/trunk/lib/Target/Mips/Mips.h Mon Apr 27 20:04:53 2009
@@ -25,7 +25,7 @@
   FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
   FunctionPass *createMipsCodePrinterPass(raw_ostream &OS, 
                                           MipsTargetMachine &TM,
-                                          unsigned OptLevel, bool Verbose);
+                                          bool Fast, bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for Mips registers.  This defines a mapping from

Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Mon Apr 27 20:04:53 2009
@@ -105,7 +105,7 @@
 // Install an instruction selector pass using 
 // the ISelDag to gen Mips code.
 bool MipsTargetMachine::
-addInstSelector(PassManagerBase &PM, unsigned OptLevel) 
+addInstSelector(PassManagerBase &PM, bool Fast) 
 {
   PM.add(createMipsISelDag(*this));
   return false;
@@ -115,7 +115,7 @@
 // machine code is emitted. return true if -print-machineinstrs should 
 // print out the code after the passes.
 bool MipsTargetMachine::
-addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) 
+addPreEmitPass(PassManagerBase &PM, bool Fast) 
 {
   PM.add(createMipsDelaySlotFillerPass(*this));
   return true;
@@ -124,10 +124,10 @@
 // Implements the AssemblyEmitter for the target. Must return
 // true if AssemblyEmitter is supported
 bool MipsTargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                    bool Verbose, raw_ostream &Out) 
 {
   // Output assembly language.
-  PM.add(createMipsCodePrinterPass(Out, *this, OptLevel, Verbose));
+  PM.add(createMipsCodePrinterPass(Out, *this, Fast, Verbose));
   return false;
 }

Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Mon Apr 27 20:04:53 2009
@@ -57,9 +57,9 @@
     static unsigned getModuleMatchQuality(const Module &M);
 
     // Pass Pipeline Configuration
-    virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-    virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-    virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+    virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+    virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
+    virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                     bool Verbose, raw_ostream &Out);
   };
 

Modified: llvm/trunk/lib/Target/PIC16/PIC16.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16.h Mon Apr 27 20:04:53 2009
@@ -75,7 +75,7 @@
   FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
   FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS, 
                                            PIC16TargetMachine &TM,
-                                           unsigned OptLevel, bool Verbose);
+                                           bool Fast, bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for PIC16 registers.  This defines a mapping from

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Mon Apr 27 20:04:53 2009
@@ -161,9 +161,8 @@
 ///
 FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
                                                PIC16TargetMachine &tm,
-                                               unsigned OptLevel,
-                                               bool verbose) {
-  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                               bool fast, bool verbose) {
+  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }
 
 void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Mon Apr 27 20:04:53 2009
@@ -24,9 +24,9 @@
 
 namespace llvm {
   struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
-    explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
-                             const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V) {
+  PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
+                    const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V) {
       CurBank = "";
       FunctionLabelBegin = '@';
       IsRomData = false;

Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Mon Apr 27 20:04:53 2009
@@ -55,18 +55,17 @@
   return new PIC16TargetAsmInfo(*this);
 }
 
-bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
-                                         unsigned OptLevel) {
+bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   // Install an instruction selector.
   PM.add(createPIC16ISelDag(*this));
   return false;
 }
 
 bool PIC16TargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose,
+addAssemblyEmitter(PassManagerBase &PM, bool Fast, bool Verbose,
                    raw_ostream &Out) {
   // Output assembly language.
-  PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
+  PM.add(createPIC16CodePrinterPass(Out, *this, Fast, Verbose));
   return false;
 }
 

Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h Mon Apr 27 20:04:53 2009
@@ -57,8 +57,8 @@
     return const_cast<PIC16TargetLowering*>(&TLInfo); 
   }
 
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
                                   bool Verbose, raw_ostream &Out);
 }; // PIC16TargetMachine.
 

Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Mon Apr 27 20:04:53 2009
@@ -54,9 +54,9 @@
     StringSet<> FnStubs, GVStubs, HiddenGVStubs;
     const PPCSubtarget &Subtarget;
   public:
-    explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                           const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V),
+    PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                  const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V),
         Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
 
     virtual const char *getPassName() const {
@@ -297,9 +297,9 @@
     DwarfWriter *DW;
     MachineModuleInfo *MMI;
   public:
-    explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
-                                const TargetAsmInfo *T, unsigned OL, bool V)
-      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
+    PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
+                       const TargetAsmInfo *T, bool F, bool V)
+      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
 
     virtual const char *getPassName() const {
       return "Linux PPC Assembly Printer";
@@ -326,9 +326,9 @@
     MachineModuleInfo *MMI;
     raw_ostream &OS;
   public:
-    explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
-                                 const TargetAsmInfo *T, unsigned OL, bool V)
-      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
+    PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
+                        const TargetAsmInfo *T, bool F, bool V)
+      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0), OS(O) {}
 
     virtual const char *getPassName() const {
       return "Darwin PPC Assembly Printer";
@@ -1176,15 +1176,13 @@
 ///
 FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
                                             PPCTargetMachine &tm,
-                                            unsigned OptLevel, bool verbose) {
+                                            bool fast, bool verbose) {
   const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
 
   if (Subtarget->isDarwin()) {
-    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
-                                   OptLevel, verbose);
+    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
   } else {
-    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
-                                  OptLevel, verbose);
+    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
   }
 }
 

Modified: llvm/trunk/lib/Target/PowerPC/PPC.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPC.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPC.h Mon Apr 27 20:04:53 2009
@@ -28,7 +28,7 @@
 FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
 FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
                                       PPCTargetMachine &TM,
-                                      unsigned OptLevel, bool Verbose);
+                                      bool Fast, bool Verbose);
 FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
                                        MachineCodeEmitter &MCE);
 } // end namespace llvm;

Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Apr 27 20:04:53 2009
@@ -129,31 +129,29 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   // Install an instruction selector.
   PM.add(createPPCISelDag(*this));
   return false;
 }
 
-bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
+bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
   
   // Must run branch selection immediately preceding the asm printer.
   PM.add(createPPCBranchSelectionPass());
   return false;
 }
 
-bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                          unsigned OptLevel,
-                                          bool Verbose,
-                                          raw_ostream &Out) {
+bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+                                          bool Verbose, raw_ostream &Out) {
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
   if (AsmPrinterCtor)
-    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
+    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
 
   return false;
 }
 
-bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
   // FIXME: This should be moved to TargetJITInfo!!
@@ -178,20 +176,20 @@
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
   }
 
   return false;
 }
 
-bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
                                             bool DumpAsm, MachineCodeEmitter &MCE) {
   // Machine code emitter pass for PowerPC.
   PM.add(createPPCCodeEmitterPass(*this, MCE));
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
   }
 
   return false;

Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Mon Apr 27 20:04:53 2009
@@ -46,7 +46,7 @@
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             PPCTargetMachine &tm, 
-                                            unsigned OptLevel, bool verbose);
+                                            bool fast, bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -76,13 +76,13 @@
   }
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
   virtual bool getEnableTailMergeDefault() const;
 };

Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp Mon Apr 27 20:04:53 2009
@@ -48,9 +48,9 @@
     typedef std::map<const Value *, unsigned> ValueMapTy;
     ValueMapTy NumberForBB;
   public:
-    explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                             const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V) {}
+    SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                    const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V) {}
 
     virtual const char *getPassName() const {
       return "Sparc Assembly Printer";
@@ -82,9 +82,8 @@
 ///
 FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
                                                TargetMachine &tm,
-                                               unsigned OptLevel,
-                                               bool verbose) {
-  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                               bool fast, bool verbose) {
+  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }
 
 /// runOnMachineFunction - This uses the printInstruction()

Modified: llvm/trunk/lib/Target/Sparc/Sparc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/Sparc.h (original)
+++ llvm/trunk/lib/Target/Sparc/Sparc.h Mon Apr 27 20:04:53 2009
@@ -25,7 +25,7 @@
 
   FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
   FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM,
-                                           unsigned OptLevel, bool Verbose);
+                                           bool Fast, bool Verbose);
   FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
   FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
 } // end namespace llvm;

Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Mon Apr 27 20:04:53 2009
@@ -68,8 +68,7 @@
 #endif
 }
 
-bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
-                                         unsigned OptLevel) {
+bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   PM.add(createSparcISelDag(*this));
   return false;
 }
@@ -77,17 +76,15 @@
 /// addPreEmitPass - This pass may be implemented by targets that want to run
 /// passes immediately before machine code is emitted.  This should return
 /// true if -print-machineinstrs should print out the code after the passes.
-bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel){
+bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
   PM.add(createSparcFPMoverPass(*this));
   PM.add(createSparcDelaySlotFillerPass(*this));
   return true;
 }
 
-bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel,
-                                            bool Verbose,
-                                            raw_ostream &Out) {
+bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+                                            bool Verbose, raw_ostream &Out) {
   // Output assembly language.
-  PM.add(createSparcCodePrinterPass(Out, *this, OptLevel, Verbose));
+  PM.add(createSparcCodePrinterPass(Out, *this, Fast, Verbose));
   return false;
 }

Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Mon Apr 27 20:04:53 2009
@@ -51,9 +51,9 @@
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                   bool Verbose, raw_ostream &Out);
 };
 

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Mon Apr 27 20:04:53 2009
@@ -33,9 +33,9 @@
   MachineModuleInfo *MMI;
   const X86Subtarget *Subtarget;
  public:
-  explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
-                            const TargetAsmInfo *T, unsigned OL, bool V)
-    : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
+  X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
+                   const TargetAsmInfo *T, bool F, bool V)
+    : AsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {
     Subtarget = &TM.getSubtarget<X86Subtarget>();
   }
 

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Mon Apr 27 20:04:53 2009
@@ -25,15 +25,13 @@
 ///
 FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
                                              X86TargetMachine &tm,
-                                             unsigned OptLevel, bool verbose) {
+                                             bool fast, bool verbose) {
   const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
 
   if (Subtarget->isFlavorIntel()) {
-    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(),
-                                  OptLevel, verbose);
+    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
   } else {
-    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(),
-                                OptLevel, verbose);
+    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
   }
 }
 

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h Mon Apr 27 20:04:53 2009
@@ -25,9 +25,9 @@
 namespace llvm {
 
 struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
-  explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
-                              const TargetAsmInfo *T, unsigned OL, bool V)
-    : AsmPrinter(O, TM, T, OL, V) {}
+  X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
+                     const TargetAsmInfo *T, bool F, bool V)
+    : AsmPrinter(O, TM, T, F, V) {}
 
   virtual const char *getPassName() const {
     return "X86 Intel-Style Assembly Printer";

Modified: llvm/trunk/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86.h (original)
+++ llvm/trunk/lib/Target/X86/X86.h Mon Apr 27 20:04:53 2009
@@ -25,7 +25,7 @@
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned OptSize);
+FunctionPass *createX86ISelDag(X86TargetMachine &TM, bool Fast);
 
 /// createX86FloatingPointStackifierPass - This function returns a pass which
 /// converts floating point register references and pseudo instructions into
@@ -44,7 +44,7 @@
 ///
 FunctionPass *createX86CodePrinterPass(raw_ostream &o,
                                        X86TargetMachine &tm,
-                                       unsigned OptLevel, bool Verbose);
+                                       bool fast, bool Verbose);
 
 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
 /// to the specified MCE object.

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Apr 27 20:04:53 2009
@@ -134,8 +134,8 @@
     bool OptForSize;
 
   public:
-    explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
-      : SelectionDAGISel(tm, OptLevel),
+    X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
+      : SelectionDAGISel(tm, fast),
         TM(tm), X86Lowering(*TM.getTargetLowering()),
         Subtarget(&TM.getSubtarget<X86Subtarget>()),
         OptForSize(false) {}
@@ -306,7 +306,7 @@
 
 bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
                                                  SDNode *Root) const {
-  if (OptLevel == 0) return false;
+  if (Fast) return false;
 
   if (U == Root)
     switch (U->getOpcode()) {
@@ -512,7 +512,7 @@
 
 
 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
-/// This is only run if not in -O0 mode.
+/// This is only run if not in -fast mode (aka -O0).
 /// This allows the instruction selector to pick more read-modify-write
 /// instructions. This is a common case:
 ///
@@ -714,10 +714,10 @@
   OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
 
   DEBUG(BB->dump());
-  if (OptLevel != 0)
+  if (!Fast)
     PreprocessForRMW();
 
-  // FIXME: This should only happen when not compiled with -O0.
+  // FIXME: This should only happen when not -fast.
   PreprocessForFPConvert();
 
   // Codegen the basic block.
@@ -1744,6 +1744,6 @@
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned OptLevel) {
-  return new X86DAGToDAGISel(TM, OptLevel);
+FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
+  return new X86DAGToDAGISel(TM, Fast);
 }

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Apr 27 20:04:53 2009
@@ -180,9 +180,9 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   // Install an instruction selector.
-  PM.add(createX86ISelDag(*this, OptLevel));
+  PM.add(createX86ISelDag(*this, Fast));
 
   // If we're using Fast-ISel, clean up the mess.
   if (EnableFastISel)
@@ -194,29 +194,27 @@
   return false;
 }
 
-bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, bool Fast) {
   // Calculate and set max stack object alignment early, so we can decide
   // whether we will need stack realignment (and thus FP).
   PM.add(createX86MaxStackAlignmentCalculatorPass());
   return false;  // -print-machineinstr shouldn't print after this.
 }
 
-bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, bool Fast) {
   PM.add(createX86FloatingPointStackifierPass());
   return true;  // -print-machineinstr should print after this.
 }
 
-bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                          unsigned OptLevel,
-                                          bool Verbose,
-                                          raw_ostream &Out) {
+bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+                                          bool Verbose, raw_ostream &Out) {
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
   if (AsmPrinterCtor)
-    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
+    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
   return false;
 }
 
-bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // FIXME: Move this to TargetJITInfo!
   // On Darwin, do not override 64-bit setting made in X86TargetMachine().
@@ -238,20 +236,19 @@
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
   }
 
   return false;
 }
 
-bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel, bool DumpAsm,
-                                            MachineCodeEmitter &MCE) {
+bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+                                        bool DumpAsm, MachineCodeEmitter &MCE) {
   PM.add(createX86CodeEmitterPass(*this, MCE));
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
   }
 
   return false;

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Mon Apr 27 20:04:53 2009
@@ -45,7 +45,7 @@
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             X86TargetMachine &tm,
-                                            unsigned OptLevel, bool verbose);
+                                            bool fast, bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -74,14 +74,14 @@
   }
 
   // Set up the pass pipeline.
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addPreRegAlloc(PassManagerBase &PM, bool Fast);
+  virtual bool addPostRegAlloc(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
 
   /// symbolicAddressesAreRIPRel - Return true if symbolic addresses are

Modified: llvm/trunk/lib/Target/XCore/XCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCore.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCore.h (original)
+++ llvm/trunk/lib/Target/XCore/XCore.h Mon Apr 27 20:04:53 2009
@@ -24,7 +24,7 @@
   FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
   FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
                                            XCoreTargetMachine &TM,
-                                           unsigned OptLevel, bool Verbose);
+                                           bool Fast, bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for XCore registers.  This defines a mapping from

Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Mon Apr 27 20:04:53 2009
@@ -58,8 +58,8 @@
     const XCoreSubtarget &Subtarget;
   public:
     XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
-                    const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V), DW(0),
+                    const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V), DW(0),
         Subtarget(*TM.getSubtargetImpl()) {}
 
     virtual const char *getPassName() const {
@@ -105,9 +105,8 @@
 ///
 FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
                                                XCoreTargetMachine &tm,
-                                               unsigned OptLevel,
-                                               bool verbose) {
-  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                               bool fast, bool verbose) {
+  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }
 
 // PrintEscapedString - Print each character of the specified string, escaping

Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Mon Apr 27 20:04:53 2009
@@ -55,17 +55,14 @@
   return 0;
 }
 
-bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
-                                         unsigned OptLevel) {
+bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   PM.add(createXCoreISelDag(*this));
   return false;
 }
 
-bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel,
-                                            bool Verbose,
-                                            raw_ostream &Out) {
+bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+                                            bool Verbose, raw_ostream &Out) {
   // Output assembly language.
-  PM.add(createXCoreCodePrinterPass(Out, *this, OptLevel, Verbose));
+  PM.add(createXCoreCodePrinterPass(Out, *this, Fast, Verbose));
   return false;
 }

Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Mon Apr 27 20:04:53 2009
@@ -52,8 +52,8 @@
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                   bool Verbose, raw_ostream &Out);
 };
 

Modified: llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll Mon Apr 27 20:04:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0
+; RUN: llvm-as < %s | llc -fast
 
 define float @test(i32 %tmp12771278) {
         switch i32 %tmp12771278, label %bb1279 [

Modified: llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll Mon Apr 27 20:04:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0
+; RUN: llvm-as < %s | llc -fast
 	
 %struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32 }
 @cl_pf_opts = external global %struct.cl_perfunc_opts		; <%struct.cl_perfunc_opts*> [#uses=2]

Modified: llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll Mon Apr 27 20:04:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0
+; RUN: llvm-as < %s | llc -fast
 ; PR 1323
 
 ; ModuleID = 'test.bc'

Modified: llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll Mon Apr 27 20:04:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o -
+; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -fast -relocation-model=pic -o -
 ; PR1638
 
 @.str242 = external constant [3 x i8]		; <[3 x i8]*> [#uses=1]

Modified: llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll Mon Apr 27 20:04:53 2009
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local
+; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -fast -regalloc=local
 
 	%struct.CGPoint = type { double, double }
 	%struct.NSArray = type { %struct.NSObject }

Modified: llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll Mon Apr 27 20:04:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -O0 -fast-isel=false | grep mov | count 5
+; RUN: llvm-as < %s | llc -march=x86 -fast -fast-isel=false | grep mov | count 5
 ; PR2343
 
 	%llvm.dbg.anchor.type = type { i32, i32 }

Modified: llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll Mon Apr 27 20:04:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast
 
 define fastcc void @optimize_bit_field() nounwind {
 bb4:

Modified: llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll Mon Apr 27 20:04:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast -regalloc=local | not grep sil
 ; rdar://6787136
 
 	%struct.X = type { i8, [32 x i8] }

Modified: llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/add-with-overflow.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/add-with-overflow.ll (original)
+++ llvm/trunk/test/CodeGen/X86/add-with-overflow.ll Mon Apr 27 20:04:53 2009
@@ -1,7 +1,7 @@
 ; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 2
 ; RUN: llvm-as < %s | llc -march=x86 | grep {jb} | count 2
-; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jo} | count 2
-; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jb} | count 2
+; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jo} | count 2
+; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jb} | count 2
 
 @ok = internal constant [4 x i8] c"%d\0A\00"
 @no = internal constant [4 x i8] c"no\0A\00"

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll Mon Apr 27 20:04:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -O0
+; RUN: llvm-as < %s | llc -march=x86 -fast
 
 ; This file is for regression tests for cases where FastISel needs
 ; to gracefully bail out and let SelectionDAGISel take over.

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll Mon Apr 27 20:04:53 2009
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -O0 | grep movslq
-; RUN: llvm-as < %s | llc -march=x86 -O0
+; RUN: llvm-as < %s | llc -march=x86-64 -fast | grep movslq
+; RUN: llvm-as < %s | llc -march=x86 -fast
 ; PR3181
 
 ; GEP indices are interpreted as signed integers, so they

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll Mon Apr 27 20:04:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {sarl	\$80, %eax}
+; RUN: llvm-as < %s | llc -march=x86 -fast | grep {sarl	\$80, %eax}
 ; PR3242
 
 define i32 @foo(i32 %x) nounwind {

Modified: llvm/trunk/test/CodeGen/X86/pr1489.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr1489.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr1489.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr1489.ll Mon Apr 27 20:04:53 2009
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 1082126238 | count 3
-; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 3058016715 | count 1
+; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 1082126238 | count 3
+; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 3058016715 | count 1
 ;; magic constants are 3.999f and half of 3.999
 ; ModuleID = '1489.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"

Modified: llvm/trunk/test/CodeGen/X86/volatile.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/volatile.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/volatile.ll (original)
+++ llvm/trunk/test/CodeGen/X86/volatile.ll Mon Apr 27 20:04:53 2009
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 | grep movsd | count 5
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -O0 | grep movsd | count 5
+; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -fast | grep movsd | count 5
 
 @x = external global double
 

Modified: llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll (original)
+++ llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll Mon Apr 27 20:04:53 2009
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc
-; RUN: llvm-as < %s | llc -O0
+; RUN: llvm-as < %s | llc -fast
 	%llvm.dbg.anchor.type = type { i32, i32 }
 	%llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 }
 	%llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8* }

Modified: llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-30-Method.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/2009-01-30-Method.ll (original)
+++ llvm/trunk/test/DebugInfo/2009-01-30-Method.ll Mon Apr 27 20:04:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0 | grep "\\"foo" | count 3
+; RUN: llvm-as < %s | llc -fast | grep "\\"foo" | count 3
 ; 1 declaration, 1 definition and 1 pubnames entry.
 target triple = "i386-apple-darwin*"
 	%llvm.dbg.anchor.type = type { i32, i32 }

Modified: llvm/trunk/test/DebugInfo/deaddebuglabel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/deaddebuglabel.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/deaddebuglabel.ll (original)
+++ llvm/trunk/test/DebugInfo/deaddebuglabel.ll Mon Apr 27 20:04:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0 | grep "label" | count 8
+; RUN: llvm-as < %s | llc -fast | grep "label" | count 8
 ; PR2614
 ; XFAIL: *
 

Modified: llvm/trunk/test/DebugInfo/forwardDecl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/forwardDecl.ll?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/forwardDecl.ll (original)
+++ llvm/trunk/test/DebugInfo/forwardDecl.ll Mon Apr 27 20:04:53 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0 | %prcontext ST 1 | grep 0x1 | count 1
+; RUN: llvm-as < %s | llc -fast | %prcontext ST 1 | grep 0x1 | count 1
 
 target triple = "i386-apple-darwin9.6"
 	%llvm.dbg.anchor.type = type { i32, i32 }

Modified: llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-06-StackTrace.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp Mon Apr 27 20:04:53 2009
@@ -1,7 +1,7 @@
 // This is a regression test on debug info to make sure that we can get a
 // meaningful stack trace from a C++ program.
 // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
-// RUN:    llc --disable-fp-elim -o %t.s -f -O0 -relocation-model=pic
+// RUN:    llc --disable-fp-elim -o %t.s -f -fast -relocation-model=pic
 // RUN: %compile_c %t.s -o %t.o
 // RUN: %link %t.o -o %t.exe
 // RUN: echo {break DeepStack::deepest\nrun 17\nwhere\n} > %t.in 

Modified: llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-30-Pubnames.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp Mon Apr 27 20:04:53 2009
@@ -1,7 +1,7 @@
 // This is a regression test on debug info to make sure that we can access 
 // qualified global names.
 // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
-// RUN:   llc --disable-fp-elim -o %t.s -f -O0
+// RUN:   llc --disable-fp-elim -o %t.s -f -fast
 // RUN: %compile_c %t.s -o %t.o
 // RUN: %link %t.o -o %t.exe
 // RUN: %llvmdsymutil %t.exe 

Modified: llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-04-21-DtorNames-dbg.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp Mon Apr 27 20:04:53 2009
@@ -1,4 +1,4 @@
-// RUN: %llvmgcc -c -g %s -o - | llc -O0 -f -o %t.s
+// RUN: %llvmgcc -c -g %s -o - | llc -fast -f -o %t.s
 // RUN: %compile_c %t.s -o %t.o
 // PR4025
 

Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Mon Apr 27 20:04:53 2009
@@ -55,13 +55,8 @@
 
 static cl::opt<bool> Force("f", cl::desc("Overwrite output files"));
 
-// Determine optimization level. Level -O0 is equivalent to "fast" code gen.
-static cl::opt<unsigned>
-OptLevel("O",
-         cl::desc("Optimization level. Similar to llvm-gcc -O. (default: -O3)"),
-         cl::Prefix,
-         cl::ZeroOrMore,
-         cl::init(3));
+static cl::opt<bool> Fast("fast",
+      cl::desc("Generate code quickly, potentially sacrificing code quality"));
 
 static cl::opt<std::string>
 TargetTriple("mtriple", cl::desc("Override target triple for module"));
@@ -262,7 +257,7 @@
       PM.add(createVerifierPass());
 
     // Ask the target to add backend passes as necessary.
-    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OptLevel)) {
+    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, Fast)) {
       std::cerr << argv[0] << ": target does not support generation of this"
                 << " file type!\n";
       if (Out != &outs()) delete Out;
@@ -288,7 +283,7 @@
     // Override default to generate verbose assembly.
     Target.setAsmVerbosityDefault(true);
 
-    switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OptLevel)) {
+    switch (Target.addPassesToEmitFile(Passes, *Out, FileType, Fast)) {
     default:
       assert(0 && "Invalid file model!");
       return 1;
@@ -309,7 +304,7 @@
       break;
     }
 
-    if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) {
+    if (Target.addPassesToEmitFileFinish(Passes, MCE, Fast)) {
       std::cerr << argv[0] << ": target does not support generation of this"
                 << " file type!\n";
       if (Out != &outs()) delete Out;

Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Mon Apr 27 20:04:53 2009
@@ -650,7 +650,7 @@
   O << "\";\n\n";
 
   O << "  if (TAI->doesSupportDebugInformation() &&\n"
-    << "      DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n"
+    << "      DW->ShouldEmitDwarfDebug() && !Fast) {\n"
     << "    DebugLoc CurDL = MI->getDebugLoc();\n\n"
     << "    if (!CurDL.isUnknown()) {\n"
     << "      static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n"

Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=70275&r1=70274&r2=70275&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Apr 27 20:04:53 2009
@@ -465,7 +465,7 @@
       NumInputRootOps = N->getNumChildren();
 
       if (DisablePatternForFastISel(N, CGP))
-        emitCheck("OptLevel != 0");
+        emitCheck("!Fast");
 
       emitCheck(PredicateCheck);
     }




From evan.cheng at apple.com  Mon Apr 27 21:12:36 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Apr 2009 02:12:36 -0000
Subject: [llvm-commits] [llvm] r70279 - in /llvm/trunk:
 lib/CodeGen/TwoAddressInstructionPass.cpp
 test/CodeGen/X86/2009-04-27-LiveIntervalsAssert2.ll
Message-ID: <200904280212.n3S2CaNj031623@zion.cs.uiuc.edu>

Author: evancheng
Date: Mon Apr 27 21:12:36 2009
New Revision: 70279

URL: http://llvm.org/viewvc/llvm-project?rev=70279&view=rev
Log:
Fix for PR4051. When 2address pass delete an instruction, update kill info when necessary.

Added:
    llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert2.ll
Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=70279&r1=70278&r2=70279&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Mon Apr 27 21:12:36 2009
@@ -88,6 +88,9 @@
     bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
                            unsigned &LastDef);
 
+    MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB,
+                                   unsigned Dist);
+
     bool isProfitableToCommute(unsigned regB, unsigned regC,
                                MachineInstr *MI, MachineBasicBlock *MBB,
                                unsigned Dist);
@@ -310,6 +313,28 @@
   return !(LastUse > LastDef && LastUse < Dist);
 }
 
+MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg,
+                                                         MachineBasicBlock *MBB,
+                                                         unsigned Dist) {
+  unsigned LastUseDist = Dist;
+  MachineInstr *LastUse = 0;
+  for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
+         E = MRI->reg_end(); I != E; ++I) {
+    MachineOperand &MO = I.getOperand();
+    MachineInstr *MI = MO.getParent();
+    if (MI->getParent() != MBB)
+      continue;
+    DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
+    if (DI == DistanceMap.end())
+      continue;
+    if (MO.isUse() && DI->second < LastUseDist) {
+      LastUse = DI->first;
+      LastUseDist = DI->second;
+    }
+  }
+  return LastUse;
+}
+
 /// isCopyToReg - Return true if the specified MI is a copy instruction or
 /// a extract_subreg instruction. It also returns the source and destination
 /// registers and whether they are physical registers by reference.
@@ -684,7 +709,9 @@
 
 /// isSafeToDelete - If the specified instruction does not produce any side
 /// effects and all of its defs are dead, then it's safe to delete.
-static bool isSafeToDelete(MachineInstr *MI, const TargetInstrInfo *TII) {
+static bool isSafeToDelete(MachineInstr *MI, unsigned Reg,
+                           const TargetInstrInfo *TII,
+                           SmallVector<unsigned, 4> &Kills) {
   const TargetInstrDesc &TID = MI->getDesc();
   if (TID.mayStore() || TID.isCall())
     return false;
@@ -693,10 +720,12 @@
 
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
-    if (!MO.isReg() || !MO.isDef())
+    if (!MO.isReg())
       continue;
-    if (!MO.isDead())
+    if (MO.isDef() && !MO.isDead())
       return false;
+    if (MO.isUse() && MO.getReg() != Reg && MO.isKill())
+      Kills.push_back(MO.getReg());
   }
 
   return true;
@@ -787,11 +816,53 @@
           if (!isKilled(*mi, regB, MRI, TII)) {
             // If regA is dead and the instruction can be deleted, just delete
             // it so it doesn't clobber regB.
-            if (mi->getOperand(ti).isDead() && isSafeToDelete(mi, TII)) {
-              mbbi->erase(mi); // Nuke the old inst.
-              mi = nmi;
-              ++NumDeletes;
-              break; // Done with this instruction.
+            SmallVector<unsigned, 4> Kills;
+            if (mi->getOperand(ti).isDead() &&
+                isSafeToDelete(mi, regB, TII, Kills)) {
+              SmallVector<std::pair<std::pair<unsigned, bool>
+                ,MachineInstr*>, 4> NewKills;
+              bool ReallySafe = true;
+              // If this instruction kills some virtual registers, we need
+              // update the kill information. If it's not possible to do so,
+              // then bail out.
+              while (!Kills.empty()) {
+                unsigned Kill = Kills.back();
+                Kills.pop_back();
+                if (TargetRegisterInfo::isPhysicalRegister(Kill)) {
+                  ReallySafe = false;
+                  break;
+                }
+                MachineInstr *LastKill = FindLastUseInMBB(Kill, &*mbbi, Dist);
+                if (LastKill) {
+                  bool isModRef = LastKill->modifiesRegister(Kill);
+                  NewKills.push_back(std::make_pair(std::make_pair(Kill,isModRef),
+                                                    LastKill));
+                } else {
+                  ReallySafe = false;
+                  break;
+                }
+              }
+
+              if (ReallySafe) {
+                if (LV) {
+                  while (!NewKills.empty()) {
+                    MachineInstr *NewKill = NewKills.back().second;
+                    unsigned Kill = NewKills.back().first.first;
+                    bool isDead = NewKills.back().first.second;
+                    NewKills.pop_back();
+                    if (LV->removeVirtualRegisterKilled(Kill,  mi)) {
+                      if (isDead)
+                        LV->addVirtualRegisterDead(Kill, NewKill);
+                      else
+                        LV->addVirtualRegisterKilled(Kill, NewKill);
+                    }
+                  }
+                }
+                mbbi->erase(mi); // Nuke the old inst.
+                mi = nmi;
+                ++NumDeletes;
+                break; // Done with this instruction.
+              }
             }
 
             // If this instruction is commutative, check to see if C dies.  If

Added: llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert2.ll?rev=70279&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert2.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert2.ll Mon Apr 27 21:12:36 2009
@@ -0,0 +1,23 @@
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9
+; PR4051
+
+define void @int163(i32 %p_4, i32 %p_5) nounwind {
+entry:
+	%0 = tail call i32 @foo(i32 1) nounwind		; <i32> [#uses=2]
+	%1 = icmp eq i32 %0, 0		; <i1> [#uses=1]
+	br i1 %1, label %bb.i, label %bar.exit
+
+bb.i:		; preds = %entry
+	%2 = lshr i32 1, %0		; <i32> [#uses=1]
+	%3 = icmp eq i32 %2, 0		; <i1> [#uses=1]
+	%retval.i = select i1 %3, i32 1, i32 %p_5		; <i32> [#uses=1]
+	br label %bar.exit
+
+bar.exit:		; preds = %bb.i, %entry
+	%4 = phi i32 [ %retval.i, %bb.i ], [ %p_5, %entry ]		; <i32> [#uses=1]
+	%5 = icmp eq i32 %4, 0		; <i1> [#uses=0]
+	%6 = tail call i32 @foo(i32 %p_5) nounwind		; <i32> [#uses=0]
+	ret void
+}
+
+declare i32 @foo(i32)




From duraid at octopus.com.au  Mon Apr 27 23:30:11 2009
From: duraid at octopus.com.au (Duraid Madina)
Date: Tue, 28 Apr 2009 04:30:11 -0000
Subject: [llvm-commits] [test-suite] r70287 -
 /test-suite/trunk/SingleSource/Benchmarks/Misc/salsa20.c
Message-ID: <200904280430.n3S4UBZr003174@zion.cs.uiuc.edu>

Author: duraid
Date: Mon Apr 27 23:30:11 2009
New Revision: 70287

URL: http://llvm.org/viewvc/llvm-project?rev=70287&view=rev
Log:
sampo's vector goodness will hopefully do something to this


Added:
    test-suite/trunk/SingleSource/Benchmarks/Misc/salsa20.c

Added: test-suite/trunk/SingleSource/Benchmarks/Misc/salsa20.c
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/salsa20.c?rev=70287&view=auto

==============================================================================
--- test-suite/trunk/SingleSource/Benchmarks/Misc/salsa20.c (added)
+++ test-suite/trunk/SingleSource/Benchmarks/Misc/salsa20.c Mon Apr 27 23:30:11 2009
@@ -0,0 +1,65 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+
+/* salsa20 is due to Daniel J. Bernstein, who has stated
+   "My policy is that Salsa20 is free for everyone to use."
+   ( http://cr.yp.to/snuffle/ip.pdf )
+*/
+
+uint32_t STATE[16];
+uint32_t outbuf[16];  
+uint32_t ptr=0;
+
+#define R(a,b) (((a) << (b)) | ((a) >> (32 - (b))))
+void salsa20(uint32_t out[16],uint32_t in[16]) {
+  uint32_t i, x[16];
+
+  for (i = 0;i < 16;++i)
+    x[i] = in[i];
+    
+  for (i = 20;i > 0;i -= 2) {
+    x[ 4] ^= R(x[ 0]+x[12], 7);  x[ 8] ^= R(x[ 4]+x[ 0], 9);
+    x[12] ^= R(x[ 8]+x[ 4],13);  x[ 0] ^= R(x[12]+x[ 8],18);
+    x[ 9] ^= R(x[ 5]+x[ 1], 7);  x[13] ^= R(x[ 9]+x[ 5], 9);
+    x[ 1] ^= R(x[13]+x[ 9],13);  x[ 5] ^= R(x[ 1]+x[13],18);
+    x[14] ^= R(x[10]+x[ 6], 7);  x[ 2] ^= R(x[14]+x[10], 9);
+    x[ 6] ^= R(x[ 2]+x[14],13);  x[10] ^= R(x[ 6]+x[ 2],18);
+    x[ 3] ^= R(x[15]+x[11], 7);  x[ 7] ^= R(x[ 3]+x[15], 9);
+    x[11] ^= R(x[ 7]+x[ 3],13);  x[15] ^= R(x[11]+x[ 7],18);
+    x[ 1] ^= R(x[ 0]+x[ 3], 7);  x[ 2] ^= R(x[ 1]+x[ 0], 9);
+    x[ 3] ^= R(x[ 2]+x[ 1],13);  x[ 0] ^= R(x[ 3]+x[ 2],18);
+    x[ 6] ^= R(x[ 5]+x[ 4], 7);  x[ 7] ^= R(x[ 6]+x[ 5], 9);
+    x[ 4] ^= R(x[ 7]+x[ 6],13);  x[ 5] ^= R(x[ 4]+x[ 7],18);
+    x[11] ^= R(x[10]+x[ 9], 7);  x[ 8] ^= R(x[11]+x[10], 9);
+    x[ 9] ^= R(x[ 8]+x[11],13);  x[10] ^= R(x[ 9]+x[ 8],18);
+    x[12] ^= R(x[15]+x[14], 7);  x[13] ^= R(x[12]+x[15], 9);
+    x[14] ^= R(x[13]+x[12],13);  x[15] ^= R(x[14]+x[13],18);
+  }
+  for (i = 0;i < 16;++i) out[i] = x[i] + in[i];
+}
+
+uint32_t salsa(void) {
+  if(ptr==0) {
+    salsa20(outbuf, STATE);
+    (uint64_t)STATE[0]++;
+  }
+  
+  ptr = (ptr+1) & 0xF;
+  return(outbuf[ptr]);
+}
+
+int main(void) {
+  uint32_t val, i;
+
+  for(i=0; i<16; i++)
+    STATE[i] = (0xedababe5+(i+13))^(0xdeadbeef-i);
+  
+  for(i=0; i<537919488; i++)
+    salsa();
+
+  printf("got:       %x\n", val = salsa());
+  printf("should be: %x\n", 0xf655703d);
+  return(val != 0xf655703d);
+}
+




From kremenek at apple.com  Mon Apr 27 23:35:21 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Tue, 28 Apr 2009 04:35:21 -0000
Subject: [llvm-commits] [llvm] r70288 - /llvm/tags/checker/checker-0.190/
Message-ID: <200904280435.n3S4ZLJC003335@zion.cs.uiuc.edu>

Author: kremenek
Date: Mon Apr 27 23:35:20 2009
New Revision: 70288

URL: http://llvm.org/viewvc/llvm-project?rev=70288&view=rev
Log:
Tagging checker-0.190.

Added:
    llvm/tags/checker/checker-0.190/
      - copied from r70287, llvm/trunk/



From clattner at apple.com  Tue Apr 28 00:48:01 2009
From: clattner at apple.com (Chris Lattner)
Date: Mon, 27 Apr 2009 22:48:01 -0700
Subject: [llvm-commits] [llvm] r70225 - in /llvm/trunk:
	include/llvm/CodeGen/ include/llvm/Target/
	lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/
	lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/Generic/
	test/CodeGen/X86/ utils/TableGen/
In-Reply-To: <200904271841.n3RIfW0N015595@zion.cs.uiuc.edu>
References: <200904271841.n3RIfW0N015595@zion.cs.uiuc.edu>
Message-ID: <1A2A5DC6-AEA8-411C-BA17-2AE8421FCAD2@apple.com>

On Apr 27, 2009, at 11:41 AM, Nate Begeman wrote:
> URL: http://llvm.org/viewvc/llvm-project?rev=70225&view=rev
> Log:
> 2nd attempt, fixing SSE4.1 issues and implementing feedback from  
> duncan.

Woot again, this is awesome work!

Most of the comments below are me bitching about int vs unsigned.  I  
think it is actually really important to get this right, particularly  
with this change.  Without being clear on that, it is easy to get  
confused about what is an index into the elements of a mask (which  
should be unsigned) vs what is a mask value (which is -1 or a small  
integer).  I think that using int and unsigned consistently is a good  
way to help with this.



> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Apr 27  
> 13:41:29 2009
> @@ -353,6 +353,13 @@
>   SDValue getConvertRndSat(MVT VT, DebugLoc dl, SDValue Val, SDValue  
> DTy,
>                            SDValue STy,
>                            SDValue Rnd, SDValue Sat, ISD::CvtCode  
> Code);
> +
> +  /// getVectorShuffle - Return an ISD::VECTOR_SHUFFLE node.  The  
> number of
> +  /// elements in VT, which must be a vector type, must match the  
> number of
> +  /// mask elements NumElts.  A negative integer mask element is  
> treated as
> +  /// undefined.
> +  SDValue getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, SDValue  
> N2,
> +                           const int *MaskElts);

Any reason to allow any negative?  Why not require exactly -1?

>
> +class ShuffleVectorSDNode : public SDNode {

Please add a comment above this explaining what this is all about and  
giving an example.

>
> +  SDUse Ops[2];
> +  int *Mask;

Please add a commend explaining who owns the memory for Mask.  When  
does it need to get deallocated (if ever)?  Should this be "const  
int*" or can the mask actually be modified once the node is created?

> +protected:
> +  friend class SelectionDAG;
> +  ShuffleVectorSDNode(MVT VT, DebugLoc dl, SDValue N1, SDValue N2,  
> int *M)

If Mask is marked const, M can be too.

> +
> +  void getMask(SmallVectorImpl<int> &M) const {
> +    MVT VT = getValueType(0);
> +    M.clear();
> +    for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
> +      M.push_back(Mask[i]);
> +  }
> +  int getMaskElt(unsigned Idx) const {
> +    assert(Idx < getValueType(0).getVectorNumElements() && "Idx out  
> of range!");
> +    return Mask[Idx];
> +  }
> +
> +  bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }


>
> +  int  getSplatIndex() const {
> +    assert(isSplat() && "Cannot get splat index for non-splat!");
> +    return Mask[0];
> +  static bool isSplatMask(const int *Mask, MVT VT);

  -> body copied from below:
> +bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) {
> +  int Idx = -1;
> +  for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
> +    if (Idx < 0) Idx = Mask[i];
> +    if (Mask[i] >= 0 && Mask[i] != Idx)
> +      return false;
> +  }
> +  return true;
> +}

This doesn't seem like it would recognize SHUFFLE(X,UNDEF, -1, 1,1,1)

correctly as a splat of element 1.  isSplatMask will return true, but  
getSplatIndex will return -1.

Maybe instead of having both methods, just have "getSplatIndex" which  
would return -1 if it isn't a splat, or the index if so.


> +++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Apr 27  
> 13:41:29 2009
> @@ -28,6 +28,7 @@
> #include "llvm/ADT/APFloat.h"
> #include "llvm/ADT/DenseMap.h"
> #include "llvm/ADT/SmallSet.h"
> +#include "llvm/ADT/SmallVector.h"
> #include "llvm/ADT/STLExtras.h"
> #include "llvm/CodeGen/DebugLoc.h"
> #include "llvm/Target/TargetMachine.h"
> @@ -328,7 +329,7 @@
>   /// support *some* VECTOR_SHUFFLE operations, those with specific  
> masks.
>   /// By default, if a target supports the VECTOR_SHUFFLE node, all  
> mask values
>   /// are assumed to be legal.
> -  virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const {
> +  virtual bool isShuffleMaskLegal(SmallVectorImpl<int> &Mask, MVT  
> VT) const {

Two issues:
1. It isn't a big deal, but it doesn't seem like there is any need to  
require Mask to be passed in as a small vector.  It seems that just  
passing in a 'const int *' is enough.
2. If you do want to pass in a smallvector, please mark it const.  The  
implementations of isShuffleMaskLegal should not be able to modify the  
vector.

> @@ -336,9 +337,7 @@
>   /// used by Targets can use this to indicate if there is a suitable
>   /// VECTOR_SHUFFLE that can be used to replace a VAND with a  
> constant
>   /// pool entry.
> +  virtual bool isVectorClearMaskLegal(SmallVectorImpl<int> &M, MVT  
> VT) const {

Likewise.

> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 27  
> 13:41:29 2009
> @@ -5164,9 +5178,8 @@
>       // to examine the mask.
>       if (BCNumEltsChanged)
>         return SDValue();
> +      int Idx = cast<ShuffleVectorSDNode>(InVec)->getMaskElt(Elt);
> +      int NumElems = InVec.getValueType().getVectorNumElements();
>       InVec = (Idx < NumElems) ? InVec.getOperand(0) :  
> InVec.getOperand(1);
>       if (InVec.getOpcode() == ISD::BIT_CONVERT)
>         InVec = InVec.getOperand(0);

Above this blob, the code is:
     } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {

Please use dyn_cast<ShuffleVectorSDNode> in the "else if", eliminating  
the need for the cast<>.

I don't think that extractelement indices are always *guaranteed* to  
be valid constants.  If they were not, this will assert and die, which  
is bad.  If they are out range you can treat them like undef tho.


> @@ -5256,56 +5268,36 @@
>   }
>
>   // If everything is good, we can make a shuffle operation.
> -  MVT IndexVT = MVT::i32;
>   if (VecIn1.getNode()) {
> -    SmallVector<SDValue, 8> BuildVecIndices;
> +    SmallVector<int, 8> Mask;
>     for (unsigned i = 0; i != NumInScalars; ++i) {
>       if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
> -        BuildVecIndices.push_back(DAG.getUNDEF(IndexVT));
> +        Mask.push_back(-1);
>         continue;
>       }
>
> -      SDValue Extract = N->getOperand(i);
> -
>       // If extracting from the first vector, just use the index  
> directly.
> +      SDValue Extract = N->getOperand(i);
>       SDValue ExtVal = Extract.getOperand(1);
>       if (Extract.getOperand(0) == VecIn1) {
> +        Mask.push_back(cast<ConstantSDNode>(ExtVal)->getZExtValue());

Likewise, if the index is invalid, we should bail out of creating the  
shuffle.

> @@ -5325,8 +5317,10 @@
> }
>
> SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
> +  return SDValue();

This is an amazing optimization, but I'm not sure it is intended. :)

> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 27  
> 13:41:29 2009
>
> +/// promoteShuffle - Promote a shuffle mask of a vector VT to  
> perform the
> +/// same shuffle on a vector of NVT.  Must not create an illegal  
> shuffle mask.
> +/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>

This comment should explain that "promote" in this instance means that  
it results in a shuffle with (equal to or) more elements than the  
input shuffle does.  "Promote" is overloaded so much in codegen that  
it might be better to pick a different word :).  It is also worth  
clarifying that it is up to the caller to verify that the resultant  
shuffle mask will be legal, the comment makes it sound like the callee  
might do it.

>
> +SDValue SelectionDAGLegalize::promoteShuffle(MVT NVT, MVT VT,  
> DebugLoc dl,
> +                                             SDValue N1, SDValue N2,
> +                                             SmallVectorImpl<int>  
> &Mask) const {
> +  MVT EltVT = NVT.getVectorElementType();
> +  int NumMaskElts = VT.getVectorNumElements();
> +  int NumDestElts = NVT.getVectorNumElements();

Any reason not to make these unsigned?

> @@ -1705,16 +1674,21 @@
>       break;
>     }
>     break;
> -  case ISD::VECTOR_SHUFFLE:
> +  case ISD::VECTOR_SHUFFLE: {
>     Tmp1 = LegalizeOp(Node->getOperand(0));   // Legalize the input  
> vectors,
>     Tmp2 = LegalizeOp(Node->getOperand(1));   // but not the shuffle  
> mask.
> -    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node- 
> >getOperand(2));
> +    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
> +    MVT VT = Result.getValueType();
> +
> +    // Copy the Mask to a local SmallVector for use wi

comment fragment.

> @@ -1725,26 +1699,21 @@
> +      int NumElems = VT.getVectorNumElements();

unsigned?

>       SmallVector<SDValue, 8> Ops;
> +      for (int i = 0; i != NumElems; ++i) {

unsigned?

> @@ -5490,6 +5457,7 @@
>
>   // FIXME: it would be far nicer to change this into  
> map<SDValue,uint64_t>
>   // and use a bitmask instead of a list of elements.
> +  // FIXME: this doesn't treat <0, u, 0, u> for example, as a splat.

I assume that this should use your splat predicate?

> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Mon  
> Apr 27 13:41:29 2009
> @@ -761,6 +761,7 @@
>                                                   SDValue &Hi) {
>   // The low and high parts of the original input give four input  
> vectors.
>   SDValue Inputs[4];
> +  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);

Any reason not to change SplitVecRes_VECTOR_SHUFFLE to take a  
ShuffleVectorSDNode* directly and do the cast in the caller?  That  
makes the type an explicit part of its interface.

> @@ -1761,8 +1747,9 @@
> }
>
> SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(SDNode *N) {
> +  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
>   MVT VT = N->getValueType(0);
> -  unsigned NumElts = VT.getVectorNumElements();
> +  int NumElts = VT.getVectorNumElements();

unsigned?

> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Apr 27  
> 13:41:29 2009
> @@ -1126,6 +1133,110 @@
>   return SDValue(CondCodeNodes[Cond], 0);
> }
>
> +static void commuteShuffle(SDValue &N1, SDValue &N2,  
> SmallVectorImpl<int> &M) {

Is this generally useful?  Should this be a method on the node?   
Please add a comment.

> +SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue  
> N1,
> +                                       SDValue N2, const int *Mask) {
> +  assert(N1.getValueType() == N2.getValueType() && "Invalid  
> VECTOR_SHUFFLE");
> +  assert(VT.isVector() && N1.getValueType().isVector() &&
> +         "Vector Shuffle VTs must be a vectors");
> +  assert(VT.getVectorElementType() ==  
> N1.getValueType().getVectorElementType()
> +         && "Vector Shuffle VTs must have same element type");
> +
> +  // Canonicalize shuffle undef, undef -> undef
> +  if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF)
> +    return N1;
> +
> +  // Validate that all indices in Mask are within the range of the  
> elements
> +  // input to the shuffle.
> +  int NElts = VT.getVectorNumElements();
unsigned?

>
> +  SmallVector<int, 8> MaskVec;
> +  for (int i = 0; i != NElts; ++i) {
unsigned i?


>
> +    if (Mask[i] >= (NElts * 2)) {
> +      assert(0 && "Index out of range");

Please change this to do the test in the assert:

assert(Mask[i] < (NElts * 2) && "Index out of range");

> +  // Canonicalize shuffle v, v -> v, undef
> +  if (N1 == N2) {
> +    N2 = getUNDEF(VT);
> +    for (int i = 0; i != NElts; ++i)
unsigned i;

> +  // Canonicalize all index into lhs, -> shuffle lhs, undef
> +  // Canonicalize all index into rhs, -> shuffle rhs, undef
> +  bool AllLHS = true, AllRHS = true;
> +  bool N2Undef = N2.getOpcode() == ISD::UNDEF;
> +  for (int i = 0; i != NElts; ++i) {
unsigned i;

>
> +    if (MaskVec[i] >= NElts) {
> +      if (N2Undef)
> +        MaskVec[i] = -1;
> +      else
> +        AllLHS = false;
> +    } else if (MaskVec[i] >= 0) {
> +      AllRHS = false;
> +    }
> +  }
> +  if (AllLHS && AllRHS)
> +    return getUNDEF(VT);

> +  if (AllLHS)
> +    N2 = getUNDEF(VT);

How about:

> +  if (AllLHS && !N2Undef)
> +    N2 = getUNDEF(VT);

to speed up the common case when asking for shuffle(V,undef)


> +  // If Identity shuffle, or all shuffle in to undef, return that  
> node.
> +  bool AllUndef = true;
> +  bool Identity = true;
> +  for (int i = 0; i < NElts; ++i) {
unsigned i;  do you hate me yet? :)

> +  FoldingSetNodeID ID;
> +  SDValue Ops[2] = { N1, N2 };
> +  AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2);
> +  for (int i = 0; i != NElts; ++i)
unsigned i;

> @@ -2087,19 +2198,18 @@
> SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned  
> i) {
>   MVT VT = N->getValueType(0);
>   DebugLoc dl = N->getDebugLoc();
> +  const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);

If possible, this method should take a const ShuffleVectorSDNode*,  
instead of SDNode*.

> +  int NumElems = VT.getVectorNumElements();
unsigned

> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon  
> Apr 27 13:41:29 2009
> @@ -2435,37 +2431,42 @@
>
> // Utility for visitShuffleVector - Returns true if the mask is mask  
> starting
> // from SIndx and increasing to the element length (undefs are  
> allowed).
> +static bool SequentialMask(SmallVectorImpl<int> &Mask, int SIndx) {

Should this be a static method or ShuffleVectorSDNode or no?

>
> +  int MaskNumElts = Mask.size();
> +  for (int i = 0; i != MaskNumElts; ++i)
unsigned i / MaskNumElts;

> void SelectionDAGLowering::visitShuffleVector(User &I) {
> +  SmallVector<int, 8> Mask;
>   SDValue Src1 = getValue(I.getOperand(0));
>   SDValue Src2 = getValue(I.getOperand(1));
>
> +  // Convert the ConstantVector mask operand into an array of ints,  
> with -1
> +  // representing undef values.
> +  SmallVector<Constant*, 8> MaskElts;
> +  cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
> +  int MaskNumElts = MaskElts.size();
> +  for (int i = 0; i != MaskNumElts; ++i) {
unsigned i/MaskNumElts;
...

>   int SrcNumElts = SrcVT.getVectorNumElements();

unsigned?

> +    SmallVector<int, 8> MappedOps;
>     for (int i = 0; i != MaskNumElts; ++i) {

unsigned?

> @@ -2541,20 +2531,19 @@
>     int MaxRange[2] = {-1, -1};
>
>     for (int i = 0; i != MaskNumElts; ++i) {
unsigned i

> @@ -2627,12 +2608,10 @@
>   MVT PtrVT = TLI.getPointerTy();
>   SmallVector<SDValue,8> Ops;
>   for (int i = 0; i != MaskNumElts; ++i) {
unsigned i

> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Apr 27  
> 13:41:29 2009
> @@ -2825,14 +2694,15 @@
>   if (ISD::isNON_EXTLoad(V2))
>     return false;
>
> -  unsigned NumElems = Mask->getNumOperands();
> +  int NumElems = Op->getValueType(0).getVectorNumElements();
unsigned

>
> +
>   if (NumElems != 2 && NumElems != 4)
>     return false;
> -  for (unsigned i = 0, e = NumElems/2; i != e; ++i)
> -    if (!isUndefOrEqual(Mask->getOperand(i), i))
> +  for (int i = 0, e = NumElems/2; i != e; ++i)
unsigned i
>
> +    if (!isUndefOrEqual(Op->getMaskElt(i), i))
>       return false;
> +  for (int i = NumElems/2; i != NumElems; ++i)
unsigned i

> @@ -2883,34 +2730,25 @@
> }
>
> /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can  
> be resolved
> +/// to an zero vector.
> +/// FIXME: move to dag combiner?

How about to a method on ShuffleVectorSDNode?
>
> +static bool isZeroShuffle(ShuffleVectorSDNode *N) {
>   SDValue V1 = N->getOperand(0);
>   SDValue V2 = N->getOperand(1);
> +  int NumElems = N->getValueType(0).getVectorNumElements();
> +  for (int i = 0; i != NumElems; ++i) {
unsigned i/NumElems.

> @@ -2958,127 +2796,92 @@
>
> /// NormalizeMask - V2 is a splat, modify the mask (if needed) so  
> all elements
> /// that point to V2 points to its first element.
> +static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp,  
> SelectionDAG &DAG) {
> +  MVT VT = SVOp->getValueType(0);
> +  int NumElems = VT.getVectorNumElements();
> +
>
>   bool Changed = false;
> +  SmallVector<int, 8> MaskVec;
> +  SVOp->getMask(MaskVec);
> +
> +  for (int i = 0; i != NumElems; ++i) {

unsigned i/NumElems

-Chris



From stoklund at 2pi.dk  Tue Apr 28 01:15:00 2009
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 28 Apr 2009 06:15:00 -0000
Subject: [llvm-commits] [llvm] r70290 - /llvm/trunk/CREDITS.TXT
Message-ID: <200904280615.n3S6F0Pc006529@zion.cs.uiuc.edu>

Author: stoklund
Date: Tue Apr 28 01:15:00 2009
New Revision: 70290

URL: http://llvm.org/viewvc/llvm-project?rev=70290&view=rev
Log:
Initial test commit

Modified:
    llvm/trunk/CREDITS.TXT

Modified: llvm/trunk/CREDITS.TXT
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CREDITS.TXT?rev=70290&r1=70289&r2=70290&view=diff

==============================================================================
--- llvm/trunk/CREDITS.TXT (original)
+++ llvm/trunk/CREDITS.TXT Tue Apr 28 01:15:00 2009
@@ -290,3 +290,4 @@
 D: Darwin exception handling
 D: MMX & SSSE3 instructions
 D: SPEC2006 support
+




From evan.cheng at apple.com  Tue Apr 28 01:24:09 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Apr 2009 06:24:09 -0000
Subject: [llvm-commits] [llvm] r70291 - in /llvm/trunk:
 lib/CodeGen/LiveInterval.cpp test/CodeGen/X86/2009-04-27-CoalescerAssert.ll
Message-ID: <200904280624.n3S6O9BW006842@zion.cs.uiuc.edu>

Author: evancheng
Date: Tue Apr 28 01:24:09 2009
New Revision: 70291

URL: http://llvm.org/viewvc/llvm-project?rev=70291&view=rev
Log:
Fix PR4034. Bug in LiveInterval::join when it's compacting new valno's.

Added:
    llvm/trunk/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll
Modified:
    llvm/trunk/lib/CodeGen/LiveInterval.cpp

Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=70291&r1=70290&r2=70291&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Apr 28 01:24:09 2009
@@ -458,7 +458,7 @@
   for (unsigned i = 0; i < NumNewVals; ++i) {
     VNInfo *VNI = NewVNInfo[i];
     if (VNI) {
-      if (i >= NumVals)
+      if (NumValNos >= NumVals)
         valnos.push_back(VNI);
       else 
         valnos[NumValNos] = VNI;

Added: llvm/trunk/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll?rev=70291&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll Tue Apr 28 01:24:09 2009
@@ -0,0 +1,1457 @@
+; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu
+; PR4034
+
+	%struct.BiContextType = type { i16, i8 }
+	%struct.Bitstream = type { i32, i32, i32, i32, i8*, i32 }
+	%struct.DataPartition = type { %struct.Bitstream*, %struct.DecodingEnvironment, i32 (%struct.SyntaxElement*, %struct.ImageParameters*, %struct.DataPartition*)* }
+	%struct.DecRefPicMarking_t = type { i32, i32, i32, i32, i32, %struct.DecRefPicMarking_t* }
+	%struct.DecodingEnvironment = type { i32, i32, i32, i32, i32, i8*, i32* }
+	%struct.ImageParameters = type { i32, i32, i32, i32, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [16 x [16 x i16]], [6 x [32 x i32]], [16 x [16 x i32]], [4 x [12 x [4 x [4 x i32]]]], [16 x i32], i8**, i32*, i32***, i32**, i32, i32, i32, i32, %struct.Slice*, %struct.Macroblock*, i32, i32, i32, i32, i32, i32, %struct.DecRefPicMarking_t*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32***, i32***, i32****, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x [2 x i32]], [3 x [2 x i32]], i32, i32, i64, i64, %struct.timeb, %struct.timeb, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+	%struct.Macroblock = type { i32, [2 x i32], i32, i32, %struct.Macroblock*, %struct.Macroblock*, i32, [2 x [4 x [4 x [2 x i32]]]], i32, i64, i64, i32, i32, [4 x i8], [4 x i8], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+	%struct.MotionInfoContexts = type { [4 x [11 x %struct.BiContextType]], [2 x [9 x %struct.BiContextType]], [2 x [10 x %struct.BiContextType]], [2 x [6 x %struct.BiContextType]], [4 x %struct.BiContextType], [4 x %struct.BiContextType], [3 x %struct.BiContextType] }
+	%struct.PixelPos = type { i32, i32, i32, i32, i32, i32 }
+	%struct.Slice = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.DataPartition*, %struct.MotionInfoContexts*, %struct.TextureInfoContexts*, i32, i32*, i32*, i32*, i32, i32*, i32*, i32*, i32 (%struct.ImageParameters*, %struct.inp_par*)*, i32, i32, i32, i32 }
+	%struct.SyntaxElement = type { i32, i32, i32, i32, i32, i32, i32, i32, void (i32, i32, i32*, i32*)*, void (%struct.SyntaxElement*, %struct.ImageParameters*, %struct.DecodingEnvironment*)* }
+	%struct.TextureInfoContexts = type { [2 x %struct.BiContextType], [4 x %struct.BiContextType], [3 x [4 x %struct.BiContextType]], [10 x [4 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [5 x %struct.BiContextType]], [10 x [5 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]] }
+	%struct.inp_par = type { [1000 x i8], [1000 x i8], [1000 x i8], i32, i32, i32, i32, i32, i32, i32, i32 }
+	%struct.timeb = type { i64, i16, i16, i16 }
+ at get_mb_block_pos = external global void (i32, i32*, i32*)*		; <void (i32, i32*, i32*)**> [#uses=1]
+ at img = external global %struct.ImageParameters*		; <%struct.ImageParameters**> [#uses=14]
+ at llvm.used = appending global [1 x i8*] [i8* bitcast (void (i32, i32, i32, i32, %struct.PixelPos*)* @getAffNeighbour to i8*)], section "llvm.metadata"		; <[1 x i8*]*> [#uses=0]
+
+define void @getAffNeighbour(i32 %curr_mb_nr, i32 %xN, i32 %yN, i32 %is_chroma, %struct.PixelPos* %pix) nounwind {
+entry:
+	%Opq.sa.calc = add i32 0, 2		; <i32> [#uses=2]
+	%0 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=3]
+	%1 = getelementptr %struct.ImageParameters* %0, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%2 = load %struct.Macroblock** %1, align 8		; <%struct.Macroblock*> [#uses=24]
+	%3 = zext i32 %curr_mb_nr to i64		; <i64> [#uses=24]
+	%4 = sext i32 %is_chroma to i64		; <i64> [#uses=8]
+	br label %meshBB392
+
+entry.fragment:		; preds = %meshBB392
+	%Opq.sa.calc747 = add i32 %Opq.sa.calc921, 70		; <i32> [#uses=0]
+	%5 = getelementptr %struct.ImageParameters* %0, i64 0, i32 119, i64 %4, i64 0		; <i32*> [#uses=1]
+	%6 = load i32* %5, align 4		; <i32> [#uses=2]
+	%7 = getelementptr %struct.ImageParameters* %0, i64 0, i32 119, i64 %4, i64 1		; <i32*> [#uses=1]
+	%8 = load i32* %7, align 4		; <i32> [#uses=5]
+	br label %entry.fragment181
+
+entry.fragment181:		; preds = %entry.fragment
+	%Opq.sa.calc863 = add i32 %Opq.sa.calc921, -50		; <i32> [#uses=4]
+	%9 = getelementptr %struct.PixelPos* %pix, i64 0, i32 0		; <i32*> [#uses=4]
+	store i32 0, i32* %9, align 4
+	%10 = add i32 %8, -1		; <i32> [#uses=6]
+	%11 = icmp slt i32 %10, %yN		; <i1> [#uses=1]
+	br i1 %11, label %meshBB448, label %bb
+
+bb:		; preds = %entry.fragment181
+	%Opq.sa.calc460 = add i32 %Opq.sa.calc863, 50		; <i32> [#uses=0]
+	%12 = add i32 %6, -1		; <i32> [#uses=5]
+	%13 = icmp slt i32 %12, %xN		; <i1> [#uses=1]
+	br label %bb.fragment
+
+bb.fragment:		; preds = %bb
+	%Opq.sa.calc976 = add i32 %Opq.sa.calc863, 13		; <i32> [#uses=3]
+	%.not8 = icmp sgt i32 %yN, -1		; <i1> [#uses=1]
+	%14 = icmp sgt i32 %8, %yN		; <i1> [#uses=1]
+	%or.cond.not = and i1 %14, %.not8		; <i1> [#uses=3]
+	%or.cond1 = and i1 %or.cond.not, %13		; <i1> [#uses=1]
+	br i1 %or.cond1, label %meshBB396, label %bb3
+
+bb3:		; preds = %bb.fragment
+	%Opq.sa.calc462 = sub i32 %Opq.sa.calc976, -152		; <i32> [#uses=5]
+	%Opq.sa.calc461 = sub i32 %Opq.sa.calc462, 168		; <i32> [#uses=2]
+	%15 = icmp slt i32 %xN, 0		; <i1> [#uses=1]
+	br i1 %15, label %bb4, label %meshBB404
+
+bb4:		; preds = %bb3
+	%Opq.sa.calc467 = xor i32 %Opq.sa.calc462, 171		; <i32> [#uses=2]
+	%Opq.sa.calc465 = sub i32 %Opq.sa.calc467, %Opq.sa.calc462		; <i32> [#uses=1]
+	%Opq.sa.calc466 = xor i32 %Opq.sa.calc465, -164		; <i32> [#uses=1]
+	%16 = icmp slt i32 %yN, 0		; <i1> [#uses=1]
+	br i1 %16, label %meshBB428, label %meshBB392
+
+bb5:		; preds = %meshBB428
+	%Opq.sa.calc470 = sub i32 %Opq.sa.calc897, -49		; <i32> [#uses=1]
+	%17 = getelementptr %struct.Macroblock* %2, i64 %3, i32 20		; <i32*> [#uses=1]
+	%18 = load i32* %17, align 4		; <i32> [#uses=1]
+	br label %bb5.fragment
+
+bb5.fragment:		; preds = %bb5
+	%Opq.sa.calc873 = sub i32 %Opq.sa.calc470, 169		; <i32> [#uses=7]
+	%19 = icmp eq i32 %18, 0		; <i1> [#uses=1]
+	%20 = and i32 %curr_mb_nr, 1		; <i32> [#uses=1]
+	%21 = icmp eq i32 %20, 0		; <i1> [#uses=2]
+	br i1 %19, label %bb6, label %bb13
+
+bb6:		; preds = %bb5.fragment
+	%Opq.sa.calc473 = xor i32 %Opq.sa.calc873, 81		; <i32> [#uses=1]
+	br i1 %21, label %bb7, label %meshBB348
+
+bb7:		; preds = %bb6
+	%Opq.sa.calc476 = add i32 %Opq.sa.calc873, -58		; <i32> [#uses=1]
+	%22 = getelementptr %struct.Macroblock* %2, i64 %3, i32 25		; <i32*> [#uses=1]
+	%23 = load i32* %22, align 8		; <i32> [#uses=1]
+	%24 = add i32 %23, 1		; <i32> [#uses=1]
+	%25 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	br label %meshBB388
+
+bb7.fragment:		; preds = %meshBB388
+	%Opq.sa.calc709 = sub i32 %Opq.sa.calc886, 143		; <i32> [#uses=1]
+	%Opq.sa.calc707 = add i32 %Opq.sa.calc709, %Opq.sa.calc886		; <i32> [#uses=1]
+	%Opq.sa.calc708 = xor i32 %Opq.sa.calc707, 474		; <i32> [#uses=0]
+	store i32 %.SV194.phi, i32* %.SV196.phi, align 4
+	%26 = getelementptr %struct.Macroblock* %.load17.SV.phi, i64 %.load36.SV.phi, i32 29		; <i32*> [#uses=1]
+	%27 = load i32* %26, align 8		; <i32> [#uses=2]
+	store i32 %27, i32* %.load67.SV.phi, align 4
+	br label %bb96
+
+bb8:		; preds = %meshBB348
+	%Opq.sa.calc479 = sub i32 %Opq.sa.calc805, 141		; <i32> [#uses=1]
+	%28 = getelementptr %struct.Macroblock* %2, i64 %3, i32 22		; <i32*> [#uses=2]
+	%29 = load i32* %28, align 4		; <i32> [#uses=2]
+	%30 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=2]
+	br label %meshBB368
+
+bb8.fragment:		; preds = %meshBB368
+	%Opq.sa.calc765 = sub i32 %Opq.sa.calc768, -115		; <i32> [#uses=2]
+	store i32 %.SV198.phi, i32* %.SV200.phi, align 4
+	%31 = getelementptr %struct.Macroblock* %.load16.SV.phi, i64 %.load35.SV.phi, i32 26		; <i32*> [#uses=2]
+	%32 = load i32* %31, align 4		; <i32> [#uses=4]
+	store i32 %32, i32* %.load66.SV.phi, align 4
+	%33 = load i32* %31, align 4		; <i32> [#uses=1]
+	%34 = icmp eq i32 %33, 0		; <i1> [#uses=1]
+	br i1 %34, label %bb96, label %bb9
+
+bb9:		; preds = %bb8.fragment
+	%Opq.sa.calc482 = xor i32 %Opq.sa.calc765, 163		; <i32> [#uses=0]
+	%35 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%36 = getelementptr %struct.ImageParameters* %35, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%37 = load %struct.Macroblock** %36, align 8		; <%struct.Macroblock*> [#uses=1]
+	%38 = load i32* %.SV76.phi, align 4		; <i32> [#uses=1]
+	br label %bb9.fragment
+
+bb9.fragment:		; preds = %bb9
+	%Opq.sa.calc999 = add i32 %Opq.sa.calc765, -44		; <i32> [#uses=1]
+	%39 = sext i32 %38 to i64		; <i64> [#uses=1]
+	%40 = getelementptr %struct.Macroblock* %37, i64 %39, i32 20		; <i32*> [#uses=1]
+	%41 = load i32* %40, align 4		; <i32> [#uses=1]
+	%42 = icmp eq i32 %41, 0		; <i1> [#uses=1]
+	br i1 %42, label %bb96, label %bb11
+
+bb11:		; preds = %bb9.fragment
+	%Opq.sa.calc485 = sub i32 %Opq.sa.calc999, 200		; <i32> [#uses=2]
+	%43 = add i32 %.SV78.phi, 1		; <i32> [#uses=1]
+	br label %meshBB332
+
+bb11.fragment:		; preds = %meshBB332
+	%Opq.sa.calc954 = xor i32 %Opq.link.mask859, 233		; <i32> [#uses=0]
+	store i32 %.SV206.phi, i32* %.load81.SV.phi, align 4
+	%44 = add i32 %.load50.SV.phi, %yN		; <i32> [#uses=1]
+	%45 = ashr i32 %44, 1		; <i32> [#uses=1]
+	br label %bb96
+
+bb13:		; preds = %bb5.fragment
+	%Opq.sa.calc490 = xor i32 %Opq.sa.calc873, 175		; <i32> [#uses=1]
+	%Opq.sa.calc488 = sub i32 %Opq.sa.calc490, %Opq.sa.calc873		; <i32> [#uses=1]
+	%Opq.sa.calc489 = sub i32 %Opq.sa.calc488, 133		; <i32> [#uses=1]
+	%46 = getelementptr %struct.Macroblock* %2, i64 %3, i32 25		; <i32*> [#uses=1]
+	br label %meshBB360
+
+bb13.fragment:		; preds = %meshBB360
+	%Opq.sa.calc870 = add i32 %Opq.sa.calc866, -129		; <i32> [#uses=3]
+	%47 = load i32* %.SV208.phi, align 8		; <i32> [#uses=3]
+	br i1 %.load74.SV.phi, label %bb14, label %meshBB412
+
+bb14:		; preds = %bb13.fragment
+	%Opq.sa.calc493 = add i32 %Opq.sa.calc870, 103		; <i32> [#uses=1]
+	%48 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=2]
+	store i32 %47, i32* %48, align 4
+	%49 = getelementptr %struct.Macroblock* %2, i64 %3, i32 29		; <i32*> [#uses=2]
+	br label %bb14.fragment
+
+bb14.fragment:		; preds = %bb14
+	%Opq.sa.calc723 = sub i32 %Opq.sa.calc493, 117		; <i32> [#uses=4]
+	%50 = load i32* %49, align 8		; <i32> [#uses=4]
+	store i32 %50, i32* %.SV52.phi1113, align 4
+	%51 = load i32* %49, align 8		; <i32> [#uses=1]
+	%52 = icmp eq i32 %51, 0		; <i1> [#uses=1]
+	br i1 %52, label %meshBB, label %bb15
+
+bb15:		; preds = %bb14.fragment
+	%Opq.sa.calc496 = sub i32 %Opq.sa.calc723, -8		; <i32> [#uses=1]
+	%53 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%54 = getelementptr %struct.ImageParameters* %53, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%55 = load %struct.Macroblock** %54, align 8		; <%struct.Macroblock*> [#uses=1]
+	%56 = load i32* %.SV208.phi, align 8		; <i32> [#uses=1]
+	br label %meshBB324
+
+bb15.fragment:		; preds = %meshBB324
+	%Opq.sa.calc925 = xor i32 %Opq.sa.calc750, 215		; <i32> [#uses=2]
+	%57 = sext i32 %.SV214.phi to i64		; <i64> [#uses=1]
+	%58 = getelementptr %struct.Macroblock* %.SV212.phi, i64 %57, i32 20		; <i32*> [#uses=1]
+	%59 = load i32* %58, align 4		; <i32> [#uses=1]
+	%60 = icmp eq i32 %59, 0		; <i1> [#uses=1]
+	br i1 %60, label %bb16, label %bb96
+
+bb16:		; preds = %bb15.fragment
+	%Opq.sa.calc499 = sub i32 %Opq.sa.calc925, -140		; <i32> [#uses=0]
+	%61 = add i32 %.SV87.phi, 1		; <i32> [#uses=1]
+	br label %bb16.fragment
+
+bb16.fragment:		; preds = %bb16
+	%Opq.sa.calc968 = add i32 %Opq.sa.calc925, 129		; <i32> [#uses=0]
+	store i32 %61, i32* %.SV91.phi, align 4
+	%62 = shl i32 %yN, 1		; <i32> [#uses=1]
+	br label %bb96
+
+bb19:		; preds = %meshBB412
+	%Opq.sa.calc502 = sub i32 %Opq.sa.calc932, -94		; <i32> [#uses=0]
+	%63 = add i32 %.SV87.phi1030, 1		; <i32> [#uses=1]
+	%64 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	br label %bb19.fragment
+
+bb19.fragment:		; preds = %bb19
+	%Opq.sa.calc880 = xor i32 %Opq.sa.calc932, 246		; <i32> [#uses=0]
+	store i32 %63, i32* %64, align 4
+	%65 = getelementptr %struct.Macroblock* %2, i64 %3, i32 29		; <i32*> [#uses=1]
+	%66 = load i32* %65, align 8		; <i32> [#uses=2]
+	store i32 %66, i32* %.SV52.phi1186, align 4
+	br label %bb96
+
+bb21:		; preds = %meshBB392
+	%Opq.sa.calc505 = add i32 %Opq.sa.calc921, -40		; <i32> [#uses=2]
+	br i1 %or.cond.not.SV.phi, label %meshBB360, label %bb97
+
+bb23:		; preds = %meshBB360
+	%Opq.sa.calc509 = xor i32 %Opq.sa.calc866, 70		; <i32> [#uses=1]
+	%Opq.sa.calc508 = sub i32 %Opq.sa.calc509, -19		; <i32> [#uses=0]
+	%67 = getelementptr %struct.Macroblock* %2, i64 %3, i32 20		; <i32*> [#uses=1]
+	%68 = load i32* %67, align 4		; <i32> [#uses=1]
+	%69 = icmp eq i32 %68, 0		; <i1> [#uses=1]
+	%70 = and i32 %curr_mb_nr, 1		; <i32> [#uses=1]
+	%71 = icmp eq i32 %70, 0		; <i1> [#uses=2]
+	br label %bb23.fragment
+
+bb23.fragment:		; preds = %bb23
+	%Opq.sa.calc847 = sub i32 %Opq.sa.calc866, -9		; <i32> [#uses=2]
+	%72 = getelementptr %struct.Macroblock* %2, i64 %3, i32 22		; <i32*> [#uses=3]
+	%73 = load i32* %72, align 4		; <i32> [#uses=3]
+	%74 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=3]
+	store i32 %73, i32* %74, align 4
+	br label %bb23.fragment182
+
+bb23.fragment182:		; preds = %bb23.fragment
+	%Opq.sa.calc744 = xor i32 %Opq.sa.calc847, 152		; <i32> [#uses=4]
+	%Opq.sa.calc742 = add i32 %Opq.sa.calc744, %Opq.sa.calc847		; <i32> [#uses=1]
+	%Opq.sa.calc743 = add i32 %Opq.sa.calc742, -149		; <i32> [#uses=2]
+	%75 = getelementptr %struct.Macroblock* %2, i64 %3, i32 26		; <i32*> [#uses=2]
+	%76 = load i32* %75, align 4		; <i32> [#uses=3]
+	store i32 %76, i32* %.SV52.phi1113, align 4
+	%77 = load i32* %75, align 4		; <i32> [#uses=1]
+	%78 = icmp ne i32 %77, 0		; <i1> [#uses=2]
+	br i1 %69, label %meshBB344, label %meshBB432
+
+bb24:		; preds = %meshBB344
+	%Opq.sa.calc512 = add i32 %Opq.sa.calc716, -55		; <i32> [#uses=3]
+	br i1 %.SV96.phi, label %bb25, label %bb32
+
+bb25:		; preds = %bb24
+	%Opq.sa.calc515 = sub i32 %Opq.sa.calc716, 18		; <i32> [#uses=1]
+	br i1 %.SV135.phi, label %bb26, label %bb96
+
+bb26:		; preds = %bb25
+	%Opq.sa.calc519 = xor i32 %Opq.sa.calc515, 23		; <i32> [#uses=2]
+	%Opq.sa.calc518 = xor i32 %Opq.sa.calc519, 84		; <i32> [#uses=1]
+	%79 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%80 = getelementptr %struct.ImageParameters* %79, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%81 = load %struct.Macroblock** %80, align 8		; <%struct.Macroblock*> [#uses=1]
+	%82 = load i32* %.SV99.phi, align 4		; <i32> [#uses=1]
+	br label %meshBB340
+
+bb26.fragment:		; preds = %meshBB340
+	%Opq.sa.calc918 = xor i32 %Opq.sa.calc754, 228		; <i32> [#uses=4]
+	%Opq.sa.calc916 = add i32 %Opq.sa.calc918, %Opq.sa.calc754		; <i32> [#uses=1]
+	%Opq.sa.calc917 = add i32 %Opq.sa.calc916, -237		; <i32> [#uses=1]
+	%83 = sext i32 %.SV230.phi to i64		; <i64> [#uses=1]
+	%84 = getelementptr %struct.Macroblock* %.SV228.phi, i64 %83, i32 20		; <i32*> [#uses=1]
+	%85 = load i32* %84, align 4		; <i32> [#uses=1]
+	%86 = icmp eq i32 %85, 0		; <i1> [#uses=1]
+	br i1 %86, label %meshBB420, label %meshBB356
+
+bb28:		; preds = %meshBB356
+	%Opq.sa.calc522 = xor i32 %Opq.sa.calc983, 107		; <i32> [#uses=2]
+	%87 = and i32 %yN, 1		; <i32> [#uses=1]
+	%88 = icmp eq i32 %87, 0		; <i1> [#uses=1]
+	br i1 %88, label %bb29, label %bb30
+
+bb29:		; preds = %bb28
+	%Opq.sa.calc525 = xor i32 %Opq.sa.calc522, 151		; <i32> [#uses=2]
+	%89 = ashr i32 %yN, 1		; <i32> [#uses=1]
+	br label %meshBB340
+
+bb30:		; preds = %bb28
+	%Opq.sa.calc528 = sub i32 %Opq.sa.calc522, -64		; <i32> [#uses=1]
+	%90 = add i32 %.SV104.phi1160, 1		; <i32> [#uses=1]
+	br label %bb30.fragment
+
+bb30.fragment:		; preds = %bb30
+	%Opq.sa.calc791 = add i32 %Opq.sa.calc528, -14		; <i32> [#uses=0]
+	store i32 %90, i32* %.SV111.phi1159, align 4
+	%91 = ashr i32 %yN, 1		; <i32> [#uses=1]
+	br label %bb96
+
+bb32:		; preds = %bb24
+	%Opq.sa.calc531 = xor i32 %Opq.sa.calc512, 50		; <i32> [#uses=1]
+	br i1 %.SV135.phi, label %bb33, label %meshBB324
+
+bb33:		; preds = %bb32
+	%Opq.sa.calc534 = sub i32 %Opq.sa.calc512, -75		; <i32> [#uses=2]
+	%92 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%93 = getelementptr %struct.ImageParameters* %92, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%94 = load %struct.Macroblock** %93, align 8		; <%struct.Macroblock*> [#uses=1]
+	%95 = load i32* %.SV99.phi, align 4		; <i32> [#uses=1]
+	br label %bb33.fragment
+
+bb33.fragment:		; preds = %bb33
+	%Opq.sa.calc712 = add i32 %Opq.sa.calc534, -109		; <i32> [#uses=3]
+	%96 = sext i32 %95 to i64		; <i64> [#uses=1]
+	%97 = getelementptr %struct.Macroblock* %94, i64 %96, i32 20		; <i32*> [#uses=1]
+	%98 = load i32* %97, align 4		; <i32> [#uses=1]
+	%99 = icmp eq i32 %98, 0		; <i1> [#uses=1]
+	br i1 %99, label %bb34, label %meshBB
+
+bb34:		; preds = %bb33.fragment
+	%Opq.sa.calc537 = add i32 %Opq.sa.calc712, 8		; <i32> [#uses=1]
+	%100 = add i32 %.SV104.phi, 1		; <i32> [#uses=1]
+	br label %meshBB328
+
+bb34.fragment:		; preds = %meshBB328
+	%Opq.sa.calc965 = xor i32 %Opq.sa.calc787, 251		; <i32> [#uses=0]
+	store i32 %.SV238.phi, i32* %.load116.SV.phi, align 4
+	br label %bb96
+
+bb35:		; preds = %meshBB
+	%Opq.sa.calc541 = add i32 %Opq.sa.calc828, -112		; <i32> [#uses=3]
+	%Opq.sa.calc540 = xor i32 %Opq.sa.calc541, 3		; <i32> [#uses=1]
+	%101 = and i32 %yN, 1		; <i32> [#uses=1]
+	%102 = icmp eq i32 %101, 0		; <i1> [#uses=1]
+	br i1 %102, label %meshBB372, label %meshBB448
+
+bb36:		; preds = %meshBB372
+	%Opq.sa.calc544 = sub i32 %Opq.sa.calc812, -10		; <i32> [#uses=0]
+	%103 = add i32 %.SV43.phi1015, %yN		; <i32> [#uses=1]
+	br label %bb36.fragment
+
+bb36.fragment:		; preds = %bb36
+	%Opq.sa.calc762 = add i32 %Opq.sa.calc812, -69		; <i32> [#uses=0]
+	%104 = ashr i32 %103, 1		; <i32> [#uses=1]
+	br label %bb96
+
+bb37:		; preds = %meshBB448
+	%Opq.sa.calc547 = add i32 %Opq.sa.calc958, -49		; <i32> [#uses=1]
+	%105 = add i32 %.SV104.phi1157, 1		; <i32> [#uses=1]
+	br label %meshBB348
+
+bb37.fragment:		; preds = %meshBB348
+	%Opq.sa.calc728 = add i32 %Opq.sa.calc805, -5		; <i32> [#uses=0]
+	store i32 %.SV242.phi, i32* %.load115.SV.phi, align 4
+	%106 = add i32 %.load48.SV.phi, %yN		; <i32> [#uses=1]
+	%107 = ashr i32 %106, 1		; <i32> [#uses=1]
+	br label %bb96
+
+bb39:		; preds = %meshBB432
+	%Opq.sa.calc550 = sub i32 %Opq.sa.calc798, -214		; <i32> [#uses=0]
+	br i1 %.SV96.phi1038, label %bb40, label %bb48
+
+bb40:		; preds = %bb39
+	%Opq.sa.calc554 = xor i32 %Opq.sa.calc798, 14		; <i32> [#uses=4]
+	%Opq.sa.calc553 = sub i32 %Opq.sa.calc554, 7		; <i32> [#uses=1]
+	br i1 %.SV135.phi1039, label %meshBB336, label %meshBB444
+
+bb41:		; preds = %meshBB336
+	%Opq.sa.calc557 = sub i32 %Opq.sa.calc979, 143		; <i32> [#uses=1]
+	%108 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%109 = getelementptr %struct.ImageParameters* %108, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%110 = load %struct.Macroblock** %109, align 8		; <%struct.Macroblock*> [#uses=1]
+	%111 = load i32* %.SV99.phi1128, align 4		; <i32> [#uses=1]
+	br label %bb41.fragment
+
+bb41.fragment:		; preds = %bb41
+	%Opq.sa.calc987 = xor i32 %Opq.sa.calc557, 213		; <i32> [#uses=4]
+	%112 = sext i32 %111 to i64		; <i64> [#uses=1]
+	%113 = getelementptr %struct.Macroblock* %110, i64 %112, i32 20		; <i32*> [#uses=1]
+	%114 = load i32* %113, align 4		; <i32> [#uses=1]
+	%115 = icmp eq i32 %114, 0		; <i1> [#uses=1]
+	br i1 %115, label %bb42, label %bb96
+
+bb42:		; preds = %bb41.fragment
+	%Opq.sa.calc560 = add i32 %Opq.sa.calc987, -221		; <i32> [#uses=1]
+	%116 = ashr i32 %.SV43.phi1230, 1		; <i32> [#uses=1]
+	%117 = icmp sgt i32 %116, %yN		; <i1> [#uses=1]
+	br i1 %117, label %meshBB432, label %bb44
+
+bb43:		; preds = %meshBB432
+	%Opq.sa.calc563 = xor i32 %Opq.sa.calc798, 31		; <i32> [#uses=0]
+	%118 = shl i32 %yN, 1		; <i32> [#uses=1]
+	br label %bb96
+
+bb44:		; preds = %bb42
+	%Opq.sa.calc566 = sub i32 %Opq.sa.calc987, 217		; <i32> [#uses=1]
+	%119 = add i32 %.SV104.phi1127, 1		; <i32> [#uses=1]
+	br label %meshBB332
+
+bb44.fragment:		; preds = %meshBB332
+	%Opq.sa.calc894 = add i32 %Opq.sa.calc856, -200		; <i32> [#uses=1]
+	store i32 %.SV248.phi, i32* %.load114.SV.phi, align 4
+	%120 = shl i32 %yN, 1		; <i32> [#uses=1]
+	%121 = sub i32 %120, %.load46.SV.phi		; <i32> [#uses=1]
+	br label %meshBB376
+
+bb48:		; preds = %bb39
+	%Opq.sa.calc569 = sub i32 %Opq.sa.calc798, -110		; <i32> [#uses=1]
+	br i1 %.SV135.phi1039, label %bb49, label %bb96
+
+bb49:		; preds = %bb48
+	%Opq.sa.calc572 = add i32 %Opq.sa.calc798, 84		; <i32> [#uses=0]
+	%122 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%123 = getelementptr %struct.ImageParameters* %122, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%124 = load %struct.Macroblock** %123, align 8		; <%struct.Macroblock*> [#uses=1]
+	%125 = load i32* %.SV99.phi1037, align 4		; <i32> [#uses=1]
+	br label %bb49.fragment
+
+bb49.fragment:		; preds = %bb49
+	%Opq.sa.calc860 = sub i32 %Opq.sa.calc569, 114		; <i32> [#uses=5]
+	%126 = sext i32 %125 to i64		; <i64> [#uses=1]
+	%127 = getelementptr %struct.Macroblock* %124, i64 %126, i32 20		; <i32*> [#uses=1]
+	%128 = load i32* %127, align 4		; <i32> [#uses=1]
+	%129 = icmp eq i32 %128, 0		; <i1> [#uses=1]
+	br i1 %129, label %bb50, label %meshBB380
+
+bb50:		; preds = %bb49.fragment
+	%Opq.sa.calc577 = add i32 %Opq.sa.calc860, 12		; <i32> [#uses=2]
+	%130 = ashr i32 %.SV43.phi1178, 1		; <i32> [#uses=1]
+	%131 = icmp sgt i32 %130, %yN		; <i1> [#uses=1]
+	br i1 %131, label %meshBB328, label %bb52
+
+bb51:		; preds = %meshBB328
+	%Opq.sa.calc580 = xor i32 %Opq.sa.calc787, 194		; <i32> [#uses=0]
+	%132 = shl i32 %yN, 1		; <i32> [#uses=1]
+	%133 = or i32 %132, 1		; <i32> [#uses=1]
+	br label %bb96
+
+bb52:		; preds = %bb50
+	%Opq.sa.calc584 = sub i32 %Opq.sa.calc860, -65		; <i32> [#uses=2]
+	%Opq.sa.calc583 = sub i32 %Opq.sa.calc584, 50		; <i32> [#uses=1]
+	%134 = add i32 %.SV104.phi1036, 1		; <i32> [#uses=1]
+	store i32 %134, i32* %.SV111.phi1035, align 4
+	br label %meshBB384
+
+bb52.fragment:		; preds = %meshBB384
+	%Opq.sa.calc844 = add i32 %Opq.sa.calc901, -214		; <i32> [#uses=1]
+	%135 = shl i32 %yN, 1		; <i32> [#uses=1]
+	%136 = or i32 %135, 1		; <i32> [#uses=1]
+	%137 = sub i32 %136, %.load44.SV.phi		; <i32> [#uses=1]
+	br label %meshBB388
+
+bb54:		; preds = %meshBB380
+	%Opq.sa.calc589 = add i32 %Opq.sa.calc946, 108		; <i32> [#uses=1]
+	%138 = add i32 %.SV104.phi1124, 1		; <i32> [#uses=1]
+	br label %bb54.fragment
+
+bb54.fragment:		; preds = %bb54
+	%Opq.sa.calc883 = xor i32 %Opq.sa.calc589, 119		; <i32> [#uses=2]
+	store i32 %138, i32* %.SV111.phi1123, align 4
+	br label %meshBB440
+
+bb56:		; preds = %meshBB404
+	%Opq.sa.calc592 = sub i32 %Opq.sa.calc939, 87		; <i32> [#uses=2]
+	%.not4 = icmp sgt i32 %xN, -1		; <i1> [#uses=1]
+	%139 = icmp sgt i32 %.SV40.phi, %xN		; <i1> [#uses=1]
+	br label %meshBB364
+
+bb56.fragment:		; preds = %meshBB364
+	%Opq.sa.calc1002 = xor i32 %Opq.link.mask737, 77		; <i32> [#uses=6]
+	%or.cond5 = and i1 %.SV256.phi, %.not4.SV.phi		; <i1> [#uses=1]
+	%140 = icmp slt i32 %yN, 0		; <i1> [#uses=2]
+	br i1 %or.cond5, label %bb58, label %bb83
+
+bb58:		; preds = %bb56.fragment
+	%Opq.sa.calc596 = xor i32 %Opq.sa.calc1002, 73		; <i32> [#uses=1]
+	%Opq.sa.calc595 = add i32 %Opq.sa.calc596, 147		; <i32> [#uses=0]
+	br i1 %140, label %bb59, label %bb76
+
+bb59:		; preds = %bb58
+	%Opq.sa.calc599 = add i32 %Opq.sa.calc1002, 151		; <i32> [#uses=0]
+	%141 = getelementptr %struct.Macroblock* %2, i64 %3, i32 20		; <i32*> [#uses=1]
+	%142 = load i32* %141, align 4		; <i32> [#uses=1]
+	br label %bb59.fragment
+
+bb59.fragment:		; preds = %bb59
+	%Opq.sa.calc731 = sub i32 %Opq.sa.calc1002, -161		; <i32> [#uses=3]
+	%143 = icmp eq i32 %142, 0		; <i1> [#uses=1]
+	%144 = and i32 %curr_mb_nr, 1		; <i32> [#uses=1]
+	%145 = icmp eq i32 %144, 0		; <i1> [#uses=2]
+	br i1 %143, label %bb60, label %bb68
+
+bb60:		; preds = %bb59.fragment
+	%Opq.sa.calc602 = xor i32 %Opq.sa.calc731, 1		; <i32> [#uses=2]
+	br i1 %145, label %bb61, label %bb66
+
+bb61:		; preds = %bb60
+	%Opq.sa.calc605 = xor i32 %Opq.sa.calc731, 57		; <i32> [#uses=1]
+	%146 = getelementptr %struct.Macroblock* %2, i64 %3, i32 23		; <i32*> [#uses=2]
+	%147 = load i32* %146, align 8		; <i32> [#uses=3]
+	%148 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=3]
+	br label %bb61.fragment
+
+bb61.fragment:		; preds = %bb61
+	%Opq.sa.calc700 = sub i32 %Opq.sa.calc605, 108		; <i32> [#uses=3]
+	store i32 %147, i32* %148, align 4
+	%149 = getelementptr %struct.Macroblock* %2, i64 %3, i32 27		; <i32*> [#uses=4]
+	%150 = load i32* %149, align 8		; <i32> [#uses=1]
+	%151 = icmp eq i32 %150, 0		; <i1> [#uses=1]
+	br i1 %151, label %bb65, label %bb62
+
+bb62:		; preds = %bb61.fragment
+	%Opq.sa.calc608 = add i32 %Opq.sa.calc700, -94		; <i32> [#uses=1]
+	%152 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=2]
+	%153 = getelementptr %struct.ImageParameters* %152, i64 0, i32 45		; <i32*> [#uses=1]
+	%154 = load i32* %153, align 4		; <i32> [#uses=1]
+	%155 = icmp eq i32 %154, 1		; <i1> [#uses=1]
+	br i1 %155, label %bb63, label %bb64
+
+bb63:		; preds = %bb62
+	%Opq.sa.calc611 = add i32 %Opq.sa.calc700, -101		; <i32> [#uses=2]
+	%156 = getelementptr %struct.ImageParameters* %152, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%157 = load %struct.Macroblock** %156, align 8		; <%struct.Macroblock*> [#uses=1]
+	%158 = load i32* %146, align 8		; <i32> [#uses=1]
+	br label %meshBB452
+
+bb63.fragment:		; preds = %meshBB452
+	%Opq.sa.calc891 = add i32 %Opq.link.mask823, 18		; <i32> [#uses=2]
+	%Opq.sa.calc890 = add i32 %Opq.sa.calc891, -3		; <i32> [#uses=2]
+	%159 = sext i32 %.SV266.phi to i64		; <i64> [#uses=1]
+	%160 = getelementptr %struct.Macroblock* %.SV264.phi, i64 %159, i32 20		; <i32*> [#uses=1]
+	%161 = load i32* %160, align 4		; <i32> [#uses=1]
+	%162 = icmp eq i32 %161, 0		; <i1> [#uses=1]
+	br i1 %162, label %bb64, label %meshBB456
+
+bb64:		; preds = %bb63.fragment, %bb62
+	%.SV38.phi1132 = phi i64 [ %.SV38.phi1110, %bb63.fragment ], [ %.SV38.phi1098, %bb62 ]		; <i64> [#uses=1]
+	%.SV52.phi1131 = phi i32* [ %.SV52.phi1109, %bb63.fragment ], [ %.SV52.phi1097, %bb62 ]		; <i32*> [#uses=1]
+	%.SV68.phi1130 = phi i32 [ %.SV68.phi1108, %bb63.fragment ], [ %.SV68.phi1096, %bb62 ]		; <i32> [#uses=1]
+	%.SV70.phi1129 = phi i32 [ %.SV70.phi1107, %bb63.fragment ], [ %.SV70.phi1095, %bb62 ]		; <i32> [#uses=1]
+	%Opq.link.SV615.phi = phi i32 [ %Opq.sa.calc890, %bb63.fragment ], [ %Opq.sa.calc608, %bb62 ]		; <i32> [#uses=1]
+	%.SV150.phi = phi i32* [ %.SV150.phi1060, %bb63.fragment ], [ %148, %bb62 ]		; <i32*> [#uses=1]
+	%.SV152.phi = phi i32* [ %.SV152.phi1059, %bb63.fragment ], [ %149, %bb62 ]		; <i32*> [#uses=1]
+	%.SV148.phi = phi i32 [ %.SV148.phi1057, %bb63.fragment ], [ %147, %bb62 ]		; <i32> [#uses=1]
+	%Opq.link.mask = and i32 %Opq.link.SV615.phi, 1		; <i32> [#uses=1]
+	%Opq.sa.calc614 = add i32 %Opq.link.mask, 189		; <i32> [#uses=1]
+	%163 = add i32 %.SV148.phi, 1		; <i32> [#uses=1]
+	store i32 %163, i32* %.SV150.phi, align 4
+	br label %bb65
+
+bb65:		; preds = %meshBB456, %bb64, %bb61.fragment
+	%.SV38.phi1144 = phi i64 [ %.SV38.phi1137, %meshBB456 ], [ %.SV38.phi1098, %bb61.fragment ], [ %.SV38.phi1132, %bb64 ]		; <i64> [#uses=1]
+	%.SV52.phi1143 = phi i32* [ %.SV52.phi1136, %meshBB456 ], [ %.SV52.phi1097, %bb61.fragment ], [ %.SV52.phi1131, %bb64 ]		; <i32*> [#uses=1]
+	%.SV68.phi1142 = phi i32 [ %.SV68.phi1135, %meshBB456 ], [ %.SV68.phi1096, %bb61.fragment ], [ %.SV68.phi1130, %bb64 ]		; <i32> [#uses=1]
+	%.SV70.phi1141 = phi i32 [ %.SV70.phi1134, %meshBB456 ], [ %.SV70.phi1095, %bb61.fragment ], [ %.SV70.phi1129, %bb64 ]		; <i32> [#uses=1]
+	%.SV152.phi1058 = phi i32* [ %.SV152.phi1133, %meshBB456 ], [ %149, %bb61.fragment ], [ %.SV152.phi, %bb64 ]		; <i32*> [#uses=1]
+	%Opq.link.SV618.phi = phi i32 [ %Opq.sa.calc816, %meshBB456 ], [ %Opq.sa.calc700, %bb61.fragment ], [ %Opq.sa.calc614, %bb64 ]		; <i32> [#uses=1]
+	%Opq.link.mask620 = and i32 %Opq.link.SV618.phi, 40		; <i32> [#uses=1]
+	%Opq.sa.calc617 = add i32 %Opq.link.mask620, -35		; <i32> [#uses=2]
+	%164 = load i32* %.SV152.phi1058, align 8		; <i32> [#uses=1]
+	br label %meshBB436
+
+bb65.fragment:		; preds = %meshBB436
+	%Opq.sa.calc832 = add i32 %Opq.link.mask706, 1		; <i32> [#uses=2]
+	store i32 %.SV268.phi, i32* %.load62.SV.phi, align 4
+	br label %meshBB364
+
+bb66:		; preds = %bb60
+	%Opq.sa.calc621 = add i32 %Opq.sa.calc602, -217		; <i32> [#uses=1]
+	%165 = add i32 %curr_mb_nr, -1		; <i32> [#uses=1]
+	%166 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	br label %meshBB420
+
+bb66.fragment:		; preds = %meshBB420
+	%Opq.sa.calc795 = xor i32 %Opq.sa.calc837, 105		; <i32> [#uses=2]
+	%Opq.sa.calc794 = sub i32 %Opq.sa.calc795, 167		; <i32> [#uses=1]
+	store i32 %.SV270.phi, i32* %.SV272.phi, align 4
+	store i32 1, i32* %.load61.SV.phi, align 4
+	br label %meshBB444
+
+bb68:		; preds = %bb59.fragment
+	%Opq.sa.calc624 = sub i32 %Opq.sa.calc731, 229		; <i32> [#uses=3]
+	%167 = getelementptr %struct.Macroblock* %2, i64 %3, i32 23		; <i32*> [#uses=1]
+	br label %meshBB344
+
+bb68.fragment:		; preds = %meshBB344
+	%Opq.sa.calc784 = sub i32 %Opq.link.mask722, 3		; <i32> [#uses=5]
+	%168 = load i32* %.SV274.phi, align 8		; <i32> [#uses=3]
+	br i1 %.load144.SV.phi, label %bb69, label %meshBB412
+
+bb69:		; preds = %bb68.fragment
+	%Opq.sa.calc627 = add i32 %Opq.sa.calc784, 163		; <i32> [#uses=0]
+	%169 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=2]
+	store i32 %168, i32* %169, align 4
+	%170 = getelementptr %struct.Macroblock* %2, i64 %3, i32 27		; <i32*> [#uses=2]
+	br label %bb69.fragment
+
+bb69.fragment:		; preds = %bb69
+	%Opq.sa.calc996 = sub i32 %Opq.sa.calc784, -9		; <i32> [#uses=3]
+	%Opq.sa.calc994 = sub i32 %Opq.sa.calc996, %Opq.sa.calc784		; <i32> [#uses=1]
+	%Opq.sa.calc995 = sub i32 %Opq.sa.calc994, 3		; <i32> [#uses=2]
+	%171 = load i32* %170, align 8		; <i32> [#uses=3]
+	store i32 %171, i32* %.SV52.phi1170, align 4
+	%172 = load i32* %170, align 8		; <i32> [#uses=1]
+	%173 = icmp eq i32 %172, 0		; <i1> [#uses=1]
+	br i1 %173, label %meshBB396, label %meshBB400
+
+bb70:		; preds = %meshBB400
+	%Opq.sa.calc630 = add i32 %Opq.sa.calc824, -203		; <i32> [#uses=2]
+	%174 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%175 = getelementptr %struct.ImageParameters* %174, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%176 = load %struct.Macroblock** %175, align 8		; <%struct.Macroblock*> [#uses=1]
+	%177 = load i32* %.SV156.phi, align 8		; <i32> [#uses=1]
+	br label %meshBB428
+
+bb70.fragment:		; preds = %meshBB428
+	%Opq.sa.calc739 = xor i32 %Opq.sa.calc897, 213		; <i32> [#uses=2]
+	%Opq.sa.calc738 = sub i32 %Opq.sa.calc739, 1		; <i32> [#uses=2]
+	%178 = sext i32 %.SV280.phi to i64		; <i64> [#uses=1]
+	%179 = getelementptr %struct.Macroblock* %.SV278.phi, i64 %178, i32 20		; <i32*> [#uses=1]
+	%180 = load i32* %179, align 4		; <i32> [#uses=1]
+	%181 = icmp eq i32 %180, 0		; <i1> [#uses=1]
+	br i1 %181, label %meshBB452, label %meshBB356
+
+bb71:		; preds = %meshBB452
+	%Opq.sa.calc633 = xor i32 %Opq.sa.calc820, 118		; <i32> [#uses=1]
+	%182 = add i32 %.SV158.phi1106, 1		; <i32> [#uses=1]
+	br label %meshBB352
+
+bb71.fragment:		; preds = %meshBB352
+	%Opq.sa.calc809 = sub i32 %Opq.sa.calc876, 17		; <i32> [#uses=2]
+	store i32 %.SV282.phi, i32* %.load163.SV.phi, align 4
+	%183 = shl i32 %yN, 1		; <i32> [#uses=1]
+	br label %meshBB436
+
+bb74:		; preds = %meshBB412
+	%Opq.sa.calc636 = xor i32 %Opq.sa.calc932, 233		; <i32> [#uses=1]
+	%184 = add i32 %.SV158.phi1063, 1		; <i32> [#uses=1]
+	%185 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	br label %bb74.fragment
+
+bb74.fragment:		; preds = %bb74
+	%Opq.sa.calc1011 = sub i32 %Opq.sa.calc636, -19		; <i32> [#uses=0]
+	store i32 %184, i32* %185, align 4
+	%186 = getelementptr %struct.Macroblock* %2, i64 %3, i32 27		; <i32*> [#uses=1]
+	%187 = load i32* %186, align 8		; <i32> [#uses=2]
+	store i32 %187, i32* %.SV52.phi1186, align 4
+	br label %bb96
+
+bb76:		; preds = %bb58
+	%Opq.sa.calc640 = xor i32 %Opq.sa.calc1002, 71		; <i32> [#uses=4]
+	%Opq.sa.calc639 = xor i32 %Opq.sa.calc640, 219		; <i32> [#uses=0]
+	%188 = icmp eq i32 %yN, 0		; <i1> [#uses=1]
+	br i1 %188, label %bb77, label %bb79
+
+bb77:		; preds = %bb76
+	%Opq.sa.calc643 = add i32 %Opq.sa.calc640, 2		; <i32> [#uses=2]
+	%189 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%190 = getelementptr %struct.ImageParameters* %189, i64 0, i32 45		; <i32*> [#uses=1]
+	%191 = load i32* %190, align 4		; <i32> [#uses=1]
+	%192 = icmp eq i32 %191, 2		; <i1> [#uses=1]
+	br i1 %192, label %meshBB416, label %bb79
+
+bb78:		; preds = %meshBB416
+	%Opq.sa.calc647 = xor i32 %Opq.sa.calc971, 25		; <i32> [#uses=2]
+	%Opq.sa.calc646 = sub i32 %Opq.sa.calc647, 29		; <i32> [#uses=0]
+	%193 = getelementptr %struct.Macroblock* %2, i64 %3, i32 23		; <i32*> [#uses=1]
+	%194 = load i32* %193, align 8		; <i32> [#uses=1]
+	%195 = add i32 %194, 1		; <i32> [#uses=1]
+	br label %bb78.fragment
+
+bb78.fragment:		; preds = %bb78
+	%Opq.sa.calc850 = sub i32 %Opq.sa.calc647, -93		; <i32> [#uses=0]
+	%196 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	store i32 %195, i32* %196, align 4
+	store i32 1, i32* %.SV52.phi1200, align 4
+	%197 = add i32 %yN, -1		; <i32> [#uses=1]
+	br label %bb98
+
+bb79:		; preds = %bb77, %bb76
+	%Opq.link.SV652.phi = phi i32 [ %Opq.sa.calc643, %bb77 ], [ %Opq.sa.calc640, %bb76 ]		; <i32> [#uses=1]
+	%Opq.link.mask654 = and i32 %Opq.link.SV652.phi, 8		; <i32> [#uses=1]
+	%Opq.sa.calc651 = sub i32 %Opq.link.mask654, -2		; <i32> [#uses=3]
+	%Opq.sa.calc650 = xor i32 %Opq.sa.calc651, 1		; <i32> [#uses=2]
+	br i1 %or.cond.not.SV.phi1094, label %meshBB456, label %meshBB352
+
+bb81:		; preds = %meshBB456
+	%Opq.sa.calc655 = add i32 %Opq.sa.calc816, 56		; <i32> [#uses=0]
+	%198 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	store i32 %curr_mb_nr, i32* %198, align 4
+	store i32 1, i32* %.SV52.phi1136, align 4
+	br label %bb98
+
+bb83:		; preds = %bb56.fragment
+	%Opq.sa.calc658 = sub i32 %Opq.sa.calc1002, 73		; <i32> [#uses=3]
+	br i1 %140, label %bb84, label %meshBB424
+
+bb84:		; preds = %bb83
+	%Opq.sa.calc661 = xor i32 %Opq.sa.calc658, 22		; <i32> [#uses=1]
+	%199 = getelementptr %struct.Macroblock* %2, i64 %3, i32 20		; <i32*> [#uses=1]
+	%200 = load i32* %199, align 4		; <i32> [#uses=1]
+	br label %meshBB400
+
+bb84.fragment:		; preds = %meshBB400
+	%Opq.sa.calc802 = xor i32 %Opq.sa.calc824, 240		; <i32> [#uses=3]
+	%201 = icmp eq i32 %.SV290.phi, 0		; <i1> [#uses=1]
+	%202 = and i32 %curr_mb_nr, 1		; <i32> [#uses=1]
+	%203 = icmp eq i32 %202, 0		; <i1> [#uses=2]
+	br i1 %201, label %meshBB372, label %bb89
+
+bb85:		; preds = %meshBB372
+	%Opq.sa.calc667 = sub i32 %Opq.sa.calc812, 20		; <i32> [#uses=3]
+	%Opq.sa.calc666 = sub i32 %Opq.sa.calc667, 84		; <i32> [#uses=2]
+	%Opq.sa.calc664 = add i32 %Opq.sa.calc666, %Opq.sa.calc667		; <i32> [#uses=1]
+	%Opq.sa.calc665 = add i32 %Opq.sa.calc664, -112		; <i32> [#uses=2]
+	br i1 %.SV167.phi, label %meshBB336, label %meshBB440
+
+bb86:		; preds = %meshBB336
+	%Opq.sa.calc670 = sub i32 %Opq.sa.calc979, 35		; <i32> [#uses=1]
+	%204 = getelementptr %struct.Macroblock* %2, i64 %3, i32 24		; <i32*> [#uses=1]
+	%205 = load i32* %204, align 4		; <i32> [#uses=1]
+	%206 = add i32 %205, 1		; <i32> [#uses=1]
+	%207 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	br label %bb86.fragment
+
+bb86.fragment:		; preds = %bb86
+	%Opq.sa.calc943 = xor i32 %Opq.sa.calc670, 123		; <i32> [#uses=2]
+	store i32 %206, i32* %207, align 4
+	%208 = getelementptr %struct.Macroblock* %2, i64 %3, i32 28		; <i32*> [#uses=1]
+	%209 = load i32* %208, align 4		; <i32> [#uses=2]
+	store i32 %209, i32* %.SV52.phi1234, align 4
+	br label %meshBB424
+
+bb87:		; preds = %meshBB440
+	%Opq.sa.calc674 = xor i32 %Opq.sa.calc990, 44		; <i32> [#uses=1]
+	%Opq.sa.calc673 = xor i32 %Opq.sa.calc674, 160		; <i32> [#uses=1]
+	store i32 0, i32* %.SV52.phi1235, align 4
+	br label %meshBB408
+
+bb89:		; preds = %bb84.fragment
+	%Opq.sa.calc677 = sub i32 %Opq.sa.calc802, -183		; <i32> [#uses=1]
+	%210 = getelementptr %struct.Macroblock* %2, i64 %3, i32 24		; <i32*> [#uses=2]
+	br label %bb89.fragment
+
+bb89.fragment:		; preds = %bb89
+	%Opq.sa.calc962 = add i32 %Opq.sa.calc677, -188		; <i32> [#uses=3]
+	%211 = load i32* %210, align 4		; <i32> [#uses=3]
+	br i1 %203, label %bb90, label %meshBB408
+
+bb90:		; preds = %bb89.fragment
+	%Opq.sa.calc680 = xor i32 %Opq.sa.calc962, 92		; <i32> [#uses=1]
+	%212 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=2]
+	store i32 %211, i32* %212, align 4
+	%213 = getelementptr %struct.Macroblock* %2, i64 %3, i32 28		; <i32*> [#uses=2]
+	br label %bb90.fragment
+
+bb90.fragment:		; preds = %bb90
+	%Opq.sa.calc773 = sub i32 %Opq.sa.calc680, 60		; <i32> [#uses=3]
+	%Opq.sa.calc772 = add i32 %Opq.sa.calc773, -25		; <i32> [#uses=2]
+	%214 = load i32* %213, align 4		; <i32> [#uses=3]
+	store i32 %214, i32* %.SV52.phi1190, align 4
+	%215 = load i32* %213, align 4		; <i32> [#uses=1]
+	%216 = icmp eq i32 %215, 0		; <i1> [#uses=1]
+	br i1 %216, label %meshBB416, label %meshBB368
+
+bb91:		; preds = %meshBB368
+	%Opq.sa.calc683 = sub i32 %Opq.sa.calc768, -7		; <i32> [#uses=0]
+	%217 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%218 = getelementptr %struct.ImageParameters* %217, i64 0, i32 39		; <%struct.Macroblock**> [#uses=1]
+	%219 = load %struct.Macroblock** %218, align 8		; <%struct.Macroblock*> [#uses=1]
+	%220 = load i32* %.SV170.phi, align 4		; <i32> [#uses=1]
+	br label %bb91.fragment
+
+bb91.fragment:		; preds = %bb91
+	%Opq.sa.calc853 = xor i32 %Opq.sa.calc768, 8		; <i32> [#uses=1]
+	%221 = sext i32 %220 to i64		; <i64> [#uses=1]
+	%222 = getelementptr %struct.Macroblock* %219, i64 %221, i32 20		; <i32*> [#uses=1]
+	%223 = load i32* %222, align 4		; <i32> [#uses=1]
+	%224 = icmp eq i32 %223, 0		; <i1> [#uses=1]
+	br i1 %224, label %bb92, label %bb96
+
+bb92:		; preds = %bb91.fragment
+	%Opq.sa.calc686 = xor i32 %Opq.sa.calc853, 2		; <i32> [#uses=1]
+	%225 = add i32 %.SV172.phi, 1		; <i32> [#uses=1]
+	br label %bb92.fragment
+
+bb92.fragment:		; preds = %bb92
+	%Opq.sa.calc1005 = xor i32 %Opq.sa.calc686, 130		; <i32> [#uses=2]
+	store i32 %225, i32* %.SV176.phi, align 4
+	%226 = shl i32 %yN, 1		; <i32> [#uses=1]
+	br label %meshBB380
+
+bb95:		; preds = %meshBB408
+	%Opq.sa.calc689 = xor i32 %Opq.sa.calc912, 207		; <i32> [#uses=3]
+	%227 = add i32 %.SV172.phi1074, 1		; <i32> [#uses=1]
+	%228 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	br label %meshBB384
+
+bb95.fragment:		; preds = %meshBB384
+	%Opq.sa.calc841 = sub i32 %Opq.sa.calc901, 76		; <i32> [#uses=0]
+	store i32 %.SV306.phi, i32* %.SV308.phi, align 4
+	%229 = getelementptr %struct.Macroblock* %.load.SV.phi, i64 %.load20.SV.phi, i32 28		; <i32*> [#uses=1]
+	%230 = load i32* %229, align 4		; <i32> [#uses=2]
+	store i32 %230, i32* %.load53.SV.phi, align 4
+	br label %bb96
+
+bb96:		; preds = %meshBB444, %meshBB440, %meshBB436, %meshBB424, %meshBB420, %meshBB416, %meshBB396, %meshBB388, %meshBB380, %meshBB376, %meshBB364, %meshBB356, %meshBB340, %meshBB324, %meshBB, %bb95.fragment, %bb91.fragment, %bb74.fragment, %bb51, %bb48, %bb43, %bb41.fragment, %bb37.fragment, %bb36.fragment, %bb34.fragment, %bb30.fragment, %bb25, %bb19.fragment, %bb16.fragment, %bb15.fragment, %bb11.fragment, %bb9.fragment, %bb8.fragment, %bb7.fragment
+	%.SV38.phi1087 = phi i64 [ %.SV38.phi1224, %meshBB444 ], [ %.SV38.phi1210, %meshBB440 ], [ %.SV38.phi1147, %meshBB436 ], [ %.SV38.phi1197, %meshBB424 ], [ %.SV38.phi1194, %meshBB420 ], [ %.SV38.phi1201, %meshBB416 ], [ %.SV38.phi, %meshBB396 ], [ %.SV38.phi1118, %meshBB388 ], [ %.SV38.phi1207, %meshBB380 ], [ %.SV38.phi1153, %meshBB376 ], [ %.SV38.phi1098, %meshBB364 ], [ %.SV38.phi1121, %meshBB356 ], [ %.SV38.phi1167, %meshBB340 ], [ %.SV38.phi1175, %meshBB324 ], [ %.SV38.phi1183, %meshBB ], [ %.SV38.phi1164, %bb91.fragment ], [ %.SV38.phi1179, %bb48 ], [ %.SV38.phi1231, %bb41.fragment ], [ %.SV38.phi1172, %bb25 ], [ %.SV38.phi1175, %bb15.fragment ], [ %.SV38.phi1164, %bb9.fragment ], [ %.SV38.phi1164, %bb8.fragment ], [ %.SV38.phi1221, %bb95.fragment ], [ %.SV38.phi1187, %bb74.fragment ], [ %.SV38.phi1227, %bb51 ], [ %.SV38.phi1179, %bb43 ], [ %.SV38.phi1103, %bb37.fragment ], [ %.SV38.phi1214, %bb36.fragment ], [ %.SV38.phi1227, %bb34.fragment ], [ %.SV38.phi1121, %bb30!
 .fragment ], [ %.SV38.phi1187, %bb19.fragment ], [ %.SV38.phi1175, %bb16.fragment ], [ %.SV38.phi1204, %bb11.fragment ], [ %.SV38.phi1118, %bb7.fragment ]		; <i64> [#uses=2]
+	%.SV68.phi1086 = phi i32 [ %.SV68.phi1223, %meshBB444 ], [ %.SV68.phi1209, %meshBB440 ], [ %.SV68.phi1146, %meshBB436 ], [ %.SV68.phi1196, %meshBB424 ], [ %.SV68.phi1193, %meshBB420 ], [ %.SV68.phi1199, %meshBB416 ], [ %.SV68.phi, %meshBB396 ], [ %.SV68.phi1117, %meshBB388 ], [ %.SV68.phi1206, %meshBB380 ], [ %.SV68.phi1152, %meshBB376 ], [ %.SV68.phi1096, %meshBB364 ], [ %.SV68.phi1120, %meshBB356 ], [ %.SV68.phi1166, %meshBB340 ], [ %.SV68.phi1174, %meshBB324 ], [ %.SV68.phi1181, %meshBB ], [ %.SV68.phi1162, %bb91.fragment ], [ %.SV68.phi1177, %bb48 ], [ %.SV68.phi1229, %bb41.fragment ], [ %.SV68.phi1169, %bb25 ], [ %.SV68.phi1174, %bb15.fragment ], [ %.SV68.phi1162, %bb9.fragment ], [ %.SV68.phi1162, %bb8.fragment ], [ %.SV68.phi1220, %bb95.fragment ], [ %.SV68.phi1185, %bb74.fragment ], [ %.SV68.phi1226, %bb51 ], [ %.SV68.phi1177, %bb43 ], [ %.SV68.phi1100, %bb37.fragment ], [ %.SV68.phi1212, %bb36.fragment ], [ %.SV68.phi1226, %bb34.fragment ], [ %.SV68.phi1120, %bb30!
 .fragment ], [ %.SV68.phi1185, %bb19.fragment ], [ %.SV68.phi1174, %bb16.fragment ], [ %.SV68.phi1203, %bb11.fragment ], [ %.SV68.phi1117, %bb7.fragment ]		; <i32> [#uses=2]
+	%.SV70.phi1085 = phi i32 [ %.SV70.phi1222, %meshBB444 ], [ %.SV70.phi1208, %meshBB440 ], [ %.SV70.phi1145, %meshBB436 ], [ %.SV70.phi1195, %meshBB424 ], [ %.SV70.phi1192, %meshBB420 ], [ %.SV70.phi1198, %meshBB416 ], [ %.SV70.phi, %meshBB396 ], [ %.SV70.phi1116, %meshBB388 ], [ %.SV70.phi1205, %meshBB380 ], [ %.SV70.phi1151, %meshBB376 ], [ %.SV70.phi1095, %meshBB364 ], [ %.SV70.phi1119, %meshBB356 ], [ %.SV70.phi1165, %meshBB340 ], [ %.SV70.phi1173, %meshBB324 ], [ %.SV70.phi1180, %meshBB ], [ %.SV70.phi1161, %bb91.fragment ], [ %.SV70.phi1176, %bb48 ], [ %.SV70.phi1228, %bb41.fragment ], [ %.SV70.phi1168, %bb25 ], [ %.SV70.phi1173, %bb15.fragment ], [ %.SV70.phi1161, %bb9.fragment ], [ %.SV70.phi1161, %bb8.fragment ], [ %.SV70.phi1219, %bb95.fragment ], [ %.SV70.phi1184, %bb74.fragment ], [ %.SV70.phi1225, %bb51 ], [ %.SV70.phi1176, %bb43 ], [ %.SV70.phi1099, %bb37.fragment ], [ %.SV70.phi1211, %bb36.fragment ], [ %.SV70.phi1225, %bb34.fragment ], [ %.SV70.phi1119, %bb30!
 .fragment ], [ %.SV70.phi1184, %bb19.fragment ], [ %.SV70.phi1173, %bb16.fragment ], [ %.SV70.phi1202, %bb11.fragment ], [ %.SV70.phi1116, %bb7.fragment ]		; <i32> [#uses=2]
+	%.SV.phi = phi i32 [ %.SV.phi1048, %meshBB444 ], [ %.SV.phi1056, %meshBB440 ], [ %.SV.phi1067, %meshBB436 ], [ %.SV.phi1072, %meshBB424 ], [ %.SV.phi1044, %meshBB420 ], [ %.SV.phi1076, %meshBB416 ], [ %.SV.phi1065, %meshBB396 ], [ %.SV.phi1054, %meshBB388 ], [ %.SV.phi1052, %meshBB380 ], [ %.SV.phi1050, %meshBB376 ], [ %.SV.phi1062, %meshBB364 ], [ %.SV.phi1046, %meshBB356 ], [ %.SV.phi1042, %meshBB340 ], [ %.SV.phi1032, %meshBB324 ], [ %.SV.phi1034, %meshBB ], [ %.SV178.phi, %bb91.fragment ], [ %.SV118.phi1040, %bb48 ], [ %.SV118.phi1125, %bb41.fragment ], [ %.SV118.phi, %bb25 ], [ %.load94.SV.phi, %bb15.fragment ], [ %32, %bb9.fragment ], [ %32, %bb8.fragment ], [ %230, %bb95.fragment ], [ %187, %bb74.fragment ], [ %.SV118.phi1081, %bb51 ], [ %.SV118.phi1040, %bb43 ], [ %.load131.SV.phi, %bb37.fragment ], [ %.SV118.phi1154, %bb36.fragment ], [ %.load129.SV.phi, %bb34.fragment ], [ %.SV118.phi1158, %bb30.fragment ], [ %66, %bb19.fragment ], [ %.SV93.phi, %bb16.fragment ],!
  [ %.load84.SV.phi, %bb11.fragment ], [ %27, %bb7.fragment ]		; <i32> [#uses=1]
+	%yM.0.SV.phi = phi i32 [ -1, %meshBB444 ], [ %yN, %meshBB440 ], [ %yM.0.SV.phi1066, %meshBB436 ], [ %yN, %meshBB424 ], [ %yN, %meshBB420 ], [ -1, %meshBB416 ], [ -1, %meshBB396 ], [ %yM.0.SV.phi1053, %meshBB388 ], [ %yM.0.SV.phi1051, %meshBB380 ], [ %yM.0.SV.phi1049, %meshBB376 ], [ %yN, %meshBB364 ], [ %yN, %meshBB356 ], [ %yM.0.SV.phi1041, %meshBB340 ], [ -1, %meshBB324 ], [ -1, %meshBB ], [ %yN, %bb91.fragment ], [ -1, %bb48 ], [ %yN, %bb41.fragment ], [ -1, %bb25 ], [ %yN, %bb15.fragment ], [ %yN, %bb9.fragment ], [ -1, %bb8.fragment ], [ %yN, %bb95.fragment ], [ %yN, %bb74.fragment ], [ %133, %bb51 ], [ %118, %bb43 ], [ %107, %bb37.fragment ], [ %104, %bb36.fragment ], [ %yN, %bb34.fragment ], [ %91, %bb30.fragment ], [ %yN, %bb19.fragment ], [ %62, %bb16.fragment ], [ %45, %bb11.fragment ], [ %yN, %bb7.fragment ]		; <i32> [#uses=2]
+	%Opq.sa.calc693 = add i32 0, 15		; <i32> [#uses=2]
+	%Opq.sa.calc692 = xor i32 %Opq.sa.calc693, 8		; <i32> [#uses=1]
+	%231 = icmp eq i32 %.SV.phi, 0		; <i1> [#uses=1]
+	br i1 %231, label %bb97, label %meshBB404
+
+bb97:		; preds = %meshBB424, %meshBB408, %meshBB352, %bb96, %bb21
+	%.SV38.phi1150 = phi i64 [ %.SV38.phi1197, %meshBB424 ], [ %.SV38.phi1218, %meshBB408 ], [ %.SV38.phi1140, %meshBB352 ], [ %.SV38.phi1087, %bb96 ], [ %4, %bb21 ]		; <i64> [#uses=1]
+	%.SV68.phi1149 = phi i32 [ %.SV68.phi1196, %meshBB424 ], [ %.SV68.phi1216, %meshBB408 ], [ %.SV68.phi1139, %meshBB352 ], [ %.SV68.phi1086, %bb96 ], [ %.SV68.phi1021, %bb21 ]		; <i32> [#uses=1]
+	%.SV70.phi1148 = phi i32 [ %.SV70.phi1195, %meshBB424 ], [ %.SV70.phi1215, %meshBB408 ], [ %.SV70.phi1138, %meshBB352 ], [ %.SV70.phi1085, %bb96 ], [ %.SV70.phi1027, %bb21 ]		; <i32> [#uses=1]
+	%yM.0.reg2mem.0.SV.phi = phi i32 [ -1, %meshBB424 ], [ -1, %meshBB408 ], [ -1, %meshBB352 ], [ %yM.0.SV.phi, %bb96 ], [ -1, %bb21 ]		; <i32> [#uses=1]
+	%Opq.sa.calc694 = xor i32 0, 243		; <i32> [#uses=1]
+	%232 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%233 = getelementptr %struct.ImageParameters* %232, i64 0, i32 45		; <i32*> [#uses=1]
+	br label %bb97.fragment
+
+bb97.fragment:		; preds = %bb97
+	%Opq.sa.calc928 = xor i32 %Opq.sa.calc694, 128		; <i32> [#uses=1]
+	%234 = load i32* %233, align 4		; <i32> [#uses=1]
+	%235 = icmp eq i32 %234, 0		; <i1> [#uses=1]
+	br i1 %235, label %return, label %bb98
+
+bb98:		; preds = %meshBB444, %meshBB404, %bb97.fragment, %bb81, %bb78.fragment
+	%.SV38.phi1093 = phi i64 [ %.SV38.phi1224, %meshBB444 ], [ %.SV38.phi1017, %meshBB404 ], [ %.SV38.phi1150, %bb97.fragment ], [ %.SV38.phi1137, %bb81 ], [ %.SV38.phi1201, %bb78.fragment ]		; <i64> [#uses=2]
+	%.SV68.phi1092 = phi i32 [ %.SV68.phi1223, %meshBB444 ], [ %.SV68.phi1023, %meshBB404 ], [ %.SV68.phi1149, %bb97.fragment ], [ %.SV68.phi1135, %bb81 ], [ %.SV68.phi1199, %bb78.fragment ]		; <i32> [#uses=2]
+	%.SV70.phi1091 = phi i32 [ %.SV70.phi1222, %meshBB444 ], [ %.SV70.phi1028, %meshBB404 ], [ %.SV70.phi1148, %bb97.fragment ], [ %.SV70.phi1134, %bb81 ], [ %.SV70.phi1198, %bb78.fragment ]		; <i32> [#uses=2]
+	%yM.0.reg2mem.1.SV.phi1068 = phi i32 [ %yN, %meshBB444 ], [ %yM.0.reg2mem.1.SV.phi1077, %meshBB404 ], [ %yM.0.reg2mem.0.SV.phi, %bb97.fragment ], [ %yN, %bb81 ], [ %197, %bb78.fragment ]		; <i32> [#uses=1]
+	%Opq.sa.calc695 = xor i32 0, 23		; <i32> [#uses=2]
+	%236 = and i32 %.SV70.phi1091, %xN		; <i32> [#uses=1]
+	%237 = getelementptr %struct.PixelPos* %pix, i64 0, i32 2		; <i32*> [#uses=2]
+	store i32 %236, i32* %237, align 4
+	%238 = and i32 %yM.0.reg2mem.1.SV.phi1068, %.SV68.phi1092		; <i32> [#uses=1]
+	%239 = getelementptr %struct.PixelPos* %pix, i64 0, i32 3		; <i32*> [#uses=2]
+	store i32 %238, i32* %239, align 4
+	%240 = getelementptr %struct.PixelPos* %pix, i64 0, i32 5		; <i32*> [#uses=1]
+	br label %meshBB376
+
+bb98.fragment:		; preds = %meshBB376
+	%Opq.sa.calc1008 = sub i32 %Opq.link.mask911, 13		; <i32> [#uses=1]
+	%241 = getelementptr %struct.PixelPos* %pix, i64 0, i32 4		; <i32*> [#uses=4]
+	%242 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1		; <i32*> [#uses=1]
+	%243 = load i32* %242, align 4		; <i32> [#uses=1]
+	%244 = load void (i32, i32*, i32*)** @get_mb_block_pos, align 8		; <void (i32, i32*, i32*)*> [#uses=1]
+	tail call void %244(i32 %243, i32* %241, i32* %.SV317.phi) nounwind
+	%245 = load i32* %241, align 4		; <i32> [#uses=1]
+	%246 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%247 = getelementptr %struct.ImageParameters* %246, i64 0, i32 119, i64 %.load39.SV.phi, i64 0		; <i32*> [#uses=1]
+	%248 = load i32* %247, align 4		; <i32> [#uses=1]
+	%249 = mul i32 %248, %245		; <i32> [#uses=2]
+	store i32 %249, i32* %241, align 4
+	br label %bb98.fragment183
+
+bb98.fragment183:		; preds = %bb98.fragment
+	%Opq.sa.calc777 = sub i32 %Opq.sa.calc1008, -158		; <i32> [#uses=1]
+	%Opq.sa.calc776 = sub i32 %Opq.sa.calc777, 46		; <i32> [#uses=0]
+	%250 = load i32* %.SV317.phi, align 4		; <i32> [#uses=1]
+	%251 = load %struct.ImageParameters** @img, align 8		; <%struct.ImageParameters*> [#uses=1]
+	%252 = getelementptr %struct.ImageParameters* %251, i64 0, i32 119, i64 %.load39.SV.phi, i64 1		; <i32*> [#uses=1]
+	%253 = load i32* %252, align 4		; <i32> [#uses=1]
+	%254 = mul i32 %253, %250		; <i32> [#uses=1]
+	%255 = load i32* %.SV313.phi, align 4		; <i32> [#uses=1]
+	%256 = add i32 %255, %249		; <i32> [#uses=1]
+	store i32 %256, i32* %241, align 4
+	%257 = load i32* %.SV315.phi, align 4		; <i32> [#uses=1]
+	%258 = add i32 %257, %254		; <i32> [#uses=1]
+	store i32 %258, i32* %.SV317.phi, align 4
+	ret void
+
+return:		; preds = %meshBB448, %meshBB396, %bb97.fragment
+	%Opq.link.SV697.phi = phi i32 [ %Opq.sa.calc957, %meshBB448 ], [ %Opq.sa.calc758, %meshBB396 ], [ %Opq.sa.calc928, %bb97.fragment ]		; <i32> [#uses=1]
+	%Opq.link.mask699 = and i32 %Opq.link.SV697.phi, 0		; <i32> [#uses=1]
+	%Opq.sa.calc696 = add i32 %Opq.link.mask699, 238		; <i32> [#uses=0]
+	ret void
+
+meshBB:		; preds = %bb33.fragment, %bb14.fragment
+	%.SV38.phi1183 = phi i64 [ %.SV38.phi1115, %bb14.fragment ], [ %.SV38.phi1172, %bb33.fragment ]		; <i64> [#uses=3]
+	%.SV68.phi1181 = phi i32 [ %.SV68.phi1112, %bb14.fragment ], [ %.SV68.phi1169, %bb33.fragment ]		; <i32> [#uses=3]
+	%.SV70.phi1180 = phi i32 [ %.SV70.phi1111, %bb14.fragment ], [ %.SV70.phi1168, %bb33.fragment ]		; <i32> [#uses=3]
+	%.SV104.phi1084 = phi i32 [ undef, %bb14.fragment ], [ %.SV104.phi, %bb33.fragment ]		; <i32> [#uses=1]
+	%.SV111.phi1083 = phi i32* [ undef, %bb14.fragment ], [ %.SV111.phi, %bb33.fragment ]		; <i32*> [#uses=1]
+	%.SV118.phi1082 = phi i32 [ undef, %bb14.fragment ], [ %.SV118.phi, %bb33.fragment ]		; <i32> [#uses=2]
+	%.SV.phi1034 = phi i32 [ %50, %bb14.fragment ], [ undef, %bb33.fragment ]		; <i32> [#uses=1]
+	%meshStackVariable.phi = phi i32 [ %Opq.sa.calc723, %bb14.fragment ], [ %Opq.sa.calc712, %bb33.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV829.phi = phi i32 [ %Opq.sa.calc723, %bb14.fragment ], [ %Opq.sa.calc534, %bb33.fragment ]		; <i32> [#uses=1]
+	%Opq.link.mask831 = and i32 %Opq.link.SV829.phi, 0		; <i32> [#uses=1]
+	%Opq.sa.calc828 = sub i32 %Opq.link.mask831, -117		; <i32> [#uses=2]
+	%meshCmp = icmp eq i32 %meshStackVariable.phi, 3		; <i1> [#uses=1]
+	br i1 %meshCmp, label %bb35, label %bb96
+
+meshBB324:		; preds = %bb32, %bb15
+	%.SV38.phi1175 = phi i64 [ %.SV38.phi1172, %bb32 ], [ %.SV38.phi1115, %bb15 ]		; <i64> [#uses=3]
+	%.SV68.phi1174 = phi i32 [ %.SV68.phi1169, %bb32 ], [ %.SV68.phi1112, %bb15 ]		; <i32> [#uses=3]
+	%.SV70.phi1173 = phi i32 [ %.SV70.phi1168, %bb32 ], [ %.SV70.phi1111, %bb15 ]		; <i32> [#uses=3]
+	%.load94.SV.phi = phi i32 [ undef, %bb32 ], [ %50, %bb15 ]		; <i32> [#uses=1]
+	%.SV212.phi = phi %struct.Macroblock* [ undef, %bb32 ], [ %55, %bb15 ]		; <%struct.Macroblock*> [#uses=1]
+	%.SV214.phi = phi i32 [ undef, %bb32 ], [ %56, %bb15 ]		; <i32> [#uses=1]
+	%meshStackVariable325.phi = phi i32 [ %Opq.sa.calc531, %bb32 ], [ %Opq.sa.calc496, %bb15 ]		; <i32> [#uses=1]
+	%Opq.link.SV751.phi = phi i32 [ %Opq.sa.calc512, %bb32 ], [ %Opq.sa.calc723, %bb15 ]		; <i32> [#uses=1]
+	%.SV.phi1032 = phi i32 [ %.SV118.phi, %bb32 ], [ undef, %bb15 ]		; <i32> [#uses=1]
+	%.SV93.phi = phi i32 [ undef, %bb32 ], [ %50, %bb15 ]		; <i32> [#uses=1]
+	%.SV91.phi = phi i32* [ undef, %bb32 ], [ %48, %bb15 ]		; <i32*> [#uses=1]
+	%.SV87.phi = phi i32 [ undef, %bb32 ], [ %47, %bb15 ]		; <i32> [#uses=1]
+	%Opq.link.mask753 = and i32 %Opq.link.SV751.phi, 4		; <i32> [#uses=1]
+	%Opq.sa.calc750 = add i32 %Opq.link.mask753, 203		; <i32> [#uses=1]
+	%meshCmp327 = icmp eq i32 %meshStackVariable325.phi, 14		; <i1> [#uses=1]
+	br i1 %meshCmp327, label %bb15.fragment, label %bb96
+
+meshBB328:		; preds = %bb50, %bb34
+	%.SV38.phi1227 = phi i64 [ %.SV38.phi1179, %bb50 ], [ %.SV38.phi1172, %bb34 ]		; <i64> [#uses=2]
+	%.SV68.phi1226 = phi i32 [ %.SV68.phi1177, %bb50 ], [ %.SV68.phi1169, %bb34 ]		; <i32> [#uses=2]
+	%.SV70.phi1225 = phi i32 [ %.SV70.phi1176, %bb50 ], [ %.SV70.phi1168, %bb34 ]		; <i32> [#uses=2]
+	%.SV118.phi1081 = phi i32 [ %.SV118.phi1040, %bb50 ], [ %.SV118.phi, %bb34 ]		; <i32> [#uses=1]
+	%.load129.SV.phi = phi i32 [ undef, %bb50 ], [ %.SV118.phi, %bb34 ]		; <i32> [#uses=1]
+	%.load116.SV.phi = phi i32* [ undef, %bb50 ], [ %.SV111.phi, %bb34 ]		; <i32*> [#uses=1]
+	%.SV238.phi = phi i32 [ undef, %bb50 ], [ %100, %bb34 ]		; <i32> [#uses=1]
+	%meshStackVariable329.phi = phi i32 [ %Opq.sa.calc577, %bb50 ], [ %Opq.sa.calc537, %bb34 ]		; <i32> [#uses=1]
+	%Opq.link.SV788.phi = phi i32 [ %Opq.sa.calc577, %bb50 ], [ %Opq.sa.calc712, %bb34 ]		; <i32> [#uses=1]
+	%Opq.link.mask790 = and i32 %Opq.link.SV788.phi, 1		; <i32> [#uses=1]
+	%Opq.sa.calc787 = sub i32 %Opq.link.mask790, -227		; <i32> [#uses=2]
+	%meshCmp331 = icmp eq i32 %meshStackVariable329.phi, 11		; <i1> [#uses=1]
+	br i1 %meshCmp331, label %bb34.fragment, label %bb51
+
+meshBB332:		; preds = %bb44, %bb11
+	%.SV38.phi1204 = phi i64 [ %.SV38.phi1231, %bb44 ], [ %.SV38.phi1164, %bb11 ]		; <i64> [#uses=2]
+	%.SV68.phi1203 = phi i32 [ %.SV68.phi1229, %bb44 ], [ %.SV68.phi1162, %bb11 ]		; <i32> [#uses=2]
+	%.SV70.phi1202 = phi i32 [ %.SV70.phi1228, %bb44 ], [ %.SV70.phi1161, %bb11 ]		; <i32> [#uses=2]
+	%.load127.SV.phi = phi i32 [ %.SV118.phi1125, %bb44 ], [ undef, %bb11 ]		; <i32> [#uses=1]
+	%.load114.SV.phi = phi i32* [ %.SV111.phi1126, %bb44 ], [ undef, %bb11 ]		; <i32*> [#uses=1]
+	%.load46.SV.phi = phi i32 [ %.SV43.phi1230, %bb44 ], [ undef, %bb11 ]		; <i32> [#uses=1]
+	%.SV248.phi = phi i32 [ %119, %bb44 ], [ undef, %bb11 ]		; <i32> [#uses=1]
+	%.load84.SV.phi = phi i32 [ undef, %bb44 ], [ %32, %bb11 ]		; <i32> [#uses=1]
+	%.load81.SV.phi = phi i32* [ undef, %bb44 ], [ %.SV80.phi, %bb11 ]		; <i32*> [#uses=1]
+	%.load50.SV.phi = phi i32 [ undef, %bb44 ], [ %.SV43.phi1163, %bb11 ]		; <i32> [#uses=1]
+	%.SV206.phi = phi i32 [ undef, %bb44 ], [ %43, %bb11 ]		; <i32> [#uses=1]
+	%meshStackVariable333.phi = phi i32 [ %Opq.sa.calc566, %bb44 ], [ %Opq.sa.calc485, %bb11 ]		; <i32> [#uses=1]
+	%Opq.link.SV857.phi = phi i32 [ %Opq.sa.calc987, %bb44 ], [ %Opq.sa.calc485, %bb11 ]		; <i32> [#uses=1]
+	%Opq.link.mask859 = and i32 %Opq.link.SV857.phi, 4		; <i32> [#uses=2]
+	%Opq.sa.calc856 = add i32 %Opq.link.mask859, 204		; <i32> [#uses=2]
+	%meshCmp335 = icmp eq i32 %meshStackVariable333.phi, 4		; <i1> [#uses=1]
+	br i1 %meshCmp335, label %bb11.fragment, label %bb44.fragment
+
+meshBB336:		; preds = %bb85, %bb40
+	%.SV52.phi1234 = phi i32* [ %.SV52.phi1213, %bb85 ], [ undef, %bb40 ]		; <i32*> [#uses=1]
+	%.SV38.phi1231 = phi i64 [ %.SV38.phi1214, %bb85 ], [ %.SV38.phi1179, %bb40 ]		; <i64> [#uses=4]
+	%.SV43.phi1230 = phi i32 [ undef, %bb85 ], [ %.SV43.phi1178, %bb40 ]		; <i32> [#uses=3]
+	%.SV68.phi1229 = phi i32 [ %.SV68.phi1212, %bb85 ], [ %.SV68.phi1177, %bb40 ]		; <i32> [#uses=4]
+	%.SV70.phi1228 = phi i32 [ %.SV70.phi1211, %bb85 ], [ %.SV70.phi1176, %bb40 ]		; <i32> [#uses=4]
+	%.SV99.phi1128 = phi i32* [ undef, %bb85 ], [ %.SV99.phi1037, %bb40 ]		; <i32*> [#uses=1]
+	%.SV104.phi1127 = phi i32 [ undef, %bb85 ], [ %.SV104.phi1036, %bb40 ]		; <i32> [#uses=2]
+	%.SV111.phi1126 = phi i32* [ undef, %bb85 ], [ %.SV111.phi1035, %bb40 ]		; <i32*> [#uses=2]
+	%.SV118.phi1125 = phi i32 [ undef, %bb85 ], [ %.SV118.phi1040, %bb40 ]		; <i32> [#uses=3]
+	%meshStackVariable337.phi = phi i32 [ %Opq.sa.calc665, %bb85 ], [ %Opq.sa.calc553, %bb40 ]		; <i32> [#uses=1]
+	%Opq.link.SV980.phi = phi i32 [ %Opq.sa.calc667, %bb85 ], [ %Opq.sa.calc554, %bb40 ]		; <i32> [#uses=1]
+	%Opq.link.mask982 = and i32 %Opq.link.SV980.phi, 1		; <i32> [#uses=1]
+	%Opq.sa.calc979 = sub i32 %Opq.link.mask982, -153		; <i32> [#uses=2]
+	%meshCmp339 = icmp eq i32 %meshStackVariable337.phi, 4		; <i1> [#uses=1]
+	br i1 %meshCmp339, label %bb41, label %bb86
+
+meshBB340:		; preds = %bb29, %bb26
+	%.SV38.phi1167 = phi i64 [ %.SV38.phi1121, %bb29 ], [ %.SV38.phi1172, %bb26 ]		; <i64> [#uses=3]
+	%.SV68.phi1166 = phi i32 [ %.SV68.phi1120, %bb29 ], [ %.SV68.phi1169, %bb26 ]		; <i32> [#uses=3]
+	%.SV70.phi1165 = phi i32 [ %.SV70.phi1119, %bb29 ], [ %.SV70.phi1168, %bb26 ]		; <i32> [#uses=3]
+	%.SV104.phi1080 = phi i32 [ undef, %bb29 ], [ %.SV104.phi, %bb26 ]		; <i32> [#uses=1]
+	%.SV111.phi1079 = phi i32* [ undef, %bb29 ], [ %.SV111.phi, %bb26 ]		; <i32*> [#uses=1]
+	%.SV118.phi1078 = phi i32 [ %.SV118.phi1158, %bb29 ], [ %.SV118.phi, %bb26 ]		; <i32> [#uses=1]
+	%.load123.SV.phi = phi i32 [ undef, %bb29 ], [ %.SV118.phi, %bb26 ]		; <i32> [#uses=2]
+	%.SV228.phi = phi %struct.Macroblock* [ undef, %bb29 ], [ %81, %bb26 ]		; <%struct.Macroblock*> [#uses=1]
+	%.SV230.phi = phi i32 [ undef, %bb29 ], [ %82, %bb26 ]		; <i32> [#uses=1]
+	%meshStackVariable341.phi = phi i32 [ %Opq.sa.calc525, %bb29 ], [ %Opq.sa.calc518, %bb26 ]		; <i32> [#uses=1]
+	%Opq.link.SV755.phi = phi i32 [ %Opq.sa.calc525, %bb29 ], [ %Opq.sa.calc519, %bb26 ]		; <i32> [#uses=1]
+	%.SV.phi1042 = phi i32 [ %.SV118.phi1158, %bb29 ], [ undef, %bb26 ]		; <i32> [#uses=1]
+	%yM.0.SV.phi1041 = phi i32 [ %89, %bb29 ], [ undef, %bb26 ]		; <i32> [#uses=1]
+	%Opq.link.mask757 = and i32 %Opq.link.SV755.phi, 12		; <i32> [#uses=1]
+	%Opq.sa.calc754 = add i32 %Opq.link.mask757, 225		; <i32> [#uses=2]
+	%meshCmp343 = icmp eq i32 %meshStackVariable341.phi, 9		; <i1> [#uses=1]
+	br i1 %meshCmp343, label %bb26.fragment, label %bb96
+
+meshBB344:		; preds = %bb68, %bb23.fragment182
+	%.SV38.phi1172 = phi i64 [ %.SV38.phi1115, %bb23.fragment182 ], [ %.SV38.phi1098, %bb68 ]		; <i64> [#uses=8]
+	%.SV52.phi1170 = phi i32* [ undef, %bb23.fragment182 ], [ %.SV52.phi1097, %bb68 ]		; <i32*> [#uses=2]
+	%.SV68.phi1169 = phi i32 [ %.SV68.phi1112, %bb23.fragment182 ], [ %.SV68.phi1096, %bb68 ]		; <i32> [#uses=8]
+	%.SV70.phi1168 = phi i32 [ %.SV70.phi1111, %bb23.fragment182 ], [ %.SV70.phi1095, %bb68 ]		; <i32> [#uses=8]
+	%.load144.SV.phi = phi i1 [ undef, %bb23.fragment182 ], [ %145, %bb68 ]		; <i1> [#uses=1]
+	%.SV274.phi = phi i32* [ undef, %bb23.fragment182 ], [ %167, %bb68 ]		; <i32*> [#uses=2]
+	%.SV118.phi = phi i32 [ %76, %bb23.fragment182 ], [ undef, %bb68 ]		; <i32> [#uses=7]
+	%.SV135.phi = phi i1 [ %78, %bb23.fragment182 ], [ undef, %bb68 ]		; <i1> [#uses=2]
+	%meshStackVariable345.phi = phi i32 [ %Opq.sa.calc743, %bb23.fragment182 ], [ %Opq.sa.calc624, %bb68 ]		; <i32> [#uses=1]
+	%Opq.link.SV717.phi = phi i32 [ %Opq.sa.calc744, %bb23.fragment182 ], [ %Opq.sa.calc624, %bb68 ]		; <i32> [#uses=1]
+	%Opq.link.SV720.phi = phi i32 [ %Opq.sa.calc743, %bb23.fragment182 ], [ %Opq.sa.calc624, %bb68 ]		; <i32> [#uses=1]
+	%.SV96.phi = phi i1 [ %71, %bb23.fragment182 ], [ undef, %bb68 ]		; <i1> [#uses=1]
+	%.SV99.phi = phi i32* [ %72, %bb23.fragment182 ], [ undef, %bb68 ]		; <i32*> [#uses=2]
+	%.SV104.phi = phi i32 [ %73, %bb23.fragment182 ], [ undef, %bb68 ]		; <i32> [#uses=3]
+	%.SV111.phi = phi i32* [ %74, %bb23.fragment182 ], [ undef, %bb68 ]		; <i32*> [#uses=3]
+	%Opq.link.mask722 = and i32 %Opq.link.SV720.phi, 9		; <i32> [#uses=3]
+	%Opq.link.mask719 = and i32 %Opq.link.SV717.phi, 0		; <i32> [#uses=1]
+	%Opq.sa.calc715 = sub i32 %Opq.link.mask719, %Opq.link.mask722		; <i32> [#uses=1]
+	%Opq.sa.calc716 = sub i32 %Opq.sa.calc715, -101		; <i32> [#uses=2]
+	%meshCmp347 = icmp eq i32 %meshStackVariable345.phi, 9		; <i1> [#uses=1]
+	br i1 %meshCmp347, label %bb68.fragment, label %bb24
+
+meshBB348:		; preds = %bb37, %bb6
+	%.SV38.phi1103 = phi i64 [ %.SV38.phi1014, %bb6 ], [ %.SV38.phi1019, %bb37 ]		; <i64> [#uses=2]
+	%.SV43.phi1102 = phi i32 [ %.SV43.phi, %bb6 ], [ %.SV43.phi1018, %bb37 ]		; <i32> [#uses=1]
+	%.SV52.phi1101 = phi i32* [ %.SV52.phi, %bb6 ], [ undef, %bb37 ]		; <i32*> [#uses=1]
+	%.SV68.phi1100 = phi i32 [ %.SV68.phi1020, %bb6 ], [ %.SV68.phi1025, %bb37 ]		; <i32> [#uses=2]
+	%.SV70.phi1099 = phi i32 [ %.SV70.phi1026, %bb6 ], [ %.SV70.phi1233, %bb37 ]		; <i32> [#uses=2]
+	%.load131.SV.phi = phi i32 [ undef, %bb6 ], [ %.SV118.phi1155, %bb37 ]		; <i32> [#uses=1]
+	%.load115.SV.phi = phi i32* [ undef, %bb6 ], [ %.SV111.phi1156, %bb37 ]		; <i32*> [#uses=1]
+	%.load48.SV.phi = phi i32 [ undef, %bb6 ], [ %.SV43.phi1018, %bb37 ]		; <i32> [#uses=1]
+	%.SV242.phi = phi i32 [ undef, %bb6 ], [ %105, %bb37 ]		; <i32> [#uses=1]
+	%meshStackVariable349.phi = phi i32 [ %Opq.sa.calc473, %bb6 ], [ %Opq.sa.calc547, %bb37 ]		; <i32> [#uses=1]
+	%Opq.link.SV806.phi = phi i32 [ %Opq.sa.calc873, %bb6 ], [ %Opq.sa.calc958, %bb37 ]		; <i32> [#uses=1]
+	%Opq.link.mask808 = and i32 %Opq.link.SV806.phi, 12		; <i32> [#uses=1]
+	%Opq.sa.calc805 = sub i32 %Opq.link.mask808, -147		; <i32> [#uses=3]
+	%meshCmp351 = icmp eq i32 %meshStackVariable349.phi, 13		; <i1> [#uses=1]
+	br i1 %meshCmp351, label %bb37.fragment, label %bb8
+
+meshBB352:		; preds = %bb79, %bb71
+	%.SV38.phi1140 = phi i64 [ %.SV38.phi1110, %bb71 ], [ %.SV38.phi1098, %bb79 ]		; <i64> [#uses=2]
+	%.SV68.phi1139 = phi i32 [ %.SV68.phi1108, %bb71 ], [ %.SV68.phi1096, %bb79 ]		; <i32> [#uses=2]
+	%.SV70.phi1138 = phi i32 [ %.SV70.phi1107, %bb71 ], [ %.SV70.phi1095, %bb79 ]		; <i32> [#uses=2]
+	%.load166.SV.phi = phi i32 [ %.SV164.phi1104, %bb71 ], [ undef, %bb79 ]		; <i32> [#uses=1]
+	%.load163.SV.phi = phi i32* [ %.SV162.phi1105, %bb71 ], [ undef, %bb79 ]		; <i32*> [#uses=1]
+	%.SV282.phi = phi i32 [ %182, %bb71 ], [ undef, %bb79 ]		; <i32> [#uses=1]
+	%meshStackVariable353.phi = phi i32 [ %Opq.sa.calc633, %bb71 ], [ %Opq.sa.calc650, %bb79 ]		; <i32> [#uses=1]
+	%Opq.link.SV877.phi = phi i32 [ %Opq.sa.calc820, %bb71 ], [ %Opq.sa.calc650, %bb79 ]		; <i32> [#uses=1]
+	%Opq.link.mask879 = and i32 %Opq.link.SV877.phi, 1		; <i32> [#uses=1]
+	%Opq.sa.calc876 = add i32 %Opq.link.mask879, 18		; <i32> [#uses=1]
+	%meshCmp355 = icmp eq i32 %meshStackVariable353.phi, 11		; <i1> [#uses=1]
+	br i1 %meshCmp355, label %bb97, label %bb71.fragment
+
+meshBB356:		; preds = %bb70.fragment, %bb26.fragment
+	%.SV104.phi1160 = phi i32 [ undef, %bb70.fragment ], [ %.SV104.phi1080, %bb26.fragment ]		; <i32> [#uses=1]
+	%.SV111.phi1159 = phi i32* [ undef, %bb70.fragment ], [ %.SV111.phi1079, %bb26.fragment ]		; <i32*> [#uses=1]
+	%.SV118.phi1158 = phi i32 [ undef, %bb70.fragment ], [ %.SV118.phi1078, %bb26.fragment ]		; <i32> [#uses=3]
+	%.SV38.phi1121 = phi i64 [ %.SV38.phi1014, %bb70.fragment ], [ %.SV38.phi1167, %bb26.fragment ]		; <i64> [#uses=3]
+	%.SV68.phi1120 = phi i32 [ %.SV68.phi1020, %bb70.fragment ], [ %.SV68.phi1166, %bb26.fragment ]		; <i32> [#uses=3]
+	%.SV70.phi1119 = phi i32 [ %.SV70.phi1026, %bb70.fragment ], [ %.SV70.phi1165, %bb26.fragment ]		; <i32> [#uses=3]
+	%.SV.phi1046 = phi i32 [ %.load165.SV.phi, %bb70.fragment ], [ %.load123.SV.phi, %bb26.fragment ]		; <i32> [#uses=1]
+	%meshStackVariable357.phi = phi i32 [ %Opq.sa.calc738, %bb70.fragment ], [ %Opq.sa.calc917, %bb26.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV984.phi = phi i32 [ %Opq.sa.calc738, %bb70.fragment ], [ %Opq.sa.calc918, %bb26.fragment ]		; <i32> [#uses=1]
+	%Opq.link.mask986 = and i32 %Opq.link.SV984.phi, 9		; <i32> [#uses=1]
+	%Opq.sa.calc983 = xor i32 %Opq.link.mask986, 251		; <i32> [#uses=1]
+	%meshCmp359 = icmp eq i32 %meshStackVariable357.phi, 9		; <i1> [#uses=1]
+	br i1 %meshCmp359, label %bb28, label %bb96
+
+meshBB360:		; preds = %bb21, %bb13
+	%.SV38.phi1115 = phi i64 [ %4, %bb21 ], [ %.SV38.phi1014, %bb13 ]		; <i64> [#uses=5]
+	%.SV52.phi1113 = phi i32* [ %.SV52.phi1022, %bb21 ], [ %.SV52.phi, %bb13 ]		; <i32*> [#uses=3]
+	%.SV68.phi1112 = phi i32 [ %.SV68.phi1021, %bb21 ], [ %.SV68.phi1020, %bb13 ]		; <i32> [#uses=5]
+	%.SV70.phi1111 = phi i32 [ %.SV70.phi1027, %bb21 ], [ %.SV70.phi1026, %bb13 ]		; <i32> [#uses=5]
+	%.load74.SV.phi = phi i1 [ undef, %bb21 ], [ %21, %bb13 ]		; <i1> [#uses=1]
+	%.SV208.phi = phi i32* [ undef, %bb21 ], [ %46, %bb13 ]		; <i32*> [#uses=2]
+	%meshStackVariable361.phi = phi i32 [ %Opq.sa.calc505, %bb21 ], [ %Opq.sa.calc489, %bb13 ]		; <i32> [#uses=1]
+	%Opq.link.SV867.phi = phi i32 [ %Opq.sa.calc505, %bb21 ], [ %Opq.sa.calc873, %bb13 ]		; <i32> [#uses=1]
+	%Opq.link.mask869 = and i32 %Opq.link.SV867.phi, 1		; <i32> [#uses=1]
+	%Opq.sa.calc866 = add i32 %Opq.link.mask869, 148		; <i32> [#uses=4]
+	%meshCmp363 = icmp eq i32 %meshStackVariable361.phi, 16		; <i1> [#uses=1]
+	br i1 %meshCmp363, label %bb13.fragment, label %bb23
+
+meshBB364:		; preds = %bb65.fragment, %bb56
+	%.SV38.phi1098 = phi i64 [ %.SV38.phi1017, %bb56 ], [ %.SV38.phi1147, %bb65.fragment ]		; <i64> [#uses=11]
+	%.SV52.phi1097 = phi i32* [ %.SV52.phi1024, %bb56 ], [ undef, %bb65.fragment ]		; <i32*> [#uses=8]
+	%.SV68.phi1096 = phi i32 [ %.SV68.phi1023, %bb56 ], [ %.SV68.phi1146, %bb65.fragment ]		; <i32> [#uses=11]
+	%.SV70.phi1095 = phi i32 [ %.SV70.phi1028, %bb56 ], [ %.SV70.phi1145, %bb65.fragment ]		; <i32> [#uses=11]
+	%or.cond.not.SV.phi1094 = phi i1 [ %or.cond.not.SV.phi1029, %bb56 ], [ undef, %bb65.fragment ]		; <i1> [#uses=1]
+	%.SV.phi1062 = phi i32 [ undef, %bb56 ], [ %.SV268.phi, %bb65.fragment ]		; <i32> [#uses=1]
+	%.not4.SV.phi = phi i1 [ %.not4, %bb56 ], [ undef, %bb65.fragment ]		; <i1> [#uses=1]
+	%.SV256.phi = phi i1 [ %139, %bb56 ], [ undef, %bb65.fragment ]		; <i1> [#uses=1]
+	%meshStackVariable365.phi = phi i32 [ %Opq.sa.calc592, %bb56 ], [ %Opq.sa.calc832, %bb65.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV735.phi = phi i32 [ %Opq.sa.calc592, %bb56 ], [ %Opq.sa.calc832, %bb65.fragment ]		; <i32> [#uses=1]
+	%Opq.link.mask737 = and i32 %Opq.link.SV735.phi, 0		; <i32> [#uses=2]
+	%Opq.sa.calc734 = sub i32 %Opq.link.mask737, -242		; <i32> [#uses=0]
+	%meshCmp367 = icmp eq i32 %meshStackVariable365.phi, 1		; <i1> [#uses=1]
+	br i1 %meshCmp367, label %bb96, label %bb56.fragment
+
+meshBB368:		; preds = %bb90.fragment, %bb8
+	%.SV38.phi1164 = phi i64 [ %.SV38.phi1103, %bb8 ], [ %.SV38.phi1191, %bb90.fragment ]		; <i64> [#uses=5]
+	%.SV43.phi1163 = phi i32 [ %.SV43.phi1102, %bb8 ], [ undef, %bb90.fragment ]		; <i32> [#uses=1]
+	%.SV68.phi1162 = phi i32 [ %.SV68.phi1100, %bb8 ], [ %.SV68.phi1189, %bb90.fragment ]		; <i32> [#uses=5]
+	%.SV70.phi1161 = phi i32 [ %.SV70.phi1099, %bb8 ], [ %.SV70.phi1188, %bb90.fragment ]		; <i32> [#uses=5]
+	%.SV178.phi = phi i32 [ undef, %bb8 ], [ %214, %bb90.fragment ]		; <i32> [#uses=2]
+	%.SV176.phi = phi i32* [ undef, %bb8 ], [ %212, %bb90.fragment ]		; <i32*> [#uses=1]
+	%.SV170.phi = phi i32* [ undef, %bb8 ], [ %210, %bb90.fragment ]		; <i32*> [#uses=1]
+	%.SV172.phi = phi i32 [ undef, %bb8 ], [ %211, %bb90.fragment ]		; <i32> [#uses=1]
+	%.SV76.phi = phi i32* [ %28, %bb8 ], [ undef, %bb90.fragment ]		; <i32*> [#uses=1]
+	%.SV78.phi = phi i32 [ %29, %bb8 ], [ undef, %bb90.fragment ]		; <i32> [#uses=1]
+	%.SV80.phi = phi i32* [ %30, %bb8 ], [ undef, %bb90.fragment ]		; <i32*> [#uses=1]
+	%.load66.SV.phi = phi i32* [ %.SV52.phi1101, %bb8 ], [ undef, %bb90.fragment ]		; <i32*> [#uses=1]
+	%.load35.SV.phi = phi i64 [ %3, %bb8 ], [ undef, %bb90.fragment ]		; <i64> [#uses=1]
+	%.load16.SV.phi = phi %struct.Macroblock* [ %2, %bb8 ], [ undef, %bb90.fragment ]		; <%struct.Macroblock*> [#uses=1]
+	%.SV198.phi = phi i32 [ %29, %bb8 ], [ undef, %bb90.fragment ]		; <i32> [#uses=1]
+	%.SV200.phi = phi i32* [ %30, %bb8 ], [ undef, %bb90.fragment ]		; <i32*> [#uses=1]
+	%meshStackVariable369.phi = phi i32 [ %Opq.sa.calc479, %bb8 ], [ %Opq.sa.calc772, %bb90.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV769.phi = phi i32 [ %Opq.sa.calc805, %bb8 ], [ %Opq.sa.calc772, %bb90.fragment ]		; <i32> [#uses=1]
+	%Opq.link.mask771 = and i32 %Opq.link.SV769.phi, 2		; <i32> [#uses=1]
+	%Opq.sa.calc768 = xor i32 %Opq.link.mask771, 135		; <i32> [#uses=3]
+	%meshCmp371 = icmp eq i32 %meshStackVariable369.phi, 2		; <i1> [#uses=1]
+	br i1 %meshCmp371, label %bb91, label %bb8.fragment
+
+meshBB372:		; preds = %bb84.fragment, %bb35
+	%.SV38.phi1214 = phi i64 [ %.SV38.phi1191, %bb84.fragment ], [ %.SV38.phi1183, %bb35 ]		; <i64> [#uses=3]
+	%.SV52.phi1213 = phi i32* [ %.SV52.phi1190, %bb84.fragment ], [ undef, %bb35 ]		; <i32*> [#uses=2]
+	%.SV68.phi1212 = phi i32 [ %.SV68.phi1189, %bb84.fragment ], [ %.SV68.phi1181, %bb35 ]		; <i32> [#uses=3]
+	%.SV70.phi1211 = phi i32 [ %.SV70.phi1188, %bb84.fragment ], [ %.SV70.phi1180, %bb35 ]		; <i32> [#uses=3]
+	%.SV118.phi1154 = phi i32 [ undef, %bb84.fragment ], [ %.SV118.phi1082, %bb35 ]		; <i32> [#uses=1]
+	%.SV167.phi = phi i1 [ %203, %bb84.fragment ], [ undef, %bb35 ]		; <i1> [#uses=1]
+	%meshStackVariable373.phi = phi i32 [ %Opq.sa.calc802, %bb84.fragment ], [ %Opq.sa.calc540, %bb35 ]		; <i32> [#uses=1]
+	%Opq.link.SV813.phi = phi i32 [ %Opq.sa.calc802, %bb84.fragment ], [ %Opq.sa.calc541, %bb35 ]		; <i32> [#uses=1]
+	%Opq.link.mask815 = and i32 %Opq.link.SV813.phi, 0		; <i32> [#uses=1]
+	%Opq.sa.calc812 = sub i32 %Opq.link.mask815, -121		; <i32> [#uses=3]
+	%meshCmp375 = icmp eq i32 %meshStackVariable373.phi, 6		; <i1> [#uses=1]
+	br i1 %meshCmp375, label %bb36, label %bb85
+
+meshBB376:		; preds = %bb98, %bb44.fragment
+	%.SV38.phi1153 = phi i64 [ %.SV38.phi1093, %bb98 ], [ %.SV38.phi1204, %bb44.fragment ]		; <i64> [#uses=1]
+	%.SV68.phi1152 = phi i32 [ %.SV68.phi1092, %bb98 ], [ %.SV68.phi1203, %bb44.fragment ]		; <i32> [#uses=1]
+	%.SV70.phi1151 = phi i32 [ %.SV70.phi1091, %bb98 ], [ %.SV70.phi1202, %bb44.fragment ]		; <i32> [#uses=1]
+	%.load39.SV.phi = phi i64 [ %.SV38.phi1093, %bb98 ], [ undef, %bb44.fragment ]		; <i64> [#uses=2]
+	%.SV313.phi = phi i32* [ %237, %bb98 ], [ undef, %bb44.fragment ]		; <i32*> [#uses=1]
+	%.SV315.phi = phi i32* [ %239, %bb98 ], [ undef, %bb44.fragment ]		; <i32*> [#uses=1]
+	%.SV317.phi = phi i32* [ %240, %bb98 ], [ undef, %bb44.fragment ]		; <i32*> [#uses=3]
+	%.SV.phi1050 = phi i32 [ undef, %bb98 ], [ %.load127.SV.phi, %bb44.fragment ]		; <i32> [#uses=1]
+	%yM.0.SV.phi1049 = phi i32 [ undef, %bb98 ], [ %121, %bb44.fragment ]		; <i32> [#uses=1]
+	%meshStackVariable377.phi = phi i32 [ %Opq.sa.calc695, %bb98 ], [ %Opq.sa.calc894, %bb44.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV909.phi = phi i32 [ %Opq.sa.calc695, %bb98 ], [ %Opq.sa.calc856, %bb44.fragment ]		; <i32> [#uses=1]
+	%Opq.link.mask911 = and i32 %Opq.link.SV909.phi, 16		; <i32> [#uses=2]
+	%Opq.sa.calc908 = add i32 %Opq.link.mask911, -11		; <i32> [#uses=0]
+	%meshCmp379 = icmp eq i32 %meshStackVariable377.phi, 8		; <i1> [#uses=1]
+	br i1 %meshCmp379, label %bb96, label %bb98.fragment
+
+meshBB380:		; preds = %bb92.fragment, %bb49.fragment
+	%.SV38.phi1207 = phi i64 [ %.SV38.phi1164, %bb92.fragment ], [ %.SV38.phi1179, %bb49.fragment ]		; <i64> [#uses=2]
+	%.SV68.phi1206 = phi i32 [ %.SV68.phi1162, %bb92.fragment ], [ %.SV68.phi1177, %bb49.fragment ]		; <i32> [#uses=2]
+	%.SV70.phi1205 = phi i32 [ %.SV70.phi1161, %bb92.fragment ], [ %.SV70.phi1176, %bb49.fragment ]		; <i32> [#uses=2]
+	%.SV104.phi1124 = phi i32 [ undef, %bb92.fragment ], [ %.SV104.phi1036, %bb49.fragment ]		; <i32> [#uses=1]
+	%.SV111.phi1123 = phi i32* [ undef, %bb92.fragment ], [ %.SV111.phi1035, %bb49.fragment ]		; <i32*> [#uses=1]
+	%.SV118.phi1122 = phi i32 [ undef, %bb92.fragment ], [ %.SV118.phi1040, %bb49.fragment ]		; <i32> [#uses=1]
+	%meshStackVariable381.phi = phi i32 [ %Opq.sa.calc1005, %bb92.fragment ], [ %Opq.sa.calc860, %bb49.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV947.phi = phi i32 [ %Opq.sa.calc1005, %bb92.fragment ], [ %Opq.sa.calc860, %bb49.fragment ]		; <i32> [#uses=1]
+	%.SV.phi1052 = phi i32 [ %.SV178.phi, %bb92.fragment ], [ undef, %bb49.fragment ]		; <i32> [#uses=1]
+	%yM.0.SV.phi1051 = phi i32 [ %226, %bb92.fragment ], [ undef, %bb49.fragment ]		; <i32> [#uses=1]
+	%Opq.link.mask949 = and i32 %Opq.link.SV947.phi, 1		; <i32> [#uses=1]
+	%Opq.sa.calc946 = sub i32 %Opq.link.mask949, -4		; <i32> [#uses=1]
+	%meshCmp383 = icmp eq i32 %meshStackVariable381.phi, 1		; <i1> [#uses=1]
+	br i1 %meshCmp383, label %bb54, label %bb96
+
+meshBB384:		; preds = %bb95, %bb52
+	%.SV38.phi1221 = phi i64 [ %.SV38.phi1179, %bb52 ], [ %.SV38.phi1218, %bb95 ]		; <i64> [#uses=2]
+	%.SV68.phi1220 = phi i32 [ %.SV68.phi1177, %bb52 ], [ %.SV68.phi1216, %bb95 ]		; <i32> [#uses=2]
+	%.SV70.phi1219 = phi i32 [ %.SV70.phi1176, %bb52 ], [ %.SV70.phi1215, %bb95 ]		; <i32> [#uses=2]
+	%.load53.SV.phi = phi i32* [ undef, %bb52 ], [ %.SV52.phi1217, %bb95 ]		; <i32*> [#uses=1]
+	%.load20.SV.phi = phi i64 [ undef, %bb52 ], [ %3, %bb95 ]		; <i64> [#uses=1]
+	%.load.SV.phi = phi %struct.Macroblock* [ undef, %bb52 ], [ %2, %bb95 ]		; <%struct.Macroblock*> [#uses=1]
+	%.SV306.phi = phi i32 [ undef, %bb52 ], [ %227, %bb95 ]		; <i32> [#uses=1]
+	%.SV308.phi = phi i32* [ undef, %bb52 ], [ %228, %bb95 ]		; <i32*> [#uses=1]
+	%.load126.SV.phi = phi i32 [ %.SV118.phi1040, %bb52 ], [ undef, %bb95 ]		; <i32> [#uses=1]
+	%.load44.SV.phi = phi i32 [ %.SV43.phi1178, %bb52 ], [ undef, %bb95 ]		; <i32> [#uses=1]
+	%meshStackVariable385.phi = phi i32 [ %Opq.sa.calc583, %bb52 ], [ %Opq.sa.calc689, %bb95 ]		; <i32> [#uses=1]
+	%Opq.link.SV902.phi = phi i32 [ %Opq.sa.calc860, %bb52 ], [ %Opq.sa.calc689, %bb95 ]		; <i32> [#uses=1]
+	%Opq.link.SV905.phi = phi i32 [ %Opq.sa.calc584, %bb52 ], [ %Opq.sa.calc689, %bb95 ]		; <i32> [#uses=1]
+	%Opq.link.mask907 = and i32 %Opq.link.SV905.phi, 0		; <i32> [#uses=0]
+	%Opq.link.mask904 = and i32 %Opq.link.SV902.phi, 1		; <i32> [#uses=1]
+	%Opq.sa.calc901 = xor i32 %Opq.link.mask904, 227		; <i32> [#uses=3]
+	%meshCmp387 = icmp eq i32 %meshStackVariable385.phi, 5		; <i1> [#uses=1]
+	br i1 %meshCmp387, label %bb95.fragment, label %bb52.fragment
+
+meshBB388:		; preds = %bb52.fragment, %bb7
+	%.SV38.phi1118 = phi i64 [ %.SV38.phi1014, %bb7 ], [ %.SV38.phi1221, %bb52.fragment ]		; <i64> [#uses=2]
+	%.SV68.phi1117 = phi i32 [ %.SV68.phi1020, %bb7 ], [ %.SV68.phi1220, %bb52.fragment ]		; <i32> [#uses=2]
+	%.SV70.phi1116 = phi i32 [ %.SV70.phi1026, %bb7 ], [ %.SV70.phi1219, %bb52.fragment ]		; <i32> [#uses=2]
+	%.SV.phi1054 = phi i32 [ undef, %bb7 ], [ %.load126.SV.phi, %bb52.fragment ]		; <i32> [#uses=1]
+	%yM.0.SV.phi1053 = phi i32 [ undef, %bb7 ], [ %137, %bb52.fragment ]		; <i32> [#uses=1]
+	%.load67.SV.phi = phi i32* [ %.SV52.phi, %bb7 ], [ undef, %bb52.fragment ]		; <i32*> [#uses=1]
+	%.load36.SV.phi = phi i64 [ %3, %bb7 ], [ undef, %bb52.fragment ]		; <i64> [#uses=1]
+	%.load17.SV.phi = phi %struct.Macroblock* [ %2, %bb7 ], [ undef, %bb52.fragment ]		; <%struct.Macroblock*> [#uses=1]
+	%.SV194.phi = phi i32 [ %24, %bb7 ], [ undef, %bb52.fragment ]		; <i32> [#uses=1]
+	%.SV196.phi = phi i32* [ %25, %bb7 ], [ undef, %bb52.fragment ]		; <i32*> [#uses=1]
+	%meshStackVariable389.phi = phi i32 [ %Opq.sa.calc476, %bb7 ], [ %Opq.sa.calc844, %bb52.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV887.phi = phi i32 [ %Opq.sa.calc873, %bb7 ], [ %Opq.sa.calc901, %bb52.fragment ]		; <i32> [#uses=1]
+	%Opq.link.mask889 = and i32 %Opq.link.SV887.phi, 64		; <i32> [#uses=1]
+	%Opq.sa.calc886 = sub i32 %Opq.link.mask889, -170		; <i32> [#uses=2]
+	%meshCmp391 = icmp eq i32 %meshStackVariable389.phi, 12		; <i1> [#uses=1]
+	br i1 %meshCmp391, label %bb96, label %bb7.fragment
+
+meshBB392:		; preds = %bb4, %entry
+	%meshStackVariable393.phi = phi i32 [ %Opq.sa.calc466, %bb4 ], [ %Opq.sa.calc, %entry ]		; <i32> [#uses=1]
+	%Opq.link.SV922.phi = phi i32 [ %Opq.sa.calc462, %bb4 ], [ %Opq.sa.calc, %entry ]		; <i32> [#uses=1]
+	%or.cond.not.SV.phi = phi i1 [ %or.cond.not, %bb4 ], [ undef, %entry ]		; <i1> [#uses=1]
+	%.SV70.phi1027 = phi i32 [ %12, %bb4 ], [ undef, %entry ]		; <i32> [#uses=2]
+	%.SV52.phi1022 = phi i32* [ %9, %bb4 ], [ undef, %entry ]		; <i32*> [#uses=1]
+	%.SV68.phi1021 = phi i32 [ %10, %bb4 ], [ undef, %entry ]		; <i32> [#uses=2]
+	%.SV43.phi1015 = phi i32 [ %8, %bb4 ], [ undef, %entry ]		; <i32> [#uses=3]
+	%Opq.link.mask924 = and i32 %Opq.link.SV922.phi, 2		; <i32> [#uses=1]
+	%Opq.sa.calc921 = add i32 %Opq.link.mask924, 57		; <i32> [#uses=3]
+	%meshCmp395 = icmp eq i32 %meshStackVariable393.phi, 2		; <i1> [#uses=1]
+	br i1 %meshCmp395, label %entry.fragment, label %bb21
+
+meshBB396:		; preds = %bb69.fragment, %bb.fragment
+	%.SV.phi1065 = phi i32 [ undef, %bb.fragment ], [ %171, %bb69.fragment ]		; <i32> [#uses=1]
+	%meshStackVariable397.phi = phi i32 [ %Opq.sa.calc976, %bb.fragment ], [ %Opq.sa.calc995, %bb69.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV759.phi = phi i32 [ %Opq.sa.calc976, %bb.fragment ], [ %Opq.sa.calc995, %bb69.fragment ]		; <i32> [#uses=1]
+	%.SV70.phi = phi i32 [ %12, %bb.fragment ], [ %.SV70.phi1168, %bb69.fragment ]		; <i32> [#uses=1]
+	%.SV68.phi = phi i32 [ %10, %bb.fragment ], [ %.SV68.phi1169, %bb69.fragment ]		; <i32> [#uses=1]
+	%.SV38.phi = phi i64 [ %4, %bb.fragment ], [ %.SV38.phi1172, %bb69.fragment ]		; <i64> [#uses=1]
+	%Opq.link.mask761 = and i32 %Opq.link.SV759.phi, 6		; <i32> [#uses=1]
+	%Opq.sa.calc758 = add i32 %Opq.link.mask761, 53		; <i32> [#uses=1]
+	%meshCmp399 = icmp eq i32 %meshStackVariable397.phi, 6		; <i1> [#uses=1]
+	br i1 %meshCmp399, label %bb96, label %return
+
+meshBB400:		; preds = %bb84, %bb69.fragment
+	%.SV38.phi1191 = phi i64 [ %.SV38.phi1098, %bb84 ], [ %.SV38.phi1172, %bb69.fragment ]		; <i64> [#uses=5]
+	%.SV52.phi1190 = phi i32* [ %.SV52.phi1097, %bb84 ], [ undef, %bb69.fragment ]		; <i32*> [#uses=3]
+	%.SV68.phi1189 = phi i32 [ %.SV68.phi1096, %bb84 ], [ %.SV68.phi1169, %bb69.fragment ]		; <i32> [#uses=5]
+	%.SV70.phi1188 = phi i32 [ %.SV70.phi1095, %bb84 ], [ %.SV70.phi1168, %bb69.fragment ]		; <i32> [#uses=5]
+	%.SV290.phi = phi i32 [ %200, %bb84 ], [ undef, %bb69.fragment ]		; <i32> [#uses=1]
+	%.SV164.phi = phi i32 [ undef, %bb84 ], [ %171, %bb69.fragment ]		; <i32> [#uses=2]
+	%meshStackVariable401.phi = phi i32 [ %Opq.sa.calc661, %bb84 ], [ %Opq.sa.calc996, %bb69.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV825.phi = phi i32 [ %Opq.sa.calc658, %bb84 ], [ %Opq.sa.calc996, %bb69.fragment ]		; <i32> [#uses=1]
+	%.SV162.phi = phi i32* [ undef, %bb84 ], [ %169, %bb69.fragment ]		; <i32*> [#uses=1]
+	%.SV156.phi = phi i32* [ undef, %bb84 ], [ %.SV274.phi, %bb69.fragment ]		; <i32*> [#uses=1]
+	%.SV158.phi = phi i32 [ undef, %bb84 ], [ %168, %bb69.fragment ]		; <i32> [#uses=1]
+	%Opq.link.mask827 = and i32 %Opq.link.SV825.phi, 4		; <i32> [#uses=1]
+	%Opq.sa.calc824 = xor i32 %Opq.link.mask827, 228		; <i32> [#uses=2]
+	%meshCmp403 = icmp eq i32 %meshStackVariable401.phi, 15		; <i1> [#uses=1]
+	br i1 %meshCmp403, label %bb70, label %bb84.fragment
+
+meshBB404:		; preds = %bb96, %bb3
+	%yM.0.reg2mem.1.SV.phi1077 = phi i32 [ %yM.0.SV.phi, %bb96 ], [ undef, %bb3 ]		; <i32> [#uses=1]
+	%meshStackVariable405.phi = phi i32 [ %Opq.sa.calc692, %bb96 ], [ %Opq.sa.calc461, %bb3 ]		; <i32> [#uses=1]
+	%Opq.link.SV940.phi = phi i32 [ %Opq.sa.calc693, %bb96 ], [ %Opq.sa.calc461, %bb3 ]		; <i32> [#uses=1]
+	%or.cond.not.SV.phi1029 = phi i1 [ undef, %bb96 ], [ %or.cond.not, %bb3 ]		; <i1> [#uses=1]
+	%.SV70.phi1028 = phi i32 [ %.SV70.phi1085, %bb96 ], [ %12, %bb3 ]		; <i32> [#uses=2]
+	%.SV52.phi1024 = phi i32* [ undef, %bb96 ], [ %9, %bb3 ]		; <i32*> [#uses=1]
+	%.SV68.phi1023 = phi i32 [ %.SV68.phi1086, %bb96 ], [ %10, %bb3 ]		; <i32> [#uses=2]
+	%.SV38.phi1017 = phi i64 [ %.SV38.phi1087, %bb96 ], [ %4, %bb3 ]		; <i64> [#uses=2]
+	%.SV40.phi = phi i32 [ undef, %bb96 ], [ %6, %bb3 ]		; <i32> [#uses=1]
+	%Opq.link.mask942 = and i32 %Opq.link.SV940.phi, 6		; <i32> [#uses=1]
+	%Opq.sa.calc939 = sub i32 %Opq.link.mask942, -87		; <i32> [#uses=1]
+	%meshCmp407 = icmp eq i32 %meshStackVariable405.phi, 6		; <i1> [#uses=1]
+	br i1 %meshCmp407, label %bb56, label %bb98
+
+meshBB408:		; preds = %bb89.fragment, %bb87
+	%.SV38.phi1218 = phi i64 [ %.SV38.phi1191, %bb89.fragment ], [ %.SV38.phi1210, %bb87 ]		; <i64> [#uses=2]
+	%.SV52.phi1217 = phi i32* [ %.SV52.phi1190, %bb89.fragment ], [ %.SV52.phi1235, %bb87 ]		; <i32*> [#uses=1]
+	%.SV68.phi1216 = phi i32 [ %.SV68.phi1189, %bb89.fragment ], [ %.SV68.phi1209, %bb87 ]		; <i32> [#uses=2]
+	%.SV70.phi1215 = phi i32 [ %.SV70.phi1188, %bb89.fragment ], [ %.SV70.phi1208, %bb87 ]		; <i32> [#uses=2]
+	%.SV172.phi1074 = phi i32 [ %211, %bb89.fragment ], [ undef, %bb87 ]		; <i32> [#uses=1]
+	%meshStackVariable409.phi = phi i32 [ %Opq.sa.calc962, %bb89.fragment ], [ %Opq.sa.calc673, %bb87 ]		; <i32> [#uses=1]
+	%Opq.link.SV913.phi = phi i32 [ %Opq.sa.calc962, %bb89.fragment ], [ %Opq.sa.calc990, %bb87 ]		; <i32> [#uses=1]
+	%Opq.link.mask915 = and i32 %Opq.link.SV913.phi, 9		; <i32> [#uses=1]
+	%Opq.sa.calc912 = xor i32 %Opq.link.mask915, 195		; <i32> [#uses=1]
+	%meshCmp411 = icmp eq i32 %meshStackVariable409.phi, 1		; <i1> [#uses=1]
+	br i1 %meshCmp411, label %bb97, label %bb95
+
+meshBB412:		; preds = %bb68.fragment, %bb13.fragment
+	%.SV38.phi1187 = phi i64 [ %.SV38.phi1115, %bb13.fragment ], [ %.SV38.phi1172, %bb68.fragment ]		; <i64> [#uses=2]
+	%.SV52.phi1186 = phi i32* [ %.SV52.phi1113, %bb13.fragment ], [ %.SV52.phi1170, %bb68.fragment ]		; <i32*> [#uses=2]
+	%.SV68.phi1185 = phi i32 [ %.SV68.phi1112, %bb13.fragment ], [ %.SV68.phi1169, %bb68.fragment ]		; <i32> [#uses=2]
+	%.SV70.phi1184 = phi i32 [ %.SV70.phi1111, %bb13.fragment ], [ %.SV70.phi1168, %bb68.fragment ]		; <i32> [#uses=2]
+	%.SV158.phi1063 = phi i32 [ undef, %bb13.fragment ], [ %168, %bb68.fragment ]		; <i32> [#uses=1]
+	%.SV87.phi1030 = phi i32 [ %47, %bb13.fragment ], [ undef, %bb68.fragment ]		; <i32> [#uses=1]
+	%meshStackVariable413.phi = phi i32 [ %Opq.sa.calc870, %bb13.fragment ], [ %Opq.sa.calc784, %bb68.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV933.phi = phi i32 [ %Opq.sa.calc870, %bb13.fragment ], [ %Opq.link.mask722, %bb68.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV936.phi = phi i32 [ %Opq.sa.calc866, %bb13.fragment ], [ %Opq.sa.calc784, %bb68.fragment ]		; <i32> [#uses=1]
+	%Opq.link.mask938 = and i32 %Opq.link.SV936.phi, 4		; <i32> [#uses=1]
+	%Opq.link.mask935 = and i32 %Opq.link.SV933.phi, 0		; <i32> [#uses=1]
+	%Opq.sa.calc931 = sub i32 %Opq.link.mask935, %Opq.link.mask938		; <i32> [#uses=1]
+	%Opq.sa.calc932 = xor i32 %Opq.sa.calc931, -51		; <i32> [#uses=3]
+	%meshCmp415 = icmp eq i32 %meshStackVariable413.phi, 6		; <i1> [#uses=1]
+	br i1 %meshCmp415, label %bb74, label %bb19
+
+meshBB416:		; preds = %bb90.fragment, %bb77
+	%.SV38.phi1201 = phi i64 [ %.SV38.phi1191, %bb90.fragment ], [ %.SV38.phi1098, %bb77 ]		; <i64> [#uses=2]
+	%.SV52.phi1200 = phi i32* [ undef, %bb90.fragment ], [ %.SV52.phi1097, %bb77 ]		; <i32*> [#uses=1]
+	%.SV68.phi1199 = phi i32 [ %.SV68.phi1189, %bb90.fragment ], [ %.SV68.phi1096, %bb77 ]		; <i32> [#uses=2]
+	%.SV70.phi1198 = phi i32 [ %.SV70.phi1188, %bb90.fragment ], [ %.SV70.phi1095, %bb77 ]		; <i32> [#uses=2]
+	%.SV.phi1076 = phi i32 [ %214, %bb90.fragment ], [ undef, %bb77 ]		; <i32> [#uses=1]
+	%meshStackVariable417.phi = phi i32 [ %Opq.sa.calc773, %bb90.fragment ], [ %Opq.sa.calc643, %bb77 ]		; <i32> [#uses=1]
+	%Opq.link.SV973.phi = phi i32 [ %Opq.sa.calc773, %bb90.fragment ], [ %Opq.sa.calc640, %bb77 ]		; <i32> [#uses=1]
+	%Opq.link.mask975 = and i32 %Opq.link.SV973.phi, 10		; <i32> [#uses=1]
+	%Opq.sa.calc972 = xor i32 %Opq.link.mask975, 110		; <i32> [#uses=1]
+	%Opq.sa.calc971 = add i32 %Opq.sa.calc972, -19		; <i32> [#uses=1]
+	%meshCmp419 = icmp eq i32 %meshStackVariable417.phi, 12		; <i1> [#uses=1]
+	br i1 %meshCmp419, label %bb78, label %bb96
+
+meshBB420:		; preds = %bb66, %bb26.fragment
+	%.SV38.phi1194 = phi i64 [ %.SV38.phi1098, %bb66 ], [ %.SV38.phi1167, %bb26.fragment ]		; <i64> [#uses=2]
+	%.SV68.phi1193 = phi i32 [ %.SV68.phi1096, %bb66 ], [ %.SV68.phi1166, %bb26.fragment ]		; <i32> [#uses=2]
+	%.SV70.phi1192 = phi i32 [ %.SV70.phi1095, %bb66 ], [ %.SV70.phi1165, %bb26.fragment ]		; <i32> [#uses=2]
+	%.load61.SV.phi = phi i32* [ %.SV52.phi1097, %bb66 ], [ undef, %bb26.fragment ]		; <i32*> [#uses=1]
+	%.SV270.phi = phi i32 [ %165, %bb66 ], [ undef, %bb26.fragment ]		; <i32> [#uses=1]
+	%.SV272.phi = phi i32* [ %166, %bb66 ], [ undef, %bb26.fragment ]		; <i32*> [#uses=1]
+	%.SV.phi1044 = phi i32 [ undef, %bb66 ], [ %.load123.SV.phi, %bb26.fragment ]		; <i32> [#uses=1]
+	%meshStackVariable421.phi = phi i32 [ %Opq.sa.calc621, %bb66 ], [ %Opq.sa.calc918, %bb26.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV838.phi = phi i32 [ %Opq.sa.calc602, %bb66 ], [ %Opq.sa.calc918, %bb26.fragment ]		; <i32> [#uses=1]
+	%Opq.link.mask840 = and i32 %Opq.link.SV838.phi, 9		; <i32> [#uses=2]
+	%Opq.sa.calc837 = sub i32 %Opq.link.mask840, -202		; <i32> [#uses=2]
+	%Opq.sa.calc835 = sub i32 %Opq.sa.calc837, %Opq.link.mask840		; <i32> [#uses=1]
+	%Opq.sa.calc836 = xor i32 %Opq.sa.calc835, 176		; <i32> [#uses=0]
+	%meshCmp423 = icmp eq i32 %meshStackVariable421.phi, 9		; <i1> [#uses=1]
+	br i1 %meshCmp423, label %bb96, label %bb66.fragment
+
+meshBB424:		; preds = %bb86.fragment, %bb83
+	%.SV38.phi1197 = phi i64 [ %.SV38.phi1231, %bb86.fragment ], [ %.SV38.phi1098, %bb83 ]		; <i64> [#uses=2]
+	%.SV68.phi1196 = phi i32 [ %.SV68.phi1229, %bb86.fragment ], [ %.SV68.phi1096, %bb83 ]		; <i32> [#uses=2]
+	%.SV70.phi1195 = phi i32 [ %.SV70.phi1228, %bb86.fragment ], [ %.SV70.phi1095, %bb83 ]		; <i32> [#uses=2]
+	%.SV.phi1072 = phi i32 [ %209, %bb86.fragment ], [ undef, %bb83 ]		; <i32> [#uses=1]
+	%meshStackVariable425.phi = phi i32 [ %Opq.sa.calc943, %bb86.fragment ], [ %Opq.sa.calc658, %bb83 ]		; <i32> [#uses=1]
+	%Opq.link.SV951.phi = phi i32 [ %Opq.sa.calc943, %bb86.fragment ], [ %Opq.sa.calc1002, %bb83 ]		; <i32> [#uses=1]
+	%Opq.link.mask953 = and i32 %Opq.link.SV951.phi, 12		; <i32> [#uses=1]
+	%Opq.sa.calc950 = sub i32 %Opq.link.mask953, -208		; <i32> [#uses=0]
+	%meshCmp427 = icmp eq i32 %meshStackVariable425.phi, 4		; <i1> [#uses=1]
+	br i1 %meshCmp427, label %bb97, label %bb96
+
+meshBB428:		; preds = %bb70, %bb4
+	%.SV158.phi1090 = phi i32 [ %.SV158.phi, %bb70 ], [ undef, %bb4 ]		; <i32> [#uses=1]
+	%.SV162.phi1089 = phi i32* [ %.SV162.phi, %bb70 ], [ undef, %bb4 ]		; <i32*> [#uses=1]
+	%.SV164.phi1088 = phi i32 [ %.SV164.phi, %bb70 ], [ undef, %bb4 ]		; <i32> [#uses=1]
+	%.load165.SV.phi = phi i32 [ %.SV164.phi, %bb70 ], [ undef, %bb4 ]		; <i32> [#uses=1]
+	%.SV278.phi = phi %struct.Macroblock* [ %176, %bb70 ], [ undef, %bb4 ]		; <%struct.Macroblock*> [#uses=1]
+	%.SV280.phi = phi i32 [ %177, %bb70 ], [ undef, %bb4 ]		; <i32> [#uses=1]
+	%meshStackVariable429.phi = phi i32 [ %Opq.sa.calc630, %bb70 ], [ %Opq.sa.calc467, %bb4 ]		; <i32> [#uses=1]
+	%Opq.link.SV898.phi = phi i32 [ %Opq.sa.calc630, %bb70 ], [ %Opq.sa.calc462, %bb4 ]		; <i32> [#uses=1]
+	%.SV70.phi1026 = phi i32 [ %.SV70.phi1188, %bb70 ], [ %12, %bb4 ]		; <i32> [#uses=5]
+	%.SV52.phi = phi i32* [ undef, %bb70 ], [ %9, %bb4 ]		; <i32*> [#uses=3]
+	%.SV68.phi1020 = phi i32 [ %.SV68.phi1189, %bb70 ], [ %10, %bb4 ]		; <i32> [#uses=5]
+	%.SV38.phi1014 = phi i64 [ %.SV38.phi1191, %bb70 ], [ %4, %bb4 ]		; <i64> [#uses=5]
+	%.SV43.phi = phi i32 [ undef, %bb70 ], [ %8, %bb4 ]		; <i32> [#uses=1]
+	%Opq.link.mask900 = and i32 %Opq.link.SV898.phi, 4		; <i32> [#uses=1]
+	%Opq.sa.calc897 = xor i32 %Opq.link.mask900, 193		; <i32> [#uses=3]
+	%meshCmp431 = icmp eq i32 %meshStackVariable429.phi, 5		; <i1> [#uses=1]
+	br i1 %meshCmp431, label %bb5, label %bb70.fragment
+
+meshBB432:		; preds = %bb42, %bb23.fragment182
+	%.SV38.phi1179 = phi i64 [ %.SV38.phi1115, %bb23.fragment182 ], [ %.SV38.phi1231, %bb42 ]		; <i64> [#uses=7]
+	%.SV43.phi1178 = phi i32 [ %.SV43.phi1015, %bb23.fragment182 ], [ %.SV43.phi1230, %bb42 ]		; <i32> [#uses=3]
+	%.SV68.phi1177 = phi i32 [ %.SV68.phi1112, %bb23.fragment182 ], [ %.SV68.phi1229, %bb42 ]		; <i32> [#uses=7]
+	%.SV70.phi1176 = phi i32 [ %.SV70.phi1111, %bb23.fragment182 ], [ %.SV70.phi1228, %bb42 ]		; <i32> [#uses=7]
+	%.SV118.phi1040 = phi i32 [ %76, %bb23.fragment182 ], [ %.SV118.phi1125, %bb42 ]		; <i32> [#uses=7]
+	%.SV135.phi1039 = phi i1 [ %78, %bb23.fragment182 ], [ undef, %bb42 ]		; <i1> [#uses=2]
+	%meshStackVariable433.phi = phi i32 [ %Opq.sa.calc744, %bb23.fragment182 ], [ %Opq.sa.calc560, %bb42 ]		; <i32> [#uses=1]
+	%Opq.link.SV799.phi = phi i32 [ %Opq.sa.calc744, %bb23.fragment182 ], [ %Opq.sa.calc987, %bb42 ]		; <i32> [#uses=1]
+	%.SV96.phi1038 = phi i1 [ %71, %bb23.fragment182 ], [ undef, %bb42 ]		; <i1> [#uses=1]
+	%.SV99.phi1037 = phi i32* [ %72, %bb23.fragment182 ], [ undef, %bb42 ]		; <i32*> [#uses=2]
+	%.SV104.phi1036 = phi i32 [ %73, %bb23.fragment182 ], [ %.SV104.phi1127, %bb42 ]		; <i32> [#uses=3]
+	%.SV111.phi1035 = phi i32* [ %74, %bb23.fragment182 ], [ %.SV111.phi1126, %bb42 ]		; <i32*> [#uses=3]
+	%Opq.link.mask801 = and i32 %Opq.link.SV799.phi, 6		; <i32> [#uses=1]
+	%Opq.sa.calc798 = xor i32 %Opq.link.mask801, 3		; <i32> [#uses=5]
+	%meshCmp435 = icmp eq i32 %meshStackVariable433.phi, 1		; <i1> [#uses=1]
+	br i1 %meshCmp435, label %bb43, label %bb39
+
+meshBB436:		; preds = %bb71.fragment, %bb65
+	%.SV38.phi1147 = phi i64 [ %.SV38.phi1144, %bb65 ], [ %.SV38.phi1140, %bb71.fragment ]		; <i64> [#uses=2]
+	%.SV68.phi1146 = phi i32 [ %.SV68.phi1142, %bb65 ], [ %.SV68.phi1139, %bb71.fragment ]		; <i32> [#uses=2]
+	%.SV70.phi1145 = phi i32 [ %.SV70.phi1141, %bb65 ], [ %.SV70.phi1138, %bb71.fragment ]		; <i32> [#uses=2]
+	%.SV.phi1067 = phi i32 [ undef, %bb65 ], [ %.load166.SV.phi, %bb71.fragment ]		; <i32> [#uses=1]
+	%yM.0.SV.phi1066 = phi i32 [ undef, %bb65 ], [ %183, %bb71.fragment ]		; <i32> [#uses=1]
+	%.load62.SV.phi = phi i32* [ %.SV52.phi1143, %bb65 ], [ undef, %bb71.fragment ]		; <i32*> [#uses=1]
+	%.SV268.phi = phi i32 [ %164, %bb65 ], [ undef, %bb71.fragment ]		; <i32> [#uses=2]
+	%meshStackVariable437.phi = phi i32 [ %Opq.sa.calc617, %bb65 ], [ %Opq.sa.calc809, %bb71.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV704.phi = phi i32 [ %Opq.sa.calc617, %bb65 ], [ %Opq.sa.calc809, %bb71.fragment ]		; <i32> [#uses=1]
+	%Opq.link.mask706 = and i32 %Opq.link.SV704.phi, 0		; <i32> [#uses=2]
+	%Opq.sa.calc703 = add i32 %Opq.link.mask706, 216		; <i32> [#uses=0]
+	%meshCmp439 = icmp eq i32 %meshStackVariable437.phi, 2		; <i1> [#uses=1]
+	br i1 %meshCmp439, label %bb96, label %bb65.fragment
+
+meshBB440:		; preds = %bb85, %bb54.fragment
+	%.SV52.phi1235 = phi i32* [ %.SV52.phi1213, %bb85 ], [ undef, %bb54.fragment ]		; <i32*> [#uses=2]
+	%.SV38.phi1210 = phi i64 [ %.SV38.phi1214, %bb85 ], [ %.SV38.phi1207, %bb54.fragment ]		; <i64> [#uses=2]
+	%.SV68.phi1209 = phi i32 [ %.SV68.phi1212, %bb85 ], [ %.SV68.phi1206, %bb54.fragment ]		; <i32> [#uses=2]
+	%.SV70.phi1208 = phi i32 [ %.SV70.phi1211, %bb85 ], [ %.SV70.phi1205, %bb54.fragment ]		; <i32> [#uses=2]
+	%.SV.phi1056 = phi i32 [ undef, %bb85 ], [ %.SV118.phi1122, %bb54.fragment ]		; <i32> [#uses=1]
+	%meshStackVariable441.phi = phi i32 [ %Opq.sa.calc666, %bb85 ], [ %Opq.sa.calc883, %bb54.fragment ]		; <i32> [#uses=1]
+	%Opq.link.SV991.phi = phi i32 [ %Opq.sa.calc665, %bb85 ], [ %Opq.sa.calc883, %bb54.fragment ]		; <i32> [#uses=1]
+	%Opq.link.mask993 = and i32 %Opq.link.SV991.phi, 6		; <i32> [#uses=1]
+	%Opq.sa.calc990 = xor i32 %Opq.link.mask993, 139		; <i32> [#uses=2]
+	%meshCmp443 = icmp eq i32 %meshStackVariable441.phi, 6		; <i1> [#uses=1]
+	br i1 %meshCmp443, label %bb96, label %bb87
+
+meshBB444:		; preds = %bb66.fragment, %bb40
+	%.SV38.phi1224 = phi i64 [ %.SV38.phi1194, %bb66.fragment ], [ %.SV38.phi1179, %bb40 ]		; <i64> [#uses=2]
+	%.SV68.phi1223 = phi i32 [ %.SV68.phi1193, %bb66.fragment ], [ %.SV68.phi1177, %bb40 ]		; <i32> [#uses=2]
+	%.SV70.phi1222 = phi i32 [ %.SV70.phi1192, %bb66.fragment ], [ %.SV70.phi1176, %bb40 ]		; <i32> [#uses=2]
+	%.SV.phi1048 = phi i32 [ undef, %bb66.fragment ], [ %.SV118.phi1040, %bb40 ]		; <i32> [#uses=1]
+	%meshStackVariable445.phi = phi i32 [ %Opq.sa.calc794, %bb66.fragment ], [ %Opq.sa.calc554, %bb40 ]		; <i32> [#uses=1]
+	%Opq.link.SV781.phi = phi i32 [ %Opq.sa.calc795, %bb66.fragment ], [ %Opq.sa.calc554, %bb40 ]		; <i32> [#uses=1]
+	%Opq.link.mask783 = and i32 %Opq.link.SV781.phi, 10		; <i32> [#uses=1]
+	%Opq.sa.calc780 = add i32 %Opq.link.mask783, 1		; <i32> [#uses=0]
+	%meshCmp447 = icmp eq i32 %meshStackVariable445.phi, 11		; <i1> [#uses=1]
+	br i1 %meshCmp447, label %bb96, label %bb98
+
+meshBB448:		; preds = %bb35, %entry.fragment181
+	%.SV70.phi1233 = phi i32 [ undef, %entry.fragment181 ], [ %.SV70.phi1180, %bb35 ]		; <i32> [#uses=1]
+	%.SV104.phi1157 = phi i32 [ undef, %entry.fragment181 ], [ %.SV104.phi1084, %bb35 ]		; <i32> [#uses=1]
+	%.SV111.phi1156 = phi i32* [ undef, %entry.fragment181 ], [ %.SV111.phi1083, %bb35 ]		; <i32*> [#uses=1]
+	%.SV118.phi1155 = phi i32 [ undef, %entry.fragment181 ], [ %.SV118.phi1082, %bb35 ]		; <i32> [#uses=1]
+	%.SV68.phi1025 = phi i32 [ %10, %entry.fragment181 ], [ %.SV68.phi1181, %bb35 ]		; <i32> [#uses=1]
+	%meshStackVariable449.phi = phi i32 [ %Opq.sa.calc863, %entry.fragment181 ], [ %Opq.sa.calc541, %bb35 ]		; <i32> [#uses=1]
+	%Opq.link.SV959.phi = phi i32 [ %Opq.sa.calc863, %entry.fragment181 ], [ %Opq.sa.calc828, %bb35 ]		; <i32> [#uses=1]
+	%.SV38.phi1019 = phi i64 [ %4, %entry.fragment181 ], [ %.SV38.phi1183, %bb35 ]		; <i64> [#uses=1]
+	%.SV43.phi1018 = phi i32 [ %8, %entry.fragment181 ], [ %.SV43.phi1015, %bb35 ]		; <i32> [#uses=2]
+	%Opq.link.mask961 = and i32 %Opq.link.SV959.phi, 1		; <i32> [#uses=1]
+	%Opq.sa.calc958 = xor i32 %Opq.link.mask961, 63		; <i32> [#uses=3]
+	%Opq.sa.calc957 = xor i32 %Opq.sa.calc958, 126		; <i32> [#uses=1]
+	%meshCmp451 = icmp eq i32 %meshStackVariable449.phi, 5		; <i1> [#uses=1]
+	br i1 %meshCmp451, label %bb37, label %return
+
+meshBB452:		; preds = %bb70.fragment, %bb63
+	%.SV38.phi1110 = phi i64 [ %.SV38.phi1014, %bb70.fragment ], [ %.SV38.phi1098, %bb63 ]		; <i64> [#uses=3]
+	%.SV52.phi1109 = phi i32* [ undef, %bb70.fragment ], [ %.SV52.phi1097, %bb63 ]		; <i32*> [#uses=2]
+	%.SV68.phi1108 = phi i32 [ %.SV68.phi1020, %bb70.fragment ], [ %.SV68.phi1096, %bb63 ]		; <i32> [#uses=3]
+	%.SV70.phi1107 = phi i32 [ %.SV70.phi1026, %bb70.fragment ], [ %.SV70.phi1095, %bb63 ]		; <i32> [#uses=3]
+	%.SV158.phi1106 = phi i32 [ %.SV158.phi1090, %bb70.fragment ], [ undef, %bb63 ]		; <i32> [#uses=1]
+	%.SV162.phi1105 = phi i32* [ %.SV162.phi1089, %bb70.fragment ], [ undef, %bb63 ]		; <i32*> [#uses=1]
+	%.SV164.phi1104 = phi i32 [ %.SV164.phi1088, %bb70.fragment ], [ undef, %bb63 ]		; <i32> [#uses=1]
+	%.SV264.phi = phi %struct.Macroblock* [ undef, %bb70.fragment ], [ %157, %bb63 ]		; <%struct.Macroblock*> [#uses=1]
+	%.SV266.phi = phi i32 [ undef, %bb70.fragment ], [ %158, %bb63 ]		; <i32> [#uses=1]
+	%meshStackVariable453.phi = phi i32 [ %Opq.sa.calc739, %bb70.fragment ], [ %Opq.sa.calc611, %bb63 ]		; <i32> [#uses=1]
+	%Opq.link.SV821.phi = phi i32 [ %Opq.sa.calc897, %bb70.fragment ], [ %Opq.sa.calc611, %bb63 ]		; <i32> [#uses=1]
+	%.SV150.phi1060 = phi i32* [ undef, %bb70.fragment ], [ %148, %bb63 ]		; <i32*> [#uses=1]
+	%.SV152.phi1059 = phi i32* [ undef, %bb70.fragment ], [ %149, %bb63 ]		; <i32*> [#uses=2]
+	%.SV148.phi1057 = phi i32 [ undef, %bb70.fragment ], [ %147, %bb63 ]		; <i32> [#uses=1]
+	%Opq.link.mask823 = and i32 %Opq.link.SV821.phi, 4		; <i32> [#uses=2]
+	%Opq.sa.calc820 = sub i32 %Opq.link.mask823, -97		; <i32> [#uses=2]
+	%meshCmp455 = icmp eq i32 %meshStackVariable453.phi, 6		; <i1> [#uses=1]
+	br i1 %meshCmp455, label %bb63.fragment, label %bb71
+
+meshBB456:		; preds = %bb79, %bb63.fragment
+	%.SV38.phi1137 = phi i64 [ %.SV38.phi1110, %bb63.fragment ], [ %.SV38.phi1098, %bb79 ]		; <i64> [#uses=2]
+	%.SV52.phi1136 = phi i32* [ %.SV52.phi1109, %bb63.fragment ], [ %.SV52.phi1097, %bb79 ]		; <i32*> [#uses=2]
+	%.SV68.phi1135 = phi i32 [ %.SV68.phi1108, %bb63.fragment ], [ %.SV68.phi1096, %bb79 ]		; <i32> [#uses=2]
+	%.SV70.phi1134 = phi i32 [ %.SV70.phi1107, %bb63.fragment ], [ %.SV70.phi1095, %bb79 ]		; <i32> [#uses=2]
+	%.SV152.phi1133 = phi i32* [ %.SV152.phi1059, %bb63.fragment ], [ undef, %bb79 ]		; <i32*> [#uses=1]
+	%meshStackVariable457.phi = phi i32 [ %Opq.sa.calc890, %bb63.fragment ], [ %Opq.sa.calc651, %bb79 ]		; <i32> [#uses=1]
+	%Opq.link.SV817.phi = phi i32 [ %Opq.sa.calc891, %bb63.fragment ], [ %Opq.sa.calc651, %bb79 ]		; <i32> [#uses=1]
+	%Opq.link.mask819 = and i32 %Opq.link.SV817.phi, 2		; <i32> [#uses=1]
+	%Opq.sa.calc816 = add i32 %Opq.link.mask819, 186		; <i32> [#uses=2]
+	%meshCmp459 = icmp eq i32 %meshStackVariable457.phi, 10		; <i1> [#uses=1]
+	br i1 %meshCmp459, label %bb81, label %bb65
+}




From zaimoni at zaimoni.com  Tue Apr 28 04:07:29 2009
From: zaimoni at zaimoni.com (Kenneth Boyd)
Date: Tue, 28 Apr 2009 04:07:29 -0500
Subject: [llvm-commits] [Fwd: Re: [LLVMdev] mingw build problems]
Message-ID: <49F6C751.4050209@zaimoni.com>



-------- Original Message --------
Subject: 	Re: [LLVMdev] mingw build problems
Date: 	Tue, 28 Apr 2009 04:04:31 -0500
From: 	Kenneth Boyd <zaimoni at zaimoni.com>
To: 	LLVM Developers Mailing List <llvmdev at cs.uiuc.edu>
References: 	<ee2e06e90904170758r493088rc8571cf0a489d49b at mail.gmail.com>



Jay Foad wrote:
> I'm trying to cross-compile LLVM with build=, host=target=. I'm using
> the following packages from Debian lenny:
>
> mingw32 4.2.1.dfsg-1
> mingw32-binutils 2.18.50-20080109-1
> mingw32-runtime 3.13-1
>
> The first problem I hit was when I configured with CC, CXX, AR and
> RANLIB set to mingw cross-tools, but forgot to specify NM as well.
> This resulted in a load of warnings that scrolled off the screen:
>
> nm: AliasAnalysis.o: File format not recognized
> nm: AliasAnalysisCounter.o: File format not recognized
> nm: AliasAnalysisEvaluator.o: File format not recognized
> nm: AliasDebugger.o: File format not recognized
> nm: AliasSetTracker.o: File format not recognized
> nm: Analysis.o: File format not recognized
> ...
>
> followed by millions of undefined symbols when linking any executable:
>
> llvm[2]: Linking Debug executable opt
> /home/foad/llvm/objdir-mingw/tools/opt/Debug/AnalysisWrappers.o: In
> function `~CallGraphPrinter':
> /home/foad/svn/llvm-project/llvm/trunk/tools/opt/AnalysisWrappers.cpp:71:
> undefined reference to `llvm::ModulePass::~ModulePass()'
> /home/foad/svn/llvm-project/llvm/trunk/tools/opt/AnalysisWrappers.cpp:71:
> undefined reference to `llvm::ModulePass::~ModulePass()'
> /home/foad/llvm/objdir-mingw/tools/opt/Debug/AnalysisWrappers.o: In
> function `~ExternalFunctionsPassedConstants':
> /home/foad/svn/llvm-project/llvm/trunk/tools/opt/AnalysisWrappers.cpp:32:
> undefined reference to `llvm::ModulePass::~ModulePass()'
> /home/foad/svn/llvm-project/llvm/trunk/tools/opt/AnalysisWrappers.cpp:32:
> undefined reference to `llvm::ModulePass::~ModulePass()'
> /home/foad/llvm/objdir-mingw/tools/opt/Debug/AnalysisWrappers.o:AnalysisWrappers.cpp:(.debug_info+0x1ba6):
> undefined reference to `llvm::CallGraphLinkVar'
> ...
>
> The attached patch makes GenLibDeps.pl notice that nm has failed, so
> that the build fails immediately rather than giving more obscure
> errors later on.
>   
I see (the hard way) that this patch also turns the fallback code for 
broken pipes on cmd.exe command shell into dead code (which breaks 
native MinGW build/ActivePerl ).

That said, dying on totally absent nm makes sense.  Attaching patch to 
retain die on absent nm while permitting the fallback code to run.

Kenneth Boyd


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From stoklund at 2pi.dk  Tue Apr 28 11:34:09 2009
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 28 Apr 2009 16:34:09 -0000
Subject: [llvm-commits] [llvm] r70296 - in /llvm/trunk:
 include/llvm/Target/TargetRegisterInfo.h
 lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
Message-ID: <200904281634.n3SGY9RM005510@zion.cs.uiuc.edu>

Author: stoklund
Date: Tue Apr 28 11:34:09 2009
New Revision: 70296

URL: http://llvm.org/viewvc/llvm-project?rev=70296&view=rev
Log:
Move getSubRegisterRegClass from ScheduleDagSDNodesEmit.cpp to a TargetRegisterClass method.
Also make the method non-asserting. It will return NULL when given an invalid subreg index.

The method is needed by an upcoming patch.

Modified:
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=70296&r1=70295&r2=70296&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Tue Apr 28 11:34:09 2009
@@ -148,6 +148,16 @@
     return I;
   }
 
+  /// getSubRegisterRegClass - Return the register class of subregisters with
+  /// index SubIdx, or NULL if no such class exists.
+  const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
+    assert(SubIdx>0 && "Invalid subregister index");
+    for (unsigned s = 0; s != SubIdx-1; ++s)
+      if (!SubRegClasses[s])
+        return NULL;
+    return SubRegClasses[SubIdx-1];
+  }
+
   /// superregclasses_begin / superregclasses_end - Loop over all of
   /// the superreg register classes of this register class.
   sc_iterator superregclasses_begin() const {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp?rev=70296&r1=70295&r2=70296&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Tue Apr 28 11:34:09 2009
@@ -329,18 +329,6 @@
   }
 }
 
-/// getSubRegisterRegClass - Returns the register class of specified register
-/// class' "SubIdx"'th sub-register class.
-static const TargetRegisterClass*
-getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx) {
-  // Pick the register class of the subregister
-  TargetRegisterInfo::regclass_iterator I =
-    TRC->subregclasses_begin() + SubIdx-1;
-  assert(I < TRC->subregclasses_end() &&
-         "Invalid subregister index for register class");
-  return *I;
-}
-
 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
 /// "SubIdx"'th sub-register class is the specified register class and whose
 /// type matches the specified type.
@@ -350,7 +338,7 @@
   // Pick the register class of the superegister for this type
   for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
          E = TRC->superregclasses_end(); I != E; ++I)
-    if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
+    if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC)
       return *I;
   assert(false && "Couldn't find the register class");
   return 0;
@@ -388,7 +376,8 @@
     // Figure out the register class to create for the destreg.
     unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
     const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
-    const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
+    const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
+    assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
 
     // Figure out the register class to create for the destreg.
     // Note that if we're going to directly use an existing register,




From sanjiv.gupta at microchip.com  Tue Apr 28 11:34:21 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Tue, 28 Apr 2009 16:34:21 -0000
Subject: [llvm-commits] [llvm] r70297 - in /llvm/trunk:
 include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp
Message-ID: <200904281634.n3SGYL2H005530@zion.cs.uiuc.edu>

Author: sgupta
Date: Tue Apr 28 11:34:20 2009
New Revision: 70297

URL: http://llvm.org/viewvc/llvm-project?rev=70297&view=rev
Log:
Initialized arrays can be in any address space.

Modified:
    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=70297&r1=70296&r2=70297&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Tue Apr 28 11:34:20 2009
@@ -390,7 +390,7 @@
     void EmitXXStructorList(Constant *List);
     void EmitGlobalConstantStruct(const ConstantStruct* CVS,
                                   unsigned AddrSpace);
-    void EmitGlobalConstantArray(const ConstantArray* CVA);
+    void EmitGlobalConstantArray(const ConstantArray* CVA, unsigned AddrSpace);
     void EmitGlobalConstantVector(const ConstantVector* CP);
     void EmitGlobalConstantFP(const ConstantFP* CFP, unsigned AddrSpace);
     void EmitGlobalConstantLargeInt(const ConstantInt* CI, unsigned AddrSpace);

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=70297&r1=70296&r2=70297&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Apr 28 11:34:20 2009
@@ -971,12 +971,13 @@
   O << '\n';
 }
 
-void AsmPrinter::EmitGlobalConstantArray(const ConstantArray *CVA) {
+void AsmPrinter::EmitGlobalConstantArray(const ConstantArray *CVA,
+                                         unsigned AddrSpace) {
   if (CVA->isString()) {
     EmitString(CVA);
   } else { // Not a string.  Print the values in successive locations
     for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i)
-      EmitGlobalConstant(CVA->getOperand(i));
+      EmitGlobalConstant(CVA->getOperand(i), AddrSpace);
   }
 }
 
@@ -1233,7 +1234,7 @@
     EmitZeros(Size, AddrSpace);
     return;
   } else if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) {
-    EmitGlobalConstantArray(CVA);
+    EmitGlobalConstantArray(CVA , AddrSpace);
     return;
   } else if (const ConstantStruct *CVS = dyn_cast<ConstantStruct>(CV)) {
     EmitGlobalConstantStruct(CVS, AddrSpace);




From stoklund at 2pi.dk  Tue Apr 28 11:34:36 2009
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 28 Apr 2009 16:34:36 -0000
Subject: [llvm-commits] [llvm] r70298 -
	/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
Message-ID: <200904281634.n3SGYatQ005557@zion.cs.uiuc.edu>

Author: stoklund
Date: Tue Apr 28 11:34:35 2009
New Revision: 70298

URL: http://llvm.org/viewvc/llvm-project?rev=70298&view=rev
Log:
Don't coalesce a physical register with an incompatible virtual register.

If the physical register does not belong to the virtual register's regclass,
don't coalesce. The physical register could be an invalid operand for an
instruction using the vreg.

The regclass matching is done after determining the actual subregisters being copied.

Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=70298&r1=70297&r2=70298&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue Apr 28 11:34:35 2009
@@ -1160,22 +1160,25 @@
 
   DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
 
-  unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
+  unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
   bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
   bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
   bool isSubRegToReg = CopyMI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG;
   unsigned SubIdx = 0;
   if (isExtSubReg) {
-    DstReg = CopyMI->getOperand(0).getReg();
-    SrcReg = CopyMI->getOperand(1).getReg();
+    DstReg    = CopyMI->getOperand(0).getReg();
+    DstSubIdx = CopyMI->getOperand(0).getSubReg();
+    SrcReg    = CopyMI->getOperand(1).getReg();
+    SrcSubIdx = CopyMI->getOperand(2).getImm();
   } else if (isInsSubReg || isSubRegToReg) {
     if (CopyMI->getOperand(2).getSubReg()) {
       DOUT << "\tSource of insert_subreg is already coalesced "
            << "to another register.\n";
       return false;  // Not coalescable.
     }
-    DstReg = CopyMI->getOperand(0).getReg();
-    SrcReg = CopyMI->getOperand(2).getReg();
+    DstReg    = CopyMI->getOperand(0).getReg();
+    DstSubIdx = CopyMI->getOperand(3).getImm();
+    SrcReg    = CopyMI->getOperand(2).getReg();
   } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
     assert(0 && "Unrecognized copy instruction!");
     return false;
@@ -1206,6 +1209,40 @@
     return false;  // Not coalescable.
   }
 
+  // Check that a physical source register is compatible with dst regclass
+  if (SrcIsPhys) {
+    unsigned SrcSubReg = SrcSubIdx ?
+      tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg;
+    const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
+    const TargetRegisterClass *DstSubRC = DstRC;
+    if (DstSubIdx)
+      DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
+    assert(DstSubRC && "Illegal subregister index");
+    if (!DstSubRC->contains(SrcSubReg)) {
+      DOUT << "\tIncompatible destination regclass: "
+           << tri_->getName(SrcSubReg) << " not in " << DstSubRC->getName()
+           << ".\n";
+      return false;             // Not coalescable.
+    }
+  }
+
+  // Check that a physical dst register is compatible with source regclass
+  if (DstIsPhys) {
+    unsigned DstSubReg = DstSubIdx ?
+      tri_->getSubReg(DstReg, DstSubIdx) : DstReg;
+    const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg);
+    const TargetRegisterClass *SrcSubRC = SrcRC;
+    if (SrcSubIdx)
+      SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
+    assert(SrcSubRC && "Illegal subregister index");
+    if (!SrcSubRC->contains(DstReg)) {
+      DOUT << "\tIncompatible source regclass: "
+           << tri_->getName(DstSubReg) << " not in " << SrcSubRC->getName()
+           << ".\n";
+      return false;             // Not coalescable.
+    }
+  }
+
   // Should be non-null only when coalescing to a sub-register class.
   bool CrossRC = false;
   const TargetRegisterClass *NewRC = NULL;




From stefanus.dutoit at rapidmind.com  Tue Apr 28 11:37:58 2009
From: stefanus.dutoit at rapidmind.com (Stefanus Du Toit)
Date: Tue, 28 Apr 2009 16:37:58 -0000
Subject: [llvm-commits] [llvm] r70299 -
	/llvm/trunk/lib/System/Win32/DynamicLibrary.inc
Message-ID: <200904281637.n3SGbxC5005750@zion.cs.uiuc.edu>

Author: sdt
Date: Tue Apr 28 11:37:58 2009
New Revision: 70299

URL: http://llvm.org/viewvc/llvm-project?rev=70299&view=rev
Log:
Fix choice of version of Windows callback to use to consider not only the Visual Studio version, but also the Windows SDK version.

Patch by Tareq Siraj.

Modified:
    llvm/trunk/lib/System/Win32/DynamicLibrary.inc

Modified: llvm/trunk/lib/System/Win32/DynamicLibrary.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/DynamicLibrary.inc?rev=70299&r1=70298&r2=70299&view=diff

==============================================================================
--- llvm/trunk/lib/System/Win32/DynamicLibrary.inc (original)
+++ llvm/trunk/lib/System/Win32/DynamicLibrary.inc Tue Apr 28 11:37:58 2009
@@ -19,6 +19,10 @@
  #include <dbghelp.h>
 #endif
 
+#ifdef _MSC_VER
+ #include <ntverp.h>
+#endif
+
 #ifdef __MINGW32__
  #if (HAVE_LIBIMAGEHLP != 1)
   #error "libimagehlp.a should be present"
@@ -44,7 +48,14 @@
 #endif
 
 extern "C" {
-#if !defined(_MSC_VER) || _MSC_VER < 1500
+// Use old callback if:
+//  - Not using Visual Studio
+//  - Visual Studio 2005 or earlier but only if we are not using the Windows SDK 
+//    or Windows SDK version is older than 6.0
+// Use new callback if:
+//  - Newer Visual Studio (comes with newer SDK).
+//  - Visual Studio 2005 with Windows SDK 6.0+
+#if !defined(_MSC_VER) || _MSC_VER < 1500 && (!defined(VER_PRODUCTBUILD) || VER_PRODUCTBUILD < 6000)
   static BOOL CALLBACK ELM_Callback(PSTR  ModuleName,
                                     ModuleBaseType ModuleBase,
                                     ULONG ModuleSize,




From sanjiv.gupta at microchip.com  Tue Apr 28 11:39:45 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Tue, 28 Apr 2009 16:39:45 -0000
Subject: [llvm-commits] [llvm] r70300 -
	/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
Message-ID: <200904281639.n3SGdjRw005832@zion.cs.uiuc.edu>

Author: sgupta
Date: Tue Apr 28 11:39:45 2009
New Revision: 70300

URL: http://llvm.org/viewvc/llvm-project?rev=70300&view=rev
Log:
GlobalValue is always pointer type, so an assert isn't required.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=70300&r1=70299&r2=70300&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Tue Apr 28 11:39:45 2009
@@ -483,13 +483,8 @@
   // It is BUILD_PAIR((PIC16Lo TGA), (PIC16Hi TGA)) and Op is BUILD_PAIR
   SDValue TGA = Op.getOperand(0).getOperand(0);
   GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(TGA);
-  const Type *ValueType = GSDN->getGlobal()->getType();
+  int AddrSpace = GSDN->getGlobal()->getType()->getAddressSpace();
 
-  if (!isa<PointerType>(ValueType)) {
-    assert(0 && "TGA must be of a PointerType");
-  }
-
-  int AddrSpace = dyn_cast<PointerType>(ValueType)->getAddressSpace();
   if (AddrSpace == PIC16ISD::ROM_SPACE)
     return true;
 




From dalej at apple.com  Tue Apr 28 12:15:40 2009
From: dalej at apple.com (Dale Johannesen)
Date: Tue, 28 Apr 2009 17:15:40 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r70301 -
	/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp
Message-ID: <200904281715.n3SHFfNR008189@zion.cs.uiuc.edu>

Author: johannes
Date: Tue Apr 28 12:15:29 2009
New Revision: 70301

URL: http://llvm.org/viewvc/llvm-project?rev=70301&view=rev
Log:
Prevent the code handling virtual base classes
from getting confused by similar ObjC types.
6831493.


Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-types.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=70301&r1=70300&r2=70301&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Tue Apr 28 12:15:29 2009
@@ -1685,11 +1685,11 @@
   // If already in table, reuse.
   if (!newTy) {
     newTy = copy_node(oldTy);
-    tree F2 = 0, prevF2 = 0;
+    tree F2 = 0, prevF2 = 0, F;
     // Copy the fields up to the TYPE_DECL separator.
     // VAR_DECLs can also appear, representing static members.  Possibly some
     // other junk I haven't hit yet, just skip anything that's not a FIELD:(
-    for (tree F = TYPE_FIELDS(oldTy); F; prevF2 = F2, F = TREE_CHAIN(F)) {
+    for (F = TYPE_FIELDS(oldTy); F; prevF2 = F2, F = TREE_CHAIN(F)) {
       if (TREE_CODE(F) == TYPE_DECL)
         break;
       if (TREE_CODE(F) == FIELD_DECL) {
@@ -1701,6 +1701,14 @@
         TREE_CHAIN(F2) = 0;
       }
     }
+    // If we didn't find a TYPE_DECL this isn't the virtual base class case.
+    // The ObjC trees for bitfield instance variables can look similar enough
+    // to the C++ virtual base case to get this far, but these don't have
+    // the TYPE_DECL sentinel, nor the virtual base class allocation problem.
+    if (!F || TREE_CODE(F) != TYPE_DECL) {
+      BaseTypesMap[oldTy] = oldTy;
+      return oldTy;
+    }
     BaseTypesMap[oldTy] = newTy;
     BaseTypesMap[newTy] = oldTy;
     /* Prevent gcc's garbage collector from destroying newTy.  The




From dalej at apple.com  Tue Apr 28 12:16:30 2009
From: dalej at apple.com (Dale Johannesen)
Date: Tue, 28 Apr 2009 17:16:30 -0000
Subject: [llvm-commits] [llvm] r70302 -
	/llvm/trunk/test/FrontendObjC/2009-04-28-bitfield-vs-vbc.m
Message-ID: <200904281716.n3SHGVQo008243@zion.cs.uiuc.edu>

Author: johannes
Date: Tue Apr 28 12:16:30 2009
New Revision: 70302

URL: http://llvm.org/viewvc/llvm-project?rev=70302&view=rev
Log:
Test for llvm-gcc bug fixed by 70301.


Added:
    llvm/trunk/test/FrontendObjC/2009-04-28-bitfield-vs-vbc.m

Added: llvm/trunk/test/FrontendObjC/2009-04-28-bitfield-vs-vbc.m
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendObjC/2009-04-28-bitfield-vs-vbc.m?rev=70302&view=auto

==============================================================================
--- llvm/trunk/test/FrontendObjC/2009-04-28-bitfield-vs-vbc.m (added)
+++ llvm/trunk/test/FrontendObjC/2009-04-28-bitfield-vs-vbc.m Tue Apr 28 12:16:30 2009
@@ -0,0 +1,127 @@
+// RUN: %llvmgcc -S -x objective-c -m32 %s -o %t
+// This used to crash, 6831493.
+#include <stdlib.h>
+
+struct s0 {
+  double x;
+};
+
+ at interface I2 {
+  struct s0 _iv1;
+}
+ at end
+
+ at interface I3 : I2 {
+  unsigned int _iv2 :1;
+  unsigned : 0;
+  unsigned int _iv3 : 3;
+}
+ at end
+
+ at interface I4 : I3 {
+  char _iv4;
+}
+ at end
+
+ at interface I5 : I4 {
+  char _iv5;
+  int _iv6;
+  int _iv7;
+}
+
+ at property int P1;
+ at end
+
+ at implementation I2
+ at end
+
+ at implementation I3
+ at end
+
+ at implementation I4 
+ at end
+
+ at interface I5 ()
+ at property int P2;
+ at end
+
+#if 0
+int g2 = sizeof(I2);
+int g3 = sizeof(I3);
+int g4 = sizeof(I4);
+int g5_0 = sizeof(I5);
+#endif
+
+ at implementation I5
+#ifdef __x86_64
+ at synthesize P1 = _MadeUpName;
+ at synthesize P2 = _AnotherMadeUpName;
+#else
+ at synthesize P1 = _iv6;
+ at synthesize P2 = _iv7;
+#endif
+ at end
+
+#if 0
+int g5_1 = sizeof(I5);
+#endif
+
+ at interface T0_I0 {
+  double iv_A_0;
+  char iv_A_1;
+}
+ at end
+
+ at interface T0_I1 : T0_I0 {
+  char iv_B_0;
+}
+ at end
+
+ at interface T0_I2 : T0_I1 {
+  char iv_C_0;
+}
+ at end
+
+#if 0
+int g6 = sizeof(T0_I0);
+int g7 = sizeof(T0_I1);
+int g8 = sizeof(T0_I2);
+#endif
+  
+ at implementation T0_I0 @end
+ at implementation T0_I1 @end  
+ at implementation T0_I2 @end
+
+void f0(I2*i2,I3*i3,I4*i4,I5*i5,T0_I0*t0_i0,T0_I1*t0_i1,T0_I2*t0_i2) {
+}
+
+// Thomas Wang's ui32 hash.
+unsigned hash_ui32_to_ui32(unsigned a) {
+  a = (a ^ 61) ^ (a >> 16);
+  a = a + (a << 3);
+  a = a ^ (a >> 4);
+  a = a * 0x27d4eb2d;
+  a = a ^ (a >> 15);
+  return a;
+}
+
+unsigned char hash_ui32_to_ui8(unsigned ui) {
+  ui = hash_ui32_to_ui32(ui);
+  ui ^= ui>>8;
+  ui ^= ui>>8;
+  ui ^= ui>>8;
+  return (unsigned char) ui;
+}
+
+void *init() {
+  unsigned i, N = 1024;
+  unsigned char *p = malloc(N);
+  for (i=0; i != N; ++i)
+    p[i] = hash_ui32_to_ui8(i);
+  return p;
+}
+
+int main(){
+  void *p = init();
+  f0(p,p,p,p,p,p,p);
+}




From dalej at apple.com  Tue Apr 28 12:52:45 2009
From: dalej at apple.com (Dale Johannesen)
Date: Tue, 28 Apr 2009 17:52:45 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r70306 -
 /llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/image-info-1.m
Message-ID: <200904281752.n3SHqjh3009875@zion.cs.uiuc.edu>

Author: johannes
Date: Tue Apr 28 12:52:45 2009
New Revision: 70306

URL: http://llvm.org/viewvc/llvm-project?rev=70306&view=rev
Log:
Adjust test to allow different syntax from llvm-gcc.


Modified:
    llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/image-info-1.m

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/image-info-1.m
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/image-info-1.m?rev=70306&r1=70305&r2=70306&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/image-info-1.m (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/image-info-1.m Tue Apr 28 12:52:45 2009
@@ -6,4 +6,5 @@
 @end
 @implementation  INTF
 @end
-/* { dg-final { scan-assembler "L_OBJC_IMAGE_INFO:\n\t.long\t0\n\t.long\t16" } } */
+/* LLVM LOCAL allow different spelling */
+/* { dg-final { scan-assembler "L_OBJC_IMAGE_INFO:\n\t(.long\t0|.space\t4)\n\t.long\t16" } } */




From dalej at apple.com  Tue Apr 28 13:03:34 2009
From: dalej at apple.com (Dale Johannesen)
Date: Tue, 28 Apr 2009 18:03:34 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r70308 -
 /llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/utf16-x86-cfstring-1.m
Message-ID: <200904281803.n3SI3YcN010272@zion.cs.uiuc.edu>

Author: johannes
Date: Tue Apr 28 13:03:33 2009
New Revision: 70308

URL: http://llvm.org/viewvc/llvm-project?rev=70308&view=rev
Log:
Allow for different llvm syntax.  This fixes 1 of the 2
failures here; the other involves matching full 8-bit,
non-ASCII characters, and I can't figure out a way to get
the harness to match these.  Output is OK.


Modified:
    llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/utf16-x86-cfstring-1.m

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/utf16-x86-cfstring-1.m
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/utf16-x86-cfstring-1.m?rev=70308&r1=70307&r2=70308&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/utf16-x86-cfstring-1.m (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/utf16-x86-cfstring-1.m Tue Apr 28 13:03:33 2009
@@ -12,6 +12,7 @@
 }
 /* { dg-final { scan-assembler ".section __TEXT,__ustring" } } */
 /* LLVM LOCAL begin same data, very different syntax */
-/* { dg-final { scan-assembler "___utf16_string_1:.*\n\t(.byte\t-110\n\t.byte\t33\n\t.byte\t32\n\t.byte\t0|.asciz\t\"\\\\622! \\\\000)" } } */
+/* { dg-final { scan-assembler "___utf16_string_1:.*\n\t(.byte\t-110\n\t.byte\t33\n\t.byte\t32\n\t.byte\t0|.asciz\t\"\\\\622! \\\\000|.asciz\t\"\\\\222! \\\\000)" } } */
 /* { dg-final { scan-assembler "___utf16_string_2:.*\n\t(.byte\t1\n\t.byte\t-40\n\t.byte\t0\n\t.byte\t-36|.asciz\t\"\\\\001\\\\730\\\\000\\\\734)" } } */
-/* LLVM LOCAL end */
\ No newline at end of file
+/* LLVM LOCAL end */
+




From evan.cheng at apple.com  Tue Apr 28 13:29:28 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Apr 2009 18:29:28 -0000
Subject: [llvm-commits] [llvm] r70309 - in /llvm/trunk:
 include/llvm/Target/TargetRegisterInfo.h
 lib/CodeGen/SimpleRegisterCoalescing.cpp
Message-ID: <200904281829.n3SITTq0011191@zion.cs.uiuc.edu>

Author: evancheng
Date: Tue Apr 28 13:29:27 2009
New Revision: 70309

URL: http://llvm.org/viewvc/llvm-project?rev=70309&view=rev
Log:
Move getMatchingSuperReg() out of coalescer and into TargetRegisterInfo.

Modified:
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=70309&r1=70308&r2=70309&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Tue Apr 28 13:29:27 2009
@@ -476,6 +476,16 @@
   /// exist.
   virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
 
+  /// getMatchingSuperReg - Return a super-register of the specified register
+  /// Reg so its sub-register of index SubIdx is Reg.
+  unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 
+                               const TargetRegisterClass *RC) const {
+    for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
+      if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
+        return SR;
+    return 0;
+  }
+
   //===--------------------------------------------------------------------===//
   // Register Class Information
   //

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=70309&r1=70308&r2=70309&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue Apr 28 13:29:27 2009
@@ -1000,18 +1000,6 @@
   }
 }
 
-/// getMatchingSuperReg - Return a super-register of the specified register
-/// Reg so its sub-register of index SubIdx is Reg.
-static unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 
-                                    const TargetRegisterClass *RC,
-                                    const TargetRegisterInfo* TRI) {
-  for (const unsigned *SRs = TRI->getSuperRegisters(Reg);
-       unsigned SR = *SRs; ++SRs)
-    if (Reg == TRI->getSubReg(SR, SubIdx) && RC->contains(SR))
-      return SR;
-  return 0;
-}
-
 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
 /// two virtual registers from different register classes.
 bool
@@ -1064,7 +1052,7 @@
           TargetRegisterInfo::isPhysicalRegister(SrcReg)
           ? tri_->getPhysicalRegisterRegClass(SrcReg)
           : mri_->getRegClass(SrcReg);
-        if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
+        if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
           return true;
       }
     }
@@ -1080,7 +1068,7 @@
           TargetRegisterInfo::isPhysicalRegister(DstReg)
           ? tri_->getPhysicalRegisterRegClass(DstReg)
           : mri_->getRegClass(DstReg);
-        if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
+        if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
           return true;
       }
     }
@@ -1097,7 +1085,7 @@
                                                unsigned SrcReg, unsigned SubIdx,
                                                unsigned &RealDstReg) {
   const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
-  RealDstReg = getMatchingSuperReg(DstReg, SubIdx, RC, tri_);
+  RealDstReg = tri_->getMatchingSuperReg(DstReg, SubIdx, RC);
   assert(RealDstReg && "Invalid extract_subreg instruction!");
 
   // For this type of EXTRACT_SUBREG, conservatively
@@ -1127,7 +1115,7 @@
                                                unsigned SrcReg, unsigned SubIdx,
                                                unsigned &RealSrcReg) {
   const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
-  RealSrcReg = getMatchingSuperReg(SrcReg, SubIdx, RC, tri_);
+  RealSrcReg = tri_->getMatchingSuperReg(SrcReg, SubIdx, RC);
   assert(RealSrcReg && "Invalid extract_subreg instruction!");
 
   LiveInterval &RHS = li_->getInterval(DstReg);




From bob.wilson at apple.com  Tue Apr 28 14:41:45 2009
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 28 Apr 2009 19:41:45 -0000
Subject: [llvm-commits] [llvm] r70319 -
	/llvm/trunk/utils/TableGen/TGParser.cpp
Message-ID: <200904281941.n3SJfj2K013990@zion.cs.uiuc.edu>

Author: bwilson
Date: Tue Apr 28 14:41:44 2009
New Revision: 70319

URL: http://llvm.org/viewvc/llvm-project?rev=70319&view=rev
Log:
Fix trailing whitespace and 80-col. violations in recent TableGen changes.

Modified:
    llvm/trunk/utils/TableGen/TGParser.cpp

Modified: llvm/trunk/utils/TableGen/TGParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGParser.cpp?rev=70319&r1=70318&r2=70319&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/TGParser.cpp (original)
+++ llvm/trunk/utils/TableGen/TGParser.cpp Tue Apr 28 14:41:44 2009
@@ -38,7 +38,7 @@
   MultiClass *MC;
   std::vector<Init*> TemplateArgs;
   SubMultiClassReference() : MC(0) {}
-  
+
   bool isInvalid() const { return MC == 0; }
   void dump() const;
 };
@@ -228,7 +228,7 @@
 
     CurMultiClass->DefPrototypes.push_back(NewDef);
   }
-  
+
   const std::vector<std::string> &SMCTArgs = SMC->Rec.getTemplateArgs();
 
   // Ensure that an appropriate number of template arguments are
@@ -236,7 +236,7 @@
   if (SMCTArgs.size() < SubMultiClass.TemplateArgs.size())
     return Error(SubMultiClass.RefLoc,
                  "More template args specified than expected");
-  
+
   // Loop over all of the template arguments, setting them to the specified
   // value or leaving them as the default if necessary.
   for (unsigned i = 0, e = SMCTArgs.size(); i != e; ++i) {
@@ -244,13 +244,13 @@
       // If a value is specified for this template arg, set it in the
       // superclass now.
       if (SetValue(CurRec, SubMultiClass.RefLoc, SMCTArgs[i],
-                   std::vector<unsigned>(), 
+                   std::vector<unsigned>(),
                    SubMultiClass.TemplateArgs[i]))
         return true;
 
       // Resolve it next.
       CurRec->resolveReferencesTo(CurRec->getValue(SMCTArgs[i]));
-      
+
       // Now remove it.
       CurRec->removeValue(SMCTArgs[i]);
 
@@ -264,7 +264,7 @@
         Record *Def = *j;
 
         if (SetValue(Def, SubMultiClass.RefLoc, SMCTArgs[i],
-                     std::vector<unsigned>(), 
+                     std::vector<unsigned>(),
                      SubMultiClass.TemplateArgs[i]))
           return true;
 
@@ -277,7 +277,7 @@
     } else if (!CurRec->getValue(SMCTArgs[i])->getValue()->isComplete()) {
       return Error(SubMultiClass.RefLoc,
                    "Value not specified for template argument #"
-                   + utostr(i) + " (" + SMCTArgs[i] + ") of subclass '" + 
+                   + utostr(i) + " (" + SMCTArgs[i] + ") of subclass '" +
                    SMC->Rec.getName() + "'!");
     }
   }
@@ -331,8 +331,8 @@
   return Result;
 }
 
-/// ParseMultiClassID - Parse and resolve a reference to a multiclass name.  This returns
-/// null on error.
+/// ParseMultiClassID - Parse and resolve a reference to a multiclass name.
+/// This returns null on error.
 ///
 ///    MultiClassID ::= ID
 ///
@@ -341,11 +341,11 @@
     TokError("expected name for ClassID");
     return 0;
   }
-  
+
   MultiClass *Result = MultiClasses[Lex.getCurStrVal()];
   if (Result == 0)
     TokError("Couldn't find class '" + Lex.getCurStrVal() + "'");
-  
+
   Lex.Lex();
   return Result;
 }
@@ -412,8 +412,9 @@
   return Result;
 }
 
-/// ParseSubMultiClassReference - Parse a reference to a subclass or to a templated
-/// submulticlass.  This returns a SubMultiClassRefTy with a null Record* on error.
+/// ParseSubMultiClassReference - Parse a reference to a subclass or to a
+/// templated submulticlass.  This returns a SubMultiClassRefTy with a null
+/// Record* on error.
 ///
 ///  SubMultiClassRef ::= MultiClassID
 ///  SubMultiClassRef ::= MultiClassID '<' ValueList '>'
@@ -422,27 +423,27 @@
 ParseSubMultiClassReference(MultiClass *CurMC) {
   SubMultiClassReference Result;
   Result.RefLoc = Lex.getLoc();
-  
+
   Result.MC = ParseMultiClassID();
   if (Result.MC == 0) return Result;
-  
+
   // If there is no template arg list, we're done.
   if (Lex.getCode() != tgtok::less)
     return Result;
   Lex.Lex();  // Eat the '<'
-  
+
   if (Lex.getCode() == tgtok::greater) {
     TokError("subclass reference requires a non-empty list of template values");
     Result.MC = 0;
     return Result;
   }
-  
+
   Result.TemplateArgs = ParseValueList(&CurMC->Rec);
   if (Result.TemplateArgs.empty()) {
     Result.MC = 0;   // Error parsing value list.
     return Result;
   }
-    
+
   if (Lex.getCode() != tgtok::greater) {
     TokError("expected '>' in template value list");
     Result.MC = 0;
@@ -854,7 +855,8 @@
          return 0;
        }
        Lex.Lex();  // eat the ')'
-       Operator = (new BinOpInit(Code, LHS, RHS, Type))->Fold(CurRec, CurMultiClass);
+       Operator = (new BinOpInit(Code, LHS, RHS, Type))->Fold(CurRec,
+                                                              CurMultiClass);
     }
 
     // If the operator name is present, parse it.
@@ -1496,7 +1498,8 @@
 
 /// ParseMultiClass - Parse a multiclass definition.
 ///
-///  MultiClassInst ::= MULTICLASS ID TemplateArgList? ':' BaseMultiClassList '{' MultiClassDef+ '}'
+///  MultiClassInst ::= MULTICLASS ID TemplateArgList?
+///                     ':' BaseMultiClassList '{' MultiClassDef+ '}'
 ///
 bool TGParser::ParseMultiClass() {
   assert(Lex.getCode() == tgtok::MultiClass && "Unexpected token");
@@ -1524,17 +1527,18 @@
     inherits = true;
 
     Lex.Lex();
-    
+
     // Read all of the submulticlasses.
-    SubMultiClassReference SubMultiClass = ParseSubMultiClassReference(CurMultiClass);
+    SubMultiClassReference SubMultiClass =
+      ParseSubMultiClassReference(CurMultiClass);
     while (1) {
       // Check for error.
       if (SubMultiClass.MC == 0) return true;
-     
+
       // Add it.
       if (AddSubMultiClass(CurMultiClass, SubMultiClass))
         return true;
-      
+
       if (Lex.getCode() != tgtok::comma) break;
       Lex.Lex(); // eat ','.
       SubMultiClass = ParseSubMultiClassReference(CurMultiClass);
@@ -1606,7 +1610,8 @@
       Record *DefProto = MC->DefPrototypes[i];
 
       // Add the suffix to the defm name to get the new name.
-      Record *CurRec = new Record(DefmPrefix + DefProto->getName(), DefmPrefixLoc);
+      Record *CurRec = new Record(DefmPrefix + DefProto->getName(),
+                                  DefmPrefixLoc);
 
       SubClassReference Ref;
       Ref.RefLoc = DefmPrefixLoc;
@@ -1616,7 +1621,8 @@
       // Loop over all of the template arguments, setting them to the specified
       // value or leaving them as the default if necessary.
       for (unsigned i = 0, e = TArgs.size(); i != e; ++i) {
-        if (i < TemplateVals.size()) { // A value is specified for this temp-arg?
+        // Check if a value is specified for this temp-arg.
+        if (i < TemplateVals.size()) {
           // Set it now.
           if (SetValue(CurRec, DefmPrefixLoc, TArgs[i], std::vector<unsigned>(),
                        TemplateVals[i]))
@@ -1629,7 +1635,8 @@
           CurRec->removeValue(TArgs[i]);
 
         } else if (!CurRec->getValue(TArgs[i])->getValue()->isComplete()) {
-          return Error(SubClassLoc, "value not specified for template argument #"+
+          return Error(SubClassLoc,
+                       "value not specified for template argument #"+
                        utostr(i) + " (" + TArgs[i] + ") of multiclassclass '" +
                        MC->Rec.getName() + "'");
         }




From asl at math.spbu.ru  Tue Apr 28 16:49:33 2009
From: asl at math.spbu.ru (Anton Korobeynikov)
Date: Tue, 28 Apr 2009 21:49:33 -0000
Subject: [llvm-commits] [llvm] r70328 - in /llvm/trunk:
 lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
 lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
 test/CodeGen/X86/2009-04-29-InlineAsmPMemoryModifier.ll
Message-ID: <200904282149.n3SLnXlK018271@zion.cs.uiuc.edu>

Author: asl
Date: Tue Apr 28 16:49:33 2009
New Revision: 70328

URL: http://llvm.org/viewvc/llvm-project?rev=70328&view=rev
Log:
Properly print 'P' modifier on inline asm memory operands.
This should fix PR3379 and PR4064.
Patch inspired by Edwin T?r?k!

Added:
    llvm/trunk/test/CodeGen/X86/2009-04-29-InlineAsmPMemoryModifier.ll
Modified:
    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=70328&r1=70327&r2=70328&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Tue Apr 28 16:49:33 2009
@@ -570,12 +570,13 @@
 }
 
 void X86ATTAsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
-                                            const char *Modifier){
+                                            const char *Modifier,
+                                            bool NotRIPRel) {
   MachineOperand BaseReg  = MI->getOperand(Op);
   MachineOperand IndexReg = MI->getOperand(Op+2);
   const MachineOperand &DispSpec = MI->getOperand(Op+3);
 
-  bool NotRIPRel = IndexReg.getReg() || BaseReg.getReg();
+  NotRIPRel |= IndexReg.getReg() || BaseReg.getReg();
   if (DispSpec.isGlobal() ||
       DispSpec.isCPI() ||
       DispSpec.isJTI() ||
@@ -615,14 +616,14 @@
 }
 
 void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
-                                         const char *Modifier){
+                                         const char *Modifier, bool NotRIPRel){
   assert(isMem(MI, Op) && "Invalid memory reference!");
   MachineOperand Segment = MI->getOperand(Op+4);
   if (Segment.getReg()) {
       printOperand(MI, Op+4, Modifier);
       O << ':';
     }
-  printLeaMemReference(MI, Op, Modifier);
+  printLeaMemReference(MI, Op, Modifier, NotRIPRel);
 }
 
 void X86ATTAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
@@ -723,7 +724,7 @@
       return false;
 
     case 'P': // Don't print @PLT, but do print as memory.
-      printOperand(MI, OpNo, "mem");
+      printOperand(MI, OpNo, "mem", /*NotRIPRel=*/true);
       return false;
     }
   }
@@ -749,7 +750,7 @@
       // These only apply to registers, ignore on mem.
       break;
     case 'P': // Don't print @PLT, but do print as memory.
-      printOperand(MI, OpNo, "mem");
+      printMemReference(MI, OpNo, "mem", /*NotRIPRel=*/true);
       return false;
     }
   }

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=70328&r1=70327&r2=70328&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Tue Apr 28 16:49:33 2009
@@ -112,9 +112,9 @@
   void printMachineInstruction(const MachineInstr *MI);
   void printSSECC(const MachineInstr *MI, unsigned Op);
   void printMemReference(const MachineInstr *MI, unsigned Op,
-                         const char *Modifier=NULL);
+                         const char *Modifier=NULL, bool NotRIPRel = false);
   void printLeaMemReference(const MachineInstr *MI, unsigned Op,
-                            const char *Modifier=NULL);
+                            const char *Modifier=NULL, bool NotRIPRel = false);
   void printPICJumpTableSetLabel(unsigned uid,
                                  const MachineBasicBlock *MBB) const;
   void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,

Added: llvm/trunk/test/CodeGen/X86/2009-04-29-InlineAsmPMemoryModifier.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-29-InlineAsmPMemoryModifier.ll?rev=70328&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-29-InlineAsmPMemoryModifier.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-04-29-InlineAsmPMemoryModifier.ll Tue Apr 28 16:49:33 2009
@@ -0,0 +1,12 @@
+; RUN: llvm-as < %s | llc -march=x86-64 | grep gs: | not grep rip
+; PR3379
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+ at per_cpu__cpu_number = external global i32              ; <i32*> [#uses=1]
+
+define void @pat_init() nounwind {
+entry:
+        %0 = call i32 asm "movl %gs:${1:P},$0", "=r,*m,~{dirflag},~{fpsr},~{flags}"(i32* @per_cpu__cpu_number) nounwind         ; <i32> [#uses=0]
+        unreachable
+}




From gohman at apple.com  Tue Apr 28 16:54:24 2009
From: gohman at apple.com (Dan Gohman)
Date: Tue, 28 Apr 2009 21:54:24 -0000
Subject: [llvm-commits] [llvm] r70331 -
	/llvm/trunk/test/Analysis/ScalarEvolution/avoid-smax-1.ll
Message-ID: <200904282154.n3SLsO9G018524@zion.cs.uiuc.edu>

Author: djg
Date: Tue Apr 28 16:54:23 2009
New Revision: 70331

URL: http://llvm.org/viewvc/llvm-project?rev=70331&view=rev
Log:
Fix a grammaro in a comment.

Modified:
    llvm/trunk/test/Analysis/ScalarEvolution/avoid-smax-1.ll

Modified: llvm/trunk/test/Analysis/ScalarEvolution/avoid-smax-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/avoid-smax-1.ll?rev=70331&r1=70330&r2=70331&view=diff

==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/avoid-smax-1.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/avoid-smax-1.ll Tue Apr 28 16:54:23 2009
@@ -6,7 +6,7 @@
 ; for the bb6 loop without using a maximum calculation (icmp, select)
 ; because it should be able to prove that the comparison is guarded
 ; by an appropriate conditional branch. Unfortunately, indvars is
-; not yet able to find the comparison for the other too loops in
+; not yet able to find the comparison for the other two loops in
 ; this testcase.
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"




From gohman at apple.com  Tue Apr 28 17:03:27 2009
From: gohman at apple.com (Dan Gohman)
Date: Tue, 28 Apr 2009 22:03:27 -0000
Subject: [llvm-commits] [llvm] r70333 -
 /llvm/trunk/test/Transforms/IndVarSimplify/2003-09-23-NotAtTop.ll
Message-ID: <200904282203.n3SM3Rl9018869@zion.cs.uiuc.edu>

Author: djg
Date: Tue Apr 28 17:03:26 2009
New Revision: 70333

URL: http://llvm.org/viewvc/llvm-project?rev=70333&view=rev
Log:
Make this testcase slightly less trivial, so that it doesn't fail
if indvars happens to optimize away the unused primary induction
variable.

Modified:
    llvm/trunk/test/Transforms/IndVarSimplify/2003-09-23-NotAtTop.ll

Modified: llvm/trunk/test/Transforms/IndVarSimplify/2003-09-23-NotAtTop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/2003-09-23-NotAtTop.ll?rev=70333&r1=70332&r2=70333&view=diff

==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/2003-09-23-NotAtTop.ll (original)
+++ llvm/trunk/test/Transforms/IndVarSimplify/2003-09-23-NotAtTop.ll Tue Apr 28 17:03:26 2009
@@ -9,7 +9,8 @@
 
 Loop:           ; preds = %Loop, %0
         %NonIndvar = phi i32 [ 200, %0 ], [ %NonIndvarNext, %Loop ]             ; <i32> [#uses=1]
-        %Canonical = phi i32 [ 0, %0 ], [ %CanonicalNext, %Loop ]               ; <i32> [#uses=1]
+        %Canonical = phi i32 [ 0, %0 ], [ %CanonicalNext, %Loop ]               ; <i32> [#uses=2]
+        store i32 %Canonical, i32* null
         %NonIndvarNext = sdiv i32 %NonIndvar, 2         ; <i32> [#uses=1]
         %CanonicalNext = add i32 %Canonical, 1          ; <i32> [#uses=1]
         br label %Loop




From gohman at apple.com  Tue Apr 28 17:05:13 2009
From: gohman at apple.com (Dan Gohman)
Date: Tue, 28 Apr 2009 22:05:13 -0000
Subject: [llvm-commits] [llvm] r70334 -
	/llvm/trunk/test/Transforms/LoopSimplify/single-backedge.ll
Message-ID: <200904282205.n3SM5DUG018923@zion.cs.uiuc.edu>

Author: djg
Date: Tue Apr 28 17:05:13 2009
New Revision: 70334

URL: http://llvm.org/viewvc/llvm-project?rev=70334&view=rev
Log:
As with r70333, give the primary induction variable a use so
that it can't be trivially eliminated.

Modified:
    llvm/trunk/test/Transforms/LoopSimplify/single-backedge.ll

Modified: llvm/trunk/test/Transforms/LoopSimplify/single-backedge.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopSimplify/single-backedge.ll?rev=70334&r1=70333&r2=70334&view=diff

==============================================================================
--- llvm/trunk/test/Transforms/LoopSimplify/single-backedge.ll (original)
+++ llvm/trunk/test/Transforms/LoopSimplify/single-backedge.ll Tue Apr 28 17:05:13 2009
@@ -8,7 +8,8 @@
 ; <label>:0
 	br label %Loop
 Loop:		; preds = %BE2, %BE1, %0
-	%IV = phi i32 [ 1, %0 ], [ %IV2, %BE1 ], [ %IV2, %BE2 ]		; <i32> [#uses=1]
+	%IV = phi i32 [ 1, %0 ], [ %IV2, %BE1 ], [ %IV2, %BE2 ]		; <i32> [#uses=2]
+	store i32 %IV, i32* null
 	%IV2 = add i32 %IV, 2		; <i32> [#uses=2]
 	br i1 %C, label %BE1, label %BE2
 BE1:		; preds = %Loop




From isanbard at gmail.com  Tue Apr 28 19:09:22 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 00:09:22 -0000
Subject: [llvm-commits] [llvm] r70340 -
	/llvm/trunk/include/llvm/Target/TargetOptions.h
Message-ID: <200904290009.n3T09M9V022493@zion.cs.uiuc.edu>

Author: void
Date: Tue Apr 28 19:09:22 2009
New Revision: 70340

URL: http://llvm.org/viewvc/llvm-project?rev=70340&view=rev
Log:
Correct comment.

Modified:
    llvm/trunk/include/llvm/Target/TargetOptions.h

Modified: llvm/trunk/include/llvm/Target/TargetOptions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=70340&r1=70339&r2=70340&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOptions.h (original)
+++ llvm/trunk/include/llvm/Target/TargetOptions.h Tue Apr 28 19:09:22 2009
@@ -108,7 +108,7 @@
   /// generated.
   extern bool DisableJumpTables;
 
-  /// FastISel - This flag enables fast-path instruction selection
+  /// EnableFastISel - This flag enables fast-path instruction selection
   /// which trades away generated code quality in favor of reducing
   /// compile time.
   extern bool EnableFastISel;




From isanbard at gmail.com  Tue Apr 28 19:15:42 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 00:15:42 -0000
Subject: [llvm-commits] [llvm] r70343 - in /llvm/trunk: docs/CommandGuide/
 include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/
 lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/
 lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Alpha/AsmPrinter/
 lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CellSPU/AsmPrinter/
 lib/Target/CppBackend/ lib/Target/IA64/ lib/Target/IA64/AsmPrinter/
 lib/Target/MSIL/ lib/Target/Mips/ lib/Target/Mips/AsmPrinter/
 lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/PowerPC/Asm...
Message-ID: <200904290015.n3T0FjH5022866@zion.cs.uiuc.edu>

Author: void
Date: Tue Apr 28 19:15:41 2009
New Revision: 70343

URL: http://llvm.org/viewvc/llvm-project?rev=70343&view=rev
Log:
Second attempt:

Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.

Modified:
    llvm/trunk/docs/CommandGuide/llc.pod
    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
    llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
    llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
    llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
    llvm/trunk/include/llvm/Target/TargetMachine.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/lib/Target/ARM/ARM.h
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/Alpha/Alpha.h
    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
    llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
    llvm/trunk/lib/Target/CBackend/CBackend.cpp
    llvm/trunk/lib/Target/CBackend/CTargetMachine.h
    llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
    llvm/trunk/lib/Target/CellSPU/SPU.h
    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
    llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
    llvm/trunk/lib/Target/IA64/IA64.h
    llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
    llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
    llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
    llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
    llvm/trunk/lib/Target/Mips/Mips.h
    llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
    llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
    llvm/trunk/lib/Target/PIC16/PIC16.h
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
    llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
    llvm/trunk/lib/Target/PowerPC/PPC.h
    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
    llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
    llvm/trunk/lib/Target/Sparc/Sparc.h
    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
    llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
    llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
    llvm/trunk/lib/Target/X86/X86.h
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.h
    llvm/trunk/lib/Target/XCore/XCore.h
    llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
    llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
    llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
    llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
    llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
    llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
    llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
    llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
    llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
    llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
    llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
    llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
    llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
    llvm/trunk/test/CodeGen/X86/pr1489.ll
    llvm/trunk/test/CodeGen/X86/volatile.ll
    llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
    llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
    llvm/trunk/test/DebugInfo/deaddebuglabel.ll
    llvm/trunk/test/DebugInfo/forwardDecl.ll
    llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
    llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
    llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
    llvm/trunk/tools/llc/llc.cpp
    llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp

Modified: llvm/trunk/docs/CommandGuide/llc.pod
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CommandGuide/llc.pod?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/docs/CommandGuide/llc.pod (original)
+++ llvm/trunk/docs/CommandGuide/llc.pod Tue Apr 28 19:15:41 2009
@@ -41,6 +41,12 @@
 
 Print a summary of command line options.
 
+=item B<-O>=I<uint>
+
+Generate code at different optimization levels. These correspond to the I<-O0>,
+I<-O1>, I<-O2>, I<-O3>, and I<-O4> optimization levels used by B<llvm-gcc> and
+B<clang>.
+
 =item B<-f>
 
 Overwrite output files. By default, B<llc> will refuse to overwrite

Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Tue Apr 28 19:15:41 2009
@@ -65,8 +65,8 @@
     // Necessary for external weak linkage support
     std::set<const GlobalValue*> ExtWeakSymbols;
 
-    /// Fast - Generating code via fast instruction selection.
-    bool Fast;
+    /// OptLevel - Generating code at a specific optimization level.
+    unsigned OptLevel;
   public:
     /// Output stream on which we're printing assembly code.
     ///
@@ -110,8 +110,8 @@
     bool VerboseAsm;
 
   protected:
-    AsmPrinter(raw_ostream &o, TargetMachine &TM,
-               const TargetAsmInfo *T, bool F, bool V);
+    explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
+                        const TargetAsmInfo *T, unsigned OL, bool V);
     
   public:
     virtual ~AsmPrinter();

Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Tue Apr 28 19:15:41 2009
@@ -81,7 +81,7 @@
   void EndFunction(MachineFunction *MF);
 
   /// ValidDebugInfo - Return true if V represents valid debug info value.
-  bool ValidDebugInfo(Value *V, bool FastISel);
+  bool ValidDebugInfo(Value *V, unsigned OptLevel);
 
   /// RecordSourceLine - Register a source line with debug info. Returns a
   /// unique label ID used to generate a label and provide correspondence to

Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Tue Apr 28 19:15:41 2009
@@ -42,11 +42,11 @@
       llvm::linkOcamlGC();
       llvm::linkShadowStackGC();
       
-      (void) llvm::createBURRListDAGScheduler(NULL, false);
-      (void) llvm::createTDRRListDAGScheduler(NULL, false);
-      (void) llvm::createTDListDAGScheduler(NULL, false);
-      (void) llvm::createFastDAGScheduler(NULL, false);
-      (void) llvm::createDefaultScheduler(NULL, false);
+      (void) llvm::createBURRListDAGScheduler(NULL, 3);
+      (void) llvm::createTDRRListDAGScheduler(NULL, 3);
+      (void) llvm::createTDListDAGScheduler(NULL, 3);
+      (void) llvm::createFastDAGScheduler(NULL, 3);
+      (void) llvm::createDefaultScheduler(NULL, 3);
 
     }
   } ForceCodegenLinking; // Force link by creating a global definition.

Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Tue Apr 28 19:15:41 2009
@@ -32,7 +32,7 @@
 
 class RegisterScheduler : public MachinePassRegistryNode {
 public:
-  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, bool);
+  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned);
 
   static MachinePassRegistry Registry;
 
@@ -64,27 +64,27 @@
 /// createBURRListDAGScheduler - This creates a bottom up register usage
 /// reduction list scheduler.
 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
-                                               bool Fast);
+                                               unsigned OptLevel);
 
 /// createTDRRListDAGScheduler - This creates a top down register usage
 /// reduction list scheduler.
 ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
-                                               bool Fast);
+                                               unsigned OptLevel);
 
 /// createTDListDAGScheduler - This creates a top-down list scheduler with
 /// a hazard recognizer.
 ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
-                                             bool Fast);
+                                             unsigned OptLevel);
 
 /// createFastDAGScheduler - This creates a "fast" scheduler.
 ///
 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
-                                           bool Fast);
+                                           unsigned OptLevel);
 
 /// createDefaultScheduler - This creates an instruction scheduler appropriate
 /// for the target.
 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
-                                           bool Fast);
+                                           unsigned OptLevel);
 
 } // end namespace llvm
 

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Apr 28 19:15:41 2009
@@ -202,7 +202,7 @@
   /// certain types of nodes together, or eliminating superfluous nodes.  The
   /// Level argument controls whether Combine is allowed to produce nodes and
   /// types that are illegal on the target.
-  void Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast);
+  void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned OptLevel);
 
   /// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that
   /// only uses types natively supported by the target.  Returns "true" if it
@@ -218,7 +218,7 @@
   ///
   /// Note that this is an involved process that may invalidate pointers into
   /// the graph.
-  void Legalize(bool TypesNeedLegalizing, bool Fast);
+  void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
 
   /// RemoveDeadNodes - This method deletes all unreachable nodes in the
   /// SelectionDAG.

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Tue Apr 28 19:15:41 2009
@@ -51,10 +51,10 @@
   MachineBasicBlock *BB;
   AliasAnalysis *AA;
   GCFunctionInfo *GFI;
-  bool Fast;
+  unsigned OptLevel;
   static char ID;
 
-  explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
+  explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
   virtual ~SelectionDAGISel();
   
   TargetLowering &getTargetLowering() { return TLI; }

Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
+++ llvm/trunk/include/llvm/Target/TargetMachine.h Tue Apr 28 19:15:41 2009
@@ -213,7 +213,7 @@
   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
                                                raw_ostream &,
                                                CodeGenFileType,
-                                               bool /*Fast*/) {
+                                               unsigned /* OptLevel */) {
     return FileModel::None;
   }
 
@@ -222,7 +222,8 @@
   /// used to finish up adding passes to emit the file, if necessary.
   ///
   virtual bool addPassesToEmitFileFinish(PassManagerBase &,
-                                         MachineCodeEmitter *, bool /*Fast*/) {
+                                         MachineCodeEmitter *,
+                                         unsigned /* OptLevel */) {
     return true;
   }
  
@@ -234,7 +235,7 @@
   ///
   virtual bool addPassesToEmitMachineCode(PassManagerBase &,
                                           MachineCodeEmitter &,
-                                          bool /*Fast*/) {
+                                          unsigned /* OptLevel */) {
     return true;
   }
 
@@ -243,7 +244,8 @@
   /// use this.
   virtual bool WantsWholeFile() const { return false; }
   virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
-                                        CodeGenFileType, bool /*Fast*/) {
+                                        CodeGenFileType,
+                                        unsigned /* OptLevel */) {
     return true;
   }
 };
@@ -258,16 +260,16 @@
   /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
   /// both emitting to assembly files or machine code output.
   ///
-  bool addCommonCodeGenPasses(PassManagerBase &, bool /*Fast*/);
+  bool addCommonCodeGenPasses(PassManagerBase &, unsigned /* OptLevel */);
 
 public:
   
   /// addPassesToEmitFile - Add passes to the specified pass manager to get the
   /// specified file emitted.  Typically this will involve several steps of code
-  /// generation.  If Fast is set to true, the code generator should emit code
-  /// as fast as possible, though the generated code may be less efficient.
-  /// This method should return FileModel::Error if emission of this file type
-  /// is not supported.
+  /// generation.  If OptLevel is 0, the code generator should emit code as fast
+  /// as possible, though the generated code may be less efficient.  This method
+  /// should return FileModel::Error if emission of this file type is not
+  /// supported.
   ///
   /// The default implementation of this method adds components from the
   /// LLVM retargetable code generator, invoking the methods below to get
@@ -276,14 +278,15 @@
   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
                                                raw_ostream &Out,
                                                CodeGenFileType FileType,
-                                               bool Fast);
+                                               unsigned OptLevel);
   
   /// addPassesToEmitFileFinish - If the passes to emit the specified file had
   /// to be split up (e.g., to add an object writer pass), this method can be
   /// used to finish up adding passes to emit the file, if necessary.
   ///
   virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
-                                         MachineCodeEmitter *MCE, bool Fast);
+                                         MachineCodeEmitter *MCE,
+                                         unsigned OptLevel);
  
   /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
   /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
@@ -292,21 +295,22 @@
   /// not supported.
   ///
   virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
-                                          MachineCodeEmitter &MCE, bool Fast);
+                                          MachineCodeEmitter &MCE,
+                                          unsigned OptLevel);
   
   /// Target-Independent Code Generator Pass Configuration Options.
   
   /// addInstSelector - This method should add any "last minute" LLVM->LLVM
   /// passes, then install an instruction selector pass, which converts from
   /// LLVM code to machine instructions.
-  virtual bool addInstSelector(PassManagerBase &, bool /*Fast*/) {
+  virtual bool addInstSelector(PassManagerBase &, unsigned /* OptLevel */) {
     return true;
   }
 
   /// addPreRegAllocPasses - This method may be implemented by targets that want
   /// to run passes immediately before register allocation. This should return
   /// true if -print-machineinstrs should print after these passes.
-  virtual bool addPreRegAlloc(PassManagerBase &, bool /*Fast*/) {
+  virtual bool addPreRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
     return false;
   }
 
@@ -314,14 +318,14 @@
   /// want to run passes after register allocation but before prolog-epilog
   /// insertion.  This should return true if -print-machineinstrs should print
   /// after these passes.
-  virtual bool addPostRegAlloc(PassManagerBase &, bool /*Fast*/) {
+  virtual bool addPostRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
     return false;
   }
   
   /// addPreEmitPass - This pass may be implemented by targets that want to run
   /// passes immediately before machine code is emitted.  This should return
   /// true if -print-machineinstrs should print out the code after the passes.
-  virtual bool addPreEmitPass(PassManagerBase &, bool /*Fast*/) {
+  virtual bool addPreEmitPass(PassManagerBase &, unsigned /* OptLevel */) {
     return false;
   }
   
@@ -329,7 +333,7 @@
   /// addAssemblyEmitter - This pass should be overridden by the target to add
   /// the asmprinter, if asm emission is supported.  If this is not supported,
   /// 'true' should be returned.
-  virtual bool addAssemblyEmitter(PassManagerBase &, bool /*Fast*/,
+  virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /* OptLevel */,
                                   bool /* VerboseAsmDefault */, raw_ostream &) {
     return true;
   }
@@ -337,7 +341,7 @@
   /// addCodeEmitter - This pass should be overridden by the target to add a
   /// code emitter, if supported.  If this is not supported, 'true' should be
   /// returned. If DumpAsm is true, the generated assembly is printed to cerr.
-  virtual bool addCodeEmitter(PassManagerBase &, bool /*Fast*/,
+  virtual bool addCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
                               bool /*DumpAsm*/, MachineCodeEmitter &) {
     return true;
   }
@@ -346,7 +350,7 @@
   /// a code emitter (without setting flags), if supported.  If this is not
   /// supported, 'true' should be returned.  If DumpAsm is true, the generated
   /// assembly is printed to cerr.
-  virtual bool addSimpleCodeEmitter(PassManagerBase &, bool /*Fast*/,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
                                     bool /*DumpAsm*/, MachineCodeEmitter &) {
     return true;
   }

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Apr 28 19:15:41 2009
@@ -42,8 +42,8 @@
 
 char AsmPrinter::ID = 0;
 AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
-                       const TargetAsmInfo *T, bool F, bool VDef)
-  : MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o),
+                       const TargetAsmInfo *T, unsigned OL, bool VDef)
+  : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
     TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
     IsInTextSection(false)
 {

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Tue Apr 28 19:15:41 2009
@@ -3351,7 +3351,7 @@
   }
 
   /// ValidDebugInfo - Return true if V represents valid debug info value.
-  bool ValidDebugInfo(Value *V, bool FastISel) {
+  bool ValidDebugInfo(Value *V, unsigned OptLevel) {
     if (!V)
       return false;
 
@@ -3393,7 +3393,7 @@
     case DW_TAG_lexical_block:
       /// FIXME. This interfers with the qualitfy of generated code when 
       /// during optimization.
-      if (FastISel == false)
+      if (OptLevel != 0)
         return false;
     default:
       break;
@@ -3574,7 +3574,7 @@
       return 0;
 
     SmallVector<DbgScope *, 2> &Scopes = I->second;
-    if (Scopes.empty()) return 0;
+    assert(!Scopes.empty() && "We should have at least one debug scope!");
     DbgScope *Scope = Scopes.back(); Scopes.pop_back();
     unsigned ID = MMI->NextLabelID();
     MMI->RecordUsedDbgLabel(ID);
@@ -4731,8 +4731,8 @@
 }
 
 /// ValidDebugInfo - Return true if V represents valid debug info value.
-bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) {
-  return DD && DD->ValidDebugInfo(V, FastISel);
+bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
+  return DD && DD->ValidDebugInfo(V, OptLevel);
 }
 
 /// RecordSourceLine - Records location information and associates it with a 

Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Tue Apr 28 19:15:41 2009
@@ -55,9 +55,9 @@
 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                        raw_ostream &Out,
                                        CodeGenFileType FileType,
-                                       bool Fast) {
+                                       unsigned OptLevel) {
   // Add common CodeGen passes.
-  if (addCommonCodeGenPasses(PM, Fast))
+  if (addCommonCodeGenPasses(PM, OptLevel))
     return FileModel::Error;
 
   // Fold redundant debug labels.
@@ -66,17 +66,17 @@
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
+  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (!Fast)
+  if (OptLevel != 0)
     PM.add(createLoopAlignerPass());
 
   switch (FileType) {
   default:
     break;
   case TargetMachine::AssemblyFile:
-    if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(), Out))
+    if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
       return FileModel::Error;
     return FileModel::AsmFile;
   case TargetMachine::ObjectFile:
@@ -94,9 +94,9 @@
 /// finish up adding passes to emit the file, if necessary.
 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
                                                   MachineCodeEmitter *MCE,
-                                                  bool Fast) {
+                                                  unsigned OptLevel) {
   if (MCE)
-    addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
+    addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
 
   PM.add(createGCInfoDeleter());
 
@@ -114,15 +114,15 @@
 ///
 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
                                                    MachineCodeEmitter &MCE,
-                                                   bool Fast) {
+                                                   unsigned OptLevel) {
   // Add common CodeGen passes.
-  if (addCommonCodeGenPasses(PM, Fast))
+  if (addCommonCodeGenPasses(PM, OptLevel))
     return true;
 
-  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
+  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
+  addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
 
   PM.add(createGCInfoDeleter());
 
@@ -135,11 +135,12 @@
 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
 /// both emitting to assembly files or machine code output.
 ///
-bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
+bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
+                                               unsigned OptLevel) {
   // Standard LLVM-Level Passes.
 
   // Run loop strength reduction before anything else.
-  if (!Fast) {
+  if (OptLevel != 0) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     if (PrintLSR)
       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
@@ -153,7 +154,7 @@
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
-  if (!Fast)
+  if (OptLevel != 0)
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
   PM.add(createStackProtectorPass(getTargetLowering()));
@@ -167,38 +168,38 @@
 
   // Enable FastISel with -fast, but allow that to be overridden.
   if (EnableFastISelOption == cl::BOU_TRUE ||
-      (Fast && EnableFastISelOption != cl::BOU_FALSE))
+      (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
     EnableFastISel = true;
 
   // Ask the target for an isel.
-  if (addInstSelector(PM, Fast))
+  if (addInstSelector(PM, OptLevel))
     return true;
 
   // Print the instruction selected machine code...
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (!Fast) {
+  if (OptLevel != 0) {
     PM.add(createMachineLICMPass());
     PM.add(createMachineSinkingPass());
   }
 
   // Run pre-ra passes.
-  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
+  if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Perform register allocation.
   PM.add(createRegisterAllocator());
 
   // Perform stack slot coloring.
-  if (!Fast)
+  if (OptLevel != 0)
     PM.add(createStackSlotColoringPass());
 
   if (PrintMachineCode)  // Print the register-allocated code
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Run post-ra passes.
-  if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
+  if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   if (PrintMachineCode)
@@ -216,7 +217,7 @@
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Second pass scheduler.
-  if (!Fast && !DisablePostRAScheduler) {
+  if (OptLevel != 0 && !DisablePostRAScheduler) {
     PM.add(createPostRAScheduler());
 
     if (PrintMachineCode)
@@ -224,7 +225,7 @@
   }
 
   // Branch folding must be run after regalloc and prolog/epilog insertion.
-  if (!Fast)
+  if (OptLevel != 0)
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 
   if (PrintMachineCode)

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Apr 28 19:15:41 2009
@@ -57,9 +57,9 @@
     SelectionDAG &DAG;
     const TargetLowering &TLI;
     CombineLevel Level;
+    unsigned OptLevel;
     bool LegalOperations;
     bool LegalTypes;
-    bool Fast;
 
     // Worklist of all of the nodes that need to be simplified.
     std::vector<SDNode*> WorkList;
@@ -254,13 +254,13 @@
     }
 
 public:
-    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
+    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
       : DAG(D),
         TLI(D.getTargetLoweringInfo()),
         Level(Unrestricted),
+        OptLevel(OL),
         LegalOperations(false),
         LegalTypes(false),
-        Fast(fast),
         AA(A) {}
 
     /// Run - runs the dag combiner on all nodes in the work list
@@ -4784,7 +4784,7 @@
   SDValue Ptr   = LD->getBasePtr();
 
   // Try to infer better alignment information than the load already has.
-  if (!Fast && LD->isUnindexed()) {
+  if (OptLevel != 0 && LD->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > LD->getAlignment())
         return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
@@ -4904,7 +4904,7 @@
   SDValue Ptr   = ST->getBasePtr();
 
   // Try to infer better alignment information than the store already has.
-  if (!Fast && ST->isUnindexed()) {
+  if (OptLevel != 0 && ST->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > ST->getAlignment())
         return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
@@ -6084,8 +6084,9 @@
 
 // SelectionDAG::Combine - This is the entry point for the file.
 //
-void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) {
+void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
+                           unsigned OptLevel) {
   /// run - This is the main entry point to this class.
   ///
-  DAGCombiner(*this, AA, Fast).Run(Level);
+  DAGCombiner(*this, AA, OptLevel).Run(Level);
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Apr 28 19:15:41 2009
@@ -327,7 +327,7 @@
   default: break;
   case Intrinsic::dbg_stoppoint: {
     DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
-    if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) {
+    if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
       DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
       std::string Dir, FN;
       unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
@@ -344,7 +344,7 @@
   }
   case Intrinsic::dbg_region_start: {
     DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
-    if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) {
+    if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
       unsigned ID = 
         DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
@@ -354,7 +354,7 @@
   }
   case Intrinsic::dbg_region_end: {
     DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
-    if (DW && DW->ValidDebugInfo(REI->getContext(), true)) {
+    if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
      unsigned ID = 0;
      DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
      if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
@@ -380,7 +380,7 @@
     DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
     Value *SP = FSI->getSubprogram();
 
-    if (DW->ValidDebugInfo(SP, true)) {
+    if (DW->ValidDebugInfo(SP, 0)) {
       // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
       // (most?) gdb expects.
       DebugLoc PrevLoc = DL;
@@ -425,7 +425,7 @@
   case Intrinsic::dbg_declare: {
     DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
     Value *Variable = DI->getVariable();
-    if (DW && DW->ValidDebugInfo(Variable, true)) {
+    if (DW && DW->ValidDebugInfo(Variable, 0)) {
       // Determine the address of the declared object.
       Value *Address = DI->getAddress();
       if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Apr 28 19:15:41 2009
@@ -55,8 +55,8 @@
 class VISIBILITY_HIDDEN SelectionDAGLegalize {
   TargetLowering &TLI;
   SelectionDAG &DAG;
+  unsigned OptLevel;
   bool TypesNeedLegalizing;
-  bool Fast;
 
   // Libcall insertion helpers.
 
@@ -139,7 +139,7 @@
 
 public:
   explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
-                                bool fast);
+                                unsigned ol);
 
   /// getTypeAction - Return how we should legalize values of this type, either
   /// it is already legal or we need to expand it into multiple registers of
@@ -345,9 +345,9 @@
 }
 
 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
-                                           bool types, bool fast)
-  : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
-    Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
+                                           bool types, unsigned ol)
+  : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
+    TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) {
   assert(MVT::LAST_VALUETYPE <= 32 &&
          "Too many value types for ValueTypeActions to hold!");
 }
@@ -1271,7 +1271,7 @@
         unsigned Line = DSP->getLine();
         unsigned Col = DSP->getColumn();
 
-        if (Fast) {
+        if (OptLevel == 0) {
           // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
           // won't hurt anything.
           if (useDEBUG_LOC) {
@@ -8566,9 +8566,9 @@
 
 // SelectionDAG::Legalize - This is the entry point for the file.
 //
-void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
+void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) {
   /// run - This is the main entry point to this class.
   ///
-  SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG();
+  SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG();
 }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Tue Apr 28 19:15:41 2009
@@ -630,6 +630,6 @@
 //===----------------------------------------------------------------------===//
 
 llvm::ScheduleDAGSDNodes *
-llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
+llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
   return new ScheduleDAGFast(*IS->MF);
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Tue Apr 28 19:15:41 2009
@@ -261,7 +261,7 @@
 /// new hazard recognizer. This scheduler takes ownership of the hazard
 /// recognizer and deletes it when done.
 ScheduleDAGSDNodes *
-llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) {
+llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
   return new ScheduleDAGList(*IS->MF,
                              new LatencyPriorityQueue(),
                              IS->CreateTargetHazardRecognizer());

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Apr 28 19:15:41 2009
@@ -1505,7 +1505,7 @@
 //===----------------------------------------------------------------------===//
 
 llvm::ScheduleDAGSDNodes *
-llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
+llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
   const TargetMachine &TM = IS->TM;
   const TargetInstrInfo *TII = TM.getInstrInfo();
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
@@ -1519,7 +1519,7 @@
 }
 
 llvm::ScheduleDAGSDNodes *
-llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
+llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
   const TargetMachine &TM = IS->TM;
   const TargetInstrInfo *TII = TM.getInstrInfo();
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Tue Apr 28 19:15:41 2009
@@ -3910,9 +3910,9 @@
   case Intrinsic::dbg_stoppoint: {
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
-    if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
+    if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
       MachineFunction &MF = DAG.getMachineFunction();
-      if (Fast)
+      if (OptLevel == 0)
         DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
                                         SPI.getLine(),
                                         SPI.getColumn(),
@@ -3930,7 +3930,8 @@
   case Intrinsic::dbg_region_start: {
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
-    if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
+
+    if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) {
       unsigned LabelID =
         DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
       DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
@@ -3942,8 +3943,8 @@
   case Intrinsic::dbg_region_end: {
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
-    if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
 
+    if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) {
       MachineFunction &MF = DAG.getMachineFunction();
       DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
       std::string SPName;
@@ -3952,7 +3953,7 @@
           && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
           // This is end of inlined function. Debugging information for
           // inlined function is not handled yet (only supported by FastISel).
-        if (Fast) {
+        if (OptLevel == 0) {
           unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
           if (ID != 0)
             // Returned ID is 0 if this is unbalanced "end of inlined
@@ -3978,9 +3979,9 @@
     if (!DW) return 0;
     DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
     Value *SP = FSI.getSubprogram();
-    if (SP && DW->ValidDebugInfo(SP, Fast)) {
-        MachineFunction &MF = DAG.getMachineFunction();
-      if (Fast) {
+    if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
+      MachineFunction &MF = DAG.getMachineFunction();
+      if (OptLevel == 0) {
         // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
         // (most?) gdb expects.
         DebugLoc PrevLoc = CurDebugLoc;
@@ -4051,11 +4052,11 @@
     return 0;
   }
   case Intrinsic::dbg_declare: {
-    if (Fast) {
+    if (OptLevel == 0) {
       DwarfWriter *DW = DAG.getDwarfWriter();
       DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
       Value *Variable = DI.getVariable();
-      if (DW && DW->ValidDebugInfo(Variable, Fast))
+      if (DW && DW->ValidDebugInfo(Variable, OptLevel))
         DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
                                 getValue(DI.getAddress()), getValue(Variable)));
     } else {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Tue Apr 28 19:15:41 2009
@@ -355,17 +355,17 @@
   ///
   FunctionLoweringInfo &FuncInfo;
 
-  /// Fast - We are in -fast mode.
+  /// OptLevel - What optimization level we're generating code for.
   /// 
-  bool Fast;
+  unsigned OptLevel;
   
   /// GFI - Garbage collection metadata for the function.
   GCFunctionInfo *GFI;
 
   SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
-                       FunctionLoweringInfo &funcinfo, bool fast)
+                       FunctionLoweringInfo &funcinfo, unsigned ol)
     : CurDebugLoc(DebugLoc::getUnknownLoc()), 
-      TLI(tli), DAG(dag), FuncInfo(funcinfo), Fast(fast) {
+      TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
   }
 
   void init(GCFunctionInfo *gfi, AliasAnalysis &aa);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Apr 28 19:15:41 2009
@@ -136,16 +136,16 @@
   /// createDefaultScheduler - This creates an instruction scheduler appropriate
   /// for the target.
   ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
-                                             bool Fast) {
+                                             unsigned OptLevel) {
     const TargetLowering &TLI = IS->getTargetLowering();
 
-    if (Fast)
-      return createFastDAGScheduler(IS, Fast);
+    if (OptLevel == 0)
+      return createFastDAGScheduler(IS, OptLevel);
     if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
-      return createTDListDAGScheduler(IS, Fast);
+      return createTDListDAGScheduler(IS, OptLevel);
     assert(TLI.getSchedulingPreference() ==
          TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
-    return createBURRListDAGScheduler(IS, Fast);
+    return createBURRListDAGScheduler(IS, OptLevel);
   }
 }
 
@@ -262,13 +262,13 @@
 // SelectionDAGISel code
 //===----------------------------------------------------------------------===//
 
-SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
+SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
   FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
   FuncInfo(new FunctionLoweringInfo(TLI)),
   CurDAG(new SelectionDAG(TLI, *FuncInfo)),
-  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)),
+  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)),
   GFI(),
-  Fast(fast),
+  OptLevel(OL),
   DAGSize(0)
 {}
 
@@ -576,9 +576,9 @@
   // Run the DAG combiner in pre-legalize mode.
   if (TimePassesIsEnabled) {
     NamedRegionTimer T("DAG Combining 1", GroupName);
-    CurDAG->Combine(Unrestricted, *AA, Fast);
+    CurDAG->Combine(Unrestricted, *AA, OptLevel);
   } else {
-    CurDAG->Combine(Unrestricted, *AA, Fast);
+    CurDAG->Combine(Unrestricted, *AA, OptLevel);
   }
   
   DOUT << "Optimized lowered selection DAG:\n";
@@ -608,9 +608,9 @@
       // Run the DAG combiner in post-type-legalize mode.
       if (TimePassesIsEnabled) {
         NamedRegionTimer T("DAG Combining after legalize types", GroupName);
-        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
+        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
       } else {
-        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
+        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
       }
 
       DOUT << "Optimized type-legalized selection DAG:\n";
@@ -622,9 +622,9 @@
 
   if (TimePassesIsEnabled) {
     NamedRegionTimer T("DAG Legalization", GroupName);
-    CurDAG->Legalize(DisableLegalizeTypes, Fast);
+    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
   } else {
-    CurDAG->Legalize(DisableLegalizeTypes, Fast);
+    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
   }
   
   DOUT << "Legalized selection DAG:\n";
@@ -635,9 +635,9 @@
   // Run the DAG combiner in post-legalize mode.
   if (TimePassesIsEnabled) {
     NamedRegionTimer T("DAG Combining 2", GroupName);
-    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
+    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
   } else {
-    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
+    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
   }
   
   DOUT << "Optimized legalized selection DAG:\n";
@@ -645,7 +645,7 @@
 
   if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
   
-  if (!Fast)
+  if (OptLevel != 0)
     ComputeLiveOutVRegInfo();
 
   // Third, instruction select all of the operations to machine code, adding the
@@ -1082,7 +1082,7 @@
     RegisterScheduler::setDefault(Ctor);
   }
   
-  return Ctor(this, Fast);
+  return Ctor(this, OptLevel);
 }
 
 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {

Modified: llvm/trunk/lib/Target/ARM/ARM.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.h (original)
+++ llvm/trunk/lib/Target/ARM/ARM.h Tue Apr 28 19:15:41 2009
@@ -91,7 +91,7 @@
 FunctionPass *createARMISelDag(ARMTargetMachine &TM);
 FunctionPass *createARMCodePrinterPass(raw_ostream &O,
                                        ARMTargetMachine &TM,
-                                       bool Fast, bool Verbose);
+                                       unsigned OptLevel, bool Verbose);
 FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
                                        MachineCodeEmitter &MCE);
 FunctionPass *createARMLoadStoreOptimizationPass();

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Tue Apr 28 19:15:41 2009
@@ -138,35 +138,37 @@
 
 
 // Pass Pipeline Configuration
-bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
   PM.add(createARMISelDag(*this));
   return false;
 }
 
-bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
+bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
   // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
-  if (!Fast && !DisableLdStOpti && !Subtarget.isThumb())
+  if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
     PM.add(createARMLoadStoreOptimizationPass());
 
-  if (!Fast && !DisableIfConversion && !Subtarget.isThumb())
+  if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
     PM.add(createIfConverterPass());
 
   PM.add(createARMConstantIslandPass());
   return true;
 }
 
-bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
-                                          bool Verbose, raw_ostream &Out) {
+bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                          unsigned OptLevel,
+                                          bool Verbose,
+                                          raw_ostream &Out) {
   // Output assembly language.
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
   if (AsmPrinterCtor)
-    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
+    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
 
   return false;
 }
 
 
-bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
+bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // FIXME: Move this to TargetJITInfo!
   if (DefRelocModel == Reloc::Default)
@@ -177,20 +179,22 @@
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
   }
 
   return false;
 }
 
-bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
-                                        bool DumpAsm, MachineCodeEmitter &MCE) {
+bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+                                            unsigned OptLevel,
+                                            bool DumpAsm,
+                                            MachineCodeEmitter &MCE) {
   // Machine code emitter pass for ARM.
   PM.add(createARMCodeEmitterPass(*this, MCE));
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
   }
 
   return false;

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Tue Apr 28 19:15:41 2009
@@ -41,7 +41,7 @@
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             ARMTargetMachine &tm,
-                                            bool fast, bool verbose);
+                                            unsigned OptLevel, bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -69,13 +69,13 @@
   virtual const TargetAsmInfo *createTargetAsmInfo() const;
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
 };
 

Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Tue Apr 28 19:15:41 2009
@@ -80,9 +80,9 @@
     /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
     bool InCPMode;
   public:
-    ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                  const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
+    explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                           const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
         InCPMode(false) {
       Subtarget = &TM.getSubtarget<ARMSubtarget>();
     }
@@ -1061,8 +1061,8 @@
 ///
 FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
                                              ARMTargetMachine &tm,
-                                             bool fast, bool verbose) {
-  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                             unsigned OptLevel, bool verbose) {
+  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 
 namespace {

Modified: llvm/trunk/lib/Target/Alpha/Alpha.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/Alpha.h (original)
+++ llvm/trunk/lib/Target/Alpha/Alpha.h Tue Apr 28 19:15:41 2009
@@ -26,7 +26,7 @@
   FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
   FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
                                            TargetMachine &TM,
-                                           bool Fast, bool Verbose);
+                                           unsigned OptLevel, bool Verbose);
   FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
   FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
                                            MachineCodeEmitter &MCE);

Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Tue Apr 28 19:15:41 2009
@@ -76,31 +76,34 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
+                                         unsigned OptLevel) {
   PM.add(createAlphaISelDag(*this));
   return false;
 }
-bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
+bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
+                                        unsigned OptLevel) {
   // Must run branch selection immediately preceding the asm printer
   PM.add(createAlphaBranchSelectionPass());
   return false;
 }
-bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
+bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                            unsigned OptLevel,
                                             bool Verbose,
                                             raw_ostream &Out) {
   PM.add(createAlphaLLRPPass(*this));
-  PM.add(createAlphaCodePrinterPass(Out, *this, Fast, Verbose));
+  PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }
-bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                         bool DumpAsm, MachineCodeEmitter &MCE) {
   PM.add(createAlphaCodeEmitterPass(*this, MCE));
   if (DumpAsm)
-    PM.add(createAlphaCodePrinterPass(errs(), *this, Fast, true));
+    PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel, true));
   return false;
 }
 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
-                                              bool Fast, bool DumpAsm,
+                                              unsigned OptLevel, bool DumpAsm,
                                               MachineCodeEmitter &MCE) {
-  return addCodeEmitter(PM, Fast, DumpAsm, MCE);
+  return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
 }

Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Tue Apr 28 19:15:41 2009
@@ -58,13 +58,13 @@
   static unsigned getModuleMatchQuality(const Module &M);
   
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
 };
 

Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Tue Apr 28 19:15:41 2009
@@ -36,9 +36,9 @@
     /// Unique incrementer for label values for referencing Global values.
     ///
 
-    AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
-                    const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(o, tm, T, F, V) {}
+    explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
+                             const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(o, tm, T, OL, V) {}
 
     virtual const char *getPassName() const {
       return "Alpha Assembly Printer";
@@ -68,8 +68,9 @@
 ///
 FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
                                                TargetMachine &tm,
-                                               bool fast, bool verbose) {
-  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                               unsigned OptLevel,
+                                               bool verbose) {
+  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 
 #include "AlphaGenAsmWriter.inc"

Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
+++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Tue Apr 28 19:15:41 2009
@@ -3587,7 +3587,7 @@
 bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
                                               raw_ostream &o,
                                               CodeGenFileType FileType,
-                                              bool Fast) {
+                                              unsigned OptLevel) {
   if (FileType != TargetMachine::AssemblyFile) return true;
 
   PM.add(createGCLoweringPass());

Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Tue Apr 28 19:15:41 2009
@@ -27,7 +27,8 @@
 
   virtual bool WantsWholeFile() const { return true; }
   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
-                                        CodeGenFileType FileType, bool Fast);
+                                        CodeGenFileType FileType,
+                                        unsigned OptLevel);
 
   // This class always works, but must be requested explicitly on 
   // llc command line.

Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Tue Apr 28 19:15:41 2009
@@ -48,9 +48,9 @@
   class VISIBILITY_HIDDEN SPUAsmPrinter : public AsmPrinter {
     std::set<std::string> FnStubs, GVStubs;
   public:
-    SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                  const TargetAsmInfo *T, bool F, bool V) :
-      AsmPrinter(O, TM, T, F, V) {}
+    explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                           const TargetAsmInfo *T, unsigned OL, bool V) :
+      AsmPrinter(O, TM, T, OL, V) {}
 
     virtual const char *getPassName() const {
       return "STI CBEA SPU Assembly Printer";
@@ -615,6 +615,6 @@
 ///
 FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
                                             SPUTargetMachine &tm,
-                                            bool fast, bool verbose) {
-  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                            unsigned OptLevel, bool verbose) {
+  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }

Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPU.h Tue Apr 28 19:15:41 2009
@@ -25,7 +25,7 @@
   FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
   FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
                                         SPUTargetMachine &tm,
-                                        bool fast, bool verbose);
+                                        unsigned OptLevel, bool verbose);
 
   /*--== Utility functions/predicates/etc used all over the place: --==*/
   //! Predicate test for a signed 10-bit value

Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Tue Apr 28 19:15:41 2009
@@ -81,15 +81,17 @@
 //===----------------------------------------------------------------------===//
 
 bool
-SPUTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast)
+SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel)
 {
   // Install an instruction selector.
   PM.add(createSPUISelDag(*this));
   return false;
 }
 
-bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
-                                          bool Verbose, raw_ostream &Out) {
-  PM.add(createSPUAsmPrinterPass(Out, *this, Fast, Verbose));
+bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                          unsigned OptLevel,
+                                          bool Verbose,
+                                          raw_ostream &Out) {
+  PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }

Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Tue Apr 28 19:15:41 2009
@@ -83,9 +83,9 @@
   }
   
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool /*Fast*/);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool /*Fast*/, 
-                                  bool /*Verbose*/, raw_ostream &Out);
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+                                  bool Verbose, raw_ostream &Out);
 };
 
 } // end namespace llvm

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Tue Apr 28 19:15:41 2009
@@ -1995,7 +1995,7 @@
 bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
                                                 raw_ostream &o,
                                                 CodeGenFileType FileType,
-                                                bool Fast) {
+                                                unsigned OptLevel) {
   if (FileType != TargetMachine::AssemblyFile) return true;
   PM.add(new CppWriter(o));
   return false;

Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Tue Apr 28 19:15:41 2009
@@ -29,7 +29,8 @@
 
   virtual bool WantsWholeFile() const { return true; }
   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
-                                        CodeGenFileType FileType, bool Fast);
+                                        CodeGenFileType FileType,
+                                        unsigned OptLevel);
 
   // This class always works, but shouldn't be the default in most cases.
   static unsigned getModuleMatchQuality(const Module &M) { return 1; }

Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Tue Apr 28 19:15:41 2009
@@ -37,9 +37,9 @@
   class IA64AsmPrinter : public AsmPrinter {
     std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
   public:
-    IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
-                   const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V) {}
+    explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
+                            const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V) {}
 
     virtual const char *getPassName() const {
       return "IA64 Assembly Printer";
@@ -370,6 +370,7 @@
 ///
 FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
                                               IA64TargetMachine &tm,
-                                              bool fast, bool verbose) {
-  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                              unsigned OptLevel,
+                                              bool verbose) {
+  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }

Modified: llvm/trunk/lib/Target/IA64/IA64.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64.h Tue Apr 28 19:15:41 2009
@@ -37,7 +37,7 @@
 ///
 FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
                                         IA64TargetMachine &tm,
-                                        bool fast, bool verbose);
+                                        unsigned OptLevel, bool verbose);
 
 } // End llvm namespace
 

Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Tue Apr 28 19:15:41 2009
@@ -72,19 +72,21 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLEvel){
   PM.add(createIA64DAGToDAGInstructionSelector(*this));
   return false;
 }
 
-bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
+bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
   // Make sure everything is bundled happily
   PM.add(createIA64BundlingPass(*this));
   return true;
 }
-bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
-                                           bool Verbose, raw_ostream &Out) {
-  PM.add(createIA64CodePrinterPass(Out, *this, Fast, Verbose));
+bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                           unsigned OptLevel,
+                                           bool Verbose,
+                                           raw_ostream &Out) {
+  PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }
 

Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64TargetMachine.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.h Tue Apr 28 19:15:41 2009
@@ -51,9 +51,9 @@
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                                   bool Verbose, raw_ostream &Out);
 };
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
+++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Tue Apr 28 19:15:41 2009
@@ -35,7 +35,8 @@
 
     virtual bool WantsWholeFile() const { return true; }
     virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
-                                         CodeGenFileType FileType, bool Fast);
+                                          CodeGenFileType FileType,
+                                          unsigned OptLevel);
 
     // This class always works, but shouldn't be the default in most cases.
     static unsigned getModuleMatchQuality(const Module &M) { return 1; }
@@ -1662,7 +1663,8 @@
 //===----------------------------------------------------------------------===//
 
 bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o,
-                                          CodeGenFileType FileType, bool Fast)
+                                          CodeGenFileType FileType,
+                                          unsigned OptLevel)
 {
   if (FileType != TargetMachine::AssemblyFile) return true;
   MSILWriter* Writer = new MSILWriter(o);

Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Tue Apr 28 19:15:41 2009
@@ -49,9 +49,9 @@
   class VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
     const MipsSubtarget *Subtarget;
   public:
-    MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM, 
-                   const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V) {
+    explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM, 
+                            const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V) {
       Subtarget = &TM.getSubtarget<MipsSubtarget>();
     }
 
@@ -91,8 +91,8 @@
 /// regardless of whether the function is in SSA form.
 FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
                                               MipsTargetMachine &tm,
-                                              bool fast, bool verbose) {
-  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                              unsigned OptLevel, bool verbose) {
+  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/Mips/Mips.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.h (original)
+++ llvm/trunk/lib/Target/Mips/Mips.h Tue Apr 28 19:15:41 2009
@@ -25,7 +25,7 @@
   FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
   FunctionPass *createMipsCodePrinterPass(raw_ostream &OS, 
                                           MipsTargetMachine &TM,
-                                          bool Fast, bool Verbose);
+                                          unsigned OptLevel, bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for Mips registers.  This defines a mapping from

Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Tue Apr 28 19:15:41 2009
@@ -105,7 +105,7 @@
 // Install an instruction selector pass using 
 // the ISelDag to gen Mips code.
 bool MipsTargetMachine::
-addInstSelector(PassManagerBase &PM, bool Fast) 
+addInstSelector(PassManagerBase &PM, unsigned OptLevel) 
 {
   PM.add(createMipsISelDag(*this));
   return false;
@@ -115,7 +115,7 @@
 // machine code is emitted. return true if -print-machineinstrs should 
 // print out the code after the passes.
 bool MipsTargetMachine::
-addPreEmitPass(PassManagerBase &PM, bool Fast) 
+addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) 
 {
   PM.add(createMipsDelaySlotFillerPass(*this));
   return true;
@@ -124,10 +124,10 @@
 // Implements the AssemblyEmitter for the target. Must return
 // true if AssemblyEmitter is supported
 bool MipsTargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                    bool Verbose, raw_ostream &Out) 
 {
   // Output assembly language.
-  PM.add(createMipsCodePrinterPass(Out, *this, Fast, Verbose));
+  PM.add(createMipsCodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }

Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Tue Apr 28 19:15:41 2009
@@ -57,9 +57,9 @@
     static unsigned getModuleMatchQuality(const Module &M);
 
     // Pass Pipeline Configuration
-    virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-    virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
-    virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+    virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+    virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
+    virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
                                     bool Verbose, raw_ostream &Out);
   };
 

Modified: llvm/trunk/lib/Target/PIC16/PIC16.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16.h Tue Apr 28 19:15:41 2009
@@ -75,7 +75,7 @@
   FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
   FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS, 
                                            PIC16TargetMachine &TM,
-                                           bool Fast, bool Verbose);
+                                           unsigned OptLevel, bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for PIC16 registers.  This defines a mapping from

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Tue Apr 28 19:15:41 2009
@@ -161,8 +161,9 @@
 ///
 FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
                                                PIC16TargetMachine &tm,
-                                               bool fast, bool verbose) {
-  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                               unsigned OptLevel,
+                                               bool verbose) {
+  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 
 void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Tue Apr 28 19:15:41 2009
@@ -24,9 +24,9 @@
 
 namespace llvm {
   struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
-  PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
-                    const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V) {
+    explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
+                             const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V) {
       CurBank = "";
       FunctionLabelBegin = '@';
       IsRomData = false;

Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Tue Apr 28 19:15:41 2009
@@ -55,17 +55,18 @@
   return new PIC16TargetAsmInfo(*this);
 }
 
-bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
+                                         unsigned OptLevel) {
   // Install an instruction selector.
   PM.add(createPIC16ISelDag(*this));
   return false;
 }
 
 bool PIC16TargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, bool Fast, bool Verbose,
+addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose,
                    raw_ostream &Out) {
   // Output assembly language.
-  PM.add(createPIC16CodePrinterPass(Out, *this, Fast, Verbose));
+  PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }
 

Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h Tue Apr 28 19:15:41 2009
@@ -57,8 +57,8 @@
     return const_cast<PIC16TargetLowering*>(&TLInfo); 
   }
 
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
                                   bool Verbose, raw_ostream &Out);
 }; // PIC16TargetMachine.
 

Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Tue Apr 28 19:15:41 2009
@@ -54,9 +54,9 @@
     StringSet<> FnStubs, GVStubs, HiddenGVStubs;
     const PPCSubtarget &Subtarget;
   public:
-    PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                  const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V),
+    explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                           const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V),
         Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
 
     virtual const char *getPassName() const {
@@ -297,9 +297,9 @@
     DwarfWriter *DW;
     MachineModuleInfo *MMI;
   public:
-    PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
-                       const TargetAsmInfo *T, bool F, bool V)
-      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
+    explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
+                                const TargetAsmInfo *T, unsigned OL, bool V)
+      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
 
     virtual const char *getPassName() const {
       return "Linux PPC Assembly Printer";
@@ -326,9 +326,9 @@
     MachineModuleInfo *MMI;
     raw_ostream &OS;
   public:
-    PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
-                        const TargetAsmInfo *T, bool F, bool V)
-      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0), OS(O) {}
+    explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
+                                 const TargetAsmInfo *T, unsigned OL, bool V)
+      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
 
     virtual const char *getPassName() const {
       return "Darwin PPC Assembly Printer";
@@ -1176,13 +1176,15 @@
 ///
 FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
                                             PPCTargetMachine &tm,
-                                            bool fast, bool verbose) {
+                                            unsigned OptLevel, bool verbose) {
   const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
 
   if (Subtarget->isDarwin()) {
-    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
+                                   OptLevel, verbose);
   } else {
-    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
+                                  OptLevel, verbose);
   }
 }
 

Modified: llvm/trunk/lib/Target/PowerPC/PPC.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPC.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPC.h Tue Apr 28 19:15:41 2009
@@ -28,7 +28,7 @@
 FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
 FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
                                       PPCTargetMachine &TM,
-                                      bool Fast, bool Verbose);
+                                      unsigned OptLevel, bool Verbose);
 FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
                                        MachineCodeEmitter &MCE);
 } // end namespace llvm;

Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Tue Apr 28 19:15:41 2009
@@ -129,29 +129,31 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
   // Install an instruction selector.
   PM.add(createPPCISelDag(*this));
   return false;
 }
 
-bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
+bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
   
   // Must run branch selection immediately preceding the asm printer.
   PM.add(createPPCBranchSelectionPass());
   return false;
 }
 
-bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
-                                          bool Verbose, raw_ostream &Out) {
+bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                          unsigned OptLevel,
+                                          bool Verbose,
+                                          raw_ostream &Out) {
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
   if (AsmPrinterCtor)
-    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
+    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
 
   return false;
 }
 
-bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
+bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
   // FIXME: This should be moved to TargetJITInfo!!
@@ -176,20 +178,20 @@
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
   }
 
   return false;
 }
 
-bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                             bool DumpAsm, MachineCodeEmitter &MCE) {
   // Machine code emitter pass for PowerPC.
   PM.add(createPPCCodeEmitterPass(*this, MCE));
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
   }
 
   return false;

Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Tue Apr 28 19:15:41 2009
@@ -46,7 +46,7 @@
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             PPCTargetMachine &tm, 
-                                            bool fast, bool verbose);
+                                            unsigned OptLevel, bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -76,13 +76,13 @@
   }
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
   virtual bool getEnableTailMergeDefault() const;
 };

Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp Tue Apr 28 19:15:41 2009
@@ -48,9 +48,9 @@
     typedef std::map<const Value *, unsigned> ValueMapTy;
     ValueMapTy NumberForBB;
   public:
-    SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                    const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V) {}
+    explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                             const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V) {}
 
     virtual const char *getPassName() const {
       return "Sparc Assembly Printer";
@@ -82,8 +82,9 @@
 ///
 FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
                                                TargetMachine &tm,
-                                               bool fast, bool verbose) {
-  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                               unsigned OptLevel,
+                                               bool verbose) {
+  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 
 /// runOnMachineFunction - This uses the printInstruction()

Modified: llvm/trunk/lib/Target/Sparc/Sparc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/Sparc.h (original)
+++ llvm/trunk/lib/Target/Sparc/Sparc.h Tue Apr 28 19:15:41 2009
@@ -25,7 +25,7 @@
 
   FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
   FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM,
-                                           bool Fast, bool Verbose);
+                                           unsigned OptLevel, bool Verbose);
   FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
   FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
 } // end namespace llvm;

Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Tue Apr 28 19:15:41 2009
@@ -68,7 +68,8 @@
 #endif
 }
 
-bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
+                                         unsigned OptLevel) {
   PM.add(createSparcISelDag(*this));
   return false;
 }
@@ -76,15 +77,17 @@
 /// addPreEmitPass - This pass may be implemented by targets that want to run
 /// passes immediately before machine code is emitted.  This should return
 /// true if -print-machineinstrs should print out the code after the passes.
-bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
+bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel){
   PM.add(createSparcFPMoverPass(*this));
   PM.add(createSparcDelaySlotFillerPass(*this));
   return true;
 }
 
-bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
-                                            bool Verbose, raw_ostream &Out) {
+bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                            unsigned OptLevel,
+                                            bool Verbose,
+                                            raw_ostream &Out) {
   // Output assembly language.
-  PM.add(createSparcCodePrinterPass(Out, *this, Fast, Verbose));
+  PM.add(createSparcCodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }

Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Tue Apr 28 19:15:41 2009
@@ -51,9 +51,9 @@
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                                   bool Verbose, raw_ostream &Out);
 };
 

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Tue Apr 28 19:15:41 2009
@@ -33,9 +33,9 @@
   MachineModuleInfo *MMI;
   const X86Subtarget *Subtarget;
  public:
-  X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
-                   const TargetAsmInfo *T, bool F, bool V)
-    : AsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {
+  explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
+                            const TargetAsmInfo *T, unsigned OL, bool V)
+    : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
     Subtarget = &TM.getSubtarget<X86Subtarget>();
   }
 

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Tue Apr 28 19:15:41 2009
@@ -25,13 +25,15 @@
 ///
 FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
                                              X86TargetMachine &tm,
-                                             bool fast, bool verbose) {
+                                             unsigned OptLevel, bool verbose) {
   const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
 
   if (Subtarget->isFlavorIntel()) {
-    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(),
+                                  OptLevel, verbose);
   } else {
-    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(),
+                                OptLevel, verbose);
   }
 }
 

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h Tue Apr 28 19:15:41 2009
@@ -25,9 +25,9 @@
 namespace llvm {
 
 struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
-  X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
-                     const TargetAsmInfo *T, bool F, bool V)
-    : AsmPrinter(O, TM, T, F, V) {}
+  explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
+                              const TargetAsmInfo *T, unsigned OL, bool V)
+    : AsmPrinter(O, TM, T, OL, V) {}
 
   virtual const char *getPassName() const {
     return "X86 Intel-Style Assembly Printer";

Modified: llvm/trunk/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86.h (original)
+++ llvm/trunk/lib/Target/X86/X86.h Tue Apr 28 19:15:41 2009
@@ -25,7 +25,7 @@
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *createX86ISelDag(X86TargetMachine &TM, bool Fast);
+FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned OptSize);
 
 /// createX86FloatingPointStackifierPass - This function returns a pass which
 /// converts floating point register references and pseudo instructions into
@@ -44,7 +44,7 @@
 ///
 FunctionPass *createX86CodePrinterPass(raw_ostream &o,
                                        X86TargetMachine &tm,
-                                       bool fast, bool Verbose);
+                                       unsigned OptLevel, bool Verbose);
 
 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
 /// to the specified MCE object.

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Apr 28 19:15:41 2009
@@ -134,8 +134,8 @@
     bool OptForSize;
 
   public:
-    X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
-      : SelectionDAGISel(tm, fast),
+    explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
+      : SelectionDAGISel(tm, OptLevel),
         TM(tm), X86Lowering(*TM.getTargetLowering()),
         Subtarget(&TM.getSubtarget<X86Subtarget>()),
         OptForSize(false) {}
@@ -306,7 +306,7 @@
 
 bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
                                                  SDNode *Root) const {
-  if (Fast) return false;
+  if (OptLevel == 0) return false;
 
   if (U == Root)
     switch (U->getOpcode()) {
@@ -512,7 +512,7 @@
 
 
 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
-/// This is only run if not in -fast mode (aka -O0).
+/// This is only run if not in -O0 mode.
 /// This allows the instruction selector to pick more read-modify-write
 /// instructions. This is a common case:
 ///
@@ -714,10 +714,10 @@
   OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
 
   DEBUG(BB->dump());
-  if (!Fast)
+  if (OptLevel != 0)
     PreprocessForRMW();
 
-  // FIXME: This should only happen when not -fast.
+  // FIXME: This should only happen when not compiled with -O0.
   PreprocessForFPConvert();
 
   // Codegen the basic block.
@@ -1744,6 +1744,6 @@
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
-  return new X86DAGToDAGISel(TM, Fast);
+FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned OptLevel) {
+  return new X86DAGToDAGISel(TM, OptLevel);
 }

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Tue Apr 28 19:15:41 2009
@@ -180,9 +180,9 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool X86TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
   // Install an instruction selector.
-  PM.add(createX86ISelDag(*this, Fast));
+  PM.add(createX86ISelDag(*this, OptLevel));
 
   // If we're using Fast-ISel, clean up the mess.
   if (EnableFastISel)
@@ -194,27 +194,29 @@
   return false;
 }
 
-bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, bool Fast) {
+bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
   // Calculate and set max stack object alignment early, so we can decide
   // whether we will need stack realignment (and thus FP).
   PM.add(createX86MaxStackAlignmentCalculatorPass());
   return false;  // -print-machineinstr shouldn't print after this.
 }
 
-bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, bool Fast) {
+bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
   PM.add(createX86FloatingPointStackifierPass());
   return true;  // -print-machineinstr should print after this.
 }
 
-bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
-                                          bool Verbose, raw_ostream &Out) {
+bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                          unsigned OptLevel,
+                                          bool Verbose,
+                                          raw_ostream &Out) {
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
   if (AsmPrinterCtor)
-    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
+    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
   return false;
 }
 
-bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
+bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // FIXME: Move this to TargetJITInfo!
   // On Darwin, do not override 64-bit setting made in X86TargetMachine().
@@ -236,19 +238,20 @@
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
   }
 
   return false;
 }
 
-bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
-                                        bool DumpAsm, MachineCodeEmitter &MCE) {
+bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+                                            unsigned OptLevel, bool DumpAsm,
+                                            MachineCodeEmitter &MCE) {
   PM.add(createX86CodeEmitterPass(*this, MCE));
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
+      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
   }
 
   return false;

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Tue Apr 28 19:15:41 2009
@@ -45,7 +45,7 @@
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             X86TargetMachine &tm,
-                                            bool fast, bool verbose);
+                                            unsigned OptLevel, bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -74,14 +74,14 @@
   }
 
   // Set up the pass pipeline.
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addPreRegAlloc(PassManagerBase &PM, bool Fast);
-  virtual bool addPostRegAlloc(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
 
   /// symbolicAddressesAreRIPRel - Return true if symbolic addresses are

Modified: llvm/trunk/lib/Target/XCore/XCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCore.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCore.h (original)
+++ llvm/trunk/lib/Target/XCore/XCore.h Tue Apr 28 19:15:41 2009
@@ -24,7 +24,7 @@
   FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
   FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
                                            XCoreTargetMachine &TM,
-                                           bool Fast, bool Verbose);
+                                           unsigned OptLevel, bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for XCore registers.  This defines a mapping from

Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Tue Apr 28 19:15:41 2009
@@ -58,8 +58,8 @@
     const XCoreSubtarget &Subtarget;
   public:
     XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
-                    const TargetAsmInfo *T, bool F, bool V)
-      : AsmPrinter(O, TM, T, F, V), DW(0),
+                    const TargetAsmInfo *T, unsigned OL, bool V)
+      : AsmPrinter(O, TM, T, OL, V), DW(0),
         Subtarget(*TM.getSubtargetImpl()) {}
 
     virtual const char *getPassName() const {
@@ -105,8 +105,9 @@
 ///
 FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
                                                XCoreTargetMachine &tm,
-                                               bool fast, bool verbose) {
-  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
+                                               unsigned OptLevel,
+                                               bool verbose) {
+  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 
 // PrintEscapedString - Print each character of the specified string, escaping

Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Tue Apr 28 19:15:41 2009
@@ -55,14 +55,17 @@
   return 0;
 }
 
-bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
+bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
+                                         unsigned OptLevel) {
   PM.add(createXCoreISelDag(*this));
   return false;
 }
 
-bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
-                                            bool Verbose, raw_ostream &Out) {
+bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                            unsigned OptLevel,
+                                            bool Verbose,
+                                            raw_ostream &Out) {
   // Output assembly language.
-  PM.add(createXCoreCodePrinterPass(Out, *this, Fast, Verbose));
+  PM.add(createXCoreCodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }

Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Tue Apr 28 19:15:41 2009
@@ -52,8 +52,8 @@
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
                                   bool Verbose, raw_ostream &Out);
 };
 

Modified: llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll Tue Apr 28 19:15:41 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast
+; RUN: llvm-as < %s | llc -O0
 
 define float @test(i32 %tmp12771278) {
         switch i32 %tmp12771278, label %bb1279 [

Modified: llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll Tue Apr 28 19:15:41 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast
+; RUN: llvm-as < %s | llc -O0
 	
 %struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32 }
 @cl_pf_opts = external global %struct.cl_perfunc_opts		; <%struct.cl_perfunc_opts*> [#uses=2]

Modified: llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll Tue Apr 28 19:15:41 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast
+; RUN: llvm-as < %s | llc -O0
 ; PR 1323
 
 ; ModuleID = 'test.bc'

Modified: llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll Tue Apr 28 19:15:41 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -fast -relocation-model=pic -o -
+; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o -
 ; PR1638
 
 @.str242 = external constant [3 x i8]		; <[3 x i8]*> [#uses=1]

Modified: llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll Tue Apr 28 19:15:41 2009
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -fast -regalloc=local
+; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local
 
 	%struct.CGPoint = type { double, double }
 	%struct.NSArray = type { %struct.NSObject }

Modified: llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll Tue Apr 28 19:15:41 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -fast -fast-isel=false | grep mov | count 5
+; RUN: llvm-as < %s | llc -march=x86 -O0 -fast-isel=false | grep mov | count 5
 ; PR2343
 
 	%llvm.dbg.anchor.type = type { i32, i32 }

Modified: llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll Tue Apr 28 19:15:41 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0
 
 define fastcc void @optimize_bit_field() nounwind {
 bb4:

Modified: llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll Tue Apr 28 19:15:41 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast -regalloc=local | not grep sil
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil
 ; rdar://6787136
 
 	%struct.X = type { i8, [32 x i8] }

Modified: llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/add-with-overflow.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/add-with-overflow.ll (original)
+++ llvm/trunk/test/CodeGen/X86/add-with-overflow.ll Tue Apr 28 19:15:41 2009
@@ -1,7 +1,7 @@
 ; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 2
 ; RUN: llvm-as < %s | llc -march=x86 | grep {jb} | count 2
-; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jo} | count 2
-; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jb} | count 2
+; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jo} | count 2
+; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jb} | count 2
 
 @ok = internal constant [4 x i8] c"%d\0A\00"
 @no = internal constant [4 x i8] c"no\0A\00"

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll Tue Apr 28 19:15:41 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -fast
+; RUN: llvm-as < %s | llc -march=x86 -O0
 
 ; This file is for regression tests for cases where FastISel needs
 ; to gracefully bail out and let SelectionDAGISel take over.

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll Tue Apr 28 19:15:41 2009
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -fast | grep movslq
-; RUN: llvm-as < %s | llc -march=x86 -fast
+; RUN: llvm-as < %s | llc -march=x86-64 -O0 | grep movslq
+; RUN: llvm-as < %s | llc -march=x86 -O0
 ; PR3181
 
 ; GEP indices are interpreted as signed integers, so they

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll Tue Apr 28 19:15:41 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -fast | grep {sarl	\$80, %eax}
+; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {sarl	\$80, %eax}
 ; PR3242
 
 define i32 @foo(i32 %x) nounwind {

Modified: llvm/trunk/test/CodeGen/X86/pr1489.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr1489.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr1489.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr1489.ll Tue Apr 28 19:15:41 2009
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 1082126238 | count 3
-; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 3058016715 | count 1
+; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 1082126238 | count 3
+; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 3058016715 | count 1
 ;; magic constants are 3.999f and half of 3.999
 ; ModuleID = '1489.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"

Modified: llvm/trunk/test/CodeGen/X86/volatile.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/volatile.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/volatile.ll (original)
+++ llvm/trunk/test/CodeGen/X86/volatile.ll Tue Apr 28 19:15:41 2009
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 | grep movsd | count 5
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -fast | grep movsd | count 5
+; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -O0 | grep movsd | count 5
 
 @x = external global double
 

Modified: llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll (original)
+++ llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll Tue Apr 28 19:15:41 2009
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc
-; RUN: llvm-as < %s | llc -fast
+; RUN: llvm-as < %s | llc -O0
 	%llvm.dbg.anchor.type = type { i32, i32 }
 	%llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 }
 	%llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8* }

Modified: llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-30-Method.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/2009-01-30-Method.ll (original)
+++ llvm/trunk/test/DebugInfo/2009-01-30-Method.ll Tue Apr 28 19:15:41 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast | grep "\\"foo" | count 3
+; RUN: llvm-as < %s | llc -O0 | grep "\\"foo" | count 3
 ; 1 declaration, 1 definition and 1 pubnames entry.
 target triple = "i386-apple-darwin*"
 	%llvm.dbg.anchor.type = type { i32, i32 }

Modified: llvm/trunk/test/DebugInfo/deaddebuglabel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/deaddebuglabel.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/deaddebuglabel.ll (original)
+++ llvm/trunk/test/DebugInfo/deaddebuglabel.ll Tue Apr 28 19:15:41 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast | grep "label" | count 8
+; RUN: llvm-as < %s | llc -O0 | grep "label" | count 8
 ; PR2614
 ; XFAIL: *
 

Modified: llvm/trunk/test/DebugInfo/forwardDecl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/forwardDecl.ll?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/DebugInfo/forwardDecl.ll (original)
+++ llvm/trunk/test/DebugInfo/forwardDecl.ll Tue Apr 28 19:15:41 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast | %prcontext ST 1 | grep 0x1 | count 1
+; RUN: llvm-as < %s | llc -O0 | %prcontext ST 1 | grep 0x1 | count 1
 
 target triple = "i386-apple-darwin9.6"
 	%llvm.dbg.anchor.type = type { i32, i32 }

Modified: llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-06-StackTrace.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp Tue Apr 28 19:15:41 2009
@@ -1,7 +1,7 @@
 // This is a regression test on debug info to make sure that we can get a
 // meaningful stack trace from a C++ program.
 // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
-// RUN:    llc --disable-fp-elim -o %t.s -f -fast -relocation-model=pic
+// RUN:    llc --disable-fp-elim -o %t.s -f -O0 -relocation-model=pic
 // RUN: %compile_c %t.s -o %t.o
 // RUN: %link %t.o -o %t.exe
 // RUN: echo {break DeepStack::deepest\nrun 17\nwhere\n} > %t.in 

Modified: llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-30-Pubnames.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp (original)
+++ llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp Tue Apr 28 19:15:41 2009
@@ -1,7 +1,7 @@
 // This is a regression test on debug info to make sure that we can access 
 // qualified global names.
 // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
-// RUN:   llc --disable-fp-elim -o %t.s -f -fast
+// RUN:   llc --disable-fp-elim -o %t.s -f -O0
 // RUN: %compile_c %t.s -o %t.o
 // RUN: %link %t.o -o %t.exe
 // RUN: %llvmdsymutil %t.exe 

Modified: llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-04-21-DtorNames-dbg.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp (original)
+++ llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp Tue Apr 28 19:15:41 2009
@@ -1,4 +1,4 @@
-// RUN: %llvmgcc -c -g %s -o - | llc -fast -f -o %t.s
+// RUN: %llvmgcc -c -g %s -o - | llc -O0 -f -o %t.s
 // RUN: %compile_c %t.s -o %t.o
 // PR4025
 

Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Tue Apr 28 19:15:41 2009
@@ -55,8 +55,13 @@
 
 static cl::opt<bool> Force("f", cl::desc("Overwrite output files"));
 
-static cl::opt<bool> Fast("fast",
-      cl::desc("Generate code quickly, potentially sacrificing code quality"));
+// Determine optimization level. Level -O0 is equivalent to "fast" code gen.
+static cl::opt<unsigned>
+OptLevel("O",
+         cl::desc("Optimization level. Similar to llvm-gcc -O. (default: -O3)"),
+         cl::Prefix,
+         cl::ZeroOrMore,
+         cl::init(3));
 
 static cl::opt<std::string>
 TargetTriple("mtriple", cl::desc("Override target triple for module"));
@@ -257,7 +262,7 @@
       PM.add(createVerifierPass());
 
     // Ask the target to add backend passes as necessary.
-    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, Fast)) {
+    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OptLevel)) {
       std::cerr << argv[0] << ": target does not support generation of this"
                 << " file type!\n";
       if (Out != &outs()) delete Out;
@@ -283,7 +288,7 @@
     // Override default to generate verbose assembly.
     Target.setAsmVerbosityDefault(true);
 
-    switch (Target.addPassesToEmitFile(Passes, *Out, FileType, Fast)) {
+    switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OptLevel)) {
     default:
       assert(0 && "Invalid file model!");
       return 1;
@@ -304,7 +309,7 @@
       break;
     }
 
-    if (Target.addPassesToEmitFileFinish(Passes, MCE, Fast)) {
+    if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) {
       std::cerr << argv[0] << ": target does not support generation of this"
                 << " file type!\n";
       if (Out != &outs()) delete Out;

Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Tue Apr 28 19:15:41 2009
@@ -650,7 +650,7 @@
   O << "\";\n\n";
 
   O << "  if (TAI->doesSupportDebugInformation() &&\n"
-    << "      DW->ShouldEmitDwarfDebug() && !Fast) {\n"
+    << "      DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n"
     << "    DebugLoc CurDL = MI->getDebugLoc();\n\n"
     << "    if (!CurDL.isUnknown()) {\n"
     << "      static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n"

Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=70343&r1=70342&r2=70343&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Tue Apr 28 19:15:41 2009
@@ -465,7 +465,7 @@
       NumInputRootOps = N->getNumChildren();
 
       if (DisablePatternForFastISel(N, CGP))
-        emitCheck("!Fast");
+        emitCheck("OptLevel != 0");
 
       emitCheck(PredicateCheck);
     }




From isanbard at gmail.com  Tue Apr 28 19:15:55 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 00:15:55 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r70345 -
	/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Message-ID: <200904290015.n3T0Ft0a022885@zion.cs.uiuc.edu>

Author: void
Date: Tue Apr 28 19:15:55 2009
New Revision: 70345

URL: http://llvm.org/viewvc/llvm-project?rev=70345&view=rev
Log:
Pass in the value of "optimize" instead of just indicated if it's "fast" or
not. This coincides with the '-fast to -O#' change.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=70345&r1=70344&r2=70345&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Tue Apr 28 19:15:55 2009
@@ -591,7 +591,7 @@
     // Note, this also adds codegenerator level optimization passes.
     switch (TheTarget->addPassesToEmitFile(*PM, *AsmOutRawStream,
                                            TargetMachine::AssemblyFile,
-                                           /*FAST*/optimize == 0)) {
+                                           optimize)) {
     default:
     case FileModel::Error:
       cerr << "Error interfacing to target machine!\n";
@@ -600,7 +600,7 @@
       break;
     }
 
-    if (TheTarget->addPassesToEmitFileFinish(*PM, 0, /*Fast*/optimize == 0)) {
+    if (TheTarget->addPassesToEmitFileFinish(*PM, 0, optimize)) {
       cerr << "Error interfacing to target machine!\n";
       exit(1);
     }
@@ -737,7 +737,7 @@
       // Note, this also adds codegenerator level optimization passes.
       switch (TheTarget->addPassesToEmitFile(*PM, *AsmOutRawStream,
                                              TargetMachine::AssemblyFile,
-                                             /*FAST*/optimize == 0)) {
+                                             optimize)) {
       default:
       case FileModel::Error:
         cerr << "Error interfacing to target machine!\n";
@@ -746,7 +746,7 @@
         break;
       }
 
-      if (TheTarget->addPassesToEmitFileFinish(*PM, 0, /*Fast*/optimize == 0)) {
+      if (TheTarget->addPassesToEmitFileFinish(*PM, 0, optimize)) {
         cerr << "Error interfacing to target machine!\n";
         exit(1);
       }




From isanbard at gmail.com  Tue Apr 28 19:32:19 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 00:32:19 -0000
Subject: [llvm-commits] [llvm] r70347 - in /llvm/trunk:
 include/llvm-c/ExecutionEngine.h
 include/llvm/ExecutionEngine/ExecutionEngine.h
 lib/ExecutionEngine/ExecutionEngine.cpp
 lib/ExecutionEngine/ExecutionEngineBindings.cpp
 lib/ExecutionEngine/Interpreter/Interpreter.cpp
 lib/ExecutionEngine/Interpreter/Interpreter.h
 lib/ExecutionEngine/JIT/JIT.cpp lib/ExecutionEngine/JIT/JIT.h
 lib/ExecutionEngine/JIT/TargetSelect.cpp
Message-ID: <200904290032.n3T0WJCR023496@zion.cs.uiuc.edu>

Author: void
Date: Tue Apr 28 19:32:19 2009
New Revision: 70347

URL: http://llvm.org/viewvc/llvm-project?rev=70347&view=rev
Log:
The second part of the change from -fast to -O#. This changes the JIT to accept
an optimization level instead of a simple boolean telling it to generate code
"fast" or the other type of "fast".

Modified:
    llvm/trunk/include/llvm-c/ExecutionEngine.h
    llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h
    llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
    llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp
    llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp
    llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h
    llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp
    llvm/trunk/lib/ExecutionEngine/JIT/JIT.h
    llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp

Modified: llvm/trunk/include/llvm-c/ExecutionEngine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/ExecutionEngine.h?rev=70347&r1=70346&r2=70347&view=diff

==============================================================================
--- llvm/trunk/include/llvm-c/ExecutionEngine.h (original)
+++ llvm/trunk/include/llvm-c/ExecutionEngine.h Tue Apr 28 19:32:19 2009
@@ -62,7 +62,7 @@
 
 int LLVMCreateJITCompiler(LLVMExecutionEngineRef *OutJIT,
                           LLVMModuleProviderRef MP,
-                          int Fast,
+                          unsigned OptLevel,
                           char **OutError);
 
 void LLVMDisposeExecutionEngine(LLVMExecutionEngineRef EE);

Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h?rev=70347&r1=70346&r2=70347&view=diff

==============================================================================
--- llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h (original)
+++ llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Tue Apr 28 19:32:19 2009
@@ -84,7 +84,7 @@
   // libraries, the JIT and Interpreter set these functions to ctor pointers
   // at startup time if they are linked in.
   typedef ExecutionEngine *(*EECtorFn)(ModuleProvider*, std::string*,
-                                       bool Fast);
+                                       unsigned OptLevel);
   static EECtorFn JITCtor, InterpCtor;
 
   /// LazyFunctionCreator - If an unknown function is needed, this function
@@ -114,7 +114,7 @@
   static ExecutionEngine *create(ModuleProvider *MP,
                                  bool ForceInterpreter = false,
                                  std::string *ErrorStr = 0,
-                                 bool Fast = false);
+                                 unsigned OptLevel = 3);
   
   /// create - This is the factory method for creating an execution engine which
   /// is appropriate for the current machine.  This takes ownership of the
@@ -127,7 +127,7 @@
   static ExecutionEngine *createJIT(ModuleProvider *MP,
                                     std::string *ErrorStr = 0,
                                     JITMemoryManager *JMM = 0,
-                                    bool Fast = false);
+                                    unsigned OptLevel = 3);
   
   
   

Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp?rev=70347&r1=70346&r2=70347&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Tue Apr 28 19:32:19 2009
@@ -383,7 +383,7 @@
 ExecutionEngine *ExecutionEngine::create(ModuleProvider *MP,
                                          bool ForceInterpreter,
                                          std::string *ErrorStr,
-                                         bool Fast) {
+                                         unsigned OptLevel) {
   ExecutionEngine *EE = 0;
 
   // Make sure we can resolve symbols in the program as well. The zero arg
@@ -393,11 +393,11 @@
 
   // Unless the interpreter was explicitly selected, try making a JIT.
   if (!ForceInterpreter && JITCtor)
-    EE = JITCtor(MP, ErrorStr, Fast);
+    EE = JITCtor(MP, ErrorStr, OptLevel);
 
   // If we can't make a JIT, make an interpreter instead.
   if (EE == 0 && InterpCtor)
-    EE = InterpCtor(MP, ErrorStr, Fast);
+    EE = InterpCtor(MP, ErrorStr, OptLevel);
 
   return EE;
 }

Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp?rev=70347&r1=70346&r2=70347&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp Tue Apr 28 19:32:19 2009
@@ -114,11 +114,11 @@
 
 int LLVMCreateJITCompiler(LLVMExecutionEngineRef *OutJIT,
                           LLVMModuleProviderRef MP,
-                          int Fast,
+                          unsigned OptLevel,
                           char **OutError) {
   std::string Error;
   if (ExecutionEngine *JIT = ExecutionEngine::createJIT(unwrap(MP), &Error, 0,
-                                                        Fast != 0)) {
+                                                        OptLevel)) {
     *OutJIT = wrap(JIT);
     return 0;
   }

Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp?rev=70347&r1=70346&r2=70347&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp Tue Apr 28 19:32:19 2009
@@ -37,7 +37,7 @@
 /// create - Create a new interpreter object.  This can never fail.
 ///
 ExecutionEngine *Interpreter::create(ModuleProvider *MP, std::string* ErrStr,
-                                     bool Fast /*unused*/) {
+                                     unsigned OptLevel /*unused*/) {
   // Tell this ModuleProvide to materialize and release the module
   if (!MP->materializeModule(ErrStr))
     // We got an error, just return 0

Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h?rev=70347&r1=70346&r2=70347&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h (original)
+++ llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h Tue Apr 28 19:32:19 2009
@@ -108,7 +108,7 @@
   /// create - Create an interpreter ExecutionEngine. This can never fail.
   ///
   static ExecutionEngine *create(ModuleProvider *M, std::string *ErrorStr = 0,
-                                 bool Fast /*unused*/ = 0);
+                                 unsigned OptLevel /*unused*/ = 3);
 
   /// run - Start execution with the specified function and arguments.
   ///

Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp?rev=70347&r1=70346&r2=70347&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp Tue Apr 28 19:32:19 2009
@@ -196,8 +196,8 @@
 ExecutionEngine *ExecutionEngine::createJIT(ModuleProvider *MP,
                                             std::string *ErrorStr,
                                             JITMemoryManager *JMM,
-                                            bool Fast) {
-  ExecutionEngine *EE = JIT::createJIT(MP, ErrorStr, JMM, Fast);
+                                            unsigned OptLevel) {
+  ExecutionEngine *EE = JIT::createJIT(MP, ErrorStr, JMM, OptLevel);
   if (!EE) return 0;
   
   // Make sure we can resolve symbols in the program as well. The zero arg
@@ -207,7 +207,7 @@
 }
 
 JIT::JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji,
-         JITMemoryManager *JMM, bool Fast)
+         JITMemoryManager *JMM, unsigned OptLevel)
   : ExecutionEngine(MP), TM(tm), TJI(tji) {
   setTargetData(TM.getTargetData());
 
@@ -223,7 +223,7 @@
 
   // Turn the machine code intermediate representation into bytes in memory that
   // may be executed.
-  if (TM.addPassesToEmitMachineCode(PM, *MCE, Fast)) {
+  if (TM.addPassesToEmitMachineCode(PM, *MCE, OptLevel)) {
     cerr << "Target does not support machine code emission!\n";
     abort();
   }
@@ -272,7 +272,7 @@
 
     // Turn the machine code intermediate representation into bytes in memory
     // that may be executed.
-    if (TM.addPassesToEmitMachineCode(PM, *MCE, false /*fast*/)) {
+    if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
       cerr << "Target does not support machine code emission!\n";
       abort();
     }
@@ -305,7 +305,7 @@
     
     // Turn the machine code intermediate representation into bytes in memory
     // that may be executed.
-    if (TM.addPassesToEmitMachineCode(PM, *MCE, false /*fast*/)) {
+    if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
       cerr << "Target does not support machine code emission!\n";
       abort();
     }
@@ -337,7 +337,7 @@
     
     // Turn the machine code intermediate representation into bytes in memory
     // that may be executed.
-    if (TM.addPassesToEmitMachineCode(PM, *MCE, false /*fast*/)) {
+    if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
       cerr << "Target does not support machine code emission!\n";
       abort();
     }

Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.h?rev=70347&r1=70346&r2=70347&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JIT.h (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.h Tue Apr 28 19:32:19 2009
@@ -55,7 +55,7 @@
   JITState *jitstate;
 
   JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji, 
-      JITMemoryManager *JMM, bool Fast);
+      JITMemoryManager *JMM, unsigned OptLevel);
 public:
   ~JIT();
 
@@ -71,8 +71,8 @@
   /// for the current target.  Otherwise, return null.
   ///
   static ExecutionEngine *create(ModuleProvider *MP, std::string *Err,
-                                 bool Fast = false) {
-    return createJIT(MP, Err, 0, Fast);
+                                 unsigned OptLevel = 3) {
+    return createJIT(MP, Err, 0, OptLevel);
   }
 
   virtual void addModuleProvider(ModuleProvider *MP);
@@ -148,7 +148,7 @@
   MachineCodeEmitter *getCodeEmitter() const { return MCE; }
   
   static ExecutionEngine *createJIT(ModuleProvider *MP, std::string *Err,
-                                    JITMemoryManager *JMM, bool Fast);
+                                    JITMemoryManager *JMM, unsigned OptLevel);
   
 private:
   static MachineCodeEmitter *createEmitter(JIT &J, JITMemoryManager *JMM);

Modified: llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp?rev=70347&r1=70346&r2=70347&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp Tue Apr 28 19:32:19 2009
@@ -42,7 +42,7 @@
 /// available for the current target.  Otherwise, return null.
 ///
 ExecutionEngine *JIT::createJIT(ModuleProvider *MP, std::string *ErrorStr,
-                                JITMemoryManager *JMM, bool Fast) {
+                                JITMemoryManager *JMM, unsigned OptLevel) {
   const TargetMachineRegistry::entry *TheArch = MArch;
   if (TheArch == 0) {
     std::string Error;
@@ -74,7 +74,7 @@
 
   // If the target supports JIT code generation, return a new JIT now.
   if (TargetJITInfo *TJ = Target->getJITInfo())
-    return new JIT(MP, *Target, *TJ, JMM, Fast);
+    return new JIT(MP, *Target, *TJ, JMM, OptLevel);
 
   if (ErrorStr)
     *ErrorStr = "target does not support JIT code generation";




From evan.cheng at apple.com  Tue Apr 28 19:42:27 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Apr 2009 00:42:27 -0000
Subject: [llvm-commits] [llvm] r70351 -
	/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
Message-ID: <200904290042.n3T0gRDm023926@zion.cs.uiuc.edu>

Author: evancheng
Date: Tue Apr 28 19:42:27 2009
New Revision: 70351

URL: http://llvm.org/viewvc/llvm-project?rev=70351&view=rev
Log:
Determine allocation 'preference' with right register class. I haven't seen this changing codegen so no test case.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=70351&r1=70350&r2=70351&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Tue Apr 28 19:42:27 2009
@@ -799,8 +799,14 @@
           Reg = SrcReg;
         else if (vrm_->isAssignedReg(SrcReg))
           Reg = vrm_->getPhys(SrcReg);
-        if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
-          cur->preference = Reg;
+        if (Reg) {
+          if (SrcSubReg)
+            Reg = tri_->getSubReg(Reg, SrcSubReg);
+          if (DstSubReg)
+            Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
+          if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
+            cur->preference = Reg;
+        }
       }
     }
   }
@@ -1265,14 +1271,10 @@
   // If copy coalescer has assigned a "preferred" register, check if it's
   // available first.
   if (cur->preference) {
+    DOUT << "(preferred: " << tri_->getName(cur->preference) << ") ";
     if (prt_->isRegAvail(cur->preference) && 
-        RC->contains(cur->preference)) {
-      DOUT << "\t\tassigned the preferred register: "
-           << tri_->getName(cur->preference) << "\n";
+        RC->contains(cur->preference))
       return cur->preference;
-    } else
-      DOUT << "\t\tunable to assign the preferred register: "
-           << tri_->getName(cur->preference) << "\n";
   }
 
   if (!DowngradedRegs.empty()) {




From gohman at apple.com  Tue Apr 28 19:59:18 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 29 Apr 2009 00:59:18 -0000
Subject: [llvm-commits] [llvm] r70354 -
 /llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h
Message-ID: <200904290059.n3T0xQt6024452@zion.cs.uiuc.edu>

Author: djg
Date: Tue Apr 28 19:59:03 2009
New Revision: 70354

URL: http://llvm.org/viewvc/llvm-project?rev=70354&view=rev
Log:
Add some more doxygen comments to SCEVAddRec.

Modified:
    llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h

Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h?rev=70354&r1=70353&r2=70354&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h (original)
+++ llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h Tue Apr 28 19:59:03 2009
@@ -357,7 +357,10 @@
 
   //===--------------------------------------------------------------------===//
   /// SCEVAddRecExpr - This node represents a polynomial recurrence on the trip
-  /// count of the specified loop.
+  /// count of the specified loop.  This is the primary focus of the
+  /// ScalarEvolution framework; all the other SCEV subclasses are mostly just
+  /// supporting infrastructure to allow SCEVAddRecExpr expressions to be
+  /// created and analyzed.
   ///
   /// All operands of an AddRec are required to be loop invariant.
   ///




From gohman at apple.com  Tue Apr 28 20:54:53 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 29 Apr 2009 01:54:53 -0000
Subject: [llvm-commits] [llvm] r70357 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <200904290155.n3T1t14a026059@zion.cs.uiuc.edu>

Author: djg
Date: Tue Apr 28 20:54:20 2009
New Revision: 70357

URL: http://llvm.org/viewvc/llvm-project?rev=70357&view=rev
Log:
Update comments to reflect the current code.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=70357&r1=70356&r2=70357&view=diff

==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Apr 28 20:54:20 2009
@@ -717,8 +717,8 @@
       // that value once it has finished.
       SCEVHandle BECount = getBackedgeTakenCount(AR->getLoop());
       if (!isa<SCEVCouldNotCompute>(BECount)) {
-        // Compute the extent of AR and divide it by the step value. This is
-        // used to determine if it's safe to extend the stride value.
+        // Manually compute the final value for AR, checking for
+        // overflow at each step.
         SCEVHandle Start = AR->getStart();
         SCEVHandle Step = AR->getStepRecurrence(*this);
 
@@ -806,8 +806,8 @@
       // that value once it has finished.
       SCEVHandle BECount = getBackedgeTakenCount(AR->getLoop());
       if (!isa<SCEVCouldNotCompute>(BECount)) {
-        // Compute the extent of AR and divide it by the step value. This is
-        // used to determine if it's safe to extend the stride value.
+        // Manually compute the final value for AR, checking for
+        // overflow at each step.
         SCEVHandle Start = AR->getStart();
         SCEVHandle Step = AR->getStepRecurrence(*this);
 




From sabre at nondot.org  Tue Apr 28 22:45:21 2009
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 29 Apr 2009 03:45:21 -0000
Subject: [llvm-commits] [llvm] r70360 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/TargetLowering.cpp
 test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
Message-ID: <200904290345.n3T3jQ0C029279@zion.cs.uiuc.edu>

Author: lattner
Date: Tue Apr 28 22:45:07 2009
New Revision: 70360

URL: http://llvm.org/viewvc/llvm-project?rev=70360&view=rev
Log:
Disable the load-shrinking optimization from looking at
anything larger than 64-bits, avoiding a crash.  This should
really be fixed to use APInts, though type legalization happens
to help us out and we get good code on the attached testcase at
least.

This fixes rdar://6836460

Added:
    llvm/trunk/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=70360&r1=70359&r2=70360&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Apr 28 22:45:07 2009
@@ -1538,19 +1538,22 @@
           N0.getOperand(0).getNode()->hasOneUse() &&
           isa<ConstantSDNode>(N0.getOperand(1))) {
         LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
-        uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
         uint64_t bestMask = 0;
         unsigned bestWidth = 0, bestOffset = 0;
-        if (!Lod->isVolatile() && Lod->isUnindexed()) {
+        if (!Lod->isVolatile() && Lod->isUnindexed() &&
+            // FIXME: This uses getZExtValue() below so it only works on i64 and
+            // below.
+            N0.getValueType().getSizeInBits() <= 64) {
           unsigned origWidth = N0.getValueType().getSizeInBits();
           // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 
           // 8 bits, but have to be careful...
           if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
             origWidth = Lod->getMemoryVT().getSizeInBits();
+          uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
           for (unsigned width = origWidth / 2; width>=8; width /= 2) {
             uint64_t newMask = (1ULL << width) - 1;
             for (unsigned offset=0; offset<origWidth/width; offset++) {
-              if ((newMask & Mask)==Mask) {
+              if ((newMask & Mask) == Mask) {
                 if (!TD->isLittleEndian())
                   bestOffset = (origWidth/width - offset - 1) * (width/8);
                 else

Added: llvm/trunk/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll?rev=70360&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll (added)
+++ llvm/trunk/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll Tue Apr 28 22:45:07 2009
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llc
+; rdar://6836460
+
+define i32 @test(i128* %P) nounwind {
+entry:
+	%tmp48 = load i128* %P
+	%and49 = and i128 %tmp48, 18446744073709551616		; <i128> [#uses=1]
+	%tobool = icmp ne i128 %and49, 0		; <i1> [#uses=1]
+	br i1 %tobool, label %if.then50, label %if.end61
+
+if.then50:		; preds = %if.then20
+	ret i32 1241
+
+if.end61:		; preds = %if.then50, %if.then20, %entry
+	ret i32 123
+}




From sanjiv.gupta at microchip.com  Tue Apr 28 23:43:24 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Wed, 29 Apr 2009 04:43:24 -0000
Subject: [llvm-commits] [llvm] r70366 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGNodes.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/Target/PIC16/PIC16ISelLowering.cpp
Message-ID: <200904290443.n3T4hPCp031152@zion.cs.uiuc.edu>

Author: sgupta
Date: Tue Apr 28 23:43:24 2009
New Revision: 70366

URL: http://llvm.org/viewvc/llvm-project?rev=70366&view=rev
Log:
Add a public method called getAddressSpace() to the GlobalAddressSDNode.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=70366&r1=70365&r2=70366&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Apr 28 23:43:24 2009
@@ -1814,6 +1814,8 @@
 
   GlobalValue *getGlobal() const { return TheGlobal; }
   int64_t getOffset() const { return Offset; }
+  // Return the address space this GlobalAddress belongs to.
+  unsigned getAddressSpace() const;
 
   static bool classof(const GlobalAddressSDNode *) { return true; }
   static bool classof(const SDNode *N) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=70366&r1=70365&r2=70366&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Apr 28 23:43:24 2009
@@ -5649,6 +5649,13 @@
   DumpNodesr(errs(), this, 0, 0, once);
 }
 
+
+// getAddressSpace - Return the address space this GlobalAddress belongs to.
+unsigned GlobalAddressSDNode::getAddressSpace() const {
+  return getGlobal()->getType()->getAddressSpace();
+}
+
+
 const Type *ConstantPoolSDNode::getType() const {
   if (isMachineConstantPoolEntry())
     return Val.MachineCPVal->getType();

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=70366&r1=70365&r2=70366&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Tue Apr 28 23:43:24 2009
@@ -483,9 +483,8 @@
   // It is BUILD_PAIR((PIC16Lo TGA), (PIC16Hi TGA)) and Op is BUILD_PAIR
   SDValue TGA = Op.getOperand(0).getOperand(0);
   GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(TGA);
-  int AddrSpace = GSDN->getGlobal()->getType()->getAddressSpace();
 
-  if (AddrSpace == PIC16ISD::ROM_SPACE)
+  if (GSDN->getAddressSpace() == PIC16ISD::ROM_SPACE)
     return true;
 
   // Any other address space return it false




From natebegeman at mac.com  Wed Apr 29 00:20:52 2009
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 29 Apr 2009 05:20:52 -0000
Subject: [llvm-commits] [llvm] r70372 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 include/llvm/CodeGen/SelectionDAGNodes.h
 include/llvm/Target/TargetLowering.h
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
 lib/CodeGen/SelectionDAG/LegalizeTypes.h
 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
Message-ID: <200904290520.n3T5KrSx032280@zion.cs.uiuc.edu>

Author: sampo
Date: Wed Apr 29 00:20:52 2009
New Revision: 70372

URL: http://llvm.org/viewvc/llvm-project?rev=70372&view=rev
Log:
Implement review feedback for vector shuffle work.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/include/llvm/Target/TargetLowering.h
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70372&r1=70371&r2=70372&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Apr 29 00:20:52 2009
@@ -356,7 +356,7 @@
   
   /// getVectorShuffle - Return an ISD::VECTOR_SHUFFLE node.  The number of
   /// elements in VT, which must be a vector type, must match the number of
-  /// mask elements NumElts.  A negative integer mask element is treated as
+  /// mask elements NumElts.  A integer mask element equal to -1 is treated as
   /// undefined.
   SDValue getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, SDValue N2, 
                            const int *MaskElts);
@@ -822,7 +822,7 @@
 
   /// getShuffleScalarElt - Returns the scalar element that will make up the ith
   /// element of the result of the vector shuffle.
-  SDValue getShuffleScalarElt(const SDNode *N, unsigned Idx);
+  SDValue getShuffleScalarElt(const ShuffleVectorSDNode *N, unsigned Idx);
 
 private:
   bool RemoveNodeFromCSEMaps(SDNode *N);

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=70372&r1=70371&r2=70372&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Apr 29 00:20:52 2009
@@ -1704,12 +1704,24 @@
   }
 };
 
+/// ShuffleVectorSDNode - This SDNode is used to implement the code generator
+/// support for the llvm IR shufflevector instruction.  It combines elements
+/// from two input vectors into a new input vector, with the selection and
+/// ordering of elements determined by an array of integers, referred to as
+/// the shuffle mask.  For input vectors of width N, mask indices of 0..N-1
+/// refer to elements from the LHS input, and indices from N to 2N-1 the RHS.
+/// An index of -1 is treated as undef, such that the code generator may put
+/// any value in the corresponding element of the result.
 class ShuffleVectorSDNode : public SDNode {
   SDUse Ops[2];
-  int *Mask;
+
+  // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
+  // is freed when the SelectionDAG object is destroyed.
+  const int *Mask;
 protected:
   friend class SelectionDAG;
-  ShuffleVectorSDNode(MVT VT, DebugLoc dl, SDValue N1, SDValue N2, int *M)
+  ShuffleVectorSDNode(MVT VT, DebugLoc dl, SDValue N1, SDValue N2, 
+                      const int *M)
     : SDNode(ISD::VECTOR_SHUFFLE, dl, getSDVTList(VT)), Mask(M) {
     InitOperands(Ops, N1, N2);
   }

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=70372&r1=70371&r2=70372&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Apr 29 00:20:52 2009
@@ -329,7 +329,8 @@
   /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
   /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
   /// are assumed to be legal.
-  virtual bool isShuffleMaskLegal(SmallVectorImpl<int> &Mask, MVT VT) const {
+  virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
+                                  MVT VT) const {
     return true;
   }
 
@@ -337,7 +338,8 @@
   /// used by Targets can use this to indicate if there is a suitable
   /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
   /// pool entry.
-  virtual bool isVectorClearMaskLegal(SmallVectorImpl<int> &M, MVT VT) const {
+  virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
+                                      MVT VT) const {
     return false;
   }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70372&r1=70371&r2=70372&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Apr 29 00:20:52 2009
@@ -5163,13 +5163,14 @@
     }
 
     LoadSDNode *LN0 = NULL;
+    const ShuffleVectorSDNode *SVN = NULL;
     if (ISD::isNormalLoad(InVec.getNode())) {
       LN0 = cast<LoadSDNode>(InVec);
     } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
                InVec.getOperand(0).getValueType() == EVT &&
                ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
       LN0 = cast<LoadSDNode>(InVec.getOperand(0));
-    } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
+    } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
       // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
       // =>
       // (load $addr+1*size)
@@ -5178,14 +5179,17 @@
       // to examine the mask.
       if (BCNumEltsChanged)
         return SDValue();
-      int Idx = cast<ShuffleVectorSDNode>(InVec)->getMaskElt(Elt);
-      int NumElems = InVec.getValueType().getVectorNumElements();
-      InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
+
+      // Select the input vector, guarding against out of range extract vector.
+      unsigned NumElems = VT.getVectorNumElements();
+      int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt);
+      InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
+
       if (InVec.getOpcode() == ISD::BIT_CONVERT)
         InVec = InVec.getOperand(0);
       if (ISD::isNormalLoad(InVec.getNode())) {
         LN0 = cast<LoadSDNode>(InVec);
-        Elt = (Idx < NumElems) ? Idx : Idx - NumElems;
+        Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems;
       }
     }
 
@@ -5280,7 +5284,11 @@
       SDValue Extract = N->getOperand(i);
       SDValue ExtVal = Extract.getOperand(1);
       if (Extract.getOperand(0) == VecIn1) {
-        Mask.push_back(cast<ConstantSDNode>(ExtVal)->getZExtValue());
+        unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
+        if (ExtIndex > VT.getVectorNumElements())
+          return SDValue();
+        
+        Mask.push_back(ExtIndex);
         continue;
       }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70372&r1=70371&r2=70372&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Apr 29 00:20:52 2009
@@ -267,10 +267,13 @@
                             bool isVolatile, SDValue ValOp,
                             unsigned StWidth, DebugLoc dl);
 
-  /// promoteShuffle - Promote a shuffle mask of a vector VT to perform the
-  /// same shuffle on a vector of NVT.  Must not create an illegal shuffle mask.
-  SDValue promoteShuffle(MVT NVT, MVT VT, DebugLoc dl, SDValue N1, SDValue N2, 
-                         SmallVectorImpl<int> &Mask) const;
+  /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
+  /// performs the same shuffe in terms of order or result bytes, but on a type
+  /// whose vector element type is narrower than the original shuffle type.
+  /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
+  SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
+                                     SDValue N1, SDValue N2, 
+                                     SmallVectorImpl<int> &Mask) const;
 
   bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
                                     SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
@@ -313,15 +316,17 @@
 };
 }
 
-/// promoteShuffle - Promote a shuffle mask of a vector VT to perform the
-/// same shuffle on a vector of NVT.  Must not create an illegal shuffle mask.
+/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
+/// performs the same shuffe in terms of order or result bytes, but on a type
+/// whose vector element type is narrower than the original shuffle type.
 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
-SDValue SelectionDAGLegalize::promoteShuffle(MVT NVT, MVT VT, DebugLoc dl, 
-                                             SDValue N1, SDValue N2,
+SDValue 
+SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT,  DebugLoc dl, 
+                                                 SDValue N1, SDValue N2,
                                              SmallVectorImpl<int> &Mask) const {
   MVT EltVT = NVT.getVectorElementType();
-  int NumMaskElts = VT.getVectorNumElements();
-  int NumDestElts = NVT.getVectorNumElements();
+  unsigned NumMaskElts = VT.getVectorNumElements();
+  unsigned NumDestElts = NVT.getVectorNumElements();
   unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
 
   assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
@@ -330,7 +335,7 @@
     return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
   
   SmallVector<int, 8> NewMask;
-  for (int i = 0; i != NumMaskElts; ++i) {
+  for (unsigned i = 0; i != NumMaskElts; ++i) {
     int Idx = Mask[i];
     for (unsigned j = 0; j != NumEltsGrowth; ++j) {
       if (Idx < 0) 
@@ -339,7 +344,7 @@
         NewMask.push_back(Idx * NumEltsGrowth + j);
     }
   }
-  assert((int)NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
+  assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
   assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
   return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
 }
@@ -1678,7 +1683,7 @@
     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
     MVT VT = Result.getValueType();
 
-    // Copy the Mask to a local SmallVector for use wi
+    // Copy the Mask to a local SmallVector for use with isShuffleMaskLegal.
     SmallVector<int, 8> Mask;
     cast<ShuffleVectorSDNode>(Result)->getMask(Mask);
 
@@ -1698,14 +1703,14 @@
       // FALLTHROUGH
     case TargetLowering::Expand: {
       MVT EltVT = VT.getVectorElementType();
-      int NumElems = VT.getVectorNumElements();
+      unsigned NumElems = VT.getVectorNumElements();
       SmallVector<SDValue, 8> Ops;
-      for (int i = 0; i != NumElems; ++i) {
+      for (unsigned i = 0; i != NumElems; ++i) {
         if (Mask[i] < 0) {
           Ops.push_back(DAG.getUNDEF(EltVT));
           continue;
         }
-        int Idx = Mask[i];
+        unsigned Idx = Mask[i];
         if (Idx < NumElems)
           Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
                                     DAG.getIntPtrConstant(Idx)));
@@ -1726,7 +1731,7 @@
       Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
 
       // Convert the shuffle mask to the right # elements.
-      Result = promoteShuffle(NVT, OVT, dl, Tmp1, Tmp2, Mask);
+      Result = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
       Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
       break;
     }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=70372&r1=70371&r2=70372&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed Apr 29 00:20:52 2009
@@ -559,7 +559,8 @@
   void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi);
-  void SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo, SDValue &Hi);
+  void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo, 
+                                  SDValue &Hi);
   void SplitVecRes_VSETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
 
   // Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
@@ -602,7 +603,7 @@
   SDValue WidenVecRes_SELECT(SDNode* N);
   SDValue WidenVecRes_SELECT_CC(SDNode* N);
   SDValue WidenVecRes_UNDEF(SDNode *N);
-  SDValue WidenVecRes_VECTOR_SHUFFLE(SDNode *N);
+  SDValue WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N);
   SDValue WidenVecRes_VSETCC(SDNode* N);
 
   SDValue WidenVecRes_Binary(SDNode *N);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=70372&r1=70371&r2=70372&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Wed Apr 29 00:20:52 2009
@@ -383,7 +383,8 @@
   case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
   case ISD::SCALAR_TO_VECTOR:  SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
   case ISD::LOAD:              SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
-  case ISD::VECTOR_SHUFFLE:    SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
+  case ISD::VECTOR_SHUFFLE:
+      SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); break;
   case ISD::VSETCC:            SplitVecRes_VSETCC(N, Lo, Hi); break;
 
   case ISD::CTTZ:
@@ -757,11 +758,10 @@
   Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
 }
 
-void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
-                                                  SDValue &Hi) {
+void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
+                                                  SDValue &Lo, SDValue &Hi) {
   // The low and high parts of the original input give four input vectors.
   SDValue Inputs[4];
-  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
   DebugLoc dl = N->getDebugLoc();
   GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
   GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
@@ -786,7 +786,7 @@
     bool useBuildVector = false;
     for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
       // The mask element.  This indexes into the input.
-      int Idx = SVN->getMaskElt(FirstMaskIdx + MaskOffset);
+      int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
 
       // The input vector this mask element indexes into.
       unsigned Input = (unsigned)Idx / NewElts;
@@ -831,7 +831,7 @@
       // Extract the input elements by hand.
       for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
         // The mask element.  This indexes into the input.
-        int Idx = SVN->getMaskElt(FirstMaskIdx + MaskOffset);
+        int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
 
         // The input vector this mask element indexes into.
         unsigned Input = (unsigned)Idx / NewElts;
@@ -1102,7 +1102,8 @@
   case ISD::SELECT:            Res = WidenVecRes_SELECT(N); break;
   case ISD::SELECT_CC:         Res = WidenVecRes_SELECT_CC(N); break;
   case ISD::UNDEF:             Res = WidenVecRes_UNDEF(N); break;
-  case ISD::VECTOR_SHUFFLE:    Res = WidenVecRes_VECTOR_SHUFFLE(N); break;
+  case ISD::VECTOR_SHUFFLE:    
+      Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); break;
   case ISD::VSETCC:            Res = WidenVecRes_VSETCC(N); break;
 
   case ISD::ADD:
@@ -1684,13 +1685,12 @@
  return DAG.getUNDEF(WidenVT);
 }
 
-SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(SDNode *N) {
-  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
+SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
   MVT VT = N->getValueType(0);
-  int NumElts = VT.getVectorNumElements();
   DebugLoc dl = N->getDebugLoc();
 
   MVT WidenVT = TLI.getTypeToTransformTo(VT);
+  unsigned NumElts = VT.getVectorNumElements();
   unsigned WidenNumElts = WidenVT.getVectorNumElements();
 
   SDValue InOp1 = GetWidenedVector(N->getOperand(0));
@@ -1698,14 +1698,14 @@
 
   // Adjust mask based on new input vector length.
   SmallVector<int, 16> NewMask;
-  for (int i = 0; i < NumElts; ++i) {
-    int Idx = SVN->getMaskElt(i);
-    if (Idx < NumElts)
+  for (unsigned i = 0; i != NumElts; ++i) {
+    int Idx = N->getMaskElt(i);
+    if (Idx < (int)NumElts)
       NewMask.push_back(Idx);
     else
       NewMask.push_back(Idx - NumElts + WidenNumElts);
   }
-  for (unsigned i = NumElts; i < WidenNumElts; ++i)
+  for (unsigned i = NumElts; i != WidenNumElts; ++i)
     NewMask.push_back(-1);
   return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=70372&r1=70371&r2=70372&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Apr 29 00:20:52 2009
@@ -1133,6 +1133,9 @@
   return SDValue(CondCodeNodes[Cond], 0);
 }
 
+// commuteShuffle - swaps the values of N1 and N2, and swaps all indices in
+// the shuffle mask M that point at N1 to point at N2, and indices that point
+// N2 to point at N1.
 static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) {
   std::swap(N1, N2);
   int NElts = M.size();
@@ -1158,21 +1161,18 @@
 
   // Validate that all indices in Mask are within the range of the elements 
   // input to the shuffle.
-  int NElts = VT.getVectorNumElements();
+  unsigned NElts = VT.getVectorNumElements();
   SmallVector<int, 8> MaskVec;
-  for (int i = 0; i != NElts; ++i) {
-    if (Mask[i] >= (NElts * 2)) {
-      assert(0 && "Index out of range");
-      return SDValue();
-    }
+  for (unsigned i = 0; i != NElts; ++i) {
+    assert(Mask[i] < (int)(NElts * 2) && "Index out of range");
     MaskVec.push_back(Mask[i]);
   }
   
   // Canonicalize shuffle v, v -> v, undef
   if (N1 == N2) {
     N2 = getUNDEF(VT);
-    for (int i = 0; i != NElts; ++i)
-      if (MaskVec[i] >= NElts) MaskVec[i] -= NElts;
+    for (unsigned i = 0; i != NElts; ++i)
+      if (MaskVec[i] >= (int)NElts) MaskVec[i] -= NElts;
   }
   
   // Canonicalize shuffle undef, v -> v, undef.  Commute the shuffle mask.
@@ -1183,8 +1183,8 @@
   // Canonicalize all index into rhs, -> shuffle rhs, undef
   bool AllLHS = true, AllRHS = true;
   bool N2Undef = N2.getOpcode() == ISD::UNDEF;
-  for (int i = 0; i != NElts; ++i) {
-    if (MaskVec[i] >= NElts) {
+  for (unsigned i = 0; i != NElts; ++i) {
+    if (MaskVec[i] >= (int)NElts) {
       if (N2Undef)
         MaskVec[i] = -1;
       else
@@ -1195,7 +1195,7 @@
   }
   if (AllLHS && AllRHS)
     return getUNDEF(VT);
-  if (AllLHS)
+  if (AllLHS && !N2Undef)
     N2 = getUNDEF(VT);
   if (AllRHS) {
     N1 = getUNDEF(VT);
@@ -1205,8 +1205,8 @@
   // If Identity shuffle, or all shuffle in to undef, return that node.
   bool AllUndef = true;
   bool Identity = true;
-  for (int i = 0; i < NElts; ++i) {
-    if (MaskVec[i] >= 0 && MaskVec[i] != i) Identity = false;
+  for (unsigned i = 0; i != NElts; ++i) {
+    if (MaskVec[i] >= 0 && MaskVec[i] != (int)i) Identity = false;
     if (MaskVec[i] >= 0) AllUndef = false;
   }
   if (Identity)
@@ -1217,7 +1217,7 @@
   FoldingSetNodeID ID;
   SDValue Ops[2] = { N1, N2 };
   AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2);
-  for (int i = 0; i != NElts; ++i)
+  for (unsigned i = 0; i != NElts; ++i)
     ID.AddInteger(MaskVec[i]);
   
   void* IP = 0;
@@ -2195,14 +2195,14 @@
 
 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
 /// element of the result of the vector shuffle.
-SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) {
+SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N,
+                                          unsigned i) {
   MVT VT = N->getValueType(0);
   DebugLoc dl = N->getDebugLoc();
-  const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
-  int Index = SVN->getMaskElt(i);
-  if (Index < 0)
+  if (N->getMaskElt(i) < 0)
     return getUNDEF(VT.getVectorElementType());
-  int NumElems = VT.getVectorNumElements();
+  unsigned Index = N->getMaskElt(i);
+  unsigned NumElems = VT.getVectorNumElements();
   SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
   Index %= NumElems;
 
@@ -2217,8 +2217,8 @@
                       : getUNDEF(VT.getVectorElementType());
   if (V.getOpcode() == ISD::BUILD_VECTOR)
     return V.getOperand(Index);
-  if (V.getOpcode() == ISD::VECTOR_SHUFFLE)
-    return getShuffleScalarElt(V.getNode(), Index);
+  if (const ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(V))
+    return getShuffleScalarElt(SVN, Index);
   return SDValue();
 }
 
@@ -5726,11 +5726,19 @@
 }
 
 bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) {
-  int Idx = -1;
-  for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
-    if (Idx < 0) Idx = Mask[i];
+  // Find the first non-undef value in the shuffle mask.
+  unsigned i, e;
+  for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i)
+    /* search */;
+
+  // If we hit the end of the mask looking for a non-undef value, return false.
+  if (i == e)
+    return false;
+  
+  // Make sure all remaining elements are either undef or the same as the first
+  // non-undef value.
+  for (int Idx = Mask[i]; i != e; ++i)
     if (Mask[i] >= 0 && Mask[i] != Idx)
       return false;
-  }
   return true;
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70372&r1=70371&r2=70372&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed Apr 29 00:20:52 2009
@@ -2431,10 +2431,10 @@
 
 // Utility for visitShuffleVector - Returns true if the mask is mask starting
 // from SIndx and increasing to the element length (undefs are allowed).
-static bool SequentialMask(SmallVectorImpl<int> &Mask, int SIndx) {
-  int MaskNumElts = Mask.size();
-  for (int i = 0; i != MaskNumElts; ++i)
-    if ((Mask[i] >= 0) && (Mask[i] != i + SIndx))
+static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
+  unsigned MaskNumElts = Mask.size();
+  for (unsigned i = 0; i != MaskNumElts; ++i)
+    if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
       return false;
   return true;
 }
@@ -2448,8 +2448,8 @@
   // representing undef values.
   SmallVector<Constant*, 8> MaskElts;
   cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
-  int MaskNumElts = MaskElts.size();
-  for (int i = 0; i != MaskNumElts; ++i) {
+  unsigned MaskNumElts = MaskElts.size();
+  for (unsigned i = 0; i != MaskNumElts; ++i) {
     if (isa<UndefValue>(MaskElts[i]))
       Mask.push_back(-1);
     else
@@ -2458,7 +2458,7 @@
   
   MVT VT = TLI.getValueType(I.getType());
   MVT SrcVT = Src1.getValueType();
-  int SrcNumElts = SrcVT.getVectorNumElements();
+  unsigned SrcNumElts = SrcVT.getVectorNumElements();
 
   if (SrcNumElts == MaskNumElts) {
     setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
@@ -2498,9 +2498,9 @@
 
     // Readjust mask for new input vector length.
     SmallVector<int, 8> MappedOps;
-    for (int i = 0; i != MaskNumElts; ++i) {
+    for (unsigned i = 0; i != MaskNumElts; ++i) {
       int Idx = Mask[i];
-      if (Idx < SrcNumElts)
+      if (Idx < (int)SrcNumElts)
         MappedOps.push_back(Idx);
       else
         MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
@@ -2511,32 +2511,19 @@
   }
 
   if (SrcNumElts > MaskNumElts) {
-    // Resulting vector is shorter than the incoming vector.
-    if (SrcNumElts == MaskNumElts && SequentialMask(Mask,0)) {
-      // Shuffle extracts 1st vector.
-      setValue(&I, Src1);
-      return;
-    }
-
-    if (SrcNumElts == MaskNumElts && SequentialMask(Mask,MaskNumElts)) {
-      // Shuffle extracts 2nd vector.
-      setValue(&I, Src2);
-      return;
-    }
-
     // Analyze the access pattern of the vector to see if we can extract
     // two subvectors and do the shuffle. The analysis is done by calculating
     // the range of elements the mask access on both vectors.
     int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
     int MaxRange[2] = {-1, -1};
 
-    for (int i = 0; i != MaskNumElts; ++i) {
+    for (unsigned i = 0; i != MaskNumElts; ++i) {
       int Idx = Mask[i];
       int Input = 0;
       if (Idx < 0)
         continue;
       
-      if (Idx >= SrcNumElts) {
+      if (Idx >= (int)SrcNumElts) {
         Input = 1;
         Idx -= SrcNumElts;
       }
@@ -2551,18 +2538,18 @@
     int RangeUse[2] = { 2, 2 };  // 0 = Unused, 1 = Extract, 2 = Can not Extract.
     int StartIdx[2];  // StartIdx to extract from
     for (int Input=0; Input < 2; ++Input) {
-      if (MinRange[Input] == SrcNumElts+1 && MaxRange[Input] == -1) {
+      if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
         RangeUse[Input] = 0; // Unused
         StartIdx[Input] = 0;
-      } else if (MaxRange[Input] - MinRange[Input] < MaskNumElts) {
+      } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
         // Fits within range but we should see if we can find a good
         // start index that is a multiple of the mask length.
-        if (MaxRange[Input] < MaskNumElts) {
+        if (MaxRange[Input] < (int)MaskNumElts) {
           RangeUse[Input] = 1; // Extract from beginning of the vector
           StartIdx[Input] = 0;
         } else {
           StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
-          if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
+          if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
               StartIdx[Input] + MaskNumElts < SrcNumElts)
             RangeUse[Input] = 1; // Extract from a multiple of the mask length.
         }
@@ -2586,11 +2573,11 @@
       }
       // Calculate new mask.
       SmallVector<int, 8> MappedOps;
-      for (int i = 0; i != MaskNumElts; ++i) {
+      for (unsigned i = 0; i != MaskNumElts; ++i) {
         int Idx = Mask[i];
         if (Idx < 0)
           MappedOps.push_back(Idx);
-        else if (Idx < SrcNumElts)
+        else if (Idx < (int)SrcNumElts)
           MappedOps.push_back(Idx - StartIdx[0]);
         else
           MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
@@ -2607,12 +2594,12 @@
   MVT EltVT = VT.getVectorElementType();
   MVT PtrVT = TLI.getPointerTy();
   SmallVector<SDValue,8> Ops;
-  for (int i = 0; i != MaskNumElts; ++i) {
+  for (unsigned i = 0; i != MaskNumElts; ++i) {
     if (Mask[i] < 0) {
       Ops.push_back(DAG.getUNDEF(EltVT));
     } else {
       int Idx = Mask[i];
-      if (Idx < SrcNumElts)
+      if (Idx < (int)SrcNumElts)
         Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
                                   EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
       else

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=70372&r1=70371&r2=70372&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Apr 29 00:20:52 2009
@@ -2154,7 +2154,7 @@
 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
 /// is suitable for input to PSHUFD or PSHUFW.  That is, it doesn't reference
 /// the second operand.
-static bool isPSHUFDMask(SmallVectorImpl<int> &Mask, MVT VT) {
+static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, MVT VT) {
   if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
     return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
   if (VT == MVT::v2f64 || VT == MVT::v2i64)
@@ -2170,7 +2170,7 @@
 
 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
 /// is suitable for input to PSHUFHW.
-static bool isPSHUFHWMask(SmallVectorImpl<int> &Mask, MVT VT) {
+static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
   if (VT != MVT::v8i16)
     return false;
   
@@ -2195,7 +2195,7 @@
 
 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
 /// is suitable for input to PSHUFLW.
-static bool isPSHUFLWMask(SmallVectorImpl<int> &Mask, MVT VT) {
+static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
   if (VT != MVT::v8i16)
     return false;
   
@@ -2220,7 +2220,7 @@
 
 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
-static bool isSHUFPMask(SmallVectorImpl<int> &Mask, MVT VT) {
+static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
   int NumElems = VT.getVectorNumElements();
   if (NumElems != 2 && NumElems != 4)
     return false;
@@ -2246,7 +2246,7 @@
 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
 /// half elements to come from vector 1 (which would equal the dest.) and
 /// the upper half to come from vector 2.
-static bool isCommutedSHUFPMask(SmallVectorImpl<int> &Mask, MVT VT) {
+static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
   int NumElems = VT.getVectorNumElements();
   
   if (NumElems != 2 && NumElems != 4) 
@@ -2337,7 +2337,7 @@
 
 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
-static bool isUNPCKLMask(SmallVectorImpl<int> &Mask, MVT VT,
+static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, MVT VT,
                          bool V2IsSplat = false) {
   int NumElts = VT.getVectorNumElements();
   if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
@@ -2367,7 +2367,7 @@
 
 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
-static bool isUNPCKHMask(SmallVectorImpl<int> &Mask, MVT VT, 
+static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, MVT VT, 
                          bool V2IsSplat = false) {
   int NumElts = VT.getVectorNumElements();
   if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
@@ -2398,7 +2398,7 @@
 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
 /// <0, 0, 1, 1>
-static bool isUNPCKL_v_undef_Mask(SmallVectorImpl<int> &Mask, MVT VT) {
+static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
   int NumElems = VT.getVectorNumElements();
   if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
     return false;
@@ -2423,7 +2423,7 @@
 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
 /// <2, 2, 3, 3>
-static bool isUNPCKH_v_undef_Mask(SmallVectorImpl<int> &Mask, MVT VT) {
+static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
   int NumElems = VT.getVectorNumElements();
   if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
     return false;
@@ -2448,7 +2448,7 @@
 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to MOVSS,
 /// MOVSD, and MOVD, i.e. setting the lowest element.
-static bool isMOVLMask(SmallVectorImpl<int> &Mask, MVT VT) {
+static bool isMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT) {
   int NumElts = VT.getVectorNumElements();
   if (NumElts != 2 && NumElts != 4)
     return false;
@@ -2472,7 +2472,7 @@
 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
 /// of what x86 movss want. X86 movs requires the lowest  element to be lowest
 /// element of vector 2 and the other elements to come from vector 1 in order.
-static bool isCommutedMOVLMask(SmallVectorImpl<int> &Mask, MVT VT,
+static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT,
                                bool V2IsSplat = false, bool V2IsUndef = false) {
   int NumOps = VT.getVectorNumElements();
   if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
@@ -2619,14 +2619,14 @@
 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
                                     SelectionDAG &DAG) {
   MVT VT = SVOp->getValueType(0);
-  int NumElems = VT.getVectorNumElements();
+  unsigned NumElems = VT.getVectorNumElements();
   SmallVector<int, 8> MaskVec;
   
-  for (int i = 0; i != NumElems; ++i) {
+  for (unsigned i = 0; i != NumElems; ++i) {
     int idx = SVOp->getMaskElt(i);
     if (idx < 0)
       MaskVec.push_back(idx);
-    else if (idx < NumElems)
+    else if (idx < (int)NumElems)
       MaskVec.push_back(idx + NumElems);
     else
       MaskVec.push_back(idx - NumElems);
@@ -2638,12 +2638,12 @@
 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
 /// the two vector operands have swapped position.
 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, MVT VT) {
-  int NumElems = VT.getVectorNumElements();
-  for (int i = 0; i != NumElems; ++i) {
+  unsigned NumElems = VT.getVectorNumElements();
+  for (unsigned i = 0; i != NumElems; ++i) {
     int idx = Mask[i];
     if (idx < 0)
       continue;
-    else if (idx < NumElems)
+    else if (idx < (int)NumElems)
       Mask[i] = idx + NumElems;
     else
       Mask[i] = idx - NumElems;
@@ -2694,14 +2694,14 @@
   if (ISD::isNON_EXTLoad(V2))
     return false;
 
-  int NumElems = Op->getValueType(0).getVectorNumElements();
+  unsigned NumElems = Op->getValueType(0).getVectorNumElements();
   
   if (NumElems != 2 && NumElems != 4)
     return false;
-  for (int i = 0, e = NumElems/2; i != e; ++i)
+  for (unsigned i = 0, e = NumElems/2; i != e; ++i)
     if (!isUndefOrEqual(Op->getMaskElt(i), i))
       return false;
-  for (int i = NumElems/2; i != NumElems; ++i)
+  for (unsigned i = NumElems/2; i != NumElems; ++i)
     if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
       return false;
   return true;
@@ -2731,14 +2731,14 @@
 
 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
 /// to an zero vector. 
-/// FIXME: move to dag combiner?
+/// FIXME: move to dag combiner / method on ShuffleVectorSDNode
 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
   SDValue V1 = N->getOperand(0);
   SDValue V2 = N->getOperand(1);
-  int NumElems = N->getValueType(0).getVectorNumElements();
-  for (int i = 0; i != NumElems; ++i) {
+  unsigned NumElems = N->getValueType(0).getVectorNumElements();
+  for (unsigned i = 0; i != NumElems; ++i) {
     int Idx = N->getMaskElt(i);
-    if (Idx >= NumElems) {
+    if (Idx >= (int)NumElems) {
       unsigned Opc = V2.getOpcode();
       if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
         continue;
@@ -2798,14 +2798,14 @@
 /// that point to V2 points to its first element.
 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
   MVT VT = SVOp->getValueType(0);
-  int NumElems = VT.getVectorNumElements();
+  unsigned NumElems = VT.getVectorNumElements();
   
   bool Changed = false;
   SmallVector<int, 8> MaskVec;
   SVOp->getMask(MaskVec);
   
-  for (int i = 0; i != NumElems; ++i) {
-    if (MaskVec[i] > NumElems) {
+  for (unsigned i = 0; i != NumElems; ++i) {
+    if (MaskVec[i] > (int)NumElems) {
       MaskVec[i] = NumElems;
       Changed = true;
     }
@@ -6917,7 +6917,8 @@
 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
 /// are assumed to be legal.
 bool
-X86TargetLowering::isShuffleMaskLegal(SmallVectorImpl<int> &M, MVT VT) const {
+X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 
+                                      MVT VT) const {
   // Only do shuffles on 128-bit vector types for now.
   if (VT.getSizeInBits() == 64)
     return false;
@@ -6937,7 +6938,7 @@
 }
 
 bool
-X86TargetLowering::isVectorClearMaskLegal(SmallVectorImpl<int> &Mask,
+X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
                                           MVT VT) const {
   unsigned NumElts = VT.getVectorNumElements();
   // FIXME: This collection of masks seems suspect.

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=70372&r1=70371&r2=70372&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Apr 29 00:20:52 2009
@@ -470,13 +470,15 @@
     /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
     /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
     /// values are assumed to be legal.
-    virtual bool isShuffleMaskLegal(SmallVectorImpl<int> &Mask, MVT VT) const;
+    virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
+                                    MVT VT) const;
 
     /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
     /// used by Targets can use this to indicate if there is a suitable
     /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
     /// pool entry.
-    virtual bool isVectorClearMaskLegal(SmallVectorImpl<int> &M, MVT VT) const;
+    virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
+                                        MVT VT) const;
 
     /// ShouldShrinkFPConstant - If true, then instruction selection should
     /// seek to shrink the FP constant of the specified type to a smaller type




From clattner at apple.com  Wed Apr 29 01:13:02 2009
From: clattner at apple.com (Chris Lattner)
Date: Tue, 28 Apr 2009 23:13:02 -0700
Subject: [llvm-commits] [llvm] r70372 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAG.h
	include/llvm/CodeGen/SelectionDAGNodes.h
	include/llvm/Target/TargetLowering.h
	lib/CodeGen/SelectionDAG/DAGCombiner.cpp
	lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	lib/CodeGen/SelectionDAG/LegalizeTypes.h
	lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
	lib/CodeGen/SelectionDAG/SelectionDAG.cpp
	lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
	lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
In-Reply-To: <200904290520.n3T5KrSx032280@zion.cs.uiuc.edu>
References: <200904290520.n3T5KrSx032280@zion.cs.uiuc.edu>
Message-ID: <5DD45716-3236-4DD1-98A3-857C71D1C61C@apple.com>

On Apr 28, 2009, at 10:20 PM, Nate Begeman wrote:
> URL: http://llvm.org/viewvc/llvm-project?rev=70372&view=rev
> Log:
> Implement review feedback for vector shuffle work.

Very nice!

> bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) {
> -  int Idx = -1;
> -  for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
> -    if (Idx < 0) Idx = Mask[i];
> +  // Find the first non-undef value in the shuffle mask.
> +  unsigned i, e;
> +  for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0;  
> ++i)
> +    /* search */;
> +
> +  // If we hit the end of the mask looking for a non-undef value,  
> return false.
> +  if (i == e)
> +    return false;

Is this even possible?  Since shuffle mask elements are immutable once  
a node is created, and the getShuffle method checks for this, I think  
this is impossible.  This can be an assert.

-Chris



From baldrick at free.fr  Wed Apr 29 01:22:45 2009
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 29 Apr 2009 08:22:45 +0200
Subject: [llvm-commits] [llvm] r70372 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAG.h
	include/llvm/CodeGen/SelectionDAGNodes.h
	include/llvm/Target/TargetLowering.h
	lib/CodeGen/SelectionDAG/DAGCombiner.cpp
	lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	lib/CodeGen/SelectionDAG/LegalizeTypes.h
	lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
	lib/CodeGen/SelectionDAG/SelectionDAG.cpp
	lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
	lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
In-Reply-To: <200904290520.n3T5KrSx032280@zion.cs.uiuc.edu>
References: <200904290520.n3T5KrSx032280@zion.cs.uiuc.edu>
Message-ID: <200904290822.46028.baldrick@free.fr>

Hi Nate, thanks for doing this.

> Implement review feedback for vector shuffle work.

    /// VECTOR_SHUFFLE(VEC1, VEC2, SHUFFLEVEC) - Returns a vector, of the same
    /// type as VEC1/VEC2.  SHUFFLEVEC is a BUILD_VECTOR of constant int values
    /// (maybe of an illegal datatype) or undef that indicate which value each
    /// result element will get.  The elements of VEC1/VEC2 are enumerated in
    /// order.  This is quite similar to the Altivec 'vperm' instruction, except
    /// that the indices must be constants and are in terms of the element size
    /// of VEC1/VEC2, not in terms of bytes.
    VECTOR_SHUFFLE,

This comment in SelectionDAGNodes.h wasn't updated.

Ciao,

Duncan.


From sabre at nondot.org  Wed Apr 29 01:46:32 2009
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 29 Apr 2009 06:46:32 -0000
Subject: [llvm-commits] [llvm] r70375 -
	/llvm/trunk/test/FrontendC/2009-04-28-UnionArrayCrash.c
Message-ID: <200904290646.n3T6kX2l002529@zion.cs.uiuc.edu>

Author: lattner
Date: Wed Apr 29 01:46:27 2009
New Revision: 70375

URL: http://llvm.org/viewvc/llvm-project?rev=70375&view=rev
Log:
testcase for PR4082

Added:
    llvm/trunk/test/FrontendC/2009-04-28-UnionArrayCrash.c

Added: llvm/trunk/test/FrontendC/2009-04-28-UnionArrayCrash.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2009-04-28-UnionArrayCrash.c?rev=70375&view=auto

==============================================================================
--- llvm/trunk/test/FrontendC/2009-04-28-UnionArrayCrash.c (added)
+++ llvm/trunk/test/FrontendC/2009-04-28-UnionArrayCrash.c Wed Apr 29 01:46:27 2009
@@ -0,0 +1,11 @@
+// RUN: %llvmgcc -S %s -o - 
+// PR4082
+union U {
+  int I;
+  double F;
+};
+
+union U arr[] = { { .I = 4 }, { .F = 123.} };
+union U *P = &arr[0];
+
+




From sabre at nondot.org  Wed Apr 29 01:47:08 2009
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 29 Apr 2009 06:47:08 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r70376 -
	/llvm-gcc-4.2/trunk/gcc/c-typeck.c
Message-ID: <200904290647.n3T6l8a6002559@zion.cs.uiuc.edu>

Author: lattner
Date: Wed Apr 29 01:47:07 2009
New Revision: 70376

URL: http://llvm.org/viewvc/llvm-project?rev=70376&view=rev
Log:
fit in 80 cols

Modified:
    llvm-gcc-4.2/trunk/gcc/c-typeck.c

Modified: llvm-gcc-4.2/trunk/gcc/c-typeck.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/c-typeck.c?rev=70376&r1=70375&r2=70376&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/c-typeck.c (original)
+++ llvm-gcc-4.2/trunk/gcc/c-typeck.c Wed Apr 29 01:47:07 2009
@@ -2130,8 +2130,8 @@
           ty = TYPE_MAIN_VARIANT (ty);
 
         ar = build4 (ARRAY_REF, ty, ar, index, NULL_TREE, NULL_TREE);
-        /* Mirror logic from build_indirect_ref to set TREE_THIS_VOLATILE and other
-         * flags.
+        /* Mirror logic from build_indirect_ref to set TREE_THIS_VOLATILE and
+         * other flags.
          */
         TREE_READONLY (ar) = TYPE_READONLY (TREE_TYPE (ar));
         TREE_THIS_VOLATILE(ar) = TYPE_VOLATILE(TREE_TYPE (ar));




From sabre at nondot.org  Wed Apr 29 01:47:25 2009
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 29 Apr 2009 06:47:25 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r70377 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <200904290647.n3T6lP3m002576@zion.cs.uiuc.edu>

Author: lattner
Date: Wed Apr 29 01:47:25 2009
New Revision: 70377

URL: http://llvm.org/viewvc/llvm-project?rev=70377&view=rev
Log:
Fix PR4082 and test/FrontendC/2009-04-28-UnionArrayCrash.c 

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=70377&r1=70376&r2=70377&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Apr 29 01:47:25 2009
@@ -7337,10 +7337,10 @@
   tree ArrayType = TREE_TYPE(Array);
   tree Index = TREE_OPERAND(exp, 1);
   tree IndexType = TREE_TYPE(Index);
-  assert((TREE_CODE (ArrayType) == ARRAY_TYPE ||
-          TREE_CODE (ArrayType) == POINTER_TYPE ||
-          TREE_CODE (ArrayType) == REFERENCE_TYPE ||
-          TREE_CODE (ArrayType) == BLOCK_POINTER_TYPE) &&
+  assert((TREE_CODE(ArrayType) == ARRAY_TYPE ||
+          TREE_CODE(ArrayType) == POINTER_TYPE ||
+          TREE_CODE(ArrayType) == REFERENCE_TYPE ||
+          TREE_CODE(ArrayType) == BLOCK_POINTER_TYPE) &&
          "Unknown ARRAY_REF!");
 
   // Check for variable sized reference.
@@ -7350,12 +7350,24 @@
   // As an LLVM extension, we allow ARRAY_REF with a pointer as the first
   // operand.  This construct maps directly to a getelementptr instruction.
   Constant *ArrayAddr;
-  if (TREE_CODE (ArrayType) == ARRAY_TYPE) {
+  if (TREE_CODE(ArrayType) == ARRAY_TYPE) {
     // First subtract the lower bound, if any, in the type of the index.
     tree LowerBound = array_ref_low_bound(exp);
     if (!integer_zerop(LowerBound))
       Index = fold(build2(MINUS_EXPR, IndexType, Index, LowerBound));
     ArrayAddr = EmitLV(Array);
+    
+    // The GCC array expression value may not compile to an LLVM array type if
+    // (for example) the array value is an array of unions.  In this case, the
+    // array literal will turn into an LLVM constant struct, which has struct
+    // type.  Do a cast to the correct type just to be certain everything is
+    // kosher.
+    const PointerType *ResPTy = cast<PointerType>(ArrayAddr->getType());
+    if (!isa<llvm::ArrayType>(ResPTy->getElementType())) {
+      const Type *RealArrayTy = ConvertType(ArrayType);
+      ResPTy = PointerType::getUnqual(RealArrayTy);
+      ArrayAddr = TheFolder->CreateBitCast(ArrayAddr, ResPTy);
+    }    
   } else {
     ArrayAddr = Convert(Array);
   }
@@ -7368,7 +7380,7 @@
                                         !TYPE_UNSIGNED(IndexType));
 
   std::vector<Value*> Idx;
-  if (TREE_CODE (ArrayType) == ARRAY_TYPE)
+  if (TREE_CODE(ArrayType) == ARRAY_TYPE)
     Idx.push_back(ConstantInt::get(IntPtrTy, 0));
   Idx.push_back(IndexVal);
 




From baldrick at free.fr  Wed Apr 29 01:58:43 2009
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 29 Apr 2009 08:58:43 +0200
Subject: [llvm-commits] [llvm-gcc-4.2] r70377 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
In-Reply-To: <200904290647.n3T6lP3m002576@zion.cs.uiuc.edu>
References: <200904290647.n3T6lP3m002576@zion.cs.uiuc.edu>
Message-ID: <200904290858.43761.baldrick@free.fr>

Hi Chris,

> +    // The GCC array expression value may not compile to an LLVM array type if
> +    // (for example) the array value is an array of unions.  In this case, the
> +    // array literal will turn into an LLVM constant struct, which has struct
> +    // type.  Do a cast to the correct type just to be certain everything is
> +    // kosher.

I think it would be better to require EmitLV to always return a pointer
of the right type.  This means that the bitcast should be somewhere else.
I will take care of this once things calm down here :)

Ciao,

Duncan.


From evan.cheng at apple.com  Wed Apr 29 02:16:34 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Apr 2009 07:16:34 -0000
Subject: [llvm-commits] [llvm] r70378 - in /llvm/trunk:
 lib/CodeGen/RegAllocLinearScan.cpp
 test/CodeGen/X86/2009-04-29-LinearScanBug.ll
Message-ID: <200904290716.n3T7GYRR003963@zion.cs.uiuc.edu>

Author: evancheng
Date: Wed Apr 29 02:16:34 2009
New Revision: 70378

URL: http://llvm.org/viewvc/llvm-project?rev=70378&view=rev
Log:
spillPhysRegAroundRegDefsUses() may have invalidated iterators stored in fixed_ IntervalPtrs. Reset them.

Added:
    llvm/trunk/test/CodeGen/X86/2009-04-29-LinearScanBug.ll
Modified:
    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=70378&r1=70377&r2=70378&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Apr 29 02:16:34 2009
@@ -978,6 +978,15 @@
         li_->getApproximateInstructionCount(*cur) == 0) {
       // Spill a physical register around defs and uses.
       if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
+        // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
+        // in fixed_. Reset them.
+        for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
+          IntervalPtr &IP = fixed_[i];
+          LiveInterval *I = IP.first;
+          if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
+            IP.second = I->advanceTo(I->begin(), StartPosition);
+        }
+
         DowngradedRegs.clear();
         assignRegOrStackSlotAtInterval(cur);
       } else {

Added: llvm/trunk/test/CodeGen/X86/2009-04-29-LinearScanBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-29-LinearScanBug.ll?rev=70378&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-29-LinearScanBug.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-04-29-LinearScanBug.ll Wed Apr 29 02:16:34 2009
@@ -0,0 +1,215 @@
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin10
+; rdar://6837009
+
+	type { %struct.pf_state*, %struct.pf_state*, %struct.pf_state*, i32 }		; type %0
+	type { %2 }		; type %1
+	type { %struct.pf_addr, %struct.pf_addr }		; type %2
+	type { %struct.in6_addr }		; type %3
+	type { [4 x i32] }		; type %4
+	type { %struct.pfi_dynaddr*, [4 x i8] }		; type %5
+	type { %struct.pfi_dynaddr*, %struct.pfi_dynaddr** }		; type %6
+	type { %struct.pfr_ktable*, %struct.pfr_ktable*, %struct.pfr_ktable*, i32 }		; type %7
+	type { %struct.pfr_ktable* }		; type %8
+	type { i8* }		; type %9
+	type { %11 }		; type %10
+	type { i8*, i8*, %struct.radix_node* }		; type %11
+	type { [2 x %struct.pf_rulequeue], %13, %13 }		; type %12
+	type { %struct.pf_rulequeue*, %struct.pf_rule**, i32, i32, i32 }		; type %13
+	type { %struct.pf_anchor*, %struct.pf_anchor*, %struct.pf_anchor*, i32 }		; type %14
+	type { %struct.pfi_kif*, %struct.pfi_kif*, %struct.pfi_kif*, i32 }		; type %15
+	type { %struct.ifnet*, %struct.ifnet** }		; type %16
+	type { %18 }		; type %17
+	type { %struct.pkthdr, %19 }		; type %18
+	type { %struct.m_ext, [176 x i8] }		; type %19
+	type { %struct.ifmultiaddr*, %struct.ifmultiaddr** }		; type %20
+	type { i32, %22 }		; type %21
+	type { i8*, [4 x i8] }		; type %22
+	type { %struct.tcphdr* }		; type %23
+	type { %struct.pf_ike_state }		; type %24
+	type { %struct.pf_state_key*, %struct.pf_state_key*, %struct.pf_state_key*, i32 }		; type %25
+	type { %struct.pf_src_node*, %struct.pf_src_node*, %struct.pf_src_node*, i32 }		; type %26
+	%struct.anon = type { %struct.pf_state*, %struct.pf_state** }
+	%struct.au_mask_t = type { i32, i32 }
+	%struct.bpf_if = type opaque
+	%struct.dlil_threading_info = type opaque
+	%struct.ether_header = type { [6 x i8], [6 x i8], i16 }
+	%struct.ext_refsq = type { %struct.ext_refsq*, %struct.ext_refsq* }
+	%struct.hook_desc = type { %struct.hook_desc_head, void (i8*)*, i8* }
+	%struct.hook_desc_head = type { %struct.hook_desc*, %struct.hook_desc** }
+	%struct.if_data_internal = type { i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, %struct.au_mask_t, i32, i32, i32 }
+	%struct.ifaddr = type { %struct.sockaddr*, %struct.sockaddr*, %struct.sockaddr*, %struct.ifnet*, %struct.ifaddrhead, void (i32, %struct.rtentry*, %struct.sockaddr*)*, i32, i32, i32, void (%struct.ifaddr*)*, void (%struct.ifaddr*, i32)*, i32 }
+	%struct.ifaddrhead = type { %struct.ifaddr*, %struct.ifaddr** }
+	%struct.ifmultiaddr = type { %20, %struct.sockaddr*, %struct.ifmultiaddr*, %struct.ifnet*, i32, i8*, i32, void (i8*)* }
+	%struct.ifmultihead = type { %struct.ifmultiaddr* }
+	%struct.ifnet = type { i8*, i8*, %16, %struct.ifaddrhead, i32, i32 (%struct.ifnet*, %struct.sockaddr*)*, i32, %struct.bpf_if*, i16, i16, i16, i16, i32, i8*, i32, %struct.if_data_internal, i32, i32 (%struct.ifnet*, %struct.mbuf*)*, i32 (%struct.ifnet*, i32, i8*)*, i32 (%struct.ifnet*, i32, i32 (%struct.ifnet*, %struct.mbuf*)*)*, void (%struct.ifnet*)*, i32 (%struct.ifnet*, %struct.mbuf*, i8*, i32*)*, void (%struct.ifnet*, %struct.kev_msg*)*, i32 (%struct.ifnet*, %struct.mbuf**, %struct.sockaddr*, i8*, i8*)*, i32, %struct.ifnet_filter_head, i32, i8*, i32, %struct.ifmultihead, i32, i32 (%struct.ifnet*, i32, %struct.ifnet_demux_desc*, i32)*, i32 (%struct.ifnet*, i32)*, %struct.proto_hash_entry*, i8*, %struct.dlil_threading_info*, i8*, %struct.ifqueue, [1 x i32], i32, %struct.ifprefixhead, %struct.lck_rw_t*, %21, i32, %struct.thread*, %struct.pfi_kif*, %struct.lck_mtx_t*, %struct.route }
+	%struct.ifnet_demux_desc = type { i32, i8*, i32 }
+	%struct.ifnet_filter = type opaque
+	%struct.ifnet_filter_head = type { %struct.ifnet_filter*, %struct.ifnet_filter** }
+	%struct.ifprefix = type { %struct.sockaddr*, %struct.ifnet*, %struct.ifprefixhead, i8, i8 }
+	%struct.ifprefixhead = type { %struct.ifprefix*, %struct.ifprefix** }
+	%struct.ifqueue = type { i8*, i8*, i32, i32, i32 }
+	%struct.in6_addr = type { %4 }
+	%struct.in_addr = type { i32 }
+	%struct.kev_d_vectors = type { i32, i8* }
+	%struct.kev_msg = type { i32, i32, i32, i32, [5 x %struct.kev_d_vectors] }
+	%struct.lck_mtx_t = type { [3 x i32] }
+	%struct.lck_rw_t = type <{ [3 x i32] }>
+	%struct.m_ext = type { i8*, void (i8*, i32, i8*)*, i32, i8*, %struct.ext_refsq, %struct.au_mask_t* }
+	%struct.m_hdr = type { %struct.mbuf*, %struct.mbuf*, i32, i8*, i16, i16 }
+	%struct.m_tag = type { %struct.packet_tags, i16, i16, i32 }
+	%struct.mbuf = type { %struct.m_hdr, %17 }
+	%struct.packet_tags = type { %struct.m_tag* }
+	%struct.pf_addr = type { %3 }
+	%struct.pf_addr_wrap = type <{ %1, %5, i8, i8, [6 x i8] }>
+	%struct.pf_anchor = type { %14, %14, %struct.pf_anchor*, %struct.pf_anchor_node, [64 x i8], [1024 x i8], %struct.pf_ruleset, i32, i32 }
+	%struct.pf_anchor_node = type { %struct.pf_anchor* }
+	%struct.pf_app_state = type { void (%struct.pf_state*, i32, i32, %struct.pf_pdesc*, %struct.pfi_kif*)*, i32 (%struct.pf_app_state*, %struct.pf_app_state*)*, i32 (%struct.pf_app_state*, %struct.pf_app_state*)*, %24 }
+	%struct.pf_ike_state = type { i64 }
+	%struct.pf_mtag = type { i8*, i32, i32, i16, i8, i8 }
+	%struct.pf_palist = type { %struct.pf_pooladdr*, %struct.pf_pooladdr** }
+	%struct.pf_pdesc = type { %struct.pf_threshold, i64, %23, %struct.pf_addr, %struct.pf_addr, %struct.pf_rule*, %struct.pf_addr*, %struct.pf_addr*, %struct.ether_header*, %struct.mbuf*, i32, %struct.pf_mtag*, i16*, i32, i16, i8, i8, i8, i8 }
+	%struct.pf_pool = type { %struct.pf_palist, [2 x i32], %struct.pf_pooladdr*, [4 x i8], %struct.in6_addr, %struct.pf_addr, i32, [2 x i16], i8, i8, [1 x i32] }
+	%struct.pf_pooladdr = type <{ %struct.pf_addr_wrap, %struct.pf_palist, [2 x i32], [16 x i8], %struct.pfi_kif*, [1 x i32] }>
+	%struct.pf_rule = type <{ %struct.pf_rule_addr, %struct.pf_rule_addr, [8 x %struct.pf_rule_ptr], [64 x i8], [16 x i8], [64 x i8], [64 x i8], [64 x i8], [64 x i8], [32 x i8], %struct.pf_rulequeue, [2 x i32], %struct.pf_pool, i64, [2 x i64], [2 x i64], %struct.pfi_kif*, [4 x i8], %struct.pf_anchor*, [4 x i8], %struct.pfr_ktable*, [4 x i8], i32, i32, [26 x i32], i32, i32, i32, i32, i32, i32, %struct.au_mask_t, i32, i32, i32, i32, i32, i32, i32, i16, i16, i16, i16, i16, [2 x i8], %struct.pf_rule_gid, %struct.pf_rule_gid, i32, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, [2 x i8] }>
+	%struct.pf_rule_addr = type <{ %struct.pf_addr_wrap, %struct.pf_rule_xport, i8, [7 x i8] }>
+	%struct.pf_rule_gid = type { [2 x i32], i8, [3 x i8] }
+	%struct.pf_rule_ptr = type { %struct.pf_rule*, [4 x i8] }
+	%struct.pf_rule_xport = type { i32, [4 x i8] }
+	%struct.pf_rulequeue = type { %struct.pf_rule*, %struct.pf_rule** }
+	%struct.pf_ruleset = type { [5 x %12], %struct.pf_anchor*, i32, i32, i32 }
+	%struct.pf_src_node = type <{ %26, %struct.pf_addr, %struct.pf_addr, %struct.pf_rule_ptr, %struct.pfi_kif*, [2 x i64], [2 x i64], i32, i32, %struct.pf_threshold, i64, i64, i8, i8, [2 x i8] }>
+	%struct.pf_state = type <{ i64, i32, i32, %struct.anon, %struct.anon, %0, %struct.pf_state_peer, %struct.pf_state_peer, %struct.pf_rule_ptr, %struct.pf_rule_ptr, %struct.pf_rule_ptr, %struct.pf_addr, %struct.hook_desc_head, %struct.pf_state_key*, %struct.pfi_kif*, %struct.pfi_kif*, %struct.pf_src_node*, %struct.pf_src_node*, [2 x i64], [2 x i64], i64, i64, i64, i16, i8, i8, i8, i8, [6 x i8] }>
+	%struct.pf_state_host = type { %struct.pf_addr, %struct.in_addr }
+	%struct.pf_state_key = type { %struct.pf_state_host, %struct.pf_state_host, %struct.pf_state_host, i8, i8, i8, i8, %struct.pf_app_state*, %25, %25, %struct.anon, i16 }
+	%struct.pf_state_peer = type { i32, i32, i32, i16, i8, i8, i16, i8, %struct.pf_state_scrub*, [3 x i8] }
+	%struct.pf_state_scrub = type { %struct.au_mask_t, i32, i32, i32, i16, i8, i8, i32 }
+	%struct.pf_threshold = type { i32, i32, i32, i32 }
+	%struct.pfi_dynaddr = type { %6, %struct.pf_addr, %struct.pf_addr, %struct.pf_addr, %struct.pf_addr, %struct.pfr_ktable*, %struct.pfi_kif*, i8*, i32, i32, i32, i8, i8 }
+	%struct.pfi_kif = type { [16 x i8], %15, [2 x [2 x [2 x i64]]], [2 x [2 x [2 x i64]]], i64, i32, i8*, %struct.ifnet*, i32, i32, %6 }
+	%struct.pfr_ktable = type { %struct.pfr_tstats, %7, %8, %struct.radix_node_head*, %struct.radix_node_head*, %struct.pfr_ktable*, %struct.pfr_ktable*, %struct.pf_ruleset*, i64, i32 }
+	%struct.pfr_table = type { [1024 x i8], [32 x i8], i32, i8 }
+	%struct.pfr_tstats = type { %struct.pfr_table, [2 x [3 x i64]], [2 x [3 x i64]], i64, i64, i64, i32, [2 x i32] }
+	%struct.pkthdr = type { i32, %struct.ifnet*, i8*, i32, i32, i32, i16, i16, %struct.packet_tags }
+	%struct.proto_hash_entry = type opaque
+	%struct.radix_mask = type { i16, i8, i8, %struct.radix_mask*, %9, i32 }
+	%struct.radix_node = type { %struct.radix_mask*, %struct.radix_node*, i16, i8, i8, %10 }
+	%struct.radix_node_head = type { %struct.radix_node*, i32, i32, %struct.radix_node* (i8*, i8*, %struct.radix_node_head*, %struct.radix_node*)*, %struct.radix_node* (i8*, i8*, %struct.radix_node_head*, %struct.radix_node*)*, %struct.radix_node* (i8*, i8*, %struct.radix_node_head*)*, %struct.radix_node* (i8*, i8*, %struct.radix_node_head*)*, %struct.radix_node* (i8*, %struct.radix_node_head*)*, %struct.radix_node* (i8*, %struct.radix_node_head*, i32 (%struct.radix_node*, i8*)*, i8*)*, %struct.radix_node* (i8*, i8*, %struct.radix_node_head*)*, %struct.radix_node* (i8*, i8*, %struct.radix_node_head*, i32 (%struct.radix_node*, i8*)*, i8*)*, %struct.radix_node* (i8*, %struct.radix_node_head*)*, i32 (%struct.radix_node_head*, i32 (%struct.radix_node*, i8*)*, i8*)*, i32 (%struct.radix_node_head*, i8*, i8*, i32 (%struct.radix_node*, i8*)*, i8*)*, void (%struct.radix_node*, %struct.radix_node_head*)*, [3 x %struct.radix_node], i32 }
+	%struct.route = type { %struct.rtentry*, i32, %struct.sockaddr }
+	%struct.rt_metrics = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32] }
+	%struct.rtentry = type { [2 x %struct.radix_node], %struct.sockaddr*, i32, i32, %struct.ifnet*, %struct.ifaddr*, %struct.sockaddr*, i8*, void (i8*)*, %struct.rt_metrics, %struct.rtentry*, %struct.rtentry*, i32, %struct.lck_mtx_t }
+	%struct.sockaddr = type { i8, i8, [14 x i8] }
+	%struct.tcphdr = type { i16, i16, i32, i32, i8, i8, i16, i16, i16 }
+	%struct.thread = type opaque
+ at llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (%struct.pf_state_key*, %struct.pf_state_key*)* @pf_state_compare_ext_gwy to i8*)], section "llvm.metadata"		; <[1 x i8*]*> [#uses=0]
+
+define fastcc i32 @pf_state_compare_ext_gwy(%struct.pf_state_key* nocapture %a, %struct.pf_state_key* nocapture %b) nounwind optsize ssp {
+entry:
+	%0 = zext i8 0 to i32		; <i32> [#uses=2]
+	%1 = load i8* null, align 1		; <i8> [#uses=2]
+	%2 = zext i8 %1 to i32		; <i32> [#uses=1]
+	%3 = sub i32 %0, %2		; <i32> [#uses=1]
+	%4 = icmp eq i8 0, %1		; <i1> [#uses=1]
+	br i1 %4, label %bb1, label %bb79
+
+bb1:		; preds = %entry
+	%5 = load i8* null, align 4		; <i8> [#uses=2]
+	%6 = zext i8 %5 to i32		; <i32> [#uses=2]
+	%7 = getelementptr %struct.pf_state_key* %b, i32 0, i32 3		; <i8*> [#uses=1]
+	%8 = load i8* %7, align 4		; <i8> [#uses=2]
+	%9 = zext i8 %8 to i32		; <i32> [#uses=1]
+	%10 = sub i32 %6, %9		; <i32> [#uses=1]
+	%11 = icmp eq i8 %5, %8		; <i1> [#uses=1]
+	br i1 %11, label %bb3, label %bb79
+
+bb3:		; preds = %bb1
+	switch i32 %0, label %bb23 [
+		i32 1, label %bb4
+		i32 6, label %bb6
+		i32 17, label %bb10
+		i32 47, label %bb17
+		i32 50, label %bb21
+		i32 58, label %bb4
+	]
+
+bb4:		; preds = %bb3, %bb3
+	%12 = load i16* null, align 4		; <i16> [#uses=1]
+	%13 = zext i16 %12 to i32		; <i32> [#uses=1]
+	%14 = sub i32 0, %13		; <i32> [#uses=1]
+	br i1 false, label %bb23, label %bb79
+
+bb6:		; preds = %bb3
+	%15 = load i16* null, align 4		; <i16> [#uses=1]
+	%16 = zext i16 %15 to i32		; <i32> [#uses=1]
+	%17 = sub i32 0, %16		; <i32> [#uses=1]
+	ret i32 %17
+
+bb10:		; preds = %bb3
+	%18 = load i8* null, align 1		; <i8> [#uses=2]
+	%19 = zext i8 %18 to i32		; <i32> [#uses=1]
+	%20 = sub i32 0, %19		; <i32> [#uses=1]
+	%21 = icmp eq i8 0, %18		; <i1> [#uses=1]
+	br i1 %21, label %bb12, label %bb79
+
+bb12:		; preds = %bb10
+	%22 = load i16* null, align 4		; <i16> [#uses=1]
+	%23 = zext i16 %22 to i32		; <i32> [#uses=1]
+	%24 = sub i32 0, %23		; <i32> [#uses=1]
+	ret i32 %24
+
+bb17:		; preds = %bb3
+	%25 = load i8* null, align 1		; <i8> [#uses=2]
+	%26 = icmp eq i8 %25, 1		; <i1> [#uses=1]
+	br i1 %26, label %bb18, label %bb23
+
+bb18:		; preds = %bb17
+	%27 = icmp eq i8 %25, 0		; <i1> [#uses=1]
+	br i1 %27, label %bb19, label %bb23
+
+bb19:		; preds = %bb18
+	%28 = load i16* null, align 4		; <i16> [#uses=1]
+	%29 = zext i16 %28 to i32		; <i32> [#uses=1]
+	%30 = sub i32 0, %29		; <i32> [#uses=1]
+	br i1 false, label %bb23, label %bb79
+
+bb21:		; preds = %bb3
+	%31 = getelementptr %struct.pf_state_key* %a, i32 0, i32 1, i32 1, i32 0		; <i32*> [#uses=1]
+	%32 = load i32* %31, align 4		; <i32> [#uses=2]
+	%33 = getelementptr %struct.pf_state_key* %b, i32 0, i32 1, i32 1, i32 0		; <i32*> [#uses=1]
+	%34 = load i32* %33, align 4		; <i32> [#uses=2]
+	%35 = sub i32 %32, %34		; <i32> [#uses=1]
+	%36 = icmp eq i32 %32, %34		; <i1> [#uses=1]
+	br i1 %36, label %bb23, label %bb79
+
+bb23:		; preds = %bb21, %bb19, %bb18, %bb17, %bb4, %bb3
+	%cond = icmp eq i32 %6, 2		; <i1> [#uses=1]
+	br i1 %cond, label %bb24, label %bb70
+
+bb24:		; preds = %bb23
+	ret i32 1
+
+bb70:		; preds = %bb23
+	%37 = load i32 (%struct.pf_app_state*, %struct.pf_app_state*)** null, align 4		; <i32 (%struct.pf_app_state*, %struct.pf_app_state*)*> [#uses=3]
+	br i1 false, label %bb78, label %bb73
+
+bb73:		; preds = %bb70
+	%38 = load i32 (%struct.pf_app_state*, %struct.pf_app_state*)** null, align 4		; <i32 (%struct.pf_app_state*, %struct.pf_app_state*)*> [#uses=2]
+	%39 = icmp eq i32 (%struct.pf_app_state*, %struct.pf_app_state*)* %38, null		; <i1> [#uses=1]
+	br i1 %39, label %bb78, label %bb74
+
+bb74:		; preds = %bb73
+	%40 = ptrtoint i32 (%struct.pf_app_state*, %struct.pf_app_state*)* %37 to i32		; <i32> [#uses=1]
+	%41 = sub i32 0, %40		; <i32> [#uses=1]
+	%42 = icmp eq i32 (%struct.pf_app_state*, %struct.pf_app_state*)* %38, %37		; <i1> [#uses=1]
+	br i1 %42, label %bb76, label %bb79
+
+bb76:		; preds = %bb74
+	%43 = tail call i32 %37(%struct.pf_app_state* null, %struct.pf_app_state* null) nounwind		; <i32> [#uses=1]
+	ret i32 %43
+
+bb78:		; preds = %bb73, %bb70
+	ret i32 0
+
+bb79:		; preds = %bb74, %bb21, %bb19, %bb10, %bb4, %bb1, %entry
+	%.0 = phi i32 [ %3, %entry ], [ %10, %bb1 ], [ %14, %bb4 ], [ %20, %bb10 ], [ %30, %bb19 ], [ %35, %bb21 ], [ %41, %bb74 ]		; <i32> [#uses=1]
+	ret i32 %.0
+}




From sanjiv.gupta at microchip.com  Wed Apr 29 03:23:34 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Wed, 29 Apr 2009 08:23:34 -0000
Subject: [llvm-commits] [llvm] r70379 -
	/llvm/trunk/include/llvm/Target/TargetAsmInfo.h
Message-ID: <200904290823.n3T8Nb9l017311@zion.cs.uiuc.edu>

Author: sgupta
Date: Wed Apr 29 03:23:18 2009
New Revision: 70379

URL: http://llvm.org/viewvc/llvm-project?rev=70379&view=rev
Log:
Add directive to declare external globals.

Modified:
    llvm/trunk/include/llvm/Target/TargetAsmInfo.h

Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=70379&r1=70378&r2=70379&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Wed Apr 29 03:23:18 2009
@@ -384,6 +384,11 @@
     /// GlobalDirective - This is the directive used to declare a global entity.
     ///
     const char *GlobalDirective;          // Defaults to NULL.
+
+    /// ExternDirective - This is the directive used to declare external 
+    /// globals.
+    ///
+    const char *ExternDirective;          // Defaults to NULL.
     
     /// SetDirective - This is the name of a directive that can be used to tell
     /// the assembler to set the value of a variable to some expression.
@@ -801,6 +806,9 @@
     const char *getGlobalDirective() const {
       return GlobalDirective;
     }
+    const char *getExternDirective() const {
+      return ExternDirective;
+    }
     const char *getSetDirective() const {
       return SetDirective;
     }




From clattner at apple.com  Wed Apr 29 11:12:02 2009
From: clattner at apple.com (Chris Lattner)
Date: Wed, 29 Apr 2009 09:12:02 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r70377 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
In-Reply-To: <200904290858.43761.baldrick@free.fr>
References: <200904290647.n3T6lP3m002576@zion.cs.uiuc.edu>
	<200904290858.43761.baldrick@free.fr>
Message-ID: <B32F5C95-9FF0-463D-B28D-8169CA1A1AB5@apple.com>


On Apr 28, 2009, at 11:58 PM, Duncan Sands wrote:

> Hi Chris,
>
>> +    // The GCC array expression value may not compile to an LLVM  
>> array type if
>> +    // (for example) the array value is an array of unions.  In  
>> this case, the
>> +    // array literal will turn into an LLVM constant struct, which  
>> has struct
>> +    // type.  Do a cast to the correct type just to be certain  
>> everything is
>> +    // kosher.
>
> I think it would be better to require EmitLV to always return a  
> pointer
> of the right type.  This means that the bitcast should be somewhere  
> else.
> I will take care of this once things calm down here :)

Yeah, I didn't know the best way to do that.  Thanks Duncan!

-Chris


From magnus.xm.reftel at stericsson.com  Wed Apr 29 11:04:27 2009
From: magnus.xm.reftel at stericsson.com (Magnus Reftel XM)
Date: Wed, 29 Apr 2009 18:04:27 +0200
Subject: [llvm-commits] Llvm-db build failure on rev 70380
Message-ID: <70B331E6E4F30240AD5B629EED8D318C086B3829@esealmw112.eemea.ericsson.se>

Hi,

llvm-db fails to link on Cygwin in rev 70380. It has worked for me
before, but I'm not sure at which revision I did a clean build most
recently. Please see attached log.

Regards
Magnus Reftel
-------------- next part --------------
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From anton at korobeynikov.info  Wed Apr 29 11:19:18 2009
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Wed, 29 Apr 2009 20:19:18 +0400
Subject: [llvm-commits] Llvm-db build failure on rev 70380
In-Reply-To: <70B331E6E4F30240AD5B629EED8D318C086B3829@esealmw112.eemea.ericsson.se>
References: <70B331E6E4F30240AD5B629EED8D318C086B3829@esealmw112.eemea.ericsson.se>
Message-ID: <b087fca00904290919l7a91970dyef73da7b48d1d4ca@mail.gmail.com>

> llvm-db fails to link on Cygwin in rev 70380. It has worked for me
> before, but I'm not sure at which revision I did a clean build most
> recently. Please see attached log.
Have you updated compiler recently? If yes - please do make clean and
rebuild the whole LLVM.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From dalej at apple.com  Wed Apr 29 11:38:47 2009
From: dalej at apple.com (Dale Johannesen)
Date: Wed, 29 Apr 2009 16:38:47 -0000
Subject: [llvm-commits] [llvm] r70386 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp
 test/Transforms/LoopStrengthReduce/2009-04-28-no-reduce-mul.ll
Message-ID: <200904291638.n3TGcliJ001885@zion.cs.uiuc.edu>

Author: johannes
Date: Wed Apr 29 11:38:47 2009
New Revision: 70386

URL: http://llvm.org/viewvc/llvm-project?rev=70386&view=rev
Log:
Fix recent regression in gcc.dg/pr26719.c (6835035).


Added:
    llvm/trunk/test/Transforms/LoopStrengthReduce/2009-04-28-no-reduce-mul.ll
Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=70386&r1=70385&r2=70386&view=diff

==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Apr 29 11:38:47 2009
@@ -812,11 +812,14 @@
         SCEVHandle Step = AR->getStepRecurrence(*this);
 
         // Check whether the backedge-taken count can be losslessly casted to
-        // the addrec's type. The count is always unsigned.
+        // the addrec's type. The count needs to be the same whether sign
+        // extended or zero extended.
         SCEVHandle CastedBECount =
           getTruncateOrZeroExtend(BECount, Start->getType());
         if (BECount ==
-            getTruncateOrZeroExtend(CastedBECount, BECount->getType())) {
+            getTruncateOrZeroExtend(CastedBECount, BECount->getType()) &&
+            BECount ==
+            getTruncateOrSignExtend(CastedBECount, BECount->getType())) {
           const Type *WideTy =
             IntegerType::get(getTypeSizeInBits(Start->getType()) * 2);
           SCEVHandle SMul =

Added: llvm/trunk/test/Transforms/LoopStrengthReduce/2009-04-28-no-reduce-mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/2009-04-28-no-reduce-mul.ll?rev=70386&view=auto

==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/2009-04-28-no-reduce-mul.ll (added)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/2009-04-28-no-reduce-mul.ll Wed Apr 29 11:38:47 2009
@@ -0,0 +1,43 @@
+; RUN: llvm-as < %s | opt -loop-reduce | llvm-dis | grep mul | count 3
+; The multiply in bb2 must not be reduced to an add, as the sext causes the
+; %1 argument to become negative after a while.
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.6"
+ at table = common global [32 x [256 x i32]] zeroinitializer, align 32		; <[32 x [256 x i32]]*> [#uses=2]
+
+define i32 @main() nounwind {
+bb4.thread:
+	br label %bb2
+
+bb2:		; preds = %bb4, %bb2, %bb4.thread
+	%i.0.reg2mem.0.ph = phi i32 [ 0, %bb4.thread ], [ %i.0.reg2mem.0.ph, %bb2 ], [ %indvar.next9, %bb4 ]		; <i32> [#uses=4]
+	%j.0.reg2mem.0 = phi i32 [ 0, %bb4.thread ], [ %indvar.next, %bb2 ], [ 0, %bb4 ]		; <i32> [#uses=3]
+	%0 = trunc i32 %j.0.reg2mem.0 to i8		; <i8> [#uses=1]
+	%1 = sext i8 %0 to i32		; <i32> [#uses=1]
+	%2 = mul i32 %1, %i.0.reg2mem.0.ph		; <i32> [#uses=1]
+	%3 = getelementptr [32 x [256 x i32]]* @table, i32 0, i32 %i.0.reg2mem.0.ph, i32 %j.0.reg2mem.0		; <i32*> [#uses=1]
+	store i32 %2, i32* %3, align 4
+	%indvar.next = add i32 %j.0.reg2mem.0, 1		; <i32> [#uses=2]
+	%exitcond = icmp eq i32 %indvar.next, 256		; <i1> [#uses=1]
+	br i1 %exitcond, label %bb4, label %bb2
+
+bb4:		; preds = %bb2
+	%indvar.next9 = add i32 %i.0.reg2mem.0.ph, 1		; <i32> [#uses=2]
+	%exitcond10 = icmp eq i32 %indvar.next9, 32		; <i1> [#uses=1]
+	br i1 %exitcond10, label %bb5, label %bb2
+
+bb5:		; preds = %bb4
+	%4 = load i32* getelementptr ([32 x [256 x i32]]* @table, i32 0, i32 9, i32 132), align 16		; <i32> [#uses=1]
+	%5 = icmp eq i32 %4, -1116		; <i1> [#uses=1]
+	br i1 %5, label %bb7, label %bb6
+
+bb6:		; preds = %bb5
+	tail call void @abort() noreturn nounwind
+	unreachable
+
+bb7:		; preds = %bb5
+	ret i32 0
+}
+
+declare void @abort() noreturn nounwind




From natebegeman at mac.com  Wed Apr 29 13:13:32 2009
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 29 Apr 2009 18:13:32 -0000
Subject: [llvm-commits] [llvm] r70391 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGNodes.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Message-ID: <200904291813.n3TIDWRM005372@zion.cs.uiuc.edu>

Author: sampo
Date: Wed Apr 29 13:13:31 2009
New Revision: 70391

URL: http://llvm.org/viewvc/llvm-project?rev=70391&view=rev
Log:
Update comment, replace theoretically impossible check with an assert.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=70391&r1=70390&r2=70391&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Apr 29 13:13:31 2009
@@ -317,13 +317,13 @@
     /// IDX, which must be a multiple of the result vector length.
     EXTRACT_SUBVECTOR,
 
-    /// VECTOR_SHUFFLE(VEC1, VEC2, SHUFFLEVEC) - Returns a vector, of the same
-    /// type as VEC1/VEC2.  SHUFFLEVEC is a BUILD_VECTOR of constant int values
-    /// (maybe of an illegal datatype) or undef that indicate which value each
-    /// result element will get.  The elements of VEC1/VEC2 are enumerated in
-    /// order.  This is quite similar to the Altivec 'vperm' instruction, except
-    /// that the indices must be constants and are in terms of the element size
-    /// of VEC1/VEC2, not in terms of bytes.
+    /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 
+    /// VEC1/VEC2.  A VECTOR_SHUFFLE node also contains an array of constant int 
+    /// values that indicate which value (or undef) each result element will
+    /// get.  These constant ints are accessible through the 
+    /// ShuffleVectorSDNode class.  This is quite similar to the Altivec 
+    /// 'vperm' instruction, except that the indices must be constants and are
+    /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
     VECTOR_SHUFFLE,
 
     /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=70391&r1=70390&r2=70391&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Apr 29 13:13:31 2009
@@ -5731,9 +5731,7 @@
   for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i)
     /* search */;
 
-  // If we hit the end of the mask looking for a non-undef value, return false.
-  if (i == e)
-    return false;
+  assert(i != e && "VECTOR_SHUFFLE node with all undef indices!");
   
   // Make sure all remaining elements are either undef or the same as the first
   // non-undef value.




From gohman at apple.com  Wed Apr 29 15:27:53 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 29 Apr 2009 20:27:53 -0000
Subject: [llvm-commits] [llvm] r70405 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp
 test/Analysis/ScalarEvolution/sext-inreg.ll
Message-ID: <200904292027.n3TKRrg9010167@zion.cs.uiuc.edu>

Author: djg
Date: Wed Apr 29 15:27:52 2009
New Revision: 70405

URL: http://llvm.org/viewvc/llvm-project?rev=70405&view=rev
Log:
Include the source type in SCEV cast expression debug output, and
print sext, zext, and trunc, instead of signextend, zeroextend,
and truncate, respectively, for consistency with the main IR.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp
    llvm/trunk/test/Analysis/ScalarEvolution/sext-inreg.ll

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=70405&r1=70404&r2=70405&view=diff

==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Apr 29 15:27:52 2009
@@ -219,7 +219,7 @@
 }
 
 void SCEVTruncateExpr::print(raw_ostream &OS) const {
-  OS << "(truncate " << *Op << " to " << *Ty << ")";
+  OS << "(trunc " << *Op->getType() << " " << *Op << " to " << *Ty << ")";
 }
 
 // SCEVZeroExtends - Only allow the creation of one SCEVZeroExtendExpr for any
@@ -240,7 +240,7 @@
 }
 
 void SCEVZeroExtendExpr::print(raw_ostream &OS) const {
-  OS << "(zeroextend " << *Op << " to " << *Ty << ")";
+  OS << "(zext " << *Op->getType() << " " << *Op << " to " << *Ty << ")";
 }
 
 // SCEVSignExtends - Only allow the creation of one SCEVSignExtendExpr for any
@@ -261,7 +261,7 @@
 }
 
 void SCEVSignExtendExpr::print(raw_ostream &OS) const {
-  OS << "(signextend " << *Op << " to " << *Ty << ")";
+  OS << "(sext " << *Op->getType() << " " << *Op << " to " << *Ty << ")";
 }
 
 // SCEVCommExprs - Only allow the creation of one SCEVCommutativeExpr for any

Modified: llvm/trunk/test/Analysis/ScalarEvolution/sext-inreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/sext-inreg.ll?rev=70405&r1=70404&r2=70405&view=diff

==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/sext-inreg.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/sext-inreg.ll Wed Apr 29 15:27:52 2009
@@ -1,5 +1,6 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
-; RUN:  | grep {signextend \{0,+,199\}<bb> to i64} | count 2
+; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output > %t
+; RUN: grep {sext i57 \{0,+,199\}<bb> to i64} %t | count 1
+; RUN: grep {sext i59 \{0,+,199\}<bb> to i64} %t | count 1
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin9.6"




From stoklund at 2pi.dk  Wed Apr 29 15:45:30 2009
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 29 Apr 2009 22:45:30 +0200
Subject: [llvm-commits] [PATCH] Teach -join-cross-class-copies to intersect
	register classes
Message-ID: <B7BFD531-05C9-4138-AC82-9267607AA674@2pi.dk>

This patch series teaches -join-register-classes to properly intersect  
register classes when joining two virtual registers. This avoids  
generating bad machine code in the blackfin backend. It should have no  
effect on other targets.

=== 01-tablegen-subclass.patch

Loosen TableGen's definition of a register subclass so a subclass is  
allowed to have a larger spill size. This is consistent with what - 
join-cross-class-copies does now.

See my ramblings here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-April/021966.html

This patch is not actually necessary to solve my blackfin problems -  
it ensures that -join-cross-class-copies doesn't change behaviour on  
Alpha, PPC, SPU, and X86 where a register may have multiple spill sizes.

=== 02-intersection-regclass.patch

Implement the intersection(A, B) function that find the largest common  
subclass of two register classes.

=== 03-join-cross-intersection.patch

Use intersection() to determine the new register class of a joined  
virtual register.




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From stoklund at 2pi.dk  Wed Apr 29 15:57:16 2009
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 29 Apr 2009 20:57:16 -0000
Subject: [llvm-commits] [llvm] r70408 - in /llvm/trunk:
 include/llvm/CodeGen/MachineInstr.h lib/CodeGen/MachineInstr.cpp
Message-ID: <200904292057.n3TKvGmd011049@zion.cs.uiuc.edu>

Author: stoklund
Date: Wed Apr 29 15:57:16 2009
New Revision: 70408

URL: http://llvm.org/viewvc/llvm-project?rev=70408&view=rev
Log:
MachineInstr::isRegTiedTo{Use,Def}Operand can safely be made const.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineInstr.h
    llvm/trunk/lib/CodeGen/MachineInstr.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=70408&r1=70407&r2=70408&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Wed Apr 29 15:57:16 2009
@@ -245,12 +245,12 @@
   /// check if the register def is tied to a source operand, due to either
   /// two-address elimination or inline assembly constraints. Returns the
   /// first tied use operand index by reference is UseOpIdx is not null.
-  bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0);
+  bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
 
   /// isRegTiedToDefOperand - Return true if the use operand of the specified
   /// index is tied to an def operand. It also returns the def operand index by
   /// reference if DefOpIdx is not null.
-  bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0);
+  bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
 
   /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
   ///

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=70408&r1=70407&r2=70408&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Wed Apr 29 15:57:16 2009
@@ -709,7 +709,8 @@
 /// check if the register def is tied to a source operand, due to either
 /// two-address elimination or inline assembly constraints. Returns the
 /// first tied use operand index by reference is UseOpIdx is not null.
-bool MachineInstr::isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx){
+bool MachineInstr::
+isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
   if (getOpcode() == TargetInstrInfo::INLINEASM) {
     assert(DefOpIdx >= 2);
     const MachineOperand &MO = getOperand(DefOpIdx);
@@ -759,7 +760,8 @@
 /// isRegTiedToDefOperand - Return true if the operand of the specified index
 /// is a register use and it is tied to an def operand. It also returns the def
 /// operand index by reference.
-bool MachineInstr::isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx){
+bool MachineInstr::
+isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
   if (getOpcode() == TargetInstrInfo::INLINEASM) {
     const MachineOperand &MO = getOperand(UseOpIdx);
     if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)




From gohman at apple.com  Wed Apr 29 16:06:20 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 29 Apr 2009 21:06:20 -0000
Subject: [llvm-commits] [llvm] r70410 -
 /llvm/trunk/test/Analysis/ScalarEvolution/2009-04-22-TruncCast.ll
Message-ID: <200904292106.n3TL6Lwp011333@zion.cs.uiuc.edu>

Author: djg
Date: Wed Apr 29 16:06:20 2009
New Revision: 70410

URL: http://llvm.org/viewvc/llvm-project?rev=70410&view=rev
Log:
Fix this test to match the new output from scalar-evolution.

Modified:
    llvm/trunk/test/Analysis/ScalarEvolution/2009-04-22-TruncCast.ll

Modified: llvm/trunk/test/Analysis/ScalarEvolution/2009-04-22-TruncCast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/2009-04-22-TruncCast.ll?rev=70410&r1=70409&r2=70410&view=diff

==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/2009-04-22-TruncCast.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/2009-04-22-TruncCast.ll Wed Apr 29 16:06:20 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution | grep truncate | not grep extend
+; RUN: llvm-as < %s | opt -analyze -scalar-evolution | grep {(trunc i} | not grep ext
 
 define i16 @test1(i8 %x) {
   %A = sext i8 %x to i32




From evan.cheng at apple.com  Wed Apr 29 16:16:17 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Apr 2009 14:16:17 -0700
Subject: [llvm-commits] [llvm] r70343 - in /llvm/trunk:
	docs/CommandGuide/ include/llvm/CodeGen/ include/llvm/Target/
	lib/CodeGen/ lib/CodeGen/AsmPrinter/
	lib/CodeGen/SelectionDAG/ lib/Target/ARM/
	lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/
	lib/Target/Alpha/AsmPrinter/ lib/Target/CBackend/
	lib/Target/CellSPU/ lib/Target/CellSPU/AsmPrinter/
	lib/Target/CppBackend/ lib/Target/IA64/
	lib/Target/IA64/AsmPrinter/ lib/Target/MSIL/ lib/Target/Mips/
	lib/Target/Mips/AsmPrinter/ lib/Target/PIC16/
	lib/Target/PowerPC/ lib/Target/PowerPC/Asm...
In-Reply-To: <200904290015.n3T0FjH5022866@zion.cs.uiuc.edu>
References: <200904290015.n3T0FjH5022866@zion.cs.uiuc.edu>
Message-ID: <6AF69534-B678-4E4B-855C-756FE47E4193@apple.com>

Bill, you still have to change LTOCodeGenerator.cpp. Also, rather than  
an unsigned for OptLevel, should it be an enum instead? We basically  
want to support a knob with 3 levels: no optimization, default  
optimization, aggressive optimization. Those correspond to -O0, -O1 / - 
O2 / -Os, -O3.

Evan

On Apr 28, 2009, at 5:15 PM, Bill Wendling wrote:

> Author: void
> Date: Tue Apr 28 19:15:41 2009
> New Revision: 70343
>
> URL: http://llvm.org/viewvc/llvm-project?rev=70343&view=rev
> Log:
> Second attempt:
>
> Massive check in. This changes the "-fast" flag to "-O#" in llc. If  
> you want to
> use the old behavior, the flag is -O0. This change allows for finer- 
> grained
> control over which optimizations are run at different -O levels.
>
> Most of this work was pretty mechanical. The majority of the fixes  
> came from
> verifying that a "fast" variable wasn't used anymore. The JIT still  
> uses a
> "Fast" flag. I'll change the JIT with a follow-up patch.
>
> Modified:
>    llvm/trunk/docs/CommandGuide/llc.pod
>    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
>    llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
>    llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>    llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
>    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
>    llvm/trunk/include/llvm/Target/TargetMachine.h
>    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
>    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
>    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>    llvm/trunk/lib/Target/ARM/ARM.h
>    llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
>    llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
>    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>    llvm/trunk/lib/Target/Alpha/Alpha.h
>    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
>    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
>    llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>    llvm/trunk/lib/Target/CBackend/CBackend.cpp
>    llvm/trunk/lib/Target/CBackend/CTargetMachine.h
>    llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>    llvm/trunk/lib/Target/CellSPU/SPU.h
>    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
>    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
>    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
>    llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
>    llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>    llvm/trunk/lib/Target/IA64/IA64.h
>    llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
>    llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
>    llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
>    llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>    llvm/trunk/lib/Target/Mips/Mips.h
>    llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
>    llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
>    llvm/trunk/lib/Target/PIC16/PIC16.h
>    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
>    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
>    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
>    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
>    llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>    llvm/trunk/lib/Target/PowerPC/PPC.h
>    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
>    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
>    llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
>    llvm/trunk/lib/Target/Sparc/Sparc.h
>    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
>    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
>    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
>    llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
>    llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
>    llvm/trunk/lib/Target/X86/X86.h
>    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
>    llvm/trunk/lib/Target/X86/X86TargetMachine.h
>    llvm/trunk/lib/Target/XCore/XCore.h
>    llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
>    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
>    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
>    llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
>    llvm/trunk/test/CodeGen/Generic/2006-06-13- 
> ComputeMaskedBitsCrash.ll
>    llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
>    llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
>    llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
>    llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
>    llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
>    llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
>    llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
>    llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
>    llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
>    llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
>    llvm/trunk/test/CodeGen/X86/pr1489.ll
>    llvm/trunk/test/CodeGen/X86/volatile.ll
>    llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
>    llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
>    llvm/trunk/test/DebugInfo/deaddebuglabel.ll
>    llvm/trunk/test/DebugInfo/forwardDecl.ll
>    llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
>    llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
>    llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
>    llvm/trunk/tools/llc/llc.cpp
>    llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
>    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>
> Modified: llvm/trunk/docs/CommandGuide/llc.pod
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CommandGuide/llc.pod?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/docs/CommandGuide/llc.pod (original)
> +++ llvm/trunk/docs/CommandGuide/llc.pod Tue Apr 28 19:15:41 2009
> @@ -41,6 +41,12 @@
>
> Print a summary of command line options.
>
> +=item B<-O>=I<uint>
> +
> +Generate code at different optimization levels. These correspond to  
> the I<-O0>,
> +I<-O1>, I<-O2>, I<-O3>, and I<-O4> optimization levels used by  
> B<llvm-gcc> and
> +B<clang>.
> +
> =item B<-f>
>
> Overwrite output files. By default, B<llc> will refuse to overwrite
>
> Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Tue Apr 28 19:15:41  
> 2009
> @@ -65,8 +65,8 @@
>     // Necessary for external weak linkage support
>     std::set<const GlobalValue*> ExtWeakSymbols;
>
> -    /// Fast - Generating code via fast instruction selection.
> -    bool Fast;
> +    /// OptLevel - Generating code at a specific optimization level.
> +    unsigned OptLevel;
>   public:
>     /// Output stream on which we're printing assembly code.
>     ///
> @@ -110,8 +110,8 @@
>     bool VerboseAsm;
>
>   protected:
> -    AsmPrinter(raw_ostream &o, TargetMachine &TM,
> -               const TargetAsmInfo *T, bool F, bool V);
> +    explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
> +                        const TargetAsmInfo *T, unsigned OL, bool V);
>
>   public:
>     virtual ~AsmPrinter();
>
> Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Tue Apr 28  
> 19:15:41 2009
> @@ -81,7 +81,7 @@
>   void EndFunction(MachineFunction *MF);
>
>   /// ValidDebugInfo - Return true if V represents valid debug info  
> value.
> -  bool ValidDebugInfo(Value *V, bool FastISel);
> +  bool ValidDebugInfo(Value *V, unsigned OptLevel);
>
>   /// RecordSourceLine - Register a source line with debug info.  
> Returns a
>   /// unique label ID used to generate a label and provide  
> correspondence to
>
> Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h  
> (original)
> +++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Tue  
> Apr 28 19:15:41 2009
> @@ -42,11 +42,11 @@
>       llvm::linkOcamlGC();
>       llvm::linkShadowStackGC();
>
> -      (void) llvm::createBURRListDAGScheduler(NULL, false);
> -      (void) llvm::createTDRRListDAGScheduler(NULL, false);
> -      (void) llvm::createTDListDAGScheduler(NULL, false);
> -      (void) llvm::createFastDAGScheduler(NULL, false);
> -      (void) llvm::createDefaultScheduler(NULL, false);
> +      (void) llvm::createBURRListDAGScheduler(NULL, 3);
> +      (void) llvm::createTDRRListDAGScheduler(NULL, 3);
> +      (void) llvm::createTDListDAGScheduler(NULL, 3);
> +      (void) llvm::createFastDAGScheduler(NULL, 3);
> +      (void) llvm::createDefaultScheduler(NULL, 3);
>
>     }
>   } ForceCodegenLinking; // Force link by creating a global  
> definition.
>
> Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Tue Apr 28  
> 19:15:41 2009
> @@ -32,7 +32,7 @@
>
> class RegisterScheduler : public MachinePassRegistryNode {
> public:
> -  typedef ScheduleDAGSDNodes *(*FunctionPassCtor) 
> (SelectionDAGISel*, bool);
> +  typedef ScheduleDAGSDNodes *(*FunctionPassCtor) 
> (SelectionDAGISel*, unsigned);
>
>   static MachinePassRegistry Registry;
>
> @@ -64,27 +64,27 @@
> /// createBURRListDAGScheduler - This creates a bottom up register  
> usage
> /// reduction list scheduler.
> ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
> -                                               bool Fast);
> +                                               unsigned OptLevel);
>
> /// createTDRRListDAGScheduler - This creates a top down register  
> usage
> /// reduction list scheduler.
> ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
> -                                               bool Fast);
> +                                               unsigned OptLevel);
>
> /// createTDListDAGScheduler - This creates a top-down list  
> scheduler with
> /// a hazard recognizer.
> ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
> -                                             bool Fast);
> +                                             unsigned OptLevel);
>
> /// createFastDAGScheduler - This creates a "fast" scheduler.
> ///
> ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
> -                                           bool Fast);
> +                                           unsigned OptLevel);
>
> /// createDefaultScheduler - This creates an instruction scheduler  
> appropriate
> /// for the target.
> ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
> -                                           bool Fast);
> +                                           unsigned OptLevel);
>
> } // end namespace llvm
>
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Apr 28  
> 19:15:41 2009
> @@ -202,7 +202,7 @@
>   /// certain types of nodes together, or eliminating superfluous  
> nodes.  The
>   /// Level argument controls whether Combine is allowed to produce  
> nodes and
>   /// types that are illegal on the target.
> -  void Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast);
> +  void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned  
> OptLevel);
>
>   /// LegalizeTypes - This transforms the SelectionDAG into a  
> SelectionDAG that
>   /// only uses types natively supported by the target.  Returns  
> "true" if it
> @@ -218,7 +218,7 @@
>   ///
>   /// Note that this is an involved process that may invalidate  
> pointers into
>   /// the graph.
> -  void Legalize(bool TypesNeedLegalizing, bool Fast);
> +  void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
>
>   /// RemoveDeadNodes - This method deletes all unreachable nodes in  
> the
>   /// SelectionDAG.
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Tue Apr 28  
> 19:15:41 2009
> @@ -51,10 +51,10 @@
>   MachineBasicBlock *BB;
>   AliasAnalysis *AA;
>   GCFunctionInfo *GFI;
> -  bool Fast;
> +  unsigned OptLevel;
>   static char ID;
>
> -  explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
> +  explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
>   virtual ~SelectionDAGISel();
>
>   TargetLowering &getTargetLowering() { return TLI; }
>
> Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetMachine.h Tue Apr 28  
> 19:15:41 2009
> @@ -213,7 +213,7 @@
>   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
>                                                raw_ostream &,
>                                                CodeGenFileType,
> -                                               bool /*Fast*/) {
> +                                               unsigned /* OptLevel  
> */) {
>     return FileModel::None;
>   }
>
> @@ -222,7 +222,8 @@
>   /// used to finish up adding passes to emit the file, if necessary.
>   ///
>   virtual bool addPassesToEmitFileFinish(PassManagerBase &,
> -                                         MachineCodeEmitter *,  
> bool /*Fast*/) {
> +                                         MachineCodeEmitter *,
> +                                         unsigned /* OptLevel */) {
>     return true;
>   }
>
> @@ -234,7 +235,7 @@
>   ///
>   virtual bool addPassesToEmitMachineCode(PassManagerBase &,
>                                           MachineCodeEmitter &,
> -                                          bool /*Fast*/) {
> +                                          unsigned /* OptLevel */) {
>     return true;
>   }
>
> @@ -243,7 +244,8 @@
>   /// use this.
>   virtual bool WantsWholeFile() const { return false; }
>   virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
> -                                        CodeGenFileType, bool / 
> *Fast*/) {
> +                                        CodeGenFileType,
> +                                        unsigned /* OptLevel */) {
>     return true;
>   }
> };
> @@ -258,16 +260,16 @@
>   /// addCommonCodeGenPasses - Add standard LLVM codegen passes used  
> for
>   /// both emitting to assembly files or machine code output.
>   ///
> -  bool addCommonCodeGenPasses(PassManagerBase &, bool /*Fast*/);
> +  bool addCommonCodeGenPasses(PassManagerBase &, unsigned /*  
> OptLevel */);
>
> public:
>
>   /// addPassesToEmitFile - Add passes to the specified pass manager  
> to get the
>   /// specified file emitted.  Typically this will involve several  
> steps of code
> -  /// generation.  If Fast is set to true, the code generator  
> should emit code
> -  /// as fast as possible, though the generated code may be less  
> efficient.
> -  /// This method should return FileModel::Error if emission of  
> this file type
> -  /// is not supported.
> +  /// generation.  If OptLevel is 0, the code generator should emit  
> code as fast
> +  /// as possible, though the generated code may be less  
> efficient.  This method
> +  /// should return FileModel::Error if emission of this file type  
> is not
> +  /// supported.
>   ///
>   /// The default implementation of this method adds components from  
> the
>   /// LLVM retargetable code generator, invoking the methods below  
> to get
> @@ -276,14 +278,15 @@
>   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
>                                                raw_ostream &Out,
>                                                CodeGenFileType  
> FileType,
> -                                               bool Fast);
> +                                               unsigned OptLevel);
>
>   /// addPassesToEmitFileFinish - If the passes to emit the  
> specified file had
>   /// to be split up (e.g., to add an object writer pass), this  
> method can be
>   /// used to finish up adding passes to emit the file, if necessary.
>   ///
>   virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
> -                                         MachineCodeEmitter *MCE,  
> bool Fast);
> +                                         MachineCodeEmitter *MCE,
> +                                         unsigned OptLevel);
>
>   /// addPassesToEmitMachineCode - Add passes to the specified pass  
> manager to
>   /// get machine code emitted.  This uses a MachineCodeEmitter  
> object to handle
> @@ -292,21 +295,22 @@
>   /// not supported.
>   ///
>   virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
> -                                          MachineCodeEmitter &MCE,  
> bool Fast);
> +                                          MachineCodeEmitter &MCE,
> +                                          unsigned OptLevel);
>
>   /// Target-Independent Code Generator Pass Configuration Options.
>
>   /// addInstSelector - This method should add any "last minute"  
> LLVM->LLVM
>   /// passes, then install an instruction selector pass, which  
> converts from
>   /// LLVM code to machine instructions.
> -  virtual bool addInstSelector(PassManagerBase &, bool /*Fast*/) {
> +  virtual bool addInstSelector(PassManagerBase &, unsigned /*  
> OptLevel */) {
>     return true;
>   }
>
>   /// addPreRegAllocPasses - This method may be implemented by  
> targets that want
>   /// to run passes immediately before register allocation. This  
> should return
>   /// true if -print-machineinstrs should print after these passes.
> -  virtual bool addPreRegAlloc(PassManagerBase &, bool /*Fast*/) {
> +  virtual bool addPreRegAlloc(PassManagerBase &, unsigned /*  
> OptLevel */) {
>     return false;
>   }
>
> @@ -314,14 +318,14 @@
>   /// want to run passes after register allocation but before prolog- 
> epilog
>   /// insertion.  This should return true if -print-machineinstrs  
> should print
>   /// after these passes.
> -  virtual bool addPostRegAlloc(PassManagerBase &, bool /*Fast*/) {
> +  virtual bool addPostRegAlloc(PassManagerBase &, unsigned /*  
> OptLevel */) {
>     return false;
>   }
>
>   /// addPreEmitPass - This pass may be implemented by targets that  
> want to run
>   /// passes immediately before machine code is emitted.  This  
> should return
>   /// true if -print-machineinstrs should print out the code after  
> the passes.
> -  virtual bool addPreEmitPass(PassManagerBase &, bool /*Fast*/) {
> +  virtual bool addPreEmitPass(PassManagerBase &, unsigned /*  
> OptLevel */) {
>     return false;
>   }
>
> @@ -329,7 +333,7 @@
>   /// addAssemblyEmitter - This pass should be overridden by the  
> target to add
>   /// the asmprinter, if asm emission is supported.  If this is not  
> supported,
>   /// 'true' should be returned.
> -  virtual bool addAssemblyEmitter(PassManagerBase &, bool /*Fast*/,
> +  virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /*  
> OptLevel */,
>                                   bool /* VerboseAsmDefault */,  
> raw_ostream &) {
>     return true;
>   }
> @@ -337,7 +341,7 @@
>   /// addCodeEmitter - This pass should be overridden by the target  
> to add a
>   /// code emitter, if supported.  If this is not supported, 'true'  
> should be
>   /// returned. If DumpAsm is true, the generated assembly is  
> printed to cerr.
> -  virtual bool addCodeEmitter(PassManagerBase &, bool /*Fast*/,
> +  virtual bool addCodeEmitter(PassManagerBase &, unsigned /*  
> OptLevel */,
>                               bool /*DumpAsm*/, MachineCodeEmitter  
> &) {
>     return true;
>   }
> @@ -346,7 +350,7 @@
>   /// a code emitter (without setting flags), if supported.  If this  
> is not
>   /// supported, 'true' should be returned.  If DumpAsm is true, the  
> generated
>   /// assembly is printed to cerr.
> -  virtual bool addSimpleCodeEmitter(PassManagerBase &, bool /*Fast*/,
> +  virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /*  
> OptLevel */,
>                                     bool /*DumpAsm*/,  
> MachineCodeEmitter &) {
>     return true;
>   }
>
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -42,8 +42,8 @@
>
> char AsmPrinter::ID = 0;
> AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
> -                       const TargetAsmInfo *T, bool F, bool VDef)
> -  : MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o),
> +                       const TargetAsmInfo *T, unsigned OL, bool  
> VDef)
> +  : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
>     TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
>     IsInTextSection(false)
> {
>
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -3351,7 +3351,7 @@
>   }
>
>   /// ValidDebugInfo - Return true if V represents valid debug info  
> value.
> -  bool ValidDebugInfo(Value *V, bool FastISel) {
> +  bool ValidDebugInfo(Value *V, unsigned OptLevel) {
>     if (!V)
>       return false;
>
> @@ -3393,7 +3393,7 @@
>     case DW_TAG_lexical_block:
>       /// FIXME. This interfers with the qualitfy of generated code  
> when
>       /// during optimization.
> -      if (FastISel == false)
> +      if (OptLevel != 0)
>         return false;
>     default:
>       break;
> @@ -3574,7 +3574,7 @@
>       return 0;
>
>     SmallVector<DbgScope *, 2> &Scopes = I->second;
> -    if (Scopes.empty()) return 0;
> +    assert(!Scopes.empty() && "We should have at least one debug  
> scope!");
>     DbgScope *Scope = Scopes.back(); Scopes.pop_back();
>     unsigned ID = MMI->NextLabelID();
>     MMI->RecordUsedDbgLabel(ID);
> @@ -4731,8 +4731,8 @@
> }
>
> /// ValidDebugInfo - Return true if V represents valid debug info  
> value.
> -bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) {
> -  return DD && DD->ValidDebugInfo(V, FastISel);
> +bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
> +  return DD && DD->ValidDebugInfo(V, OptLevel);
> }
>
> /// RecordSourceLine - Records location information and associates  
> it with a
>
> Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Tue Apr 28 19:15:41  
> 2009
> @@ -55,9 +55,9 @@
> LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
>                                        raw_ostream &Out,
>                                        CodeGenFileType FileType,
> -                                       bool Fast) {
> +                                       unsigned OptLevel) {
>   // Add common CodeGen passes.
> -  if (addCommonCodeGenPasses(PM, Fast))
> +  if (addCommonCodeGenPasses(PM, OptLevel))
>     return FileModel::Error;
>
>   // Fold redundant debug labels.
> @@ -66,17 +66,17 @@
>   if (PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
> -  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
> +  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
> -  if (!Fast)
> +  if (OptLevel != 0)
>     PM.add(createLoopAlignerPass());
>
>   switch (FileType) {
>   default:
>     break;
>   case TargetMachine::AssemblyFile:
> -    if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(), Out))
> +    if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(),  
> Out))
>       return FileModel::Error;
>     return FileModel::AsmFile;
>   case TargetMachine::ObjectFile:
> @@ -94,9 +94,9 @@
> /// finish up adding passes to emit the file, if necessary.
> bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
>                                                   MachineCodeEmitter  
> *MCE,
> -                                                  bool Fast) {
> +                                                  unsigned  
> OptLevel) {
>   if (MCE)
> -    addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
> +    addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
>
>   PM.add(createGCInfoDeleter());
>
> @@ -114,15 +114,15 @@
> ///
> bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase  
> &PM,
>                                                     
> MachineCodeEmitter &MCE,
> -                                                   bool Fast) {
> +                                                   unsigned  
> OptLevel) {
>   // Add common CodeGen passes.
> -  if (addCommonCodeGenPasses(PM, Fast))
> +  if (addCommonCodeGenPasses(PM, OptLevel))
>     return true;
>
> -  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
> +  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
> -  addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
> +  addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
>
>   PM.add(createGCInfoDeleter());
>
> @@ -135,11 +135,12 @@
> /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
> /// both emitting to assembly files or machine code output.
> ///
> -bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,  
> bool Fast) {
> +bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
> +                                               unsigned OptLevel) {
>   // Standard LLVM-Level Passes.
>
>   // Run loop strength reduction before anything else.
> -  if (!Fast) {
> +  if (OptLevel != 0) {
>     PM.add(createLoopStrengthReducePass(getTargetLowering()));
>     if (PrintLSR)
>       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n",  
> &errs()));
> @@ -153,7 +154,7 @@
>   // Make sure that no unreachable blocks are instruction selected.
>   PM.add(createUnreachableBlockEliminationPass());
>
> -  if (!Fast)
> +  if (OptLevel != 0)
>     PM.add(createCodeGenPreparePass(getTargetLowering()));
>
>   PM.add(createStackProtectorPass(getTargetLowering()));
> @@ -167,38 +168,38 @@
>
>   // Enable FastISel with -fast, but allow that to be overridden.
>   if (EnableFastISelOption == cl::BOU_TRUE ||
> -      (Fast && EnableFastISelOption != cl::BOU_FALSE))
> +      (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
>     EnableFastISel = true;
>
>   // Ask the target for an isel.
> -  if (addInstSelector(PM, Fast))
> +  if (addInstSelector(PM, OptLevel))
>     return true;
>
>   // Print the instruction selected machine code...
>   if (PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
> -  if (!Fast) {
> +  if (OptLevel != 0) {
>     PM.add(createMachineLICMPass());
>     PM.add(createMachineSinkingPass());
>   }
>
>   // Run pre-ra passes.
> -  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
> +  if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
>   // Perform register allocation.
>   PM.add(createRegisterAllocator());
>
>   // Perform stack slot coloring.
> -  if (!Fast)
> +  if (OptLevel != 0)
>     PM.add(createStackSlotColoringPass());
>
>   if (PrintMachineCode)  // Print the register-allocated code
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
>   // Run post-ra passes.
> -  if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
> +  if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
>   if (PrintMachineCode)
> @@ -216,7 +217,7 @@
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
>   // Second pass scheduler.
> -  if (!Fast && !DisablePostRAScheduler) {
> +  if (OptLevel != 0 && !DisablePostRAScheduler) {
>     PM.add(createPostRAScheduler());
>
>     if (PrintMachineCode)
> @@ -224,7 +225,7 @@
>   }
>
>   // Branch folding must be run after regalloc and prolog/epilog  
> insertion.
> -  if (!Fast)
> +  if (OptLevel != 0)
>     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
>
>   if (PrintMachineCode)
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -57,9 +57,9 @@
>     SelectionDAG &DAG;
>     const TargetLowering &TLI;
>     CombineLevel Level;
> +    unsigned OptLevel;
>     bool LegalOperations;
>     bool LegalTypes;
> -    bool Fast;
>
>     // Worklist of all of the nodes that need to be simplified.
>     std::vector<SDNode*> WorkList;
> @@ -254,13 +254,13 @@
>     }
>
> public:
> -    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
> +    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
>       : DAG(D),
>         TLI(D.getTargetLoweringInfo()),
>         Level(Unrestricted),
> +        OptLevel(OL),
>         LegalOperations(false),
>         LegalTypes(false),
> -        Fast(fast),
>         AA(A) {}
>
>     /// Run - runs the dag combiner on all nodes in the work list
> @@ -4784,7 +4784,7 @@
>   SDValue Ptr   = LD->getBasePtr();
>
>   // Try to infer better alignment information than the load already  
> has.
> -  if (!Fast && LD->isUnindexed()) {
> +  if (OptLevel != 0 && LD->isUnindexed()) {
>     if (unsigned Align = InferAlignment(Ptr, DAG)) {
>       if (Align > LD->getAlignment())
>         return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc 
> (),
> @@ -4904,7 +4904,7 @@
>   SDValue Ptr   = ST->getBasePtr();
>
>   // Try to infer better alignment information than the store  
> already has.
> -  if (!Fast && ST->isUnindexed()) {
> +  if (OptLevel != 0 && ST->isUnindexed()) {
>     if (unsigned Align = InferAlignment(Ptr, DAG)) {
>       if (Align > ST->getAlignment())
>         return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
> @@ -6084,8 +6084,9 @@
>
> // SelectionDAG::Combine - This is the entry point for the file.
> //
> -void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,  
> bool Fast) {
> +void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
> +                           unsigned OptLevel) {
>   /// run - This is the main entry point to this class.
>   ///
> -  DAGCombiner(*this, AA, Fast).Run(Level);
> +  DAGCombiner(*this, AA, OptLevel).Run(Level);
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -327,7 +327,7 @@
>   default: break;
>   case Intrinsic::dbg_stoppoint: {
>     DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
> -    if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) {
> +    if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
>       DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
>       std::string Dir, FN;
>       unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
> @@ -344,7 +344,7 @@
>   }
>   case Intrinsic::dbg_region_start: {
>     DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
> -    if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) {
> +    if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
>       unsigned ID =
>         DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext 
> ()));
>       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
> @@ -354,7 +354,7 @@
>   }
>   case Intrinsic::dbg_region_end: {
>     DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
> -    if (DW && DW->ValidDebugInfo(REI->getContext(), true)) {
> +    if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
>      unsigned ID = 0;
>      DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
>      if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction 
> ())) {
> @@ -380,7 +380,7 @@
>     DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
>     Value *SP = FSI->getSubprogram();
>
> -    if (DW->ValidDebugInfo(SP, true)) {
> +    if (DW->ValidDebugInfo(SP, 0)) {
>       // llvm.dbg.func.start implicitly defines a dbg_stoppoint  
> which is what
>       // (most?) gdb expects.
>       DebugLoc PrevLoc = DL;
> @@ -425,7 +425,7 @@
>   case Intrinsic::dbg_declare: {
>     DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
>     Value *Variable = DI->getVariable();
> -    if (DW && DW->ValidDebugInfo(Variable, true)) {
> +    if (DW && DW->ValidDebugInfo(Variable, 0)) {
>       // Determine the address of the declared object.
>       Value *Address = DI->getAddress();
>       if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -55,8 +55,8 @@
> class VISIBILITY_HIDDEN SelectionDAGLegalize {
>   TargetLowering &TLI;
>   SelectionDAG &DAG;
> +  unsigned OptLevel;
>   bool TypesNeedLegalizing;
> -  bool Fast;
>
>   // Libcall insertion helpers.
>
> @@ -139,7 +139,7 @@
>
> public:
>   explicit SelectionDAGLegalize(SelectionDAG &DAG, bool  
> TypesNeedLegalizing,
> -                                bool fast);
> +                                unsigned ol);
>
>   /// getTypeAction - Return how we should legalize values of this  
> type, either
>   /// it is already legal or we need to expand it into multiple  
> registers of
> @@ -345,9 +345,9 @@
> }
>
> SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
> -                                           bool types, bool fast)
> -  : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing 
> (types),
> -    Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
> +                                           bool types, unsigned ol)
> +  : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
> +    TypesNeedLegalizing(types), ValueTypeActions 
> (TLI.getValueTypeActions()) {
>   assert(MVT::LAST_VALUETYPE <= 32 &&
>          "Too many value types for ValueTypeActions to hold!");
> }
> @@ -1271,7 +1271,7 @@
>         unsigned Line = DSP->getLine();
>         unsigned Col = DSP->getColumn();
>
> -        if (Fast) {
> +        if (OptLevel == 0) {
>           // A bit self-referential to have DebugLoc on Debug_Loc  
> nodes, but it
>           // won't hurt anything.
>           if (useDEBUG_LOC) {
> @@ -8566,9 +8566,9 @@
>
> // SelectionDAG::Legalize - This is the entry point for the file.
> //
> -void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
> +void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned  
> OptLevel) {
>   /// run - This is the main entry point to this class.
>   ///
> -  SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG 
> ();
> +  SelectionDAGLegalize(*this, TypesNeedLegalizing,  
> OptLevel).LegalizeDAG();
> }
>
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Tue Apr  
> 28 19:15:41 2009
> @@ -630,6 +630,6 @@
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> llvm::ScheduleDAGSDNodes *
> -llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
> +llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
>   return new ScheduleDAGFast(*IS->MF);
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Tue Apr  
> 28 19:15:41 2009
> @@ -261,7 +261,7 @@
> /// new hazard recognizer. This scheduler takes ownership of the  
> hazard
> /// recognizer and deletes it when done.
> ScheduleDAGSDNodes *
> -llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) {
> +llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>   return new ScheduleDAGList(*IS->MF,
>                              new LatencyPriorityQueue(),
>                              IS->CreateTargetHazardRecognizer());
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue  
> Apr 28 19:15:41 2009
> @@ -1505,7 +1505,7 @@
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> llvm::ScheduleDAGSDNodes *
> -llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
> +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>   const TargetMachine &TM = IS->TM;
>   const TargetInstrInfo *TII = TM.getInstrInfo();
>   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
> @@ -1519,7 +1519,7 @@
> }
>
> llvm::ScheduleDAGSDNodes *
> -llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
> +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
>   const TargetMachine &TM = IS->TM;
>   const TargetInstrInfo *TII = TM.getInstrInfo();
>   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Tue  
> Apr 28 19:15:41 2009
> @@ -3910,9 +3910,9 @@
>   case Intrinsic::dbg_stoppoint: {
>     DwarfWriter *DW = DAG.getDwarfWriter();
>     DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
> -    if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
> +    if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
>       MachineFunction &MF = DAG.getMachineFunction();
> -      if (Fast)
> +      if (OptLevel == 0)
>         DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
>                                         SPI.getLine(),
>                                         SPI.getColumn(),
> @@ -3930,7 +3930,8 @@
>   case Intrinsic::dbg_region_start: {
>     DwarfWriter *DW = DAG.getDwarfWriter();
>     DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
> -    if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
> +
> +    if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) {
>       unsigned LabelID =
>         DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
>       DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
> @@ -3942,8 +3943,8 @@
>   case Intrinsic::dbg_region_end: {
>     DwarfWriter *DW = DAG.getDwarfWriter();
>     DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
> -    if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
>
> +    if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) {
>       MachineFunction &MF = DAG.getMachineFunction();
>       DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
>       std::string SPName;
> @@ -3952,7 +3953,7 @@
>           && strcmp(SPName.c_str(), MF.getFunction()->getNameStart 
> ())) {
>           // This is end of inlined function. Debugging information  
> for
>           // inlined function is not handled yet (only supported by  
> FastISel).
> -        if (Fast) {
> +        if (OptLevel == 0) {
>           unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
>           if (ID != 0)
>             // Returned ID is 0 if this is unbalanced "end of inlined
> @@ -3978,9 +3979,9 @@
>     if (!DW) return 0;
>     DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
>     Value *SP = FSI.getSubprogram();
> -    if (SP && DW->ValidDebugInfo(SP, Fast)) {
> -        MachineFunction &MF = DAG.getMachineFunction();
> -      if (Fast) {
> +    if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
> +      MachineFunction &MF = DAG.getMachineFunction();
> +      if (OptLevel == 0) {
>         // llvm.dbg.func.start implicitly defines a dbg_stoppoint  
> which is what
>         // (most?) gdb expects.
>         DebugLoc PrevLoc = CurDebugLoc;
> @@ -4051,11 +4052,11 @@
>     return 0;
>   }
>   case Intrinsic::dbg_declare: {
> -    if (Fast) {
> +    if (OptLevel == 0) {
>       DwarfWriter *DW = DAG.getDwarfWriter();
>       DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
>       Value *Variable = DI.getVariable();
> -      if (DW && DW->ValidDebugInfo(Variable, Fast))
> +      if (DW && DW->ValidDebugInfo(Variable, OptLevel))
>         DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot 
> (),
>                                 getValue(DI.getAddress()), getValue 
> (Variable)));
>     } else {
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Tue Apr  
> 28 19:15:41 2009
> @@ -355,17 +355,17 @@
>   ///
>   FunctionLoweringInfo &FuncInfo;
>
> -  /// Fast - We are in -fast mode.
> +  /// OptLevel - What optimization level we're generating code for.
>   ///
> -  bool Fast;
> +  unsigned OptLevel;
>
>   /// GFI - Garbage collection metadata for the function.
>   GCFunctionInfo *GFI;
>
>   SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
> -                       FunctionLoweringInfo &funcinfo, bool fast)
> +                       FunctionLoweringInfo &funcinfo, unsigned ol)
>     : CurDebugLoc(DebugLoc::getUnknownLoc()),
> -      TLI(tli), DAG(dag), FuncInfo(funcinfo), Fast(fast) {
> +      TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
>   }
>
>   void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Apr  
> 28 19:15:41 2009
> @@ -136,16 +136,16 @@
>   /// createDefaultScheduler - This creates an instruction scheduler  
> appropriate
>   /// for the target.
>   ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
> -                                             bool Fast) {
> +                                             unsigned OptLevel) {
>     const TargetLowering &TLI = IS->getTargetLowering();
>
> -    if (Fast)
> -      return createFastDAGScheduler(IS, Fast);
> +    if (OptLevel == 0)
> +      return createFastDAGScheduler(IS, OptLevel);
>     if (TLI.getSchedulingPreference() ==  
> TargetLowering::SchedulingForLatency)
> -      return createTDListDAGScheduler(IS, Fast);
> +      return createTDListDAGScheduler(IS, OptLevel);
>     assert(TLI.getSchedulingPreference() ==
>          TargetLowering::SchedulingForRegPressure && "Unknown sched  
> type!");
> -    return createBURRListDAGScheduler(IS, Fast);
> +    return createBURRListDAGScheduler(IS, OptLevel);
>   }
> }
>
> @@ -262,13 +262,13 @@
> // SelectionDAGISel code
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> -SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
> +SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
>   FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
>   FuncInfo(new FunctionLoweringInfo(TLI)),
>   CurDAG(new SelectionDAG(TLI, *FuncInfo)),
> -  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)),
> +  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)),
>   GFI(),
> -  Fast(fast),
> +  OptLevel(OL),
>   DAGSize(0)
> {}
>
> @@ -576,9 +576,9 @@
>   // Run the DAG combiner in pre-legalize mode.
>   if (TimePassesIsEnabled) {
>     NamedRegionTimer T("DAG Combining 1", GroupName);
> -    CurDAG->Combine(Unrestricted, *AA, Fast);
> +    CurDAG->Combine(Unrestricted, *AA, OptLevel);
>   } else {
> -    CurDAG->Combine(Unrestricted, *AA, Fast);
> +    CurDAG->Combine(Unrestricted, *AA, OptLevel);
>   }
>
>   DOUT << "Optimized lowered selection DAG:\n";
> @@ -608,9 +608,9 @@
>       // Run the DAG combiner in post-type-legalize mode.
>       if (TimePassesIsEnabled) {
>         NamedRegionTimer T("DAG Combining after legalize types",  
> GroupName);
> -        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
> +        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
>       } else {
> -        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
> +        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
>       }
>
>       DOUT << "Optimized type-legalized selection DAG:\n";
> @@ -622,9 +622,9 @@
>
>   if (TimePassesIsEnabled) {
>     NamedRegionTimer T("DAG Legalization", GroupName);
> -    CurDAG->Legalize(DisableLegalizeTypes, Fast);
> +    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
>   } else {
> -    CurDAG->Legalize(DisableLegalizeTypes, Fast);
> +    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
>   }
>
>   DOUT << "Legalized selection DAG:\n";
> @@ -635,9 +635,9 @@
>   // Run the DAG combiner in post-legalize mode.
>   if (TimePassesIsEnabled) {
>     NamedRegionTimer T("DAG Combining 2", GroupName);
> -    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
> +    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
>   } else {
> -    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
> +    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
>   }
>
>   DOUT << "Optimized legalized selection DAG:\n";
> @@ -645,7 +645,7 @@
>
>   if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
>
> -  if (!Fast)
> +  if (OptLevel != 0)
>     ComputeLiveOutVRegInfo();
>
>   // Third, instruction select all of the operations to machine  
> code, adding the
> @@ -1082,7 +1082,7 @@
>     RegisterScheduler::setDefault(Ctor);
>   }
>
> -  return Ctor(this, Fast);
> +  return Ctor(this, OptLevel);
> }
>
> ScheduleHazardRecognizer  
> *SelectionDAGISel::CreateTargetHazardRecognizer() {
>
> Modified: llvm/trunk/lib/Target/ARM/ARM.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARM.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARM.h Tue Apr 28 19:15:41 2009
> @@ -91,7 +91,7 @@
> FunctionPass *createARMISelDag(ARMTargetMachine &TM);
> FunctionPass *createARMCodePrinterPass(raw_ostream &O,
>                                        ARMTargetMachine &TM,
> -                                       bool Fast, bool Verbose);
> +                                       unsigned OptLevel, bool  
> Verbose);
> FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
>                                        MachineCodeEmitter &MCE);
> FunctionPass *createARMLoadStoreOptimizationPass();
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -138,35 +138,37 @@
>
>
> // Pass Pipeline Configuration
> -bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,  
> unsigned OptLevel) {
>   PM.add(createARMISelDag(*this));
>   return false;
> }
>
> -bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, bool  
> Fast) {
> +bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel) {
>   // FIXME: temporarily disabling load / store optimization pass for  
> Thumb mode.
> -  if (!Fast && !DisableLdStOpti && !Subtarget.isThumb())
> +  if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
>     PM.add(createARMLoadStoreOptimizationPass());
>
> -  if (!Fast && !DisableIfConversion && !Subtarget.isThumb())
> +  if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
>     PM.add(createIfConverterPass());
>
>   PM.add(createARMConstantIslandPass());
>   return true;
> }
>
> -bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool  
> Fast,
> -                                          bool Verbose, raw_ostream  
> &Out) {
> +bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                          unsigned OptLevel,
> +                                          bool Verbose,
> +                                          raw_ostream &Out) {
>   // Output assembly language.
>   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>   if (AsmPrinterCtor)
> -    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
> +    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>
>   return false;
> }
>
>
> -bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
> +bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                       bool DumpAsm,  
> MachineCodeEmitter &MCE) {
>   // FIXME: Move this to TargetJITInfo!
>   if (DefRelocModel == Reloc::Default)
> @@ -177,20 +179,22 @@
>   if (DumpAsm) {
>     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>     if (AsmPrinterCtor)
> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>   }
>
>   return false;
> }
>
> -bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,  
> bool Fast,
> -                                        bool DumpAsm,  
> MachineCodeEmitter &MCE) {
> +bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
> +                                            unsigned OptLevel,
> +                                            bool DumpAsm,
> +                                            MachineCodeEmitter  
> &MCE) {
>   // Machine code emitter pass for ARM.
>   PM.add(createARMCodeEmitterPass(*this, MCE));
>   if (DumpAsm) {
>     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>     if (AsmPrinterCtor)
> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>   }
>
>   return false;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Tue Apr 28 19:15:41  
> 2009
> @@ -41,7 +41,7 @@
>   // set this functions to ctor pointer at startup time if they are  
> linked in.
>   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>                                             ARMTargetMachine &tm,
> -                                            bool fast, bool verbose);
> +                                            unsigned OptLevel, bool  
> verbose);
>   static AsmPrinterCtorFn AsmPrinterCtor;
>
> public:
> @@ -69,13 +69,13 @@
>   virtual const TargetAsmInfo *createTargetAsmInfo() const;
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
>                               bool DumpAsm, MachineCodeEmitter &MCE);
> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                     bool DumpAsm, MachineCodeEmitter  
> &MCE);
> };
>
>
> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Tue Apr  
> 28 19:15:41 2009
> @@ -80,9 +80,9 @@
>     /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
>     bool InCPMode;
>   public:
> -    ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                  const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V), DW(0), MMI(NULL), AFI(NULL), MCP 
> (NULL),
> +    explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
> +                           const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL),  
> MCP(NULL),
>         InCPMode(false) {
>       Subtarget = &TM.getSubtarget<ARMSubtarget>();
>     }
> @@ -1061,8 +1061,8 @@
> ///
> FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
>                                              ARMTargetMachine &tm,
> -                                             bool fast, bool  
> verbose) {
> -  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                             unsigned OptLevel,  
> bool verbose) {
> +  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,  
> verbose);
> }
>
> namespace {
>
> Modified: llvm/trunk/lib/Target/Alpha/Alpha.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/Alpha.h (original)
> +++ llvm/trunk/lib/Target/Alpha/Alpha.h Tue Apr 28 19:15:41 2009
> @@ -26,7 +26,7 @@
>   FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
>   FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
>                                            TargetMachine &TM,
> -                                           bool Fast, bool Verbose);
> +                                           unsigned OptLevel, bool  
> Verbose);
>   FunctionPass *createAlphaPatternInstructionSelector(TargetMachine  
> &TM);
>   FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
>                                            MachineCodeEmitter &MCE);
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -76,31 +76,34 @@
> // Pass Pipeline Configuration
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> -bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
> +                                         unsigned OptLevel) {
>   PM.add(createAlphaISelDag(*this));
>   return false;
> }
> -bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, bool  
> Fast) {
> +bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
> +                                        unsigned OptLevel) {
>   // Must run branch selection immediately preceding the asm printer
>   PM.add(createAlphaBranchSelectionPass());
>   return false;
> }
> -bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,  
> bool Fast,
> +bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                            unsigned OptLevel,
>                                             bool Verbose,
>                                             raw_ostream &Out) {
>   PM.add(createAlphaLLRPPass(*this));
> -  PM.add(createAlphaCodePrinterPass(Out, *this, Fast, Verbose));
> +  PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
> -bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, bool  
> Fast,
> +bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,  
> unsigned OptLevel,
>                                         bool DumpAsm,  
> MachineCodeEmitter &MCE) {
>   PM.add(createAlphaCodeEmitterPass(*this, MCE));
>   if (DumpAsm)
> -    PM.add(createAlphaCodePrinterPass(errs(), *this, Fast, true));
> +    PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel,  
> true));
>   return false;
> }
> bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
> -                                              bool Fast, bool  
> DumpAsm,
> +                                              unsigned OptLevel,  
> bool DumpAsm,
>                                               MachineCodeEmitter  
> &MCE) {
> -  return addCodeEmitter(PM, Fast, DumpAsm, MCE);
> +  return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
> }
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Tue Apr 28  
> 19:15:41 2009
> @@ -58,13 +58,13 @@
>   static unsigned getModuleMatchQuality(const Module &M);
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
>                               bool DumpAsm, MachineCodeEmitter &MCE);
> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                     bool DumpAsm, MachineCodeEmitter  
> &MCE);
> };
>
>
> Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Tue  
> Apr 28 19:15:41 2009
> @@ -36,9 +36,9 @@
>     /// Unique incrementer for label values for referencing Global  
> values.
>     ///
>
> -    AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
> -                    const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(o, tm, T, F, V) {}
> +    explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
> +                             const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(o, tm, T, OL, V) {}
>
>     virtual const char *getPassName() const {
>       return "Alpha Assembly Printer";
> @@ -68,8 +68,9 @@
> ///
> FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
>                                                TargetMachine &tm,
> -                                               bool fast, bool  
> verbose) {
> -  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                               unsigned OptLevel,
> +                                               bool verbose) {
> +  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> OptLevel, verbose);
> }
>
> #include "AlphaGenAsmWriter.inc"
>
> Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
> +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Tue Apr 28 19:15:41  
> 2009
> @@ -3587,7 +3587,7 @@
> bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>                                               raw_ostream &o,
>                                               CodeGenFileType  
> FileType,
> -                                              bool Fast) {
> +                                              unsigned OptLevel) {
>   if (FileType != TargetMachine::AssemblyFile) return true;
>
>   PM.add(createGCLoweringPass());
>
> Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Tue Apr 28  
> 19:15:41 2009
> @@ -27,7 +27,8 @@
>
>   virtual bool WantsWholeFile() const { return true; }
>   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream  
> &Out,
> -                                        CodeGenFileType FileType,  
> bool Fast);
> +                                        CodeGenFileType FileType,
> +                                        unsigned OptLevel);
>
>   // This class always works, but must be requested explicitly on
>   // llc command line.
>
> Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Tue  
> Apr 28 19:15:41 2009
> @@ -48,9 +48,9 @@
>   class VISIBILITY_HIDDEN SPUAsmPrinter : public AsmPrinter {
>     std::set<std::string> FnStubs, GVStubs;
>   public:
> -    SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                  const TargetAsmInfo *T, bool F, bool V) :
> -      AsmPrinter(O, TM, T, F, V) {}
> +    explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
> +                           const TargetAsmInfo *T, unsigned OL,  
> bool V) :
> +      AsmPrinter(O, TM, T, OL, V) {}
>
>     virtual const char *getPassName() const {
>       return "STI CBEA SPU Assembly Printer";
> @@ -615,6 +615,6 @@
> ///
> FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
>                                             SPUTargetMachine &tm,
> -                                            bool fast, bool  
> verbose) {
> -  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                            unsigned OptLevel, bool  
> verbose) {
> +  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> OptLevel, verbose);
> }
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPU.h Tue Apr 28 19:15:41 2009
> @@ -25,7 +25,7 @@
>   FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
>   FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
>                                         SPUTargetMachine &tm,
> -                                        bool fast, bool verbose);
> +                                        unsigned OptLevel, bool  
> verbose);
>
>   /*--== Utility functions/predicates/etc used all over the place: -- 
> ==*/
>   //! Predicate test for a signed 10-bit value
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -81,15 +81,17 @@
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> bool
> -SPUTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast)
> +SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel)
> {
>   // Install an instruction selector.
>   PM.add(createSPUISelDag(*this));
>   return false;
> }
>
> -bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool  
> Fast,
> -                                          bool Verbose, raw_ostream  
> &Out) {
> -  PM.add(createSPUAsmPrinterPass(Out, *this, Fast, Verbose));
> +bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                          unsigned OptLevel,
> +                                          bool Verbose,
> +                                          raw_ostream &Out) {
> +  PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Tue Apr 28  
> 19:15:41 2009
> @@ -83,9 +83,9 @@
>   }
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool /*Fast*/);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool /*Fast*/,
> -                                  bool /*Verbose*/, raw_ostream  
> &Out);
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
> +                                  bool Verbose, raw_ostream &Out);
> };
>
> } // end namespace llvm
>
> Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
> +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -1995,7 +1995,7 @@
> bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>                                                 raw_ostream &o,
>                                                 CodeGenFileType  
> FileType,
> -                                                bool Fast) {
> +                                                unsigned OptLevel) {
>   if (FileType != TargetMachine::AssemblyFile) return true;
>   PM.add(new CppWriter(o));
>   return false;
>
> Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Tue Apr 28  
> 19:15:41 2009
> @@ -29,7 +29,8 @@
>
>   virtual bool WantsWholeFile() const { return true; }
>   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream  
> &Out,
> -                                        CodeGenFileType FileType,  
> bool Fast);
> +                                        CodeGenFileType FileType,
> +                                        unsigned OptLevel);
>
>   // This class always works, but shouldn't be the default in most  
> cases.
>   static unsigned getModuleMatchQuality(const Module &M) { return 1; }
>
> Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Tue Apr  
> 28 19:15:41 2009
> @@ -37,9 +37,9 @@
>   class IA64AsmPrinter : public AsmPrinter {
>     std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
>   public:
> -    IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                   const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V) {}
> +    explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
> +                            const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(O, TM, T, OL, V) {}
>
>     virtual const char *getPassName() const {
>       return "IA64 Assembly Printer";
> @@ -370,6 +370,7 @@
> ///
> FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
>                                               IA64TargetMachine &tm,
> -                                              bool fast, bool  
> verbose) {
> -  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                              unsigned OptLevel,
> +                                              bool verbose) {
> +  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,  
> verbose);
> }
>
> Modified: llvm/trunk/lib/Target/IA64/IA64.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64.h (original)
> +++ llvm/trunk/lib/Target/IA64/IA64.h Tue Apr 28 19:15:41 2009
> @@ -37,7 +37,7 @@
> ///
> FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
>                                         IA64TargetMachine &tm,
> -                                        bool fast, bool verbose);
> +                                        unsigned OptLevel, bool  
> verbose);
>
> } // End llvm namespace
>
>
> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -72,19 +72,21 @@
> // Pass Pipeline Configuration
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> -bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,  
> unsigned OptLEvel){
>   PM.add(createIA64DAGToDAGInstructionSelector(*this));
>   return false;
> }
>
> -bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, bool  
> Fast) {
> +bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,  
> unsigned OptLevel) {
>   // Make sure everything is bundled happily
>   PM.add(createIA64BundlingPass(*this));
>   return true;
> }
> -bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,  
> bool Fast,
> -                                           bool Verbose,  
> raw_ostream &Out) {
> -  PM.add(createIA64CodePrinterPass(Out, *this, Fast, Verbose));
> +bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                           unsigned OptLevel,
> +                                           bool Verbose,
> +                                           raw_ostream &Out) {
> +  PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
>
> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.h Tue Apr 28  
> 19:15:41 2009
> @@ -51,9 +51,9 @@
>   static unsigned getModuleMatchQuality(const Module &M);
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> };
> } // End llvm namespace
>
> Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
> +++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Tue Apr 28 19:15:41 2009
> @@ -35,7 +35,8 @@
>
>     virtual bool WantsWholeFile() const { return true; }
>     virtual bool addPassesToEmitWholeFile(PassManager &PM,  
> raw_ostream &Out,
> -                                         CodeGenFileType FileType,  
> bool Fast);
> +                                          CodeGenFileType FileType,
> +                                          unsigned OptLevel);
>
>     // This class always works, but shouldn't be the default in most  
> cases.
>     static unsigned getModuleMatchQuality(const Module &M) { return  
> 1; }
> @@ -1662,7 +1663,8 @@
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM,  
> raw_ostream &o,
> -                                          CodeGenFileType FileType,  
> bool Fast)
> +                                          CodeGenFileType FileType,
> +                                          unsigned OptLevel)
> {
>   if (FileType != TargetMachine::AssemblyFile) return true;
>   MSILWriter* Writer = new MSILWriter(o);
>
> Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Tue Apr  
> 28 19:15:41 2009
> @@ -49,9 +49,9 @@
>   class VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
>     const MipsSubtarget *Subtarget;
>   public:
> -    MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
> -                   const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V) {
> +    explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
> +                            const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(O, TM, T, OL, V) {
>       Subtarget = &TM.getSubtarget<MipsSubtarget>();
>     }
>
> @@ -91,8 +91,8 @@
> /// regardless of whether the function is in SSA form.
> FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
>                                               MipsTargetMachine &tm,
> -                                              bool fast, bool  
> verbose) {
> -  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                              unsigned OptLevel,  
> bool verbose) {
> +  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,  
> verbose);
> }
>
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> Modified: llvm/trunk/lib/Target/Mips/Mips.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/Mips.h (original)
> +++ llvm/trunk/lib/Target/Mips/Mips.h Tue Apr 28 19:15:41 2009
> @@ -25,7 +25,7 @@
>   FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
>   FunctionPass *createMipsCodePrinterPass(raw_ostream &OS,
>                                           MipsTargetMachine &TM,
> -                                          bool Fast, bool Verbose);
> +                                          unsigned OptLevel, bool  
> Verbose);
> } // end namespace llvm;
>
> // Defines symbolic names for Mips registers.  This defines a  
> mapping from
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -105,7 +105,7 @@
> // Install an instruction selector pass using
> // the ISelDag to gen Mips code.
> bool MipsTargetMachine::
> -addInstSelector(PassManagerBase &PM, bool Fast)
> +addInstSelector(PassManagerBase &PM, unsigned OptLevel)
> {
>   PM.add(createMipsISelDag(*this));
>   return false;
> @@ -115,7 +115,7 @@
> // machine code is emitted. return true if -print-machineinstrs should
> // print out the code after the passes.
> bool MipsTargetMachine::
> -addPreEmitPass(PassManagerBase &PM, bool Fast)
> +addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
> {
>   PM.add(createMipsDelaySlotFillerPass(*this));
>   return true;
> @@ -124,10 +124,10 @@
> // Implements the AssemblyEmitter for the target. Must return
> // true if AssemblyEmitter is supported
> bool MipsTargetMachine::
> -addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
>                    bool Verbose, raw_ostream &Out)
> {
>   // Output assembly language.
> -  PM.add(createMipsCodePrinterPass(Out, *this, Fast, Verbose));
> +  PM.add(createMipsCodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Tue Apr 28  
> 19:15:41 2009
> @@ -57,9 +57,9 @@
>     static unsigned getModuleMatchQuality(const Module &M);
>
>     // Pass Pipeline Configuration
> -    virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -    virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
> -    virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +    virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +    virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> +    virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                     bool Verbose, raw_ostream &Out);
>   };
>
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16.h Tue Apr 28 19:15:41 2009
> @@ -75,7 +75,7 @@
>   FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
>   FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
>                                            PIC16TargetMachine &TM,
> -                                           bool Fast, bool Verbose);
> +                                           unsigned OptLevel, bool  
> Verbose);
> } // end namespace llvm;
>
> // Defines symbolic names for PIC16 registers.  This defines a  
> mapping from
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -161,8 +161,9 @@
> ///
> FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
>                                                PIC16TargetMachine &tm,
> -                                               bool fast, bool  
> verbose) {
> -  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                               unsigned OptLevel,
> +                                               bool verbose) {
> +  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> OptLevel, verbose);
> }
>
> void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int  
> opNum) {
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Tue Apr 28  
> 19:15:41 2009
> @@ -24,9 +24,9 @@
>
> namespace llvm {
>   struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
> -  PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
> -                    const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V) {
> +    explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
> +                             const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(O, TM, T, OL, V) {
>       CurBank = "";
>       FunctionLabelBegin = '@';
>       IsRomData = false;
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -55,17 +55,18 @@
>   return new PIC16TargetAsmInfo(*this);
> }
>
> -bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
> +                                         unsigned OptLevel) {
>   // Install an instruction selector.
>   PM.add(createPIC16ISelDag(*this));
>   return false;
> }
>
> bool PIC16TargetMachine::
> -addAssemblyEmitter(PassManagerBase &PM, bool Fast, bool Verbose,
> +addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool  
> Verbose,
>                    raw_ostream &Out) {
>   // Output assembly language.
> -  PM.add(createPIC16CodePrinterPass(Out, *this, Fast, Verbose));
> +  PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h Tue Apr 28  
> 19:15:41 2009
> @@ -57,8 +57,8 @@
>     return const_cast<PIC16TargetLowering*>(&TLInfo);
>   }
>
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> }; // PIC16TargetMachine.
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Tue  
> Apr 28 19:15:41 2009
> @@ -54,9 +54,9 @@
>     StringSet<> FnStubs, GVStubs, HiddenGVStubs;
>     const PPCSubtarget &Subtarget;
>   public:
> -    PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                  const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V),
> +    explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
> +                           const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(O, TM, T, OL, V),
>         Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
>
>     virtual const char *getPassName() const {
> @@ -297,9 +297,9 @@
>     DwarfWriter *DW;
>     MachineModuleInfo *MMI;
>   public:
> -    PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
> -                       const TargetAsmInfo *T, bool F, bool V)
> -      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
> +    explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
> +                                const TargetAsmInfo *T, unsigned  
> OL, bool V)
> +      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
>
>     virtual const char *getPassName() const {
>       return "Linux PPC Assembly Printer";
> @@ -326,9 +326,9 @@
>     MachineModuleInfo *MMI;
>     raw_ostream &OS;
>   public:
> -    PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
> -                        const TargetAsmInfo *T, bool F, bool V)
> -      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0), OS(O) {}
> +    explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine  
> &TM,
> +                                 const TargetAsmInfo *T, unsigned  
> OL, bool V)
> +      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
>
>     virtual const char *getPassName() const {
>       return "Darwin PPC Assembly Printer";
> @@ -1176,13 +1176,15 @@
> ///
> FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
>                                             PPCTargetMachine &tm,
> -                                            bool fast, bool  
> verbose) {
> +                                            unsigned OptLevel, bool  
> verbose) {
>   const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
>
>   if (Subtarget->isDarwin()) {
> -    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> fast, verbose);
> +    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
> +                                   OptLevel, verbose);
>   } else {
> -    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> fast, verbose);
> +    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
> +                                  OptLevel, verbose);
>   }
> }
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPC.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPC.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPC.h Tue Apr 28 19:15:41 2009
> @@ -28,7 +28,7 @@
> FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
> FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
>                                       PPCTargetMachine &TM,
> -                                      bool Fast, bool Verbose);
> +                                      unsigned OptLevel, bool  
> Verbose);
> FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
>                                        MachineCodeEmitter &MCE);
> } // end namespace llvm;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -129,29 +129,31 @@
> // Pass Pipeline Configuration
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> -bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,  
> unsigned OptLevel) {
>   // Install an instruction selector.
>   PM.add(createPPCISelDag(*this));
>   return false;
> }
>
> -bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool  
> Fast) {
> +bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel) {
>
>   // Must run branch selection immediately preceding the asm printer.
>   PM.add(createPPCBranchSelectionPass());
>   return false;
> }
>
> -bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool  
> Fast,
> -                                          bool Verbose, raw_ostream  
> &Out) {
> +bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                          unsigned OptLevel,
> +                                          bool Verbose,
> +                                          raw_ostream &Out) {
>   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>   if (AsmPrinterCtor)
> -    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
> +    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>
>   return false;
> }
>
> -bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
> +bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                       bool DumpAsm,  
> MachineCodeEmitter &MCE) {
>   // The JIT should use the static relocation model in ppc32 mode,  
> PIC in ppc64.
>   // FIXME: This should be moved to TargetJITInfo!!
> @@ -176,20 +178,20 @@
>   if (DumpAsm) {
>     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>     if (AsmPrinterCtor)
> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>   }
>
>   return false;
> }
>
> -bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,  
> bool Fast,
> +bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,  
> unsigned OptLevel,
>                                             bool DumpAsm,  
> MachineCodeEmitter &MCE) {
>   // Machine code emitter pass for PowerPC.
>   PM.add(createPPCCodeEmitterPass(*this, MCE));
>   if (DumpAsm) {
>     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>     if (AsmPrinterCtor)
> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>   }
>
>   return false;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Tue Apr 28  
> 19:15:41 2009
> @@ -46,7 +46,7 @@
>   // set this functions to ctor pointer at startup time if they are  
> linked in.
>   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>                                             PPCTargetMachine &tm,
> -                                            bool fast, bool verbose);
> +                                            unsigned OptLevel, bool  
> verbose);
>   static AsmPrinterCtorFn AsmPrinterCtor;
>
> public:
> @@ -76,13 +76,13 @@
>   }
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
>                               bool DumpAsm, MachineCodeEmitter &MCE);
> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                     bool DumpAsm, MachineCodeEmitter  
> &MCE);
>   virtual bool getEnableTailMergeDefault() const;
> };
>
> Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp Tue  
> Apr 28 19:15:41 2009
> @@ -48,9 +48,9 @@
>     typedef std::map<const Value *, unsigned> ValueMapTy;
>     ValueMapTy NumberForBB;
>   public:
> -    SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                    const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V) {}
> +    explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
> +                             const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +      : AsmPrinter(O, TM, T, OL, V) {}
>
>     virtual const char *getPassName() const {
>       return "Sparc Assembly Printer";
> @@ -82,8 +82,9 @@
> ///
> FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
>                                                TargetMachine &tm,
> -                                               bool fast, bool  
> verbose) {
> -  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                               unsigned OptLevel,
> +                                               bool verbose) {
> +  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> OptLevel, verbose);
> }
>
> /// runOnMachineFunction - This uses the printInstruction()
>
> Modified: llvm/trunk/lib/Target/Sparc/Sparc.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/Sparc.h (original)
> +++ llvm/trunk/lib/Target/Sparc/Sparc.h Tue Apr 28 19:15:41 2009
> @@ -25,7 +25,7 @@
>
>   FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
>   FunctionPass *createSparcCodePrinterPass(raw_ostream &OS,  
> TargetMachine &TM,
> -                                           bool Fast, bool Verbose);
> +                                           unsigned OptLevel, bool  
> Verbose);
>   FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
>   FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
> } // end namespace llvm;
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -68,7 +68,8 @@
> #endif
> }
>
> -bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
> +                                         unsigned OptLevel) {
>   PM.add(createSparcISelDag(*this));
>   return false;
> }
> @@ -76,15 +77,17 @@
> /// addPreEmitPass - This pass may be implemented by targets that  
> want to run
> /// passes immediately before machine code is emitted.  This should  
> return
> /// true if -print-machineinstrs should print out the code after the  
> passes.
> -bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, bool  
> Fast) {
> +bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,  
> unsigned OptLevel){
>   PM.add(createSparcFPMoverPass(*this));
>   PM.add(createSparcDelaySlotFillerPass(*this));
>   return true;
> }
>
> -bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,  
> bool Fast,
> -                                            bool Verbose,  
> raw_ostream &Out) {
> +bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                            unsigned OptLevel,
> +                                            bool Verbose,
> +                                            raw_ostream &Out) {
>   // Output assembly language.
> -  PM.add(createSparcCodePrinterPass(Out, *this, Fast, Verbose));
> +  PM.add(createSparcCodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Tue Apr 28  
> 19:15:41 2009
> @@ -51,9 +51,9 @@
>   static unsigned getModuleMatchQuality(const Module &M);
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> };
>
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Tue Apr  
> 28 19:15:41 2009
> @@ -33,9 +33,9 @@
>   MachineModuleInfo *MMI;
>   const X86Subtarget *Subtarget;
>  public:
> -  X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
> -                   const TargetAsmInfo *T, bool F, bool V)
> -    : AsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {
> +  explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
> +                            const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +    : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
>     Subtarget = &TM.getSubtarget<X86Subtarget>();
>   }
>
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Tue Apr  
> 28 19:15:41 2009
> @@ -25,13 +25,15 @@
> ///
> FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
>                                              X86TargetMachine &tm,
> -                                             bool fast, bool  
> verbose) {
> +                                             unsigned OptLevel,  
> bool verbose) {
>   const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
>
>   if (Subtarget->isFlavorIntel()) {
> -    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> fast, verbose);
> +    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(),
> +                                  OptLevel, verbose);
>   } else {
> -    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(),
> +                                OptLevel, verbose);
>   }
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h  
> (original)
> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h Tue  
> Apr 28 19:15:41 2009
> @@ -25,9 +25,9 @@
> namespace llvm {
>
> struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
> -  X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
> -                     const TargetAsmInfo *T, bool F, bool V)
> -    : AsmPrinter(O, TM, T, F, V) {}
> +  explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
> +                              const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +    : AsmPrinter(O, TM, T, OL, V) {}
>
>   virtual const char *getPassName() const {
>     return "X86 Intel-Style Assembly Printer";
>
> Modified: llvm/trunk/lib/Target/X86/X86.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86.h (original)
> +++ llvm/trunk/lib/Target/X86/X86.h Tue Apr 28 19:15:41 2009
> @@ -25,7 +25,7 @@
> /// createX86ISelDag - This pass converts a legalized DAG into a
> /// X86-specific DAG, ready for instruction scheduling.
> ///
> -FunctionPass *createX86ISelDag(X86TargetMachine &TM, bool Fast);
> +FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned  
> OptSize);
>
> /// createX86FloatingPointStackifierPass - This function returns a  
> pass which
> /// converts floating point register references and pseudo  
> instructions into
> @@ -44,7 +44,7 @@
> ///
> FunctionPass *createX86CodePrinterPass(raw_ostream &o,
>                                        X86TargetMachine &tm,
> -                                       bool fast, bool Verbose);
> +                                       unsigned OptLevel, bool  
> Verbose);
>
> /// createX86CodeEmitterPass - Return a pass that emits the  
> collected X86 code
> /// to the specified MCE object.
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -134,8 +134,8 @@
>     bool OptForSize;
>
>   public:
> -    X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
> -      : SelectionDAGISel(tm, fast),
> +    explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
> +      : SelectionDAGISel(tm, OptLevel),
>         TM(tm), X86Lowering(*TM.getTargetLowering()),
>         Subtarget(&TM.getSubtarget<X86Subtarget>()),
>         OptForSize(false) {}
> @@ -306,7 +306,7 @@
>
> bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
>                                                  SDNode *Root) const {
> -  if (Fast) return false;
> +  if (OptLevel == 0) return false;
>
>   if (U == Root)
>     switch (U->getOpcode()) {
> @@ -512,7 +512,7 @@
>
>
> /// PreprocessForRMW - Preprocess the DAG to make instruction  
> selection better.
> -/// This is only run if not in -fast mode (aka -O0).
> +/// This is only run if not in -O0 mode.
> /// This allows the instruction selector to pick more read-modify- 
> write
> /// instructions. This is a common case:
> ///
> @@ -714,10 +714,10 @@
>   OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
>
>   DEBUG(BB->dump());
> -  if (!Fast)
> +  if (OptLevel != 0)
>     PreprocessForRMW();
>
> -  // FIXME: This should only happen when not -fast.
> +  // FIXME: This should only happen when not compiled with -O0.
>   PreprocessForFPConvert();
>
>   // Codegen the basic block.
> @@ -1744,6 +1744,6 @@
> /// createX86ISelDag - This pass converts a legalized DAG into a
> /// X86-specific DAG, ready for instruction scheduling.
> ///
> -FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool  
> Fast) {
> -  return new X86DAGToDAGISel(TM, Fast);
> +FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned  
> OptLevel) {
> +  return new X86DAGToDAGISel(TM, OptLevel);
> }
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -180,9 +180,9 @@
> // Pass Pipeline Configuration
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> -bool X86TargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool X86TargetMachine::addInstSelector(PassManagerBase &PM,  
> unsigned OptLevel) {
>   // Install an instruction selector.
> -  PM.add(createX86ISelDag(*this, Fast));
> +  PM.add(createX86ISelDag(*this, OptLevel));
>
>   // If we're using Fast-ISel, clean up the mess.
>   if (EnableFastISel)
> @@ -194,27 +194,29 @@
>   return false;
> }
>
> -bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, bool  
> Fast) {
> +bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned  
> OptLevel) {
>   // Calculate and set max stack object alignment early, so we can  
> decide
>   // whether we will need stack realignment (and thus FP).
>   PM.add(createX86MaxStackAlignmentCalculatorPass());
>   return false;  // -print-machineinstr shouldn't print after this.
> }
>
> -bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, bool  
> Fast) {
> +bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,  
> unsigned OptLevel) {
>   PM.add(createX86FloatingPointStackifierPass());
>   return true;  // -print-machineinstr should print after this.
> }
>
> -bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool  
> Fast,
> -                                          bool Verbose, raw_ostream  
> &Out) {
> +bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                          unsigned OptLevel,
> +                                          bool Verbose,
> +                                          raw_ostream &Out) {
>   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>   if (AsmPrinterCtor)
> -    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
> +    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
> -bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
> +bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                       bool DumpAsm,  
> MachineCodeEmitter &MCE) {
>   // FIXME: Move this to TargetJITInfo!
>   // On Darwin, do not override 64-bit setting made in  
> X86TargetMachine().
> @@ -236,19 +238,20 @@
>   if (DumpAsm) {
>     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>     if (AsmPrinterCtor)
> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>   }
>
>   return false;
> }
>
> -bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,  
> bool Fast,
> -                                        bool DumpAsm,  
> MachineCodeEmitter &MCE) {
> +bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
> +                                            unsigned OptLevel, bool  
> DumpAsm,
> +                                            MachineCodeEmitter  
> &MCE) {
>   PM.add(createX86CodeEmitterPass(*this, MCE));
>   if (DumpAsm) {
>     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
>     if (AsmPrinterCtor)
> -      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
> +      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
>   }
>
>   return false;
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Tue Apr 28 19:15:41  
> 2009
> @@ -45,7 +45,7 @@
>   // set this functions to ctor pointer at startup time if they are  
> linked in.
>   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>                                             X86TargetMachine &tm,
> -                                            bool fast, bool verbose);
> +                                            unsigned OptLevel, bool  
> verbose);
>   static AsmPrinterCtorFn AsmPrinterCtor;
>
> public:
> @@ -74,14 +74,14 @@
>   }
>
>   // Set up the pass pipeline.
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addPreRegAlloc(PassManagerBase &PM, bool Fast);
> -  virtual bool addPostRegAlloc(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> -  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
>                               bool DumpAsm, MachineCodeEmitter &MCE);
> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                     bool DumpAsm, MachineCodeEmitter  
> &MCE);
>
>   /// symbolicAddressesAreRIPRel - Return true if symbolic addresses  
> are
>
> Modified: llvm/trunk/lib/Target/XCore/XCore.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCore.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/XCore/XCore.h (original)
> +++ llvm/trunk/lib/Target/XCore/XCore.h Tue Apr 28 19:15:41 2009
> @@ -24,7 +24,7 @@
>   FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
>   FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
>                                            XCoreTargetMachine &TM,
> -                                           bool Fast, bool Verbose);
> +                                           unsigned OptLevel, bool  
> Verbose);
> } // end namespace llvm;
>
> // Defines symbolic names for XCore registers.  This defines a  
> mapping from
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -58,8 +58,8 @@
>     const XCoreSubtarget &Subtarget;
>   public:
>     XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
> -                    const TargetAsmInfo *T, bool F, bool V)
> -      : AsmPrinter(O, TM, T, F, V), DW(0),
> +                    const TargetAsmInfo *T, unsigned OL, bool V)
> +      : AsmPrinter(O, TM, T, OL, V), DW(0),
>         Subtarget(*TM.getSubtargetImpl()) {}
>
>     virtual const char *getPassName() const {
> @@ -105,8 +105,9 @@
> ///
> FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
>                                                XCoreTargetMachine &tm,
> -                                               bool fast, bool  
> verbose) {
> -  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast,  
> verbose);
> +                                               unsigned OptLevel,
> +                                               bool verbose) {
> +  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(),  
> OptLevel, verbose);
> }
>
> // PrintEscapedString - Print each character of the specified  
> string, escaping
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -55,14 +55,17 @@
>   return 0;
> }
>
> -bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, bool  
> Fast) {
> +bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
> +                                         unsigned OptLevel) {
>   PM.add(createXCoreISelDag(*this));
>   return false;
> }
>
> -bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,  
> bool Fast,
> -                                            bool Verbose,  
> raw_ostream &Out) {
> +bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> +                                            unsigned OptLevel,
> +                                            bool Verbose,
> +                                            raw_ostream &Out) {
>   // Output assembly language.
> -  PM.add(createXCoreCodePrinterPass(Out, *this, Fast, Verbose));
> +  PM.add(createXCoreCodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Tue Apr 28  
> 19:15:41 2009
> @@ -52,8 +52,8 @@
>   static unsigned getModuleMatchQuality(const Module &M);
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
> +  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> };
>
>
> Modified: llvm/trunk/test/CodeGen/Generic/2006-06-12- 
> LowerSwitchCrash.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll  
> (original)
> +++ llvm/trunk/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll  
> Tue Apr 28 19:15:41 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -fast
> +; RUN: llvm-as < %s | llc -O0
>
> define float @test(i32 %tmp12771278) {
>         switch i32 %tmp12771278, label %bb1279 [
>
> Modified: llvm/trunk/test/CodeGen/Generic/2006-06-13- 
> ComputeMaskedBitsCrash.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/Generic/2006-06-13- 
> ComputeMaskedBitsCrash.ll (original)
> +++ llvm/trunk/test/CodeGen/Generic/2006-06-13- 
> ComputeMaskedBitsCrash.ll Tue Apr 28 19:15:41 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -fast
> +; RUN: llvm-as < %s | llc -O0
> 	
> %struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8,  
> i8, i8, i8, i32, i32, i32, i32, i32, i32, i32 }
> @cl_pf_opts = external global %struct.cl_perfunc_opts		; < 
> %struct.cl_perfunc_opts*> [#uses=2]
>
> Modified: llvm/trunk/test/CodeGen/Generic/2007-04-13- 
> SwitchLowerBadPhi.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll  
> (original)
> +++ llvm/trunk/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll  
> Tue Apr 28 19:15:41 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -fast
> +; RUN: llvm-as < %s | llc -O0
> ; PR 1323
>
> ; ModuleID = 'test.bc'
>
> Modified: llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll Tue Apr 28  
> 19:15:41 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -fast - 
> relocation-model=pic -o -
> +; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -O0 - 
> relocation-model=pic -o -
> ; PR1638
>
> @.str242 = external constant [3 x i8]		; <[3 x i8]*> [#uses=1]
>
> Modified: llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll  
> (original)
> +++ llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll Tue  
> Apr 28 19:15:41 2009
> @@ -1,5 +1,5 @@
> ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin
> -; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation- 
> model=pic -disable-fp-elim -fast -regalloc=local
> +; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation- 
> model=pic -disable-fp-elim -O0 -regalloc=local
>
> 	%struct.CGPoint = type { double, double }
> 	%struct.NSArray = type { %struct.NSObject }
>
> Modified: llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/2008-05-21-CoalescerBug.ll Tue Apr  
> 28 19:15:41 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -march=x86 -fast -fast-isel=false | grep  
> mov | count 5
> +; RUN: llvm-as < %s | llc -march=x86 -O0 -fast-isel=false | grep  
> mov | count 5
> ; PR2343
>
> 	%llvm.dbg.anchor.type = type { i32, i32 }
>
> Modified: llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/2009-03-23-LinearScanBug.ll Tue Apr  
> 28 19:15:41 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast
> +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0
>
> define fastcc void @optimize_bit_field() nounwind {
> bb4:
>
> Modified: llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll Tue Apr 28  
> 19:15:41 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast - 
> regalloc=local | not grep sil
> +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0 - 
> regalloc=local | not grep sil
> ; rdar://6787136
>
> 	%struct.X = type { i8, [32 x i8] }
>
> Modified: llvm/trunk/test/CodeGen/X86/add-with-overflow.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/add-with-overflow.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/add-with-overflow.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/add-with-overflow.ll Tue Apr 28  
> 19:15:41 2009
> @@ -1,7 +1,7 @@
> ; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 2
> ; RUN: llvm-as < %s | llc -march=x86 | grep {jb} | count 2
> -; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jo} | count 2
> -; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jb} | count 2
> +; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jo} | count 2
> +; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jb} | count 2
>
> @ok = internal constant [4 x i8] c"%d\0A\00"
> @no = internal constant [4 x i8] c"no\0A\00"
>
> Modified: llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/fast-isel-bail.ll Tue Apr 28  
> 19:15:41 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -march=x86 -fast
> +; RUN: llvm-as < %s | llc -march=x86 -O0
>
> ; This file is for regression tests for cases where FastISel needs
> ; to gracefully bail out and let SelectionDAGISel take over.
>
> Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/fast-isel-gep-sext.ll Tue Apr 28  
> 19:15:41 2009
> @@ -1,5 +1,5 @@
> -; RUN: llvm-as < %s | llc -march=x86-64 -fast | grep movslq
> -; RUN: llvm-as < %s | llc -march=x86 -fast
> +; RUN: llvm-as < %s | llc -march=x86-64 -O0 | grep movslq
> +; RUN: llvm-as < %s | llc -march=x86 -O0
> ; PR3181
>
> ; GEP indices are interpreted as signed integers, so they
>
> Modified: llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll Tue Apr 28  
> 19:15:41 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -march=x86 -fast | grep {sarl	\$80, %eax}
> +; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {sarl	\$80, %eax}
> ; PR3242
>
> define i32 @foo(i32 %x) nounwind {
>
> Modified: llvm/trunk/test/CodeGen/X86/pr1489.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr1489.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/pr1489.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/pr1489.ll Tue Apr 28 19:15:41 2009
> @@ -1,5 +1,5 @@
> -; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep  
> 1082126238 | count 3
> -; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep  
> 3058016715 | count 1
> +; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep  
> 1082126238 | count 3
> +; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep  
> 3058016715 | count 1
> ;; magic constants are 3.999f and half of 3.999
> ; ModuleID = '1489.c'
> target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32- 
> i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
>
> Modified: llvm/trunk/test/CodeGen/X86/volatile.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/volatile.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/volatile.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/volatile.ll Tue Apr 28 19:15:41 2009
> @@ -1,5 +1,5 @@
> ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 | grep movsd |  
> count 5
> -; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -fast | grep movsd  
> | count 5
> +; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -O0 | grep movsd |  
> count 5
>
> @x = external global double
>
>
> Modified: llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll  
> (original)
> +++ llvm/trunk/test/DebugInfo/2008-11-05-InlinedFuncStart.ll Tue Apr  
> 28 19:15:41 2009
> @@ -1,5 +1,5 @@
> ; RUN: llvm-as < %s | llc
> -; RUN: llvm-as < %s | llc -fast
> +; RUN: llvm-as < %s | llc -O0
> 	%llvm.dbg.anchor.type = type { i32, i32 }
> 	%llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64,  
> i64, i64, i32, i32 }
> 	%llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8* }
>
> Modified: llvm/trunk/test/DebugInfo/2009-01-30-Method.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2009-01-30-Method.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/DebugInfo/2009-01-30-Method.ll (original)
> +++ llvm/trunk/test/DebugInfo/2009-01-30-Method.ll Tue Apr 28  
> 19:15:41 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -fast | grep "\\"foo" | count 3
> +; RUN: llvm-as < %s | llc -O0 | grep "\\"foo" | count 3
> ; 1 declaration, 1 definition and 1 pubnames entry.
> target triple = "i386-apple-darwin*"
> 	%llvm.dbg.anchor.type = type { i32, i32 }
>
> Modified: llvm/trunk/test/DebugInfo/deaddebuglabel.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/deaddebuglabel.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/DebugInfo/deaddebuglabel.ll (original)
> +++ llvm/trunk/test/DebugInfo/deaddebuglabel.ll Tue Apr 28 19:15:41  
> 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -fast | grep "label" | count 8
> +; RUN: llvm-as < %s | llc -O0 | grep "label" | count 8
> ; PR2614
> ; XFAIL: *
>
>
> Modified: llvm/trunk/test/DebugInfo/forwardDecl.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/forwardDecl.ll?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/DebugInfo/forwardDecl.ll (original)
> +++ llvm/trunk/test/DebugInfo/forwardDecl.ll Tue Apr 28 19:15:41 2009
> @@ -1,4 +1,4 @@
> -; RUN: llvm-as < %s | llc -fast | %prcontext ST 1 | grep 0x1 |  
> count 1
> +; RUN: llvm-as < %s | llc -O0 | %prcontext ST 1 | grep 0x1 | count 1
>
> target triple = "i386-apple-darwin9.6"
> 	%llvm.dbg.anchor.type = type { i32, i32 }
>
> Modified: llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-06-StackTrace.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp (original)
> +++ llvm/trunk/test/FrontendC++/2006-11-06-StackTrace.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -1,7 +1,7 @@
> // This is a regression test on debug info to make sure that we can  
> get a
> // meaningful stack trace from a C++ program.
> // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
> -// RUN:    llc --disable-fp-elim -o %t.s -f -fast -relocation- 
> model=pic
> +// RUN:    llc --disable-fp-elim -o %t.s -f -O0 -relocation-model=pic
> // RUN: %compile_c %t.s -o %t.o
> // RUN: %link %t.o -o %t.exe
> // RUN: echo {break DeepStack::deepest\nrun 17\nwhere\n} > %t.in
>
> Modified: llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2006-11-30-Pubnames.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp (original)
> +++ llvm/trunk/test/FrontendC++/2006-11-30-Pubnames.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -1,7 +1,7 @@
> // This is a regression test on debug info to make sure that we can  
> access
> // qualified global names.
> // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
> -// RUN:   llc --disable-fp-elim -o %t.s -f -fast
> +// RUN:   llc --disable-fp-elim -o %t.s -f -O0
> // RUN: %compile_c %t.s -o %t.o
> // RUN: %link %t.o -o %t.exe
> // RUN: %llvmdsymutil %t.exe
>
> Modified: llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-04-21-DtorNames-dbg.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp  
> (original)
> +++ llvm/trunk/test/FrontendC++/2009-04-21-DtorNames-dbg.cpp Tue Apr  
> 28 19:15:41 2009
> @@ -1,4 +1,4 @@
> -// RUN: %llvmgcc -c -g %s -o - | llc -fast -f -o %t.s
> +// RUN: %llvmgcc -c -g %s -o - | llc -O0 -f -o %t.s
> // RUN: %compile_c %t.s -o %t.o
> // PR4025
>
>
> Modified: llvm/trunk/tools/llc/llc.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/tools/llc/llc.cpp (original)
> +++ llvm/trunk/tools/llc/llc.cpp Tue Apr 28 19:15:41 2009
> @@ -55,8 +55,13 @@
>
> static cl::opt<bool> Force("f", cl::desc("Overwrite output files"));
>
> -static cl::opt<bool> Fast("fast",
> -      cl::desc("Generate code quickly, potentially sacrificing code  
> quality"));
> +// Determine optimization level. Level -O0 is equivalent to "fast"  
> code gen.
> +static cl::opt<unsigned>
> +OptLevel("O",
> +         cl::desc("Optimization level. Similar to llvm-gcc -O.  
> (default: -O3)"),
> +         cl::Prefix,
> +         cl::ZeroOrMore,
> +         cl::init(3));
>
> static cl::opt<std::string>
> TargetTriple("mtriple", cl::desc("Override target triple for  
> module"));
> @@ -257,7 +262,7 @@
>       PM.add(createVerifierPass());
>
>     // Ask the target to add backend passes as necessary.
> -    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, Fast)) {
> +    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType,  
> OptLevel)) {
>       std::cerr << argv[0] << ": target does not support generation  
> of this"
>                 << " file type!\n";
>       if (Out != &outs()) delete Out;
> @@ -283,7 +288,7 @@
>     // Override default to generate verbose assembly.
>     Target.setAsmVerbosityDefault(true);
>
> -    switch (Target.addPassesToEmitFile(Passes, *Out, FileType,  
> Fast)) {
> +    switch (Target.addPassesToEmitFile(Passes, *Out, FileType,  
> OptLevel)) {
>     default:
>       assert(0 && "Invalid file model!");
>       return 1;
> @@ -304,7 +309,7 @@
>       break;
>     }
>
> -    if (Target.addPassesToEmitFileFinish(Passes, MCE, Fast)) {
> +    if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) {
>       std::cerr << argv[0] << ": target does not support generation  
> of this"
>                 << " file type!\n";
>       if (Out != &outs()) delete Out;
>
> Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Tue Apr 28  
> 19:15:41 2009
> @@ -650,7 +650,7 @@
>   O << "\";\n\n";
>
>   O << "  if (TAI->doesSupportDebugInformation() &&\n"
> -    << "      DW->ShouldEmitDwarfDebug() && !Fast) {\n"
> +    << "      DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n"
>     << "    DebugLoc CurDL = MI->getDebugLoc();\n\n"
>     << "    if (!CurDL.isUnknown()) {\n"
>     << "      static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n"
>
> Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=70343&r1=70342&r2=70343&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Tue Apr 28 19:15:41  
> 2009
> @@ -465,7 +465,7 @@
>       NumInputRootOps = N->getNumChildren();
>
>       if (DisablePatternForFastISel(N, CGP))
> -        emitCheck("!Fast");
> +        emitCheck("OptLevel != 0");
>
>       emitCheck(PredicateCheck);
>     }
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From isanbard at gmail.com  Wed Apr 29 16:22:00 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 21:22:00 -0000
Subject: [llvm-commits] [llvm] r70411 -
	/llvm/trunk/tools/lto/LTOCodeGenerator.cpp
Message-ID: <200904292122.n3TLM0o1011985@zion.cs.uiuc.edu>

Author: void
Date: Wed Apr 29 16:22:00 2009
New Revision: 70411

URL: http://llvm.org/viewvc/llvm-project?rev=70411&view=rev
Log:
Don't use 'false' for 'fast isel' here.

Modified:
    llvm/trunk/tools/lto/LTOCodeGenerator.cpp

Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=70411&r1=70410&r2=70411&view=diff

==============================================================================
--- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original)
+++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Apr 29 16:22:00 2009
@@ -442,7 +442,7 @@
     MachineCodeEmitter* mce = NULL;
 
     switch (_target->addPassesToEmitFile(*codeGenPasses, out,
-                                      TargetMachine::AssemblyFile, false)) {
+                                      TargetMachine::AssemblyFile, 3)) {
         case FileModel::MachOFile:
             mce = AddMachOWriter(*codeGenPasses, out, *_target);
             break;
@@ -457,7 +457,7 @@
             return true;
     }
 
-    if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce, false)) {
+    if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce, 3)) {
         errMsg = "target does not support generation of this file type";
         return true;
     }




From isanbard at gmail.com  Wed Apr 29 16:23:37 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 14:23:37 -0700
Subject: [llvm-commits] [llvm] r70343 - in /llvm/trunk:
	docs/CommandGuide/ include/llvm/CodeGen/ include/llvm/Target/
	lib/CodeGen/ lib/CodeGen/AsmPrinter/
	lib/CodeGen/SelectionDAG/ lib/Target/ARM/
	lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Al
Message-ID: <16e5fdf90904291423i962f280v5ad16a0972a23eb5@mail.gmail.com>

On Wed, Apr 29, 2009 at 2:16 PM, Evan Cheng <evan.cheng at apple.com> wrote:
> Bill, you still have to change LTOCodeGenerator.cpp.

Done.

> Also, rather than
> an unsigned for OptLevel, should it be an enum instead? We basically
> want to support a knob with 3 levels: no optimization, default
> optimization, aggressive optimization. Those correspond to -O0, -O1 / -
> O2 / -Os, -O3.
>
I'll look into this.

-bw


From evan.cheng at apple.com  Wed Apr 29 16:28:13 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Apr 2009 14:28:13 -0700
Subject: [llvm-commits] [llvm] r70343 - in
	/llvm/trunk:	docs/CommandGuide/ include/llvm/CodeGen/
	include/llvm/Target/	lib/CodeGen/
	lib/CodeGen/AsmPrinter/	lib/CodeGen/SelectionDAG/
	lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/
	lib/Target/Al
In-Reply-To: <16e5fdf90904291423i962f280v5ad16a0972a23eb5@mail.gmail.com>
References: <16e5fdf90904291423i962f280v5ad16a0972a23eb5@mail.gmail.com>
Message-ID: <EAB29BD4-DC21-405C-8CE1-32F75440160E@apple.com>


On Apr 29, 2009, at 2:23 PM, Bill Wendling wrote:

> On Wed, Apr 29, 2009 at 2:16 PM, Evan Cheng <evan.cheng at apple.com>  
> wrote:
>> Bill, you still have to change LTOCodeGenerator.cpp.
>
> Done.
>
>> Also, rather than
>> an unsigned for OptLevel, should it be an enum instead? We basically
>> want to support a knob with 3 levels: no optimization, default
>> optimization, aggressive optimization. Those correspond to -O0, - 
>> O1 / -
>> O2 / -Os, -O3.
>>
> I'll look into this.

Thanks. With an enum, we can actually document what the values  
mean. :-) For llc, lli, and LTO, I think it makes sense to use the  
"aggressive" level by default.

Evan

>
> -bw
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Wed Apr 29 16:31:06 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Apr 2009 14:31:06 -0700
Subject: [llvm-commits] [llvm] r70391 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAGNodes.h
	lib/CodeGen/SelectionDAG/SelectionDAG.cpp
In-Reply-To: <200904291813.n3TIDWRM005372@zion.cs.uiuc.edu>
References: <200904291813.n3TIDWRM005372@zion.cs.uiuc.edu>
Message-ID: <C52962EB-B6D7-4B0A-995C-DAFFC227938F@apple.com>

I still see this:

SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
   return SDValue();
...

Is the transformations disabled on purpose?

Evan

On Apr 29, 2009, at 11:13 AM, Nate Begeman wrote:

> Author: sampo
> Date: Wed Apr 29 13:13:31 2009
> New Revision: 70391
>
> URL: http://llvm.org/viewvc/llvm-project?rev=70391&view=rev
> Log:
> Update comment, replace theoretically impossible check with an assert.
>
> Modified:
>    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=70391&r1=70390&r2=70391&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Apr 29  
> 13:13:31 2009
> @@ -317,13 +317,13 @@
>     /// IDX, which must be a multiple of the result vector length.
>     EXTRACT_SUBVECTOR,
>
> -    /// VECTOR_SHUFFLE(VEC1, VEC2, SHUFFLEVEC) - Returns a vector,  
> of the same
> -    /// type as VEC1/VEC2.  SHUFFLEVEC is a BUILD_VECTOR of  
> constant int values
> -    /// (maybe of an illegal datatype) or undef that indicate which  
> value each
> -    /// result element will get.  The elements of VEC1/VEC2 are  
> enumerated in
> -    /// order.  This is quite similar to the Altivec 'vperm'  
> instruction, except
> -    /// that the indices must be constants and are in terms of the  
> element size
> -    /// of VEC1/VEC2, not in terms of bytes.
> +    /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same  
> type as
> +    /// VEC1/VEC2.  A VECTOR_SHUFFLE node also contains an array of  
> constant int
> +    /// values that indicate which value (or undef) each result  
> element will
> +    /// get.  These constant ints are accessible through the
> +    /// ShuffleVectorSDNode class.  This is quite similar to the  
> Altivec
> +    /// 'vperm' instruction, except that the indices must be  
> constants and are
> +    /// in terms of the element size of VEC1/VEC2, not in terms of  
> bytes.
>     VECTOR_SHUFFLE,
>
>     /// SCALAR_TO_VECTOR(VAL) - This represents the operation of  
> loading a
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=70391&r1=70390&r2=70391&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Apr 29  
> 13:13:31 2009
> @@ -5731,9 +5731,7 @@
>   for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; + 
> +i)
>     /* search */;
>
> -  // If we hit the end of the mask looking for a non-undef value,  
> return false.
> -  if (i == e)
> -    return false;
> +  assert(i != e && "VECTOR_SHUFFLE node with all undef indices!");
>
>   // Make sure all remaining elements are either undef or the same  
> as the first
>   // non-undef value.
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From gohman at apple.com  Wed Apr 29 17:01:06 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 29 Apr 2009 22:01:06 -0000
Subject: [llvm-commits] [llvm] r70416 -
	/llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
Message-ID: <200904292201.n3TM16u3013084@zion.cs.uiuc.edu>

Author: djg
Date: Wed Apr 29 17:01:05 2009
New Revision: 70416

URL: http://llvm.org/viewvc/llvm-project?rev=70416&view=rev
Log:
Reword and tidy up some comments.

Modified:
    llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp?rev=70416&r1=70415&r2=70416&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp Wed Apr 29 17:01:05 2009
@@ -10,33 +10,44 @@
 // This file implements Loop Index Splitting Pass. This pass handles three
 // kinds of loops.
 //
-// [1] Loop is eliminated when loop body is executed only once. For example,
+// [1] A loop may be eliminated if the body is executed exactly once.
+//     For example,
+//
 // for (i = 0; i < N; ++i) {
-//   if ( i == X) {
-//     ...
+//   if (i == X) {
+//     body;
 //   }
 // }
 //
-// [2] Loop's iteration space is shrunk if loop body is executed for certain
-//     range only. For example,
-// 
+// is transformed to
+//
+// i = X;
+// body;
+//
+// [2] A loop's iteration space may be shrunk if the loop body is executed
+//     for a proper sub-range of the loop's iteration space. For example,
+//
 // for (i = 0; i < N; ++i) {
-//   if ( i > A && i < B) {
+//   if (i > A && i < B) {
 //     ...
 //   }
 // }
-// is trnasformed to iterators from A to B, if A > 0 and B < N.
 //
-// [3] Loop is split if the loop body is dominated by an branch. For example,
+// is transformed to iterators from A to B, if A > 0 and B < N.
+//
+// [3] A loop may be split if the loop body is dominated by a branch.
+//     For example,
 //
 // for (i = LB; i < UB; ++i) { if (i < SV) A; else B; }
 //
 // is transformed into
+//
 // AEV = BSV = SV
 // for (i = LB; i < min(UB, AEV); ++i)
 //    A;
 // for (i = max(LB, BSV); i < UB; ++i);
 //    B;
+//
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "loop-index-split"
@@ -1060,7 +1071,7 @@
   DT->changeImmediateDominator(B_ExitBlock, B_ExitingBlock);
   DF->changeImmediateDominator(B_ExitBlock, B_ExitingBlock, DT);
 
- //[*] Split ALoop's exit edge. This creates a new block which
+  //[*] Split ALoop's exit edge. This creates a new block which
   //    serves two purposes. First one is to hold PHINode defnitions
   //    to ensure that ALoop's LCSSA form. Second use it to act
   //    as a preheader for BLoop.




From gohman at apple.com  Wed Apr 29 17:28:28 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 29 Apr 2009 22:28:28 -0000
Subject: [llvm-commits] [llvm] r70421 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/sext-iv-0.ll
 test/Analysis/ScalarEvolution/sext-iv-1.ll
Message-ID: <200904292228.n3TMSTaZ014041@zion.cs.uiuc.edu>

Author: djg
Date: Wed Apr 29 17:28:28 2009
New Revision: 70421

URL: http://llvm.org/viewvc/llvm-project?rev=70421&view=rev
Log:
Generalize the cast-of-addrec folding to handle folding of SCEVs like
(sext i8 {-128,+,1} to i64) to i64 {-128,+,1}, where the iteration
crosses from negative to positive, but is still safe if the trip
count is within range.

Added:
    llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-0.ll
    llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-1.ll
Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=70421&r1=70420&r2=70421&view=diff

==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Apr 29 17:28:28 2009
@@ -718,7 +718,7 @@
       SCEVHandle BECount = getBackedgeTakenCount(AR->getLoop());
       if (!isa<SCEVCouldNotCompute>(BECount)) {
         // Manually compute the final value for AR, checking for
-        // overflow at each step.
+        // overflow.
         SCEVHandle Start = AR->getStart();
         SCEVHandle Step = AR->getStepRecurrence(*this);
 
@@ -730,41 +730,34 @@
             getTruncateOrZeroExtend(CastedBECount, BECount->getType())) {
           const Type *WideTy =
             IntegerType::get(getTypeSizeInBits(Start->getType()) * 2);
+          // Check whether Start+Step*BECount has no unsigned overflow.
           SCEVHandle ZMul =
             getMulExpr(CastedBECount,
                        getTruncateOrZeroExtend(Step, Start->getType()));
-          // Check whether Start+Step*BECount has no unsigned overflow.
-          if (getZeroExtendExpr(ZMul, WideTy) ==
-              getMulExpr(getZeroExtendExpr(CastedBECount, WideTy),
-                         getZeroExtendExpr(Step, WideTy))) {
-            SCEVHandle Add = getAddExpr(Start, ZMul);
-            if (getZeroExtendExpr(Add, WideTy) ==
-                getAddExpr(getZeroExtendExpr(Start, WideTy),
-                           getZeroExtendExpr(ZMul, WideTy)))
-              // Return the expression with the addrec on the outside.
-              return getAddRecExpr(getZeroExtendExpr(Start, Ty),
-                                   getZeroExtendExpr(Step, Ty),
-                                   AR->getLoop());
-          }
+          SCEVHandle Add = getAddExpr(Start, ZMul);
+          if (getZeroExtendExpr(Add, WideTy) ==
+              getAddExpr(getZeroExtendExpr(Start, WideTy),
+                         getMulExpr(getZeroExtendExpr(CastedBECount, WideTy),
+                                    getZeroExtendExpr(Step, WideTy))))
+            // Return the expression with the addrec on the outside.
+            return getAddRecExpr(getZeroExtendExpr(Start, Ty),
+                                 getZeroExtendExpr(Step, Ty),
+                                 AR->getLoop());
 
           // Similar to above, only this time treat the step value as signed.
           // This covers loops that count down.
           SCEVHandle SMul =
             getMulExpr(CastedBECount,
                        getTruncateOrSignExtend(Step, Start->getType()));
-          // Check whether Start+Step*BECount has no unsigned overflow.
-          if (getSignExtendExpr(SMul, WideTy) ==
-              getMulExpr(getZeroExtendExpr(CastedBECount, WideTy),
-                         getSignExtendExpr(Step, WideTy))) {
-            SCEVHandle Add = getAddExpr(Start, SMul);
-            if (getZeroExtendExpr(Add, WideTy) ==
-                getAddExpr(getZeroExtendExpr(Start, WideTy),
-                           getSignExtendExpr(SMul, WideTy)))
-              // Return the expression with the addrec on the outside.
-              return getAddRecExpr(getZeroExtendExpr(Start, Ty),
-                                   getSignExtendExpr(Step, Ty),
-                                   AR->getLoop());
-          }
+          Add = getAddExpr(Start, SMul);
+          if (getZeroExtendExpr(Add, WideTy) ==
+              getAddExpr(getZeroExtendExpr(Start, WideTy),
+                         getMulExpr(getZeroExtendExpr(CastedBECount, WideTy),
+                                    getSignExtendExpr(Step, WideTy))))
+            // Return the expression with the addrec on the outside.
+            return getAddRecExpr(getZeroExtendExpr(Start, Ty),
+                                 getSignExtendExpr(Step, Ty),
+                                 AR->getLoop());
         }
       }
     }
@@ -807,37 +800,31 @@
       SCEVHandle BECount = getBackedgeTakenCount(AR->getLoop());
       if (!isa<SCEVCouldNotCompute>(BECount)) {
         // Manually compute the final value for AR, checking for
-        // overflow at each step.
+        // overflow.
         SCEVHandle Start = AR->getStart();
         SCEVHandle Step = AR->getStepRecurrence(*this);
 
         // Check whether the backedge-taken count can be losslessly casted to
-        // the addrec's type. The count needs to be the same whether sign
-        // extended or zero extended.
+        // the addrec's type. The count is always unsigned.
         SCEVHandle CastedBECount =
           getTruncateOrZeroExtend(BECount, Start->getType());
         if (BECount ==
-            getTruncateOrZeroExtend(CastedBECount, BECount->getType()) &&
-            BECount ==
-            getTruncateOrSignExtend(CastedBECount, BECount->getType())) {
+            getTruncateOrZeroExtend(CastedBECount, BECount->getType())) {
           const Type *WideTy =
             IntegerType::get(getTypeSizeInBits(Start->getType()) * 2);
+          // Check whether Start+Step*BECount has no signed overflow.
           SCEVHandle SMul =
             getMulExpr(CastedBECount,
                        getTruncateOrSignExtend(Step, Start->getType()));
-          // Check whether Start+Step*BECount has no signed overflow.
-          if (getSignExtendExpr(SMul, WideTy) ==
-              getMulExpr(getSignExtendExpr(CastedBECount, WideTy),
-                         getSignExtendExpr(Step, WideTy))) {
-            SCEVHandle Add = getAddExpr(Start, SMul);
-            if (getSignExtendExpr(Add, WideTy) ==
-                getAddExpr(getSignExtendExpr(Start, WideTy),
-                           getSignExtendExpr(SMul, WideTy)))
-              // Return the expression with the addrec on the outside.
-              return getAddRecExpr(getSignExtendExpr(Start, Ty),
-                                   getSignExtendExpr(Step, Ty),
-                                   AR->getLoop());
-          }
+          SCEVHandle Add = getAddExpr(Start, SMul);
+          if (getSignExtendExpr(Add, WideTy) ==
+              getAddExpr(getSignExtendExpr(Start, WideTy),
+                         getMulExpr(getZeroExtendExpr(CastedBECount, WideTy),
+                                    getSignExtendExpr(Step, WideTy))))
+            // Return the expression with the addrec on the outside.
+            return getAddRecExpr(getSignExtendExpr(Start, Ty),
+                                 getSignExtendExpr(Step, Ty),
+                                 AR->getLoop());
         }
       }
     }

Added: llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-0.ll?rev=70421&view=auto

==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-0.ll (added)
+++ llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-0.ll Wed Apr 29 17:28:28 2009
@@ -0,0 +1,31 @@
+; RUN: llvm-as < %s | opt -disable-output -scalar-evolution -analyze \
+; RUN:  | grep { -->  \{-128,+,1\}<bb1>		Exits: 127} | count 5
+
+; Convert (sext {-128,+,1}) to {sext(-128),+,sext(1)}, since the
+; trip count is within range where this is safe.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @foo(double* nocapture %x) nounwind {
+bb1.thread:
+	br label %bb1
+
+bb1:		; preds = %bb1, %bb1.thread
+	%i.0.reg2mem.0 = phi i64 [ -128, %bb1.thread ], [ %8, %bb1 ]		; <i64> [#uses=3]
+	%0 = trunc i64 %i.0.reg2mem.0 to i8		; <i8> [#uses=1]
+	%1 = trunc i64 %i.0.reg2mem.0 to i9		; <i8> [#uses=1]
+	%2 = sext i9 %1 to i64		; <i64> [#uses=1]
+	%3 = getelementptr double* %x, i64 %2		; <double*> [#uses=1]
+	%4 = load double* %3, align 8		; <double> [#uses=1]
+	%5 = mul double %4, 3.900000e+00		; <double> [#uses=1]
+	%6 = sext i8 %0 to i64		; <i64> [#uses=1]
+	%7 = getelementptr double* %x, i64 %6		; <double*> [#uses=1]
+	store double %5, double* %7, align 8
+	%8 = add i64 %i.0.reg2mem.0, 1		; <i64> [#uses=2]
+	%9 = icmp sgt i64 %8, 127		; <i1> [#uses=1]
+	br i1 %9, label %return, label %bb1
+
+return:		; preds = %bb1
+	ret void
+}

Added: llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-1.ll?rev=70421&view=auto

==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-1.ll (added)
+++ llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-1.ll Wed Apr 29 17:28:28 2009
@@ -0,0 +1,100 @@
+; RUN: llvm-as < %s | opt -disable-output -scalar-evolution -analyze \
+; RUN:  | grep { -->  (sext i. \{.\*,+,.\*\}<bb1> to i64)} | count 5
+
+; Don't convert (sext {...,+,...}) to {sext(...),+,sext(...)} in cases
+; where the trip count is not within range.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @foo0(double* nocapture %x) nounwind {
+bb1.thread:
+	br label %bb1
+
+bb1:		; preds = %bb1, %bb1.thread
+	%i.0.reg2mem.0 = phi i64 [ -128, %bb1.thread ], [ %8, %bb1 ]		; <i64> [#uses=3]
+	%0 = trunc i64 %i.0.reg2mem.0 to i7		; <i8> [#uses=1]
+	%1 = trunc i64 %i.0.reg2mem.0 to i9		; <i8> [#uses=1]
+	%2 = sext i9 %1 to i64		; <i64> [#uses=1]
+	%3 = getelementptr double* %x, i64 %2		; <double*> [#uses=1]
+	%4 = load double* %3, align 8		; <double> [#uses=1]
+	%5 = mul double %4, 3.900000e+00		; <double> [#uses=1]
+	%6 = sext i7 %0 to i64		; <i64> [#uses=1]
+	%7 = getelementptr double* %x, i64 %6		; <double*> [#uses=1]
+	store double %5, double* %7, align 8
+	%8 = add i64 %i.0.reg2mem.0, 1		; <i64> [#uses=2]
+	%9 = icmp sgt i64 %8, 127		; <i1> [#uses=1]
+	br i1 %9, label %return, label %bb1
+
+return:		; preds = %bb1
+	ret void
+}
+
+define void @foo1(double* nocapture %x) nounwind {
+bb1.thread:
+	br label %bb1
+
+bb1:		; preds = %bb1, %bb1.thread
+	%i.0.reg2mem.0 = phi i64 [ -128, %bb1.thread ], [ %8, %bb1 ]		; <i64> [#uses=3]
+	%0 = trunc i64 %i.0.reg2mem.0 to i8		; <i8> [#uses=1]
+	%1 = trunc i64 %i.0.reg2mem.0 to i9		; <i8> [#uses=1]
+	%2 = sext i9 %1 to i64		; <i64> [#uses=1]
+	%3 = getelementptr double* %x, i64 %2		; <double*> [#uses=1]
+	%4 = load double* %3, align 8		; <double> [#uses=1]
+	%5 = mul double %4, 3.900000e+00		; <double> [#uses=1]
+	%6 = sext i8 %0 to i64		; <i64> [#uses=1]
+	%7 = getelementptr double* %x, i64 %6		; <double*> [#uses=1]
+	store double %5, double* %7, align 8
+	%8 = add i64 %i.0.reg2mem.0, 1		; <i64> [#uses=2]
+	%9 = icmp sgt i64 %8, 128		; <i1> [#uses=1]
+	br i1 %9, label %return, label %bb1
+
+return:		; preds = %bb1
+	ret void
+}
+
+define void @foo2(double* nocapture %x) nounwind {
+bb1.thread:
+	br label %bb1
+
+bb1:		; preds = %bb1, %bb1.thread
+	%i.0.reg2mem.0 = phi i64 [ -129, %bb1.thread ], [ %8, %bb1 ]		; <i64> [#uses=3]
+	%0 = trunc i64 %i.0.reg2mem.0 to i8		; <i8> [#uses=1]
+	%1 = trunc i64 %i.0.reg2mem.0 to i9		; <i8> [#uses=1]
+	%2 = sext i9 %1 to i64		; <i64> [#uses=1]
+	%3 = getelementptr double* %x, i64 %2		; <double*> [#uses=1]
+	%4 = load double* %3, align 8		; <double> [#uses=1]
+	%5 = mul double %4, 3.900000e+00		; <double> [#uses=1]
+	%6 = sext i8 %0 to i64		; <i64> [#uses=1]
+	%7 = getelementptr double* %x, i64 %6		; <double*> [#uses=1]
+	store double %5, double* %7, align 8
+	%8 = add i64 %i.0.reg2mem.0, 1		; <i64> [#uses=2]
+	%9 = icmp sgt i64 %8, 127		; <i1> [#uses=1]
+	br i1 %9, label %return, label %bb1
+
+return:		; preds = %bb1
+	ret void
+}
+
+define void @foo3(double* nocapture %x) nounwind {
+bb1.thread:
+	br label %bb1
+
+bb1:		; preds = %bb1, %bb1.thread
+	%i.0.reg2mem.0 = phi i64 [ -128, %bb1.thread ], [ %8, %bb1 ]		; <i64> [#uses=3]
+	%0 = trunc i64 %i.0.reg2mem.0 to i8		; <i8> [#uses=1]
+	%1 = trunc i64 %i.0.reg2mem.0 to i9		; <i8> [#uses=1]
+	%2 = sext i9 %1 to i64		; <i64> [#uses=1]
+	%3 = getelementptr double* %x, i64 %2		; <double*> [#uses=1]
+	%4 = load double* %3, align 8		; <double> [#uses=1]
+	%5 = mul double %4, 3.900000e+00		; <double> [#uses=1]
+	%6 = sext i8 %0 to i64		; <i64> [#uses=1]
+	%7 = getelementptr double* %x, i64 %6		; <double*> [#uses=1]
+	store double %5, double* %7, align 8
+	%8 = add i64 %i.0.reg2mem.0, -1		; <i64> [#uses=2]
+	%9 = icmp sgt i64 %8, 127		; <i1> [#uses=1]
+	br i1 %9, label %return, label %bb1
+
+return:		; preds = %bb1
+	ret void
+}




From gohman at apple.com  Wed Apr 29 17:29:01 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 29 Apr 2009 22:29:01 -0000
Subject: [llvm-commits] [llvm] r70422 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <200904292229.n3TMT1NX014070@zion.cs.uiuc.edu>

Author: djg
Date: Wed Apr 29 17:29:01 2009
New Revision: 70422

URL: http://llvm.org/viewvc/llvm-project?rev=70422&view=rev
Log:
Implement getSCEVAtScope for SCEV cast expressions.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=70422&r1=70421&r2=70422&view=diff

==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Apr 29 17:29:01 2009
@@ -2707,8 +2707,31 @@
     return UnknownValue;
   }
 
-  //assert(0 && "Unknown SCEV type!");
-  return UnknownValue;
+  if (SCEVZeroExtendExpr *Cast = dyn_cast<SCEVZeroExtendExpr>(V)) {
+    SCEVHandle Op = getSCEVAtScope(Cast->getOperand(), L);
+    if (Op == UnknownValue) return Op;
+    if (Op == Cast->getOperand())
+      return Cast;  // must be loop invariant
+    return getZeroExtendExpr(Op, Cast->getType());
+  }
+
+  if (SCEVSignExtendExpr *Cast = dyn_cast<SCEVSignExtendExpr>(V)) {
+    SCEVHandle Op = getSCEVAtScope(Cast->getOperand(), L);
+    if (Op == UnknownValue) return Op;
+    if (Op == Cast->getOperand())
+      return Cast;  // must be loop invariant
+    return getSignExtendExpr(Op, Cast->getType());
+  }
+
+  if (SCEVTruncateExpr *Cast = dyn_cast<SCEVTruncateExpr>(V)) {
+    SCEVHandle Op = getSCEVAtScope(Cast->getOperand(), L);
+    if (Op == UnknownValue) return Op;
+    if (Op == Cast->getOperand())
+      return Cast;  // must be loop invariant
+    return getTruncateExpr(Op, Cast->getType());
+  }
+
+  assert(0 && "Unknown SCEV type!");
 }
 
 /// getSCEVAtScope - Return a SCEV expression handle for the specified value




From natebegeman at mac.com  Wed Apr 29 17:47:45 2009
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 29 Apr 2009 22:47:45 -0000
Subject: [llvm-commits] [llvm] r70425 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/Target/X86/X86ISelLowering.cpp
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/vec_shuffle-22.ll
 test/CodeGen/X86/vec_shuffle.ll
Message-ID: <200904292247.n3TMljbT014749@zion.cs.uiuc.edu>

Author: sampo
Date: Wed Apr 29 17:47:44 2009
New Revision: 70425

URL: http://llvm.org/viewvc/llvm-project?rev=70425&view=rev
Log:
Fix infinite recursion in the C++ code which handles movddup by making it unnecessary.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/vec_shuffle-22.ll
    llvm/trunk/test/CodeGen/X86/vec_shuffle.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70425&r1=70424&r2=70425&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Apr 29 17:47:44 2009
@@ -3946,8 +3946,8 @@
       MVT TVT = MVT::getVectorVT(EVT, NumElems);
       if (TLI.isTypeLegal(TVT)) {
         // Turn this into a bit convert of the vector input.
-        Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
-                             LegalizeOp(Node->getOperand(0)));
+        Tmp1 = LegalizeOp(Node->getOperand(0));
+        Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Tmp1);
         break;
       } else if (NumElems == 1) {
         // Turn this into a bit convert of the scalar input.

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=70425&r1=70424&r2=70425&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Apr 29 17:47:44 2009
@@ -2884,44 +2884,6 @@
   return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
 }
 
-/// isVectorLoad - Returns true if the node is a vector load, a scalar
-/// load that's promoted to vector, or a load bitcasted.
-static bool isVectorLoad(SDValue Op) {
-  assert(Op.getValueType().isVector() && "Expected a vector type");
-  if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR ||
-      Op.getOpcode() == ISD::BIT_CONVERT) {
-    return isa<LoadSDNode>(Op.getOperand(0));
-  }
-  return isa<LoadSDNode>(Op);
-}
-
-
-/// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
-///
-static SDValue CanonicalizeMovddup(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
-                                   bool HasSSE3) {
-  // If we have sse3 and shuffle has more than one use or input is a load, then
-  // use movddup. Otherwise, use movlhps.
-  SDValue V1 = SV->getOperand(0);
-  
-  bool UseMovddup = HasSSE3 && (!SV->hasOneUse() || isVectorLoad(V1));
-  MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32;
-  MVT VT = SV->getValueType(0);
-  if (VT == PVT)
-    return SDValue(SV, 0);
-  
-  DebugLoc dl = SV->getDebugLoc();
-  V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
-  if (PVT.getVectorNumElements() == 2) {
-    int Mask[2] = { 0, 0 };
-    V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), Mask);
-  } else {
-    int Mask[4] = { 0, 1, 0, 1 };
-    V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), Mask);
-  }
-  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
-}
-
 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
 /// vector of zero or undef vector.  This produces a shuffle where the low
 /// element of V2 is swizzled into the zero/undef vector, landing at element
@@ -3977,11 +3939,6 @@
   if (isZeroShuffle(SVOp))
     return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
 
-  // Canonicalize movddup shuffles.
-  if (V2IsUndef && Subtarget->hasSSE2() && VT.getSizeInBits() == 128 &&
-      X86::isMOVDDUPMask(SVOp))
-    return CanonicalizeMovddup(SVOp, DAG, Subtarget->hasSSE3());
-
   // Promote splats to v4f32.
   if (SVOp->isSplat()) {
     if (isMMX || NumElems < 4) 

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=70425&r1=70424&r2=70425&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Apr 29 17:47:44 2009
@@ -748,10 +748,12 @@
 } // AddedComplexity
 } // Constraints = "$src1 = $dst"
 
-let AddedComplexity = 20 in
+let AddedComplexity = 20 in {
 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
           (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
-
+def : Pat<(v2i64 (movddup VR128:$src, (undef))),
+          (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
+}
 
 
 
@@ -2430,9 +2432,17 @@
 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
                    (undef)),
           (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
+
+let AddedComplexity = 5 in {
 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
           (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
-
+def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
+          (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
+def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
+          (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
+def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
+          (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
+}
 
 // Arithmetic
 let Constraints = "$src1 = $dst" in {

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-22.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-22.ll?rev=70425&r1=70424&r2=70425&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-22.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-22.ll Wed Apr 29 17:47:44 2009
@@ -1,6 +1,9 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2       | not grep shuf
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2,-sse3 | grep movlhps | count 2
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse3       | grep movddup | count 1
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=pentium-m -o %t -f
+; RUN: grep movlhps %t | count 1
+; RUN: grep pshufd %t | count 1
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 -o %t -f
+; RUN: grep movlhps %t | count 1
+; RUN: grep movddup %t | count 1
 
 define <4 x float> @t1(<4 x float> %a) nounwind  {
 entry:

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle.ll?rev=70425&r1=70424&r2=70425&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle.ll Wed Apr 29 17:47:44 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t -f
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 -o %t -f
 ; RUN: grep shufp   %t | count 1
 ; RUN: grep movupd  %t | count 1
 ; RUN: grep pshufhw %t | count 1




From natebegeman at me.com  Wed Apr 29 17:49:32 2009
From: natebegeman at me.com (Nate Begeman)
Date: Wed, 29 Apr 2009 15:49:32 -0700
Subject: [llvm-commits] [llvm] r70391 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGNodes.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
In-Reply-To: <C52962EB-B6D7-4B0A-995C-DAFFC227938F@apple.com>
References: <200904291813.n3TIDWRM005372@zion.cs.uiuc.edu>
	<C52962EB-B6D7-4B0A-995C-DAFFC227938F@apple.com>
Message-ID: <CB30EFDD-B26C-4371-A1CD-30ACE392B56C@me.com>

Yes.  A rewrite of the VECTOR_SHUFFLE dag combine code is coming; the  
old code was both ineffectual and didn't keep nodes canonicalized.

Nate

On Apr 29, 2009, at 2:31 PM, Evan Cheng wrote:

> I still see this:
>
> SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
>   return SDValue();
> ...
>
> Is the transformations disabled on purpose?
>
> Evan
>
> On Apr 29, 2009, at 11:13 AM, Nate Begeman wrote:
>
>> Author: sampo
>> Date: Wed Apr 29 13:13:31 2009
>> New Revision: 70391
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=70391&view=rev
>> Log:
>> Update comment, replace theoretically impossible check with an  
>> assert.
>>
>> Modified:
>>   llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
>>   llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=70391&r1=70390&r2=70391&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Apr 29
>> 13:13:31 2009
>> @@ -317,13 +317,13 @@
>>    /// IDX, which must be a multiple of the result vector length.
>>    EXTRACT_SUBVECTOR,
>>
>> -    /// VECTOR_SHUFFLE(VEC1, VEC2, SHUFFLEVEC) - Returns a vector,
>> of the same
>> -    /// type as VEC1/VEC2.  SHUFFLEVEC is a BUILD_VECTOR of
>> constant int values
>> -    /// (maybe of an illegal datatype) or undef that indicate which
>> value each
>> -    /// result element will get.  The elements of VEC1/VEC2 are
>> enumerated in
>> -    /// order.  This is quite similar to the Altivec 'vperm'
>> instruction, except
>> -    /// that the indices must be constants and are in terms of the
>> element size
>> -    /// of VEC1/VEC2, not in terms of bytes.
>> +    /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same
>> type as
>> +    /// VEC1/VEC2.  A VECTOR_SHUFFLE node also contains an array of
>> constant int
>> +    /// values that indicate which value (or undef) each result
>> element will
>> +    /// get.  These constant ints are accessible through the
>> +    /// ShuffleVectorSDNode class.  This is quite similar to the
>> Altivec
>> +    /// 'vperm' instruction, except that the indices must be
>> constants and are
>> +    /// in terms of the element size of VEC1/VEC2, not in terms of
>> bytes.
>>    VECTOR_SHUFFLE,
>>
>>    /// SCALAR_TO_VECTOR(VAL) - This represents the operation of
>> loading a
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=70391&r1=70390&r2=70391&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Apr 29
>> 13:13:31 2009
>> @@ -5731,9 +5731,7 @@
>>  for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; +
>> +i)
>>    /* search */;
>>
>> -  // If we hit the end of the mask looking for a non-undef value,
>> return false.
>> -  if (i == e)
>> -    return false;
>> +  assert(i != e && "VECTOR_SHUFFLE node with all undef indices!");
>>
>>  // Make sure all remaining elements are either undef or the same
>> as the first
>>  // non-undef value.
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From dalej at apple.com  Wed Apr 29 17:57:20 2009
From: dalej at apple.com (Dale Johannesen)
Date: Wed, 29 Apr 2009 22:57:20 -0000
Subject: [llvm-commits] [llvm] r70427 -
	/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Message-ID: <200904292257.n3TMvKus015048@zion.cs.uiuc.edu>

Author: johannes
Date: Wed Apr 29 17:57:20 2009
New Revision: 70427

URL: http://llvm.org/viewvc/llvm-project?rev=70427&view=rev
Log:
Print correct instruction in dump.


Modified:
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=70427&r1=70426&r2=70427&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Wed Apr 29 17:57:20 2009
@@ -1808,7 +1808,7 @@
       DOUT << "    Examining use ";
       DEBUG(WriteAsOperand(*DOUT, UsersToProcess.back().OperandValToReplace,
                            /*PrintType=*/false));
-      DOUT << " in Inst: " << *Inst;
+      DOUT << " in Inst: " << *(User.Inst);
 
       // If this instruction wants to use the post-incremented value, move it
       // after the post-inc and use its value instead of the PHI.




From isanbard at gmail.com  Wed Apr 29 18:10:58 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 16:10:58 -0700
Subject: [llvm-commits] [llvm] r70343 - in /llvm/trunk:
	docs/CommandGuide/ include/llvm/CodeGen/ include/llvm/Target/
	lib/CodeGen/ lib/CodeGen/AsmPrinter/
	lib/CodeGen/SelectionDAG/ lib/Target/ARM/
	lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Al
In-Reply-To: <EAB29BD4-DC21-405C-8CE1-32F75440160E@apple.com>
References: <16e5fdf90904291423i962f280v5ad16a0972a23eb5@mail.gmail.com>
	<EAB29BD4-DC21-405C-8CE1-32F75440160E@apple.com>
Message-ID: <16e5fdf90904291610k47d45170q5f5ce8d665a013b3@mail.gmail.com>

On Wed, Apr 29, 2009 at 2:28 PM, Evan Cheng <evan.cheng at apple.com> wrote:
>
> On Apr 29, 2009, at 2:23 PM, Bill Wendling wrote:
>
>> On Wed, Apr 29, 2009 at 2:16 PM, Evan Cheng <evan.cheng at apple.com>
>> wrote:
>>> Bill, you still have to change LTOCodeGenerator.cpp.
>>
>> Done.
>>
>>> Also, rather than
>>> an unsigned for OptLevel, should it be an enum instead? We basically
>>> want to support a knob with 3 levels: no optimization, default
>>> optimization, aggressive optimization. Those correspond to -O0, -
>>> O1 / -
>>> O2 / -Os, -O3.
>>>
>> I'll look into this.
>
> Thanks. With an enum, we can actually document what the values
> mean. :-)

Obviously madness! ;-)

> For llc, lli, and LTO, I think it makes sense to use the
> "aggressive" level by default.
>
I was thinking of having an "LTO" level in the enum...

-bw


From evan.cheng at apple.com  Wed Apr 29 18:18:56 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Apr 2009 16:18:56 -0700
Subject: [llvm-commits] [llvm] r70343 - in
	/llvm/trunk:	docs/CommandGuide/ include/llvm/CodeGen/
	include/llvm/Target/	lib/CodeGen/
	lib/CodeGen/AsmPrinter/	lib/CodeGen/SelectionDAG/
	lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/
	lib/Target/Al
In-Reply-To: <16e5fdf90904291610k47d45170q5f5ce8d665a013b3@mail.gmail.com>
References: <16e5fdf90904291423i962f280v5ad16a0972a23eb5@mail.gmail.com>
	<EAB29BD4-DC21-405C-8CE1-32F75440160E@apple.com>
	<16e5fdf90904291610k47d45170q5f5ce8d665a013b3@mail.gmail.com>
Message-ID: <111ED6F1-BC0E-4541-8DBC-B3D390E3B070@apple.com>


On Apr 29, 2009, at 4:10 PM, Bill Wendling wrote:

> On Wed, Apr 29, 2009 at 2:28 PM, Evan Cheng <evan.cheng at apple.com>  
> wrote:
>>
>> On Apr 29, 2009, at 2:23 PM, Bill Wendling wrote:
>>
>>> On Wed, Apr 29, 2009 at 2:16 PM, Evan Cheng <evan.cheng at apple.com>
>>> wrote:
>>>> Bill, you still have to change LTOCodeGenerator.cpp.
>>>
>>> Done.
>>>
>>>> Also, rather than
>>>> an unsigned for OptLevel, should it be an enum instead? We  
>>>> basically
>>>> want to support a knob with 3 levels: no optimization, default
>>>> optimization, aggressive optimization. Those correspond to -O0, -
>>>> O1 / -
>>>> O2 / -Os, -O3.
>>>>
>>> I'll look into this.
>>
>> Thanks. With an enum, we can actually document what the values
>> mean. :-)
>
> Obviously madness! ;-)
>
>> For llc, lli, and LTO, I think it makes sense to use the
>> "aggressive" level by default.
>>
> I was thinking of having an "LTO" level in the enum...

Why? LTO should not influence how we run codegen passes.

Evan

>
> -bw
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From jyasskin at google.com  Wed Apr 29 18:24:05 2009
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Wed, 29 Apr 2009 16:24:05 -0700
Subject: [llvm-commits] CallbackVH implementation
Message-ID: <bb55930e0904291624h5dbb07bbo6384f75f7669d6b3@mail.gmail.com>

Let me know if you had different names or an entirely different
interface in mind.

I'm a little skeptical of the public copy constructor on CallbackVH,
since it'll slice off any subclass-specific data, but that may not be
a big deal in actual use.

Jeffrey
-------------- next part --------------
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From isanbard at gmail.com  Wed Apr 29 18:26:21 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 23:26:21 -0000
Subject: [llvm-commits] [llvm] r70437 - in /llvm/trunk:
 include/llvm/Support/CommandLine.h lib/Support/CommandLine.cpp
Message-ID: <200904292326.n3TNQM1e015993@zion.cs.uiuc.edu>

Author: void
Date: Wed Apr 29 18:26:16 2009
New Revision: 70437

URL: http://llvm.org/viewvc/llvm-project?rev=70437&view=rev
Log:
Add support for a character after a command line option. Like '-Os'.

Modified:
    llvm/trunk/include/llvm/Support/CommandLine.h
    llvm/trunk/lib/Support/CommandLine.cpp

Modified: llvm/trunk/include/llvm/Support/CommandLine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CommandLine.h?rev=70437&r1=70436&r2=70437&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/CommandLine.h (original)
+++ llvm/trunk/include/llvm/Support/CommandLine.h Wed Apr 29 18:26:16 2009
@@ -679,6 +679,28 @@
 
 EXTERN_TEMPLATE_INSTANTIATION(class basic_parser<std::string>);
 
+//--------------------------------------------------
+// parser<char>
+//
+template<>
+class parser<char> : public basic_parser<char> {
+public:
+  // parse - Return true on error.
+  bool parse(Option &, const char *, const std::string &Arg,
+             char &Value) {
+    Value = Arg[0];
+    return false;
+  }
+
+  // getValueName - Overload in subclass to provide a better default value.
+  virtual const char *getValueName() const { return "char"; }
+
+  // An out-of-line virtual method to provide a 'home' for this class.
+  virtual void anchor();
+};
+
+EXTERN_TEMPLATE_INSTANTIATION(class basic_parser<char>);
+
 //===----------------------------------------------------------------------===//
 // applicator class - This class is used because we must use partial
 // specialization to handle literal string arguments specially (const char* does
@@ -923,6 +945,7 @@
 EXTERN_TEMPLATE_INSTANTIATION(class opt<unsigned>);
 EXTERN_TEMPLATE_INSTANTIATION(class opt<int>);
 EXTERN_TEMPLATE_INSTANTIATION(class opt<std::string>);
+EXTERN_TEMPLATE_INSTANTIATION(class opt<char>);
 EXTERN_TEMPLATE_INSTANTIATION(class opt<bool>);
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Support/CommandLine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=70437&r1=70436&r2=70437&view=diff

==============================================================================
--- llvm/trunk/lib/Support/CommandLine.cpp (original)
+++ llvm/trunk/lib/Support/CommandLine.cpp Wed Apr 29 18:26:16 2009
@@ -45,10 +45,12 @@
 TEMPLATE_INSTANTIATION(class basic_parser<double>);
 TEMPLATE_INSTANTIATION(class basic_parser<float>);
 TEMPLATE_INSTANTIATION(class basic_parser<std::string>);
+TEMPLATE_INSTANTIATION(class basic_parser<char>);
 
 TEMPLATE_INSTANTIATION(class opt<unsigned>);
 TEMPLATE_INSTANTIATION(class opt<int>);
 TEMPLATE_INSTANTIATION(class opt<std::string>);
+TEMPLATE_INSTANTIATION(class opt<char>);
 TEMPLATE_INSTANTIATION(class opt<bool>);
 
 void Option::anchor() {}
@@ -60,6 +62,7 @@
 void parser<double>::anchor() {}
 void parser<float>::anchor() {}
 void parser<std::string>::anchor() {}
+void parser<char>::anchor() {}
 
 //===----------------------------------------------------------------------===//
 




From isanbard at gmail.com  Wed Apr 29 18:28:48 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 23:28:48 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r70438 -
	/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Message-ID: <200904292328.n3TNSnSN016130@zion.cs.uiuc.edu>

Author: void
Date: Wed Apr 29 18:28:45 2009
New Revision: 70438

URL: http://llvm.org/viewvc/llvm-project?rev=70438&view=rev
Log:
Use enums for the optimization level instead of a bare "unsigned' value.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=70438&r1=70437&r2=70438&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Apr 29 18:28:45 2009
@@ -587,11 +587,21 @@
     FunctionPassManager *PM = PerFunctionPasses;    
     HasPerFunctionPasses = true;
 
+    CodeGenOpt::Level OptLevel = CodeGenOpt::Default;
+
+    switch (optimize) {
+    default: break;
+    case 1: OptLevel = CodeGenOpt::One; break;
+    case 2: OptLevel = CodeGenOpt::Two; break;
+    case 3: OptLevel = CodeGenOpt::Aggressive; break;
+    case 4: OptLevel = CodeGenOpt::LTO; break;
+    }
+
     // Normal mode, emit a .s file by running the code generator.
     // Note, this also adds codegenerator level optimization passes.
     switch (TheTarget->addPassesToEmitFile(*PM, *AsmOutRawStream,
                                            TargetMachine::AssemblyFile,
-                                           optimize)) {
+                                           OptLevel)) {
     default:
     case FileModel::Error:
       cerr << "Error interfacing to target machine!\n";
@@ -600,7 +610,7 @@
       break;
     }
 
-    if (TheTarget->addPassesToEmitFileFinish(*PM, 0, optimize)) {
+    if (TheTarget->addPassesToEmitFileFinish(*PM, 0, OptLevel)) {
       cerr << "Error interfacing to target machine!\n";
       exit(1);
     }
@@ -733,11 +743,21 @@
         new FunctionPassManager(new ExistingModuleProvider(TheModule));
       PM->add(new TargetData(*TheTarget->getTargetData()));
 
+      CodeGenOpt::Level OptLevel = CodeGenOpt::Default;
+
+      switch (optimize) {
+      default: break;
+      case 1: OptLevel = CodeGenOpt::One; break;
+      case 2: OptLevel = CodeGenOpt::Two; break;
+      case 3: OptLevel = CodeGenOpt::Aggressive; break;
+      case 4: OptLevel = CodeGenOpt::LTO; break;
+      }
+
       // Normal mode, emit a .s file by running the code generator.
       // Note, this also adds codegenerator level optimization passes.
       switch (TheTarget->addPassesToEmitFile(*PM, *AsmOutRawStream,
                                              TargetMachine::AssemblyFile,
-                                             optimize)) {
+                                             OptLevel)) {
       default:
       case FileModel::Error:
         cerr << "Error interfacing to target machine!\n";
@@ -746,7 +766,7 @@
         break;
       }
 
-      if (TheTarget->addPassesToEmitFileFinish(*PM, 0, optimize)) {
+      if (TheTarget->addPassesToEmitFileFinish(*PM, 0, OptLevel)) {
         cerr << "Error interfacing to target machine!\n";
         exit(1);
       }




From isanbard at gmail.com  Wed Apr 29 18:29:45 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 23:29:45 -0000
Subject: [llvm-commits] [llvm] r70440 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/ExecutionEngine/ include/llvm/Target/
 lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/
 lib/ExecutionEngine/ lib/ExecutionEngine/Interpreter/
 lib/ExecutionEngine/JIT/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/
 lib/Target/Alpha/ lib/Target/Alpha/AsmPrinter/ lib/Target/CBackend/
 lib/Target/CellSPU/ lib/Target/CellSPU/AsmPrinter/ lib/Target/CppBackend/
 lib/Target/IA64/ lib/Target/IA64/AsmPrinter/ lib/Target/MSIL/
 lib/Target/Mips...
Message-ID: <200904292330.n3TNU2Fc016290@zion.cs.uiuc.edu>

Author: void
Date: Wed Apr 29 18:29:43 2009
New Revision: 70440

URL: http://llvm.org/viewvc/llvm-project?rev=70440&view=rev
Log:
Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.

Modified:
    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
    llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
    llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
    llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
    llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h
    llvm/trunk/include/llvm/Target/TargetMachine.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
    llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp
    llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp
    llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h
    llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp
    llvm/trunk/lib/ExecutionEngine/JIT/JIT.h
    llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp
    llvm/trunk/lib/Target/ARM/ARM.h
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/Alpha/Alpha.h
    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
    llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
    llvm/trunk/lib/Target/CBackend/CBackend.cpp
    llvm/trunk/lib/Target/CBackend/CTargetMachine.h
    llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
    llvm/trunk/lib/Target/CellSPU/SPU.h
    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
    llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
    llvm/trunk/lib/Target/IA64/IA64.h
    llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
    llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
    llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
    llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
    llvm/trunk/lib/Target/Mips/Mips.h
    llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
    llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
    llvm/trunk/lib/Target/PIC16/PIC16.h
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
    llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
    llvm/trunk/lib/Target/PowerPC/PPC.h
    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
    llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
    llvm/trunk/lib/Target/Sparc/Sparc.h
    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
    llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
    llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
    llvm/trunk/lib/Target/X86/X86.h
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.h
    llvm/trunk/lib/Target/XCore/XCore.h
    llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
    llvm/trunk/tools/llc/llc.cpp
    llvm/trunk/tools/lli/lli.cpp
    llvm/trunk/tools/lto/LTOCodeGenerator.cpp
    llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Wed Apr 29 18:29:43 2009
@@ -16,9 +16,10 @@
 #ifndef LLVM_CODEGEN_ASMPRINTER_H
 #define LLVM_CODEGEN_ASMPRINTER_H
 
+#include "llvm/ADT/DenseMap.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/Support/DataTypes.h"
-#include "llvm/ADT/DenseMap.h"
+#include "llvm/Target/TargetMachine.h"
 #include <set>
 
 namespace llvm {
@@ -66,7 +67,7 @@
     std::set<const GlobalValue*> ExtWeakSymbols;
 
     /// OptLevel - Generating code at a specific optimization level.
-    unsigned OptLevel;
+    CodeGenOpt::Level OptLevel;
   public:
     /// Output stream on which we're printing assembly code.
     ///
@@ -111,7 +112,7 @@
 
   protected:
     explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
-                        const TargetAsmInfo *T, unsigned OL, bool V);
+                        const TargetAsmInfo *T, CodeGenOpt::Level OL, bool V);
     
   public:
     virtual ~AsmPrinter();

Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Wed Apr 29 18:29:43 2009
@@ -21,6 +21,7 @@
 #define LLVM_CODEGEN_DWARFWRITER_H
 
 #include "llvm/Pass.h"
+#include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
 
@@ -81,7 +82,7 @@
   void EndFunction(MachineFunction *MF);
 
   /// ValidDebugInfo - Return true if V represents valid debug info value.
-  bool ValidDebugInfo(Value *V, unsigned OptLevel);
+  bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel);
 
   /// RecordSourceLine - Register a source line with debug info. Returns a
   /// unique label ID used to generate a label and provide correspondence to

Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Wed Apr 29 18:29:43 2009
@@ -18,6 +18,7 @@
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
 #include "llvm/CodeGen/GCs.h"
+#include "llvm/Target/TargetMachine.h"
 
 namespace {
   struct ForceCodegenLinking {
@@ -42,11 +43,11 @@
       llvm::linkOcamlGC();
       llvm::linkShadowStackGC();
       
-      (void) llvm::createBURRListDAGScheduler(NULL, 3);
-      (void) llvm::createTDRRListDAGScheduler(NULL, 3);
-      (void) llvm::createTDListDAGScheduler(NULL, 3);
-      (void) llvm::createFastDAGScheduler(NULL, 3);
-      (void) llvm::createDefaultScheduler(NULL, 3);
+      (void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+      (void) llvm::createTDRRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+      (void) llvm::createTDListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+      (void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+      (void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default);
 
     }
   } ForceCodegenLinking; // Force link by creating a global definition.

Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Wed Apr 29 18:29:43 2009
@@ -16,6 +16,7 @@
 #define LLVM_CODEGENSCHEDULERREGISTRY_H
 
 #include "llvm/CodeGen/MachinePassRegistry.h"
+#include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
 
@@ -32,7 +33,8 @@
 
 class RegisterScheduler : public MachinePassRegistryNode {
 public:
-  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned);
+  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
+                                                  CodeGenOpt::Level);
 
   static MachinePassRegistry Registry;
 
@@ -64,27 +66,27 @@
 /// createBURRListDAGScheduler - This creates a bottom up register usage
 /// reduction list scheduler.
 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
-                                               unsigned OptLevel);
+                                               CodeGenOpt::Level OptLevel);
 
 /// createTDRRListDAGScheduler - This creates a top down register usage
 /// reduction list scheduler.
 ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
-                                               unsigned OptLevel);
+                                               CodeGenOpt::Level OptLevel);
 
 /// createTDListDAGScheduler - This creates a top-down list scheduler with
 /// a hazard recognizer.
 ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
-                                             unsigned OptLevel);
+                                             CodeGenOpt::Level OptLevel);
 
 /// createFastDAGScheduler - This creates a "fast" scheduler.
 ///
 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
-                                           unsigned OptLevel);
+                                           CodeGenOpt::Level OptLevel);
 
 /// createDefaultScheduler - This creates an instruction scheduler appropriate
 /// for the target.
 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
-                                           unsigned OptLevel);
+                                           CodeGenOpt::Level OptLevel);
 
 } // end namespace llvm
 

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Apr 29 18:29:43 2009
@@ -20,7 +20,7 @@
 #include "llvm/ADT/FoldingSet.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
-
+#include "llvm/Target/TargetMachine.h"
 #include <cassert>
 #include <vector>
 #include <map>
@@ -30,7 +30,6 @@
 
 class AliasAnalysis;
 class TargetLowering;
-class TargetMachine;
 class MachineModuleInfo;
 class DwarfWriter;
 class MachineFunction;
@@ -202,7 +201,8 @@
   /// certain types of nodes together, or eliminating superfluous nodes.  The
   /// Level argument controls whether Combine is allowed to produce nodes and
   /// types that are illegal on the target.
-  void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned OptLevel);
+  void Combine(CombineLevel Level, AliasAnalysis &AA,
+               CodeGenOpt::Level OptLevel);
 
   /// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that
   /// only uses types natively supported by the target.  Returns "true" if it
@@ -218,7 +218,7 @@
   ///
   /// Note that this is an involved process that may invalidate pointers into
   /// the graph.
-  void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
+  void Legalize(bool TypesNeedLegalizing, CodeGenOpt::Level OptLevel);
 
   /// RemoveDeadNodes - This method deletes all unreachable nodes in the
   /// SelectionDAG.

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Wed Apr 29 18:29:43 2009
@@ -51,10 +51,11 @@
   MachineBasicBlock *BB;
   AliasAnalysis *AA;
   GCFunctionInfo *GFI;
-  unsigned OptLevel;
+  CodeGenOpt::Level OptLevel;
   static char ID;
 
-  explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
+  explicit SelectionDAGISel(TargetMachine &tm,
+                            CodeGenOpt::Level OL = CodeGenOpt::Default);
   virtual ~SelectionDAGISel();
   
   TargetLowering &getTargetLowering() { return TLI; }

Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h (original)
+++ llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Wed Apr 29 18:29:43 2009
@@ -18,8 +18,9 @@
 #include <vector>
 #include <map>
 #include <string>
-#include "llvm/System/Mutex.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/System/Mutex.h"
+#include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
 
@@ -84,7 +85,7 @@
   // libraries, the JIT and Interpreter set these functions to ctor pointers
   // at startup time if they are linked in.
   typedef ExecutionEngine *(*EECtorFn)(ModuleProvider*, std::string*,
-                                       unsigned OptLevel);
+                                       CodeGenOpt::Level OptLevel);
   static EECtorFn JITCtor, InterpCtor;
 
   /// LazyFunctionCreator - If an unknown function is needed, this function
@@ -114,7 +115,8 @@
   static ExecutionEngine *create(ModuleProvider *MP,
                                  bool ForceInterpreter = false,
                                  std::string *ErrorStr = 0,
-                                 unsigned OptLevel = 3);
+                                 CodeGenOpt::Level OptLevel =
+                                   CodeGenOpt::Default);
   
   /// create - This is the factory method for creating an execution engine which
   /// is appropriate for the current machine.  This takes ownership of the
@@ -127,10 +129,9 @@
   static ExecutionEngine *createJIT(ModuleProvider *MP,
                                     std::string *ErrorStr = 0,
                                     JITMemoryManager *JMM = 0,
-                                    unsigned OptLevel = 3);
-  
-  
-  
+                                    CodeGenOpt::Level OptLevel =
+                                      CodeGenOpt::Default);
+
   /// addModuleProvider - Add a ModuleProvider to the list of modules that we
   /// can JIT from.  Note that this takes ownership of the ModuleProvider: when
   /// the ExecutionEngine is destroyed, it destroys the MP as well.

Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
+++ llvm/trunk/include/llvm/Target/TargetMachine.h Wed Apr 29 18:29:43 2009
@@ -68,6 +68,19 @@
   };
 }
 
+// Code generation optimization level.
+namespace CodeGenOpt {
+  enum Level {
+    Default,
+    None,
+    One,
+    Two,
+    Size,
+    Aggressive,
+    LTO
+  };
+}
+
 //===----------------------------------------------------------------------===//
 ///
 /// TargetMachine - Primary interface to the complete machine description for
@@ -213,7 +226,7 @@
   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
                                                raw_ostream &,
                                                CodeGenFileType,
-                                               unsigned /* OptLevel */) {
+                                               CodeGenOpt::Level) {
     return FileModel::None;
   }
 
@@ -223,7 +236,7 @@
   ///
   virtual bool addPassesToEmitFileFinish(PassManagerBase &,
                                          MachineCodeEmitter *,
-                                         unsigned /* OptLevel */) {
+                                         CodeGenOpt::Level) {
     return true;
   }
  
@@ -235,7 +248,7 @@
   ///
   virtual bool addPassesToEmitMachineCode(PassManagerBase &,
                                           MachineCodeEmitter &,
-                                          unsigned /* OptLevel */) {
+                                          CodeGenOpt::Level) {
     return true;
   }
 
@@ -245,7 +258,7 @@
   virtual bool WantsWholeFile() const { return false; }
   virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
                                         CodeGenFileType,
-                                        unsigned /* OptLevel */) {
+                                        CodeGenOpt::Level) {
     return true;
   }
 };
@@ -260,13 +273,13 @@
   /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
   /// both emitting to assembly files or machine code output.
   ///
-  bool addCommonCodeGenPasses(PassManagerBase &, unsigned /* OptLevel */);
+  bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level);
 
 public:
   
   /// addPassesToEmitFile - Add passes to the specified pass manager to get the
   /// specified file emitted.  Typically this will involve several steps of code
-  /// generation.  If OptLevel is 0, the code generator should emit code as fast
+  /// generation.  If OptLevel is None, the code generator should emit code as fast
   /// as possible, though the generated code may be less efficient.  This method
   /// should return FileModel::Error if emission of this file type is not
   /// supported.
@@ -278,7 +291,7 @@
   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
                                                raw_ostream &Out,
                                                CodeGenFileType FileType,
-                                               unsigned OptLevel);
+                                               CodeGenOpt::Level);
   
   /// addPassesToEmitFileFinish - If the passes to emit the specified file had
   /// to be split up (e.g., to add an object writer pass), this method can be
@@ -286,7 +299,7 @@
   ///
   virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
                                          MachineCodeEmitter *MCE,
-                                         unsigned OptLevel);
+                                         CodeGenOpt::Level);
  
   /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
   /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
@@ -296,21 +309,21 @@
   ///
   virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
                                           MachineCodeEmitter &MCE,
-                                          unsigned OptLevel);
+                                          CodeGenOpt::Level);
   
   /// Target-Independent Code Generator Pass Configuration Options.
   
   /// addInstSelector - This method should add any "last minute" LLVM->LLVM
   /// passes, then install an instruction selector pass, which converts from
   /// LLVM code to machine instructions.
-  virtual bool addInstSelector(PassManagerBase &, unsigned /* OptLevel */) {
+  virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
     return true;
   }
 
   /// addPreRegAllocPasses - This method may be implemented by targets that want
   /// to run passes immediately before register allocation. This should return
   /// true if -print-machineinstrs should print after these passes.
-  virtual bool addPreRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
+  virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
     return false;
   }
 
@@ -318,14 +331,14 @@
   /// want to run passes after register allocation but before prolog-epilog
   /// insertion.  This should return true if -print-machineinstrs should print
   /// after these passes.
-  virtual bool addPostRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
+  virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
     return false;
   }
   
   /// addPreEmitPass - This pass may be implemented by targets that want to run
   /// passes immediately before machine code is emitted.  This should return
   /// true if -print-machineinstrs should print out the code after the passes.
-  virtual bool addPreEmitPass(PassManagerBase &, unsigned /* OptLevel */) {
+  virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
     return false;
   }
   
@@ -333,7 +346,7 @@
   /// addAssemblyEmitter - This pass should be overridden by the target to add
   /// the asmprinter, if asm emission is supported.  If this is not supported,
   /// 'true' should be returned.
-  virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /* OptLevel */,
+  virtual bool addAssemblyEmitter(PassManagerBase &, CodeGenOpt::Level,
                                   bool /* VerboseAsmDefault */, raw_ostream &) {
     return true;
   }
@@ -341,7 +354,7 @@
   /// addCodeEmitter - This pass should be overridden by the target to add a
   /// code emitter, if supported.  If this is not supported, 'true' should be
   /// returned. If DumpAsm is true, the generated assembly is printed to cerr.
-  virtual bool addCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
+  virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
                               bool /*DumpAsm*/, MachineCodeEmitter &) {
     return true;
   }
@@ -350,7 +363,7 @@
   /// a code emitter (without setting flags), if supported.  If this is not
   /// supported, 'true' should be returned.  If DumpAsm is true, the generated
   /// assembly is printed to cerr.
-  virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
                                     bool /*DumpAsm*/, MachineCodeEmitter &) {
     return true;
   }

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Apr 29 18:29:43 2009
@@ -27,7 +27,6 @@
 #include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/ADT/SmallPtrSet.h"
@@ -42,7 +41,7 @@
 
 char AsmPrinter::ID = 0;
 AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
-                       const TargetAsmInfo *T, unsigned OL, bool VDef)
+                       const TargetAsmInfo *T, CodeGenOpt::Level OL, bool VDef)
   : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
     TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
     IsInTextSection(false)

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Wed Apr 29 18:29:43 2009
@@ -3351,7 +3351,7 @@
   }
 
   /// ValidDebugInfo - Return true if V represents valid debug info value.
-  bool ValidDebugInfo(Value *V, unsigned OptLevel) {
+  bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) {
     if (!V)
       return false;
 
@@ -3393,7 +3393,7 @@
     case DW_TAG_lexical_block:
       /// FIXME. This interfers with the qualitfy of generated code when 
       /// during optimization.
-      if (OptLevel != 0)
+      if (OptLevel != CodeGenOpt::None)
         return false;
     default:
       break;
@@ -4731,7 +4731,7 @@
 }
 
 /// ValidDebugInfo - Return true if V represents valid debug info value.
-bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
+bool DwarfWriter::ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) {
   return DD && DD->ValidDebugInfo(V, OptLevel);
 }
 

Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Apr 29 18:29:43 2009
@@ -55,7 +55,7 @@
 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                        raw_ostream &Out,
                                        CodeGenFileType FileType,
-                                       unsigned OptLevel) {
+                                       CodeGenOpt::Level OptLevel) {
   // Add common CodeGen passes.
   if (addCommonCodeGenPasses(PM, OptLevel))
     return FileModel::Error;
@@ -69,7 +69,7 @@
   if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (OptLevel != 0)
+  if (OptLevel != CodeGenOpt::None)
     PM.add(createLoopAlignerPass());
 
   switch (FileType) {
@@ -94,7 +94,7 @@
 /// finish up adding passes to emit the file, if necessary.
 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
                                                   MachineCodeEmitter *MCE,
-                                                  unsigned OptLevel) {
+                                                  CodeGenOpt::Level OptLevel) {
   if (MCE)
     addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
 
@@ -114,7 +114,7 @@
 ///
 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
                                                    MachineCodeEmitter &MCE,
-                                                   unsigned OptLevel) {
+                                                   CodeGenOpt::Level OptLevel) {
   // Add common CodeGen passes.
   if (addCommonCodeGenPasses(PM, OptLevel))
     return true;
@@ -132,15 +132,15 @@
   return false; // success!
 }
 
-/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
-/// both emitting to assembly files or machine code output.
+/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
+/// emitting to assembly files or machine code output.
 ///
 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
-                                               unsigned OptLevel) {
+                                               CodeGenOpt::Level OptLevel) {
   // Standard LLVM-Level Passes.
 
   // Run loop strength reduction before anything else.
-  if (OptLevel != 0) {
+  if (OptLevel != CodeGenOpt::None) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     if (PrintLSR)
       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
@@ -154,7 +154,7 @@
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
-  if (OptLevel != 0)
+  if (OptLevel != CodeGenOpt::None)
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
   PM.add(createStackProtectorPass(getTargetLowering()));
@@ -168,7 +168,7 @@
 
   // Enable FastISel with -fast, but allow that to be overridden.
   if (EnableFastISelOption == cl::BOU_TRUE ||
-      (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
+      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
     EnableFastISel = true;
 
   // Ask the target for an isel.
@@ -179,7 +179,7 @@
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (OptLevel != 0) {
+  if (OptLevel != CodeGenOpt::None) {
     PM.add(createMachineLICMPass());
     PM.add(createMachineSinkingPass());
   }
@@ -192,7 +192,7 @@
   PM.add(createRegisterAllocator());
 
   // Perform stack slot coloring.
-  if (OptLevel != 0)
+  if (OptLevel != CodeGenOpt::None)
     PM.add(createStackSlotColoringPass());
 
   if (PrintMachineCode)  // Print the register-allocated code
@@ -217,7 +217,7 @@
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Second pass scheduler.
-  if (OptLevel != 0 && !DisablePostRAScheduler) {
+  if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
     PM.add(createPostRAScheduler());
 
     if (PrintMachineCode)
@@ -225,7 +225,7 @@
   }
 
   // Branch folding must be run after regalloc and prolog/epilog insertion.
-  if (OptLevel != 0)
+  if (OptLevel != CodeGenOpt::None)
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 
   if (PrintMachineCode)

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Apr 29 18:29:43 2009
@@ -57,7 +57,7 @@
     SelectionDAG &DAG;
     const TargetLowering &TLI;
     CombineLevel Level;
-    unsigned OptLevel;
+    CodeGenOpt::Level OptLevel;
     bool LegalOperations;
     bool LegalTypes;
 
@@ -254,7 +254,7 @@
     }
 
 public:
-    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
+    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
       : DAG(D),
         TLI(D.getTargetLoweringInfo()),
         Level(Unrestricted),
@@ -4784,7 +4784,7 @@
   SDValue Ptr   = LD->getBasePtr();
 
   // Try to infer better alignment information than the load already has.
-  if (OptLevel != 0 && LD->isUnindexed()) {
+  if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > LD->getAlignment())
         return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
@@ -4904,7 +4904,7 @@
   SDValue Ptr   = ST->getBasePtr();
 
   // Try to infer better alignment information than the store already has.
-  if (OptLevel != 0 && ST->isUnindexed()) {
+  if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > ST->getAlignment())
         return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
@@ -6093,7 +6093,7 @@
 // SelectionDAG::Combine - This is the entry point for the file.
 //
 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
-                           unsigned OptLevel) {
+                           CodeGenOpt::Level OptLevel) {
   /// run - This is the main entry point to this class.
   ///
   DAGCombiner(*this, AA, OptLevel).Run(Level);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Apr 29 18:29:43 2009
@@ -327,7 +327,7 @@
   default: break;
   case Intrinsic::dbg_stoppoint: {
     DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
-    if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
+    if (DW && DW->ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) {
       DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
       std::string Dir, FN;
       unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
@@ -344,7 +344,7 @@
   }
   case Intrinsic::dbg_region_start: {
     DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
-    if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
+    if (DW && DW->ValidDebugInfo(RSI->getContext(), CodeGenOpt::None)) {
       unsigned ID = 
         DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
@@ -354,7 +354,7 @@
   }
   case Intrinsic::dbg_region_end: {
     DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
-    if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
+    if (DW && DW->ValidDebugInfo(REI->getContext(), CodeGenOpt::None)) {
      unsigned ID = 0;
      DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
      if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
@@ -380,7 +380,7 @@
     DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
     Value *SP = FSI->getSubprogram();
 
-    if (DW->ValidDebugInfo(SP, 0)) {
+    if (DW->ValidDebugInfo(SP, CodeGenOpt::None)) {
       // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
       // (most?) gdb expects.
       DebugLoc PrevLoc = DL;
@@ -425,7 +425,7 @@
   case Intrinsic::dbg_declare: {
     DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
     Value *Variable = DI->getVariable();
-    if (DW && DW->ValidDebugInfo(Variable, 0)) {
+    if (DW && DW->ValidDebugInfo(Variable, CodeGenOpt::None)) {
       // Determine the address of the declared object.
       Value *Address = DI->getAddress();
       if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Apr 29 18:29:43 2009
@@ -55,7 +55,7 @@
 class VISIBILITY_HIDDEN SelectionDAGLegalize {
   TargetLowering &TLI;
   SelectionDAG &DAG;
-  unsigned OptLevel;
+  CodeGenOpt::Level OptLevel;
   bool TypesNeedLegalizing;
 
   // Libcall insertion helpers.
@@ -139,7 +139,7 @@
 
 public:
   explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
-                                unsigned ol);
+                                CodeGenOpt::Level ol);
 
   /// getTypeAction - Return how we should legalize values of this type, either
   /// it is already legal or we need to expand it into multiple registers of
@@ -350,7 +350,7 @@
 }
 
 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
-                                           bool types, unsigned ol)
+                                           bool types, CodeGenOpt::Level ol)
   : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
     TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) {
   assert(MVT::LAST_VALUETYPE <= 32 &&
@@ -1276,7 +1276,7 @@
         unsigned Line = DSP->getLine();
         unsigned Col = DSP->getColumn();
 
-        if (OptLevel == 0) {
+        if (OptLevel == CodeGenOpt::None) {
           // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
           // won't hurt anything.
           if (useDEBUG_LOC) {
@@ -8571,7 +8571,8 @@
 
 // SelectionDAG::Legalize - This is the entry point for the file.
 //
-void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) {
+void SelectionDAG::Legalize(bool TypesNeedLegalizing,
+                            CodeGenOpt::Level OptLevel) {
   /// run - This is the main entry point to this class.
   ///
   SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG();

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Wed Apr 29 18:29:43 2009
@@ -630,6 +630,6 @@
 //===----------------------------------------------------------------------===//
 
 llvm::ScheduleDAGSDNodes *
-llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
   return new ScheduleDAGFast(*IS->MF);
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Wed Apr 29 18:29:43 2009
@@ -261,7 +261,7 @@
 /// new hazard recognizer. This scheduler takes ownership of the hazard
 /// recognizer and deletes it when done.
 ScheduleDAGSDNodes *
-llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createTDListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
   return new ScheduleDAGList(*IS->MF,
                              new LatencyPriorityQueue(),
                              IS->CreateTargetHazardRecognizer());

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Apr 29 18:29:43 2009
@@ -1505,7 +1505,7 @@
 //===----------------------------------------------------------------------===//
 
 llvm::ScheduleDAGSDNodes *
-llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
   const TargetMachine &TM = IS->TM;
   const TargetInstrInfo *TII = TM.getInstrInfo();
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
@@ -1519,7 +1519,7 @@
 }
 
 llvm::ScheduleDAGSDNodes *
-llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
   const TargetMachine &TM = IS->TM;
   const TargetInstrInfo *TII = TM.getInstrInfo();
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed Apr 29 18:29:43 2009
@@ -45,7 +45,6 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetIntrinsicInfo.h"
 #include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/CommandLine.h"
@@ -335,7 +334,8 @@
             DwarfWriter *DW = DAG.getDwarfWriter();
             DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
 
-            if (DW && DW->ValidDebugInfo(SPI->getContext(), false)) {
+            if (DW && DW->ValidDebugInfo(SPI->getContext(),
+                                         CodeGenOpt::Default)) {
               DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
               std::string Dir, FN;
               unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
@@ -354,7 +354,7 @@
               DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
               Value *SP = FSI->getSubprogram();
 
-              if (DW->ValidDebugInfo(SP, false)) {
+              if (DW->ValidDebugInfo(SP, CodeGenOpt::Default)) {
                 DISubprogram Subprogram(cast<GlobalVariable>(SP));
                 DICompileUnit CU(Subprogram.getCompileUnit());
                 std::string Dir, FN;
@@ -3899,7 +3899,7 @@
     DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
     if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
       MachineFunction &MF = DAG.getMachineFunction();
-      if (OptLevel == 0)
+      if (OptLevel == CodeGenOpt::None)
         DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
                                         SPI.getLine(),
                                         SPI.getColumn(),
@@ -3940,7 +3940,7 @@
           && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
           // This is end of inlined function. Debugging information for
           // inlined function is not handled yet (only supported by FastISel).
-        if (OptLevel == 0) {
+        if (OptLevel == CodeGenOpt::None) {
           unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
           if (ID != 0)
             // Returned ID is 0 if this is unbalanced "end of inlined
@@ -3968,7 +3968,7 @@
     Value *SP = FSI.getSubprogram();
     if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
       MachineFunction &MF = DAG.getMachineFunction();
-      if (OptLevel == 0) {
+      if (OptLevel == CodeGenOpt::None) {
         // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
         // (most?) gdb expects.
         DebugLoc PrevLoc = CurDebugLoc;
@@ -4039,7 +4039,7 @@
     return 0;
   }
   case Intrinsic::dbg_declare: {
-    if (OptLevel == 0) {
+    if (OptLevel == CodeGenOpt::None) {
       DwarfWriter *DW = DAG.getDwarfWriter();
       DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
       Value *Variable = DI.getVariable();

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Wed Apr 29 18:29:43 2009
@@ -23,6 +23,7 @@
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/Support/CallSite.h"
+#include "llvm/Target/TargetMachine.h"
 #include <vector>
 #include <set>
 
@@ -357,13 +358,14 @@
 
   /// OptLevel - What optimization level we're generating code for.
   /// 
-  unsigned OptLevel;
+  CodeGenOpt::Level OptLevel;
   
   /// GFI - Garbage collection metadata for the function.
   GCFunctionInfo *GFI;
 
   SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
-                       FunctionLoweringInfo &funcinfo, unsigned ol)
+                       FunctionLoweringInfo &funcinfo,
+                       CodeGenOpt::Level ol)
     : CurDebugLoc(DebugLoc::getUnknownLoc()), 
       TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
   }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Apr 29 18:29:43 2009
@@ -136,10 +136,10 @@
   /// createDefaultScheduler - This creates an instruction scheduler appropriate
   /// for the target.
   ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
-                                             unsigned OptLevel) {
+                                             CodeGenOpt::Level OptLevel) {
     const TargetLowering &TLI = IS->getTargetLowering();
 
-    if (OptLevel == 0)
+    if (OptLevel == CodeGenOpt::None)
       return createFastDAGScheduler(IS, OptLevel);
     if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
       return createTDListDAGScheduler(IS, OptLevel);
@@ -262,7 +262,7 @@
 // SelectionDAGISel code
 //===----------------------------------------------------------------------===//
 
-SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
+SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
   FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
   FuncInfo(new FunctionLoweringInfo(TLI)),
   CurDAG(new SelectionDAG(TLI, *FuncInfo)),
@@ -645,7 +645,7 @@
 
   if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
   
-  if (OptLevel != 0)
+  if (OptLevel != CodeGenOpt::None)
     ComputeLiveOutVRegInfo();
 
   // Third, instruction select all of the operations to machine code, adding the

Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Wed Apr 29 18:29:43 2009
@@ -383,7 +383,7 @@
 ExecutionEngine *ExecutionEngine::create(ModuleProvider *MP,
                                          bool ForceInterpreter,
                                          std::string *ErrorStr,
-                                         unsigned OptLevel) {
+                                         CodeGenOpt::Level OptLevel) {
   ExecutionEngine *EE = 0;
 
   // Make sure we can resolve symbols in the program as well. The zero arg

Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp Wed Apr 29 18:29:43 2009
@@ -114,7 +114,7 @@
 
 int LLVMCreateJITCompiler(LLVMExecutionEngineRef *OutJIT,
                           LLVMModuleProviderRef MP,
-                          unsigned OptLevel,
+                          CodeGenOpt::Level OptLevel,
                           char **OutError) {
   std::string Error;
   if (ExecutionEngine *JIT = ExecutionEngine::createJIT(unwrap(MP), &Error, 0,

Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp Wed Apr 29 18:29:43 2009
@@ -37,7 +37,7 @@
 /// create - Create a new interpreter object.  This can never fail.
 ///
 ExecutionEngine *Interpreter::create(ModuleProvider *MP, std::string* ErrStr,
-                                     unsigned OptLevel /*unused*/) {
+                                     CodeGenOpt::Level OptLevel /*unused*/) {
   // Tell this ModuleProvide to materialize and release the module
   if (!MP->materializeModule(ErrStr))
     // We got an error, just return 0

Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h (original)
+++ llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h Wed Apr 29 18:29:43 2009
@@ -108,7 +108,7 @@
   /// create - Create an interpreter ExecutionEngine. This can never fail.
   ///
   static ExecutionEngine *create(ModuleProvider *M, std::string *ErrorStr = 0,
-                                 unsigned OptLevel /*unused*/ = 3);
+                                 CodeGenOpt::Level = CodeGenOpt::Default);
 
   /// run - Start execution with the specified function and arguments.
   ///

Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp Wed Apr 29 18:29:43 2009
@@ -196,7 +196,7 @@
 ExecutionEngine *ExecutionEngine::createJIT(ModuleProvider *MP,
                                             std::string *ErrorStr,
                                             JITMemoryManager *JMM,
-                                            unsigned OptLevel) {
+                                            CodeGenOpt::Level OptLevel) {
   ExecutionEngine *EE = JIT::createJIT(MP, ErrorStr, JMM, OptLevel);
   if (!EE) return 0;
   
@@ -207,7 +207,7 @@
 }
 
 JIT::JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji,
-         JITMemoryManager *JMM, unsigned OptLevel)
+         JITMemoryManager *JMM, CodeGenOpt::Level OptLevel)
   : ExecutionEngine(MP), TM(tm), TJI(tji) {
   setTargetData(TM.getTargetData());
 
@@ -272,7 +272,7 @@
 
     // Turn the machine code intermediate representation into bytes in memory
     // that may be executed.
-    if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
+    if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) {
       cerr << "Target does not support machine code emission!\n";
       abort();
     }
@@ -305,7 +305,7 @@
     
     // Turn the machine code intermediate representation into bytes in memory
     // that may be executed.
-    if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
+    if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) {
       cerr << "Target does not support machine code emission!\n";
       abort();
     }
@@ -337,7 +337,7 @@
     
     // Turn the machine code intermediate representation into bytes in memory
     // that may be executed.
-    if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
+    if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) {
       cerr << "Target does not support machine code emission!\n";
       abort();
     }

Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JIT.h (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.h Wed Apr 29 18:29:43 2009
@@ -55,7 +55,7 @@
   JITState *jitstate;
 
   JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji, 
-      JITMemoryManager *JMM, unsigned OptLevel);
+      JITMemoryManager *JMM, CodeGenOpt::Level OptLevel);
 public:
   ~JIT();
 
@@ -71,7 +71,8 @@
   /// for the current target.  Otherwise, return null.
   ///
   static ExecutionEngine *create(ModuleProvider *MP, std::string *Err,
-                                 unsigned OptLevel = 3) {
+                                 CodeGenOpt::Level OptLevel =
+                                   CodeGenOpt::Default) {
     return createJIT(MP, Err, 0, OptLevel);
   }
 
@@ -148,7 +149,8 @@
   MachineCodeEmitter *getCodeEmitter() const { return MCE; }
   
   static ExecutionEngine *createJIT(ModuleProvider *MP, std::string *Err,
-                                    JITMemoryManager *JMM, unsigned OptLevel);
+                                    JITMemoryManager *JMM,
+                                    CodeGenOpt::Level OptLevel);
   
 private:
   static MachineCodeEmitter *createEmitter(JIT &J, JITMemoryManager *JMM);

Modified: llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp Wed Apr 29 18:29:43 2009
@@ -42,7 +42,8 @@
 /// available for the current target.  Otherwise, return null.
 ///
 ExecutionEngine *JIT::createJIT(ModuleProvider *MP, std::string *ErrorStr,
-                                JITMemoryManager *JMM, unsigned OptLevel) {
+                                JITMemoryManager *JMM,
+                                CodeGenOpt::Level OptLevel) {
   const TargetMachineRegistry::entry *TheArch = MArch;
   if (TheArch == 0) {
     std::string Error;

Modified: llvm/trunk/lib/Target/ARM/ARM.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.h (original)
+++ llvm/trunk/lib/Target/ARM/ARM.h Wed Apr 29 18:29:43 2009
@@ -15,6 +15,7 @@
 #ifndef TARGET_ARM_H
 #define TARGET_ARM_H
 
+#include "llvm/Target/TargetMachine.h"
 #include <cassert>
 
 namespace llvm {
@@ -91,7 +92,8 @@
 FunctionPass *createARMISelDag(ARMTargetMachine &TM);
 FunctionPass *createARMCodePrinterPass(raw_ostream &O,
                                        ARMTargetMachine &TM,
-                                       unsigned OptLevel, bool Verbose);
+                                       CodeGenOpt::Level OptLevel,
+                                       bool Verbose);
 FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
                                        MachineCodeEmitter &MCE);
 FunctionPass *createARMLoadStoreOptimizationPass();

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Apr 29 18:29:43 2009
@@ -138,17 +138,20 @@
 
 
 // Pass Pipeline Configuration
-bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
+                                       CodeGenOpt::Level OptLevel) {
   PM.add(createARMISelDag(*this));
   return false;
 }
 
-bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
+bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM,
+                                      CodeGenOpt::Level OptLevel) {
   // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
-  if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
+  if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
     PM.add(createARMLoadStoreOptimizationPass());
 
-  if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
+  if (OptLevel != CodeGenOpt::None &&
+      !DisableIfConversion && !Subtarget.isThumb())
     PM.add(createIfConverterPass());
 
   PM.add(createARMConstantIslandPass());
@@ -156,7 +159,7 @@
 }
 
 bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                          unsigned OptLevel,
+                                          CodeGenOpt::Level OptLevel,
                                           bool Verbose,
                                           raw_ostream &Out) {
   // Output assembly language.
@@ -168,8 +171,10 @@
 }
 
 
-bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
-                                      bool DumpAsm, MachineCodeEmitter &MCE) {
+bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM,
+                                      CodeGenOpt::Level OptLevel,
+                                      bool DumpAsm,
+                                      MachineCodeEmitter &MCE) {
   // FIXME: Move this to TargetJITInfo!
   if (DefRelocModel == Reloc::Default)
     setRelocationModel(Reloc::Static);
@@ -186,7 +191,7 @@
 }
 
 bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel,
+                                            CodeGenOpt::Level OptLevel,
                                             bool DumpAsm,
                                             MachineCodeEmitter &MCE) {
   // Machine code emitter pass for ARM.

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Wed Apr 29 18:29:43 2009
@@ -41,7 +41,8 @@
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             ARMTargetMachine &tm,
-                                            unsigned OptLevel, bool verbose);
+                                            CodeGenOpt::Level OptLevel,
+                                            bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -69,14 +70,17 @@
   virtual const TargetAsmInfo *createTargetAsmInfo() const;
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM,
+                                  CodeGenOpt::Level OptLevel,
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
-                                    bool DumpAsm, MachineCodeEmitter &MCE);
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+                                    CodeGenOpt::Level OptLevel,
+                                    bool DumpAsm,
+                                    MachineCodeEmitter &MCE);
 };
 
 /// ThumbTargetMachine - Thumb target machine.

Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Wed Apr 29 18:29:43 2009
@@ -81,7 +81,8 @@
     bool InCPMode;
   public:
     explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                           const TargetAsmInfo *T, unsigned OL, bool V)
+                           const TargetAsmInfo *T, CodeGenOpt::Level OL,
+                           bool V)
       : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
         InCPMode(false) {
       Subtarget = &TM.getSubtarget<ARMSubtarget>();
@@ -1061,7 +1062,8 @@
 ///
 FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
                                              ARMTargetMachine &tm,
-                                             unsigned OptLevel, bool verbose) {
+                                             CodeGenOpt::Level OptLevel,
+                                             bool verbose) {
   return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 

Modified: llvm/trunk/lib/Target/Alpha/Alpha.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/Alpha.h (original)
+++ llvm/trunk/lib/Target/Alpha/Alpha.h Wed Apr 29 18:29:43 2009
@@ -15,18 +15,20 @@
 #ifndef TARGET_ALPHA_H
 #define TARGET_ALPHA_H
 
+#include "llvm/Target/TargetMachine.h"
+
 namespace llvm {
 
   class AlphaTargetMachine;
   class FunctionPass;
-  class TargetMachine;
   class MachineCodeEmitter;
   class raw_ostream;
 
   FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
   FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
                                            TargetMachine &TM,
-                                           unsigned OptLevel, bool Verbose);
+                                           CodeGenOpt::Level OptLevel,
+                                           bool Verbose);
   FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
   FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
                                            MachineCodeEmitter &MCE);

Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Wed Apr 29 18:29:43 2009
@@ -77,25 +77,26 @@
 //===----------------------------------------------------------------------===//
 
 bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
-                                         unsigned OptLevel) {
+                                         CodeGenOpt::Level OptLevel) {
   PM.add(createAlphaISelDag(*this));
   return false;
 }
 bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
-                                        unsigned OptLevel) {
+                                        CodeGenOpt::Level OptLevel) {
   // Must run branch selection immediately preceding the asm printer
   PM.add(createAlphaBranchSelectionPass());
   return false;
 }
 bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel,
+                                            CodeGenOpt::Level OptLevel,
                                             bool Verbose,
                                             raw_ostream &Out) {
   PM.add(createAlphaLLRPPass(*this));
   PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;
 }
-bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
+                                        CodeGenOpt::Level OptLevel,
                                         bool DumpAsm, MachineCodeEmitter &MCE) {
   PM.add(createAlphaCodeEmitterPass(*this, MCE));
   if (DumpAsm)
@@ -103,7 +104,8 @@
   return false;
 }
 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
-                                              unsigned OptLevel, bool DumpAsm,
+                                              CodeGenOpt::Level OptLevel,
+                                              bool DumpAsm,
                                               MachineCodeEmitter &MCE) {
   return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
 }

Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Wed Apr 29 18:29:43 2009
@@ -58,14 +58,17 @@
   static unsigned getModuleMatchQuality(const Module &M);
   
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM,
+                                  CodeGenOpt::Level OptLevel,
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
-                                    bool DumpAsm, MachineCodeEmitter &MCE);
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+                                    CodeGenOpt::Level OptLevel,
+                                    bool DumpAsm,
+                                    MachineCodeEmitter &MCE);
 };
 
 } // end namespace llvm

Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Wed Apr 29 18:29:43 2009
@@ -37,7 +37,8 @@
     ///
 
     explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
-                             const TargetAsmInfo *T, unsigned OL, bool V)
+                             const TargetAsmInfo *T, CodeGenOpt::Level OL,
+                             bool V)
       : AsmPrinter(o, tm, T, OL, V) {}
 
     virtual const char *getPassName() const {
@@ -68,7 +69,7 @@
 ///
 FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
                                                TargetMachine &tm,
-                                               unsigned OptLevel,
+                                               CodeGenOpt::Level OptLevel,
                                                bool verbose) {
   return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }

Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
+++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Wed Apr 29 18:29:43 2009
@@ -3587,7 +3587,7 @@
 bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
                                               raw_ostream &o,
                                               CodeGenFileType FileType,
-                                              unsigned OptLevel) {
+                                              CodeGenOpt::Level OptLevel) {
   if (FileType != TargetMachine::AssemblyFile) return true;
 
   PM.add(createGCLoweringPass());

Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Wed Apr 29 18:29:43 2009
@@ -28,7 +28,7 @@
   virtual bool WantsWholeFile() const { return true; }
   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
                                         CodeGenFileType FileType,
-                                        unsigned OptLevel);
+                                        CodeGenOpt::Level OptLevel);
 
   // This class always works, but must be requested explicitly on 
   // llc command line.

Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Wed Apr 29 18:29:43 2009
@@ -49,7 +49,8 @@
     std::set<std::string> FnStubs, GVStubs;
   public:
     explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                           const TargetAsmInfo *T, unsigned OL, bool V) :
+                           const TargetAsmInfo *T, CodeGenOpt::Level OL,
+                           bool V) :
       AsmPrinter(O, TM, T, OL, V) {}
 
     virtual const char *getPassName() const {
@@ -288,8 +289,9 @@
     DwarfWriter *DW;
     MachineModuleInfo *MMI;
   public:
-    LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
-                    const TargetAsmInfo *T, bool F, bool V)
+    explicit LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
+                             const TargetAsmInfo *T, CodeGenOpt::Level F,
+                             bool V)
       : SPUAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
 
     virtual const char *getPassName() const {
@@ -615,6 +617,7 @@
 ///
 FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
                                             SPUTargetMachine &tm,
-                                            unsigned OptLevel, bool verbose) {
+                                            CodeGenOpt::Level OptLevel,
+                                            bool verbose) {
   return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }

Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPU.h Wed Apr 29 18:29:43 2009
@@ -16,6 +16,7 @@
 #define LLVM_TARGET_IBMCELLSPU_H
 
 #include "llvm/Support/DataTypes.h"
+#include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
   class SPUTargetMachine;
@@ -25,7 +26,8 @@
   FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
   FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
                                         SPUTargetMachine &tm,
-                                        unsigned OptLevel, bool verbose);
+                                        CodeGenOpt::Level OptLevel,
+                                        bool verbose);
 
   /*--== Utility functions/predicates/etc used all over the place: --==*/
   //! Predicate test for a signed 10-bit value

Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Wed Apr 29 18:29:43 2009
@@ -81,7 +81,8 @@
 //===----------------------------------------------------------------------===//
 
 bool
-SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel)
+SPUTargetMachine::addInstSelector(PassManagerBase &PM,
+                                  CodeGenOpt::Level OptLevel)
 {
   // Install an instruction selector.
   PM.add(createSPUISelDag(*this));
@@ -89,7 +90,7 @@
 }
 
 bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                          unsigned OptLevel,
+                                          CodeGenOpt::Level OptLevel,
                                           bool Verbose,
                                           raw_ostream &Out) {
   PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));

Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Wed Apr 29 18:29:43 2009
@@ -83,8 +83,10 @@
   }
   
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addInstSelector(PassManagerBase &PM,
+                               CodeGenOpt::Level OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM,
+                                  CodeGenOpt::Level OptLevel,
                                   bool Verbose, raw_ostream &Out);
 };
 

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Wed Apr 29 18:29:43 2009
@@ -1995,7 +1995,7 @@
 bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
                                                 raw_ostream &o,
                                                 CodeGenFileType FileType,
-                                                unsigned OptLevel) {
+                                                CodeGenOpt::Level OptLevel) {
   if (FileType != TargetMachine::AssemblyFile) return true;
   PM.add(new CppWriter(o));
   return false;

Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Wed Apr 29 18:29:43 2009
@@ -30,7 +30,7 @@
   virtual bool WantsWholeFile() const { return true; }
   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
                                         CodeGenFileType FileType,
-                                        unsigned OptLevel);
+                                        CodeGenOpt::Level OptLevel);
 
   // This class always works, but shouldn't be the default in most cases.
   static unsigned getModuleMatchQuality(const Module &M) { return 1; }

Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Wed Apr 29 18:29:43 2009
@@ -25,7 +25,6 @@
 #include "llvm/CodeGen/DwarfWriter.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/Target/TargetAsmInfo.h"
-#include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Mangler.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/ADT/Statistic.h"
@@ -38,7 +37,8 @@
     std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
   public:
     explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
-                            const TargetAsmInfo *T, unsigned OL, bool V)
+                            const TargetAsmInfo *T, CodeGenOpt::Level OL,
+                            bool V)
       : AsmPrinter(O, TM, T, OL, V) {}
 
     virtual const char *getPassName() const {
@@ -370,7 +370,7 @@
 ///
 FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
                                               IA64TargetMachine &tm,
-                                              unsigned OptLevel,
+                                              CodeGenOpt::Level OptLevel,
                                               bool verbose) {
   return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }

Modified: llvm/trunk/lib/Target/IA64/IA64.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64.h Wed Apr 29 18:29:43 2009
@@ -14,6 +14,8 @@
 #ifndef TARGET_IA64_H
 #define TARGET_IA64_H
 
+#include "llvm/Target/TargetMachine.h"
+
 namespace llvm {
 
 class IA64TargetMachine;
@@ -37,7 +39,8 @@
 ///
 FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
                                         IA64TargetMachine &tm,
-                                        unsigned OptLevel, bool verbose);
+                                        CodeGenOpt::Level OptLevel,
+                                        bool verbose);
 
 } // End llvm namespace
 

Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Wed Apr 29 18:29:43 2009
@@ -72,18 +72,20 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLEvel){
+bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,
+                                        CodeGenOpt::Level OptLevel){
   PM.add(createIA64DAGToDAGInstructionSelector(*this));
   return false;
 }
 
-bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
+bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,
+                                       CodeGenOpt::Level OptLevel) {
   // Make sure everything is bundled happily
   PM.add(createIA64BundlingPass(*this));
   return true;
 }
 bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                           unsigned OptLevel,
+                                           CodeGenOpt::Level OptLevel,
                                            bool Verbose,
                                            raw_ostream &Out) {
   PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));

Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64TargetMachine.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.h Wed Apr 29 18:29:43 2009
@@ -51,9 +51,10 @@
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM,
+                                  CodeGenOpt::Level OptLevel,
                                   bool Verbose, raw_ostream &Out);
 };
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
+++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Wed Apr 29 18:29:43 2009
@@ -36,7 +36,7 @@
     virtual bool WantsWholeFile() const { return true; }
     virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
                                           CodeGenFileType FileType,
-                                          unsigned OptLevel);
+                                          CodeGenOpt::Level OptLevel);
 
     // This class always works, but shouldn't be the default in most cases.
     static unsigned getModuleMatchQuality(const Module &M) { return 1; }
@@ -1664,7 +1664,7 @@
 
 bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o,
                                           CodeGenFileType FileType,
-                                          unsigned OptLevel)
+                                          CodeGenOpt::Level OptLevel)
 {
   if (FileType != TargetMachine::AssemblyFile) return true;
   MSILWriter* Writer = new MSILWriter(o);

Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Wed Apr 29 18:29:43 2009
@@ -50,7 +50,8 @@
     const MipsSubtarget *Subtarget;
   public:
     explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM, 
-                            const TargetAsmInfo *T, unsigned OL, bool V)
+                            const TargetAsmInfo *T, CodeGenOpt::Level OL,
+                            bool V)
       : AsmPrinter(O, TM, T, OL, V) {
       Subtarget = &TM.getSubtarget<MipsSubtarget>();
     }
@@ -91,7 +92,8 @@
 /// regardless of whether the function is in SSA form.
 FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
                                               MipsTargetMachine &tm,
-                                              unsigned OptLevel, bool verbose) {
+                                              CodeGenOpt::Level OptLevel,
+                                              bool verbose) {
   return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }
 

Modified: llvm/trunk/lib/Target/Mips/Mips.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.h (original)
+++ llvm/trunk/lib/Target/Mips/Mips.h Wed Apr 29 18:29:43 2009
@@ -15,6 +15,8 @@
 #ifndef TARGET_MIPS_H
 #define TARGET_MIPS_H
 
+#include "llvm/Target/TargetMachine.h"
+
 namespace llvm {
   class MipsTargetMachine;
   class FunctionPass;
@@ -25,7 +27,8 @@
   FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
   FunctionPass *createMipsCodePrinterPass(raw_ostream &OS, 
                                           MipsTargetMachine &TM,
-                                          unsigned OptLevel, bool Verbose);
+                                          CodeGenOpt::Level OptLevel,
+                                          bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for Mips registers.  This defines a mapping from

Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Wed Apr 29 18:29:43 2009
@@ -105,7 +105,7 @@
 // Install an instruction selector pass using 
 // the ISelDag to gen Mips code.
 bool MipsTargetMachine::
-addInstSelector(PassManagerBase &PM, unsigned OptLevel) 
+addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel) 
 {
   PM.add(createMipsISelDag(*this));
   return false;
@@ -115,7 +115,7 @@
 // machine code is emitted. return true if -print-machineinstrs should 
 // print out the code after the passes.
 bool MipsTargetMachine::
-addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) 
+addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) 
 {
   PM.add(createMipsDelaySlotFillerPass(*this));
   return true;
@@ -124,7 +124,7 @@
 // Implements the AssemblyEmitter for the target. Must return
 // true if AssemblyEmitter is supported
 bool MipsTargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, 
                    bool Verbose, raw_ostream &Out) 
 {
   // Output assembly language.

Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Wed Apr 29 18:29:43 2009
@@ -57,9 +57,12 @@
     static unsigned getModuleMatchQuality(const Module &M);
 
     // Pass Pipeline Configuration
-    virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-    virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-    virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+    virtual bool addInstSelector(PassManagerBase &PM,
+                                 CodeGenOpt::Level OptLevel);
+    virtual bool addPreEmitPass(PassManagerBase &PM,
+                                CodeGenOpt::Level OptLevel);
+    virtual bool addAssemblyEmitter(PassManagerBase &PM,
+                                    CodeGenOpt::Level OptLevel,
                                     bool Verbose, raw_ostream &Out);
   };
 

Modified: llvm/trunk/lib/Target/PIC16/PIC16.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16.h Wed Apr 29 18:29:43 2009
@@ -15,6 +15,7 @@
 #ifndef LLVM_TARGET_PIC16_H
 #define LLVM_TARGET_PIC16_H
 
+#include "llvm/Target/TargetMachine.h"
 #include <iosfwd>
 #include <cassert>
 
@@ -75,7 +76,8 @@
   FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
   FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS, 
                                            PIC16TargetMachine &TM,
-                                           unsigned OptLevel, bool Verbose);
+                                           CodeGenOpt::Level OptLevel,
+                                           bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for PIC16 registers.  This defines a mapping from

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Wed Apr 29 18:29:43 2009
@@ -161,7 +161,7 @@
 ///
 FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
                                                PIC16TargetMachine &tm,
-                                               unsigned OptLevel,
+                                               CodeGenOpt::Level OptLevel,
                                                bool verbose) {
   return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Wed Apr 29 18:29:43 2009
@@ -25,7 +25,8 @@
 namespace llvm {
   struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
     explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
-                             const TargetAsmInfo *T, unsigned OL, bool V)
+                             const TargetAsmInfo *T, CodeGenOpt::Level OL,
+                             bool V)
       : AsmPrinter(O, TM, T, OL, V) {
       CurBank = "";
       FunctionLabelBegin = '@';

Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Wed Apr 29 18:29:43 2009
@@ -56,15 +56,15 @@
 }
 
 bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
-                                         unsigned OptLevel) {
+                                         CodeGenOpt::Level OptLevel) {
   // Install an instruction selector.
   PM.add(createPIC16ISelDag(*this));
   return false;
 }
 
 bool PIC16TargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose,
-                   raw_ostream &Out) {
+addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
+                   bool Verbose, raw_ostream &Out) {
   // Output assembly language.
   PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
   return false;

Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h Wed Apr 29 18:29:43 2009
@@ -57,8 +57,10 @@
     return const_cast<PIC16TargetLowering*>(&TLInfo); 
   }
 
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addInstSelector(PassManagerBase &PM,
+                               CodeGenOpt::Level OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM,
+                                  CodeGenOpt::Level OptLevel,
                                   bool Verbose, raw_ostream &Out);
 }; // PIC16TargetMachine.
 

Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Wed Apr 29 18:29:43 2009
@@ -55,7 +55,8 @@
     const PPCSubtarget &Subtarget;
   public:
     explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                           const TargetAsmInfo *T, unsigned OL, bool V)
+                           const TargetAsmInfo *T, CodeGenOpt::Level OL,
+                           bool V)
       : AsmPrinter(O, TM, T, OL, V),
         Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
 
@@ -298,7 +299,8 @@
     MachineModuleInfo *MMI;
   public:
     explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
-                                const TargetAsmInfo *T, unsigned OL, bool V)
+                                const TargetAsmInfo *T, CodeGenOpt::Level OL,
+                                bool V)
       : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
 
     virtual const char *getPassName() const {
@@ -327,7 +329,8 @@
     raw_ostream &OS;
   public:
     explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
-                                 const TargetAsmInfo *T, unsigned OL, bool V)
+                                 const TargetAsmInfo *T, CodeGenOpt::Level OL,
+                                 bool V)
       : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
 
     virtual const char *getPassName() const {
@@ -1176,7 +1179,8 @@
 ///
 FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
                                             PPCTargetMachine &tm,
-                                            unsigned OptLevel, bool verbose) {
+                                            CodeGenOpt::Level OptLevel,
+                                            bool verbose) {
   const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
 
   if (Subtarget->isDarwin()) {

Modified: llvm/trunk/lib/Target/PowerPC/PPC.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPC.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPC.h Wed Apr 29 18:29:43 2009
@@ -18,6 +18,8 @@
 // GCC #defines PPC on Linux but we use it as our namespace name
 #undef PPC
 
+#include "llvm/Target/TargetMachine.h"
+
 namespace llvm {
   class PPCTargetMachine;
   class FunctionPass;
@@ -28,7 +30,7 @@
 FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
 FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
                                       PPCTargetMachine &TM,
-                                      unsigned OptLevel, bool Verbose);
+                                      CodeGenOpt::Level OptLevel, bool Verbose);
 FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
                                        MachineCodeEmitter &MCE);
 } // end namespace llvm;

Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Wed Apr 29 18:29:43 2009
@@ -129,21 +129,22 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
+                                       CodeGenOpt::Level OptLevel) {
   // Install an instruction selector.
   PM.add(createPPCISelDag(*this));
   return false;
 }
 
-bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
-  
+bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
+                                      CodeGenOpt::Level OptLevel) {
   // Must run branch selection immediately preceding the asm printer.
   PM.add(createPPCBranchSelectionPass());
   return false;
 }
 
 bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                          unsigned OptLevel,
+                                          CodeGenOpt::Level OptLevel,
                                           bool Verbose,
                                           raw_ostream &Out) {
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
@@ -153,7 +154,8 @@
   return false;
 }
 
-bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
+                                      CodeGenOpt::Level OptLevel,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
   // FIXME: This should be moved to TargetJITInfo!!
@@ -184,7 +186,8 @@
   return false;
 }
 
-bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+                                            CodeGenOpt::Level OptLevel,
                                             bool DumpAsm, MachineCodeEmitter &MCE) {
   // Machine code emitter pass for PowerPC.
   PM.add(createPPCCodeEmitterPass(*this, MCE));

Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Wed Apr 29 18:29:43 2009
@@ -46,7 +46,8 @@
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             PPCTargetMachine &tm, 
-                                            unsigned OptLevel, bool verbose);
+                                            CodeGenOpt::Level OptLevel,
+                                            bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -76,13 +77,15 @@
   }
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM,
+                                  CodeGenOpt::Level OptLevel, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+                                    CodeGenOpt::Level OptLevel,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
   virtual bool getEnableTailMergeDefault() const;
 };

Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp Wed Apr 29 18:29:43 2009
@@ -49,7 +49,8 @@
     ValueMapTy NumberForBB;
   public:
     explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                             const TargetAsmInfo *T, unsigned OL, bool V)
+                             const TargetAsmInfo *T, CodeGenOpt::Level OL,
+                             bool V)
       : AsmPrinter(O, TM, T, OL, V) {}
 
     virtual const char *getPassName() const {
@@ -82,7 +83,7 @@
 ///
 FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
                                                TargetMachine &tm,
-                                               unsigned OptLevel,
+                                               CodeGenOpt::Level OptLevel,
                                                bool verbose) {
   return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }

Modified: llvm/trunk/lib/Target/Sparc/Sparc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/Sparc.h (original)
+++ llvm/trunk/lib/Target/Sparc/Sparc.h Wed Apr 29 18:29:43 2009
@@ -15,17 +15,18 @@
 #ifndef TARGET_SPARC_H
 #define TARGET_SPARC_H
 
+#include "llvm/Target/TargetMachine.h"
 #include <cassert>
 
 namespace llvm {
   class FunctionPass;
-  class TargetMachine;
   class SparcTargetMachine;
   class raw_ostream;
 
   FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
   FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM,
-                                           unsigned OptLevel, bool Verbose);
+                                           CodeGenOpt::Level OptLevel,
+                                           bool Verbose);
   FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
   FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
 } // end namespace llvm;

Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Wed Apr 29 18:29:43 2009
@@ -69,7 +69,7 @@
 }
 
 bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
-                                         unsigned OptLevel) {
+                                         CodeGenOpt::Level OptLevel) {
   PM.add(createSparcISelDag(*this));
   return false;
 }
@@ -77,14 +77,15 @@
 /// addPreEmitPass - This pass may be implemented by targets that want to run
 /// passes immediately before machine code is emitted.  This should return
 /// true if -print-machineinstrs should print out the code after the passes.
-bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel){
+bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
+                                        CodeGenOpt::Level OptLevel){
   PM.add(createSparcFPMoverPass(*this));
   PM.add(createSparcDelaySlotFillerPass(*this));
   return true;
 }
 
 bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel,
+                                            CodeGenOpt::Level OptLevel,
                                             bool Verbose,
                                             raw_ostream &Out) {
   // Output assembly language.

Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Wed Apr 29 18:29:43 2009
@@ -51,9 +51,10 @@
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM,
+                                  CodeGenOpt::Level OptLevel,
                                   bool Verbose, raw_ostream &Out);
 };
 

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Wed Apr 29 18:29:43 2009
@@ -34,7 +34,8 @@
   const X86Subtarget *Subtarget;
  public:
   explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
-                            const TargetAsmInfo *T, unsigned OL, bool V)
+                            const TargetAsmInfo *T, CodeGenOpt::Level OL,
+                            bool V)
     : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
     Subtarget = &TM.getSubtarget<X86Subtarget>();
   }

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Wed Apr 29 18:29:43 2009
@@ -25,7 +25,8 @@
 ///
 FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
                                              X86TargetMachine &tm,
-                                             unsigned OptLevel, bool verbose) {
+                                             CodeGenOpt::Level OptLevel,
+                                             bool verbose) {
   const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
 
   if (Subtarget->isFlavorIntel()) {

Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h Wed Apr 29 18:29:43 2009
@@ -26,7 +26,8 @@
 
 struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
   explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
-                              const TargetAsmInfo *T, unsigned OL, bool V)
+                              const TargetAsmInfo *T, CodeGenOpt::Level OL,
+                              bool V)
     : AsmPrinter(O, TM, T, OL, V) {}
 
   virtual const char *getPassName() const {

Modified: llvm/trunk/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86.h (original)
+++ llvm/trunk/lib/Target/X86/X86.h Wed Apr 29 18:29:43 2009
@@ -15,6 +15,8 @@
 #ifndef TARGET_X86_H
 #define TARGET_X86_H
 
+#include "llvm/Target/TargetMachine.h"
+
 namespace llvm {
 
 class X86TargetMachine;
@@ -25,7 +27,7 @@
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned OptSize);
+FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel);
 
 /// createX86FloatingPointStackifierPass - This function returns a pass which
 /// converts floating point register references and pseudo instructions into
@@ -44,7 +46,8 @@
 ///
 FunctionPass *createX86CodePrinterPass(raw_ostream &o,
                                        X86TargetMachine &tm,
-                                       unsigned OptLevel, bool Verbose);
+                                       CodeGenOpt::Level OptLevel,
+                                       bool Verbose);
 
 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
 /// to the specified MCE object.

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Apr 29 18:29:43 2009
@@ -134,7 +134,7 @@
     bool OptForSize;
 
   public:
-    explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
+    explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
       : SelectionDAGISel(tm, OptLevel),
         TM(tm), X86Lowering(*TM.getTargetLowering()),
         Subtarget(&TM.getSubtarget<X86Subtarget>()),
@@ -306,7 +306,7 @@
 
 bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
                                                  SDNode *Root) const {
-  if (OptLevel == 0) return false;
+  if (OptLevel == CodeGenOpt::None) return false;
 
   if (U == Root)
     switch (U->getOpcode()) {
@@ -714,7 +714,7 @@
   OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
 
   DEBUG(BB->dump());
-  if (OptLevel != 0)
+  if (OptLevel != CodeGenOpt::None)
     PreprocessForRMW();
 
   // FIXME: This should only happen when not compiled with -O0.
@@ -1744,6 +1744,7 @@
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned OptLevel) {
+FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
+                                     llvm::CodeGenOpt::Level OptLevel) {
   return new X86DAGToDAGISel(TM, OptLevel);
 }

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Wed Apr 29 18:29:43 2009
@@ -180,7 +180,8 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
+                                       CodeGenOpt::Level OptLevel) {
   // Install an instruction selector.
   PM.add(createX86ISelDag(*this, OptLevel));
 
@@ -194,20 +195,22 @@
   return false;
 }
 
-bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
+                                      CodeGenOpt::Level OptLevel) {
   // Calculate and set max stack object alignment early, so we can decide
   // whether we will need stack realignment (and thus FP).
   PM.add(createX86MaxStackAlignmentCalculatorPass());
   return false;  // -print-machineinstr shouldn't print after this.
 }
 
-bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
+                                       CodeGenOpt::Level OptLevel) {
   PM.add(createX86FloatingPointStackifierPass());
   return true;  // -print-machineinstr should print after this.
 }
 
 bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                          unsigned OptLevel,
+                                          CodeGenOpt::Level OptLevel,
                                           bool Verbose,
                                           raw_ostream &Out) {
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
@@ -216,7 +219,8 @@
   return false;
 }
 
-bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
+                                      CodeGenOpt::Level OptLevel,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // FIXME: Move this to TargetJITInfo!
   // On Darwin, do not override 64-bit setting made in X86TargetMachine().
@@ -245,7 +249,8 @@
 }
 
 bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel, bool DumpAsm,
+                                            CodeGenOpt::Level OptLevel,
+                                            bool DumpAsm,
                                             MachineCodeEmitter &MCE) {
   PM.add(createX86CodeEmitterPass(*this, MCE));
   if (DumpAsm) {

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Wed Apr 29 18:29:43 2009
@@ -45,7 +45,8 @@
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             X86TargetMachine &tm,
-                                            unsigned OptLevel, bool verbose);
+                                            CodeGenOpt::Level OptLevel,
+                                            bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -74,14 +75,16 @@
   }
 
   // Set up the pass pipeline.
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM,
+                                  CodeGenOpt::Level OptLevel, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+                                    CodeGenOpt::Level OptLevel,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
 
   /// symbolicAddressesAreRIPRel - Return true if symbolic addresses are

Modified: llvm/trunk/lib/Target/XCore/XCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCore.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCore.h (original)
+++ llvm/trunk/lib/Target/XCore/XCore.h Wed Apr 29 18:29:43 2009
@@ -15,6 +15,8 @@
 #ifndef TARGET_XCORE_H
 #define TARGET_XCORE_H
 
+#include "llvm/Target/TargetMachine.h"
+
 namespace llvm {
   class FunctionPass;
   class TargetMachine;
@@ -24,7 +26,8 @@
   FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
   FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
                                            XCoreTargetMachine &TM,
-                                           unsigned OptLevel, bool Verbose);
+                                           CodeGenOpt::Level OptLevel,
+                                           bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for XCore registers.  This defines a mapping from

Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Wed Apr 29 18:29:43 2009
@@ -57,8 +57,9 @@
     DwarfWriter *DW;
     const XCoreSubtarget &Subtarget;
   public:
-    XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
-                    const TargetAsmInfo *T, unsigned OL, bool V)
+    explicit XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
+                             const TargetAsmInfo *T, CodeGenOpt::Level OL,
+                             bool V)
       : AsmPrinter(O, TM, T, OL, V), DW(0),
         Subtarget(*TM.getSubtargetImpl()) {}
 
@@ -105,7 +106,7 @@
 ///
 FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
                                                XCoreTargetMachine &tm,
-                                               unsigned OptLevel,
+                                               CodeGenOpt::Level OptLevel,
                                                bool verbose) {
   return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
 }

Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Wed Apr 29 18:29:43 2009
@@ -56,13 +56,13 @@
 }
 
 bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
-                                         unsigned OptLevel) {
+                                         CodeGenOpt::Level OptLevel) {
   PM.add(createXCoreISelDag(*this));
   return false;
 }
 
 bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel,
+                                            CodeGenOpt::Level OptLevel,
                                             bool Verbose,
                                             raw_ostream &Out) {
   // Output assembly language.

Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Wed Apr 29 18:29:43 2009
@@ -52,8 +52,9 @@
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM,
+                                  CodeGenOpt::Level OptLevel, 
                                   bool Verbose, raw_ostream &Out);
 };
 

Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Wed Apr 29 18:29:43 2009
@@ -56,12 +56,12 @@
 static cl::opt<bool> Force("f", cl::desc("Overwrite output files"));
 
 // Determine optimization level. Level -O0 is equivalent to "fast" code gen.
-static cl::opt<unsigned>
+static cl::opt<char>
 OptLevel("O",
-         cl::desc("Optimization level. Similar to llvm-gcc -O. (default: -O3)"),
+         cl::desc("Optimization level. Similar to llvm-gcc -O."),
          cl::Prefix,
          cl::ZeroOrMore,
-         cl::init(3));
+         cl::init(' '));
 
 static cl::opt<std::string>
 TargetTriple("mtriple", cl::desc("Override target triple for module"));
@@ -253,6 +253,19 @@
   raw_ostream *Out = GetOutputStream(argv[0]);
   if (Out == 0) return 1;
 
+  CodeGenOpt::Level OLvl = CodeGenOpt::Aggressive;
+
+  switch (OptLevel) {
+  default:
+  case ' ': break;
+  case '0': OLvl = CodeGenOpt::None; break;
+  case '1': OLvl = CodeGenOpt::One; break;
+  case '2': OLvl = CodeGenOpt::Two; break;
+  case 's': OLvl = CodeGenOpt::Size; break;
+  case '3': OLvl = CodeGenOpt::Aggressive; break;
+  case '4': OLvl = CodeGenOpt::LTO; break;
+  }
+
   // If this target requires addPassesToEmitWholeFile, do it now.  This is
   // used by strange things like the C backend.
   if (Target.WantsWholeFile()) {
@@ -262,7 +275,7 @@
       PM.add(createVerifierPass());
 
     // Ask the target to add backend passes as necessary.
-    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OptLevel)) {
+    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OLvl)) {
       std::cerr << argv[0] << ": target does not support generation of this"
                 << " file type!\n";
       if (Out != &outs()) delete Out;
@@ -288,7 +301,7 @@
     // Override default to generate verbose assembly.
     Target.setAsmVerbosityDefault(true);
 
-    switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OptLevel)) {
+    switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OLvl)) {
     default:
       assert(0 && "Invalid file model!");
       return 1;
@@ -309,7 +322,7 @@
       break;
     }
 
-    if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) {
+    if (Target.addPassesToEmitFileFinish(Passes, MCE, OLvl)) {
       std::cerr << argv[0] << ": target does not support generation of this"
                 << " file type!\n";
       if (Out != &outs()) delete Out;

Modified: llvm/trunk/tools/lli/lli.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lli/lli.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/tools/lli/lli.cpp (original)
+++ llvm/trunk/tools/lli/lli.cpp Wed Apr 29 18:29:43 2009
@@ -122,7 +122,9 @@
   if (!TargetTriple.empty())
     Mod->setTargetTriple(TargetTriple);
 
-  EE = ExecutionEngine::create(MP, ForceInterpreter, &ErrorMsg, Fast);
+  EE = ExecutionEngine::create(MP, ForceInterpreter, &ErrorMsg,
+                               Fast ?
+                                 CodeGenOpt::None : CodeGenOpt::Aggressive);
   if (!EE && !ErrorMsg.empty()) {
     std::cerr << argv[0] << ":error creating EE: " << ErrorMsg << "\n";
     exit(1);

Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original)
+++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Apr 29 18:29:43 2009
@@ -442,7 +442,8 @@
     MachineCodeEmitter* mce = NULL;
 
     switch (_target->addPassesToEmitFile(*codeGenPasses, out,
-                                      TargetMachine::AssemblyFile, 3)) {
+                                         TargetMachine::AssemblyFile,
+                                         CodeGenOpt::Default)) {
         case FileModel::MachOFile:
             mce = AddMachOWriter(*codeGenPasses, out, *_target);
             break;
@@ -457,7 +458,8 @@
             return true;
     }
 
-    if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce, 3)) {
+    if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce,
+                                           CodeGenOpt::Default)) {
         errMsg = "target does not support generation of this file type";
         return true;
     }

Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Wed Apr 29 18:29:43 2009
@@ -650,7 +650,7 @@
   O << "\";\n\n";
 
   O << "  if (TAI->doesSupportDebugInformation() &&\n"
-    << "      DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n"
+    << "      DW->ShouldEmitDwarfDebug() && OptLevel != CodeGenOpt::None) {\n"
     << "    DebugLoc CurDL = MI->getDebugLoc();\n\n"
     << "    if (!CurDL.isUnknown()) {\n"
     << "      static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n"

Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=70440&r1=70439&r2=70440&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Wed Apr 29 18:29:43 2009
@@ -465,7 +465,7 @@
       NumInputRootOps = N->getNumChildren();
 
       if (DisablePatternForFastISel(N, CGP))
-        emitCheck("OptLevel != 0");
+        emitCheck("OptLevel != CodeGenOpt::None");
 
       emitCheck(PredicateCheck);
     }




From isanbard at gmail.com  Wed Apr 29 18:36:59 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 16:36:59 -0700
Subject: [llvm-commits] [llvm] r70343 - in /llvm/trunk:
	docs/CommandGuide/ include/llvm/CodeGen/ include/llvm/Target/
	lib/CodeGen/ lib/CodeGen/AsmPrinter/
	lib/CodeGen/SelectionDAG/ lib/Target/ARM/
	lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Al
In-Reply-To: <111ED6F1-BC0E-4541-8DBC-B3D390E3B070@apple.com>
References: <16e5fdf90904291423i962f280v5ad16a0972a23eb5@mail.gmail.com>
	<EAB29BD4-DC21-405C-8CE1-32F75440160E@apple.com>
	<16e5fdf90904291610k47d45170q5f5ce8d665a013b3@mail.gmail.com>
	<111ED6F1-BC0E-4541-8DBC-B3D390E3B070@apple.com>
Message-ID: <16e5fdf90904291636q4ccf0e52kddc5810209023b7a@mail.gmail.com>

On Wed, Apr 29, 2009 at 4:18 PM, Evan Cheng <evan.cheng at apple.com> wrote:
>
> On Apr 29, 2009, at 4:10 PM, Bill Wendling wrote:
>
>> I was thinking of having an "LTO" level in the enum...
>
> Why? LTO should not influence how we run codegen passes.
>
To coincide with the "-O4" option. But if you don't think it's
necessary, then I'll remove it.

-bw


From isanbard at gmail.com  Wed Apr 29 18:40:44 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 23:40:44 -0000
Subject: [llvm-commits] [llvm] r70445 - in /llvm/trunk:
 include/llvm/Target/TargetMachine.h tools/llc/llc.cpp
 tools/lto/LTOCodeGenerator.cpp
Message-ID: <200904292340.n3TNejcO016770@zion.cs.uiuc.edu>

Author: void
Date: Wed Apr 29 18:40:42 2009
New Revision: 70445

URL: http://llvm.org/viewvc/llvm-project?rev=70445&view=rev
Log:
Remove LTO optimization level.

Modified:
    llvm/trunk/include/llvm/Target/TargetMachine.h
    llvm/trunk/tools/llc/llc.cpp
    llvm/trunk/tools/lto/LTOCodeGenerator.cpp

Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=70445&r1=70444&r2=70445&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
+++ llvm/trunk/include/llvm/Target/TargetMachine.h Wed Apr 29 18:40:42 2009
@@ -76,8 +76,7 @@
     One,
     Two,
     Size,
-    Aggressive,
-    LTO
+    Aggressive
   };
 }
 

Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=70445&r1=70444&r2=70445&view=diff

==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Wed Apr 29 18:40:42 2009
@@ -263,7 +263,6 @@
   case '2': OLvl = CodeGenOpt::Two; break;
   case 's': OLvl = CodeGenOpt::Size; break;
   case '3': OLvl = CodeGenOpt::Aggressive; break;
-  case '4': OLvl = CodeGenOpt::LTO; break;
   }
 
   // If this target requires addPassesToEmitWholeFile, do it now.  This is

Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=70445&r1=70444&r2=70445&view=diff

==============================================================================
--- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original)
+++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Apr 29 18:40:42 2009
@@ -443,7 +443,7 @@
 
     switch (_target->addPassesToEmitFile(*codeGenPasses, out,
                                          TargetMachine::AssemblyFile,
-                                         CodeGenOpt::Default)) {
+                                         CodeGenOpt::Aggressive)) {
         case FileModel::MachOFile:
             mce = AddMachOWriter(*codeGenPasses, out, *_target);
             break;
@@ -459,7 +459,7 @@
     }
 
     if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce,
-                                           CodeGenOpt::Default)) {
+                                           CodeGenOpt::Aggressive)) {
         errMsg = "target does not support generation of this file type";
         return true;
     }




From kremenek at apple.com  Wed Apr 29 18:41:00 2009
From: kremenek at apple.com (Ted Kremenek)
Date: Wed, 29 Apr 2009 23:41:00 -0000
Subject: [llvm-commits] [llvm] r70446 - /llvm/tags/checker/checker-0.191/
Message-ID: <200904292341.n3TNf0wH016786@zion.cs.uiuc.edu>

Author: kremenek
Date: Wed Apr 29 18:40:59 2009
New Revision: 70446

URL: http://llvm.org/viewvc/llvm-project?rev=70446&view=rev
Log:
Tagging checker-0.191.

Added:
    llvm/tags/checker/checker-0.191/
      - copied from r70445, llvm/trunk/



From dalej at apple.com  Wed Apr 29 18:43:16 2009
From: dalej at apple.com (Dale Johannesen)
Date: Wed, 29 Apr 2009 16:43:16 -0700
Subject: [llvm-commits] [llvm] r70343 - in
	/llvm/trunk:	docs/CommandGuide/ include/llvm/CodeGen/
	include/llvm/Target/	lib/CodeGen/
	lib/CodeGen/AsmPrinter/	lib/CodeGen/SelectionDAG/
	lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/
	lib/Target/Al
In-Reply-To: <16e5fdf90904291636q4ccf0e52kddc5810209023b7a@mail.gmail.com>
References: <16e5fdf90904291423i962f280v5ad16a0972a23eb5@mail.gmail.com>
	<EAB29BD4-DC21-405C-8CE1-32F75440160E@apple.com>
	<16e5fdf90904291610k47d45170q5f5ce8d665a013b3@mail.gmail.com>
	<111ED6F1-BC0E-4541-8DBC-B3D390E3B070@apple.com>
	<16e5fdf90904291636q4ccf0e52kddc5810209023b7a@mail.gmail.com>
Message-ID: <ADEC2B14-76BC-4313-8EC7-5854B8B66E4F@apple.com>


On Apr 29, 2009, at 4:36 PMPDT, Bill Wendling wrote:

> On Wed, Apr 29, 2009 at 4:18 PM, Evan Cheng <evan.cheng at apple.com>  
> wrote:
>>
>> On Apr 29, 2009, at 4:10 PM, Bill Wendling wrote:
>>
>>> I was thinking of having an "LTO" level in the enum...
>>
>> Why? LTO should not influence how we run codegen passes.
>>
> To coincide with the "-O4" option. But if you don't think it's
> necessary, then I'll remove it.

There are multiple-function machine level optimizations possible, for  
example taking advantage of knowledge of register usage in a different  
function.  Why not leave the hook?  Maybe some brave soul will work on  
it:)



From isanbard at gmail.com  Wed Apr 29 18:46:50 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 23:46:50 -0000
Subject: [llvm-commits] [llvm] r70449 - /llvm/trunk/tools/llc/llc.cpp
Message-ID: <200904292346.n3TNkpkH016991@zion.cs.uiuc.edu>

Author: void
Date: Wed Apr 29 18:46:43 2009
New Revision: 70449

URL: http://llvm.org/viewvc/llvm-project?rev=70449&view=rev
Log:
Error out with bad optimization level specified.

Modified:
    llvm/trunk/tools/llc/llc.cpp

Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=70449&r1=70448&r2=70449&view=diff

==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Wed Apr 29 18:46:43 2009
@@ -58,7 +58,7 @@
 // Determine optimization level. Level -O0 is equivalent to "fast" code gen.
 static cl::opt<char>
 OptLevel("O",
-         cl::desc("Optimization level. Similar to llvm-gcc -O."),
+         cl::desc("Optimization level. [-O0, -O1, -O2, -Os, or -O3]"),
          cl::Prefix,
          cl::ZeroOrMore,
          cl::init(' '));
@@ -257,6 +257,8 @@
 
   switch (OptLevel) {
   default:
+    std::cerr << argv[0] << ": invalid optimization level.\n";
+    return 1;
   case ' ': break;
   case '0': OLvl = CodeGenOpt::None; break;
   case '1': OLvl = CodeGenOpt::One; break;




From isanbard at gmail.com  Wed Apr 29 18:48:39 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 29 Apr 2009 16:48:39 -0700
Subject: [llvm-commits] [llvm] r70343 - in /llvm/trunk:
	docs/CommandGuide/ include/llvm/CodeGen/ include/llvm/Target/
	lib/CodeGen/ lib/CodeGen/AsmPrinter/
	lib/CodeGen/SelectionDAG/ lib/Target/ARM/
	lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Al
In-Reply-To: <ADEC2B14-76BC-4313-8EC7-5854B8B66E4F@apple.com>
References: <16e5fdf90904291423i962f280v5ad16a0972a23eb5@mail.gmail.com>
	<EAB29BD4-DC21-405C-8CE1-32F75440160E@apple.com>
	<16e5fdf90904291610k47d45170q5f5ce8d665a013b3@mail.gmail.com>
	<111ED6F1-BC0E-4541-8DBC-B3D390E3B070@apple.com>
	<16e5fdf90904291636q4ccf0e52kddc5810209023b7a@mail.gmail.com>
	<ADEC2B14-76BC-4313-8EC7-5854B8B66E4F@apple.com>
Message-ID: <16e5fdf90904291648w6c73dc97mc7f9c360164eab7b@mail.gmail.com>

On Wed, Apr 29, 2009 at 4:43 PM, Dale Johannesen <dalej at apple.com> wrote:
>
> On Apr 29, 2009, at 4:36 PMPDT, Bill Wendling wrote:
>
>> On Wed, Apr 29, 2009 at 4:18 PM, Evan Cheng <evan.cheng at apple.com>
>> wrote:
>>>
>>> On Apr 29, 2009, at 4:10 PM, Bill Wendling wrote:
>>>
>>>> I was thinking of having an "LTO" level in the enum...
>>>
>>> Why? LTO should not influence how we run codegen passes.
>>>
>> To coincide with the "-O4" option. But if you don't think it's
>> necessary, then I'll remove it.
>
> There are multiple-function machine level optimizations possible, for
> example taking advantage of knowledge of register usage in a different
> function. ?Why not leave the hook? ?Maybe some brave soul will work on
> it:)
>
Brave soul indeed. :-) It's okay now. If someone wants to try this
out, then it's easy to add this option back in...

-bw



From clattner at apple.com  Wed Apr 29 19:00:56 2009
From: clattner at apple.com (Chris Lattner)
Date: Wed, 29 Apr 2009 17:00:56 -0700
Subject: [llvm-commits] [llvm] r70421 - in /llvm/trunk:
	lib/Analysis/ScalarEvolution.cpp
	test/Analysis/ScalarEvolution/sext-iv-0.ll
	test/Analysis/ScalarEvolution/sext-iv-1.ll
In-Reply-To: <200904292228.n3TMSTaZ014041@zion.cs.uiuc.edu>
References: <200904292228.n3TMSTaZ014041@zion.cs.uiuc.edu>
Message-ID: <A9B1D156-A10D-4CB4-B92D-D3EC50C70990@apple.com>


On Apr 29, 2009, at 3:28 PM, Dan Gohman wrote:

> Author: djg
> Date: Wed Apr 29 17:28:28 2009
> New Revision: 70421
>
> URL: http://llvm.org/viewvc/llvm-project?rev=70421&view=rev
> Log:
> Generalize the cast-of-addrec folding to handle folding of SCEVs like
> (sext i8 {-128,+,1} to i64) to i64 {-128,+,1}, where the iteration
> crosses from negative to positive, but is still safe if the trip
> count is within range.

Does this fix the rest of PR1301?

-Chris


From sabre at nondot.org  Wed Apr 29 19:24:34 2009
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 30 Apr 2009 00:24:34 -0000
Subject: [llvm-commits] [llvm] r70453 -
	/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
Message-ID: <200904300024.n3U0OYC5018387@zion.cs.uiuc.edu>

Author: lattner
Date: Wed Apr 29 19:24:33 2009
New Revision: 70453

URL: http://llvm.org/viewvc/llvm-project?rev=70453&view=rev
Log:
remove progname which is never set. PR4085


Modified:
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=70453&r1=70452&r2=70453&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Wed Apr 29 19:24:33 2009
@@ -94,7 +94,6 @@
   /// CppWriter - This class is the main chunk of code that converts an LLVM
   /// module to a C++ translation unit.
   class CppWriter : public ModulePass {
-    const char* progname;
     raw_ostream &Out;
     const Module *TheModule;
     uint64_t uniqueNum;
@@ -218,7 +217,7 @@
   }
 
   void CppWriter::error(const std::string& msg) {
-    cerr << progname << ": " << msg << "\n";
+    cerr << msg << "\n";
     exit(2);
   }
 




From isanbard at gmail.com  Wed Apr 29 19:43:39 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 30 Apr 2009 00:43:39 -0000
Subject: [llvm-commits] [llvm] r70454 - in /llvm/trunk:
 bindings/ocaml/executionengine/executionengine_ocaml.c
 lib/ExecutionEngine/ExecutionEngineBindings.cpp
Message-ID: <200904300043.n3U0hdWO018944@zion.cs.uiuc.edu>

Author: void
Date: Wed Apr 29 19:43:39 2009
New Revision: 70454

URL: http://llvm.org/viewvc/llvm-project?rev=70454&view=rev
Log:
Fix the JIT bindings for ocaml.

Modified:
    llvm/trunk/bindings/ocaml/executionengine/executionengine_ocaml.c
    llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp

Modified: llvm/trunk/bindings/ocaml/executionengine/executionengine_ocaml.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/executionengine/executionengine_ocaml.c?rev=70454&r1=70453&r2=70454&view=diff

==============================================================================
--- llvm/trunk/bindings/ocaml/executionengine/executionengine_ocaml.c (original)
+++ llvm/trunk/bindings/ocaml/executionengine/executionengine_ocaml.c Wed Apr 29 19:43:39 2009
@@ -181,7 +181,7 @@
 llvm_ee_create_jit(LLVMModuleProviderRef MP) {
   LLVMExecutionEngineRef JIT;
   char *Error;
-  if (LLVMCreateJITCompiler(&JIT, MP, 0, &Error))
+  if (LLVMCreateJITCompiler(&JIT, MP, 3, &Error))
     llvm_raise(llvm_ee_error_exn, Error);
   return JIT;
 }
@@ -191,7 +191,7 @@
 llvm_ee_create_fast_jit(LLVMModuleProviderRef MP) {
   LLVMExecutionEngineRef JIT;
   char *Error;
-  if (LLVMCreateJITCompiler(&JIT, MP, 1, &Error))
+  if (LLVMCreateJITCompiler(&JIT, MP, 0, &Error))
     llvm_raise(llvm_ee_error_exn, Error);
   return JIT;
 }

Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp?rev=70454&r1=70453&r2=70454&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp Wed Apr 29 19:43:39 2009
@@ -114,11 +114,12 @@
 
 int LLVMCreateJITCompiler(LLVMExecutionEngineRef *OutJIT,
                           LLVMModuleProviderRef MP,
-                          CodeGenOpt::Level OptLevel,
+                          unsigned OptLevel,
                           char **OutError) {
   std::string Error;
-  if (ExecutionEngine *JIT = ExecutionEngine::createJIT(unwrap(MP), &Error, 0,
-                                                        OptLevel)) {
+  if (ExecutionEngine *JIT =
+      ExecutionEngine::createJIT(unwrap(MP), &Error, 0,
+                                 (CodeGenOpt::Level)OptLevel)) {
     *OutJIT = wrap(JIT);
     return 0;
   }




From evan.cheng at apple.com  Wed Apr 29 19:44:03 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Apr 2009 17:44:03 -0700
Subject: [llvm-commits] [llvm] r70440 - in /llvm/trunk:
	include/llvm/CodeGen/ include/llvm/ExecutionEngine/
	include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/
	lib/CodeGen/SelectionDAG/ lib/ExecutionEngine/
	lib/ExecutionEngine/Interpreter/ lib/ExecutionEngine/JIT/
	lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/
	lib/Target/Alpha/AsmPrinter/ lib/Target/CBackend/
	lib/Target/CellSPU/ lib/Target/CellSPU/AsmPrinter/
	lib/Target/CppBackend/ lib/Target/IA64/
	lib/Target/IA64/AsmPrinter/ lib/Target/MSIL/ lib/Target/Mips...
In-Reply-To: <200904292330.n3TNU2Fc016290@zion.cs.uiuc.edu>
References: <200904292330.n3TNU2Fc016290@zion.cs.uiuc.edu>
Message-ID: <217D05A0-A843-43DA-96AA-8F992012C252@apple.com>

Please remove CodeGenOpt::Size. Optimizing for size is a different  
knob from the general codegen optimization level. We place function  
notes on function declarations that indicate a function should be  
optimized for size.

Also, why do we need CodeGenOpt::Default in addition to  
CodeGenOpt::One Two, and Aggressive? How do you expect  
CodeGenOpt::Default be used? Why not just have "None", "Default",  
"Aggressive"?

Evan

On Apr 29, 2009, at 4:29 PM, Bill Wendling wrote:

> Author: void
> Date: Wed Apr 29 18:29:43 2009
> New Revision: 70440
>
> URL: http://llvm.org/viewvc/llvm-project?rev=70440&view=rev
> Log:
> Instead of passing in an unsigned value for the optimization level,  
> use an enum,
> which better identifies what the optimization is doing. And is more  
> flexible for
> future uses.
>
> Modified:
>    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
>    llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
>    llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>    llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
>    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
>    llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h
>    llvm/trunk/include/llvm/Target/TargetMachine.h
>    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
>    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
>    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
>    llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
>    llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp
>    llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp
>    llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h
>    llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp
>    llvm/trunk/lib/ExecutionEngine/JIT/JIT.h
>    llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp
>    llvm/trunk/lib/Target/ARM/ARM.h
>    llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
>    llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
>    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>    llvm/trunk/lib/Target/Alpha/Alpha.h
>    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
>    llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
>    llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
>    llvm/trunk/lib/Target/CBackend/CBackend.cpp
>    llvm/trunk/lib/Target/CBackend/CTargetMachine.h
>    llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
>    llvm/trunk/lib/Target/CellSPU/SPU.h
>    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
>    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
>    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
>    llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
>    llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
>    llvm/trunk/lib/Target/IA64/IA64.h
>    llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
>    llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
>    llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
>    llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
>    llvm/trunk/lib/Target/Mips/Mips.h
>    llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
>    llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
>    llvm/trunk/lib/Target/PIC16/PIC16.h
>    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
>    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
>    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
>    llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
>    llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
>    llvm/trunk/lib/Target/PowerPC/PPC.h
>    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
>    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
>    llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
>    llvm/trunk/lib/Target/Sparc/Sparc.h
>    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
>    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
>    llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
>    llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
>    llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
>    llvm/trunk/lib/Target/X86/X86.h
>    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
>    llvm/trunk/lib/Target/X86/X86TargetMachine.h
>    llvm/trunk/lib/Target/XCore/XCore.h
>    llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
>    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
>    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
>    llvm/trunk/tools/llc/llc.cpp
>    llvm/trunk/tools/lli/lli.cpp
>    llvm/trunk/tools/lto/LTOCodeGenerator.cpp
>    llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
>    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Wed Apr 29 18:29:43  
> 2009
> @@ -16,9 +16,10 @@
> #ifndef LLVM_CODEGEN_ASMPRINTER_H
> #define LLVM_CODEGEN_ASMPRINTER_H
>
> +#include "llvm/ADT/DenseMap.h"
> #include "llvm/CodeGen/MachineFunctionPass.h"
> #include "llvm/Support/DataTypes.h"
> -#include "llvm/ADT/DenseMap.h"
> +#include "llvm/Target/TargetMachine.h"
> #include <set>
>
> namespace llvm {
> @@ -66,7 +67,7 @@
>     std::set<const GlobalValue*> ExtWeakSymbols;
>
>     /// OptLevel - Generating code at a specific optimization level.
> -    unsigned OptLevel;
> +    CodeGenOpt::Level OptLevel;
>   public:
>     /// Output stream on which we're printing assembly code.
>     ///
> @@ -111,7 +112,7 @@
>
>   protected:
>     explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
> -                        const TargetAsmInfo *T, unsigned OL, bool V);
> +                        const TargetAsmInfo *T, CodeGenOpt::Level  
> OL, bool V);
>
>   public:
>     virtual ~AsmPrinter();
>
> Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Wed Apr 29  
> 18:29:43 2009
> @@ -21,6 +21,7 @@
> #define LLVM_CODEGEN_DWARFWRITER_H
>
> #include "llvm/Pass.h"
> +#include "llvm/Target/TargetMachine.h"
>
> namespace llvm {
>
> @@ -81,7 +82,7 @@
>   void EndFunction(MachineFunction *MF);
>
>   /// ValidDebugInfo - Return true if V represents valid debug info  
> value.
> -  bool ValidDebugInfo(Value *V, unsigned OptLevel);
> +  bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel);
>
>   /// RecordSourceLine - Register a source line with debug info.  
> Returns a
>   /// unique label ID used to generate a label and provide  
> correspondence to
>
> Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h  
> (original)
> +++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Wed  
> Apr 29 18:29:43 2009
> @@ -18,6 +18,7 @@
> #include "llvm/CodeGen/Passes.h"
> #include "llvm/CodeGen/SchedulerRegistry.h"
> #include "llvm/CodeGen/GCs.h"
> +#include "llvm/Target/TargetMachine.h"
>
> namespace {
>   struct ForceCodegenLinking {
> @@ -42,11 +43,11 @@
>       llvm::linkOcamlGC();
>       llvm::linkShadowStackGC();
>
> -      (void) llvm::createBURRListDAGScheduler(NULL, 3);
> -      (void) llvm::createTDRRListDAGScheduler(NULL, 3);
> -      (void) llvm::createTDListDAGScheduler(NULL, 3);
> -      (void) llvm::createFastDAGScheduler(NULL, 3);
> -      (void) llvm::createDefaultScheduler(NULL, 3);
> +      (void) llvm::createBURRListDAGScheduler(NULL,  
> llvm::CodeGenOpt::Default);
> +      (void) llvm::createTDRRListDAGScheduler(NULL,  
> llvm::CodeGenOpt::Default);
> +      (void) llvm::createTDListDAGScheduler(NULL,  
> llvm::CodeGenOpt::Default);
> +      (void) llvm::createFastDAGScheduler(NULL,  
> llvm::CodeGenOpt::Default);
> +      (void) llvm::createDefaultScheduler(NULL,  
> llvm::CodeGenOpt::Default);
>
>     }
>   } ForceCodegenLinking; // Force link by creating a global  
> definition.
>
> Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Wed Apr 29  
> 18:29:43 2009
> @@ -16,6 +16,7 @@
> #define LLVM_CODEGENSCHEDULERREGISTRY_H
>
> #include "llvm/CodeGen/MachinePassRegistry.h"
> +#include "llvm/Target/TargetMachine.h"
>
> namespace llvm {
>
> @@ -32,7 +33,8 @@
>
> class RegisterScheduler : public MachinePassRegistryNode {
> public:
> -  typedef ScheduleDAGSDNodes *(*FunctionPassCtor) 
> (SelectionDAGISel*, unsigned);
> +  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
> +                                                  CodeGenOpt::Level);
>
>   static MachinePassRegistry Registry;
>
> @@ -64,27 +66,27 @@
> /// createBURRListDAGScheduler - This creates a bottom up register  
> usage
> /// reduction list scheduler.
> ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
> -                                               unsigned OptLevel);
> +                                               CodeGenOpt::Level  
> OptLevel);
>
> /// createTDRRListDAGScheduler - This creates a top down register  
> usage
> /// reduction list scheduler.
> ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
> -                                               unsigned OptLevel);
> +                                               CodeGenOpt::Level  
> OptLevel);
>
> /// createTDListDAGScheduler - This creates a top-down list  
> scheduler with
> /// a hazard recognizer.
> ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
> -                                             unsigned OptLevel);
> +                                             CodeGenOpt::Level  
> OptLevel);
>
> /// createFastDAGScheduler - This creates a "fast" scheduler.
> ///
> ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
> -                                           unsigned OptLevel);
> +                                           CodeGenOpt::Level  
> OptLevel);
>
> /// createDefaultScheduler - This creates an instruction scheduler  
> appropriate
> /// for the target.
> ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
> -                                           unsigned OptLevel);
> +                                           CodeGenOpt::Level  
> OptLevel);
>
> } // end namespace llvm
>
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Apr 29  
> 18:29:43 2009
> @@ -20,7 +20,7 @@
> #include "llvm/ADT/FoldingSet.h"
> #include "llvm/ADT/StringMap.h"
> #include "llvm/CodeGen/SelectionDAGNodes.h"
> -
> +#include "llvm/Target/TargetMachine.h"
> #include <cassert>
> #include <vector>
> #include <map>
> @@ -30,7 +30,6 @@
>
> class AliasAnalysis;
> class TargetLowering;
> -class TargetMachine;
> class MachineModuleInfo;
> class DwarfWriter;
> class MachineFunction;
> @@ -202,7 +201,8 @@
>   /// certain types of nodes together, or eliminating superfluous  
> nodes.  The
>   /// Level argument controls whether Combine is allowed to produce  
> nodes and
>   /// types that are illegal on the target.
> -  void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned  
> OptLevel);
> +  void Combine(CombineLevel Level, AliasAnalysis &AA,
> +               CodeGenOpt::Level OptLevel);
>
>   /// LegalizeTypes - This transforms the SelectionDAG into a  
> SelectionDAG that
>   /// only uses types natively supported by the target.  Returns  
> "true" if it
> @@ -218,7 +218,7 @@
>   ///
>   /// Note that this is an involved process that may invalidate  
> pointers into
>   /// the graph.
> -  void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
> +  void Legalize(bool TypesNeedLegalizing, CodeGenOpt::Level  
> OptLevel);
>
>   /// RemoveDeadNodes - This method deletes all unreachable nodes in  
> the
>   /// SelectionDAG.
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Wed Apr 29  
> 18:29:43 2009
> @@ -51,10 +51,11 @@
>   MachineBasicBlock *BB;
>   AliasAnalysis *AA;
>   GCFunctionInfo *GFI;
> -  unsigned OptLevel;
> +  CodeGenOpt::Level OptLevel;
>   static char ID;
>
> -  explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
> +  explicit SelectionDAGISel(TargetMachine &tm,
> +                            CodeGenOpt::Level OL =  
> CodeGenOpt::Default);
>   virtual ~SelectionDAGISel();
>
>   TargetLowering &getTargetLowering() { return TLI; }
>
> Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h  
> (original)
> +++ llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Wed  
> Apr 29 18:29:43 2009
> @@ -18,8 +18,9 @@
> #include <vector>
> #include <map>
> #include <string>
> -#include "llvm/System/Mutex.h"
> #include "llvm/ADT/SmallVector.h"
> +#include "llvm/System/Mutex.h"
> +#include "llvm/Target/TargetMachine.h"
>
> namespace llvm {
>
> @@ -84,7 +85,7 @@
>   // libraries, the JIT and Interpreter set these functions to ctor  
> pointers
>   // at startup time if they are linked in.
>   typedef ExecutionEngine *(*EECtorFn)(ModuleProvider*, std::string*,
> -                                       unsigned OptLevel);
> +                                       CodeGenOpt::Level OptLevel);
>   static EECtorFn JITCtor, InterpCtor;
>
>   /// LazyFunctionCreator - If an unknown function is needed, this  
> function
> @@ -114,7 +115,8 @@
>   static ExecutionEngine *create(ModuleProvider *MP,
>                                  bool ForceInterpreter = false,
>                                  std::string *ErrorStr = 0,
> -                                 unsigned OptLevel = 3);
> +                                 CodeGenOpt::Level OptLevel =
> +                                   CodeGenOpt::Default);
>
>   /// create - This is the factory method for creating an execution  
> engine which
>   /// is appropriate for the current machine.  This takes ownership  
> of the
> @@ -127,10 +129,9 @@
>   static ExecutionEngine *createJIT(ModuleProvider *MP,
>                                     std::string *ErrorStr = 0,
>                                     JITMemoryManager *JMM = 0,
> -                                    unsigned OptLevel = 3);
> -
> -
> -
> +                                    CodeGenOpt::Level OptLevel =
> +                                      CodeGenOpt::Default);
> +
>   /// addModuleProvider - Add a ModuleProvider to the list of  
> modules that we
>   /// can JIT from.  Note that this takes ownership of the  
> ModuleProvider: when
>   /// the ExecutionEngine is destroyed, it destroys the MP as well.
>
> Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetMachine.h Wed Apr 29  
> 18:29:43 2009
> @@ -68,6 +68,19 @@
>   };
> }
>
> +// Code generation optimization level.
> +namespace CodeGenOpt {
> +  enum Level {
> +    Default,
> +    None,
> +    One,
> +    Two,
> +    Size,
> +    Aggressive,
> +    LTO
> +  };
> +}
> +
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
> ///
> /// TargetMachine - Primary interface to the complete machine  
> description for
> @@ -213,7 +226,7 @@
>   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
>                                                raw_ostream &,
>                                                CodeGenFileType,
> -                                               unsigned /* OptLevel  
> */) {
> +                                               CodeGenOpt::Level) {
>     return FileModel::None;
>   }
>
> @@ -223,7 +236,7 @@
>   ///
>   virtual bool addPassesToEmitFileFinish(PassManagerBase &,
>                                          MachineCodeEmitter *,
> -                                         unsigned /* OptLevel */) {
> +                                         CodeGenOpt::Level) {
>     return true;
>   }
>
> @@ -235,7 +248,7 @@
>   ///
>   virtual bool addPassesToEmitMachineCode(PassManagerBase &,
>                                           MachineCodeEmitter &,
> -                                          unsigned /* OptLevel */) {
> +                                          CodeGenOpt::Level) {
>     return true;
>   }
>
> @@ -245,7 +258,7 @@
>   virtual bool WantsWholeFile() const { return false; }
>   virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
>                                         CodeGenFileType,
> -                                        unsigned /* OptLevel */) {
> +                                        CodeGenOpt::Level) {
>     return true;
>   }
> };
> @@ -260,13 +273,13 @@
>   /// addCommonCodeGenPasses - Add standard LLVM codegen passes used  
> for
>   /// both emitting to assembly files or machine code output.
>   ///
> -  bool addCommonCodeGenPasses(PassManagerBase &, unsigned /*  
> OptLevel */);
> +  bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level);
>
> public:
>
>   /// addPassesToEmitFile - Add passes to the specified pass manager  
> to get the
>   /// specified file emitted.  Typically this will involve several  
> steps of code
> -  /// generation.  If OptLevel is 0, the code generator should emit  
> code as fast
> +  /// generation.  If OptLevel is None, the code generator should  
> emit code as fast
>   /// as possible, though the generated code may be less efficient.   
> This method
>   /// should return FileModel::Error if emission of this file type  
> is not
>   /// supported.
> @@ -278,7 +291,7 @@
>   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
>                                                raw_ostream &Out,
>                                                CodeGenFileType  
> FileType,
> -                                               unsigned OptLevel);
> +                                               CodeGenOpt::Level);
>
>   /// addPassesToEmitFileFinish - If the passes to emit the  
> specified file had
>   /// to be split up (e.g., to add an object writer pass), this  
> method can be
> @@ -286,7 +299,7 @@
>   ///
>   virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
>                                          MachineCodeEmitter *MCE,
> -                                         unsigned OptLevel);
> +                                         CodeGenOpt::Level);
>
>   /// addPassesToEmitMachineCode - Add passes to the specified pass  
> manager to
>   /// get machine code emitted.  This uses a MachineCodeEmitter  
> object to handle
> @@ -296,21 +309,21 @@
>   ///
>   virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
>                                           MachineCodeEmitter &MCE,
> -                                          unsigned OptLevel);
> +                                          CodeGenOpt::Level);
>
>   /// Target-Independent Code Generator Pass Configuration Options.
>
>   /// addInstSelector - This method should add any "last minute"  
> LLVM->LLVM
>   /// passes, then install an instruction selector pass, which  
> converts from
>   /// LLVM code to machine instructions.
> -  virtual bool addInstSelector(PassManagerBase &, unsigned /*  
> OptLevel */) {
> +  virtual bool addInstSelector(PassManagerBase &,  
> CodeGenOpt::Level) {
>     return true;
>   }
>
>   /// addPreRegAllocPasses - This method may be implemented by  
> targets that want
>   /// to run passes immediately before register allocation. This  
> should return
>   /// true if -print-machineinstrs should print after these passes.
> -  virtual bool addPreRegAlloc(PassManagerBase &, unsigned /*  
> OptLevel */) {
> +  virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
>     return false;
>   }
>
> @@ -318,14 +331,14 @@
>   /// want to run passes after register allocation but before prolog- 
> epilog
>   /// insertion.  This should return true if -print-machineinstrs  
> should print
>   /// after these passes.
> -  virtual bool addPostRegAlloc(PassManagerBase &, unsigned /*  
> OptLevel */) {
> +  virtual bool addPostRegAlloc(PassManagerBase &,  
> CodeGenOpt::Level) {
>     return false;
>   }
>
>   /// addPreEmitPass - This pass may be implemented by targets that  
> want to run
>   /// passes immediately before machine code is emitted.  This  
> should return
>   /// true if -print-machineinstrs should print out the code after  
> the passes.
> -  virtual bool addPreEmitPass(PassManagerBase &, unsigned /*  
> OptLevel */) {
> +  virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
>     return false;
>   }
>
> @@ -333,7 +346,7 @@
>   /// addAssemblyEmitter - This pass should be overridden by the  
> target to add
>   /// the asmprinter, if asm emission is supported.  If this is not  
> supported,
>   /// 'true' should be returned.
> -  virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /*  
> OptLevel */,
> +  virtual bool addAssemblyEmitter(PassManagerBase &,  
> CodeGenOpt::Level,
>                                   bool /* VerboseAsmDefault */,  
> raw_ostream &) {
>     return true;
>   }
> @@ -341,7 +354,7 @@
>   /// addCodeEmitter - This pass should be overridden by the target  
> to add a
>   /// code emitter, if supported.  If this is not supported, 'true'  
> should be
>   /// returned. If DumpAsm is true, the generated assembly is  
> printed to cerr.
> -  virtual bool addCodeEmitter(PassManagerBase &, unsigned /*  
> OptLevel */,
> +  virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
>                               bool /*DumpAsm*/, MachineCodeEmitter  
> &) {
>     return true;
>   }
> @@ -350,7 +363,7 @@
>   /// a code emitter (without setting flags), if supported.  If this  
> is not
>   /// supported, 'true' should be returned.  If DumpAsm is true, the  
> generated
>   /// assembly is printed to cerr.
> -  virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /*  
> OptLevel */,
> +  virtual bool addSimpleCodeEmitter(PassManagerBase &,  
> CodeGenOpt::Level,
>                                     bool /*DumpAsm*/,  
> MachineCodeEmitter &) {
>     return true;
>   }
>
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -27,7 +27,6 @@
> #include "llvm/Target/TargetAsmInfo.h"
> #include "llvm/Target/TargetData.h"
> #include "llvm/Target/TargetLowering.h"
> -#include "llvm/Target/TargetMachine.h"
> #include "llvm/Target/TargetOptions.h"
> #include "llvm/Target/TargetRegisterInfo.h"
> #include "llvm/ADT/SmallPtrSet.h"
> @@ -42,7 +41,7 @@
>
> char AsmPrinter::ID = 0;
> AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
> -                       const TargetAsmInfo *T, unsigned OL, bool  
> VDef)
> +                       const TargetAsmInfo *T, CodeGenOpt::Level  
> OL, bool VDef)
>   : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
>     TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
>     IsInTextSection(false)
>
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -3351,7 +3351,7 @@
>   }
>
>   /// ValidDebugInfo - Return true if V represents valid debug info  
> value.
> -  bool ValidDebugInfo(Value *V, unsigned OptLevel) {
> +  bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) {
>     if (!V)
>       return false;
>
> @@ -3393,7 +3393,7 @@
>     case DW_TAG_lexical_block:
>       /// FIXME. This interfers with the qualitfy of generated code  
> when
>       /// during optimization.
> -      if (OptLevel != 0)
> +      if (OptLevel != CodeGenOpt::None)
>         return false;
>     default:
>       break;
> @@ -4731,7 +4731,7 @@
> }
>
> /// ValidDebugInfo - Return true if V represents valid debug info  
> value.
> -bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
> +bool DwarfWriter::ValidDebugInfo(Value *V, CodeGenOpt::Level  
> OptLevel) {
>   return DD && DD->ValidDebugInfo(V, OptLevel);
> }
>
>
> Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Apr 29 18:29:43  
> 2009
> @@ -55,7 +55,7 @@
> LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
>                                        raw_ostream &Out,
>                                        CodeGenFileType FileType,
> -                                       unsigned OptLevel) {
> +                                       CodeGenOpt::Level OptLevel) {
>   // Add common CodeGen passes.
>   if (addCommonCodeGenPasses(PM, OptLevel))
>     return FileModel::Error;
> @@ -69,7 +69,7 @@
>   if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
> -  if (OptLevel != 0)
> +  if (OptLevel != CodeGenOpt::None)
>     PM.add(createLoopAlignerPass());
>
>   switch (FileType) {
> @@ -94,7 +94,7 @@
> /// finish up adding passes to emit the file, if necessary.
> bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
>                                                   MachineCodeEmitter  
> *MCE,
> -                                                  unsigned  
> OptLevel) {
> +                                                  CodeGenOpt::Level  
> OptLevel) {
>   if (MCE)
>     addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
>
> @@ -114,7 +114,7 @@
> ///
> bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase  
> &PM,
>                                                     
> MachineCodeEmitter &MCE,
> -                                                   unsigned  
> OptLevel) {
> +                                                    
> CodeGenOpt::Level OptLevel) {
>   // Add common CodeGen passes.
>   if (addCommonCodeGenPasses(PM, OptLevel))
>     return true;
> @@ -132,15 +132,15 @@
>   return false; // success!
> }
>
> -/// addCommonCodeGenPasses - Add standard LLVM codegen passes used  
> for
> -/// both emitting to assembly files or machine code output.
> +/// addCommonCodeGenPasses - Add standard LLVM codegen passes used  
> for both
> +/// emitting to assembly files or machine code output.
> ///
> bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
> -                                               unsigned OptLevel) {
> +                                               CodeGenOpt::Level  
> OptLevel) {
>   // Standard LLVM-Level Passes.
>
>   // Run loop strength reduction before anything else.
> -  if (OptLevel != 0) {
> +  if (OptLevel != CodeGenOpt::None) {
>     PM.add(createLoopStrengthReducePass(getTargetLowering()));
>     if (PrintLSR)
>       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n",  
> &errs()));
> @@ -154,7 +154,7 @@
>   // Make sure that no unreachable blocks are instruction selected.
>   PM.add(createUnreachableBlockEliminationPass());
>
> -  if (OptLevel != 0)
> +  if (OptLevel != CodeGenOpt::None)
>     PM.add(createCodeGenPreparePass(getTargetLowering()));
>
>   PM.add(createStackProtectorPass(getTargetLowering()));
> @@ -168,7 +168,7 @@
>
>   // Enable FastISel with -fast, but allow that to be overridden.
>   if (EnableFastISelOption == cl::BOU_TRUE ||
> -      (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
> +      (OptLevel == CodeGenOpt::None && EnableFastISelOption !=  
> cl::BOU_FALSE))
>     EnableFastISel = true;
>
>   // Ask the target for an isel.
> @@ -179,7 +179,7 @@
>   if (PrintMachineCode)
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
> -  if (OptLevel != 0) {
> +  if (OptLevel != CodeGenOpt::None) {
>     PM.add(createMachineLICMPass());
>     PM.add(createMachineSinkingPass());
>   }
> @@ -192,7 +192,7 @@
>   PM.add(createRegisterAllocator());
>
>   // Perform stack slot coloring.
> -  if (OptLevel != 0)
> +  if (OptLevel != CodeGenOpt::None)
>     PM.add(createStackSlotColoringPass());
>
>   if (PrintMachineCode)  // Print the register-allocated code
> @@ -217,7 +217,7 @@
>     PM.add(createMachineFunctionPrinterPass(cerr));
>
>   // Second pass scheduler.
> -  if (OptLevel != 0 && !DisablePostRAScheduler) {
> +  if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
>     PM.add(createPostRAScheduler());
>
>     if (PrintMachineCode)
> @@ -225,7 +225,7 @@
>   }
>
>   // Branch folding must be run after regalloc and prolog/epilog  
> insertion.
> -  if (OptLevel != 0)
> +  if (OptLevel != CodeGenOpt::None)
>     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
>
>   if (PrintMachineCode)
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -57,7 +57,7 @@
>     SelectionDAG &DAG;
>     const TargetLowering &TLI;
>     CombineLevel Level;
> -    unsigned OptLevel;
> +    CodeGenOpt::Level OptLevel;
>     bool LegalOperations;
>     bool LegalTypes;
>
> @@ -254,7 +254,7 @@
>     }
>
> public:
> -    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
> +    DAGCombiner(SelectionDAG &D, AliasAnalysis &A,  
> CodeGenOpt::Level OL)
>       : DAG(D),
>         TLI(D.getTargetLoweringInfo()),
>         Level(Unrestricted),
> @@ -4784,7 +4784,7 @@
>   SDValue Ptr   = LD->getBasePtr();
>
>   // Try to infer better alignment information than the load already  
> has.
> -  if (OptLevel != 0 && LD->isUnindexed()) {
> +  if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
>     if (unsigned Align = InferAlignment(Ptr, DAG)) {
>       if (Align > LD->getAlignment())
>         return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc 
> (),
> @@ -4904,7 +4904,7 @@
>   SDValue Ptr   = ST->getBasePtr();
>
>   // Try to infer better alignment information than the store  
> already has.
> -  if (OptLevel != 0 && ST->isUnindexed()) {
> +  if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
>     if (unsigned Align = InferAlignment(Ptr, DAG)) {
>       if (Align > ST->getAlignment())
>         return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
> @@ -6093,7 +6093,7 @@
> // SelectionDAG::Combine - This is the entry point for the file.
> //
> void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
> -                           unsigned OptLevel) {
> +                           CodeGenOpt::Level OptLevel) {
>   /// run - This is the main entry point to this class.
>   ///
>   DAGCombiner(*this, AA, OptLevel).Run(Level);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -327,7 +327,7 @@
>   default: break;
>   case Intrinsic::dbg_stoppoint: {
>     DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
> -    if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
> +    if (DW && DW->ValidDebugInfo(SPI->getContext(),  
> CodeGenOpt::None)) {
>       DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
>       std::string Dir, FN;
>       unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
> @@ -344,7 +344,7 @@
>   }
>   case Intrinsic::dbg_region_start: {
>     DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
> -    if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
> +    if (DW && DW->ValidDebugInfo(RSI->getContext(),  
> CodeGenOpt::None)) {
>       unsigned ID =
>         DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext 
> ()));
>       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
> @@ -354,7 +354,7 @@
>   }
>   case Intrinsic::dbg_region_end: {
>     DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
> -    if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
> +    if (DW && DW->ValidDebugInfo(REI->getContext(),  
> CodeGenOpt::None)) {
>      unsigned ID = 0;
>      DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
>      if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction 
> ())) {
> @@ -380,7 +380,7 @@
>     DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
>     Value *SP = FSI->getSubprogram();
>
> -    if (DW->ValidDebugInfo(SP, 0)) {
> +    if (DW->ValidDebugInfo(SP, CodeGenOpt::None)) {
>       // llvm.dbg.func.start implicitly defines a dbg_stoppoint  
> which is what
>       // (most?) gdb expects.
>       DebugLoc PrevLoc = DL;
> @@ -425,7 +425,7 @@
>   case Intrinsic::dbg_declare: {
>     DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
>     Value *Variable = DI->getVariable();
> -    if (DW && DW->ValidDebugInfo(Variable, 0)) {
> +    if (DW && DW->ValidDebugInfo(Variable, CodeGenOpt::None)) {
>       // Determine the address of the declared object.
>       Value *Address = DI->getAddress();
>       if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -55,7 +55,7 @@
> class VISIBILITY_HIDDEN SelectionDAGLegalize {
>   TargetLowering &TLI;
>   SelectionDAG &DAG;
> -  unsigned OptLevel;
> +  CodeGenOpt::Level OptLevel;
>   bool TypesNeedLegalizing;
>
>   // Libcall insertion helpers.
> @@ -139,7 +139,7 @@
>
> public:
>   explicit SelectionDAGLegalize(SelectionDAG &DAG, bool  
> TypesNeedLegalizing,
> -                                unsigned ol);
> +                                CodeGenOpt::Level ol);
>
>   /// getTypeAction - Return how we should legalize values of this  
> type, either
>   /// it is already legal or we need to expand it into multiple  
> registers of
> @@ -350,7 +350,7 @@
> }
>
> SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
> -                                           bool types, unsigned ol)
> +                                           bool types,  
> CodeGenOpt::Level ol)
>   : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
>     TypesNeedLegalizing(types), ValueTypeActions 
> (TLI.getValueTypeActions()) {
>   assert(MVT::LAST_VALUETYPE <= 32 &&
> @@ -1276,7 +1276,7 @@
>         unsigned Line = DSP->getLine();
>         unsigned Col = DSP->getColumn();
>
> -        if (OptLevel == 0) {
> +        if (OptLevel == CodeGenOpt::None) {
>           // A bit self-referential to have DebugLoc on Debug_Loc  
> nodes, but it
>           // won't hurt anything.
>           if (useDEBUG_LOC) {
> @@ -8571,7 +8571,8 @@
>
> // SelectionDAG::Legalize - This is the entry point for the file.
> //
> -void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned  
> OptLevel) {
> +void SelectionDAG::Legalize(bool TypesNeedLegalizing,
> +                            CodeGenOpt::Level OptLevel) {
>   /// run - This is the main entry point to this class.
>   ///
>   SelectionDAGLegalize(*this, TypesNeedLegalizing,  
> OptLevel).LegalizeDAG();
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Wed Apr  
> 29 18:29:43 2009
> @@ -630,6 +630,6 @@
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> llvm::ScheduleDAGSDNodes *
> -llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
> +llvm::createFastDAGScheduler(SelectionDAGISel *IS,  
> CodeGenOpt::Level) {
>   return new ScheduleDAGFast(*IS->MF);
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Wed Apr  
> 29 18:29:43 2009
> @@ -261,7 +261,7 @@
> /// new hazard recognizer. This scheduler takes ownership of the  
> hazard
> /// recognizer and deletes it when done.
> ScheduleDAGSDNodes *
> -llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
> +llvm::createTDListDAGScheduler(SelectionDAGISel *IS,  
> CodeGenOpt::Level) {
>   return new ScheduleDAGList(*IS->MF,
>                              new LatencyPriorityQueue(),
>                              IS->CreateTargetHazardRecognizer());
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed  
> Apr 29 18:29:43 2009
> @@ -1505,7 +1505,7 @@
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> llvm::ScheduleDAGSDNodes *
> -llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
> +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,  
> CodeGenOpt::Level) {
>   const TargetMachine &TM = IS->TM;
>   const TargetInstrInfo *TII = TM.getInstrInfo();
>   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
> @@ -1519,7 +1519,7 @@
> }
>
> llvm::ScheduleDAGSDNodes *
> -llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
> +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,  
> CodeGenOpt::Level) {
>   const TargetMachine &TM = IS->TM;
>   const TargetInstrInfo *TII = TM.getInstrInfo();
>   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed  
> Apr 29 18:29:43 2009
> @@ -45,7 +45,6 @@
> #include "llvm/Target/TargetInstrInfo.h"
> #include "llvm/Target/TargetIntrinsicInfo.h"
> #include "llvm/Target/TargetLowering.h"
> -#include "llvm/Target/TargetMachine.h"
> #include "llvm/Target/TargetOptions.h"
> #include "llvm/Support/Compiler.h"
> #include "llvm/Support/CommandLine.h"
> @@ -335,7 +334,8 @@
>             DwarfWriter *DW = DAG.getDwarfWriter();
>             DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
>
> -            if (DW && DW->ValidDebugInfo(SPI->getContext(), false)) {
> +            if (DW && DW->ValidDebugInfo(SPI->getContext(),
> +                                         CodeGenOpt::Default)) {
>               DICompileUnit CU(cast<GlobalVariable>(SPI->getContext 
> ()));
>               std::string Dir, FN;
>               unsigned SrcFile = DW->getOrCreateSourceID 
> (CU.getDirectory(Dir),
> @@ -354,7 +354,7 @@
>               DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
>               Value *SP = FSI->getSubprogram();
>
> -              if (DW->ValidDebugInfo(SP, false)) {
> +              if (DW->ValidDebugInfo(SP, CodeGenOpt::Default)) {
>                 DISubprogram Subprogram(cast<GlobalVariable>(SP));
>                 DICompileUnit CU(Subprogram.getCompileUnit());
>                 std::string Dir, FN;
> @@ -3899,7 +3899,7 @@
>     DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
>     if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
>       MachineFunction &MF = DAG.getMachineFunction();
> -      if (OptLevel == 0)
> +      if (OptLevel == CodeGenOpt::None)
>         DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
>                                         SPI.getLine(),
>                                         SPI.getColumn(),
> @@ -3940,7 +3940,7 @@
>           && strcmp(SPName.c_str(), MF.getFunction()->getNameStart 
> ())) {
>           // This is end of inlined function. Debugging information  
> for
>           // inlined function is not handled yet (only supported by  
> FastISel).
> -        if (OptLevel == 0) {
> +        if (OptLevel == CodeGenOpt::None) {
>           unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
>           if (ID != 0)
>             // Returned ID is 0 if this is unbalanced "end of inlined
> @@ -3968,7 +3968,7 @@
>     Value *SP = FSI.getSubprogram();
>     if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
>       MachineFunction &MF = DAG.getMachineFunction();
> -      if (OptLevel == 0) {
> +      if (OptLevel == CodeGenOpt::None) {
>         // llvm.dbg.func.start implicitly defines a dbg_stoppoint  
> which is what
>         // (most?) gdb expects.
>         DebugLoc PrevLoc = CurDebugLoc;
> @@ -4039,7 +4039,7 @@
>     return 0;
>   }
>   case Intrinsic::dbg_declare: {
> -    if (OptLevel == 0) {
> +    if (OptLevel == CodeGenOpt::None) {
>       DwarfWriter *DW = DAG.getDwarfWriter();
>       DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
>       Value *Variable = DI.getVariable();
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Wed Apr  
> 29 18:29:43 2009
> @@ -23,6 +23,7 @@
> #include "llvm/CodeGen/SelectionDAGNodes.h"
> #include "llvm/CodeGen/ValueTypes.h"
> #include "llvm/Support/CallSite.h"
> +#include "llvm/Target/TargetMachine.h"
> #include <vector>
> #include <set>
>
> @@ -357,13 +358,14 @@
>
>   /// OptLevel - What optimization level we're generating code for.
>   ///
> -  unsigned OptLevel;
> +  CodeGenOpt::Level OptLevel;
>
>   /// GFI - Garbage collection metadata for the function.
>   GCFunctionInfo *GFI;
>
>   SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
> -                       FunctionLoweringInfo &funcinfo, unsigned ol)
> +                       FunctionLoweringInfo &funcinfo,
> +                       CodeGenOpt::Level ol)
>     : CurDebugLoc(DebugLoc::getUnknownLoc()),
>       TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
>   }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp  
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Apr  
> 29 18:29:43 2009
> @@ -136,10 +136,10 @@
>   /// createDefaultScheduler - This creates an instruction scheduler  
> appropriate
>   /// for the target.
>   ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
> -                                             unsigned OptLevel) {
> +                                             CodeGenOpt::Level  
> OptLevel) {
>     const TargetLowering &TLI = IS->getTargetLowering();
>
> -    if (OptLevel == 0)
> +    if (OptLevel == CodeGenOpt::None)
>       return createFastDAGScheduler(IS, OptLevel);
>     if (TLI.getSchedulingPreference() ==  
> TargetLowering::SchedulingForLatency)
>       return createTDListDAGScheduler(IS, OptLevel);
> @@ -262,7 +262,7 @@
> // SelectionDAGISel code
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> -SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
> +SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,  
> CodeGenOpt::Level OL) :
>   FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
>   FuncInfo(new FunctionLoweringInfo(TLI)),
>   CurDAG(new SelectionDAG(TLI, *FuncInfo)),
> @@ -645,7 +645,7 @@
>
>   if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
>
> -  if (OptLevel != 0)
> +  if (OptLevel != CodeGenOpt::None)
>     ComputeLiveOutVRegInfo();
>
>   // Third, instruction select all of the operations to machine  
> code, adding the
>
> Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp (original)
> +++ llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -383,7 +383,7 @@
> ExecutionEngine *ExecutionEngine::create(ModuleProvider *MP,
>                                          bool ForceInterpreter,
>                                          std::string *ErrorStr,
> -                                         unsigned OptLevel) {
> +                                         CodeGenOpt::Level  
> OptLevel) {
>   ExecutionEngine *EE = 0;
>
>   // Make sure we can resolve symbols in the program as well. The  
> zero arg
>
> Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp  
> (original)
> +++ llvm/trunk/lib/ExecutionEngine/ExecutionEngineBindings.cpp Wed  
> Apr 29 18:29:43 2009
> @@ -114,7 +114,7 @@
>
> int LLVMCreateJITCompiler(LLVMExecutionEngineRef *OutJIT,
>                           LLVMModuleProviderRef MP,
> -                          unsigned OptLevel,
> +                          CodeGenOpt::Level OptLevel,
>                           char **OutError) {
>   std::string Error;
>   if (ExecutionEngine *JIT = ExecutionEngine::createJIT(unwrap(MP),  
> &Error, 0,
>
> Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp  
> (original)
> +++ llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp Wed  
> Apr 29 18:29:43 2009
> @@ -37,7 +37,7 @@
> /// create - Create a new interpreter object.  This can never fail.
> ///
> ExecutionEngine *Interpreter::create(ModuleProvider *MP,  
> std::string* ErrStr,
> -                                     unsigned OptLevel /*unused*/) {
> +                                     CodeGenOpt::Level OptLevel / 
> *unused*/) {
>   // Tell this ModuleProvide to materialize and release the module
>   if (!MP->materializeModule(ErrStr))
>     // We got an error, just return 0
>
> Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h  
> (original)
> +++ llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h Wed Apr  
> 29 18:29:43 2009
> @@ -108,7 +108,7 @@
>   /// create - Create an interpreter ExecutionEngine. This can never  
> fail.
>   ///
>   static ExecutionEngine *create(ModuleProvider *M, std::string  
> *ErrorStr = 0,
> -                                 unsigned OptLevel /*unused*/ = 3);
> +                                 CodeGenOpt::Level =  
> CodeGenOpt::Default);
>
>   /// run - Start execution with the specified function and arguments.
>   ///
>
> Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp (original)
> +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp Wed Apr 29 18:29:43  
> 2009
> @@ -196,7 +196,7 @@
> ExecutionEngine *ExecutionEngine::createJIT(ModuleProvider *MP,
>                                             std::string *ErrorStr,
>                                             JITMemoryManager *JMM,
> -                                            unsigned OptLevel) {
> +                                            CodeGenOpt::Level  
> OptLevel) {
>   ExecutionEngine *EE = JIT::createJIT(MP, ErrorStr, JMM, OptLevel);
>   if (!EE) return 0;
>
> @@ -207,7 +207,7 @@
> }
>
> JIT::JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji,
> -         JITMemoryManager *JMM, unsigned OptLevel)
> +         JITMemoryManager *JMM, CodeGenOpt::Level OptLevel)
>   : ExecutionEngine(MP), TM(tm), TJI(tji) {
>   setTargetData(TM.getTargetData());
>
> @@ -272,7 +272,7 @@
>
>     // Turn the machine code intermediate representation into bytes  
> in memory
>     // that may be executed.
> -    if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
> +    if (TM.addPassesToEmitMachineCode(PM, *MCE,  
> CodeGenOpt::Default)) {
>       cerr << "Target does not support machine code emission!\n";
>       abort();
>     }
> @@ -305,7 +305,7 @@
>
>     // Turn the machine code intermediate representation into bytes  
> in memory
>     // that may be executed.
> -    if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
> +    if (TM.addPassesToEmitMachineCode(PM, *MCE,  
> CodeGenOpt::Default)) {
>       cerr << "Target does not support machine code emission!\n";
>       abort();
>     }
> @@ -337,7 +337,7 @@
>
>     // Turn the machine code intermediate representation into bytes  
> in memory
>     // that may be executed.
> -    if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
> +    if (TM.addPassesToEmitMachineCode(PM, *MCE,  
> CodeGenOpt::Default)) {
>       cerr << "Target does not support machine code emission!\n";
>       abort();
>     }
>
> Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.h (original)
> +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.h Wed Apr 29 18:29:43 2009
> @@ -55,7 +55,7 @@
>   JITState *jitstate;
>
>   JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji,
> -      JITMemoryManager *JMM, unsigned OptLevel);
> +      JITMemoryManager *JMM, CodeGenOpt::Level OptLevel);
> public:
>   ~JIT();
>
> @@ -71,7 +71,8 @@
>   /// for the current target.  Otherwise, return null.
>   ///
>   static ExecutionEngine *create(ModuleProvider *MP, std::string *Err,
> -                                 unsigned OptLevel = 3) {
> +                                 CodeGenOpt::Level OptLevel =
> +                                   CodeGenOpt::Default) {
>     return createJIT(MP, Err, 0, OptLevel);
>   }
>
> @@ -148,7 +149,8 @@
>   MachineCodeEmitter *getCodeEmitter() const { return MCE; }
>
>   static ExecutionEngine *createJIT(ModuleProvider *MP, std::string  
> *Err,
> -                                    JITMemoryManager *JMM, unsigned  
> OptLevel);
> +                                    JITMemoryManager *JMM,
> +                                    CodeGenOpt::Level OptLevel);
>
> private:
>   static MachineCodeEmitter *createEmitter(JIT &J, JITMemoryManager  
> *JMM);
>
> Modified: llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp (original)
> +++ llvm/trunk/lib/ExecutionEngine/JIT/TargetSelect.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -42,7 +42,8 @@
> /// available for the current target.  Otherwise, return null.
> ///
> ExecutionEngine *JIT::createJIT(ModuleProvider *MP, std::string  
> *ErrorStr,
> -                                JITMemoryManager *JMM, unsigned  
> OptLevel) {
> +                                JITMemoryManager *JMM,
> +                                CodeGenOpt::Level OptLevel) {
>   const TargetMachineRegistry::entry *TheArch = MArch;
>   if (TheArch == 0) {
>     std::string Error;
>
> Modified: llvm/trunk/lib/Target/ARM/ARM.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARM.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARM.h Wed Apr 29 18:29:43 2009
> @@ -15,6 +15,7 @@
> #ifndef TARGET_ARM_H
> #define TARGET_ARM_H
>
> +#include "llvm/Target/TargetMachine.h"
> #include <cassert>
>
> namespace llvm {
> @@ -91,7 +92,8 @@
> FunctionPass *createARMISelDag(ARMTargetMachine &TM);
> FunctionPass *createARMCodePrinterPass(raw_ostream &O,
>                                        ARMTargetMachine &TM,
> -                                       unsigned OptLevel, bool  
> Verbose);
> +                                       CodeGenOpt::Level OptLevel,
> +                                       bool Verbose);
> FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
>                                        MachineCodeEmitter &MCE);
> FunctionPass *createARMLoadStoreOptimizationPass();
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -138,17 +138,20 @@
>
>
> // Pass Pipeline Configuration
> -bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,  
> unsigned OptLevel) {
> +bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
> +                                       CodeGenOpt::Level OptLevel) {
>   PM.add(createARMISelDag(*this));
>   return false;
> }
>
> -bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel) {
> +bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM,
> +                                      CodeGenOpt::Level OptLevel) {
>   // FIXME: temporarily disabling load / store optimization pass for  
> Thumb mode.
> -  if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
> +  if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && ! 
> Subtarget.isThumb())
>     PM.add(createARMLoadStoreOptimizationPass());
>
> -  if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
> +  if (OptLevel != CodeGenOpt::None &&
> +      !DisableIfConversion && !Subtarget.isThumb())
>     PM.add(createIfConverterPass());
>
>   PM.add(createARMConstantIslandPass());
> @@ -156,7 +159,7 @@
> }
>
> bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> -                                          unsigned OptLevel,
> +                                          CodeGenOpt::Level OptLevel,
>                                           bool Verbose,
>                                           raw_ostream &Out) {
>   // Output assembly language.
> @@ -168,8 +171,10 @@
> }
>
>
> -bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
> -                                      bool DumpAsm,  
> MachineCodeEmitter &MCE) {
> +bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM,
> +                                      CodeGenOpt::Level OptLevel,
> +                                      bool DumpAsm,
> +                                      MachineCodeEmitter &MCE) {
>   // FIXME: Move this to TargetJITInfo!
>   if (DefRelocModel == Reloc::Default)
>     setRelocationModel(Reloc::Static);
> @@ -186,7 +191,7 @@
> }
>
> bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
> -                                            unsigned OptLevel,
> +                                            CodeGenOpt::Level  
> OptLevel,
>                                             bool DumpAsm,
>                                             MachineCodeEmitter &MCE) {
>   // Machine code emitter pass for ARM.
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Wed Apr 29 18:29:43  
> 2009
> @@ -41,7 +41,8 @@
>   // set this functions to ctor pointer at startup time if they are  
> linked in.
>   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
>                                             ARMTargetMachine &tm,
> -                                            unsigned OptLevel, bool  
> verbose);
> +                                            CodeGenOpt::Level  
> OptLevel,
> +                                            bool verbose);
>   static AsmPrinterCtorFn AsmPrinterCtor;
>
> public:
> @@ -69,14 +70,17 @@
>   virtual const TargetAsmInfo *createTargetAsmInfo() const;
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> -  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
> +  virtual bool addInstSelector(PassManagerBase &PM,  
> CodeGenOpt::Level OptLevel);
> +  virtual bool addPreEmitPass(PassManagerBase &PM,  
> CodeGenOpt::Level OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM,
> +                                  CodeGenOpt::Level OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> -  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
> +  virtual bool addCodeEmitter(PassManagerBase &PM,  
> CodeGenOpt::Level OptLevel,
>                               bool DumpAsm, MachineCodeEmitter &MCE);
> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
> -                                    bool DumpAsm,  
> MachineCodeEmitter &MCE);
> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
> +                                    CodeGenOpt::Level OptLevel,
> +                                    bool DumpAsm,
> +                                    MachineCodeEmitter &MCE);
> };
>
> /// ThumbTargetMachine - Thumb target machine.
>
> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Wed Apr  
> 29 18:29:43 2009
> @@ -81,7 +81,8 @@
>     bool InCPMode;
>   public:
>     explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                           const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +                           const TargetAsmInfo *T,  
> CodeGenOpt::Level OL,
> +                           bool V)
>       : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP 
> (NULL),
>         InCPMode(false) {
>       Subtarget = &TM.getSubtarget<ARMSubtarget>();
> @@ -1061,7 +1062,8 @@
> ///
> FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
>                                              ARMTargetMachine &tm,
> -                                             unsigned OptLevel,  
> bool verbose) {
> +                                             CodeGenOpt::Level  
> OptLevel,
> +                                             bool verbose) {
>   return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,  
> verbose);
> }
>
>
> Modified: llvm/trunk/lib/Target/Alpha/Alpha.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/Alpha.h (original)
> +++ llvm/trunk/lib/Target/Alpha/Alpha.h Wed Apr 29 18:29:43 2009
> @@ -15,18 +15,20 @@
> #ifndef TARGET_ALPHA_H
> #define TARGET_ALPHA_H
>
> +#include "llvm/Target/TargetMachine.h"
> +
> namespace llvm {
>
>   class AlphaTargetMachine;
>   class FunctionPass;
> -  class TargetMachine;
>   class MachineCodeEmitter;
>   class raw_ostream;
>
>   FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
>   FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
>                                            TargetMachine &TM,
> -                                           unsigned OptLevel, bool  
> Verbose);
> +                                           CodeGenOpt::Level  
> OptLevel,
> +                                           bool Verbose);
>   FunctionPass *createAlphaPatternInstructionSelector(TargetMachine  
> &TM);
>   FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
>                                            MachineCodeEmitter &MCE);
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -77,25 +77,26 @@
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
> -                                         unsigned OptLevel) {
> +                                         CodeGenOpt::Level  
> OptLevel) {
>   PM.add(createAlphaISelDag(*this));
>   return false;
> }
> bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
> -                                        unsigned OptLevel) {
> +                                        CodeGenOpt::Level OptLevel) {
>   // Must run branch selection immediately preceding the asm printer
>   PM.add(createAlphaBranchSelectionPass());
>   return false;
> }
> bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> -                                            unsigned OptLevel,
> +                                            CodeGenOpt::Level  
> OptLevel,
>                                             bool Verbose,
>                                             raw_ostream &Out) {
>   PM.add(createAlphaLLRPPass(*this));
>   PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
> }
> -bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,  
> unsigned OptLevel,
> +bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
> +                                        CodeGenOpt::Level OptLevel,
>                                         bool DumpAsm,  
> MachineCodeEmitter &MCE) {
>   PM.add(createAlphaCodeEmitterPass(*this, MCE));
>   if (DumpAsm)
> @@ -103,7 +104,8 @@
>   return false;
> }
> bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
> -                                              unsigned OptLevel,  
> bool DumpAsm,
> +                                              CodeGenOpt::Level  
> OptLevel,
> +                                              bool DumpAsm,
>                                               MachineCodeEmitter  
> &MCE) {
>   return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
> }
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Wed Apr 29  
> 18:29:43 2009
> @@ -58,14 +58,17 @@
>   static unsigned getModuleMatchQuality(const Module &M);
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> -  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
> +  virtual bool addInstSelector(PassManagerBase &PM,  
> CodeGenOpt::Level OptLevel);
> +  virtual bool addPreEmitPass(PassManagerBase &PM,  
> CodeGenOpt::Level OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM,
> +                                  CodeGenOpt::Level OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> -  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
> +  virtual bool addCodeEmitter(PassManagerBase &PM,  
> CodeGenOpt::Level OptLevel,
>                               bool DumpAsm, MachineCodeEmitter &MCE);
> -  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
> -                                    bool DumpAsm,  
> MachineCodeEmitter &MCE);
> +  virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
> +                                    CodeGenOpt::Level OptLevel,
> +                                    bool DumpAsm,
> +                                    MachineCodeEmitter &MCE);
> };
>
> } // end namespace llvm
>
> Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Wed  
> Apr 29 18:29:43 2009
> @@ -37,7 +37,8 @@
>     ///
>
>     explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
> -                             const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +                             const TargetAsmInfo *T,  
> CodeGenOpt::Level OL,
> +                             bool V)
>       : AsmPrinter(o, tm, T, OL, V) {}
>
>     virtual const char *getPassName() const {
> @@ -68,7 +69,7 @@
> ///
> FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
>                                                TargetMachine &tm,
> -                                               unsigned OptLevel,
> +                                               CodeGenOpt::Level  
> OptLevel,
>                                                bool verbose) {
>   return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,  
> verbose);
> }
>
> Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
> +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Wed Apr 29 18:29:43  
> 2009
> @@ -3587,7 +3587,7 @@
> bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>                                               raw_ostream &o,
>                                               CodeGenFileType  
> FileType,
> -                                              unsigned OptLevel) {
> +                                              CodeGenOpt::Level  
> OptLevel) {
>   if (FileType != TargetMachine::AssemblyFile) return true;
>
>   PM.add(createGCLoweringPass());
>
> Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Wed Apr 29  
> 18:29:43 2009
> @@ -28,7 +28,7 @@
>   virtual bool WantsWholeFile() const { return true; }
>   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream  
> &Out,
>                                         CodeGenFileType FileType,
> -                                        unsigned OptLevel);
> +                                        CodeGenOpt::Level OptLevel);
>
>   // This class always works, but must be requested explicitly on
>   // llc command line.
>
> Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Wed  
> Apr 29 18:29:43 2009
> @@ -49,7 +49,8 @@
>     std::set<std::string> FnStubs, GVStubs;
>   public:
>     explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                           const TargetAsmInfo *T, unsigned OL,  
> bool V) :
> +                           const TargetAsmInfo *T,  
> CodeGenOpt::Level OL,
> +                           bool V) :
>       AsmPrinter(O, TM, T, OL, V) {}
>
>     virtual const char *getPassName() const {
> @@ -288,8 +289,9 @@
>     DwarfWriter *DW;
>     MachineModuleInfo *MMI;
>   public:
> -    LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
> -                    const TargetAsmInfo *T, bool F, bool V)
> +    explicit LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
> +                             const TargetAsmInfo *T,  
> CodeGenOpt::Level F,
> +                             bool V)
>       : SPUAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
>
>     virtual const char *getPassName() const {
> @@ -615,6 +617,7 @@
> ///
> FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
>                                             SPUTargetMachine &tm,
> -                                            unsigned OptLevel, bool  
> verbose) {
> +                                            CodeGenOpt::Level  
> OptLevel,
> +                                            bool verbose) {
>   return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,  
> verbose);
> }
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPU.h Wed Apr 29 18:29:43 2009
> @@ -16,6 +16,7 @@
> #define LLVM_TARGET_IBMCELLSPU_H
>
> #include "llvm/Support/DataTypes.h"
> +#include "llvm/Target/TargetMachine.h"
>
> namespace llvm {
>   class SPUTargetMachine;
> @@ -25,7 +26,8 @@
>   FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
>   FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
>                                         SPUTargetMachine &tm,
> -                                        unsigned OptLevel, bool  
> verbose);
> +                                        CodeGenOpt::Level OptLevel,
> +                                        bool verbose);
>
>   /*--== Utility functions/predicates/etc used all over the place: -- 
> ==*/
>   //! Predicate test for a signed 10-bit value
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -81,7 +81,8 @@
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> bool
> -SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel)
> +SPUTargetMachine::addInstSelector(PassManagerBase &PM,
> +                                  CodeGenOpt::Level OptLevel)
> {
>   // Install an instruction selector.
>   PM.add(createSPUISelDag(*this));
> @@ -89,7 +90,7 @@
> }
>
> bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> -                                          unsigned OptLevel,
> +                                          CodeGenOpt::Level OptLevel,
>                                           bool Verbose,
>                                           raw_ostream &Out) {
>   PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Wed Apr 29  
> 18:29:43 2009
> @@ -83,8 +83,10 @@
>   }
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
> +  virtual bool addInstSelector(PassManagerBase &PM,
> +                               CodeGenOpt::Level OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM,
> +                                  CodeGenOpt::Level OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> };
>
>
> Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
> +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -1995,7 +1995,7 @@
> bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
>                                                 raw_ostream &o,
>                                                 CodeGenFileType  
> FileType,
> -                                                unsigned OptLevel) {
> +                                                CodeGenOpt::Level  
> OptLevel) {
>   if (FileType != TargetMachine::AssemblyFile) return true;
>   PM.add(new CppWriter(o));
>   return false;
>
> Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Wed Apr 29  
> 18:29:43 2009
> @@ -30,7 +30,7 @@
>   virtual bool WantsWholeFile() const { return true; }
>   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream  
> &Out,
>                                         CodeGenFileType FileType,
> -                                        unsigned OptLevel);
> +                                        CodeGenOpt::Level OptLevel);
>
>   // This class always works, but shouldn't be the default in most  
> cases.
>   static unsigned getModuleMatchQuality(const Module &M) { return 1; }
>
> Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Wed Apr  
> 29 18:29:43 2009
> @@ -25,7 +25,6 @@
> #include "llvm/CodeGen/DwarfWriter.h"
> #include "llvm/CodeGen/MachineFunctionPass.h"
> #include "llvm/Target/TargetAsmInfo.h"
> -#include "llvm/Target/TargetMachine.h"
> #include "llvm/Support/Mangler.h"
> #include "llvm/Support/raw_ostream.h"
> #include "llvm/ADT/Statistic.h"
> @@ -38,7 +37,8 @@
>     std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
>   public:
>     explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                            const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +                            const TargetAsmInfo *T,  
> CodeGenOpt::Level OL,
> +                            bool V)
>       : AsmPrinter(O, TM, T, OL, V) {}
>
>     virtual const char *getPassName() const {
> @@ -370,7 +370,7 @@
> ///
> FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
>                                               IA64TargetMachine &tm,
> -                                              unsigned OptLevel,
> +                                              CodeGenOpt::Level  
> OptLevel,
>                                               bool verbose) {
>   return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,  
> verbose);
> }
>
> Modified: llvm/trunk/lib/Target/IA64/IA64.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64.h (original)
> +++ llvm/trunk/lib/Target/IA64/IA64.h Wed Apr 29 18:29:43 2009
> @@ -14,6 +14,8 @@
> #ifndef TARGET_IA64_H
> #define TARGET_IA64_H
>
> +#include "llvm/Target/TargetMachine.h"
> +
> namespace llvm {
>
> class IA64TargetMachine;
> @@ -37,7 +39,8 @@
> ///
> FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
>                                         IA64TargetMachine &tm,
> -                                        unsigned OptLevel, bool  
> verbose);
> +                                        CodeGenOpt::Level OptLevel,
> +                                        bool verbose);
>
> } // End llvm namespace
>
>
> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -72,18 +72,20 @@
> // Pass Pipeline Configuration
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
> -bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,  
> unsigned OptLEvel){
> +bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,
> +                                        CodeGenOpt::Level OptLevel){
>   PM.add(createIA64DAGToDAGInstructionSelector(*this));
>   return false;
> }
>
> -bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,  
> unsigned OptLevel) {
> +bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,
> +                                       CodeGenOpt::Level OptLevel) {
>   // Make sure everything is bundled happily
>   PM.add(createIA64BundlingPass(*this));
>   return true;
> }
> bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
> -                                           unsigned OptLevel,
> +                                           CodeGenOpt::Level  
> OptLevel,
>                                            bool Verbose,
>                                            raw_ostream &Out) {
>   PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
>
> Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.h Wed Apr 29  
> 18:29:43 2009
> @@ -51,9 +51,10 @@
>   static unsigned getModuleMatchQuality(const Module &M);
>
>   // Pass Pipeline Configuration
> -  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> -  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
> +  virtual bool addInstSelector(PassManagerBase &PM,  
> CodeGenOpt::Level OptLevel);
> +  virtual bool addPreEmitPass(PassManagerBase &PM,  
> CodeGenOpt::Level OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM,
> +                                  CodeGenOpt::Level OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> };
> } // End llvm namespace
>
> Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
> +++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Wed Apr 29 18:29:43 2009
> @@ -36,7 +36,7 @@
>     virtual bool WantsWholeFile() const { return true; }
>     virtual bool addPassesToEmitWholeFile(PassManager &PM,  
> raw_ostream &Out,
>                                           CodeGenFileType FileType,
> -                                          unsigned OptLevel);
> +                                          CodeGenOpt::Level  
> OptLevel);
>
>     // This class always works, but shouldn't be the default in most  
> cases.
>     static unsigned getModuleMatchQuality(const Module &M) { return  
> 1; }
> @@ -1664,7 +1664,7 @@
>
> bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM,  
> raw_ostream &o,
>                                           CodeGenFileType FileType,
> -                                          unsigned OptLevel)
> +                                          CodeGenOpt::Level OptLevel)
> {
>   if (FileType != TargetMachine::AssemblyFile) return true;
>   MSILWriter* Writer = new MSILWriter(o);
>
> Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Wed Apr  
> 29 18:29:43 2009
> @@ -50,7 +50,8 @@
>     const MipsSubtarget *Subtarget;
>   public:
>     explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
> -                            const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +                            const TargetAsmInfo *T,  
> CodeGenOpt::Level OL,
> +                            bool V)
>       : AsmPrinter(O, TM, T, OL, V) {
>       Subtarget = &TM.getSubtarget<MipsSubtarget>();
>     }
> @@ -91,7 +92,8 @@
> /// regardless of whether the function is in SSA form.
> FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
>                                               MipsTargetMachine &tm,
> -                                              unsigned OptLevel,  
> bool verbose) {
> +                                              CodeGenOpt::Level  
> OptLevel,
> +                                              bool verbose) {
>   return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,  
> verbose);
> }
>
>
> Modified: llvm/trunk/lib/Target/Mips/Mips.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/Mips.h (original)
> +++ llvm/trunk/lib/Target/Mips/Mips.h Wed Apr 29 18:29:43 2009
> @@ -15,6 +15,8 @@
> #ifndef TARGET_MIPS_H
> #define TARGET_MIPS_H
>
> +#include "llvm/Target/TargetMachine.h"
> +
> namespace llvm {
>   class MipsTargetMachine;
>   class FunctionPass;
> @@ -25,7 +27,8 @@
>   FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
>   FunctionPass *createMipsCodePrinterPass(raw_ostream &OS,
>                                           MipsTargetMachine &TM,
> -                                          unsigned OptLevel, bool  
> Verbose);
> +                                          CodeGenOpt::Level OptLevel,
> +                                          bool Verbose);
> } // end namespace llvm;
>
> // Defines symbolic names for Mips registers.  This defines a  
> mapping from
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -105,7 +105,7 @@
> // Install an instruction selector pass using
> // the ISelDag to gen Mips code.
> bool MipsTargetMachine::
> -addInstSelector(PassManagerBase &PM, unsigned OptLevel)
> +addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
> {
>   PM.add(createMipsISelDag(*this));
>   return false;
> @@ -115,7 +115,7 @@
> // machine code is emitted. return true if -print-machineinstrs should
> // print out the code after the passes.
> bool MipsTargetMachine::
> -addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
> +addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
> {
>   PM.add(createMipsDelaySlotFillerPass(*this));
>   return true;
> @@ -124,7 +124,7 @@
> // Implements the AssemblyEmitter for the target. Must return
> // true if AssemblyEmitter is supported
> bool MipsTargetMachine::
> -addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
> +addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
>                    bool Verbose, raw_ostream &Out)
> {
>   // Output assembly language.
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Wed Apr 29  
> 18:29:43 2009
> @@ -57,9 +57,12 @@
>     static unsigned getModuleMatchQuality(const Module &M);
>
>     // Pass Pipeline Configuration
> -    virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> -    virtual bool addPreEmitPass(PassManagerBase &PM, unsigned  
> OptLevel);
> -    virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
> +    virtual bool addInstSelector(PassManagerBase &PM,
> +                                 CodeGenOpt::Level OptLevel);
> +    virtual bool addPreEmitPass(PassManagerBase &PM,
> +                                CodeGenOpt::Level OptLevel);
> +    virtual bool addAssemblyEmitter(PassManagerBase &PM,
> +                                    CodeGenOpt::Level OptLevel,
>                                     bool Verbose, raw_ostream &Out);
>   };
>
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16.h Wed Apr 29 18:29:43 2009
> @@ -15,6 +15,7 @@
> #ifndef LLVM_TARGET_PIC16_H
> #define LLVM_TARGET_PIC16_H
>
> +#include "llvm/Target/TargetMachine.h"
> #include <iosfwd>
> #include <cassert>
>
> @@ -75,7 +76,8 @@
>   FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
>   FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
>                                            PIC16TargetMachine &TM,
> -                                           unsigned OptLevel, bool  
> Verbose);
> +                                           CodeGenOpt::Level  
> OptLevel,
> +                                           bool Verbose);
> } // end namespace llvm;
>
> // Defines symbolic names for PIC16 registers.  This defines a  
> mapping from
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -161,7 +161,7 @@
> ///
> FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
>                                                PIC16TargetMachine &tm,
> -                                               unsigned OptLevel,
> +                                               CodeGenOpt::Level  
> OptLevel,
>                                                bool verbose) {
>   return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel,  
> verbose);
> }
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.h Wed Apr 29  
> 18:29:43 2009
> @@ -25,7 +25,8 @@
> namespace llvm {
>   struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
>     explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
> -                             const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +                             const TargetAsmInfo *T,  
> CodeGenOpt::Level OL,
> +                             bool V)
>       : AsmPrinter(O, TM, T, OL, V) {
>       CurBank = "";
>       FunctionLabelBegin = '@';
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Wed Apr 29  
> 18:29:43 2009
> @@ -56,15 +56,15 @@
> }
>
> bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
> -                                         unsigned OptLevel) {
> +                                         CodeGenOpt::Level  
> OptLevel) {
>   // Install an instruction selector.
>   PM.add(createPIC16ISelDag(*this));
>   return false;
> }
>
> bool PIC16TargetMachine::
> -addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool  
> Verbose,
> -                   raw_ostream &Out) {
> +addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
> +                   bool Verbose, raw_ostream &Out) {
>   // Output assembly language.
>   PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
>   return false;
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.h Wed Apr 29  
> 18:29:43 2009
> @@ -57,8 +57,10 @@
>     return const_cast<PIC16TargetLowering*>(&TLInfo);
>   }
>
> -  virtual bool addInstSelector(PassManagerBase &PM, unsigned  
> OptLevel);
> -  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned  
> OptLevel,
> +  virtual bool addInstSelector(PassManagerBase &PM,
> +                               CodeGenOpt::Level OptLevel);
> +  virtual bool addAssemblyEmitter(PassManagerBase &PM,
> +                                  CodeGenOpt::Level OptLevel,
>                                   bool Verbose, raw_ostream &Out);
> }; // PIC16TargetMachine.
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=70440&r1=70439&r2=70440&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp  
> (original)
> +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Wed  
> Apr 29 18:29:43 2009
> @@ -55,7 +55,8 @@
>     const PPCSubtarget &Subtarget;
>   public:
>     explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
> -                           const TargetAsmInfo *T, unsigned OL,  
> bool V)
> +                           const TargetAsmInfo *T,  
> CodeGenOpt::Level OL,
> +                           bool V)
>       : AsmPrinter(O, TM, T, OL, V),
>         Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
>
> @@ -298,7 +299,8 @@
>     MachineModuleInfo *MMI;
>   public:
>     explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
> -                                const TargetAsmInfo *T, un