From eli.friedman at gmail.com Mon Jun 1 04:14:55 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 01 Jun 2009 09:14:55 -0000 Subject: [llvm-commits] [llvm] r72688 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2009-06-01-BitcastIntPadding.ll Message-ID: <200906010914.n519EvY6005825@zion.cs.uiuc.edu> Author: efriedma Date: Mon Jun 1 04:14:32 2009 New Revision: 72688 URL: http://llvm.org/viewvc/llvm-project?rev=72688&view=rev Log: PR4286: Make RewriteLoadUserOfWholeAlloca and RewriteStoreUserOfWholeAlloca deal with tail padding because isSafeUseOfBitCastedAllocation expects them to. Otherwise, we crash trying to erase the bitcast. Added: llvm/trunk/test/Transforms/ScalarRepl/2009-06-01-BitcastIntPadding.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=72688&r1=72687&r2=72688&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Jun 1 04:14:32 2009 @@ -903,11 +903,13 @@ // If this isn't a store of an integer to the whole alloca, it may be a store // to the first element. Just ignore the store in this case and normal SROA - // will handle it. We don't handle types here that have tail padding, like - // an alloca of type {i1}. + // will handle it. if (!isa(SrcVal->getType()) || - TD->getTypeSizeInBits(SrcVal->getType()) != AllocaSizeBits) + TD->getTypeAllocSizeInBits(SrcVal->getType()) != AllocaSizeBits) return; + // Handle tail padding by extending the operand + if (TD->getTypeSizeInBits(SrcVal->getType()) != AllocaSizeBits) + SrcVal = new ZExtInst(SrcVal, IntegerType::get(AllocaSizeBits), "", SI); DOUT << "PROMOTING STORE TO WHOLE ALLOCA: " << *AI << *SI; @@ -1016,10 +1018,9 @@ // If this isn't a load of the whole alloca to an integer, it may be a load // of the first element. Just ignore the load in this case and normal SROA - // will handle it. We don't handle types here that have tail padding, like - // an alloca of type {i1}. + // will handle it. if (!isa(LI->getType()) || - TD->getTypeSizeInBits(LI->getType()) != AllocaSizeBits) + TD->getTypeAllocSizeInBits(LI->getType()) != AllocaSizeBits) return; DOUT << "PROMOTING LOAD OF WHOLE ALLOCA: " << *AI << *LI; @@ -1035,7 +1036,7 @@ ArrayEltBitOffset = TD->getTypeAllocSizeInBits(ArrayEltTy); } - Value *ResultVal = Constant::getNullValue(LI->getType()); + Value *ResultVal = Constant::getNullValue(IntegerType::get(AllocaSizeBits)); for (unsigned i = 0, e = NewElts.size(); i != e; ++i) { // Load the value from the alloca. If the NewElt is an aggregate, cast @@ -1082,7 +1083,11 @@ ResultVal = BinaryOperator::CreateOr(SrcField, ResultVal, "", LI); } - + + // Handle tail padding by truncating the result + if (TD->getTypeSizeInBits(LI->getType()) != AllocaSizeBits) + ResultVal = new TruncInst(ResultVal, LI->getType(), "", LI); + LI->replaceAllUsesWith(ResultVal); LI->eraseFromParent(); } Added: llvm/trunk/test/Transforms/ScalarRepl/2009-06-01-BitcastIntPadding.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/2009-06-01-BitcastIntPadding.ll?rev=72688&view=auto ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/2009-06-01-BitcastIntPadding.ll (added) +++ llvm/trunk/test/Transforms/ScalarRepl/2009-06-01-BitcastIntPadding.ll Mon Jun 1 04:14:32 2009 @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | opt -scalarrepl +; PR4286 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "x86_64-undermydesk-freebsd8.0" + %struct.singlebool = type <{ i8 }> + +define zeroext i8 @doit() nounwind { +entry: + %a = alloca %struct.singlebool, align 1 ; <%struct.singlebool*> [#uses=2] + %storetmp.i = bitcast %struct.singlebool* %a to i1* ; [#uses=1] + store i1 true, i1* %storetmp.i + %tmp = getelementptr %struct.singlebool* %a, i64 0, i32 0 ; [#uses=1] + %tmp1 = load i8* %tmp ; [#uses=1] + ret i8 %tmp1 +} + From baldrick at free.fr Mon Jun 1 08:38:25 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 01 Jun 2009 15:38:25 +0200 Subject: [llvm-commits] [llvm] r72688 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2009-06-01-BitcastIntPadding.ll In-Reply-To: <200906010914.n519EvY6005825@zion.cs.uiuc.edu> References: <200906010914.n519EvY6005825@zion.cs.uiuc.edu> Message-ID: <4A23D9D1.20200@free.fr> Hi Eli, > + %a = alloca %struct.singlebool, align 1 ; <%struct.singlebool*> [#uses=2] > + %storetmp.i = bitcast %struct.singlebool* %a to i1* ; [#uses=1] > + store i1 true, i1* %storetmp.i > + %tmp = getelementptr %struct.singlebool* %a, i64 0, i32 0 ; [#uses=1] > + %tmp1 = load i8* %tmp ; [#uses=1] > + ret i8 %tmp1 what does this return? It's unspecified as to what is stored in the extra bits when you do an i1 store (in fact it is zero, but we may want to keep some freedom here). Ciao, Duncan. From dalej at apple.com Mon Jun 1 13:05:03 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 1 Jun 2009 11:05:03 -0700 Subject: [llvm-commits] [llvm] r72606 - in /llvm/trunk: include/llvm/ADT/APFloat.h lib/Support/APFloat.cpp In-Reply-To: <200905300349.n4U3njD1030452@zion.cs.uiuc.edu> References: <200905300349.n4U3njD1030452@zion.cs.uiuc.edu> Message-ID: On May 29, 2009, at 8:49 PMPDT, Mike Stump wrote: > Author: mrs > Date: Fri May 29 22:49:43 2009 > New Revision: 72606 > > URL: http://llvm.org/viewvc/llvm-project?rev=72606&view=rev > Log: > Add support for letting the client choose different flavors of > NaNs. Testcase to be > added in clang. What problem are you trying to solve with this? I'm skeptical this is a good idea. > Modified: > llvm/trunk/include/llvm/ADT/APFloat.h > llvm/trunk/lib/Support/APFloat.cpp > > Modified: llvm/trunk/include/llvm/ADT/APFloat.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APFloat.h?rev=72606&r1=72605&r2=72606&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/ADT/APFloat.h (original) > +++ llvm/trunk/include/llvm/ADT/APFloat.h Fri May 29 22:49:43 2009 > @@ -174,7 +174,7 @@ > // Constructors. > APFloat(const fltSemantics &, const char *); > APFloat(const fltSemantics &, integerPart); > - APFloat(const fltSemantics &, fltCategory, bool negative); > + APFloat(const fltSemantics &, fltCategory, bool negative, > unsigned type=0); > explicit APFloat(double d); > explicit APFloat(float f); > explicit APFloat(const APInt &, bool isIEEE = false); > @@ -188,8 +188,9 @@ > static APFloat getInf(const fltSemantics &Sem, bool Negative = > false) { > return APFloat(Sem, fcInfinity, Negative); > } > - static APFloat getNaN(const fltSemantics &Sem, bool Negative = > false) { > - return APFloat(Sem, fcNaN, Negative); > + static APFloat getNaN(const fltSemantics &Sem, bool Negative = > false, > + long unsigned type=0) { > + return APFloat(Sem, fcNaN, Negative, type); > } > > /// Profile - Used to insert APFloat objects, or objects that > contain > @@ -296,7 +297,7 @@ > opStatus modSpecials(const APFloat &); > > /* Miscellany. */ > - void makeNaN(void); > + void makeNaN(unsigned = 0); > opStatus normalize(roundingMode, lostFraction); > opStatus addOrSubtract(const APFloat &, roundingMode, bool > subtract); > cmpResult compareAbsoluteValue(const APFloat &) const; > > Modified: llvm/trunk/lib/Support/APFloat.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/APFloat.cpp?rev=72606&r1=72605&r2=72606&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Support/APFloat.cpp (original) > +++ llvm/trunk/lib/Support/APFloat.cpp Fri May 29 22:49:43 2009 > @@ -598,12 +598,18 @@ > > /* Make this number a NaN, with an arbitrary but deterministic value > for the significand. If double or longer, this is a signalling > NaN, > - which may not be ideal. */ > + which may not be ideal. If float, this is QNaN(0). */ > void > -APFloat::makeNaN(void) > +APFloat::makeNaN(unsigned type) > { > category = fcNaN; > - APInt::tcSet(significandParts(), ~0U, partCount()); > + // FIXME: Add double and long double support for QNaN(0). > + if (semantics->precision == 24 && semantics->maxExponent == 127) { > + type |= 0x7fc00000U; > + type &= ~0x80000000U; > + } else > + type = ~0U; > + APInt::tcSet(significandParts(), type, partCount()); > } > > APFloat & > @@ -662,16 +668,16 @@ > } > > APFloat::APFloat(const fltSemantics &ourSemantics, > - fltCategory ourCategory, bool negative) > + fltCategory ourCategory, bool negative, unsigned > type) > { > assertArithmeticOK(ourSemantics); > initialize(&ourSemantics); > category = ourCategory; > sign = negative; > - if(category == fcNormal) > + if (category == fcNormal) > category = fcZero; > else if (ourCategory == fcNaN) > - makeNaN(); > + makeNaN(type); > } > > APFloat::APFloat(const fltSemantics &ourSemantics, const char *text) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From mrs at apple.com Mon Jun 1 13:11:53 2009 From: mrs at apple.com (Mike Stump) Date: Mon, 1 Jun 2009 11:11:53 -0700 Subject: [llvm-commits] [llvm] r72606 - in /llvm/trunk: include/llvm/ADT/APFloat.h lib/Support/APFloat.cpp In-Reply-To: References: <200905300349.n4U3njD1030452@zion.cs.uiuc.edu> Message-ID: On Jun 1, 2009, at 11:05 AM, Dale Johannesen wrote: > On May 29, 2009, at 8:49 PMPDT, Mike Stump wrote: > What problem are you trying to solve with this? I'm skeptical this is > a good idea. You gotta love standards: http://gcc.gnu.org/onlinedocs/gcc-4.4.0/gcc/Other-Builtins.html#index-g_t_005f_005fbuiltin_005fnan-2885 so many fun and interesting bits. From edwintorok at gmail.com Mon Jun 1 13:20:55 2009 From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=) Date: Mon, 01 Jun 2009 21:20:55 +0300 Subject: [llvm-commits] [PATCH] ANSI colors for clang! In-Reply-To: <4A22DE44.9010406@gmail.com> References: <4A211D99.1050104@gmail.com> <6570BAAF-67FF-4033-B496-1A078CC65B61@apple.com> <4A22DE44.9010406@gmail.com> Message-ID: <4A241C07.20309@gmail.com> On 2009-05-31 22:45, T?r?k Edwin wrote: > On 2009-05-31 22:13, Chris Lattner wrote: > >> +raw_ostream &raw_fd_ostream::changeColor(enum Colors colors, bool bold, >> + bool bg) >> +{ >> + if (!oldColors) >> + oldColors = sys::Process::SaveCurrentColor(); >> >> Does raw_fd_ostream really need a oldColors member? >> > > For win32 yes. On Unix its an unused field. > oldColors is gone in new version. > >> Is this to push/ >> pop the current color? If so, could the state be saved outside the >> stream itself? Maybe an RAII object that installs a new color and >> saves the old one... restoring it when destroyed would be better? >> That way raw_ostream could just have "give me your current color" and >> "change color" interfaces, which would be very simple and nice. >> >> > > > I save the terminal default colors in a static constructor in win32/process.inc now, so oldColors and SaveCurrentColors is not needed. >> A lot of the complexity of the patch looks like it has to do with >> Windows support. Please find someone with a real VC++ build to verify >> that it actually works :) >> I've tested it myself on VC++2k8 Express, by generating a .sln using cmake-gui (Express edition didn't like the .sln in win32/, but worked fine with the one from cmake). Apart from a compilation failure in ilist.h (solved by the attached patch) everything went smoothly, and my (blindly) written color support for win32 consoles actually worked the first time I tried: it printed an error that it can't find string.h in color! >> Thanks a lot for tackling this Edwin, it looks very useful! >> Can I commit the patch(es)? Best regards, --Edwin -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm_win32_ilist.patch Type: text/x-diff Size: 1211 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090601/afbd11dd/attachment.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm.patch Type: text/x-diff Size: 9313 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090601/afbd11dd/attachment-0001.bin From dalej at apple.com Mon Jun 1 13:31:37 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 1 Jun 2009 11:31:37 -0700 Subject: [llvm-commits] [llvm] r72606 - in /llvm/trunk: include/llvm/ADT/APFloat.h lib/Support/APFloat.cpp In-Reply-To: References: <200905300349.n4U3njD1030452@zion.cs.uiuc.edu> Message-ID: <13AC3569-F9D4-4B02-9293-3E3F91D35496@apple.com> On Jun 1, 2009, at 11:11 AMPDT, Mike Stump wrote: > On Jun 1, 2009, at 11:05 AM, Dale Johannesen wrote: >> On May 29, 2009, at 8:49 PMPDT, Mike Stump wrote: >> What problem are you trying to solve with this? I'm skeptical this >> is >> a good idea. > > You gotta love standards: > > http://gcc.gnu.org/onlinedocs/gcc-4.4.0/gcc/Other-Builtins.html#index-g_t_005f_005fbuiltin_005fnan-2885 > > so many fun and interesting bits. Apparently you're trying to support the builtin_nan functions. Those allow the user to specify only the significand. How exactly does this relate to your "type" operand (which obviously has nothing to do with types, whatever it might be)? Is the caller supposed to do the truncation to the significand size, or are you expecting APFloat to do this? Please document better. I'm not sure modifying makeNaN is a good way to do this; that was intended for cases where the caller doesn't know, or care, what the exact representation might be, i.e. the callee is supposed to choose. That's not the same thing as having a default argument; that is still the caller choosing. The end result is the same, though, so this is probably OK in principle. From asl at math.spbu.ru Mon Jun 1 14:03:18 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 01 Jun 2009 19:03:18 -0000 Subject: [llvm-commits] [llvm] r72696 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Message-ID: <200906011903.n51J3IXO029834@zion.cs.uiuc.edu> Author: asl Date: Mon Jun 1 14:03:17 2009 New Revision: 72696 URL: http://llvm.org/viewvc/llvm-project?rev=72696&view=rev Log: Do not emit "generic" CPU string. This fixes PR4291. Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=72696&r1=72695&r2=72696&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Mon Jun 1 14:03:17 2009 @@ -820,7 +820,9 @@ // Emit ARM Build Attributes if (Subtarget->isTargetELF()) { // CPU Type - O << "\t.cpu " << Subtarget->getCPUString() << '\n'; + std::string CPUString = Subtarget->getCPUString(); + if (CPUString != "generic") + O << "\t.cpu " << CPUString << '\n'; // FIXME: Emit FPU type if (Subtarget->hasVFP2()) From bruno.cardoso at gmail.com Mon Jun 1 14:57:38 2009 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 01 Jun 2009 19:57:38 -0000 Subject: [llvm-commits] [llvm] r72697 - in /llvm/trunk/lib: ExecutionEngine/JIT/JIT.h Target/ARM/ARM.h Target/ARM/ARMCodeEmitter.cpp Target/Alpha/AlphaCodeEmitter.cpp Target/PowerPC/PPCCodeEmitter.cpp Target/PowerPC/PPCTargetMachine.cpp Target/X86/X86.h Target/X86/X86CodeEmitter.cpp Target/X86/X86TargetMachine.cpp Message-ID: <200906011957.n51Jvc9n031503@zion.cs.uiuc.edu> Author: bruno Date: Mon Jun 1 14:57:37 2009 New Revision: 72697 URL: http://llvm.org/viewvc/llvm-project?rev=72697&view=rev Log: Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.h llvm/trunk/lib/Target/ARM/ARM.h llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp llvm/trunk/lib/Target/X86/X86.h llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.h?rev=72697&r1=72696&r2=72697&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.h (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.h Mon Jun 1 14:57:37 2009 @@ -51,7 +51,7 @@ class JIT : public ExecutionEngine { TargetMachine &TM; // The current target we are compiling to TargetJITInfo &TJI; // The JITInfo for the target we are compiling to - JITCodeEmitter *JCE; // JCE object + JITCodeEmitter *JCE; // JCE object JITState *jitstate; Modified: llvm/trunk/lib/Target/ARM/ARM.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=72697&r1=72696&r2=72697&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.h (original) +++ llvm/trunk/lib/Target/ARM/ARM.h Mon Jun 1 14:57:37 2009 @@ -98,15 +98,10 @@ FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM, MachineCodeEmitter &MCE); -FunctionPass *createARMCodeEmitterPass( - ARMTargetMachine &TM, MachineCodeEmitter &MCE); -/* -template< class machineCodeEmitter> -FunctionPass *createARMCodeEmitterPass( - ARMTargetMachine &TM, machineCodeEmitter &MCE); -*/ -FunctionPass *createARMJITCodeEmitterPass( - ARMTargetMachine &TM, JITCodeEmitter &JCE); +FunctionPass *createARMCodeEmitterPass( ARMTargetMachine &TM, + MachineCodeEmitter &MCE); +FunctionPass *createARMJITCodeEmitterPass( ARMTargetMachine &TM, + JITCodeEmitter &JCE); FunctionPass *createARMLoadStoreOptimizationPass(); FunctionPass *createARMConstantIslandPass(); Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=72697&r1=72696&r2=72697&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Jun 1 14:57:37 2009 @@ -45,34 +45,31 @@ class ARMCodeEmitter { public: - /// getBinaryCodeForInstr - This function, generated by the /// CodeEmitterGenerator using TableGen, produces the binary encoding for /// machine instructions. - unsigned getBinaryCodeForInstr(const MachineInstr &MI); }; - template< class machineCodeEmitter> - class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass, - public ARMCodeEmitter - { + template + class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass, + public ARMCodeEmitter { ARMJITInfo *JTI; const ARMInstrInfo *II; const TargetData *TD; TargetMachine &TM; - machineCodeEmitter &MCE; + CodeEmitter &MCE; const std::vector *MCPEs; const std::vector *MJTEs; bool IsPIC; public: static char ID; - explicit Emitter(TargetMachine &tm, machineCodeEmitter &mce) + explicit Emitter(TargetMachine &tm, CodeEmitter &mce) : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm), MCE(mce), MCPEs(0), MJTEs(0), IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} - Emitter(TargetMachine &tm, machineCodeEmitter &mce, + Emitter(TargetMachine &tm, CodeEmitter &mce, const ARMInstrInfo &ii, const TargetData &td) : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm), MCE(mce), MCPEs(0), MJTEs(0), @@ -170,30 +167,28 @@ void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, intptr_t JTBase = 0); }; - template - char Emitter::ID = 0; + template + char Emitter::ID = 0; } /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code /// to the specified MCE object. namespace llvm { - -FunctionPass *createARMCodeEmitterPass( - ARMTargetMachine &TM, MachineCodeEmitter &MCE) -{ + +FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM, + MachineCodeEmitter &MCE) { return new Emitter(TM, MCE); } -FunctionPass *createARMJITCodeEmitterPass( - ARMTargetMachine &TM, JITCodeEmitter &JCE) -{ +FunctionPass *createARMJITCodeEmitterPass(ARMTargetMachine &TM, + JITCodeEmitter &JCE) { return new Emitter(TM, JCE); } } // end namespace llvm -template< class machineCodeEmitter> -bool Emitter< machineCodeEmitter>::runOnMachineFunction(MachineFunction &MF) { +template +bool Emitter::runOnMachineFunction(MachineFunction &MF) { assert((MF.getTarget().getRelocationModel() != Reloc::Default || MF.getTarget().getRelocationModel() != Reloc::Static) && "JIT relocation model must be set to static or default!"); @@ -222,8 +217,8 @@ /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. /// -template< class machineCodeEmitter> -unsigned Emitter< machineCodeEmitter>::getShiftOp(unsigned Imm) const { +template +unsigned Emitter::getShiftOp(unsigned Imm) const { switch (ARM_AM::getAM2ShiftOpc(Imm)) { default: assert(0 && "Unknown shift opc!"); case ARM_AM::asr: return 2; @@ -237,9 +232,9 @@ /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. -template< class machineCodeEmitter> -unsigned Emitter< machineCodeEmitter>::getMachineOpValue(const MachineInstr &MI, - const MachineOperand &MO) { +template +unsigned Emitter::getMachineOpValue(const MachineInstr &MI, + const MachineOperand &MO) { if (MO.isReg()) return ARMRegisterInfo::getRegisterNumbering(MO.getReg()); else if (MO.isImm()) @@ -267,18 +262,19 @@ /// emitGlobalAddress - Emit the specified address to the code stream. /// -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, - bool NeedStub, intptr_t ACPV) { - MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), - Reloc, GV, ACPV, NeedStub)); +template +void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, + bool NeedStub, intptr_t ACPV) { + MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, + GV, ACPV, NeedStub)); } /// emitExternalSymbolAddress - Arrange for the address of an external symbol to /// be emitted to the current location in the function, and allow it to be PC /// relative. -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitExternalSymbolAddress(const char *ES, unsigned Reloc) { +template +void Emitter::emitExternalSymbolAddress(const char *ES, + unsigned Reloc) { MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), Reloc, ES)); } @@ -286,8 +282,9 @@ /// emitConstPoolAddress - Arrange for the address of an constant pool /// to be emitted to the current location in the function, and allow it to be PC /// relative. -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc) { +template +void Emitter::emitConstPoolAddress(unsigned CPI, + unsigned Reloc) { // Tell JIT emitter we'll resolve the address. MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), Reloc, CPI, 0, true)); @@ -296,22 +293,23 @@ /// emitJumpTableAddress - Arrange for the address of a jump table to /// be emitted to the current location in the function, and allow it to be PC /// relative. -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) { +template +void Emitter::emitJumpTableAddress(unsigned JTIndex, + unsigned Reloc) { MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), Reloc, JTIndex, 0, true)); } /// emitMachineBasicBlock - Emit the specified address basic block. -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB, - unsigned Reloc, intptr_t JTBase) { +template +void Emitter::emitMachineBasicBlock(MachineBasicBlock *BB, + unsigned Reloc, intptr_t JTBase) { MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), Reloc, BB, JTBase)); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitWordLE(unsigned Binary) { +template +void Emitter::emitWordLE(unsigned Binary) { #ifndef NDEBUG DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0') << Binary << std::dec << "\n"; @@ -319,8 +317,8 @@ MCE.emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitDWordLE(uint64_t Binary) { +template +void Emitter::emitDWordLE(uint64_t Binary) { #ifndef NDEBUG DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0') << (unsigned)Binary << std::dec << "\n"; @@ -330,8 +328,8 @@ MCE.emitDWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitInstruction(const MachineInstr &MI) { +template +void Emitter::emitInstruction(const MachineInstr &MI) { DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI; NumEmitted++; // Keep track of the # of mi's emitted @@ -397,8 +395,8 @@ } } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) { +template +void Emitter::emitConstPoolInstruction(const MachineInstr &MI) { unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; @@ -465,8 +463,8 @@ } } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) { +template +void Emitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { const MachineOperand &MO0 = MI.getOperand(0); const MachineOperand &MO1 = MI.getOperand(1); assert(MO1.isImm() && "Not a valid so_imm value!"); @@ -507,8 +505,8 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) { +template +void Emitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { // It's basically add r, pc, (LJTI - $+8) const TargetInstrDesc &TID = MI.getDesc(); @@ -536,8 +534,8 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) { +template +void Emitter::emitPseudoMoveInstruction(const MachineInstr &MI) { unsigned Opcode = MI.getDesc().Opcode; // Part of binary is determined by TableGn. @@ -576,15 +574,15 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::addPCLabel(unsigned LabelID) { +template +void Emitter::addPCLabel(unsigned LabelID) { DOUT << " ** LPC" << LabelID << " @ " << (void*)MCE.getCurrentPCValue() << '\n'; JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) { +template +void Emitter::emitPseudoInstruction(const MachineInstr &MI) { unsigned Opcode = MI.getDesc().Opcode; switch (Opcode) { default: @@ -653,8 +651,9 @@ } } -template< class machineCodeEmitter> -unsigned Emitter< machineCodeEmitter>::getMachineSoRegOpValue(const MachineInstr &MI, +template +unsigned Emitter::getMachineSoRegOpValue( + const MachineInstr &MI, const TargetInstrDesc &TID, const MachineOperand &MO, unsigned OpIdx) { @@ -712,8 +711,8 @@ return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; } -template< class machineCodeEmitter> -unsigned Emitter< machineCodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) { +template +unsigned Emitter::getMachineSoImmOpValue(unsigned SoImm) { // Encode rotate_imm. unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1) << ARMII::SoRotImmShift; @@ -723,9 +722,9 @@ return Binary; } -template< class machineCodeEmitter> -unsigned Emitter< machineCodeEmitter>::getAddrModeSBit(const MachineInstr &MI, - const TargetInstrDesc &TID) const { +template +unsigned Emitter::getAddrModeSBit(const MachineInstr &MI, + const TargetInstrDesc &TID) const { for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){ const MachineOperand &MO = MI.getOperand(i-1); if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) @@ -734,8 +733,9 @@ return 0; } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitDataProcessingInstruction(const MachineInstr &MI, +template +void Emitter::emitDataProcessingInstruction( + const MachineInstr &MI, unsigned ImplicitRd, unsigned ImplicitRn) { const TargetInstrDesc &TID = MI.getDesc(); @@ -798,8 +798,9 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitLoadStoreInstruction(const MachineInstr &MI, +template +void Emitter::emitLoadStoreInstruction( + const MachineInstr &MI, unsigned ImplicitRd, unsigned ImplicitRn) { const TargetInstrDesc &TID = MI.getDesc(); @@ -873,9 +874,9 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI, - unsigned ImplicitRn) { +template +void Emitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, + unsigned ImplicitRn) { const TargetInstrDesc &TID = MI.getDesc(); unsigned Form = TID.TSFlags & ARMII::FormMask; bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; @@ -957,8 +958,9 @@ return Binary; } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { +template +void Emitter::emitLoadStoreMultipleInstruction( + const MachineInstr &MI) { // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -990,8 +992,8 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) { +template +void Emitter::emitMulFrmInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Part of binary is determined by TableGn. @@ -1028,8 +1030,8 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitExtendInstruction(const MachineInstr &MI) { +template +void Emitter::emitExtendInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Part of binary is determined by TableGn. @@ -1066,8 +1068,8 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) { +template +void Emitter::emitMiscArithInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Part of binary is determined by TableGn. @@ -1105,8 +1107,8 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitBranchInstruction(const MachineInstr &MI) { +template +void Emitter::emitBranchInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); if (TID.Opcode == ARM::TPsoft) @@ -1124,8 +1126,8 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitInlineJumpTable(unsigned JTIndex) { +template +void Emitter::emitInlineJumpTable(unsigned JTIndex) { // Remember the base address of the inline jump table. uintptr_t JTBase = MCE.getCurrentPCValue(); JTI->addJumpTableBaseAddr(JTIndex, JTBase); @@ -1144,8 +1146,8 @@ } } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) { +template +void Emitter::emitMiscBranchInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Handle jump tables. @@ -1225,8 +1227,8 @@ return Binary; } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) { +template +void Emitter::emitVFPArithInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Part of binary is determined by TableGn. @@ -1265,8 +1267,9 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitVFPConversionInstruction(const MachineInstr &MI) { +template +void Emitter::emitVFPConversionInstruction( + const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); unsigned Form = TID.TSFlags & ARMII::FormMask; @@ -1322,8 +1325,8 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) { +template +void Emitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1357,8 +1360,9 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { +template +void Emitter::emitVFPLoadStoreMultipleInstruction( + const MachineInstr &MI) { // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1392,8 +1396,8 @@ emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMiscInstruction(const MachineInstr &MI) { +template +void Emitter::emitMiscInstruction(const MachineInstr &MI) { // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); Modified: llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp?rev=72697&r1=72696&r2=72697&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp Mon Jun 1 14:57:37 2009 @@ -32,7 +32,7 @@ class AlphaCodeEmitter { MachineCodeEmitter &MCE; public: - AlphaCodeEmitter( MachineCodeEmitter &mce) : MCE(mce) {} + AlphaCodeEmitter(MachineCodeEmitter &mce) : MCE(mce) {} /// getBinaryCodeForInstr - This function, generated by the /// CodeEmitterGenerator using TableGen, produces the binary encoding for @@ -42,25 +42,25 @@ /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr - unsigned getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO); + unsigned getMachineOpValue(const MachineInstr &MI, + const MachineOperand &MO); }; - template + template class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass, public AlphaCodeEmitter { const AlphaInstrInfo *II; - TargetMachine &TM; - machineCodeEmitter &MCE; + TargetMachine &TM; + CodeEmitter &MCE; public: static char ID; - explicit Emitter(TargetMachine &tm, machineCodeEmitter &mce) - : MachineFunctionPass(&ID), AlphaCodeEmitter( mce), + explicit Emitter(TargetMachine &tm, CodeEmitter &mce) + : MachineFunctionPass(&ID), AlphaCodeEmitter(mce), II(0), TM(tm), MCE(mce) {} - Emitter(TargetMachine &tm, machineCodeEmitter &mce, - const AlphaInstrInfo& ii) - : MachineFunctionPass(&ID), AlphaCodeEmitter( mce), + Emitter(TargetMachine &tm, CodeEmitter &mce, const AlphaInstrInfo& ii) + : MachineFunctionPass(&ID), AlphaCodeEmitter(mce), II(&ii), TM(tm), MCE(mce) {} bool runOnMachineFunction(MachineFunction &MF); @@ -75,25 +75,25 @@ void emitBasicBlock(MachineBasicBlock &MBB); }; - template - char Emitter::ID = 0; + template + char Emitter::ID = 0; } -/// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha code -/// to the specified MCE object. +/// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha +/// code to the specified MCE object. -FunctionPass *llvm::createAlphaCodeEmitterPass( AlphaTargetMachine &TM, +FunctionPass *llvm::createAlphaCodeEmitterPass(AlphaTargetMachine &TM, MachineCodeEmitter &MCE) { return new Emitter(TM, MCE); } -FunctionPass *llvm::createAlphaJITCodeEmitterPass( AlphaTargetMachine &TM, - JITCodeEmitter &JCE) { +FunctionPass *llvm::createAlphaJITCodeEmitterPass(AlphaTargetMachine &TM, + JITCodeEmitter &JCE) { return new Emitter(TM, JCE); } -template -bool Emitter::runOnMachineFunction(MachineFunction &MF) { +template +bool Emitter::runOnMachineFunction(MachineFunction &MF) { II = ((AlphaTargetMachine&)MF.getTarget()).getInstrInfo(); do { @@ -105,8 +105,8 @@ return false; } -template -void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { +template +void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { MCE.StartMachineBasicBlock(&MBB); for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) { @@ -165,7 +165,7 @@ } unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, - const MachineOperand &MO) { + const MachineOperand &MO) { unsigned rv = 0; // Return value; defaults to 0 for unhandled cases // or things that get fixed up later by the JIT. Modified: llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=72697&r1=72696&r2=72697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp Mon Jun 1 14:57:37 2009 @@ -23,7 +23,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/Support/Debug.h" +#include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include "llvm/Target/TargetOptions.h" using namespace llvm; @@ -33,8 +33,8 @@ TargetMachine &TM; MachineCodeEmitter &MCE; public: - PPCCodeEmitter( TargetMachine &tm, MachineCodeEmitter &mce) : - TM( tm), MCE( mce) {} + PPCCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce): + TM(tm), MCE(mce) {} /// getBinaryCodeForInstr - This function, generated by the /// CodeEmitterGenerator using TableGen, produces the binary encoding for @@ -44,7 +44,8 @@ /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr - unsigned getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO); + unsigned getMachineOpValue(const MachineInstr &MI, + const MachineOperand &MO); /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record /// its address in the function into this pointer. @@ -52,12 +53,12 @@ void *MovePCtoLROffset; }; - template + template class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass, public PPCCodeEmitter { TargetMachine &TM; - machineCodeEmitter &MCE; + CodeEmitter &MCE; void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); @@ -66,8 +67,8 @@ public: static char ID; - Emitter(TargetMachine &tm, machineCodeEmitter &mce) - : MachineFunctionPass(&ID), PPCCodeEmitter( tm, mce), TM(tm), MCE(mce) {} + Emitter(TargetMachine &tm, CodeEmitter &mce) + : MachineFunctionPass(&ID), PPCCodeEmitter(tm, mce), TM(tm), MCE(mce) {} const char *getPassName() const { return "PowerPC Machine Code Emitter"; } @@ -84,24 +85,24 @@ unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; } }; - template - char Emitter::ID = 0; + template + char Emitter::ID = 0; } /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code /// to the specified MCE object. FunctionPass *llvm::createPPCCodeEmitterPass(PPCTargetMachine &TM, - MachineCodeEmitter &MCE) { + MachineCodeEmitter &MCE) { return new Emitter(TM, MCE); } FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM, - JITCodeEmitter &JCE) { + JITCodeEmitter &JCE) { return new Emitter(TM, JCE); } -template -bool Emitter::runOnMachineFunction(MachineFunction &MF) { +template +bool Emitter::runOnMachineFunction(MachineFunction &MF) { assert((MF.getTarget().getRelocationModel() != Reloc::Default || MF.getTarget().getRelocationModel() != Reloc::Static) && "JIT relocation model must be set to static or default!"); @@ -117,8 +118,8 @@ return false; } -template -void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { +template +void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { MCE.StartMachineBasicBlock(&MBB); for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){ Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=72697&r1=72696&r2=72697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Jun 1 14:57:37 2009 @@ -220,7 +220,8 @@ bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, - bool DumpAsm, MachineCodeEmitter &MCE) { + bool DumpAsm, + MachineCodeEmitter &MCE) { // Machine code emitter pass for PowerPC. PM.add(createPPCCodeEmitterPass(*this, MCE)); if (DumpAsm) { @@ -234,7 +235,8 @@ bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, - bool DumpAsm, JITCodeEmitter &JCE) { + bool DumpAsm, + JITCodeEmitter &JCE) { // Machine code emitter pass for PowerPC. PM.add(createPPCJITCodeEmitterPass(*this, JCE)); if (DumpAsm) { Modified: llvm/trunk/lib/Target/X86/X86.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=72697&r1=72696&r2=72697&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.h (original) +++ llvm/trunk/lib/Target/X86/X86.h Mon Jun 1 14:57:37 2009 @@ -28,7 +28,8 @@ /// createX86ISelDag - This pass converts a legalized DAG into a /// X86-specific DAG, ready for instruction scheduling. /// -FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel); +FunctionPass *createX86ISelDag(X86TargetMachine &TM, + CodeGenOpt::Level OptLevel); /// createX86FloatingPointStackifierPass - This function returns a pass which /// converts floating point register references and pseudo instructions into @@ -53,10 +54,10 @@ /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code /// to the specified MCE object. -FunctionPass *createX86CodeEmitterPass( - X86TargetMachine &TM, MachineCodeEmitter &MCE); -FunctionPass *createX86JITCodeEmitterPass( - X86TargetMachine &TM, JITCodeEmitter &JCE); +FunctionPass *createX86CodeEmitterPass(X86TargetMachine &TM, + MachineCodeEmitter &MCE); +FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM, + JITCodeEmitter &JCE); /// createX86EmitCodeToMemory - Returns a pass that converts a register /// allocated function into raw machine code in a dynamically @@ -64,8 +65,8 @@ /// FunctionPass *createEmitX86CodeToMemory(); -/// createX86MaxStackAlignmentCalculatorPass - This function returns a pass which -/// calculates maximal stack alignment required for function +/// createX86MaxStackAlignmentCalculatorPass - This function returns a pass +/// which calculates maximal stack alignment required for function /// FunctionPass *createX86MaxStackAlignmentCalculatorPass(); Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=72697&r1=72696&r2=72697&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Mon Jun 1 14:57:37 2009 @@ -36,22 +36,22 @@ STATISTIC(NumEmitted, "Number of machine instructions emitted"); namespace { -template< class machineCodeEmitter> +template class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass { const X86InstrInfo *II; const TargetData *TD; X86TargetMachine &TM; - machineCodeEmitter &MCE; + CodeEmitter &MCE; intptr_t PICBaseOffset; bool Is64BitMode; bool IsPIC; public: static char ID; - explicit Emitter(X86TargetMachine &tm, machineCodeEmitter &mce) + explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce) : MachineFunctionPass(&ID), II(0), TD(0), TM(tm), MCE(mce), PICBaseOffset(0), Is64BitMode(false), IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} - Emitter(X86TargetMachine &tm, machineCodeEmitter &mce, + Emitter(X86TargetMachine &tm, CodeEmitter &mce, const X86InstrInfo &ii, const TargetData &td, bool is64) : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm), MCE(mce), PICBaseOffset(0), Is64BitMode(is64), @@ -99,8 +99,8 @@ bool gvNeedsNonLazyPtr(const GlobalValue *GV); }; -template< class machineCodeEmitter> - char Emitter::ID = 0; +template + char Emitter::ID = 0; } /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code @@ -108,21 +108,19 @@ namespace llvm { -FunctionPass *createX86CodeEmitterPass( - X86TargetMachine &TM, MachineCodeEmitter &MCE) -{ +FunctionPass *createX86CodeEmitterPass(X86TargetMachine &TM, + MachineCodeEmitter &MCE) { return new Emitter(TM, MCE); } -FunctionPass *createX86JITCodeEmitterPass( - X86TargetMachine &TM, JITCodeEmitter &JCE) -{ +FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM, + JITCodeEmitter &JCE) { return new Emitter(TM, JCE); } } // end namespace llvm -template< class machineCodeEmitter> -bool Emitter::runOnMachineFunction(MachineFunction &MF) { +template +bool Emitter::runOnMachineFunction(MachineFunction &MF) { MCE.setModuleInfo(&getAnalysis()); @@ -156,8 +154,8 @@ /// necessary to resolve the address of this block later and emits a dummy /// value. /// -template< class machineCodeEmitter> -void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { +template +void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { // Remember where this reference was and where it is to so we can // deal with it later. MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), @@ -168,8 +166,8 @@ /// emitGlobalAddress - Emit the specified address to the code stream assuming /// this is part of a "take the address of a global" instruction. /// -template< class machineCodeEmitter> -void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, +template +void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, intptr_t Disp /* = 0 */, intptr_t PCAdj /* = 0 */, bool NeedStub /* = false */, @@ -195,8 +193,9 @@ /// emitExternalSymbolAddress - Arrange for the address of an external symbol to /// be emitted to the current location in the function, and allow it to be PC /// relative. -template< class machineCodeEmitter> -void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) { +template +void Emitter::emitExternalSymbolAddress(const char *ES, + unsigned Reloc) { intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0; MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), Reloc, ES, RelocCST)); @@ -209,8 +208,8 @@ /// emitConstPoolAddress - Arrange for the address of an constant pool /// to be emitted to the current location in the function, and allow it to be PC /// relative. -template< class machineCodeEmitter> -void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc, +template +void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp /* = 0 */, intptr_t PCAdj /* = 0 */) { intptr_t RelocCST = 0; @@ -230,8 +229,8 @@ /// emitJumpTableAddress - Arrange for the address of a jump table to /// be emitted to the current location in the function, and allow it to be PC /// relative. -template< class machineCodeEmitter> -void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc, +template +void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc, intptr_t PCAdj /* = 0 */) { intptr_t RelocCST = 0; if (Reloc == X86::reloc_picrel_word) @@ -247,8 +246,8 @@ MCE.emitWordLE(0); } -template< class machineCodeEmitter> -unsigned Emitter::getX86RegNum(unsigned RegNo) const { +template +unsigned Emitter::getX86RegNum(unsigned RegNo) const { return II->getRegisterInfo().getX86RegNum(RegNo); } @@ -258,24 +257,27 @@ return RM | (RegOpcode << 3) | (Mod << 6); } -template< class machineCodeEmitter> -void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){ +template +void Emitter::emitRegModRMByte(unsigned ModRMReg, + unsigned RegOpcodeFld){ MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg))); } -template< class machineCodeEmitter> -void Emitter::emitRegModRMByte(unsigned RegOpcodeFld) { +template +void Emitter::emitRegModRMByte(unsigned RegOpcodeFld) { MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0)); } -template< class machineCodeEmitter> -void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) { +template +void Emitter::emitSIBByte(unsigned SS, + unsigned Index, + unsigned Base) { // SIB byte is in the same format as the ModRMByte... MCE.emitByte(ModRMByte(SS, Index, Base)); } -template< class machineCodeEmitter> -void Emitter::emitConstant(uint64_t Val, unsigned Size) { +template +void Emitter::emitConstant(uint64_t Val, unsigned Size) { // Output the constant in little endian byte order... for (unsigned i = 0; i != Size; ++i) { MCE.emitByte(Val & 255); @@ -289,16 +291,16 @@ return Value == (signed char)Value; } -template< class machineCodeEmitter> -bool Emitter::gvNeedsNonLazyPtr(const GlobalValue *GV) { +template +bool Emitter::gvNeedsNonLazyPtr(const GlobalValue *GV) { // For Darwin, simulate the linktime GOT by using the same non-lazy-pointer // mechanism as 32-bit mode. return (!Is64BitMode || TM.getSubtarget().isTargetDarwin()) && TM.getSubtarget().GVRequiresExtraLoad(GV, TM, false); } -template< class machineCodeEmitter> -void Emitter::emitDisplacementField(const MachineOperand *RelocOp, +template +void Emitter::emitDisplacementField(const MachineOperand *RelocOp, int DispVal, intptr_t PCAdj) { // If this is a simple integer displacement that doesn't require a relocation, // emit it now. @@ -332,8 +334,8 @@ } } -template< class machineCodeEmitter> -void Emitter::emitMemModRMByte(const MachineInstr &MI, +template +void Emitter::emitMemModRMByte(const MachineInstr &MI, unsigned Op, unsigned RegOpcodeField, intptr_t PCAdj) { const MachineOperand &Op3 = MI.getOperand(Op+3); @@ -450,8 +452,8 @@ } } -template< class machineCodeEmitter> -void Emitter::emitInstruction( +template +void Emitter::emitInstruction( const MachineInstr &MI, const TargetInstrDesc *Desc) { DOUT << MI; @@ -672,7 +674,8 @@ getX86RegNum(MI.getOperand(CurOp).getReg())); CurOp += 2; if (CurOp != NumOps) - emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc)); + emitConstant(MI.getOperand(CurOp++).getImm(), + X86InstrInfo::sizeOfImm(Desc)); break; case X86II::MRMSrcMem: { @@ -692,7 +695,8 @@ PCAdj); CurOp += AddrOperands + 1; if (CurOp != NumOps) - emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc)); + emitConstant(MI.getOperand(CurOp++).getImm(), + X86InstrInfo::sizeOfImm(Desc)); break; } Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=72697&r1=72696&r2=72697&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Jun 1 14:57:37 2009 @@ -116,7 +116,7 @@ return getJITMatchQuality()/2; } -X86_32TargetMachine::X86_32TargetMachine(const Module &M, const std::string &FS) +X86_32TargetMachine::X86_32TargetMachine(const Module &M, const std::string &FS) : X86TargetMachine(M, FS, false) { } @@ -221,7 +221,8 @@ bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, - bool DumpAsm, MachineCodeEmitter &MCE) { + bool DumpAsm, + MachineCodeEmitter &MCE) { // FIXME: Move this to TargetJITInfo! // On Darwin, do not override 64-bit setting made in X86TargetMachine(). if (DefRelocModel == Reloc::Default && @@ -250,7 +251,8 @@ bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, - bool DumpAsm, JITCodeEmitter &JCE) { + bool DumpAsm, + JITCodeEmitter &JCE) { // FIXME: Move this to TargetJITInfo! // On Darwin, do not override 64-bit setting made in X86TargetMachine(). if (DefRelocModel == Reloc::Default && From asl at math.spbu.ru Mon Jun 1 15:00:49 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 01 Jun 2009 20:00:49 -0000 Subject: [llvm-commits] [llvm] r72698 - in /llvm/trunk/lib/Target/ARM: ARMSubtarget.cpp ARMSubtarget.h Message-ID: <200906012000.n51K0oab031613@zion.cs.uiuc.edu> Author: asl Date: Mon Jun 1 15:00:48 2009 New Revision: 72698 URL: http://llvm.org/viewvc/llvm-project?rev=72698&view=rev Log: Implement review feedback. Make thumb2 'normal' subtarget feature Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=72698&r1=72697&r2=72698&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Jun 1 15:00:48 2009 @@ -20,7 +20,8 @@ bool isThumb) : ARMArchVersion(V4T) , ARMFPUType(None) - , ThumbMode((isThumb ? Thumb1 : ThumbNone)) + , IsThumb(isThumb) + , ThumbMode(Thumb1) , UseThumbBacktraces(false) , IsR9Reserved(false) , stackAlignment(4) @@ -41,22 +42,18 @@ if (Len >= 5 && TT.substr(0, 4) == "armv") Idx = 4; else if (Len >= 6 && TT.substr(0, 6) == "thumb") { - isThumb = true; + IsThumb = true; if (Len >= 7 && TT[5] == 'v') Idx = 6; } if (Idx) { unsigned SubVer = TT[Idx]; if (SubVer > '4' && SubVer <= '9') { - if (SubVer >= '7') { + if (SubVer >= '7') ARMArchVersion = V7A; - if (isThumb) - ThumbMode = Thumb2; - } else if (SubVer == '6') { + else if (SubVer == '6') ARMArchVersion = V6; - if (isThumb && Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') - ThumbMode = Thumb2; - } else if (SubVer == '5') { + else if (SubVer == '5') { ARMArchVersion = V5T; if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') ARMArchVersion = V5TE; Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=72698&r1=72697&r2=72698&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon Jun 1 15:00:48 2009 @@ -31,7 +31,6 @@ }; enum ThumbTypeEnum { - ThumbNone, Thumb1, Thumb2 }; @@ -43,7 +42,10 @@ /// ARMFPUType - Floating Point Unit type. ARMFPEnum ARMFPUType; - /// ThumbMode - ARM if in ARM mode, otherwise indicates Thumb version. + /// IsThumb - True if we are in thumb mode, false if in ARM mode. + bool IsThumb; + + /// ThumbMode - Indicates supported Thumb version. ThumbTypeEnum ThumbMode; /// UseThumbBacktraces - True if we use thumb style backtraces. @@ -102,8 +104,8 @@ bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; } bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } - bool isThumb() const { return ThumbMode >= Thumb1; } - bool isThumb2() const { return ThumbMode >= Thumb2; } + bool isThumb() const { return IsThumb; } + bool isThumb2() const { return IsThumb && (ThumbMode >= Thumb2); } bool useThumbBacktraces() const { return UseThumbBacktraces; } bool isR9Reserved() const { return IsR9Reserved; } From isanbard at gmail.com Mon Jun 1 15:08:20 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 1 Jun 2009 13:08:20 -0700 Subject: [llvm-commits] [llvm] r72604 - in /llvm/trunk/lib: CodeGen/ CodeGen/AsmPrinter/ CodeGen/SelectionDAG/ Support/ System/Unix/ Target/ Target/ARM/ Target/CellSPU/ Target/PIC16/ Target/X86/ Target/X86/AsmPrinter/ Target/XCore/ VMCore/ In-Reply-To: <4A20E889.9050108@wxs.nl> References: <200905300109.n4U19tfZ024643@zion.cs.uiuc.edu> <4A20E889.9050108@wxs.nl> Message-ID: <86DB41FC-825F-42EA-A0D6-5E5CAA19E115@gmail.com> On May 30, 2009, at 1:04 AM, Frits van Bommel wrote: > Bill Wendling wrote: >> Author: void >> Date: Fri May 29 20:09:53 2009 >> New Revision: 72604 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=72604&view=rev >> Log: >> Untabification. > >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) >> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri May 29 >> 20:09:53 2009 >> @@ -969,12 +969,6 @@ >> DbgScope *Parent = NULL; >> DIBlock Block(V); >> >> - // Don't create a new scope if we already created one for an >> inlined function. >> - DenseMap::iterator >> - II = AbstractInstanceRootMap.find(V); >> - if (II != AbstractInstanceRootMap.end()) >> - return LexicalScopeStack.back(); >> - >> if (!Block.isNull()) { >> DIDescriptor ParentDesc = Block.getContext(); >> Parent = >> @@ -1030,6 +1024,8 @@ >> AddLabel(Die, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr, >> DWLabel("func_end", SubprogramCount)); >> >> + // Add the scope's contents. >> + ConstructDbgScope(ConcreteInst, StartID, EndID, Die, Unit); >> ParentDie->AddChild(Die); >> } > > I don't see any tabs being removed in this part... Oops... Weird that the buildbots and nightly tests didn't scream about this... -bw From isanbard at gmail.com Mon Jun 1 15:18:47 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 01 Jun 2009 20:18:47 -0000 Subject: [llvm-commits] [llvm] r72699 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <200906012018.n51KIlHf032352@zion.cs.uiuc.edu> Author: void Date: Mon Jun 1 15:18:46 2009 New Revision: 72699 URL: http://llvm.org/viewvc/llvm-project?rev=72699&view=rev Log: Accidental commit. This isn't ready for prime time just yet. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=72699&r1=72698&r2=72699&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Jun 1 15:18:46 2009 @@ -969,6 +969,12 @@ DbgScope *Parent = NULL; DIBlock Block(V); + // Don't create a new scope if we already created one for an inlined function. + DenseMap::iterator + II = AbstractInstanceRootMap.find(V); + if (II != AbstractInstanceRootMap.end()) + return LexicalScopeStack.back(); + if (!Block.isNull()) { DIDescriptor ParentDesc = Block.getContext(); Parent = @@ -1024,8 +1030,6 @@ AddLabel(Die, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr, DWLabel("func_end", SubprogramCount)); - // Add the scope's contents. - ConstructDbgScope(ConcreteInst, StartID, EndID, Die, Unit); ParentDie->AddChild(Die); } From isanbard at gmail.com Mon Jun 1 15:18:56 2009 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 1 Jun 2009 13:18:56 -0700 Subject: [llvm-commits] [llvm] r72604 - in /llvm/trunk/lib: CodeGen/ CodeGen/AsmPrinter/ CodeGen/SelectionDAG/ Support/ System/Unix/ Target/ Target/ARM/ Target/CellSPU/ Target/PIC16/ Target/X86/ Target/X86/AsmPrinter/ Target/XCore/ VMCore/ In-Reply-To: <4A20E889.9050108@wxs.nl> References: <200905300109.n4U19tfZ024643@zion.cs.uiuc.edu> <4A20E889.9050108@wxs.nl> Message-ID: On May 30, 2009, at 1:04 AM, Frits van Bommel wrote: > Bill Wendling wrote: >> Author: void >> Date: Fri May 29 20:09:53 2009 >> New Revision: 72604 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=72604&view=rev >> Log: >> Untabification. > >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) >> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri May 29 >> 20:09:53 2009 >> @@ -969,12 +969,6 @@ >> DbgScope *Parent = NULL; >> DIBlock Block(V); >> >> - // Don't create a new scope if we already created one for an >> inlined function. >> - DenseMap::iterator >> - II = AbstractInstanceRootMap.find(V); >> - if (II != AbstractInstanceRootMap.end()) >> - return LexicalScopeStack.back(); >> - >> if (!Block.isNull()) { >> DIDescriptor ParentDesc = Block.getContext(); >> Parent = >> @@ -1030,6 +1024,8 @@ >> AddLabel(Die, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr, >> DWLabel("func_end", SubprogramCount)); >> >> + // Add the scope's contents. >> + ConstructDbgScope(ConcreteInst, StartID, EndID, Die, Unit); >> ParentDie->AddChild(Die); >> } > > I don't see any tabs being removed in this part... Removed it. Thanks for catching this! -bw From kledzik at apple.com Mon Jun 1 15:33:09 2009 From: kledzik at apple.com (Nick Kledzik) Date: Mon, 01 Jun 2009 20:33:09 -0000 Subject: [llvm-commits] [llvm] r72700 - in /llvm/trunk/tools/lto: LTOModule.cpp LTOModule.h Message-ID: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> Author: kledzik Date: Mon Jun 1 15:33:09 2009 New Revision: 72700 URL: http://llvm.org/viewvc/llvm-project?rev=72700&view=rev Log: libLTO needs to handle i386 magic objc class symbols Parse __OBJC data structures and synthesize magic .objc_ symbols. Also, alter mangler so that objc method names are readable. Modified: llvm/trunk/tools/lto/LTOModule.cpp llvm/trunk/tools/lto/LTOModule.h Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=72700&r1=72699&r2=72700&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Mon Jun 1 15:33:09 2009 @@ -14,6 +14,7 @@ #include "LTOModule.h" +#include "llvm/Constants.h" #include "llvm/Module.h" #include "llvm/ModuleProvider.h" #include "llvm/ADT/OwningPtr.h" @@ -176,11 +177,123 @@ } } -void LTOModule::addDefinedDataSymbol(GlobalValue* v, Mangler &mangler) +// get string that data pointer points to +bool LTOModule::objcClassNameFromExpression(Constant* c, std::string& name) +{ + if (ConstantExpr* ce = dyn_cast(c)) { + Constant* op = ce->getOperand(0); + if (GlobalVariable* gvn = dyn_cast(op)) { + Constant* cn = gvn->getInitializer(); + if (ConstantArray* ca = dyn_cast(cn)) { + if ( ca->isCString() ) { + name = ".objc_class_name_" + ca->getAsString(); + return true; + } + } + } + } + return false; +} + +// parse i386/ppc ObjC class data structure +void LTOModule::addObjCClass(GlobalVariable* clgv) +{ + if (ConstantStruct* c = dyn_cast(clgv->getInitializer())) { + // second slot in __OBJC,__class is pointer to superclass name + std::string superclassName; + if ( objcClassNameFromExpression(c->getOperand(1), superclassName) ) { + NameAndAttributes info; + if ( _undefines.find(superclassName.c_str()) == _undefines.end() ) { + const char* symbolName = ::strdup(superclassName.c_str()); + info.name = ::strdup(symbolName); + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; + // string is owned by _undefines + _undefines[info.name] = info; + } + } + // third slot in __OBJC,__class is pointer to class name + std::string className; + if ( objcClassNameFromExpression(c->getOperand(2), className) ) { + const char* symbolName = ::strdup(className.c_str()); + NameAndAttributes info; + info.name = symbolName; + info.attributes = (lto_symbol_attributes) + (LTO_SYMBOL_PERMISSIONS_DATA | + LTO_SYMBOL_DEFINITION_REGULAR | + LTO_SYMBOL_SCOPE_DEFAULT); + _symbols.push_back(info); + _defines[info.name] = 1; + } + } +} + + +// parse i386/ppc ObjC category data structure +void LTOModule::addObjCCategory(GlobalVariable* clgv) +{ + if (ConstantStruct* c = dyn_cast(clgv->getInitializer())) { + // second slot in __OBJC,__category is pointer to target class name + std::string targetclassName; + if ( objcClassNameFromExpression(c->getOperand(1), targetclassName) ) { + NameAndAttributes info; + if ( _undefines.find(targetclassName.c_str()) == _undefines.end() ){ + const char* symbolName = ::strdup(targetclassName.c_str()); + info.name = ::strdup(symbolName); + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; + // string is owned by _undefines + _undefines[info.name] = info; + } + } + } +} + + +// parse i386/ppc ObjC class list data structure +void LTOModule::addObjCClassRef(GlobalVariable* clgv) +{ + std::string targetclassName; + if ( objcClassNameFromExpression(clgv->getInitializer(), targetclassName) ){ + NameAndAttributes info; + if ( _undefines.find(targetclassName.c_str()) == _undefines.end() ) { + const char* symbolName = ::strdup(targetclassName.c_str()); + info.name = ::strdup(symbolName); + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; + // string is owned by _undefines + _undefines[info.name] = info; + } + } +} + + +void LTOModule::addDefinedDataSymbol(GlobalValue* v, Mangler& mangler) { // add to list of defined symbols addDefinedSymbol(v, mangler, false); + // special case i386/ppc ObjC data structures in magic sections + if ( v->hasSection() ) { + // special case if this data blob is an ObjC class definition + if ( v->getSection().compare(0, 15, "__OBJC,__class,") == 0 ) { + if (GlobalVariable* gv = dyn_cast(v)) { + addObjCClass(gv); + } + } + + // special case if this data blob is an ObjC category definition + else if ( v->getSection().compare(0, 18, "__OBJC,__category,") == 0 ) { + if (GlobalVariable* gv = dyn_cast(v)) { + addObjCCategory(gv); + } + } + + // special case if this data blob is the list of referenced classes + else if ( v->getSection().compare(0, 18, "__OBJC,__cls_refs,") == 0 ) { + if (GlobalVariable* gv = dyn_cast(v)) { + addObjCClassRef(gv); + } + } + } + // add external symbols referenced by this data. for (unsigned count = 0, total = v->getNumOperands(); count != total; ++count) { @@ -192,9 +305,13 @@ void LTOModule::addDefinedSymbol(GlobalValue* def, Mangler &mangler, bool isFunction) { + // ignore all llvm.* symbols + if ( strncmp(def->getNameStart(), "llvm.", 5) == 0 ) + return; + // string is owned by _defines const char* symbolName = ::strdup(mangler.getValueName(def).c_str()); - + // set alignment part log2() can have rounding errors uint32_t align = def->getAlignment(); uint32_t attr = align ? CountTrailingZeros_32(def->getAlignment()) : 0; @@ -241,25 +358,28 @@ } void LTOModule::addAsmGlobalSymbol(const char *name) { - // string is owned by _defines - const char *symbolName = ::strdup(name); - uint32_t attr = LTO_SYMBOL_DEFINITION_REGULAR; - attr |= LTO_SYMBOL_SCOPE_DEFAULT; - - // add to table of symbols - NameAndAttributes info; - info.name = symbolName; - info.attributes = (lto_symbol_attributes)attr; - _symbols.push_back(info); - _defines[info.name] = 1; + // only add new define if not already defined + if ( _defines.count(name, &name[strlen(name)+1]) == 0 ) + return; + + // string is owned by _defines + const char *symbolName = ::strdup(name); + uint32_t attr = LTO_SYMBOL_DEFINITION_REGULAR; + attr |= LTO_SYMBOL_SCOPE_DEFAULT; + NameAndAttributes info; + info.name = symbolName; + info.attributes = (lto_symbol_attributes)attr; + _symbols.push_back(info); + _defines[info.name] = 1; } void LTOModule::addPotentialUndefinedSymbol(GlobalValue* decl, Mangler &mangler) { - const char* name = mangler.getValueName(decl).c_str(); // ignore all llvm.* symbols - if ( strncmp(name, "llvm.", 5) == 0 ) - return; + if ( strncmp(decl->getNameStart(), "llvm.", 5) == 0 ) + return; + + const char* name = mangler.getValueName(decl).c_str(); // we already have the symbol if (_undefines.find(name) != _undefines.end()) @@ -306,6 +426,14 @@ // Use mangler to add GlobalPrefix to names to match linker names. Mangler mangler(*_module, _target->getTargetAsmInfo()->getGlobalPrefix()); + // add chars used in ObjC method names so method names aren't mangled + mangler.markCharAcceptable('['); + mangler.markCharAcceptable(']'); + mangler.markCharAcceptable('('); + mangler.markCharAcceptable(')'); + mangler.markCharAcceptable('-'); + mangler.markCharAcceptable('+'); + mangler.markCharAcceptable(' '); // add functions for (Module::iterator f = _module->begin(); f != _module->end(); ++f) { Modified: llvm/trunk/tools/lto/LTOModule.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.h?rev=72700&r1=72699&r2=72700&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.h (original) +++ llvm/trunk/tools/lto/LTOModule.h Mon Jun 1 15:33:09 2009 @@ -77,13 +77,19 @@ void addDefinedDataSymbol(llvm::GlobalValue* v, llvm::Mangler &mangler); void addAsmGlobalSymbol(const char *); + void addObjCClass(llvm::GlobalVariable* clgv); + void addObjCCategory(llvm::GlobalVariable* clgv); + void addObjCClassRef(llvm::GlobalVariable* clgv); + bool objcClassNameFromExpression(llvm::Constant* c, + std::string& name); + static bool isTargetMatch(llvm::MemoryBuffer* memBuffer, const char* triplePrefix); - + static LTOModule* makeLTOModule(llvm::MemoryBuffer* buffer, std::string& errMsg); static llvm::MemoryBuffer* makeBuffer(const void* mem, size_t length); - + typedef llvm::StringMap StringSet; struct NameAndAttributes { From mrs at apple.com Mon Jun 1 16:02:35 2009 From: mrs at apple.com (Mike Stump) Date: Mon, 01 Jun 2009 21:02:35 -0000 Subject: [llvm-commits] [llvm] r72702 - /llvm/trunk/include/llvm/ADT/APFloat.h Message-ID: <200906012102.n51L2ZUB001770@zion.cs.uiuc.edu> Author: mrs Date: Mon Jun 1 16:02:35 2009 New Revision: 72702 URL: http://llvm.org/viewvc/llvm-project?rev=72702&view=rev Log: Dcoument that the opauque value used to construct QNaNs is truncated as necessary. Modified: llvm/trunk/include/llvm/ADT/APFloat.h Modified: llvm/trunk/include/llvm/ADT/APFloat.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APFloat.h?rev=72702&r1=72701&r2=72702&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/APFloat.h (original) +++ llvm/trunk/include/llvm/ADT/APFloat.h Mon Jun 1 16:02:35 2009 @@ -192,7 +192,7 @@ /// /// \param Negative - True iff the NaN generated should be negative. /// \param type - The unspecified fill bits for creating the NaN, 0 by - /// default. + /// default. The value is truncated as necessary. static APFloat getNaN(const fltSemantics &Sem, bool Negative = false, unsigned type = 0) { return APFloat(Sem, fcNaN, Negative, type); From mrs at apple.com Mon Jun 1 16:02:58 2009 From: mrs at apple.com (Mike Stump) Date: Mon, 1 Jun 2009 14:02:58 -0700 Subject: [llvm-commits] [llvm] r72606 - in /llvm/trunk: include/llvm/ADT/APFloat.h lib/Support/APFloat.cpp In-Reply-To: <13AC3569-F9D4-4B02-9293-3E3F91D35496@apple.com> References: <200905300349.n4U3njD1030452@zion.cs.uiuc.edu> <13AC3569-F9D4-4B02-9293-3E3F91D35496@apple.com> Message-ID: <5928709B-7202-405A-8E1D-473F164FEA21@apple.com> On Jun 1, 2009, at 11:31 AM, Dale Johannesen wrote: > Is the caller supposed to do the truncation to the significand size, > or are you expecting APFloat to do > this? Fixed in 72702, thanks. From nlewycky at google.com Mon Jun 1 16:11:28 2009 From: nlewycky at google.com (Nick Lewycky) Date: Mon, 1 Jun 2009 14:11:28 -0700 Subject: [llvm-commits] [llvm] r72700 - in /llvm/trunk/tools/lto: LTOModule.cpp LTOModule.h In-Reply-To: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> References: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> Message-ID: 2009/6/1 Nick Kledzik > Author: kledzik > Date: Mon Jun 1 15:33:09 2009 > New Revision: 72700 > > URL: http://llvm.org/viewvc/llvm-project?rev=72700&view=rev > Log: > libLTO needs to handle i386 magic objc class > symbols > Parse __OBJC data structures and synthesize magic .objc_ symbols. > Also, alter mangler so that objc method names are readable. Hi Nick, could you please elaborate on why exactly libLTO needs to change? While I don't doubt that this fixes a bug, I can't see how this language-specific logic could possibly belong in libLTO. > > > Modified: > llvm/trunk/tools/lto/LTOModule.cpp > llvm/trunk/tools/lto/LTOModule.h > > Modified: llvm/trunk/tools/lto/LTOModule.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=72700&r1=72699&r2=72700&view=diff > > > ============================================================================== > --- llvm/trunk/tools/lto/LTOModule.cpp (original) > +++ llvm/trunk/tools/lto/LTOModule.cpp Mon Jun 1 15:33:09 2009 > @@ -14,6 +14,7 @@ > > #include "LTOModule.h" > > +#include "llvm/Constants.h" > #include "llvm/Module.h" > #include "llvm/ModuleProvider.h" > #include "llvm/ADT/OwningPtr.h" > @@ -176,11 +177,123 @@ > } > } > > -void LTOModule::addDefinedDataSymbol(GlobalValue* v, Mangler &mangler) > +// get string that data pointer points to > +bool LTOModule::objcClassNameFromExpression(Constant* c, std::string& > name) > +{ > + if (ConstantExpr* ce = dyn_cast(c)) { Is there any reason not to just assert on this? Will it ever really be called on constants that aren't known to be objcClassNames? > > + Constant* op = ce->getOperand(0); > + if (GlobalVariable* gvn = dyn_cast(op)) { > + Constant* cn = gvn->getInitializer(); > + if (ConstantArray* ca = dyn_cast(cn)) { > + if ( ca->isCString() ) { > + name = ".objc_class_name_" + ca->getAsString(); > + return true; > + } > + } > + } > + } > + return false; > +} > + > +// parse i386/ppc ObjC class data structure > +void LTOModule::addObjCClass(GlobalVariable* clgv) > +{ > + if (ConstantStruct* c = > dyn_cast(clgv->getInitializer())) { Here again, perhaps it should just assert that this is true? > > + // second slot in __OBJC,__class is pointer to superclass name > + std::string superclassName; > + if ( objcClassNameFromExpression(c->getOperand(1), superclassName) > ) { > + NameAndAttributes info; > + if ( _undefines.find(superclassName.c_str()) == > _undefines.end() ) { > + const char* symbolName = ::strdup(superclassName.c_str()); > + info.name = ::strdup(symbolName); > + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; > + // string is owned by _undefines > + _undefines[info.name] = info; Perhaps the non-libLTO side of the Apple linker should ignore symbols it knows are objC specific? Or perhaps you could run a domain-specific LLVM pass which would delete these globals as needed? If somehow you need them to exist but still be marked undefined, perhaps libLTO should expose an interface for marking symbols undefined instead of an interface specific to Apple's implementation of the objC language? It just seems like this is breaking encapsulation, the linker has linking rules that don't much care what the source language was. Nick > > + } > + } > + // third slot in __OBJC,__class is pointer to class name > + std::string className; > + if ( objcClassNameFromExpression(c->getOperand(2), className) ) { > + const char* symbolName = ::strdup(className.c_str()); > + NameAndAttributes info; > + info.name = symbolName; > + info.attributes = (lto_symbol_attributes) > + (LTO_SYMBOL_PERMISSIONS_DATA | > + LTO_SYMBOL_DEFINITION_REGULAR | > + LTO_SYMBOL_SCOPE_DEFAULT); > + _symbols.push_back(info); > + _defines[info.name] = 1; > + } > + } > +} > + > + > +// parse i386/ppc ObjC category data structure > +void LTOModule::addObjCCategory(GlobalVariable* clgv) > +{ > + if (ConstantStruct* c = > dyn_cast(clgv->getInitializer())) { > + // second slot in __OBJC,__category is pointer to target class > name > + std::string targetclassName; > + if ( objcClassNameFromExpression(c->getOperand(1), > targetclassName) ) { > + NameAndAttributes info; > + if ( _undefines.find(targetclassName.c_str()) == > _undefines.end() ){ > + const char* symbolName = > ::strdup(targetclassName.c_str()); > + info.name = ::strdup(symbolName); > + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; > + // string is owned by _undefines > + _undefines[info.name] = info; > + } > + } > + } > +} > + > + > +// parse i386/ppc ObjC class list data structure > +void LTOModule::addObjCClassRef(GlobalVariable* clgv) > +{ > + std::string targetclassName; > + if ( objcClassNameFromExpression(clgv->getInitializer(), > targetclassName) ){ > + NameAndAttributes info; > + if ( _undefines.find(targetclassName.c_str()) == _undefines.end() > ) { > + const char* symbolName = ::strdup(targetclassName.c_str()); > + info.name = ::strdup(symbolName); > + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; > + // string is owned by _undefines > + _undefines[info.name] = info; > + } > + } > +} > + > + > +void LTOModule::addDefinedDataSymbol(GlobalValue* v, Mangler& mangler) > { > // add to list of defined symbols > addDefinedSymbol(v, mangler, false); > > + // special case i386/ppc ObjC data structures in magic sections > + if ( v->hasSection() ) { > + // special case if this data blob is an ObjC class definition > + if ( v->getSection().compare(0, 15, "__OBJC,__class,") == 0 ) { > + if (GlobalVariable* gv = dyn_cast(v)) { > + addObjCClass(gv); > + } > + } > + > + // special case if this data blob is an ObjC category definition > + else if ( v->getSection().compare(0, 18, "__OBJC,__category,") == > 0 ) { > + if (GlobalVariable* gv = dyn_cast(v)) { > + addObjCCategory(gv); > + } > + } > + > + // special case if this data blob is the list of referenced > classes > + else if ( v->getSection().compare(0, 18, "__OBJC,__cls_refs,") == > 0 ) { > + if (GlobalVariable* gv = dyn_cast(v)) { > + addObjCClassRef(gv); > + } > + } > + } > + > // add external symbols referenced by this data. > for (unsigned count = 0, total = v->getNumOperands(); > count != total; ++count) { > @@ -192,9 +305,13 @@ > void LTOModule::addDefinedSymbol(GlobalValue* def, Mangler &mangler, > bool isFunction) > { > + // ignore all llvm.* symbols > + if ( strncmp(def->getNameStart(), "llvm.", 5) == 0 ) > + return; > + > // string is owned by _defines > const char* symbolName = ::strdup(mangler.getValueName(def).c_str()); > - > + > // set alignment part log2() can have rounding errors > uint32_t align = def->getAlignment(); > uint32_t attr = align ? CountTrailingZeros_32(def->getAlignment()) : 0; > @@ -241,25 +358,28 @@ > } > > void LTOModule::addAsmGlobalSymbol(const char *name) { > - // string is owned by _defines > - const char *symbolName = ::strdup(name); > - uint32_t attr = LTO_SYMBOL_DEFINITION_REGULAR; > - attr |= LTO_SYMBOL_SCOPE_DEFAULT; > - > - // add to table of symbols > - NameAndAttributes info; > - info.name = symbolName; > - info.attributes = (lto_symbol_attributes)attr; > - _symbols.push_back(info); > - _defines[info.name] = 1; > + // only add new define if not already defined > + if ( _defines.count(name, &name[strlen(name)+1]) == 0 ) > + return; > + > + // string is owned by _defines > + const char *symbolName = ::strdup(name); > + uint32_t attr = LTO_SYMBOL_DEFINITION_REGULAR; > + attr |= LTO_SYMBOL_SCOPE_DEFAULT; > + NameAndAttributes info; > + info.name = symbolName; > + info.attributes = (lto_symbol_attributes)attr; > + _symbols.push_back(info); > + _defines[info.name] = 1; > } > > void LTOModule::addPotentialUndefinedSymbol(GlobalValue* decl, Mangler > &mangler) > { > - const char* name = mangler.getValueName(decl).c_str(); > // ignore all llvm.* symbols > - if ( strncmp(name, "llvm.", 5) == 0 ) > - return; > + if ( strncmp(decl->getNameStart(), "llvm.", 5) == 0 ) > + return; > + > + const char* name = mangler.getValueName(decl).c_str(); > > // we already have the symbol > if (_undefines.find(name) != _undefines.end()) > @@ -306,6 +426,14 @@ > > // Use mangler to add GlobalPrefix to names to match linker names. > Mangler mangler(*_module, > _target->getTargetAsmInfo()->getGlobalPrefix()); > + // add chars used in ObjC method names so method names aren't > mangled > + mangler.markCharAcceptable('['); > + mangler.markCharAcceptable(']'); > + mangler.markCharAcceptable('('); > + mangler.markCharAcceptable(')'); > + mangler.markCharAcceptable('-'); > + mangler.markCharAcceptable('+'); > + mangler.markCharAcceptable(' '); > > // add functions > for (Module::iterator f = _module->begin(); f != _module->end(); > ++f) { > > Modified: llvm/trunk/tools/lto/LTOModule.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.h?rev=72700&r1=72699&r2=72700&view=diff > > > ============================================================================== > --- llvm/trunk/tools/lto/LTOModule.h (original) > +++ llvm/trunk/tools/lto/LTOModule.h Mon Jun 1 15:33:09 2009 > @@ -77,13 +77,19 @@ > void addDefinedDataSymbol(llvm::GlobalValue* v, > llvm::Mangler > &mangler); > void addAsmGlobalSymbol(const char *); > + void addObjCClass(llvm::GlobalVariable* clgv); > + void addObjCCategory(llvm::GlobalVariable* clgv); > + void addObjCClassRef(llvm::GlobalVariable* clgv); > + bool objcClassNameFromExpression(llvm::Constant* c, > + std::string& name); > + > static bool isTargetMatch(llvm::MemoryBuffer* memBuffer, > const char* > triplePrefix); > - > + > static LTOModule* makeLTOModule(llvm::MemoryBuffer* buffer, > std::string& > errMsg); > static llvm::MemoryBuffer* makeBuffer(const void* mem, size_t length); > - > + > typedef llvm::StringMap StringSet; > > struct NameAndAttributes { > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090601/6bd80ddd/attachment.html From kledzik at apple.com Mon Jun 1 16:43:20 2009 From: kledzik at apple.com (Nick Kledzik) Date: Mon, 1 Jun 2009 14:43:20 -0700 Subject: [llvm-commits] [llvm] r72700 - in /llvm/trunk/tools/lto: LTOModule.cpp LTOModule.h In-Reply-To: References: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> Message-ID: On Jun 1, 2009, at 2:11 PM, Nick Lewycky wrote: > 2009/6/1 Nick Kledzik > Author: kledzik > Date: Mon Jun 1 15:33:09 2009 > New Revision: 72700 > > URL: http://llvm.org/viewvc/llvm-project?rev=72700&view=rev > Log: > libLTO needs to handle i386 magic objc > class symbols > Parse __OBJC data structures and synthesize magic .objc_ symbols. > Also, alter mangler so that objc method names are readable. > > Hi Nick, could you please elaborate on why exactly libLTO needs to > change? While I don't doubt that this fixes a bug, I can't see how > this language-specific logic could possibly belong in libLTO. It is not just language specific. It is only for Objective-C for ppc or i386 on Darwin. My thinking was that the extra logic is only executed if the GlobalVariable has a custom section with a specific name, that it would not impact other languages or architectures. This issue is that the old ObjC object format did some strange contortions to avoid real linker symbols. For instance the ObjC class data structure is allocated statically in the executable that defines it. That data structures contains a pointer to it superclass. But instead of just initializing that part of the struct to the address of its superclass, and letting the static and dynamic linkers do the rest, the runtime works by having that field point to a C-string that is the name of the superclass on disk. At runtime the objc initialization swaps that pointer out to point to the actual super class. As far as the linkers know it is just a pointer to a string. But someone wanted the linker to issue errors at build time if the superclass was not found. So they figured out a way in mach-o object format to use an absolute symbol (.objc_class_name_Foo = 0) and a floating reference ( .reference .objc_class_name_Bar) to trick the linker into erroring when a class was missing. This patch emulates that same behavior. In addition, when processing mach-o files, the current Darwin linker ignores those absolute and floating reference symbols, and instead parses the __OBJC,__class data structures and infers those symbols. The libLTO.dylib interfaces does not allow the linker to view the contents of a bitcode file, just its symbols. So having libLTO synthesize those symbols fits well with the Darwin linker. Would you prefer if the changes were wrapped in a isTargetDarwin() test? -Nick > > > > > Modified: > llvm/trunk/tools/lto/LTOModule.cpp > llvm/trunk/tools/lto/LTOModule.h > > Modified: llvm/trunk/tools/lto/LTOModule.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=72700&r1=72699&r2=72700&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/tools/lto/LTOModule.cpp (original) > +++ llvm/trunk/tools/lto/LTOModule.cpp Mon Jun 1 15:33:09 2009 > @@ -14,6 +14,7 @@ > > #include "LTOModule.h" > > +#include "llvm/Constants.h" > #include "llvm/Module.h" > #include "llvm/ModuleProvider.h" > #include "llvm/ADT/OwningPtr.h" > @@ -176,11 +177,123 @@ > } > } > > -void LTOModule::addDefinedDataSymbol(GlobalValue* v, Mangler > &mangler) > +// get string that data pointer points to > +bool LTOModule::objcClassNameFromExpression(Constant* c, > std::string& name) > +{ > + if (ConstantExpr* ce = dyn_cast(c)) { > > Is there any reason not to just assert on this? Will it ever really > be called on constants that aren't known to be objcClassNames? > > > + Constant* op = ce->getOperand(0); > + if (GlobalVariable* gvn = dyn_cast(op)) { > + Constant* cn = gvn->getInitializer(); > + if (ConstantArray* ca = dyn_cast(cn)) { > + if ( ca->isCString() ) { > + name = ".objc_class_name_" + ca->getAsString(); > + return true; > + } > + } > + } > + } > + return false; > +} > + > +// parse i386/ppc ObjC class data structure > +void LTOModule::addObjCClass(GlobalVariable* clgv) > +{ > + if (ConstantStruct* c = dyn_cast(clgv- > >getInitializer())) { > > Here again, perhaps it should just assert that this is true? > > > + // second slot in __OBJC,__class is pointer to superclass > name > + std::string superclassName; > + if ( objcClassNameFromExpression(c->getOperand(1), > superclassName) ) { > + NameAndAttributes info; > + if ( _undefines.find(superclassName.c_str()) == > _undefines.end() ) { > + const char* symbolName > = ::strdup(superclassName.c_str()); > + info.name = ::strdup(symbolName); > + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; > + // string is owned by _undefines > + _undefines[info.name] = info; > > Perhaps the non-libLTO side of the Apple linker should ignore > symbols it knows are objC specific? Or perhaps you could run a > domain-specific LLVM pass which would delete these globals as > needed? If somehow you need them to exist but still be marked > undefined, perhaps libLTO should expose an interface for marking > symbols undefined instead of an interface specific to Apple's > implementation of the objC language? > > It just seems like this is breaking encapsulation, the linker has > linking rules that don't much care what the source language was. > > Nick > > > + } > + } > + // third slot in __OBJC,__class is pointer to class name > + std::string className; > + if ( objcClassNameFromExpression(c->getOperand(2), > className) ) { > + const char* symbolName = ::strdup(className.c_str()); > + NameAndAttributes info; > + info.name = symbolName; > + info.attributes = (lto_symbol_attributes) > + (LTO_SYMBOL_PERMISSIONS_DATA | > + LTO_SYMBOL_DEFINITION_REGULAR | > + LTO_SYMBOL_SCOPE_DEFAULT); > + _symbols.push_back(info); > + _defines[info.name] = 1; > + } > + } > +} > + > + > +// parse i386/ppc ObjC category data structure > +void LTOModule::addObjCCategory(GlobalVariable* clgv) > +{ > + if (ConstantStruct* c = dyn_cast(clgv- > >getInitializer())) { > + // second slot in __OBJC,__category is pointer to target > class name > + std::string targetclassName; > + if ( objcClassNameFromExpression(c->getOperand(1), > targetclassName) ) { > + NameAndAttributes info; > + if ( _undefines.find(targetclassName.c_str()) == > _undefines.end() ){ > + const char* symbolName > = ::strdup(targetclassName.c_str()); > + info.name = ::strdup(symbolName); > + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; > + // string is owned by _undefines > + _undefines[info.name] = info; > + } > + } > + } > +} > + > + > +// parse i386/ppc ObjC class list data structure > +void LTOModule::addObjCClassRef(GlobalVariable* clgv) > +{ > + std::string targetclassName; > + if ( objcClassNameFromExpression(clgv->getInitializer(), > targetclassName) ){ > + NameAndAttributes info; > + if ( _undefines.find(targetclassName.c_str()) == > _undefines.end() ) { > + const char* symbolName > = ::strdup(targetclassName.c_str()); > + info.name = ::strdup(symbolName); > + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; > + // string is owned by _undefines > + _undefines[info.name] = info; > + } > + } > +} > + > + > +void LTOModule::addDefinedDataSymbol(GlobalValue* v, Mangler& > mangler) > { > // add to list of defined symbols > addDefinedSymbol(v, mangler, false); > > + // special case i386/ppc ObjC data structures in magic sections > + if ( v->hasSection() ) { > + // special case if this data blob is an ObjC class definition > + if ( v->getSection().compare(0, 15, "__OBJC,__class,") == > 0 ) { > + if (GlobalVariable* gv = dyn_cast(v)) { > + addObjCClass(gv); > + } > + } > + > + // special case if this data blob is an ObjC category > definition > + else if ( v->getSection().compare(0, 18, > "__OBJC,__category,") == 0 ) { > + if (GlobalVariable* gv = dyn_cast(v)) { > + addObjCCategory(gv); > + } > + } > + > + // special case if this data blob is the list of referenced > classes > + else if ( v->getSection().compare(0, 18, > "__OBJC,__cls_refs,") == 0 ) { > + if (GlobalVariable* gv = dyn_cast(v)) { > + addObjCClassRef(gv); > + } > + } > + } > + > // add external symbols referenced by this data. > for (unsigned count = 0, total = v->getNumOperands(); > count != total; + > +count) { > @@ -192,9 +305,13 @@ > void LTOModule::addDefinedSymbol(GlobalValue* def, Mangler &mangler, > bool isFunction) > { > + // ignore all llvm.* symbols > + if ( strncmp(def->getNameStart(), "llvm.", 5) == 0 ) > + return; > + > // string is owned by _defines > const char* symbolName > = ::strdup(mangler.getValueName(def).c_str()); > - > + > // set alignment part log2() can have rounding errors > uint32_t align = def->getAlignment(); > uint32_t attr = align ? CountTrailingZeros_32(def- > >getAlignment()) : 0; > @@ -241,25 +358,28 @@ > } > > void LTOModule::addAsmGlobalSymbol(const char *name) { > - // string is owned by _defines > - const char *symbolName = ::strdup(name); > - uint32_t attr = LTO_SYMBOL_DEFINITION_REGULAR; > - attr |= LTO_SYMBOL_SCOPE_DEFAULT; > - > - // add to table of symbols > - NameAndAttributes info; > - info.name = symbolName; > - info.attributes = (lto_symbol_attributes)attr; > - _symbols.push_back(info); > - _defines[info.name] = 1; > + // only add new define if not already defined > + if ( _defines.count(name, &name[strlen(name)+1]) == 0 ) > + return; > + > + // string is owned by _defines > + const char *symbolName = ::strdup(name); > + uint32_t attr = LTO_SYMBOL_DEFINITION_REGULAR; > + attr |= LTO_SYMBOL_SCOPE_DEFAULT; > + NameAndAttributes info; > + info.name = symbolName; > + info.attributes = (lto_symbol_attributes)attr; > + _symbols.push_back(info); > + _defines[info.name] = 1; > } > > void LTOModule::addPotentialUndefinedSymbol(GlobalValue* decl, > Mangler &mangler) > { > - const char* name = mangler.getValueName(decl).c_str(); > // ignore all llvm.* symbols > - if ( strncmp(name, "llvm.", 5) == 0 ) > - return; > + if ( strncmp(decl->getNameStart(), "llvm.", 5) == 0 ) > + return; > + > + const char* name = mangler.getValueName(decl).c_str(); > > // we already have the symbol > if (_undefines.find(name) != _undefines.end()) > @@ -306,6 +426,14 @@ > > // Use mangler to add GlobalPrefix to names to match linker > names. > Mangler mangler(*_module, _target->getTargetAsmInfo()- > >getGlobalPrefix()); > + // add chars used in ObjC method names so method names > aren't mangled > + mangler.markCharAcceptable('['); > + mangler.markCharAcceptable(']'); > + mangler.markCharAcceptable('('); > + mangler.markCharAcceptable(')'); > + mangler.markCharAcceptable('-'); > + mangler.markCharAcceptable('+'); > + mangler.markCharAcceptable(' '); > > // add functions > for (Module::iterator f = _module->begin(); f != _module- > >end(); ++f) { > > Modified: llvm/trunk/tools/lto/LTOModule.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.h?rev=72700&r1=72699&r2=72700&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/tools/lto/LTOModule.h (original) > +++ llvm/trunk/tools/lto/LTOModule.h Mon Jun 1 15:33:09 2009 > @@ -77,13 +77,19 @@ > void addDefinedDataSymbol(llvm::GlobalValue* v, > > llvm::Mangler &mangler); > void addAsmGlobalSymbol(const char *); > + void addObjCClass(llvm::GlobalVariable* clgv); > + void addObjCCategory(llvm::GlobalVariable* > clgv); > + void addObjCClassRef(llvm::GlobalVariable* > clgv); > + bool > objcClassNameFromExpression(llvm::Constant* c, > + std::string& > name); > + > static bool isTargetMatch(llvm::MemoryBuffer* > memBuffer, > const char* > triplePrefix); > - > + > static LTOModule* makeLTOModule(llvm::MemoryBuffer* buffer, > std::string& > errMsg); > static llvm::MemoryBuffer* makeBuffer(const void* mem, size_t > length); > - > + > typedef llvm::StringMap StringSet; > > struct NameAndAttributes { > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090601/75c6313e/attachment.html From eli.friedman at gmail.com Mon Jun 1 18:09:07 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 1 Jun 2009 16:09:07 -0700 Subject: [llvm-commits] [llvm] r72688 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2009-06-01-BitcastIntPadding.ll In-Reply-To: <4A23D9D1.20200@free.fr> References: <200906010914.n519EvY6005825@zion.cs.uiuc.edu> <4A23D9D1.20200@free.fr> Message-ID: On Mon, Jun 1, 2009 at 6:38 AM, Duncan Sands wrote: > Hi Eli, > >> + ? ? %a = alloca %struct.singlebool, align 1 ? ? ? ? ; <%struct.singlebool*> [#uses=2] >> + ? ? %storetmp.i = bitcast %struct.singlebool* %a to i1* ? ? ? ? ? ? ; [#uses=1] >> + ? ? store i1 true, i1* %storetmp.i >> + ? ? %tmp = getelementptr %struct.singlebool* %a, i64 0, i32 0 ? ? ? ? ? ? ? ; [#uses=1] >> + ? ? %tmp1 = load i8* %tmp ? ? ? ? ? ; [#uses=1] >> + ? ? ret i8 %tmp1 > > what does this return? ?It's unspecified as to what is stored in > the extra bits when you do an i1 store (in fact it is zero, but > we may want to keep some freedom here). It returns something with a bottom bit of 1. Note that this is a simplified version of the original testcase. -Eli From dalej at apple.com Mon Jun 1 18:12:54 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 01 Jun 2009 23:12:54 -0000 Subject: [llvm-commits] [llvm] r72705 - /llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Message-ID: <200906012312.n51NCsxw006146@zion.cs.uiuc.edu> Author: johannes Date: Mon Jun 1 18:12:52 2009 New Revision: 72705 URL: http://llvm.org/viewvc/llvm-project?rev=72705&view=rev Log: Trailing whitespace. Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=72705&r1=72704&r2=72705&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Mon Jun 1 18:12:52 2009 @@ -244,7 +244,7 @@ SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, dl, VT, SDValue(Carry,0), RHS); - return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag, + return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag, LHS, SDValue(AddCarry,0)); } From dalej at apple.com Mon Jun 1 18:13:43 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 01 Jun 2009 23:13:43 -0000 Subject: [llvm-commits] [llvm] r72706 - /llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Message-ID: <200906012313.n51NDh9i006183@zion.cs.uiuc.edu> Author: johannes Date: Mon Jun 1 18:13:42 2009 New Revision: 72706 URL: http://llvm.org/viewvc/llvm-project?rev=72706&view=rev Log: Comment grammaro/clarification. Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=72706&r1=72705&r2=72706&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Mon Jun 1 18:13:42 2009 @@ -1409,10 +1409,10 @@ // Put one value on stack. SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl); - // ADDC and ADDE produces two results. + // ADDC and ADDE produce two results. SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag); - // ADDE has three operands, the last one is a flag. + // ADDE has three operands, the last one is the carry bit. if (Op.getOpcode() == ISD::ADDE) return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1), NewVal, Op.getOperand(2)); From nlewycky at google.com Mon Jun 1 18:20:20 2009 From: nlewycky at google.com (Nick Lewycky) Date: Mon, 1 Jun 2009 16:20:20 -0700 Subject: [llvm-commits] [llvm] r72700 - in /llvm/trunk/tools/lto: LTOModule.cpp LTOModule.h In-Reply-To: References: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> Message-ID: 2009/6/1 Nick Kledzik > > On Jun 1, 2009, at 2:11 PM, Nick Lewycky wrote: > > 2009/6/1 Nick Kledzik > >> Author: kledzik >> Date: Mon Jun 1 15:33:09 2009 >> New Revision: 72700 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=72700&view=rev >> Log: >> libLTO needs to handle i386 magic objc class >> symbols >> Parse __OBJC data structures and synthesize magic .objc_ symbols. >> Also, alter mangler so that objc method names are readable. > > > Hi Nick, could you please elaborate on why exactly libLTO needs to change? > While I don't doubt that this fixes a bug, I can't see how this > language-specific logic could possibly belong in libLTO. > > It is not just language specific. It is only for Objective-C for ppc or > i386 on Darwin. My thinking was that the extra logic is only executed if > the GlobalVariable has a custom section with a specific name, that it would > not impact other languages or architectures. > That's a good policy. > This issue is that the old ObjC object format did some > strange contortions to avoid real linker symbols. For instance the ObjC > class data structure is allocated statically in the executable that defines > it. That data structures contains a pointer to it superclass. But instead > of just initializing that part of the struct to the address of its > superclass, and letting the static and dynamic linkers do the rest, the > runtime works by having that field point to a C-string that is the name of > the superclass on disk. At runtime the objc initialization swaps that > pointer out to point to the actual super class. As far as the linkers know > it is just a pointer to a string. But someone wanted the linker to issue > errors at build time if the superclass was not found. So they figured out a > way in mach-o object format to use an absolute symbol (.objc_class_name_Foo > = 0) and a floating reference ( .reference .objc_class_name_Bar) to trick > the linker into erroring when a class was missing. This patch emulates > that same behavior. > Tricky! I haven't thought it through fully but it sounds like you may be able to simulate some of this with the private linkage type which is described in LangRef as "This doesn't show up in any symbol table in the object file." At the very least, I'd appreciate a comment block in libLTO explaining why this stuff is there. Pretty much the same thing you wrote in the paragraph above. In addition, when processing mach-o files, the current Darwin linker ignores > those absolute and floating reference symbols, and instead parses the > __OBJC,__class data structures and infers those symbols. The libLTO.dylib > interfaces does not allow the linker to view the contents of a bitcode file, > just its symbols. So having libLTO synthesize those symbols fits well with > the Darwin linker. > > Would you prefer if the changes were wrapped in a isTargetDarwin() test? > It doesn't much matter because nobody else will call these new add* methods. (Right?) The mangler change has me a little concerned but I can wrap that in an isTargetDarwin() myself if I find that it is responsible for breaking things on me. Also, thanks for taking the time to write up the rationale! Nick > > -Nick > > > > > > >> >> >> Modified: >> llvm/trunk/tools/lto/LTOModule.cpp >> llvm/trunk/tools/lto/LTOModule.h >> >> Modified: llvm/trunk/tools/lto/LTOModule.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=72700&r1=72699&r2=72700&view=diff >> >> >> ============================================================================== >> --- llvm/trunk/tools/lto/LTOModule.cpp (original) >> +++ llvm/trunk/tools/lto/LTOModule.cpp Mon Jun 1 15:33:09 2009 >> @@ -14,6 +14,7 @@ >> >> #include "LTOModule.h" >> >> +#include "llvm/Constants.h" >> #include "llvm/Module.h" >> #include "llvm/ModuleProvider.h" >> #include "llvm/ADT/OwningPtr.h" >> @@ -176,11 +177,123 @@ >> } >> } >> >> -void LTOModule::addDefinedDataSymbol(GlobalValue* v, Mangler &mangler) >> +// get string that data pointer points to >> +bool LTOModule::objcClassNameFromExpression(Constant* c, std::string& >> name) >> +{ >> + if (ConstantExpr* ce = dyn_cast(c)) { > > > Is there any reason not to just assert on this? Will it ever really be > called on constants that aren't known to be objcClassNames? > > >> >> + Constant* op = ce->getOperand(0); >> + if (GlobalVariable* gvn = dyn_cast(op)) { >> + Constant* cn = gvn->getInitializer(); >> + if (ConstantArray* ca = dyn_cast(cn)) { >> + if ( ca->isCString() ) { >> + name = ".objc_class_name_" + ca->getAsString(); >> + return true; >> + } >> + } >> + } >> + } >> + return false; >> +} >> + >> +// parse i386/ppc ObjC class data structure >> +void LTOModule::addObjCClass(GlobalVariable* clgv) >> +{ >> + if (ConstantStruct* c = >> dyn_cast(clgv->getInitializer())) { > > > Here again, perhaps it should just assert that this is true? > > >> >> + // second slot in __OBJC,__class is pointer to superclass name >> + std::string superclassName; >> + if ( objcClassNameFromExpression(c->getOperand(1), >> superclassName) ) { >> + NameAndAttributes info; >> + if ( _undefines.find(superclassName.c_str()) == >> _undefines.end() ) { >> + const char* symbolName = >> ::strdup(superclassName.c_str()); >> + info.name = ::strdup(symbolName); >> + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; >> + // string is owned by _undefines >> + _undefines[info.name] = info; > > > Perhaps the non-libLTO side of the Apple linker should ignore symbols it > knows are objC specific? Or perhaps you could run a domain-specific LLVM > pass which would delete these globals as needed? If somehow you need them to > exist but still be marked undefined, perhaps libLTO should expose an > interface for marking symbols undefined instead of an interface specific to > Apple's implementation of the objC language? > > It just seems like this is breaking encapsulation, the linker has linking > rules that don't much care what the source language was. > > Nick > > >> >> + } >> + } >> + // third slot in __OBJC,__class is pointer to class name >> + std::string className; >> + if ( objcClassNameFromExpression(c->getOperand(2), className) ) >> { >> + const char* symbolName = ::strdup(className.c_str()); >> + NameAndAttributes info; >> + info.name = symbolName; >> + info.attributes = (lto_symbol_attributes) >> + (LTO_SYMBOL_PERMISSIONS_DATA | >> + LTO_SYMBOL_DEFINITION_REGULAR | >> + LTO_SYMBOL_SCOPE_DEFAULT); >> + _symbols.push_back(info); >> + _defines[info.name] = 1; >> + } >> + } >> +} >> + >> + >> +// parse i386/ppc ObjC category data structure >> +void LTOModule::addObjCCategory(GlobalVariable* clgv) >> +{ >> + if (ConstantStruct* c = >> dyn_cast(clgv->getInitializer())) { >> + // second slot in __OBJC,__category is pointer to target class >> name >> + std::string targetclassName; >> + if ( objcClassNameFromExpression(c->getOperand(1), >> targetclassName) ) { >> + NameAndAttributes info; >> + if ( _undefines.find(targetclassName.c_str()) == >> _undefines.end() ){ >> + const char* symbolName = >> ::strdup(targetclassName.c_str()); >> + info.name = ::strdup(symbolName); >> + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; >> + // string is owned by _undefines >> + _undefines[info.name] = info; >> + } >> + } >> + } >> +} >> + >> + >> +// parse i386/ppc ObjC class list data structure >> +void LTOModule::addObjCClassRef(GlobalVariable* clgv) >> +{ >> + std::string targetclassName; >> + if ( objcClassNameFromExpression(clgv->getInitializer(), >> targetclassName) ){ >> + NameAndAttributes info; >> + if ( _undefines.find(targetclassName.c_str()) == _undefines.end() >> ) { >> + const char* symbolName = ::strdup(targetclassName.c_str()); >> + info.name = ::strdup(symbolName); >> + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; >> + // string is owned by _undefines >> + _undefines[info.name] = info; >> + } >> + } >> +} >> + >> + >> +void LTOModule::addDefinedDataSymbol(GlobalValue* v, Mangler& mangler) >> { >> // add to list of defined symbols >> addDefinedSymbol(v, mangler, false); >> >> + // special case i386/ppc ObjC data structures in magic sections >> + if ( v->hasSection() ) { >> + // special case if this data blob is an ObjC class definition >> + if ( v->getSection().compare(0, 15, "__OBJC,__class,") == 0 ) { >> + if (GlobalVariable* gv = dyn_cast(v)) { >> + addObjCClass(gv); >> + } >> + } >> + >> + // special case if this data blob is an ObjC category definition >> + else if ( v->getSection().compare(0, 18, "__OBJC,__category,") == >> 0 ) { >> + if (GlobalVariable* gv = dyn_cast(v)) { >> + addObjCCategory(gv); >> + } >> + } >> + >> + // special case if this data blob is the list of referenced >> classes >> + else if ( v->getSection().compare(0, 18, "__OBJC,__cls_refs,") == >> 0 ) { >> + if (GlobalVariable* gv = dyn_cast(v)) { >> + addObjCClassRef(gv); >> + } >> + } >> + } >> + >> // add external symbols referenced by this data. >> for (unsigned count = 0, total = v->getNumOperands(); >> count != total; ++count) { >> @@ -192,9 +305,13 @@ >> void LTOModule::addDefinedSymbol(GlobalValue* def, Mangler &mangler, >> bool isFunction) >> { >> + // ignore all llvm.* symbols >> + if ( strncmp(def->getNameStart(), "llvm.", 5) == 0 ) >> + return; >> + >> // string is owned by _defines >> const char* symbolName = ::strdup(mangler.getValueName(def).c_str()); >> - >> + >> // set alignment part log2() can have rounding errors >> uint32_t align = def->getAlignment(); >> uint32_t attr = align ? CountTrailingZeros_32(def->getAlignment()) : >> 0; >> @@ -241,25 +358,28 @@ >> } >> >> void LTOModule::addAsmGlobalSymbol(const char *name) { >> - // string is owned by _defines >> - const char *symbolName = ::strdup(name); >> - uint32_t attr = LTO_SYMBOL_DEFINITION_REGULAR; >> - attr |= LTO_SYMBOL_SCOPE_DEFAULT; >> - >> - // add to table of symbols >> - NameAndAttributes info; >> - info.name = symbolName; >> - info.attributes = (lto_symbol_attributes)attr; >> - _symbols.push_back(info); >> - _defines[info.name] = 1; >> + // only add new define if not already defined >> + if ( _defines.count(name, &name[strlen(name)+1]) == 0 ) >> + return; >> + >> + // string is owned by _defines >> + const char *symbolName = ::strdup(name); >> + uint32_t attr = LTO_SYMBOL_DEFINITION_REGULAR; >> + attr |= LTO_SYMBOL_SCOPE_DEFAULT; >> + NameAndAttributes info; >> + info.name = symbolName; >> + info.attributes = (lto_symbol_attributes)attr; >> + _symbols.push_back(info); >> + _defines[info.name] = 1; >> } >> >> void LTOModule::addPotentialUndefinedSymbol(GlobalValue* decl, Mangler >> &mangler) >> { >> - const char* name = mangler.getValueName(decl).c_str(); >> // ignore all llvm.* symbols >> - if ( strncmp(name, "llvm.", 5) == 0 ) >> - return; >> + if ( strncmp(decl->getNameStart(), "llvm.", 5) == 0 ) >> + return; >> + >> + const char* name = mangler.getValueName(decl).c_str(); >> >> // we already have the symbol >> if (_undefines.find(name) != _undefines.end()) >> @@ -306,6 +426,14 @@ >> >> // Use mangler to add GlobalPrefix to names to match linker names. >> Mangler mangler(*_module, >> _target->getTargetAsmInfo()->getGlobalPrefix()); >> + // add chars used in ObjC method names so method names aren't >> mangled >> + mangler.markCharAcceptable('['); >> + mangler.markCharAcceptable(']'); >> + mangler.markCharAcceptable('('); >> + mangler.markCharAcceptable(')'); >> + mangler.markCharAcceptable('-'); >> + mangler.markCharAcceptable('+'); >> + mangler.markCharAcceptable(' '); >> >> // add functions >> for (Module::iterator f = _module->begin(); f != _module->end(); >> ++f) { >> >> Modified: llvm/trunk/tools/lto/LTOModule.h >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.h?rev=72700&r1=72699&r2=72700&view=diff >> >> >> ============================================================================== >> --- llvm/trunk/tools/lto/LTOModule.h (original) >> +++ llvm/trunk/tools/lto/LTOModule.h Mon Jun 1 15:33:09 2009 >> @@ -77,13 +77,19 @@ >> void addDefinedDataSymbol(llvm::GlobalValue* v, >> llvm::Mangler >> &mangler); >> void addAsmGlobalSymbol(const char *); >> + void addObjCClass(llvm::GlobalVariable* clgv); >> + void addObjCCategory(llvm::GlobalVariable* clgv); >> + void addObjCClassRef(llvm::GlobalVariable* clgv); >> + bool objcClassNameFromExpression(llvm::Constant* >> c, >> + std::string& name); >> + >> static bool isTargetMatch(llvm::MemoryBuffer* memBuffer, >> const char* >> triplePrefix); >> - >> + >> static LTOModule* makeLTOModule(llvm::MemoryBuffer* buffer, >> std::string& >> errMsg); >> static llvm::MemoryBuffer* makeBuffer(const void* mem, size_t length); >> - >> + >> typedef llvm::StringMap StringSet; >> >> struct NameAndAttributes { >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090601/cb337dc5/attachment.html From dalej at apple.com Mon Jun 1 18:27:21 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 01 Jun 2009 23:27:21 -0000 Subject: [llvm-commits] [llvm] r72707 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/X86/ utils/TableGen/ Message-ID: <200906012327.n51NRMqY006632@zion.cs.uiuc.edu> Author: johannes Date: Mon Jun 1 18:27:20 2009 New Revision: 72707 URL: http://llvm.org/viewvc/llvm-project?rev=72707&view=rev Log: Make the implicit inputs and outputs of target-independent ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust all target-independent code to use this format. Most targets will still produce a Flag-setting target-dependent version when selection is done. X86 is converted to use i32 instead, which means TableGen needs to produce different code in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit in xxxInstrInfo, currently set only for X86; in principle this is temporary and should go away when all other targets have been converted. All relevant X86 instruction patterns are modified to represent setting and using EFLAGS explicitly. The same can be done on other targets. The immediate behavior change is that an ADC/ADD pair are no longer tightly coupled in the X86 scheduler; they can be separated by instructions that don't clobber the flags (MOV). I will soon add some peephole optimizations based on using other instructions that set the flags to feed into ADC. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/include/llvm/Target/Target.td llvm/trunk/include/llvm/Target/TargetSelectionDAG.td llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86Instr64bit.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/CodeGenTarget.h llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Jun 1 18:27:20 2009 @@ -324,6 +324,14 @@ return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, getRegister(Reg, N.getValueType()), N); } + // This version of getCopyToReg has the register (and its type) as an + // explicit output. + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, MVT VT, unsigned Reg, + SDValue N) { + SDVTList VTs = getVTList(MVT::Other, VT); + SDValue Ops[] = { Chain, getRegister(Reg, VT), N}; + return getNode(ISD::CopyToReg, dl, VTs, Ops, 3); + } // This version of the getCopyToReg method takes an extra operand, which // indicates that there is potentially an incoming flag value (if Flag is not Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Jun 1 18:27:20 2009 @@ -242,14 +242,11 @@ // remainder result. SDIVREM, UDIVREM, - // CARRY_FALSE - This node is used when folding other nodes, - // like ADDC/SUBC, which indicate the carry result is always false. - CARRY_FALSE, - // Carry-setting nodes for multiple precision addition and subtraction. // These nodes take two operands of the same value type, and produce two // results. The first result is the normal add or sub result, the second - // result is the carry flag result. + // result is the carry flag result (type i1 or whatever it got expanded to + // for the target, value 0 or 1). ADDC, SUBC, // Carry-using nodes for multiple precision addition and subtraction. These @@ -258,7 +255,8 @@ // produce two results; the normal result of the add or sub, and the output // carry flag. These nodes both read and write a carry flag to allow them // to them to be chained together for add and sub of arbitrarily large - // values. + // values. The carry flag (input and output) has type i1 or whatever it + // got expanded to for the target, and has value 0 or 1. ADDE, SUBE, // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Mon Jun 1 18:27:20 2009 @@ -326,6 +326,11 @@ // Sparc manual specifies its instructions in the format [31..0] (big), while // PowerPC specifies them using the format [0..31] (little). bit isLittleEndianEncoding = 0; + + // Targets that can support the HasI1 argument on ADDC and ADDE, rather than + // Flag, have this bit set. This is transitional and should go away when all + // targets have been switched over. + bit supportsHasI1 = 0; } // Standard Instructions. Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Mon Jun 1 18:27:20 2009 @@ -216,6 +216,8 @@ def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand +def SDNPInI1 : SDNodeProperty; // Read an extra I1 operand +def SDNPOutI1 : SDNodeProperty; // Write an extra I1 result //===----------------------------------------------------------------------===// // Selection DAG Node definitions. @@ -289,13 +291,13 @@ def xor : SDNode<"ISD::XOR" , SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, - [SDNPCommutative, SDNPOutFlag]>; + [SDNPCommutative, SDNPOutI1]>; def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, - [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; + [SDNPCommutative, SDNPInI1, SDNPOutI1]>; def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, - [SDNPOutFlag]>; + [SDNPOutI1]>; def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, - [SDNPOutFlag, SDNPInFlag]>; + [SDNPInI1, SDNPOutI1]>; def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jun 1 18:27:20 2009 @@ -1085,8 +1085,7 @@ // If the flag result is dead, turn this into an ADD. if (N->hasNUsesOfValue(0, 1)) return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), - DAG.getNode(ISD::CARRY_FALSE, - N->getDebugLoc(), MVT::Flag)); + DAG.getConstant(0, N->getValueType(1))); // canonicalize constant to RHS. if (N0C && !N1C) @@ -1094,10 +1093,9 @@ // fold (addc x, 0) -> x + no carry out if (N1C && N1C->isNullValue()) - return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, - N->getDebugLoc(), MVT::Flag)); + return CombineTo(N, N0, DAG.getConstant(0, N1.getValueType())); - // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. + // fold (addc a, b) -> (or a, b), 0 iff a and b share no bits. APInt LHSZero, LHSOne; APInt RHSZero, RHSOne; APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); @@ -1111,8 +1109,7 @@ if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), - DAG.getNode(ISD::CARRY_FALSE, - N->getDebugLoc(), MVT::Flag)); + DAG.getConstant(0, N1.getValueType())); } return SDValue(); @@ -1131,8 +1128,9 @@ N1, N0, CarryIn); // fold (adde x, y, false) -> (addc x, y) - if (CarryIn.getOpcode() == ISD::CARRY_FALSE) - return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); + if (ConstantSDNode *N2C = dyn_cast(CarryIn)) + if (N2C->getAPIntValue()==0) + return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); return SDValue(); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Jun 1 18:27:20 2009 @@ -98,6 +98,10 @@ case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; case ISD::SMULO: case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; + case ISD::ADDC: + case ISD::SUBC: Res = PromoteIntRes_ADDSUBC(N, ResNo); break; + case ISD::ADDE: + case ISD::SUBE: Res = PromoteIntRes_ADDSUBE(N, ResNo); break; case ISD::ATOMIC_LOAD_ADD: case ISD::ATOMIC_LOAD_SUB: @@ -121,6 +125,35 @@ SetPromotedInteger(SDValue(N, ResNo), Res); } +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBC(SDNode *N, unsigned ResNo) { + // Only the carry bit result is expected to be promoted. + assert(ResNo == 1 && "Only carry bit result promotion currently supported!"); + return PromoteIntRes_Overflow(N); +} + +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBE(SDNode *N, unsigned ResNo) { + // Only the carry bit result is expected to be promoted. + assert(ResNo == 1 && "Only carry bit result promotion currently supported!"); + // This is a ternary operator, so clone a slightly modified + // PromoteIntRes_Overflow here (this is the only client). + if (ResNo == 1) { + // Simply change the return type of the boolean result. + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); + MVT ValueVTs[] = { N->getValueType(0), NVT }; + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; + SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), + DAG.getVTList(ValueVTs, 2), Ops, 3); + + // Modified the sum result - switch anything that used the old sum to use + // the new one. + ReplaceValueWith(SDValue(N, 0), Res); + + return SDValue(Res.getNode(), 1); + } + assert(0 && "Do not know how to promote this operator!"); + abort(); +} + SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { // Sign-extend the new bits, and continue the assertion. SDValue Op = SExtPromotedInteger(N->getOperand(0)); @@ -419,7 +452,7 @@ return Res; } -/// Promote the overflow flag of an overflowing arithmetic node. +/// Promote the overflow or carry result of an overflowing arithmetic node. SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { // Simply change the return type of the boolean result. MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); @@ -666,6 +699,8 @@ assert(0 && "Do not know how to promote this operator's operand!"); abort(); + case ISD::ADDE: + case ISD::SUBE: Res = PromoteIntOp_ADDSUBE(N, OpNo); break; case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; @@ -743,6 +778,13 @@ } } +SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBE(SDNode *N, unsigned OpNo) { + assert(OpNo == 2 && "Don't know how to promote this operand!"); + return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), + N->getOperand(1), + GetPromotedInteger(N->getOperand(2))); +} + SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { SDValue Op = GetPromotedInteger(N->getOperand(0)); return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); @@ -1063,7 +1105,7 @@ TLI.isOperationLegalOrCustom(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) { // Emit this X << 1 as X+X. - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); SDValue LoOps[2] = { InL, InL }; Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; @@ -1299,7 +1341,7 @@ TLI.getTypeToExpandTo(NVT)); if (hasCarry) { - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); if (N->getOpcode() == ISD::ADD) { Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); @@ -1344,7 +1386,7 @@ DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), LHSL, LHSH); GetExpandedInteger(N->getOperand(1), RHSL, RHSH); - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); SDValue LoOps[2] = { LHSL, RHSL }; SDValue HiOps[3] = { LHSH, RHSH }; @@ -1358,8 +1400,8 @@ Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); } - // Legalized the flag result - switch anything that used the old flag to - // use the new one. + // Legalized the second result (carry bit) - switch anything that used the + // result to use the new one. ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); } @@ -1370,7 +1412,7 @@ DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), LHSL, LHSH); GetExpandedInteger(N->getOperand(1), RHSL, RHSH); - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; SDValue HiOps[3] = { LHSH, RHSH }; @@ -1378,8 +1420,8 @@ HiOps[2] = Lo.getValue(1); Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); - // Legalized the flag result - switch anything that used the old flag to - // use the new one. + // Legalized the second result (carry bit) - switch anything that used the + // result to use the new one. ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Jun 1 18:27:20 2009 @@ -242,6 +242,8 @@ // Integer Result Promotion. void PromoteIntegerResult(SDNode *N, unsigned ResNo); + SDValue PromoteIntRes_ADDSUBC(SDNode *N, unsigned ResNo); + SDValue PromoteIntRes_ADDSUBE(SDNode *N, unsigned ResNo); SDValue PromoteIntRes_AssertSext(SDNode *N); SDValue PromoteIntRes_AssertZext(SDNode *N); SDValue PromoteIntRes_Atomic1(AtomicSDNode *N); @@ -278,6 +280,7 @@ // Integer Operand Promotion. bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo); + SDValue PromoteIntOp_ADDSUBE(SDNode *N, unsigned OpNo); SDValue PromoteIntOp_ANY_EXTEND(SDNode *N); SDValue PromoteIntOp_BIT_CONVERT(SDNode *N); SDValue PromoteIntOp_BUILD_PAIR(SDNode *N); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Mon Jun 1 18:27:20 2009 @@ -268,6 +268,13 @@ unsigned N = Node->getNumOperands(); while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) --N; + // Skip hard registers set as a side effect (i.e. not result 0). + while (N && Node->getOperand(N - 1).getOpcode() == ISD::CopyToReg && + Node->getOperand(N-1).getResNo() != 0 && + !TargetRegisterInfo::isVirtualRegister( + dyn_cast(Node->getOperand(N-1).getOperand(1)) + ->getReg())) + --N; if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) --N; // Ignore chain if it exists. return N; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 1 18:27:20 2009 @@ -5257,7 +5257,6 @@ case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; - case ISD::CARRY_FALSE: return "carry_false"; case ISD::ADDC: return "addc"; case ISD::ADDE: return "adde"; case ISD::SADDO: return "saddo"; Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jun 1 18:27:20 2009 @@ -190,6 +190,28 @@ setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); } + // ADDE and SUBE are lowered to local versions that contain EFLAGS explicitly. + // ADDC and SUBC are lowered to local versions so EFLAGS will be an i32 + // rather than the Flag used by the generic patterns. + setOperationAction(ISD::ADDC , MVT::i8 , Custom); + setOperationAction(ISD::ADDC , MVT::i16 , Custom); + setOperationAction(ISD::ADDC , MVT::i32 , Custom); + setOperationAction(ISD::SUBC , MVT::i8 , Custom); + setOperationAction(ISD::SUBC , MVT::i16 , Custom); + setOperationAction(ISD::SUBC , MVT::i32 , Custom); + setOperationAction(ISD::ADDE , MVT::i8 , Custom); + setOperationAction(ISD::ADDE , MVT::i16 , Custom); + setOperationAction(ISD::ADDE , MVT::i32 , Custom); + setOperationAction(ISD::SUBE , MVT::i8 , Custom); + setOperationAction(ISD::SUBE , MVT::i16 , Custom); + setOperationAction(ISD::SUBE , MVT::i32 , Custom); + if (Subtarget->is64Bit()) { + setOperationAction(ISD::ADDC , MVT::i64 , Custom); + setOperationAction(ISD::SUBC , MVT::i64 , Custom); + setOperationAction(ISD::ADDE , MVT::i64 , Custom); + setOperationAction(ISD::SUBE , MVT::i64 , Custom); + } + // Scalar integer divide and remainder are lowered to use operations that // produce two results, to match the available instructions. This exposes // the two-result form to trivial CSE, which is able to combine x/y and x%y @@ -6475,6 +6497,21 @@ return Sum; } +SDValue X86TargetLowering::LowerADDSUBE(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); + return DAG.getNode(Op.getOpcode()==ISD::ADDE ? X86ISD::ADDE : X86ISD::SUBE, + dl, VTs, Op.getOperand(0), Op.getOperand(1), + Op.getOperand(2).getValue(1)); +} + +SDValue X86TargetLowering::LowerADDSUBC(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); + return DAG.getNode(Op.getOpcode()==ISD::ADDC ? X86ISD::ADD : X86ISD::SUB, + dl, VTs, Op.getOperand(0), Op.getOperand(1)); +} + SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { MVT T = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); @@ -6543,6 +6580,10 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); + case ISD::ADDC: + case ISD::SUBC: return LowerADDSUBC(Op,DAG); + case ISD::ADDE: + case ISD::SUBE: return LowerADDSUBE(Op,DAG); case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); @@ -6791,6 +6832,10 @@ case X86ISD::INC: return "X86ISD::INC"; case X86ISD::DEC: return "X86ISD::DEC"; case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; + case X86ISD::ADDE: return "X86ISD::ADDE"; + case X86ISD::SUBE: return "X86ISD::SUBE"; + case X86ISD::ADDC: return "X86ISD::ADDC"; + case X86ISD::SUBC: return "X86ISD::SUBC"; } } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Jun 1 18:27:20 2009 @@ -243,6 +243,14 @@ ADD, SUB, SMUL, UMUL, INC, DEC, + // ADDC, SUBC - Arithmetic operations setting carry bit. The normal + // arithmetic operations do this, but they represent it as Flag, and + // we want the i32 EFLAGS register here. + ADDC, SUBC, + + // ADDE, SUBE - Arithmetic operations with extra FLAGS (EFLAGS) inputs. + ADDE, SUBE, + // MUL_IMM - X86 specific multiply by immediate. MUL_IMM }; @@ -576,7 +584,9 @@ std::pair FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool isSigned); - + + SDValue LowerADDSUBC(SDValue Op, SelectionDAG &DAG); + SDValue LowerADDSUBE(SDValue Op, SelectionDAG &DAG); SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Mon Jun 1 18:27:20 2009 @@ -383,31 +383,52 @@ let Uses = [EFLAGS] in { let isTwoAddress = 1 in { let isCommutable = 1 in -def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), +def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>; + [(set GR64:$dst, + (X86adde_flag GR64:$src1, GR64:$src2, EFLAGS)), + (implicit EFLAGS)]>; -def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), +def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), + (ins GR64:$src1, i64mem:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>; + [(set GR64:$dst, + (X86adde_flag GR64:$src1, (load addr:$src2), EFLAGS)), + (implicit EFLAGS)]>; -def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), +def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), + (ins GR64:$src1, i64i8imm:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>; -def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), + [(set GR64:$dst, + (X86adde_flag GR64:$src1, i64immSExt8:$src2, EFLAGS)), + (implicit EFLAGS)]>; +def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), + (ins GR64:$src1, i64i32imm:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>; + [(set GR64:$dst, + (X86adde_flag GR64:$src1, i64immSExt32:$src2, + EFLAGS)), + (implicit EFLAGS)]>; } // isTwoAddress def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>; + [(store (X86adde_flag (load addr:$dst), GR64:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; + [(store (X86adde_flag (load addr:$dst), i64immSExt8:$src2, + EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; + [(store (X86adde_flag (load addr:$dst), i64immSExt8:$src2, + EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; } // Uses = [EFLAGS] let isTwoAddress = 1 in { @@ -456,31 +477,52 @@ let Uses = [EFLAGS] in { let isTwoAddress = 1 in { -def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), +def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>; + [(set GR64:$dst, + (X86sube_flag GR64:$src1, GR64:$src2, EFLAGS)), + (implicit EFLAGS)]>; -def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), +def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), + (ins GR64:$src1, i64mem:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>; + [(set GR64:$dst, + (X86sube_flag GR64:$src1, (load addr:$src2), EFLAGS)), + (implicit EFLAGS)]>; -def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), +def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), + (ins GR64:$src1, i64i8imm:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>; -def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), + [(set GR64:$dst, + (X86sube_flag GR64:$src1, i64immSExt8:$src2, EFLAGS)), + (implicit EFLAGS)]>; +def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), + (ins GR64:$src1, i64i32imm:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>; + [(set GR64:$dst, + (X86sube_flag GR64:$src1, i64immSExt32:$src2, + EFLAGS)), + (implicit EFLAGS)]>; } // isTwoAddress def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>; + [(store (X86sube_flag (load addr:$dst), GR64:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; + [(store (X86sube_flag (load addr:$dst), i64immSExt8:$src2, + EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>; + [(store (X86sube_flag (load addr:$dst), i64immSExt32:$src2, + EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; } // Uses = [EFLAGS] } // Defs = [EFLAGS] Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Jun 1 18:27:20 2009 @@ -34,6 +34,11 @@ [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>]>; +// Unary and binary operators that both read and write EFLAGS as a side-effect. +def SDTBinaryArithRWFlags : SDTypeProfile<1, 3, + [SDTCisInt<0>, SDTCisSameAs<0, 1>, + SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; + def SDTX86BrCond : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; @@ -156,6 +161,8 @@ def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>; def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; +def X86adde_flag : SDNode<"X86ISD::ADDE", SDTBinaryArithRWFlags, [SDNPInI1]>; +def X86sube_flag : SDNode<"X86ISD::SUBE", SDTBinaryArithRWFlags, [SDNPInI1]>; def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; @@ -2274,81 +2281,127 @@ let Uses = [EFLAGS] in { let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y -def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), +def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), + (ins GR8:$src1, GR8:$src2), "adc{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>; + [(set GR8:$dst, (X86adde_flag GR8:$src1, GR8:$src2, EFLAGS)), + (implicit EFLAGS)]>; def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize; + [(set GR16:$dst, + (X86adde_flag GR16:$src1, GR16:$src2, EFLAGS)), + (implicit EFLAGS)]>, + OpSize; def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; + [(set GR32:$dst, + (X86adde_flag GR32:$src1, GR32:$src2, EFLAGS)), + (implicit EFLAGS)]>; } def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2), "adc{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>; + [(set GR8:$dst, + (X86adde_flag GR8:$src1, (load addr:$src2), EFLAGS)), + (implicit EFLAGS)]>; def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>, + [(set GR16:$dst, + (X86adde_flag GR16:$src1, (load addr:$src2), EFLAGS)), + (implicit EFLAGS)]>, OpSize; def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>; -def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), + [(set GR32:$dst, + (X86adde_flag GR32:$src1, (load addr:$src2), EFLAGS)), + (implicit EFLAGS)]>; +def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), + (ins GR8:$src1, i8imm:$src2), "adc{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>; + [(set GR8:$dst, + (X86adde_flag GR8:$src1, imm:$src2, EFLAGS)), + (implicit EFLAGS)]>; def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize; + [(set GR16:$dst, + (X86adde_flag GR16:$src1, imm:$src2, EFLAGS)), + (implicit EFLAGS)]>, OpSize; def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>, - OpSize; + [(set GR16:$dst, + (X86adde_flag GR16:$src1, i16immSExt8:$src2, EFLAGS)), + (implicit EFLAGS)]>, OpSize; def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; + [(set GR32:$dst, + (X86adde_flag GR32:$src1, imm:$src2, EFLAGS)), + (implicit EFLAGS)]>; def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>; + [(set GR32:$dst, + (X86adde_flag GR32:$src1, i32immSExt8:$src2, EFLAGS)), + (implicit EFLAGS)]>; let isTwoAddress = 0 in { - def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), + def ADC8mr : I<0x10, MRMDestMem, (outs), + (ins i8mem:$dst, GR8:$src2), "adc{b}\t{$src2, $dst|$dst, $src2}", - [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>; - def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), + [(store (X86adde_flag (load addr:$dst), GR8:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; + def ADC16mr : I<0x11, MRMDestMem, (outs), + (ins i16mem:$dst, GR16:$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>, - OpSize; - def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), + [(store (X86adde_flag (load addr:$dst), GR16:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>, OpSize; + def ADC32mr : I<0x11, MRMDestMem, (outs), + (ins i32mem:$dst, GR32:$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>; - def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2), + [(store (X86adde_flag (load addr:$dst), GR32:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; + def ADC8mi : Ii8<0x80, MRM2m, (outs), + (ins i8mem:$dst, i8imm:$src2), "adc{b}\t{$src2, $dst|$dst, $src2}", - [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; - def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2), + [(store (X86adde_flag (loadi8 addr:$dst), imm:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; + def ADC16mi : Ii16<0x81, MRM2m, (outs), + (ins i16mem:$dst, i16imm:$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, - OpSize; - def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2), + [(store (X86adde_flag (loadi16 addr:$dst), imm:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>, OpSize; + def ADC16mi8 : Ii8<0x83, MRM2m, (outs), + (ins i16mem:$dst, i16i8imm :$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, - OpSize; - def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2), + [(store (X86adde_flag (load addr:$dst), i16immSExt8:$src2, + EFLAGS), + addr:$dst), + (implicit EFLAGS)]>, OpSize; + def ADC32mi : Ii32<0x81, MRM2m, (outs), + (ins i32mem:$dst, i32imm:$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; - def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2), + [(store (X86adde_flag (loadi32 addr:$dst), imm:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; + def ADC32mi8 : Ii8<0x83, MRM2m, (outs), + (ins i32mem:$dst, i32i8imm:$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; -} + [(store (X86adde_flag (load addr:$dst), i32immSExt8:$src2, + EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; + } } // Uses = [EFLAGS] // Register-Register Subtraction @@ -2453,77 +2506,115 @@ def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), "sbb{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>; + [(set GR8:$dst, (X86sube_flag GR8:$src1, GR8:$src2, EFLAGS)), + (implicit EFLAGS)]>; def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize; + [(set GR16:$dst, + (X86sube_flag GR16:$src1, GR16:$src2, EFLAGS)), + (implicit EFLAGS)]>, OpSize; def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; + [(set GR32:$dst, + (X86sube_flag GR32:$src1, GR32:$src2, EFLAGS)), + (implicit EFLAGS)]>; let isTwoAddress = 0 in { def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), "sbb{b}\t{$src2, $dst|$dst, $src2}", - [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>; + [(store (X86sube_flag (load addr:$dst), GR8:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>, + [(store (X86sube_flag (load addr:$dst), GR16:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>, OpSize; def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>; + [(store (X86sube_flag (load addr:$dst), GR32:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2), "sbb{b}\t{$src2, $dst|$dst, $src2}", - [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; + [(store (X86sube_flag (loadi8 addr:$dst), imm:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, + [(store (X86sube_flag (loadi16 addr:$dst), imm:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>, OpSize; def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, + [(store (X86sube_flag (load addr:$dst), i16immSExt8:$src2, + EFLAGS), + addr:$dst), + (implicit EFLAGS)]>, OpSize; def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; + [(store (X86sube_flag (loadi32 addr:$dst), imm:$src2, EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; + [(store (X86sube_flag (load addr:$dst), i32immSExt8:$src2, + EFLAGS), + addr:$dst), + (implicit EFLAGS)]>; } def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2), "sbb{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>; + [(set GR8:$dst, + (X86sube_flag GR8:$src1, (load addr:$src2), EFLAGS)), + (implicit EFLAGS)]>; def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>, + [(set GR16:$dst, + (X86sube_flag GR16:$src1, (load addr:$src2), EFLAGS)), + (implicit EFLAGS)]>, OpSize; def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>; + [(set GR32:$dst, + (X86sube_flag GR32:$src1, (load addr:$src2), EFLAGS)), + (implicit EFLAGS)]>; def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), "sbb{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>; + [(set GR8:$dst, + (X86sube_flag GR8:$src1, imm:$src2, EFLAGS)), + (implicit EFLAGS)]>; def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize; + [(set GR16:$dst, + (X86sube_flag GR16:$src1, imm:$src2, EFLAGS)), + (implicit EFLAGS)]>, OpSize; def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>, - OpSize; + [(set GR16:$dst, + (X86sube_flag GR16:$src1, i16immSExt8:$src2, EFLAGS)), + (implicit EFLAGS)]>, OpSize; def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>; + [(set GR32:$dst, + (X86sube_flag GR32:$src1, imm:$src2, EFLAGS)), + (implicit EFLAGS)]>; def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>; + [(set GR32:$dst, + (X86sube_flag GR32:$src1, i32immSExt8:$src2, EFLAGS)), + (implicit EFLAGS)]>; } // Uses = [EFLAGS] } // Defs = [EFLAGS] Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Mon Jun 1 18:27:20 2009 @@ -399,9 +399,13 @@ } else if (PropList[i]->getName() == "SDNPHasChain") { Properties |= 1 << SDNPHasChain; } else if (PropList[i]->getName() == "SDNPOutFlag") { - Properties |= 1 << SDNPOutFlag; + Properties |= 1 << SDNPOutFlag; + assert(!(Properties & (1<getName() == "SDNPInFlag") { Properties |= 1 << SDNPInFlag; + assert(!(Properties & (1<getName() == "SDNPOptInFlag") { Properties |= 1 << SDNPOptInFlag; } else if (PropList[i]->getName() == "SDNPMayStore") { @@ -412,6 +416,14 @@ Properties |= 1 << SDNPSideEffect; } else if (PropList[i]->getName() == "SDNPMemOperand") { Properties |= 1 << SDNPMemOperand; + } else if (PropList[i]->getName() == "SDNPInI1") { + Properties |= 1 << SDNPInI1; + assert(!(Properties & (1<getName() == "SDNPOutI1") { + Properties |= 1 << SDNPOutI1; + assert(!(Properties & (1<getName() << "' on node '" << R->getName() << "'!\n"; Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Jun 1 18:27:20 2009 @@ -385,6 +385,13 @@ return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); } +/// supportsHasI1 - Return whether this target supports the implicit I1, +/// rather than Flags, for ADDC/ADDE +/// +bool CodeGenTarget::supportsHasI1() const { + return getInstructionSet()->getValueAsBit("supportsHasI1"); +} + //===----------------------------------------------------------------------===// // ComplexPattern implementation // Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.h (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.h Mon Jun 1 18:27:20 2009 @@ -43,7 +43,9 @@ SDNPMayLoad, SDNPMayStore, SDNPSideEffect, - SDNPMemOperand + SDNPMemOperand, + SDNPInI1, + SDNPOutI1 }; // ComplexPattern attributes. @@ -209,10 +211,12 @@ void getInstructionsByEnumValue(std::vector &NumberedInstructions); - /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]? /// bool isLittleEndianEncoding() const; + + /// supportsHasI1 - does this target understand HasI1 for ADDE and ADDC? + bool supportsHasI1() const; }; /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=72707&r1=72706&r2=72707&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Jun 1 18:27:20 2009 @@ -670,7 +670,8 @@ HasChain = true; FoldedChains.push_back(std::make_pair(RootName, CInfo.getNumResults())); } - if (NodeHasProperty(Child, SDNPOutFlag, CGP)) { + if (NodeHasProperty(Child, SDNPOutFlag, CGP) || + NodeHasProperty(Child, SDNPOutI1, CGP)) { assert(FoldedFlag.first == "" && FoldedFlag.second == 0 && "Pattern folded multiple nodes which produce flags?"); FoldedFlag = std::make_pair(RootName, @@ -969,6 +970,10 @@ PatternHasProperty(Pattern, SDNPInFlag, CGP); bool NodeHasOutFlag = isRoot && PatternHasProperty(Pattern, SDNPOutFlag, CGP); + bool NodeHasInI1 = isRoot && + PatternHasProperty(Pattern, SDNPInI1, CGP); + bool NodeHasOutI1 = isRoot && + PatternHasProperty(Pattern, SDNPOutI1, CGP); bool NodeHasChain = InstPatNode && PatternHasProperty(InstPatNode, SDNPHasChain, CGP); bool InputHasChain = isRoot && @@ -1054,10 +1059,13 @@ // Emit all the chain and CopyToReg stuff. bool ChainEmitted = NodeHasChain; - if (NodeHasInFlag || HasImpInputs) + // InFlag and InI1 cannot both be set (checked in + // CodeGenDAGPatterns), so use the same variables for both. + if (NodeHasInFlag || HasImpInputs || NodeHasInI1) EmitInFlagSelectCode(Pattern, "N", ChainEmitted, InFlagDecled, ResNodeDecled, true); - if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs) { + if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs || + NodeHasInI1) { if (!InFlagDecled) { emitCode("SDValue InFlag(0, 0);"); InFlagDecled = true; @@ -1113,7 +1121,7 @@ } if (NodeHasChain) Code += ", MVT::Other"; - if (NodeHasOutFlag) + if (NodeHasOutFlag || (NodeHasOutI1 && !CGT.supportsHasI1())) Code += ", MVT::Flag"; // Inputs. @@ -1173,7 +1181,8 @@ } Code += ", &Ops" + utostr(OpsNo) + "[0], Ops" + utostr(OpsNo) + ".size()"; - } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs) + } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs || + NodeHasInI1) AllOps.push_back("InFlag"); unsigned NumOps = AllOps.size(); @@ -1207,7 +1216,7 @@ NodeOps.push_back("Tmp" + utostr(ResNo)); } else { - if (NodeHasOutFlag) { + if (NodeHasOutFlag || NodeHasOutI1) { if (!InFlagDecled) { After.push_back("SDValue InFlag(ResNode, " + utostr(NumResults+NumDstRegs+(unsigned)NodeHasChain) + @@ -1228,13 +1237,15 @@ utostr(NumResults+NumDstRegs) + ")"); } - if (NodeHasOutFlag) { + if (NodeHasOutFlag || NodeHasOutI1) { if (FoldedFlag.first != "") { - ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + ".getNode(), " + + ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + + ".getNode(), " + utostr(FoldedFlag.second) + ")"); ReplaceTos.push_back("InFlag"); } else { - assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP)); + assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP) || + NodeHasProperty(Pattern, SDNPOutI1, CGP)); ReplaceFroms.push_back("SDValue(N.getNode(), " + utostr(NumPatResults + (unsigned)InputHasChain) + ")"); @@ -1251,7 +1262,8 @@ } // User does not expect the instruction would produce a chain! - if ((!InputHasChain && NodeHasChain) && NodeHasOutFlag) { + if ((!InputHasChain && NodeHasChain) && + (NodeHasOutFlag || NodeHasOutI1)) { ; } else if (InputHasChain && !NodeHasChain) { // One of the inner node produces a chain. @@ -1391,6 +1403,8 @@ unsigned OpNo = (unsigned) NodeHasProperty(N, SDNPHasChain, CGP); bool HasInFlag = NodeHasProperty(N, SDNPInFlag, CGP); + bool HasInI1 = NodeHasProperty(N, SDNPInI1, CGP); + bool InFlagDefined = false; for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) { TreePatternNode *Child = N->getChild(i); if (!Child->isLeaf()) { @@ -1424,21 +1438,41 @@ emitCode("SDValue InFlag(0, 0);"); InFlagDecled = true; } - std::string Decl = (!ResNodeDecled) ? "SDNode *" : ""; - emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + ChainName + + if (HasInI1) { + if (!ResNodeDecled) { + emitCode("SDNode * ResNode;"); + } + if (T.supportsHasI1()) + emitCode("ResNode = CurDAG->getCopyToReg(" + ChainName + + ", " + RootName + ".getDebugLoc()" + + ", " + getEnumName(RVT) + + ", " + getQualifiedName(RR) + + ", " + RootName + utostr(OpNo) + ").getNode();"); + else + emitCode("ResNode = CurDAG->getCopyToReg(" + ChainName + + ", " + RootName + ".getDebugLoc()" + + ", " + getQualifiedName(RR) + + ", " + RootName + utostr(OpNo) + + ", InFlag).getNode();"); + InFlagDefined = true; + } else { + std::string Decl = (!ResNodeDecled) ? "SDNode *" : ""; + emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + ChainName + ", " + RootName + ".getDebugLoc()" + ", " + getQualifiedName(RR) + - ", " + RootName + utostr(OpNo) + ", InFlag).getNode();"); - ResNodeDecled = true; + ", " + RootName + utostr(OpNo) + + ", InFlag).getNode();"); + } emitCode(ChainName + " = SDValue(ResNode, 0);"); emitCode("InFlag = SDValue(ResNode, 1);"); + ResNodeDecled = true; } } } } } - if (HasInFlag) { + if (HasInFlag || (HasInI1 && !InFlagDefined)) { if (!InFlagDecled) { emitCode("SDValue InFlag = " + RootName + ".getOperand(" + utostr(OpNo) + ");"); From kledzik at apple.com Mon Jun 1 18:41:10 2009 From: kledzik at apple.com (Nick Kledzik) Date: Mon, 01 Jun 2009 23:41:10 -0000 Subject: [llvm-commits] [llvm] r72708 - /llvm/trunk/tools/lto/LTOModule.cpp Message-ID: <200906012341.n51NfAW4007041@zion.cs.uiuc.edu> Author: kledzik Date: Mon Jun 1 18:41:09 2009 New Revision: 72708 URL: http://llvm.org/viewvc/llvm-project?rev=72708&view=rev Log: update comments about .objc_ symbols being generated Modified: llvm/trunk/tools/lto/LTOModule.cpp Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=72708&r1=72707&r2=72708&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Mon Jun 1 18:41:09 2009 @@ -270,8 +270,26 @@ // add to list of defined symbols addDefinedSymbol(v, mangler, false); - // special case i386/ppc ObjC data structures in magic sections - if ( v->hasSection() ) { + // Special case i386/ppc ObjC data structures in magic sections: + // The issue is that the old ObjC object format did some strange + // contortions to avoid real linker symbols. For instance, the + // ObjC class data structure is allocated statically in the executable + // that defines that class. That data structures contains a pointer to + // its superclass. But instead of just initializing that part of the + // struct to the address of its superclass, and letting the static and + // dynamic linkers do the rest, the runtime works by having that field + // instead point to a C-string that is the name of the superclass. + // At runtime the objc initialization updates that pointer and sets + // it to point to the actual super class. As far as the linker + // knows it is just a pointer to a string. But then someone wanted the + // linker to issue errors at build time if the superclass was not found. + // So they figured out a way in mach-o object format to use an absolute + // symbols (.objc_class_name_Foo = 0) and a floating reference + // (.reference .objc_class_name_Bar) to cause the linker into erroring when + // a class was missing. + // The following synthesizes the implicit .objc_* symbols for the linker + // from the ObjC data structures generated by the front end. + if ( v->hasSection() /* && isTargetDarwin */ ) { // special case if this data blob is an ObjC class definition if ( v->getSection().compare(0, 15, "__OBJC,__class,") == 0 ) { if (GlobalVariable* gv = dyn_cast(v)) { From kledzik at apple.com Mon Jun 1 18:46:15 2009 From: kledzik at apple.com (Nick Kledzik) Date: Mon, 1 Jun 2009 16:46:15 -0700 Subject: [llvm-commits] [llvm] r72700 - in /llvm/trunk/tools/lto: LTOModule.cpp LTOModule.h In-Reply-To: References: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> Message-ID: <8174BFCE-A4AB-49C7-8234-C543C03D1BEB@apple.com> On Jun 1, 2009, at 4:20 PM, Nick Lewycky wrote: > 2009/6/1 Nick Kledzik > > On Jun 1, 2009, at 2:11 PM, Nick Lewycky wrote: > >> 2009/6/1 Nick Kledzik >> Author: kledzik >> Date: Mon Jun 1 15:33:09 2009 >> New Revision: 72700 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=72700&view=rev >> Log: >> libLTO needs to handle i386 magic objc >> class symbols >> Parse __OBJC data structures and synthesize magic .objc_ symbols. >> Also, alter mangler so that objc method names are readable. >> >> Hi Nick, could you please elaborate on why exactly libLTO needs to >> change? While I don't doubt that this fixes a bug, I can't see how >> this language-specific logic could possibly belong in libLTO. > > It is not just language specific. It is only for Objective-C for > ppc or i386 on Darwin. My thinking was that the extra logic is > only executed if the GlobalVariable has a custom section with a > specific name, that it would not impact other languages or > architectures. > > That's a good policy. > > This issue is that the old ObjC object format did some strange > contortions to avoid real linker symbols. For instance the ObjC > class data structure is allocated statically in the executable that > defines it. That data structures contains a pointer to it > superclass. But instead of just initializing that part of the > struct to the address of its superclass, and letting the static and > dynamic linkers do the rest, the runtime works by having that field > point to a C-string that is the name of the superclass on disk. At > runtime the objc initialization swaps that pointer out to point to > the actual super class. As far as the linkers know it is just a > pointer to a string. But someone wanted the linker to issue errors > at build time if the superclass was not found. So they figured out > a way in mach-o object format to use an absolute symbol > (.objc_class_name_Foo = 0) and a floating reference > ( .reference .objc_class_name_Bar) to trick the linker into erroring > when a class was missing. This patch emulates that same behavior. > > Tricky! > > I haven't thought it through fully but it sounds like you may be > able to simulate some of this with the private linkage type which is > described in LangRef as "This doesn't show up in any symbol table in > the object file." We might be able to have the front end name the class data structure with a .objc_class_name name, but the real problem is the contents of the various data structures that need to both point to a string and (for error checking and archive loading) reference a .objc_class_name symbol. > > > At the very least, I'd appreciate a comment block in libLTO > explaining why this stuff is there. Pretty much the same thing you > wrote in the paragraph above. I just committed that as a comment. Thanks for nudging me to do that. -Nick > > > In addition, when processing mach-o files, the current Darwin linker > ignores those absolute and floating reference symbols, and instead > parses the __OBJC,__class data structures and infers those symbols. > The libLTO.dylib interfaces does not allow the linker to view the > contents of a bitcode file, just its symbols. So having libLTO > synthesize those symbols fits well with the Darwin linker. > > Would you prefer if the changes were wrapped in a isTargetDarwin() > test? > > It doesn't much matter because nobody else will call these new add* > methods. (Right?) The mangler change has me a little concerned but I > can wrap that in an isTargetDarwin() myself if I find that it is > responsible for breaking things on me. > > Also, thanks for taking the time to write up the rationale! > > Nick > > > -Nick > > > >> >> >> >> >> Modified: >> llvm/trunk/tools/lto/LTOModule.cpp >> llvm/trunk/tools/lto/LTOModule.h >> >> Modified: llvm/trunk/tools/lto/LTOModule.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=72700&r1=72699&r2=72700&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/tools/lto/LTOModule.cpp (original) >> +++ llvm/trunk/tools/lto/LTOModule.cpp Mon Jun 1 15:33:09 2009 >> @@ -14,6 +14,7 @@ >> >> #include "LTOModule.h" >> >> +#include "llvm/Constants.h" >> #include "llvm/Module.h" >> #include "llvm/ModuleProvider.h" >> #include "llvm/ADT/OwningPtr.h" >> @@ -176,11 +177,123 @@ >> } >> } >> >> -void LTOModule::addDefinedDataSymbol(GlobalValue* v, Mangler >> &mangler) >> +// get string that data pointer points to >> +bool LTOModule::objcClassNameFromExpression(Constant* c, >> std::string& name) >> +{ >> + if (ConstantExpr* ce = dyn_cast(c)) { >> >> Is there any reason not to just assert on this? Will it ever really >> be called on constants that aren't known to be objcClassNames? >> >> >> + Constant* op = ce->getOperand(0); >> + if (GlobalVariable* gvn = dyn_cast(op)) { >> + Constant* cn = gvn->getInitializer(); >> + if (ConstantArray* ca = dyn_cast(cn)) { >> + if ( ca->isCString() ) { >> + name = ".objc_class_name_" + ca->getAsString(); >> + return true; >> + } >> + } >> + } >> + } >> + return false; >> +} >> + >> +// parse i386/ppc ObjC class data structure >> +void LTOModule::addObjCClass(GlobalVariable* clgv) >> +{ >> + if (ConstantStruct* c = dyn_cast(clgv- >> >getInitializer())) { >> >> Here again, perhaps it should just assert that this is true? >> >> >> + // second slot in __OBJC,__class is pointer to superclass >> name >> + std::string superclassName; >> + if ( objcClassNameFromExpression(c->getOperand(1), >> superclassName) ) { >> + NameAndAttributes info; >> + if ( _undefines.find(superclassName.c_str()) == >> _undefines.end() ) { >> + const char* symbolName >> = ::strdup(superclassName.c_str()); >> + info.name = ::strdup(symbolName); >> + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; >> + // string is owned by _undefines >> + _undefines[info.name] = info; >> >> Perhaps the non-libLTO side of the Apple linker should ignore >> symbols it knows are objC specific? Or perhaps you could run a >> domain-specific LLVM pass which would delete these globals as >> needed? If somehow you need them to exist but still be marked >> undefined, perhaps libLTO should expose an interface for marking >> symbols undefined instead of an interface specific to Apple's >> implementation of the objC language? >> >> It just seems like this is breaking encapsulation, the linker has >> linking rules that don't much care what the source language was. >> >> Nick >> >> >> + } >> + } >> + // third slot in __OBJC,__class is pointer to class name >> + std::string className; >> + if ( objcClassNameFromExpression(c->getOperand(2), >> className) ) { >> + const char* symbolName = ::strdup(className.c_str()); >> + NameAndAttributes info; >> + info.name = symbolName; >> + info.attributes = (lto_symbol_attributes) >> + (LTO_SYMBOL_PERMISSIONS_DATA | >> + LTO_SYMBOL_DEFINITION_REGULAR | >> + LTO_SYMBOL_SCOPE_DEFAULT); >> + _symbols.push_back(info); >> + _defines[info.name] = 1; >> + } >> + } >> +} >> + >> + >> +// parse i386/ppc ObjC category data structure >> +void LTOModule::addObjCCategory(GlobalVariable* clgv) >> +{ >> + if (ConstantStruct* c = dyn_cast(clgv- >> >getInitializer())) { >> + // second slot in __OBJC,__category is pointer to target >> class name >> + std::string targetclassName; >> + if ( objcClassNameFromExpression(c->getOperand(1), >> targetclassName) ) { >> + NameAndAttributes info; >> + if ( _undefines.find(targetclassName.c_str()) == >> _undefines.end() ){ >> + const char* symbolName >> = ::strdup(targetclassName.c_str()); >> + info.name = ::strdup(symbolName); >> + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; >> + // string is owned by _undefines >> + _undefines[info.name] = info; >> + } >> + } >> + } >> +} >> + >> + >> +// parse i386/ppc ObjC class list data structure >> +void LTOModule::addObjCClassRef(GlobalVariable* clgv) >> +{ >> + std::string targetclassName; >> + if ( objcClassNameFromExpression(clgv->getInitializer(), >> targetclassName) ){ >> + NameAndAttributes info; >> + if ( _undefines.find(targetclassName.c_str()) == >> _undefines.end() ) { >> + const char* symbolName >> = ::strdup(targetclassName.c_str()); >> + info.name = ::strdup(symbolName); >> + info.attributes = LTO_SYMBOL_DEFINITION_UNDEFINED; >> + // string is owned by _undefines >> + _undefines[info.name] = info; >> + } >> + } >> +} >> + >> + >> +void LTOModule::addDefinedDataSymbol(GlobalValue* v, Mangler& >> mangler) >> { >> // add to list of defined symbols >> addDefinedSymbol(v, mangler, false); >> >> + // special case i386/ppc ObjC data structures in magic sections >> + if ( v->hasSection() ) { >> + // special case if this data blob is an ObjC class >> definition >> + if ( v->getSection().compare(0, 15, "__OBJC,__class,") == >> 0 ) { >> + if (GlobalVariable* gv = dyn_cast(v)) { >> + addObjCClass(gv); >> + } >> + } >> + >> + // special case if this data blob is an ObjC category >> definition >> + else if ( v->getSection().compare(0, 18, >> "__OBJC,__category,") == 0 ) { >> + if (GlobalVariable* gv = dyn_cast(v)) { >> + addObjCCategory(gv); >> + } >> + } >> + >> + // special case if this data blob is the list of >> referenced classes >> + else if ( v->getSection().compare(0, 18, >> "__OBJC,__cls_refs,") == 0 ) { >> + if (GlobalVariable* gv = dyn_cast(v)) { >> + addObjCClassRef(gv); >> + } >> + } >> + } >> + >> // add external symbols referenced by this data. >> for (unsigned count = 0, total = v->getNumOperands(); >> count != total; + >> +count) { >> @@ -192,9 +305,13 @@ >> void LTOModule::addDefinedSymbol(GlobalValue* def, Mangler &mangler, >> bool isFunction) >> { >> + // ignore all llvm.* symbols >> + if ( strncmp(def->getNameStart(), "llvm.", 5) == 0 ) >> + return; >> + >> // string is owned by _defines >> const char* symbolName >> = ::strdup(mangler.getValueName(def).c_str()); >> - >> + >> // set alignment part log2() can have rounding errors >> uint32_t align = def->getAlignment(); >> uint32_t attr = align ? CountTrailingZeros_32(def- >> >getAlignment()) : 0; >> @@ -241,25 +358,28 @@ >> } >> >> void LTOModule::addAsmGlobalSymbol(const char *name) { >> - // string is owned by _defines >> - const char *symbolName = ::strdup(name); >> - uint32_t attr = LTO_SYMBOL_DEFINITION_REGULAR; >> - attr |= LTO_SYMBOL_SCOPE_DEFAULT; >> - >> - // add to table of symbols >> - NameAndAttributes info; >> - info.name = symbolName; >> - info.attributes = (lto_symbol_attributes)attr; >> - _symbols.push_back(info); >> - _defines[info.name] = 1; >> + // only add new define if not already defined >> + if ( _defines.count(name, &name[strlen(name)+1]) == 0 ) >> + return; >> + >> + // string is owned by _defines >> + const char *symbolName = ::strdup(name); >> + uint32_t attr = LTO_SYMBOL_DEFINITION_REGULAR; >> + attr |= LTO_SYMBOL_SCOPE_DEFAULT; >> + NameAndAttributes info; >> + info.name = symbolName; >> + info.attributes = (lto_symbol_attributes)attr; >> + _symbols.push_back(info); >> + _defines[info.name] = 1; >> } >> >> void LTOModule::addPotentialUndefinedSymbol(GlobalValue* decl, >> Mangler &mangler) >> { >> - const char* name = mangler.getValueName(decl).c_str(); >> // ignore all llvm.* symbols >> - if ( strncmp(name, "llvm.", 5) == 0 ) >> - return; >> + if ( strncmp(decl->getNameStart(), "llvm.", 5) == 0 ) >> + return; >> + >> + const char* name = mangler.getValueName(decl).c_str(); >> >> // we already have the symbol >> if (_undefines.find(name) != _undefines.end()) >> @@ -306,6 +426,14 @@ >> >> // Use mangler to add GlobalPrefix to names to match linker >> names. >> Mangler mangler(*_module, _target->getTargetAsmInfo()- >> >getGlobalPrefix()); >> + // add chars used in ObjC method names so method names >> aren't mangled >> + mangler.markCharAcceptable('['); >> + mangler.markCharAcceptable(']'); >> + mangler.markCharAcceptable('('); >> + mangler.markCharAcceptable(')'); >> + mangler.markCharAcceptable('-'); >> + mangler.markCharAcceptable('+'); >> + mangler.markCharAcceptable(' '); >> >> // add functions >> for (Module::iterator f = _module->begin(); f != _module- >> >end(); ++f) { >> >> Modified: llvm/trunk/tools/lto/LTOModule.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.h?rev=72700&r1=72699&r2=72700&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/tools/lto/LTOModule.h (original) >> +++ llvm/trunk/tools/lto/LTOModule.h Mon Jun 1 15:33:09 2009 >> @@ -77,13 +77,19 @@ >> void addDefinedDataSymbol(llvm::GlobalValue* >> v, >> >> llvm::Mangler &mangler); >> void addAsmGlobalSymbol(const char *); >> + void addObjCClass(llvm::GlobalVariable* >> clgv); >> + void addObjCCategory(llvm::GlobalVariable* >> clgv); >> + void addObjCClassRef(llvm::GlobalVariable* >> clgv); >> + bool >> objcClassNameFromExpression(llvm::Constant* c, >> + std::string& >> name); >> + >> static bool isTargetMatch(llvm::MemoryBuffer* >> memBuffer, >> const char* >> triplePrefix); >> - >> + >> static LTOModule* makeLTOModule(llvm::MemoryBuffer* buffer, >> >> std::string& errMsg); >> static llvm::MemoryBuffer* makeBuffer(const void* mem, size_t >> length); >> - >> + >> typedef llvm::StringMap StringSet; >> >> struct NameAndAttributes { >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090601/a311c75a/attachment.html From dalej at apple.com Mon Jun 1 18:48:58 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 01 Jun 2009 23:48:58 -0000 Subject: [llvm-commits] [llvm] r72709 - /llvm/trunk/lib/Target/X86/X86.td Message-ID: <200906012348.n51NmwBH007260@zion.cs.uiuc.edu> Author: johannes Date: Mon Jun 1 18:48:58 2009 New Revision: 72709 URL: http://llvm.org/viewvc/llvm-project?rev=72709&view=rev Log: Add missing file. Modified: llvm/trunk/lib/Target/X86/X86.td Modified: llvm/trunk/lib/Target/X86/X86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=72709&r1=72708&r2=72709&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.td (original) +++ llvm/trunk/lib/Target/X86/X86.td Mon Jun 1 18:48:58 2009 @@ -151,6 +151,8 @@ 19, 20, 24]; + + let supportsHasI1 = 1; } //===----------------------------------------------------------------------===// From evan.cheng at apple.com Mon Jun 1 19:56:08 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 02 Jun 2009 00:56:08 -0000 Subject: [llvm-commits] [llvm] r72710 - in /llvm/trunk: lib/Transforms/IPO/GlobalOpt.cpp test/Transforms/GlobalOpt/2009-06-01-RecursivePHI.ll Message-ID: <200906020056.n520u8Ye009421@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jun 1 19:56:07 2009 New Revision: 72710 URL: http://llvm.org/viewvc/llvm-project?rev=72710&view=rev Log: Avoid infinite looping in AllGlobalLoadUsesSimpleEnoughForHeapSRA(). This can happen when PHI uses are recursively dependent on each other. Added: llvm/trunk/test/Transforms/GlobalOpt/2009-06-01-RecursivePHI.ll Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=72710&r1=72709&r2=72710&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Mon Jun 1 19:56:07 2009 @@ -1020,7 +1020,8 @@ /// of a load) are simple enough to perform heap SRA on. This permits GEP's /// that index through the array and struct field, icmps of null, and PHIs. static bool LoadUsesSimpleEnoughForHeapSRA(Value *V, - SmallPtrSet &LoadUsingPHIs) { + SmallPtrSet &LoadUsingPHIs, + SmallPtrSet &LoadUsingPHIsPerLoad) { // We permit two users of the load: setcc comparing against the null // pointer, and a getelementptr of a specific form. for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){ @@ -1044,12 +1045,17 @@ } if (PHINode *PN = dyn_cast(User)) { - // If we have already recursively analyzed this PHI, then it is safe. - if (LoadUsingPHIs.insert(PN)) + if (!LoadUsingPHIsPerLoad.insert(PN)) + // This means some phi nodes are dependent on each other. + // Avoid infinite looping! + return false; + if (!LoadUsingPHIs.insert(PN)) + // If we have already analyzed this PHI, then it is safe. continue; // Make sure all uses of the PHI are simple enough to transform. - if (!LoadUsesSimpleEnoughForHeapSRA(PN, LoadUsingPHIs)) + if (!LoadUsesSimpleEnoughForHeapSRA(PN, + LoadUsingPHIs, LoadUsingPHIsPerLoad)) return false; continue; @@ -1068,11 +1074,15 @@ static bool AllGlobalLoadUsesSimpleEnoughForHeapSRA(GlobalVariable *GV, MallocInst *MI) { SmallPtrSet LoadUsingPHIs; + SmallPtrSet LoadUsingPHIsPerLoad; for (Value::use_iterator UI = GV->use_begin(), E = GV->use_end(); UI != E; ++UI) - if (LoadInst *LI = dyn_cast(*UI)) - if (!LoadUsesSimpleEnoughForHeapSRA(LI, LoadUsingPHIs)) + if (LoadInst *LI = dyn_cast(*UI)) { + if (!LoadUsesSimpleEnoughForHeapSRA(LI, LoadUsingPHIs, + LoadUsingPHIsPerLoad)) return false; + LoadUsingPHIsPerLoad.clear(); + } // If we reach here, we know that all uses of the loads and transitive uses // (through PHI nodes) are simple enough to transform. However, we don't know Added: llvm/trunk/test/Transforms/GlobalOpt/2009-06-01-RecursivePHI.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalOpt/2009-06-01-RecursivePHI.ll?rev=72710&view=auto ============================================================================== --- llvm/trunk/test/Transforms/GlobalOpt/2009-06-01-RecursivePHI.ll (added) +++ llvm/trunk/test/Transforms/GlobalOpt/2009-06-01-RecursivePHI.ll Mon Jun 1 19:56:07 2009 @@ -0,0 +1,117 @@ +; RUN: llvm-as < %s | opt -globalopt + + %struct.s_annealing_sched = type { i32, float, float, float, float } + %struct.s_bb = type { i32, i32, i32, i32 } + %struct.s_net = type { i8*, i32, i32*, float, float } + %struct.s_placer_opts = type { i32, float, i32, i32, i8*, i32, i32 } + at net = internal global %struct.s_net* null ; <%struct.s_net**> [#uses=4] + +define fastcc void @alloc_and_load_placement_structs(i32 %place_cost_type, i32 %num_regions, float %place_cost_exp, float*** nocapture %old_region_occ_x, float*** nocapture %old_region_occ_y) nounwind ssp { +entry: + br i1 undef, label %bb.i, label %my_malloc.exit + +bb.i: ; preds = %entry + unreachable + +my_malloc.exit: ; preds = %entry + br i1 undef, label %bb.i81, label %my_malloc.exit83 + +bb.i81: ; preds = %my_malloc.exit + unreachable + +my_malloc.exit83: ; preds = %my_malloc.exit + br i1 undef, label %bb.i.i57, label %my_calloc.exit.i + +bb.i.i57: ; preds = %my_malloc.exit83 + unreachable + +my_calloc.exit.i: ; preds = %my_malloc.exit83 + br i1 undef, label %bb.i4.i, label %my_calloc.exit5.i + +bb.i4.i: ; preds = %my_calloc.exit.i + unreachable + +my_calloc.exit5.i: ; preds = %my_calloc.exit.i + %.pre.i58 = load %struct.s_net** @net, align 4 ; <%struct.s_net*> [#uses=1] + br label %bb17.i78 + +bb1.i61: ; preds = %bb4.preheader.i, %bb1.i61 + br i1 undef, label %bb1.i61, label %bb5.i62 + +bb5.i62: ; preds = %bb1.i61 + br i1 undef, label %bb6.i64, label %bb15.preheader.i + +bb15.preheader.i: ; preds = %bb4.preheader.i, %bb5.i62 + br label %bb16.i77 + +bb6.i64: ; preds = %bb5.i62 + br i1 undef, label %bb7.i65, label %bb8.i67 + +bb7.i65: ; preds = %bb6.i64 + unreachable + +bb8.i67: ; preds = %bb6.i64 + br i1 undef, label %bb.i1.i68, label %my_malloc.exit.i70 + +bb.i1.i68: ; preds = %bb8.i67 + unreachable + +my_malloc.exit.i70: ; preds = %bb8.i67 + %0 = load %struct.s_net** @net, align 4 ; <%struct.s_net*> [#uses=1] + br i1 undef, label %bb9.i71, label %bb16.i77 + +bb9.i71: ; preds = %bb9.i71, %my_malloc.exit.i70 + %1 = load %struct.s_net** @net, align 4 ; <%struct.s_net*> [#uses=1] + br i1 undef, label %bb9.i71, label %bb16.i77 + +bb16.i77: ; preds = %bb9.i71, %my_malloc.exit.i70, %bb15.preheader.i + %.pre41.i.rle244 = phi %struct.s_net* [ %.pre41.i, %bb15.preheader.i ], [ %0, %my_malloc.exit.i70 ], [ %1, %bb9.i71 ] ; <%struct.s_net*> [#uses=1] + br label %bb17.i78 + +bb17.i78: ; preds = %bb16.i77, %my_calloc.exit5.i + %.pre41.i = phi %struct.s_net* [ %.pre41.i.rle244, %bb16.i77 ], [ %.pre.i58, %my_calloc.exit5.i ] ; <%struct.s_net*> [#uses=1] + br i1 undef, label %bb4.preheader.i, label %alloc_and_load_unique_pin_list.exit + +bb4.preheader.i: ; preds = %bb17.i78 + br i1 undef, label %bb1.i61, label %bb15.preheader.i + +alloc_and_load_unique_pin_list.exit: ; preds = %bb17.i78 + ret void +} + +define void @read_net(i8* %net_file) nounwind ssp { +entry: + br i1 undef, label %bb3.us.us.i, label %bb6.preheader + +bb6.preheader: ; preds = %entry + br i1 undef, label %bb7, label %bb + +bb3.us.us.i: ; preds = %entry + unreachable + +bb: ; preds = %bb6.preheader + br i1 undef, label %bb.i34, label %bb1.i38 + +bb.i34: ; preds = %bb + unreachable + +bb1.i38: ; preds = %bb + %0 = malloc %struct.s_net, i32 undef ; <%struct.s_net*> [#uses=1] + br i1 undef, label %bb.i1.i39, label %my_malloc.exit2.i + +bb.i1.i39: ; preds = %bb1.i38 + unreachable + +my_malloc.exit2.i: ; preds = %bb1.i38 + store %struct.s_net* %0, %struct.s_net** @net, align 4 + br i1 undef, label %bb.i7.i40, label %my_malloc.exit8.i + +bb.i7.i40: ; preds = %my_malloc.exit2.i + unreachable + +my_malloc.exit8.i: ; preds = %my_malloc.exit2.i + unreachable + +bb7: ; preds = %bb6.preheader + unreachable +} From dalej at apple.com Mon Jun 1 22:12:58 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 02 Jun 2009 03:12:58 -0000 Subject: [llvm-commits] [llvm] r72712 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/X86/ utils/TableGen/ Message-ID: <200906020312.n523CxcR013341@zion.cs.uiuc.edu> Author: johannes Date: Mon Jun 1 22:12:52 2009 New Revision: 72712 URL: http://llvm.org/viewvc/llvm-project?rev=72712&view=rev Log: Revert 72707 and 72709, for the moment. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/include/llvm/Target/Target.td llvm/trunk/include/llvm/Target/TargetSelectionDAG.td llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/X86/X86.td llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86Instr64bit.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/CodeGenTarget.h llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Jun 1 22:12:52 2009 @@ -324,14 +324,6 @@ return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, getRegister(Reg, N.getValueType()), N); } - // This version of getCopyToReg has the register (and its type) as an - // explicit output. - SDValue getCopyToReg(SDValue Chain, DebugLoc dl, MVT VT, unsigned Reg, - SDValue N) { - SDVTList VTs = getVTList(MVT::Other, VT); - SDValue Ops[] = { Chain, getRegister(Reg, VT), N}; - return getNode(ISD::CopyToReg, dl, VTs, Ops, 3); - } // This version of the getCopyToReg method takes an extra operand, which // indicates that there is potentially an incoming flag value (if Flag is not Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Jun 1 22:12:52 2009 @@ -242,11 +242,14 @@ // remainder result. SDIVREM, UDIVREM, + // CARRY_FALSE - This node is used when folding other nodes, + // like ADDC/SUBC, which indicate the carry result is always false. + CARRY_FALSE, + // Carry-setting nodes for multiple precision addition and subtraction. // These nodes take two operands of the same value type, and produce two // results. The first result is the normal add or sub result, the second - // result is the carry flag result (type i1 or whatever it got expanded to - // for the target, value 0 or 1). + // result is the carry flag result. ADDC, SUBC, // Carry-using nodes for multiple precision addition and subtraction. These @@ -255,8 +258,7 @@ // produce two results; the normal result of the add or sub, and the output // carry flag. These nodes both read and write a carry flag to allow them // to them to be chained together for add and sub of arbitrarily large - // values. The carry flag (input and output) has type i1 or whatever it - // got expanded to for the target, and has value 0 or 1. + // values. ADDE, SUBE, // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Mon Jun 1 22:12:52 2009 @@ -326,11 +326,6 @@ // Sparc manual specifies its instructions in the format [31..0] (big), while // PowerPC specifies them using the format [0..31] (little). bit isLittleEndianEncoding = 0; - - // Targets that can support the HasI1 argument on ADDC and ADDE, rather than - // Flag, have this bit set. This is transitional and should go away when all - // targets have been switched over. - bit supportsHasI1 = 0; } // Standard Instructions. Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Mon Jun 1 22:12:52 2009 @@ -216,8 +216,6 @@ def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand -def SDNPInI1 : SDNodeProperty; // Read an extra I1 operand -def SDNPOutI1 : SDNodeProperty; // Write an extra I1 result //===----------------------------------------------------------------------===// // Selection DAG Node definitions. @@ -291,13 +289,13 @@ def xor : SDNode<"ISD::XOR" , SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, - [SDNPCommutative, SDNPOutI1]>; + [SDNPCommutative, SDNPOutFlag]>; def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, - [SDNPCommutative, SDNPInI1, SDNPOutI1]>; + [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, - [SDNPOutI1]>; + [SDNPOutFlag]>; def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, - [SDNPInI1, SDNPOutI1]>; + [SDNPOutFlag, SDNPInFlag]>; def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jun 1 22:12:52 2009 @@ -1085,7 +1085,8 @@ // If the flag result is dead, turn this into an ADD. if (N->hasNUsesOfValue(0, 1)) return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), - DAG.getConstant(0, N->getValueType(1))); + DAG.getNode(ISD::CARRY_FALSE, + N->getDebugLoc(), MVT::Flag)); // canonicalize constant to RHS. if (N0C && !N1C) @@ -1093,9 +1094,10 @@ // fold (addc x, 0) -> x + no carry out if (N1C && N1C->isNullValue()) - return CombineTo(N, N0, DAG.getConstant(0, N1.getValueType())); + return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, + N->getDebugLoc(), MVT::Flag)); - // fold (addc a, b) -> (or a, b), 0 iff a and b share no bits. + // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. APInt LHSZero, LHSOne; APInt RHSZero, RHSOne; APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); @@ -1109,7 +1111,8 @@ if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), - DAG.getConstant(0, N1.getValueType())); + DAG.getNode(ISD::CARRY_FALSE, + N->getDebugLoc(), MVT::Flag)); } return SDValue(); @@ -1128,9 +1131,8 @@ N1, N0, CarryIn); // fold (adde x, y, false) -> (addc x, y) - if (ConstantSDNode *N2C = dyn_cast(CarryIn)) - if (N2C->getAPIntValue()==0) - return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); + if (CarryIn.getOpcode() == ISD::CARRY_FALSE) + return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); return SDValue(); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Jun 1 22:12:52 2009 @@ -98,10 +98,6 @@ case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; case ISD::SMULO: case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; - case ISD::ADDC: - case ISD::SUBC: Res = PromoteIntRes_ADDSUBC(N, ResNo); break; - case ISD::ADDE: - case ISD::SUBE: Res = PromoteIntRes_ADDSUBE(N, ResNo); break; case ISD::ATOMIC_LOAD_ADD: case ISD::ATOMIC_LOAD_SUB: @@ -125,35 +121,6 @@ SetPromotedInteger(SDValue(N, ResNo), Res); } -SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBC(SDNode *N, unsigned ResNo) { - // Only the carry bit result is expected to be promoted. - assert(ResNo == 1 && "Only carry bit result promotion currently supported!"); - return PromoteIntRes_Overflow(N); -} - -SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBE(SDNode *N, unsigned ResNo) { - // Only the carry bit result is expected to be promoted. - assert(ResNo == 1 && "Only carry bit result promotion currently supported!"); - // This is a ternary operator, so clone a slightly modified - // PromoteIntRes_Overflow here (this is the only client). - if (ResNo == 1) { - // Simply change the return type of the boolean result. - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); - MVT ValueVTs[] = { N->getValueType(0), NVT }; - SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; - SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), - DAG.getVTList(ValueVTs, 2), Ops, 3); - - // Modified the sum result - switch anything that used the old sum to use - // the new one. - ReplaceValueWith(SDValue(N, 0), Res); - - return SDValue(Res.getNode(), 1); - } - assert(0 && "Do not know how to promote this operator!"); - abort(); -} - SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { // Sign-extend the new bits, and continue the assertion. SDValue Op = SExtPromotedInteger(N->getOperand(0)); @@ -452,7 +419,7 @@ return Res; } -/// Promote the overflow or carry result of an overflowing arithmetic node. +/// Promote the overflow flag of an overflowing arithmetic node. SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { // Simply change the return type of the boolean result. MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); @@ -699,8 +666,6 @@ assert(0 && "Do not know how to promote this operator's operand!"); abort(); - case ISD::ADDE: - case ISD::SUBE: Res = PromoteIntOp_ADDSUBE(N, OpNo); break; case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; @@ -778,13 +743,6 @@ } } -SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBE(SDNode *N, unsigned OpNo) { - assert(OpNo == 2 && "Don't know how to promote this operand!"); - return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), - N->getOperand(1), - GetPromotedInteger(N->getOperand(2))); -} - SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { SDValue Op = GetPromotedInteger(N->getOperand(0)); return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); @@ -1105,7 +1063,7 @@ TLI.isOperationLegalOrCustom(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) { // Emit this X << 1 as X+X. - SDVTList VTList = DAG.getVTList(NVT, MVT::i1); + SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); SDValue LoOps[2] = { InL, InL }; Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; @@ -1341,7 +1299,7 @@ TLI.getTypeToExpandTo(NVT)); if (hasCarry) { - SDVTList VTList = DAG.getVTList(NVT, MVT::i1); + SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); if (N->getOpcode() == ISD::ADD) { Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); @@ -1386,7 +1344,7 @@ DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), LHSL, LHSH); GetExpandedInteger(N->getOperand(1), RHSL, RHSH); - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); SDValue LoOps[2] = { LHSL, RHSL }; SDValue HiOps[3] = { LHSH, RHSH }; @@ -1400,8 +1358,8 @@ Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); } - // Legalized the second result (carry bit) - switch anything that used the - // result to use the new one. + // Legalized the flag result - switch anything that used the old flag to + // use the new one. ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); } @@ -1412,7 +1370,7 @@ DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), LHSL, LHSH); GetExpandedInteger(N->getOperand(1), RHSL, RHSH); - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; SDValue HiOps[3] = { LHSH, RHSH }; @@ -1420,8 +1378,8 @@ HiOps[2] = Lo.getValue(1); Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); - // Legalized the second result (carry bit) - switch anything that used the - // result to use the new one. + // Legalized the flag result - switch anything that used the old flag to + // use the new one. ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Jun 1 22:12:52 2009 @@ -242,8 +242,6 @@ // Integer Result Promotion. void PromoteIntegerResult(SDNode *N, unsigned ResNo); - SDValue PromoteIntRes_ADDSUBC(SDNode *N, unsigned ResNo); - SDValue PromoteIntRes_ADDSUBE(SDNode *N, unsigned ResNo); SDValue PromoteIntRes_AssertSext(SDNode *N); SDValue PromoteIntRes_AssertZext(SDNode *N); SDValue PromoteIntRes_Atomic1(AtomicSDNode *N); @@ -280,7 +278,6 @@ // Integer Operand Promotion. bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo); - SDValue PromoteIntOp_ADDSUBE(SDNode *N, unsigned OpNo); SDValue PromoteIntOp_ANY_EXTEND(SDNode *N); SDValue PromoteIntOp_BIT_CONVERT(SDNode *N); SDValue PromoteIntOp_BUILD_PAIR(SDNode *N); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Mon Jun 1 22:12:52 2009 @@ -268,13 +268,6 @@ unsigned N = Node->getNumOperands(); while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) --N; - // Skip hard registers set as a side effect (i.e. not result 0). - while (N && Node->getOperand(N - 1).getOpcode() == ISD::CopyToReg && - Node->getOperand(N-1).getResNo() != 0 && - !TargetRegisterInfo::isVirtualRegister( - dyn_cast(Node->getOperand(N-1).getOperand(1)) - ->getReg())) - --N; if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) --N; // Ignore chain if it exists. return N; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 1 22:12:52 2009 @@ -5257,6 +5257,7 @@ case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; + case ISD::CARRY_FALSE: return "carry_false"; case ISD::ADDC: return "addc"; case ISD::ADDE: return "adde"; case ISD::SADDO: return "saddo"; Modified: llvm/trunk/lib/Target/X86/X86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.td (original) +++ llvm/trunk/lib/Target/X86/X86.td Mon Jun 1 22:12:52 2009 @@ -151,8 +151,6 @@ 19, 20, 24]; - - let supportsHasI1 = 1; } //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jun 1 22:12:52 2009 @@ -190,28 +190,6 @@ setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); } - // ADDE and SUBE are lowered to local versions that contain EFLAGS explicitly. - // ADDC and SUBC are lowered to local versions so EFLAGS will be an i32 - // rather than the Flag used by the generic patterns. - setOperationAction(ISD::ADDC , MVT::i8 , Custom); - setOperationAction(ISD::ADDC , MVT::i16 , Custom); - setOperationAction(ISD::ADDC , MVT::i32 , Custom); - setOperationAction(ISD::SUBC , MVT::i8 , Custom); - setOperationAction(ISD::SUBC , MVT::i16 , Custom); - setOperationAction(ISD::SUBC , MVT::i32 , Custom); - setOperationAction(ISD::ADDE , MVT::i8 , Custom); - setOperationAction(ISD::ADDE , MVT::i16 , Custom); - setOperationAction(ISD::ADDE , MVT::i32 , Custom); - setOperationAction(ISD::SUBE , MVT::i8 , Custom); - setOperationAction(ISD::SUBE , MVT::i16 , Custom); - setOperationAction(ISD::SUBE , MVT::i32 , Custom); - if (Subtarget->is64Bit()) { - setOperationAction(ISD::ADDC , MVT::i64 , Custom); - setOperationAction(ISD::SUBC , MVT::i64 , Custom); - setOperationAction(ISD::ADDE , MVT::i64 , Custom); - setOperationAction(ISD::SUBE , MVT::i64 , Custom); - } - // Scalar integer divide and remainder are lowered to use operations that // produce two results, to match the available instructions. This exposes // the two-result form to trivial CSE, which is able to combine x/y and x%y @@ -6497,21 +6475,6 @@ return Sum; } -SDValue X86TargetLowering::LowerADDSUBE(SDValue Op, SelectionDAG &DAG) { - DebugLoc dl = Op.getDebugLoc(); - SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); - return DAG.getNode(Op.getOpcode()==ISD::ADDE ? X86ISD::ADDE : X86ISD::SUBE, - dl, VTs, Op.getOperand(0), Op.getOperand(1), - Op.getOperand(2).getValue(1)); -} - -SDValue X86TargetLowering::LowerADDSUBC(SDValue Op, SelectionDAG &DAG) { - DebugLoc dl = Op.getDebugLoc(); - SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); - return DAG.getNode(Op.getOpcode()==ISD::ADDC ? X86ISD::ADD : X86ISD::SUB, - dl, VTs, Op.getOperand(0), Op.getOperand(1)); -} - SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { MVT T = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); @@ -6580,10 +6543,6 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); - case ISD::ADDC: - case ISD::SUBC: return LowerADDSUBC(Op,DAG); - case ISD::ADDE: - case ISD::SUBE: return LowerADDSUBE(Op,DAG); case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); @@ -6832,10 +6791,6 @@ case X86ISD::INC: return "X86ISD::INC"; case X86ISD::DEC: return "X86ISD::DEC"; case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; - case X86ISD::ADDE: return "X86ISD::ADDE"; - case X86ISD::SUBE: return "X86ISD::SUBE"; - case X86ISD::ADDC: return "X86ISD::ADDC"; - case X86ISD::SUBC: return "X86ISD::SUBC"; } } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Jun 1 22:12:52 2009 @@ -243,14 +243,6 @@ ADD, SUB, SMUL, UMUL, INC, DEC, - // ADDC, SUBC - Arithmetic operations setting carry bit. The normal - // arithmetic operations do this, but they represent it as Flag, and - // we want the i32 EFLAGS register here. - ADDC, SUBC, - - // ADDE, SUBE - Arithmetic operations with extra FLAGS (EFLAGS) inputs. - ADDE, SUBE, - // MUL_IMM - X86 specific multiply by immediate. MUL_IMM }; @@ -584,9 +576,7 @@ std::pair FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool isSigned); - - SDValue LowerADDSUBC(SDValue Op, SelectionDAG &DAG); - SDValue LowerADDSUBE(SDValue Op, SelectionDAG &DAG); + SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Mon Jun 1 22:12:52 2009 @@ -383,52 +383,31 @@ let Uses = [EFLAGS] in { let isTwoAddress = 1 in { let isCommutable = 1 in -def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), - (ins GR64:$src1, GR64:$src2), +def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, - (X86adde_flag GR64:$src1, GR64:$src2, EFLAGS)), - (implicit EFLAGS)]>; + [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>; -def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), - (ins GR64:$src1, i64mem:$src2), +def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, - (X86adde_flag GR64:$src1, (load addr:$src2), EFLAGS)), - (implicit EFLAGS)]>; + [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>; -def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), - (ins GR64:$src1, i64i8imm:$src2), +def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, - (X86adde_flag GR64:$src1, i64immSExt8:$src2, EFLAGS)), - (implicit EFLAGS)]>; -def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), - (ins GR64:$src1, i64i32imm:$src2), + [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>; +def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, - (X86adde_flag GR64:$src1, i64immSExt32:$src2, - EFLAGS)), - (implicit EFLAGS)]>; + [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>; } // isTwoAddress def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(store (X86adde_flag (load addr:$dst), GR64:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; + [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>; def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(store (X86adde_flag (load addr:$dst), i64immSExt8:$src2, - EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; + [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", - [(store (X86adde_flag (load addr:$dst), i64immSExt8:$src2, - EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; + [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; } // Uses = [EFLAGS] let isTwoAddress = 1 in { @@ -477,52 +456,31 @@ let Uses = [EFLAGS] in { let isTwoAddress = 1 in { -def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), - (ins GR64:$src1, GR64:$src2), +def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, - (X86sube_flag GR64:$src1, GR64:$src2, EFLAGS)), - (implicit EFLAGS)]>; + [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>; -def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), - (ins GR64:$src1, i64mem:$src2), +def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, - (X86sube_flag GR64:$src1, (load addr:$src2), EFLAGS)), - (implicit EFLAGS)]>; + [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>; -def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), - (ins GR64:$src1, i64i8imm:$src2), +def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, - (X86sube_flag GR64:$src1, i64immSExt8:$src2, EFLAGS)), - (implicit EFLAGS)]>; -def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), - (ins GR64:$src1, i64i32imm:$src2), + [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>; +def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, - (X86sube_flag GR64:$src1, i64immSExt32:$src2, - EFLAGS)), - (implicit EFLAGS)]>; + [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>; } // isTwoAddress def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(store (X86sube_flag (load addr:$dst), GR64:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; + [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>; def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(store (X86sube_flag (load addr:$dst), i64immSExt8:$src2, - EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; + [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", - [(store (X86sube_flag (load addr:$dst), i64immSExt32:$src2, - EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; + [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>; } // Uses = [EFLAGS] } // Defs = [EFLAGS] Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Jun 1 22:12:52 2009 @@ -34,11 +34,6 @@ [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>]>; -// Unary and binary operators that both read and write EFLAGS as a side-effect. -def SDTBinaryArithRWFlags : SDTypeProfile<1, 3, - [SDTCisInt<0>, SDTCisSameAs<0, 1>, - SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; - def SDTX86BrCond : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; @@ -161,8 +156,6 @@ def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>; def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; -def X86adde_flag : SDNode<"X86ISD::ADDE", SDTBinaryArithRWFlags, [SDNPInI1]>; -def X86sube_flag : SDNode<"X86ISD::SUBE", SDTBinaryArithRWFlags, [SDNPInI1]>; def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; @@ -2281,127 +2274,81 @@ let Uses = [EFLAGS] in { let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y -def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), - (ins GR8:$src1, GR8:$src2), +def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), "adc{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (X86adde_flag GR8:$src1, GR8:$src2, EFLAGS)), - (implicit EFLAGS)]>; + [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>; def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, - (X86adde_flag GR16:$src1, GR16:$src2, EFLAGS)), - (implicit EFLAGS)]>, - OpSize; + [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize; def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, - (X86adde_flag GR32:$src1, GR32:$src2, EFLAGS)), - (implicit EFLAGS)]>; + [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; } def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2), "adc{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, - (X86adde_flag GR8:$src1, (load addr:$src2), EFLAGS)), - (implicit EFLAGS)]>; + [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>; def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, - (X86adde_flag GR16:$src1, (load addr:$src2), EFLAGS)), - (implicit EFLAGS)]>, + [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>, OpSize; def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, - (X86adde_flag GR32:$src1, (load addr:$src2), EFLAGS)), - (implicit EFLAGS)]>; -def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), - (ins GR8:$src1, i8imm:$src2), + [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>; +def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), "adc{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, - (X86adde_flag GR8:$src1, imm:$src2, EFLAGS)), - (implicit EFLAGS)]>; + [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>; def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, - (X86adde_flag GR16:$src1, imm:$src2, EFLAGS)), - (implicit EFLAGS)]>, OpSize; + [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize; def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, - (X86adde_flag GR16:$src1, i16immSExt8:$src2, EFLAGS)), - (implicit EFLAGS)]>, OpSize; + [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>, + OpSize; def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, - (X86adde_flag GR32:$src1, imm:$src2, EFLAGS)), - (implicit EFLAGS)]>; + [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, - (X86adde_flag GR32:$src1, i32immSExt8:$src2, EFLAGS)), - (implicit EFLAGS)]>; + [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>; let isTwoAddress = 0 in { - def ADC8mr : I<0x10, MRMDestMem, (outs), - (ins i8mem:$dst, GR8:$src2), + def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), "adc{b}\t{$src2, $dst|$dst, $src2}", - [(store (X86adde_flag (load addr:$dst), GR8:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; - def ADC16mr : I<0x11, MRMDestMem, (outs), - (ins i16mem:$dst, GR16:$src2), + [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>; + def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(store (X86adde_flag (load addr:$dst), GR16:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>, OpSize; - def ADC32mr : I<0x11, MRMDestMem, (outs), - (ins i32mem:$dst, GR32:$src2), + [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>, + OpSize; + def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(store (X86adde_flag (load addr:$dst), GR32:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; - def ADC8mi : Ii8<0x80, MRM2m, (outs), - (ins i8mem:$dst, i8imm:$src2), + [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>; + def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2), "adc{b}\t{$src2, $dst|$dst, $src2}", - [(store (X86adde_flag (loadi8 addr:$dst), imm:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; - def ADC16mi : Ii16<0x81, MRM2m, (outs), - (ins i16mem:$dst, i16imm:$src2), + [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; + def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(store (X86adde_flag (loadi16 addr:$dst), imm:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>, OpSize; - def ADC16mi8 : Ii8<0x83, MRM2m, (outs), - (ins i16mem:$dst, i16i8imm :$src2), + [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, + OpSize; + def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2), "adc{w}\t{$src2, $dst|$dst, $src2}", - [(store (X86adde_flag (load addr:$dst), i16immSExt8:$src2, - EFLAGS), - addr:$dst), - (implicit EFLAGS)]>, OpSize; - def ADC32mi : Ii32<0x81, MRM2m, (outs), - (ins i32mem:$dst, i32imm:$src2), + [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, + OpSize; + def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(store (X86adde_flag (loadi32 addr:$dst), imm:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; - def ADC32mi8 : Ii8<0x83, MRM2m, (outs), - (ins i32mem:$dst, i32i8imm:$src2), + [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; + def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2), "adc{l}\t{$src2, $dst|$dst, $src2}", - [(store (X86adde_flag (load addr:$dst), i32immSExt8:$src2, - EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; - } + [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; +} } // Uses = [EFLAGS] // Register-Register Subtraction @@ -2506,115 +2453,77 @@ def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), "sbb{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (X86sube_flag GR8:$src1, GR8:$src2, EFLAGS)), - (implicit EFLAGS)]>; + [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>; def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, - (X86sube_flag GR16:$src1, GR16:$src2, EFLAGS)), - (implicit EFLAGS)]>, OpSize; + [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize; def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, - (X86sube_flag GR32:$src1, GR32:$src2, EFLAGS)), - (implicit EFLAGS)]>; + [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; let isTwoAddress = 0 in { def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), "sbb{b}\t{$src2, $dst|$dst, $src2}", - [(store (X86sube_flag (load addr:$dst), GR8:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; + [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>; def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(store (X86sube_flag (load addr:$dst), GR16:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>, + [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>, OpSize; def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(store (X86sube_flag (load addr:$dst), GR32:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; + [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>; def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2), "sbb{b}\t{$src2, $dst|$dst, $src2}", - [(store (X86sube_flag (loadi8 addr:$dst), imm:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; + [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(store (X86sube_flag (loadi16 addr:$dst), imm:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>, + [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, OpSize; def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(store (X86sube_flag (load addr:$dst), i16immSExt8:$src2, - EFLAGS), - addr:$dst), - (implicit EFLAGS)]>, + [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, OpSize; def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(store (X86sube_flag (loadi32 addr:$dst), imm:$src2, EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; + [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(store (X86sube_flag (load addr:$dst), i32immSExt8:$src2, - EFLAGS), - addr:$dst), - (implicit EFLAGS)]>; + [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; } def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2), "sbb{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, - (X86sube_flag GR8:$src1, (load addr:$src2), EFLAGS)), - (implicit EFLAGS)]>; + [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>; def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, - (X86sube_flag GR16:$src1, (load addr:$src2), EFLAGS)), - (implicit EFLAGS)]>, + [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>, OpSize; def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, - (X86sube_flag GR32:$src1, (load addr:$src2), EFLAGS)), - (implicit EFLAGS)]>; + [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>; def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), "sbb{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, - (X86sube_flag GR8:$src1, imm:$src2, EFLAGS)), - (implicit EFLAGS)]>; + [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>; def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, - (X86sube_flag GR16:$src1, imm:$src2, EFLAGS)), - (implicit EFLAGS)]>, OpSize; + [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize; def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), "sbb{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, - (X86sube_flag GR16:$src1, i16immSExt8:$src2, EFLAGS)), - (implicit EFLAGS)]>, OpSize; + [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>, + OpSize; def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, - (X86sube_flag GR32:$src1, imm:$src2, EFLAGS)), - (implicit EFLAGS)]>; + [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>; def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), "sbb{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, - (X86sube_flag GR32:$src1, i32immSExt8:$src2, EFLAGS)), - (implicit EFLAGS)]>; + [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>; } // Uses = [EFLAGS] } // Defs = [EFLAGS] Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Mon Jun 1 22:12:52 2009 @@ -399,13 +399,9 @@ } else if (PropList[i]->getName() == "SDNPHasChain") { Properties |= 1 << SDNPHasChain; } else if (PropList[i]->getName() == "SDNPOutFlag") { - Properties |= 1 << SDNPOutFlag; - assert(!(Properties & (1<getName() == "SDNPInFlag") { Properties |= 1 << SDNPInFlag; - assert(!(Properties & (1<getName() == "SDNPOptInFlag") { Properties |= 1 << SDNPOptInFlag; } else if (PropList[i]->getName() == "SDNPMayStore") { @@ -416,14 +412,6 @@ Properties |= 1 << SDNPSideEffect; } else if (PropList[i]->getName() == "SDNPMemOperand") { Properties |= 1 << SDNPMemOperand; - } else if (PropList[i]->getName() == "SDNPInI1") { - Properties |= 1 << SDNPInI1; - assert(!(Properties & (1<getName() == "SDNPOutI1") { - Properties |= 1 << SDNPOutI1; - assert(!(Properties & (1<getName() << "' on node '" << R->getName() << "'!\n"; Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Jun 1 22:12:52 2009 @@ -385,13 +385,6 @@ return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); } -/// supportsHasI1 - Return whether this target supports the implicit I1, -/// rather than Flags, for ADDC/ADDE -/// -bool CodeGenTarget::supportsHasI1() const { - return getInstructionSet()->getValueAsBit("supportsHasI1"); -} - //===----------------------------------------------------------------------===// // ComplexPattern implementation // Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.h (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.h Mon Jun 1 22:12:52 2009 @@ -43,9 +43,7 @@ SDNPMayLoad, SDNPMayStore, SDNPSideEffect, - SDNPMemOperand, - SDNPInI1, - SDNPOutI1 + SDNPMemOperand }; // ComplexPattern attributes. @@ -211,12 +209,10 @@ void getInstructionsByEnumValue(std::vector &NumberedInstructions); + /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]? /// bool isLittleEndianEncoding() const; - - /// supportsHasI1 - does this target understand HasI1 for ADDE and ADDC? - bool supportsHasI1() const; }; /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=72712&r1=72711&r2=72712&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Jun 1 22:12:52 2009 @@ -670,8 +670,7 @@ HasChain = true; FoldedChains.push_back(std::make_pair(RootName, CInfo.getNumResults())); } - if (NodeHasProperty(Child, SDNPOutFlag, CGP) || - NodeHasProperty(Child, SDNPOutI1, CGP)) { + if (NodeHasProperty(Child, SDNPOutFlag, CGP)) { assert(FoldedFlag.first == "" && FoldedFlag.second == 0 && "Pattern folded multiple nodes which produce flags?"); FoldedFlag = std::make_pair(RootName, @@ -970,10 +969,6 @@ PatternHasProperty(Pattern, SDNPInFlag, CGP); bool NodeHasOutFlag = isRoot && PatternHasProperty(Pattern, SDNPOutFlag, CGP); - bool NodeHasInI1 = isRoot && - PatternHasProperty(Pattern, SDNPInI1, CGP); - bool NodeHasOutI1 = isRoot && - PatternHasProperty(Pattern, SDNPOutI1, CGP); bool NodeHasChain = InstPatNode && PatternHasProperty(InstPatNode, SDNPHasChain, CGP); bool InputHasChain = isRoot && @@ -1059,13 +1054,10 @@ // Emit all the chain and CopyToReg stuff. bool ChainEmitted = NodeHasChain; - // InFlag and InI1 cannot both be set (checked in - // CodeGenDAGPatterns), so use the same variables for both. - if (NodeHasInFlag || HasImpInputs || NodeHasInI1) + if (NodeHasInFlag || HasImpInputs) EmitInFlagSelectCode(Pattern, "N", ChainEmitted, InFlagDecled, ResNodeDecled, true); - if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs || - NodeHasInI1) { + if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs) { if (!InFlagDecled) { emitCode("SDValue InFlag(0, 0);"); InFlagDecled = true; @@ -1121,7 +1113,7 @@ } if (NodeHasChain) Code += ", MVT::Other"; - if (NodeHasOutFlag || (NodeHasOutI1 && !CGT.supportsHasI1())) + if (NodeHasOutFlag) Code += ", MVT::Flag"; // Inputs. @@ -1181,8 +1173,7 @@ } Code += ", &Ops" + utostr(OpsNo) + "[0], Ops" + utostr(OpsNo) + ".size()"; - } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs || - NodeHasInI1) + } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs) AllOps.push_back("InFlag"); unsigned NumOps = AllOps.size(); @@ -1216,7 +1207,7 @@ NodeOps.push_back("Tmp" + utostr(ResNo)); } else { - if (NodeHasOutFlag || NodeHasOutI1) { + if (NodeHasOutFlag) { if (!InFlagDecled) { After.push_back("SDValue InFlag(ResNode, " + utostr(NumResults+NumDstRegs+(unsigned)NodeHasChain) + @@ -1237,15 +1228,13 @@ utostr(NumResults+NumDstRegs) + ")"); } - if (NodeHasOutFlag || NodeHasOutI1) { + if (NodeHasOutFlag) { if (FoldedFlag.first != "") { - ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + - ".getNode(), " + + ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + ".getNode(), " + utostr(FoldedFlag.second) + ")"); ReplaceTos.push_back("InFlag"); } else { - assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP) || - NodeHasProperty(Pattern, SDNPOutI1, CGP)); + assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP)); ReplaceFroms.push_back("SDValue(N.getNode(), " + utostr(NumPatResults + (unsigned)InputHasChain) + ")"); @@ -1262,8 +1251,7 @@ } // User does not expect the instruction would produce a chain! - if ((!InputHasChain && NodeHasChain) && - (NodeHasOutFlag || NodeHasOutI1)) { + if ((!InputHasChain && NodeHasChain) && NodeHasOutFlag) { ; } else if (InputHasChain && !NodeHasChain) { // One of the inner node produces a chain. @@ -1403,8 +1391,6 @@ unsigned OpNo = (unsigned) NodeHasProperty(N, SDNPHasChain, CGP); bool HasInFlag = NodeHasProperty(N, SDNPInFlag, CGP); - bool HasInI1 = NodeHasProperty(N, SDNPInI1, CGP); - bool InFlagDefined = false; for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) { TreePatternNode *Child = N->getChild(i); if (!Child->isLeaf()) { @@ -1438,41 +1424,21 @@ emitCode("SDValue InFlag(0, 0);"); InFlagDecled = true; } - if (HasInI1) { - if (!ResNodeDecled) { - emitCode("SDNode * ResNode;"); - } - if (T.supportsHasI1()) - emitCode("ResNode = CurDAG->getCopyToReg(" + ChainName + - ", " + RootName + ".getDebugLoc()" + - ", " + getEnumName(RVT) + - ", " + getQualifiedName(RR) + - ", " + RootName + utostr(OpNo) + ").getNode();"); - else - emitCode("ResNode = CurDAG->getCopyToReg(" + ChainName + - ", " + RootName + ".getDebugLoc()" + - ", " + getQualifiedName(RR) + - ", " + RootName + utostr(OpNo) + - ", InFlag).getNode();"); - InFlagDefined = true; - } else { - std::string Decl = (!ResNodeDecled) ? "SDNode *" : ""; - emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + ChainName + + std::string Decl = (!ResNodeDecled) ? "SDNode *" : ""; + emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + ChainName + ", " + RootName + ".getDebugLoc()" + ", " + getQualifiedName(RR) + - ", " + RootName + utostr(OpNo) + - ", InFlag).getNode();"); - } + ", " + RootName + utostr(OpNo) + ", InFlag).getNode();"); + ResNodeDecled = true; emitCode(ChainName + " = SDValue(ResNode, 0);"); emitCode("InFlag = SDValue(ResNode, 1);"); - ResNodeDecled = true; } } } } } - if (HasInFlag || (HasInI1 && !InFlagDefined)) { + if (HasInFlag) { if (!InFlagDecled) { emitCode("SDValue InFlag = " + RootName + ".getOperand(" + utostr(OpNo) + ");"); From eli.friedman at gmail.com Mon Jun 1 22:47:55 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 1 Jun 2009 20:47:55 -0700 Subject: [llvm-commits] [llvm] r72707 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/X86/ utils/TableGen/ In-Reply-To: <200906012327.n51NRMqY006632@zion.cs.uiuc.edu> References: <200906012327.n51NRMqY006632@zion.cs.uiuc.edu> Message-ID: On Mon, Jun 1, 2009 at 4:27 PM, Dale Johannesen wrote: > Author: johannes > Date: Mon Jun ?1 18:27:20 2009 > New Revision: 72707 > > URL: http://llvm.org/viewvc/llvm-project?rev=72707&view=rev > Log: > Make the implicit inputs and outputs of target-independent > ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) > instead of MVT::Flag. ?Remove CARRY_FALSE in favor of 0; adjust > all target-independent code to use this format. I noticed you backed this out... the approach seems extremely messy in terms of affecting non-x86 backends. I'd suggest instead adding a target flag that would make LegalizeTypes expand ADD/SUB using UADDO/USUBO rather than ADDC/SUBC/ADDE/SUBE. That would have no effect on non-x86 backends, and I don't think it would be too hard to make the x86 backend give the right result. -Eli From tonic at nondot.org Mon Jun 1 22:57:37 2009 From: tonic at nondot.org (Tanya Lattner) Date: Mon, 1 Jun 2009 22:57:37 -0500 Subject: [llvm-commits] CVS: llvm-www/robots.txt Message-ID: <200906020357.n523vbbo015162@zion.cs.uiuc.edu> Changes in directory llvm-www: robots.txt updated: 1.6 -> 1.7 --- Log message: Add svn to the disallow list. --- Diffs of the changes: (+1 -0) robots.txt | 1 + 1 files changed, 1 insertion(+) Index: llvm-www/robots.txt diff -u llvm-www/robots.txt:1.6 llvm-www/robots.txt:1.7 --- llvm-www/robots.txt:1.6 Tue Sep 23 12:31:03 2008 +++ llvm-www/robots.txt Mon Jun 1 22:56:41 2009 @@ -9,3 +9,4 @@ Disallow: /nightlytest2 Disallow: /devmtg/2008-08/*.m4v$ Disallow: /devmtg/2008-08/*.3gp$ +Disallow: /svn From anon at cs.uiuc.edu Tue Jun 2 04:19:10 2009 From: anon at cs.uiuc.edu (anon at cs.uiuc.edu) Date: Tue, 2 Jun 2009 04:19:10 -0500 Subject: [llvm-commits] CVS: llvm-www/demo/index.cgi Message-ID: <200906020919.n529JArG006285@zion.cs.uiuc.edu> Changes in directory llvm-www/demo: index.cgi updated: 1.98 -> 1.99 --- Log message: Turn on support for nested functions. Requested by Eric Smith. --- Diffs of the changes: (+1 -1) index.cgi | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-www/demo/index.cgi diff -u llvm-www/demo/index.cgi:1.98 llvm-www/demo/index.cgi:1.99 --- llvm-www/demo/index.cgi:1.98 Wed Mar 4 07:20:10 2009 +++ llvm-www/demo/index.cgi Tue Jun 2 04:13:14 2009 @@ -357,7 +357,7 @@ $stats = "-ftime-report" if ( $c->param('showstats') ); try_run( "llvm C/C++/Fortran front-end (llvm-gcc)", - "llvm-gcc -emit-llvm -msse3 -W -Wall -O2 $stats -o $bytecodeFile -c $inputFile > $outputFile 2>&1", + "llvm-gcc -emit-llvm -fnested-functions -msse3 -W -Wall -O2 $stats -o $bytecodeFile -c $inputFile > $outputFile 2>&1", $outputFile ); if ( $c->param('showstats') && -s $timerFile ) { From baldrick at free.fr Tue Jun 2 05:24:01 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 02 Jun 2009 12:24:01 +0200 Subject: [llvm-commits] [llvm] r72700 - in /llvm/trunk/tools/lto: LTOModule.cpp LTOModule.h In-Reply-To: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> References: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> Message-ID: <4A24FDC1.7010907@free.fr> Hi Nick, > libLTO needs to handle i386 magic objc class symbols > Parse __OBJC data structures and synthesize magic .objc_ symbols. > Also, alter mangler so that objc method names are readable. I appreciate that you're trying to solve a tricky problem, but do we really want to push this kind of objc junk into LLVM? Can't it be fixed in the objc front-end instead, or alternatively by moving this logic the llvm parts of llvm-gcc, for example? Also, I don't see how having this in LTOModule can be correct. What if someone links .bc files together by hand using llvm-link? Surely this should either be in the generic llvm linker code, or in the code generators? Ciao, Duncan. From anon at cs.uiuc.edu Tue Jun 2 10:02:05 2009 From: anon at cs.uiuc.edu (anon at cs.uiuc.edu) Date: Tue, 2 Jun 2009 10:02:05 -0500 Subject: [llvm-commits] CVS: llvm-www/demo/index.cgi Message-ID: <200906021502.n52F24HG018874@zion.cs.uiuc.edu> Changes in directory llvm-www/demo: index.cgi updated: 1.99 -> 1.100 --- Log message: The -fnested-functions option is not recognized by C++. Turn it back off again for the moment. --- Diffs of the changes: (+1 -1) index.cgi | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-www/demo/index.cgi diff -u llvm-www/demo/index.cgi:1.99 llvm-www/demo/index.cgi:1.100 --- llvm-www/demo/index.cgi:1.99 Tue Jun 2 04:13:14 2009 +++ llvm-www/demo/index.cgi Tue Jun 2 09:59:04 2009 @@ -357,7 +357,7 @@ $stats = "-ftime-report" if ( $c->param('showstats') ); try_run( "llvm C/C++/Fortran front-end (llvm-gcc)", - "llvm-gcc -emit-llvm -fnested-functions -msse3 -W -Wall -O2 $stats -o $bytecodeFile -c $inputFile > $outputFile 2>&1", + "llvm-gcc -emit-llvm -msse3 -W -Wall -O2 $stats -o $bytecodeFile -c $inputFile > $outputFile 2>&1", $outputFile ); if ( $c->param('showstats') && -s $timerFile ) { From skabet at gmail.com Tue Jun 2 04:28:48 2009 From: skabet at gmail.com (Anders Johnsen) Date: Tue, 2 Jun 2009 11:28:48 +0200 Subject: [llvm-commits] CVS: llvm-www/demo/index.cgi In-Reply-To: <200906020919.n529JArG006285@zion.cs.uiuc.edu> References: <200906020919.n529JArG006285@zion.cs.uiuc.edu> Message-ID: <5be2d90906020228v2b1707afh968accf7d89067a4@mail.gmail.com> Hi, Would it be possible to also make optimizations optional? Thanks, Anders Johnsen On Tue, Jun 2, 2009 at 11:19, wrote: > > > Changes in directory llvm-www/demo: > > index.cgi updated: 1.98 -> 1.99 > --- > Log message: > > Turn on support for nested functions. Requested by Eric Smith. > > > --- > Diffs of the changes: (+1 -1) > > index.cgi | 2 +- > 1 files changed, 1 insertion(+), 1 deletion(-) > > > Index: llvm-www/demo/index.cgi > diff -u llvm-www/demo/index.cgi:1.98 llvm-www/demo/index.cgi:1.99 > --- llvm-www/demo/index.cgi:1.98 Wed Mar 4 07:20:10 2009 > +++ llvm-www/demo/index.cgi Tue Jun 2 04:13:14 2009 > @@ -357,7 +357,7 @@ > $stats = "-ftime-report" > if ( $c->param('showstats') ); > try_run( "llvm C/C++/Fortran front-end (llvm-gcc)", > - "llvm-gcc -emit-llvm -msse3 -W -Wall -O2 $stats -o $bytecodeFile -c > $inputFile > $outputFile 2>&1", > + "llvm-gcc -emit-llvm -fnested-functions -msse3 -W -Wall -O2 $stats > -o $bytecodeFile -c $inputFile > $outputFile 2>&1", > $outputFile ); > > if ( $c->param('showstats') && -s $timerFile ) { > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090602/c98ae4f8/attachment.html From aaronngray.lists at googlemail.com Tue Jun 2 11:33:53 2009 From: aaronngray.lists at googlemail.com (Aaron Gray) Date: Tue, 2 Jun 2009 17:33:53 +0100 Subject: [llvm-commits] MachO header file creation Message-ID: <3092C7E75F0740D280018C126E4958C9@HPLAPTOP> This patch moves structures and classes into header files, providing two new headers and one new .cpp file, in preparation for merging in the Direct Object Emission changes. MachO.h * Main MachO data structures MachOWriter.h * MachOWriter class MachOWriter.cpp * MachO methods * Separated out EmitRelocations() from EmitSections() as separate function MachOCodeEmitter.h * MachOCodeEmitter class MachOCodeEmitter.cpp * MachOCodeEmitter methods * Moved clear() methods from startFunction() to finishFunction() Since there is no real usage of the MachO backend and the changes are minimal and non functional changes this proposed patch should be easy to review. Aaron -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090602/020fb1df/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: MachO.patch Type: application/octet-stream Size: 79205 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090602/020fb1df/attachment.obj From lhames at gmail.com Tue Jun 2 11:53:26 2009 From: lhames at gmail.com (Lang Hames) Date: Tue, 02 Jun 2009 16:53:26 -0000 Subject: [llvm-commits] [llvm] r72729 - in /llvm/trunk: include/llvm/CodeGen/LiveInterval.h include/llvm/CodeGen/LiveIntervalAnalysis.h include/llvm/CodeGen/LiveStackAnalysis.h lib/CodeGen/LiveInterval.cpp lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/LiveStackAnalysis.cpp lib/CodeGen/RegAllocLinearScan.cpp lib/CodeGen/SimpleRegisterCoalescing.cpp lib/CodeGen/SimpleRegisterCoalescing.h lib/CodeGen/Spiller.cpp lib/CodeGen/Spiller.h lib/CodeGen/StrongPHIElimination.cpp lib/CodeGen/VirtRegRewriter.cpp Message-ID: <200906021653.n52GrRl8022721@zion.cs.uiuc.edu> Author: lhames Date: Tue Jun 2 11:53:25 2009 New Revision: 72729 URL: http://llvm.org/viewvc/llvm-project?rev=72729&view=rev Log: Update to in-place spilling framework. Includes live interval scaling and trivial rewriter. Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h llvm/trunk/lib/CodeGen/LiveInterval.cpp llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h llvm/trunk/lib/CodeGen/Spiller.cpp llvm/trunk/lib/CodeGen/Spiller.h llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=72729&r1=72728&r2=72729&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Tue Jun 2 11:53:25 2009 @@ -113,6 +113,26 @@ VNInfoList valnos; // value#'s public: + + struct InstrSlots { + enum { + LOAD = 0, + USE = 1, + DEF = 2, + STORE = 3, + NUM = 4 + }; + + static unsigned scale(unsigned slot, unsigned factor) { + unsigned index = slot / NUM, + offset = slot % NUM; + assert(index <= ~0U / (factor * NUM) && + "Rescaled interval would overflow"); + return index * NUM * factor + offset; + } + + }; + LiveInterval(unsigned Reg, float Weight, bool IsSS = false) : reg(Reg), weight(Weight), preference(0) { if (IsSS) @@ -414,6 +434,10 @@ /// Also remove the value# from value# list. void removeValNo(VNInfo *ValNo); + /// scaleNumbering - Renumber VNI and ranges to provide gaps for new + /// instructions. + void scaleNumbering(unsigned factor); + /// getSize - Returns the sum of sizes of all the LiveRange's. /// unsigned getSize() const; Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=72729&r1=72728&r2=72729&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Tue Jun 2 11:53:25 2009 @@ -92,20 +92,12 @@ std::vector ClonedMIs; + typedef LiveInterval::InstrSlots InstrSlots; + public: static char ID; // Pass identification, replacement for typeid LiveIntervals() : MachineFunctionPass(&ID) {} - struct InstrSlots { - enum { - LOAD = 0, - USE = 1, - DEF = 2, - STORE = 3, - NUM = 4 - }; - }; - static unsigned getBaseIndex(unsigned index) { return index - (index % InstrSlots::NUM); } @@ -226,6 +218,13 @@ return getInstructionFromIndex(Index) == 0; } + /// hasGapAfterInstr - Return true if the successive instruction slot, + /// i.e. Index + InstrSlots::Num, is not occupied. + bool hasGapAfterInstr(unsigned Index) { + Index = getBaseIndex(Index + InstrSlots::NUM); + return getInstructionFromIndex(Index) == 0; + } + /// findGapBeforeInstr - Find an empty instruction slot before the /// specified index. If "Furthest" is true, find one that's furthest /// away from the index (but before any index that's occupied). @@ -394,6 +393,10 @@ /// computeNumbering - Compute the index numbering. void computeNumbering(); + /// scaleNumbering - Rescale interval numbers to introduce gaps for new + /// instructions + void scaleNumbering(int factor); + /// intervalIsInOneMBB - Returns true if the specified interval is entirely /// within a single basic block. bool intervalIsInOneMBB(const LiveInterval &li) const; Modified: llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h?rev=72729&r1=72728&r2=72729&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h Tue Jun 2 11:53:25 2009 @@ -48,6 +48,8 @@ iterator begin() { return S2IMap.begin(); } iterator end() { return S2IMap.end(); } + void scaleNumbering(int factor); + unsigned getNumIntervals() const { return (unsigned)S2IMap.size(); } LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=72729&r1=72728&r2=72729&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Jun 2 11:53:25 2009 @@ -359,6 +359,29 @@ } } +/// scaleNumbering - Renumber VNI and ranges to provide gaps for new +/// instructions. +void LiveInterval::scaleNumbering(unsigned factor) { + // Scale ranges. + for (iterator RI = begin(), RE = end(); RI != RE; ++RI) { + RI->start = InstrSlots::scale(RI->start, factor); + RI->end = InstrSlots::scale(RI->end, factor); + } + + // Scale VNI info. + for (vni_iterator VNI = vni_begin(), VNIE = vni_end(); VNI != VNIE; ++VNI) { + VNInfo *vni = *VNI; + if (vni->def != ~0U && vni->def != ~1U) { + vni->def = InstrSlots::scale(vni->def, factor); + } + + for (unsigned i = 0; i < vni->kills.size(); ++i) { + if (vni->kills[i] != 0) + vni->kills[i] = InstrSlots::scale(vni->kills[i], factor); + } + } +} + /// getLiveRangeContaining - Return the live range that contains the /// specified index, or null if there is none. LiveInterval::const_iterator Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=72729&r1=72728&r2=72729&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Tue Jun 2 11:53:25 2009 @@ -36,6 +36,7 @@ #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" #include +#include #include using namespace llvm; @@ -243,6 +244,49 @@ } } +void LiveIntervals::scaleNumbering(int factor) { + // Need to + // * scale MBB begin and end points + // * scale all ranges. + // * Update VNI structures. + // * Scale instruction numberings + + // Scale the MBB indices. + Idx2MBBMap.clear(); + for (MachineFunction::iterator MBB = mf_->begin(), MBBE = mf_->end(); + MBB != MBBE; ++MBB) { + std::pair &mbbIndices = MBB2IdxMap[MBB->getNumber()]; + mbbIndices.first = InstrSlots::scale(mbbIndices.first, factor); + mbbIndices.second = InstrSlots::scale(mbbIndices.second, factor); + Idx2MBBMap.push_back(std::make_pair(mbbIndices.first, MBB)); + } + std::sort(Idx2MBBMap.begin(), Idx2MBBMap.end(), Idx2MBBCompare()); + + // Scale the intervals. + for (iterator LI = begin(), LE = end(); LI != LE; ++LI) { + LI->second->scaleNumbering(factor); + } + + // Scale MachineInstrs. + Mi2IndexMap oldmi2iMap = mi2iMap_; + unsigned highestSlot = 0; + for (Mi2IndexMap::iterator MI = oldmi2iMap.begin(), ME = oldmi2iMap.end(); + MI != ME; ++MI) { + unsigned newSlot = InstrSlots::scale(MI->second, factor); + mi2iMap_[MI->first] = newSlot; + highestSlot = std::max(highestSlot, newSlot); + } + + i2miMap_.clear(); + i2miMap_.resize(highestSlot + 1); + for (Mi2IndexMap::iterator MI = mi2iMap_.begin(), ME = mi2iMap_.end(); + MI != ME; ++MI) { + i2miMap_[MI->second] = MI->first; + } + +} + + /// runOnMachineFunction - Register allocate the whole function /// bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { Modified: llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp?rev=72729&r1=72728&r2=72729&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp Tue Jun 2 11:53:25 2009 @@ -15,15 +15,24 @@ #define DEBUG_TYPE "livestacks" #include "llvm/CodeGen/LiveStackAnalysis.h" +#include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/Passes.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/Debug.h" #include "llvm/ADT/Statistic.h" +#include using namespace llvm; char LiveStacks::ID = 0; static RegisterPass X("livestacks", "Live Stack Slot Analysis"); +void LiveStacks::scaleNumbering(int factor) { + // Scale the intervals. + for (iterator LI = begin(), LE = end(); LI != LE; ++LI) { + LI->second.scaleNumbering(factor); + } +} + void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(AU); Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=72729&r1=72728&r2=72729&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Tue Jun 2 11:53:25 2009 @@ -40,6 +40,8 @@ #include #include #include +#include + using namespace llvm; STATISTIC(NumIters , "Number of iterations performed"); @@ -310,6 +312,93 @@ static RegisterPass X("linearscan-regalloc", "Linear Scan Register Allocator"); +bool validateRegAlloc(MachineFunction *mf, LiveIntervals *lis, + VirtRegMap *vrm) { + + MachineRegisterInfo *mri = &mf->getRegInfo(); + const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo(); + bool allocationValid = true; + + + for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); + itr != end; ++itr) { + + LiveInterval *li = itr->second; + + if (TargetRegisterInfo::isPhysicalRegister(li->reg)) { + continue; + } + + if (vrm->hasPhys(li->reg)) { + const TargetRegisterClass *trc = mri->getRegClass(li->reg); + + if (lis->hasInterval(vrm->getPhys(li->reg))) { + if (li->overlaps(lis->getInterval(vrm->getPhys(li->reg)))) { + std::cerr << "vreg " << li->reg << " overlaps its assigned preg " + << vrm->getPhys(li->reg) << "(" << tri->getName(vrm->getPhys(li->reg)) << ")\n"; + } + } + + TargetRegisterClass::iterator fReg = + std::find(trc->allocation_order_begin(*mf), trc->allocation_order_end(*mf), + vrm->getPhys(li->reg)); + + if (fReg == trc->allocation_order_end(*mf)) { + std::cerr << "preg " << vrm->getPhys(li->reg) + << "(" << tri->getName(vrm->getPhys(li->reg)) << ") is not in the allocation set for vreg " + << li->reg << "\n"; + allocationValid &= false; + } + } + else { + std::cerr << "No preg for vreg " << li->reg << "\n"; + // What about conflicting loads/stores? + continue; + } + + for (LiveIntervals::iterator itr2 = next(itr); itr2 != end; ++itr2) { + + LiveInterval *li2 = itr2->second; + + if (li2->empty()) + continue; + + if (TargetRegisterInfo::isPhysicalRegister(li2->reg)) { + if (li->overlaps(*li2)) { + if (vrm->getPhys(li->reg) == li2->reg || + tri->areAliases(vrm->getPhys(li->reg), li2->reg)) { + std::cerr << "vreg " << li->reg << " overlaps preg " + << li2->reg << "(" << tri->getName(li2->reg) << ") which aliases " + << vrm->getPhys(li->reg) << "(" << tri->getName(vrm->getPhys(li->reg)) << ")\n"; + allocationValid &= false; + } + } + } + else { + + if (!vrm->hasPhys(li2->reg)) { + continue; + } + + if (li->overlaps(*li2)) { + if (vrm->getPhys(li->reg) == vrm->getPhys(li2->reg) || + tri->areAliases(vrm->getPhys(li->reg), vrm->getPhys(li2->reg))) { + std::cerr << "vreg " << li->reg << " (preg " << vrm->getPhys(li->reg) + << ") overlaps vreg " << li2->reg << " (preg " << vrm->getPhys(li2->reg) + << ") and " << vrm->getPhys(li->reg) << " aliases " << vrm->getPhys(li2->reg) << "\n"; + allocationValid &= false; + } + } + } + } + + } + + return allocationValid; + +} + + void RALinScan::ComputeRelatedRegClasses() { // First pass, add all reg classes to the union, and determine at least one // reg class that each register is in. @@ -430,16 +519,17 @@ if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter()); if (NewSpillFramework) { - spiller_.reset(createSpiller(mf_, li_, vrm_)); - } - else { - spiller_.reset(0); + spiller_.reset(createSpiller(mf_, li_, ls_, vrm_)); } - + initIntervalSets(); linearScan(); + if (NewSpillFramework) { + bool allocValid = validateRegAlloc(mf_, li_, vrm_); + } + // Rewrite spill code and update the PhysRegsUsed set. rewriter_->runOnMachineFunction(*mf_, *vrm_, li_); @@ -454,6 +544,7 @@ NextReloadMap.clear(); DowngradedRegs.clear(); DowngradeMap.clear(); + spiller_.reset(0); return true; } @@ -1127,8 +1218,7 @@ if (!NewSpillFramework) { added = li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_); - } - else { + } else { added = spiller_->spill(cur); } @@ -1192,7 +1282,9 @@ // The earliest start of a Spilled interval indicates up to where // in handled we need to roll back + unsigned earliestStart = cur->beginNumber(); + LiveInterval *earliestStartInterval = cur; // Spill live intervals of virtual regs mapped to the physical register we // want to clear (and its aliases). We only spill those that overlap with the @@ -1201,17 +1293,48 @@ // mark our rollback point. std::vector added; while (!spillIs.empty()) { + bool epicFail = false; LiveInterval *sli = spillIs.back(); spillIs.pop_back(); DOUT << "\t\t\tspilling(a): " << *sli << '\n'; earliestStart = std::min(earliestStart, sli->beginNumber()); - std::vector newIs = - li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_); + earliestStartInterval = + (earliestStartInterval->beginNumber() < sli->beginNumber()) ? + earliestStartInterval : sli; + + if (earliestStartInterval->beginNumber()!=earliestStart) { + epicFail |= true; + std::cerr << "What the 1 - " + << "earliestStart = " << earliestStart + << "earliestStartInterval = " << earliestStartInterval->beginNumber() + << "\n"; + } + + std::vector newIs; + if (!NewSpillFramework) { + newIs = li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_); + } else { + newIs = spiller_->spill(sli); + } addStackInterval(sli, ls_, li_, mri_, *vrm_); std::copy(newIs.begin(), newIs.end(), std::back_inserter(added)); spilled.insert(sli->reg); + + if (earliestStartInterval->beginNumber()!=earliestStart) { + epicFail |= true; + std::cerr << "What the 2 - " + << "earliestStart = " << earliestStart + << "earliestStartInterval = " << earliestStartInterval->beginNumber() + << "\n"; + } + + if (epicFail) { + //abort(); + } } + earliestStart = earliestStartInterval->beginNumber(); + DOUT << "\t\trolling back to: " << earliestStart << '\n'; // Scan handled in reverse order up to the earliest start of a Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=72729&r1=72728&r2=72729&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue Jun 2 11:53:25 2009 @@ -2598,7 +2598,7 @@ static bool isZeroLengthInterval(LiveInterval *li) { for (LiveInterval::Ranges::const_iterator i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i) - if (i->end - i->start > LiveIntervals::InstrSlots::NUM) + if (i->end - i->start > LiveInterval::InstrSlots::NUM) return false; return true; } Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=72729&r1=72728&r2=72729&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Tue Jun 2 11:53:25 2009 @@ -133,7 +133,7 @@ if (!li_->hasInterval(Reg)) return 0; return li_->getApproximateInstructionCount(li_->getInterval(Reg)) * - LiveIntervals::InstrSlots::NUM; + LiveInterval::InstrSlots::NUM; } /// print - Implement the dump method. Modified: llvm/trunk/lib/CodeGen/Spiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=72729&r1=72728&r2=72729&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Spiller.cpp (original) +++ llvm/trunk/lib/CodeGen/Spiller.cpp Tue Jun 2 11:53:25 2009 @@ -12,6 +12,7 @@ #include "Spiller.h" #include "VirtRegMap.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" +#include "llvm/CodeGen/LiveStackAnalysis.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -19,28 +20,105 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/Debug.h" -#include -#include - using namespace llvm; Spiller::~Spiller() {} namespace { -class TrivialSpiller : public Spiller { -public: - TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm) : - mf(mf), lis(lis), vrm(vrm) +/// Utility class for spillers. +class SpillerBase : public Spiller { +protected: + + MachineFunction *mf; + LiveIntervals *lis; + LiveStacks *ls; + MachineFrameInfo *mfi; + MachineRegisterInfo *mri; + const TargetInstrInfo *tii; + VirtRegMap *vrm; + + /// Construct a spiller base. + SpillerBase(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls, VirtRegMap *vrm) : + mf(mf), lis(lis), ls(ls), vrm(vrm) { mfi = mf->getFrameInfo(); mri = &mf->getRegInfo(); tii = mf->getTarget().getInstrInfo(); } - std::vector spill(LiveInterval *li) { + /// Insert a store of the given vreg to the given stack slot immediately + /// after the given instruction. Returns the base index of the inserted + /// instruction. The caller is responsible for adding an appropriate + /// LiveInterval to the LiveIntervals analysis. + unsigned insertStoreFor(MachineInstr *mi, unsigned ss, + unsigned newVReg, + const TargetRegisterClass *trc) { + MachineBasicBlock::iterator nextInstItr(mi); + ++nextInstItr; + + if (!lis->hasGapAfterInstr(lis->getInstructionIndex(mi))) { + lis->scaleNumbering(2); + ls->scaleNumbering(2); + } + + unsigned miIdx = lis->getInstructionIndex(mi); + + assert(lis->hasGapAfterInstr(miIdx)); + + tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, newVReg, + true, ss, trc); + MachineBasicBlock::iterator storeInstItr(mi); + ++storeInstItr; + MachineInstr *storeInst = &*storeInstItr; + unsigned storeInstIdx = miIdx + LiveInterval::InstrSlots::NUM; + + assert(lis->getInstructionFromIndex(storeInstIdx) == 0 && + "Store inst index already in use."); + + lis->InsertMachineInstrInMaps(storeInst, storeInstIdx); + + return storeInstIdx; + } + + /// Insert a load of the given veg from the given stack slot immediately + /// before the given instruction. Returns the base index of the inserted + /// instruction. The caller is responsible for adding an appropriate + /// LiveInterval to the LiveIntervals analysis. + unsigned insertLoadFor(MachineInstr *mi, unsigned ss, + unsigned newVReg, + const TargetRegisterClass *trc) { + MachineBasicBlock::iterator useInstItr(mi); + + if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) { + lis->scaleNumbering(2); + ls->scaleNumbering(2); + } + + unsigned miIdx = lis->getInstructionIndex(mi); + + assert(lis->hasGapBeforeInstr(miIdx)); + + tii->loadRegFromStackSlot(*mi->getParent(), useInstItr, newVReg, ss, trc); + MachineBasicBlock::iterator loadInstItr(mi); + --loadInstItr; + MachineInstr *loadInst = &*loadInstItr; + unsigned loadInstIdx = miIdx - LiveInterval::InstrSlots::NUM; + + assert(lis->getInstructionFromIndex(loadInstIdx) == 0 && + "Load inst index already in use."); + + lis->InsertMachineInstrInMaps(loadInst, loadInstIdx); + + return loadInstIdx; + } - DOUT << "Trivial spiller spilling " << *li << "\n"; + + /// Add spill ranges for every use/def of the live interval, inserting loads + /// immediately before each use, and stores after each def. No folding is + /// attempted. + std::vector trivialSpillEverywhere(LiveInterval *li) { + DOUT << "Spilling everywhere " << *li << "\n"; assert(li->weight != HUGE_VALF && "Attempting to spill already spilled value."); @@ -51,16 +129,16 @@ std::vector added; const TargetRegisterClass *trc = mri->getRegClass(li->reg); - /*unsigned ss = mfi->CreateStackObject(trc->getSize(), - trc->getAlignment());*/ unsigned ss = vrm->assignVirt2StackSlot(li->reg); - MachineRegisterInfo::reg_iterator regItr = mri->reg_begin(li->reg); - - while (regItr != mri->reg_end()) { + for (MachineRegisterInfo::reg_iterator + regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) { MachineInstr *mi = &*regItr; - + do { + ++regItr; + } while (regItr != mri->reg_end() && (&*regItr == mi)); + SmallVector indices; bool hasUse = false; bool hasDef = false; @@ -78,12 +156,12 @@ } unsigned newVReg = mri->createVirtualRegister(trc); - LiveInterval *newLI = &lis->getOrCreateInterval(newVReg); - newLI->weight = HUGE_VALF; - vrm->grow(); vrm->assignVirt2StackSlot(newVReg, ss); + LiveInterval *newLI = &lis->getOrCreateInterval(newVReg); + newLI->weight = HUGE_VALF; + for (unsigned i = 0; i < indices.size(); ++i) { mi->getOperand(indices[i]).setReg(newVReg); @@ -92,6 +170,8 @@ } } + assert(hasUse || hasDef); + if (hasUse) { unsigned loadInstIdx = insertLoadFor(mi, ss, newVReg, trc); unsigned start = lis->getDefIndex(loadInstIdx), @@ -103,7 +183,6 @@ LiveRange lr(start, end, vni); newLI->addRange(lr); - added.push_back(newLI); } if (hasDef) { @@ -117,90 +196,34 @@ LiveRange lr(start, end, vni); newLI->addRange(lr); - added.push_back(newLI); } - regItr = mri->reg_begin(li->reg); + added.push_back(newLI); } return added; } +}; -private: - - MachineFunction *mf; - LiveIntervals *lis; - MachineFrameInfo *mfi; - MachineRegisterInfo *mri; - const TargetInstrInfo *tii; - VirtRegMap *vrm; - - - - void makeRoomForInsertBefore(MachineInstr *mi) { - if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) { - lis->computeNumbering(); - } - - assert(lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))); - } - - unsigned insertStoreFor(MachineInstr *mi, unsigned ss, - unsigned newVReg, - const TargetRegisterClass *trc) { - MachineBasicBlock::iterator nextInstItr(mi); - ++nextInstItr; - - makeRoomForInsertBefore(&*nextInstItr); - - unsigned miIdx = lis->getInstructionIndex(mi); - - tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, newVReg, - true, ss, trc); - MachineBasicBlock::iterator storeInstItr(mi); - ++storeInstItr; - MachineInstr *storeInst = &*storeInstItr; - unsigned storeInstIdx = miIdx + LiveIntervals::InstrSlots::NUM; - - assert(lis->getInstructionFromIndex(storeInstIdx) == 0 && - "Store inst index already in use."); - - lis->InsertMachineInstrInMaps(storeInst, storeInstIdx); - - return storeInstIdx; - } - - unsigned insertLoadFor(MachineInstr *mi, unsigned ss, - unsigned newVReg, - const TargetRegisterClass *trc) { - MachineBasicBlock::iterator useInstItr(mi); - - makeRoomForInsertBefore(mi); - - unsigned miIdx = lis->getInstructionIndex(mi); - - tii->loadRegFromStackSlot(*mi->getParent(), useInstItr, newVReg, ss, trc); - MachineBasicBlock::iterator loadInstItr(mi); - --loadInstItr; - MachineInstr *loadInst = &*loadInstItr; - unsigned loadInstIdx = miIdx - LiveIntervals::InstrSlots::NUM; - assert(lis->getInstructionFromIndex(loadInstIdx) == 0 && - "Load inst index already in use."); - - lis->InsertMachineInstrInMaps(loadInst, loadInstIdx); +/// Spills any live range using the spill-everywhere method with no attempt at +/// folding. +class TrivialSpiller : public SpillerBase { +public: + TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls, VirtRegMap *vrm) : + SpillerBase(mf, lis, ls, vrm) {} - return loadInstIdx; + std::vector spill(LiveInterval *li) { + return trivialSpillEverywhere(li); } }; } - llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis, - VirtRegMap *vrm) { - return new TrivialSpiller(mf, lis, vrm); + LiveStacks *ls, VirtRegMap *vrm) { + return new TrivialSpiller(mf, lis, ls, vrm); } Modified: llvm/trunk/lib/CodeGen/Spiller.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.h?rev=72729&r1=72728&r2=72729&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Spiller.h (original) +++ llvm/trunk/lib/CodeGen/Spiller.h Tue Jun 2 11:53:25 2009 @@ -13,8 +13,9 @@ #include namespace llvm { - struct LiveInterval; + class LiveInterval; class LiveIntervals; + class LiveStacks; class MachineFunction; class VirtRegMap; @@ -30,7 +31,7 @@ /// Create and return a spiller object, as specified on the command line. Spiller* createSpiller(MachineFunction *mf, LiveIntervals *li, - VirtRegMap *vrm); + LiveStacks *ls, VirtRegMap *vrm); } #endif Modified: llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp?rev=72729&r1=72728&r2=72729&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Tue Jun 2 11:53:25 2009 @@ -1027,7 +1027,7 @@ if (MBB != PInstr->getParent() && InputI.liveAt(LI.getMBBStartIdx(PInstr->getParent())) && InputI.expiredAt(LI.getInstructionIndex(PInstr) + - LiveIntervals::InstrSlots::NUM)) + LiveInterval::InstrSlots::NUM)) InputI.removeRange(LI.getMBBStartIdx(PInstr->getParent()), LI.getInstructionIndex(PInstr), true); Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=72729&r1=72728&r2=72729&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Tue Jun 2 11:53:25 2009 @@ -33,15 +33,16 @@ STATISTIC(NumModRefUnfold, "Number of modref unfolded"); namespace { - enum RewriterName { simple, local }; + enum RewriterName { simple, local, trivial }; } static cl::opt RewriterOpt("rewriter", cl::desc("Rewriter to use: (default: local)"), cl::Prefix, - cl::values(clEnumVal(simple, "simple rewriter"), - clEnumVal(local, "local rewriter"), + cl::values(clEnumVal(simple, "simple rewriter"), + clEnumVal(local, "local rewriter"), + clEnumVal(trivial, "trivial rewriter"), clEnumValEnd), cl::init(local)); @@ -126,6 +127,42 @@ }; +/// This class is intended for use with the new spilling framework only. It +/// rewrites vreg def/uses to use the assigned preg, but does not insert any +/// spill code. +struct VISIBILITY_HIDDEN TrivialRewriter : public VirtRegRewriter { + + bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM, + LiveIntervals* LIs) { + DOUT << "********** REWRITE MACHINE CODE **********\n"; + DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; + MachineRegisterInfo *mri = &MF.getRegInfo(); + + bool changed = false; + + for (LiveIntervals::iterator liItr = LIs->begin(), liEnd = LIs->end(); + liItr != liEnd; ++liItr) { + + if (TargetRegisterInfo::isVirtualRegister(liItr->first)) { + if (VRM.hasPhys(liItr->first)) { + unsigned preg = VRM.getPhys(liItr->first); + mri->replaceRegWith(liItr->first, preg); + mri->setPhysRegUsed(preg); + changed = true; + } + } + else { + if (!liItr->second->empty()) { + mri->setPhysRegUsed(liItr->first); + } + } + } + + return changed; + } + +}; + // ************************************************************************ // /// AvailableSpills - As the local rewriter is scanning and rewriting an MBB @@ -2182,5 +2219,7 @@ return new LocalRewriter(); case simple: return new SimpleRewriter(); + case trivial: + return new TrivialRewriter(); } } From devang.patel at gmail.com Tue Jun 2 12:04:55 2009 From: devang.patel at gmail.com (Devang Patel) Date: Tue, 2 Jun 2009 10:04:55 -0700 Subject: [llvm-commits] [llvm] r72700 - in /llvm/trunk/tools/lto: LTOModule.cpp LTOModule.h In-Reply-To: <4A24FDC1.7010907@free.fr> References: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> <4A24FDC1.7010907@free.fr> Message-ID: <352a1fb20906021004va2266dak4fd12227c4469f65@mail.gmail.com> On Tue, Jun 2, 2009 at 3:24 AM, Duncan Sands wrote: > > What if someone links .bc files together by hand using llvm-link? > Why do you think it won't work without this LTOModule patch ? - Devang From dpatel at apple.com Tue Jun 2 12:26:30 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 02 Jun 2009 17:26:30 -0000 Subject: [llvm-commits] [llvm] r72731 - /llvm/trunk/include/llvm/PassAnalysisSupport.h Message-ID: <200906021726.n52HQUp6023854@zion.cs.uiuc.edu> Author: dpatel Date: Tue Jun 2 12:26:29 2009 New Revision: 72731 URL: http://llvm.org/viewvc/llvm-project?rev=72731&view=rev Log: Simplify assertion message to avoid confusion. Modified: llvm/trunk/include/llvm/PassAnalysisSupport.h Modified: llvm/trunk/include/llvm/PassAnalysisSupport.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassAnalysisSupport.h?rev=72731&r1=72730&r2=72731&view=diff ============================================================================== --- llvm/trunk/include/llvm/PassAnalysisSupport.h (original) +++ llvm/trunk/include/llvm/PassAnalysisSupport.h Tue Jun 2 12:26:29 2009 @@ -226,23 +226,21 @@ template AnalysisType &Pass::getAnalysisID(const PassInfo *PI, Function &F) { assert(PI && "getAnalysis for unregistered pass!"); - assert(Resolver&&"Pass has not been inserted into a PassManager object!"); - // PI *must* appear in AnalysisImpls. Because the number of passes used - // should be a small number, we just do a linear search over a (dense) - // vector. - Pass *ResultPass = Resolver->findImplPass(this, PI, F); - assert (ResultPass && - "getAnalysis*() called on an analysis that was not " - "'required' by pass!"); - - // Because the AnalysisType may not be a subclass of pass (for - // AnalysisGroups), we must use dynamic_cast here to potentially adjust the - // return pointer (because the class may multiply inherit, once from pass, - // once from AnalysisType). - // - AnalysisType *Result = dynamic_cast(ResultPass); - assert(Result && "Pass does not implement interface required!"); - return *Result; + assert(Resolver && "Pass has not been inserted into a PassManager object!"); + // PI *must* appear in AnalysisImpls. Because the number of passes used + // should be a small number, we just do a linear search over a (dense) + // vector. + Pass *ResultPass = Resolver->findImplPass(this, PI, F); + assert (ResultPass && "Unable to find requested analysis info"); + + // Because the AnalysisType may not be a subclass of pass (for + // AnalysisGroups), we must use dynamic_cast here to potentially adjust the + // return pointer (because the class may multiply inherit, once from pass, + // once from AnalysisType). + // + AnalysisType *Result = dynamic_cast(ResultPass); + assert(Result && "Pass does not implement interface required!"); + return *Result; } } // End llvm namespace From devang.patel at gmail.com Tue Jun 2 12:32:46 2009 From: devang.patel at gmail.com (Devang Patel) Date: Tue, 2 Jun 2009 10:32:46 -0700 Subject: [llvm-commits] [llvm] r70270 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Alpha/AsmPrinter/ lib Message-ID: <352a1fb20906021032tb1909afn3c2e0eb8818f0d82@mail.gmail.com> On Mon, Apr 27, 2009 at 5:21 PM, Bill Wendling wrote: > Author: void Date: Mon Apr 27 19:21:31 2009 New Revision: 70270 URL: >http://llvm.org/viewvc/llvm-project?rev=70270&view=rev Log: Massive check in. This >changes the "-fast" flag to "-O#" in llc. If you want to use the old behavior, the flag is -O0. >This change allows for finer-grained control over which optimizations are run at different -O >levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying >that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'm not 100% sure >if it's necessary to change it there... We won't to encode this info in bit code and avoid globals like this. We already use a function attribute for -Os. Why not do the same here ? - Devang From resistor at mac.com Tue Jun 2 12:35:55 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Jun 2009 17:35:55 -0000 Subject: [llvm-commits] [llvm] r72732 - /llvm/trunk/lib/System/Atomic.cpp Message-ID: <200906021735.n52HZuoZ024144@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 2 12:35:55 2009 New Revision: 72732 URL: http://llvm.org/viewvc/llvm-project?rev=72732&view=rev Log: Undef MemoryFence when compiling on MSVC. Modified: llvm/trunk/lib/System/Atomic.cpp Modified: llvm/trunk/lib/System/Atomic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Atomic.cpp?rev=72732&r1=72731&r2=72732&view=diff ============================================================================== --- llvm/trunk/lib/System/Atomic.cpp (original) +++ llvm/trunk/lib/System/Atomic.cpp Tue Jun 2 12:35:55 2009 @@ -18,6 +18,7 @@ #if defined(_MSC_VER) #include +#undef MemoryFence #endif void sys::MemoryFence() { From evan.cheng at apple.com Tue Jun 2 13:00:46 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 2 Jun 2009 11:00:46 -0700 Subject: [llvm-commits] [llvm] r72707 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/X86/ utils/TableGen/ In-Reply-To: <200906012327.n51NRMqY006632@zion.cs.uiuc.edu> References: <200906012327.n51NRMqY006632@zion.cs.uiuc.edu> Message-ID: <668F172C-93E7-47E8-9B1F-333154602253@apple.com> Hi Dale, On first glance, the patch mostly looks good. But I don't care for "supportsHasI1". I would have added ADDC_FLAG / ADDE_FLAG opcodes and have those use MVT::EFLAGS and change ADDC / ADDE to use MVT::i1 to represent the flag value. Thanks, Evan On Jun 1, 2009, at 4:27 PM, Dale Johannesen wrote: > Author: johannes > Date: Mon Jun 1 18:27:20 2009 > New Revision: 72707 > > URL: http://llvm.org/viewvc/llvm-project?rev=72707&view=rev > Log: > Make the implicit inputs and outputs of target-independent > ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) > instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust > all target-independent code to use this format. > > Most targets will still produce a Flag-setting target-dependent > version when selection is done. X86 is converted to use i32 > instead, which means TableGen needs to produce different code > in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit > in xxxInstrInfo, currently set only for X86; in principle this > is temporary and should go away when all other targets have > been converted. All relevant X86 instruction patterns are > modified to represent setting and using EFLAGS explicitly. The > same can be done on other targets. > > The immediate behavior change is that an ADC/ADD pair are no > longer tightly coupled in the X86 scheduler; they can be > separated by instructions that don't clobber the flags (MOV). > I will soon add some peephole optimizations based on using > other instructions that set the flags to feed into ADC. > > > Modified: > llvm/trunk/include/llvm/CodeGen/SelectionDAG.h > llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h > llvm/trunk/include/llvm/Target/Target.td > llvm/trunk/include/llvm/Target/TargetSelectionDAG.td > llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h > llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > llvm/trunk/lib/Target/X86/X86ISelLowering.h > llvm/trunk/lib/Target/X86/X86Instr64bit.td > llvm/trunk/lib/Target/X86/X86InstrInfo.td > llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp > llvm/trunk/utils/TableGen/CodeGenTarget.cpp > llvm/trunk/utils/TableGen/CodeGenTarget.h > llvm/trunk/utils/TableGen/DAGISelEmitter.cpp > > Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) > +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Jun 1 > 18:27:20 2009 > @@ -324,6 +324,14 @@ > return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, > getRegister(Reg, N.getValueType()), N); > } > + // This version of getCopyToReg has the register (and its type) > as an > + // explicit output. > + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, MVT VT, unsigned > Reg, > + SDValue N) { > + SDVTList VTs = getVTList(MVT::Other, VT); > + SDValue Ops[] = { Chain, getRegister(Reg, VT), N}; > + return getNode(ISD::CopyToReg, dl, VTs, Ops, 3); > + } > > // This version of the getCopyToReg method takes an extra operand, > which > // indicates that there is potentially an incoming flag value (if > Flag is not > > Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) > +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Jun 1 > 18:27:20 2009 > @@ -242,14 +242,11 @@ > // remainder result. > SDIVREM, UDIVREM, > > - // CARRY_FALSE - This node is used when folding other nodes, > - // like ADDC/SUBC, which indicate the carry result is always > false. > - CARRY_FALSE, > - > // Carry-setting nodes for multiple precision addition and > subtraction. > // These nodes take two operands of the same value type, and > produce two > // results. The first result is the normal add or sub result, > the second > - // result is the carry flag result. > + // result is the carry flag result (type i1 or whatever it got > expanded to > + // for the target, value 0 or 1). > ADDC, SUBC, > > // Carry-using nodes for multiple precision addition and > subtraction. These > @@ -258,7 +255,8 @@ > // produce two results; the normal result of the add or sub, and > the output > // carry flag. These nodes both read and write a carry flag to > allow them > // to them to be chained together for add and sub of arbitrarily > large > - // values. > + // values. The carry flag (input and output) has type i1 or > whatever it > + // got expanded to for the target, and has value 0 or 1. > ADDE, SUBE, > > // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for > addition. > > Modified: llvm/trunk/include/llvm/Target/Target.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Target/Target.td (original) > +++ llvm/trunk/include/llvm/Target/Target.td Mon Jun 1 18:27:20 2009 > @@ -326,6 +326,11 @@ > // Sparc manual specifies its instructions in the format [31..0] > (big), while > // PowerPC specifies them using the format [0..31] (little). > bit isLittleEndianEncoding = 0; > + > + // Targets that can support the HasI1 argument on ADDC and ADDE, > rather than > + // Flag, have this bit set. This is transitional and should go > away when all > + // targets have been switched over. > + bit supportsHasI1 = 0; > } > > // Standard Instructions. > > Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) > +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Mon Jun 1 > 18:27:20 2009 > @@ -216,6 +216,8 @@ > def SDNPMayLoad : SDNodeProperty; // May read memory, sets > 'mayLoad'. > def SDNPSideEffect : SDNodeProperty; // Sets > 'HasUnmodelledSideEffects'. > def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc > MemOperand > +def SDNPInI1 : SDNodeProperty; // Read an extra I1 operand > +def SDNPOutI1 : SDNodeProperty; // Write an extra I1 result > > // > = > = > = > ----------------------------------------------------------------------= > ==// > // Selection DAG Node definitions. > @@ -289,13 +291,13 @@ > def xor : SDNode<"ISD::XOR" , SDTIntBinOp, > [SDNPCommutative, SDNPAssociative]>; > def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, > - [SDNPCommutative, SDNPOutFlag]>; > + [SDNPCommutative, SDNPOutI1]>; > def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, > - [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; > + [SDNPCommutative, SDNPInI1, SDNPOutI1]>; > def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, > - [SDNPOutFlag]>; > + [SDNPOutI1]>; > def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, > - [SDNPOutFlag, SDNPInFlag]>; > + [SDNPInI1, SDNPOutI1]>; > > def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; > def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jun 1 > 18:27:20 2009 > @@ -1085,8 +1085,7 @@ > // If the flag result is dead, turn this into an ADD. > if (N->hasNUsesOfValue(0, 1)) > return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, > N1, N0), > - DAG.getNode(ISD::CARRY_FALSE, > - N->getDebugLoc(), MVT::Flag)); > + DAG.getConstant(0, N->getValueType(1))); > > // canonicalize constant to RHS. > if (N0C && !N1C) > @@ -1094,10 +1093,9 @@ > > // fold (addc x, 0) -> x + no carry out > if (N1C && N1C->isNullValue()) > - return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, > - N->getDebugLoc(), > MVT::Flag)); > + return CombineTo(N, N0, DAG.getConstant(0, N1.getValueType())); > > - // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share > no bits. > + // fold (addc a, b) -> (or a, b), 0 iff a and b share no bits. > APInt LHSZero, LHSOne; > APInt RHSZero, RHSOne; > APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); > @@ -1111,8 +1109,7 @@ > if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || > (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) > return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, > N0, N1), > - DAG.getNode(ISD::CARRY_FALSE, > - N->getDebugLoc(), MVT::Flag)); > + DAG.getConstant(0, N1.getValueType())); > } > > return SDValue(); > @@ -1131,8 +1128,9 @@ > N1, N0, CarryIn); > > // fold (adde x, y, false) -> (addc x, y) > - if (CarryIn.getOpcode() == ISD::CARRY_FALSE) > - return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), > N1, N0); > + if (ConstantSDNode *N2C = dyn_cast(CarryIn)) > + if (N2C->getAPIntValue()==0) > + return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList > (), N1, N0); > > return SDValue(); > } > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp > (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon > Jun 1 18:27:20 2009 > @@ -98,6 +98,10 @@ > case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); > break; > case ISD::SMULO: > case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; > + case ISD::ADDC: > + case ISD::SUBC: Res = PromoteIntRes_ADDSUBC(N, ResNo); > break; > + case ISD::ADDE: > + case ISD::SUBE: Res = PromoteIntRes_ADDSUBE(N, ResNo); > break; > > case ISD::ATOMIC_LOAD_ADD: > case ISD::ATOMIC_LOAD_SUB: > @@ -121,6 +125,35 @@ > SetPromotedInteger(SDValue(N, ResNo), Res); > } > > +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBC(SDNode *N, unsigned > ResNo) { > + // Only the carry bit result is expected to be promoted. > + assert(ResNo == 1 && "Only carry bit result promotion currently > supported!"); > + return PromoteIntRes_Overflow(N); > +} > + > +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBE(SDNode *N, unsigned > ResNo) { > + // Only the carry bit result is expected to be promoted. > + assert(ResNo == 1 && "Only carry bit result promotion currently > supported!"); > + // This is a ternary operator, so clone a slightly modified > + // PromoteIntRes_Overflow here (this is the only client). > + if (ResNo == 1) { > + // Simply change the return type of the boolean result. > + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); > + MVT ValueVTs[] = { N->getValueType(0), NVT }; > + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N- > >getOperand(2) }; > + SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), > + DAG.getVTList(ValueVTs, 2), Ops, 3); > + > + // Modified the sum result - switch anything that used the old > sum to use > + // the new one. > + ReplaceValueWith(SDValue(N, 0), Res); > + > + return SDValue(Res.getNode(), 1); > + } > + assert(0 && "Do not know how to promote this operator!"); > + abort(); > +} > + > SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { > // Sign-extend the new bits, and continue the assertion. > SDValue Op = SExtPromotedInteger(N->getOperand(0)); > @@ -419,7 +452,7 @@ > return Res; > } > > -/// Promote the overflow flag of an overflowing arithmetic node. > +/// Promote the overflow or carry result of an overflowing > arithmetic node. > SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { > // Simply change the return type of the boolean result. > MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); > @@ -666,6 +699,8 @@ > assert(0 && "Do not know how to promote this operator's > operand!"); > abort(); > > + case ISD::ADDE: > + case ISD::SUBE: Res = PromoteIntOp_ADDSUBE(N, OpNo); break; > case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; > case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; > case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; > @@ -743,6 +778,13 @@ > } > } > > +SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBE(SDNode *N, unsigned > OpNo) { > + assert(OpNo == 2 && "Don't know how to promote this operand!"); > + return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), > + N->getOperand(1), > + GetPromotedInteger(N->getOperand > (2))); > +} > + > SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { > SDValue Op = GetPromotedInteger(N->getOperand(0)); > return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N- > >getValueType(0), Op); > @@ -1063,7 +1105,7 @@ > TLI.isOperationLegalOrCustom(ISD::ADDC, > TLI.getTypeToExpandTo > (NVT))) { > // Emit this X << 1 as X+X. > - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); > + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); > SDValue LoOps[2] = { InL, InL }; > Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); > SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; > @@ -1299,7 +1341,7 @@ > TLI.getTypeToExpandTo(NVT)); > > if (hasCarry) { > - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); > + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); > if (N->getOpcode() == ISD::ADD) { > Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); > HiOps[2] = Lo.getValue(1); > @@ -1344,7 +1386,7 @@ > DebugLoc dl = N->getDebugLoc(); > GetExpandedInteger(N->getOperand(0), LHSL, LHSH); > GetExpandedInteger(N->getOperand(1), RHSL, RHSH); > - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); > + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); > SDValue LoOps[2] = { LHSL, RHSL }; > SDValue HiOps[3] = { LHSH, RHSH }; > > @@ -1358,8 +1400,8 @@ > Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); > } > > - // Legalized the flag result - switch anything that used the old > flag to > - // use the new one. > + // Legalized the second result (carry bit) - switch anything that > used the > + // result to use the new one. > ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); > } > > @@ -1370,7 +1412,7 @@ > DebugLoc dl = N->getDebugLoc(); > GetExpandedInteger(N->getOperand(0), LHSL, LHSH); > GetExpandedInteger(N->getOperand(1), RHSL, RHSH); > - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); > + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); > SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; > SDValue HiOps[3] = { LHSH, RHSH }; > > @@ -1378,8 +1420,8 @@ > HiOps[2] = Lo.getValue(1); > Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); > > - // Legalized the flag result - switch anything that used the old > flag to > - // use the new one. > + // Legalized the second result (carry bit) - switch anything that > used the > + // result to use the new one. > ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); > } > > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Jun 1 > 18:27:20 2009 > @@ -242,6 +242,8 @@ > > // Integer Result Promotion. > void PromoteIntegerResult(SDNode *N, unsigned ResNo); > + SDValue PromoteIntRes_ADDSUBC(SDNode *N, unsigned ResNo); > + SDValue PromoteIntRes_ADDSUBE(SDNode *N, unsigned ResNo); > SDValue PromoteIntRes_AssertSext(SDNode *N); > SDValue PromoteIntRes_AssertZext(SDNode *N); > SDValue PromoteIntRes_Atomic1(AtomicSDNode *N); > @@ -278,6 +280,7 @@ > > // Integer Operand Promotion. > bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo); > + SDValue PromoteIntOp_ADDSUBE(SDNode *N, unsigned OpNo); > SDValue PromoteIntOp_ANY_EXTEND(SDNode *N); > SDValue PromoteIntOp_BIT_CONVERT(SDNode *N); > SDValue PromoteIntOp_BUILD_PAIR(SDNode *N); > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp > (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Mon > Jun 1 18:27:20 2009 > @@ -268,6 +268,13 @@ > unsigned N = Node->getNumOperands(); > while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) > --N; > + // Skip hard registers set as a side effect (i.e. not result 0). > + while (N && Node->getOperand(N - 1).getOpcode() == ISD::CopyToReg > && > + Node->getOperand(N-1).getResNo() != 0 && > + !TargetRegisterInfo::isVirtualRegister( > + dyn_cast(Node->getOperand > (N-1).getOperand(1)) > + ->getReg())) > + --N; > if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) > --N; // Ignore chain if it exists. > return N; > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 1 > 18:27:20 2009 > @@ -5257,7 +5257,6 @@ > case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; > case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; > case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; > - case ISD::CARRY_FALSE: return "carry_false"; > case ISD::ADDC: return "addc"; > case ISD::ADDE: return "adde"; > case ISD::SADDO: return "saddo"; > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jun 1 > 18:27:20 2009 > @@ -190,6 +190,28 @@ > setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); > } > > + // ADDE and SUBE are lowered to local versions that contain > EFLAGS explicitly. > + // ADDC and SUBC are lowered to local versions so EFLAGS will be > an i32 > + // rather than the Flag used by the generic patterns. > + setOperationAction(ISD::ADDC , MVT::i8 , Custom); > + setOperationAction(ISD::ADDC , MVT::i16 , Custom); > + setOperationAction(ISD::ADDC , MVT::i32 , Custom); > + setOperationAction(ISD::SUBC , MVT::i8 , Custom); > + setOperationAction(ISD::SUBC , MVT::i16 , Custom); > + setOperationAction(ISD::SUBC , MVT::i32 , Custom); > + setOperationAction(ISD::ADDE , MVT::i8 , Custom); > + setOperationAction(ISD::ADDE , MVT::i16 , Custom); > + setOperationAction(ISD::ADDE , MVT::i32 , Custom); > + setOperationAction(ISD::SUBE , MVT::i8 , Custom); > + setOperationAction(ISD::SUBE , MVT::i16 , Custom); > + setOperationAction(ISD::SUBE , MVT::i32 , Custom); > + if (Subtarget->is64Bit()) { > + setOperationAction(ISD::ADDC , MVT::i64 , Custom); > + setOperationAction(ISD::SUBC , MVT::i64 , Custom); > + setOperationAction(ISD::ADDE , MVT::i64 , Custom); > + setOperationAction(ISD::SUBE , MVT::i64 , Custom); > + } > + > // Scalar integer divide and remainder are lowered to use > operations that > // produce two results, to match the available instructions. This > exposes > // the two-result form to trivial CSE, which is able to combine x/ > y and x%y > @@ -6475,6 +6497,21 @@ > return Sum; > } > > +SDValue X86TargetLowering::LowerADDSUBE(SDValue Op, SelectionDAG > &DAG) { > + DebugLoc dl = Op.getDebugLoc(); > + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); > + return DAG.getNode(Op.getOpcode()==ISD::ADDE ? X86ISD::ADDE : > X86ISD::SUBE, > + dl, VTs, Op.getOperand(0), Op.getOperand(1), > + Op.getOperand(2).getValue(1)); > +} > + > +SDValue X86TargetLowering::LowerADDSUBC(SDValue Op, SelectionDAG > &DAG) { > + DebugLoc dl = Op.getDebugLoc(); > + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); > + return DAG.getNode(Op.getOpcode()==ISD::ADDC ? X86ISD::ADD : > X86ISD::SUB, > + dl, VTs, Op.getOperand(0), Op.getOperand(1)); > +} > + > SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG > &DAG) { > MVT T = Op.getValueType(); > DebugLoc dl = Op.getDebugLoc(); > @@ -6543,6 +6580,10 @@ > SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG > &DAG) { > switch (Op.getOpcode()) { > default: assert(0 && "Should not custom lower this!"); > + case ISD::ADDC: > + case ISD::SUBC: return LowerADDSUBC(Op,DAG); > + case ISD::ADDE: > + case ISD::SUBE: return LowerADDSUBE(Op,DAG); > case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); > case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); > case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); > @@ -6791,6 +6832,10 @@ > case X86ISD::INC: return "X86ISD::INC"; > case X86ISD::DEC: return "X86ISD::DEC"; > case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; > + case X86ISD::ADDE: return "X86ISD::ADDE"; > + case X86ISD::SUBE: return "X86ISD::SUBE"; > + case X86ISD::ADDC: return "X86ISD::ADDC"; > + case X86ISD::SUBC: return "X86ISD::SUBC"; > } > } > > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Jun 1 18:27:20 > 2009 > @@ -243,6 +243,14 @@ > ADD, SUB, SMUL, UMUL, > INC, DEC, > > + // ADDC, SUBC - Arithmetic operations setting carry bit. The > normal > + // arithmetic operations do this, but they represent it as > Flag, and > + // we want the i32 EFLAGS register here. > + ADDC, SUBC, > + > + // ADDE, SUBE - Arithmetic operations with extra FLAGS > (EFLAGS) inputs. > + ADDE, SUBE, > + > // MUL_IMM - X86 specific multiply by immediate. > MUL_IMM > }; > @@ -576,7 +584,9 @@ > > std::pair FP_TO_INTHelper(SDValue Op, > SelectionDAG &DAG, > bool isSigned); > - > + > + SDValue LowerADDSUBC(SDValue Op, SelectionDAG &DAG); > + SDValue LowerADDSUBE(SDValue Op, SelectionDAG &DAG); > SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); > SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); > SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); > > Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) > +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Mon Jun 1 18:27:20 > 2009 > @@ -383,31 +383,52 @@ > let Uses = [EFLAGS] in { > let isTwoAddress = 1 in { > let isCommutable = 1 in > -def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins > GR64:$src1, GR64:$src2), > +def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), > + (ins GR64:$src1, GR64:$src2), > "adc{q}\t{$src2, $dst|$dst, $src2}", > - [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>; > + [(set GR64:$dst, > + (X86adde_flag GR64:$src1, GR64:$src2, > EFLAGS)), > + (implicit EFLAGS)]>; > > -def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins > GR64:$src1, i64mem:$src2), > +def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), > + (ins GR64:$src1, i64mem:$src2), > "adc{q}\t{$src2, $dst|$dst, $src2}", > - [(set GR64:$dst, (adde GR64:$src1, (load addr: > $src2)))]>; > + [(set GR64:$dst, > + (X86adde_flag GR64:$src1, (load addr: > $src2), EFLAGS)), > + (implicit EFLAGS)]>; > > -def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, > i64i8imm:$src2), > +def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), > + (ins GR64:$src1, i64i8imm:$src2), > "adc{q}\t{$src2, $dst|$dst, $src2}", > - [(set GR64:$dst, (adde GR64:$src1, > i64immSExt8:$src2))]>; > -def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins > GR64:$src1, i64i32imm:$src2), > + [(set GR64:$dst, > + (X86adde_flag GR64:$src1, > i64immSExt8:$src2, EFLAGS)), > + (implicit EFLAGS)]>; > +def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), > + (ins GR64:$src1, i64i32imm:$src2), > "adc{q}\t{$src2, $dst|$dst, $src2}", > - [(set GR64:$dst, (adde GR64:$src1, > i64immSExt32:$src2))]>; > + [(set GR64:$dst, > + (X86adde_flag GR64:$src1, > i64immSExt32:$src2, > + EFLAGS)), > + (implicit EFLAGS)]>; > } // isTwoAddress > > def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, > GR64:$src2), > "adc{q}\t{$src2, $dst|$dst, $src2}", > - [(store (adde (load addr:$dst), GR64:$src2), addr: > $dst)]>; > + [(store (X86adde_flag (load addr:$dst), > GR64:$src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm : > $src2), > "adc{q}\t{$src2, $dst|$dst, $src2}", > - [(store (adde (load addr:$dst), > i64immSExt8:$src2), addr:$dst)]>; > + [(store (X86adde_flag (load addr:$dst), > i64immSExt8:$src2, > + EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, > i64i32imm:$src2), > "adc{q}\t{$src2, $dst|$dst, $src2}", > - [(store (adde (load addr:$dst), > i64immSExt8:$src2), addr:$dst)]>; > + [(store (X86adde_flag (load addr:$dst), > i64immSExt8:$src2, > + EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > } // Uses = [EFLAGS] > > let isTwoAddress = 1 in { > @@ -456,31 +477,52 @@ > > let Uses = [EFLAGS] in { > let isTwoAddress = 1 in { > -def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins > GR64:$src1, GR64:$src2), > +def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), > + (ins GR64:$src1, GR64:$src2), > "sbb{q}\t{$src2, $dst|$dst, $src2}", > - [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))] > >; > + [(set GR64:$dst, > + (X86sube_flag GR64:$src1, GR64:$src2, > EFLAGS)), > + (implicit EFLAGS)]>; > > -def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins > GR64:$src1, i64mem:$src2), > +def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), > + (ins GR64:$src1, i64mem:$src2), > "sbb{q}\t{$src2, $dst|$dst, $src2}", > - [(set GR64:$dst, (sube GR64:$src1, (load addr: > $src2)))]>; > + [(set GR64:$dst, > + (X86sube_flag GR64:$src1, (load addr: > $src2), EFLAGS)), > + (implicit EFLAGS)]>; > > -def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, > i64i8imm:$src2), > +def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), > + (ins GR64:$src1, i64i8imm:$src2), > "sbb{q}\t{$src2, $dst|$dst, $src2}", > - [(set GR64:$dst, (sube GR64:$src1, > i64immSExt8:$src2))]>; > -def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins > GR64:$src1, i64i32imm:$src2), > + [(set GR64:$dst, > + (X86sube_flag GR64:$src1, > i64immSExt8:$src2, EFLAGS)), > + (implicit EFLAGS)]>; > +def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), > + (ins GR64:$src1, i64i32imm:$src2), > "sbb{q}\t{$src2, $dst|$dst, $src2}", > - [(set GR64:$dst, (sube GR64:$src1, > i64immSExt32:$src2))]>; > + [(set GR64:$dst, > + (X86sube_flag GR64:$src1, > i64immSExt32:$src2, > + EFLAGS)), > + (implicit EFLAGS)]>; > } // isTwoAddress > > def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, > GR64:$src2), > "sbb{q}\t{$src2, $dst|$dst, $src2}", > - [(store (sube (load addr:$dst), GR64:$src2), addr: > $dst)]>; > + [(store (X86sube_flag (load addr:$dst), > GR64:$src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm : > $src2), > "sbb{q}\t{$src2, $dst|$dst, $src2}", > - [(store (sube (load addr:$dst), i64immSExt8:$src2), > addr:$dst)]>; > + [(store (X86sube_flag (load addr:$dst), > i64immSExt8:$src2, > + EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, > i64i32imm:$src2), > "sbb{q}\t{$src2, $dst|$dst, $src2}", > - [(store (sube (load addr:$dst), i64immSExt32:$src2), > addr:$dst)]>; > + [(store (X86sube_flag (load addr:$dst), > i64immSExt32:$src2, > + EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > } // Uses = [EFLAGS] > } // Defs = [EFLAGS] > > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Jun 1 18:27:20 2009 > @@ -34,6 +34,11 @@ > [SDTCisSameAs<0, 1>, > SDTCisSameAs<0, 2>, > SDTCisInt<0>]>; > +// Unary and binary operators that both read and write EFLAGS as a > side-effect. > +def SDTBinaryArithRWFlags : SDTypeProfile<1, 3, > + [SDTCisInt<0>, SDTCisSameAs<0, 1>, > + SDTCisSameAs<0, 2>, SDTCisVT<3, > i32>]>; > + > def SDTX86BrCond : SDTypeProfile<0, 3, > [SDTCisVT<0, OtherVT>, > SDTCisVT<1, i8>, SDTCisVT<2, i32>] > >; > @@ -156,6 +161,8 @@ > def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>; > def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; > def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; > +def X86adde_flag : SDNode<"X86ISD::ADDE", SDTBinaryArithRWFlags, > [SDNPInI1]>; > +def X86sube_flag : SDNode<"X86ISD::SUBE", SDTBinaryArithRWFlags, > [SDNPInI1]>; > > def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; > > @@ -2274,81 +2281,127 @@ > > let Uses = [EFLAGS] in { > let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y > -def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, > GR8:$src2), > +def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), > + (ins GR8:$src1, GR8:$src2), > "adc{b}\t{$src2, $dst|$dst, $src2}", > - [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>; > + [(set GR8:$dst, (X86adde_flag GR8:$src1, > GR8:$src2, EFLAGS)), > + (implicit EFLAGS)]>; > def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst), > (ins GR16:$src1, GR16:$src2), > "adc{w}\t{$src2, $dst|$dst, $src2}", > - [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, > OpSize; > + [(set GR16:$dst, > + (X86adde_flag GR16:$src1, GR16:$src2, > EFLAGS)), > + (implicit EFLAGS)]>, > + OpSize; > def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), > (ins GR32:$src1, GR32:$src2), > "adc{l}\t{$src2, $dst|$dst, $src2}", > - [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; > + [(set GR32:$dst, > + (X86adde_flag GR32:$src1, GR32:$src2, > EFLAGS)), > + (implicit EFLAGS)]>; > } > def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst), > (ins GR8:$src1, i8mem:$src2), > "adc{b}\t{$src2, $dst|$dst, $src2}", > - [(set GR8:$dst, (adde GR8:$src1, (load addr: > $src2)))]>; > + [(set GR8:$dst, > + (X86adde_flag GR8:$src1, (load addr:$src2), > EFLAGS)), > + (implicit EFLAGS)]>; > def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst), > (ins GR16:$src1, i16mem:$src2), > "adc{w}\t{$src2, $dst|$dst, $src2}", > - [(set GR16:$dst, (adde GR16:$src1, (load addr: > $src2)))]>, > + [(set GR16:$dst, > + (X86adde_flag GR16:$src1, (load addr:$src2), > EFLAGS)), > + (implicit EFLAGS)]>, > OpSize; > def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), > (ins GR32:$src1, i32mem:$src2), > "adc{l}\t{$src2, $dst|$dst, $src2}", > - [(set GR32:$dst, (adde GR32:$src1, (load addr: > $src2)))]>; > -def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, > i8imm:$src2), > + [(set GR32:$dst, > + (X86adde_flag GR32:$src1, (load addr:$src2), > EFLAGS)), > + (implicit EFLAGS)]>; > +def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), > + (ins GR8:$src1, i8imm:$src2), > "adc{b}\t{$src2, $dst|$dst, $src2}", > - [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>; > + [(set GR8:$dst, > + (X86adde_flag GR8:$src1, imm:$src2, EFLAGS)), > + (implicit EFLAGS)]>; > def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst), > (ins GR16:$src1, i16imm:$src2), > "adc{w}\t{$src2, $dst|$dst, $src2}", > - [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, > OpSize; > + [(set GR16:$dst, > + (X86adde_flag GR16:$src1, imm:$src2, EFLAGS)), > + (implicit EFLAGS)]>, OpSize; > def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst), > (ins GR16:$src1, i16i8imm:$src2), > "adc{w}\t{$src2, $dst|$dst, $src2}", > - [(set GR16:$dst, (adde GR16:$src1, > i16immSExt8:$src2))]>, > - OpSize; > + [(set GR16:$dst, > + (X86adde_flag GR16:$src1, i16immSExt8:$src2, > EFLAGS)), > + (implicit EFLAGS)]>, OpSize; > def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), > (ins GR32:$src1, i32imm:$src2), > "adc{l}\t{$src2, $dst|$dst, $src2}", > - [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; > + [(set GR32:$dst, > + (X86adde_flag GR32:$src1, imm:$src2, EFLAGS)), > + (implicit EFLAGS)]>; > def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), > (ins GR32:$src1, i32i8imm:$src2), > "adc{l}\t{$src2, $dst|$dst, $src2}", > - [(set GR32:$dst, (adde GR32:$src1, > i32immSExt8:$src2))]>; > + [(set GR32:$dst, > + (X86adde_flag GR32:$src1, i32immSExt8:$src2, > EFLAGS)), > + (implicit EFLAGS)]>; > > let isTwoAddress = 0 in { > - def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, > GR8:$src2), > + def ADC8mr : I<0x10, MRMDestMem, (outs), > + (ins i8mem:$dst, GR8:$src2), > "adc{b}\t{$src2, $dst|$dst, $src2}", > - [(store (adde (load addr:$dst), GR8:$src2), addr: > $dst)]>; > - def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, > GR16:$src2), > + [(store (X86adde_flag (load addr:$dst), > GR8:$src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > + def ADC16mr : I<0x11, MRMDestMem, (outs), > + (ins i16mem:$dst, GR16:$src2), > "adc{w}\t{$src2, $dst|$dst, $src2}", > - [(store (adde (load addr:$dst), GR16:$src2), > addr:$dst)]>, > - OpSize; > - def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, > GR32:$src2), > + [(store (X86adde_flag (load addr:$dst), > GR16:$src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>, OpSize; > + def ADC32mr : I<0x11, MRMDestMem, (outs), > + (ins i32mem:$dst, GR32:$src2), > "adc{l}\t{$src2, $dst|$dst, $src2}", > - [(store (adde (load addr:$dst), GR32:$src2), > addr:$dst)]>; > - def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm: > $src2), > + [(store (X86adde_flag (load addr:$dst), > GR32:$src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > + def ADC8mi : Ii8<0x80, MRM2m, (outs), > + (ins i8mem:$dst, i8imm:$src2), > "adc{b}\t{$src2, $dst|$dst, $src2}", > - [(store (adde (loadi8 addr:$dst), imm:$src2), > addr:$dst)]>; > - def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm: > $src2), > + [(store (X86adde_flag (loadi8 addr:$dst), imm: > $src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > + def ADC16mi : Ii16<0x81, MRM2m, (outs), > + (ins i16mem:$dst, i16imm:$src2), > "adc{w}\t{$src2, $dst|$dst, $src2}", > - [(store (adde (loadi16 addr:$dst), imm:$src2), > addr:$dst)]>, > - OpSize; > - def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, > i16i8imm :$src2), > + [(store (X86adde_flag (loadi16 addr:$dst), imm: > $src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>, OpSize; > + def ADC16mi8 : Ii8<0x83, MRM2m, (outs), > + (ins i16mem:$dst, i16i8imm :$src2), > "adc{w}\t{$src2, $dst|$dst, $src2}", > - [(store (adde (load addr:$dst), i16immSExt8:$src2), > addr:$dst)]>, > - OpSize; > - def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm: > $src2), > + [(store (X86adde_flag (load addr:$dst), > i16immSExt8:$src2, > + EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>, OpSize; > + def ADC32mi : Ii32<0x81, MRM2m, (outs), > + (ins i32mem:$dst, i32imm:$src2), > "adc{l}\t{$src2, $dst|$dst, $src2}", > - [(store (adde (loadi32 addr:$dst), imm:$src2), > addr:$dst)]>; > - def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, > i32i8imm :$src2), > + [(store (X86adde_flag (loadi32 addr:$dst), imm: > $src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > + def ADC32mi8 : Ii8<0x83, MRM2m, (outs), > + (ins i32mem:$dst, i32i8imm:$src2), > "adc{l}\t{$src2, $dst|$dst, $src2}", > - [(store (adde (load addr:$dst), i32immSExt8:$src2), > addr:$dst)]>; > -} > + [(store (X86adde_flag (load addr:$dst), > i32immSExt8:$src2, > + EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > + } > } // Uses = [EFLAGS] > > // Register-Register Subtraction > @@ -2453,77 +2506,115 @@ > def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst), > (ins GR8:$src1, GR8:$src2), > "sbb{b}\t{$src2, $dst|$dst, $src2}", > - [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>; > + [(set GR8:$dst, (X86sube_flag GR8:$src1, > GR8:$src2, EFLAGS)), > + (implicit EFLAGS)]>; > def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst), > (ins GR16:$src1, GR16:$src2), > "sbb{w}\t{$src2, $dst|$dst, $src2}", > - [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, > OpSize; > + [(set GR16:$dst, > + (X86sube_flag GR16:$src1, GR16:$src2, > EFLAGS)), > + (implicit EFLAGS)]>, OpSize; > def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), > (ins GR32:$src1, GR32:$src2), > "sbb{l}\t{$src2, $dst|$dst, $src2}", > - [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; > + [(set GR32:$dst, > + (X86sube_flag GR32:$src1, GR32:$src2, > EFLAGS)), > + (implicit EFLAGS)]>; > > let isTwoAddress = 0 in { > def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, > GR8:$src2), > "sbb{b}\t{$src2, $dst|$dst, $src2}", > - [(store (sube (load addr:$dst), GR8:$src2), addr: > $dst)]>; > + [(store (X86sube_flag (load addr:$dst), > GR8:$src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, > GR16:$src2), > "sbb{w}\t{$src2, $dst|$dst, $src2}", > - [(store (sube (load addr:$dst), GR16:$src2), > addr:$dst)]>, > + [(store (X86sube_flag (load addr:$dst), > GR16:$src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>, > OpSize; > def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, > GR32:$src2), > "sbb{l}\t{$src2, $dst|$dst, $src2}", > - [(store (sube (load addr:$dst), GR32:$src2), > addr:$dst)]>; > + [(store (X86sube_flag (load addr:$dst), > GR32:$src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm: > $src2), > "sbb{b}\t{$src2, $dst|$dst, $src2}", > - [(store (sube (loadi8 addr:$dst), imm:$src2), > addr:$dst)]>; > + [(store (X86sube_flag (loadi8 addr:$dst), imm: > $src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm: > $src2), > "sbb{w}\t{$src2, $dst|$dst, $src2}", > - [(store (sube (loadi16 addr:$dst), imm:$src2), > addr:$dst)]>, > + [(store (X86sube_flag (loadi16 addr:$dst), imm: > $src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>, > OpSize; > def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, > i16i8imm :$src2), > "sbb{w}\t{$src2, $dst|$dst, $src2}", > - [(store (sube (load addr:$dst), i16immSExt8:$src2), > addr:$dst)]>, > + [(store (X86sube_flag (load addr:$dst), > i16immSExt8:$src2, > + EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>, > OpSize; > def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm: > $src2), > "sbb{l}\t{$src2, $dst|$dst, $src2}", > - [(store (sube (loadi32 addr:$dst), imm:$src2), > addr:$dst)]>; > + [(store (X86sube_flag (loadi32 addr:$dst), imm: > $src2, EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, > i32i8imm :$src2), > "sbb{l}\t{$src2, $dst|$dst, $src2}", > - [(store (sube (load addr:$dst), i32immSExt8:$src2), > addr:$dst)]>; > + [(store (X86sube_flag (load addr:$dst), > i32immSExt8:$src2, > + EFLAGS), > + addr:$dst), > + (implicit EFLAGS)]>; > } > def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, > i8mem:$src2), > "sbb{b}\t{$src2, $dst|$dst, $src2}", > - [(set GR8:$dst, (sube GR8:$src1, (load addr: > $src2)))]>; > + [(set GR8:$dst, > + (X86sube_flag GR8:$src1, (load addr: > $src2), EFLAGS)), > + (implicit EFLAGS)]>; > def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst), > (ins GR16:$src1, i16mem:$src2), > "sbb{w}\t{$src2, $dst|$dst, $src2}", > - [(set GR16:$dst, (sube GR16:$src1, (load addr: > $src2)))]>, > + [(set GR16:$dst, > + (X86sube_flag GR16:$src1, (load addr: > $src2), EFLAGS)), > + (implicit EFLAGS)]>, > OpSize; > def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), > (ins GR32:$src1, i32mem:$src2), > "sbb{l}\t{$src2, $dst|$dst, $src2}", > - [(set GR32:$dst, (sube GR32:$src1, (load addr: > $src2)))]>; > + [(set GR32:$dst, > + (X86sube_flag GR32:$src1, (load addr: > $src2), EFLAGS)), > + (implicit EFLAGS)]>; > def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, > i8imm:$src2), > "sbb{b}\t{$src2, $dst|$dst, $src2}", > - [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>; > + [(set GR8:$dst, > + (X86sube_flag GR8:$src1, imm:$src2, > EFLAGS)), > + (implicit EFLAGS)]>; > def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst), > (ins GR16:$src1, i16imm:$src2), > "sbb{w}\t{$src2, $dst|$dst, $src2}", > - [(set GR16:$dst, (sube GR16:$src1, imm:$src2))] > >, OpSize; > + [(set GR16:$dst, > + (X86sube_flag GR16:$src1, imm:$src2, > EFLAGS)), > + (implicit EFLAGS)]>, OpSize; > def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst), > (ins GR16:$src1, i16i8imm:$src2), > "sbb{w}\t{$src2, $dst|$dst, $src2}", > - [(set GR16:$dst, (sube GR16:$src1, > i16immSExt8:$src2))]>, > - OpSize; > + [(set GR16:$dst, > + (X86sube_flag GR16:$src1, > i16immSExt8:$src2, EFLAGS)), > + (implicit EFLAGS)]>, OpSize; > def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), > (ins GR32:$src1, i32imm:$src2), > "sbb{l}\t{$src2, $dst|$dst, $src2}", > - [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>; > + [(set GR32:$dst, > + (X86sube_flag GR32:$src1, imm:$src2, > EFLAGS)), > + (implicit EFLAGS)]>; > def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), > (ins GR32:$src1, i32i8imm:$src2), > "sbb{l}\t{$src2, $dst|$dst, $src2}", > - [(set GR32:$dst, (sube GR32:$src1, > i32immSExt8:$src2))]>; > + [(set GR32:$dst, > + (X86sube_flag GR32:$src1, > i32immSExt8:$src2, EFLAGS)), > + (implicit EFLAGS)]>; > } // Uses = [EFLAGS] > } // Defs = [EFLAGS] > > > Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) > +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Mon Jun 1 > 18:27:20 2009 > @@ -399,9 +399,13 @@ > } else if (PropList[i]->getName() == "SDNPHasChain") { > Properties |= 1 << SDNPHasChain; > } else if (PropList[i]->getName() == "SDNPOutFlag") { > - Properties |= 1 << SDNPOutFlag; > + Properties |= 1 << SDNPOutFlag; > + assert(!(Properties & (1< + "Can't handle OutFlag and OutI1"); > } else if (PropList[i]->getName() == "SDNPInFlag") { > Properties |= 1 << SDNPInFlag; > + assert(!(Properties & (1< + "Can't handle InFlag and InI1"); > } else if (PropList[i]->getName() == "SDNPOptInFlag") { > Properties |= 1 << SDNPOptInFlag; > } else if (PropList[i]->getName() == "SDNPMayStore") { > @@ -412,6 +416,14 @@ > Properties |= 1 << SDNPSideEffect; > } else if (PropList[i]->getName() == "SDNPMemOperand") { > Properties |= 1 << SDNPMemOperand; > + } else if (PropList[i]->getName() == "SDNPInI1") { > + Properties |= 1 << SDNPInI1; > + assert(!(Properties & (1< + "Can't handle InFlag and InI1"); > + } else if (PropList[i]->getName() == "SDNPOutI1") { > + Properties |= 1 << SDNPOutI1; > + assert(!(Properties & (1< + "Can't handle OutFlag and OutI1"); > } else { > cerr << "Unknown SD Node property '" << PropList[i]->getName() > << "' on node '" << R->getName() << "'!\n"; > > Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) > +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Jun 1 18:27:20 > 2009 > @@ -385,6 +385,13 @@ > return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); > } > > +/// supportsHasI1 - Return whether this target supports the > implicit I1, > +/// rather than Flags, for ADDC/ADDE > +/// > +bool CodeGenTarget::supportsHasI1() const { > + return getInstructionSet()->getValueAsBit("supportsHasI1"); > +} > + > // > = > = > = > ----------------------------------------------------------------------= > ==// > // ComplexPattern implementation > // > > Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/CodeGenTarget.h (original) > +++ llvm/trunk/utils/TableGen/CodeGenTarget.h Mon Jun 1 18:27:20 2009 > @@ -43,7 +43,9 @@ > SDNPMayLoad, > SDNPMayStore, > SDNPSideEffect, > - SDNPMemOperand > + SDNPMemOperand, > + SDNPInI1, > + SDNPOutI1 > }; > > // ComplexPattern attributes. > @@ -209,10 +211,12 @@ > void getInstructionsByEnumValue(std::vector CodeGenInstruction*> > > &NumberedInstructions); > > - > /// isLittleEndianEncoding - are instruction bit patterns defined > as [0..n]? > /// > bool isLittleEndianEncoding() const; > + > + /// supportsHasI1 - does this target understand HasI1 for ADDE > and ADDC? > + bool supportsHasI1() const; > }; > > /// ComplexPattern - ComplexPattern info, corresponding to the > ComplexPattern > > Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=72707&r1=72706&r2=72707&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Jun 1 18:27:20 > 2009 > @@ -670,7 +670,8 @@ > HasChain = true; > FoldedChains.push_back(std::make_pair(RootName, > CInfo.getNumResults())); > } > - if (NodeHasProperty(Child, SDNPOutFlag, CGP)) { > + if (NodeHasProperty(Child, SDNPOutFlag, CGP) || > + NodeHasProperty(Child, SDNPOutI1, CGP)) { > assert(FoldedFlag.first == "" && FoldedFlag.second == 0 && > "Pattern folded multiple nodes which produce flags?"); > FoldedFlag = std::make_pair(RootName, > @@ -969,6 +970,10 @@ > PatternHasProperty(Pattern, SDNPInFlag, CGP); > bool NodeHasOutFlag = isRoot && > PatternHasProperty(Pattern, SDNPOutFlag, CGP); > + bool NodeHasInI1 = isRoot && > + PatternHasProperty(Pattern, SDNPInI1, CGP); > + bool NodeHasOutI1 = isRoot && > + PatternHasProperty(Pattern, SDNPOutI1, CGP); > bool NodeHasChain = InstPatNode && > PatternHasProperty(InstPatNode, SDNPHasChain, CGP); > bool InputHasChain = isRoot && > @@ -1054,10 +1059,13 @@ > > // Emit all the chain and CopyToReg stuff. > bool ChainEmitted = NodeHasChain; > - if (NodeHasInFlag || HasImpInputs) > + // InFlag and InI1 cannot both be set (checked in > + // CodeGenDAGPatterns), so use the same variables for both. > + if (NodeHasInFlag || HasImpInputs || NodeHasInI1) > EmitInFlagSelectCode(Pattern, "N", ChainEmitted, > InFlagDecled, ResNodeDecled, true); > - if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs) { > + if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs || > + NodeHasInI1) { > if (!InFlagDecled) { > emitCode("SDValue InFlag(0, 0);"); > InFlagDecled = true; > @@ -1113,7 +1121,7 @@ > } > if (NodeHasChain) > Code += ", MVT::Other"; > - if (NodeHasOutFlag) > + if (NodeHasOutFlag || (NodeHasOutI1 && !CGT.supportsHasI1())) > Code += ", MVT::Flag"; > > // Inputs. > @@ -1173,7 +1181,8 @@ > } > Code += ", &Ops" + utostr(OpsNo) + "[0], Ops" + utostr > (OpsNo) + > ".size()"; > - } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs) > + } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs || > + NodeHasInI1) > AllOps.push_back("InFlag"); > > unsigned NumOps = AllOps.size(); > @@ -1207,7 +1216,7 @@ > NodeOps.push_back("Tmp" + utostr(ResNo)); > } else { > > - if (NodeHasOutFlag) { > + if (NodeHasOutFlag || NodeHasOutI1) { > if (!InFlagDecled) { > After.push_back("SDValue InFlag(ResNode, " + > utostr(NumResults+NumDstRegs+(unsigned) > NodeHasChain) + > @@ -1228,13 +1237,15 @@ > utostr(NumResults+NumDstRegs) + ")"); > } > > - if (NodeHasOutFlag) { > + if (NodeHasOutFlag || NodeHasOutI1) { > if (FoldedFlag.first != "") { > - ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + > ".getNode(), " + > + ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + > + ".getNode(), " + > utostr(FoldedFlag.second) + ")"); > ReplaceTos.push_back("InFlag"); > } else { > - assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP)); > + assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP) || > + NodeHasProperty(Pattern, SDNPOutI1, CGP)); > ReplaceFroms.push_back("SDValue(N.getNode(), " + > utostr(NumPatResults + (unsigned) > InputHasChain) > + ")"); > @@ -1251,7 +1262,8 @@ > } > > // User does not expect the instruction would produce a chain! > - if ((!InputHasChain && NodeHasChain) && NodeHasOutFlag) { > + if ((!InputHasChain && NodeHasChain) && > + (NodeHasOutFlag || NodeHasOutI1)) { > ; > } else if (InputHasChain && !NodeHasChain) { > // One of the inner node produces a chain. > @@ -1391,6 +1403,8 @@ > unsigned OpNo = > (unsigned) NodeHasProperty(N, SDNPHasChain, CGP); > bool HasInFlag = NodeHasProperty(N, SDNPInFlag, CGP); > + bool HasInI1 = NodeHasProperty(N, SDNPInI1, CGP); > + bool InFlagDefined = false; > for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, + > +OpNo) { > TreePatternNode *Child = N->getChild(i); > if (!Child->isLeaf()) { > @@ -1424,21 +1438,41 @@ > emitCode("SDValue InFlag(0, 0);"); > InFlagDecled = true; > } > - std::string Decl = (!ResNodeDecled) ? "SDNode *" : ""; > - emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + > ChainName + > + if (HasInI1) { > + if (!ResNodeDecled) { > + emitCode("SDNode * ResNode;"); > + } > + if (T.supportsHasI1()) > + emitCode("ResNode = CurDAG->getCopyToReg(" + > ChainName + > + ", " + RootName + ".getDebugLoc()" + > + ", " + getEnumName(RVT) + > + ", " + getQualifiedName(RR) + > + ", " + RootName + utostr(OpNo) + > ").getNode();"); > + else > + emitCode("ResNode = CurDAG->getCopyToReg(" + > ChainName + > + ", " + RootName + ".getDebugLoc()" + > + ", " + getQualifiedName(RR) + > + ", " + RootName + utostr(OpNo) + > + ", InFlag).getNode();"); > + InFlagDefined = true; > + } else { > + std::string Decl = (!ResNodeDecled) ? "SDNode *" : > ""; > + emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + > ChainName + > ", " + RootName + ".getDebugLoc()" + > ", " + getQualifiedName(RR) + > - ", " + RootName + utostr(OpNo) + ", > InFlag).getNode();"); > - ResNodeDecled = true; > + ", " + RootName + utostr(OpNo) + > + ", InFlag).getNode();"); > + } > emitCode(ChainName + " = SDValue(ResNode, 0);"); > emitCode("InFlag = SDValue(ResNode, 1);"); > + ResNodeDecled = true; > } > } > } > } > } > > - if (HasInFlag) { > + if (HasInFlag || (HasInI1 && !InFlagDefined)) { > if (!InFlagDecled) { > emitCode("SDValue InFlag = " + RootName + > ".getOperand(" + utostr(OpNo) + ");"); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From nicolas.geoffray at lip6.fr Tue Jun 2 13:18:23 2009 From: nicolas.geoffray at lip6.fr (Nicolas Geoffray) Date: Tue, 02 Jun 2009 20:18:23 +0200 Subject: [llvm-commits] [llvm] r72707 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/X86/ utils/TableGen/ In-Reply-To: <668F172C-93E7-47E8-9B1F-333154602253@apple.com> References: <200906012327.n51NRMqY006632@zion.cs.uiuc.edu> <668F172C-93E7-47E8-9B1F-333154602253@apple.com> Message-ID: <4A256CEF.6070400@lip6.fr> For what it's worth, I'm having failures in VMKit's testsuite with this patch. I know you guys won't run VMKit's testsuite :), but if you intend to apply the patch, could you run llvm testsuite with it before applying it? Thanks! Nicolas Evan Cheng wrote: > Hi Dale, > > On first glance, the patch mostly looks good. But I don't care for > "supportsHasI1". I would have added ADDC_FLAG / ADDE_FLAG opcodes and > have those use MVT::EFLAGS and change ADDC / ADDE to use MVT::i1 to > represent the flag value. > > Thanks, > > Evan > > On Jun 1, 2009, at 4:27 PM, Dale Johannesen wrote: > > >> Author: johannes >> Date: Mon Jun 1 18:27:20 2009 >> New Revision: 72707 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=72707&view=rev >> Log: >> Make the implicit inputs and outputs of target-independent >> ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) >> instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust >> all target-independent code to use this format. >> >> Most targets will still produce a Flag-setting target-dependent >> version when selection is done. X86 is converted to use i32 >> instead, which means TableGen needs to produce different code >> in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit >> in xxxInstrInfo, currently set only for X86; in principle this >> is temporary and should go away when all other targets have >> been converted. All relevant X86 instruction patterns are >> modified to represent setting and using EFLAGS explicitly. The >> same can be done on other targets. >> >> The immediate behavior change is that an ADC/ADD pair are no >> longer tightly coupled in the X86 scheduler; they can be >> separated by instructions that don't clobber the flags (MOV). >> I will soon add some peephole optimizations based on using >> other instructions that set the flags to feed into ADC. >> >> >> Modified: >> llvm/trunk/include/llvm/CodeGen/SelectionDAG.h >> llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h >> llvm/trunk/include/llvm/Target/Target.td >> llvm/trunk/include/llvm/Target/TargetSelectionDAG.td >> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp >> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp >> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h >> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp >> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >> llvm/trunk/lib/Target/X86/X86ISelLowering.h >> llvm/trunk/lib/Target/X86/X86Instr64bit.td >> llvm/trunk/lib/Target/X86/X86InstrInfo.td >> llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >> llvm/trunk/utils/TableGen/CodeGenTarget.cpp >> llvm/trunk/utils/TableGen/CodeGenTarget.h >> llvm/trunk/utils/TableGen/DAGISelEmitter.cpp >> >> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) >> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Jun 1 >> 18:27:20 2009 >> @@ -324,6 +324,14 @@ >> return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, >> getRegister(Reg, N.getValueType()), N); >> } >> + // This version of getCopyToReg has the register (and its type) >> as an >> + // explicit output. >> + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, MVT VT, unsigned >> Reg, >> + SDValue N) { >> + SDVTList VTs = getVTList(MVT::Other, VT); >> + SDValue Ops[] = { Chain, getRegister(Reg, VT), N}; >> + return getNode(ISD::CopyToReg, dl, VTs, Ops, 3); >> + } >> >> // This version of the getCopyToReg method takes an extra operand, >> which >> // indicates that there is potentially an incoming flag value (if >> Flag is not >> >> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) >> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Jun 1 >> 18:27:20 2009 >> @@ -242,14 +242,11 @@ >> // remainder result. >> SDIVREM, UDIVREM, >> >> - // CARRY_FALSE - This node is used when folding other nodes, >> - // like ADDC/SUBC, which indicate the carry result is always >> false. >> - CARRY_FALSE, >> - >> // Carry-setting nodes for multiple precision addition and >> subtraction. >> // These nodes take two operands of the same value type, and >> produce two >> // results. The first result is the normal add or sub result, >> the second >> - // result is the carry flag result. >> + // result is the carry flag result (type i1 or whatever it got >> expanded to >> + // for the target, value 0 or 1). >> ADDC, SUBC, >> >> // Carry-using nodes for multiple precision addition and >> subtraction. These >> @@ -258,7 +255,8 @@ >> // produce two results; the normal result of the add or sub, and >> the output >> // carry flag. These nodes both read and write a carry flag to >> allow them >> // to them to be chained together for add and sub of arbitrarily >> large >> - // values. >> + // values. The carry flag (input and output) has type i1 or >> whatever it >> + // got expanded to for the target, and has value 0 or 1. >> ADDE, SUBE, >> >> // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for >> addition. >> >> Modified: llvm/trunk/include/llvm/Target/Target.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/include/llvm/Target/Target.td (original) >> +++ llvm/trunk/include/llvm/Target/Target.td Mon Jun 1 18:27:20 2009 >> @@ -326,6 +326,11 @@ >> // Sparc manual specifies its instructions in the format [31..0] >> (big), while >> // PowerPC specifies them using the format [0..31] (little). >> bit isLittleEndianEncoding = 0; >> + >> + // Targets that can support the HasI1 argument on ADDC and ADDE, >> rather than >> + // Flag, have this bit set. This is transitional and should go >> away when all >> + // targets have been switched over. >> + bit supportsHasI1 = 0; >> } >> >> // Standard Instructions. >> >> Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) >> +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Mon Jun 1 >> 18:27:20 2009 >> @@ -216,6 +216,8 @@ >> def SDNPMayLoad : SDNodeProperty; // May read memory, sets >> 'mayLoad'. >> def SDNPSideEffect : SDNodeProperty; // Sets >> 'HasUnmodelledSideEffects'. >> def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc >> MemOperand >> +def SDNPInI1 : SDNodeProperty; // Read an extra I1 operand >> +def SDNPOutI1 : SDNodeProperty; // Write an extra I1 result >> >> // >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> // Selection DAG Node definitions. >> @@ -289,13 +291,13 @@ >> def xor : SDNode<"ISD::XOR" , SDTIntBinOp, >> [SDNPCommutative, SDNPAssociative]>; >> def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, >> - [SDNPCommutative, SDNPOutFlag]>; >> + [SDNPCommutative, SDNPOutI1]>; >> def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, >> - [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; >> + [SDNPCommutative, SDNPInI1, SDNPOutI1]>; >> def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, >> - [SDNPOutFlag]>; >> + [SDNPOutI1]>; >> def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, >> - [SDNPOutFlag, SDNPInFlag]>; >> + [SDNPInI1, SDNPOutI1]>; >> >> def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; >> def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jun 1 >> 18:27:20 2009 >> @@ -1085,8 +1085,7 @@ >> // If the flag result is dead, turn this into an ADD. >> if (N->hasNUsesOfValue(0, 1)) >> return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, >> N1, N0), >> - DAG.getNode(ISD::CARRY_FALSE, >> - N->getDebugLoc(), MVT::Flag)); >> + DAG.getConstant(0, N->getValueType(1))); >> >> // canonicalize constant to RHS. >> if (N0C && !N1C) >> @@ -1094,10 +1093,9 @@ >> >> // fold (addc x, 0) -> x + no carry out >> if (N1C && N1C->isNullValue()) >> - return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, >> - N->getDebugLoc(), >> MVT::Flag)); >> + return CombineTo(N, N0, DAG.getConstant(0, N1.getValueType())); >> >> - // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share >> no bits. >> + // fold (addc a, b) -> (or a, b), 0 iff a and b share no bits. >> APInt LHSZero, LHSOne; >> APInt RHSZero, RHSOne; >> APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); >> @@ -1111,8 +1109,7 @@ >> if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || >> (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) >> return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, >> N0, N1), >> - DAG.getNode(ISD::CARRY_FALSE, >> - N->getDebugLoc(), MVT::Flag)); >> + DAG.getConstant(0, N1.getValueType())); >> } >> >> return SDValue(); >> @@ -1131,8 +1128,9 @@ >> N1, N0, CarryIn); >> >> // fold (adde x, y, false) -> (addc x, y) >> - if (CarryIn.getOpcode() == ISD::CARRY_FALSE) >> - return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), >> N1, N0); >> + if (ConstantSDNode *N2C = dyn_cast(CarryIn)) >> + if (N2C->getAPIntValue()==0) >> + return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList >> (), N1, N0); >> >> return SDValue(); >> } >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp >> (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon >> Jun 1 18:27:20 2009 >> @@ -98,6 +98,10 @@ >> case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); >> break; >> case ISD::SMULO: >> case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; >> + case ISD::ADDC: >> + case ISD::SUBC: Res = PromoteIntRes_ADDSUBC(N, ResNo); >> break; >> + case ISD::ADDE: >> + case ISD::SUBE: Res = PromoteIntRes_ADDSUBE(N, ResNo); >> break; >> >> case ISD::ATOMIC_LOAD_ADD: >> case ISD::ATOMIC_LOAD_SUB: >> @@ -121,6 +125,35 @@ >> SetPromotedInteger(SDValue(N, ResNo), Res); >> } >> >> +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBC(SDNode *N, unsigned >> ResNo) { >> + // Only the carry bit result is expected to be promoted. >> + assert(ResNo == 1 && "Only carry bit result promotion currently >> supported!"); >> + return PromoteIntRes_Overflow(N); >> +} >> + >> +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBE(SDNode *N, unsigned >> ResNo) { >> + // Only the carry bit result is expected to be promoted. >> + assert(ResNo == 1 && "Only carry bit result promotion currently >> supported!"); >> + // This is a ternary operator, so clone a slightly modified >> + // PromoteIntRes_Overflow here (this is the only client). >> + if (ResNo == 1) { >> + // Simply change the return type of the boolean result. >> + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); >> + MVT ValueVTs[] = { N->getValueType(0), NVT }; >> + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N- >> >>> getOperand(2) }; >>> >> + SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), >> + DAG.getVTList(ValueVTs, 2), Ops, 3); >> + >> + // Modified the sum result - switch anything that used the old >> sum to use >> + // the new one. >> + ReplaceValueWith(SDValue(N, 0), Res); >> + >> + return SDValue(Res.getNode(), 1); >> + } >> + assert(0 && "Do not know how to promote this operator!"); >> + abort(); >> +} >> + >> SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { >> // Sign-extend the new bits, and continue the assertion. >> SDValue Op = SExtPromotedInteger(N->getOperand(0)); >> @@ -419,7 +452,7 @@ >> return Res; >> } >> >> -/// Promote the overflow flag of an overflowing arithmetic node. >> +/// Promote the overflow or carry result of an overflowing >> arithmetic node. >> SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { >> // Simply change the return type of the boolean result. >> MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); >> @@ -666,6 +699,8 @@ >> assert(0 && "Do not know how to promote this operator's >> operand!"); >> abort(); >> >> + case ISD::ADDE: >> + case ISD::SUBE: Res = PromoteIntOp_ADDSUBE(N, OpNo); break; >> case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; >> case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; >> case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; >> @@ -743,6 +778,13 @@ >> } >> } >> >> +SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBE(SDNode *N, unsigned >> OpNo) { >> + assert(OpNo == 2 && "Don't know how to promote this operand!"); >> + return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), >> + N->getOperand(1), >> + GetPromotedInteger(N->getOperand >> (2))); >> +} >> + >> SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { >> SDValue Op = GetPromotedInteger(N->getOperand(0)); >> return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N- >> >>> getValueType(0), Op); >>> >> @@ -1063,7 +1105,7 @@ >> TLI.isOperationLegalOrCustom(ISD::ADDC, >> TLI.getTypeToExpandTo >> (NVT))) { >> // Emit this X << 1 as X+X. >> - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); >> + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); >> SDValue LoOps[2] = { InL, InL }; >> Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); >> SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; >> @@ -1299,7 +1341,7 @@ >> TLI.getTypeToExpandTo(NVT)); >> >> if (hasCarry) { >> - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); >> + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); >> if (N->getOpcode() == ISD::ADD) { >> Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); >> HiOps[2] = Lo.getValue(1); >> @@ -1344,7 +1386,7 @@ >> DebugLoc dl = N->getDebugLoc(); >> GetExpandedInteger(N->getOperand(0), LHSL, LHSH); >> GetExpandedInteger(N->getOperand(1), RHSL, RHSH); >> - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); >> + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); >> SDValue LoOps[2] = { LHSL, RHSL }; >> SDValue HiOps[3] = { LHSH, RHSH }; >> >> @@ -1358,8 +1400,8 @@ >> Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); >> } >> >> - // Legalized the flag result - switch anything that used the old >> flag to >> - // use the new one. >> + // Legalized the second result (carry bit) - switch anything that >> used the >> + // result to use the new one. >> ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); >> } >> >> @@ -1370,7 +1412,7 @@ >> DebugLoc dl = N->getDebugLoc(); >> GetExpandedInteger(N->getOperand(0), LHSL, LHSH); >> GetExpandedInteger(N->getOperand(1), RHSL, RHSH); >> - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); >> + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); >> SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; >> SDValue HiOps[3] = { LHSH, RHSH }; >> >> @@ -1378,8 +1420,8 @@ >> HiOps[2] = Lo.getValue(1); >> Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); >> >> - // Legalized the flag result - switch anything that used the old >> flag to >> - // use the new one. >> + // Legalized the second result (carry bit) - switch anything that >> used the >> + // result to use the new one. >> ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); >> } >> >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Jun 1 >> 18:27:20 2009 >> @@ -242,6 +242,8 @@ >> >> // Integer Result Promotion. >> void PromoteIntegerResult(SDNode *N, unsigned ResNo); >> + SDValue PromoteIntRes_ADDSUBC(SDNode *N, unsigned ResNo); >> + SDValue PromoteIntRes_ADDSUBE(SDNode *N, unsigned ResNo); >> SDValue PromoteIntRes_AssertSext(SDNode *N); >> SDValue PromoteIntRes_AssertZext(SDNode *N); >> SDValue PromoteIntRes_Atomic1(AtomicSDNode *N); >> @@ -278,6 +280,7 @@ >> >> // Integer Operand Promotion. >> bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo); >> + SDValue PromoteIntOp_ADDSUBE(SDNode *N, unsigned OpNo); >> SDValue PromoteIntOp_ANY_EXTEND(SDNode *N); >> SDValue PromoteIntOp_BIT_CONVERT(SDNode *N); >> SDValue PromoteIntOp_BUILD_PAIR(SDNode *N); >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >> (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Mon >> Jun 1 18:27:20 2009 >> @@ -268,6 +268,13 @@ >> unsigned N = Node->getNumOperands(); >> while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) >> --N; >> + // Skip hard registers set as a side effect (i.e. not result 0). >> + while (N && Node->getOperand(N - 1).getOpcode() == ISD::CopyToReg >> && >> + Node->getOperand(N-1).getResNo() != 0 && >> + !TargetRegisterInfo::isVirtualRegister( >> + dyn_cast(Node->getOperand >> (N-1).getOperand(1)) >> + ->getReg())) >> + --N; >> if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) >> --N; // Ignore chain if it exists. >> return N; >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 1 >> 18:27:20 2009 >> @@ -5257,7 +5257,6 @@ >> case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; >> case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; >> case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; >> - case ISD::CARRY_FALSE: return "carry_false"; >> case ISD::ADDC: return "addc"; >> case ISD::ADDE: return "adde"; >> case ISD::SADDO: return "saddo"; >> >> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) >> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jun 1 >> 18:27:20 2009 >> @@ -190,6 +190,28 @@ >> setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); >> } >> >> + // ADDE and SUBE are lowered to local versions that contain >> EFLAGS explicitly. >> + // ADDC and SUBC are lowered to local versions so EFLAGS will be >> an i32 >> + // rather than the Flag used by the generic patterns. >> + setOperationAction(ISD::ADDC , MVT::i8 , Custom); >> + setOperationAction(ISD::ADDC , MVT::i16 , Custom); >> + setOperationAction(ISD::ADDC , MVT::i32 , Custom); >> + setOperationAction(ISD::SUBC , MVT::i8 , Custom); >> + setOperationAction(ISD::SUBC , MVT::i16 , Custom); >> + setOperationAction(ISD::SUBC , MVT::i32 , Custom); >> + setOperationAction(ISD::ADDE , MVT::i8 , Custom); >> + setOperationAction(ISD::ADDE , MVT::i16 , Custom); >> + setOperationAction(ISD::ADDE , MVT::i32 , Custom); >> + setOperationAction(ISD::SUBE , MVT::i8 , Custom); >> + setOperationAction(ISD::SUBE , MVT::i16 , Custom); >> + setOperationAction(ISD::SUBE , MVT::i32 , Custom); >> + if (Subtarget->is64Bit()) { >> + setOperationAction(ISD::ADDC , MVT::i64 , Custom); >> + setOperationAction(ISD::SUBC , MVT::i64 , Custom); >> + setOperationAction(ISD::ADDE , MVT::i64 , Custom); >> + setOperationAction(ISD::SUBE , MVT::i64 , Custom); >> + } >> + >> // Scalar integer divide and remainder are lowered to use >> operations that >> // produce two results, to match the available instructions. This >> exposes >> // the two-result form to trivial CSE, which is able to combine x/ >> y and x%y >> @@ -6475,6 +6497,21 @@ >> return Sum; >> } >> >> +SDValue X86TargetLowering::LowerADDSUBE(SDValue Op, SelectionDAG >> &DAG) { >> + DebugLoc dl = Op.getDebugLoc(); >> + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); >> + return DAG.getNode(Op.getOpcode()==ISD::ADDE ? X86ISD::ADDE : >> X86ISD::SUBE, >> + dl, VTs, Op.getOperand(0), Op.getOperand(1), >> + Op.getOperand(2).getValue(1)); >> +} >> + >> +SDValue X86TargetLowering::LowerADDSUBC(SDValue Op, SelectionDAG >> &DAG) { >> + DebugLoc dl = Op.getDebugLoc(); >> + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); >> + return DAG.getNode(Op.getOpcode()==ISD::ADDC ? X86ISD::ADD : >> X86ISD::SUB, >> + dl, VTs, Op.getOperand(0), Op.getOperand(1)); >> +} >> + >> SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG >> &DAG) { >> MVT T = Op.getValueType(); >> DebugLoc dl = Op.getDebugLoc(); >> @@ -6543,6 +6580,10 @@ >> SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG >> &DAG) { >> switch (Op.getOpcode()) { >> default: assert(0 && "Should not custom lower this!"); >> + case ISD::ADDC: >> + case ISD::SUBC: return LowerADDSUBC(Op,DAG); >> + case ISD::ADDE: >> + case ISD::SUBE: return LowerADDSUBE(Op,DAG); >> case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); >> case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); >> case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); >> @@ -6791,6 +6832,10 @@ >> case X86ISD::INC: return "X86ISD::INC"; >> case X86ISD::DEC: return "X86ISD::DEC"; >> case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; >> + case X86ISD::ADDE: return "X86ISD::ADDE"; >> + case X86ISD::SUBE: return "X86ISD::SUBE"; >> + case X86ISD::ADDC: return "X86ISD::ADDC"; >> + case X86ISD::SUBC: return "X86ISD::SUBC"; >> } >> } >> >> >> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) >> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Jun 1 18:27:20 >> 2009 >> @@ -243,6 +243,14 @@ >> ADD, SUB, SMUL, UMUL, >> INC, DEC, >> >> + // ADDC, SUBC - Arithmetic operations setting carry bit. The >> normal >> + // arithmetic operations do this, but they represent it as >> Flag, and >> + // we want the i32 EFLAGS register here. >> + ADDC, SUBC, >> + >> + // ADDE, SUBE - Arithmetic operations with extra FLAGS >> (EFLAGS) inputs. >> + ADDE, SUBE, >> + >> // MUL_IMM - X86 specific multiply by immediate. >> MUL_IMM >> }; >> @@ -576,7 +584,9 @@ >> >> std::pair FP_TO_INTHelper(SDValue Op, >> SelectionDAG &DAG, >> bool isSigned); >> - >> + >> + SDValue LowerADDSUBC(SDValue Op, SelectionDAG &DAG); >> + SDValue LowerADDSUBE(SDValue Op, SelectionDAG &DAG); >> SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); >> SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); >> SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); >> >> Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) >> +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Mon Jun 1 18:27:20 >> 2009 >> @@ -383,31 +383,52 @@ >> let Uses = [EFLAGS] in { >> let isTwoAddress = 1 in { >> let isCommutable = 1 in >> -def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins >> GR64:$src1, GR64:$src2), >> +def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), >> + (ins GR64:$src1, GR64:$src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>; >> + [(set GR64:$dst, >> + (X86adde_flag GR64:$src1, GR64:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> >> -def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins >> GR64:$src1, i64mem:$src2), >> +def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), >> + (ins GR64:$src1, i64mem:$src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (adde GR64:$src1, (load addr: >> $src2)))]>; >> + [(set GR64:$dst, >> + (X86adde_flag GR64:$src1, (load addr: >> $src2), EFLAGS)), >> + (implicit EFLAGS)]>; >> >> -def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, >> i64i8imm:$src2), >> +def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), >> + (ins GR64:$src1, i64i8imm:$src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (adde GR64:$src1, >> i64immSExt8:$src2))]>; >> -def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins >> GR64:$src1, i64i32imm:$src2), >> + [(set GR64:$dst, >> + (X86adde_flag GR64:$src1, >> i64immSExt8:$src2, EFLAGS)), >> + (implicit EFLAGS)]>; >> +def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), >> + (ins GR64:$src1, i64i32imm:$src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (adde GR64:$src1, >> i64immSExt32:$src2))]>; >> + [(set GR64:$dst, >> + (X86adde_flag GR64:$src1, >> i64immSExt32:$src2, >> + EFLAGS)), >> + (implicit EFLAGS)]>; >> } // isTwoAddress >> >> def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, >> GR64:$src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), GR64:$src2), addr: >> $dst)]>; >> + [(store (X86adde_flag (load addr:$dst), >> GR64:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm : >> $src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), >> i64immSExt8:$src2), addr:$dst)]>; >> + [(store (X86adde_flag (load addr:$dst), >> i64immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, >> i64i32imm:$src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), >> i64immSExt8:$src2), addr:$dst)]>; >> + [(store (X86adde_flag (load addr:$dst), >> i64immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> } // Uses = [EFLAGS] >> >> let isTwoAddress = 1 in { >> @@ -456,31 +477,52 @@ >> >> let Uses = [EFLAGS] in { >> let isTwoAddress = 1 in { >> -def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins >> GR64:$src1, GR64:$src2), >> +def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), >> + (ins GR64:$src1, GR64:$src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))] >> >>> ; >>> >> + [(set GR64:$dst, >> + (X86sube_flag GR64:$src1, GR64:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> >> -def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins >> GR64:$src1, i64mem:$src2), >> +def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), >> + (ins GR64:$src1, i64mem:$src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (sube GR64:$src1, (load addr: >> $src2)))]>; >> + [(set GR64:$dst, >> + (X86sube_flag GR64:$src1, (load addr: >> $src2), EFLAGS)), >> + (implicit EFLAGS)]>; >> >> -def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, >> i64i8imm:$src2), >> +def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), >> + (ins GR64:$src1, i64i8imm:$src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (sube GR64:$src1, >> i64immSExt8:$src2))]>; >> -def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins >> GR64:$src1, i64i32imm:$src2), >> + [(set GR64:$dst, >> + (X86sube_flag GR64:$src1, >> i64immSExt8:$src2, EFLAGS)), >> + (implicit EFLAGS)]>; >> +def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), >> + (ins GR64:$src1, i64i32imm:$src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (sube GR64:$src1, >> i64immSExt32:$src2))]>; >> + [(set GR64:$dst, >> + (X86sube_flag GR64:$src1, >> i64immSExt32:$src2, >> + EFLAGS)), >> + (implicit EFLAGS)]>; >> } // isTwoAddress >> >> def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, >> GR64:$src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), GR64:$src2), addr: >> $dst)]>; >> + [(store (X86sube_flag (load addr:$dst), >> GR64:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm : >> $src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), i64immSExt8:$src2), >> addr:$dst)]>; >> + [(store (X86sube_flag (load addr:$dst), >> i64immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, >> i64i32imm:$src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), i64immSExt32:$src2), >> addr:$dst)]>; >> + [(store (X86sube_flag (load addr:$dst), >> i64immSExt32:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> } // Uses = [EFLAGS] >> } // Defs = [EFLAGS] >> >> >> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) >> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Jun 1 18:27:20 2009 >> @@ -34,6 +34,11 @@ >> [SDTCisSameAs<0, 1>, >> SDTCisSameAs<0, 2>, >> SDTCisInt<0>]>; >> +// Unary and binary operators that both read and write EFLAGS as a >> side-effect. >> +def SDTBinaryArithRWFlags : SDTypeProfile<1, 3, >> + [SDTCisInt<0>, SDTCisSameAs<0, 1>, >> + SDTCisSameAs<0, 2>, SDTCisVT<3, >> i32>]>; >> + >> def SDTX86BrCond : SDTypeProfile<0, 3, >> [SDTCisVT<0, OtherVT>, >> SDTCisVT<1, i8>, SDTCisVT<2, i32>] >> >>> ; >>> >> @@ -156,6 +161,8 @@ >> def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>; >> def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; >> def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; >> +def X86adde_flag : SDNode<"X86ISD::ADDE", SDTBinaryArithRWFlags, >> [SDNPInI1]>; >> +def X86sube_flag : SDNode<"X86ISD::SUBE", SDTBinaryArithRWFlags, >> [SDNPInI1]>; >> >> def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; >> >> @@ -2274,81 +2281,127 @@ >> >> let Uses = [EFLAGS] in { >> let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y >> -def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, >> GR8:$src2), >> +def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), >> + (ins GR8:$src1, GR8:$src2), >> "adc{b}\t{$src2, $dst|$dst, $src2}", >> - [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>; >> + [(set GR8:$dst, (X86adde_flag GR8:$src1, >> GR8:$src2, EFLAGS)), >> + (implicit EFLAGS)]>; >> def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst), >> (ins GR16:$src1, GR16:$src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, >> OpSize; >> + [(set GR16:$dst, >> + (X86adde_flag GR16:$src1, GR16:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>, >> + OpSize; >> def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), >> (ins GR32:$src1, GR32:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; >> + [(set GR32:$dst, >> + (X86adde_flag GR32:$src1, GR32:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> } >> def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst), >> (ins GR8:$src1, i8mem:$src2), >> "adc{b}\t{$src2, $dst|$dst, $src2}", >> - [(set GR8:$dst, (adde GR8:$src1, (load addr: >> $src2)))]>; >> + [(set GR8:$dst, >> + (X86adde_flag GR8:$src1, (load addr:$src2), >> EFLAGS)), >> + (implicit EFLAGS)]>; >> def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst), >> (ins GR16:$src1, i16mem:$src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (adde GR16:$src1, (load addr: >> $src2)))]>, >> + [(set GR16:$dst, >> + (X86adde_flag GR16:$src1, (load addr:$src2), >> EFLAGS)), >> + (implicit EFLAGS)]>, >> OpSize; >> def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), >> (ins GR32:$src1, i32mem:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (adde GR32:$src1, (load addr: >> $src2)))]>; >> -def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, >> i8imm:$src2), >> + [(set GR32:$dst, >> + (X86adde_flag GR32:$src1, (load addr:$src2), >> EFLAGS)), >> + (implicit EFLAGS)]>; >> +def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), >> + (ins GR8:$src1, i8imm:$src2), >> "adc{b}\t{$src2, $dst|$dst, $src2}", >> - [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>; >> + [(set GR8:$dst, >> + (X86adde_flag GR8:$src1, imm:$src2, EFLAGS)), >> + (implicit EFLAGS)]>; >> def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst), >> (ins GR16:$src1, i16imm:$src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, >> OpSize; >> + [(set GR16:$dst, >> + (X86adde_flag GR16:$src1, imm:$src2, EFLAGS)), >> + (implicit EFLAGS)]>, OpSize; >> def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst), >> (ins GR16:$src1, i16i8imm:$src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (adde GR16:$src1, >> i16immSExt8:$src2))]>, >> - OpSize; >> + [(set GR16:$dst, >> + (X86adde_flag GR16:$src1, i16immSExt8:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>, OpSize; >> def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), >> (ins GR32:$src1, i32imm:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; >> + [(set GR32:$dst, >> + (X86adde_flag GR32:$src1, imm:$src2, EFLAGS)), >> + (implicit EFLAGS)]>; >> def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), >> (ins GR32:$src1, i32i8imm:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (adde GR32:$src1, >> i32immSExt8:$src2))]>; >> + [(set GR32:$dst, >> + (X86adde_flag GR32:$src1, i32immSExt8:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> >> let isTwoAddress = 0 in { >> - def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, >> GR8:$src2), >> + def ADC8mr : I<0x10, MRMDestMem, (outs), >> + (ins i8mem:$dst, GR8:$src2), >> "adc{b}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), GR8:$src2), addr: >> $dst)]>; >> - def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, >> GR16:$src2), >> + [(store (X86adde_flag (load addr:$dst), >> GR8:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> + def ADC16mr : I<0x11, MRMDestMem, (outs), >> + (ins i16mem:$dst, GR16:$src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), GR16:$src2), >> addr:$dst)]>, >> - OpSize; >> - def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, >> GR32:$src2), >> + [(store (X86adde_flag (load addr:$dst), >> GR16:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>, OpSize; >> + def ADC32mr : I<0x11, MRMDestMem, (outs), >> + (ins i32mem:$dst, GR32:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), GR32:$src2), >> addr:$dst)]>; >> - def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm: >> $src2), >> + [(store (X86adde_flag (load addr:$dst), >> GR32:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> + def ADC8mi : Ii8<0x80, MRM2m, (outs), >> + (ins i8mem:$dst, i8imm:$src2), >> "adc{b}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (loadi8 addr:$dst), imm:$src2), >> addr:$dst)]>; >> - def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm: >> $src2), >> + [(store (X86adde_flag (loadi8 addr:$dst), imm: >> $src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> + def ADC16mi : Ii16<0x81, MRM2m, (outs), >> + (ins i16mem:$dst, i16imm:$src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (loadi16 addr:$dst), imm:$src2), >> addr:$dst)]>, >> - OpSize; >> - def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, >> i16i8imm :$src2), >> + [(store (X86adde_flag (loadi16 addr:$dst), imm: >> $src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>, OpSize; >> + def ADC16mi8 : Ii8<0x83, MRM2m, (outs), >> + (ins i16mem:$dst, i16i8imm :$src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), i16immSExt8:$src2), >> addr:$dst)]>, >> - OpSize; >> - def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm: >> $src2), >> + [(store (X86adde_flag (load addr:$dst), >> i16immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>, OpSize; >> + def ADC32mi : Ii32<0x81, MRM2m, (outs), >> + (ins i32mem:$dst, i32imm:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (loadi32 addr:$dst), imm:$src2), >> addr:$dst)]>; >> - def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, >> i32i8imm :$src2), >> + [(store (X86adde_flag (loadi32 addr:$dst), imm: >> $src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> + def ADC32mi8 : Ii8<0x83, MRM2m, (outs), >> + (ins i32mem:$dst, i32i8imm:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), i32immSExt8:$src2), >> addr:$dst)]>; >> -} >> + [(store (X86adde_flag (load addr:$dst), >> i32immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> + } >> } // Uses = [EFLAGS] >> >> // Register-Register Subtraction >> @@ -2453,77 +2506,115 @@ >> def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst), >> (ins GR8:$src1, GR8:$src2), >> "sbb{b}\t{$src2, $dst|$dst, $src2}", >> - [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>; >> + [(set GR8:$dst, (X86sube_flag GR8:$src1, >> GR8:$src2, EFLAGS)), >> + (implicit EFLAGS)]>; >> def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst), >> (ins GR16:$src1, GR16:$src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, >> OpSize; >> + [(set GR16:$dst, >> + (X86sube_flag GR16:$src1, GR16:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>, OpSize; >> def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), >> (ins GR32:$src1, GR32:$src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; >> + [(set GR32:$dst, >> + (X86sube_flag GR32:$src1, GR32:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> >> let isTwoAddress = 0 in { >> def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, >> GR8:$src2), >> "sbb{b}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), GR8:$src2), addr: >> $dst)]>; >> + [(store (X86sube_flag (load addr:$dst), >> GR8:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, >> GR16:$src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), GR16:$src2), >> addr:$dst)]>, >> + [(store (X86sube_flag (load addr:$dst), >> GR16:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>, >> OpSize; >> def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, >> GR32:$src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), GR32:$src2), >> addr:$dst)]>; >> + [(store (X86sube_flag (load addr:$dst), >> GR32:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm: >> $src2), >> "sbb{b}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (loadi8 addr:$dst), imm:$src2), >> addr:$dst)]>; >> + [(store (X86sube_flag (loadi8 addr:$dst), imm: >> $src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm: >> $src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (loadi16 addr:$dst), imm:$src2), >> addr:$dst)]>, >> + [(store (X86sube_flag (loadi16 addr:$dst), imm: >> $src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>, >> OpSize; >> def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, >> i16i8imm :$src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), i16immSExt8:$src2), >> addr:$dst)]>, >> + [(store (X86sube_flag (load addr:$dst), >> i16immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>, >> OpSize; >> def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm: >> $src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (loadi32 addr:$dst), imm:$src2), >> addr:$dst)]>; >> + [(store (X86sube_flag (loadi32 addr:$dst), imm: >> $src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, >> i32i8imm :$src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), i32immSExt8:$src2), >> addr:$dst)]>; >> + [(store (X86sube_flag (load addr:$dst), >> i32immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> } >> def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, >> i8mem:$src2), >> "sbb{b}\t{$src2, $dst|$dst, $src2}", >> - [(set GR8:$dst, (sube GR8:$src1, (load addr: >> $src2)))]>; >> + [(set GR8:$dst, >> + (X86sube_flag GR8:$src1, (load addr: >> $src2), EFLAGS)), >> + (implicit EFLAGS)]>; >> def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst), >> (ins GR16:$src1, i16mem:$src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (sube GR16:$src1, (load addr: >> $src2)))]>, >> + [(set GR16:$dst, >> + (X86sube_flag GR16:$src1, (load addr: >> $src2), EFLAGS)), >> + (implicit EFLAGS)]>, >> OpSize; >> def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), >> (ins GR32:$src1, i32mem:$src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (sube GR32:$src1, (load addr: >> $src2)))]>; >> + [(set GR32:$dst, >> + (X86sube_flag GR32:$src1, (load addr: >> $src2), EFLAGS)), >> + (implicit EFLAGS)]>; >> def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, >> i8imm:$src2), >> "sbb{b}\t{$src2, $dst|$dst, $src2}", >> - [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>; >> + [(set GR8:$dst, >> + (X86sube_flag GR8:$src1, imm:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst), >> (ins GR16:$src1, i16imm:$src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (sube GR16:$src1, imm:$src2))] >> >>> , OpSize; >>> >> + [(set GR16:$dst, >> + (X86sube_flag GR16:$src1, imm:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>, OpSize; >> def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst), >> (ins GR16:$src1, i16i8imm:$src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (sube GR16:$src1, >> i16immSExt8:$src2))]>, >> - OpSize; >> + [(set GR16:$dst, >> + (X86sube_flag GR16:$src1, >> i16immSExt8:$src2, EFLAGS)), >> + (implicit EFLAGS)]>, OpSize; >> def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), >> (ins GR32:$src1, i32imm:$src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>; >> + [(set GR32:$dst, >> + (X86sube_flag GR32:$src1, imm:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), >> (ins GR32:$src1, i32i8imm:$src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (sube GR32:$src1, >> i32immSExt8:$src2))]>; >> + [(set GR32:$dst, >> + (X86sube_flag GR32:$src1, >> i32immSExt8:$src2, EFLAGS)), >> + (implicit EFLAGS)]>; >> } // Uses = [EFLAGS] >> } // Defs = [EFLAGS] >> >> >> Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) >> +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Mon Jun 1 >> 18:27:20 2009 >> @@ -399,9 +399,13 @@ >> } else if (PropList[i]->getName() == "SDNPHasChain") { >> Properties |= 1 << SDNPHasChain; >> } else if (PropList[i]->getName() == "SDNPOutFlag") { >> - Properties |= 1 << SDNPOutFlag; >> + Properties |= 1 << SDNPOutFlag; >> + assert(!(Properties & (1<> + "Can't handle OutFlag and OutI1"); >> } else if (PropList[i]->getName() == "SDNPInFlag") { >> Properties |= 1 << SDNPInFlag; >> + assert(!(Properties & (1<> + "Can't handle InFlag and InI1"); >> } else if (PropList[i]->getName() == "SDNPOptInFlag") { >> Properties |= 1 << SDNPOptInFlag; >> } else if (PropList[i]->getName() == "SDNPMayStore") { >> @@ -412,6 +416,14 @@ >> Properties |= 1 << SDNPSideEffect; >> } else if (PropList[i]->getName() == "SDNPMemOperand") { >> Properties |= 1 << SDNPMemOperand; >> + } else if (PropList[i]->getName() == "SDNPInI1") { >> + Properties |= 1 << SDNPInI1; >> + assert(!(Properties & (1<> + "Can't handle InFlag and InI1"); >> + } else if (PropList[i]->getName() == "SDNPOutI1") { >> + Properties |= 1 << SDNPOutI1; >> + assert(!(Properties & (1<> + "Can't handle OutFlag and OutI1"); >> } else { >> cerr << "Unknown SD Node property '" << PropList[i]->getName() >> << "' on node '" << R->getName() << "'!\n"; >> >> Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) >> +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Jun 1 18:27:20 >> 2009 >> @@ -385,6 +385,13 @@ >> return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); >> } >> >> +/// supportsHasI1 - Return whether this target supports the >> implicit I1, >> +/// rather than Flags, for ADDC/ADDE >> +/// >> +bool CodeGenTarget::supportsHasI1() const { >> + return getInstructionSet()->getValueAsBit("supportsHasI1"); >> +} >> + >> // >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> // ComplexPattern implementation >> // >> >> Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/utils/TableGen/CodeGenTarget.h (original) >> +++ llvm/trunk/utils/TableGen/CodeGenTarget.h Mon Jun 1 18:27:20 2009 >> @@ -43,7 +43,9 @@ >> SDNPMayLoad, >> SDNPMayStore, >> SDNPSideEffect, >> - SDNPMemOperand >> + SDNPMemOperand, >> + SDNPInI1, >> + SDNPOutI1 >> }; >> >> // ComplexPattern attributes. >> @@ -209,10 +211,12 @@ >> void getInstructionsByEnumValue(std::vector> CodeGenInstruction*> >> >> &NumberedInstructions); >> >> - >> /// isLittleEndianEncoding - are instruction bit patterns defined >> as [0..n]? >> /// >> bool isLittleEndianEncoding() const; >> + >> + /// supportsHasI1 - does this target understand HasI1 for ADDE >> and ADDC? >> + bool supportsHasI1() const; >> }; >> >> /// ComplexPattern - ComplexPattern info, corresponding to the >> ComplexPattern >> >> Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) >> +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Jun 1 18:27:20 >> 2009 >> @@ -670,7 +670,8 @@ >> HasChain = true; >> FoldedChains.push_back(std::make_pair(RootName, >> CInfo.getNumResults())); >> } >> - if (NodeHasProperty(Child, SDNPOutFlag, CGP)) { >> + if (NodeHasProperty(Child, SDNPOutFlag, CGP) || >> + NodeHasProperty(Child, SDNPOutI1, CGP)) { >> assert(FoldedFlag.first == "" && FoldedFlag.second == 0 && >> "Pattern folded multiple nodes which produce flags?"); >> FoldedFlag = std::make_pair(RootName, >> @@ -969,6 +970,10 @@ >> PatternHasProperty(Pattern, SDNPInFlag, CGP); >> bool NodeHasOutFlag = isRoot && >> PatternHasProperty(Pattern, SDNPOutFlag, CGP); >> + bool NodeHasInI1 = isRoot && >> + PatternHasProperty(Pattern, SDNPInI1, CGP); >> + bool NodeHasOutI1 = isRoot && >> + PatternHasProperty(Pattern, SDNPOutI1, CGP); >> bool NodeHasChain = InstPatNode && >> PatternHasProperty(InstPatNode, SDNPHasChain, CGP); >> bool InputHasChain = isRoot && >> @@ -1054,10 +1059,13 @@ >> >> // Emit all the chain and CopyToReg stuff. >> bool ChainEmitted = NodeHasChain; >> - if (NodeHasInFlag || HasImpInputs) >> + // InFlag and InI1 cannot both be set (checked in >> + // CodeGenDAGPatterns), so use the same variables for both. >> + if (NodeHasInFlag || HasImpInputs || NodeHasInI1) >> EmitInFlagSelectCode(Pattern, "N", ChainEmitted, >> InFlagDecled, ResNodeDecled, true); >> - if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs) { >> + if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs || >> + NodeHasInI1) { >> if (!InFlagDecled) { >> emitCode("SDValue InFlag(0, 0);"); >> InFlagDecled = true; >> @@ -1113,7 +1121,7 @@ >> } >> if (NodeHasChain) >> Code += ", MVT::Other"; >> - if (NodeHasOutFlag) >> + if (NodeHasOutFlag || (NodeHasOutI1 && !CGT.supportsHasI1())) >> Code += ", MVT::Flag"; >> >> // Inputs. >> @@ -1173,7 +1181,8 @@ >> } >> Code += ", &Ops" + utostr(OpsNo) + "[0], Ops" + utostr >> (OpsNo) + >> ".size()"; >> - } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs) >> + } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs || >> + NodeHasInI1) >> AllOps.push_back("InFlag"); >> >> unsigned NumOps = AllOps.size(); >> @@ -1207,7 +1216,7 @@ >> NodeOps.push_back("Tmp" + utostr(ResNo)); >> } else { >> >> - if (NodeHasOutFlag) { >> + if (NodeHasOutFlag || NodeHasOutI1) { >> if (!InFlagDecled) { >> After.push_back("SDValue InFlag(ResNode, " + >> utostr(NumResults+NumDstRegs+(unsigned) >> NodeHasChain) + >> @@ -1228,13 +1237,15 @@ >> utostr(NumResults+NumDstRegs) + ")"); >> } >> >> - if (NodeHasOutFlag) { >> + if (NodeHasOutFlag || NodeHasOutI1) { >> if (FoldedFlag.first != "") { >> - ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + >> ".getNode(), " + >> + ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + >> + ".getNode(), " + >> utostr(FoldedFlag.second) + ")"); >> ReplaceTos.push_back("InFlag"); >> } else { >> - assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP)); >> + assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP) || >> + NodeHasProperty(Pattern, SDNPOutI1, CGP)); >> ReplaceFroms.push_back("SDValue(N.getNode(), " + >> utostr(NumPatResults + (unsigned) >> InputHasChain) >> + ")"); >> @@ -1251,7 +1262,8 @@ >> } >> >> // User does not expect the instruction would produce a chain! >> - if ((!InputHasChain && NodeHasChain) && NodeHasOutFlag) { >> + if ((!InputHasChain && NodeHasChain) && >> + (NodeHasOutFlag || NodeHasOutI1)) { >> ; >> } else if (InputHasChain && !NodeHasChain) { >> // One of the inner node produces a chain. >> @@ -1391,6 +1403,8 @@ >> unsigned OpNo = >> (unsigned) NodeHasProperty(N, SDNPHasChain, CGP); >> bool HasInFlag = NodeHasProperty(N, SDNPInFlag, CGP); >> + bool HasInI1 = NodeHasProperty(N, SDNPInI1, CGP); >> + bool InFlagDefined = false; >> for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, + >> +OpNo) { >> TreePatternNode *Child = N->getChild(i); >> if (!Child->isLeaf()) { >> @@ -1424,21 +1438,41 @@ >> emitCode("SDValue InFlag(0, 0);"); >> InFlagDecled = true; >> } >> - std::string Decl = (!ResNodeDecled) ? "SDNode *" : ""; >> - emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + >> ChainName + >> + if (HasInI1) { >> + if (!ResNodeDecled) { >> + emitCode("SDNode * ResNode;"); >> + } >> + if (T.supportsHasI1()) >> + emitCode("ResNode = CurDAG->getCopyToReg(" + >> ChainName + >> + ", " + RootName + ".getDebugLoc()" + >> + ", " + getEnumName(RVT) + >> + ", " + getQualifiedName(RR) + >> + ", " + RootName + utostr(OpNo) + >> ").getNode();"); >> + else >> + emitCode("ResNode = CurDAG->getCopyToReg(" + >> ChainName + >> + ", " + RootName + ".getDebugLoc()" + >> + ", " + getQualifiedName(RR) + >> + ", " + RootName + utostr(OpNo) + >> + ", InFlag).getNode();"); >> + InFlagDefined = true; >> + } else { >> + std::string Decl = (!ResNodeDecled) ? "SDNode *" : >> ""; >> + emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + >> ChainName + >> ", " + RootName + ".getDebugLoc()" + >> ", " + getQualifiedName(RR) + >> - ", " + RootName + utostr(OpNo) + ", >> InFlag).getNode();"); >> - ResNodeDecled = true; >> + ", " + RootName + utostr(OpNo) + >> + ", InFlag).getNode();"); >> + } >> emitCode(ChainName + " = SDValue(ResNode, 0);"); >> emitCode("InFlag = SDValue(ResNode, 1);"); >> + ResNodeDecled = true; >> } >> } >> } >> } >> } >> >> - if (HasInFlag) { >> + if (HasInFlag || (HasInI1 && !InFlagDefined)) { >> if (!InFlagDecled) { >> emitCode("SDValue InFlag = " + RootName + >> ".getOperand(" + utostr(OpNo) + ");"); >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From dalej at apple.com Tue Jun 2 13:20:16 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 2 Jun 2009 11:20:16 -0700 Subject: [llvm-commits] [llvm] r72707 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/X86/ utils/TableGen/ In-Reply-To: <4A256CEF.6070400@lip6.fr> References: <200906012327.n51NRMqY006632@zion.cs.uiuc.edu> <668F172C-93E7-47E8-9B1F-333154602253@apple.com> <4A256CEF.6070400@lip6.fr> Message-ID: <74E67F8C-A16D-4D07-8C24-6302A456A405@apple.com> On Jun 2, 2009, at 11:18 AMPDT, Nicolas Geoffray wrote: > For what it's worth, I'm having failures in VMKit's testsuite with > this > patch. I know you guys won't run VMKit's testsuite :), but if you > intend > to apply the patch, could you run llvm testsuite with it before > applying it? > > Thanks! > Nicolas I've already backed it out, it was causing some bootstrap problem also (which I've so far been unable to reproduce:( ) > Evan Cheng wrote: >> Hi Dale, >> >> On first glance, the patch mostly looks good. But I don't care for >> "supportsHasI1". I would have added ADDC_FLAG / ADDE_FLAG opcodes and >> have those use MVT::EFLAGS and change ADDC / ADDE to use MVT::i1 to >> represent the flag value. >> >> Thanks, >> >> Evan >> >> On Jun 1, 2009, at 4:27 PM, Dale Johannesen wrote: >> >> >>> Author: johannes >>> Date: Mon Jun 1 18:27:20 2009 >>> New Revision: 72707 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=72707&view=rev >>> Log: >>> Make the implicit inputs and outputs of target-independent >>> ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) >>> instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust >>> all target-independent code to use this format. >>> >>> Most targets will still produce a Flag-setting target-dependent >>> version when selection is done. X86 is converted to use i32 >>> instead, which means TableGen needs to produce different code >>> in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit >>> in xxxInstrInfo, currently set only for X86; in principle this >>> is temporary and should go away when all other targets have >>> been converted. All relevant X86 instruction patterns are >>> modified to represent setting and using EFLAGS explicitly. The >>> same can be done on other targets. >>> >>> The immediate behavior change is that an ADC/ADD pair are no >>> longer tightly coupled in the X86 scheduler; they can be >>> separated by instructions that don't clobber the flags (MOV). >>> I will soon add some peephole optimizations based on using >>> other instructions that set the flags to feed into ADC. >>> >>> >>> Modified: >>> llvm/trunk/include/llvm/CodeGen/SelectionDAG.h >>> llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h >>> llvm/trunk/include/llvm/Target/Target.td >>> llvm/trunk/include/llvm/Target/TargetSelectionDAG.td >>> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp >>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp >>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h >>> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp >>> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >>> llvm/trunk/lib/Target/X86/X86ISelLowering.h >>> llvm/trunk/lib/Target/X86/X86Instr64bit.td >>> llvm/trunk/lib/Target/X86/X86InstrInfo.td >>> llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >>> llvm/trunk/utils/TableGen/CodeGenTarget.cpp >>> llvm/trunk/utils/TableGen/CodeGenTarget.h >>> llvm/trunk/utils/TableGen/DAGISelEmitter.cpp >>> >>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) >>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Jun 1 >>> 18:27:20 2009 >>> @@ -324,6 +324,14 @@ >>> return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, >>> getRegister(Reg, N.getValueType()), N); >>> } >>> + // This version of getCopyToReg has the register (and its type) >>> as an >>> + // explicit output. >>> + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, MVT VT, unsigned >>> Reg, >>> + SDValue N) { >>> + SDVTList VTs = getVTList(MVT::Other, VT); >>> + SDValue Ops[] = { Chain, getRegister(Reg, VT), N}; >>> + return getNode(ISD::CopyToReg, dl, VTs, Ops, 3); >>> + } >>> >>> // This version of the getCopyToReg method takes an extra operand, >>> which >>> // indicates that there is potentially an incoming flag value (if >>> Flag is not >>> >>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) >>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Jun 1 >>> 18:27:20 2009 >>> @@ -242,14 +242,11 @@ >>> // remainder result. >>> SDIVREM, UDIVREM, >>> >>> - // CARRY_FALSE - This node is used when folding other nodes, >>> - // like ADDC/SUBC, which indicate the carry result is always >>> false. >>> - CARRY_FALSE, >>> - >>> // Carry-setting nodes for multiple precision addition and >>> subtraction. >>> // These nodes take two operands of the same value type, and >>> produce two >>> // results. The first result is the normal add or sub result, >>> the second >>> - // result is the carry flag result. >>> + // result is the carry flag result (type i1 or whatever it got >>> expanded to >>> + // for the target, value 0 or 1). >>> ADDC, SUBC, >>> >>> // Carry-using nodes for multiple precision addition and >>> subtraction. These >>> @@ -258,7 +255,8 @@ >>> // produce two results; the normal result of the add or sub, and >>> the output >>> // carry flag. These nodes both read and write a carry flag to >>> allow them >>> // to them to be chained together for add and sub of arbitrarily >>> large >>> - // values. >>> + // values. The carry flag (input and output) has type i1 or >>> whatever it >>> + // got expanded to for the target, and has value 0 or 1. >>> ADDE, SUBE, >>> >>> // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for >>> addition. >>> >>> Modified: llvm/trunk/include/llvm/Target/Target.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/include/llvm/Target/Target.td (original) >>> +++ llvm/trunk/include/llvm/Target/Target.td Mon Jun 1 18:27:20 >>> 2009 >>> @@ -326,6 +326,11 @@ >>> // Sparc manual specifies its instructions in the format [31..0] >>> (big), while >>> // PowerPC specifies them using the format [0..31] (little). >>> bit isLittleEndianEncoding = 0; >>> + >>> + // Targets that can support the HasI1 argument on ADDC and ADDE, >>> rather than >>> + // Flag, have this bit set. This is transitional and should go >>> away when all >>> + // targets have been switched over. >>> + bit supportsHasI1 = 0; >>> } >>> >>> // Standard Instructions. >>> >>> Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) >>> +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Mon Jun 1 >>> 18:27:20 2009 >>> @@ -216,6 +216,8 @@ >>> def SDNPMayLoad : SDNodeProperty; // May read memory, sets >>> 'mayLoad'. >>> def SDNPSideEffect : SDNodeProperty; // Sets >>> 'HasUnmodelledSideEffects'. >>> def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc >>> MemOperand >>> +def SDNPInI1 : SDNodeProperty; // Read an extra I1 operand >>> +def SDNPOutI1 : SDNodeProperty; // Write an extra I1 result >>> >>> // >>> = >>> = >>> = >>> ----------------------------------------------------------------------= >>> ==// >>> // Selection DAG Node definitions. >>> @@ -289,13 +291,13 @@ >>> def xor : SDNode<"ISD::XOR" , SDTIntBinOp, >>> [SDNPCommutative, SDNPAssociative]>; >>> def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, >>> - [SDNPCommutative, SDNPOutFlag]>; >>> + [SDNPCommutative, SDNPOutI1]>; >>> def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, >>> - [SDNPCommutative, SDNPOutFlag, >>> SDNPInFlag]>; >>> + [SDNPCommutative, SDNPInI1, SDNPOutI1]>; >>> def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, >>> - [SDNPOutFlag]>; >>> + [SDNPOutI1]>; >>> def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, >>> - [SDNPOutFlag, SDNPInFlag]>; >>> + [SDNPInI1, SDNPOutI1]>; >>> >>> def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; >>> def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; >>> >>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) >>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jun 1 >>> 18:27:20 2009 >>> @@ -1085,8 +1085,7 @@ >>> // If the flag result is dead, turn this into an ADD. >>> if (N->hasNUsesOfValue(0, 1)) >>> return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, >>> N1, N0), >>> - DAG.getNode(ISD::CARRY_FALSE, >>> - N->getDebugLoc(), MVT::Flag)); >>> + DAG.getConstant(0, N->getValueType(1))); >>> >>> // canonicalize constant to RHS. >>> if (N0C && !N1C) >>> @@ -1094,10 +1093,9 @@ >>> >>> // fold (addc x, 0) -> x + no carry out >>> if (N1C && N1C->isNullValue()) >>> - return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, >>> - N->getDebugLoc(), >>> MVT::Flag)); >>> + return CombineTo(N, N0, DAG.getConstant(0, N1.getValueType())); >>> >>> - // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share >>> no bits. >>> + // fold (addc a, b) -> (or a, b), 0 iff a and b share no bits. >>> APInt LHSZero, LHSOne; >>> APInt RHSZero, RHSOne; >>> APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); >>> @@ -1111,8 +1109,7 @@ >>> if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || >>> (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) >>> return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, >>> N0, N1), >>> - DAG.getNode(ISD::CARRY_FALSE, >>> - N->getDebugLoc(), MVT::Flag)); >>> + DAG.getConstant(0, N1.getValueType())); >>> } >>> >>> return SDValue(); >>> @@ -1131,8 +1128,9 @@ >>> N1, N0, CarryIn); >>> >>> // fold (adde x, y, false) -> (addc x, y) >>> - if (CarryIn.getOpcode() == ISD::CARRY_FALSE) >>> - return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), >>> N1, N0); >>> + if (ConstantSDNode *N2C = dyn_cast(CarryIn)) >>> + if (N2C->getAPIntValue()==0) >>> + return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList >>> (), N1, N0); >>> >>> return SDValue(); >>> } >>> >>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ >>> LegalizeIntegerTypes.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp >>> (original) >>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon >>> Jun 1 18:27:20 2009 >>> @@ -98,6 +98,10 @@ >>> case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); >>> break; >>> case ISD::SMULO: >>> case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; >>> + case ISD::ADDC: >>> + case ISD::SUBC: Res = PromoteIntRes_ADDSUBC(N, ResNo); >>> break; >>> + case ISD::ADDE: >>> + case ISD::SUBE: Res = PromoteIntRes_ADDSUBE(N, ResNo); >>> break; >>> >>> case ISD::ATOMIC_LOAD_ADD: >>> case ISD::ATOMIC_LOAD_SUB: >>> @@ -121,6 +125,35 @@ >>> SetPromotedInteger(SDValue(N, ResNo), Res); >>> } >>> >>> +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBC(SDNode *N, unsigned >>> ResNo) { >>> + // Only the carry bit result is expected to be promoted. >>> + assert(ResNo == 1 && "Only carry bit result promotion currently >>> supported!"); >>> + return PromoteIntRes_Overflow(N); >>> +} >>> + >>> +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBE(SDNode *N, unsigned >>> ResNo) { >>> + // Only the carry bit result is expected to be promoted. >>> + assert(ResNo == 1 && "Only carry bit result promotion currently >>> supported!"); >>> + // This is a ternary operator, so clone a slightly modified >>> + // PromoteIntRes_Overflow here (this is the only client). >>> + if (ResNo == 1) { >>> + // Simply change the return type of the boolean result. >>> + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); >>> + MVT ValueVTs[] = { N->getValueType(0), NVT }; >>> + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N- >>> >>>> getOperand(2) }; >>>> >>> + SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), >>> + DAG.getVTList(ValueVTs, 2), Ops, 3); >>> + >>> + // Modified the sum result - switch anything that used the old >>> sum to use >>> + // the new one. >>> + ReplaceValueWith(SDValue(N, 0), Res); >>> + >>> + return SDValue(Res.getNode(), 1); >>> + } >>> + assert(0 && "Do not know how to promote this operator!"); >>> + abort(); >>> +} >>> + >>> SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { >>> // Sign-extend the new bits, and continue the assertion. >>> SDValue Op = SExtPromotedInteger(N->getOperand(0)); >>> @@ -419,7 +452,7 @@ >>> return Res; >>> } >>> >>> -/// Promote the overflow flag of an overflowing arithmetic node. >>> +/// Promote the overflow or carry result of an overflowing >>> arithmetic node. >>> SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { >>> // Simply change the return type of the boolean result. >>> MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); >>> @@ -666,6 +699,8 @@ >>> assert(0 && "Do not know how to promote this operator's >>> operand!"); >>> abort(); >>> >>> + case ISD::ADDE: >>> + case ISD::SUBE: Res = PromoteIntOp_ADDSUBE(N, OpNo); >>> break; >>> case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; >>> case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; >>> case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; >>> @@ -743,6 +778,13 @@ >>> } >>> } >>> >>> +SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBE(SDNode *N, unsigned >>> OpNo) { >>> + assert(OpNo == 2 && "Don't know how to promote this operand!"); >>> + return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), >>> + N->getOperand(1), >>> + GetPromotedInteger(N->getOperand >>> (2))); >>> +} >>> + >>> SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { >>> SDValue Op = GetPromotedInteger(N->getOperand(0)); >>> return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N- >>> >>>> getValueType(0), Op); >>>> >>> @@ -1063,7 +1105,7 @@ >>> TLI.isOperationLegalOrCustom(ISD::ADDC, >>> TLI.getTypeToExpandTo >>> (NVT))) { >>> // Emit this X << 1 as X+X. >>> - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); >>> + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); >>> SDValue LoOps[2] = { InL, InL }; >>> Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); >>> SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; >>> @@ -1299,7 +1341,7 @@ >>> TLI.getTypeToExpandTo(NVT)); >>> >>> if (hasCarry) { >>> - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); >>> + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); >>> if (N->getOpcode() == ISD::ADD) { >>> Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); >>> HiOps[2] = Lo.getValue(1); >>> @@ -1344,7 +1386,7 @@ >>> DebugLoc dl = N->getDebugLoc(); >>> GetExpandedInteger(N->getOperand(0), LHSL, LHSH); >>> GetExpandedInteger(N->getOperand(1), RHSL, RHSH); >>> - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); >>> + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); >>> SDValue LoOps[2] = { LHSL, RHSL }; >>> SDValue HiOps[3] = { LHSH, RHSH }; >>> >>> @@ -1358,8 +1400,8 @@ >>> Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); >>> } >>> >>> - // Legalized the flag result - switch anything that used the old >>> flag to >>> - // use the new one. >>> + // Legalized the second result (carry bit) - switch anything that >>> used the >>> + // result to use the new one. >>> ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); >>> } >>> >>> @@ -1370,7 +1412,7 @@ >>> DebugLoc dl = N->getDebugLoc(); >>> GetExpandedInteger(N->getOperand(0), LHSL, LHSH); >>> GetExpandedInteger(N->getOperand(1), RHSL, RHSH); >>> - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); >>> + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); >>> SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; >>> SDValue HiOps[3] = { LHSH, RHSH }; >>> >>> @@ -1378,8 +1420,8 @@ >>> HiOps[2] = Lo.getValue(1); >>> Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); >>> >>> - // Legalized the flag result - switch anything that used the old >>> flag to >>> - // use the new one. >>> + // Legalized the second result (carry bit) - switch anything that >>> used the >>> + // result to use the new one. >>> ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); >>> } >>> >>> >>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) >>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Jun 1 >>> 18:27:20 2009 >>> @@ -242,6 +242,8 @@ >>> >>> // Integer Result Promotion. >>> void PromoteIntegerResult(SDNode *N, unsigned ResNo); >>> + SDValue PromoteIntRes_ADDSUBC(SDNode *N, unsigned ResNo); >>> + SDValue PromoteIntRes_ADDSUBE(SDNode *N, unsigned ResNo); >>> SDValue PromoteIntRes_AssertSext(SDNode *N); >>> SDValue PromoteIntRes_AssertZext(SDNode *N); >>> SDValue PromoteIntRes_Atomic1(AtomicSDNode *N); >>> @@ -278,6 +280,7 @@ >>> >>> // Integer Operand Promotion. >>> bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo); >>> + SDValue PromoteIntOp_ADDSUBE(SDNode *N, unsigned OpNo); >>> SDValue PromoteIntOp_ANY_EXTEND(SDNode *N); >>> SDValue PromoteIntOp_BIT_CONVERT(SDNode *N); >>> SDValue PromoteIntOp_BUILD_PAIR(SDNode *N); >>> >>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >>> (original) >>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Mon >>> Jun 1 18:27:20 2009 >>> @@ -268,6 +268,13 @@ >>> unsigned N = Node->getNumOperands(); >>> while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) >>> --N; >>> + // Skip hard registers set as a side effect (i.e. not result 0). >>> + while (N && Node->getOperand(N - 1).getOpcode() == ISD::CopyToReg >>> && >>> + Node->getOperand(N-1).getResNo() != 0 && >>> + !TargetRegisterInfo::isVirtualRegister( >>> + dyn_cast(Node->getOperand >>> (N-1).getOperand(1)) >>> + ->getReg())) >>> + --N; >>> if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) >>> --N; // Ignore chain if it exists. >>> return N; >>> >>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) >>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 1 >>> 18:27:20 2009 >>> @@ -5257,7 +5257,6 @@ >>> case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; >>> case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; >>> case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; >>> - case ISD::CARRY_FALSE: return "carry_false"; >>> case ISD::ADDC: return "addc"; >>> case ISD::ADDE: return "adde"; >>> case ISD::SADDO: return "saddo"; >>> >>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) >>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jun 1 >>> 18:27:20 2009 >>> @@ -190,6 +190,28 @@ >>> setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); >>> } >>> >>> + // ADDE and SUBE are lowered to local versions that contain >>> EFLAGS explicitly. >>> + // ADDC and SUBC are lowered to local versions so EFLAGS will be >>> an i32 >>> + // rather than the Flag used by the generic patterns. >>> + setOperationAction(ISD::ADDC , MVT::i8 , Custom); >>> + setOperationAction(ISD::ADDC , MVT::i16 , Custom); >>> + setOperationAction(ISD::ADDC , MVT::i32 , Custom); >>> + setOperationAction(ISD::SUBC , MVT::i8 , Custom); >>> + setOperationAction(ISD::SUBC , MVT::i16 , Custom); >>> + setOperationAction(ISD::SUBC , MVT::i32 , Custom); >>> + setOperationAction(ISD::ADDE , MVT::i8 , Custom); >>> + setOperationAction(ISD::ADDE , MVT::i16 , Custom); >>> + setOperationAction(ISD::ADDE , MVT::i32 , Custom); >>> + setOperationAction(ISD::SUBE , MVT::i8 , Custom); >>> + setOperationAction(ISD::SUBE , MVT::i16 , Custom); >>> + setOperationAction(ISD::SUBE , MVT::i32 , Custom); >>> + if (Subtarget->is64Bit()) { >>> + setOperationAction(ISD::ADDC , MVT::i64 , >>> Custom); >>> + setOperationAction(ISD::SUBC , MVT::i64 , >>> Custom); >>> + setOperationAction(ISD::ADDE , MVT::i64 , >>> Custom); >>> + setOperationAction(ISD::SUBE , MVT::i64 , >>> Custom); >>> + } >>> + >>> // Scalar integer divide and remainder are lowered to use >>> operations that >>> // produce two results, to match the available instructions. This >>> exposes >>> // the two-result form to trivial CSE, which is able to combine x/ >>> y and x%y >>> @@ -6475,6 +6497,21 @@ >>> return Sum; >>> } >>> >>> +SDValue X86TargetLowering::LowerADDSUBE(SDValue Op, SelectionDAG >>> &DAG) { >>> + DebugLoc dl = Op.getDebugLoc(); >>> + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); >>> + return DAG.getNode(Op.getOpcode()==ISD::ADDE ? X86ISD::ADDE : >>> X86ISD::SUBE, >>> + dl, VTs, Op.getOperand(0), Op.getOperand(1), >>> + Op.getOperand(2).getValue(1)); >>> +} >>> + >>> +SDValue X86TargetLowering::LowerADDSUBC(SDValue Op, SelectionDAG >>> &DAG) { >>> + DebugLoc dl = Op.getDebugLoc(); >>> + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); >>> + return DAG.getNode(Op.getOpcode()==ISD::ADDC ? X86ISD::ADD : >>> X86ISD::SUB, >>> + dl, VTs, Op.getOperand(0), Op.getOperand(1)); >>> +} >>> + >>> SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG >>> &DAG) { >>> MVT T = Op.getValueType(); >>> DebugLoc dl = Op.getDebugLoc(); >>> @@ -6543,6 +6580,10 @@ >>> SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG >>> &DAG) { >>> switch (Op.getOpcode()) { >>> default: assert(0 && "Should not custom lower this!"); >>> + case ISD::ADDC: >>> + case ISD::SUBC: return LowerADDSUBC(Op,DAG); >>> + case ISD::ADDE: >>> + case ISD::SUBE: return LowerADDSUBE(Op,DAG); >>> case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); >>> case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); >>> case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); >>> @@ -6791,6 +6832,10 @@ >>> case X86ISD::INC: return "X86ISD::INC"; >>> case X86ISD::DEC: return "X86ISD::DEC"; >>> case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; >>> + case X86ISD::ADDE: return "X86ISD::ADDE"; >>> + case X86ISD::SUBE: return "X86ISD::SUBE"; >>> + case X86ISD::ADDC: return "X86ISD::ADDC"; >>> + case X86ISD::SUBC: return "X86ISD::SUBC"; >>> } >>> } >>> >>> >>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) >>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Jun 1 18:27:20 >>> 2009 >>> @@ -243,6 +243,14 @@ >>> ADD, SUB, SMUL, UMUL, >>> INC, DEC, >>> >>> + // ADDC, SUBC - Arithmetic operations setting carry bit. The >>> normal >>> + // arithmetic operations do this, but they represent it as >>> Flag, and >>> + // we want the i32 EFLAGS register here. >>> + ADDC, SUBC, >>> + >>> + // ADDE, SUBE - Arithmetic operations with extra FLAGS >>> (EFLAGS) inputs. >>> + ADDE, SUBE, >>> + >>> // MUL_IMM - X86 specific multiply by immediate. >>> MUL_IMM >>> }; >>> @@ -576,7 +584,9 @@ >>> >>> std::pair FP_TO_INTHelper(SDValue Op, >>> SelectionDAG &DAG, >>> bool isSigned); >>> - >>> + >>> + SDValue LowerADDSUBC(SDValue Op, SelectionDAG &DAG); >>> + SDValue LowerADDSUBE(SDValue Op, SelectionDAG &DAG); >>> SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); >>> SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); >>> SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); >>> >>> Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) >>> +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Mon Jun 1 18:27:20 >>> 2009 >>> @@ -383,31 +383,52 @@ >>> let Uses = [EFLAGS] in { >>> let isTwoAddress = 1 in { >>> let isCommutable = 1 in >>> -def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins >>> GR64:$src1, GR64:$src2), >>> +def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), >>> + (ins GR64:$src1, GR64:$src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (adde GR64:$src1, >>> GR64:$src2))]>; >>> + [(set GR64:$dst, >>> + (X86adde_flag GR64:$src1, GR64:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> >>> -def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins >>> GR64:$src1, i64mem:$src2), >>> +def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), >>> + (ins GR64:$src1, i64mem:$src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (adde GR64:$src1, (load addr: >>> $src2)))]>; >>> + [(set GR64:$dst, >>> + (X86adde_flag GR64:$src1, (load addr: >>> $src2), EFLAGS)), >>> + (implicit EFLAGS)]>; >>> >>> -def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, >>> i64i8imm:$src2), >>> +def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), >>> + (ins GR64:$src1, i64i8imm:$src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (adde GR64:$src1, >>> i64immSExt8:$src2))]>; >>> -def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins >>> GR64:$src1, i64i32imm:$src2), >>> + [(set GR64:$dst, >>> + (X86adde_flag GR64:$src1, >>> i64immSExt8:$src2, EFLAGS)), >>> + (implicit EFLAGS)]>; >>> +def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), >>> + (ins GR64:$src1, i64i32imm: >>> $src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (adde GR64:$src1, >>> i64immSExt32:$src2))]>; >>> + [(set GR64:$dst, >>> + (X86adde_flag GR64:$src1, >>> i64immSExt32:$src2, >>> + EFLAGS)), >>> + (implicit EFLAGS)]>; >>> } // isTwoAddress >>> >>> def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, >>> GR64:$src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), GR64:$src2), >>> addr: >>> $dst)]>; >>> + [(store (X86adde_flag (load addr:$dst), >>> GR64:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, >>> i64i8imm : >>> $src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), >>> i64immSExt8:$src2), addr:$dst)]>; >>> + [(store (X86adde_flag (load addr:$dst), >>> i64immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, >>> i64i32imm:$src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), >>> i64immSExt8:$src2), addr:$dst)]>; >>> + [(store (X86adde_flag (load addr:$dst), >>> i64immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> } // Uses = [EFLAGS] >>> >>> let isTwoAddress = 1 in { >>> @@ -456,31 +477,52 @@ >>> >>> let Uses = [EFLAGS] in { >>> let isTwoAddress = 1 in { >>> -def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins >>> GR64:$src1, GR64:$src2), >>> +def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), >>> + (ins GR64:$src1, GR64:$src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (sube GR64:$src1, >>> GR64:$src2))] >>> >>>> ; >>>> >>> + [(set GR64:$dst, >>> + (X86sube_flag GR64:$src1, GR64:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> >>> -def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins >>> GR64:$src1, i64mem:$src2), >>> +def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), >>> + (ins GR64:$src1, i64mem:$src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (sube GR64:$src1, (load addr: >>> $src2)))]>; >>> + [(set GR64:$dst, >>> + (X86sube_flag GR64:$src1, (load addr: >>> $src2), EFLAGS)), >>> + (implicit EFLAGS)]>; >>> >>> -def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, >>> i64i8imm:$src2), >>> +def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), >>> + (ins GR64:$src1, i64i8imm:$src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (sube GR64:$src1, >>> i64immSExt8:$src2))]>; >>> -def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins >>> GR64:$src1, i64i32imm:$src2), >>> + [(set GR64:$dst, >>> + (X86sube_flag GR64:$src1, >>> i64immSExt8:$src2, EFLAGS)), >>> + (implicit EFLAGS)]>; >>> +def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), >>> + (ins GR64:$src1, i64i32imm: >>> $src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (sube GR64:$src1, >>> i64immSExt32:$src2))]>; >>> + [(set GR64:$dst, >>> + (X86sube_flag GR64:$src1, >>> i64immSExt32:$src2, >>> + EFLAGS)), >>> + (implicit EFLAGS)]>; >>> } // isTwoAddress >>> >>> def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, >>> GR64:$src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), GR64:$src2), >>> addr: >>> $dst)]>; >>> + [(store (X86sube_flag (load addr:$dst), >>> GR64:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, >>> i64i8imm : >>> $src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), i64immSExt8:$src2), >>> addr:$dst)]>; >>> + [(store (X86sube_flag (load addr:$dst), >>> i64immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, >>> i64i32imm:$src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), i64immSExt32:$src2), >>> addr:$dst)]>; >>> + [(store (X86sube_flag (load addr:$dst), >>> i64immSExt32:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> } // Uses = [EFLAGS] >>> } // Defs = [EFLAGS] >>> >>> >>> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) >>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Jun 1 18:27:20 >>> 2009 >>> @@ -34,6 +34,11 @@ >>> [SDTCisSameAs<0, 1>, >>> SDTCisSameAs<0, 2>, >>> SDTCisInt<0>]>; >>> +// Unary and binary operators that both read and write EFLAGS as a >>> side-effect. >>> +def SDTBinaryArithRWFlags : SDTypeProfile<1, 3, >>> + [SDTCisInt<0>, SDTCisSameAs<0, >>> 1>, >>> + SDTCisSameAs<0, 2>, SDTCisVT<3, >>> i32>]>; >>> + >>> def SDTX86BrCond : SDTypeProfile<0, 3, >>> [SDTCisVT<0, OtherVT>, >>> SDTCisVT<1, i8>, SDTCisVT<2, i32>] >>> >>>> ; >>>> >>> @@ -156,6 +161,8 @@ >>> def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>; >>> def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; >>> def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; >>> +def X86adde_flag : SDNode<"X86ISD::ADDE", SDTBinaryArithRWFlags, >>> [SDNPInI1]>; >>> +def X86sube_flag : SDNode<"X86ISD::SUBE", SDTBinaryArithRWFlags, >>> [SDNPInI1]>; >>> >>> def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; >>> >>> @@ -2274,81 +2281,127 @@ >>> >>> let Uses = [EFLAGS] in { >>> let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y >>> -def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, >>> GR8:$src2), >>> +def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), >>> + (ins GR8:$src1, GR8:$src2), >>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>; >>> + [(set GR8:$dst, (X86adde_flag GR8:$src1, >>> GR8:$src2, EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst), >>> (ins GR16:$src1, GR16:$src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, >>> OpSize; >>> + [(set GR16:$dst, >>> + (X86adde_flag GR16:$src1, GR16:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>, >>> + OpSize; >>> def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), >>> (ins GR32:$src1, GR32:$src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; >>> + [(set GR32:$dst, >>> + (X86adde_flag GR32:$src1, GR32:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> } >>> def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst), >>> (ins GR8:$src1, i8mem:$src2), >>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR8:$dst, (adde GR8:$src1, (load addr: >>> $src2)))]>; >>> + [(set GR8:$dst, >>> + (X86adde_flag GR8:$src1, (load addr:$src2), >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst), >>> (ins GR16:$src1, i16mem:$src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (adde GR16:$src1, (load addr: >>> $src2)))]>, >>> + [(set GR16:$dst, >>> + (X86adde_flag GR16:$src1, (load addr:$src2), >>> EFLAGS)), >>> + (implicit EFLAGS)]>, >>> OpSize; >>> def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), >>> (ins GR32:$src1, i32mem:$src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (adde GR32:$src1, (load addr: >>> $src2)))]>; >>> -def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, >>> i8imm:$src2), >>> + [(set GR32:$dst, >>> + (X86adde_flag GR32:$src1, (load addr:$src2), >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> +def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), >>> + (ins GR8:$src1, i8imm:$src2), >>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>; >>> + [(set GR8:$dst, >>> + (X86adde_flag GR8:$src1, imm:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst), >>> (ins GR16:$src1, i16imm:$src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, >>> OpSize; >>> + [(set GR16:$dst, >>> + (X86adde_flag GR16:$src1, imm:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>, OpSize; >>> def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst), >>> (ins GR16:$src1, i16i8imm:$src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (adde GR16:$src1, >>> i16immSExt8:$src2))]>, >>> - OpSize; >>> + [(set GR16:$dst, >>> + (X86adde_flag GR16:$src1, i16immSExt8:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>, OpSize; >>> def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), >>> (ins GR32:$src1, i32imm:$src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; >>> + [(set GR32:$dst, >>> + (X86adde_flag GR32:$src1, imm:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), >>> (ins GR32:$src1, i32i8imm:$src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (adde GR32:$src1, >>> i32immSExt8:$src2))]>; >>> + [(set GR32:$dst, >>> + (X86adde_flag GR32:$src1, i32immSExt8:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> >>> let isTwoAddress = 0 in { >>> - def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, >>> GR8:$src2), >>> + def ADC8mr : I<0x10, MRMDestMem, (outs), >>> + (ins i8mem:$dst, GR8:$src2), >>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), GR8:$src2), >>> addr: >>> $dst)]>; >>> - def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, >>> GR16:$src2), >>> + [(store (X86adde_flag (load addr:$dst), >>> GR8:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> + def ADC16mr : I<0x11, MRMDestMem, (outs), >>> + (ins i16mem:$dst, GR16:$src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), GR16:$src2), >>> addr:$dst)]>, >>> - OpSize; >>> - def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, >>> GR32:$src2), >>> + [(store (X86adde_flag (load addr:$dst), >>> GR16:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>, OpSize; >>> + def ADC32mr : I<0x11, MRMDestMem, (outs), >>> + (ins i32mem:$dst, GR32:$src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), GR32:$src2), >>> addr:$dst)]>; >>> - def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm: >>> $src2), >>> + [(store (X86adde_flag (load addr:$dst), >>> GR32:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> + def ADC8mi : Ii8<0x80, MRM2m, (outs), >>> + (ins i8mem:$dst, i8imm:$src2), >>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (loadi8 addr:$dst), imm:$src2), >>> addr:$dst)]>; >>> - def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, >>> i16imm: >>> $src2), >>> + [(store (X86adde_flag (loadi8 addr:$dst), imm: >>> $src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> + def ADC16mi : Ii16<0x81, MRM2m, (outs), >>> + (ins i16mem:$dst, i16imm:$src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (loadi16 addr:$dst), imm:$src2), >>> addr:$dst)]>, >>> - OpSize; >>> - def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, >>> i16i8imm :$src2), >>> + [(store (X86adde_flag (loadi16 addr:$dst), imm: >>> $src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>, OpSize; >>> + def ADC16mi8 : Ii8<0x83, MRM2m, (outs), >>> + (ins i16mem:$dst, i16i8imm : >>> $src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), i16immSExt8:$src2), >>> addr:$dst)]>, >>> - OpSize; >>> - def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, >>> i32imm: >>> $src2), >>> + [(store (X86adde_flag (load addr:$dst), >>> i16immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>, OpSize; >>> + def ADC32mi : Ii32<0x81, MRM2m, (outs), >>> + (ins i32mem:$dst, i32imm:$src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (loadi32 addr:$dst), imm:$src2), >>> addr:$dst)]>; >>> - def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, >>> i32i8imm :$src2), >>> + [(store (X86adde_flag (loadi32 addr:$dst), imm: >>> $src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> + def ADC32mi8 : Ii8<0x83, MRM2m, (outs), >>> + (ins i32mem:$dst, i32i8imm: >>> $src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), i32immSExt8:$src2), >>> addr:$dst)]>; >>> -} >>> + [(store (X86adde_flag (load addr:$dst), >>> i32immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> + } >>> } // Uses = [EFLAGS] >>> >>> // Register-Register Subtraction >>> @@ -2453,77 +2506,115 @@ >>> def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst), >>> (ins GR8:$src1, GR8:$src2), >>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>; >>> + [(set GR8:$dst, (X86sube_flag GR8:$src1, >>> GR8:$src2, EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst), >>> (ins GR16:$src1, GR16:$src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, >>> OpSize; >>> + [(set GR16:$dst, >>> + (X86sube_flag GR16:$src1, GR16:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>, OpSize; >>> def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), >>> (ins GR32:$src1, GR32:$src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; >>> + [(set GR32:$dst, >>> + (X86sube_flag GR32:$src1, GR32:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> >>> let isTwoAddress = 0 in { >>> def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, >>> GR8:$src2), >>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), GR8:$src2), >>> addr: >>> $dst)]>; >>> + [(store (X86sube_flag (load addr:$dst), >>> GR8:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, >>> GR16:$src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), GR16:$src2), >>> addr:$dst)]>, >>> + [(store (X86sube_flag (load addr:$dst), >>> GR16:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>, >>> OpSize; >>> def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, >>> GR32:$src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), GR32:$src2), >>> addr:$dst)]>; >>> + [(store (X86sube_flag (load addr:$dst), >>> GR32:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm: >>> $src2), >>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (loadi8 addr:$dst), imm:$src2), >>> addr:$dst)]>; >>> + [(store (X86sube_flag (loadi8 addr:$dst), imm: >>> $src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm: >>> $src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (loadi16 addr:$dst), imm:$src2), >>> addr:$dst)]>, >>> + [(store (X86sube_flag (loadi16 addr:$dst), imm: >>> $src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>, >>> OpSize; >>> def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, >>> i16i8imm :$src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), i16immSExt8:$src2), >>> addr:$dst)]>, >>> + [(store (X86sube_flag (load addr:$dst), >>> i16immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>, >>> OpSize; >>> def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm: >>> $src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (loadi32 addr:$dst), imm:$src2), >>> addr:$dst)]>; >>> + [(store (X86sube_flag (loadi32 addr:$dst), imm: >>> $src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, >>> i32i8imm :$src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), i32immSExt8:$src2), >>> addr:$dst)]>; >>> + [(store (X86sube_flag (load addr:$dst), >>> i32immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> } >>> def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, >>> i8mem:$src2), >>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR8:$dst, (sube GR8:$src1, (load addr: >>> $src2)))]>; >>> + [(set GR8:$dst, >>> + (X86sube_flag GR8:$src1, (load addr: >>> $src2), EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst), >>> (ins GR16:$src1, i16mem:$src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (sube GR16:$src1, (load addr: >>> $src2)))]>, >>> + [(set GR16:$dst, >>> + (X86sube_flag GR16:$src1, (load addr: >>> $src2), EFLAGS)), >>> + (implicit EFLAGS)]>, >>> OpSize; >>> def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), >>> (ins GR32:$src1, i32mem:$src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (sube GR32:$src1, (load addr: >>> $src2)))]>; >>> + [(set GR32:$dst, >>> + (X86sube_flag GR32:$src1, (load addr: >>> $src2), EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, >>> i8imm:$src2), >>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>; >>> + [(set GR8:$dst, >>> + (X86sube_flag GR8:$src1, imm:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst), >>> (ins GR16:$src1, i16imm:$src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (sube GR16:$src1, imm:$src2))] >>> >>>> , OpSize; >>>> >>> + [(set GR16:$dst, >>> + (X86sube_flag GR16:$src1, imm:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>, OpSize; >>> def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst), >>> (ins GR16:$src1, i16i8imm:$src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (sube GR16:$src1, >>> i16immSExt8:$src2))]>, >>> - OpSize; >>> + [(set GR16:$dst, >>> + (X86sube_flag GR16:$src1, >>> i16immSExt8:$src2, EFLAGS)), >>> + (implicit EFLAGS)]>, OpSize; >>> def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), >>> (ins GR32:$src1, i32imm:$src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (sube GR32:$src1, imm: >>> $src2))]>; >>> + [(set GR32:$dst, >>> + (X86sube_flag GR32:$src1, imm:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), >>> (ins GR32:$src1, i32i8imm:$src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (sube GR32:$src1, >>> i32immSExt8:$src2))]>; >>> + [(set GR32:$dst, >>> + (X86sube_flag GR32:$src1, >>> i32immSExt8:$src2, EFLAGS)), >>> + (implicit EFLAGS)]>; >>> } // Uses = [EFLAGS] >>> } // Defs = [EFLAGS] >>> >>> >>> Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) >>> +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Mon Jun 1 >>> 18:27:20 2009 >>> @@ -399,9 +399,13 @@ >>> } else if (PropList[i]->getName() == "SDNPHasChain") { >>> Properties |= 1 << SDNPHasChain; >>> } else if (PropList[i]->getName() == "SDNPOutFlag") { >>> - Properties |= 1 << SDNPOutFlag; >>> + Properties |= 1 << SDNPOutFlag; >>> + assert(!(Properties & (1<>> + "Can't handle OutFlag and OutI1"); >>> } else if (PropList[i]->getName() == "SDNPInFlag") { >>> Properties |= 1 << SDNPInFlag; >>> + assert(!(Properties & (1<>> + "Can't handle InFlag and InI1"); >>> } else if (PropList[i]->getName() == "SDNPOptInFlag") { >>> Properties |= 1 << SDNPOptInFlag; >>> } else if (PropList[i]->getName() == "SDNPMayStore") { >>> @@ -412,6 +416,14 @@ >>> Properties |= 1 << SDNPSideEffect; >>> } else if (PropList[i]->getName() == "SDNPMemOperand") { >>> Properties |= 1 << SDNPMemOperand; >>> + } else if (PropList[i]->getName() == "SDNPInI1") { >>> + Properties |= 1 << SDNPInI1; >>> + assert(!(Properties & (1<>> + "Can't handle InFlag and InI1"); >>> + } else if (PropList[i]->getName() == "SDNPOutI1") { >>> + Properties |= 1 << SDNPOutI1; >>> + assert(!(Properties & (1<>> + "Can't handle OutFlag and OutI1"); >>> } else { >>> cerr << "Unknown SD Node property '" << PropList[i]->getName() >>> << "' on node '" << R->getName() << "'!\n"; >>> >>> Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) >>> +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Jun 1 18:27:20 >>> 2009 >>> @@ -385,6 +385,13 @@ >>> return getInstructionSet()- >>> >getValueAsBit("isLittleEndianEncoding"); >>> } >>> >>> +/// supportsHasI1 - Return whether this target supports the >>> implicit I1, >>> +/// rather than Flags, for ADDC/ADDE >>> +/// >>> +bool CodeGenTarget::supportsHasI1() const { >>> + return getInstructionSet()->getValueAsBit("supportsHasI1"); >>> +} >>> + >>> // >>> = >>> = >>> = >>> ----------------------------------------------------------------------= >>> ==// >>> // ComplexPattern implementation >>> // >>> >>> Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/utils/TableGen/CodeGenTarget.h (original) >>> +++ llvm/trunk/utils/TableGen/CodeGenTarget.h Mon Jun 1 18:27:20 >>> 2009 >>> @@ -43,7 +43,9 @@ >>> SDNPMayLoad, >>> SDNPMayStore, >>> SDNPSideEffect, >>> - SDNPMemOperand >>> + SDNPMemOperand, >>> + SDNPInI1, >>> + SDNPOutI1 >>> }; >>> >>> // ComplexPattern attributes. >>> @@ -209,10 +211,12 @@ >>> void getInstructionsByEnumValue(std::vector>> CodeGenInstruction*> >>> >>> &NumberedInstructions); >>> >>> - >>> /// isLittleEndianEncoding - are instruction bit patterns defined >>> as [0..n]? >>> /// >>> bool isLittleEndianEncoding() const; >>> + >>> + /// supportsHasI1 - does this target understand HasI1 for ADDE >>> and ADDC? >>> + bool supportsHasI1() const; >>> }; >>> >>> /// ComplexPattern - ComplexPattern info, corresponding to the >>> ComplexPattern >>> >>> Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) >>> +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Jun 1 18:27:20 >>> 2009 >>> @@ -670,7 +670,8 @@ >>> HasChain = true; >>> FoldedChains.push_back(std::make_pair(RootName, >>> CInfo.getNumResults())); >>> } >>> - if (NodeHasProperty(Child, SDNPOutFlag, CGP)) { >>> + if (NodeHasProperty(Child, SDNPOutFlag, CGP) || >>> + NodeHasProperty(Child, SDNPOutI1, CGP)) { >>> assert(FoldedFlag.first == "" && FoldedFlag.second == 0 && >>> "Pattern folded multiple nodes which produce flags?"); >>> FoldedFlag = std::make_pair(RootName, >>> @@ -969,6 +970,10 @@ >>> PatternHasProperty(Pattern, SDNPInFlag, CGP); >>> bool NodeHasOutFlag = isRoot && >>> PatternHasProperty(Pattern, SDNPOutFlag, CGP); >>> + bool NodeHasInI1 = isRoot && >>> + PatternHasProperty(Pattern, SDNPInI1, CGP); >>> + bool NodeHasOutI1 = isRoot && >>> + PatternHasProperty(Pattern, SDNPOutI1, CGP); >>> bool NodeHasChain = InstPatNode && >>> PatternHasProperty(InstPatNode, SDNPHasChain, CGP); >>> bool InputHasChain = isRoot && >>> @@ -1054,10 +1059,13 @@ >>> >>> // Emit all the chain and CopyToReg stuff. >>> bool ChainEmitted = NodeHasChain; >>> - if (NodeHasInFlag || HasImpInputs) >>> + // InFlag and InI1 cannot both be set (checked in >>> + // CodeGenDAGPatterns), so use the same variables for both. >>> + if (NodeHasInFlag || HasImpInputs || NodeHasInI1) >>> EmitInFlagSelectCode(Pattern, "N", ChainEmitted, >>> InFlagDecled, ResNodeDecled, true); >>> - if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs) { >>> + if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs || >>> + NodeHasInI1) { >>> if (!InFlagDecled) { >>> emitCode("SDValue InFlag(0, 0);"); >>> InFlagDecled = true; >>> @@ -1113,7 +1121,7 @@ >>> } >>> if (NodeHasChain) >>> Code += ", MVT::Other"; >>> - if (NodeHasOutFlag) >>> + if (NodeHasOutFlag || (NodeHasOutI1 && !CGT.supportsHasI1())) >>> Code += ", MVT::Flag"; >>> >>> // Inputs. >>> @@ -1173,7 +1181,8 @@ >>> } >>> Code += ", &Ops" + utostr(OpsNo) + "[0], Ops" + utostr >>> (OpsNo) + >>> ".size()"; >>> - } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs) >>> + } else if (NodeHasInFlag || NodeHasOptInFlag || >>> HasImpInputs || >>> + NodeHasInI1) >>> AllOps.push_back("InFlag"); >>> >>> unsigned NumOps = AllOps.size(); >>> @@ -1207,7 +1216,7 @@ >>> NodeOps.push_back("Tmp" + utostr(ResNo)); >>> } else { >>> >>> - if (NodeHasOutFlag) { >>> + if (NodeHasOutFlag || NodeHasOutI1) { >>> if (!InFlagDecled) { >>> After.push_back("SDValue InFlag(ResNode, " + >>> utostr(NumResults+NumDstRegs+(unsigned) >>> NodeHasChain) + >>> @@ -1228,13 +1237,15 @@ >>> utostr(NumResults+NumDstRegs) + ")"); >>> } >>> >>> - if (NodeHasOutFlag) { >>> + if (NodeHasOutFlag || NodeHasOutI1) { >>> if (FoldedFlag.first != "") { >>> - ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + >>> ".getNode(), " + >>> + ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + >>> + ".getNode(), " + >>> utostr(FoldedFlag.second) + ")"); >>> ReplaceTos.push_back("InFlag"); >>> } else { >>> - assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP)); >>> + assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP) || >>> + NodeHasProperty(Pattern, SDNPOutI1, CGP)); >>> ReplaceFroms.push_back("SDValue(N.getNode(), " + >>> utostr(NumPatResults + (unsigned) >>> InputHasChain) >>> + ")"); >>> @@ -1251,7 +1262,8 @@ >>> } >>> >>> // User does not expect the instruction would produce a chain! >>> - if ((!InputHasChain && NodeHasChain) && NodeHasOutFlag) { >>> + if ((!InputHasChain && NodeHasChain) && >>> + (NodeHasOutFlag || NodeHasOutI1)) { >>> ; >>> } else if (InputHasChain && !NodeHasChain) { >>> // One of the inner node produces a chain. >>> @@ -1391,6 +1403,8 @@ >>> unsigned OpNo = >>> (unsigned) NodeHasProperty(N, SDNPHasChain, CGP); >>> bool HasInFlag = NodeHasProperty(N, SDNPInFlag, CGP); >>> + bool HasInI1 = NodeHasProperty(N, SDNPInI1, CGP); >>> + bool InFlagDefined = false; >>> for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, + >>> +OpNo) { >>> TreePatternNode *Child = N->getChild(i); >>> if (!Child->isLeaf()) { >>> @@ -1424,21 +1438,41 @@ >>> emitCode("SDValue InFlag(0, 0);"); >>> InFlagDecled = true; >>> } >>> - std::string Decl = (!ResNodeDecled) ? "SDNode *" : >>> ""; >>> - emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + >>> ChainName + >>> + if (HasInI1) { >>> + if (!ResNodeDecled) { >>> + emitCode("SDNode * ResNode;"); >>> + } >>> + if (T.supportsHasI1()) >>> + emitCode("ResNode = CurDAG->getCopyToReg(" + >>> ChainName + >>> + ", " + RootName + ".getDebugLoc()" + >>> + ", " + getEnumName(RVT) + >>> + ", " + getQualifiedName(RR) + >>> + ", " + RootName + utostr(OpNo) + >>> ").getNode();"); >>> + else >>> + emitCode("ResNode = CurDAG->getCopyToReg(" + >>> ChainName + >>> + ", " + RootName + ".getDebugLoc()" + >>> + ", " + getQualifiedName(RR) + >>> + ", " + RootName + utostr(OpNo) + >>> + ", InFlag).getNode();"); >>> + InFlagDefined = true; >>> + } else { >>> + std::string Decl = (!ResNodeDecled) ? "SDNode *" : >>> ""; >>> + emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + >>> ChainName + >>> ", " + RootName + ".getDebugLoc()" + >>> ", " + getQualifiedName(RR) + >>> - ", " + RootName + utostr(OpNo) + ", >>> InFlag).getNode();"); >>> - ResNodeDecled = true; >>> + ", " + RootName + utostr(OpNo) + >>> + ", InFlag).getNode();"); >>> + } >>> emitCode(ChainName + " = SDValue(ResNode, 0);"); >>> emitCode("InFlag = SDValue(ResNode, 1);"); >>> + ResNodeDecled = true; >>> } >>> } >>> } >>> } >>> } >>> >>> - if (HasInFlag) { >>> + if (HasInFlag || (HasInI1 && !InFlagDefined)) { >>> if (!InFlagDecled) { >>> emitCode("SDValue InFlag = " + RootName + >>> ".getOperand(" + utostr(OpNo) + ");"); >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Tue Jun 2 13:23:04 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 2 Jun 2009 11:23:04 -0700 Subject: [llvm-commits] [llvm] r72707 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/X86/ utils/TableGen/ In-Reply-To: <668F172C-93E7-47E8-9B1F-333154602253@apple.com> References: <200906012327.n51NRMqY006632@zion.cs.uiuc.edu> <668F172C-93E7-47E8-9B1F-333154602253@apple.com> Message-ID: <38A54C06-E377-4C3C-8A3B-BB24A194E5A2@apple.com> On Jun 2, 2009, at 11:00 AMPDT, Evan Cheng wrote: > Hi Dale, > > On first glance, the patch mostly looks good. But I don't care for > "supportsHasI1". I would have added ADDC_FLAG / ADDE_FLAG opcodes and > have those use MVT::EFLAGS I assume you mean MVT::Flag > and change ADDC / ADDE to use MVT::i1 to > represent the flag value. Offhand I don't like that, it means a fair amount of parallel but subtly different code in the target-independent parts and calls for changing all non-x86 BEs to use addc_flag. This way, the target- independent code is clean and the complexities are all in TableGen. I agree HasI1 is not a thing of beauty; let me think about it more. This is not far off Eli's suggestion of hijacking UADDO to replace ADDC with i1, what do you think of that? > Thanks, > > Evan > > On Jun 1, 2009, at 4:27 PM, Dale Johannesen wrote: > >> Author: johannes >> Date: Mon Jun 1 18:27:20 2009 >> New Revision: 72707 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=72707&view=rev >> Log: >> Make the implicit inputs and outputs of target-independent >> ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) >> instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust >> all target-independent code to use this format. >> >> Most targets will still produce a Flag-setting target-dependent >> version when selection is done. X86 is converted to use i32 >> instead, which means TableGen needs to produce different code >> in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit >> in xxxInstrInfo, currently set only for X86; in principle this >> is temporary and should go away when all other targets have >> been converted. All relevant X86 instruction patterns are >> modified to represent setting and using EFLAGS explicitly. The >> same can be done on other targets. >> >> The immediate behavior change is that an ADC/ADD pair are no >> longer tightly coupled in the X86 scheduler; they can be >> separated by instructions that don't clobber the flags (MOV). >> I will soon add some peephole optimizations based on using >> other instructions that set the flags to feed into ADC. >> >> >> Modified: >> llvm/trunk/include/llvm/CodeGen/SelectionDAG.h >> llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h >> llvm/trunk/include/llvm/Target/Target.td >> llvm/trunk/include/llvm/Target/TargetSelectionDAG.td >> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp >> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp >> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h >> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp >> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >> llvm/trunk/lib/Target/X86/X86ISelLowering.h >> llvm/trunk/lib/Target/X86/X86Instr64bit.td >> llvm/trunk/lib/Target/X86/X86InstrInfo.td >> llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >> llvm/trunk/utils/TableGen/CodeGenTarget.cpp >> llvm/trunk/utils/TableGen/CodeGenTarget.h >> llvm/trunk/utils/TableGen/DAGISelEmitter.cpp >> >> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) >> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Jun 1 >> 18:27:20 2009 >> @@ -324,6 +324,14 @@ >> return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, >> getRegister(Reg, N.getValueType()), N); >> } >> + // This version of getCopyToReg has the register (and its type) >> as an >> + // explicit output. >> + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, MVT VT, unsigned >> Reg, >> + SDValue N) { >> + SDVTList VTs = getVTList(MVT::Other, VT); >> + SDValue Ops[] = { Chain, getRegister(Reg, VT), N}; >> + return getNode(ISD::CopyToReg, dl, VTs, Ops, 3); >> + } >> >> // This version of the getCopyToReg method takes an extra operand, >> which >> // indicates that there is potentially an incoming flag value (if >> Flag is not >> >> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) >> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Jun 1 >> 18:27:20 2009 >> @@ -242,14 +242,11 @@ >> // remainder result. >> SDIVREM, UDIVREM, >> >> - // CARRY_FALSE - This node is used when folding other nodes, >> - // like ADDC/SUBC, which indicate the carry result is always >> false. >> - CARRY_FALSE, >> - >> // Carry-setting nodes for multiple precision addition and >> subtraction. >> // These nodes take two operands of the same value type, and >> produce two >> // results. The first result is the normal add or sub result, >> the second >> - // result is the carry flag result. >> + // result is the carry flag result (type i1 or whatever it got >> expanded to >> + // for the target, value 0 or 1). >> ADDC, SUBC, >> >> // Carry-using nodes for multiple precision addition and >> subtraction. These >> @@ -258,7 +255,8 @@ >> // produce two results; the normal result of the add or sub, and >> the output >> // carry flag. These nodes both read and write a carry flag to >> allow them >> // to them to be chained together for add and sub of arbitrarily >> large >> - // values. >> + // values. The carry flag (input and output) has type i1 or >> whatever it >> + // got expanded to for the target, and has value 0 or 1. >> ADDE, SUBE, >> >> // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for >> addition. >> >> Modified: llvm/trunk/include/llvm/Target/Target.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/include/llvm/Target/Target.td (original) >> +++ llvm/trunk/include/llvm/Target/Target.td Mon Jun 1 18:27:20 2009 >> @@ -326,6 +326,11 @@ >> // Sparc manual specifies its instructions in the format [31..0] >> (big), while >> // PowerPC specifies them using the format [0..31] (little). >> bit isLittleEndianEncoding = 0; >> + >> + // Targets that can support the HasI1 argument on ADDC and ADDE, >> rather than >> + // Flag, have this bit set. This is transitional and should go >> away when all >> + // targets have been switched over. >> + bit supportsHasI1 = 0; >> } >> >> // Standard Instructions. >> >> Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) >> +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Mon Jun 1 >> 18:27:20 2009 >> @@ -216,6 +216,8 @@ >> def SDNPMayLoad : SDNodeProperty; // May read memory, sets >> 'mayLoad'. >> def SDNPSideEffect : SDNodeProperty; // Sets >> 'HasUnmodelledSideEffects'. >> def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc >> MemOperand >> +def SDNPInI1 : SDNodeProperty; // Read an extra I1 operand >> +def SDNPOutI1 : SDNodeProperty; // Write an extra I1 result >> >> // >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> // Selection DAG Node definitions. >> @@ -289,13 +291,13 @@ >> def xor : SDNode<"ISD::XOR" , SDTIntBinOp, >> [SDNPCommutative, SDNPAssociative]>; >> def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, >> - [SDNPCommutative, SDNPOutFlag]>; >> + [SDNPCommutative, SDNPOutI1]>; >> def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, >> - [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; >> + [SDNPCommutative, SDNPInI1, SDNPOutI1]>; >> def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, >> - [SDNPOutFlag]>; >> + [SDNPOutI1]>; >> def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, >> - [SDNPOutFlag, SDNPInFlag]>; >> + [SDNPInI1, SDNPOutI1]>; >> >> def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; >> def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jun 1 >> 18:27:20 2009 >> @@ -1085,8 +1085,7 @@ >> // If the flag result is dead, turn this into an ADD. >> if (N->hasNUsesOfValue(0, 1)) >> return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, >> N1, N0), >> - DAG.getNode(ISD::CARRY_FALSE, >> - N->getDebugLoc(), MVT::Flag)); >> + DAG.getConstant(0, N->getValueType(1))); >> >> // canonicalize constant to RHS. >> if (N0C && !N1C) >> @@ -1094,10 +1093,9 @@ >> >> // fold (addc x, 0) -> x + no carry out >> if (N1C && N1C->isNullValue()) >> - return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, >> - N->getDebugLoc(), >> MVT::Flag)); >> + return CombineTo(N, N0, DAG.getConstant(0, N1.getValueType())); >> >> - // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share >> no bits. >> + // fold (addc a, b) -> (or a, b), 0 iff a and b share no bits. >> APInt LHSZero, LHSOne; >> APInt RHSZero, RHSOne; >> APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); >> @@ -1111,8 +1109,7 @@ >> if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || >> (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) >> return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, >> N0, N1), >> - DAG.getNode(ISD::CARRY_FALSE, >> - N->getDebugLoc(), MVT::Flag)); >> + DAG.getConstant(0, N1.getValueType())); >> } >> >> return SDValue(); >> @@ -1131,8 +1128,9 @@ >> N1, N0, CarryIn); >> >> // fold (adde x, y, false) -> (addc x, y) >> - if (CarryIn.getOpcode() == ISD::CARRY_FALSE) >> - return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), >> N1, N0); >> + if (ConstantSDNode *N2C = dyn_cast(CarryIn)) >> + if (N2C->getAPIntValue()==0) >> + return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList >> (), N1, N0); >> >> return SDValue(); >> } >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ >> LegalizeIntegerTypes.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp >> (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon >> Jun 1 18:27:20 2009 >> @@ -98,6 +98,10 @@ >> case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); >> break; >> case ISD::SMULO: >> case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; >> + case ISD::ADDC: >> + case ISD::SUBC: Res = PromoteIntRes_ADDSUBC(N, ResNo); >> break; >> + case ISD::ADDE: >> + case ISD::SUBE: Res = PromoteIntRes_ADDSUBE(N, ResNo); >> break; >> >> case ISD::ATOMIC_LOAD_ADD: >> case ISD::ATOMIC_LOAD_SUB: >> @@ -121,6 +125,35 @@ >> SetPromotedInteger(SDValue(N, ResNo), Res); >> } >> >> +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBC(SDNode *N, unsigned >> ResNo) { >> + // Only the carry bit result is expected to be promoted. >> + assert(ResNo == 1 && "Only carry bit result promotion currently >> supported!"); >> + return PromoteIntRes_Overflow(N); >> +} >> + >> +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBE(SDNode *N, unsigned >> ResNo) { >> + // Only the carry bit result is expected to be promoted. >> + assert(ResNo == 1 && "Only carry bit result promotion currently >> supported!"); >> + // This is a ternary operator, so clone a slightly modified >> + // PromoteIntRes_Overflow here (this is the only client). >> + if (ResNo == 1) { >> + // Simply change the return type of the boolean result. >> + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); >> + MVT ValueVTs[] = { N->getValueType(0), NVT }; >> + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N- >>> getOperand(2) }; >> + SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), >> + DAG.getVTList(ValueVTs, 2), Ops, 3); >> + >> + // Modified the sum result - switch anything that used the old >> sum to use >> + // the new one. >> + ReplaceValueWith(SDValue(N, 0), Res); >> + >> + return SDValue(Res.getNode(), 1); >> + } >> + assert(0 && "Do not know how to promote this operator!"); >> + abort(); >> +} >> + >> SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { >> // Sign-extend the new bits, and continue the assertion. >> SDValue Op = SExtPromotedInteger(N->getOperand(0)); >> @@ -419,7 +452,7 @@ >> return Res; >> } >> >> -/// Promote the overflow flag of an overflowing arithmetic node. >> +/// Promote the overflow or carry result of an overflowing >> arithmetic node. >> SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { >> // Simply change the return type of the boolean result. >> MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); >> @@ -666,6 +699,8 @@ >> assert(0 && "Do not know how to promote this operator's >> operand!"); >> abort(); >> >> + case ISD::ADDE: >> + case ISD::SUBE: Res = PromoteIntOp_ADDSUBE(N, OpNo); >> break; >> case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; >> case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; >> case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; >> @@ -743,6 +778,13 @@ >> } >> } >> >> +SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBE(SDNode *N, unsigned >> OpNo) { >> + assert(OpNo == 2 && "Don't know how to promote this operand!"); >> + return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), >> + N->getOperand(1), >> + GetPromotedInteger(N->getOperand >> (2))); >> +} >> + >> SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { >> SDValue Op = GetPromotedInteger(N->getOperand(0)); >> return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N- >>> getValueType(0), Op); >> @@ -1063,7 +1105,7 @@ >> TLI.isOperationLegalOrCustom(ISD::ADDC, >> TLI.getTypeToExpandTo >> (NVT))) { >> // Emit this X << 1 as X+X. >> - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); >> + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); >> SDValue LoOps[2] = { InL, InL }; >> Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); >> SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; >> @@ -1299,7 +1341,7 @@ >> TLI.getTypeToExpandTo(NVT)); >> >> if (hasCarry) { >> - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); >> + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); >> if (N->getOpcode() == ISD::ADD) { >> Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); >> HiOps[2] = Lo.getValue(1); >> @@ -1344,7 +1386,7 @@ >> DebugLoc dl = N->getDebugLoc(); >> GetExpandedInteger(N->getOperand(0), LHSL, LHSH); >> GetExpandedInteger(N->getOperand(1), RHSL, RHSH); >> - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); >> + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); >> SDValue LoOps[2] = { LHSL, RHSL }; >> SDValue HiOps[3] = { LHSH, RHSH }; >> >> @@ -1358,8 +1400,8 @@ >> Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); >> } >> >> - // Legalized the flag result - switch anything that used the old >> flag to >> - // use the new one. >> + // Legalized the second result (carry bit) - switch anything that >> used the >> + // result to use the new one. >> ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); >> } >> >> @@ -1370,7 +1412,7 @@ >> DebugLoc dl = N->getDebugLoc(); >> GetExpandedInteger(N->getOperand(0), LHSL, LHSH); >> GetExpandedInteger(N->getOperand(1), RHSL, RHSH); >> - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); >> + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); >> SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; >> SDValue HiOps[3] = { LHSH, RHSH }; >> >> @@ -1378,8 +1420,8 @@ >> HiOps[2] = Lo.getValue(1); >> Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); >> >> - // Legalized the flag result - switch anything that used the old >> flag to >> - // use the new one. >> + // Legalized the second result (carry bit) - switch anything that >> used the >> + // result to use the new one. >> ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); >> } >> >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Jun 1 >> 18:27:20 2009 >> @@ -242,6 +242,8 @@ >> >> // Integer Result Promotion. >> void PromoteIntegerResult(SDNode *N, unsigned ResNo); >> + SDValue PromoteIntRes_ADDSUBC(SDNode *N, unsigned ResNo); >> + SDValue PromoteIntRes_ADDSUBE(SDNode *N, unsigned ResNo); >> SDValue PromoteIntRes_AssertSext(SDNode *N); >> SDValue PromoteIntRes_AssertZext(SDNode *N); >> SDValue PromoteIntRes_Atomic1(AtomicSDNode *N); >> @@ -278,6 +280,7 @@ >> >> // Integer Operand Promotion. >> bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo); >> + SDValue PromoteIntOp_ADDSUBE(SDNode *N, unsigned OpNo); >> SDValue PromoteIntOp_ANY_EXTEND(SDNode *N); >> SDValue PromoteIntOp_BIT_CONVERT(SDNode *N); >> SDValue PromoteIntOp_BUILD_PAIR(SDNode *N); >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >> (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Mon >> Jun 1 18:27:20 2009 >> @@ -268,6 +268,13 @@ >> unsigned N = Node->getNumOperands(); >> while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) >> --N; >> + // Skip hard registers set as a side effect (i.e. not result 0). >> + while (N && Node->getOperand(N - 1).getOpcode() == ISD::CopyToReg >> && >> + Node->getOperand(N-1).getResNo() != 0 && >> + !TargetRegisterInfo::isVirtualRegister( >> + dyn_cast(Node->getOperand >> (N-1).getOperand(1)) >> + ->getReg())) >> + --N; >> if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) >> --N; // Ignore chain if it exists. >> return N; >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 1 >> 18:27:20 2009 >> @@ -5257,7 +5257,6 @@ >> case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; >> case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; >> case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; >> - case ISD::CARRY_FALSE: return "carry_false"; >> case ISD::ADDC: return "addc"; >> case ISD::ADDE: return "adde"; >> case ISD::SADDO: return "saddo"; >> >> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) >> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jun 1 >> 18:27:20 2009 >> @@ -190,6 +190,28 @@ >> setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); >> } >> >> + // ADDE and SUBE are lowered to local versions that contain >> EFLAGS explicitly. >> + // ADDC and SUBC are lowered to local versions so EFLAGS will be >> an i32 >> + // rather than the Flag used by the generic patterns. >> + setOperationAction(ISD::ADDC , MVT::i8 , Custom); >> + setOperationAction(ISD::ADDC , MVT::i16 , Custom); >> + setOperationAction(ISD::ADDC , MVT::i32 , Custom); >> + setOperationAction(ISD::SUBC , MVT::i8 , Custom); >> + setOperationAction(ISD::SUBC , MVT::i16 , Custom); >> + setOperationAction(ISD::SUBC , MVT::i32 , Custom); >> + setOperationAction(ISD::ADDE , MVT::i8 , Custom); >> + setOperationAction(ISD::ADDE , MVT::i16 , Custom); >> + setOperationAction(ISD::ADDE , MVT::i32 , Custom); >> + setOperationAction(ISD::SUBE , MVT::i8 , Custom); >> + setOperationAction(ISD::SUBE , MVT::i16 , Custom); >> + setOperationAction(ISD::SUBE , MVT::i32 , Custom); >> + if (Subtarget->is64Bit()) { >> + setOperationAction(ISD::ADDC , MVT::i64 , Custom); >> + setOperationAction(ISD::SUBC , MVT::i64 , Custom); >> + setOperationAction(ISD::ADDE , MVT::i64 , Custom); >> + setOperationAction(ISD::SUBE , MVT::i64 , Custom); >> + } >> + >> // Scalar integer divide and remainder are lowered to use >> operations that >> // produce two results, to match the available instructions. This >> exposes >> // the two-result form to trivial CSE, which is able to combine x/ >> y and x%y >> @@ -6475,6 +6497,21 @@ >> return Sum; >> } >> >> +SDValue X86TargetLowering::LowerADDSUBE(SDValue Op, SelectionDAG >> &DAG) { >> + DebugLoc dl = Op.getDebugLoc(); >> + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); >> + return DAG.getNode(Op.getOpcode()==ISD::ADDE ? X86ISD::ADDE : >> X86ISD::SUBE, >> + dl, VTs, Op.getOperand(0), Op.getOperand(1), >> + Op.getOperand(2).getValue(1)); >> +} >> + >> +SDValue X86TargetLowering::LowerADDSUBC(SDValue Op, SelectionDAG >> &DAG) { >> + DebugLoc dl = Op.getDebugLoc(); >> + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); >> + return DAG.getNode(Op.getOpcode()==ISD::ADDC ? X86ISD::ADD : >> X86ISD::SUB, >> + dl, VTs, Op.getOperand(0), Op.getOperand(1)); >> +} >> + >> SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG >> &DAG) { >> MVT T = Op.getValueType(); >> DebugLoc dl = Op.getDebugLoc(); >> @@ -6543,6 +6580,10 @@ >> SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG >> &DAG) { >> switch (Op.getOpcode()) { >> default: assert(0 && "Should not custom lower this!"); >> + case ISD::ADDC: >> + case ISD::SUBC: return LowerADDSUBC(Op,DAG); >> + case ISD::ADDE: >> + case ISD::SUBE: return LowerADDSUBE(Op,DAG); >> case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); >> case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); >> case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); >> @@ -6791,6 +6832,10 @@ >> case X86ISD::INC: return "X86ISD::INC"; >> case X86ISD::DEC: return "X86ISD::DEC"; >> case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; >> + case X86ISD::ADDE: return "X86ISD::ADDE"; >> + case X86ISD::SUBE: return "X86ISD::SUBE"; >> + case X86ISD::ADDC: return "X86ISD::ADDC"; >> + case X86ISD::SUBC: return "X86ISD::SUBC"; >> } >> } >> >> >> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) >> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Jun 1 18:27:20 >> 2009 >> @@ -243,6 +243,14 @@ >> ADD, SUB, SMUL, UMUL, >> INC, DEC, >> >> + // ADDC, SUBC - Arithmetic operations setting carry bit. The >> normal >> + // arithmetic operations do this, but they represent it as >> Flag, and >> + // we want the i32 EFLAGS register here. >> + ADDC, SUBC, >> + >> + // ADDE, SUBE - Arithmetic operations with extra FLAGS >> (EFLAGS) inputs. >> + ADDE, SUBE, >> + >> // MUL_IMM - X86 specific multiply by immediate. >> MUL_IMM >> }; >> @@ -576,7 +584,9 @@ >> >> std::pair FP_TO_INTHelper(SDValue Op, >> SelectionDAG &DAG, >> bool isSigned); >> - >> + >> + SDValue LowerADDSUBC(SDValue Op, SelectionDAG &DAG); >> + SDValue LowerADDSUBE(SDValue Op, SelectionDAG &DAG); >> SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); >> SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); >> SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); >> >> Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) >> +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Mon Jun 1 18:27:20 >> 2009 >> @@ -383,31 +383,52 @@ >> let Uses = [EFLAGS] in { >> let isTwoAddress = 1 in { >> let isCommutable = 1 in >> -def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins >> GR64:$src1, GR64:$src2), >> +def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), >> + (ins GR64:$src1, GR64:$src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>; >> + [(set GR64:$dst, >> + (X86adde_flag GR64:$src1, GR64:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> >> -def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins >> GR64:$src1, i64mem:$src2), >> +def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), >> + (ins GR64:$src1, i64mem:$src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (adde GR64:$src1, (load addr: >> $src2)))]>; >> + [(set GR64:$dst, >> + (X86adde_flag GR64:$src1, (load addr: >> $src2), EFLAGS)), >> + (implicit EFLAGS)]>; >> >> -def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, >> i64i8imm:$src2), >> +def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), >> + (ins GR64:$src1, i64i8imm:$src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (adde GR64:$src1, >> i64immSExt8:$src2))]>; >> -def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins >> GR64:$src1, i64i32imm:$src2), >> + [(set GR64:$dst, >> + (X86adde_flag GR64:$src1, >> i64immSExt8:$src2, EFLAGS)), >> + (implicit EFLAGS)]>; >> +def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), >> + (ins GR64:$src1, i64i32imm: >> $src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (adde GR64:$src1, >> i64immSExt32:$src2))]>; >> + [(set GR64:$dst, >> + (X86adde_flag GR64:$src1, >> i64immSExt32:$src2, >> + EFLAGS)), >> + (implicit EFLAGS)]>; >> } // isTwoAddress >> >> def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, >> GR64:$src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), GR64:$src2), addr: >> $dst)]>; >> + [(store (X86adde_flag (load addr:$dst), >> GR64:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm : >> $src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), >> i64immSExt8:$src2), addr:$dst)]>; >> + [(store (X86adde_flag (load addr:$dst), >> i64immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, >> i64i32imm:$src2), >> "adc{q}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), >> i64immSExt8:$src2), addr:$dst)]>; >> + [(store (X86adde_flag (load addr:$dst), >> i64immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> } // Uses = [EFLAGS] >> >> let isTwoAddress = 1 in { >> @@ -456,31 +477,52 @@ >> >> let Uses = [EFLAGS] in { >> let isTwoAddress = 1 in { >> -def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins >> GR64:$src1, GR64:$src2), >> +def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), >> + (ins GR64:$src1, GR64:$src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))] >>> ; >> + [(set GR64:$dst, >> + (X86sube_flag GR64:$src1, GR64:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> >> -def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins >> GR64:$src1, i64mem:$src2), >> +def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), >> + (ins GR64:$src1, i64mem:$src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (sube GR64:$src1, (load addr: >> $src2)))]>; >> + [(set GR64:$dst, >> + (X86sube_flag GR64:$src1, (load addr: >> $src2), EFLAGS)), >> + (implicit EFLAGS)]>; >> >> -def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, >> i64i8imm:$src2), >> +def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), >> + (ins GR64:$src1, i64i8imm:$src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (sube GR64:$src1, >> i64immSExt8:$src2))]>; >> -def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins >> GR64:$src1, i64i32imm:$src2), >> + [(set GR64:$dst, >> + (X86sube_flag GR64:$src1, >> i64immSExt8:$src2, EFLAGS)), >> + (implicit EFLAGS)]>; >> +def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), >> + (ins GR64:$src1, i64i32imm: >> $src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(set GR64:$dst, (sube GR64:$src1, >> i64immSExt32:$src2))]>; >> + [(set GR64:$dst, >> + (X86sube_flag GR64:$src1, >> i64immSExt32:$src2, >> + EFLAGS)), >> + (implicit EFLAGS)]>; >> } // isTwoAddress >> >> def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, >> GR64:$src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), GR64:$src2), addr: >> $dst)]>; >> + [(store (X86sube_flag (load addr:$dst), >> GR64:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm : >> $src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), i64immSExt8:$src2), >> addr:$dst)]>; >> + [(store (X86sube_flag (load addr:$dst), >> i64immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, >> i64i32imm:$src2), >> "sbb{q}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), i64immSExt32:$src2), >> addr:$dst)]>; >> + [(store (X86sube_flag (load addr:$dst), >> i64immSExt32:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> } // Uses = [EFLAGS] >> } // Defs = [EFLAGS] >> >> >> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) >> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Jun 1 18:27:20 >> 2009 >> @@ -34,6 +34,11 @@ >> [SDTCisSameAs<0, 1>, >> SDTCisSameAs<0, 2>, >> SDTCisInt<0>]>; >> +// Unary and binary operators that both read and write EFLAGS as a >> side-effect. >> +def SDTBinaryArithRWFlags : SDTypeProfile<1, 3, >> + [SDTCisInt<0>, SDTCisSameAs<0, 1>, >> + SDTCisSameAs<0, 2>, SDTCisVT<3, >> i32>]>; >> + >> def SDTX86BrCond : SDTypeProfile<0, 3, >> [SDTCisVT<0, OtherVT>, >> SDTCisVT<1, i8>, SDTCisVT<2, i32>] >>> ; >> @@ -156,6 +161,8 @@ >> def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>; >> def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; >> def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; >> +def X86adde_flag : SDNode<"X86ISD::ADDE", SDTBinaryArithRWFlags, >> [SDNPInI1]>; >> +def X86sube_flag : SDNode<"X86ISD::SUBE", SDTBinaryArithRWFlags, >> [SDNPInI1]>; >> >> def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; >> >> @@ -2274,81 +2281,127 @@ >> >> let Uses = [EFLAGS] in { >> let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y >> -def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, >> GR8:$src2), >> +def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), >> + (ins GR8:$src1, GR8:$src2), >> "adc{b}\t{$src2, $dst|$dst, $src2}", >> - [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>; >> + [(set GR8:$dst, (X86adde_flag GR8:$src1, >> GR8:$src2, EFLAGS)), >> + (implicit EFLAGS)]>; >> def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst), >> (ins GR16:$src1, GR16:$src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, >> OpSize; >> + [(set GR16:$dst, >> + (X86adde_flag GR16:$src1, GR16:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>, >> + OpSize; >> def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), >> (ins GR32:$src1, GR32:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; >> + [(set GR32:$dst, >> + (X86adde_flag GR32:$src1, GR32:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> } >> def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst), >> (ins GR8:$src1, i8mem:$src2), >> "adc{b}\t{$src2, $dst|$dst, $src2}", >> - [(set GR8:$dst, (adde GR8:$src1, (load addr: >> $src2)))]>; >> + [(set GR8:$dst, >> + (X86adde_flag GR8:$src1, (load addr:$src2), >> EFLAGS)), >> + (implicit EFLAGS)]>; >> def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst), >> (ins GR16:$src1, i16mem:$src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (adde GR16:$src1, (load addr: >> $src2)))]>, >> + [(set GR16:$dst, >> + (X86adde_flag GR16:$src1, (load addr:$src2), >> EFLAGS)), >> + (implicit EFLAGS)]>, >> OpSize; >> def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), >> (ins GR32:$src1, i32mem:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (adde GR32:$src1, (load addr: >> $src2)))]>; >> -def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, >> i8imm:$src2), >> + [(set GR32:$dst, >> + (X86adde_flag GR32:$src1, (load addr:$src2), >> EFLAGS)), >> + (implicit EFLAGS)]>; >> +def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), >> + (ins GR8:$src1, i8imm:$src2), >> "adc{b}\t{$src2, $dst|$dst, $src2}", >> - [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>; >> + [(set GR8:$dst, >> + (X86adde_flag GR8:$src1, imm:$src2, EFLAGS)), >> + (implicit EFLAGS)]>; >> def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst), >> (ins GR16:$src1, i16imm:$src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, >> OpSize; >> + [(set GR16:$dst, >> + (X86adde_flag GR16:$src1, imm:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>, OpSize; >> def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst), >> (ins GR16:$src1, i16i8imm:$src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (adde GR16:$src1, >> i16immSExt8:$src2))]>, >> - OpSize; >> + [(set GR16:$dst, >> + (X86adde_flag GR16:$src1, i16immSExt8:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>, OpSize; >> def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), >> (ins GR32:$src1, i32imm:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; >> + [(set GR32:$dst, >> + (X86adde_flag GR32:$src1, imm:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), >> (ins GR32:$src1, i32i8imm:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (adde GR32:$src1, >> i32immSExt8:$src2))]>; >> + [(set GR32:$dst, >> + (X86adde_flag GR32:$src1, i32immSExt8:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> >> let isTwoAddress = 0 in { >> - def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, >> GR8:$src2), >> + def ADC8mr : I<0x10, MRMDestMem, (outs), >> + (ins i8mem:$dst, GR8:$src2), >> "adc{b}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), GR8:$src2), addr: >> $dst)]>; >> - def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, >> GR16:$src2), >> + [(store (X86adde_flag (load addr:$dst), >> GR8:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> + def ADC16mr : I<0x11, MRMDestMem, (outs), >> + (ins i16mem:$dst, GR16:$src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), GR16:$src2), >> addr:$dst)]>, >> - OpSize; >> - def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, >> GR32:$src2), >> + [(store (X86adde_flag (load addr:$dst), >> GR16:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>, OpSize; >> + def ADC32mr : I<0x11, MRMDestMem, (outs), >> + (ins i32mem:$dst, GR32:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), GR32:$src2), >> addr:$dst)]>; >> - def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm: >> $src2), >> + [(store (X86adde_flag (load addr:$dst), >> GR32:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> + def ADC8mi : Ii8<0x80, MRM2m, (outs), >> + (ins i8mem:$dst, i8imm:$src2), >> "adc{b}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (loadi8 addr:$dst), imm:$src2), >> addr:$dst)]>; >> - def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm: >> $src2), >> + [(store (X86adde_flag (loadi8 addr:$dst), imm: >> $src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> + def ADC16mi : Ii16<0x81, MRM2m, (outs), >> + (ins i16mem:$dst, i16imm:$src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (loadi16 addr:$dst), imm:$src2), >> addr:$dst)]>, >> - OpSize; >> - def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, >> i16i8imm :$src2), >> + [(store (X86adde_flag (loadi16 addr:$dst), imm: >> $src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>, OpSize; >> + def ADC16mi8 : Ii8<0x83, MRM2m, (outs), >> + (ins i16mem:$dst, i16i8imm : >> $src2), >> "adc{w}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), i16immSExt8:$src2), >> addr:$dst)]>, >> - OpSize; >> - def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm: >> $src2), >> + [(store (X86adde_flag (load addr:$dst), >> i16immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>, OpSize; >> + def ADC32mi : Ii32<0x81, MRM2m, (outs), >> + (ins i32mem:$dst, i32imm:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (loadi32 addr:$dst), imm:$src2), >> addr:$dst)]>; >> - def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, >> i32i8imm :$src2), >> + [(store (X86adde_flag (loadi32 addr:$dst), imm: >> $src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> + def ADC32mi8 : Ii8<0x83, MRM2m, (outs), >> + (ins i32mem:$dst, i32i8imm:$src2), >> "adc{l}\t{$src2, $dst|$dst, $src2}", >> - [(store (adde (load addr:$dst), i32immSExt8:$src2), >> addr:$dst)]>; >> -} >> + [(store (X86adde_flag (load addr:$dst), >> i32immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> + } >> } // Uses = [EFLAGS] >> >> // Register-Register Subtraction >> @@ -2453,77 +2506,115 @@ >> def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst), >> (ins GR8:$src1, GR8:$src2), >> "sbb{b}\t{$src2, $dst|$dst, $src2}", >> - [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>; >> + [(set GR8:$dst, (X86sube_flag GR8:$src1, >> GR8:$src2, EFLAGS)), >> + (implicit EFLAGS)]>; >> def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst), >> (ins GR16:$src1, GR16:$src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, >> OpSize; >> + [(set GR16:$dst, >> + (X86sube_flag GR16:$src1, GR16:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>, OpSize; >> def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), >> (ins GR32:$src1, GR32:$src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; >> + [(set GR32:$dst, >> + (X86sube_flag GR32:$src1, GR32:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> >> let isTwoAddress = 0 in { >> def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, >> GR8:$src2), >> "sbb{b}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), GR8:$src2), addr: >> $dst)]>; >> + [(store (X86sube_flag (load addr:$dst), >> GR8:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, >> GR16:$src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), GR16:$src2), >> addr:$dst)]>, >> + [(store (X86sube_flag (load addr:$dst), >> GR16:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>, >> OpSize; >> def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, >> GR32:$src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), GR32:$src2), >> addr:$dst)]>; >> + [(store (X86sube_flag (load addr:$dst), >> GR32:$src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm: >> $src2), >> "sbb{b}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (loadi8 addr:$dst), imm:$src2), >> addr:$dst)]>; >> + [(store (X86sube_flag (loadi8 addr:$dst), imm: >> $src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm: >> $src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (loadi16 addr:$dst), imm:$src2), >> addr:$dst)]>, >> + [(store (X86sube_flag (loadi16 addr:$dst), imm: >> $src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>, >> OpSize; >> def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, >> i16i8imm :$src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), i16immSExt8:$src2), >> addr:$dst)]>, >> + [(store (X86sube_flag (load addr:$dst), >> i16immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>, >> OpSize; >> def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm: >> $src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (loadi32 addr:$dst), imm:$src2), >> addr:$dst)]>; >> + [(store (X86sube_flag (loadi32 addr:$dst), imm: >> $src2, EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, >> i32i8imm :$src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(store (sube (load addr:$dst), i32immSExt8:$src2), >> addr:$dst)]>; >> + [(store (X86sube_flag (load addr:$dst), >> i32immSExt8:$src2, >> + EFLAGS), >> + addr:$dst), >> + (implicit EFLAGS)]>; >> } >> def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, >> i8mem:$src2), >> "sbb{b}\t{$src2, $dst|$dst, $src2}", >> - [(set GR8:$dst, (sube GR8:$src1, (load addr: >> $src2)))]>; >> + [(set GR8:$dst, >> + (X86sube_flag GR8:$src1, (load addr: >> $src2), EFLAGS)), >> + (implicit EFLAGS)]>; >> def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst), >> (ins GR16:$src1, i16mem:$src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (sube GR16:$src1, (load addr: >> $src2)))]>, >> + [(set GR16:$dst, >> + (X86sube_flag GR16:$src1, (load addr: >> $src2), EFLAGS)), >> + (implicit EFLAGS)]>, >> OpSize; >> def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), >> (ins GR32:$src1, i32mem:$src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (sube GR32:$src1, (load addr: >> $src2)))]>; >> + [(set GR32:$dst, >> + (X86sube_flag GR32:$src1, (load addr: >> $src2), EFLAGS)), >> + (implicit EFLAGS)]>; >> def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, >> i8imm:$src2), >> "sbb{b}\t{$src2, $dst|$dst, $src2}", >> - [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>; >> + [(set GR8:$dst, >> + (X86sube_flag GR8:$src1, imm:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst), >> (ins GR16:$src1, i16imm:$src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (sube GR16:$src1, imm:$src2))] >>> , OpSize; >> + [(set GR16:$dst, >> + (X86sube_flag GR16:$src1, imm:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>, OpSize; >> def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst), >> (ins GR16:$src1, i16i8imm:$src2), >> "sbb{w}\t{$src2, $dst|$dst, $src2}", >> - [(set GR16:$dst, (sube GR16:$src1, >> i16immSExt8:$src2))]>, >> - OpSize; >> + [(set GR16:$dst, >> + (X86sube_flag GR16:$src1, >> i16immSExt8:$src2, EFLAGS)), >> + (implicit EFLAGS)]>, OpSize; >> def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), >> (ins GR32:$src1, i32imm:$src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (sube GR32:$src1, imm: >> $src2))]>; >> + [(set GR32:$dst, >> + (X86sube_flag GR32:$src1, imm:$src2, >> EFLAGS)), >> + (implicit EFLAGS)]>; >> def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), >> (ins GR32:$src1, i32i8imm:$src2), >> "sbb{l}\t{$src2, $dst|$dst, $src2}", >> - [(set GR32:$dst, (sube GR32:$src1, >> i32immSExt8:$src2))]>; >> + [(set GR32:$dst, >> + (X86sube_flag GR32:$src1, >> i32immSExt8:$src2, EFLAGS)), >> + (implicit EFLAGS)]>; >> } // Uses = [EFLAGS] >> } // Defs = [EFLAGS] >> >> >> Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) >> +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Mon Jun 1 >> 18:27:20 2009 >> @@ -399,9 +399,13 @@ >> } else if (PropList[i]->getName() == "SDNPHasChain") { >> Properties |= 1 << SDNPHasChain; >> } else if (PropList[i]->getName() == "SDNPOutFlag") { >> - Properties |= 1 << SDNPOutFlag; >> + Properties |= 1 << SDNPOutFlag; >> + assert(!(Properties & (1<> + "Can't handle OutFlag and OutI1"); >> } else if (PropList[i]->getName() == "SDNPInFlag") { >> Properties |= 1 << SDNPInFlag; >> + assert(!(Properties & (1<> + "Can't handle InFlag and InI1"); >> } else if (PropList[i]->getName() == "SDNPOptInFlag") { >> Properties |= 1 << SDNPOptInFlag; >> } else if (PropList[i]->getName() == "SDNPMayStore") { >> @@ -412,6 +416,14 @@ >> Properties |= 1 << SDNPSideEffect; >> } else if (PropList[i]->getName() == "SDNPMemOperand") { >> Properties |= 1 << SDNPMemOperand; >> + } else if (PropList[i]->getName() == "SDNPInI1") { >> + Properties |= 1 << SDNPInI1; >> + assert(!(Properties & (1<> + "Can't handle InFlag and InI1"); >> + } else if (PropList[i]->getName() == "SDNPOutI1") { >> + Properties |= 1 << SDNPOutI1; >> + assert(!(Properties & (1<> + "Can't handle OutFlag and OutI1"); >> } else { >> cerr << "Unknown SD Node property '" << PropList[i]->getName() >> << "' on node '" << R->getName() << "'!\n"; >> >> Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) >> +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Jun 1 18:27:20 >> 2009 >> @@ -385,6 +385,13 @@ >> return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); >> } >> >> +/// supportsHasI1 - Return whether this target supports the >> implicit I1, >> +/// rather than Flags, for ADDC/ADDE >> +/// >> +bool CodeGenTarget::supportsHasI1() const { >> + return getInstructionSet()->getValueAsBit("supportsHasI1"); >> +} >> + >> // >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> // ComplexPattern implementation >> // >> >> Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/utils/TableGen/CodeGenTarget.h (original) >> +++ llvm/trunk/utils/TableGen/CodeGenTarget.h Mon Jun 1 18:27:20 >> 2009 >> @@ -43,7 +43,9 @@ >> SDNPMayLoad, >> SDNPMayStore, >> SDNPSideEffect, >> - SDNPMemOperand >> + SDNPMemOperand, >> + SDNPInI1, >> + SDNPOutI1 >> }; >> >> // ComplexPattern attributes. >> @@ -209,10 +211,12 @@ >> void getInstructionsByEnumValue(std::vector> CodeGenInstruction*> >> >> &NumberedInstructions); >> >> - >> /// isLittleEndianEncoding - are instruction bit patterns defined >> as [0..n]? >> /// >> bool isLittleEndianEncoding() const; >> + >> + /// supportsHasI1 - does this target understand HasI1 for ADDE >> and ADDC? >> + bool supportsHasI1() const; >> }; >> >> /// ComplexPattern - ComplexPattern info, corresponding to the >> ComplexPattern >> >> Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=72707&r1=72706&r2=72707&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) >> +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Jun 1 18:27:20 >> 2009 >> @@ -670,7 +670,8 @@ >> HasChain = true; >> FoldedChains.push_back(std::make_pair(RootName, >> CInfo.getNumResults())); >> } >> - if (NodeHasProperty(Child, SDNPOutFlag, CGP)) { >> + if (NodeHasProperty(Child, SDNPOutFlag, CGP) || >> + NodeHasProperty(Child, SDNPOutI1, CGP)) { >> assert(FoldedFlag.first == "" && FoldedFlag.second == 0 && >> "Pattern folded multiple nodes which produce flags?"); >> FoldedFlag = std::make_pair(RootName, >> @@ -969,6 +970,10 @@ >> PatternHasProperty(Pattern, SDNPInFlag, CGP); >> bool NodeHasOutFlag = isRoot && >> PatternHasProperty(Pattern, SDNPOutFlag, CGP); >> + bool NodeHasInI1 = isRoot && >> + PatternHasProperty(Pattern, SDNPInI1, CGP); >> + bool NodeHasOutI1 = isRoot && >> + PatternHasProperty(Pattern, SDNPOutI1, CGP); >> bool NodeHasChain = InstPatNode && >> PatternHasProperty(InstPatNode, SDNPHasChain, CGP); >> bool InputHasChain = isRoot && >> @@ -1054,10 +1059,13 @@ >> >> // Emit all the chain and CopyToReg stuff. >> bool ChainEmitted = NodeHasChain; >> - if (NodeHasInFlag || HasImpInputs) >> + // InFlag and InI1 cannot both be set (checked in >> + // CodeGenDAGPatterns), so use the same variables for both. >> + if (NodeHasInFlag || HasImpInputs || NodeHasInI1) >> EmitInFlagSelectCode(Pattern, "N", ChainEmitted, >> InFlagDecled, ResNodeDecled, true); >> - if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs) { >> + if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs || >> + NodeHasInI1) { >> if (!InFlagDecled) { >> emitCode("SDValue InFlag(0, 0);"); >> InFlagDecled = true; >> @@ -1113,7 +1121,7 @@ >> } >> if (NodeHasChain) >> Code += ", MVT::Other"; >> - if (NodeHasOutFlag) >> + if (NodeHasOutFlag || (NodeHasOutI1 && !CGT.supportsHasI1())) >> Code += ", MVT::Flag"; >> >> // Inputs. >> @@ -1173,7 +1181,8 @@ >> } >> Code += ", &Ops" + utostr(OpsNo) + "[0], Ops" + utostr >> (OpsNo) + >> ".size()"; >> - } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs) >> + } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs >> || >> + NodeHasInI1) >> AllOps.push_back("InFlag"); >> >> unsigned NumOps = AllOps.size(); >> @@ -1207,7 +1216,7 @@ >> NodeOps.push_back("Tmp" + utostr(ResNo)); >> } else { >> >> - if (NodeHasOutFlag) { >> + if (NodeHasOutFlag || NodeHasOutI1) { >> if (!InFlagDecled) { >> After.push_back("SDValue InFlag(ResNode, " + >> utostr(NumResults+NumDstRegs+(unsigned) >> NodeHasChain) + >> @@ -1228,13 +1237,15 @@ >> utostr(NumResults+NumDstRegs) + ")"); >> } >> >> - if (NodeHasOutFlag) { >> + if (NodeHasOutFlag || NodeHasOutI1) { >> if (FoldedFlag.first != "") { >> - ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + >> ".getNode(), " + >> + ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + >> + ".getNode(), " + >> utostr(FoldedFlag.second) + ")"); >> ReplaceTos.push_back("InFlag"); >> } else { >> - assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP)); >> + assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP) || >> + NodeHasProperty(Pattern, SDNPOutI1, CGP)); >> ReplaceFroms.push_back("SDValue(N.getNode(), " + >> utostr(NumPatResults + (unsigned) >> InputHasChain) >> + ")"); >> @@ -1251,7 +1262,8 @@ >> } >> >> // User does not expect the instruction would produce a chain! >> - if ((!InputHasChain && NodeHasChain) && NodeHasOutFlag) { >> + if ((!InputHasChain && NodeHasChain) && >> + (NodeHasOutFlag || NodeHasOutI1)) { >> ; >> } else if (InputHasChain && !NodeHasChain) { >> // One of the inner node produces a chain. >> @@ -1391,6 +1403,8 @@ >> unsigned OpNo = >> (unsigned) NodeHasProperty(N, SDNPHasChain, CGP); >> bool HasInFlag = NodeHasProperty(N, SDNPInFlag, CGP); >> + bool HasInI1 = NodeHasProperty(N, SDNPInI1, CGP); >> + bool InFlagDefined = false; >> for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, + >> +OpNo) { >> TreePatternNode *Child = N->getChild(i); >> if (!Child->isLeaf()) { >> @@ -1424,21 +1438,41 @@ >> emitCode("SDValue InFlag(0, 0);"); >> InFlagDecled = true; >> } >> - std::string Decl = (!ResNodeDecled) ? "SDNode *" : ""; >> - emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + >> ChainName + >> + if (HasInI1) { >> + if (!ResNodeDecled) { >> + emitCode("SDNode * ResNode;"); >> + } >> + if (T.supportsHasI1()) >> + emitCode("ResNode = CurDAG->getCopyToReg(" + >> ChainName + >> + ", " + RootName + ".getDebugLoc()" + >> + ", " + getEnumName(RVT) + >> + ", " + getQualifiedName(RR) + >> + ", " + RootName + utostr(OpNo) + >> ").getNode();"); >> + else >> + emitCode("ResNode = CurDAG->getCopyToReg(" + >> ChainName + >> + ", " + RootName + ".getDebugLoc()" + >> + ", " + getQualifiedName(RR) + >> + ", " + RootName + utostr(OpNo) + >> + ", InFlag).getNode();"); >> + InFlagDefined = true; >> + } else { >> + std::string Decl = (!ResNodeDecled) ? "SDNode *" : >> ""; >> + emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + >> ChainName + >> ", " + RootName + ".getDebugLoc()" + >> ", " + getQualifiedName(RR) + >> - ", " + RootName + utostr(OpNo) + ", >> InFlag).getNode();"); >> - ResNodeDecled = true; >> + ", " + RootName + utostr(OpNo) + >> + ", InFlag).getNode();"); >> + } >> emitCode(ChainName + " = SDValue(ResNode, 0);"); >> emitCode("InFlag = SDValue(ResNode, 1);"); >> + ResNodeDecled = true; >> } >> } >> } >> } >> } >> >> - if (HasInFlag) { >> + if (HasInFlag || (HasInI1 && !InFlagDefined)) { >> if (!InFlagDecled) { >> emitCode("SDValue InFlag = " + RootName + >> ".getOperand(" + utostr(OpNo) + ");"); >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Tue Jun 2 13:23:07 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 02 Jun 2009 20:23:07 +0200 Subject: [llvm-commits] [llvm] r72700 - in /llvm/trunk/tools/lto: LTOModule.cpp LTOModule.h In-Reply-To: <352a1fb20906021004va2266dak4fd12227c4469f65@mail.gmail.com> References: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> <4A24FDC1.7010907@free.fr> <352a1fb20906021004va2266dak4fd12227c4469f65@mail.gmail.com> Message-ID: <4A256E0B.8030202@free.fr> Devang Patel wrote: > On Tue, Jun 2, 2009 at 3:24 AM, Duncan Sands wrote: >> What if someone links .bc files together by hand using llvm-link? >> > > Why do you think it won't work without this LTOModule patch ? Too many negatives... not sure what you are asking. Ciao, Duncan. From eli.friedman at gmail.com Tue Jun 2 13:31:35 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 2 Jun 2009 11:31:35 -0700 Subject: [llvm-commits] [llvm] r72700 - in /llvm/trunk/tools/lto: LTOModule.cpp LTOModule.h In-Reply-To: <4A256E0B.8030202@free.fr> References: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> <4A24FDC1.7010907@free.fr> <352a1fb20906021004va2266dak4fd12227c4469f65@mail.gmail.com> <4A256E0B.8030202@free.fr> Message-ID: On Tue, Jun 2, 2009 at 11:23 AM, Duncan Sands wrote: > Devang Patel wrote: >> On Tue, Jun 2, 2009 at 3:24 AM, Duncan Sands wrote: >>> What if someone links .bc files together by hand using llvm-link? >>> >> >> Why do you think it won't work without this LTOModule patch ? > > Too many negatives... not sure what you are asking. >From the description, I think this is an issue of emulating some funny linker hacks in LTO mode rather than an issue of actual linking. So whether two files are linked with llvm-link has no effect on the issue. -Eli From baldrick at free.fr Tue Jun 2 14:04:51 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 02 Jun 2009 21:04:51 +0200 Subject: [llvm-commits] [llvm] r72700 - in /llvm/trunk/tools/lto: LTOModule.cpp LTOModule.h In-Reply-To: References: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> <4A24FDC1.7010907@free.fr> <352a1fb20906021004va2266dak4fd12227c4469f65@mail.gmail.com> <4A256E0B.8030202@free.fr> Message-ID: <4A2577D3.30302@free.fr> >>From the description, I think this is an issue of emulating some funny > linker hacks in LTO mode rather than an issue of actual linking. So > whether two files are linked with llvm-link has no effect on the > issue. Isn't LTO supposed to be more or less equivalent to: link using llvm-link, optimize using opt, codegen using llc? If so, that means that any hack needed for LTO should also be needed by one of llvm-link, opt or llc... Ciao, Duncan. From evan.cheng at apple.com Tue Jun 2 15:09:32 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 02 Jun 2009 20:09:32 -0000 Subject: [llvm-commits] [llvm] r72734 - in /llvm/trunk: lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/abi-isel.ll test/CodeGen/X86/ga-offset.ll test/CodeGen/X86/x86-store-gv-addr.ll Message-ID: <200906022009.n52K9WXn029696@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jun 2 15:09:31 2009 New Revision: 72734 URL: http://llvm.org/viewvc/llvm-project?rev=72734&view=rev Log: On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit. Added: llvm/trunk/test/CodeGen/X86/x86-store-gv-addr.ll Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/CodeGen/X86/abi-isel.ll llvm/trunk/test/CodeGen/X86/ga-offset.ll Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=72734&r1=72733&r2=72734&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Jun 2 15:09:31 2009 @@ -1399,16 +1399,16 @@ def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), (MOV64mi32 addr:$dst, tconstpool:$src)>, - Requires<[SmallCode, IsStatic]>; + Requires<[SmallCode, IsStatic, IsNotDarwin]>; def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), (MOV64mi32 addr:$dst, tjumptable:$src)>, - Requires<[SmallCode, IsStatic]>; + Requires<[SmallCode, IsStatic, IsNotDarwin]>; def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), (MOV64mi32 addr:$dst, tglobaladdr:$src)>, - Requires<[SmallCode, IsStatic]>; + Requires<[SmallCode, IsStatic, IsNotDarwin]>; def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), (MOV64mi32 addr:$dst, texternalsym:$src)>, - Requires<[SmallCode, IsStatic]>; + Requires<[SmallCode, IsStatic, IsNotDarwin]>; // Calls // Direct PC relative function call for small code model. 32-bit displacement Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=72734&r1=72733&r2=72734&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Jun 2 15:09:31 2009 @@ -237,6 +237,7 @@ def OptForSpeed : Predicate<"!OptForSize">; def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; +def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; //===----------------------------------------------------------------------===// // X86 Instruction Format Definitions. Modified: llvm/trunk/test/CodeGen/X86/abi-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/abi-isel.ll?rev=72734&r1=72733&r2=72734&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/abi-isel.ll (original) +++ llvm/trunk/test/CodeGen/X86/abi-isel.ll Tue Jun 2 15:09:31 2009 @@ -146,7 +146,7 @@ ; RUN: grep movl %t | count 91 ; RUN: not grep addl %t ; RUN: not grep subl %t -; RUN: grep leaq %t | count 70 +; RUN: grep leaq %t | count 81 ; RUN: grep movq %t | count 56 ; RUN: grep addq %t | count 20 ; RUN: grep subq %t | count 14 @@ -160,7 +160,7 @@ ; RUN: not grep @PLT %t ; RUN: not grep @PLTOFF %t ; RUN: grep {call \\\*} %t | count 10 -; RUN: grep {%rip} %t | count 139 +; RUN: grep {%rip} %t | count 150 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small > %t ; RUN: not grep leal %t ; RUN: grep movl %t | count 95 Modified: llvm/trunk/test/CodeGen/X86/ga-offset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ga-offset.ll?rev=72734&r1=72733&r2=72734&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/ga-offset.ll (original) +++ llvm/trunk/test/CodeGen/X86/ga-offset.ll Tue Jun 2 15:09:31 2009 @@ -2,7 +2,7 @@ ; RUN: not grep lea %t ; RUN: not grep add %t ; RUN: grep mov %t | count 1 -; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=static > %t +; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu -relocation-model=static > %t ; RUN: not grep lea %t ; RUN: not grep add %t ; RUN: grep mov %t | count 1 Added: llvm/trunk/test/CodeGen/X86/x86-store-gv-addr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-store-gv-addr.ll?rev=72734&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/x86-store-gv-addr.ll (added) +++ llvm/trunk/test/CodeGen/X86/x86-store-gv-addr.ll Tue Jun 2 15:09:31 2009 @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=static | grep lea +; RUN: llvm-as < %s | llc -mtriple=x86_64-pc-linux-gnu -relocation-model=static | not grep lea + + at v = external global i32, align 8 + at v_addr = external global i32*, align 8 + +define void @t() nounwind optsize { + store i32* @v, i32** @v_addr, align 8 + unreachable +} From lhames at gmail.com Tue Jun 2 15:30:04 2009 From: lhames at gmail.com (Lang Hames) Date: Tue, 02 Jun 2009 20:30:04 -0000 Subject: [llvm-commits] [llvm] r72735 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Message-ID: <200906022030.n52KU4Kk030315@zion.cs.uiuc.edu> Author: lhames Date: Tue Jun 2 15:30:03 2009 New Revision: 72735 URL: http://llvm.org/viewvc/llvm-project?rev=72735&view=rev Log: Fixed warning, removed some temporary validation code that snuck in during my last commit. Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=72735&r1=72734&r2=72735&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Tue Jun 2 15:30:03 2009 @@ -312,93 +312,6 @@ static RegisterPass X("linearscan-regalloc", "Linear Scan Register Allocator"); -bool validateRegAlloc(MachineFunction *mf, LiveIntervals *lis, - VirtRegMap *vrm) { - - MachineRegisterInfo *mri = &mf->getRegInfo(); - const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo(); - bool allocationValid = true; - - - for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); - itr != end; ++itr) { - - LiveInterval *li = itr->second; - - if (TargetRegisterInfo::isPhysicalRegister(li->reg)) { - continue; - } - - if (vrm->hasPhys(li->reg)) { - const TargetRegisterClass *trc = mri->getRegClass(li->reg); - - if (lis->hasInterval(vrm->getPhys(li->reg))) { - if (li->overlaps(lis->getInterval(vrm->getPhys(li->reg)))) { - std::cerr << "vreg " << li->reg << " overlaps its assigned preg " - << vrm->getPhys(li->reg) << "(" << tri->getName(vrm->getPhys(li->reg)) << ")\n"; - } - } - - TargetRegisterClass::iterator fReg = - std::find(trc->allocation_order_begin(*mf), trc->allocation_order_end(*mf), - vrm->getPhys(li->reg)); - - if (fReg == trc->allocation_order_end(*mf)) { - std::cerr << "preg " << vrm->getPhys(li->reg) - << "(" << tri->getName(vrm->getPhys(li->reg)) << ") is not in the allocation set for vreg " - << li->reg << "\n"; - allocationValid &= false; - } - } - else { - std::cerr << "No preg for vreg " << li->reg << "\n"; - // What about conflicting loads/stores? - continue; - } - - for (LiveIntervals::iterator itr2 = next(itr); itr2 != end; ++itr2) { - - LiveInterval *li2 = itr2->second; - - if (li2->empty()) - continue; - - if (TargetRegisterInfo::isPhysicalRegister(li2->reg)) { - if (li->overlaps(*li2)) { - if (vrm->getPhys(li->reg) == li2->reg || - tri->areAliases(vrm->getPhys(li->reg), li2->reg)) { - std::cerr << "vreg " << li->reg << " overlaps preg " - << li2->reg << "(" << tri->getName(li2->reg) << ") which aliases " - << vrm->getPhys(li->reg) << "(" << tri->getName(vrm->getPhys(li->reg)) << ")\n"; - allocationValid &= false; - } - } - } - else { - - if (!vrm->hasPhys(li2->reg)) { - continue; - } - - if (li->overlaps(*li2)) { - if (vrm->getPhys(li->reg) == vrm->getPhys(li2->reg) || - tri->areAliases(vrm->getPhys(li->reg), vrm->getPhys(li2->reg))) { - std::cerr << "vreg " << li->reg << " (preg " << vrm->getPhys(li->reg) - << ") overlaps vreg " << li2->reg << " (preg " << vrm->getPhys(li2->reg) - << ") and " << vrm->getPhys(li->reg) << " aliases " << vrm->getPhys(li2->reg) << "\n"; - allocationValid &= false; - } - } - } - } - - } - - return allocationValid; - -} - - void RALinScan::ComputeRelatedRegClasses() { // First pass, add all reg classes to the union, and determine at least one // reg class that each register is in. @@ -526,10 +439,6 @@ linearScan(); - if (NewSpillFramework) { - bool allocValid = validateRegAlloc(mf_, li_, vrm_); - } - // Rewrite spill code and update the PhysRegsUsed set. rewriter_->runOnMachineFunction(*mf_, *vrm_, li_); From devang.patel at gmail.com Tue Jun 2 15:32:18 2009 From: devang.patel at gmail.com (Devang Patel) Date: Tue, 2 Jun 2009 13:32:18 -0700 Subject: [llvm-commits] [llvm] r72700 - in /llvm/trunk/tools/lto: LTOModule.cpp LTOModule.h In-Reply-To: <4A2577D3.30302@free.fr> References: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> <4A24FDC1.7010907@free.fr> <352a1fb20906021004va2266dak4fd12227c4469f65@mail.gmail.com> <4A256E0B.8030202@free.fr> <4A2577D3.30302@free.fr> Message-ID: <352a1fb20906021332r5de4a74aw5e13ae380f5942e5@mail.gmail.com> On Tue, Jun 2, 2009 at 12:04 PM, Duncan Sands wrote: >>>From the description, I think this is an issue of emulating some funny >> linker hacks in LTO mode rather than an issue of actual linking. ?So >> whether two files are linked with llvm-link has no effect on the >> issue. > > Isn't LTO supposed to be more or less equivalent to: link using > llvm-link, optimize using opt, codegen using llc? No. In LTO mode, the linker collects and shares information from bitcode files as well as from non-bitcode object files. llvm-link+opt+llc path does not collect & share any info from non-bit code file. Actually llvlm-link+opt+llc is essentially same as generate bitcode+opt+llc in this regard. >?If so, that > means that any hack needed for LTO should also be needed by one > of llvm-link, opt or llc... > > Ciao, > > Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- - Devang From edwintorok at gmail.com Tue Jun 2 15:33:00 2009 From: edwintorok at gmail.com (Torok Edwin) Date: Tue, 02 Jun 2009 20:33:00 -0000 Subject: [llvm-commits] [llvm] r72736 - /llvm/trunk/include/llvm/ADT/ilist.h Message-ID: <200906022033.n52KX0qB030438@zion.cs.uiuc.edu> Author: edwin Date: Tue Jun 2 15:32:59 2009 New Revision: 72736 URL: http://llvm.org/viewvc/llvm-project?rev=72736&view=rev Log: fix build on VC++2k8. Modified: llvm/trunk/include/llvm/ADT/ilist.h Modified: llvm/trunk/include/llvm/ADT/ilist.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ilist.h?rev=72736&r1=72735&r2=72736&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/ilist.h (original) +++ llvm/trunk/include/llvm/ADT/ilist.h Tue Jun 2 15:32:59 2009 @@ -481,8 +481,8 @@ L2.setTail(0); // Remove [first, last) from its old position. - NodeTy *First = &*first, *Prev = getPrev(First); - NodeTy *Next = last.getNodePtrUnchecked(), *Last = getPrev(Next); + NodeTy *First = &*first, *Prev = this->getPrev(First); + NodeTy *Next = last.getNodePtrUnchecked(), *Last = this->getPrev(Next); if (Prev) this->setNext(Prev, Next); else @@ -491,7 +491,7 @@ // Splice [first, last) into its new position. NodeTy *PosNext = position.getNodePtrUnchecked(); - NodeTy *PosPrev = getPrev(PosNext); + NodeTy *PosPrev = this->getPrev(PosNext); // Fix head of list... if (PosPrev) @@ -504,7 +504,7 @@ this->setNext(Last, PosNext); this->setPrev(PosNext, Last); - transferNodesFromList(L2, First, PosNext); + this->transferNodesFromList(L2, First, PosNext); // Now that everything is set, restore the pointers to the list sentinels. L2.setTail(L2Sentinel); From evan.cheng at apple.com Tue Jun 2 15:59:24 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 2 Jun 2009 13:59:24 -0700 Subject: [llvm-commits] [llvm] r70270 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Alpha/AsmPrinter/ lib In-Reply-To: <352a1fb20906021032tb1909afn3c2e0eb8818f0d82@mail.gmail.com> References: <352a1fb20906021032tb1909afn3c2e0eb8818f0d82@mail.gmail.com> Message-ID: <236B22EC-8D07-4655-951B-9FF060A5FEAD@apple.com> On Jun 2, 2009, at 10:32 AM, Devang Patel wrote: > On Mon, Apr 27, 2009 at 5:21 PM, Bill Wendling > wrote: >> Author: void Date: Mon Apr 27 19:21:31 2009 New Revision: 70270 URL: >> http://llvm.org/viewvc/llvm-project?rev=70270&view=rev Log: Massive >> check in. This >> changes the "-fast" flag to "-O#" in llc. If you want to use the >> old behavior, the flag is -O0. >> This change allows for finer-grained control over which >> optimizations are run at different -O >> levels. Most of this work was pretty mechanical. The majority of >> the fixes came from verifying >> that a "fast" variable wasn't used anymore. The JIT still uses a >> "Fast" flag. I'm not 100% sure >> if it's necessary to change it there... > > We won't to encode this info in bit code and avoid globals like this. > We already use a function attribute for -Os. Why not do the same here > ? This controls what codegen passes are being run. It's done once for the whole compilation. Function notes are for finer grain control that tell these passes to "behave" differently for individual functions. Yes, we could use function notes to control optimization level for individual functions. But I view that as a different issue. Evan > - > Devang > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Tue Jun 2 16:09:59 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 2 Jun 2009 14:09:59 -0700 Subject: [llvm-commits] [llvm] r72707 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/X86/ utils/TableGen/ In-Reply-To: <38A54C06-E377-4C3C-8A3B-BB24A194E5A2@apple.com> References: <200906012327.n51NRMqY006632@zion.cs.uiuc.edu> <668F172C-93E7-47E8-9B1F-333154602253@apple.com> <38A54C06-E377-4C3C-8A3B-BB24A194E5A2@apple.com> Message-ID: On Jun 2, 2009, at 11:23 AM, Dale Johannesen wrote: > > On Jun 2, 2009, at 11:00 AMPDT, Evan Cheng wrote: > >> Hi Dale, >> >> On first glance, the patch mostly looks good. But I don't care for >> "supportsHasI1". I would have added ADDC_FLAG / ADDE_FLAG opcodes and >> have those use MVT::EFLAGS > I assume you mean MVT::Flag >> and change ADDC / ADDE to use MVT::i1 to >> represent the flag value. > > Offhand I don't like that, it means a fair amount of parallel but > subtly different code in the target-independent parts and calls for > changing all non-x86 BEs to use addc_flag. This way, the target- > independent code is clean and the complexities are all in TableGen. > I agree HasI1 is not a thing of beauty; let me think about it more. But doesn't this mean ADDC produces a MVT::Flag for some targets but MVT::i1 for others? How would that work? > > This is not far off Eli's suggestion of hijacking UADDO to replace > ADDC with i1, what do you think of that? I suppose that's possible because they do seem similar. Evan > >> Thanks, >> >> Evan >> >> On Jun 1, 2009, at 4:27 PM, Dale Johannesen wrote: >> >>> Author: johannes >>> Date: Mon Jun 1 18:27:20 2009 >>> New Revision: 72707 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=72707&view=rev >>> Log: >>> Make the implicit inputs and outputs of target-independent >>> ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) >>> instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust >>> all target-independent code to use this format. >>> >>> Most targets will still produce a Flag-setting target-dependent >>> version when selection is done. X86 is converted to use i32 >>> instead, which means TableGen needs to produce different code >>> in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit >>> in xxxInstrInfo, currently set only for X86; in principle this >>> is temporary and should go away when all other targets have >>> been converted. All relevant X86 instruction patterns are >>> modified to represent setting and using EFLAGS explicitly. The >>> same can be done on other targets. >>> >>> The immediate behavior change is that an ADC/ADD pair are no >>> longer tightly coupled in the X86 scheduler; they can be >>> separated by instructions that don't clobber the flags (MOV). >>> I will soon add some peephole optimizations based on using >>> other instructions that set the flags to feed into ADC. >>> >>> >>> Modified: >>> llvm/trunk/include/llvm/CodeGen/SelectionDAG.h >>> llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h >>> llvm/trunk/include/llvm/Target/Target.td >>> llvm/trunk/include/llvm/Target/TargetSelectionDAG.td >>> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp >>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp >>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h >>> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp >>> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >>> llvm/trunk/lib/Target/X86/X86ISelLowering.h >>> llvm/trunk/lib/Target/X86/X86Instr64bit.td >>> llvm/trunk/lib/Target/X86/X86InstrInfo.td >>> llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >>> llvm/trunk/utils/TableGen/CodeGenTarget.cpp >>> llvm/trunk/utils/TableGen/CodeGenTarget.h >>> llvm/trunk/utils/TableGen/DAGISelEmitter.cpp >>> >>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) >>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Jun 1 >>> 18:27:20 2009 >>> @@ -324,6 +324,14 @@ >>> return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, >>> getRegister(Reg, N.getValueType()), N); >>> } >>> + // This version of getCopyToReg has the register (and its type) >>> as an >>> + // explicit output. >>> + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, MVT VT, unsigned >>> Reg, >>> + SDValue N) { >>> + SDVTList VTs = getVTList(MVT::Other, VT); >>> + SDValue Ops[] = { Chain, getRegister(Reg, VT), N}; >>> + return getNode(ISD::CopyToReg, dl, VTs, Ops, 3); >>> + } >>> >>> // This version of the getCopyToReg method takes an extra operand, >>> which >>> // indicates that there is potentially an incoming flag value (if >>> Flag is not >>> >>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) >>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Jun 1 >>> 18:27:20 2009 >>> @@ -242,14 +242,11 @@ >>> // remainder result. >>> SDIVREM, UDIVREM, >>> >>> - // CARRY_FALSE - This node is used when folding other nodes, >>> - // like ADDC/SUBC, which indicate the carry result is always >>> false. >>> - CARRY_FALSE, >>> - >>> // Carry-setting nodes for multiple precision addition and >>> subtraction. >>> // These nodes take two operands of the same value type, and >>> produce two >>> // results. The first result is the normal add or sub result, >>> the second >>> - // result is the carry flag result. >>> + // result is the carry flag result (type i1 or whatever it got >>> expanded to >>> + // for the target, value 0 or 1). >>> ADDC, SUBC, >>> >>> // Carry-using nodes for multiple precision addition and >>> subtraction. These >>> @@ -258,7 +255,8 @@ >>> // produce two results; the normal result of the add or sub, and >>> the output >>> // carry flag. These nodes both read and write a carry flag to >>> allow them >>> // to them to be chained together for add and sub of arbitrarily >>> large >>> - // values. >>> + // values. The carry flag (input and output) has type i1 or >>> whatever it >>> + // got expanded to for the target, and has value 0 or 1. >>> ADDE, SUBE, >>> >>> // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for >>> addition. >>> >>> Modified: llvm/trunk/include/llvm/Target/Target.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/include/llvm/Target/Target.td (original) >>> +++ llvm/trunk/include/llvm/Target/Target.td Mon Jun 1 18:27:20 >>> 2009 >>> @@ -326,6 +326,11 @@ >>> // Sparc manual specifies its instructions in the format [31..0] >>> (big), while >>> // PowerPC specifies them using the format [0..31] (little). >>> bit isLittleEndianEncoding = 0; >>> + >>> + // Targets that can support the HasI1 argument on ADDC and ADDE, >>> rather than >>> + // Flag, have this bit set. This is transitional and should go >>> away when all >>> + // targets have been switched over. >>> + bit supportsHasI1 = 0; >>> } >>> >>> // Standard Instructions. >>> >>> Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) >>> +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Mon Jun 1 >>> 18:27:20 2009 >>> @@ -216,6 +216,8 @@ >>> def SDNPMayLoad : SDNodeProperty; // May read memory, sets >>> 'mayLoad'. >>> def SDNPSideEffect : SDNodeProperty; // Sets >>> 'HasUnmodelledSideEffects'. >>> def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc >>> MemOperand >>> +def SDNPInI1 : SDNodeProperty; // Read an extra I1 operand >>> +def SDNPOutI1 : SDNodeProperty; // Write an extra I1 result >>> >>> // >>> = >>> = >>> = >>> ----------------------------------------------------------------------= >>> ==// >>> // Selection DAG Node definitions. >>> @@ -289,13 +291,13 @@ >>> def xor : SDNode<"ISD::XOR" , SDTIntBinOp, >>> [SDNPCommutative, SDNPAssociative]>; >>> def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, >>> - [SDNPCommutative, SDNPOutFlag]>; >>> + [SDNPCommutative, SDNPOutI1]>; >>> def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, >>> - [SDNPCommutative, SDNPOutFlag, SDNPInFlag] >>> >; >>> + [SDNPCommutative, SDNPInI1, SDNPOutI1]>; >>> def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, >>> - [SDNPOutFlag]>; >>> + [SDNPOutI1]>; >>> def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, >>> - [SDNPOutFlag, SDNPInFlag]>; >>> + [SDNPInI1, SDNPOutI1]>; >>> >>> def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; >>> def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; >>> >>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) >>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jun 1 >>> 18:27:20 2009 >>> @@ -1085,8 +1085,7 @@ >>> // If the flag result is dead, turn this into an ADD. >>> if (N->hasNUsesOfValue(0, 1)) >>> return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, >>> N1, N0), >>> - DAG.getNode(ISD::CARRY_FALSE, >>> - N->getDebugLoc(), MVT::Flag)); >>> + DAG.getConstant(0, N->getValueType(1))); >>> >>> // canonicalize constant to RHS. >>> if (N0C && !N1C) >>> @@ -1094,10 +1093,9 @@ >>> >>> // fold (addc x, 0) -> x + no carry out >>> if (N1C && N1C->isNullValue()) >>> - return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, >>> - N->getDebugLoc(), >>> MVT::Flag)); >>> + return CombineTo(N, N0, DAG.getConstant(0, N1.getValueType())); >>> >>> - // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share >>> no bits. >>> + // fold (addc a, b) -> (or a, b), 0 iff a and b share no bits. >>> APInt LHSZero, LHSOne; >>> APInt RHSZero, RHSOne; >>> APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); >>> @@ -1111,8 +1109,7 @@ >>> if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || >>> (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) >>> return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, >>> N0, N1), >>> - DAG.getNode(ISD::CARRY_FALSE, >>> - N->getDebugLoc(), MVT::Flag)); >>> + DAG.getConstant(0, N1.getValueType())); >>> } >>> >>> return SDValue(); >>> @@ -1131,8 +1128,9 @@ >>> N1, N0, CarryIn); >>> >>> // fold (adde x, y, false) -> (addc x, y) >>> - if (CarryIn.getOpcode() == ISD::CARRY_FALSE) >>> - return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), >>> N1, N0); >>> + if (ConstantSDNode *N2C = dyn_cast(CarryIn)) >>> + if (N2C->getAPIntValue()==0) >>> + return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList >>> (), N1, N0); >>> >>> return SDValue(); >>> } >>> >>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ >>> LegalizeIntegerTypes.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp >>> (original) >>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon >>> Jun 1 18:27:20 2009 >>> @@ -98,6 +98,10 @@ >>> case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); >>> break; >>> case ISD::SMULO: >>> case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; >>> + case ISD::ADDC: >>> + case ISD::SUBC: Res = PromoteIntRes_ADDSUBC(N, ResNo); >>> break; >>> + case ISD::ADDE: >>> + case ISD::SUBE: Res = PromoteIntRes_ADDSUBE(N, ResNo); >>> break; >>> >>> case ISD::ATOMIC_LOAD_ADD: >>> case ISD::ATOMIC_LOAD_SUB: >>> @@ -121,6 +125,35 @@ >>> SetPromotedInteger(SDValue(N, ResNo), Res); >>> } >>> >>> +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBC(SDNode *N, unsigned >>> ResNo) { >>> + // Only the carry bit result is expected to be promoted. >>> + assert(ResNo == 1 && "Only carry bit result promotion currently >>> supported!"); >>> + return PromoteIntRes_Overflow(N); >>> +} >>> + >>> +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBE(SDNode *N, unsigned >>> ResNo) { >>> + // Only the carry bit result is expected to be promoted. >>> + assert(ResNo == 1 && "Only carry bit result promotion currently >>> supported!"); >>> + // This is a ternary operator, so clone a slightly modified >>> + // PromoteIntRes_Overflow here (this is the only client). >>> + if (ResNo == 1) { >>> + // Simply change the return type of the boolean result. >>> + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); >>> + MVT ValueVTs[] = { N->getValueType(0), NVT }; >>> + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N- >>>> getOperand(2) }; >>> + SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), >>> + DAG.getVTList(ValueVTs, 2), Ops, 3); >>> + >>> + // Modified the sum result - switch anything that used the old >>> sum to use >>> + // the new one. >>> + ReplaceValueWith(SDValue(N, 0), Res); >>> + >>> + return SDValue(Res.getNode(), 1); >>> + } >>> + assert(0 && "Do not know how to promote this operator!"); >>> + abort(); >>> +} >>> + >>> SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { >>> // Sign-extend the new bits, and continue the assertion. >>> SDValue Op = SExtPromotedInteger(N->getOperand(0)); >>> @@ -419,7 +452,7 @@ >>> return Res; >>> } >>> >>> -/// Promote the overflow flag of an overflowing arithmetic node. >>> +/// Promote the overflow or carry result of an overflowing >>> arithmetic node. >>> SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { >>> // Simply change the return type of the boolean result. >>> MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); >>> @@ -666,6 +699,8 @@ >>> assert(0 && "Do not know how to promote this operator's >>> operand!"); >>> abort(); >>> >>> + case ISD::ADDE: >>> + case ISD::SUBE: Res = PromoteIntOp_ADDSUBE(N, OpNo); >>> break; >>> case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; >>> case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; >>> case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; >>> @@ -743,6 +778,13 @@ >>> } >>> } >>> >>> +SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBE(SDNode *N, unsigned >>> OpNo) { >>> + assert(OpNo == 2 && "Don't know how to promote this operand!"); >>> + return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), >>> + N->getOperand(1), >>> + GetPromotedInteger(N->getOperand >>> (2))); >>> +} >>> + >>> SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { >>> SDValue Op = GetPromotedInteger(N->getOperand(0)); >>> return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N- >>>> getValueType(0), Op); >>> @@ -1063,7 +1105,7 @@ >>> TLI.isOperationLegalOrCustom(ISD::ADDC, >>> TLI.getTypeToExpandTo >>> (NVT))) { >>> // Emit this X << 1 as X+X. >>> - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); >>> + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); >>> SDValue LoOps[2] = { InL, InL }; >>> Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); >>> SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; >>> @@ -1299,7 +1341,7 @@ >>> TLI.getTypeToExpandTo(NVT)); >>> >>> if (hasCarry) { >>> - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); >>> + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); >>> if (N->getOpcode() == ISD::ADD) { >>> Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); >>> HiOps[2] = Lo.getValue(1); >>> @@ -1344,7 +1386,7 @@ >>> DebugLoc dl = N->getDebugLoc(); >>> GetExpandedInteger(N->getOperand(0), LHSL, LHSH); >>> GetExpandedInteger(N->getOperand(1), RHSL, RHSH); >>> - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); >>> + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); >>> SDValue LoOps[2] = { LHSL, RHSL }; >>> SDValue HiOps[3] = { LHSH, RHSH }; >>> >>> @@ -1358,8 +1400,8 @@ >>> Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); >>> } >>> >>> - // Legalized the flag result - switch anything that used the old >>> flag to >>> - // use the new one. >>> + // Legalized the second result (carry bit) - switch anything that >>> used the >>> + // result to use the new one. >>> ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); >>> } >>> >>> @@ -1370,7 +1412,7 @@ >>> DebugLoc dl = N->getDebugLoc(); >>> GetExpandedInteger(N->getOperand(0), LHSL, LHSH); >>> GetExpandedInteger(N->getOperand(1), RHSL, RHSH); >>> - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); >>> + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); >>> SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; >>> SDValue HiOps[3] = { LHSH, RHSH }; >>> >>> @@ -1378,8 +1420,8 @@ >>> HiOps[2] = Lo.getValue(1); >>> Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); >>> >>> - // Legalized the flag result - switch anything that used the old >>> flag to >>> - // use the new one. >>> + // Legalized the second result (carry bit) - switch anything that >>> used the >>> + // result to use the new one. >>> ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); >>> } >>> >>> >>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) >>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Jun 1 >>> 18:27:20 2009 >>> @@ -242,6 +242,8 @@ >>> >>> // Integer Result Promotion. >>> void PromoteIntegerResult(SDNode *N, unsigned ResNo); >>> + SDValue PromoteIntRes_ADDSUBC(SDNode *N, unsigned ResNo); >>> + SDValue PromoteIntRes_ADDSUBE(SDNode *N, unsigned ResNo); >>> SDValue PromoteIntRes_AssertSext(SDNode *N); >>> SDValue PromoteIntRes_AssertZext(SDNode *N); >>> SDValue PromoteIntRes_Atomic1(AtomicSDNode *N); >>> @@ -278,6 +280,7 @@ >>> >>> // Integer Operand Promotion. >>> bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo); >>> + SDValue PromoteIntOp_ADDSUBE(SDNode *N, unsigned OpNo); >>> SDValue PromoteIntOp_ANY_EXTEND(SDNode *N); >>> SDValue PromoteIntOp_BIT_CONVERT(SDNode *N); >>> SDValue PromoteIntOp_BUILD_PAIR(SDNode *N); >>> >>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >>> (original) >>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Mon >>> Jun 1 18:27:20 2009 >>> @@ -268,6 +268,13 @@ >>> unsigned N = Node->getNumOperands(); >>> while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) >>> --N; >>> + // Skip hard registers set as a side effect (i.e. not result 0). >>> + while (N && Node->getOperand(N - 1).getOpcode() == ISD::CopyToReg >>> && >>> + Node->getOperand(N-1).getResNo() != 0 && >>> + !TargetRegisterInfo::isVirtualRegister( >>> + dyn_cast(Node->getOperand >>> (N-1).getOperand(1)) >>> + ->getReg())) >>> + --N; >>> if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) >>> --N; // Ignore chain if it exists. >>> return N; >>> >>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) >>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 1 >>> 18:27:20 2009 >>> @@ -5257,7 +5257,6 @@ >>> case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; >>> case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; >>> case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; >>> - case ISD::CARRY_FALSE: return "carry_false"; >>> case ISD::ADDC: return "addc"; >>> case ISD::ADDE: return "adde"; >>> case ISD::SADDO: return "saddo"; >>> >>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) >>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jun 1 >>> 18:27:20 2009 >>> @@ -190,6 +190,28 @@ >>> setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); >>> } >>> >>> + // ADDE and SUBE are lowered to local versions that contain >>> EFLAGS explicitly. >>> + // ADDC and SUBC are lowered to local versions so EFLAGS will be >>> an i32 >>> + // rather than the Flag used by the generic patterns. >>> + setOperationAction(ISD::ADDC , MVT::i8 , Custom); >>> + setOperationAction(ISD::ADDC , MVT::i16 , Custom); >>> + setOperationAction(ISD::ADDC , MVT::i32 , Custom); >>> + setOperationAction(ISD::SUBC , MVT::i8 , Custom); >>> + setOperationAction(ISD::SUBC , MVT::i16 , Custom); >>> + setOperationAction(ISD::SUBC , MVT::i32 , Custom); >>> + setOperationAction(ISD::ADDE , MVT::i8 , Custom); >>> + setOperationAction(ISD::ADDE , MVT::i16 , Custom); >>> + setOperationAction(ISD::ADDE , MVT::i32 , Custom); >>> + setOperationAction(ISD::SUBE , MVT::i8 , Custom); >>> + setOperationAction(ISD::SUBE , MVT::i16 , Custom); >>> + setOperationAction(ISD::SUBE , MVT::i32 , Custom); >>> + if (Subtarget->is64Bit()) { >>> + setOperationAction(ISD::ADDC , MVT::i64 , >>> Custom); >>> + setOperationAction(ISD::SUBC , MVT::i64 , >>> Custom); >>> + setOperationAction(ISD::ADDE , MVT::i64 , >>> Custom); >>> + setOperationAction(ISD::SUBE , MVT::i64 , >>> Custom); >>> + } >>> + >>> // Scalar integer divide and remainder are lowered to use >>> operations that >>> // produce two results, to match the available instructions. This >>> exposes >>> // the two-result form to trivial CSE, which is able to combine x/ >>> y and x%y >>> @@ -6475,6 +6497,21 @@ >>> return Sum; >>> } >>> >>> +SDValue X86TargetLowering::LowerADDSUBE(SDValue Op, SelectionDAG >>> &DAG) { >>> + DebugLoc dl = Op.getDebugLoc(); >>> + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); >>> + return DAG.getNode(Op.getOpcode()==ISD::ADDE ? X86ISD::ADDE : >>> X86ISD::SUBE, >>> + dl, VTs, Op.getOperand(0), Op.getOperand(1), >>> + Op.getOperand(2).getValue(1)); >>> +} >>> + >>> +SDValue X86TargetLowering::LowerADDSUBC(SDValue Op, SelectionDAG >>> &DAG) { >>> + DebugLoc dl = Op.getDebugLoc(); >>> + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); >>> + return DAG.getNode(Op.getOpcode()==ISD::ADDC ? X86ISD::ADD : >>> X86ISD::SUB, >>> + dl, VTs, Op.getOperand(0), Op.getOperand(1)); >>> +} >>> + >>> SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG >>> &DAG) { >>> MVT T = Op.getValueType(); >>> DebugLoc dl = Op.getDebugLoc(); >>> @@ -6543,6 +6580,10 @@ >>> SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG >>> &DAG) { >>> switch (Op.getOpcode()) { >>> default: assert(0 && "Should not custom lower this!"); >>> + case ISD::ADDC: >>> + case ISD::SUBC: return LowerADDSUBC(Op,DAG); >>> + case ISD::ADDE: >>> + case ISD::SUBE: return LowerADDSUBE(Op,DAG); >>> case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); >>> case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); >>> case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); >>> @@ -6791,6 +6832,10 @@ >>> case X86ISD::INC: return "X86ISD::INC"; >>> case X86ISD::DEC: return "X86ISD::DEC"; >>> case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; >>> + case X86ISD::ADDE: return "X86ISD::ADDE"; >>> + case X86ISD::SUBE: return "X86ISD::SUBE"; >>> + case X86ISD::ADDC: return "X86ISD::ADDC"; >>> + case X86ISD::SUBC: return "X86ISD::SUBC"; >>> } >>> } >>> >>> >>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) >>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Jun 1 18:27:20 >>> 2009 >>> @@ -243,6 +243,14 @@ >>> ADD, SUB, SMUL, UMUL, >>> INC, DEC, >>> >>> + // ADDC, SUBC - Arithmetic operations setting carry bit. The >>> normal >>> + // arithmetic operations do this, but they represent it as >>> Flag, and >>> + // we want the i32 EFLAGS register here. >>> + ADDC, SUBC, >>> + >>> + // ADDE, SUBE - Arithmetic operations with extra FLAGS >>> (EFLAGS) inputs. >>> + ADDE, SUBE, >>> + >>> // MUL_IMM - X86 specific multiply by immediate. >>> MUL_IMM >>> }; >>> @@ -576,7 +584,9 @@ >>> >>> std::pair FP_TO_INTHelper(SDValue Op, >>> SelectionDAG &DAG, >>> bool isSigned); >>> - >>> + >>> + SDValue LowerADDSUBC(SDValue Op, SelectionDAG &DAG); >>> + SDValue LowerADDSUBE(SDValue Op, SelectionDAG &DAG); >>> SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); >>> SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); >>> SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); >>> >>> Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) >>> +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Mon Jun 1 18:27:20 >>> 2009 >>> @@ -383,31 +383,52 @@ >>> let Uses = [EFLAGS] in { >>> let isTwoAddress = 1 in { >>> let isCommutable = 1 in >>> -def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins >>> GR64:$src1, GR64:$src2), >>> +def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), >>> + (ins GR64:$src1, GR64:$src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))] >>> >; >>> + [(set GR64:$dst, >>> + (X86adde_flag GR64:$src1, GR64:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> >>> -def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins >>> GR64:$src1, i64mem:$src2), >>> +def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), >>> + (ins GR64:$src1, i64mem:$src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (adde GR64:$src1, (load addr: >>> $src2)))]>; >>> + [(set GR64:$dst, >>> + (X86adde_flag GR64:$src1, (load addr: >>> $src2), EFLAGS)), >>> + (implicit EFLAGS)]>; >>> >>> -def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, >>> i64i8imm:$src2), >>> +def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), >>> + (ins GR64:$src1, i64i8imm:$src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (adde GR64:$src1, >>> i64immSExt8:$src2))]>; >>> -def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins >>> GR64:$src1, i64i32imm:$src2), >>> + [(set GR64:$dst, >>> + (X86adde_flag GR64:$src1, >>> i64immSExt8:$src2, EFLAGS)), >>> + (implicit EFLAGS)]>; >>> +def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), >>> + (ins GR64:$src1, i64i32imm: >>> $src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (adde GR64:$src1, >>> i64immSExt32:$src2))]>; >>> + [(set GR64:$dst, >>> + (X86adde_flag GR64:$src1, >>> i64immSExt32:$src2, >>> + EFLAGS)), >>> + (implicit EFLAGS)]>; >>> } // isTwoAddress >>> >>> def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, >>> GR64:$src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), GR64:$src2), >>> addr: >>> $dst)]>; >>> + [(store (X86adde_flag (load addr:$dst), >>> GR64:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, >>> i64i8imm : >>> $src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), >>> i64immSExt8:$src2), addr:$dst)]>; >>> + [(store (X86adde_flag (load addr:$dst), >>> i64immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, >>> i64i32imm:$src2), >>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), >>> i64immSExt8:$src2), addr:$dst)]>; >>> + [(store (X86adde_flag (load addr:$dst), >>> i64immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> } // Uses = [EFLAGS] >>> >>> let isTwoAddress = 1 in { >>> @@ -456,31 +477,52 @@ >>> >>> let Uses = [EFLAGS] in { >>> let isTwoAddress = 1 in { >>> -def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins >>> GR64:$src1, GR64:$src2), >>> +def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), >>> + (ins GR64:$src1, GR64:$src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (sube GR64:$src1, >>> GR64:$src2))] >>>> ; >>> + [(set GR64:$dst, >>> + (X86sube_flag GR64:$src1, GR64:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> >>> -def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins >>> GR64:$src1, i64mem:$src2), >>> +def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), >>> + (ins GR64:$src1, i64mem:$src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (sube GR64:$src1, (load addr: >>> $src2)))]>; >>> + [(set GR64:$dst, >>> + (X86sube_flag GR64:$src1, (load addr: >>> $src2), EFLAGS)), >>> + (implicit EFLAGS)]>; >>> >>> -def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, >>> i64i8imm:$src2), >>> +def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), >>> + (ins GR64:$src1, i64i8imm:$src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (sube GR64:$src1, >>> i64immSExt8:$src2))]>; >>> -def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins >>> GR64:$src1, i64i32imm:$src2), >>> + [(set GR64:$dst, >>> + (X86sube_flag GR64:$src1, >>> i64immSExt8:$src2, EFLAGS)), >>> + (implicit EFLAGS)]>; >>> +def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), >>> + (ins GR64:$src1, i64i32imm: >>> $src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR64:$dst, (sube GR64:$src1, >>> i64immSExt32:$src2))]>; >>> + [(set GR64:$dst, >>> + (X86sube_flag GR64:$src1, >>> i64immSExt32:$src2, >>> + EFLAGS)), >>> + (implicit EFLAGS)]>; >>> } // isTwoAddress >>> >>> def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, >>> GR64:$src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), GR64:$src2), >>> addr: >>> $dst)]>; >>> + [(store (X86sube_flag (load addr:$dst), >>> GR64:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, >>> i64i8imm : >>> $src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), i64immSExt8:$src2), >>> addr:$dst)]>; >>> + [(store (X86sube_flag (load addr:$dst), >>> i64immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, >>> i64i32imm:$src2), >>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), i64immSExt32:$src2), >>> addr:$dst)]>; >>> + [(store (X86sube_flag (load addr:$dst), >>> i64immSExt32:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> } // Uses = [EFLAGS] >>> } // Defs = [EFLAGS] >>> >>> >>> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) >>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Jun 1 18:27:20 >>> 2009 >>> @@ -34,6 +34,11 @@ >>> [SDTCisSameAs<0, 1>, >>> SDTCisSameAs<0, 2>, >>> SDTCisInt<0>]>; >>> +// Unary and binary operators that both read and write EFLAGS as a >>> side-effect. >>> +def SDTBinaryArithRWFlags : SDTypeProfile<1, 3, >>> + [SDTCisInt<0>, SDTCisSameAs<0, >>> 1>, >>> + SDTCisSameAs<0, 2>, SDTCisVT<3, >>> i32>]>; >>> + >>> def SDTX86BrCond : SDTypeProfile<0, 3, >>> [SDTCisVT<0, OtherVT>, >>> SDTCisVT<1, i8>, SDTCisVT<2, i32>] >>>> ; >>> @@ -156,6 +161,8 @@ >>> def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>; >>> def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; >>> def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; >>> +def X86adde_flag : SDNode<"X86ISD::ADDE", SDTBinaryArithRWFlags, >>> [SDNPInI1]>; >>> +def X86sube_flag : SDNode<"X86ISD::SUBE", SDTBinaryArithRWFlags, >>> [SDNPInI1]>; >>> >>> def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; >>> >>> @@ -2274,81 +2281,127 @@ >>> >>> let Uses = [EFLAGS] in { >>> let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y >>> -def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, >>> GR8:$src2), >>> +def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), >>> + (ins GR8:$src1, GR8:$src2), >>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>; >>> + [(set GR8:$dst, (X86adde_flag GR8:$src1, >>> GR8:$src2, EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst), >>> (ins GR16:$src1, GR16:$src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, >>> OpSize; >>> + [(set GR16:$dst, >>> + (X86adde_flag GR16:$src1, GR16:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>, >>> + OpSize; >>> def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), >>> (ins GR32:$src1, GR32:$src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; >>> + [(set GR32:$dst, >>> + (X86adde_flag GR32:$src1, GR32:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> } >>> def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst), >>> (ins GR8:$src1, i8mem:$src2), >>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR8:$dst, (adde GR8:$src1, (load addr: >>> $src2)))]>; >>> + [(set GR8:$dst, >>> + (X86adde_flag GR8:$src1, (load addr:$src2), >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst), >>> (ins GR16:$src1, i16mem:$src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (adde GR16:$src1, (load addr: >>> $src2)))]>, >>> + [(set GR16:$dst, >>> + (X86adde_flag GR16:$src1, (load addr:$src2), >>> EFLAGS)), >>> + (implicit EFLAGS)]>, >>> OpSize; >>> def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), >>> (ins GR32:$src1, i32mem:$src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (adde GR32:$src1, (load addr: >>> $src2)))]>; >>> -def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, >>> i8imm:$src2), >>> + [(set GR32:$dst, >>> + (X86adde_flag GR32:$src1, (load addr:$src2), >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> +def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), >>> + (ins GR8:$src1, i8imm:$src2), >>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>; >>> + [(set GR8:$dst, >>> + (X86adde_flag GR8:$src1, imm:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst), >>> (ins GR16:$src1, i16imm:$src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, >>> OpSize; >>> + [(set GR16:$dst, >>> + (X86adde_flag GR16:$src1, imm:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>, OpSize; >>> def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst), >>> (ins GR16:$src1, i16i8imm:$src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (adde GR16:$src1, >>> i16immSExt8:$src2))]>, >>> - OpSize; >>> + [(set GR16:$dst, >>> + (X86adde_flag GR16:$src1, i16immSExt8:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>, OpSize; >>> def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), >>> (ins GR32:$src1, i32imm:$src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; >>> + [(set GR32:$dst, >>> + (X86adde_flag GR32:$src1, imm:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), >>> (ins GR32:$src1, i32i8imm:$src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (adde GR32:$src1, >>> i32immSExt8:$src2))]>; >>> + [(set GR32:$dst, >>> + (X86adde_flag GR32:$src1, i32immSExt8:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> >>> let isTwoAddress = 0 in { >>> - def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, >>> GR8:$src2), >>> + def ADC8mr : I<0x10, MRMDestMem, (outs), >>> + (ins i8mem:$dst, GR8:$src2), >>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), GR8:$src2), >>> addr: >>> $dst)]>; >>> - def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, >>> GR16:$src2), >>> + [(store (X86adde_flag (load addr:$dst), >>> GR8:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> + def ADC16mr : I<0x11, MRMDestMem, (outs), >>> + (ins i16mem:$dst, GR16:$src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), GR16:$src2), >>> addr:$dst)]>, >>> - OpSize; >>> - def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, >>> GR32:$src2), >>> + [(store (X86adde_flag (load addr:$dst), >>> GR16:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>, OpSize; >>> + def ADC32mr : I<0x11, MRMDestMem, (outs), >>> + (ins i32mem:$dst, GR32:$src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), GR32:$src2), >>> addr:$dst)]>; >>> - def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm: >>> $src2), >>> + [(store (X86adde_flag (load addr:$dst), >>> GR32:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> + def ADC8mi : Ii8<0x80, MRM2m, (outs), >>> + (ins i8mem:$dst, i8imm:$src2), >>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (loadi8 addr:$dst), imm:$src2), >>> addr:$dst)]>; >>> - def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, >>> i16imm: >>> $src2), >>> + [(store (X86adde_flag (loadi8 addr:$dst), imm: >>> $src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> + def ADC16mi : Ii16<0x81, MRM2m, (outs), >>> + (ins i16mem:$dst, i16imm:$src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (loadi16 addr:$dst), imm:$src2), >>> addr:$dst)]>, >>> - OpSize; >>> - def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, >>> i16i8imm :$src2), >>> + [(store (X86adde_flag (loadi16 addr:$dst), imm: >>> $src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>, OpSize; >>> + def ADC16mi8 : Ii8<0x83, MRM2m, (outs), >>> + (ins i16mem:$dst, i16i8imm : >>> $src2), >>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), i16immSExt8:$src2), >>> addr:$dst)]>, >>> - OpSize; >>> - def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, >>> i32imm: >>> $src2), >>> + [(store (X86adde_flag (load addr:$dst), >>> i16immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>, OpSize; >>> + def ADC32mi : Ii32<0x81, MRM2m, (outs), >>> + (ins i32mem:$dst, i32imm:$src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (loadi32 addr:$dst), imm:$src2), >>> addr:$dst)]>; >>> - def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, >>> i32i8imm :$src2), >>> + [(store (X86adde_flag (loadi32 addr:$dst), imm: >>> $src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> + def ADC32mi8 : Ii8<0x83, MRM2m, (outs), >>> + (ins i32mem:$dst, i32i8imm: >>> $src2), >>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>> - [(store (adde (load addr:$dst), i32immSExt8:$src2), >>> addr:$dst)]>; >>> -} >>> + [(store (X86adde_flag (load addr:$dst), >>> i32immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> + } >>> } // Uses = [EFLAGS] >>> >>> // Register-Register Subtraction >>> @@ -2453,77 +2506,115 @@ >>> def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst), >>> (ins GR8:$src1, GR8:$src2), >>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>; >>> + [(set GR8:$dst, (X86sube_flag GR8:$src1, >>> GR8:$src2, EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst), >>> (ins GR16:$src1, GR16:$src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, >>> OpSize; >>> + [(set GR16:$dst, >>> + (X86sube_flag GR16:$src1, GR16:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>, OpSize; >>> def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), >>> (ins GR32:$src1, GR32:$src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; >>> + [(set GR32:$dst, >>> + (X86sube_flag GR32:$src1, GR32:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> >>> let isTwoAddress = 0 in { >>> def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, >>> GR8:$src2), >>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), GR8:$src2), >>> addr: >>> $dst)]>; >>> + [(store (X86sube_flag (load addr:$dst), >>> GR8:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, >>> GR16:$src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), GR16:$src2), >>> addr:$dst)]>, >>> + [(store (X86sube_flag (load addr:$dst), >>> GR16:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>, >>> OpSize; >>> def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, >>> GR32:$src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), GR32:$src2), >>> addr:$dst)]>; >>> + [(store (X86sube_flag (load addr:$dst), >>> GR32:$src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm: >>> $src2), >>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (loadi8 addr:$dst), imm:$src2), >>> addr:$dst)]>; >>> + [(store (X86sube_flag (loadi8 addr:$dst), imm: >>> $src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm: >>> $src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (loadi16 addr:$dst), imm:$src2), >>> addr:$dst)]>, >>> + [(store (X86sube_flag (loadi16 addr:$dst), imm: >>> $src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>, >>> OpSize; >>> def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, >>> i16i8imm :$src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), i16immSExt8:$src2), >>> addr:$dst)]>, >>> + [(store (X86sube_flag (load addr:$dst), >>> i16immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>, >>> OpSize; >>> def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm: >>> $src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (loadi32 addr:$dst), imm:$src2), >>> addr:$dst)]>; >>> + [(store (X86sube_flag (loadi32 addr:$dst), imm: >>> $src2, EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, >>> i32i8imm :$src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(store (sube (load addr:$dst), i32immSExt8:$src2), >>> addr:$dst)]>; >>> + [(store (X86sube_flag (load addr:$dst), >>> i32immSExt8:$src2, >>> + EFLAGS), >>> + addr:$dst), >>> + (implicit EFLAGS)]>; >>> } >>> def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, >>> i8mem:$src2), >>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR8:$dst, (sube GR8:$src1, (load addr: >>> $src2)))]>; >>> + [(set GR8:$dst, >>> + (X86sube_flag GR8:$src1, (load addr: >>> $src2), EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst), >>> (ins GR16:$src1, i16mem:$src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (sube GR16:$src1, (load addr: >>> $src2)))]>, >>> + [(set GR16:$dst, >>> + (X86sube_flag GR16:$src1, (load addr: >>> $src2), EFLAGS)), >>> + (implicit EFLAGS)]>, >>> OpSize; >>> def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), >>> (ins GR32:$src1, i32mem:$src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (sube GR32:$src1, (load addr: >>> $src2)))]>; >>> + [(set GR32:$dst, >>> + (X86sube_flag GR32:$src1, (load addr: >>> $src2), EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, >>> i8imm:$src2), >>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>; >>> + [(set GR8:$dst, >>> + (X86sube_flag GR8:$src1, imm:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst), >>> (ins GR16:$src1, i16imm:$src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (sube GR16:$src1, imm:$src2))] >>>> , OpSize; >>> + [(set GR16:$dst, >>> + (X86sube_flag GR16:$src1, imm:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>, OpSize; >>> def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst), >>> (ins GR16:$src1, i16i8imm:$src2), >>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR16:$dst, (sube GR16:$src1, >>> i16immSExt8:$src2))]>, >>> - OpSize; >>> + [(set GR16:$dst, >>> + (X86sube_flag GR16:$src1, >>> i16immSExt8:$src2, EFLAGS)), >>> + (implicit EFLAGS)]>, OpSize; >>> def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), >>> (ins GR32:$src1, i32imm:$src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (sube GR32:$src1, imm: >>> $src2))]>; >>> + [(set GR32:$dst, >>> + (X86sube_flag GR32:$src1, imm:$src2, >>> EFLAGS)), >>> + (implicit EFLAGS)]>; >>> def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), >>> (ins GR32:$src1, i32i8imm:$src2), >>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>> - [(set GR32:$dst, (sube GR32:$src1, >>> i32immSExt8:$src2))]>; >>> + [(set GR32:$dst, >>> + (X86sube_flag GR32:$src1, >>> i32immSExt8:$src2, EFLAGS)), >>> + (implicit EFLAGS)]>; >>> } // Uses = [EFLAGS] >>> } // Defs = [EFLAGS] >>> >>> >>> Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) >>> +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Mon Jun 1 >>> 18:27:20 2009 >>> @@ -399,9 +399,13 @@ >>> } else if (PropList[i]->getName() == "SDNPHasChain") { >>> Properties |= 1 << SDNPHasChain; >>> } else if (PropList[i]->getName() == "SDNPOutFlag") { >>> - Properties |= 1 << SDNPOutFlag; >>> + Properties |= 1 << SDNPOutFlag; >>> + assert(!(Properties & (1<>> + "Can't handle OutFlag and OutI1"); >>> } else if (PropList[i]->getName() == "SDNPInFlag") { >>> Properties |= 1 << SDNPInFlag; >>> + assert(!(Properties & (1<>> + "Can't handle InFlag and InI1"); >>> } else if (PropList[i]->getName() == "SDNPOptInFlag") { >>> Properties |= 1 << SDNPOptInFlag; >>> } else if (PropList[i]->getName() == "SDNPMayStore") { >>> @@ -412,6 +416,14 @@ >>> Properties |= 1 << SDNPSideEffect; >>> } else if (PropList[i]->getName() == "SDNPMemOperand") { >>> Properties |= 1 << SDNPMemOperand; >>> + } else if (PropList[i]->getName() == "SDNPInI1") { >>> + Properties |= 1 << SDNPInI1; >>> + assert(!(Properties & (1<>> + "Can't handle InFlag and InI1"); >>> + } else if (PropList[i]->getName() == "SDNPOutI1") { >>> + Properties |= 1 << SDNPOutI1; >>> + assert(!(Properties & (1<>> + "Can't handle OutFlag and OutI1"); >>> } else { >>> cerr << "Unknown SD Node property '" << PropList[i]->getName() >>> << "' on node '" << R->getName() << "'!\n"; >>> >>> Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) >>> +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Jun 1 18:27:20 >>> 2009 >>> @@ -385,6 +385,13 @@ >>> return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); >>> } >>> >>> +/// supportsHasI1 - Return whether this target supports the >>> implicit I1, >>> +/// rather than Flags, for ADDC/ADDE >>> +/// >>> +bool CodeGenTarget::supportsHasI1() const { >>> + return getInstructionSet()->getValueAsBit("supportsHasI1"); >>> +} >>> + >>> // >>> = >>> = >>> = >>> ----------------------------------------------------------------------= >>> ==// >>> // ComplexPattern implementation >>> // >>> >>> Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/utils/TableGen/CodeGenTarget.h (original) >>> +++ llvm/trunk/utils/TableGen/CodeGenTarget.h Mon Jun 1 18:27:20 >>> 2009 >>> @@ -43,7 +43,9 @@ >>> SDNPMayLoad, >>> SDNPMayStore, >>> SDNPSideEffect, >>> - SDNPMemOperand >>> + SDNPMemOperand, >>> + SDNPInI1, >>> + SDNPOutI1 >>> }; >>> >>> // ComplexPattern attributes. >>> @@ -209,10 +211,12 @@ >>> void getInstructionsByEnumValue(std::vector>> CodeGenInstruction*> >>> >>> &NumberedInstructions); >>> >>> - >>> /// isLittleEndianEncoding - are instruction bit patterns defined >>> as [0..n]? >>> /// >>> bool isLittleEndianEncoding() const; >>> + >>> + /// supportsHasI1 - does this target understand HasI1 for ADDE >>> and ADDC? >>> + bool supportsHasI1() const; >>> }; >>> >>> /// ComplexPattern - ComplexPattern info, corresponding to the >>> ComplexPattern >>> >>> Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=72707&r1=72706&r2=72707&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) >>> +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Jun 1 18:27:20 >>> 2009 >>> @@ -670,7 +670,8 @@ >>> HasChain = true; >>> FoldedChains.push_back(std::make_pair(RootName, >>> CInfo.getNumResults())); >>> } >>> - if (NodeHasProperty(Child, SDNPOutFlag, CGP)) { >>> + if (NodeHasProperty(Child, SDNPOutFlag, CGP) || >>> + NodeHasProperty(Child, SDNPOutI1, CGP)) { >>> assert(FoldedFlag.first == "" && FoldedFlag.second == 0 && >>> "Pattern folded multiple nodes which produce flags?"); >>> FoldedFlag = std::make_pair(RootName, >>> @@ -969,6 +970,10 @@ >>> PatternHasProperty(Pattern, SDNPInFlag, CGP); >>> bool NodeHasOutFlag = isRoot && >>> PatternHasProperty(Pattern, SDNPOutFlag, CGP); >>> + bool NodeHasInI1 = isRoot && >>> + PatternHasProperty(Pattern, SDNPInI1, CGP); >>> + bool NodeHasOutI1 = isRoot && >>> + PatternHasProperty(Pattern, SDNPOutI1, CGP); >>> bool NodeHasChain = InstPatNode && >>> PatternHasProperty(InstPatNode, SDNPHasChain, CGP); >>> bool InputHasChain = isRoot && >>> @@ -1054,10 +1059,13 @@ >>> >>> // Emit all the chain and CopyToReg stuff. >>> bool ChainEmitted = NodeHasChain; >>> - if (NodeHasInFlag || HasImpInputs) >>> + // InFlag and InI1 cannot both be set (checked in >>> + // CodeGenDAGPatterns), so use the same variables for both. >>> + if (NodeHasInFlag || HasImpInputs || NodeHasInI1) >>> EmitInFlagSelectCode(Pattern, "N", ChainEmitted, >>> InFlagDecled, ResNodeDecled, true); >>> - if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs) { >>> + if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs || >>> + NodeHasInI1) { >>> if (!InFlagDecled) { >>> emitCode("SDValue InFlag(0, 0);"); >>> InFlagDecled = true; >>> @@ -1113,7 +1121,7 @@ >>> } >>> if (NodeHasChain) >>> Code += ", MVT::Other"; >>> - if (NodeHasOutFlag) >>> + if (NodeHasOutFlag || (NodeHasOutI1 && !CGT.supportsHasI1())) >>> Code += ", MVT::Flag"; >>> >>> // Inputs. >>> @@ -1173,7 +1181,8 @@ >>> } >>> Code += ", &Ops" + utostr(OpsNo) + "[0], Ops" + utostr >>> (OpsNo) + >>> ".size()"; >>> - } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs) >>> + } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs >>> || >>> + NodeHasInI1) >>> AllOps.push_back("InFlag"); >>> >>> unsigned NumOps = AllOps.size(); >>> @@ -1207,7 +1216,7 @@ >>> NodeOps.push_back("Tmp" + utostr(ResNo)); >>> } else { >>> >>> - if (NodeHasOutFlag) { >>> + if (NodeHasOutFlag || NodeHasOutI1) { >>> if (!InFlagDecled) { >>> After.push_back("SDValue InFlag(ResNode, " + >>> utostr(NumResults+NumDstRegs+(unsigned) >>> NodeHasChain) + >>> @@ -1228,13 +1237,15 @@ >>> utostr(NumResults+NumDstRegs) + ")"); >>> } >>> >>> - if (NodeHasOutFlag) { >>> + if (NodeHasOutFlag || NodeHasOutI1) { >>> if (FoldedFlag.first != "") { >>> - ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + >>> ".getNode(), " + >>> + ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + >>> + ".getNode(), " + >>> utostr(FoldedFlag.second) + ")"); >>> ReplaceTos.push_back("InFlag"); >>> } else { >>> - assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP)); >>> + assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP) || >>> + NodeHasProperty(Pattern, SDNPOutI1, CGP)); >>> ReplaceFroms.push_back("SDValue(N.getNode(), " + >>> utostr(NumPatResults + (unsigned) >>> InputHasChain) >>> + ")"); >>> @@ -1251,7 +1262,8 @@ >>> } >>> >>> // User does not expect the instruction would produce a chain! >>> - if ((!InputHasChain && NodeHasChain) && NodeHasOutFlag) { >>> + if ((!InputHasChain && NodeHasChain) && >>> + (NodeHasOutFlag || NodeHasOutI1)) { >>> ; >>> } else if (InputHasChain && !NodeHasChain) { >>> // One of the inner node produces a chain. >>> @@ -1391,6 +1403,8 @@ >>> unsigned OpNo = >>> (unsigned) NodeHasProperty(N, SDNPHasChain, CGP); >>> bool HasInFlag = NodeHasProperty(N, SDNPInFlag, CGP); >>> + bool HasInI1 = NodeHasProperty(N, SDNPInI1, CGP); >>> + bool InFlagDefined = false; >>> for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, + >>> +OpNo) { >>> TreePatternNode *Child = N->getChild(i); >>> if (!Child->isLeaf()) { >>> @@ -1424,21 +1438,41 @@ >>> emitCode("SDValue InFlag(0, 0);"); >>> InFlagDecled = true; >>> } >>> - std::string Decl = (!ResNodeDecled) ? "SDNode *" : >>> ""; >>> - emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + >>> ChainName + >>> + if (HasInI1) { >>> + if (!ResNodeDecled) { >>> + emitCode("SDNode * ResNode;"); >>> + } >>> + if (T.supportsHasI1()) >>> + emitCode("ResNode = CurDAG->getCopyToReg(" + >>> ChainName + >>> + ", " + RootName + ".getDebugLoc()" + >>> + ", " + getEnumName(RVT) + >>> + ", " + getQualifiedName(RR) + >>> + ", " + RootName + utostr(OpNo) + >>> ").getNode();"); >>> + else >>> + emitCode("ResNode = CurDAG->getCopyToReg(" + >>> ChainName + >>> + ", " + RootName + ".getDebugLoc()" + >>> + ", " + getQualifiedName(RR) + >>> + ", " + RootName + utostr(OpNo) + >>> + ", InFlag).getNode();"); >>> + InFlagDefined = true; >>> + } else { >>> + std::string Decl = (!ResNodeDecled) ? "SDNode *" : >>> ""; >>> + emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + >>> ChainName + >>> ", " + RootName + ".getDebugLoc()" + >>> ", " + getQualifiedName(RR) + >>> - ", " + RootName + utostr(OpNo) + ", >>> InFlag).getNode();"); >>> - ResNodeDecled = true; >>> + ", " + RootName + utostr(OpNo) + >>> + ", InFlag).getNode();"); >>> + } >>> emitCode(ChainName + " = SDValue(ResNode, 0);"); >>> emitCode("InFlag = SDValue(ResNode, 1);"); >>> + ResNodeDecled = true; >>> } >>> } >>> } >>> } >>> } >>> >>> - if (HasInFlag) { >>> + if (HasInFlag || (HasInI1 && !InFlagDefined)) { >>> if (!InFlagDecled) { >>> emitCode("SDValue InFlag = " + RootName + >>> ".getOperand(" + utostr(OpNo) + ");"); >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From daniel at zuster.org Tue Jun 2 16:14:16 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 02 Jun 2009 21:14:16 -0000 Subject: [llvm-commits] [llvm] r72738 - /llvm/trunk/utils/NewNightlyTest.pl Message-ID: <200906022114.n52LEGkA031764@zion.cs.uiuc.edu> Author: ddunbar Date: Tue Jun 2 16:14:15 2009 New Revision: 72738 URL: http://llvm.org/viewvc/llvm-project?rev=72738&view=rev Log: NightlyTest: Stop running a separate Olden pass during nightly test. - Unless I'm mistaken, these results weren't even being reported and just served to clobber the previous build products and waste cycles. Modified: llvm/trunk/utils/NewNightlyTest.pl Modified: llvm/trunk/utils/NewNightlyTest.pl URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/NewNightlyTest.pl?rev=72738&r1=72737&r2=72738&view=diff ============================================================================== --- llvm/trunk/utils/NewNightlyTest.pl (original) +++ llvm/trunk/utils/NewNightlyTest.pl Tue Jun 2 16:14:15 2009 @@ -22,10 +22,7 @@ # -noremoveresults Do not remove the WEBDIR after it has been built. # -nobuild Do not build llvm. If tests are enabled perform them # on the llvm build specified in the build directory -# -notest Do not even attempt to run the test programs. Implies -# -norunningtests. -# -norunningtests Do not run the Olden benchmark suite with -# LARGE_PROBLEM_SIZE enabled. +# -notest Do not even attempt to run the test programs. # -nodejagnu Do not run feature or regression tests # -parallel Run parallel jobs with GNU Make (see -parallel-jobs). # -parallel-jobs The number of parallel Make jobs to use (default is two). @@ -128,7 +125,6 @@ $nickname=""; $NOTEST=0; $USESVN=1; -$NORUNNINGTESTS=0; $MAKECMD="make"; $SUBMITSERVER = "llvm.org"; $SUBMITSCRIPT = "/nightlytest/NightlyTestAccept.php"; @@ -145,8 +141,8 @@ if (/^-nocvsstats$/) { $NOCVSSTATS = 1; next; } if (/^-noremove$/) { $NOREMOVE = 1; next; } if (/^-noremoveresults$/){ $NOREMOVERESULTS = 1; next; } - if (/^-notest$/) { $NOTEST = 1; $NORUNNINGTESTS = 1; next; } - if (/^-norunningtests$/) { $NORUNNINGTESTS = 1; next; } + if (/^-notest$/) { $NOTEST = 1; next; } + if (/^-norunningtests$/) { next; } # Backward compatibility, ignored. if (/^-parallel-jobs$/) { $PARALLELJOBS = "$ARGV[0]"; shift; next;} if (/^-parallel$/) { $MAKEOPTS = "$MAKEOPTS -j$PARALLELJOBS -l3.0"; next; } if (/^-release$/) { $MAKEOPTS = "$MAKEOPTS ENABLE_OPTIMIZED=1 ". @@ -252,7 +248,6 @@ my $Prefix = "$WebDir/$DATE"; my $BuildLog = "$Prefix-Build-Log.txt"; my $COLog = "$Prefix-CVS-Log.txt"; -my $OldenTestsLog = "$Prefix-Olden-tests.txt"; my $SingleSourceLog = "$Prefix-SingleSource-ProgramTest.txt.gz"; my $MultiSourceLog = "$Prefix-MultiSource-ProgramTest.txt.gz"; my $ExternalLog = "$Prefix-External-ProgramTest.txt.gz"; @@ -1006,38 +1001,6 @@ } #end if !$BuildError - -############################################################## -# -# If we built the tree successfully, runs of the Olden suite with -# LARGE_PROBLEM_SIZE on so that we can get some "running" statistics. -# -############################################################## -if (!$BuildError) { - if ( $VERBOSE ) { print "OLDEN TEST SUITE STAGE\n"; } - my ($NATTime, $CBETime, $LLCTime, $JITTime, $OptTime, $BytecodeSize, - $MachCodeSize) = ("","","","","","",""); - if (!$NORUNNINGTESTS) { - ChangeDir( "$BuildDir/llvm/projects/llvm-test/MultiSource/Benchmarks/Olden", - "Olden Test Directory"); - - # Clean out previous results... - system "$NICE $MAKECMD $MAKEOPTS clean > /dev/null 2>&1"; - - # Run the nightly test in this directory, with LARGE_PROBLEM_SIZE and - # GET_STABLE_NUMBERS enabled! - if( $VERBOSE ) { - print "$MAKECMD -k $MAKEOPTS $PROGTESTOPTS report.nightly.csv.out " . - "TEST=nightly LARGE_PROBLEM_SIZE=1 GET_STABLE_NUMBERS=1 " . - "> /dev/null 2>&1\n"; - } - system "$MAKECMD -k $MAKEOPTS $PROGTESTOPTS report.nightly.csv.out " . - "TEST=nightly LARGE_PROBLEM_SIZE=1 GET_STABLE_NUMBERS=1 " . - "> /dev/null 2>&1"; - system "cp report.nightly.csv $OldenTestsLog"; - } -} - ############################################################## # # Getting end timestamp From dalej at apple.com Tue Jun 2 16:20:44 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 2 Jun 2009 14:20:44 -0700 Subject: [llvm-commits] [llvm] r72707 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/X86/ utils/TableGen/ In-Reply-To: References: <200906012327.n51NRMqY006632@zion.cs.uiuc.edu> <668F172C-93E7-47E8-9B1F-333154602253@apple.com> <38A54C06-E377-4C3C-8A3B-BB24A194E5A2@apple.com> Message-ID: <5F5FC88E-099C-48BE-84F5-DFA16BB25EAA@apple.com> On Jun 2, 2009, at 2:09 PMPDT, Evan Cheng wrote: > > On Jun 2, 2009, at 11:23 AM, Dale Johannesen wrote: > >> >> On Jun 2, 2009, at 11:00 AMPDT, Evan Cheng wrote: >> >>> Hi Dale, >>> >>> On first glance, the patch mostly looks good. But I don't care for >>> "supportsHasI1". I would have added ADDC_FLAG / ADDE_FLAG opcodes >>> and >>> have those use MVT::EFLAGS >> I assume you mean MVT::Flag >>> and change ADDC / ADDE to use MVT::i1 to >>> represent the flag value. >> >> Offhand I don't like that, it means a fair amount of parallel but >> subtly different code in the target-independent parts and calls for >> changing all non-x86 BEs to use addc_flag. This way, the target- >> independent code is clean and the complexities are all in TableGen. >> I agree HasI1 is not a thing of beauty; let me think about it more. > > But doesn't this mean ADDC produces a MVT::Flag for some targets but > MVT::i1 for others? How would that work? In the target-independent parts ADDC produces MVT::i1. When we select to target-dependent code it may get lowered to produce either i1 (as it has been legalized for the target) or Flag depending on what the target is ready for. The TableGen code that does this is pretty ugly, and hopefully that's a temporary situation; OTOH, the ugliness is pretty well limited to TableGen. Most targets don't have an analog of (implicit EFLAGS), and I'm not familiar with all the architectures, so I didn't think it practical to change all the other targets at once. >> This is not far off Eli's suggestion of hijacking UADDO to replace >> ADDC with i1, what do you think of that? > > I suppose that's possible because they do seem similar. > > Evan > >> >>> Thanks, >>> >>> Evan >>> >>> On Jun 1, 2009, at 4:27 PM, Dale Johannesen wrote: >>> >>>> Author: johannes >>>> Date: Mon Jun 1 18:27:20 2009 >>>> New Revision: 72707 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=72707&view=rev >>>> Log: >>>> Make the implicit inputs and outputs of target-independent >>>> ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) >>>> instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust >>>> all target-independent code to use this format. >>>> >>>> Most targets will still produce a Flag-setting target-dependent >>>> version when selection is done. X86 is converted to use i32 >>>> instead, which means TableGen needs to produce different code >>>> in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit >>>> in xxxInstrInfo, currently set only for X86; in principle this >>>> is temporary and should go away when all other targets have >>>> been converted. All relevant X86 instruction patterns are >>>> modified to represent setting and using EFLAGS explicitly. The >>>> same can be done on other targets. >>>> >>>> The immediate behavior change is that an ADC/ADD pair are no >>>> longer tightly coupled in the X86 scheduler; they can be >>>> separated by instructions that don't clobber the flags (MOV). >>>> I will soon add some peephole optimizations based on using >>>> other instructions that set the flags to feed into ADC. >>>> >>>> >>>> Modified: >>>> llvm/trunk/include/llvm/CodeGen/SelectionDAG.h >>>> llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h >>>> llvm/trunk/include/llvm/Target/Target.td >>>> llvm/trunk/include/llvm/Target/TargetSelectionDAG.td >>>> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp >>>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp >>>> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h >>>> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >>>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp >>>> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >>>> llvm/trunk/lib/Target/X86/X86ISelLowering.h >>>> llvm/trunk/lib/Target/X86/X86Instr64bit.td >>>> llvm/trunk/lib/Target/X86/X86InstrInfo.td >>>> llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >>>> llvm/trunk/utils/TableGen/CodeGenTarget.cpp >>>> llvm/trunk/utils/TableGen/CodeGenTarget.h >>>> llvm/trunk/utils/TableGen/DAGISelEmitter.cpp >>>> >>>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) >>>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Jun 1 >>>> 18:27:20 2009 >>>> @@ -324,6 +324,14 @@ >>>> return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, >>>> getRegister(Reg, N.getValueType()), N); >>>> } >>>> + // This version of getCopyToReg has the register (and its type) >>>> as an >>>> + // explicit output. >>>> + SDValue getCopyToReg(SDValue Chain, DebugLoc dl, MVT VT, >>>> unsigned >>>> Reg, >>>> + SDValue N) { >>>> + SDVTList VTs = getVTList(MVT::Other, VT); >>>> + SDValue Ops[] = { Chain, getRegister(Reg, VT), N}; >>>> + return getNode(ISD::CopyToReg, dl, VTs, Ops, 3); >>>> + } >>>> >>>> // This version of the getCopyToReg method takes an extra operand, >>>> which >>>> // indicates that there is potentially an incoming flag value (if >>>> Flag is not >>>> >>>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) >>>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Jun 1 >>>> 18:27:20 2009 >>>> @@ -242,14 +242,11 @@ >>>> // remainder result. >>>> SDIVREM, UDIVREM, >>>> >>>> - // CARRY_FALSE - This node is used when folding other nodes, >>>> - // like ADDC/SUBC, which indicate the carry result is always >>>> false. >>>> - CARRY_FALSE, >>>> - >>>> // Carry-setting nodes for multiple precision addition and >>>> subtraction. >>>> // These nodes take two operands of the same value type, and >>>> produce two >>>> // results. The first result is the normal add or sub result, >>>> the second >>>> - // result is the carry flag result. >>>> + // result is the carry flag result (type i1 or whatever it got >>>> expanded to >>>> + // for the target, value 0 or 1). >>>> ADDC, SUBC, >>>> >>>> // Carry-using nodes for multiple precision addition and >>>> subtraction. These >>>> @@ -258,7 +255,8 @@ >>>> // produce two results; the normal result of the add or sub, and >>>> the output >>>> // carry flag. These nodes both read and write a carry flag to >>>> allow them >>>> // to them to be chained together for add and sub of arbitrarily >>>> large >>>> - // values. >>>> + // values. The carry flag (input and output) has type i1 or >>>> whatever it >>>> + // got expanded to for the target, and has value 0 or 1. >>>> ADDE, SUBE, >>>> >>>> // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for >>>> addition. >>>> >>>> Modified: llvm/trunk/include/llvm/Target/Target.td >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/include/llvm/Target/Target.td (original) >>>> +++ llvm/trunk/include/llvm/Target/Target.td Mon Jun 1 18:27:20 >>>> 2009 >>>> @@ -326,6 +326,11 @@ >>>> // Sparc manual specifies its instructions in the format [31..0] >>>> (big), while >>>> // PowerPC specifies them using the format [0..31] (little). >>>> bit isLittleEndianEncoding = 0; >>>> + >>>> + // Targets that can support the HasI1 argument on ADDC and ADDE, >>>> rather than >>>> + // Flag, have this bit set. This is transitional and should go >>>> away when all >>>> + // targets have been switched over. >>>> + bit supportsHasI1 = 0; >>>> } >>>> >>>> // Standard Instructions. >>>> >>>> Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) >>>> +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Mon Jun 1 >>>> 18:27:20 2009 >>>> @@ -216,6 +216,8 @@ >>>> def SDNPMayLoad : SDNodeProperty; // May read memory, sets >>>> 'mayLoad'. >>>> def SDNPSideEffect : SDNodeProperty; // Sets >>>> 'HasUnmodelledSideEffects'. >>>> def SDNPMemOperand : SDNodeProperty; // Touches memory, has >>>> assoc >>>> MemOperand >>>> +def SDNPInI1 : SDNodeProperty; // Read an extra I1 >>>> operand >>>> +def SDNPOutI1 : SDNodeProperty; // Write an extra I1 >>>> result >>>> >>>> // >>>> = >>>> = >>>> = >>>> ----------------------------------------------------------------------= >>>> ==// >>>> // Selection DAG Node definitions. >>>> @@ -289,13 +291,13 @@ >>>> def xor : SDNode<"ISD::XOR" , SDTIntBinOp, >>>> [SDNPCommutative, SDNPAssociative]>; >>>> def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, >>>> - [SDNPCommutative, SDNPOutFlag]>; >>>> + [SDNPCommutative, SDNPOutI1]>; >>>> def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, >>>> - [SDNPCommutative, SDNPOutFlag, SDNPInFlag] >>>>> ; >>>> + [SDNPCommutative, SDNPInI1, SDNPOutI1]>; >>>> def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, >>>> - [SDNPOutFlag]>; >>>> + [SDNPOutI1]>; >>>> def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, >>>> - [SDNPOutFlag, SDNPInFlag]>; >>>> + [SDNPInI1, SDNPOutI1]>; >>>> >>>> def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; >>>> def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; >>>> >>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) >>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jun 1 >>>> 18:27:20 2009 >>>> @@ -1085,8 +1085,7 @@ >>>> // If the flag result is dead, turn this into an ADD. >>>> if (N->hasNUsesOfValue(0, 1)) >>>> return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, >>>> N1, N0), >>>> - DAG.getNode(ISD::CARRY_FALSE, >>>> - N->getDebugLoc(), MVT::Flag)); >>>> + DAG.getConstant(0, N->getValueType(1))); >>>> >>>> // canonicalize constant to RHS. >>>> if (N0C && !N1C) >>>> @@ -1094,10 +1093,9 @@ >>>> >>>> // fold (addc x, 0) -> x + no carry out >>>> if (N1C && N1C->isNullValue()) >>>> - return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, >>>> - N->getDebugLoc(), >>>> MVT::Flag)); >>>> + return CombineTo(N, N0, DAG.getConstant(0, >>>> N1.getValueType())); >>>> >>>> - // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share >>>> no bits. >>>> + // fold (addc a, b) -> (or a, b), 0 iff a and b share no bits. >>>> APInt LHSZero, LHSOne; >>>> APInt RHSZero, RHSOne; >>>> APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); >>>> @@ -1111,8 +1109,7 @@ >>>> if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || >>>> (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) >>>> return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, >>>> N0, N1), >>>> - DAG.getNode(ISD::CARRY_FALSE, >>>> - N->getDebugLoc(), MVT::Flag)); >>>> + DAG.getConstant(0, N1.getValueType())); >>>> } >>>> >>>> return SDValue(); >>>> @@ -1131,8 +1128,9 @@ >>>> N1, N0, CarryIn); >>>> >>>> // fold (adde x, y, false) -> (addc x, y) >>>> - if (CarryIn.getOpcode() == ISD::CARRY_FALSE) >>>> - return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N- >>>> >getVTList(), >>>> N1, N0); >>>> + if (ConstantSDNode *N2C = dyn_cast(CarryIn)) >>>> + if (N2C->getAPIntValue()==0) >>>> + return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList >>>> (), N1, N0); >>>> >>>> return SDValue(); >>>> } >>>> >>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ >>>> LegalizeIntegerTypes.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp >>>> (original) >>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp >>>> Mon >>>> Jun 1 18:27:20 2009 >>>> @@ -98,6 +98,10 @@ >>>> case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); >>>> break; >>>> case ISD::SMULO: >>>> case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; >>>> + case ISD::ADDC: >>>> + case ISD::SUBC: Res = PromoteIntRes_ADDSUBC(N, ResNo); >>>> break; >>>> + case ISD::ADDE: >>>> + case ISD::SUBE: Res = PromoteIntRes_ADDSUBE(N, ResNo); >>>> break; >>>> >>>> case ISD::ATOMIC_LOAD_ADD: >>>> case ISD::ATOMIC_LOAD_SUB: >>>> @@ -121,6 +125,35 @@ >>>> SetPromotedInteger(SDValue(N, ResNo), Res); >>>> } >>>> >>>> +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBC(SDNode *N, >>>> unsigned >>>> ResNo) { >>>> + // Only the carry bit result is expected to be promoted. >>>> + assert(ResNo == 1 && "Only carry bit result promotion currently >>>> supported!"); >>>> + return PromoteIntRes_Overflow(N); >>>> +} >>>> + >>>> +SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBE(SDNode *N, >>>> unsigned >>>> ResNo) { >>>> + // Only the carry bit result is expected to be promoted. >>>> + assert(ResNo == 1 && "Only carry bit result promotion currently >>>> supported!"); >>>> + // This is a ternary operator, so clone a slightly modified >>>> + // PromoteIntRes_Overflow here (this is the only client). >>>> + if (ResNo == 1) { >>>> + // Simply change the return type of the boolean result. >>>> + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); >>>> + MVT ValueVTs[] = { N->getValueType(0), NVT }; >>>> + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N- >>>>> getOperand(2) }; >>>> + SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), >>>> + DAG.getVTList(ValueVTs, 2), Ops, 3); >>>> + >>>> + // Modified the sum result - switch anything that used the old >>>> sum to use >>>> + // the new one. >>>> + ReplaceValueWith(SDValue(N, 0), Res); >>>> + >>>> + return SDValue(Res.getNode(), 1); >>>> + } >>>> + assert(0 && "Do not know how to promote this operator!"); >>>> + abort(); >>>> +} >>>> + >>>> SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { >>>> // Sign-extend the new bits, and continue the assertion. >>>> SDValue Op = SExtPromotedInteger(N->getOperand(0)); >>>> @@ -419,7 +452,7 @@ >>>> return Res; >>>> } >>>> >>>> -/// Promote the overflow flag of an overflowing arithmetic node. >>>> +/// Promote the overflow or carry result of an overflowing >>>> arithmetic node. >>>> SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { >>>> // Simply change the return type of the boolean result. >>>> MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); >>>> @@ -666,6 +699,8 @@ >>>> assert(0 && "Do not know how to promote this operator's >>>> operand!"); >>>> abort(); >>>> >>>> + case ISD::ADDE: >>>> + case ISD::SUBE: Res = PromoteIntOp_ADDSUBE(N, OpNo); >>>> break; >>>> case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; >>>> case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; >>>> case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; >>>> @@ -743,6 +778,13 @@ >>>> } >>>> } >>>> >>>> +SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBE(SDNode *N, unsigned >>>> OpNo) { >>>> + assert(OpNo == 2 && "Don't know how to promote this operand!"); >>>> + return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), >>>> + N->getOperand(1), >>>> + GetPromotedInteger(N->getOperand >>>> (2))); >>>> +} >>>> + >>>> SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { >>>> SDValue Op = GetPromotedInteger(N->getOperand(0)); >>>> return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N- >>>>> getValueType(0), Op); >>>> @@ -1063,7 +1105,7 @@ >>>> TLI.isOperationLegalOrCustom(ISD::ADDC, >>>> TLI.getTypeToExpandTo >>>> (NVT))) { >>>> // Emit this X << 1 as X+X. >>>> - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); >>>> + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); >>>> SDValue LoOps[2] = { InL, InL }; >>>> Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); >>>> SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; >>>> @@ -1299,7 +1341,7 @@ >>>> TLI.getTypeToExpandTo(NVT)); >>>> >>>> if (hasCarry) { >>>> - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); >>>> + SDVTList VTList = DAG.getVTList(NVT, MVT::i1); >>>> if (N->getOpcode() == ISD::ADD) { >>>> Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); >>>> HiOps[2] = Lo.getValue(1); >>>> @@ -1344,7 +1386,7 @@ >>>> DebugLoc dl = N->getDebugLoc(); >>>> GetExpandedInteger(N->getOperand(0), LHSL, LHSH); >>>> GetExpandedInteger(N->getOperand(1), RHSL, RHSH); >>>> - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); >>>> + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); >>>> SDValue LoOps[2] = { LHSL, RHSL }; >>>> SDValue HiOps[3] = { LHSH, RHSH }; >>>> >>>> @@ -1358,8 +1400,8 @@ >>>> Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); >>>> } >>>> >>>> - // Legalized the flag result - switch anything that used the old >>>> flag to >>>> - // use the new one. >>>> + // Legalized the second result (carry bit) - switch anything >>>> that >>>> used the >>>> + // result to use the new one. >>>> ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); >>>> } >>>> >>>> @@ -1370,7 +1412,7 @@ >>>> DebugLoc dl = N->getDebugLoc(); >>>> GetExpandedInteger(N->getOperand(0), LHSL, LHSH); >>>> GetExpandedInteger(N->getOperand(1), RHSL, RHSH); >>>> - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); >>>> + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1); >>>> SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; >>>> SDValue HiOps[3] = { LHSH, RHSH }; >>>> >>>> @@ -1378,8 +1420,8 @@ >>>> HiOps[2] = Lo.getValue(1); >>>> Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); >>>> >>>> - // Legalized the flag result - switch anything that used the old >>>> flag to >>>> - // use the new one. >>>> + // Legalized the second result (carry bit) - switch anything >>>> that >>>> used the >>>> + // result to use the new one. >>>> ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); >>>> } >>>> >>>> >>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) >>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Jun 1 >>>> 18:27:20 2009 >>>> @@ -242,6 +242,8 @@ >>>> >>>> // Integer Result Promotion. >>>> void PromoteIntegerResult(SDNode *N, unsigned ResNo); >>>> + SDValue PromoteIntRes_ADDSUBC(SDNode *N, unsigned ResNo); >>>> + SDValue PromoteIntRes_ADDSUBE(SDNode *N, unsigned ResNo); >>>> SDValue PromoteIntRes_AssertSext(SDNode *N); >>>> SDValue PromoteIntRes_AssertZext(SDNode *N); >>>> SDValue PromoteIntRes_Atomic1(AtomicSDNode *N); >>>> @@ -278,6 +280,7 @@ >>>> >>>> // Integer Operand Promotion. >>>> bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo); >>>> + SDValue PromoteIntOp_ADDSUBE(SDNode *N, unsigned OpNo); >>>> SDValue PromoteIntOp_ANY_EXTEND(SDNode *N); >>>> SDValue PromoteIntOp_BIT_CONVERT(SDNode *N); >>>> SDValue PromoteIntOp_BUILD_PAIR(SDNode *N); >>>> >>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ >>>> ScheduleDAGSDNodes.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp >>>> (original) >>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Mon >>>> Jun 1 18:27:20 2009 >>>> @@ -268,6 +268,13 @@ >>>> unsigned N = Node->getNumOperands(); >>>> while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) >>>> --N; >>>> + // Skip hard registers set as a side effect (i.e. not result 0). >>>> + while (N && Node->getOperand(N - 1).getOpcode() == >>>> ISD::CopyToReg >>>> && >>>> + Node->getOperand(N-1).getResNo() != 0 && >>>> + !TargetRegisterInfo::isVirtualRegister( >>>> + dyn_cast(Node->getOperand >>>> (N-1).getOperand(1)) >>>> + ->getReg())) >>>> + --N; >>>> if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) >>>> --N; // Ignore chain if it exists. >>>> return N; >>>> >>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) >>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 1 >>>> 18:27:20 2009 >>>> @@ -5257,7 +5257,6 @@ >>>> case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; >>>> case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; >>>> case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; >>>> - case ISD::CARRY_FALSE: return "carry_false"; >>>> case ISD::ADDC: return "addc"; >>>> case ISD::ADDE: return "adde"; >>>> case ISD::SADDO: return "saddo"; >>>> >>>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) >>>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jun 1 >>>> 18:27:20 2009 >>>> @@ -190,6 +190,28 @@ >>>> setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); >>>> } >>>> >>>> + // ADDE and SUBE are lowered to local versions that contain >>>> EFLAGS explicitly. >>>> + // ADDC and SUBC are lowered to local versions so EFLAGS will be >>>> an i32 >>>> + // rather than the Flag used by the generic patterns. >>>> + setOperationAction(ISD::ADDC , MVT::i8 , Custom); >>>> + setOperationAction(ISD::ADDC , MVT::i16 , Custom); >>>> + setOperationAction(ISD::ADDC , MVT::i32 , Custom); >>>> + setOperationAction(ISD::SUBC , MVT::i8 , Custom); >>>> + setOperationAction(ISD::SUBC , MVT::i16 , Custom); >>>> + setOperationAction(ISD::SUBC , MVT::i32 , Custom); >>>> + setOperationAction(ISD::ADDE , MVT::i8 , Custom); >>>> + setOperationAction(ISD::ADDE , MVT::i16 , Custom); >>>> + setOperationAction(ISD::ADDE , MVT::i32 , Custom); >>>> + setOperationAction(ISD::SUBE , MVT::i8 , Custom); >>>> + setOperationAction(ISD::SUBE , MVT::i16 , Custom); >>>> + setOperationAction(ISD::SUBE , MVT::i32 , Custom); >>>> + if (Subtarget->is64Bit()) { >>>> + setOperationAction(ISD::ADDC , MVT::i64 , >>>> Custom); >>>> + setOperationAction(ISD::SUBC , MVT::i64 , >>>> Custom); >>>> + setOperationAction(ISD::ADDE , MVT::i64 , >>>> Custom); >>>> + setOperationAction(ISD::SUBE , MVT::i64 , >>>> Custom); >>>> + } >>>> + >>>> // Scalar integer divide and remainder are lowered to use >>>> operations that >>>> // produce two results, to match the available instructions. This >>>> exposes >>>> // the two-result form to trivial CSE, which is able to combine x/ >>>> y and x%y >>>> @@ -6475,6 +6497,21 @@ >>>> return Sum; >>>> } >>>> >>>> +SDValue X86TargetLowering::LowerADDSUBE(SDValue Op, SelectionDAG >>>> &DAG) { >>>> + DebugLoc dl = Op.getDebugLoc(); >>>> + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); >>>> + return DAG.getNode(Op.getOpcode()==ISD::ADDE ? X86ISD::ADDE : >>>> X86ISD::SUBE, >>>> + dl, VTs, Op.getOperand(0), Op.getOperand(1), >>>> + Op.getOperand(2).getValue(1)); >>>> +} >>>> + >>>> +SDValue X86TargetLowering::LowerADDSUBC(SDValue Op, SelectionDAG >>>> &DAG) { >>>> + DebugLoc dl = Op.getDebugLoc(); >>>> + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); >>>> + return DAG.getNode(Op.getOpcode()==ISD::ADDC ? X86ISD::ADD : >>>> X86ISD::SUB, >>>> + dl, VTs, Op.getOperand(0), Op.getOperand(1)); >>>> +} >>>> + >>>> SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG >>>> &DAG) { >>>> MVT T = Op.getValueType(); >>>> DebugLoc dl = Op.getDebugLoc(); >>>> @@ -6543,6 +6580,10 @@ >>>> SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG >>>> &DAG) { >>>> switch (Op.getOpcode()) { >>>> default: assert(0 && "Should not custom lower this!"); >>>> + case ISD::ADDC: >>>> + case ISD::SUBC: return LowerADDSUBC(Op,DAG); >>>> + case ISD::ADDE: >>>> + case ISD::SUBE: return LowerADDSUBE(Op,DAG); >>>> case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); >>>> case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); >>>> case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); >>>> @@ -6791,6 +6832,10 @@ >>>> case X86ISD::INC: return "X86ISD::INC"; >>>> case X86ISD::DEC: return "X86ISD::DEC"; >>>> case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; >>>> + case X86ISD::ADDE: return "X86ISD::ADDE"; >>>> + case X86ISD::SUBE: return "X86ISD::SUBE"; >>>> + case X86ISD::ADDC: return "X86ISD::ADDC"; >>>> + case X86ISD::SUBC: return "X86ISD::SUBC"; >>>> } >>>> } >>>> >>>> >>>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) >>>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Jun 1 18:27:20 >>>> 2009 >>>> @@ -243,6 +243,14 @@ >>>> ADD, SUB, SMUL, UMUL, >>>> INC, DEC, >>>> >>>> + // ADDC, SUBC - Arithmetic operations setting carry bit. >>>> The >>>> normal >>>> + // arithmetic operations do this, but they represent it as >>>> Flag, and >>>> + // we want the i32 EFLAGS register here. >>>> + ADDC, SUBC, >>>> + >>>> + // ADDE, SUBE - Arithmetic operations with extra FLAGS >>>> (EFLAGS) inputs. >>>> + ADDE, SUBE, >>>> + >>>> // MUL_IMM - X86 specific multiply by immediate. >>>> MUL_IMM >>>> }; >>>> @@ -576,7 +584,9 @@ >>>> >>>> std::pair FP_TO_INTHelper(SDValue Op, >>>> SelectionDAG &DAG, >>>> bool isSigned); >>>> - >>>> + >>>> + SDValue LowerADDSUBC(SDValue Op, SelectionDAG &DAG); >>>> + SDValue LowerADDSUBE(SDValue Op, SelectionDAG &DAG); >>>> SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); >>>> SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); >>>> SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); >>>> >>>> Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) >>>> +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Mon Jun 1 18:27:20 >>>> 2009 >>>> @@ -383,31 +383,52 @@ >>>> let Uses = [EFLAGS] in { >>>> let isTwoAddress = 1 in { >>>> let isCommutable = 1 in >>>> -def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins >>>> GR64:$src1, GR64:$src2), >>>> +def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), >>>> + (ins GR64:$src1, GR64:$src2), >>>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))] >>>>> ; >>>> + [(set GR64:$dst, >>>> + (X86adde_flag GR64:$src1, GR64:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> >>>> -def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins >>>> GR64:$src1, i64mem:$src2), >>>> +def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), >>>> + (ins GR64:$src1, i64mem: >>>> $src2), >>>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR64:$dst, (adde GR64:$src1, (load addr: >>>> $src2)))]>; >>>> + [(set GR64:$dst, >>>> + (X86adde_flag GR64:$src1, (load addr: >>>> $src2), EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> >>>> -def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins >>>> GR64:$src1, >>>> i64i8imm:$src2), >>>> +def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), >>>> + (ins GR64:$src1, i64i8imm:$src2), >>>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR64:$dst, (adde GR64:$src1, >>>> i64immSExt8:$src2))]>; >>>> -def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins >>>> GR64:$src1, i64i32imm:$src2), >>>> + [(set GR64:$dst, >>>> + (X86adde_flag GR64:$src1, >>>> i64immSExt8:$src2, EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> +def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), >>>> + (ins GR64:$src1, i64i32imm: >>>> $src2), >>>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR64:$dst, (adde GR64:$src1, >>>> i64immSExt32:$src2))]>; >>>> + [(set GR64:$dst, >>>> + (X86adde_flag GR64:$src1, >>>> i64immSExt32:$src2, >>>> + EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> } // isTwoAddress >>>> >>>> def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, >>>> GR64:$src2), >>>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (adde (load addr:$dst), GR64:$src2), >>>> addr: >>>> $dst)]>; >>>> + [(store (X86adde_flag (load addr:$dst), >>>> GR64:$src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, >>>> i64i8imm : >>>> $src2), >>>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (adde (load addr:$dst), >>>> i64immSExt8:$src2), addr:$dst)]>; >>>> + [(store (X86adde_flag (load addr:$dst), >>>> i64immSExt8:$src2, >>>> + EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, >>>> i64i32imm:$src2), >>>> "adc{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (adde (load addr:$dst), >>>> i64immSExt8:$src2), addr:$dst)]>; >>>> + [(store (X86adde_flag (load addr:$dst), >>>> i64immSExt8:$src2, >>>> + EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> } // Uses = [EFLAGS] >>>> >>>> let isTwoAddress = 1 in { >>>> @@ -456,31 +477,52 @@ >>>> >>>> let Uses = [EFLAGS] in { >>>> let isTwoAddress = 1 in { >>>> -def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins >>>> GR64:$src1, GR64:$src2), >>>> +def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), >>>> + (ins GR64:$src1, >>>> GR64:$src2), >>>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR64:$dst, (sube GR64:$src1, >>>> GR64:$src2))] >>>>> ; >>>> + [(set GR64:$dst, >>>> + (X86sube_flag GR64:$src1, GR64:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> >>>> -def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins >>>> GR64:$src1, i64mem:$src2), >>>> +def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), >>>> + (ins GR64:$src1, i64mem:$src2), >>>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR64:$dst, (sube GR64:$src1, (load addr: >>>> $src2)))]>; >>>> + [(set GR64:$dst, >>>> + (X86sube_flag GR64:$src1, (load addr: >>>> $src2), EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> >>>> -def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins >>>> GR64:$src1, >>>> i64i8imm:$src2), >>>> +def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), >>>> + (ins GR64:$src1, i64i8imm:$src2), >>>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR64:$dst, (sube GR64:$src1, >>>> i64immSExt8:$src2))]>; >>>> -def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins >>>> GR64:$src1, i64i32imm:$src2), >>>> + [(set GR64:$dst, >>>> + (X86sube_flag GR64:$src1, >>>> i64immSExt8:$src2, EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> +def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), >>>> + (ins GR64:$src1, i64i32imm: >>>> $src2), >>>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR64:$dst, (sube GR64:$src1, >>>> i64immSExt32:$src2))]>; >>>> + [(set GR64:$dst, >>>> + (X86sube_flag GR64:$src1, >>>> i64immSExt32:$src2, >>>> + EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> } // isTwoAddress >>>> >>>> def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, >>>> GR64:$src2), >>>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (sube (load addr:$dst), GR64:$src2), >>>> addr: >>>> $dst)]>; >>>> + [(store (X86sube_flag (load addr:$dst), >>>> GR64:$src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, >>>> i64i8imm : >>>> $src2), >>>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (sube (load addr:$dst), i64immSExt8:$src2), >>>> addr:$dst)]>; >>>> + [(store (X86sube_flag (load addr:$dst), >>>> i64immSExt8:$src2, >>>> + EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, >>>> i64i32imm:$src2), >>>> "sbb{q}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (sube (load addr:$dst), i64immSExt32:$src2), >>>> addr:$dst)]>; >>>> + [(store (X86sube_flag (load addr:$dst), >>>> i64immSExt32:$src2, >>>> + EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> } // Uses = [EFLAGS] >>>> } // Defs = [EFLAGS] >>>> >>>> >>>> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) >>>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Jun 1 18:27:20 >>>> 2009 >>>> @@ -34,6 +34,11 @@ >>>> [SDTCisSameAs<0, 1>, >>>> SDTCisSameAs<0, 2>, >>>> SDTCisInt<0>]>; >>>> +// Unary and binary operators that both read and write EFLAGS as a >>>> side-effect. >>>> +def SDTBinaryArithRWFlags : SDTypeProfile<1, 3, >>>> + [SDTCisInt<0>, SDTCisSameAs<0, >>>> 1>, >>>> + SDTCisSameAs<0, 2>, SDTCisVT<3, >>>> i32>]>; >>>> + >>>> def SDTX86BrCond : SDTypeProfile<0, 3, >>>> [SDTCisVT<0, OtherVT>, >>>> SDTCisVT<1, i8>, SDTCisVT<2, i32>] >>>>> ; >>>> @@ -156,6 +161,8 @@ >>>> def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>; >>>> def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; >>>> def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; >>>> +def X86adde_flag : SDNode<"X86ISD::ADDE", SDTBinaryArithRWFlags, >>>> [SDNPInI1]>; >>>> +def X86sube_flag : SDNode<"X86ISD::SUBE", SDTBinaryArithRWFlags, >>>> [SDNPInI1]>; >>>> >>>> def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; >>>> >>>> @@ -2274,81 +2281,127 @@ >>>> >>>> let Uses = [EFLAGS] in { >>>> let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y >>>> -def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins >>>> GR8:$src1, >>>> GR8:$src2), >>>> +def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), >>>> + (ins GR8:$src1, GR8:$src2), >>>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>; >>>> + [(set GR8:$dst, (X86adde_flag GR8:$src1, >>>> GR8:$src2, EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst), >>>> (ins GR16:$src1, GR16:$src2), >>>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR16:$dst, (adde GR16:$src1, >>>> GR16:$src2))]>, >>>> OpSize; >>>> + [(set GR16:$dst, >>>> + (X86adde_flag GR16:$src1, GR16:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>, >>>> + OpSize; >>>> def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), >>>> (ins GR32:$src1, GR32:$src2), >>>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR32:$dst, (adde GR32:$src1, >>>> GR32:$src2))]>; >>>> + [(set GR32:$dst, >>>> + (X86adde_flag GR32:$src1, GR32:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> } >>>> def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst), >>>> (ins GR8:$src1, i8mem:$src2), >>>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR8:$dst, (adde GR8:$src1, (load addr: >>>> $src2)))]>; >>>> + [(set GR8:$dst, >>>> + (X86adde_flag GR8:$src1, (load addr:$src2), >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst), >>>> (ins GR16:$src1, i16mem:$src2), >>>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR16:$dst, (adde GR16:$src1, (load addr: >>>> $src2)))]>, >>>> + [(set GR16:$dst, >>>> + (X86adde_flag GR16:$src1, (load addr: >>>> $src2), >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>, >>>> OpSize; >>>> def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), >>>> (ins GR32:$src1, i32mem:$src2), >>>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR32:$dst, (adde GR32:$src1, (load addr: >>>> $src2)))]>; >>>> -def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, >>>> i8imm:$src2), >>>> + [(set GR32:$dst, >>>> + (X86adde_flag GR32:$src1, (load addr: >>>> $src2), >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> +def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), >>>> + (ins GR8:$src1, i8imm:$src2), >>>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>; >>>> + [(set GR8:$dst, >>>> + (X86adde_flag GR8:$src1, imm:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst), >>>> (ins GR16:$src1, i16imm:$src2), >>>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, >>>> OpSize; >>>> + [(set GR16:$dst, >>>> + (X86adde_flag GR16:$src1, imm:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>, OpSize; >>>> def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst), >>>> (ins GR16:$src1, i16i8imm:$src2), >>>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR16:$dst, (adde GR16:$src1, >>>> i16immSExt8:$src2))]>, >>>> - OpSize; >>>> + [(set GR16:$dst, >>>> + (X86adde_flag GR16:$src1, >>>> i16immSExt8:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>, OpSize; >>>> def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), >>>> (ins GR32:$src1, i32imm:$src2), >>>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; >>>> + [(set GR32:$dst, >>>> + (X86adde_flag GR32:$src1, imm:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), >>>> (ins GR32:$src1, i32i8imm:$src2), >>>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR32:$dst, (adde GR32:$src1, >>>> i32immSExt8:$src2))]>; >>>> + [(set GR32:$dst, >>>> + (X86adde_flag GR32:$src1, >>>> i32immSExt8:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> >>>> let isTwoAddress = 0 in { >>>> - def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, >>>> GR8:$src2), >>>> + def ADC8mr : I<0x10, MRMDestMem, (outs), >>>> + (ins i8mem:$dst, GR8:$src2), >>>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (adde (load addr:$dst), GR8:$src2), >>>> addr: >>>> $dst)]>; >>>> - def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, >>>> GR16:$src2), >>>> + [(store (X86adde_flag (load addr:$dst), >>>> GR8:$src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> + def ADC16mr : I<0x11, MRMDestMem, (outs), >>>> + (ins i16mem:$dst, >>>> GR16:$src2), >>>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (adde (load addr:$dst), GR16:$src2), >>>> addr:$dst)]>, >>>> - OpSize; >>>> - def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, >>>> GR32:$src2), >>>> + [(store (X86adde_flag (load addr:$dst), >>>> GR16:$src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>, OpSize; >>>> + def ADC32mr : I<0x11, MRMDestMem, (outs), >>>> + (ins i32mem:$dst, >>>> GR32:$src2), >>>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (adde (load addr:$dst), GR32:$src2), >>>> addr:$dst)]>; >>>> - def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm: >>>> $src2), >>>> + [(store (X86adde_flag (load addr:$dst), >>>> GR32:$src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> + def ADC8mi : Ii8<0x80, MRM2m, (outs), >>>> + (ins i8mem:$dst, i8imm:$src2), >>>> "adc{b}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (adde (loadi8 addr:$dst), imm:$src2), >>>> addr:$dst)]>; >>>> - def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, >>>> i16imm: >>>> $src2), >>>> + [(store (X86adde_flag (loadi8 addr:$dst), imm: >>>> $src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> + def ADC16mi : Ii16<0x81, MRM2m, (outs), >>>> + (ins i16mem:$dst, i16imm: >>>> $src2), >>>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (adde (loadi16 addr:$dst), imm:$src2), >>>> addr:$dst)]>, >>>> - OpSize; >>>> - def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, >>>> i16i8imm :$src2), >>>> + [(store (X86adde_flag (loadi16 addr:$dst), imm: >>>> $src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>, OpSize; >>>> + def ADC16mi8 : Ii8<0x83, MRM2m, (outs), >>>> + (ins i16mem:$dst, i16i8imm : >>>> $src2), >>>> "adc{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (adde (load addr:$dst), i16immSExt8:$src2), >>>> addr:$dst)]>, >>>> - OpSize; >>>> - def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, >>>> i32imm: >>>> $src2), >>>> + [(store (X86adde_flag (load addr:$dst), >>>> i16immSExt8:$src2, >>>> + EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>, OpSize; >>>> + def ADC32mi : Ii32<0x81, MRM2m, (outs), >>>> + (ins i32mem:$dst, i32imm: >>>> $src2), >>>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (adde (loadi32 addr:$dst), imm:$src2), >>>> addr:$dst)]>; >>>> - def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, >>>> i32i8imm :$src2), >>>> + [(store (X86adde_flag (loadi32 addr:$dst), imm: >>>> $src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> + def ADC32mi8 : Ii8<0x83, MRM2m, (outs), >>>> + (ins i32mem:$dst, i32i8imm: >>>> $src2), >>>> "adc{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (adde (load addr:$dst), i32immSExt8:$src2), >>>> addr:$dst)]>; >>>> -} >>>> + [(store (X86adde_flag (load addr:$dst), >>>> i32immSExt8:$src2, >>>> + EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> + } >>>> } // Uses = [EFLAGS] >>>> >>>> // Register-Register Subtraction >>>> @@ -2453,77 +2506,115 @@ >>>> def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst), >>>> (ins GR8:$src1, GR8:$src2), >>>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>; >>>> + [(set GR8:$dst, (X86sube_flag GR8:$src1, >>>> GR8:$src2, EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst), >>>> (ins GR16:$src1, GR16:$src2), >>>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR16:$dst, (sube GR16:$src1, >>>> GR16:$src2))]>, >>>> OpSize; >>>> + [(set GR16:$dst, >>>> + (X86sube_flag GR16:$src1, GR16:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>, OpSize; >>>> def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), >>>> (ins GR32:$src1, GR32:$src2), >>>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR32:$dst, (sube GR32:$src1, >>>> GR32:$src2))]>; >>>> + [(set GR32:$dst, >>>> + (X86sube_flag GR32:$src1, GR32:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> >>>> let isTwoAddress = 0 in { >>>> def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, >>>> GR8:$src2), >>>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (sube (load addr:$dst), GR8:$src2), >>>> addr: >>>> $dst)]>; >>>> + [(store (X86sube_flag (load addr:$dst), >>>> GR8:$src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, >>>> GR16:$src2), >>>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (sube (load addr:$dst), GR16:$src2), >>>> addr:$dst)]>, >>>> + [(store (X86sube_flag (load addr:$dst), >>>> GR16:$src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>, >>>> OpSize; >>>> def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, >>>> GR32:$src2), >>>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (sube (load addr:$dst), GR32:$src2), >>>> addr:$dst)]>; >>>> + [(store (X86sube_flag (load addr:$dst), >>>> GR32:$src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm: >>>> $src2), >>>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (sube (loadi8 addr:$dst), imm:$src2), >>>> addr:$dst)]>; >>>> + [(store (X86sube_flag (loadi8 addr:$dst), imm: >>>> $src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm: >>>> $src2), >>>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (sube (loadi16 addr:$dst), imm:$src2), >>>> addr:$dst)]>, >>>> + [(store (X86sube_flag (loadi16 addr:$dst), imm: >>>> $src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>, >>>> OpSize; >>>> def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, >>>> i16i8imm :$src2), >>>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (sube (load addr:$dst), i16immSExt8:$src2), >>>> addr:$dst)]>, >>>> + [(store (X86sube_flag (load addr:$dst), >>>> i16immSExt8:$src2, >>>> + EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>, >>>> OpSize; >>>> def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm: >>>> $src2), >>>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (sube (loadi32 addr:$dst), imm:$src2), >>>> addr:$dst)]>; >>>> + [(store (X86sube_flag (loadi32 addr:$dst), imm: >>>> $src2, EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, >>>> i32i8imm :$src2), >>>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(store (sube (load addr:$dst), i32immSExt8:$src2), >>>> addr:$dst)]>; >>>> + [(store (X86sube_flag (load addr:$dst), >>>> i32immSExt8:$src2, >>>> + EFLAGS), >>>> + addr:$dst), >>>> + (implicit EFLAGS)]>; >>>> } >>>> def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, >>>> i8mem:$src2), >>>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR8:$dst, (sube GR8:$src1, (load addr: >>>> $src2)))]>; >>>> + [(set GR8:$dst, >>>> + (X86sube_flag GR8:$src1, (load addr: >>>> $src2), EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst), >>>> (ins GR16:$src1, i16mem:$src2), >>>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR16:$dst, (sube GR16:$src1, (load addr: >>>> $src2)))]>, >>>> + [(set GR16:$dst, >>>> + (X86sube_flag GR16:$src1, (load addr: >>>> $src2), EFLAGS)), >>>> + (implicit EFLAGS)]>, >>>> OpSize; >>>> def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), >>>> (ins GR32:$src1, i32mem:$src2), >>>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR32:$dst, (sube GR32:$src1, (load addr: >>>> $src2)))]>; >>>> + [(set GR32:$dst, >>>> + (X86sube_flag GR32:$src1, (load addr: >>>> $src2), EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, >>>> i8imm:$src2), >>>> "sbb{b}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR8:$dst, (sube GR8:$src1, imm: >>>> $src2))]>; >>>> + [(set GR8:$dst, >>>> + (X86sube_flag GR8:$src1, imm:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst), >>>> (ins GR16:$src1, i16imm:$src2), >>>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR16:$dst, (sube GR16:$src1, imm: >>>> $src2))] >>>>> , OpSize; >>>> + [(set GR16:$dst, >>>> + (X86sube_flag GR16:$src1, imm:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>, OpSize; >>>> def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst), >>>> (ins GR16:$src1, i16i8imm:$src2), >>>> "sbb{w}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR16:$dst, (sube GR16:$src1, >>>> i16immSExt8:$src2))]>, >>>> - OpSize; >>>> + [(set GR16:$dst, >>>> + (X86sube_flag GR16:$src1, >>>> i16immSExt8:$src2, EFLAGS)), >>>> + (implicit EFLAGS)]>, OpSize; >>>> def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), >>>> (ins GR32:$src1, i32imm:$src2), >>>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR32:$dst, (sube GR32:$src1, imm: >>>> $src2))]>; >>>> + [(set GR32:$dst, >>>> + (X86sube_flag GR32:$src1, imm:$src2, >>>> EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), >>>> (ins GR32:$src1, i32i8imm:$src2), >>>> "sbb{l}\t{$src2, $dst|$dst, $src2}", >>>> - [(set GR32:$dst, (sube GR32:$src1, >>>> i32immSExt8:$src2))]>; >>>> + [(set GR32:$dst, >>>> + (X86sube_flag GR32:$src1, >>>> i32immSExt8:$src2, EFLAGS)), >>>> + (implicit EFLAGS)]>; >>>> } // Uses = [EFLAGS] >>>> } // Defs = [EFLAGS] >>>> >>>> >>>> Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) >>>> +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Mon Jun 1 >>>> 18:27:20 2009 >>>> @@ -399,9 +399,13 @@ >>>> } else if (PropList[i]->getName() == "SDNPHasChain") { >>>> Properties |= 1 << SDNPHasChain; >>>> } else if (PropList[i]->getName() == "SDNPOutFlag") { >>>> - Properties |= 1 << SDNPOutFlag; >>>> + Properties |= 1 << SDNPOutFlag; >>>> + assert(!(Properties & (1<>>> + "Can't handle OutFlag and OutI1"); >>>> } else if (PropList[i]->getName() == "SDNPInFlag") { >>>> Properties |= 1 << SDNPInFlag; >>>> + assert(!(Properties & (1<>>> + "Can't handle InFlag and InI1"); >>>> } else if (PropList[i]->getName() == "SDNPOptInFlag") { >>>> Properties |= 1 << SDNPOptInFlag; >>>> } else if (PropList[i]->getName() == "SDNPMayStore") { >>>> @@ -412,6 +416,14 @@ >>>> Properties |= 1 << SDNPSideEffect; >>>> } else if (PropList[i]->getName() == "SDNPMemOperand") { >>>> Properties |= 1 << SDNPMemOperand; >>>> + } else if (PropList[i]->getName() == "SDNPInI1") { >>>> + Properties |= 1 << SDNPInI1; >>>> + assert(!(Properties & (1<>>> + "Can't handle InFlag and InI1"); >>>> + } else if (PropList[i]->getName() == "SDNPOutI1") { >>>> + Properties |= 1 << SDNPOutI1; >>>> + assert(!(Properties & (1<>>> + "Can't handle OutFlag and OutI1"); >>>> } else { >>>> cerr << "Unknown SD Node property '" << PropList[i]->getName() >>>> << "' on node '" << R->getName() << "'!\n"; >>>> >>>> Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) >>>> +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Jun 1 18:27:20 >>>> 2009 >>>> @@ -385,6 +385,13 @@ >>>> return getInstructionSet()- >>>> >getValueAsBit("isLittleEndianEncoding"); >>>> } >>>> >>>> +/// supportsHasI1 - Return whether this target supports the >>>> implicit I1, >>>> +/// rather than Flags, for ADDC/ADDE >>>> +/// >>>> +bool CodeGenTarget::supportsHasI1() const { >>>> + return getInstructionSet()->getValueAsBit("supportsHasI1"); >>>> +} >>>> + >>>> // >>>> = >>>> = >>>> = >>>> ----------------------------------------------------------------------= >>>> ==// >>>> // ComplexPattern implementation >>>> // >>>> >>>> Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/utils/TableGen/CodeGenTarget.h (original) >>>> +++ llvm/trunk/utils/TableGen/CodeGenTarget.h Mon Jun 1 18:27:20 >>>> 2009 >>>> @@ -43,7 +43,9 @@ >>>> SDNPMayLoad, >>>> SDNPMayStore, >>>> SDNPSideEffect, >>>> - SDNPMemOperand >>>> + SDNPMemOperand, >>>> + SDNPInI1, >>>> + SDNPOutI1 >>>> }; >>>> >>>> // ComplexPattern attributes. >>>> @@ -209,10 +211,12 @@ >>>> void getInstructionsByEnumValue(std::vector>>> CodeGenInstruction*> >>>> >>>> &NumberedInstructions); >>>> >>>> - >>>> /// isLittleEndianEncoding - are instruction bit patterns defined >>>> as [0..n]? >>>> /// >>>> bool isLittleEndianEncoding() const; >>>> + >>>> + /// supportsHasI1 - does this target understand HasI1 for ADDE >>>> and ADDC? >>>> + bool supportsHasI1() const; >>>> }; >>>> >>>> /// ComplexPattern - ComplexPattern info, corresponding to the >>>> ComplexPattern >>>> >>>> Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=72707&r1=72706&r2=72707&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) >>>> +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Jun 1 >>>> 18:27:20 >>>> 2009 >>>> @@ -670,7 +670,8 @@ >>>> HasChain = true; >>>> FoldedChains.push_back(std::make_pair(RootName, >>>> CInfo.getNumResults())); >>>> } >>>> - if (NodeHasProperty(Child, SDNPOutFlag, CGP)) { >>>> + if (NodeHasProperty(Child, SDNPOutFlag, CGP) || >>>> + NodeHasProperty(Child, SDNPOutI1, CGP)) { >>>> assert(FoldedFlag.first == "" && FoldedFlag.second == 0 && >>>> "Pattern folded multiple nodes which produce flags?"); >>>> FoldedFlag = std::make_pair(RootName, >>>> @@ -969,6 +970,10 @@ >>>> PatternHasProperty(Pattern, SDNPInFlag, CGP); >>>> bool NodeHasOutFlag = isRoot && >>>> PatternHasProperty(Pattern, SDNPOutFlag, CGP); >>>> + bool NodeHasInI1 = isRoot && >>>> + PatternHasProperty(Pattern, SDNPInI1, CGP); >>>> + bool NodeHasOutI1 = isRoot && >>>> + PatternHasProperty(Pattern, SDNPOutI1, CGP); >>>> bool NodeHasChain = InstPatNode && >>>> PatternHasProperty(InstPatNode, SDNPHasChain, CGP); >>>> bool InputHasChain = isRoot && >>>> @@ -1054,10 +1059,13 @@ >>>> >>>> // Emit all the chain and CopyToReg stuff. >>>> bool ChainEmitted = NodeHasChain; >>>> - if (NodeHasInFlag || HasImpInputs) >>>> + // InFlag and InI1 cannot both be set (checked in >>>> + // CodeGenDAGPatterns), so use the same variables for both. >>>> + if (NodeHasInFlag || HasImpInputs || NodeHasInI1) >>>> EmitInFlagSelectCode(Pattern, "N", ChainEmitted, >>>> InFlagDecled, ResNodeDecled, true); >>>> - if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs) { >>>> + if (NodeHasOptInFlag || NodeHasInFlag || HasImpInputs || >>>> + NodeHasInI1) { >>>> if (!InFlagDecled) { >>>> emitCode("SDValue InFlag(0, 0);"); >>>> InFlagDecled = true; >>>> @@ -1113,7 +1121,7 @@ >>>> } >>>> if (NodeHasChain) >>>> Code += ", MVT::Other"; >>>> - if (NodeHasOutFlag) >>>> + if (NodeHasOutFlag || (NodeHasOutI1 && ! >>>> CGT.supportsHasI1())) >>>> Code += ", MVT::Flag"; >>>> >>>> // Inputs. >>>> @@ -1173,7 +1181,8 @@ >>>> } >>>> Code += ", &Ops" + utostr(OpsNo) + "[0], Ops" + utostr >>>> (OpsNo) + >>>> ".size()"; >>>> - } else if (NodeHasInFlag || NodeHasOptInFlag || >>>> HasImpInputs) >>>> + } else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs >>>> || >>>> + NodeHasInI1) >>>> AllOps.push_back("InFlag"); >>>> >>>> unsigned NumOps = AllOps.size(); >>>> @@ -1207,7 +1216,7 @@ >>>> NodeOps.push_back("Tmp" + utostr(ResNo)); >>>> } else { >>>> >>>> - if (NodeHasOutFlag) { >>>> + if (NodeHasOutFlag || NodeHasOutI1) { >>>> if (!InFlagDecled) { >>>> After.push_back("SDValue InFlag(ResNode, " + >>>> utostr(NumResults+NumDstRegs+(unsigned) >>>> NodeHasChain) + >>>> @@ -1228,13 +1237,15 @@ >>>> utostr(NumResults+NumDstRegs) + ")"); >>>> } >>>> >>>> - if (NodeHasOutFlag) { >>>> + if (NodeHasOutFlag || NodeHasOutI1) { >>>> if (FoldedFlag.first != "") { >>>> - ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + >>>> ".getNode(), " + >>>> + ReplaceFroms.push_back("SDValue(" + FoldedFlag.first + >>>> + ".getNode(), " + >>>> utostr(FoldedFlag.second) + ")"); >>>> ReplaceTos.push_back("InFlag"); >>>> } else { >>>> - assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP)); >>>> + assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP) || >>>> + NodeHasProperty(Pattern, SDNPOutI1, CGP)); >>>> ReplaceFroms.push_back("SDValue(N.getNode(), " + >>>> utostr(NumPatResults + (unsigned) >>>> InputHasChain) >>>> + ")"); >>>> @@ -1251,7 +1262,8 @@ >>>> } >>>> >>>> // User does not expect the instruction would produce a chain! >>>> - if ((!InputHasChain && NodeHasChain) && NodeHasOutFlag) { >>>> + if ((!InputHasChain && NodeHasChain) && >>>> + (NodeHasOutFlag || NodeHasOutI1)) { >>>> ; >>>> } else if (InputHasChain && !NodeHasChain) { >>>> // One of the inner node produces a chain. >>>> @@ -1391,6 +1403,8 @@ >>>> unsigned OpNo = >>>> (unsigned) NodeHasProperty(N, SDNPHasChain, CGP); >>>> bool HasInFlag = NodeHasProperty(N, SDNPInFlag, CGP); >>>> + bool HasInI1 = NodeHasProperty(N, SDNPInI1, CGP); >>>> + bool InFlagDefined = false; >>>> for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, + >>>> +OpNo) { >>>> TreePatternNode *Child = N->getChild(i); >>>> if (!Child->isLeaf()) { >>>> @@ -1424,21 +1438,41 @@ >>>> emitCode("SDValue InFlag(0, 0);"); >>>> InFlagDecled = true; >>>> } >>>> - std::string Decl = (!ResNodeDecled) ? "SDNode *" : >>>> ""; >>>> - emitCode(Decl + "ResNode = CurDAG->getCopyToReg(" + >>>> ChainName + >>>> + if (HasInI1) { >>>> + if (!ResNodeDecled) { >>>> + emitCode("SDNode * ResNode;"); >>>> + } >>>> + if (T.supportsHasI1()) >>>> + emitCode("ResNode = CurDAG->getCopyToReg(" + >>>> ChainName + >>>> + ", " + RootName + ".getDebugLoc()" + >>>> + ", " + getEnumName(RVT) + >>>> + ", " + getQualifiedName(RR) + >>>> + ", " + RootName + utostr(OpNo) + >>>> ").getNode();"); >>>> + else >>>> + emitCode("ResNode = CurDAG->getCopyToReg(" + >>>> ChainName + >>>> + ", " + RootName + ".getDebugLoc()" + >>>> + ", " + getQualifiedName(RR) + >>>> + ", " + RootName + utostr(OpNo) + >>>> + ", InFlag).getNode();"); >>>> + InFlagDefined = true; >>>> + } else { >>>> + std::string Decl = (!ResNodeDecled) ? "SDNode *" : >>>> ""; >>>> + emitCode(Decl + "ResNode = CurDAG- >>>> >getCopyToReg(" + >>>> ChainName + >>>> ", " + RootName + ".getDebugLoc()" + >>>> ", " + getQualifiedName(RR) + >>>> - ", " + RootName + utostr(OpNo) + ", >>>> InFlag).getNode();"); >>>> - ResNodeDecled = true; >>>> + ", " + RootName + utostr(OpNo) + >>>> + ", InFlag).getNode();"); >>>> + } >>>> emitCode(ChainName + " = SDValue(ResNode, 0);"); >>>> emitCode("InFlag = SDValue(ResNode, 1);"); >>>> + ResNodeDecled = true; >>>> } >>>> } >>>> } >>>> } >>>> } >>>> >>>> - if (HasInFlag) { >>>> + if (HasInFlag || (HasInI1 && !InFlagDefined)) { >>>> if (!InFlagDecled) { >>>> emitCode("SDValue InFlag = " + RootName + >>>> ".getOperand(" + utostr(OpNo) + ");"); >>>> >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Tue Jun 2 16:29:13 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 02 Jun 2009 21:29:13 -0000 Subject: [llvm-commits] [llvm] r72739 - in /llvm/trunk: lib/Transforms/Scalar/CodeGenPrepare.cpp test/CodeGen/X86/codegen-prepare-cast.ll Message-ID: <200906022129.n52LTETL032270@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 2 16:29:13 2009 New Revision: 72739 URL: http://llvm.org/viewvc/llvm-project?rev=72739&view=rev Log: Fix CodeGenPrepare's address-mode sinking to handle unusual addresses, involving Base values which do not have Pointer type. This fixes PR4297. Added: llvm/trunk/test/CodeGen/X86/codegen-prepare-cast.ll Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=72739&r1=72738&r2=72739&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Tue Jun 2 16:29:13 2009 @@ -624,8 +624,11 @@ // Add in the base register. if (AddrMode.BaseReg) { Value *V = AddrMode.BaseReg; - if (V->getType() != IntPtrTy) + if (isa(V->getType())) V = new PtrToIntInst(V, IntPtrTy, "sunkaddr", InsertPt); + if (V->getType() != IntPtrTy) + V = CastInst::CreateIntegerCast(V, IntPtrTy, /*isSigned=*/true, + "sunkaddr", InsertPt); if (Result) Result = BinaryOperator::CreateAdd(Result, V, "sunkaddr", InsertPt); else Added: llvm/trunk/test/CodeGen/X86/codegen-prepare-cast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/codegen-prepare-cast.ll?rev=72739&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/codegen-prepare-cast.ll (added) +++ llvm/trunk/test/CodeGen/X86/codegen-prepare-cast.ll Tue Jun 2 16:29:13 2009 @@ -0,0 +1,24 @@ +; RUN: llvm-as < %s | llc -march=x86-64 +; PR4297 + +target datalayout = +"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + %"byte[]" = type { i64, i8* } + %"char[][]" = type { i64, %"byte[]"* } + at .str = external constant [7 x i8] ; <[7 x i8]*> [#uses=1] + +define fastcc i32 @_Dmain(%"char[][]" %unnamed) { +entry: + %tmp = getelementptr [7 x i8]* @.str, i32 0, i32 0 ; [#uses=1] + br i1 undef, label %foreachbody, label %foreachend + +foreachbody: ; preds = %entry + %tmp4 = getelementptr i8* %tmp, i32 undef ; [#uses=1] + %tmp5 = load i8* %tmp4 ; [#uses=0] + unreachable + +foreachend: ; preds = %entry + ret i32 0 +} + From gohman at apple.com Tue Jun 2 16:37:49 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 02 Jun 2009 21:37:49 -0000 Subject: [llvm-commits] [llvm] r72740 - /llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h Message-ID: <200906022137.n52LboPo032599@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 2 16:37:43 2009 New Revision: 72740 URL: http://llvm.org/viewvc/llvm-project?rev=72740&view=rev Log: Delete an unnecessary forward declaration. Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h?rev=72740&r1=72739&r2=72740&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h Tue Jun 2 16:37:43 2009 @@ -19,7 +19,6 @@ namespace llvm { class ConstantInt; class ConstantRange; - class APInt; class DominatorTree; enum SCEVTypes { From devang.patel at gmail.com Tue Jun 2 16:43:03 2009 From: devang.patel at gmail.com (Devang Patel) Date: Tue, 2 Jun 2009 14:43:03 -0700 Subject: [llvm-commits] [llvm] r70270 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Alpha/AsmPrinter/ lib In-Reply-To: <236B22EC-8D07-4655-951B-9FF060A5FEAD@apple.com> References: <352a1fb20906021032tb1909afn3c2e0eb8818f0d82@mail.gmail.com> <236B22EC-8D07-4655-951B-9FF060A5FEAD@apple.com> Message-ID: <352a1fb20906021443g6317857eoa5ac7c89ff8cb29a@mail.gmail.com> On Tue, Jun 2, 2009 at 1:59 PM, Evan Cheng wrote: > > On Jun 2, 2009, at 10:32 AM, Devang Patel wrote: > >> We already use a function attribute for -Os. Why not do the same here >> ? > > This controls what codegen passes are being run. It's done once for > the whole compilation. This info should be encoded in bc files so that we don't have to remember passing additional command line option on llc (and other tools that operate on bc files). BTW, -Os is also applied to entire compilation unit. - Devang > Function notes are for finer grain control that > tell these passes to "behave" differently for individual functions. > Yes, we could use function notes to control optimization level for > individual functions. But I view that as a different issue. From gohman at apple.com Tue Jun 2 16:48:44 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 02 Jun 2009 21:48:44 -0000 Subject: [llvm-commits] [llvm] r72741 - in /llvm/trunk: include/llvm/Analysis/ConstantFolding.h lib/Analysis/ConstantFolding.cpp Message-ID: <200906022148.n52Lmpem000499@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 2 16:48:15 2009 New Revision: 72741 URL: http://llvm.org/viewvc/llvm-project?rev=72741&view=rev Log: Change ConstantFoldConstantExpression to accept a null TargetData pointer. The only thing it's used for are calls to ConstantFoldCompareInstOperands and ConstantFoldInstOperands, which both already accept a null TargetData pointer. This makes ConstantFoldConstantExpression easier to use in clients where TargetData is optional. Modified: llvm/trunk/include/llvm/Analysis/ConstantFolding.h llvm/trunk/lib/Analysis/ConstantFolding.cpp Modified: llvm/trunk/include/llvm/Analysis/ConstantFolding.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ConstantFolding.h?rev=72741&r1=72740&r2=72741&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ConstantFolding.h (original) +++ llvm/trunk/include/llvm/Analysis/ConstantFolding.h Tue Jun 2 16:48:15 2009 @@ -34,7 +34,7 @@ /// using the specified TargetData. If successful, the constant result is /// result is returned, if not, null is returned. Constant *ConstantFoldConstantExpression(ConstantExpr *CE, - const TargetData *TD); + const TargetData *TD = 0); /// ConstantFoldInstOperands - Attempt to constant fold an instruction with the /// specified operands. If successful, the constant result is returned, if not, Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=72741&r1=72740&r2=72741&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Tue Jun 2 16:48:15 2009 @@ -317,8 +317,6 @@ /// result is returned, if not, null is returned. Constant *llvm::ConstantFoldConstantExpression(ConstantExpr *CE, const TargetData *TD) { - assert(TD && "ConstantFoldConstantExpression requires a valid TargetData."); - SmallVector Ops; for (User::op_iterator i = CE->op_begin(), e = CE->op_end(); i != e; ++i) Ops.push_back(cast(*i)); From gohman at apple.com Tue Jun 2 19:13:49 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 03 Jun 2009 00:13:49 -0000 Subject: [llvm-commits] [llvm] r72744 - /llvm/trunk/include/llvm/Support/TargetFolder.h Message-ID: <200906030013.n530DnWD005474@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 2 19:13:48 2009 New Revision: 72744 URL: http://llvm.org/viewvc/llvm-project?rev=72744&view=rev Log: Change TargetFolder's TD member from a reference to a pointer, now that ConstantFoldConstantExpression can accept a null TargetData pointer. Modified: llvm/trunk/include/llvm/Support/TargetFolder.h Modified: llvm/trunk/include/llvm/Support/TargetFolder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetFolder.h?rev=72744&r1=72743&r2=72744&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/TargetFolder.h (original) +++ llvm/trunk/include/llvm/Support/TargetFolder.h Tue Jun 2 19:13:48 2009 @@ -9,8 +9,10 @@ // // This file defines the TargetFolder class, a helper for IRBuilder. // It provides IRBuilder with a set of methods for creating constants with -// target dependent folding. For general constant creation and folding, -// use ConstantExpr and the routines in llvm/Analysis/ConstantFolding.h. +// target dependent folding, in addition to the same target-independent +// folding that the ConstantFolder class provides. For general constant +// creation and folding, use ConstantExpr and the routines in +// llvm/Analysis/ConstantFolding.h. // //===----------------------------------------------------------------------===// @@ -26,18 +28,18 @@ /// TargetFolder - Create constants with target dependent folding. class TargetFolder { - const TargetData &TD; + const TargetData *TD; /// Fold - Fold the constant using target specific information. Constant *Fold(Constant *C) const { if (ConstantExpr *CE = dyn_cast(C)) - if (Constant *CF = ConstantFoldConstantExpression(CE, &TD)) + if (Constant *CF = ConstantFoldConstantExpression(CE, TD)) return CF; return C; } public: - TargetFolder(const TargetData &TheTD) : TD(TheTD) {} + explicit TargetFolder(const TargetData *TheTD) : TD(TheTD) {} //===--------------------------------------------------------------------===// // Binary Operators From gohman at apple.com Tue Jun 2 19:13:54 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 03 Jun 2009 00:13:54 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r72745 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Message-ID: <200906030013.n530DsTe005489@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 2 19:13:54 2009 New Revision: 72745 URL: http://llvm.org/viewvc/llvm-project?rev=72745&view=rev Log: Update for the TargetFolder API change. Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=72745&r1=72744&r2=72745&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Tue Jun 2 19:13:54 2009 @@ -433,7 +433,7 @@ TheTarget = TME->CtorFn(*TheModule, FeatureStr); assert(TheTarget->getTargetData()->isBigEndian() == BYTES_BIG_ENDIAN); - TheFolder = new TargetFolder(*TheTarget->getTargetData()); + TheFolder = new TargetFolder(TheTarget->getTargetData()); // Install information about target datalayout stuff into the module for // optimizer use. From gohman at apple.com Tue Jun 2 19:37:21 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 03 Jun 2009 00:37:21 -0000 Subject: [llvm-commits] [llvm] r72746 - in /llvm/trunk: lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/abi-isel.ll test/CodeGen/X86/ga-offset.ll test/CodeGen/X86/x86-store-gv-addr.ll Message-ID: <200906030037.n530bLxK006290@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 2 19:37:20 2009 New Revision: 72746 URL: http://llvm.org/viewvc/llvm-project?rev=72746&view=rev Log: Revert r72734. The Darwin assembler doesn't support the static relocation model on x86-64. Higher level logic should override the relocation model to PIC on x86_64-apple-darwin. Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/CodeGen/X86/abi-isel.ll llvm/trunk/test/CodeGen/X86/ga-offset.ll llvm/trunk/test/CodeGen/X86/x86-store-gv-addr.ll Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=72746&r1=72745&r2=72746&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Jun 2 19:37:20 2009 @@ -1399,16 +1399,16 @@ def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), (MOV64mi32 addr:$dst, tconstpool:$src)>, - Requires<[SmallCode, IsStatic, IsNotDarwin]>; + Requires<[SmallCode, IsStatic]>; def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), (MOV64mi32 addr:$dst, tjumptable:$src)>, - Requires<[SmallCode, IsStatic, IsNotDarwin]>; + Requires<[SmallCode, IsStatic]>; def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), (MOV64mi32 addr:$dst, tglobaladdr:$src)>, - Requires<[SmallCode, IsStatic, IsNotDarwin]>; + Requires<[SmallCode, IsStatic]>; def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), (MOV64mi32 addr:$dst, texternalsym:$src)>, - Requires<[SmallCode, IsStatic, IsNotDarwin]>; + Requires<[SmallCode, IsStatic]>; // Calls // Direct PC relative function call for small code model. 32-bit displacement Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=72746&r1=72745&r2=72746&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Jun 2 19:37:20 2009 @@ -237,7 +237,6 @@ def OptForSpeed : Predicate<"!OptForSize">; def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; -def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; //===----------------------------------------------------------------------===// // X86 Instruction Format Definitions. Modified: llvm/trunk/test/CodeGen/X86/abi-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/abi-isel.ll?rev=72746&r1=72745&r2=72746&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/abi-isel.ll (original) +++ llvm/trunk/test/CodeGen/X86/abi-isel.ll Tue Jun 2 19:37:20 2009 @@ -146,7 +146,7 @@ ; RUN: grep movl %t | count 91 ; RUN: not grep addl %t ; RUN: not grep subl %t -; RUN: grep leaq %t | count 81 +; RUN: grep leaq %t | count 70 ; RUN: grep movq %t | count 56 ; RUN: grep addq %t | count 20 ; RUN: grep subq %t | count 14 @@ -160,7 +160,7 @@ ; RUN: not grep @PLT %t ; RUN: not grep @PLTOFF %t ; RUN: grep {call \\\*} %t | count 10 -; RUN: grep {%rip} %t | count 150 +; RUN: grep {%rip} %t | count 139 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small > %t ; RUN: not grep leal %t ; RUN: grep movl %t | count 95 Modified: llvm/trunk/test/CodeGen/X86/ga-offset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ga-offset.ll?rev=72746&r1=72745&r2=72746&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/ga-offset.ll (original) +++ llvm/trunk/test/CodeGen/X86/ga-offset.ll Tue Jun 2 19:37:20 2009 @@ -2,7 +2,7 @@ ; RUN: not grep lea %t ; RUN: not grep add %t ; RUN: grep mov %t | count 1 -; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu -relocation-model=static > %t +; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=static > %t ; RUN: not grep lea %t ; RUN: not grep add %t ; RUN: grep mov %t | count 1 Modified: llvm/trunk/test/CodeGen/X86/x86-store-gv-addr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-store-gv-addr.ll?rev=72746&r1=72745&r2=72746&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/x86-store-gv-addr.ll (original) +++ llvm/trunk/test/CodeGen/X86/x86-store-gv-addr.ll Tue Jun 2 19:37:20 2009 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=static | grep lea +; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=static | not grep lea ; RUN: llvm-as < %s | llc -mtriple=x86_64-pc-linux-gnu -relocation-model=static | not grep lea @v = external global i32, align 8 From bruno.cardoso at gmail.com Tue Jun 2 22:43:31 2009 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 03 Jun 2009 03:43:31 -0000 Subject: [llvm-commits] [llvm] r72754 - in /llvm/trunk/lib/CodeGen: MachO.h MachOCodeEmitter.cpp MachOCodeEmitter.h MachOWriter.cpp MachOWriter.h Message-ID: <200906030343.n533hWvb012513@zion.cs.uiuc.edu> Author: bruno Date: Tue Jun 2 22:43:31 2009 New Revision: 72754 URL: http://llvm.org/viewvc/llvm-project?rev=72754&view=rev Log: Move structures and classes into header files, providing two new headers and one new .cpp file, in preparation for merging in the Direct Object Emission changes we're working on. No functional changes. Fixed coding style issues on the original patch. Patch by Aaron Gray Added: llvm/trunk/lib/CodeGen/MachO.h llvm/trunk/lib/CodeGen/MachOCodeEmitter.cpp llvm/trunk/lib/CodeGen/MachOCodeEmitter.h Modified: llvm/trunk/lib/CodeGen/MachOWriter.cpp llvm/trunk/lib/CodeGen/MachOWriter.h Added: llvm/trunk/lib/CodeGen/MachO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachO.h?rev=72754&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/MachO.h (added) +++ llvm/trunk/lib/CodeGen/MachO.h Tue Jun 2 22:43:31 2009 @@ -0,0 +1,423 @@ +//=== MachO.h - Mach-O structures and constants -----------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines MachO . +// +//===----------------------------------------------------------------------===// + +#ifndef MACHO_H +#define MACHO_H + +#include "llvm/Constants.h" +#include "llvm/DerivedTypes.h" +#include "llvm/CodeGen/MachineRelocation.h" +#include "llvm/Target/TargetAsmInfo.h" +#include +#include + +namespace llvm { + +typedef std::vector DataBuffer; + +/// MachOSym - This struct contains information about each symbol that is +/// added to logical symbol table for the module. This is eventually +/// turned into a real symbol table in the file. +struct MachOSym { + const GlobalValue *GV; // The global value this corresponds to. + std::string GVName; // The mangled name of the global value. + uint32_t n_strx; // index into the string table + uint8_t n_type; // type flag + uint8_t n_sect; // section number or NO_SECT + int16_t n_desc; // see + uint64_t n_value; // value for this symbol (or stab offset) + + // Constants for the n_sect field + // see + enum { NO_SECT = 0 }; // symbol is not in any section + + // Constants for the n_type field + // see + enum { N_UNDF = 0x0, // undefined, n_sect == NO_SECT + N_ABS = 0x2, // absolute, n_sect == NO_SECT + N_SECT = 0xe, // defined in section number n_sect + N_PBUD = 0xc, // prebound undefined (defined in a dylib) + N_INDR = 0xa // indirect + }; + // The following bits are OR'd into the types above. For example, a type + // of 0x0f would be an external N_SECT symbol (0x0e | 0x01). + enum { N_EXT = 0x01, // external symbol bit + N_PEXT = 0x10 // private external symbol bit + }; + + // Constants for the n_desc field + // see + enum { REFERENCE_FLAG_UNDEFINED_NON_LAZY = 0, + REFERENCE_FLAG_UNDEFINED_LAZY = 1, + REFERENCE_FLAG_DEFINED = 2, + REFERENCE_FLAG_PRIVATE_DEFINED = 3, + REFERENCE_FLAG_PRIVATE_UNDEFINED_NON_LAZY = 4, + REFERENCE_FLAG_PRIVATE_UNDEFINED_LAZY = 5 + }; + enum { N_NO_DEAD_STRIP = 0x0020, // symbol is not to be dead stripped + N_WEAK_REF = 0x0040, // symbol is weak referenced + N_WEAK_DEF = 0x0080 // coalesced symbol is a weak definition + }; + + MachOSym(const GlobalValue *gv, std::string name, uint8_t sect, + const TargetAsmInfo *TAI); + + struct SymCmp { + // FIXME: this does not appear to be sorting 'f' after 'F' + bool operator()(const MachOSym &LHS, const MachOSym &RHS) { + return LHS.GVName < RHS.GVName; + } + }; + + + /// PartitionByLocal - Simple boolean predicate that returns true if Sym is + /// a local symbol rather than an external symbol. + + static inline bool PartitionByLocal(const MachOSym &Sym) { + return (Sym.n_type & (MachOSym::N_EXT | MachOSym::N_PEXT)) == 0; + } + + /// PartitionByDefined - Simple boolean predicate that returns true if Sym is + /// defined in this module. + + static inline bool PartitionByDefined(const MachOSym &Sym) { + // FIXME: Do N_ABS or N_INDR count as defined? + return (Sym.n_type & MachOSym::N_SECT) == MachOSym::N_SECT; + } + +}; // end struct MachOSym + +/// MachOHeader - This struct contains the header information about a +/// specific architecture type/subtype pair that is emitted to the file. + +struct MachOHeader { + uint32_t magic; // mach magic number identifier + uint32_t filetype; // type of file + uint32_t ncmds; // number of load commands + uint32_t sizeofcmds; // the size of all the load commands + uint32_t flags; // flags + uint32_t reserved; // 64-bit only + + /// HeaderData - The actual data for the header which we are building + /// up for emission to the file. + DataBuffer HeaderData; + + // Constants for the filetype field + // see for additional info on the various types + enum { MH_OBJECT = 1, // relocatable object file + MH_EXECUTE = 2, // demand paged executable file + MH_FVMLIB = 3, // fixed VM shared library file + MH_CORE = 4, // core file + MH_PRELOAD = 5, // preloaded executable file + MH_DYLIB = 6, // dynamically bound shared library + MH_DYLINKER = 7, // dynamic link editor + MH_BUNDLE = 8, // dynamically bound bundle file + MH_DYLIB_STUB = 9, // shared library stub for static linking only + MH_DSYM = 10 // companion file wiht only debug sections + }; + + // Constants for the flags field + enum { MH_NOUNDEFS = 1 << 0, + // the object file has no undefined references + MH_INCRLINK = 1 << 1, + // the object file is the output of an incremental link against + // a base file and cannot be link edited again + MH_DYLDLINK = 1 << 2, + // the object file is input for the dynamic linker and cannot be + // statically link edited again. + MH_BINDATLOAD = 1 << 3, + // the object file's undefined references are bound by the + // dynamic linker when loaded. + MH_PREBOUND = 1 << 4, + // the file has its dynamic undefined references prebound + MH_SPLIT_SEGS = 1 << 5, + // the file has its read-only and read-write segments split + // see + MH_LAZY_INIT = 1 << 6, + // the shared library init routine is to be run lazily via + // catching memory faults to its writable segments (obsolete) + MH_TWOLEVEL = 1 << 7, + // the image is using two-level namespace bindings + MH_FORCE_FLAT = 1 << 8, + // the executable is forcing all images to use flat namespace + // bindings. + MH_NOMULTIDEFS = 1 << 8, + // this umbrella guarantees no multiple definitions of symbols + // in its sub-images so the two-level namespace hints can + // always be used. + MH_NOFIXPREBINDING = 1 << 10, + // do not have dyld notify the prebidning agent about this + // executable. + MH_PREBINDABLE = 1 << 11, + // the binary is not prebound but can have its prebinding + // redone. only used when MH_PREBOUND is not set. + MH_ALLMODSBOUND = 1 << 12, + // indicates that this binary binds to all two-level namespace + // modules of its dependent libraries. Only used when + // MH_PREBINDABLE and MH_TWOLEVEL are both set. + MH_SUBSECTIONS_VIA_SYMBOLS = 1 << 13, + // safe to divide up the sections into sub-sections via symbols + // for dead code stripping. + MH_CANONICAL = 1 << 14, + // the binary has been canonicalized via the unprebind operation + MH_WEAK_DEFINES = 1 << 15, + // the final linked image contains external weak symbols + MH_BINDS_TO_WEAK = 1 << 16, + // the final linked image uses weak symbols + MH_ALLOW_STACK_EXECUTION = 1 << 17 + // When this bit is set, all stacks in the task will be given + // stack execution privilege. Only used in MH_EXECUTE filetype + }; + + MachOHeader() : magic(0), filetype(0), ncmds(0), sizeofcmds(0), flags(0), + reserved(0) { } + + /// cmdSize - This routine returns the size of the MachOSection as written + /// to disk, depending on whether the destination is a 64 bit Mach-O file. + unsigned cmdSize(bool is64Bit) const { + if (is64Bit) + return 8 * sizeof(uint32_t); + else + return 7 * sizeof(uint32_t); + } + + /// setMagic - This routine sets the appropriate value for the 'magic' + /// field based on pointer size and endianness. + void setMagic(bool isLittleEndian, bool is64Bit) { + if (isLittleEndian) + if (is64Bit) magic = 0xcffaedfe; + else magic = 0xcefaedfe; + else + if (is64Bit) magic = 0xfeedfacf; + else magic = 0xfeedface; + } + +}; // end struct MachOHeader + +/// MachOSegment - This struct contains the necessary information to +/// emit the load commands for each section in the file. +struct MachOSegment { + uint32_t cmd; // LC_SEGMENT or LC_SEGMENT_64 + uint32_t cmdsize; // Total size of this struct and section commands + std::string segname; // segment name + uint64_t vmaddr; // address of this segment + uint64_t vmsize; // size of this segment, may be larger than filesize + uint64_t fileoff; // offset in file + uint64_t filesize; // amount to read from file + uint32_t maxprot; // maximum VM protection + uint32_t initprot; // initial VM protection + uint32_t nsects; // number of sections in this segment + uint32_t flags; // flags + + // The following constants are getting pulled in by one of the + // system headers, which creates a neat clash with the enum. +#if !defined(VM_PROT_NONE) +#define VM_PROT_NONE 0x00 +#endif +#if !defined(VM_PROT_READ) +#define VM_PROT_READ 0x01 +#endif +#if !defined(VM_PROT_WRITE) +#define VM_PROT_WRITE 0x02 +#endif +#if !defined(VM_PROT_EXECUTE) +#define VM_PROT_EXECUTE 0x04 +#endif +#if !defined(VM_PROT_ALL) +#define VM_PROT_ALL 0x07 +#endif + + // Constants for the vm protection fields + // see + enum { SEG_VM_PROT_NONE = VM_PROT_NONE, + SEG_VM_PROT_READ = VM_PROT_READ, // read permission + SEG_VM_PROT_WRITE = VM_PROT_WRITE, // write permission + SEG_VM_PROT_EXECUTE = VM_PROT_EXECUTE, + SEG_VM_PROT_ALL = VM_PROT_ALL + }; + + // Constants for the cmd field + // see + enum { LC_SEGMENT = 0x01, // segment of this file to be mapped + LC_SEGMENT_64 = 0x19 // 64-bit segment of this file to be mapped + }; + + /// cmdSize - This routine returns the size of the MachOSection as written + /// to disk, depending on whether the destination is a 64 bit Mach-O file. + unsigned cmdSize(bool is64Bit) const { + if (is64Bit) + return 6 * sizeof(uint32_t) + 4 * sizeof(uint64_t) + 16; + else + return 10 * sizeof(uint32_t) + 16; // addresses only 32 bits + } + + MachOSegment(const std::string &seg, bool is64Bit) + : cmd(is64Bit ? LC_SEGMENT_64 : LC_SEGMENT), cmdsize(0), segname(seg), + vmaddr(0), vmsize(0), fileoff(0), filesize(0), maxprot(VM_PROT_ALL), + initprot(VM_PROT_ALL), nsects(0), flags(0) { } +}; + +/// MachOSection - This struct contains information about each section in a +/// particular segment that is emitted to the file. This is eventually +/// turned into the SectionCommand in the load command for a particlar +/// segment. + +struct MachOSection { + std::string sectname; // name of this section, + std::string segname; // segment this section goes in + uint64_t addr; // memory address of this section + uint64_t size; // size in bytes of this section + uint32_t offset; // file offset of this section + uint32_t align; // section alignment (power of 2) + uint32_t reloff; // file offset of relocation entries + uint32_t nreloc; // number of relocation entries + uint32_t flags; // flags (section type and attributes) + uint32_t reserved1; // reserved (for offset or index) + uint32_t reserved2; // reserved (for count or sizeof) + uint32_t reserved3; // reserved (64 bit only) + + /// A unique number for this section, which will be used to match symbols + /// to the correct section. + uint32_t Index; + + /// SectionData - The actual data for this section which we are building + /// up for emission to the file. + DataBuffer SectionData; + + /// RelocBuffer - A buffer to hold the mach-o relocations before we write + /// them out at the appropriate location in the file. + DataBuffer RelocBuffer; + + /// Relocations - The relocations that we have encountered so far in this + /// section that we will need to convert to MachORelocation entries when + /// the file is written. + std::vector Relocations; + + // Constants for the section types (low 8 bits of flags field) + // see + enum { S_REGULAR = 0, + // regular section + S_ZEROFILL = 1, + // zero fill on demand section + S_CSTRING_LITERALS = 2, + // section with only literal C strings + S_4BYTE_LITERALS = 3, + // section with only 4 byte literals + S_8BYTE_LITERALS = 4, + // section with only 8 byte literals + S_LITERAL_POINTERS = 5, + // section with only pointers to literals + S_NON_LAZY_SYMBOL_POINTERS = 6, + // section with only non-lazy symbol pointers + S_LAZY_SYMBOL_POINTERS = 7, + // section with only lazy symbol pointers + S_SYMBOL_STUBS = 8, + // section with only symbol stubs + // byte size of stub in the reserved2 field + S_MOD_INIT_FUNC_POINTERS = 9, + // section with only function pointers for initialization + S_MOD_TERM_FUNC_POINTERS = 10, + // section with only function pointers for termination + S_COALESCED = 11, + // section contains symbols that are coalesced + S_GB_ZEROFILL = 12, + // zero fill on demand section (that can be larger than 4GB) + S_INTERPOSING = 13, + // section with only pairs of function pointers for interposing + S_16BYTE_LITERALS = 14 + // section with only 16 byte literals + }; + + // Constants for the section flags (high 24 bits of flags field) + // see + enum { S_ATTR_PURE_INSTRUCTIONS = 1 << 31, + // section contains only true machine instructions + S_ATTR_NO_TOC = 1 << 30, + // section contains coalesced symbols that are not to be in a + // ranlib table of contents + S_ATTR_STRIP_STATIC_SYMS = 1 << 29, + // ok to strip static symbols in this section in files with the + // MY_DYLDLINK flag + S_ATTR_NO_DEAD_STRIP = 1 << 28, + // no dead stripping + S_ATTR_LIVE_SUPPORT = 1 << 27, + // blocks are live if they reference live blocks + S_ATTR_SELF_MODIFYING_CODE = 1 << 26, + // used with i386 code stubs written on by dyld + S_ATTR_DEBUG = 1 << 25, + // a debug section + S_ATTR_SOME_INSTRUCTIONS = 1 << 10, + // section contains some machine instructions + S_ATTR_EXT_RELOC = 1 << 9, + // section has external relocation entries + S_ATTR_LOC_RELOC = 1 << 8 + // section has local relocation entries + }; + + /// cmdSize - This routine returns the size of the MachOSection as written + /// to disk, depending on whether the destination is a 64 bit Mach-O file. + unsigned cmdSize(bool is64Bit) const { + if (is64Bit) + return 7 * sizeof(uint32_t) + 2 * sizeof(uint64_t) + 32; + else + return 9 * sizeof(uint32_t) + 32; // addresses only 32 bits + } + + MachOSection(const std::string &seg, const std::string §) + : sectname(sect), segname(seg), addr(0), size(0), offset(0), align(2), + reloff(0), nreloc(0), flags(0), reserved1(0), reserved2(0), + reserved3(0) { } + +}; // end struct MachOSection + + /// MachOSymTab - This struct contains information about the offsets and + /// size of symbol table information. + /// segment. + struct MachODySymTab { + uint32_t cmd; // LC_DYSYMTAB + uint32_t cmdsize; // sizeof( MachODySymTab ) + uint32_t ilocalsym; // index to local symbols + uint32_t nlocalsym; // number of local symbols + uint32_t iextdefsym; // index to externally defined symbols + uint32_t nextdefsym; // number of externally defined symbols + uint32_t iundefsym; // index to undefined symbols + uint32_t nundefsym; // number of undefined symbols + uint32_t tocoff; // file offset to table of contents + uint32_t ntoc; // number of entries in table of contents + uint32_t modtaboff; // file offset to module table + uint32_t nmodtab; // number of module table entries + uint32_t extrefsymoff; // offset to referenced symbol table + uint32_t nextrefsyms; // number of referenced symbol table entries + uint32_t indirectsymoff; // file offset to the indirect symbol table + uint32_t nindirectsyms; // number of indirect symbol table entries + uint32_t extreloff; // offset to external relocation entries + uint32_t nextrel; // number of external relocation entries + uint32_t locreloff; // offset to local relocation entries + uint32_t nlocrel; // number of local relocation entries + + // Constants for the cmd field + // see + enum { LC_DYSYMTAB = 0x0B // dynamic link-edit symbol table info + }; + + MachODySymTab() : cmd(LC_DYSYMTAB), cmdsize(20 * sizeof(uint32_t)), + ilocalsym(0), nlocalsym(0), iextdefsym(0), nextdefsym(0), + iundefsym(0), nundefsym(0), tocoff(0), ntoc(0), modtaboff(0), + nmodtab(0), extrefsymoff(0), nextrefsyms(0), indirectsymoff(0), + nindirectsyms(0), extreloff(0), nextrel(0), locreloff(0), nlocrel(0) { } + }; + +} // end namespace llvm + +#endif + Added: llvm/trunk/lib/CodeGen/MachOCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachOCodeEmitter.cpp?rev=72754&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/MachOCodeEmitter.cpp (added) +++ llvm/trunk/lib/CodeGen/MachOCodeEmitter.cpp Tue Jun 2 22:43:31 2009 @@ -0,0 +1,207 @@ +//===-- MachOEmitter.cpp - Target-independent Mach-O Emitter code --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MachOCodeEmitter.h" +#include "llvm/Constants.h" +#include "llvm/DerivedTypes.h" +#include "llvm/Function.h" +#include "llvm/CodeGen/MachineConstantPool.h" +#include "llvm/CodeGen/MachineJumpTableInfo.h" +#include "llvm/Target/TargetAsmInfo.h" +#include "llvm/Support/Mangler.h" +#include "llvm/Support/OutputBuffer.h" + +//===----------------------------------------------------------------------===// +// MachOCodeEmitter Implementation +//===----------------------------------------------------------------------===// + +namespace llvm { + +/// startFunction - This callback is invoked when a new machine function is +/// about to be emitted. + +void MachOCodeEmitter::startFunction(MachineFunction &MF) { + const TargetData *TD = TM.getTargetData(); + const Function *F = MF.getFunction(); + + // Align the output buffer to the appropriate alignment, power of 2. + unsigned FnAlign = F->getAlignment(); + unsigned TDAlign = TD->getPrefTypeAlignment(F->getType()); + unsigned Align = Log2_32(std::max(FnAlign, TDAlign)); + assert(!(Align & (Align-1)) && "Alignment is not a power of two!"); + + // Get the Mach-O Section that this function belongs in. + MachOSection *MOS = MOW.getTextSection(); + + // FIXME: better memory management + MOS->SectionData.reserve(4096); + BufferBegin = &MOS->SectionData[0]; + BufferEnd = BufferBegin + MOS->SectionData.capacity(); + + // Upgrade the section alignment if required. + if (MOS->align < Align) MOS->align = Align; + + // Round the size up to the correct alignment for starting the new function. + if ((MOS->size & ((1 << Align) - 1)) != 0) { + MOS->size += (1 << Align); + MOS->size &= ~((1 << Align) - 1); + } + + // FIXME: Using MOS->size directly here instead of calculating it from the + // output buffer size (impossible because the code emitter deals only in raw + // bytes) forces us to manually synchronize size and write padding zero bytes + // to the output buffer for all non-text sections. For text sections, we do + // not synchonize the output buffer, and we just blow up if anyone tries to + // write non-code to it. An assert should probably be added to + // AddSymbolToSection to prevent calling it on the text section. + CurBufferPtr = BufferBegin + MOS->size; +} + +/// finishFunction - This callback is invoked after the function is completely +/// finished. + +bool MachOCodeEmitter::finishFunction(MachineFunction &MF) { + + // Get the Mach-O Section that this function belongs in. + MachOSection *MOS = MOW.getTextSection(); + + // Get a symbol for the function to add to the symbol table + // FIXME: it seems like we should call something like AddSymbolToSection + // in startFunction rather than changing the section size and symbol n_value + // here. + const GlobalValue *FuncV = MF.getFunction(); + MachOSym FnSym(FuncV, MOW.Mang->getValueName(FuncV), MOS->Index, TAI); + FnSym.n_value = MOS->size; + MOS->size = CurBufferPtr - BufferBegin; + + // Emit constant pool to appropriate section(s) + emitConstantPool(MF.getConstantPool()); + + // Emit jump tables to appropriate section + emitJumpTables(MF.getJumpTableInfo()); + + // If we have emitted any relocations to function-specific objects such as + // basic blocks, constant pools entries, or jump tables, record their + // addresses now so that we can rewrite them with the correct addresses + // later. + for (unsigned i = 0, e = Relocations.size(); i != e; ++i) { + MachineRelocation &MR = Relocations[i]; + intptr_t Addr; + + if (MR.isBasicBlock()) { + Addr = getMachineBasicBlockAddress(MR.getBasicBlock()); + MR.setConstantVal(MOS->Index); + MR.setResultPointer((void*)Addr); + } else if (MR.isJumpTableIndex()) { + Addr = getJumpTableEntryAddress(MR.getJumpTableIndex()); + MR.setConstantVal(MOW.getJumpTableSection()->Index); + MR.setResultPointer((void*)Addr); + } else if (MR.isConstantPoolIndex()) { + Addr = getConstantPoolEntryAddress(MR.getConstantPoolIndex()); + MR.setConstantVal(CPSections[MR.getConstantPoolIndex()]); + MR.setResultPointer((void*)Addr); + } else if (MR.isGlobalValue()) { + // FIXME: This should be a set or something that uniques + MOW.PendingGlobals.push_back(MR.getGlobalValue()); + } else { + assert(0 && "Unhandled relocation type"); + } + MOS->Relocations.push_back(MR); + } + Relocations.clear(); + + // Finally, add it to the symtab. + MOW.SymbolTable.push_back(FnSym); + + // Clear per-function data structures. + CPLocations.clear(); + CPSections.clear(); + JTLocations.clear(); + MBBLocations.clear(); + + return false; +} + +/// emitConstantPool - For each constant pool entry, figure out which section +/// the constant should live in, allocate space for it, and emit it to the +/// Section data buffer. +void MachOCodeEmitter::emitConstantPool(MachineConstantPool *MCP) { + const std::vector &CP = MCP->getConstants(); + if (CP.empty()) return; + + // FIXME: handle PIC codegen + assert(TM.getRelocationModel() != Reloc::PIC_ && + "PIC codegen not yet handled for mach-o jump tables!"); + + // Although there is no strict necessity that I am aware of, we will do what + // gcc for OS X does and put each constant pool entry in a section of constant + // objects of a certain size. That means that float constants go in the + // literal4 section, and double objects go in literal8, etc. + // + // FIXME: revisit this decision if we ever do the "stick everything into one + // "giant object for PIC" optimization. + for (unsigned i = 0, e = CP.size(); i != e; ++i) { + const Type *Ty = CP[i].getType(); + unsigned Size = TM.getTargetData()->getTypeAllocSize(Ty); + + MachOSection *Sec = MOW.getConstSection(CP[i].Val.ConstVal); + OutputBuffer SecDataOut(Sec->SectionData, is64Bit, isLittleEndian); + + CPLocations.push_back(Sec->SectionData.size()); + CPSections.push_back(Sec->Index); + + // FIXME: remove when we have unified size + output buffer + Sec->size += Size; + + // Allocate space in the section for the global. + // FIXME: need alignment? + // FIXME: share between here and AddSymbolToSection? + for (unsigned j = 0; j < Size; ++j) + SecDataOut.outbyte(0); + + MOW.InitMem(CP[i].Val.ConstVal, &Sec->SectionData[0], CPLocations[i], + TM.getTargetData(), Sec->Relocations); + } +} + +/// emitJumpTables - Emit all the jump tables for a given jump table info +/// record to the appropriate section. + +void MachOCodeEmitter::emitJumpTables(MachineJumpTableInfo *MJTI) { + const std::vector &JT = MJTI->getJumpTables(); + if (JT.empty()) return; + + // FIXME: handle PIC codegen + assert(TM.getRelocationModel() != Reloc::PIC_ && + "PIC codegen not yet handled for mach-o jump tables!"); + + MachOSection *Sec = MOW.getJumpTableSection(); + unsigned TextSecIndex = MOW.getTextSection()->Index; + OutputBuffer SecDataOut(Sec->SectionData, is64Bit, isLittleEndian); + + for (unsigned i = 0, e = JT.size(); i != e; ++i) { + // For each jump table, record its offset from the start of the section, + // reserve space for the relocations to the MBBs, and add the relocations. + const std::vector &MBBs = JT[i].MBBs; + JTLocations.push_back(Sec->SectionData.size()); + for (unsigned mi = 0, me = MBBs.size(); mi != me; ++mi) { + MachineRelocation MR(MOW.GetJTRelocation(Sec->SectionData.size(), + MBBs[mi])); + MR.setResultPointer((void *)JTLocations[i]); + MR.setConstantVal(TextSecIndex); + Sec->Relocations.push_back(MR); + SecDataOut.outaddr(0); + } + } + // FIXME: remove when we have unified size + output buffer + Sec->size = Sec->SectionData.size(); +} + +} // end namespace llvm + Added: llvm/trunk/lib/CodeGen/MachOCodeEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachOCodeEmitter.h?rev=72754&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/MachOCodeEmitter.h (added) +++ llvm/trunk/lib/CodeGen/MachOCodeEmitter.h Tue Jun 2 22:43:31 2009 @@ -0,0 +1,129 @@ +//===-- MachOEmitter.h - Target-independent Mach-O Emitter class ----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef MACHOCODEEMITTER_H +#define MACHOCODEEMITTER_H + +#include "MachOWriter.h" +#include "llvm/CodeGen/MachineCodeEmitter.h" +#include + +namespace llvm { + +/// MachOCodeEmitter - This class is used by the MachOWriter to emit the code +/// for functions to the Mach-O file. + +class MachOCodeEmitter : public MachineCodeEmitter { + MachOWriter &MOW; + + /// Target machine description. + TargetMachine &TM; + + /// is64Bit/isLittleEndian - This information is inferred from the target + /// machine directly, indicating what header values and flags to set. + bool is64Bit, isLittleEndian; + + const TargetAsmInfo *TAI; + + /// Relocations - These are the relocations that the function needs, as + /// emitted. + std::vector Relocations; + + /// CPLocations - This is a map of constant pool indices to offsets from the + /// start of the section for that constant pool index. + std::vector CPLocations; + + /// CPSections - This is a map of constant pool indices to the MachOSection + /// containing the constant pool entry for that index. + std::vector CPSections; + + /// JTLocations - This is a map of jump table indices to offsets from the + /// start of the section for that jump table index. + std::vector JTLocations; + + /// MBBLocations - This vector is a mapping from MBB ID's to their address. + /// It is filled in by the StartMachineBasicBlock callback and queried by + /// the getMachineBasicBlockAddress callback. + std::vector MBBLocations; + +public: + MachOCodeEmitter(MachOWriter &mow) : MOW(mow), TM(MOW.TM) + { + is64Bit = TM.getTargetData()->getPointerSizeInBits() == 64; + isLittleEndian = TM.getTargetData()->isLittleEndian(); + TAI = TM.getTargetAsmInfo(); + } + + virtual void startFunction(MachineFunction &MF); + virtual bool finishFunction(MachineFunction &MF); + + virtual void addRelocation(const MachineRelocation &MR) { + Relocations.push_back(MR); + } + + void emitConstantPool(MachineConstantPool *MCP); + void emitJumpTables(MachineJumpTableInfo *MJTI); + + virtual uintptr_t getConstantPoolEntryAddress(unsigned Index) const { + assert(CPLocations.size() > Index && "CP not emitted!"); + return CPLocations[Index]; + } + virtual uintptr_t getJumpTableEntryAddress(unsigned Index) const { + assert(JTLocations.size() > Index && "JT not emitted!"); + return JTLocations[Index]; + } + + virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) { + if (MBBLocations.size() <= (unsigned)MBB->getNumber()) + MBBLocations.resize((MBB->getNumber()+1)*2); + MBBLocations[MBB->getNumber()] = getCurrentPCOffset(); + } + + virtual uintptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const { + assert(MBBLocations.size() > (unsigned)MBB->getNumber() && + MBBLocations[MBB->getNumber()] && "MBB not emitted!"); + return MBBLocations[MBB->getNumber()]; + } + + virtual uintptr_t getLabelAddress(uint64_t Label) const { + assert(0 && "get Label not implemented"); + abort(); + return 0; + } + + virtual void emitLabel(uint64_t LabelID) { + assert(0 && "emit Label not implemented"); + abort(); + } + + virtual void setModuleInfo(llvm::MachineModuleInfo* MMI) { } + + /// JIT SPECIFIC FUNCTIONS - DO NOT IMPLEMENT THESE HERE! + virtual void startGVStub(const GlobalValue* F, unsigned StubSize, + unsigned Alignment = 1) { + assert(0 && "JIT specific function called!"); + abort(); + } + virtual void startGVStub(const GlobalValue* F, void *Buffer, + unsigned StubSize) { + assert(0 && "JIT specific function called!"); + abort(); + } + virtual void *finishGVStub(const GlobalValue* F) { + assert(0 && "JIT specific function called!"); + abort(); + return 0; + } + +}; // end class MachOCodeEmitter + +} // end namespace llvm + +#endif + Modified: llvm/trunk/lib/CodeGen/MachOWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachOWriter.cpp?rev=72754&r1=72753&r2=72754&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachOWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/MachOWriter.cpp Tue Jun 2 22:43:31 2009 @@ -23,6 +23,7 @@ //===----------------------------------------------------------------------===// #include "MachOWriter.h" +#include "MachOCodeEmitter.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" @@ -40,11 +41,12 @@ #include "llvm/Support/raw_ostream.h" #include #include -using namespace llvm; + +namespace llvm { /// AddMachOWriter - Concrete function to add the Mach-O writer to the function /// pass manager. -MachineCodeEmitter *llvm::AddMachOWriter(PassManagerBase &PM, +MachineCodeEmitter *AddMachOWriter(PassManagerBase &PM, raw_ostream &O, TargetMachine &TM) { MachOWriter *MOW = new MachOWriter(O, TM); @@ -53,304 +55,74 @@ } //===----------------------------------------------------------------------===// -// MachOCodeEmitter Implementation +// MachOWriter Implementation //===----------------------------------------------------------------------===// -namespace llvm { - /// MachOCodeEmitter - This class is used by the MachOWriter to emit the code - /// for functions to the Mach-O file. - class MachOCodeEmitter : public MachineCodeEmitter { - MachOWriter &MOW; - - /// Target machine description. - TargetMachine &TM; - - /// is64Bit/isLittleEndian - This information is inferred from the target - /// machine directly, indicating what header values and flags to set. - bool is64Bit, isLittleEndian; - - /// Relocations - These are the relocations that the function needs, as - /// emitted. - std::vector Relocations; - - /// CPLocations - This is a map of constant pool indices to offsets from the - /// start of the section for that constant pool index. - std::vector CPLocations; - - /// CPSections - This is a map of constant pool indices to the MachOSection - /// containing the constant pool entry for that index. - std::vector CPSections; - - /// JTLocations - This is a map of jump table indices to offsets from the - /// start of the section for that jump table index. - std::vector JTLocations; - - /// MBBLocations - This vector is a mapping from MBB ID's to their address. - /// It is filled in by the StartMachineBasicBlock callback and queried by - /// the getMachineBasicBlockAddress callback. - std::vector MBBLocations; - - public: - MachOCodeEmitter(MachOWriter &mow) : MOW(mow), TM(MOW.TM) { - is64Bit = TM.getTargetData()->getPointerSizeInBits() == 64; - isLittleEndian = TM.getTargetData()->isLittleEndian(); - } - - virtual void startFunction(MachineFunction &MF); - virtual bool finishFunction(MachineFunction &MF); - - virtual void addRelocation(const MachineRelocation &MR) { - Relocations.push_back(MR); - } - - void emitConstantPool(MachineConstantPool *MCP); - void emitJumpTables(MachineJumpTableInfo *MJTI); - - virtual uintptr_t getConstantPoolEntryAddress(unsigned Index) const { - assert(CPLocations.size() > Index && "CP not emitted!"); - return CPLocations[Index]; - } - virtual uintptr_t getJumpTableEntryAddress(unsigned Index) const { - assert(JTLocations.size() > Index && "JT not emitted!"); - return JTLocations[Index]; - } - - virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) { - if (MBBLocations.size() <= (unsigned)MBB->getNumber()) - MBBLocations.resize((MBB->getNumber()+1)*2); - MBBLocations[MBB->getNumber()] = getCurrentPCOffset(); - } - - virtual uintptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const { - assert(MBBLocations.size() > (unsigned)MBB->getNumber() && - MBBLocations[MBB->getNumber()] && "MBB not emitted!"); - return MBBLocations[MBB->getNumber()]; - } - - virtual uintptr_t getLabelAddress(uint64_t Label) const { - assert(0 && "get Label not implemented"); - abort(); - return 0; - } +char MachOWriter::ID = 0; - virtual void emitLabel(uint64_t LabelID) { - assert(0 && "emit Label not implemented"); - abort(); - } +MachOWriter::MachOWriter(raw_ostream &o, TargetMachine &tm) + : MachineFunctionPass(&ID), O(o), TM(tm) { + is64Bit = TM.getTargetData()->getPointerSizeInBits() == 64; + isLittleEndian = TM.getTargetData()->isLittleEndian(); + TAI = TM.getTargetAsmInfo(); - virtual void setModuleInfo(llvm::MachineModuleInfo* MMI) { } + // Create the machine code emitter object for this target. - /// JIT SPECIFIC FUNCTIONS - DO NOT IMPLEMENT THESE HERE! - virtual void startGVStub(const GlobalValue* F, unsigned StubSize, - unsigned Alignment = 1) { - assert(0 && "JIT specific function called!"); - abort(); - } - virtual void startGVStub(const GlobalValue* F, void *Buffer, - unsigned StubSize) { - assert(0 && "JIT specific function called!"); - abort(); - } - virtual void *finishGVStub(const GlobalValue* F) { - assert(0 && "JIT specific function called!"); - abort(); - return 0; - } - }; + MCE = new MachOCodeEmitter(*this); } -/// startFunction - This callback is invoked when a new machine function is -/// about to be emitted. -void MachOCodeEmitter::startFunction(MachineFunction &MF) { - const TargetData *TD = TM.getTargetData(); - const Function *F = MF.getFunction(); - - // Align the output buffer to the appropriate alignment, power of 2. - unsigned FnAlign = F->getAlignment(); - unsigned TDAlign = TD->getPrefTypeAlignment(F->getType()); - unsigned Align = Log2_32(std::max(FnAlign, TDAlign)); - assert(!(Align & (Align-1)) && "Alignment is not a power of two!"); - - // Get the Mach-O Section that this function belongs in. - MachOWriter::MachOSection *MOS = MOW.getTextSection(); - - // FIXME: better memory management - MOS->SectionData.reserve(4096); - BufferBegin = &MOS->SectionData[0]; - BufferEnd = BufferBegin + MOS->SectionData.capacity(); - - // Upgrade the section alignment if required. - if (MOS->align < Align) MOS->align = Align; - - // Round the size up to the correct alignment for starting the new function. - if ((MOS->size & ((1 << Align) - 1)) != 0) { - MOS->size += (1 << Align); - MOS->size &= ~((1 << Align) - 1); - } - - // FIXME: Using MOS->size directly here instead of calculating it from the - // output buffer size (impossible because the code emitter deals only in raw - // bytes) forces us to manually synchronize size and write padding zero bytes - // to the output buffer for all non-text sections. For text sections, we do - // not synchonize the output buffer, and we just blow up if anyone tries to - // write non-code to it. An assert should probably be added to - // AddSymbolToSection to prevent calling it on the text section. - CurBufferPtr = BufferBegin + MOS->size; - - // Clear per-function data structures. - CPLocations.clear(); - CPSections.clear(); - JTLocations.clear(); - MBBLocations.clear(); -} - -/// finishFunction - This callback is invoked after the function is completely -/// finished. -bool MachOCodeEmitter::finishFunction(MachineFunction &MF) { - // Get the Mach-O Section that this function belongs in. - MachOWriter::MachOSection *MOS = MOW.getTextSection(); - - // Get a symbol for the function to add to the symbol table - // FIXME: it seems like we should call something like AddSymbolToSection - // in startFunction rather than changing the section size and symbol n_value - // here. - const GlobalValue *FuncV = MF.getFunction(); - MachOSym FnSym(FuncV, MOW.Mang->getValueName(FuncV), MOS->Index, TM); - FnSym.n_value = MOS->size; - MOS->size = CurBufferPtr - BufferBegin; - - // Emit constant pool to appropriate section(s) - emitConstantPool(MF.getConstantPool()); - - // Emit jump tables to appropriate section - emitJumpTables(MF.getJumpTableInfo()); - - // If we have emitted any relocations to function-specific objects such as - // basic blocks, constant pools entries, or jump tables, record their - // addresses now so that we can rewrite them with the correct addresses - // later. - for (unsigned i = 0, e = Relocations.size(); i != e; ++i) { - MachineRelocation &MR = Relocations[i]; - intptr_t Addr; - - if (MR.isBasicBlock()) { - Addr = getMachineBasicBlockAddress(MR.getBasicBlock()); - MR.setConstantVal(MOS->Index); - MR.setResultPointer((void*)Addr); - } else if (MR.isJumpTableIndex()) { - Addr = getJumpTableEntryAddress(MR.getJumpTableIndex()); - MR.setConstantVal(MOW.getJumpTableSection()->Index); - MR.setResultPointer((void*)Addr); - } else if (MR.isConstantPoolIndex()) { - Addr = getConstantPoolEntryAddress(MR.getConstantPoolIndex()); - MR.setConstantVal(CPSections[MR.getConstantPoolIndex()]); - MR.setResultPointer((void*)Addr); - } else if (MR.isGlobalValue()) { - // FIXME: This should be a set or something that uniques - MOW.PendingGlobals.push_back(MR.getGlobalValue()); - } else { - assert(0 && "Unhandled relocation type"); - } - MOS->Relocations.push_back(MR); - } - Relocations.clear(); - - // Finally, add it to the symtab. - MOW.SymbolTable.push_back(FnSym); - return false; +MachOWriter::~MachOWriter() { + delete MCE; } -/// emitConstantPool - For each constant pool entry, figure out which section -/// the constant should live in, allocate space for it, and emit it to the -/// Section data buffer. -void MachOCodeEmitter::emitConstantPool(MachineConstantPool *MCP) { - const std::vector &CP = MCP->getConstants(); - if (CP.empty()) return; - - // FIXME: handle PIC codegen - assert(TM.getRelocationModel() != Reloc::PIC_ && - "PIC codegen not yet handled for mach-o jump tables!"); - - // Although there is no strict necessity that I am aware of, we will do what - // gcc for OS X does and put each constant pool entry in a section of constant - // objects of a certain size. That means that float constants go in the - // literal4 section, and double objects go in literal8, etc. - // - // FIXME: revisit this decision if we ever do the "stick everything into one - // "giant object for PIC" optimization. - for (unsigned i = 0, e = CP.size(); i != e; ++i) { - const Type *Ty = CP[i].getType(); - unsigned Size = TM.getTargetData()->getTypeAllocSize(Ty); - - MachOWriter::MachOSection *Sec = MOW.getConstSection(CP[i].Val.ConstVal); - OutputBuffer SecDataOut(Sec->SectionData, is64Bit, isLittleEndian); - - CPLocations.push_back(Sec->SectionData.size()); - CPSections.push_back(Sec->Index); - - // FIXME: remove when we have unified size + output buffer - Sec->size += Size; +bool MachOWriter::doInitialization(Module &M) { + // Set the magic value, now that we know the pointer size and endianness + Header.setMagic(isLittleEndian, is64Bit); - // Allocate space in the section for the global. - // FIXME: need alignment? - // FIXME: share between here and AddSymbolToSection? - for (unsigned j = 0; j < Size; ++j) - SecDataOut.outbyte(0); + // Set the file type + // FIXME: this only works for object files, we do not support the creation + // of dynamic libraries or executables at this time. + Header.filetype = MachOHeader::MH_OBJECT; - MOW.InitMem(CP[i].Val.ConstVal, &Sec->SectionData[0], CPLocations[i], - TM.getTargetData(), Sec->Relocations); - } + Mang = new Mangler(M); + return false; } -/// emitJumpTables - Emit all the jump tables for a given jump table info -/// record to the appropriate section. -void MachOCodeEmitter::emitJumpTables(MachineJumpTableInfo *MJTI) { - const std::vector &JT = MJTI->getJumpTables(); - if (JT.empty()) return; +bool MachOWriter::runOnMachineFunction(MachineFunction &MF) { + return false; +} - // FIXME: handle PIC codegen - assert(TM.getRelocationModel() != Reloc::PIC_ && - "PIC codegen not yet handled for mach-o jump tables!"); +/// doFinalization - Now that the module has been completely processed, emit +/// the Mach-O file to 'O'. +bool MachOWriter::doFinalization(Module &M) { + // FIXME: we don't handle debug info yet, we should probably do that. - MachOWriter::MachOSection *Sec = MOW.getJumpTableSection(); - unsigned TextSecIndex = MOW.getTextSection()->Index; - OutputBuffer SecDataOut(Sec->SectionData, is64Bit, isLittleEndian); + // Okay, the.text section has been completed, build the .data, .bss, and + // "common" sections next. + for (Module::global_iterator I = M.global_begin(), E = M.global_end(); + I != E; ++I) + EmitGlobal(I); - for (unsigned i = 0, e = JT.size(); i != e; ++i) { - // For each jump table, record its offset from the start of the section, - // reserve space for the relocations to the MBBs, and add the relocations. - const std::vector &MBBs = JT[i].MBBs; - JTLocations.push_back(Sec->SectionData.size()); - for (unsigned mi = 0, me = MBBs.size(); mi != me; ++mi) { - MachineRelocation MR(MOW.GetJTRelocation(Sec->SectionData.size(), - MBBs[mi])); - MR.setResultPointer((void *)JTLocations[i]); - MR.setConstantVal(TextSecIndex); - Sec->Relocations.push_back(MR); - SecDataOut.outaddr(0); - } - } - // FIXME: remove when we have unified size + output buffer - Sec->size = Sec->SectionData.size(); -} + // Emit the header and load commands. + EmitHeaderAndLoadCommands(); -//===----------------------------------------------------------------------===// -// MachOWriter Implementation -//===----------------------------------------------------------------------===// + // Emit the various sections and their relocation info. + EmitSections(); + EmitRelocations(); -char MachOWriter::ID = 0; -MachOWriter::MachOWriter(raw_ostream &o, TargetMachine &tm) - : MachineFunctionPass(&ID), O(o), TM(tm) { - is64Bit = TM.getTargetData()->getPointerSizeInBits() == 64; - isLittleEndian = TM.getTargetData()->isLittleEndian(); + // Write the symbol table and the string table to the end of the file. + O.write((char*)&SymT[0], SymT.size()); + O.write((char*)&StrT[0], StrT.size()); - // Create the machine code emitter object for this target. - MCE = new MachOCodeEmitter(*this); -} + // We are done with the abstract symbols. + SectionList.clear(); + SymbolTable.clear(); + DynamicSymbolTable.clear(); -MachOWriter::~MachOWriter() { - delete MCE; + // Release the name mangler object. + delete Mang; Mang = 0; + return false; } void MachOWriter::AddSymbolToSection(MachOSection *Sec, GlobalVariable *GV) { @@ -368,7 +140,7 @@ Align = Log2_32(Align); Sec->align = std::max(unsigned(Sec->align), Align); Sec->size = (Sec->size + Align - 1) & ~(Align-1); - + // Add alignment padding to buffer as well. // FIXME: remove when we have unified size + output buffer unsigned AlignedSize = Sec->size - OrigSize; @@ -377,7 +149,7 @@ } // Globals without external linkage apparently do not go in the symbol table. if (!GV->hasLocalLinkage()) { - MachOSym Sym(GV, Mang->getValueName(GV), Sec->Index, TM); + MachOSym Sym(GV, Mang->getValueName(GV), Sec->Index, TAI); Sym.n_value = Sec->size; SymbolTable.push_back(Sym); } @@ -385,14 +157,14 @@ // Record the offset of the symbol, and then allocate space for it. // FIXME: remove when we have unified size + output buffer Sec->size += Size; - - // Now that we know what section the GlovalVariable is going to be emitted + + // Now that we know what section the GlovalVariable is going to be emitted // into, update our mappings. // FIXME: We may also need to update this when outputting non-GlobalVariable // GlobalValues such as functions. GVSection[GV] = Sec; GVOffset[GV] = Sec->SectionData.size(); - + // Allocate space in the section for the global. for (unsigned i = 0; i < Size; ++i) SecDataOut.outbyte(0); @@ -402,7 +174,7 @@ const Type *Ty = GV->getType()->getElementType(); unsigned Size = TM.getTargetData()->getTypeAllocSize(Ty); bool NoInit = !GV->hasInitializer(); - + // If this global has a zero initializer, it is part of the .bss or common // section. if (NoInit || GV->getInitializer()->isNullValue()) { @@ -411,7 +183,8 @@ // merged with other symbols. if (NoInit || GV->hasLinkOnceLinkage() || GV->hasWeakLinkage() || GV->hasCommonLinkage()) { - MachOSym ExtOrCommonSym(GV, Mang->getValueName(GV), MachOSym::NO_SECT,TM); + MachOSym ExtOrCommonSym(GV, Mang->getValueName(GV), + MachOSym::NO_SECT, TAI); // For undefined (N_UNDF) external (N_EXT) types, n_value is the size in // bytes of the symbol. ExtOrCommonSym.n_value = Size; @@ -425,11 +198,11 @@ AddSymbolToSection(BSS, GV); return; } - + // Scalar read-only data goes in a literal section if the scalar is 4, 8, or // 16 bytes, or a cstring. Other read only data goes into a regular const // section. Read-write data goes in the data section. - MachOSection *Sec = GV->isConstant() ? getConstSection(GV->getInitializer()) : + MachOSection *Sec = GV->isConstant() ? getConstSection(GV->getInitializer()) : getDataSection(); AddSymbolToSection(Sec, GV); InitMem(GV->getInitializer(), &Sec->SectionData[0], GVOffset[GV], @@ -437,73 +210,25 @@ } -bool MachOWriter::runOnMachineFunction(MachineFunction &MF) { - // Nothing to do here, this is all done through the MCE object. - return false; -} - -bool MachOWriter::doInitialization(Module &M) { - // Set the magic value, now that we know the pointer size and endianness - Header.setMagic(isLittleEndian, is64Bit); - - // Set the file type - // FIXME: this only works for object files, we do not support the creation - // of dynamic libraries or executables at this time. - Header.filetype = MachOHeader::MH_OBJECT; - - Mang = new Mangler(M); - return false; -} - -/// doFinalization - Now that the module has been completely processed, emit -/// the Mach-O file to 'O'. -bool MachOWriter::doFinalization(Module &M) { - // FIXME: we don't handle debug info yet, we should probably do that. - - // Okay, the.text section has been completed, build the .data, .bss, and - // "common" sections next. - for (Module::global_iterator I = M.global_begin(), E = M.global_end(); - I != E; ++I) - EmitGlobal(I); - - // Emit the header and load commands. - EmitHeaderAndLoadCommands(); - - // Emit the various sections and their relocation info. - EmitSections(); - - // Write the symbol table and the string table to the end of the file. - O.write((char*)&SymT[0], SymT.size()); - O.write((char*)&StrT[0], StrT.size()); - - // We are done with the abstract symbols. - SectionList.clear(); - SymbolTable.clear(); - DynamicSymbolTable.clear(); - - // Release the name mangler object. - delete Mang; Mang = 0; - return false; -} void MachOWriter::EmitHeaderAndLoadCommands() { // Step #0: Fill in the segment load command size, since we need it to figure // out the rest of the header fields MachOSegment SEG("", is64Bit); SEG.nsects = SectionList.size(); - SEG.cmdsize = SEG.cmdSize(is64Bit) + + SEG.cmdsize = SEG.cmdSize(is64Bit) + SEG.nsects * SectionList[0]->cmdSize(is64Bit); - + // Step #1: calculate the number of load commands. We always have at least // one, for the LC_SEGMENT load command, plus two for the normal // and dynamic symbol tables, if there are any symbols. Header.ncmds = SymbolTable.empty() ? 1 : 3; - + // Step #2: calculate the size of the load commands Header.sizeofcmds = SEG.cmdsize; if (!SymbolTable.empty()) Header.sizeofcmds += SymTab.cmdsize + DySymTab.cmdsize; - + // Step #3: write the header to the file // Local alias to shortenify coming code. DataBuffer &FH = Header.HeaderData; @@ -518,7 +243,7 @@ FHOut.outword(Header.flags); if (is64Bit) FHOut.outword(Header.reserved); - + // Step #4: Finish filling in the segment load command and write it out for (std::vector::iterator I = SectionList.begin(), E = SectionList.end(); I != E; ++I) @@ -526,7 +251,7 @@ SEG.vmsize = SEG.filesize; SEG.fileoff = Header.cmdSize(is64Bit) + Header.sizeofcmds; - + FHOut.outword(SEG.cmd); FHOut.outword(SEG.cmdsize); FHOut.outstring(SEG.segname, 16); @@ -538,8 +263,8 @@ FHOut.outword(SEG.initprot); FHOut.outword(SEG.nsects); FHOut.outword(SEG.flags); - - // Step #5: Finish filling in the fields of the MachOSections + + // Step #5: Finish filling in the fields of the MachOSections uint64_t currentAddr = 0; for (std::vector::iterator I = SectionList.begin(), E = SectionList.end(); I != E; ++I) { @@ -550,13 +275,13 @@ // FIXME: do we need to do something with alignment here? currentAddr += MOS->size; } - + // Step #6: Emit the symbol table to temporary buffers, so that we know the // size of the string table when we write the next load command. This also // sorts and assigns indices to each of the symbols, which is necessary for // emitting relocations to externally-defined objects. BufferSymbolAndStringTable(); - + // Step #7: Calculate the number of relocations for each section and write out // the section commands for each section currentAddr += SEG.fileoff; @@ -568,7 +293,7 @@ CalculateRelocations(*MOS); MOS->reloff = MOS->nreloc ? currentAddr : 0; currentAddr += MOS->nreloc * 8; - + // write the finalized section command to the output buffer FHOut.outstring(MOS->sectname, 16); FHOut.outstring(MOS->segname, 16); @@ -584,7 +309,7 @@ if (is64Bit) FHOut.outword(MOS->reserved3); } - + // Step #8: Emit LC_SYMTAB/LC_DYSYMTAB load commands SymTab.symoff = currentAddr; SymTab.nsyms = SymbolTable.size(); @@ -620,94 +345,92 @@ FHOut.outword(DySymTab.nextrel); FHOut.outword(DySymTab.locreloff); FHOut.outword(DySymTab.nlocrel); - + O.write((char*)&FH[0], FH.size()); } /// EmitSections - Now that we have constructed the file header and load /// commands, emit the data for each section to the file. + void MachOWriter::EmitSections() { for (std::vector::iterator I = SectionList.begin(), E = SectionList.end(); I != E; ++I) // Emit the contents of each section O.write((char*)&(*I)->SectionData[0], (*I)->size); +} +void MachOWriter::EmitRelocations() { for (std::vector::iterator I = SectionList.begin(), E = SectionList.end(); I != E; ++I) // Emit the relocation entry data for each section. O.write((char*)&(*I)->RelocBuffer[0], (*I)->RelocBuffer.size()); } -/// PartitionByLocal - Simple boolean predicate that returns true if Sym is -/// a local symbol rather than an external symbol. -bool MachOWriter::PartitionByLocal(const MachOSym &Sym) { - return (Sym.n_type & (MachOSym::N_EXT | MachOSym::N_PEXT)) == 0; -} - -/// PartitionByDefined - Simple boolean predicate that returns true if Sym is -/// defined in this module. -bool MachOWriter::PartitionByDefined(const MachOSym &Sym) { - // FIXME: Do N_ABS or N_INDR count as defined? - return (Sym.n_type & MachOSym::N_SECT) == MachOSym::N_SECT; -} - /// BufferSymbolAndStringTable - Sort the symbols we encountered and assign them /// each a string table index so that they appear in the correct order in the /// output file. + void MachOWriter::BufferSymbolAndStringTable() { // The order of the symbol table is: // 1. local symbols // 2. defined external symbols (sorted by name) // 3. undefined external symbols (sorted by name) - + // Before sorting the symbols, check the PendingGlobals for any undefined // globals that need to be put in the symbol table. + for (std::vector::iterator I = PendingGlobals.begin(), E = PendingGlobals.end(); I != E; ++I) { if (GVOffset[*I] == 0 && GVSection[*I] == 0) { - MachOSym UndfSym(*I, Mang->getValueName(*I), MachOSym::NO_SECT, TM); + MachOSym UndfSym(*I, Mang->getValueName(*I), MachOSym::NO_SECT, TAI); SymbolTable.push_back(UndfSym); GVOffset[*I] = -1; } } - + // Sort the symbols by name, so that when we partition the symbols by scope // of definition, we won't have to sort by name within each partition. - std::sort(SymbolTable.begin(), SymbolTable.end(), MachOSymCmp()); - // Parition the symbol table entries so that all local symbols come before + std::sort(SymbolTable.begin(), SymbolTable.end(), MachOSym::SymCmp()); + + // Parition the symbol table entries so that all local symbols come before // all symbols with external linkage. { 1 | 2 3 } - std::partition(SymbolTable.begin(), SymbolTable.end(), PartitionByLocal); - + + std::partition(SymbolTable.begin(), SymbolTable.end(), + MachOSym::PartitionByLocal); + // Advance iterator to beginning of external symbols and partition so that // all external symbols defined in this module come before all external // symbols defined elsewhere. { 1 | 2 | 3 } + for (std::vector::iterator I = SymbolTable.begin(), E = SymbolTable.end(); I != E; ++I) { - if (!PartitionByLocal(*I)) { - std::partition(I, E, PartitionByDefined); + if (!MachOSym::PartitionByLocal(*I)) { + std::partition(I, E, MachOSym::PartitionByDefined); break; } } - // Calculate the starting index for each of the local, extern defined, and + // Calculate the starting index for each of the local, extern defined, and // undefined symbols, as well as the number of each to put in the LC_DYSYMTAB // load command. + for (std::vector::iterator I = SymbolTable.begin(), E = SymbolTable.end(); I != E; ++I) { - if (PartitionByLocal(*I)) { + if (MachOSym::PartitionByLocal(*I)) { ++DySymTab.nlocalsym; ++DySymTab.iextdefsym; ++DySymTab.iundefsym; - } else if (PartitionByDefined(*I)) { + } else if (MachOSym::PartitionByDefined(*I)) { ++DySymTab.nextdefsym; ++DySymTab.iundefsym; } else { ++DySymTab.nundefsym; } } - + // Write out a leading zero byte when emitting string table, for n_strx == 0 // which means an empty string. + OutputBuffer StrTOut(StrT, is64Bit, isLittleEndian); StrTOut.outbyte(0); @@ -716,6 +439,7 @@ // 2. strings for local symbols // Since this is the opposite order from the symbol table, which we have just // sorted, we can walk the symbol table backwards to output the string table. + for (std::vector::reverse_iterator I = SymbolTable.rbegin(), E = SymbolTable.rend(); I != E; ++I) { if (I->GVName == "") { @@ -739,7 +463,7 @@ I->n_value += GVSection[GV]->addr; if (GV && (GVOffset[GV] == -1)) GVOffset[GV] = index; - + // Emit nlist to buffer SymTOut.outword(I->n_strx); SymTOut.outbyte(I->n_type); @@ -754,6 +478,7 @@ /// and the offset into that section. From this information, create the /// appropriate target-specific MachORelocation type and add buffer it to be /// written out after we are finished writing out sections. + void MachOWriter::CalculateRelocations(MachOSection &MOS) { for (unsigned i = 0, e = MOS.Relocations.size(); i != e; ++i) { MachineRelocation &MR = MOS.Relocations[i]; @@ -763,19 +488,22 @@ // This is a scattered relocation entry if it points to a global value with // a non-zero offset. + bool Scattered = false; bool Extern = false; // Since we may not have seen the GlobalValue we were interested in yet at // the time we emitted the relocation for it, fix it up now so that it // points to the offset into the correct section. + if (MR.isGlobalValue()) { GlobalValue *GV = MR.getGlobalValue(); MachOSection *MOSPtr = GVSection[GV]; intptr_t Offset = GVOffset[GV]; - + // If we have never seen the global before, it must be to a symbol // defined in another module (N_UNDF). + if (!MOSPtr) { // FIXME: need to append stub suffix Extern = true; @@ -787,9 +515,10 @@ } MR.setResultPointer((void*)Offset); } - + // If the symbol is locally defined, pass in the address of the section and // the section index to the code which will generate the target relocation. + if (!Extern) { MachOSection &To = *SectionList[TargetSection - 1]; TargetAddr = To.addr; @@ -798,7 +527,7 @@ OutputBuffer RelocOut(MOS.RelocBuffer, is64Bit, isLittleEndian); OutputBuffer SecOut(MOS.SectionData, is64Bit, isLittleEndian); - + MOS.nreloc += GetTargetRelocation(MR, MOS.Index, TargetAddr, TargetIndex, RelocOut, SecOut, Scattered, Extern); } @@ -806,21 +535,22 @@ // InitMem - Write the value of a Constant to the specified memory location, // converting it into bytes and relocations. + void MachOWriter::InitMem(const Constant *C, void *Addr, intptr_t Offset, - const TargetData *TD, + const TargetData *TD, std::vector &MRs) { typedef std::pair CPair; std::vector WorkList; - + WorkList.push_back(CPair(C,(intptr_t)Addr + Offset)); - + intptr_t ScatteredOffset = 0; - + while (!WorkList.empty()) { const Constant *PC = WorkList.back().first; intptr_t PA = WorkList.back().second; WorkList.pop_back(); - + if (isa(PC)) { continue; } else if (const ConstantVector *CP = dyn_cast(PC)) { @@ -847,7 +577,7 @@ break; } } else if (PC->getType()->isSingleValueType()) { - uint8_t *ptr = (uint8_t *)PA; + unsigned char *ptr = (unsigned char *)PA; switch (PC->getType()->getTypeID()) { case Type::IntegerTyID: { unsigned NumBits = cast(PC->getType())->getBitWidth(); @@ -945,13 +675,15 @@ } } +//===----------------------------------------------------------------------===// +// MachOSym Implementation +//===----------------------------------------------------------------------===// + MachOSym::MachOSym(const GlobalValue *gv, std::string name, uint8_t sect, - TargetMachine &TM) : + const TargetAsmInfo *TAI) : GV(gv), n_strx(0), n_type(sect == NO_SECT ? N_UNDF : N_SECT), n_sect(sect), n_desc(0), n_value(0) { - const TargetAsmInfo *TAI = TM.getTargetAsmInfo(); - switch (GV->getLinkage()) { default: assert(0 && "Unexpected linkage type!"); @@ -974,3 +706,6 @@ break; } } + +} // end namespace llvm + Modified: llvm/trunk/lib/CodeGen/MachOWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachOWriter.h?rev=72754&r1=72753&r2=72754&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachOWriter.h (original) +++ llvm/trunk/lib/CodeGen/MachOWriter.h Tue Jun 2 22:43:31 2009 @@ -14,10 +14,8 @@ #ifndef MACHOWRITER_H #define MACHOWRITER_H -#include "llvm/Constants.h" -#include "llvm/DerivedTypes.h" +#include "MachO.h" #include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineRelocation.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachOWriterInfo.h" @@ -31,53 +29,6 @@ class OutputBuffer; class raw_ostream; - /// MachOSym - This struct contains information about each symbol that is - /// added to logical symbol table for the module. This is eventually - /// turned into a real symbol table in the file. - struct MachOSym { - const GlobalValue *GV; // The global value this corresponds to. - std::string GVName; // The mangled name of the global value. - uint32_t n_strx; // index into the string table - uint8_t n_type; // type flag - uint8_t n_sect; // section number or NO_SECT - int16_t n_desc; // see - uint64_t n_value; // value for this symbol (or stab offset) - - // Constants for the n_sect field - // see - enum { NO_SECT = 0 }; // symbol is not in any section - - // Constants for the n_type field - // see - enum { N_UNDF = 0x0, // undefined, n_sect == NO_SECT - N_ABS = 0x2, // absolute, n_sect == NO_SECT - N_SECT = 0xe, // defined in section number n_sect - N_PBUD = 0xc, // prebound undefined (defined in a dylib) - N_INDR = 0xa // indirect - }; - // The following bits are OR'd into the types above. For example, a type - // of 0x0f would be an external N_SECT symbol (0x0e | 0x01). - enum { N_EXT = 0x01, // external symbol bit - N_PEXT = 0x10 // private external symbol bit - }; - - // Constants for the n_desc field - // see - enum { REFERENCE_FLAG_UNDEFINED_NON_LAZY = 0, - REFERENCE_FLAG_UNDEFINED_LAZY = 1, - REFERENCE_FLAG_DEFINED = 2, - REFERENCE_FLAG_PRIVATE_DEFINED = 3, - REFERENCE_FLAG_PRIVATE_UNDEFINED_NON_LAZY = 4, - REFERENCE_FLAG_PRIVATE_UNDEFINED_LAZY = 5 - }; - enum { N_NO_DEAD_STRIP = 0x0020, // symbol is not to be dead stripped - N_WEAK_REF = 0x0040, // symbol is weak referenced - N_WEAK_DEF = 0x0080 // coalesced symbol is a weak definition - }; - - MachOSym(const GlobalValue *gv, std::string name, uint8_t sect, - TargetMachine &TM); - }; /// MachOWriter - This class implements the common target-independent code for /// writing Mach-O files. Targets should derive a class from this to @@ -98,7 +49,6 @@ return "Mach-O Writer"; } - typedef std::vector DataBuffer; protected: /// Output stream to send the resultant object file to. /// @@ -114,326 +64,61 @@ /// MCE - The MachineCodeEmitter object that we are exposing to emit machine /// code for functions to the .o file. + MachOCodeEmitter *MCE; /// is64Bit/isLittleEndian - This information is inferred from the target /// machine directly, indicating what header values and flags to set. - bool is64Bit, isLittleEndian; - /// doInitialization - Emit the file header and all of the global variables - /// for the module to the Mach-O file. - bool doInitialization(Module &M); - - bool runOnMachineFunction(MachineFunction &MF); - - /// doFinalization - Now that the module has been completely processed, emit - /// the Mach-O file to 'O'. - bool doFinalization(Module &M); + bool is64Bit, isLittleEndian; - /// MachOHeader - This struct contains the header information about a - /// specific architecture type/subtype pair that is emitted to the file. - struct MachOHeader { - uint32_t magic; // mach magic number identifier - uint32_t filetype; // type of file - uint32_t ncmds; // number of load commands - uint32_t sizeofcmds; // the size of all the load commands - uint32_t flags; // flags - uint32_t reserved; // 64-bit only - - /// HeaderData - The actual data for the header which we are building - /// up for emission to the file. - DataBuffer HeaderData; - - // Constants for the filetype field - // see for additional info on the various types - enum { MH_OBJECT = 1, // relocatable object file - MH_EXECUTE = 2, // demand paged executable file - MH_FVMLIB = 3, // fixed VM shared library file - MH_CORE = 4, // core file - MH_PRELOAD = 5, // preloaded executable file - MH_DYLIB = 6, // dynamically bound shared library - MH_DYLINKER = 7, // dynamic link editor - MH_BUNDLE = 8, // dynamically bound bundle file - MH_DYLIB_STUB = 9, // shared library stub for static linking only - MH_DSYM = 10 // companion file wiht only debug sections - }; - - // Constants for the flags field - enum { MH_NOUNDEFS = 1 << 0, - // the object file has no undefined references - MH_INCRLINK = 1 << 1, - // the object file is the output of an incremental link against - // a base file and cannot be link edited again - MH_DYLDLINK = 1 << 2, - // the object file is input for the dynamic linker and cannot be - // statically link edited again. - MH_BINDATLOAD = 1 << 3, - // the object file's undefined references are bound by the - // dynamic linker when loaded. - MH_PREBOUND = 1 << 4, - // the file has its dynamic undefined references prebound - MH_SPLIT_SEGS = 1 << 5, - // the file has its read-only and read-write segments split - // see - MH_LAZY_INIT = 1 << 6, - // the shared library init routine is to be run lazily via - // catching memory faults to its writable segments (obsolete) - MH_TWOLEVEL = 1 << 7, - // the image is using two-level namespace bindings - MH_FORCE_FLAT = 1 << 8, - // the executable is forcing all images to use flat namespace - // bindings. - MH_NOMULTIDEFS = 1 << 8, - // this umbrella guarantees no multiple definitions of symbols - // in its sub-images so the two-level namespace hints can - // always be used. - MH_NOFIXPREBINDING = 1 << 10, - // do not have dyld notify the prebidning agent about this - // executable. - MH_PREBINDABLE = 1 << 11, - // the binary is not prebound but can have its prebinding - // redone. only used when MH_PREBOUND is not set. - MH_ALLMODSBOUND = 1 << 12, - // indicates that this binary binds to all two-level namespace - // modules of its dependent libraries. Only used when - // MH_PREBINDABLE and MH_TWOLEVEL are both set. - MH_SUBSECTIONS_VIA_SYMBOLS = 1 << 13, - // safe to divide up the sections into sub-sections via symbols - // for dead code stripping. - MH_CANONICAL = 1 << 14, - // the binary has been canonicalized via the unprebind operation - MH_WEAK_DEFINES = 1 << 15, - // the final linked image contains external weak symbols - MH_BINDS_TO_WEAK = 1 << 16, - // the final linked image uses weak symbols - MH_ALLOW_STACK_EXECUTION = 1 << 17 - // When this bit is set, all stacks in the task will be given - // stack execution privilege. Only used in MH_EXECUTE filetype - }; + // Target Asm Info - MachOHeader() : magic(0), filetype(0), ncmds(0), sizeofcmds(0), flags(0), - reserved(0) { } - - /// cmdSize - This routine returns the size of the MachOSection as written - /// to disk, depending on whether the destination is a 64 bit Mach-O file. - unsigned cmdSize(bool is64Bit) const { - if (is64Bit) - return 8 * sizeof(uint32_t); - else - return 7 * sizeof(uint32_t); - } + const TargetAsmInfo *TAI; - /// setMagic - This routine sets the appropriate value for the 'magic' - /// field based on pointer size and endianness. - void setMagic(bool isLittleEndian, bool is64Bit) { - if (isLittleEndian) - if (is64Bit) magic = 0xcffaedfe; - else magic = 0xcefaedfe; - else - if (is64Bit) magic = 0xfeedfacf; - else magic = 0xfeedface; - } - }; - /// Header - An instance of MachOHeader that we will update while we build /// the file, and then emit during finalization. - MachOHeader Header; - /// MachOSegment - This struct contains the necessary information to - /// emit the load commands for each section in the file. - struct MachOSegment { - uint32_t cmd; // LC_SEGMENT or LC_SEGMENT_64 - uint32_t cmdsize; // Total size of this struct and section commands - std::string segname; // segment name - uint64_t vmaddr; // address of this segment - uint64_t vmsize; // size of this segment, may be larger than filesize - uint64_t fileoff; // offset in file - uint64_t filesize; // amount to read from file - uint32_t maxprot; // maximum VM protection - uint32_t initprot; // initial VM protection - uint32_t nsects; // number of sections in this segment - uint32_t flags; // flags - - // The following constants are getting pulled in by one of the - // system headers, which creates a neat clash with the enum. -#if !defined(VM_PROT_NONE) -#define VM_PROT_NONE 0x00 -#endif -#if !defined(VM_PROT_READ) -#define VM_PROT_READ 0x01 -#endif -#if !defined(VM_PROT_WRITE) -#define VM_PROT_WRITE 0x02 -#endif -#if !defined(VM_PROT_EXECUTE) -#define VM_PROT_EXECUTE 0x04 -#endif -#if !defined(VM_PROT_ALL) -#define VM_PROT_ALL 0x07 -#endif + MachOHeader Header; - // Constants for the vm protection fields - // see - enum { SEG_VM_PROT_NONE = VM_PROT_NONE, - SEG_VM_PROT_READ = VM_PROT_READ, // read permission - SEG_VM_PROT_WRITE = VM_PROT_WRITE, // write permission - SEG_VM_PROT_EXECUTE = VM_PROT_EXECUTE, - SEG_VM_PROT_ALL = VM_PROT_ALL - }; - - // Constants for the cmd field - // see - enum { LC_SEGMENT = 0x01, // segment of this file to be mapped - LC_SEGMENT_64 = 0x19 // 64-bit segment of this file to be mapped - }; - - /// cmdSize - This routine returns the size of the MachOSection as written - /// to disk, depending on whether the destination is a 64 bit Mach-O file. - unsigned cmdSize(bool is64Bit) const { - if (is64Bit) - return 6 * sizeof(uint32_t) + 4 * sizeof(uint64_t) + 16; - else - return 10 * sizeof(uint32_t) + 16; // addresses only 32 bits - } + /// doInitialization - Emit the file header and all of the global variables + /// for the module to the Mach-O file. - MachOSegment(const std::string &seg, bool is64Bit) - : cmd(is64Bit ? LC_SEGMENT_64 : LC_SEGMENT), cmdsize(0), segname(seg), - vmaddr(0), vmsize(0), fileoff(0), filesize(0), maxprot(VM_PROT_ALL), - initprot(VM_PROT_ALL), nsects(0), flags(0) { } - }; + bool doInitialization(Module &M); - /// MachOSection - This struct contains information about each section in a - /// particular segment that is emitted to the file. This is eventually - /// turned into the SectionCommand in the load command for a particlar - /// segment. - struct MachOSection { - std::string sectname; // name of this section, - std::string segname; // segment this section goes in - uint64_t addr; // memory address of this section - uint64_t size; // size in bytes of this section - uint32_t offset; // file offset of this section - uint32_t align; // section alignment (power of 2) - uint32_t reloff; // file offset of relocation entries - uint32_t nreloc; // number of relocation entries - uint32_t flags; // flags (section type and attributes) - uint32_t reserved1; // reserved (for offset or index) - uint32_t reserved2; // reserved (for count or sizeof) - uint32_t reserved3; // reserved (64 bit only) - - /// A unique number for this section, which will be used to match symbols - /// to the correct section. - uint32_t Index; - - /// SectionData - The actual data for this section which we are building - /// up for emission to the file. - DataBuffer SectionData; - - /// RelocBuffer - A buffer to hold the mach-o relocations before we write - /// them out at the appropriate location in the file. - DataBuffer RelocBuffer; - - /// Relocations - The relocations that we have encountered so far in this - /// section that we will need to convert to MachORelocation entries when - /// the file is written. - std::vector Relocations; - - // Constants for the section types (low 8 bits of flags field) - // see - enum { S_REGULAR = 0, - // regular section - S_ZEROFILL = 1, - // zero fill on demand section - S_CSTRING_LITERALS = 2, - // section with only literal C strings - S_4BYTE_LITERALS = 3, - // section with only 4 byte literals - S_8BYTE_LITERALS = 4, - // section with only 8 byte literals - S_LITERAL_POINTERS = 5, - // section with only pointers to literals - S_NON_LAZY_SYMBOL_POINTERS = 6, - // section with only non-lazy symbol pointers - S_LAZY_SYMBOL_POINTERS = 7, - // section with only lazy symbol pointers - S_SYMBOL_STUBS = 8, - // section with only symbol stubs - // byte size of stub in the reserved2 field - S_MOD_INIT_FUNC_POINTERS = 9, - // section with only function pointers for initialization - S_MOD_TERM_FUNC_POINTERS = 10, - // section with only function pointers for termination - S_COALESCED = 11, - // section contains symbols that are coalesced - S_GB_ZEROFILL = 12, - // zero fill on demand section (that can be larger than 4GB) - S_INTERPOSING = 13, - // section with only pairs of function pointers for interposing - S_16BYTE_LITERALS = 14 - // section with only 16 byte literals - }; - - // Constants for the section flags (high 24 bits of flags field) - // see - enum { S_ATTR_PURE_INSTRUCTIONS = 1 << 31, - // section contains only true machine instructions - S_ATTR_NO_TOC = 1 << 30, - // section contains coalesced symbols that are not to be in a - // ranlib table of contents - S_ATTR_STRIP_STATIC_SYMS = 1 << 29, - // ok to strip static symbols in this section in files with the - // MY_DYLDLINK flag - S_ATTR_NO_DEAD_STRIP = 1 << 28, - // no dead stripping - S_ATTR_LIVE_SUPPORT = 1 << 27, - // blocks are live if they reference live blocks - S_ATTR_SELF_MODIFYING_CODE = 1 << 26, - // used with i386 code stubs written on by dyld - S_ATTR_DEBUG = 1 << 25, - // a debug section - S_ATTR_SOME_INSTRUCTIONS = 1 << 10, - // section contains some machine instructions - S_ATTR_EXT_RELOC = 1 << 9, - // section has external relocation entries - S_ATTR_LOC_RELOC = 1 << 8 - // section has local relocation entries - }; + bool runOnMachineFunction(MachineFunction &MF); - /// cmdSize - This routine returns the size of the MachOSection as written - /// to disk, depending on whether the destination is a 64 bit Mach-O file. - unsigned cmdSize(bool is64Bit) const { - if (is64Bit) - return 7 * sizeof(uint32_t) + 2 * sizeof(uint64_t) + 32; - else - return 9 * sizeof(uint32_t) + 32; // addresses only 32 bits - } + /// doFinalization - Now that the module has been completely processed, emit + /// the Mach-O file to 'O'. - MachOSection(const std::string &seg, const std::string §) - : sectname(sect), segname(seg), addr(0), size(0), offset(0), align(2), - reloff(0), nreloc(0), flags(0), reserved1(0), reserved2(0), - reserved3(0) { } - }; + bool doFinalization(Module &M); private: /// SectionList - This is the list of sections that we have emitted to the /// file. Once the file has been completely built, the segment load command /// SectionCommands are constructed from this info. + std::vector SectionList; /// SectionLookup - This is a mapping from section name to SectionList entry + std::map SectionLookup; /// GVSection - This is a mapping from a GlobalValue to a MachOSection, /// to aid in emitting relocations. + std::map GVSection; /// GVOffset - This is a mapping from a GlobalValue to an offset from the /// start of the section in which the GV resides, to aid in emitting /// relocations. + std::map GVOffset; /// getSection - Return the section with the specified name, creating a new /// section if one does not already exist. + MachOSection *getSection(const std::string &seg, const std::string §, unsigned Flags = 0) { MachOSection *MOS = SectionLookup[seg+sect]; @@ -511,63 +196,11 @@ nsyms(0), stroff(0), strsize(0) { } }; - /// MachOSymTab - This struct contains information about the offsets and - /// size of symbol table information. - /// segment. - struct MachODySymTab { - uint32_t cmd; // LC_DYSYMTAB - uint32_t cmdsize; // sizeof( MachODySymTab ) - uint32_t ilocalsym; // index to local symbols - uint32_t nlocalsym; // number of local symbols - uint32_t iextdefsym; // index to externally defined symbols - uint32_t nextdefsym; // number of externally defined symbols - uint32_t iundefsym; // index to undefined symbols - uint32_t nundefsym; // number of undefined symbols - uint32_t tocoff; // file offset to table of contents - uint32_t ntoc; // number of entries in table of contents - uint32_t modtaboff; // file offset to module table - uint32_t nmodtab; // number of module table entries - uint32_t extrefsymoff; // offset to referenced symbol table - uint32_t nextrefsyms; // number of referenced symbol table entries - uint32_t indirectsymoff; // file offset to the indirect symbol table - uint32_t nindirectsyms; // number of indirect symbol table entries - uint32_t extreloff; // offset to external relocation entries - uint32_t nextrel; // number of external relocation entries - uint32_t locreloff; // offset to local relocation entries - uint32_t nlocrel; // number of local relocation entries - - // Constants for the cmd field - // see - enum { LC_DYSYMTAB = 0x0B // dynamic link-edit symbol table info - }; - - MachODySymTab() : cmd(LC_DYSYMTAB), cmdsize(20 * sizeof(uint32_t)), - ilocalsym(0), nlocalsym(0), iextdefsym(0), nextdefsym(0), - iundefsym(0), nundefsym(0), tocoff(0), ntoc(0), modtaboff(0), - nmodtab(0), extrefsymoff(0), nextrefsyms(0), indirectsymoff(0), - nindirectsyms(0), extreloff(0), nextrel(0), locreloff(0), nlocrel(0) { } - }; - /// SymTab - The "stab" style symbol table information MachOSymTab SymTab; /// DySymTab - symbol table info for the dynamic link editor MachODySymTab DySymTab; - struct MachOSymCmp { - // FIXME: this does not appear to be sorting 'f' after 'F' - bool operator()(const MachOSym &LHS, const MachOSym &RHS) { - return LHS.GVName < RHS.GVName; - } - }; - - /// PartitionByLocal - Simple boolean predicate that returns true if Sym is - /// a local symbol rather than an external symbol. - static bool PartitionByLocal(const MachOSym &Sym); - - /// PartitionByDefined - Simple boolean predicate that returns true if Sym - /// is defined in this module. - static bool PartitionByDefined(const MachOSym &Sym); - protected: /// SymbolTable - This is the list of symbols we have emitted to the file. @@ -601,6 +234,7 @@ void EmitGlobal(GlobalVariable *GV); void EmitHeaderAndLoadCommands(); void EmitSections(); + void EmitRelocations(); void BufferSymbolAndStringTable(); void CalculateRelocations(MachOSection &MOS); From evan.cheng at apple.com Tue Jun 2 23:59:03 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 2 Jun 2009 21:59:03 -0700 Subject: [llvm-commits] [llvm] r70270 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Alpha/AsmPrinter/ lib In-Reply-To: <352a1fb20906021443g6317857eoa5ac7c89ff8cb29a@mail.gmail.com> References: <352a1fb20906021032tb1909afn3c2e0eb8818f0d82@mail.gmail.com> <236B22EC-8D07-4655-951B-9FF060A5FEAD@apple.com> <352a1fb20906021443g6317857eoa5ac7c89ff8cb29a@mail.gmail.com> Message-ID: <83C1211A-8241-44F9-8B45-718043CA43BB@apple.com> On Jun 2, 2009, at 2:43 PM, Devang Patel wrote: > On Tue, Jun 2, 2009 at 1:59 PM, Evan Cheng > wrote: >> >> On Jun 2, 2009, at 10:32 AM, Devang Patel wrote: >> >>> We already use a function attribute for -Os. Why not do the same >>> here >>> ? >> >> This controls what codegen passes are being run. It's done once for >> the whole compilation. > > This info should be encoded in bc files so that we don't have to > remember passing additional command line option on llc (and other > tools that operate on bc files). BTW, -Os is also applied to entire > compilation unit. Sure. We can do that. That just means we can either control the codegen optimization level from llc command line or use the information encoded in bc file. This patch is still needed. Evan > > - > Devang > >> Function notes are for finer grain control that >> tell these passes to "behave" differently for individual functions. >> Yes, we could use function notes to control optimization level for >> individual functions. But I view that as a different issue. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Wed Jun 3 00:15:46 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 03 Jun 2009 05:15:46 -0000 Subject: [llvm-commits] [llvm] r72755 - /llvm/trunk/lib/CodeGen/LiveVariables.cpp Message-ID: <200906030515.n535Flij015182@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 3 00:15:46 2009 New Revision: 72755 URL: http://llvm.org/viewvc/llvm-project?rev=72755&view=rev Log: If there is a def of a super-register followed by a use of a sub-register, do *not* add an implicit def of the sub-register. e.g. EAX = ..., AX .. = AX This creates a double-def. Apparently this used to be necessary but is no longer needed. Thanks to Anton for pointing this out. Anton, I cannot create a test case without your uncommitted ARM patches. Please check in a test case for me. Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=72755&r1=72754&r2=72755&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Wed Jun 3 00:15:46 2009 @@ -242,20 +242,6 @@ } } - // There was an earlier def of a super-register. Add implicit def to that MI. - // - // A: EAX = ... - // B: ... = AX - // - // Add implicit def to A if there isn't a use of AX (or EAX) before B. - if (!PhysRegUse[Reg]) { - MachineInstr *Def = PhysRegDef[Reg]; - if (Def && !Def->modifiesRegister(Reg)) - Def->addOperand(MachineOperand::CreateReg(Reg, - true /*IsDef*/, - true /*IsImp*/)); - } - // Remember this use. PhysRegUse[Reg] = MI; for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); From evan.cheng at apple.com Wed Jun 3 01:14:59 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 03 Jun 2009 06:14:59 -0000 Subject: [llvm-commits] [llvm] r72756 - in /llvm/trunk: lib/Target/ARM/ARMLoadStoreOptimizer.cpp test/CodeGen/ARM/str_pre-2.ll Message-ID: <200906030614.n536Exl4016928@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 3 01:14:58 2009 New Revision: 72756 URL: http://llvm.org/viewvc/llvm-project?rev=72756&view=rev Log: Fold preceding / trailing base inc / dec into the single load / store as well. Added: llvm/trunk/test/CodeGen/ARM/str_pre-2.ll Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=72756&r1=72755&r2=72756&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed Jun 3 01:14:58 2009 @@ -697,7 +697,7 @@ // LDM/STM ops. for (unsigned i = 0, e = MBBII.size(); i < e; ++i) if (mergeBaseUpdateLSMultiple(MBB, MBBII[i], Advance, MBBI)) - NumMerges++; + ++NumMerges; NumMerges += MBBII.size(); // Try folding preceeding/trailing base inc/dec into those load/store @@ -705,10 +705,17 @@ for (unsigned i = 0; i != NumMemOps; ++i) if (!MemOps[i].Merged) if (mergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII,Advance,MBBI)) - NumMerges++; + ++NumMerges; // RS may be pointing to an instruction that's deleted. RS->skipTo(prior(MBBI)); + } else if (NumMemOps == 1) { + // Try folding preceeding/trailing base inc/dec into the single + // load/store. + if (mergeBaseUpdateLoadStore(MBB, MemOps[0].MBBI, TII, Advance, MBBI)) { + ++NumMerges; + RS->skipTo(prior(MBBI)); + } } CurrBase = 0; Added: llvm/trunk/test/CodeGen/ARM/str_pre-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/str_pre-2.ll?rev=72756&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/str_pre-2.ll (added) +++ llvm/trunk/test/CodeGen/ARM/str_pre-2.ll Wed Jun 3 01:14:58 2009 @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu | grep {str.*\\!} +; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #+4} + + at b = external global i64* + +define i64 @t(i64 %a) nounwind readonly { +entry: + %0 = load i64** @b, align 4 + %1 = load i64* %0, align 4 + %2 = mul i64 %1, %a + ret i64 %2 +} From baldrick at free.fr Wed Jun 3 01:38:50 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 03 Jun 2009 08:38:50 +0200 Subject: [llvm-commits] [llvm] r72700 - in /llvm/trunk/tools/lto: LTOModule.cpp LTOModule.h In-Reply-To: <352a1fb20906021332r5de4a74aw5e13ae380f5942e5@mail.gmail.com> References: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> <4A24FDC1.7010907@free.fr> <352a1fb20906021004va2266dak4fd12227c4469f65@mail.gmail.com> <4A256E0B.8030202@free.fr> <4A2577D3.30302@free.fr> <352a1fb20906021332r5de4a74aw5e13ae380f5942e5@mail.gmail.com> Message-ID: <4A261A7A.2050302@free.fr> Devang Patel wrote: > On Tue, Jun 2, 2009 at 12:04 PM, Duncan Sands wrote: >>> >From the description, I think this is an issue of emulating some funny >>> linker hacks in LTO mode rather than an issue of actual linking. So >>> whether two files are linked with llvm-link has no effect on the >>> issue. >> Isn't LTO supposed to be more or less equivalent to: link using >> llvm-link, optimize using opt, codegen using llc? > > No. In LTO mode, the linker collects and shares information from > bitcode files as well as from non-bitcode object files. > > llvm-link+opt+llc path does not collect & share any info from non-bit > code file. Actually llvlm-link+opt+llc is essentially same as generate > bitcode+opt+llc in this regard. But Nick's patch doesn't seem to have anything to do with non-bit code files... Ciao, Duncan. From nicholas at mxc.ca Wed Jun 3 02:10:44 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 03 Jun 2009 00:10:44 -0700 Subject: [llvm-commits] [llvm] r72700 - in /llvm/trunk/tools/lto: LTOModule.cpp LTOModule.h In-Reply-To: <4A261A7A.2050302@free.fr> References: <200906012033.n51KXAFq000396@zion.cs.uiuc.edu> <4A24FDC1.7010907@free.fr> <352a1fb20906021004va2266dak4fd12227c4469f65@mail.gmail.com> <4A256E0B.8030202@free.fr> <4A2577D3.30302@free.fr> <352a1fb20906021332r5de4a74aw5e13ae380f5942e5@mail.gmail.com> <4A261A7A.2050302@free.fr> Message-ID: <4A2621F4.6090306@mxc.ca> Duncan Sands wrote: > Devang Patel wrote: >> On Tue, Jun 2, 2009 at 12:04 PM, Duncan Sands wrote: >>>> >From the description, I think this is an issue of emulating some funny >>>> linker hacks in LTO mode rather than an issue of actual linking. So >>>> whether two files are linked with llvm-link has no effect on the >>>> issue. >>> Isn't LTO supposed to be more or less equivalent to: link using >>> llvm-link, optimize using opt, codegen using llc? >> No. In LTO mode, the linker collects and shares information from >> bitcode files as well as from non-bitcode object files. >> >> llvm-link+opt+llc path does not collect & share any info from non-bit >> code file. Actually llvlm-link+opt+llc is essentially same as generate >> bitcode+opt+llc in this regard. > > But Nick's patch doesn't seem to have anything to do with non-bit > code files... I think I understand the constraints on the problem. There's nothing wrong without this code in libLTO if all the inputs are .bc files*, and obviously this code doesn't matter if all the inputs to the real linker are .o files. I think the trouble is that they want to mix old objC .o files with newer objC .bc files. Your earlier suggestion about just changing the frontend was on the right track except for one problem: it would constitute a change in the ABI. A .bc file emitted with the newer compiler wouldn't behave correctly when linked with a .o file from the older frontend. Still, it seems to me that this code could be factored better. The whole analysis of the ConstantStruct etc., seems like they belong in an LLVM-aware part of the Apple linker (such a piece probably doesn't exist yet, which explains why it was added to libLTO instead) and the libLTO side should just be restricted to generic operations like 'addSymbol' or 'undefineSymbol'. Nick * It's not clear to me why not. My guess is that the runtime library has been updated to not do the startup-time rewriting of the superclass pointer, and the nonsense of having "strange contortions to avoid real linker symbols" is moot when you're doing LTO anyways since those symbols will fall away from normal LTO optimization. From jlerouge at apple.com Wed Jun 3 02:20:30 2009 From: jlerouge at apple.com (Julien Lerouge) Date: Wed, 3 Jun 2009 00:20:30 -0700 Subject: [llvm-commits] [llvm] r72650 - in /llvm/trunk: include/llvm/CodeGen/JITCodeEmitter.h include/llvm/CodeGen/MachineCodeEmitter.h include/llvm/ExecutionEngine/JITMemoryManager.h lib/CodeGen/MachOWriter.cpp lib/CodeGen/MachOWriter.h lib/ExecutionEngine/JIT/JITEmitter.cpp lib/ExecutionEngine/JIT/JITMemoryManager.cpp In-Reply-To: <200905302350.n4UNoXXG020528@zion.cs.uiuc.edu> References: <200905302350.n4UNoXXG020528@zion.cs.uiuc.edu> Message-ID: <20090603072029.GA24816@pom.apple.com> On Sat, May 30, 2009 at 11:50:33PM +0000, Bruno Cardoso Lopes wrote: > Author: bruno > Date: Sat May 30 18:50:33 2009 > New Revision: 72650 > URL: http://llvm.org/viewvc/llvm-project?rev=72650&view=rev > Log: > Use uint8_t and int32_t in {JIT,Machine}CodeEmiters > Modified: > llvm/trunk/include/llvm/CodeGen/JITCodeEmitter.h > llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h > llvm/trunk/include/llvm/ExecutionEngine/JITMemoryManager.h > llvm/trunk/lib/CodeGen/MachOWriter.cpp > llvm/trunk/lib/CodeGen/MachOWriter.h > llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp > llvm/trunk/lib/ExecutionEngine/JIT/JITMemoryManager.cpp Hello Bruno, I have a buildbot running some nightly tests here on MingW that started to complain somewhere between r72618 and r72690. Some of the tests we are running with lli are triggering the following assertion: Assertion failed: Addr && "Code generation didn't add function to GlobalAddress table!", file c:/cygwin/home/jlerouge/buildbot/llvm-src/lib/ExecutionEngine/JIT/JIT.cpp, line 603 I realize this is very vague, but maybe you have any idea where that could be coming from ? Those tests have been pretty stable for the last couple month. I'll take a closer look in the coming days, but in the meantime, I thought I'd give a heads up ;-) Thanks, Julien -- Julien Lerouge PGP Key Id: 0xB1964A62 PGP Fingerprint: 392D 4BAD DB8B CE7F 4E5F FA3C 62DB 4AA7 B196 4A62 PGP Public Key from: keyserver.pgp.com From evan.cheng at apple.com Wed Jun 3 02:40:49 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 03 Jun 2009 07:40:49 -0000 Subject: [llvm-commits] [llvm] r72757 - in /llvm/trunk: lib/Target/ARM/ARMLoadStoreOptimizer.cpp test/CodeGen/ARM/str_pre-2.ll Message-ID: <200906030740.n537en6R024014@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 3 02:40:47 2009 New Revision: 72757 URL: http://llvm.org/viewvc/llvm-project?rev=72757&view=rev Log: Temporarily revert 72756 for now. Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp llvm/trunk/test/CodeGen/ARM/str_pre-2.ll Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=72757&r1=72756&r2=72757&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed Jun 3 02:40:47 2009 @@ -709,13 +709,6 @@ // RS may be pointing to an instruction that's deleted. RS->skipTo(prior(MBBI)); - } else if (NumMemOps == 1) { - // Try folding preceeding/trailing base inc/dec into the single - // load/store. - if (mergeBaseUpdateLoadStore(MBB, MemOps[0].MBBI, TII, Advance, MBBI)) { - ++NumMerges; - RS->skipTo(prior(MBBI)); - } } CurrBase = 0; Modified: llvm/trunk/test/CodeGen/ARM/str_pre-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/str_pre-2.ll?rev=72757&r1=72756&r2=72757&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/str_pre-2.ll (original) +++ llvm/trunk/test/CodeGen/ARM/str_pre-2.ll Wed Jun 3 02:40:47 2009 @@ -1,5 +1,6 @@ ; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu | grep {str.*\\!} ; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #+4} +; XFAIL: * @b = external global i64* From evan.cheng at apple.com Wed Jun 3 04:00:54 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 03 Jun 2009 09:00:54 -0000 Subject: [llvm-commits] [llvm] r72758 - in /llvm/trunk: lib/CodeGen/VirtRegRewriter.cpp test/CodeGen/X86/2009-06-02-RewriterBug.ll Message-ID: <200906030900.n5390v1m000887@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 3 04:00:27 2009 New Revision: 72758 URL: http://llvm.org/viewvc/llvm-project?rev=72758&view=rev Log: Fix for PR4225: When rewriter reuse a value in a physical register , it clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well. Added: llvm/trunk/test/CodeGen/X86/2009-06-02-RewriterBug.ll Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=72758&r1=72757&r2=72758&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Wed Jun 3 04:00:27 2009 @@ -411,9 +411,11 @@ std::vector &KillOps) { if (RegKills[Reg]) { KillOps[Reg]->setIsKill(false); - KillOps[Reg] = NULL; - RegKills.reset(Reg); - for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) { + // KillOps[Reg] might be a def of a super-register. + unsigned KReg = KillOps[Reg]->getReg(); + KillOps[KReg] = NULL; + RegKills.reset(KReg); + for (const unsigned *SR = TRI->getSubRegisters(KReg); *SR; ++SR) { if (RegKills[*SR]) { KillOps[*SR]->setIsKill(false); KillOps[*SR] = NULL; @@ -516,8 +518,18 @@ // That can't be right. Register is killed but not re-defined and it's // being reused. Let's fix that. KillOps[Reg]->setIsKill(false); - KillOps[Reg] = NULL; - RegKills.reset(Reg); + // KillOps[Reg] might be a def of a super-register. + unsigned KReg = KillOps[Reg]->getReg(); + KillOps[KReg] = NULL; + RegKills.reset(KReg); + + // Must be a def of a super-register. Its other sub-regsters are no + // longer killed as well. + for (const unsigned *SR = TRI->getSubRegisters(KReg); *SR; ++SR) { + KillOps[*SR] = NULL; + RegKills.reset(*SR); + } + if (!MI.isRegTiedToDefOperand(i)) // Unless it's a two-address operand, this is the new kill. MO.setIsKill(); @@ -1090,6 +1102,8 @@ VRM.RemoveMachineInstrFromMaps(&NextMI); MBB.erase(&NextMI); ++NumModRefUnfold; + if (NextMII == MBB.end()) + break; } while (FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, VRM)); // Store the value back into SS. Added: llvm/trunk/test/CodeGen/X86/2009-06-02-RewriterBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-06-02-RewriterBug.ll?rev=72758&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-06-02-RewriterBug.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-06-02-RewriterBug.ll Wed Jun 3 04:00:27 2009 @@ -0,0 +1,362 @@ +; RUN: llvm-as < %s | llc -mtriple=x86_64-undermydesk-freebsd8.0 -relocation-model=pic -disable-fp-elim +; PR4225 + +define void @sha256_block1(i32* nocapture %arr, i8* nocapture %in, i64 %num) nounwind { +entry: + br i1 undef, label %while.end, label %bb.nph + +bb.nph: ; preds = %entry + br label %while.body + +while.body: ; preds = %for.end, %bb.nph + %indvar2787 = phi i64 [ 0, %bb.nph ], [ %indvar.next2788, %for.end ] ; [#uses=2] + %tmp2791 = mul i64 %indvar2787, 44 ; [#uses=0] + %ctg22996 = getelementptr i8* %in, i64 0 ; [#uses=1] + %conv = zext i32 undef to i64 ; [#uses=1] + %conv11 = zext i32 undef to i64 ; [#uses=1] + %tmp18 = load i32* undef ; [#uses=1] + %conv19 = zext i32 %tmp18 to i64 ; [#uses=1] + %tmp30 = load i32* undef ; [#uses=1] + %conv31 = zext i32 %tmp30 to i64 ; [#uses=4] + %ptrincdec3065 = load i8* null ; [#uses=1] + %conv442709 = zext i8 %ptrincdec3065 to i64 ; [#uses=1] + %shl45 = shl i64 %conv442709, 16 ; [#uses=1] + %conv632707 = zext i8 undef to i64 ; [#uses=1] + %or = or i64 %shl45, 0 ; [#uses=1] + %or55 = or i64 %or, %conv632707 ; [#uses=1] + %or64 = or i64 %or55, 0 ; [#uses=1] + %shr85 = lshr i64 %conv31, 25 ; [#uses=0] + %add = add i64 %conv11, 1508970993 ; [#uses=1] + %add95 = add i64 %add, 0 ; [#uses=1] + %add98 = add i64 %add95, 0 ; [#uses=1] + %add99 = add i64 %add98, %or64 ; [#uses=1] + %add134 = add i64 %add99, 0 ; [#uses=4] + store i32 undef, i32* undef + %shl187 = shl i64 %add134, 21 ; [#uses=0] + %and203 = and i64 %add134, %conv31 ; [#uses=1] + %xor208 = xor i64 0, %and203 ; [#uses=1] + %add212 = add i64 0, %xor208 ; [#uses=1] + %add213 = add i64 %add212, 0 ; [#uses=1] + %add248 = add i64 %add213, 0 ; [#uses=3] + %conv2852690 = zext i8 undef to i64 ; [#uses=1] + %or277 = or i64 0, %conv2852690 ; [#uses=1] + %or286 = or i64 %or277, 0 ; [#uses=1] + %neg319 = xor i64 %add248, 4294967295 ; [#uses=1] + %and321 = and i64 %neg319, %conv31 ; [#uses=1] + %xor322 = xor i64 %and321, 0 ; [#uses=1] + %add314 = add i64 %conv, 2870763221 ; [#uses=1] + %add323 = add i64 %add314, %or286 ; [#uses=1] + %add326 = add i64 %add323, %xor322 ; [#uses=1] + %add327 = add i64 %add326, 0 ; [#uses=2] + %add362 = add i64 %add327, %conv19 ; [#uses=4] + %add365 = add i64 0, %add327 ; [#uses=3] + %shl409 = shl i64 %add362, 26 ; [#uses=0] + %and431 = and i64 %add362, %add248 ; [#uses=1] + %neg433 = xor i64 %add362, -1 ; [#uses=1] + %and435 = and i64 %add134, %neg433 ; [#uses=1] + %xor436 = xor i64 %and431, %and435 ; [#uses=1] + %add428 = add i64 %conv31, 3624381080 ; [#uses=1] + %add437 = add i64 %add428, 0 ; [#uses=1] + %add440 = add i64 %add437, %xor436 ; [#uses=1] + %add441 = add i64 %add440, 0 ; [#uses=1] + %shl443 = shl i64 %add365, 30 ; [#uses=1] + %and445 = lshr i64 %add365, 2 ; [#uses=1] + %shr446 = and i64 %and445, 1073741823 ; [#uses=1] + %or447 = or i64 %shr446, %shl443 ; [#uses=1] + %xor461 = xor i64 0, %or447 ; [#uses=1] + %add473 = add i64 %xor461, 0 ; [#uses=1] + %add479 = add i64 %add473, %add441 ; [#uses=3] + %conv4932682 = zext i8 undef to i64 ; [#uses=1] + %shl494 = shl i64 %conv4932682, 16 ; [#uses=1] + %ptrincdec4903012 = load i8* null ; [#uses=1] + %conv5032681 = zext i8 %ptrincdec4903012 to i64 ; [#uses=1] + %shl504 = shl i64 %conv5032681, 8 ; [#uses=1] + %ptrincdec5003009 = load i8* null ; [#uses=1] + %conv5132680 = zext i8 %ptrincdec5003009 to i64 ; [#uses=1] + %or495 = or i64 %shl494, 0 ; [#uses=1] + %or505 = or i64 %or495, %conv5132680 ; [#uses=1] + %or514 = or i64 %or505, %shl504 ; [#uses=1] + store i32 undef, i32* undef + %or540 = or i64 undef, 0 ; [#uses=0] + %add542 = add i64 %add134, 310598401 ; [#uses=1] + %add551 = add i64 %add542, %or514 ; [#uses=1] + %add554 = add i64 %add551, 0 ; [#uses=1] + %add555 = add i64 %add554, 0 ; [#uses=1] + %or561 = or i64 undef, undef ; [#uses=1] + %or567 = or i64 undef, undef ; [#uses=1] + %and572 = lshr i64 %add479, 22 ; [#uses=1] + %shr573 = and i64 %and572, 1023 ; [#uses=1] + %or574 = or i64 %shr573, 0 ; [#uses=1] + %xor568 = xor i64 %or567, %or574 ; [#uses=1] + %xor575 = xor i64 %xor568, %or561 ; [#uses=1] + %add587 = add i64 %xor575, 0 ; [#uses=1] + %add593 = add i64 %add587, %add555 ; [#uses=1] + %ptrincdec6043000 = load i8* null ; [#uses=1] + %conv6172676 = zext i8 %ptrincdec6043000 to i64 ; [#uses=1] + %shl618 = shl i64 %conv6172676, 8 ; [#uses=1] + %ptrincdec6142997 = load i8* %ctg22996 ; [#uses=1] + %conv6272675 = zext i8 %ptrincdec6142997 to i64 ; [#uses=1] + %or619 = or i64 0, %conv6272675 ; [#uses=1] + %or628 = or i64 %or619, %shl618 ; [#uses=1] + %add656 = add i64 %add248, 607225278 ; [#uses=1] + %add665 = add i64 %add656, %or628 ; [#uses=1] + %add668 = add i64 %add665, 0 ; [#uses=1] + %add669 = add i64 %add668, 0 ; [#uses=1] + %and699 = and i64 %add479, %add365 ; [#uses=1] + %xor700 = xor i64 0, %and699 ; [#uses=1] + %add701 = add i64 0, %xor700 ; [#uses=1] + %add707 = add i64 %add701, %add669 ; [#uses=4] + %ptrincdec6242994 = load i8* null ; [#uses=1] + %conv7122673 = zext i8 %ptrincdec6242994 to i64 ; [#uses=1] + %shl713 = shl i64 %conv7122673, 24 ; [#uses=1] + %conv7412670 = zext i8 undef to i64 ; [#uses=1] + %or723 = or i64 0, %shl713 ; [#uses=1] + %or733 = or i64 %or723, %conv7412670 ; [#uses=1] + %or742 = or i64 %or733, 0 ; [#uses=2] + %conv743 = trunc i64 %or742 to i32 ; [#uses=1] + store i32 %conv743, i32* undef + %xor762 = xor i64 undef, 0 ; [#uses=0] + %add770 = add i64 %add362, 1426881987 ; [#uses=1] + %add779 = add i64 %add770, %or742 ; [#uses=1] + %add782 = add i64 %add779, 0 ; [#uses=1] + %add783 = add i64 %add782, 0 ; [#uses=1] + %shl785 = shl i64 %add707, 30 ; [#uses=1] + %and787 = lshr i64 %add707, 2 ; [#uses=1] + %shr788 = and i64 %and787, 1073741823 ; [#uses=1] + %or789 = or i64 %shr788, %shl785 ; [#uses=1] + %shl791 = shl i64 %add707, 19 ; [#uses=0] + %xor803 = xor i64 0, %or789 ; [#uses=1] + %and813 = and i64 %add593, %add479 ; [#uses=1] + %xor814 = xor i64 0, %and813 ; [#uses=1] + %add815 = add i64 %xor803, %xor814 ; [#uses=1] + %add821 = add i64 %add815, %add783 ; [#uses=1] + %add1160 = add i64 0, %add707 ; [#uses=0] + %add1157 = add i64 undef, undef ; [#uses=0] + %ptrincdec11742940 = load i8* null ; [#uses=1] + %conv11872651 = zext i8 %ptrincdec11742940 to i64 ; [#uses=1] + %shl1188 = shl i64 %conv11872651, 8 ; [#uses=1] + %or1198 = or i64 0, %shl1188 ; [#uses=1] + store i32 undef, i32* undef + %add1226 = add i64 %or1198, 3248222580 ; [#uses=1] + %add1235 = add i64 %add1226, 0 ; [#uses=1] + %add1238 = add i64 %add1235, 0 ; [#uses=1] + %add1239 = add i64 %add1238, 0 ; [#uses=1] + br label %for.cond + +for.cond: ; preds = %for.body, %while.body + %add821.pn = phi i64 [ %add821, %while.body ], [ undef, %for.body ] ; [#uses=0] + %add1239.pn = phi i64 [ %add1239, %while.body ], [ 0, %for.body ] ; [#uses=0] + br i1 undef, label %for.end, label %for.body + +for.body: ; preds = %for.cond + br label %for.cond + +for.end: ; preds = %for.cond + %indvar.next2788 = add i64 %indvar2787, 1 ; [#uses=1] + br i1 undef, label %while.end, label %while.body + +while.end: ; preds = %for.end, %entry + ret void +} + +define void @sha256_block2(i32* nocapture %arr, i8* nocapture %in, i64 %num) nounwind { +entry: + br i1 undef, label %while.end, label %bb.nph + +bb.nph: ; preds = %entry + %arrayidx5 = getelementptr i32* %arr, i64 1 ; [#uses=1] + %arrayidx9 = getelementptr i32* %arr, i64 2 ; [#uses=2] + %arrayidx13 = getelementptr i32* %arr, i64 3 ; [#uses=2] + %arrayidx25 = getelementptr i32* %arr, i64 6 ; [#uses=1] + %arrayidx29 = getelementptr i32* %arr, i64 7 ; [#uses=1] + br label %while.body + +while.body: ; preds = %for.end, %bb.nph + %tmp3 = load i32* %arr ; [#uses=2] + %conv = zext i32 %tmp3 to i64 ; [#uses=1] + %tmp10 = load i32* %arrayidx9 ; [#uses=1] + %conv11 = zext i32 %tmp10 to i64 ; [#uses=1] + %tmp14 = load i32* %arrayidx13 ; [#uses=3] + %conv15 = zext i32 %tmp14 to i64 ; [#uses=2] + %tmp18 = load i32* undef ; [#uses=2] + %conv19 = zext i32 %tmp18 to i64 ; [#uses=1] + %conv23 = zext i32 undef to i64 ; [#uses=1] + %tmp26 = load i32* %arrayidx25 ; [#uses=1] + %conv27 = zext i32 %tmp26 to i64 ; [#uses=1] + %tmp30 = load i32* %arrayidx29 ; [#uses=2] + %conv31 = zext i32 %tmp30 to i64 ; [#uses=5] + %shl72 = shl i64 %conv31, 26 ; [#uses=1] + %shr = lshr i64 %conv31, 6 ; [#uses=1] + %or74 = or i64 %shl72, %shr ; [#uses=1] + %shr85 = lshr i64 %conv31, 25 ; [#uses=0] + %xor87 = xor i64 0, %or74 ; [#uses=1] + %and902706 = and i32 %tmp30, %tmp3 ; [#uses=1] + %and90 = zext i32 %and902706 to i64 ; [#uses=1] + %xor94 = xor i64 0, %and90 ; [#uses=1] + %add = add i64 %conv11, 1508970993 ; [#uses=1] + %add95 = add i64 %add, %xor94 ; [#uses=1] + %add98 = add i64 %add95, %xor87 ; [#uses=1] + %add99 = add i64 %add98, 0 ; [#uses=2] + %xor130 = zext i32 undef to i64 ; [#uses=1] + %add134 = add i64 %add99, %conv27 ; [#uses=2] + %add131 = add i64 %xor130, 0 ; [#uses=1] + %add137 = add i64 %add131, %add99 ; [#uses=5] + %conv1422700 = zext i8 undef to i64 ; [#uses=1] + %shl143 = shl i64 %conv1422700, 24 ; [#uses=1] + %ptrincdec1393051 = load i8* undef ; [#uses=1] + %conv1512699 = zext i8 %ptrincdec1393051 to i64 ; [#uses=1] + %shl152 = shl i64 %conv1512699, 16 ; [#uses=1] + %conv1712697 = zext i8 undef to i64 ; [#uses=1] + %or153 = or i64 %shl152, %shl143 ; [#uses=1] + %or163 = or i64 %or153, %conv1712697 ; [#uses=1] + %or172 = or i64 %or163, 0 ; [#uses=1] + %and203 = and i64 %add134, %conv31 ; [#uses=1] + %xor208 = xor i64 0, %and203 ; [#uses=1] + %add200 = add i64 0, 2453635748 ; [#uses=1] + %add209 = add i64 %add200, %or172 ; [#uses=1] + %add212 = add i64 %add209, %xor208 ; [#uses=1] + %add213 = add i64 %add212, 0 ; [#uses=2] + %shl228 = shl i64 %add137, 10 ; [#uses=1] + %and230 = lshr i64 %add137, 22 ; [#uses=1] + %shr231 = and i64 %and230, 1023 ; [#uses=1] + %or232 = or i64 %shr231, %shl228 ; [#uses=1] + %xor226 = xor i64 0, %or232 ; [#uses=1] + %xor233 = xor i64 %xor226, 0 ; [#uses=1] + %and2362695 = zext i32 undef to i64 ; [#uses=1] + %xor240 = and i64 %add137, %and2362695 ; [#uses=1] + %and2432694 = and i32 %tmp18, %tmp14 ; [#uses=1] + %and243 = zext i32 %and2432694 to i64 ; [#uses=1] + %xor244 = xor i64 %xor240, %and243 ; [#uses=1] + %add248 = add i64 %add213, %conv23 ; [#uses=2] + %add245 = add i64 %xor233, %xor244 ; [#uses=1] + %add251 = add i64 %add245, %add213 ; [#uses=1] + %conv2752691 = zext i8 undef to i64 ; [#uses=1] + %shl276 = shl i64 %conv2752691, 8 ; [#uses=0] + %and317 = and i64 %add248, %add134 ; [#uses=1] + %neg319 = xor i64 %add248, 4294967295 ; [#uses=1] + %and321 = and i64 %neg319, %conv31 ; [#uses=1] + %xor322 = xor i64 %and321, %and317 ; [#uses=1] + %add314 = add i64 %conv, 2870763221 ; [#uses=1] + %add323 = add i64 %add314, 0 ; [#uses=1] + %add326 = add i64 %add323, %xor322 ; [#uses=1] + %add327 = add i64 %add326, 0 ; [#uses=2] + %and3502689 = xor i64 %add137, %conv15 ; [#uses=1] + %xor354 = and i64 %add251, %and3502689 ; [#uses=1] + %and357 = and i64 %add137, %conv15 ; [#uses=1] + %xor358 = xor i64 %xor354, %and357 ; [#uses=1] + %add362 = add i64 %add327, %conv19 ; [#uses=1] + %add359 = add i64 0, %xor358 ; [#uses=1] + %add365 = add i64 %add359, %add327 ; [#uses=1] + %add770 = add i64 %add362, 1426881987 ; [#uses=1] + %add779 = add i64 %add770, 0 ; [#uses=1] + %add782 = add i64 %add779, 0 ; [#uses=1] + %add783 = add i64 %add782, 0 ; [#uses=2] + %add818 = add i64 %add783, %add365 ; [#uses=1] + %add821 = add i64 0, %add783 ; [#uses=1] + store i32 undef, i32* undef + %add1046 = add i64 undef, undef ; [#uses=1] + %add1160 = add i64 undef, undef ; [#uses=1] + store i32 0, i32* undef + %add1235 = add i64 0, %add818 ; [#uses=1] + %add1238 = add i64 %add1235, 0 ; [#uses=1] + %add1239 = add i64 %add1238, 0 ; [#uses=1] + br label %for.cond + +for.cond: ; preds = %for.body, %while.body + %h.0 = phi i64 [ undef, %while.body ], [ %add2035, %for.body ] ; [#uses=1] + %g.0 = phi i64 [ %add1046, %while.body ], [ undef, %for.body ] ; [#uses=1] + %f.0 = phi i64 [ %add1160, %while.body ], [ undef, %for.body ] ; [#uses=1] + %add821.pn = phi i64 [ %add821, %while.body ], [ undef, %for.body ] ; [#uses=0] + %add1239.pn2648 = phi i64 [ %add1239, %while.body ], [ undef, %for.body ] ; [#uses=0] + %d.0 = phi i64 [ undef, %while.body ], [ %add2038, %for.body ] ; [#uses=2] + br i1 undef, label %for.end, label %for.body + +for.body: ; preds = %for.cond + %conv1390 = zext i32 undef to i64 ; [#uses=1] + %add1375 = add i64 0, %h.0 ; [#uses=1] + %add1384 = add i64 %add1375, 0 ; [#uses=1] + %add1391 = add i64 %add1384, %conv1390 ; [#uses=1] + %add1392 = add i64 %add1391, 0 ; [#uses=2] + %or1411 = or i64 0, undef ; [#uses=1] + %xor1405 = xor i64 0, %or1411 ; [#uses=1] + %xor1412 = xor i64 %xor1405, 0 ; [#uses=1] + %add1427 = add i64 %add1392, %d.0 ; [#uses=1] + %add1424 = add i64 %xor1412, 0 ; [#uses=1] + %add1430 = add i64 %add1424, %add1392 ; [#uses=5] + %tmp1438 = load i32* undef ; [#uses=1] + %conv1439 = zext i32 %tmp1438 to i64 ; [#uses=4] + %shl1441 = shl i64 %conv1439, 25 ; [#uses=1] + %shr1444 = lshr i64 %conv1439, 7 ; [#uses=1] + %or1445 = or i64 %shl1441, %shr1444 ; [#uses=1] + %shr1450 = lshr i64 %conv1439, 18 ; [#uses=1] + %or1451 = or i64 0, %shr1450 ; [#uses=1] + %shr1454 = lshr i64 %conv1439, 3 ; [#uses=1] + %xor1452 = xor i64 %or1451, %shr1454 ; [#uses=1] + %xor1455 = xor i64 %xor1452, %or1445 ; [#uses=1] + %conv1464 = zext i32 undef to i64 ; [#uses=4] + %shl1466 = shl i64 %conv1464, 15 ; [#uses=1] + %shr1469 = lshr i64 %conv1464, 17 ; [#uses=1] + %or1470 = or i64 %shl1466, %shr1469 ; [#uses=1] + %shr1475 = lshr i64 %conv1464, 19 ; [#uses=1] + %or1476 = or i64 0, %shr1475 ; [#uses=1] + %shr1479 = lshr i64 %conv1464, 10 ; [#uses=1] + %xor1477 = xor i64 %or1476, %shr1479 ; [#uses=1] + %xor1480 = xor i64 %xor1477, %or1470 ; [#uses=1] + %tmp1499 = load i32* null ; [#uses=1] + %conv1500 = zext i32 %tmp1499 to i64 ; [#uses=1] + %add1491 = add i64 %conv1500, 0 ; [#uses=1] + %add1501 = add i64 %add1491, %xor1455 ; [#uses=1] + %add1502 = add i64 %add1501, %xor1480 ; [#uses=1] + %conv1504 = and i64 %add1502, 4294967295 ; [#uses=1] + %tmp1541 = load i32* undef ; [#uses=1] + %conv1542 = zext i32 %tmp1541 to i64 ; [#uses=1] + %add1527 = add i64 %conv1542, %g.0 ; [#uses=1] + %add1536 = add i64 %add1527, 0 ; [#uses=1] + %add1543 = add i64 %add1536, %conv1504 ; [#uses=1] + %add1544 = add i64 %add1543, 0 ; [#uses=1] + %shl1546 = shl i64 %add1430, 30 ; [#uses=1] + %and1548 = lshr i64 %add1430, 2 ; [#uses=1] + %shr1549 = and i64 %and1548, 1073741823 ; [#uses=1] + %or1550 = or i64 %shr1549, %shl1546 ; [#uses=1] + %shl1552 = shl i64 %add1430, 19 ; [#uses=1] + %or1556 = or i64 0, %shl1552 ; [#uses=1] + %shl1559 = shl i64 %add1430, 10 ; [#uses=1] + %or1563 = or i64 0, %shl1559 ; [#uses=1] + %xor1557 = xor i64 %or1556, %or1563 ; [#uses=1] + %xor1564 = xor i64 %xor1557, %or1550 ; [#uses=1] + %add1576 = add i64 %xor1564, 0 ; [#uses=1] + %add1582 = add i64 %add1576, %add1544 ; [#uses=3] + store i32 undef, i32* undef + %tmp1693 = load i32* undef ; [#uses=1] + %conv1694 = zext i32 %tmp1693 to i64 ; [#uses=1] + %add1679 = add i64 %conv1694, %f.0 ; [#uses=1] + %add1688 = add i64 %add1679, 0 ; [#uses=1] + %add1695 = add i64 %add1688, 0 ; [#uses=1] + %add1696 = add i64 %add1695, 0 ; [#uses=1] + %shl1698 = shl i64 %add1582, 30 ; [#uses=0] + %shl1704 = shl i64 %add1582, 19 ; [#uses=0] + %add1734 = add i64 0, %add1696 ; [#uses=1] + %add1983 = add i64 0, %add1427 ; [#uses=1] + %add1992 = add i64 %add1983, 0 ; [#uses=1] + %add1999 = add i64 %add1992, 0 ; [#uses=1] + %add2000 = add i64 %add1999, 0 ; [#uses=2] + %and2030 = and i64 %add1734, %add1582 ; [#uses=1] + %xor2031 = xor i64 0, %and2030 ; [#uses=1] + %add2035 = add i64 %add2000, %add1430 ; [#uses=1] + %add2032 = add i64 0, %xor2031 ; [#uses=1] + %add2038 = add i64 %add2032, %add2000 ; [#uses=1] + store i32 0, i32* undef + br label %for.cond + +for.end: ; preds = %for.cond + store i32 undef, i32* %arrayidx5 + store i32 undef, i32* %arrayidx9 + %d.02641 = trunc i64 %d.0 to i32 ; [#uses=1] + %conv2524 = add i32 %tmp14, %d.02641 ; [#uses=1] + store i32 %conv2524, i32* %arrayidx13 + %exitcond2789 = icmp eq i64 undef, %num ; [#uses=1] + br i1 %exitcond2789, label %while.end, label %while.body + +while.end: ; preds = %for.end, %entry + ret void +} From ed at 80386.nl Wed Jun 3 04:18:17 2009 From: ed at 80386.nl (Ed Schouten) Date: Wed, 3 Jun 2009 11:18:17 +0200 Subject: [llvm-commits] [llvm] r72758 - in /llvm/trunk: lib/CodeGen/VirtRegRewriter.cpp test/CodeGen/X86/2009-06-02-RewriterBug.ll In-Reply-To: <200906030900.n5390v1m000887@zion.cs.uiuc.edu> References: <200906030900.n5390v1m000887@zion.cs.uiuc.edu> Message-ID: <20090603091817.GZ48776@hoeg.nl> Hi Evan, * Evan Cheng wrote: > Author: evancheng > Date: Wed Jun 3 04:00:27 2009 > New Revision: 72758 > > URL: http://llvm.org/viewvc/llvm-project?rev=72758&view=rev > Log: > Fix for PR4225: When rewriter reuse a value in a physical register , > it clear the register kill operand marker and its kill ops > information. However, the cleared operand may be a def of a > super-register. Clear the kill ops info for the super-register's > sub-registers as well. Thanks a lot! -- Ed Schouten WWW: http://80386.nl/ -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 195 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090603/312e39c8/attachment.bin From anton at korobeynikov.info Wed Jun 3 04:29:57 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Wed, 03 Jun 2009 13:29:57 +0400 Subject: [llvm-commits] [llvm] r72755 - /llvm/trunk/lib/CodeGen/LiveVariables.cpp In-Reply-To: <200906030515.n535Flij015182@zion.cs.uiuc.edu> References: <200906030515.n535Flij015182@zion.cs.uiuc.edu> Message-ID: <1244021397.18321.378.camel@aslstation> Hello, Evan > This creates a double-def. Apparently this used to be necessary but is no longer needed. > Thanks to Anton for pointing this out. > Anton, I cannot create a test case without your uncommitted ARM patches. Please check in a test case for me. Will do as soon as the ARM code in question will land (hopefully on Friday). -- With best regards, Anton Korobeynikov. Faculty of Mathematics & Mechanics, Saint Petersburg State University. From jay.foad at gmail.com Wed Jun 3 05:20:12 2009 From: jay.foad at gmail.com (Jay Foad) Date: Wed, 03 Jun 2009 10:20:12 -0000 Subject: [llvm-commits] [llvm] r72762 - /llvm/trunk/docs/LangRef.html Message-ID: <200906031020.n53AKEjF004361@zion.cs.uiuc.edu> Author: foad Date: Wed Jun 3 05:20:10 2009 New Revision: 72762 URL: http://llvm.org/viewvc/llvm-project?rev=72762&view=rev Log: Document how phi and invoke instructions interact with SSA form. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=72762&r1=72761&r2=72762&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Wed Jun 3 05:20:10 2009 @@ -2403,9 +2403,10 @@ exception. Additionally, this is important for implementation of 'catch' clauses in high-level languages that support them.

-

It is not valid to reference the return value of an invoke call from -anywhere not dominated by the normal label, since an unwind does not -provide a return value.

+

For the purposes of the SSA form, the definition of the value +returned by the 'invoke' instruction is deemed to occur on +the edge from the current block to the "normal" label. If the callee +unwinds then no return value is available.

Example:
@@ -4518,6 +4519,11 @@
 block and the PHI instructions: i.e. PHI instructions must be first in
 a basic block.

 
+
For the purposes of the SSA form, the use of each incoming value is
+deemed to occur on the edge from the corresponding predecessor block
+to the current block (but after any definition of an 'invoke'
+instruction's return value on the same edge).

+
 
Semantics:

 
 
At runtime, the 'phi' instruction logically takes on the value




From baldrick at free.fr  Wed Jun  3 06:54:30 2009
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 03 Jun 2009 11:54:30 -0000
Subject: [llvm-commits] [llvm] r72767 - /llvm/trunk/lib/System/Atomic.cpp
Message-ID: <200906031154.n53BsVaJ007586@zion.cs.uiuc.edu>

Author: baldrick
Date: Wed Jun  3 06:54:28 2009
New Revision: 72767

URL: http://llvm.org/viewvc/llvm-project?rev=72767&view=rev
Log:
At a newline at the end of this file.

Modified:
    llvm/trunk/lib/System/Atomic.cpp

Modified: llvm/trunk/lib/System/Atomic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Atomic.cpp?rev=72767&r1=72766&r2=72767&view=diff

==============================================================================
--- llvm/trunk/lib/System/Atomic.cpp (original)
+++ llvm/trunk/lib/System/Atomic.cpp Wed Jun  3 06:54:28 2009
@@ -50,4 +50,4 @@
 #else
 #  error No compare-and-swap implementation for your platform!
 #endif
-}
\ No newline at end of file
+}




From baldrick at free.fr  Wed Jun  3 07:05:31 2009
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 03 Jun 2009 12:05:31 -0000
Subject: [llvm-commits] [llvm] r72768 -
	/llvm/trunk/lib/Target/X86/X86FastISel.cpp
Message-ID: <200906031205.n53C5WSG007988@zion.cs.uiuc.edu>

Author: baldrick
Date: Wed Jun  3 07:05:18 2009
New Revision: 72768

URL: http://llvm.org/viewvc/llvm-project?rev=72768&view=rev
Log:
Avoid a warning "'U' might be used uninitialized in
this function" when using a not-too-smart compiler.

Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=72768&r1=72767&r2=72768&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Jun  3 07:05:18 2009
@@ -321,7 +321,7 @@
 /// X86SelectAddress - Attempt to fill in an address from the given value.
 ///
 bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
-  User *U;
+  User *U = NULL;
   unsigned Opcode = Instruction::UserOp1;
   if (Instruction *I = dyn_cast(V)) {
     Opcode = I->getOpcode();




From sanjiv.gupta at microchip.com  Wed Jun  3 08:36:46 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Wed, 03 Jun 2009 13:36:46 -0000
Subject: [llvm-commits] [llvm] r72771 - in /llvm/trunk/lib/Target/PIC16:
 PIC16.h PIC16ISelLowering.cpp
Message-ID: <200906031336.n53DalmX011462@zion.cs.uiuc.edu>

Author: sgupta
Date: Wed Jun  3 08:36:44 2009
New Revision: 72771

URL: http://llvm.org/viewvc/llvm-project?rev=72771&view=rev
Log:
Fixed a bug in which signed comparisons were being used instead of unsigned comparisons.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16.h
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp

Modified: llvm/trunk/lib/Target/PIC16/PIC16.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16.h?rev=72771&r1=72770&r2=72771&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16.h Wed Jun  3 08:36:44 2009
@@ -300,9 +300,11 @@
     case PIC16CC::LT:   return "lt";
     case PIC16CC::ULT:   return "lt";
     case PIC16CC::LE:  return "le";
+    case PIC16CC::ULE:  return "le";
     case PIC16CC::GT:  return "gt";
     case PIC16CC::UGT:  return "gt";
     case PIC16CC::GE:   return "ge";
+    case PIC16CC::UGE:   return "ge";
     }
   }
 

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=72771&r1=72770&r2=72771&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Wed Jun  3 08:36:44 2009
@@ -1557,8 +1557,8 @@
   case ISD::SETLT:  return PIC16CC::LT;
   case ISD::SETLE:  return PIC16CC::LE;
   case ISD::SETULT: return PIC16CC::ULT;
-  case ISD::SETULE: return PIC16CC::LE;
-  case ISD::SETUGE: return PIC16CC::GE;
+  case ISD::SETULE: return PIC16CC::ULE;
+  case ISD::SETUGE: return PIC16CC::UGE;
   case ISD::SETUGT: return PIC16CC::UGT;
   }
 }




From jay.foad at gmail.com  Wed Jun  3 09:38:24 2009
From: jay.foad at gmail.com (Jay Foad)
Date: Wed, 3 Jun 2009 15:38:24 +0100
Subject: [llvm-commits] [PATCH] simplify OnlyCalledDirectly()
Message-ID: 

An obvious cleanup, I think. Passes "make check". OK to apply?

Thanks,
Jay.
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From edwintorok at gmail.com  Wed Jun  3 10:06:19 2009
From: edwintorok at gmail.com (Torok Edwin)
Date: Wed, 03 Jun 2009 15:06:19 -0000
Subject: [llvm-commits] [llvm] r72773 - /llvm/trunk/docs/GoldPlugin.html
Message-ID: <200906031506.n53F6JOs014297@zion.cs.uiuc.edu>

Author: edwin
Date: Wed Jun  3 10:06:19 2009
New Revision: 72773

URL: http://llvm.org/viewvc/llvm-project?rev=72773&view=rev
Log:
Document how easy it is to use the gold plugin and have LTO with autotooled projects.
Please correct the documentation if I missed anything.

Modified:
    llvm/trunk/docs/GoldPlugin.html

Modified: llvm/trunk/docs/GoldPlugin.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GoldPlugin.html?rev=72773&r1=72772&r2=72773&view=diff

==============================================================================
--- llvm/trunk/docs/GoldPlugin.html (original)
+++ llvm/trunk/docs/GoldPlugin.html Wed Jun  3 10:06:19 2009
@@ -14,6 +14,7 @@
   
  • Usage
   
    • 
   
  • Licensing
    • 
 
@@ -136,6 +137,34 @@
 
 
 
+
    Quickstart for using LTO with autotooled projects
    
+
+
    
+  
    gold, ar and nm all support plugins now, so everything should be
+  in place for an easy to use LTO build of autotooled projects:
    
+  
      
+    
    • Follow the instructions on how to build libLLVMgold.so.
      • 
+    
    • Install the newly built binutils to $PREFIX
      • 
+    
    • Copy Release/lib/libLLVMgold.so to
+    $PREFIX/libexec/gcc/x86_64-unknown-linux-gnu/4.2.1/ and
+    $PREFIX/lib/bfd-plugins/
      • 
+    
    • Set environment variables ($PREFIX is where you installed llvm-gcc and
+    binutils):
+    
      +export CC="$PREFIX/bin/llvm-gcc -use-gold-plugin"
+export AR="$PREFIX/bin/ar --plugin libLLVMgold.so"
+export NM="$PREFIX/bin/nm --plugin libLLVMgold.so"
+export RANLIB=/bin/true #ranlib is not needed, and doesn't support .bc files in .a
+export CFLAGS="-O4"
+     
      
+     
      • 
+     
    • Configure & build the project as usual: ./configure && make && make check 
      • 
+   
    
+   
     The environment variable settings may work for non-autotooled projects
+   too, but you may need to set the LD environment variable as well.
    
+
    
+
+
 
    Licensing
    
 
 
    




From ofv at wanadoo.es  Wed Jun  3 10:11:25 2009
From: ofv at wanadoo.es (Oscar Fuentes)
Date: Wed, 03 Jun 2009 15:11:25 -0000
Subject: [llvm-commits] [llvm] r72774 - in /llvm/trunk: CMakeLists.txt
 docs/CMake.html tools/llvm-config/CMakeLists.txt
Message-ID: <200906031511.n53FBPLA014452@zion.cs.uiuc.edu>

Author: ofv
Date: Wed Jun  3 10:11:25 2009
New Revision: 72774

URL: http://llvm.org/viewvc/llvm-project?rev=72774&view=rev
Log:
CMake: Implements and documents option LLVM_ENABLE_ASSERTS.

Modified:
    llvm/trunk/CMakeLists.txt
    llvm/trunk/docs/CMake.html
    llvm/trunk/tools/llvm-config/CMakeLists.txt

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=72774&r1=72773&r2=72774&view=diff

==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Wed Jun  3 10:11:25 2009
@@ -17,6 +17,8 @@
 Please delete them.")
 endif()
 
+string(TOUPPER "${CMAKE_BUILD_TYPE}" uppercase_CMAKE_BUILD_TYPE)
+
 include(FindPerl)
 
 set(LLVM_MAIN_SRC_DIR ${CMAKE_CURRENT_SOURCE_DIR})
@@ -55,6 +57,16 @@
 
 option(LLVM_ENABLE_THREADS "Use threads if available." ON)
 
+if( uppercase_CMAKE_BUILD_TYPE STREQUAL "RELEASE" )
+  option(LLVM_ENABLE_ASSERTS "Enable asserts" OFF)
+else()
+  option(LLVM_ENABLE_ASSERTS "Enable asserts" ON)
+endif()
+
+if( LLVM_ENABLE_ASSERTS )
+  add_definitions( -D_DEBUG -UNDEBUG )
+endif()
+
 if( LLVM_TARGETS_TO_BUILD STREQUAL "all" )
   set( LLVM_TARGETS_TO_BUILD ${LLVM_ALL_TARGETS} )
 endif()

Modified: llvm/trunk/docs/CMake.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CMake.html?rev=72774&r1=72773&r2=72774&view=diff

==============================================================================
--- llvm/trunk/docs/CMake.html (original)
+++ llvm/trunk/docs/CMake.html Wed Jun  3 10:11:25 2009
@@ -248,6 +248,10 @@
   
    LLVM_ENABLE_THREADS:BOOL
    
   
    Build with threads support, if available. Defaults to ON.
    
 
+  
    LLVM_ENABLE_ASSERTS:BOOL
    
+  
    Enables code asserts. Defaults to ON if and only if
+    CMAKE_BUILD_TYPE is Release.
    
+
   
    LLVM_ENABLE_PIC:BOOL
    
   
    Add the -fPIC flag to the compiler command-line, if the
     compiler supports this flag. Some systems, like Windows, does not

Modified: llvm/trunk/tools/llvm-config/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-config/CMakeLists.txt?rev=72774&r1=72773&r2=72774&view=diff

==============================================================================
--- llvm/trunk/tools/llvm-config/CMakeLists.txt (original)
+++ llvm/trunk/tools/llvm-config/CMakeLists.txt Wed Jun  3 10:11:25 2009
@@ -87,7 +87,6 @@
   DEPENDS ${LIBDEPS}
   COMMENT "Checking for cyclic dependencies between LLVM libraries.")
 
-string(TOUPPER "${CMAKE_BUILD_TYPE}" uppercase_CMAKE_BUILD_TYPE)
 set(C_FLGS "${CMAKE_C_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${LLVM_DEFINITIONS}")
 set(CXX_FLGS "${CMAKE_CXX_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${LLVM_DEFINITIONS}")
 set(CPP_FLGS "${CMAKE_CPP_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${LLVM_DEFINITIONS}")




From ofv at wanadoo.es  Wed Jun  3 10:29:09 2009
From: ofv at wanadoo.es (Oscar Fuentes)
Date: Wed, 03 Jun 2009 15:29:09 -0000
Subject: [llvm-commits] [llvm] r72775 -
	/llvm/trunk/lib/CodeGen/CMakeLists.txt
Message-ID: <200906031529.n53FT96c014978@zion.cs.uiuc.edu>

Author: ofv
Date: Wed Jun  3 10:29:09 2009
New Revision: 72775

URL: http://llvm.org/viewvc/llvm-project?rev=72775&view=rev
Log:
CMake: Added missing source file to lib/CodeGen/CMakeLists.txt.

Modified:
    llvm/trunk/lib/CodeGen/CMakeLists.txt

Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=72775&r1=72774&r2=72775&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/CMakeLists.txt (original)
+++ llvm/trunk/lib/CodeGen/CMakeLists.txt Wed Jun  3 10:29:09 2009
@@ -16,6 +16,7 @@
   LiveStackAnalysis.cpp
   LiveVariables.cpp
   LowerSubregs.cpp
+  MachOCodeEmitter.cpp
   MachOWriter.cpp
   MachineBasicBlock.cpp
   MachineDominators.cpp




From sanjiv.gupta at microchip.com  Wed Jun  3 10:31:12 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Wed, 03 Jun 2009 15:31:12 -0000
Subject: [llvm-commits] [llvm] r72776 - in /llvm/trunk/lib/Target/PIC16:
 PIC16ISelLowering.cpp PIC16InstrInfo.cpp PIC16InstrInfo.h PIC16InstrInfo.td
Message-ID: <200906031531.n53FVDAn015084@zion.cs.uiuc.edu>

Author: sgupta
Date: Wed Jun  3 10:31:12 2009
New Revision: 72776

URL: http://llvm.org/viewvc/llvm-project?rev=72776&view=rev
Log:
FrameIndex could be used as a value (addressof (arg)) or as an address.
Expand it exactly like GlobalAddress.
Fix some more crashes (InsertBranch() not being implemented) for compiling hitec libs.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
    llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp
    llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h
    llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=72776&r1=72775&r2=72776&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Wed Jun  3 10:31:12 2009
@@ -359,11 +359,23 @@
   // Expand FrameIndex like GlobalAddress and ExternalSymbol
   // Also use Offset field for lo and hi parts. The default 
   // offset is zero.
+
+  /*
   SDValue Offset = DAG.getConstant(0, MVT::i8);
   SDValue FI = DAG.getTargetFrameIndex(Index, MVT::i8);
   SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, FI, Offset);
   SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, FI, Offset);
   return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
+  */
+
+  SDValue ES;
+  int FrameOffset;
+  SDValue FI = SDValue(N,0);
+  LegalizeFrameIndex(FI, DAG, ES, FrameOffset);
+  SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8);
+  SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset);
+  SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset);
+  return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
 }
 
 
@@ -626,12 +638,22 @@
   // Expansion of FrameIndex has Lo/Hi parts
   if (isDirectAddress(Ptr)) { 
       SDValue TFI = Ptr.getOperand(0).getOperand(0); 
+      int FrameOffset;
       if (TFI.getOpcode() == ISD::TargetFrameIndex) {
-        int FrameOffset;
         LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset);
         Hi = DAG.getConstant(1, MVT::i8);
         Offset += FrameOffset; 
         return;
+      } else if (TFI.getOpcode() == ISD::TargetExternalSymbol) {
+        // FrameIndex has already been expanded.
+        // Now just make use of its expansion
+        Lo = TFI;
+        Hi = DAG.getConstant(1, MVT::i8);
+        SDValue FOffset = Ptr.getOperand(0).getOperand(1);
+        assert (FOffset.getOpcode() == ISD::Constant && 
+                          "Invalid operand of PIC16ISD::Lo");
+        Offset += dyn_cast(FOffset)->getZExtValue();
+        return;
       }
   }
 
@@ -721,7 +743,8 @@
       for (iter=MemBytes; iter &Cond) const {
+  // Shouldn't be a fall through.
+  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
+
+  if (FBB == 0) { // One way branch.
+    if (Cond.empty()) {
+      // Unconditional branch?
+      DebugLoc dl = DebugLoc::getUnknownLoc();
+      BuildMI(&MBB, dl, get(PIC16::br_uncond)).addMBB(TBB);
+    }
+    return 1;
+  }
+
+  // FIXME: If the there are some conditions specified then conditional branch
+  // should be generated.   
+  // For the time being no instruction is being generated therefore
+  // returning NULL.
+  return 0;
+}

Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h?rev=72776&r1=72775&r2=72776&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h Wed Jun  3 10:31:12 2009
@@ -64,6 +64,11 @@
                            unsigned &SrcReg, unsigned &DstReg,
                            unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
 
+  virtual 
+  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+                        MachineBasicBlock *FBB,
+                        const SmallVectorImpl &Cond) const; 
+
   };
 } // namespace llvm
 

Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td?rev=72776&r1=72775&r2=72776&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td Wed Jun  3 10:31:12 2009
@@ -189,22 +189,22 @@
 
 // Move a Lo(TGA) to W.
 def movlw_lo_1 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
-                      "movlw LOW(${src}) + ${src2}",
+                      "movlw LOW(${src} + ${src2})",
                       [(set GPR:$dst, (PIC16Lo tglobaladdr:$src, imm:$src2 ))]>;
 
 // Move a Lo(TES) to W.
 def movlw_lo_2 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
-                      "movlw LOW(${src}) + ${src2}",
+                      "movlw LOW(${src} + ${src2})",
                       [(set GPR:$dst, (PIC16Lo texternalsym:$src, imm:$src2 ))]>;
 
 // Move a Hi(TGA) to W.
 def movlw_hi_1 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
-                      "movlw HIGH(${src}) + ${src2}",
+                      "movlw HIGH(${src} + ${src2})",
                       [(set GPR:$dst, (PIC16Hi tglobaladdr:$src, imm:$src2))]>;
 
 // Move a Hi(TES) to W.
 def movlw_hi_2 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
-                      "movlw HIGH(${src}) + ${src2}",
+                      "movlw HIGH(${src} + ${src2})",
                       [(set GPR:$dst, (PIC16Hi texternalsym:$src, imm:$src2))]>;
 }
 




From edwintorok at gmail.com  Wed Jun  3 10:42:26 2009
From: edwintorok at gmail.com (Torok Edwin)
Date: Wed, 03 Jun 2009 15:42:26 -0000
Subject: [llvm-commits] [llvm] r72778 - /llvm/trunk/docs/GoldPlugin.html
Message-ID: <200906031542.n53FgQaZ015452@zion.cs.uiuc.edu>

Author: edwin
Date: Wed Jun  3 10:42:26 2009
New Revision: 72778

URL: http://llvm.org/viewvc/llvm-project?rev=72778&view=rev
Log:
lets not forget about c++!

Modified:
    llvm/trunk/docs/GoldPlugin.html

Modified: llvm/trunk/docs/GoldPlugin.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GoldPlugin.html?rev=72778&r1=72777&r2=72778&view=diff

==============================================================================
--- llvm/trunk/docs/GoldPlugin.html (original)
+++ llvm/trunk/docs/GoldPlugin.html Wed Jun  3 10:42:26 2009
@@ -152,6 +152,7 @@
     binutils):
     
     export CC="$PREFIX/bin/llvm-gcc -use-gold-plugin"
+export CXX="$PREFIX/bin/llvm-g++ -use-gold-plugin"
 export AR="$PREFIX/bin/ar --plugin libLLVMgold.so"
 export NM="$PREFIX/bin/nm --plugin libLLVMgold.so"
 export RANLIB=/bin/true #ranlib is not needed, and doesn't support .bc files in .a




From espindola at google.com  Wed Jun  3 11:11:12 2009
From: espindola at google.com (Rafael Espindola)
Date: Wed, 3 Jun 2009 17:11:12 +0100
Subject: [llvm-commits] [llvm] r72773 - /llvm/trunk/docs/GoldPlugin.html
In-Reply-To: <200906031506.n53F6JOs014297@zion.cs.uiuc.edu>
References: <200906031506.n53F6JOs014297@zion.cs.uiuc.edu>
Message-ID: <38a0d8450906030911u6ece8f37jef8f887ef719c2c0@mail.gmail.com>

> +export AR="$PREFIX/bin/ar --plugin libLLVMgold.so"
> +export NM="$PREFIX/bin/nm --plugin libLLVMgold.so"

With the plugin copied to .../bfd-plugins/ both ar and nm should work
without the --plugin option.

Cheers,
-- 
Rafael Avila de Espindola

Google | Gordon House | Barrow Street | Dublin 4 | Ireland
Registered in Dublin, Ireland | Registration Number: 368047


From edwintorok at gmail.com  Wed Jun  3 11:20:53 2009
From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=)
Date: Wed, 03 Jun 2009 19:20:53 +0300
Subject: [llvm-commits] [llvm] r72773 - /llvm/trunk/docs/GoldPlugin.html
In-Reply-To: <38a0d8450906030911u6ece8f37jef8f887ef719c2c0@mail.gmail.com>
References: <200906031506.n53F6JOs014297@zion.cs.uiuc.edu>
	<38a0d8450906030911u6ece8f37jef8f887ef719c2c0@mail.gmail.com>
Message-ID: <4A26A2E5.4@gmail.com>

On 2009-06-03 19:11, Rafael Espindola wrote:
>> +export AR="$PREFIX/bin/ar --plugin libLLVMgold.so"
>> +export NM="$PREFIX/bin/nm --plugin libLLVMgold.so"
>>     
>
> With the plugin copied to .../bfd-plugins/ both ar and nm should work
> without the --plugin option.
>   

It doesn't work for me, maybe I am missing something.

This works:
$ /home/edwin/llvm-svn/install/bin/nm --plugin libLLVMgold.so
/home/edwin/clam/git/builds/lto/libclamav/lzma/.libs/liblzma.a

LzmaStateDecode.o:
00000000 T LzmaDecode
00000000 T LzmaDecodeProperties

But without --plugin it doesn't:
$ /home/edwin/llvm-svn/install/bin/nm
/home/edwin/clam/git/builds/lto/libclamav/lzma/.libs/liblzma.a
/home/edwin/llvm-svn/install/bin/nm: LzmaStateDecode.o: File format not
recognized

Best regards,
--Edwin



From sanjiv.gupta at microchip.com  Wed Jun  3 11:27:49 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Wed, 03 Jun 2009 16:27:49 -0000
Subject: [llvm-commits] [llvm] r72781 - in /llvm/trunk/lib/Target/PIC16:
 PIC16AsmPrinter.cpp PIC16DebugInfo.cpp PIC16DebugInfo.h
Message-ID: <200906031627.n53GRoiK017249@zion.cs.uiuc.edu>

Author: sgupta
Date: Wed Jun  3 11:27:49 2009
New Revision: 72781

URL: http://llvm.org/viewvc/llvm-project?rev=72781&view=rev
Log:
Emit file directives correctly in case of a .bc is generated by llvm-ld after linking in several .bc files.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
    llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.cpp
    llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.h

Modified: llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp?rev=72781&r1=72780&r2=72781&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16AsmPrinter.cpp Wed Jun  3 11:27:49 2009
@@ -47,6 +47,7 @@
   const Function *F = MF.getFunction();
   CurrentFnName = Mang->getValueName(F);
 
+  DbgInfo.EmitFileDirective(F);
   // Emit the function variables.
   EmitFunctionFrame(MF);
 
@@ -181,17 +182,11 @@
 
 bool PIC16AsmPrinter::doInitialization (Module &M) {
   bool Result = AsmPrinter::doInitialization(M);
-  DbgInfo.EmitFileDirective(M);
 
   // FIXME:: This is temporary solution to generate the include file.
   // The processor should be passed to llc as in input and the header file
   // should be generated accordingly.
   O << "\n\t#include P16F1937.INC\n";
-  MachineModuleInfo *MMI = getAnalysisIfAvailable();
-  assert(MMI);
-  DwarfWriter *DW = getAnalysisIfAvailable();
-  assert(DW && "Dwarf Writer is not available");
-  DW->BeginModule(&M, MMI, O, this, TAI);
 
   // Set the section names for all globals.
   for (Module::global_iterator I = M.global_begin(), E = M.global_end();
@@ -199,13 +194,14 @@
     I->setSection(TAI->SectionForGlobal(I)->getName());
   }
 
+  DbgInfo.EmitFileDirective(M);
   EmitFunctionDecls(M);
   EmitUndefinedVars(M);
   EmitDefinedVars(M);
   EmitIData(M);
   EmitUData(M);
   EmitRomData(M);
-  DbgInfo.PopulateFunctsDI(M); 
+  DbgInfo.PopulateFunctsDI(M);
   return Result;
 }
 
@@ -285,7 +281,7 @@
 bool PIC16AsmPrinter::doFinalization(Module &M) {
   printLibcallDecls();
   DbgInfo.EmitVarDebugInfo(M);
-  O << "\n\t" << ".EOF";
+  DbgInfo.EmitEOF();
   O << "\n\t" << "END\n";
   bool Result = AsmPrinter::doFinalization(M);
   return Result;

Modified: llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.cpp?rev=72781&r1=72780&r2=72781&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.cpp Wed Jun  3 11:27:49 2009
@@ -264,7 +264,29 @@
   if (CU) {
     DICompileUnit DIUnit(CU);
     std::string Dir, FN;
-    O << "\n\t.file\t\"" << DIUnit.getDirectory(Dir) <<"/"
-      << DIUnit.getFilename(FN) << "\"" ;
+    std::string File = DIUnit.getDirectory(Dir) + "/" + DIUnit.getFilename(FN);
+    O << "\n\t.file\t\"" << File << "\"\n" ;
+    CurFile = File;
   }
 }
+
+void PIC16DbgInfo::EmitFileDirective(const Function *F) {
+  std::string FunctName = F->getName();
+  DISubprogram *SP = getFunctDI(FunctName);
+  if (SP) {
+    std::string Dir, FN;
+    DICompileUnit CU = SP->getCompileUnit();
+    std::string File = CU.getDirectory(Dir) + "/" + CU.getFilename(FN);
+    if ( File != CurFile) {
+      EmitEOF();
+      O << "\n\t.file\t\"" << File << "\"\n" ;
+      CurFile = File;
+    }
+  }
+}
+
+void PIC16DbgInfo::EmitEOF() {
+  if (CurFile != "")
+    O << "\n\t.EOF";
+}
+

Modified: llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.h?rev=72781&r1=72780&r2=72781&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.h Wed Jun  3 11:27:49 2009
@@ -94,8 +94,11 @@
     std::map  FunctNameMap;
     raw_ostream &O;
     const TargetAsmInfo *TAI;
+    std::string CurFile;
   public:
-     PIC16DbgInfo(raw_ostream &o, const TargetAsmInfo *T) : O(o), TAI(T) {}
+    PIC16DbgInfo(raw_ostream &o, const TargetAsmInfo *T) : O(o), TAI(T) {
+      CurFile = "";  
+    }
     ~PIC16DbgInfo();
     void PopulateDebugInfo(DIType Ty, unsigned short &TypeNo, bool &HasAux,
                            int Aux[], std::string &TypeName);
@@ -109,6 +112,8 @@
     inline void EmitSymbol(std::string Name, int Class);
     void EmitVarDebugInfo(Module &M);
     void EmitFileDirective(Module &M);
+    void EmitFileDirective(const Function *F);
+    void EmitEOF();
   };
 } // end namespace llvm;
 #endif




From espindola at google.com  Wed Jun  3 11:28:16 2009
From: espindola at google.com (Rafael Espindola)
Date: Wed, 3 Jun 2009 17:28:16 +0100
Subject: [llvm-commits] [llvm] r72773 - /llvm/trunk/docs/GoldPlugin.html
In-Reply-To: <4A26A2E5.4@gmail.com>
References: <200906031506.n53F6JOs014297@zion.cs.uiuc.edu>
	<38a0d8450906030911u6ece8f37jef8f887ef719c2c0@mail.gmail.com>
	<4A26A2E5.4@gmail.com>
Message-ID: <38a0d8450906030928q5e5f8b51le17588675f3bf2cb@mail.gmail.com>

> But without --plugin it doesn't:
> $ /home/edwin/llvm-svn/install/bin/nm
> /home/edwin/clam/git/builds/lto/libclamav/lzma/.libs/liblzma.a
> /home/edwin/llvm-svn/install/bin/nm: LzmaStateDecode.o: File format not
> recognized

That is strange. Can you run in strace and check that it is trying to
open the bfd-plugins directory?

> Best regards,
> --Edwin
>
>

Cheers,
-- 
Rafael Avila de Espindola

Google | Gordon House | Barrow Street | Dublin 4 | Ireland
Registered in Dublin, Ireland | Registration Number: 368047


From edwintorok at gmail.com  Wed Jun  3 11:31:06 2009
From: edwintorok at gmail.com (=?UTF-8?B?VMO2csO2ayBFZHdpbg==?=)
Date: Wed, 03 Jun 2009 19:31:06 +0300
Subject: [llvm-commits] [llvm] r72773 - /llvm/trunk/docs/GoldPlugin.html
In-Reply-To: <38a0d8450906030928q5e5f8b51le17588675f3bf2cb@mail.gmail.com>
References: <200906031506.n53F6JOs014297@zion.cs.uiuc.edu>	
	<38a0d8450906030911u6ece8f37jef8f887ef719c2c0@mail.gmail.com>	
	<4A26A2E5.4@gmail.com>
	<38a0d8450906030928q5e5f8b51le17588675f3bf2cb@mail.gmail.com>
Message-ID: <4A26A54A.3070201@gmail.com>

On 2009-06-03 19:28, Rafael Espindola wrote:
>> But without --plugin it doesn't:
>> $ /home/edwin/llvm-svn/install/bin/nm
>> /home/edwin/clam/git/builds/lto/libclamav/lzma/.libs/liblzma.a
>> /home/edwin/llvm-svn/install/bin/nm: LzmaStateDecode.o: File format not
>> recognized
>>     
>
> That is strange. Can you run in strace and check that it is trying to
> open the bfd-plugins directory?
>   

It does, but it doesn't seem to load anything from there.

I attached the strace output and liblzma.a.

To reproduce my failure try running:
/bin/nm liblzma.a

vs.

/bin/nm liblzma.a --plugin libLLVMgold.so

Best regards,
--Edwin
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From daniel at zuster.org  Wed Jun  3 11:35:31 2009
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 3 Jun 2009 09:35:31 -0700
Subject: [llvm-commits] [llvm] r72776 - in /llvm/trunk/lib/Target/PIC16:
	PIC16ISelLowering.cpp PIC16InstrInfo.cpp PIC16InstrInfo.h
	PIC16InstrInfo.td
In-Reply-To: <200906031531.n53FVDAn015084@zion.cs.uiuc.edu>
References: <200906031531.n53FVDAn015084@zion.cs.uiuc.edu>
Message-ID: <6a8523d60906030935y59e7c8f4y16dd07ece66a6a8a@mail.gmail.com>

This introduced a compile warning, here:
  PIC16ISelLowering.cpp:357: warning: unused variable 'Index'

 - Daniel

On Wed, Jun 3, 2009 at 8:31 AM, Sanjiv Gupta  wrote:
> Author: sgupta
> Date: Wed Jun ?3 10:31:12 2009
> New Revision: 72776
>
> URL: http://llvm.org/viewvc/llvm-project?rev=72776&view=rev
> Log:
> FrameIndex could be used as a value (addressof (arg)) or as an address.
> Expand it exactly like GlobalAddress.
> Fix some more crashes (InsertBranch() not being implemented) for compiling hitec libs.
>
> Modified:
> ? ?llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
> ? ?llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp
> ? ?llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h
> ? ?llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=72776&r1=72775&r2=72776&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Wed Jun ?3 10:31:12 2009
> @@ -359,11 +359,23 @@
> ? // Expand FrameIndex like GlobalAddress and ExternalSymbol
> ? // Also use Offset field for lo and hi parts. The default
> ? // offset is zero.
> +
> + ?/*
> ? SDValue Offset = DAG.getConstant(0, MVT::i8);
> ? SDValue FI = DAG.getTargetFrameIndex(Index, MVT::i8);
> ? SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, FI, Offset);
> ? SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, FI, Offset);
> ? return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
> + ?*/
> +
> + ?SDValue ES;
> + ?int FrameOffset;
> + ?SDValue FI = SDValue(N,0);
> + ?LegalizeFrameIndex(FI, DAG, ES, FrameOffset);
> + ?SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8);
> + ?SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset);
> + ?SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset);
> + ?return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
> ?}
>
>
> @@ -626,12 +638,22 @@
> ? // Expansion of FrameIndex has Lo/Hi parts
> ? if (isDirectAddress(Ptr)) {
> ? ? ? SDValue TFI = Ptr.getOperand(0).getOperand(0);
> + ? ? ?int FrameOffset;
> ? ? ? if (TFI.getOpcode() == ISD::TargetFrameIndex) {
> - ? ? ? ?int FrameOffset;
> ? ? ? ? LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset);
> ? ? ? ? Hi = DAG.getConstant(1, MVT::i8);
> ? ? ? ? Offset += FrameOffset;
> ? ? ? ? return;
> + ? ? ?} else if (TFI.getOpcode() == ISD::TargetExternalSymbol) {
> + ? ? ? ?// FrameIndex has already been expanded.
> + ? ? ? ?// Now just make use of its expansion
> + ? ? ? ?Lo = TFI;
> + ? ? ? ?Hi = DAG.getConstant(1, MVT::i8);
> + ? ? ? ?SDValue FOffset = Ptr.getOperand(0).getOperand(1);
> + ? ? ? ?assert (FOffset.getOpcode() == ISD::Constant &&
> + ? ? ? ? ? ? ? ? ? ? ? ? ?"Invalid operand of PIC16ISD::Lo");
> + ? ? ? ?Offset += dyn_cast(FOffset)->getZExtValue();
> + ? ? ? ?return;
> ? ? ? }
> ? }
>
> @@ -721,7 +743,8 @@
> ? ? ? for (iter=MemBytes; iter ? ? ? ? PICLoads.push_back(SRA);
> ? ? ? }
> - ? ?} else if (ISD::isZEXTLoad(N)) {
> + ? ?} else if (ISD::isZEXTLoad(N) || ISD::isEXTLoad(N)) {
> + ? ?//} else if (ISD::isZEXTLoad(N)) {
> ? ? ? // ZeroExtendedLoad -- For all ExtdBytes use constant 0
> ? ? ? SDValue ConstZero = DAG.getConstant(0, MVT::i8);
> ? ? ? for (iter=MemBytes; iter
> Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp?rev=72776&r1=72775&r2=72776&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp Wed Jun ?3 10:31:12 2009
> @@ -184,3 +184,31 @@
> ? return false;
> ?}
>
> +/// InsertBranch - Insert a branch into the end of the specified
> +/// MachineBasicBlock. ?This operands to this method are the same as those
> +/// returned by AnalyzeBranch. ?This is invoked in cases where AnalyzeBranch
> +/// returns success and when an unconditional branch (TBB is non-null, FBB is
> +/// null, Cond is empty) needs to be inserted. It returns the number of
> +/// instructions inserted.
> +unsigned PIC16InstrInfo::
> +InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
> + ? ? ? ? ? ? MachineBasicBlock *FBB,
> + ? ? ? ? ? ? const SmallVectorImpl &Cond) const {
> + ?// Shouldn't be a fall through.
> + ?assert(TBB && "InsertBranch must not be told to insert a fallthrough");
> +
> + ?if (FBB == 0) { // One way branch.
> + ? ?if (Cond.empty()) {
> + ? ? ?// Unconditional branch?
> + ? ? ?DebugLoc dl = DebugLoc::getUnknownLoc();
> + ? ? ?BuildMI(&MBB, dl, get(PIC16::br_uncond)).addMBB(TBB);
> + ? ?}
> + ? ?return 1;
> + ?}
> +
> + ?// FIXME: If the there are some conditions specified then conditional branch
> + ?// should be generated.
> + ?// For the time being no instruction is being generated therefore
> + ?// returning NULL.
> + ?return 0;
> +}
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h?rev=72776&r1=72775&r2=72776&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h Wed Jun ?3 10:31:12 2009
> @@ -64,6 +64,11 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned &SrcReg, unsigned &DstReg,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
>
> + ?virtual
> + ?unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
> + ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *FBB,
> + ? ? ? ? ? ? ? ? ? ? ? ?const SmallVectorImpl &Cond) const;
> +
> ? };
> ?} // namespace llvm
>
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td?rev=72776&r1=72775&r2=72776&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.td Wed Jun ?3 10:31:12 2009
> @@ -189,22 +189,22 @@
>
> ?// Move a Lo(TGA) to W.
> ?def movlw_lo_1 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
> - ? ? ? ? ? ? ? ? ? ? ?"movlw LOW(${src}) + ${src2}",
> + ? ? ? ? ? ? ? ? ? ? ?"movlw LOW(${src} + ${src2})",
> ? ? ? ? ? ? ? ? ? ? ? [(set GPR:$dst, (PIC16Lo tglobaladdr:$src, imm:$src2 ))]>;
>
> ?// Move a Lo(TES) to W.
> ?def movlw_lo_2 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
> - ? ? ? ? ? ? ? ? ? ? ?"movlw LOW(${src}) + ${src2}",
> + ? ? ? ? ? ? ? ? ? ? ?"movlw LOW(${src} + ${src2})",
> ? ? ? ? ? ? ? ? ? ? ? [(set GPR:$dst, (PIC16Lo texternalsym:$src, imm:$src2 ))]>;
>
> ?// Move a Hi(TGA) to W.
> ?def movlw_hi_1 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
> - ? ? ? ? ? ? ? ? ? ? ?"movlw HIGH(${src}) + ${src2}",
> + ? ? ? ? ? ? ? ? ? ? ?"movlw HIGH(${src} + ${src2})",
> ? ? ? ? ? ? ? ? ? ? ? [(set GPR:$dst, (PIC16Hi tglobaladdr:$src, imm:$src2))]>;
>
> ?// Move a Hi(TES) to W.
> ?def movlw_hi_2 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
> - ? ? ? ? ? ? ? ? ? ? ?"movlw HIGH(${src}) + ${src2}",
> + ? ? ? ? ? ? ? ? ? ? ?"movlw HIGH(${src} + ${src2})",
> ? ? ? ? ? ? ? ? ? ? ? [(set GPR:$dst, (PIC16Hi texternalsym:$src, imm:$src2))]>;
> ?}
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



From gohman at apple.com  Wed Jun  3 11:47:12 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 03 Jun 2009 16:47:12 -0000
Subject: [llvm-commits] [llvm] r72782 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <200906031647.n53GlCrT017858@zion.cs.uiuc.edu>

Author: djg
Date: Wed Jun  3 11:47:12 2009
New Revision: 72782

URL: http://llvm.org/viewvc/llvm-project?rev=72782&view=rev
Log:
Remove unnecessary #includes.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=72782&r1=72781&r2=72782&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jun  3 11:47:12 2009
@@ -15,7 +15,6 @@
 #include "X86.h"
 #include "X86InstrBuilder.h"
 #include "X86ISelLowering.h"
-#include "X86MachineFunctionInfo.h"
 #include "X86TargetMachine.h"
 #include "llvm/CallingConv.h"
 #include "llvm/Constants.h"
@@ -25,14 +24,12 @@
 #include "llvm/Intrinsics.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/VectorExtras.h"
-#include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/PseudoSourceValue.h"
-#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Target/TargetOptions.h"




From bruno.cardoso at gmail.com  Wed Jun  3 11:55:02 2009
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 03 Jun 2009 16:55:02 -0000
Subject: [llvm-commits] [llvm] r72783 - in /llvm/trunk:
 include/llvm/CodeGen/JITCodeEmitter.h
 include/llvm/CodeGen/MachineCodeEmitter.h
 include/llvm/ExecutionEngine/JITMemoryManager.h
 lib/ExecutionEngine/JIT/JITEmitter.cpp
 lib/ExecutionEngine/JIT/JITMemoryManager.cpp
Message-ID: <200906031655.n53Gt21D018154@zion.cs.uiuc.edu>

Author: bruno
Date: Wed Jun  3 11:55:02 2009
New Revision: 72783

URL: http://llvm.org/viewvc/llvm-project?rev=72783&view=rev
Log:
Revert 72650

Modified:
    llvm/trunk/include/llvm/CodeGen/JITCodeEmitter.h
    llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h
    llvm/trunk/include/llvm/ExecutionEngine/JITMemoryManager.h
    llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp
    llvm/trunk/lib/ExecutionEngine/JIT/JITMemoryManager.cpp

Modified: llvm/trunk/include/llvm/CodeGen/JITCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/JITCodeEmitter.h?rev=72783&r1=72782&r2=72783&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/JITCodeEmitter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/JITCodeEmitter.h Wed Jun  3 11:55:02 2009
@@ -89,7 +89,7 @@
   /// emitByte - This callback is invoked when a byte needs to be written to the
   /// output stream.
   ///
-  void emitByte(uint8_t B) {
+  void emitByte(unsigned char B) {
     if (CurBufferPtr != BufferEnd)
       *CurBufferPtr++ = B;
   }
@@ -99,10 +99,10 @@
   ///
   void emitWordLE(unsigned W) {
     if (4 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (uint8_t)(W >>  0);
-      *CurBufferPtr++ = (uint8_t)(W >>  8);
-      *CurBufferPtr++ = (uint8_t)(W >> 16);
-      *CurBufferPtr++ = (uint8_t)(W >> 24);
+      *CurBufferPtr++ = (unsigned char)(W >>  0);
+      *CurBufferPtr++ = (unsigned char)(W >>  8);
+      *CurBufferPtr++ = (unsigned char)(W >> 16);
+      *CurBufferPtr++ = (unsigned char)(W >> 24);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -113,10 +113,10 @@
   ///
   void emitWordBE(unsigned W) {
     if (4 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (uint8_t)(W >> 24);
-      *CurBufferPtr++ = (uint8_t)(W >> 16);
-      *CurBufferPtr++ = (uint8_t)(W >>  8);
-      *CurBufferPtr++ = (uint8_t)(W >>  0);
+      *CurBufferPtr++ = (unsigned char)(W >> 24);
+      *CurBufferPtr++ = (unsigned char)(W >> 16);
+      *CurBufferPtr++ = (unsigned char)(W >>  8);
+      *CurBufferPtr++ = (unsigned char)(W >>  0);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -127,14 +127,14 @@
   ///
   void emitDWordLE(uint64_t W) {
     if (8 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (uint8_t)(W >>  0);
-      *CurBufferPtr++ = (uint8_t)(W >>  8);
-      *CurBufferPtr++ = (uint8_t)(W >> 16);
-      *CurBufferPtr++ = (uint8_t)(W >> 24);
-      *CurBufferPtr++ = (uint8_t)(W >> 32);
-      *CurBufferPtr++ = (uint8_t)(W >> 40);
-      *CurBufferPtr++ = (uint8_t)(W >> 48);
-      *CurBufferPtr++ = (uint8_t)(W >> 56);
+      *CurBufferPtr++ = (unsigned char)(W >>  0);
+      *CurBufferPtr++ = (unsigned char)(W >>  8);
+      *CurBufferPtr++ = (unsigned char)(W >> 16);
+      *CurBufferPtr++ = (unsigned char)(W >> 24);
+      *CurBufferPtr++ = (unsigned char)(W >> 32);
+      *CurBufferPtr++ = (unsigned char)(W >> 40);
+      *CurBufferPtr++ = (unsigned char)(W >> 48);
+      *CurBufferPtr++ = (unsigned char)(W >> 56);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -145,14 +145,14 @@
   ///
   void emitDWordBE(uint64_t W) {
     if (8 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (uint8_t)(W >> 56);
-      *CurBufferPtr++ = (uint8_t)(W >> 48);
-      *CurBufferPtr++ = (uint8_t)(W >> 40);
-      *CurBufferPtr++ = (uint8_t)(W >> 32);
-      *CurBufferPtr++ = (uint8_t)(W >> 24);
-      *CurBufferPtr++ = (uint8_t)(W >> 16);
-      *CurBufferPtr++ = (uint8_t)(W >>  8);
-      *CurBufferPtr++ = (uint8_t)(W >>  0);
+      *CurBufferPtr++ = (unsigned char)(W >> 56);
+      *CurBufferPtr++ = (unsigned char)(W >> 48);
+      *CurBufferPtr++ = (unsigned char)(W >> 40);
+      *CurBufferPtr++ = (unsigned char)(W >> 32);
+      *CurBufferPtr++ = (unsigned char)(W >> 24);
+      *CurBufferPtr++ = (unsigned char)(W >> 16);
+      *CurBufferPtr++ = (unsigned char)(W >>  8);
+      *CurBufferPtr++ = (unsigned char)(W >>  0);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -166,8 +166,8 @@
     if(Alignment <= (uintptr_t)(BufferEnd-CurBufferPtr)) {
       // Move the current buffer ptr up to the specified alignment.
       CurBufferPtr =
-        (uint8_t*)(((uintptr_t)CurBufferPtr+Alignment-1) &
-                   ~(uintptr_t)(Alignment-1));
+        (unsigned char*)(((uintptr_t)CurBufferPtr+Alignment-1) &
+                         ~(uintptr_t)(Alignment-1));
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -178,7 +178,7 @@
   /// written to the output stream.
   void emitULEB128Bytes(unsigned Value) {
     do {
-      uint8_t Byte = Value & 0x7f;
+      unsigned char Byte = Value & 0x7f;
       Value >>= 7;
       if (Value) Byte |= 0x80;
       emitByte(Byte);
@@ -187,12 +187,12 @@
   
   /// emitSLEB128Bytes - This callback is invoked when a SLEB128 needs to be
   /// written to the output stream.
-  void emitSLEB128Bytes(int32_t Value) {
-    int32_t Sign = Value >> (8 * sizeof(Value) - 1);
+  void emitSLEB128Bytes(int Value) {
+    int Sign = Value >> (8 * sizeof(Value) - 1);
     bool IsMore;
   
     do {
-      uint8_t Byte = Value & 0x7f;
+      unsigned char Byte = Value & 0x7f;
       Value >>= 7;
       IsMore = Value != Sign || ((Byte ^ Sign) & 0x40) != 0;
       if (IsMore) Byte |= 0x80;
@@ -205,14 +205,14 @@
   void emitString(const std::string &String) {
     for (unsigned i = 0, N = static_cast(String.size());
          i < N; ++i) {
-      uint8_t C = String[i];
+      unsigned char C = String[i];
       emitByte(C);
     }
     emitByte(0);
   }
   
   /// emitInt32 - Emit a int32 directive.
-  void emitInt32(int32_t Value) {
+  void emitInt32(int Value) {
     if (4 <= BufferEnd-CurBufferPtr) {
       *((uint32_t*)CurBufferPtr) = Value;
       CurBufferPtr += 4;

Modified: llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h?rev=72783&r1=72782&r2=72783&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h Wed Jun  3 11:55:02 2009
@@ -50,14 +50,14 @@
 protected:
   /// BufferBegin/BufferEnd - Pointers to the start and end of the memory
   /// allocated for this code buffer.
-  uint8_t *BufferBegin, *BufferEnd;
+  unsigned char *BufferBegin, *BufferEnd;
   
   /// CurBufferPtr - Pointer to the next byte of memory to fill when emitting 
   /// code.  This is guranteed to be in the range [BufferBegin,BufferEnd].  If
   /// this pointer is at BufferEnd, it will never move due to code emission, and
   /// all code emission requests will be ignored (this is the buffer overflow
   /// condition).
-  uint8_t *CurBufferPtr;
+  unsigned char *CurBufferPtr;
 
 public:
   virtual ~MachineCodeEmitter() {}
@@ -96,7 +96,7 @@
   /// emitByte - This callback is invoked when a byte needs to be written to the
   /// output stream.
   ///
-  void emitByte(uint8_t B) {
+  void emitByte(unsigned char B) {
     if (CurBufferPtr != BufferEnd)
       *CurBufferPtr++ = B;
   }
@@ -106,10 +106,10 @@
   ///
   void emitWordLE(unsigned W) {
     if (4 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (uint8_t)(W >>  0);
-      *CurBufferPtr++ = (uint8_t)(W >>  8);
-      *CurBufferPtr++ = (uint8_t)(W >> 16);
-      *CurBufferPtr++ = (uint8_t)(W >> 24);
+      *CurBufferPtr++ = (unsigned char)(W >>  0);
+      *CurBufferPtr++ = (unsigned char)(W >>  8);
+      *CurBufferPtr++ = (unsigned char)(W >> 16);
+      *CurBufferPtr++ = (unsigned char)(W >> 24);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -120,10 +120,10 @@
   ///
   void emitWordBE(unsigned W) {
     if (4 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (uint8_t)(W >> 24);
-      *CurBufferPtr++ = (uint8_t)(W >> 16);
-      *CurBufferPtr++ = (uint8_t)(W >>  8);
-      *CurBufferPtr++ = (uint8_t)(W >>  0);
+      *CurBufferPtr++ = (unsigned char)(W >> 24);
+      *CurBufferPtr++ = (unsigned char)(W >> 16);
+      *CurBufferPtr++ = (unsigned char)(W >>  8);
+      *CurBufferPtr++ = (unsigned char)(W >>  0);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -134,14 +134,14 @@
   ///
   void emitDWordLE(uint64_t W) {
     if (8 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (uint8_t)(W >>  0);
-      *CurBufferPtr++ = (uint8_t)(W >>  8);
-      *CurBufferPtr++ = (uint8_t)(W >> 16);
-      *CurBufferPtr++ = (uint8_t)(W >> 24);
-      *CurBufferPtr++ = (uint8_t)(W >> 32);
-      *CurBufferPtr++ = (uint8_t)(W >> 40);
-      *CurBufferPtr++ = (uint8_t)(W >> 48);
-      *CurBufferPtr++ = (uint8_t)(W >> 56);
+      *CurBufferPtr++ = (unsigned char)(W >>  0);
+      *CurBufferPtr++ = (unsigned char)(W >>  8);
+      *CurBufferPtr++ = (unsigned char)(W >> 16);
+      *CurBufferPtr++ = (unsigned char)(W >> 24);
+      *CurBufferPtr++ = (unsigned char)(W >> 32);
+      *CurBufferPtr++ = (unsigned char)(W >> 40);
+      *CurBufferPtr++ = (unsigned char)(W >> 48);
+      *CurBufferPtr++ = (unsigned char)(W >> 56);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -152,14 +152,14 @@
   ///
   void emitDWordBE(uint64_t W) {
     if (8 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (uint8_t)(W >> 56);
-      *CurBufferPtr++ = (uint8_t)(W >> 48);
-      *CurBufferPtr++ = (uint8_t)(W >> 40);
-      *CurBufferPtr++ = (uint8_t)(W >> 32);
-      *CurBufferPtr++ = (uint8_t)(W >> 24);
-      *CurBufferPtr++ = (uint8_t)(W >> 16);
-      *CurBufferPtr++ = (uint8_t)(W >>  8);
-      *CurBufferPtr++ = (uint8_t)(W >>  0);
+      *CurBufferPtr++ = (unsigned char)(W >> 56);
+      *CurBufferPtr++ = (unsigned char)(W >> 48);
+      *CurBufferPtr++ = (unsigned char)(W >> 40);
+      *CurBufferPtr++ = (unsigned char)(W >> 32);
+      *CurBufferPtr++ = (unsigned char)(W >> 24);
+      *CurBufferPtr++ = (unsigned char)(W >> 16);
+      *CurBufferPtr++ = (unsigned char)(W >>  8);
+      *CurBufferPtr++ = (unsigned char)(W >>  0);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -173,8 +173,8 @@
     if(Alignment <= (uintptr_t)(BufferEnd-CurBufferPtr)) {
       // Move the current buffer ptr up to the specified alignment.
       CurBufferPtr =
-        (uint8_t*)(((uintptr_t)CurBufferPtr+Alignment-1) &
-                   ~(uintptr_t)(Alignment-1));
+        (unsigned char*)(((uintptr_t)CurBufferPtr+Alignment-1) &
+                         ~(uintptr_t)(Alignment-1));
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -185,7 +185,7 @@
   /// written to the output stream.
   void emitULEB128Bytes(unsigned Value) {
     do {
-      uint8_t Byte = Value & 0x7f;
+      unsigned char Byte = Value & 0x7f;
       Value >>= 7;
       if (Value) Byte |= 0x80;
       emitByte(Byte);
@@ -194,12 +194,12 @@
   
   /// emitSLEB128Bytes - This callback is invoked when a SLEB128 needs to be
   /// written to the output stream.
-  void emitSLEB128Bytes(int32_t Value) {
-    int32_t Sign = Value >> (8 * sizeof(Value) - 1);
+  void emitSLEB128Bytes(int Value) {
+    int Sign = Value >> (8 * sizeof(Value) - 1);
     bool IsMore;
   
     do {
-      uint8_t Byte = Value & 0x7f;
+      unsigned char Byte = Value & 0x7f;
       Value >>= 7;
       IsMore = Value != Sign || ((Byte ^ Sign) & 0x40) != 0;
       if (IsMore) Byte |= 0x80;
@@ -212,14 +212,14 @@
   void emitString(const std::string &String) {
     for (unsigned i = 0, N = static_cast(String.size());
          i < N; ++i) {
-      uint8_t C = String[i];
+      unsigned char C = String[i];
       emitByte(C);
     }
     emitByte(0);
   }
   
   /// emitInt32 - Emit a int32 directive.
-  void emitInt32(int32_t Value) {
+  void emitInt32(int Value) {
     if (4 <= BufferEnd-CurBufferPtr) {
       *((uint32_t*)CurBufferPtr) = Value;
       CurBufferPtr += 4;

Modified: llvm/trunk/include/llvm/ExecutionEngine/JITMemoryManager.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/JITMemoryManager.h?rev=72783&r1=72782&r2=72783&view=diff

==============================================================================
--- llvm/trunk/include/llvm/ExecutionEngine/JITMemoryManager.h (original)
+++ llvm/trunk/include/llvm/ExecutionEngine/JITMemoryManager.h Wed Jun  3 11:55:02 2009
@@ -60,7 +60,7 @@
   
   /// getGOTBase - If this is managing a Global Offset Table, this method should
   /// return a pointer to its base.
-  virtual uint8_t *getGOTBase() const = 0;
+  virtual unsigned char *getGOTBase() const = 0;
   
   /// SetDlsymTable - If the JIT must be able to relocate stubs after they have
   /// been emitted, potentially because they are being copied to a process
@@ -89,8 +89,8 @@
   /// emit the function, so it doesn't pass in the size.  Instead, this method
   /// is required to pass back a "valid size".  The JIT will be careful to not
   /// write more than the returned ActualSize bytes of memory. 
-  virtual uint8_t *startFunctionBody(const Function *F, 
-                                     uintptr_t &ActualSize) = 0;
+  virtual unsigned char *startFunctionBody(const Function *F, 
+                                           uintptr_t &ActualSize) = 0;
   
   /// allocateStub - This method is called by the JIT to allocate space for a
   /// function stub (used to handle limited branch displacements) while it is
@@ -100,8 +100,9 @@
   /// thunk for it.  The stub should be "close" to the current function body,
   /// but should not be included in the 'actualsize' returned by
   /// startFunctionBody.
-  virtual uint8_t *allocateStub(const GlobalValue* F, unsigned StubSize,
-                                unsigned Alignment) = 0;
+  virtual unsigned char *allocateStub(const GlobalValue* F, unsigned StubSize,
+                                      unsigned Alignment) =0;
+  
   
   /// endFunctionBody - This method is called when the JIT is done codegen'ing
   /// the specified function.  At this point we know the size of the JIT
@@ -109,11 +110,11 @@
   /// the startFunctionBody method) and FunctionEnd which is a pointer to the 
   /// actual end of the function.  This method should mark the space allocated
   /// and remember where it is in case the client wants to deallocate it.
-  virtual void endFunctionBody(const Function *F, uint8_t *FunctionStart,
-                               uint8_t *FunctionEnd) = 0;
+  virtual void endFunctionBody(const Function *F, unsigned char *FunctionStart,
+                               unsigned char *FunctionEnd) = 0;
 
   /// allocateSpace - Allocate a memory block of the given size.
-  virtual uint8_t *allocateSpace(intptr_t Size, unsigned Alignment) = 0;
+  virtual unsigned char *allocateSpace(intptr_t Size, unsigned Alignment) = 0;
   
   /// deallocateMemForFunction - Free JIT memory for the specified function.
   /// This is never called when the JIT is currently emitting a function.
@@ -121,13 +122,14 @@
   
   /// startExceptionTable - When we finished JITing the function, if exception
   /// handling is set, we emit the exception table.
-  virtual uint8_t* startExceptionTable(const Function* F,
-                                       uintptr_t &ActualSize) = 0;
+  virtual unsigned char* startExceptionTable(const Function* F,
+                                             uintptr_t &ActualSize) = 0;
   
   /// endExceptionTable - This method is called when the JIT is done emitting
   /// the exception table.
-  virtual void endExceptionTable(const Function *F, uint8_t *TableStart,
-                                 uint8_t *TableEnd, uint8_t* FrameRegister) = 0;
+  virtual void endExceptionTable(const Function *F, unsigned char *TableStart,
+                                 unsigned char *TableEnd, 
+                                 unsigned char* FrameRegister) = 0;
 };
 
 } // end namespace llvm.

Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp?rev=72783&r1=72782&r2=72783&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Wed Jun  3 11:55:02 2009
@@ -551,7 +551,7 @@
 
     // When outputting a function stub in the context of some other function, we
     // save BufferBegin/BufferEnd/CurBufferPtr here.
-    uint8_t *SavedBufferBegin, *SavedBufferEnd, *SavedCurBufferPtr;
+    unsigned char *SavedBufferBegin, *SavedBufferEnd, *SavedCurBufferPtr;
 
     /// Relocations - These are the relocations that the function needs, as
     /// emitted.
@@ -1056,11 +1056,11 @@
   
   // FnStart is the start of the text, not the start of the constant pool and
   // other per-function data.
-  uint8_t *FnStart =
-    (uint8_t *)TheJIT->getPointerToGlobalIfAvailable(F.getFunction());
+  unsigned char *FnStart =
+    (unsigned char *)TheJIT->getPointerToGlobalIfAvailable(F.getFunction());
 
   // FnEnd is the end of the function's machine code.
-  uint8_t *FnEnd = CurBufferPtr;
+  unsigned char *FnEnd = CurBufferPtr;
 
   if (!Relocations.empty()) {
     CurFn = F.getFunction();
@@ -1183,7 +1183,7 @@
     } else {
       DOUT << "JIT: Binary code:\n";
       DOUT << std::hex;
-      uint8_t* q = FnStart;
+      unsigned char* q = FnStart;
       for (int i = 0; q < FnEnd; q += 4, ++i) {
         if (i == 4)
           i = 0;
@@ -1221,7 +1221,7 @@
     BufferBegin = CurBufferPtr = MemMgr->startExceptionTable(F.getFunction(),
                                                              ActualSize);
     BufferEnd = BufferBegin+ActualSize;
-    uint8_t* FrameRegister = DE->EmitDwarfTable(F, *this, FnStart, FnEnd);
+    unsigned char* FrameRegister = DE->EmitDwarfTable(F, *this, FnStart, FnEnd);
     MemMgr->endExceptionTable(F.getFunction(), BufferBegin, CurBufferPtr,
                               FrameRegister);
     BufferBegin = SavedBufferBegin;
@@ -1416,7 +1416,7 @@
   SavedBufferEnd = BufferEnd;
   SavedCurBufferPtr = CurBufferPtr;
   
-  BufferBegin = CurBufferPtr = (uint8_t *)Buffer;
+  BufferBegin = CurBufferPtr = (unsigned char *)Buffer;
   BufferEnd = BufferBegin+StubSize+1;
 }
 

Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITMemoryManager.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITMemoryManager.cpp?rev=72783&r1=72782&r2=72783&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JITMemoryManager.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JITMemoryManager.cpp Wed Jun  3 11:55:02 2009
@@ -257,9 +257,9 @@
     // When emitting code into a memory block, this is the block.
     MemoryRangeHeader *CurBlock;
     
-    uint8_t *CurStubPtr, *StubBase;
-    uint8_t *GOTBase;     // Target Specific reserved memory
-    void *DlsymTable;     // Stub external symbol information
+    unsigned char *CurStubPtr, *StubBase;
+    unsigned char *GOTBase;      // Target Specific reserved memory
+    void *DlsymTable;            // Stub external symbol information
 
     // Centralize memory block allocation.
     sys::MemoryBlock getNewMemoryBlock(unsigned size);
@@ -273,12 +273,12 @@
     void AllocateGOT();
     void SetDlsymTable(void *);
     
-    uint8_t *allocateStub(const GlobalValue* F, unsigned StubSize,
-                          unsigned Alignment);
+    unsigned char *allocateStub(const GlobalValue* F, unsigned StubSize,
+                                unsigned Alignment);
     
     /// startFunctionBody - When a function starts, allocate a block of free
     /// executable memory, returning a pointer to it and its actual size.
-    uint8_t *startFunctionBody(const Function *F, uintptr_t &ActualSize) {
+    unsigned char *startFunctionBody(const Function *F, uintptr_t &ActualSize) {
       
       FreeRangeHeader* candidateBlock = FreeMemoryList;
       FreeRangeHeader* head = FreeMemoryList;
@@ -301,18 +301,18 @@
       // Allocate the entire memory block.
       FreeMemoryList = candidateBlock->AllocateBlock();
       ActualSize = CurBlock->BlockSize-sizeof(MemoryRangeHeader);
-      return (uint8_t *)(CurBlock+1);
+      return (unsigned char *)(CurBlock+1);
     }
     
     /// endFunctionBody - The function F is now allocated, and takes the memory
     /// in the range [FunctionStart,FunctionEnd).
-    void endFunctionBody(const Function *F, uint8_t *FunctionStart,
-                         uint8_t *FunctionEnd) {
+    void endFunctionBody(const Function *F, unsigned char *FunctionStart,
+                         unsigned char *FunctionEnd) {
       assert(FunctionEnd > FunctionStart);
-      assert(FunctionStart == (uint8_t *)(CurBlock+1) &&
+      assert(FunctionStart == (unsigned char *)(CurBlock+1) &&
              "Mismatched function start/end!");
 
-      uintptr_t BlockSize = FunctionEnd - (uint8_t *)CurBlock;
+      uintptr_t BlockSize = FunctionEnd - (unsigned char *)CurBlock;
       FunctionBlocks[F] = CurBlock;
 
       // Release the memory at the end of this block that isn't needed.
@@ -320,17 +320,17 @@
     }
 
     /// allocateSpace - Allocate a memory block of the given size.
-    uint8_t *allocateSpace(intptr_t Size, unsigned Alignment) {
+    unsigned char *allocateSpace(intptr_t Size, unsigned Alignment) {
       CurBlock = FreeMemoryList;
       FreeMemoryList = FreeMemoryList->AllocateBlock();
 
-      uint8_t *result = (uint8_t *)CurBlock+1;
+      unsigned char *result = (unsigned char *)CurBlock+1;
 
       if (Alignment == 0) Alignment = 1;
-      result = (uint8_t*)(((intptr_t)result+Alignment-1) &
+      result = (unsigned char*)(((intptr_t)result+Alignment-1) &
                ~(intptr_t)(Alignment-1));
 
-      uintptr_t BlockSize = result + Size - (uint8_t *)CurBlock;
+      uintptr_t BlockSize = result + Size - (unsigned char *)CurBlock;
       FreeMemoryList =CurBlock->TrimAllocationToSize(FreeMemoryList, BlockSize);
 
       return result;
@@ -338,26 +338,28 @@
 
     /// startExceptionTable - Use startFunctionBody to allocate memory for the 
     /// function's exception table.
-    uint8_t* startExceptionTable(const Function* F, uintptr_t &ActualSize) {
+    unsigned char* startExceptionTable(const Function* F, 
+                                       uintptr_t &ActualSize) {
       return startFunctionBody(F, ActualSize);
     }
 
     /// endExceptionTable - The exception table of F is now allocated, 
     /// and takes the memory in the range [TableStart,TableEnd).
-    void endExceptionTable(const Function *F, uint8_t *TableStart,
-                           uint8_t *TableEnd, uint8_t* FrameRegister) {
+    void endExceptionTable(const Function *F, unsigned char *TableStart,
+                           unsigned char *TableEnd, 
+                           unsigned char* FrameRegister) {
       assert(TableEnd > TableStart);
-      assert(TableStart == (uint8_t *)(CurBlock+1) &&
+      assert(TableStart == (unsigned char *)(CurBlock+1) &&
              "Mismatched table start/end!");
       
-      uintptr_t BlockSize = TableEnd - (uint8_t *)CurBlock;
+      uintptr_t BlockSize = TableEnd - (unsigned char *)CurBlock;
       TableBlocks[F] = CurBlock;
 
       // Release the memory at the end of this block that isn't needed.
       FreeMemoryList =CurBlock->TrimAllocationToSize(FreeMemoryList, BlockSize);
     }
     
-    uint8_t *getGOTBase() const {
+    unsigned char *getGOTBase() const {
       return GOTBase;
     }
     
@@ -431,7 +433,7 @@
   sys::MemoryBlock MemBlock = getNewMemoryBlock(16 << 20);
 #endif
 
-  uint8_t *MemBase = static_cast(MemBlock.base());
+  unsigned char *MemBase = static_cast(MemBlock.base());
 
   // Allocate stubs backwards from the base, allocate functions forward
   // from the base.
@@ -490,7 +492,7 @@
 
 void DefaultJITMemoryManager::AllocateGOT() {
   assert(GOTBase == 0 && "Cannot allocate the got multiple times");
-  GOTBase = new uint8_t[sizeof(void*) * 8192];
+  GOTBase = new unsigned char[sizeof(void*) * 8192];
   HasGOT = true;
 }
 
@@ -506,12 +508,12 @@
   Blocks.clear();
 }
 
-uint8_t *DefaultJITMemoryManager::allocateStub(const GlobalValue* F,
+unsigned char *DefaultJITMemoryManager::allocateStub(const GlobalValue* F,
                                                      unsigned StubSize,
                                                      unsigned Alignment) {
   CurStubPtr -= StubSize;
-  CurStubPtr = (uint8_t*)(((intptr_t)CurStubPtr) &
-                          ~(intptr_t)(Alignment-1));
+  CurStubPtr = (unsigned char*)(((intptr_t)CurStubPtr) &
+                                ~(intptr_t)(Alignment-1));
   if (CurStubPtr < StubBase) {
     // FIXME: allocate a new block
     fprintf(stderr, "JIT ran out of memory for function stubs!\n");




From bruno.cardoso at gmail.com  Wed Jun  3 11:58:40 2009
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 3 Jun 2009 13:58:40 -0300
Subject: [llvm-commits] [llvm] r72650 - in /llvm/trunk:
	include/llvm/CodeGen/JITCodeEmitter.h
	include/llvm/CodeGen/MachineCodeEmitter.h
	include/llvm/ExecutionEngine/JITMemoryManager.h
	lib/CodeGen/MachOWriter.cpp lib/CodeGen/MachOWriter.h
	lib/ExecutionEngi
Message-ID: <275e64e40906030958x5061eaf4l8854d665a3a8eb3d@mail.gmail.com>

Hi Julien,

> Hello Bruno,
>
> I have a buildbot running some nightly tests here on MingW that started
> to complain somewhere between r72618 and r72690.
>
> Some of the tests we are running with lli are triggering the following
> assertion:
> Assertion failed: Addr && "Code generation didn't add function to
> GlobalAddress table!", file
> c:/cygwin/home/jlerouge/buildbot/llvm-src/lib/ExecutionEngine/JIT/JIT.cpp,
> line 603
>
> I realize this is very vague, but maybe you have any idea where that
> could be coming from ? Those tests have been pretty stable for the last
> couple month. I'll take a closer look in the coming days, but in the
> meantime, I thought I'd give a heads up ;-)

Could you provide me a test case so I can go further? I reverted 72650 for now.
Thanks,

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From bruno.cardoso at gmail.com  Wed Jun  3 12:47:31 2009
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 03 Jun 2009 17:47:31 -0000
Subject: [llvm-commits] [llvm] r72785 - in /llvm/trunk/lib/CodeGen:
 CMakeLists.txt ELFCodeEmitter.cpp ELFCodeEmitter.h ELFWriter.cpp
Message-ID: <200906031747.n53HlWoE020458@zion.cs.uiuc.edu>

Author: bruno
Date: Wed Jun  3 12:47:27 2009
New Revision: 72785

URL: http://llvm.org/viewvc/llvm-project?rev=72785&view=rev
Log:
Move ELFCodeEmiter stuff to new files

Added:
    llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp
    llvm/trunk/lib/CodeGen/ELFCodeEmitter.h
Modified:
    llvm/trunk/lib/CodeGen/CMakeLists.txt
    llvm/trunk/lib/CodeGen/ELFWriter.cpp

Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=72785&r1=72784&r2=72785&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/CMakeLists.txt (original)
+++ llvm/trunk/lib/CodeGen/CMakeLists.txt Wed Jun  3 12:47:27 2009
@@ -3,6 +3,7 @@
   CodePlacementOpt.cpp
   DeadMachineInstructionElim.cpp
   DwarfEHPrepare.cpp
+  ELFCodeEmitter.cpp
   ELFWriter.cpp
   GCMetadata.cpp
   GCMetadataPrinter.cpp

Added: llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp?rev=72785&view=auto

==============================================================================
--- llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp (added)
+++ llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp Wed Jun  3 12:47:27 2009
@@ -0,0 +1,94 @@
+//===-- lib/CodeGen/ELFCodeEmitter.cpp ------------------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "ELFCodeEmitter.h"
+#include "llvm/Constants.h"
+#include "llvm/DerivedTypes.h"
+#include "llvm/Function.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/Target/TargetAsmInfo.h"
+#include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Support/Mangler.h"
+#include "llvm/Support/OutputBuffer.h"
+
+//===----------------------------------------------------------------------===//
+//                       ELFCodeEmitter Implementation
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+
+/// startFunction - This callback is invoked when a new machine function is
+/// about to be emitted.
+void ELFCodeEmitter::startFunction(MachineFunction &F) {
+  // Align the output buffer to the appropriate alignment.
+  unsigned Align = 16;   // FIXME: GENERICIZE!!
+  // Get the ELF Section that this function belongs in.
+  ES = &EW.getSection(".text", ELFWriter::ELFSection::SHT_PROGBITS,
+                      ELFWriter::ELFSection::SHF_EXECINSTR |
+                      ELFWriter::ELFSection::SHF_ALLOC);
+  OutBuffer = &ES->SectionData;
+  cerr << "FIXME: This code needs to be updated for changes in the "
+       << "CodeEmitter interfaces.  In particular, this should set "
+       << "BufferBegin/BufferEnd/CurBufferPtr, not deal with OutBuffer!";
+  abort();
+
+  // Upgrade the section alignment if required.
+  if (ES->Align < Align) ES->Align = Align;
+
+  // Add padding zeros to the end of the buffer to make sure that the
+  // function will start on the correct byte alignment within the section.
+  OutputBuffer OB(*OutBuffer,
+                  TM.getTargetData()->getPointerSizeInBits() == 64,
+                  TM.getTargetData()->isLittleEndian());
+  OB.align(Align);
+  FnStart = OutBuffer->size();
+}
+
+/// finishFunction - This callback is invoked after the function is completely
+/// finished.
+bool ELFCodeEmitter::finishFunction(MachineFunction &F) {
+  // We now know the size of the function, add a symbol to represent it.
+  ELFWriter::ELFSym FnSym(F.getFunction());
+
+  // Figure out the binding (linkage) of the symbol.
+  switch (F.getFunction()->getLinkage()) {
+  default:
+    // appending linkage is illegal for functions.
+    assert(0 && "Unknown linkage type!");
+  case GlobalValue::ExternalLinkage:
+    FnSym.SetBind(ELFWriter::ELFSym::STB_GLOBAL);
+    break;
+  case GlobalValue::LinkOnceAnyLinkage:
+  case GlobalValue::LinkOnceODRLinkage:
+  case GlobalValue::WeakAnyLinkage:
+  case GlobalValue::WeakODRLinkage:
+    FnSym.SetBind(ELFWriter::ELFSym::STB_WEAK);
+    break;
+  case GlobalValue::PrivateLinkage:
+    assert (0 && "PrivateLinkage should not be in the symbol table.");
+  case GlobalValue::InternalLinkage:
+    FnSym.SetBind(ELFWriter::ELFSym::STB_LOCAL);
+    break;
+  }
+
+  ES->Size = OutBuffer->size();
+
+  FnSym.SetType(ELFWriter::ELFSym::STT_FUNC);
+  FnSym.SectionIdx = ES->SectionIdx;
+  FnSym.Value = FnStart;   // Value = Offset from start of Section.
+  FnSym.Size = OutBuffer->size()-FnStart;
+
+  // Finally, add it to the symtab.
+  EW.SymbolTable.push_back(FnSym);
+  return false;
+}
+
+} // end namespace llvm

Added: llvm/trunk/lib/CodeGen/ELFCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFCodeEmitter.h?rev=72785&view=auto

==============================================================================
--- llvm/trunk/lib/CodeGen/ELFCodeEmitter.h (added)
+++ llvm/trunk/lib/CodeGen/ELFCodeEmitter.h Wed Jun  3 12:47:27 2009
@@ -0,0 +1,87 @@
+//===-- lib/CodeGen/ELFCodeEmitter.h ----------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef ELFCODEEMITTER_H
+#define ELFCODEEMITTER_H
+
+#include "ELFWriter.h"
+#include "llvm/CodeGen/MachineCodeEmitter.h"
+#include 
+
+namespace llvm {
+
+  /// ELFCodeEmitter - This class is used by the ELFWriter to 
+  /// emit the code for functions to the ELF file.
+  class ELFCodeEmitter : public MachineCodeEmitter {
+    ELFWriter &EW;
+    TargetMachine &TM;
+    ELFWriter::ELFSection *ES;  // Section to write to.
+    std::vector *OutBuffer;
+    size_t FnStart;
+  public:
+    explicit ELFCodeEmitter(ELFWriter &ew) : EW(ew), TM(EW.TM), OutBuffer(0) {}
+
+    void startFunction(MachineFunction &F);
+    bool finishFunction(MachineFunction &F);
+
+    void addRelocation(const MachineRelocation &MR) {
+      assert(0 && "relo not handled yet!");
+    }
+
+    virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) {
+    }
+
+    virtual uintptr_t getConstantPoolEntryAddress(unsigned Index) const {
+      assert(0 && "CP not implementated yet!");
+      return 0;
+    }
+    virtual uintptr_t getJumpTableEntryAddress(unsigned Index) const {
+      assert(0 && "JT not implementated yet!");
+      return 0;
+    }
+
+    virtual uintptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const {
+      assert(0 && "JT not implementated yet!");
+      return 0;
+    }
+
+    virtual uintptr_t getLabelAddress(uint64_t Label) const {
+      assert(0 && "Label address not implementated yet!");
+      abort();
+      return 0;
+    }
+
+    virtual void emitLabel(uint64_t LabelID) {
+      assert(0 && "emit Label not implementated yet!");
+      abort();
+    }
+
+    virtual void setModuleInfo(llvm::MachineModuleInfo* MMI) { }
+
+    /// JIT SPECIFIC FUNCTIONS - DO NOT IMPLEMENT THESE HERE!
+    void startGVStub(const GlobalValue* F, unsigned StubSize,
+                     unsigned Alignment = 1) {
+      assert(0 && "JIT specific function called!");
+      abort();
+    }
+    void startGVStub(const GlobalValue* F,  void *Buffer, unsigned StubSize) {
+      assert(0 && "JIT specific function called!");
+      abort();
+    }
+    void *finishGVStub(const GlobalValue *F) {
+      assert(0 && "JIT specific function called!");
+      abort();
+      return 0;
+    }
+};  // end class ELFCodeEmitter
+
+} // end namespace llvm
+
+#endif
+

Modified: llvm/trunk/lib/CodeGen/ELFWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.cpp?rev=72785&r1=72784&r2=72785&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/ELFWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/ELFWriter.cpp Wed Jun  3 12:47:27 2009
@@ -32,6 +32,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "ELFWriter.h"
+#include "ELFCodeEmitter.h"
 #include "llvm/Module.h"
 #include "llvm/PassManager.h"
 #include "llvm/DerivedTypes.h"
@@ -61,149 +62,10 @@
 }
 
 //===----------------------------------------------------------------------===//
-//                       ELFCodeEmitter Implementation
-//===----------------------------------------------------------------------===//
-
-namespace llvm {
-  /// ELFCodeEmitter - This class is used by the ELFWriter to emit the code for
-  /// functions to the ELF file.
-  class ELFCodeEmitter : public MachineCodeEmitter {
-    ELFWriter &EW;
-    TargetMachine &TM;
-    ELFWriter::ELFSection *ES;  // Section to write to.
-    std::vector *OutBuffer;
-    size_t FnStart;
-  public:
-    explicit ELFCodeEmitter(ELFWriter &ew) : EW(ew), TM(EW.TM), OutBuffer(0) {}
-
-    void startFunction(MachineFunction &F);
-    bool finishFunction(MachineFunction &F);
-
-    void addRelocation(const MachineRelocation &MR) {
-      assert(0 && "relo not handled yet!");
-    }
-    
-    virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) {
-    }
-
-    virtual uintptr_t getConstantPoolEntryAddress(unsigned Index) const {
-      assert(0 && "CP not implementated yet!");
-      return 0;
-    }
-    virtual uintptr_t getJumpTableEntryAddress(unsigned Index) const {
-      assert(0 && "JT not implementated yet!");
-      return 0;
-    }
-
-    virtual uintptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const {
-      assert(0 && "JT not implementated yet!");
-      return 0;
-    }
-
-    virtual uintptr_t getLabelAddress(uint64_t Label) const {
-      assert(0 && "Label address not implementated yet!");
-      abort();
-      return 0;
-    }
-
-    virtual void emitLabel(uint64_t LabelID) {
-      assert(0 && "emit Label not implementated yet!");
-      abort();
-    }
-
-
-    virtual void setModuleInfo(llvm::MachineModuleInfo* MMI) { }
-
-
-    /// JIT SPECIFIC FUNCTIONS - DO NOT IMPLEMENT THESE HERE!
-    void startGVStub(const GlobalValue* F, unsigned StubSize,
-                     unsigned Alignment = 1) {
-      assert(0 && "JIT specific function called!");
-      abort();
-    }
-    void startGVStub(const GlobalValue* F,  void *Buffer, unsigned StubSize) {
-      assert(0 && "JIT specific function called!");
-      abort();
-    }
-    void *finishGVStub(const GlobalValue *F) {
-      assert(0 && "JIT specific function called!");
-      abort();
-      return 0;
-    }
-  };
-}
-
-/// startFunction - This callback is invoked when a new machine function is
-/// about to be emitted.
-void ELFCodeEmitter::startFunction(MachineFunction &F) {
-  // Align the output buffer to the appropriate alignment.
-  unsigned Align = 16;   // FIXME: GENERICIZE!!
-  // Get the ELF Section that this function belongs in.
-  ES = &EW.getSection(".text", ELFWriter::ELFSection::SHT_PROGBITS,
-                      ELFWriter::ELFSection::SHF_EXECINSTR |
-                      ELFWriter::ELFSection::SHF_ALLOC);
-  OutBuffer = &ES->SectionData;
-  cerr << "FIXME: This code needs to be updated for changes in the "
-       << "CodeEmitter interfaces.  In particular, this should set "
-       << "BufferBegin/BufferEnd/CurBufferPtr, not deal with OutBuffer!";
-  abort();
-
-  // Upgrade the section alignment if required.
-  if (ES->Align < Align) ES->Align = Align;
-
-  // Add padding zeros to the end of the buffer to make sure that the
-  // function will start on the correct byte alignment within the section.
-  OutputBuffer OB(*OutBuffer,
-                  TM.getTargetData()->getPointerSizeInBits() == 64,
-                  TM.getTargetData()->isLittleEndian());
-  OB.align(Align);
-  FnStart = OutBuffer->size();
-}
-
-/// finishFunction - This callback is invoked after the function is completely
-/// finished.
-bool ELFCodeEmitter::finishFunction(MachineFunction &F) {
-  // We now know the size of the function, add a symbol to represent it.
-  ELFWriter::ELFSym FnSym(F.getFunction());
-
-  // Figure out the binding (linkage) of the symbol.
-  switch (F.getFunction()->getLinkage()) {
-  default:
-    // appending linkage is illegal for functions.
-    assert(0 && "Unknown linkage type!");
-  case GlobalValue::ExternalLinkage:
-    FnSym.SetBind(ELFWriter::ELFSym::STB_GLOBAL);
-    break;
-  case GlobalValue::LinkOnceAnyLinkage:
-  case GlobalValue::LinkOnceODRLinkage:
-  case GlobalValue::WeakAnyLinkage:
-  case GlobalValue::WeakODRLinkage:
-    FnSym.SetBind(ELFWriter::ELFSym::STB_WEAK);
-    break;
-  case GlobalValue::PrivateLinkage:
-    assert (0 && "PrivateLinkage should not be in the symbol table.");
-  case GlobalValue::InternalLinkage:
-    FnSym.SetBind(ELFWriter::ELFSym::STB_LOCAL);
-    break;
-  }
-
-  ES->Size = OutBuffer->size();
-
-  FnSym.SetType(ELFWriter::ELFSym::STT_FUNC);
-  FnSym.SectionIdx = ES->SectionIdx;
-  FnSym.Value = FnStart;   // Value = Offset from start of Section.
-  FnSym.Size = OutBuffer->size()-FnStart;
-
-  // Finally, add it to the symtab.
-  EW.SymbolTable.push_back(FnSym);
-  return false;
-}
-
-//===----------------------------------------------------------------------===//
 //                          ELFWriter Implementation
 //===----------------------------------------------------------------------===//
 
-ELFWriter::ELFWriter(raw_ostream &o, TargetMachine &tm) 
+ELFWriter::ELFWriter(raw_ostream &o, TargetMachine &tm)
   : MachineFunctionPass(&ID), O(o), TM(tm) {
   e_flags = 0;    // e_flags defaults to 0, no flags.
 




From daniel at zuster.org  Wed Jun  3 12:52:40 2009
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 03 Jun 2009 17:52:40 -0000
Subject: [llvm-commits] [llvm] r72786 -
	/llvm/trunk/include/llvm/Support/StandardPasses.h
Message-ID: <200906031752.n53Hqe0j020611@zion.cs.uiuc.edu>

Author: ddunbar
Date: Wed Jun  3 12:52:39 2009
New Revision: 72786

URL: http://llvm.org/viewvc/llvm-project?rev=72786&view=rev
Log:
Add StandardPasses.h which embeds the standard compilation passes shared by
clang/llvm-gcc.
 - Implemented as inline functions for linking simplicity.

Added:
    llvm/trunk/include/llvm/Support/StandardPasses.h

Added: llvm/trunk/include/llvm/Support/StandardPasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=72786&view=auto

==============================================================================
--- llvm/trunk/include/llvm/Support/StandardPasses.h (added)
+++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed Jun  3 12:52:39 2009
@@ -0,0 +1,149 @@
+//===-- llvm/Support/StandardPasses.h - Standard pass lists -----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines utility functions for creating a "standard" set of
+// optimization passes, so that compilers and tools which use optimization
+// passes use the same set of standard passes.
+//
+// These are implemented as inline functions so that we do not have to worry
+// about link issues.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_SUPPORT_STANDARDPASSES_H
+#define LLVM_SUPPORT_STANDARDPASSES_H
+
+#include "llvm/PassManager.h"
+#include "llvm/Transforms/Scalar.h"
+#include "llvm/Transforms/IPO.h"
+
+namespace llvm {
+  /// createStandardFunctionPasses - Add the standard list of function passes to
+  /// the provided pass manager.
+  ///
+  /// \arg OptimizationLevel - The optimization level, corresponding to -O0,
+  /// -O1, etc.
+  static inline void createStandardFunctionPasses(FunctionPassManager *PM,
+                                                  unsigned OptimizationLevel);
+
+  /// createStandardModulePasses - Add the standard list of module passes to the
+  /// provided pass manager.
+  ///
+  /// \arg OptimizationLevel - The optimization level, corresponding to -O0,
+  /// -O1, etc.
+  /// \arg OptimizeSize - Whether the transformations should optimize for size.
+  /// \arg UnitAtATime - Allow passes which may make global module changes.
+  /// \arg UnrollLoops - Allow loop unrolling.
+  /// \arg SimplifyLibCalls - Allow library calls to be simplified.
+  /// \arg HaveExceptions - Whether the module may have code using exceptions.
+  /// \arg InliningPass - The inlining pass to use, if any, or null. This will
+  /// always be added, even at -O0.a
+  static inline void createStandardModulePasses(PassManager *PM,
+                                                unsigned OptimizationLevel,
+                                                bool OptimizeSize,
+                                                bool UnitAtATime,
+                                                bool UnrollLoops,
+                                                bool SimplifyLibCalls,
+                                                bool HaveExceptions,
+                                                Pass *InliningPass);
+
+  // Implementations
+
+  static inline void createStandardFunctionPasses(FunctionPassManager *PM,
+                                                  unsigned OptimizationLevel) {
+    if (OptimizationLevel > 0) {
+      PM->add(createCFGSimplificationPass());
+      if (OptimizationLevel == 1)
+        PM->add(createPromoteMemoryToRegisterPass());
+      else
+        PM->add(createScalarReplAggregatesPass());
+      PM->add(createInstructionCombiningPass());
+    }
+  }
+
+  static inline void createStandardModulePasses(PassManager *PM,
+                                                unsigned OptimizationLevel,
+                                                bool OptimizeSize,
+                                                bool UnitAtATime,
+                                                bool UnrollLoops,
+                                                bool SimplifyLibCalls,
+                                                bool HaveExceptions,
+                                                Pass *InliningPass) {
+    if (OptimizationLevel == 0) {
+      if (InliningPass)
+        PM->add(InliningPass);
+    } else {
+      if (UnitAtATime)
+        PM->add(createRaiseAllocationsPass());    // call %malloc -> malloc inst
+      PM->add(createCFGSimplificationPass());     // Clean up disgusting code
+       // Kill useless allocas
+      PM->add(createPromoteMemoryToRegisterPass());
+      if (UnitAtATime) {
+        PM->add(createGlobalOptimizerPass());     // Optimize out global vars
+        PM->add(createGlobalDCEPass());           // Remove unused fns and globs
+        // IP Constant Propagation
+        PM->add(createIPConstantPropagationPass());
+        PM->add(createDeadArgEliminationPass());  // Dead argument elimination
+      }
+      PM->add(createInstructionCombiningPass());  // Clean up after IPCP & DAE
+      PM->add(createCFGSimplificationPass());     // Clean up after IPCP & DAE
+      if (UnitAtATime) {
+        if (HaveExceptions)
+          PM->add(createPruneEHPass());           // Remove dead EH info
+        PM->add(createFunctionAttrsPass());       // Set readonly/readnone attrs
+      }
+      if (InliningPass)
+        PM->add(InliningPass);
+      if (OptimizationLevel > 2)
+        PM->add(createArgumentPromotionPass());   // Scalarize uninlined fn args
+      if (SimplifyLibCalls)
+        PM->add(createSimplifyLibCallsPass());    // Library Call Optimizations
+      PM->add(createInstructionCombiningPass());  // Cleanup for scalarrepl.
+      PM->add(createJumpThreadingPass());         // Thread jumps.
+      PM->add(createCFGSimplificationPass());     // Merge & remove BBs
+      PM->add(createScalarReplAggregatesPass());  // Break up aggregate allocas
+      PM->add(createInstructionCombiningPass());  // Combine silly seq's
+      PM->add(createCondPropagationPass());       // Propagate conditionals
+      PM->add(createTailCallEliminationPass());   // Eliminate tail calls
+      PM->add(createCFGSimplificationPass());     // Merge & remove BBs
+      PM->add(createReassociatePass());           // Reassociate expressions
+      PM->add(createLoopRotatePass());            // Rotate Loop
+      PM->add(createLICMPass());                  // Hoist loop invariants
+      PM->add(createLoopUnswitchPass(OptimizeSize ? true : false));
+      PM->add(createLoopIndexSplitPass());        // Split loop index
+      PM->add(createInstructionCombiningPass());  
+      PM->add(createIndVarSimplifyPass());        // Canonicalize indvars
+      PM->add(createLoopDeletionPass());          // Delete dead loops
+      if (UnrollLoops)
+        PM->add(createLoopUnrollPass());          // Unroll small loops
+      PM->add(createInstructionCombiningPass());  // Clean up after the unroller
+      PM->add(createGVNPass());                   // Remove redundancies
+      PM->add(createMemCpyOptPass());             // Remove memcpy / form memset
+      PM->add(createSCCPPass());                  // Constant prop with SCCP
+    
+      // Run instcombine after redundancy elimination to exploit opportunities
+      // opened up by them.
+      PM->add(createInstructionCombiningPass());
+      PM->add(createCondPropagationPass());       // Propagate conditionals
+      PM->add(createDeadStoreEliminationPass());  // Delete dead stores
+      PM->add(createAggressiveDCEPass());         // Delete dead instructions
+      PM->add(createCFGSimplificationPass());     // Merge & remove BBs
+
+      if (UnitAtATime) {
+        PM->add(createStripDeadPrototypesPass()); // Get rid of dead prototypes
+        PM->add(createDeadTypeEliminationPass()); // Eliminate dead types
+      }
+
+      if (OptimizationLevel > 1 && UnitAtATime)
+        PM->add(createConstantMergePass());       // Merge dup global constants
+    }
+  }
+}
+
+#endif




From daniel at zuster.org  Wed Jun  3 13:13:06 2009
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 03 Jun 2009 18:13:06 -0000
Subject: [llvm-commits] [llvm] r72788 -
	/llvm/trunk/include/llvm/Support/StandardPasses.h
Message-ID: <200906031813.n53ID601021620@zion.cs.uiuc.edu>

Author: ddunbar
Date: Wed Jun  3 13:13:05 2009
New Revision: 72788

URL: http://llvm.org/viewvc/llvm-project?rev=72788&view=rev
Log:
Remove some silly code.

Modified:
    llvm/trunk/include/llvm/Support/StandardPasses.h

Modified: llvm/trunk/include/llvm/Support/StandardPasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=72788&r1=72787&r2=72788&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/StandardPasses.h (original)
+++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed Jun  3 13:13:05 2009
@@ -115,7 +115,7 @@
       PM->add(createReassociatePass());           // Reassociate expressions
       PM->add(createLoopRotatePass());            // Rotate Loop
       PM->add(createLICMPass());                  // Hoist loop invariants
-      PM->add(createLoopUnswitchPass(OptimizeSize ? true : false));
+      PM->add(createLoopUnswitchPass(OptimizeSize));
       PM->add(createLoopIndexSplitPass());        // Split loop index
       PM->add(createInstructionCombiningPass());  
       PM->add(createIndVarSimplifyPass());        // Canonicalize indvars




From daniel at zuster.org  Wed Jun  3 13:22:15 2009
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 03 Jun 2009 18:22:15 -0000
Subject: [llvm-commits] [llvm] r72789 - /llvm/trunk/tools/opt/opt.cpp
Message-ID: <200906031822.n53IMFku021947@zion.cs.uiuc.edu>

Author: ddunbar
Date: Wed Jun  3 13:22:15 2009
New Revision: 72789

URL: http://llvm.org/viewvc/llvm-project?rev=72789&view=rev
Log:
Switch opt to using StandardPasses.h
 - No functionality change, but please check if you don't believe me.

Modified:
    llvm/trunk/tools/opt/opt.cpp

Modified: llvm/trunk/tools/opt/opt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=72789&r1=72788&r2=72789&view=diff

==============================================================================
--- llvm/trunk/tools/opt/opt.cpp (original)
+++ llvm/trunk/tools/opt/opt.cpp Wed Jun  3 13:22:15 2009
@@ -28,6 +28,7 @@
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/PluginLoader.h"
+#include "llvm/Support/StandardPasses.h"
 #include "llvm/Support/Streams.h"
 #include "llvm/Support/SystemUtils.h"
 #include "llvm/Support/raw_ostream.h"
@@ -266,79 +267,16 @@
 /// OptLevel - Optimization Level
 void AddOptimizationPasses(PassManager &MPM, FunctionPassManager &FPM,
                            unsigned OptLevel) {
+  createStandardFunctionPasses(&FPM, OptLevel);
 
-  if (OptLevel == 0) 
-    return;
-
-  FPM.add(createCFGSimplificationPass());
-  if (OptLevel == 1)
-    FPM.add(createPromoteMemoryToRegisterPass());
-  else
-    FPM.add(createScalarReplAggregatesPass());
-  FPM.add(createInstructionCombiningPass());
-
-  if (UnitAtATime)
-    MPM.add(createRaiseAllocationsPass());      // call %malloc -> malloc inst
-  MPM.add(createCFGSimplificationPass());       // Clean up disgusting code
-  MPM.add(createPromoteMemoryToRegisterPass()); // Kill useless allocas
-  if (UnitAtATime) {
-    MPM.add(createGlobalOptimizerPass());       // OptLevel out global vars
-    MPM.add(createGlobalDCEPass());             // Remove unused fns and globs
-    MPM.add(createIPConstantPropagationPass()); // IP Constant Propagation
-    MPM.add(createDeadArgEliminationPass());    // Dead argument elimination
-  }
-  MPM.add(createInstructionCombiningPass());    // Clean up after IPCP & DAE
-  MPM.add(createCFGSimplificationPass());       // Clean up after IPCP & DAE
-  if (UnitAtATime) {
-    MPM.add(createPruneEHPass());               // Remove dead EH info
-    MPM.add(createFunctionAttrsPass());         // Deduce function attrs
-  }
-  if (OptLevel > 1)
-    MPM.add(createFunctionInliningPass());      // Inline small functions
-  if (OptLevel > 2)
-    MPM.add(createArgumentPromotionPass());   // Scalarize uninlined fn args
-  if (!DisableSimplifyLibCalls)
-    MPM.add(createSimplifyLibCallsPass());    // Library Call Optimizations
-  MPM.add(createInstructionCombiningPass());  // Cleanup for scalarrepl.
-  MPM.add(createJumpThreadingPass());         // Thread jumps.
-  MPM.add(createCFGSimplificationPass());     // Merge & remove BBs
-  MPM.add(createScalarReplAggregatesPass());  // Break up aggregate allocas
-  MPM.add(createInstructionCombiningPass());  // Combine silly seq's
-  MPM.add(createCondPropagationPass());       // Propagate conditionals
-  MPM.add(createTailCallEliminationPass());   // Eliminate tail calls
-  MPM.add(createCFGSimplificationPass());     // Merge & remove BBs
-  MPM.add(createReassociatePass());           // Reassociate expressions
-  MPM.add(createLoopRotatePass());            // Rotate Loop
-  MPM.add(createLICMPass());                  // Hoist loop invariants
-  MPM.add(createLoopUnswitchPass());
-  MPM.add(createLoopIndexSplitPass());        // Split loop index
-  MPM.add(createInstructionCombiningPass());  
-  MPM.add(createIndVarSimplifyPass());        // Canonicalize indvars
-  MPM.add(createLoopDeletionPass());          // Delete dead loops
-  if (OptLevel > 1)
-    MPM.add(createLoopUnrollPass());          // Unroll small loops
-  MPM.add(createInstructionCombiningPass());  // Clean up after the unroller
-  MPM.add(createGVNPass());                   // Remove redundancies
-  MPM.add(createMemCpyOptPass());             // Remove memcpy / form memset
-  MPM.add(createSCCPPass());                  // Constant prop with SCCP
-  
-  // Run instcombine after redundancy elimination to exploit opportunities
-  // opened up by them.
-  MPM.add(createInstructionCombiningPass());
-  MPM.add(createCondPropagationPass());       // Propagate conditionals
-  MPM.add(createDeadStoreEliminationPass());  // Delete dead stores
-  MPM.add(createAggressiveDCEPass());   // Delete dead instructions
-  MPM.add(createCFGSimplificationPass());     // Merge & remove BBs
-  
-  if (UnitAtATime) {
-    MPM.add(createStripDeadPrototypesPass());   // Get rid of dead prototypes
-    MPM.add(createDeadTypeEliminationPass());   // Eliminate dead types
-  }
-  
-  if (OptLevel > 1 && UnitAtATime)
-    MPM.add(createConstantMergePass());       // Merge dup global constants 
-  
-  return;
+  llvm::Pass *InliningPass = OptLevel > 1 ? createFunctionInliningPass() : 0;
+  createStandardModulePasses(&MPM, OptLevel,
+                             /*OptimizeSize=*/ false,
+                             UnitAtATime,
+                             /*UnrollLoops=*/ OptLevel > 1,
+                             !DisableSimplifyLibCalls,
+                             /*HaveExceptions=*/ true,
+                             InliningPass);
 }
 
 void AddStandardCompilePasses(PassManager &PM) {
@@ -352,59 +290,16 @@
 
   if (DisableOptimizations) return;
 
-  addPass(PM, createRaiseAllocationsPass());     // call %malloc -> malloc inst
-  addPass(PM, createCFGSimplificationPass());    // Clean up disgusting code
-  addPass(PM, createPromoteMemoryToRegisterPass());// Kill useless allocas
-  addPass(PM, createGlobalOptimizerPass());      // Optimize out global vars
-  addPass(PM, createGlobalDCEPass());            // Remove unused fns and globs
-  addPass(PM, createIPConstantPropagationPass());// IP Constant Propagation
-  addPass(PM, createDeadArgEliminationPass());   // Dead argument elimination
-  addPass(PM, createInstructionCombiningPass()); // Clean up after IPCP & DAE
-  addPass(PM, createCFGSimplificationPass());    // Clean up after IPCP & DAE
-
-  addPass(PM, createPruneEHPass());              // Remove dead EH info
-  addPass(PM, createFunctionAttrsPass());        // Deduce function attrs
-
-  if (!DisableInline)
-    addPass(PM, createFunctionInliningPass());   // Inline small functions
-  addPass(PM, createArgumentPromotionPass());    // Scalarize uninlined fn args
-
-  addPass(PM, createSimplifyLibCallsPass());     // Library Call Optimizations
-  addPass(PM, createInstructionCombiningPass()); // Cleanup for scalarrepl.
-  addPass(PM, createJumpThreadingPass());        // Thread jumps.
-  addPass(PM, createCFGSimplificationPass());    // Merge & remove BBs
-  addPass(PM, createScalarReplAggregatesPass()); // Break up aggregate allocas
-  addPass(PM, createInstructionCombiningPass()); // Combine silly seq's
-  addPass(PM, createCondPropagationPass());      // Propagate conditionals
-
-  addPass(PM, createTailCallEliminationPass());  // Eliminate tail calls
-  addPass(PM, createCFGSimplificationPass());    // Merge & remove BBs
-  addPass(PM, createReassociatePass());          // Reassociate expressions
-  addPass(PM, createLoopRotatePass());
-  addPass(PM, createLICMPass());                 // Hoist loop invariants
-  addPass(PM, createLoopUnswitchPass());         // Unswitch loops.
-  addPass(PM, createLoopIndexSplitPass());       // Index split loops.
-  // FIXME : Removing instcombine causes nestedloop regression.
-  addPass(PM, createInstructionCombiningPass());
-  addPass(PM, createIndVarSimplifyPass());       // Canonicalize indvars
-  addPass(PM, createLoopDeletionPass());         // Delete dead loops
-  addPass(PM, createLoopUnrollPass());           // Unroll small loops
-  addPass(PM, createInstructionCombiningPass()); // Clean up after the unroller
-  addPass(PM, createGVNPass());                  // Remove redundancies
-  addPass(PM, createMemCpyOptPass());            // Remove memcpy / form memset
-  addPass(PM, createSCCPPass());                 // Constant prop with SCCP
-
-  // Run instcombine after redundancy elimination to exploit opportunities
-  // opened up by them.
-  addPass(PM, createInstructionCombiningPass());
-  addPass(PM, createCondPropagationPass());      // Propagate conditionals
-
-  addPass(PM, createDeadStoreEliminationPass()); // Delete dead stores
-  addPass(PM, createAggressiveDCEPass());        // Delete dead instructions
-  addPass(PM, createCFGSimplificationPass());    // Merge & remove BBs
-  addPass(PM, createStripDeadPrototypesPass());  // Get rid of dead prototypes
-  addPass(PM, createDeadTypeEliminationPass());  // Eliminate dead types
-  addPass(PM, createConstantMergePass());        // Merge dup global constants
+  llvm::Pass *InliningPass = !DisableInline ? createFunctionInliningPass() : 0;
+
+  // -std-compile-opts adds the same module passes as -O3.
+  createStandardModulePasses(&PM, 3, 
+                             /*OptimizeSize=*/ false,
+                             /*UnitAtATime=*/ true,
+                             /*UnrollLoops=*/ true,
+                             /*SimplifyLibCalls=*/ true,
+                             /*HaveExceptions=*/ true,
+                             InliningPass);
 }
 
 } // anonymous namespace




From edwintorok at gmail.com  Wed Jun  3 13:51:20 2009
From: edwintorok at gmail.com (=?UTF-8?B?VMO2csO2ayBFZHdpbg==?=)
Date: Wed, 03 Jun 2009 21:51:20 +0300
Subject: [llvm-commits] [llvm] r72773 - /llvm/trunk/docs/GoldPlugin.html
In-Reply-To: <4A26A54A.3070201@gmail.com>
References: <200906031506.n53F6JOs014297@zion.cs.uiuc.edu>	
	<38a0d8450906030911u6ece8f37jef8f887ef719c2c0@mail.gmail.com>	
	<4A26A2E5.4@gmail.com>
	<38a0d8450906030928q5e5f8b51le17588675f3bf2cb@mail.gmail.com>
	<4A26A54A.3070201@gmail.com>
Message-ID: <4A26C628.5060709@gmail.com>

On 2009-06-03 19:31, T?r?k Edwin wrote:
> On 2009-06-03 19:28, Rafael Espindola wrote:
>   
>>> But without --plugin it doesn't:
>>> $ /home/edwin/llvm-svn/install/bin/nm
>>> /home/edwin/clam/git/builds/lto/libclamav/lzma/.libs/liblzma.a
>>> /home/edwin/llvm-svn/install/bin/nm: LzmaStateDecode.o: File format not
>>> recognized
>>>     
>>>       
>> That is strange. Can you run in strace and check that it is trying to
>> open the bfd-plugins directory?
>>   
>>     
>
> It does, but it doesn't seem to load anything from there.
>
> I attached the strace output and liblzma.a.
>
> To reproduce my failure try running:
> /bin/nm liblzma.a
>
> vs.
>
> /bin/nm liblzma.a --plugin libLLVMgold.so
>
>   

plugin.c does this:
if (ent->d_type != DT_REG && ent->d_type != DT_LNK)
    continue;

I am using reiserfs for my /home, and IIRC it doesn't implement the
d_type field and return DT_UNKNOWN for all files.
If you get DT_UNKNOWN you should lstat(), and check the result.

Best regards,
--Edwin


From daniel at zuster.org  Wed Jun  3 14:03:17 2009
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 03 Jun 2009 19:03:17 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r72795 -
	/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Message-ID: <200906031903.n53J3H5u023774@zion.cs.uiuc.edu>

Author: ddunbar
Date: Wed Jun  3 14:03:17 2009
New Revision: 72795

URL: http://llvm.org/viewvc/llvm-project?rev=72795&view=rev
Log:
Pull out code to create the appropriate InliningPass.
 - No functionality change.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=72795&r1=72794&r2=72795&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Jun  3 14:03:17 2009
@@ -632,26 +632,31 @@
   PerModulePasses = new PassManager();
   PerModulePasses->add(new TargetData(*TheTarget->getTargetData()));
   bool HasPerModulePasses = false;
-  bool NeedAlwaysInliner = false;
-  if (flag_inline_trees <= 1) {
-    // If full inliner is not run, check if always-inline is needed to handle
-    // functions that are  marked as always_inline.
-    for (Module::iterator I = TheModule->begin(), E = TheModule->end();
-         I != E; ++I)
-      if (I->hasFnAttr(Attribute::AlwaysInline)) {
-        NeedAlwaysInliner = true;
-        break;
-      }
-  }
 
   if (!DisableLLVMOptimizations) {
+    bool NeedAlwaysInliner = false;
+    llvm::Pass *InliningPass = 0;
+    if (flag_inline_trees > 1) {                // respect -fno-inline-functions
+      InliningPass = createFunctionInliningPass();    // Inline small functions
+    } else {
+      // If full inliner is not run, check if always-inline is needed to handle
+      // functions that are  marked as always_inline.
+      for (Module::iterator I = TheModule->begin(), E = TheModule->end();
+           I != E; ++I)
+        if (I->hasFnAttr(Attribute::AlwaysInline)) {
+          NeedAlwaysInliner = true;
+          break;
+        }
+
+      if (NeedAlwaysInliner)
+        InliningPass = createAlwaysInlinerPass();  // Inline always_inline funcs
+    }
+
     HasPerModulePasses = true;
     PassManager *PM = PerModulePasses;
     if (optimize == 0) {
-      if (flag_inline_trees > 1)                // respect -fno-inline-functions
-        PM->add(createFunctionInliningPass());    // Inline small functions
-      else if (NeedAlwaysInliner)
-        PM->add(createAlwaysInlinerPass());       // Inline always_inline funcs
+      if (InliningPass)
+        PM->add(InliningPass);
     } else {
       if (flag_unit_at_a_time)
         PM->add(createRaiseAllocationsPass());    // call %malloc -> malloc inst
@@ -670,10 +675,8 @@
           PM->add(createPruneEHPass());           // Remove dead EH info
         PM->add(createFunctionAttrsPass());       // Deduce function attrs
       }
-      if (flag_inline_trees > 1)                // respect -fno-inline-functions
-        PM->add(createFunctionInliningPass());    // Inline small functions
-      else if (NeedAlwaysInliner)
-        PM->add(createAlwaysInlinerPass());       // Inline always_inline funcs
+      if (InliningPass)
+        PM->add(InliningPass);
       if (optimize > 2)
         PM->add(createArgumentPromotionPass());   // Scalarize uninlined fn args
       if (!flag_no_simplify_libcalls)




From mrs at apple.com  Wed Jun  3 14:07:46 2009
From: mrs at apple.com (Mike Stump)
Date: Wed, 03 Jun 2009 19:07:46 -0000
Subject: [llvm-commits] [llvm] r72797 -
	/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
Message-ID: <200906031907.n53J7kdM023977@zion.cs.uiuc.edu>

Author: mrs
Date: Wed Jun  3 14:07:46 2009
New Revision: 72797

URL: http://llvm.org/viewvc/llvm-project?rev=72797&view=rev
Log:
Make the buildbot see green (to make it easier to spot the next person
that puts a new warning in).

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=72797&r1=72796&r2=72797&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Wed Jun  3 14:07:46 2009
@@ -354,7 +354,8 @@
   FrameIndexSDNode *FR = dyn_cast(SDValue(N,0));
   // FIXME there isn't really debug info here
   DebugLoc dl = FR->getDebugLoc();
-  int Index = FR->getIndex();
+  // FIXME: Not used.
+  // int Index = FR->getIndex();
 
   // Expand FrameIndex like GlobalAddress and ExternalSymbol
   // Also use Offset field for lo and hi parts. The default 




From gohman at apple.com  Wed Jun  3 14:11:31 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 03 Jun 2009 19:11:31 -0000
Subject: [llvm-commits] [llvm] r72798 - in /llvm/trunk:
 lib/Transforms/Scalar/IndVarSimplify.cpp
 test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll
 test/Transforms/IndVarSimplify/variable-stride-ivs-1.ll
 test/Transforms/IndVarSimplify/variable-stride-ivs.ll
Message-ID: <200906031911.n53JBVSd024193@zion.cs.uiuc.edu>

Author: djg
Date: Wed Jun  3 14:11:31 2009
New Revision: 72798

URL: http://llvm.org/viewvc/llvm-project?rev=72798&view=rev
Log:
Don't attempt to simplify an non-affine IV expression if it can't
be simplified to a loop-invariant value. This fixes PR4315.

Added:
    llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll   (props changed)
      - copied unchanged from r72786, llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs.ll
    llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-1.ll
Removed:
    llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=72798&r1=72797&r2=72798&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Wed Jun  3 14:11:31 2009
@@ -465,17 +465,6 @@
       // Compute the final addrec to expand into code.
       SCEVHandle AR = IU->getReplacementExpr(*UI);
 
-      // FIXME: It is an extremely bad idea to indvar substitute anything more
-      // complex than affine induction variables.  Doing so will put expensive
-      // polynomial evaluations inside of the loop, and the str reduction pass
-      // currently can only reduce affine polynomials.  For now just disable
-      // indvar subst on anything more complex than an affine addrec, unless
-      // it can be expanded to a trivial value.
-      if (!Stride->isLoopInvariant(L) &&
-          !isa(AR) &&
-          L->contains(User->getParent()))
-        continue;
-
       Value *NewVal = 0;
       if (AR->isLoopInvariant(L)) {
         BasicBlock::iterator I = Rewriter.getInsertionPoint();
@@ -487,6 +476,15 @@
         Rewriter.setInsertionPoint(I);
         ++NumReplaced;
       } else {
+        // FIXME: It is an extremely bad idea to indvar substitute anything more
+        // complex than affine induction variables.  Doing so will put expensive
+        // polynomial evaluations inside of the loop, and the str reduction pass
+        // currently can only reduce affine polynomials.  For now just disable
+        // indvar subst on anything more complex than an affine addrec, unless
+        // it can be expanded to a trivial value.
+        if (!Stride->isLoopInvariant(L))
+          continue;
+
         const Type *IVTy = Offset->getType();
         const Type *UseTy = Op->getType();
 
@@ -520,7 +518,7 @@
         // induction variable, still in the canonical induction variable's
         // type, so that all expanded arithmetic is done in the same type.
         SCEVHandle NewAR = SE->getAddRecExpr(SE->getIntegerSCEV(0, LargestType),
-                                           PromotedStride, L);
+                                             PromotedStride, L);
         // Add the PromotedOffset as a separate step, because it may not be
         // loop-invariant.
         NewAR = SE->getAddExpr(NewAR, PromotedOffset);

Propchange: llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll

------------------------------------------------------------------------------
    cvs2svn:cvs-rev = 1.4

Propchange: llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll

------------------------------------------------------------------------------
    svn:eol-style = native

Propchange: llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll

------------------------------------------------------------------------------
    svn:keywords = Author Date Id Revision

Propchange: llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll

------------------------------------------------------------------------------
    svn:mergeinfo = 

Added: llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-1.ll?rev=72798&view=auto

==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-1.ll (added)
+++ llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-1.ll Wed Jun  3 14:11:31 2009
@@ -0,0 +1,43 @@
+; RUN: llvm-as < %s | opt -indvars
+; PR4315
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "x86_64-undermydesk-freebsd8.0"
+	%struct.mbuf = type <{ %struct.mbuf*, i8*, i32, i8, i8, i8, i8 }>
+
+define i32 @crash(%struct.mbuf* %m) nounwind {
+entry:
+	br label %for.cond
+
+for.cond:		; preds = %if.end, %entry
+	%i.0 = phi i32 [ 0, %entry ], [ %inc, %if.end ]		;  [#uses=3]
+	%chksum.0 = phi i8 [ 0, %entry ], [ %conv3, %if.end ]		;  [#uses=3]
+	%cmp = icmp slt i32 %i.0, 1		;  [#uses=1]
+	br i1 %cmp, label %for.body, label %do.body
+
+for.body:		; preds = %for.cond
+	br i1 undef, label %if.end, label %do.body
+
+if.end:		; preds = %for.body
+	%i.02 = trunc i32 %i.0 to i8		;  [#uses=1]
+	%conv3 = add i8 %chksum.0, %i.02		;  [#uses=1]
+	%inc = add i32 %i.0, 1		;  [#uses=1]
+	br label %for.cond
+
+do.body:		; preds = %do.cond, %for.body, %for.cond
+	%chksum.2 = phi i8 [ undef, %do.cond ], [ %chksum.0, %for.body ], [ %chksum.0, %for.cond ]		;  [#uses=1]
+	br i1 undef, label %do.cond, label %bb.nph
+
+bb.nph:		; preds = %do.body
+	br label %while.body
+
+while.body:		; preds = %while.body, %bb.nph
+	%chksum.13 = phi i8 [ undef, %while.body ], [ %chksum.2, %bb.nph ]		;  [#uses=0]
+	br i1 undef, label %do.cond, label %while.body
+
+do.cond:		; preds = %while.body, %do.body
+	br i1 false, label %do.end, label %do.body
+
+do.end:		; preds = %do.cond
+	ret i32 0
+}

Removed: llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs.ll?rev=72797&view=auto

==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs.ll (original)
+++ llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs.ll (removed)
@@ -1,43 +0,0 @@
-; RUN: llvm-as < %s | opt -indvars -instcombine | llvm-dis | \
-; RUN:   grep {store i32 0}
-; Test that -indvars can reduce variable stride IVs.  If it can reduce variable
-; stride iv's, it will make %iv. and %m.0.0 isomorphic to each other without 
-; cycles, allowing the tmp.21 subtraction to be eliminated.
-; END.
-
-define void @vnum_test8(i32* %data) {
-entry:
-        %tmp.1 = getelementptr i32* %data, i32 3                ;  [#uses=1]
-        %tmp.2 = load i32* %tmp.1               ;  [#uses=2]
-        %tmp.4 = getelementptr i32* %data, i32 4                ;  [#uses=1]
-        %tmp.5 = load i32* %tmp.4               ;  [#uses=2]
-        %tmp.8 = getelementptr i32* %data, i32 2                ;  [#uses=1]
-        %tmp.9 = load i32* %tmp.8               ;  [#uses=3]
-        %tmp.125 = icmp sgt i32 %tmp.2, 0               ;  [#uses=1]
-        br i1 %tmp.125, label %no_exit.preheader, label %return
-
-no_exit.preheader:              ; preds = %entry
-        %tmp.16 = getelementptr i32* %data, i32 %tmp.9          ;  [#uses=1]
-        br label %no_exit
-
-no_exit:                ; preds = %no_exit, %no_exit.preheader
-        %iv.ui = phi i32 [ 0, %no_exit.preheader ], [ %iv..inc.ui, %no_exit ]           ;  [#uses=1]
-        %iv. = phi i32 [ %tmp.5, %no_exit.preheader ], [ %iv..inc, %no_exit ]           ;  [#uses=2]
-        %m.0.0 = phi i32 [ %tmp.5, %no_exit.preheader ], [ %tmp.24, %no_exit ]          ;  [#uses=2]
-        store i32 2, i32* %tmp.16
-        %tmp.21 = sub i32 %m.0.0, %iv.          ;  [#uses=1]
-        store i32 %tmp.21, i32* %data
-        %tmp.24 = add i32 %m.0.0, %tmp.9                ;  [#uses=1]
-        %iv..inc = add i32 %tmp.9, %iv.         ;  [#uses=1]
-        %iv..inc.ui = add i32 %iv.ui, 1         ;  [#uses=2]
-        %iv..inc1 = bitcast i32 %iv..inc.ui to i32              ;  [#uses=1]
-        %tmp.12 = icmp slt i32 %iv..inc1, %tmp.2                ;  [#uses=1]
-        br i1 %tmp.12, label %no_exit, label %return.loopexit
-
-return.loopexit:                ; preds = %no_exit
-        br label %return
-
-return:         ; preds = %return.loopexit, %entry
-        ret void
-}
-




From daniel at zuster.org  Wed Jun  3 14:19:12 2009
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 03 Jun 2009 19:19:12 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r72800 -
	/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Message-ID: <200906031919.n53JJCue024487@zion.cs.uiuc.edu>

Author: ddunbar
Date: Wed Jun  3 14:19:08 2009
New Revision: 72800

URL: http://llvm.org/viewvc/llvm-project?rev=72800&view=rev
Log:
(llvm up) Switch to using StandardPasses.h
 - No functionality change.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=72800&r1=72799&r2=72800&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Jun  3 14:19:08 2009
@@ -45,9 +45,10 @@
 #include "llvm/Transforms/IPO.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
-#include "llvm/Support/Streams.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Support/StandardPasses.h"
+#include "llvm/Support/Streams.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/System/Program.h"
 #include 
@@ -653,74 +654,11 @@
     }
 
     HasPerModulePasses = true;
-    PassManager *PM = PerModulePasses;
-    if (optimize == 0) {
-      if (InliningPass)
-        PM->add(InliningPass);
-    } else {
-      if (flag_unit_at_a_time)
-        PM->add(createRaiseAllocationsPass());    // call %malloc -> malloc inst
-      PM->add(createCFGSimplificationPass());     // Clean up disgusting code
-      PM->add(createPromoteMemoryToRegisterPass()); // Kill useless allocas
-      if (flag_unit_at_a_time) {
-        PM->add(createGlobalOptimizerPass());     // Optimize out global vars
-        PM->add(createGlobalDCEPass());           // Remove unused fns and globs
-        PM->add(createIPConstantPropagationPass()); // IP Constant Propagation
-        PM->add(createDeadArgEliminationPass());  // Dead argument elimination
-      }
-      PM->add(createInstructionCombiningPass());  // Clean up after IPCP & DAE
-      PM->add(createCFGSimplificationPass());     // Clean up after IPCP & DAE
-      if (flag_unit_at_a_time) {
-        if (flag_exceptions)
-          PM->add(createPruneEHPass());           // Remove dead EH info
-        PM->add(createFunctionAttrsPass());       // Deduce function attrs
-      }
-      if (InliningPass)
-        PM->add(InliningPass);
-      if (optimize > 2)
-        PM->add(createArgumentPromotionPass());   // Scalarize uninlined fn args
-      if (!flag_no_simplify_libcalls)
-        PM->add(createSimplifyLibCallsPass());    // Library Call Optimizations
-      PM->add(createInstructionCombiningPass());  // Cleanup for scalarrepl.
-      PM->add(createJumpThreadingPass());         // Thread jumps.
-      PM->add(createCFGSimplificationPass());     // Merge & remove BBs
-      PM->add(createScalarReplAggregatesPass());  // Break up aggregate allocas
-      PM->add(createInstructionCombiningPass());  // Combine silly seq's
-      PM->add(createCondPropagationPass());       // Propagate conditionals
-      PM->add(createTailCallEliminationPass());   // Eliminate tail calls
-      PM->add(createCFGSimplificationPass());     // Merge & remove BBs
-      PM->add(createReassociatePass());           // Reassociate expressions
-      PM->add(createLoopRotatePass());            // Rotate Loop
-      PM->add(createLICMPass());                  // Hoist loop invariants
-      // At -O2, loop unswitch should not increase code size.
-      PM->add(createLoopUnswitchPass(optimize_size || optimize < 3));
-      PM->add(createLoopIndexSplitPass());        // Split loop index
-      PM->add(createInstructionCombiningPass());  
-      PM->add(createIndVarSimplifyPass());        // Canonicalize indvars
-      PM->add(createLoopDeletionPass());          // Delete dead loops
-      if (flag_unroll_loops)
-        PM->add(createLoopUnrollPass());          // Unroll small loops
-      PM->add(createInstructionCombiningPass());  // Clean up after the unroller
-      PM->add(createGVNPass());                   // Remove redundancies
-      PM->add(createMemCpyOptPass());             // Remove memcpy / form memset
-      PM->add(createSCCPPass());                  // Constant prop with SCCP
-    
-      // Run instcombine after redundancy elimination to exploit opportunities
-      // opened up by them.
-      PM->add(createInstructionCombiningPass());
-      PM->add(createCondPropagationPass());       // Propagate conditionals
-      PM->add(createDeadStoreEliminationPass());  // Delete dead stores
-      PM->add(createAggressiveDCEPass());         // Delete dead instructions
-      PM->add(createCFGSimplificationPass());     // Merge & remove BBs
-
-      if (flag_unit_at_a_time) {
-        PM->add(createStripDeadPrototypesPass()); // Get rid of dead prototypes
-        PM->add(createDeadTypeEliminationPass()); // Eliminate dead types
-      }
-
-      if (optimize > 1 && flag_unit_at_a_time)
-        PM->add(createConstantMergePass());       // Merge dup global constants 
-    }
+    createStandardModulePasses(PerModulePasses, optimize,
+                               optimize_size || optimize < 3,
+                               flag_unit_at_a_time, flag_unroll_loops,
+                               !flag_no_simplify_libcalls, flag_exceptions,
+                               InliningPass);
   }
 
   if (emit_llvm_bc) {




From aaronngray.lists at googlemail.com  Wed Jun  3 14:37:39 2009
From: aaronngray.lists at googlemail.com (Aaron Gray)
Date: Wed, 3 Jun 2009 20:37:39 +0100
Subject: [llvm-commits] [llvm] r72650 - in
	/llvm/trunk:include/llvm/CodeGen/JITCodeEmitter.hinclude/llvm/CodeGen/MachineCodeEmitter.hinclude/llvm/ExecutionEngine/JITMemoryManager.hlib/CodeGen/MachOWriter.cpp
	lib/CodeGen/MachOWriter.hlib/ExecutionEngi
References: <275e64e40906030958x5061eaf4l8854d665a3a8eb3d@mail.gmail.com>
Message-ID: 

Julien Lerouge,

I am about to attempt to reproduce the problem on an XP MinGW machine. But 
am unsure how you got dejaGNU and expect to work on MinGW. Did you compile 
them from source or are binaries availiable ?

BTW The patch did pass on Linux with no regressions.

Many thanks in advance,

Aaron

----- Original Message ----- 
From: "Bruno Cardoso Lopes" 
To: "Julien Lerouge" ; "Commit Messages and Patches for 
LLVM" 
Sent: Wednesday, June 03, 2009 5:58 PM
Subject: Re: [llvm-commits] [llvm] r72650 - in 
/llvm/trunk:include/llvm/CodeGen/JITCodeEmitter.hinclude/llvm/CodeGen/MachineCodeEmitter.hinclude/llvm/ExecutionEngine/JITMemoryManager.hlib/CodeGen/MachOWriter.cpp 
lib/CodeGen/MachOWriter.hlib/ExecutionEngi


> Hi Julien,
>
>> Hello Bruno,
>>
>> I have a buildbot running some nightly tests here on MingW that started
>> to complain somewhere between r72618 and r72690.
>>
>> Some of the tests we are running with lli are triggering the following
>> assertion:
>> Assertion failed: Addr && "Code generation didn't add function to
>> GlobalAddress table!", file
>> c:/cygwin/home/jlerouge/buildbot/llvm-src/lib/ExecutionEngine/JIT/JIT.cpp,
>> line 603
>>
>> I realize this is very vague, but maybe you have any idea where that
>> could be coming from ? Those tests have been pretty stable for the last
>> couple month. I'll take a closer look in the coming days, but in the
>> meantime, I thought I'd give a heads up ;-)
>
> Could you provide me a test case so I can go further? I reverted 72650 for 
> now.
> Thanks,
>
> -- 
> Bruno Cardoso Lopes
> http://www.brunocardoso.cc
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits 



From gohman at apple.com  Wed Jun  3 15:20:04 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 03 Jun 2009 20:20:04 -0000
Subject: [llvm-commits] [llvm] r72801 -
	/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Message-ID: <200906032020.n53KK405026794@zion.cs.uiuc.edu>

Author: djg
Date: Wed Jun  3 15:20:00 2009
New Revision: 72801

URL: http://llvm.org/viewvc/llvm-project?rev=72801&view=rev
Log:
Remove the redundant TM member from X86DAGToDAGISel; replace it
with an accessor method which simply casts the parent class
SelectionDAGISel's TM to the target-specific type.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=72801&r1=72800&r2=72801&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Jun  3 15:20:00 2009
@@ -113,10 +113,6 @@
   /// SelectionDAG operations.
   ///
   class VISIBILITY_HIDDEN X86DAGToDAGISel : public SelectionDAGISel {
-    /// TM - Keep a reference to X86TargetMachine.
-    ///
-    X86TargetMachine &TM;
-
     /// X86Lowering - This object fully describes how to lower LLVM code to an
     /// X86-specific SelectionDAG.
     X86TargetLowering &X86Lowering;
@@ -136,8 +132,8 @@
   public:
     explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
       : SelectionDAGISel(tm, OptLevel),
-        TM(tm), X86Lowering(*TM.getTargetLowering()),
-        Subtarget(&TM.getSubtarget()),
+        X86Lowering(*tm.getTargetLowering()),
+        Subtarget(&tm.getSubtarget()),
         OptForSize(false) {}
 
     virtual const char *getPassName() const {
@@ -243,6 +239,18 @@
     ///
     SDNode *getGlobalBaseReg();
 
+    /// getTargetMachine - Return a reference to the TargetMachine, casted
+    /// to the target-specific type.
+    const X86TargetMachine &getTargetMachine() {
+      return static_cast(TM);
+    }
+
+    /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
+    /// to the target-specific type.
+    const X86InstrInfo *getInstrInfo() {
+      return getTargetMachine().getInstrInfo();
+    }
+
 #ifndef NDEBUG
     unsigned Indent;
 #endif
@@ -674,6 +682,8 @@
 }
 
 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
+  bool SymbolicAddressesAreRIPRel =
+    getTargetMachine().symbolicAddressesAreRIPRel();
   bool is64Bit = Subtarget->is64Bit();
   DOUT << "Wrapper: 64bit " << is64Bit;
   DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
@@ -684,7 +694,7 @@
 
   // Base and index reg must be 0 in order to use rip as base.
   bool canUsePICRel = !AM.Base.Reg.getNode() && !AM.IndexReg.getNode();
-  if (is64Bit && !canUsePICRel && TM.symbolicAddressesAreRIPRel())
+  if (is64Bit && !canUsePICRel && SymbolicAddressesAreRIPRel)
     return true;
 
   if (AM.hasSymbolicDisplacement())
@@ -698,7 +708,7 @@
     uint64_t Offset = G->getOffset();
     if (!is64Bit || isInt32(AM.Disp + Offset)) {
       GlobalValue *GV = G->getGlobal();
-      bool isRIPRel = TM.symbolicAddressesAreRIPRel();
+      bool isRIPRel = SymbolicAddressesAreRIPRel;
       if (N0.getOpcode() == llvm::ISD::TargetGlobalTLSAddress) {
         TLSModel::Model model =
           getTLSModel (GV, TM.getRelocationModel());
@@ -716,16 +726,16 @@
       AM.CP = CP->getConstVal();
       AM.Align = CP->getAlignment();
       AM.Disp += Offset;
-      AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
+      AM.isRIPRel = SymbolicAddressesAreRIPRel;
       return false;
     }
   } else if (ExternalSymbolSDNode *S =dyn_cast(N0)) {
     AM.ES = S->getSymbol();
-    AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
+    AM.isRIPRel = SymbolicAddressesAreRIPRel;
     return false;
   } else if (JumpTableSDNode *J = dyn_cast(N0)) {
     AM.JT = J->getIndex();
-    AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
+    AM.isRIPRel = SymbolicAddressesAreRIPRel;
     return false;
   }
 
@@ -1300,7 +1310,7 @@
 ///
 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
   MachineFunction *MF = CurBB->getParent();
-  unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
+  unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
   return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
 }
 




From gohman at apple.com  Wed Jun  3 15:30:15 2009
From: gohman at apple.com (Dan Gohman)
Date: Wed, 03 Jun 2009 20:30:15 -0000
Subject: [llvm-commits] [llvm] r72802 - in /llvm/trunk/lib/Target:
 Alpha/AlphaISelDAGToDAG.cpp Alpha/AlphaISelLowering.cpp
 Alpha/AlphaInstrInfo.cpp Alpha/AlphaInstrInfo.h
 Alpha/AlphaMachineFunctionInfo.h Mips/MipsISelDAGToDAG.cpp
 Mips/MipsISelLowering.cpp Mips/MipsInstrInfo.cpp Mips/MipsInstrInfo.h
 Mips/MipsMachineFunction.h
Message-ID: <200906032030.n53KUFBE027291@zion.cs.uiuc.edu>

Author: djg
Date: Wed Jun  3 15:30:14 2009
New Revision: 72802

URL: http://llvm.org/viewvc/llvm-project?rev=72802&view=rev
Log:
Convert Alpha and Mips to use a MachineFunctionInfo subclass to
carry GlobalBaseReg, and GlobalRetAddr too in Alpha's case. This
eliminates the need for them to search through the
MachineRegisterInfo livein list in order to identify these
virtual registers. EmitLiveInCopies is now the only user of the
virtual register portion of MachineRegisterInfo's livein data.

Added:
    llvm/trunk/lib/Target/Alpha/AlphaMachineFunctionInfo.h
Modified:
    llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
    llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
    llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h
    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
    llvm/trunk/lib/Target/Mips/MipsMachineFunction.h

Modified: llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=72802&r1=72801&r2=72802&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Wed Jun  3 15:30:14 2009
@@ -185,8 +185,20 @@
 #include "AlphaGenDAGISel.inc"
     
 private:
-    SDValue getGlobalBaseReg();
-    SDValue getGlobalRetAddr();
+    /// getTargetMachine - Return a reference to the TargetMachine, casted
+    /// to the target-specific type.
+    const AlphaTargetMachine &getTargetMachine() {
+      return static_cast(TM);
+    }
+
+    /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
+    /// to the target-specific type.
+    const AlphaInstrInfo *getInstrInfo() {
+      return getTargetMachine().getInstrInfo();
+    }
+
+    SDNode *getGlobalBaseReg();
+    SDNode *getGlobalRetAddr();
     void SelectCALL(SDValue Op);
 
   };
@@ -195,34 +207,18 @@
 /// getGlobalBaseReg - Output the instructions required to put the
 /// GOT address into a register.
 ///
-SDValue AlphaDAGToDAGISel::getGlobalBaseReg() {
-  unsigned GP = 0;
-  for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), 
-        ee = RegInfo->livein_end(); ii != ee; ++ii)
-    if (ii->first == Alpha::R29) {
-      GP = ii->second;
-      break;
-    }
-  assert(GP && "GOT PTR not in liveins");
-  // FIXME is there anywhere sensible to get a DebugLoc here?
-  return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), 
-                                DebugLoc::getUnknownLoc(), GP, MVT::i64);
+SDNode *AlphaDAGToDAGISel::getGlobalBaseReg() {
+  MachineFunction *MF = BB->getParent();
+  unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
+  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
 }
 
-/// getRASaveReg - Grab the return address
+/// getGlobalRetAddr - Grab the return address.
 ///
-SDValue AlphaDAGToDAGISel::getGlobalRetAddr() {
-  unsigned RA = 0;
-  for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), 
-        ee = RegInfo->livein_end(); ii != ee; ++ii)
-    if (ii->first == Alpha::R26) {
-      RA = ii->second;
-      break;
-    }
-  assert(RA && "RA PTR not in liveins");
-  // FIXME is there anywhere sensible to get a DebugLoc here?
-  return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
-                               DebugLoc::getUnknownLoc(), RA, MVT::i64);
+SDNode *AlphaDAGToDAGISel::getGlobalRetAddr() {
+  MachineFunction *MF = BB->getParent();
+  unsigned GlobalRetAddr = getInstrInfo()->getGlobalRetAddr(MF);
+  return CurDAG->getRegister(GlobalRetAddr, TLI.getPointerTy()).getNode();
 }
 
 /// InstructionSelect - This callback is invoked by
@@ -256,16 +252,10 @@
                                 CurDAG->getTargetFrameIndex(FI, MVT::i32),
                                 getI64Imm(0));
   }
-  case ISD::GLOBAL_OFFSET_TABLE: {
-    SDValue Result = getGlobalBaseReg();
-    ReplaceUses(Op, Result);
-    return NULL;
-  }
-  case AlphaISD::GlobalRetAddr: {
-    SDValue Result = getGlobalRetAddr();
-    ReplaceUses(Op, Result);
-    return NULL;
-  }
+  case ISD::GLOBAL_OFFSET_TABLE:
+    return getGlobalBaseReg();
+  case AlphaISD::GlobalRetAddr:
+    return getGlobalRetAddr();
   
   case AlphaISD::DivCall: {
     SDValue Chain = CurDAG->getEntryNode();
@@ -315,7 +305,7 @@
     ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
     SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
     SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, MVT::i64, CPI,
-                                        getGlobalBaseReg());
+                                        SDValue(getGlobalBaseReg(), 0));
     return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, 
                                 CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
   }
@@ -503,7 +493,7 @@
    // Finally, once everything is in registers to pass to the call, emit the
    // call itself.
    if (Addr.getOpcode() == AlphaISD::GPRelLo) {
-     SDValue GOT = getGlobalBaseReg();
+     SDValue GOT = SDValue(getGlobalBaseReg(), 0);
      Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
      InFlag = Chain.getValue(1);
      Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, MVT::Other, 

Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=72802&r1=72801&r2=72802&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jun  3 15:30:14 2009
@@ -223,9 +223,6 @@
   SDValue Root = Op.getOperand(0);
   DebugLoc dl = Op.getDebugLoc();
 
-  AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
-  AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
-
   unsigned args_int[] = {
     Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
   unsigned args_float[] = {

Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=72802&r1=72801&r2=72802&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Wed Jun  3 15:30:14 2009
@@ -13,7 +13,9 @@
 
 #include "Alpha.h"
 #include "AlphaInstrInfo.h"
+#include "AlphaMachineFunctionInfo.h"
 #include "AlphaGenInstrInfo.inc"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -448,3 +450,54 @@
   return false;
 }
 
+/// getGlobalBaseReg - Return a virtual register initialized with the
+/// the global base register value. Output instructions required to
+/// initialize the register in the function entry block, if necessary.
+///
+unsigned AlphaInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
+  AlphaMachineFunctionInfo *AlphaFI = MF->getInfo();
+  unsigned GlobalBaseReg = AlphaFI->getGlobalBaseReg();
+  if (GlobalBaseReg != 0)
+    return GlobalBaseReg;
+
+  // Insert the set of GlobalBaseReg into the first MBB of the function
+  MachineBasicBlock &FirstMBB = MF->front();
+  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
+  MachineRegisterInfo &RegInfo = MF->getRegInfo();
+  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
+
+  GlobalBaseReg = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
+  bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Alpha::R29,
+                              &Alpha::GPRCRegClass, &Alpha::GPRCRegClass);
+  assert(Ok && "Couldn't assign to global base register!");
+  RegInfo.addLiveIn(Alpha::R29);
+
+  AlphaFI->setGlobalBaseReg(GlobalBaseReg);
+  return GlobalBaseReg;
+}
+
+/// getGlobalRetAddr - Return a virtual register initialized with the
+/// the global base register value. Output instructions required to
+/// initialize the register in the function entry block, if necessary.
+///
+unsigned AlphaInstrInfo::getGlobalRetAddr(MachineFunction *MF) const {
+  AlphaMachineFunctionInfo *AlphaFI = MF->getInfo();
+  unsigned GlobalRetAddr = AlphaFI->getGlobalRetAddr();
+  if (GlobalRetAddr != 0)
+    return GlobalRetAddr;
+
+  // Insert the set of GlobalRetAddr into the first MBB of the function
+  MachineBasicBlock &FirstMBB = MF->front();
+  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
+  MachineRegisterInfo &RegInfo = MF->getRegInfo();
+  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
+
+  GlobalRetAddr = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
+  bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalRetAddr, Alpha::R26,
+                              &Alpha::GPRCRegClass, &Alpha::GPRCRegClass);
+  assert(Ok && "Couldn't assign to global return address register!");
+  RegInfo.addLiveIn(Alpha::R26);
+
+  AlphaFI->setGlobalRetAddr(GlobalRetAddr);
+  return GlobalRetAddr;
+}

Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=72802&r1=72801&r2=72802&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Wed Jun  3 15:30:14 2009
@@ -90,6 +90,18 @@
                   MachineBasicBlock::iterator MI) const;
   bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
   bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
+
+  /// getGlobalBaseReg - Return a virtual register initialized with the
+  /// the global base register value. Output instructions required to
+  /// initialize the register in the function entry block, if necessary.
+  ///
+  unsigned getGlobalBaseReg(MachineFunction *MF) const;
+
+  /// getGlobalRetAddr - Return a virtual register initialized with the
+  /// the global return address register value. Output instructions required to
+  /// initialize the register in the function entry block, if necessary.
+  ///
+  unsigned getGlobalRetAddr(MachineFunction *MF) const;
 };
 
 }

Added: llvm/trunk/lib/Target/Alpha/AlphaMachineFunctionInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaMachineFunctionInfo.h?rev=72802&view=auto

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaMachineFunctionInfo.h (added)
+++ llvm/trunk/lib/Target/Alpha/AlphaMachineFunctionInfo.h Wed Jun  3 15:30:14 2009
@@ -0,0 +1,48 @@
+//====- AlphaMachineFuctionInfo.h - Alpha machine function info -*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares Alpha-specific per-machine-function information.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef ALPHAMACHINEFUNCTIONINFO_H
+#define ALPHAMACHINEFUNCTIONINFO_H
+
+#include "llvm/CodeGen/MachineFunction.h"
+
+namespace llvm {
+
+/// AlphaMachineFunctionInfo - This class is derived from MachineFunction
+/// private Alpha target-specific information for each MachineFunction.
+class AlphaMachineFunctionInfo : public MachineFunctionInfo {
+  /// GlobalBaseReg - keeps track of the virtual register initialized for
+  /// use as the global base register. This is used for PIC in some PIC
+  /// relocation models.
+  unsigned GlobalBaseReg;
+
+  /// GlobalRetAddr = keeps track of the virtual register initialized for
+  /// the return address value.
+  unsigned GlobalRetAddr;
+
+public:
+  AlphaMachineFunctionInfo() : GlobalBaseReg(0), GlobalRetAddr(0) {}
+
+  AlphaMachineFunctionInfo(MachineFunction &MF) : GlobalBaseReg(0),
+                                                  GlobalRetAddr(0) {}
+
+  unsigned getGlobalBaseReg() const { return GlobalBaseReg; }
+  void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
+
+  unsigned getGlobalRetAddr() const { return GlobalRetAddr; }
+  void setGlobalRetAddr(unsigned Reg) { GlobalRetAddr = Reg; }
+};
+
+} // End llvm namespace
+
+#endif

Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=72802&r1=72801&r2=72802&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Wed Jun  3 15:30:14 2009
@@ -70,7 +70,19 @@
   // Include the pieces autogenerated from the target description.
   #include "MipsGenDAGISel.inc"
 
-  SDValue getGlobalBaseReg();
+  /// getTargetMachine - Return a reference to the TargetMachine, casted
+  /// to the target-specific type.
+  const MipsTargetMachine &getTargetMachine() {
+    return static_cast(TM);
+  }
+
+  /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
+  /// to the target-specific type.
+  const MipsInstrInfo *getInstrInfo() {
+    return getTargetMachine().getInstrInfo();
+  }
+
+  SDNode *getGlobalBaseReg();
   SDNode *Select(SDValue N);
 
   // Complex Pattern.
@@ -116,19 +128,10 @@
 
 /// getGlobalBaseReg - Output the instructions required to put the
 /// GOT address into a register.
-SDValue MipsDAGToDAGISel::getGlobalBaseReg() {
-  MachineFunction* MF = BB->getParent();
-  unsigned GP = 0;
-  for(MachineRegisterInfo::livein_iterator ii = MF->getRegInfo().livein_begin(),
-        ee = MF->getRegInfo().livein_end(); ii != ee; ++ii)
-    if (ii->first == Mips::GP) {
-      GP = ii->second;
-      break;
-    }
-  assert(GP && "GOT PTR not in liveins");
-  // FIXME is there a sensible place to get debug info for this?
-  return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), 
-                                DebugLoc::getUnknownLoc(), GP, MVT::i32);
+SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
+  MachineFunction *MF = BB->getParent();
+  unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
+  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
 }
 
 /// ComplexPattern used on MipsInstrInfo
@@ -321,11 +324,8 @@
     }
 
     // Get target GOT address.
-    case ISD::GLOBAL_OFFSET_TABLE: {
-      SDValue Result = getGlobalBaseReg();
-      ReplaceUses(N, Result);
-      return NULL;
-    }
+    case ISD::GLOBAL_OFFSET_TABLE:
+      return getGlobalBaseReg();
 
     /// Handle direct and indirect calls when using PIC. On PIC, when 
     /// GOT is smaller than about 64k (small code) the GA target is 

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=72802&r1=72801&r2=72802&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Jun  3 15:30:14 2009
@@ -941,9 +941,6 @@
 
   unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
 
-  // GP must be live into PIC and non-PIC call target.
-  AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
-
   // Assign locations to all of the incoming arguments.
   SmallVector ArgLocs;
   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=72802&r1=72801&r2=72802&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Wed Jun  3 15:30:14 2009
@@ -13,8 +13,10 @@
 
 #include "MipsInstrInfo.h"
 #include "MipsTargetMachine.h"
+#include "MipsMachineFunction.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "MipsGenInstrInfo.inc"
 
 using namespace llvm;
@@ -621,3 +623,30 @@
   Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
   return false;
 }
+
+/// getGlobalBaseReg - Return a virtual register initialized with the
+/// the global base register value. Output instructions required to
+/// initialize the register in the function entry block, if necessary.
+///
+unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
+  MipsFunctionInfo *MipsFI = MF->getInfo();
+  unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
+  if (GlobalBaseReg != 0)
+    return GlobalBaseReg;
+
+  // Insert the set of GlobalBaseReg into the first MBB of the function
+  MachineBasicBlock &FirstMBB = MF->front();
+  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
+  MachineRegisterInfo &RegInfo = MF->getRegInfo();
+  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
+
+  GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
+  bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP,
+                              Mips::CPURegsRegisterClass,
+                              Mips::CPURegsRegisterClass);
+  assert(Ok && "Couldn't assign to global base register!");
+  RegInfo.addLiveIn(Mips::GP);
+
+  MipsFI->setGlobalBaseReg(GlobalBaseReg);
+  return GlobalBaseReg;
+}

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=72802&r1=72801&r2=72802&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Wed Jun  3 15:30:14 2009
@@ -216,6 +216,12 @@
   /// Insert nop instruction when hazard condition is found
   virtual void insertNoop(MachineBasicBlock &MBB, 
                           MachineBasicBlock::iterator MI) const;
+
+  /// getGlobalBaseReg - Return a virtual register initialized with the
+  /// the global base register value. Output instructions required to
+  /// initialize the register in the function entry block, if necessary.
+  ///
+  unsigned getGlobalBaseReg(MachineFunction *MF) const;
 };
 
 }

Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.h?rev=72802&r1=72801&r2=72802&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMachineFunction.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Wed Jun  3 15:30:14 2009
@@ -75,11 +75,16 @@
   /// holds the virtual register into which the sret argument is passed.
   unsigned SRetReturnReg;
 
+  /// GlobalBaseReg - keeps track of the virtual register initialized for
+  /// use as the global base register. This is used for PIC in some PIC
+  /// relocation models.
+  unsigned GlobalBaseReg;
+
 public:
   MipsFunctionInfo(MachineFunction& MF) 
   : FPStackOffset(0), RAStackOffset(0), CPUTopSavedRegOff(0), 
     FPUTopSavedRegOff(0), GPHolder(-1,-1), HasLoadArgs(false), 
-    HasStoreVarArgs(false), SRetReturnReg(0)
+    HasStoreVarArgs(false), SRetReturnReg(0), GlobalBaseReg(0)
   {}
 
   int getFPStackOffset() const { return FPStackOffset; }
@@ -124,6 +129,9 @@
 
   unsigned getSRetReturnReg() const { return SRetReturnReg; }
   void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
+
+  unsigned getGlobalBaseReg() const { return GlobalBaseReg; }
+  void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
 };
 
 } // end of namespace llvm




From isanbard at gmail.com  Wed Jun  3 15:49:35 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 03 Jun 2009 20:49:35 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r72804 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <200906032049.n53KnZVm027957@zion.cs.uiuc.edu>

Author: void
Date: Wed Jun  3 15:49:35 2009
New Revision: 72804

URL: http://llvm.org/viewvc/llvm-project?rev=72804&view=rev
Log:
Set the alignment of STRING_CSTs to be that which GCC expects it to be. We were
setting it to a default that made the alignment much larger than it needed to
be and wasting space.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=72804&r1=72803&r2=72804&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Jun  3 15:49:35 2009
@@ -7418,6 +7418,10 @@
                                            TAI ? 
                                             TAI->getStringConstantPrefix() : 
                                             ".str", TheModule);
+
+  if (optimize_size)
+    GV->setAlignment(TYPE_ALIGN(TREE_TYPE(exp)) / 8);
+
   if (SlotP) *SlotP = GV;
 #ifdef LLVM_CSTRING_SECTION
   // For Darwin, try to put it into the .cstring section.




From jlerouge at apple.com  Wed Jun  3 15:59:23 2009
From: jlerouge at apple.com (Julien Lerouge)
Date: Wed, 3 Jun 2009 13:59:23 -0700
Subject: [llvm-commits] [llvm] r72650 - in
	/llvm/trunk:	include/llvm/CodeGen/JITCodeEmitter.h	include/llvm/CodeGen/MachineCodeEmitter.h	include/llvm/ExecutionEngine/JITMemoryManager.h	lib/CodeGen/MachOWriter.cpp
	lib/CodeGen/MachOWriter.h	lib/ExecutionEngi
In-Reply-To: <275e64e40906030958x5061eaf4l8854d665a3a8eb3d@mail.gmail.com>
References: <275e64e40906030958x5061eaf4l8854d665a3a8eb3d@mail.gmail.com>
Message-ID: <20090603205923.GC24816@pom.apple.com>

On Wed, Jun 03, 2009 at 01:58:40PM -0300, Bruno Cardoso Lopes wrote:
> Hi Julien,
> 
> Could you provide me a test case so I can go further? I reverted 72650 for now.
> Thanks,
> 

Thanks, but I am not sure it's really coming from 72650. I just wanted
to have your opinion on that matter. I know that 72618 was ok, and that
the problem started to appear in 72690. I will run more tests to find
the revision. My current test case is too big to send, I'll try to
reduce it.


-- 
Julien Lerouge
PGP Key Id: 0xB1964A62
PGP Fingerprint: 392D 4BAD DB8B CE7F 4E5F FA3C 62DB 4AA7 B196 4A62
PGP Public Key from: keyserver.pgp.com


From daniel at zuster.org  Wed Jun  3 16:06:14 2009
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 03 Jun 2009 21:06:14 -0000
Subject: [llvm-commits] [llvm] r72805 - in /llvm/trunk:
 include/llvm/Support/StandardPasses.h tools/llvm-ld/Optimize.cpp
 tools/lto/LTOCodeGenerator.cpp
Message-ID: <200906032106.n53L6FFF028774@zion.cs.uiuc.edu>

Author: ddunbar
Date: Wed Jun  3 16:06:14 2009
New Revision: 72805

URL: http://llvm.org/viewvc/llvm-project?rev=72805&view=rev
Log:
Add createStandardLTOPasses to StandardPasses.h, and move lto and llvm-ld over.
 - I know it sounds crazy, but I think all the pass lists are now coalesced into
   StandardPasses.h.

Modified:
    llvm/trunk/include/llvm/Support/StandardPasses.h
    llvm/trunk/tools/llvm-ld/Optimize.cpp
    llvm/trunk/tools/lto/LTOCodeGenerator.cpp

Modified: llvm/trunk/include/llvm/Support/StandardPasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=72805&r1=72804&r2=72805&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/StandardPasses.h (original)
+++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed Jun  3 16:06:14 2009
@@ -20,6 +20,8 @@
 #define LLVM_SUPPORT_STANDARDPASSES_H
 
 #include "llvm/PassManager.h"
+#include "llvm/Analysis/Passes.h"
+#include "llvm/Analysis/Verifier.h"
 #include "llvm/Transforms/Scalar.h"
 #include "llvm/Transforms/IPO.h"
 
@@ -53,6 +55,22 @@
                                                 bool HaveExceptions,
                                                 Pass *InliningPass);
 
+  /// createStandardLTOPasses - Add the standard list of module passes suitable
+  /// for link time optimization.
+  ///
+  /// Internalize - Run the internalize pass.
+  /// RunInliner - Use a function inlining pass.
+  /// RunSecondGlobalOpt - Run the global optimizer pass twice.
+  /// VerifyEach - Run the verifier after each pass.
+  //
+  // FIXME: RunSecondGlobalOpt should go away once we resolve which of LTO or
+  // llvm-ld is better.
+  static inline void createStandardLTOPasses(PassManager *PM,
+                                             bool Internalize,
+                                             bool RunInliner,
+                                             bool RunSecondGlobalOpt,
+                                             bool VerifyEach);
+
   // Implementations
 
   static inline void createStandardFunctionPasses(FunctionPassManager *PM,
@@ -144,6 +162,89 @@
         PM->add(createConstantMergePass());       // Merge dup global constants
     }
   }
+
+  static inline void addOnePass(PassManager *PM, Pass *P, bool AndVerify) {
+    PM->add(P);
+
+    if (AndVerify)
+      PM->add(createVerifierPass());
+  }
+
+  static inline void createStandardLTOPasses(PassManager *PM,
+                                             bool Internalize,
+                                             bool RunInliner,
+                                             bool RunSecondGlobalOpt,
+                                             bool VerifyEach) {
+    // Now that composite has been compiled, scan through the module, looking
+    // for a main function.  If main is defined, mark all other functions
+    // internal.
+    if (Internalize)
+      addOnePass(PM, createInternalizePass(true), VerifyEach);
+
+    // Propagate constants at call sites into the functions they call.  This
+    // opens opportunities for globalopt (and inlining) by substituting function
+    // pointers passed as arguments to direct uses of functions.  
+    addOnePass(PM, createIPSCCPPass(), VerifyEach);
+
+    // Now that we internalized some globals, see if we can hack on them!
+    addOnePass(PM, createGlobalOptimizerPass(), VerifyEach);
+    
+    // Linking modules together can lead to duplicated global constants, only
+    // keep one copy of each constant...
+    addOnePass(PM, createConstantMergePass(), VerifyEach);
+    
+    // Remove unused arguments from functions...
+    addOnePass(PM, createDeadArgEliminationPass(), VerifyEach);
+
+    // Reduce the code after globalopt and ipsccp.  Both can open up significant
+    // simplification opportunities, and both can propagate functions through
+    // function pointers.  When this happens, we often have to resolve varargs
+    // calls, etc, so let instcombine do this.
+    addOnePass(PM, createInstructionCombiningPass(), VerifyEach);
+
+    // Inline small functions
+    if (RunInliner)
+      addOnePass(PM, createFunctionInliningPass(), VerifyEach);
+
+    addOnePass(PM, createPruneEHPass(), VerifyEach);   // Remove dead EH info.
+    // Optimize globals again.
+    if (RunSecondGlobalOpt)
+      addOnePass(PM, createGlobalOptimizerPass(), VerifyEach);
+    addOnePass(PM, createGlobalDCEPass(), VerifyEach); // Remove dead functions.
+
+    // If we didn't decide to inline a function, check to see if we can
+    // transform it to pass arguments by value instead of by reference.
+    addOnePass(PM, createArgumentPromotionPass(), VerifyEach);
+
+    // The IPO passes may leave cruft around.  Clean up after them.
+    addOnePass(PM, createInstructionCombiningPass(), VerifyEach);
+    addOnePass(PM, createJumpThreadingPass(), VerifyEach);
+    // Break up allocas
+    addOnePass(PM, createScalarReplAggregatesPass(), VerifyEach);
+
+    // Run a few AA driven optimizations here and now, to cleanup the code.
+    addOnePass(PM, createFunctionAttrsPass(), VerifyEach); // Add nocapture.
+    addOnePass(PM, createGlobalsModRefPass(), VerifyEach); // IP alias analysis.
+
+    addOnePass(PM, createLICMPass(), VerifyEach);      // Hoist loop invariants.
+    addOnePass(PM, createGVNPass(), VerifyEach);       // Remove redundancies.
+    addOnePass(PM, createMemCpyOptPass(), VerifyEach); // Remove dead memcpys.
+    // Nuke dead stores.
+    addOnePass(PM, createDeadStoreEliminationPass(), VerifyEach);
+
+    // Cleanup and simplify the code after the scalar optimizations.
+    addOnePass(PM, createInstructionCombiningPass(), VerifyEach);
+
+    addOnePass(PM, createJumpThreadingPass(), VerifyEach);
+    // Cleanup jump threading.
+    addOnePass(PM, createPromoteMemoryToRegisterPass(), VerifyEach);
+    
+    // Delete basic blocks, which optimization passes may have killed...
+    addOnePass(PM, createCFGSimplificationPass(), VerifyEach);
+
+    // Now that we have optimized the program, discard unreachable functions.
+    addOnePass(PM, createGlobalDCEPass(), VerifyEach);
+  }
 }
 
 #endif

Modified: llvm/trunk/tools/llvm-ld/Optimize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ld/Optimize.cpp?rev=72805&r1=72804&r2=72805&view=diff

==============================================================================
--- llvm/trunk/tools/llvm-ld/Optimize.cpp (original)
+++ llvm/trunk/tools/llvm-ld/Optimize.cpp Wed Jun  3 16:06:14 2009
@@ -17,6 +17,7 @@
 #include "llvm/Analysis/LoopPass.h"
 #include "llvm/Analysis/Verifier.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/StandardPasses.h"
 #include "llvm/System/DynamicLibrary.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
@@ -91,71 +92,9 @@
   // Add an appropriate TargetData instance for this module...
   addPass(Passes, new TargetData(M));
 
-  if (!DisableOptimizations) {
-    // Now that composite has been compiled, scan through the module, looking
-    // for a main function.  If main is defined, mark all other functions
-    // internal.
-    if (!DisableInternalize)
-      addPass(Passes, createInternalizePass(true));
-
-    // Propagate constants at call sites into the functions they call.  This
-    // opens opportunities for globalopt (and inlining) by substituting function
-    // pointers passed as arguments to direct uses of functions.  
-    addPass(Passes, createIPSCCPPass());
-
-    // Now that we internalized some globals, see if we can hack on them!
-    addPass(Passes, createGlobalOptimizerPass());
-
-    // Linking modules together can lead to duplicated global constants, only
-    // keep one copy of each constant...
-    addPass(Passes, createConstantMergePass());
-
-    // Remove unused arguments from functions...
-    addPass(Passes, createDeadArgEliminationPass());
-
-    // Reduce the code after globalopt and ipsccp.  Both can open up significant
-    // simplification opportunities, and both can propagate functions through
-    // function pointers.  When this happens, we often have to resolve varargs
-    // calls, etc, so let instcombine do this.
-    addPass(Passes, createInstructionCombiningPass());
-
-    if (!DisableInline)
-      addPass(Passes, createFunctionInliningPass()); // Inline small functions
-
-    addPass(Passes, createPruneEHPass());            // Remove dead EH info
-    addPass(Passes, createGlobalOptimizerPass());    // Optimize globals again.
-    addPass(Passes, createGlobalDCEPass());          // Remove dead functions
-
-    // If we didn't decide to inline a function, check to see if we can
-    // transform it to pass arguments by value instead of by reference.
-    addPass(Passes, createArgumentPromotionPass());
-
-    // The IPO passes may leave cruft around.  Clean up after them.
-    addPass(Passes, createInstructionCombiningPass());
-    addPass(Passes, createJumpThreadingPass());        // Thread jumps.
-    addPass(Passes, createScalarReplAggregatesPass()); // Break up allocas
-
-    // Run a few AA driven optimizations here and now, to cleanup the code.
-    addPass(Passes, createFunctionAttrsPass());      // Add nocapture
-    addPass(Passes, createGlobalsModRefPass());      // IP alias analysis
-
-    addPass(Passes, createLICMPass());               // Hoist loop invariants
-    addPass(Passes, createGVNPass());                // Remove redundancies
-    addPass(Passes, createMemCpyOptPass());          // Remove dead memcpy's
-    addPass(Passes, createDeadStoreEliminationPass()); // Nuke dead stores
-
-    // Cleanup and simplify the code after the scalar optimizations.
-    addPass(Passes, createInstructionCombiningPass());
-
-    addPass(Passes, createJumpThreadingPass());        // Thread jumps.
-    addPass(Passes, createPromoteMemoryToRegisterPass()); // Cleanup jumpthread.
-    
-    // Delete basic blocks, which optimization passes may have killed...
-    addPass(Passes, createCFGSimplificationPass());
-
-    // Now that we have optimized the program, discard unreachable functions...
-    addPass(Passes, createGlobalDCEPass());
-  }
+  if (!DisableOptimizations)
+    createStandardLTOPasses(&Passes, !DisableInternalize, !DisableInline,
+                            /*RunSecondGlobalOpt=*/true, VerifyEach);
 
   // If the -s or -S command line options were specified, strip the symbols out
   // of the resulting program to make it smaller.  -s and -S are GNU ld options

Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=72805&r1=72804&r2=72805&view=diff

==============================================================================
--- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original)
+++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Jun  3 16:06:14 2009
@@ -24,9 +24,10 @@
 #include "llvm/ModuleProvider.h"
 #include "llvm/Bitcode/ReaderWriter.h"
 #include "llvm/Support/CommandLine.h"
-#include "llvm/Support/SystemUtils.h"
 #include "llvm/Support/Mangler.h"
 #include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Support/StandardPasses.h"
+#include "llvm/Support/SystemUtils.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/System/Signals.h"
 #include "llvm/Analysis/Passes.h"
@@ -389,59 +390,9 @@
     // Add an appropriate TargetData instance for this module...
     passes.add(new TargetData(*_target->getTargetData()));
     
-    // Propagate constants at call sites into the functions they call.  This
-    // opens opportunities for globalopt (and inlining) by substituting function
-    // pointers passed as arguments to direct uses of functions.  
-    passes.add(createIPSCCPPass());
-
-    // Now that we internalized some globals, see if we can hack on them!
-    passes.add(createGlobalOptimizerPass());
-
-    // Linking modules together can lead to duplicated global constants, only
-    // keep one copy of each constant...
-    passes.add(createConstantMergePass());
-
-    // Remove unused arguments from functions...
-    passes.add(createDeadArgEliminationPass());
-
-    // Reduce the code after globalopt and ipsccp.  Both can open up significant
-    // simplification opportunities, and both can propagate functions through
-    // function pointers.  When this happens, we often have to resolve varargs
-    // calls, etc, so let instcombine do this.
-    passes.add(createInstructionCombiningPass());
-    if (!DisableInline)
-        passes.add(createFunctionInliningPass()); // Inline small functions
-    passes.add(createPruneEHPass());              // Remove dead EH info
-    passes.add(createGlobalDCEPass());            // Remove dead functions
-
-    // If we didn't decide to inline a function, check to see if we can
-    // transform it to pass arguments by value instead of by reference.
-    passes.add(createArgumentPromotionPass());
-
-    // The IPO passes may leave cruft around.  Clean up after them.
-    passes.add(createInstructionCombiningPass());
-    passes.add(createJumpThreadingPass());        // Thread jumps.
-    passes.add(createScalarReplAggregatesPass()); // Break up allocas
-
-    // Run a few AA driven optimizations here and now, to cleanup the code.
-    passes.add(createFunctionAttrsPass());        // Add nocapture
-    passes.add(createGlobalsModRefPass());        // IP alias analysis
-    passes.add(createLICMPass());                 // Hoist loop invariants
-    passes.add(createGVNPass());                  // Remove common subexprs
-    passes.add(createMemCpyOptPass());            // Remove dead memcpy's
-    passes.add(createDeadStoreEliminationPass()); // Nuke dead stores
-
-    // Cleanup and simplify the code after the scalar optimizations.
-    passes.add(createInstructionCombiningPass());
-    passes.add(createJumpThreadingPass());        // Thread jumps.
-    passes.add(createPromoteMemoryToRegisterPass()); // Cleanup after threading.
-
-
-    // Delete basic blocks, which optimization passes may have killed...
-    passes.add(createCFGSimplificationPass());
-
-    // Now that we have optimized the program, discard unreachable functions...
-    passes.add(createGlobalDCEPass());
+    createStandardLTOPasses(&passes, /*Internalize=*/ false, !DisableInline,
+                            /*RunSecondGlobalOpt=*/ false, 
+                            /*VerifyEach=*/ false);
 
     // Make sure everything is still good.
     passes.add(createVerifierPass());




From bruno.cardoso at gmail.com  Wed Jun  3 16:09:21 2009
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 3 Jun 2009 18:09:21 -0300
Subject: [llvm-commits] [llvm] r72650 - in /llvm/trunk:
	include/llvm/CodeGen/JITCodeEmitter.h
	include/llvm/CodeGen/MachineCodeEmitter.h
	include/llvm/ExecutionEngine/JITMemoryManager.h
	lib/CodeGen/MachOWriter.cpp lib/CodeGen/MachOWriter.h
	lib/ExecutionEngi
In-Reply-To: <20090603205923.GC24816@pom.apple.com>
References: <275e64e40906030958x5061eaf4l8854d665a3a8eb3d@mail.gmail.com>
	<20090603205923.GC24816@pom.apple.com>
Message-ID: <275e64e40906031409p533a8afbma5d8a4bdc38dcfc@mail.gmail.com>

> Thanks, but I am not sure it's really coming from 72650. I just wanted
> to have your opinion on that matter. I know that 72618 was ok, and that
> the problem started to appear in 72690. I will run more tests to find
> the revision. My current test case is too big to send, I'll try to
> reduce it.

No problem, 72650 is simple enough to be commited again if it's not
causing any trouble. Since I don't have any idea of what's causing the
regression,
I decided to revert it. I'll wait for a reduced test case then.

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From evan.cheng at apple.com  Wed Jun  3 16:13:54 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 03 Jun 2009 21:13:54 -0000
Subject: [llvm-commits] [llvm] r72806 - in /llvm/trunk:
 lib/Target/X86/X86TargetMachine.cpp
 test/CodeGen/X86/2009-03-23-MultiUseSched.ll test/CodeGen/X86/abi-isel.ll
 test/CodeGen/X86/ga-offset.ll test/CodeGen/X86/remat-constant.ll
Message-ID: <200906032113.n53LDsnd029026@zion.cs.uiuc.edu>

Author: evancheng
Date: Wed Jun  3 16:13:54 2009
New Revision: 72806

URL: http://llvm.org/viewvc/llvm-project?rev=72806&view=rev
Log:
For Darwin / x86_64, override -relocation-model=static to pic if the output is assembly since Darwin assembler does not really support -static codeine.

I view this as a temporary workaround until the assembler / linker changes.

Modified:
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
    llvm/trunk/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
    llvm/trunk/test/CodeGen/X86/abi-isel.ll
    llvm/trunk/test/CodeGen/X86/ga-offset.ll
    llvm/trunk/test/CodeGen/X86/remat-constant.ll

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=72806&r1=72805&r2=72806&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Wed Jun  3 16:13:54 2009
@@ -213,6 +213,13 @@
                                           CodeGenOpt::Level OptLevel,
                                           bool Verbose,
                                           raw_ostream &Out) {
+  // FIXME: Move this somewhere else!
+  // On Darwin, override 64-bit static relocation to pic_ since the
+  // assembler doesn't support it.
+  if (DefRelocModel == Reloc::Static &&
+      Subtarget.isTargetDarwin() && Subtarget.is64Bit())
+    setRelocationModel(Reloc::PIC_);
+
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
   if (AsmPrinterCtor)
     PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));

Modified: llvm/trunk/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-23-MultiUseSched.ll?rev=72806&r1=72805&r2=72806&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-03-23-MultiUseSched.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-03-23-MultiUseSched.ll Wed Jun  3 16:13:54 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=static -stats -info-output-file - > %t
+; RUN: llvm-as < %s | llc -mtriple=x86_64-linux -relocation-model=static -stats -info-output-file - > %t
 ; RUN: not grep spill %t
 ; RUN: not grep {%rsp} %t
 ; RUN: not grep {%rbp} %t

Modified: llvm/trunk/test/CodeGen/X86/abi-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/abi-isel.ll?rev=72806&r1=72805&r2=72806&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/abi-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/abi-isel.ll Wed Jun  3 16:13:54 2009
@@ -141,26 +141,6 @@
 ; RUN: not grep @PLTOFF %t
 ; RUN: grep {call	\\\*} %t | count 10
 ; RUN: not grep {%rip} %t
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small > %t
-; RUN: not grep leal %t
-; RUN: grep movl %t | count 91
-; RUN: not grep addl %t
-; RUN: not grep subl %t
-; RUN: grep leaq %t | count 70
-; RUN: grep movq %t | count 56
-; RUN: grep addq %t | count 20
-; RUN: grep subq %t | count 14
-; RUN: not grep movabs %t
-; RUN: not grep largecomm %t
-; RUN: not grep _GLOBAL_OFFSET_TABLE_ %t
-; RUN: not grep @GOT %t
-; RUN: not grep @GOTOFF %t
-; RUN: not grep @GOTPCREL %t
-; RUN: not grep @GOTPLT %t
-; RUN: not grep @PLT %t
-; RUN: not grep @PLTOFF %t
-; RUN: grep {call	\\\*} %t | count 10
-; RUN: grep {%rip} %t | count 139
 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small > %t
 ; RUN: not grep leal %t
 ; RUN: grep movl %t | count 95

Modified: llvm/trunk/test/CodeGen/X86/ga-offset.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ga-offset.ll?rev=72806&r1=72805&r2=72806&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/ga-offset.ll (original)
+++ llvm/trunk/test/CodeGen/X86/ga-offset.ll Wed Jun  3 16:13:54 2009
@@ -2,7 +2,7 @@
 ; RUN: not grep lea %t
 ; RUN: not grep add %t
 ; RUN: grep mov %t | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=static > %t
+; RUN: llvm-as < %s | llc -mtriple=x86_64-linux -relocation-model=static > %t
 ; RUN: not grep lea %t
 ; RUN: not grep add %t
 ; RUN: grep mov %t | count 1

Modified: llvm/trunk/test/CodeGen/X86/remat-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/remat-constant.ll?rev=72806&r1=72805&r2=72806&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/X86/remat-constant.ll (original)
+++ llvm/trunk/test/CodeGen/X86/remat-constant.ll Wed Jun  3 16:13:54 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=static -aggressive-remat | grep xmm | count 2
+; RUN: llvm-as < %s | llc -mtriple=x86_64-linux -relocation-model=static -aggressive-remat | grep xmm | count 2
 
 declare void @bar() nounwind
 




From isanbard at gmail.com  Wed Jun  3 16:18:07 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 03 Jun 2009 21:18:07 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r72807 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <200906032118.n53LI8SH029157@zion.cs.uiuc.edu>

Author: void
Date: Wed Jun  3 16:18:07 2009
New Revision: 72807

URL: http://llvm.org/viewvc/llvm-project?rev=72807&view=rev
Log:
Set the alignment for STRING_CST for all optimization levels.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=72807&r1=72806&r2=72807&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Jun  3 16:18:07 2009
@@ -7419,8 +7419,7 @@
                                             TAI->getStringConstantPrefix() : 
                                             ".str", TheModule);
 
-  if (optimize_size)
-    GV->setAlignment(TYPE_ALIGN(TREE_TYPE(exp)) / 8);
+  GV->setAlignment(TYPE_ALIGN(TREE_TYPE(exp)) / 8);
 
   if (SlotP) *SlotP = GV;
 #ifdef LLVM_CSTRING_SECTION




From aaronngray.lists at googlemail.com  Wed Jun  3 16:32:53 2009
From: aaronngray.lists at googlemail.com (Aaron Gray)
Date: Wed, 3 Jun 2009 22:32:53 +0100
Subject: [llvm-commits] LLVM on MinGW on XP
Message-ID: <9719867c0906031432w2eef1cd3s92ce5c4c9c9948fc@mail.gmail.com>

Hi Anton,

I need your advice please.

Is there anyway to run 'make test' on MinGW ?

It requites dejaGNU and expect, but looking on the web there are only dead
ends to getting them running on MinGW.

Hope you can help,

Aaron
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From stuart at apple.com  Wed Jun  3 16:39:14 2009
From: stuart at apple.com (Stuart Hastings)
Date: Wed, 03 Jun 2009 21:39:14 -0000
Subject: [llvm-commits] [llvm] r72808 -
	/llvm/trunk/lib/Target/X86/X86InstrMMX.td
Message-ID: <200906032139.n53LdES3029887@zion.cs.uiuc.edu>

Author: stuart
Date: Wed Jun  3 16:39:14 2009
New Revision: 72808

URL: http://llvm.org/viewvc/llvm-project?rev=72808&view=rev
Log:
Recognize another euphemism for MOVDQ2Q.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrMMX.td

Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=72808&r1=72807&r2=72808&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Jun  3 16:39:14 2009
@@ -680,6 +680,8 @@
 def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
                                                   (iPTR 0))))),
           (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
+def : Pat<(v2i32 (bitconvert (f64 FR64:$src))),
+          (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
 
 // CMOV* - Used to implement the SELECT DAG operation.  Expanded by the
 // scheduler into a branch sequence.




From eli.friedman at gmail.com  Wed Jun  3 16:42:06 2009
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 03 Jun 2009 21:42:06 -0000
Subject: [llvm-commits] [llvm] r72810 - in /llvm/trunk:
 include/llvm/Analysis/Dominators.h
 test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll
Message-ID: <200906032142.n53Lg6OS030002@zion.cs.uiuc.edu>

Author: efriedma
Date: Wed Jun  3 16:42:06 2009
New Revision: 72810

URL: http://llvm.org/viewvc/llvm-project?rev=72810&view=rev
Log:
PR4317: Handle splits where the new block is unreachable correctly in 
DominatorTreeBase::Split.


Added:
    llvm/trunk/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll
Modified:
    llvm/trunk/include/llvm/Analysis/Dominators.h

Modified: llvm/trunk/include/llvm/Analysis/Dominators.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Dominators.h?rev=72810&r1=72809&r2=72810&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Analysis/Dominators.h (original)
+++ llvm/trunk/include/llvm/Analysis/Dominators.h Wed Jun  3 16:42:06 2009
@@ -270,12 +270,17 @@
         NewBBIDom = PredBlocks[i];
         break;
       }
-    assert(i != PredBlocks.size() && "No reachable preds?");
+
+    // It's possible that none of the predecessors of NewBB are reachable;
+    // in that case, NewBB itself is unreachable, so nothing needs to be
+    // changed.
+    if (!NewBBIDom)
+      return;
+
     for (i = i + 1; i < PredBlocks.size(); ++i) {
       if (DT.isReachableFromEntry(PredBlocks[i]))
         NewBBIDom = DT.findNearestCommonDominator(NewBBIDom, PredBlocks[i]);
     }
-    assert(NewBBIDom && "No immediate dominator found??");
 
     // Create the new dominator tree node... and set the idom of NewBB.
     DomTreeNodeBase *NewBBNode = DT.addNewBlock(NewBB, NewBBIDom);

Added: llvm/trunk/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll?rev=72810&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll (added)
+++ llvm/trunk/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll Wed Jun  3 16:42:06 2009
@@ -0,0 +1,15 @@
+; RUN: llvm-as < %s | llc
+; PR4317
+
+declare i32 @b()
+
+define void @a() {
+entry:
+  ret void
+
+dummy:
+  invoke i32 @b() to label %reg unwind label %reg
+
+reg:
+  ret void
+}




From jlerouge at apple.com  Wed Jun  3 16:44:32 2009
From: jlerouge at apple.com (Julien Lerouge)
Date: Wed, 3 Jun 2009 14:44:32 -0700
Subject: [llvm-commits] [llvm] r72650 -
	in	/llvm/trunk:include/llvm/CodeGen/JITCodeEmitter.hinclude/llvm/CodeGe	n/MachineCodeEmitter.hinclude/llvm/ExecutionEngine/JITMemoryManager.	hlib/CodeGen/MachOWriter.cpp	lib/CodeGen/MachOWriter.hlib/ExecutionEngi
In-Reply-To: 
References: <275e64e40906030958x5061eaf4l8854d665a3a8eb3d@mail.gmail.com>
	
Message-ID: <20090603214431.GD24816@pom.apple.com>

On Wed, Jun 03, 2009 at 08:37:39PM +0100, Aaron Gray wrote:
> Julien Lerouge,
>
> I am about to attempt to reproduce the problem on an XP MinGW machine. But 
> am unsure how you got dejaGNU and expect to work on MinGW. Did you compile 
> them from source or are binaries availiable ?

Hello Aaron,

I am using a gross hack in the test/Makefile to start a cygwin shell when
dejaGNU/expect are about to be called, so it ends up using dejaGNU/expect that
come with cygwin. Doing something like the following:

ifeq ($(LLVM_ON_WIN32), 1)
TestDir      = $(shell pwd -W)
CWPATH      := $(shell echo $(RUNTESTPATH) | sed 's/\/c\//\/cygdrive\/c\//g' | sed 's/c:/\/cygdrive\/c/g' )
RUNTESTCMD   = c:/cygwin/bin/sh.exe -l -c 'cd "$(TestDir)" && \
               export PATH="$$PATH:$(CWPATH)" && \
               export DEJAGNULIBS="/usr/local/share/dejagnu/" && \
               /bin/runtest $(RUNTESTFLAGS) --build=i686-pc-mingw32'
RUNTESTPATH  =
ULIMITCMD    =
RUNTEST      = 1
SITE_EXP     = site.win32.exp
MWINSTALL    = /cygdrive/c/msys/1.0
CC           = $(MWINSTALL)$(shell which gcc)
CXX          = $(MWINSTALL)$(shell which g++)
endif

site.win32.exp is the same as site.exp, but where posix path have been replaced
with windows or cygwin path.

I think there are ways to get a native dejaGNU/expect (google turned up this:
http://www.geocities.com/henrik_bach_llvm/), but it's not as straightforward as
using cygwin IMHO.

Thanks,
Julien

-- 
Julien Lerouge
PGP Key Id: 0xB1964A62
PGP Fingerprint: 392D 4BAD DB8B CE7F 4E5F FA3C 62DB 4AA7 B196 4A62
PGP Public Key from: keyserver.pgp.com


From daniel at zuster.org  Wed Jun  3 16:51:32 2009
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 03 Jun 2009 21:51:32 -0000
Subject: [llvm-commits] [llvm] r72811 - in /llvm/trunk:
 include/llvm/Support/StandardPasses.h tools/llvm-ld/Optimize.cpp
 tools/lto/LTOCodeGenerator.cpp
Message-ID: <200906032151.n53LpWET030337@zion.cs.uiuc.edu>

Author: ddunbar
Date: Wed Jun  3 16:51:32 2009
New Revision: 72811

URL: http://llvm.org/viewvc/llvm-project?rev=72811&view=rev
Log:
Change LTO to run the global opt pass twice.
 - This matches llvm-ld.

It took a bit of archeology to figure out what the right thing to do was
(whether this was intentionally added or intentionally removed). My final
conclusion is that Chris added this intentionally here:
  http://llvm.org/viewvc/llvm-project?view=rev&revision=16913
but the changes weren't propogated to llvm-ld until here:
  http://llvm.org/viewvc/llvm-project?view=rev&revision=34058
which was after lto.cpp had been cloned off (of llvm-ld), here:
  http://llvm.org/viewvc/llvm-project?view=rev&revision=29494

>From the commit message, it looks like the motivation for running global opt
again is because we ran it prior to inlining. Based on that I updated the
comment and also only run the pass if we actually ran the inliner.

Chris, please review.

Modified:
    llvm/trunk/include/llvm/Support/StandardPasses.h
    llvm/trunk/tools/llvm-ld/Optimize.cpp
    llvm/trunk/tools/lto/LTOCodeGenerator.cpp

Modified: llvm/trunk/include/llvm/Support/StandardPasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=72811&r1=72810&r2=72811&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/StandardPasses.h (original)
+++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed Jun  3 16:51:32 2009
@@ -60,15 +60,10 @@
   ///
   /// Internalize - Run the internalize pass.
   /// RunInliner - Use a function inlining pass.
-  /// RunSecondGlobalOpt - Run the global optimizer pass twice.
   /// VerifyEach - Run the verifier after each pass.
-  //
-  // FIXME: RunSecondGlobalOpt should go away once we resolve which of LTO or
-  // llvm-ld is better.
   static inline void createStandardLTOPasses(PassManager *PM,
                                              bool Internalize,
                                              bool RunInliner,
-                                             bool RunSecondGlobalOpt,
                                              bool VerifyEach);
 
   // Implementations
@@ -173,7 +168,6 @@
   static inline void createStandardLTOPasses(PassManager *PM,
                                              bool Internalize,
                                              bool RunInliner,
-                                             bool RunSecondGlobalOpt,
                                              bool VerifyEach) {
     // Now that composite has been compiled, scan through the module, looking
     // for a main function.  If main is defined, mark all other functions
@@ -207,8 +201,8 @@
       addOnePass(PM, createFunctionInliningPass(), VerifyEach);
 
     addOnePass(PM, createPruneEHPass(), VerifyEach);   // Remove dead EH info.
-    // Optimize globals again.
-    if (RunSecondGlobalOpt)
+    // Optimize globals again if we ran the inliner.
+    if (RunInliner)
       addOnePass(PM, createGlobalOptimizerPass(), VerifyEach);
     addOnePass(PM, createGlobalDCEPass(), VerifyEach); // Remove dead functions.
 

Modified: llvm/trunk/tools/llvm-ld/Optimize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ld/Optimize.cpp?rev=72811&r1=72810&r2=72811&view=diff

==============================================================================
--- llvm/trunk/tools/llvm-ld/Optimize.cpp (original)
+++ llvm/trunk/tools/llvm-ld/Optimize.cpp Wed Jun  3 16:51:32 2009
@@ -94,7 +94,7 @@
 
   if (!DisableOptimizations)
     createStandardLTOPasses(&Passes, !DisableInternalize, !DisableInline,
-                            /*RunSecondGlobalOpt=*/true, VerifyEach);
+                            VerifyEach);
 
   // If the -s or -S command line options were specified, strip the symbols out
   // of the resulting program to make it smaller.  -s and -S are GNU ld options

Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=72811&r1=72810&r2=72811&view=diff

==============================================================================
--- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original)
+++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Jun  3 16:51:32 2009
@@ -391,7 +391,6 @@
     passes.add(new TargetData(*_target->getTargetData()));
     
     createStandardLTOPasses(&passes, /*Internalize=*/ false, !DisableInline,
-                            /*RunSecondGlobalOpt=*/ false, 
                             /*VerifyEach=*/ false);
 
     // Make sure everything is still good.




From evan.cheng at apple.com  Wed Jun  3 17:20:47 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 3 Jun 2009 15:20:47 -0700
Subject: [llvm-commits] [llvm] r72808 -
	/llvm/trunk/lib/Target/X86/X86InstrMMX.td
In-Reply-To: <200906032139.n53LdES3029887@zion.cs.uiuc.edu>
References: <200906032139.n53LdES3029887@zion.cs.uiuc.edu>
Message-ID: 

Stuart, this doesn't look right. The source in the pattern and the  
instruction are of different register classes. One is FR64, the other  
is VR128.

Evan

On Jun 3, 2009, at 2:39 PM, Stuart Hastings wrote:
>
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Jun  3 16:39:14 2009
> @@ -680,6 +680,8 @@
> def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
>                                                   (iPTR 0))))),
>           (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
> +def : Pat<(v2i32 (bitconvert (f64 FR64:$src))),
> +          (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
>
> // CMOV* - Used to implement the SELECT DAG operation.  Expanded by  
> the
> // scheduler into a branch sequence.
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From isanbard at gmail.com  Wed Jun  3 17:21:53 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 3 Jun 2009 15:21:53 -0700
Subject: [llvm-commits] [llvm] r72797 -
	/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
In-Reply-To: <200906031907.n53J7kdM023977@zion.cs.uiuc.edu>
References: <200906031907.n53J7kdM023977@zion.cs.uiuc.edu>
Message-ID: <16e5fdf90906031521n19d38455pd0baa2b760c6d989@mail.gmail.com>

On Wed, Jun 3, 2009 at 12:07 PM, Mike Stump  wrote:
> Author: mrs
> Date: Wed Jun ?3 14:07:46 2009
> New Revision: 72797
>
> URL: http://llvm.org/viewvc/llvm-project?rev=72797&view=rev
> Log:
> Make the buildbot see green (to make it easier to spot the next person
> that puts a new warning in).
>
> Modified:
> ? ?llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=72797&r1=72796&r2=72797&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Wed Jun ?3 14:07:46 2009
> @@ -354,7 +354,8 @@
> ? FrameIndexSDNode *FR = dyn_cast(SDValue(N,0));
> ? // FIXME there isn't really debug info here
> ? DebugLoc dl = FR->getDebugLoc();
> - ?int Index = FR->getIndex();
> + ?// FIXME: Not used.
> + ?// int Index = FR->getIndex();
>
Hi Mike,

If it's not used, please delete the line instead of commenting it out.

Thanks!

-bw



From jlerouge at apple.com  Wed Jun  3 17:31:16 2009
From: jlerouge at apple.com (Julien Lerouge)
Date: Wed, 3 Jun 2009 15:31:16 -0700
Subject: [llvm-commits] [llvm] r72650 - in
	/llvm/trunk:	include/llvm/CodeGen/JITCodeEmitter.h	include/llvm/CodeGen/MachineCodeEmitter.h	include/llvm/ExecutionEngine/JITMemoryManager.h	lib/CodeGen/MachOWriter.cpp
	lib/CodeGen/MachOWriter.h	lib/ExecutionEngi
In-Reply-To: <275e64e40906031409p533a8afbma5d8a4bdc38dcfc@mail.gmail.com>
References: <275e64e40906030958x5061eaf4l8854d665a3a8eb3d@mail.gmail.com>
	<20090603205923.GC24816@pom.apple.com>
	<275e64e40906031409p533a8afbma5d8a4bdc38dcfc@mail.gmail.com>
Message-ID: <20090603223115.GG24816@pom.apple.com>

On Wed, Jun 03, 2009 at 06:09:21PM -0300, Bruno Cardoso Lopes wrote:
> No problem, 72650 is simple enough to be commited again if it's not
> causing any trouble. Since I don't have any idea of what's causing the
> regression,
> I decided to revert it. I'll wait for a reduced test case then.

It's still happening with 72804, so it wasn't 72650.

Thanks,
Julien

-- 
Julien Lerouge
PGP Key Id: 0xB1964A62
PGP Fingerprint: 392D 4BAD DB8B CE7F 4E5F FA3C 62DB 4AA7 B196 4A62
PGP Public Key from: keyserver.pgp.com


From evan.cheng at apple.com  Wed Jun  3 17:31:47 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 3 Jun 2009 15:31:47 -0700
Subject: [llvm-commits] [llvm] r72808 -
	/llvm/trunk/lib/Target/X86/X86InstrMMX.td
In-Reply-To: 
References: <200906032139.n53LdES3029887@zion.cs.uiuc.edu>
	
Message-ID: <56DB530E-1D26-4C35-8F13-29464F747B9A@apple.com>

Also, you didn't commit a test case for this.

Evan

On Jun 3, 2009, at 3:20 PM, Evan Cheng wrote:

> Stuart, this doesn't look right. The source in the pattern and the  
> instruction are of different register classes. One is FR64, the  
> other is VR128.
>
> Evan
>
> On Jun 3, 2009, at 2:39 PM, Stuart Hastings wrote:
>>
>>
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Jun  3 16:39:14 2009
>> @@ -680,6 +680,8 @@
>> def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
>>                                                   (iPTR 0))))),
>>           (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
>> +def : Pat<(v2i32 (bitconvert (f64 FR64:$src))),
>> +          (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
>>
>> // CMOV* - Used to implement the SELECT DAG operation.  Expanded by  
>> the
>> // scheduler into a branch sequence.
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From aaronngray.lists at googlemail.com  Wed Jun  3 17:37:13 2009
From: aaronngray.lists at googlemail.com (Aaron Gray)
Date: Wed, 3 Jun 2009 23:37:13 +0100
Subject: [llvm-commits] [llvm] r72650 - in /llvm/trunk:
	include/llvm/CodeGen/JITCodeEmitter.h
	include/llvm/CodeGen/MachineCodeEmitter.h
	include/llvm/ExecutionEngine/JITMemoryManager.h
	lib/CodeGen/MachOWriter.cpp lib/CodeGen/MachOWriter.h
	lib/ExecutionEngi
In-Reply-To: <20090603223115.GG24816@pom.apple.com>
References: <275e64e40906030958x5061eaf4l8854d665a3a8eb3d@mail.gmail.com> 
	<20090603205923.GC24816@pom.apple.com>
	<275e64e40906031409p533a8afbma5d8a4bdc38dcfc@mail.gmail.com> 
	<20090603223115.GG24816@pom.apple.com>
Message-ID: <9719867c0906031537i7c031f3cq2acb9d0e8e66c93b@mail.gmail.com>

>It's still happening with 72804, so it wasn't 72650.
Right, thats really good news, thanks. I stil would appreciate those
MinGW/Cygwin dejaGNU testset mods.

Thanks again,

Aaron
2009/6/3 Julien Lerouge 

> On Wed, Jun 03, 2009 at 06:09:21PM -0300, Bruno Cardoso Lopes wrote:
> > No problem, 72650 is simple enough to be commited again if it's not
> > causing any trouble. Since I don't have any idea of what's causing the
> > regression,
> > I decided to revert it. I'll wait for a reduced test case then.
>
> It's still happening with 72804, so it wasn't 72650.
>
> Thanks,
> Julien
>
> --
> Julien Lerouge
> PGP Key Id: 0xB1964A62
> PGP Fingerprint: 392D 4BAD DB8B CE7F 4E5F FA3C 62DB 4AA7 B196 4A62
> PGP Public Key from: keyserver.pgp.com
> _______________________________________________
>  llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From kledzik at apple.com  Wed Jun  3 17:52:12 2009
From: kledzik at apple.com (Nick Kledzik)
Date: Wed, 03 Jun 2009 22:52:12 -0000
Subject: [llvm-commits] [llvm] r72816 -
	/llvm/trunk/tools/lto/LTOCodeGenerator.cpp
Message-ID: <200906032252.n53MqCdR032487@zion.cs.uiuc.edu>

Author: kledzik
Date: Wed Jun  3 17:52:12 2009
New Revision: 72816

URL: http://llvm.org/viewvc/llvm-project?rev=72816&view=rev
Log:
 C++ static constructors not preserved for static executable using LTO
Move setRelocationModel() to be called before TargetMachine is instantiated.

Modified:
    llvm/trunk/tools/lto/LTOCodeGenerator.cpp

Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=72816&r1=72815&r2=72816&view=diff

==============================================================================
--- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original)
+++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Jun  3 17:52:12 2009
@@ -304,6 +304,20 @@
         if ( march == NULL )
             return true;
 
+        // The relocation model is actually a static member of TargetMachine
+        // and needs to be set before the TargetMachine is instantiated.
+        switch( _codeModel ) {
+        case LTO_CODEGEN_PIC_MODEL_STATIC:
+            TargetMachine::setRelocationModel(Reloc::Static);
+            break;
+        case LTO_CODEGEN_PIC_MODEL_DYNAMIC:
+            TargetMachine::setRelocationModel(Reloc::PIC_);
+            break;
+        case LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC:
+            TargetMachine::setRelocationModel(Reloc::DynamicNoPIC);
+            break;
+        }
+
         // construct LTModule, hand over ownership of module and target
         std::string FeatureStr =
           getFeatureString(_linker.getModule()->getTargetTriple().c_str());
@@ -363,19 +377,6 @@
     if ( _target->getTargetAsmInfo()->doesSupportExceptionHandling() )
         llvm::ExceptionHandling = true;
 
-    // set codegen model
-    switch( _codeModel ) {
-        case LTO_CODEGEN_PIC_MODEL_STATIC:
-            _target->setRelocationModel(Reloc::Static);
-            break;
-        case LTO_CODEGEN_PIC_MODEL_DYNAMIC:
-            _target->setRelocationModel(Reloc::PIC_);
-            break;
-        case LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC:
-            _target->setRelocationModel(Reloc::DynamicNoPIC);
-            break;
-    }
-
     // if options were requested, set them
     if ( !_codegenOptions.empty() )
         cl::ParseCommandLineOptions(_codegenOptions.size(), 




From stuart at apple.com  Wed Jun  3 17:59:35 2009
From: stuart at apple.com (Stuart Hastings)
Date: Wed, 03 Jun 2009 22:59:35 -0000
Subject: [llvm-commits] [llvm] r72817 -
	/llvm/trunk/lib/Target/X86/X86InstrMMX.td
Message-ID: <200906032259.n53MxZZj032722@zion.cs.uiuc.edu>

Author: stuart
Date: Wed Jun  3 17:59:34 2009
New Revision: 72817

URL: http://llvm.org/viewvc/llvm-project?rev=72817&view=rev
Log:
Evan says it's wrong; back out 72808.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrMMX.td

Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=72817&r1=72816&r2=72817&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Jun  3 17:59:34 2009
@@ -680,8 +680,6 @@
 def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
                                                   (iPTR 0))))),
           (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
-def : Pat<(v2i32 (bitconvert (f64 FR64:$src))),
-          (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
 
 // CMOV* - Used to implement the SELECT DAG operation.  Expanded by the
 // scheduler into a branch sequence.




From daniel at zuster.org  Wed Jun  3 18:37:14 2009
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 03 Jun 2009 23:37:14 -0000
Subject: [llvm-commits] [test-suite] r72818 - in
 /test-suite/trunk/SingleSource: Makefile.singlesrc UnitTests/Makefile
 UnitTests/Threads/Makefile
Message-ID: <200906032337.n53NbEro001702@zion.cs.uiuc.edu>

Author: ddunbar
Date: Wed Jun  3 18:37:11 2009
New Revision: 72818

URL: http://llvm.org/viewvc/llvm-project?rev=72818&view=rev
Log:
Add a facility for skipping individual SingleSource tests.
 - Makefiles can define PROGRAMS_TO_SKIP to a list of programs which shouldn't
   be tested.

 - Currently used to skip the "tls" and "2007-04-25-weak" tests on Darwin, where
   they are essentially XFAIL.

Modified:
    test-suite/trunk/SingleSource/Makefile.singlesrc
    test-suite/trunk/SingleSource/UnitTests/Makefile
    test-suite/trunk/SingleSource/UnitTests/Threads/Makefile

Modified: test-suite/trunk/SingleSource/Makefile.singlesrc
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Makefile.singlesrc?rev=72818&r1=72817&r2=72818&view=diff

==============================================================================
--- test-suite/trunk/SingleSource/Makefile.singlesrc (original)
+++ test-suite/trunk/SingleSource/Makefile.singlesrc Wed Jun  3 18:37:11 2009
@@ -16,7 +16,9 @@
 #
 ##===----------------------------------------------------------------------===##
 
-PROGRAMS_TO_TEST = $(patsubst $(SourceDir)%,%,$(basename $(Source)))
+
+PROGRAMS_TO_TEST = $(filter-out $(PROGRAMS_TO_SKIP), \
+	$(patsubst $(SourceDir)%,%,$(basename $(Source))))
 
 include $(LEVEL)/Makefile.programs
 .PRECIOUS: Output/%.linked.rll

Modified: test-suite/trunk/SingleSource/UnitTests/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Makefile?rev=72818&r1=72817&r2=72818&view=diff

==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/Makefile (original)
+++ test-suite/trunk/SingleSource/UnitTests/Makefile Wed Jun  3 18:37:11 2009
@@ -25,5 +25,11 @@
 endif
 endif
 
+# Darwin doesn't support weak/weak_import in a way that we can test in this
+# framework.
+ifeq ($(OS),Darwin)
+PROGRAMS_TO_SKIP := 2007-04-25-weak
+endif
+
 PROGRAM_REQUIRED_TO_EXIT_OK := 1
 include $(LEVEL)/SingleSource/Makefile.singlesrc

Modified: test-suite/trunk/SingleSource/UnitTests/Threads/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Threads/Makefile?rev=72818&r1=72817&r2=72818&view=diff

==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/Threads/Makefile (original)
+++ test-suite/trunk/SingleSource/UnitTests/Threads/Makefile Wed Jun  3 18:37:11 2009
@@ -4,4 +4,9 @@
 include $(LEVEL)/Makefile.config
 LDFLAGS += -lpthread
 
+# Darwin doesn't support tls.
+ifeq ($(OS),Darwin)
+PROGRAMS_TO_SKIP := tls
+endif
+
 include $(LEVEL)/SingleSource/Makefile.singlesrc




From bruno.cardoso at gmail.com  Wed Jun  3 19:15:52 2009
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 04 Jun 2009 00:15:52 -0000
Subject: [llvm-commits] [llvm] r72821 - in /llvm/trunk:
 include/llvm/CodeGen/JITCodeEmitter.h
 include/llvm/CodeGen/MachineCodeEmitter.h
 include/llvm/ExecutionEngine/JITMemoryManager.h
 lib/ExecutionEngine/JIT/JITEmitter.cpp
 lib/ExecutionEngine/JIT/JITMemoryManager.cpp
Message-ID: <200906040015.n540FqnH003031@zion.cs.uiuc.edu>

Author: bruno
Date: Wed Jun  3 19:15:51 2009
New Revision: 72821

URL: http://llvm.org/viewvc/llvm-project?rev=72821&view=rev
Log:
Use uint8_t and int32_t in {JIT,Machine}CodeEmiters

Modified:
    llvm/trunk/include/llvm/CodeGen/JITCodeEmitter.h
    llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h
    llvm/trunk/include/llvm/ExecutionEngine/JITMemoryManager.h
    llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp
    llvm/trunk/lib/ExecutionEngine/JIT/JITMemoryManager.cpp

Modified: llvm/trunk/include/llvm/CodeGen/JITCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/JITCodeEmitter.h?rev=72821&r1=72820&r2=72821&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/JITCodeEmitter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/JITCodeEmitter.h Wed Jun  3 19:15:51 2009
@@ -89,7 +89,7 @@
   /// emitByte - This callback is invoked when a byte needs to be written to the
   /// output stream.
   ///
-  void emitByte(unsigned char B) {
+  void emitByte(uint8_t B) {
     if (CurBufferPtr != BufferEnd)
       *CurBufferPtr++ = B;
   }
@@ -99,10 +99,10 @@
   ///
   void emitWordLE(unsigned W) {
     if (4 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (unsigned char)(W >>  0);
-      *CurBufferPtr++ = (unsigned char)(W >>  8);
-      *CurBufferPtr++ = (unsigned char)(W >> 16);
-      *CurBufferPtr++ = (unsigned char)(W >> 24);
+      *CurBufferPtr++ = (uint8_t)(W >>  0);
+      *CurBufferPtr++ = (uint8_t)(W >>  8);
+      *CurBufferPtr++ = (uint8_t)(W >> 16);
+      *CurBufferPtr++ = (uint8_t)(W >> 24);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -113,10 +113,10 @@
   ///
   void emitWordBE(unsigned W) {
     if (4 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (unsigned char)(W >> 24);
-      *CurBufferPtr++ = (unsigned char)(W >> 16);
-      *CurBufferPtr++ = (unsigned char)(W >>  8);
-      *CurBufferPtr++ = (unsigned char)(W >>  0);
+      *CurBufferPtr++ = (uint8_t)(W >> 24);
+      *CurBufferPtr++ = (uint8_t)(W >> 16);
+      *CurBufferPtr++ = (uint8_t)(W >>  8);
+      *CurBufferPtr++ = (uint8_t)(W >>  0);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -127,14 +127,14 @@
   ///
   void emitDWordLE(uint64_t W) {
     if (8 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (unsigned char)(W >>  0);
-      *CurBufferPtr++ = (unsigned char)(W >>  8);
-      *CurBufferPtr++ = (unsigned char)(W >> 16);
-      *CurBufferPtr++ = (unsigned char)(W >> 24);
-      *CurBufferPtr++ = (unsigned char)(W >> 32);
-      *CurBufferPtr++ = (unsigned char)(W >> 40);
-      *CurBufferPtr++ = (unsigned char)(W >> 48);
-      *CurBufferPtr++ = (unsigned char)(W >> 56);
+      *CurBufferPtr++ = (uint8_t)(W >>  0);
+      *CurBufferPtr++ = (uint8_t)(W >>  8);
+      *CurBufferPtr++ = (uint8_t)(W >> 16);
+      *CurBufferPtr++ = (uint8_t)(W >> 24);
+      *CurBufferPtr++ = (uint8_t)(W >> 32);
+      *CurBufferPtr++ = (uint8_t)(W >> 40);
+      *CurBufferPtr++ = (uint8_t)(W >> 48);
+      *CurBufferPtr++ = (uint8_t)(W >> 56);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -145,14 +145,14 @@
   ///
   void emitDWordBE(uint64_t W) {
     if (8 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (unsigned char)(W >> 56);
-      *CurBufferPtr++ = (unsigned char)(W >> 48);
-      *CurBufferPtr++ = (unsigned char)(W >> 40);
-      *CurBufferPtr++ = (unsigned char)(W >> 32);
-      *CurBufferPtr++ = (unsigned char)(W >> 24);
-      *CurBufferPtr++ = (unsigned char)(W >> 16);
-      *CurBufferPtr++ = (unsigned char)(W >>  8);
-      *CurBufferPtr++ = (unsigned char)(W >>  0);
+      *CurBufferPtr++ = (uint8_t)(W >> 56);
+      *CurBufferPtr++ = (uint8_t)(W >> 48);
+      *CurBufferPtr++ = (uint8_t)(W >> 40);
+      *CurBufferPtr++ = (uint8_t)(W >> 32);
+      *CurBufferPtr++ = (uint8_t)(W >> 24);
+      *CurBufferPtr++ = (uint8_t)(W >> 16);
+      *CurBufferPtr++ = (uint8_t)(W >>  8);
+      *CurBufferPtr++ = (uint8_t)(W >>  0);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -166,8 +166,8 @@
     if(Alignment <= (uintptr_t)(BufferEnd-CurBufferPtr)) {
       // Move the current buffer ptr up to the specified alignment.
       CurBufferPtr =
-        (unsigned char*)(((uintptr_t)CurBufferPtr+Alignment-1) &
-                         ~(uintptr_t)(Alignment-1));
+        (uint8_t*)(((uintptr_t)CurBufferPtr+Alignment-1) &
+                   ~(uintptr_t)(Alignment-1));
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -178,7 +178,7 @@
   /// written to the output stream.
   void emitULEB128Bytes(unsigned Value) {
     do {
-      unsigned char Byte = Value & 0x7f;
+      uint8_t Byte = Value & 0x7f;
       Value >>= 7;
       if (Value) Byte |= 0x80;
       emitByte(Byte);
@@ -187,12 +187,12 @@
   
   /// emitSLEB128Bytes - This callback is invoked when a SLEB128 needs to be
   /// written to the output stream.
-  void emitSLEB128Bytes(int Value) {
-    int Sign = Value >> (8 * sizeof(Value) - 1);
+  void emitSLEB128Bytes(int32_t Value) {
+    int32_t Sign = Value >> (8 * sizeof(Value) - 1);
     bool IsMore;
   
     do {
-      unsigned char Byte = Value & 0x7f;
+      uint8_t Byte = Value & 0x7f;
       Value >>= 7;
       IsMore = Value != Sign || ((Byte ^ Sign) & 0x40) != 0;
       if (IsMore) Byte |= 0x80;
@@ -205,14 +205,14 @@
   void emitString(const std::string &String) {
     for (unsigned i = 0, N = static_cast(String.size());
          i < N; ++i) {
-      unsigned char C = String[i];
+      uint8_t C = String[i];
       emitByte(C);
     }
     emitByte(0);
   }
   
   /// emitInt32 - Emit a int32 directive.
-  void emitInt32(int Value) {
+  void emitInt32(int32_t Value) {
     if (4 <= BufferEnd-CurBufferPtr) {
       *((uint32_t*)CurBufferPtr) = Value;
       CurBufferPtr += 4;

Modified: llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h?rev=72821&r1=72820&r2=72821&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineCodeEmitter.h Wed Jun  3 19:15:51 2009
@@ -50,14 +50,14 @@
 protected:
   /// BufferBegin/BufferEnd - Pointers to the start and end of the memory
   /// allocated for this code buffer.
-  unsigned char *BufferBegin, *BufferEnd;
+  uint8_t *BufferBegin, *BufferEnd;
   
   /// CurBufferPtr - Pointer to the next byte of memory to fill when emitting 
   /// code.  This is guranteed to be in the range [BufferBegin,BufferEnd].  If
   /// this pointer is at BufferEnd, it will never move due to code emission, and
   /// all code emission requests will be ignored (this is the buffer overflow
   /// condition).
-  unsigned char *CurBufferPtr;
+  uint8_t *CurBufferPtr;
 
 public:
   virtual ~MachineCodeEmitter() {}
@@ -96,7 +96,7 @@
   /// emitByte - This callback is invoked when a byte needs to be written to the
   /// output stream.
   ///
-  void emitByte(unsigned char B) {
+  void emitByte(uint8_t B) {
     if (CurBufferPtr != BufferEnd)
       *CurBufferPtr++ = B;
   }
@@ -106,10 +106,10 @@
   ///
   void emitWordLE(unsigned W) {
     if (4 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (unsigned char)(W >>  0);
-      *CurBufferPtr++ = (unsigned char)(W >>  8);
-      *CurBufferPtr++ = (unsigned char)(W >> 16);
-      *CurBufferPtr++ = (unsigned char)(W >> 24);
+      *CurBufferPtr++ = (uint8_t)(W >>  0);
+      *CurBufferPtr++ = (uint8_t)(W >>  8);
+      *CurBufferPtr++ = (uint8_t)(W >> 16);
+      *CurBufferPtr++ = (uint8_t)(W >> 24);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -120,10 +120,10 @@
   ///
   void emitWordBE(unsigned W) {
     if (4 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (unsigned char)(W >> 24);
-      *CurBufferPtr++ = (unsigned char)(W >> 16);
-      *CurBufferPtr++ = (unsigned char)(W >>  8);
-      *CurBufferPtr++ = (unsigned char)(W >>  0);
+      *CurBufferPtr++ = (uint8_t)(W >> 24);
+      *CurBufferPtr++ = (uint8_t)(W >> 16);
+      *CurBufferPtr++ = (uint8_t)(W >>  8);
+      *CurBufferPtr++ = (uint8_t)(W >>  0);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -134,14 +134,14 @@
   ///
   void emitDWordLE(uint64_t W) {
     if (8 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (unsigned char)(W >>  0);
-      *CurBufferPtr++ = (unsigned char)(W >>  8);
-      *CurBufferPtr++ = (unsigned char)(W >> 16);
-      *CurBufferPtr++ = (unsigned char)(W >> 24);
-      *CurBufferPtr++ = (unsigned char)(W >> 32);
-      *CurBufferPtr++ = (unsigned char)(W >> 40);
-      *CurBufferPtr++ = (unsigned char)(W >> 48);
-      *CurBufferPtr++ = (unsigned char)(W >> 56);
+      *CurBufferPtr++ = (uint8_t)(W >>  0);
+      *CurBufferPtr++ = (uint8_t)(W >>  8);
+      *CurBufferPtr++ = (uint8_t)(W >> 16);
+      *CurBufferPtr++ = (uint8_t)(W >> 24);
+      *CurBufferPtr++ = (uint8_t)(W >> 32);
+      *CurBufferPtr++ = (uint8_t)(W >> 40);
+      *CurBufferPtr++ = (uint8_t)(W >> 48);
+      *CurBufferPtr++ = (uint8_t)(W >> 56);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -152,14 +152,14 @@
   ///
   void emitDWordBE(uint64_t W) {
     if (8 <= BufferEnd-CurBufferPtr) {
-      *CurBufferPtr++ = (unsigned char)(W >> 56);
-      *CurBufferPtr++ = (unsigned char)(W >> 48);
-      *CurBufferPtr++ = (unsigned char)(W >> 40);
-      *CurBufferPtr++ = (unsigned char)(W >> 32);
-      *CurBufferPtr++ = (unsigned char)(W >> 24);
-      *CurBufferPtr++ = (unsigned char)(W >> 16);
-      *CurBufferPtr++ = (unsigned char)(W >>  8);
-      *CurBufferPtr++ = (unsigned char)(W >>  0);
+      *CurBufferPtr++ = (uint8_t)(W >> 56);
+      *CurBufferPtr++ = (uint8_t)(W >> 48);
+      *CurBufferPtr++ = (uint8_t)(W >> 40);
+      *CurBufferPtr++ = (uint8_t)(W >> 32);
+      *CurBufferPtr++ = (uint8_t)(W >> 24);
+      *CurBufferPtr++ = (uint8_t)(W >> 16);
+      *CurBufferPtr++ = (uint8_t)(W >>  8);
+      *CurBufferPtr++ = (uint8_t)(W >>  0);
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -173,8 +173,8 @@
     if(Alignment <= (uintptr_t)(BufferEnd-CurBufferPtr)) {
       // Move the current buffer ptr up to the specified alignment.
       CurBufferPtr =
-        (unsigned char*)(((uintptr_t)CurBufferPtr+Alignment-1) &
-                         ~(uintptr_t)(Alignment-1));
+        (uint8_t*)(((uintptr_t)CurBufferPtr+Alignment-1) &
+                   ~(uintptr_t)(Alignment-1));
     } else {
       CurBufferPtr = BufferEnd;
     }
@@ -185,7 +185,7 @@
   /// written to the output stream.
   void emitULEB128Bytes(unsigned Value) {
     do {
-      unsigned char Byte = Value & 0x7f;
+      uint8_t Byte = Value & 0x7f;
       Value >>= 7;
       if (Value) Byte |= 0x80;
       emitByte(Byte);
@@ -194,12 +194,12 @@
   
   /// emitSLEB128Bytes - This callback is invoked when a SLEB128 needs to be
   /// written to the output stream.
-  void emitSLEB128Bytes(int Value) {
-    int Sign = Value >> (8 * sizeof(Value) - 1);
+  void emitSLEB128Bytes(int32_t Value) {
+    int32_t Sign = Value >> (8 * sizeof(Value) - 1);
     bool IsMore;
   
     do {
-      unsigned char Byte = Value & 0x7f;
+      uint8_t Byte = Value & 0x7f;
       Value >>= 7;
       IsMore = Value != Sign || ((Byte ^ Sign) & 0x40) != 0;
       if (IsMore) Byte |= 0x80;
@@ -212,14 +212,14 @@
   void emitString(const std::string &String) {
     for (unsigned i = 0, N = static_cast(String.size());
          i < N; ++i) {
-      unsigned char C = String[i];
+      uint8_t C = String[i];
       emitByte(C);
     }
     emitByte(0);
   }
   
   /// emitInt32 - Emit a int32 directive.
-  void emitInt32(int Value) {
+  void emitInt32(int32_t Value) {
     if (4 <= BufferEnd-CurBufferPtr) {
       *((uint32_t*)CurBufferPtr) = Value;
       CurBufferPtr += 4;

Modified: llvm/trunk/include/llvm/ExecutionEngine/JITMemoryManager.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/JITMemoryManager.h?rev=72821&r1=72820&r2=72821&view=diff

==============================================================================
--- llvm/trunk/include/llvm/ExecutionEngine/JITMemoryManager.h (original)
+++ llvm/trunk/include/llvm/ExecutionEngine/JITMemoryManager.h Wed Jun  3 19:15:51 2009
@@ -60,7 +60,7 @@
   
   /// getGOTBase - If this is managing a Global Offset Table, this method should
   /// return a pointer to its base.
-  virtual unsigned char *getGOTBase() const = 0;
+  virtual uint8_t *getGOTBase() const = 0;
   
   /// SetDlsymTable - If the JIT must be able to relocate stubs after they have
   /// been emitted, potentially because they are being copied to a process
@@ -89,8 +89,8 @@
   /// emit the function, so it doesn't pass in the size.  Instead, this method
   /// is required to pass back a "valid size".  The JIT will be careful to not
   /// write more than the returned ActualSize bytes of memory. 
-  virtual unsigned char *startFunctionBody(const Function *F, 
-                                           uintptr_t &ActualSize) = 0;
+  virtual uint8_t *startFunctionBody(const Function *F, 
+                                     uintptr_t &ActualSize) = 0;
   
   /// allocateStub - This method is called by the JIT to allocate space for a
   /// function stub (used to handle limited branch displacements) while it is
@@ -100,9 +100,8 @@
   /// thunk for it.  The stub should be "close" to the current function body,
   /// but should not be included in the 'actualsize' returned by
   /// startFunctionBody.
-  virtual unsigned char *allocateStub(const GlobalValue* F, unsigned StubSize,
-                                      unsigned Alignment) =0;
-  
+  virtual uint8_t *allocateStub(const GlobalValue* F, unsigned StubSize,
+                                unsigned Alignment) = 0;
   
   /// endFunctionBody - This method is called when the JIT is done codegen'ing
   /// the specified function.  At this point we know the size of the JIT
@@ -110,11 +109,11 @@
   /// the startFunctionBody method) and FunctionEnd which is a pointer to the 
   /// actual end of the function.  This method should mark the space allocated
   /// and remember where it is in case the client wants to deallocate it.
-  virtual void endFunctionBody(const Function *F, unsigned char *FunctionStart,
-                               unsigned char *FunctionEnd) = 0;
+  virtual void endFunctionBody(const Function *F, uint8_t *FunctionStart,
+                               uint8_t *FunctionEnd) = 0;
 
   /// allocateSpace - Allocate a memory block of the given size.
-  virtual unsigned char *allocateSpace(intptr_t Size, unsigned Alignment) = 0;
+  virtual uint8_t *allocateSpace(intptr_t Size, unsigned Alignment) = 0;
   
   /// deallocateMemForFunction - Free JIT memory for the specified function.
   /// This is never called when the JIT is currently emitting a function.
@@ -122,14 +121,13 @@
   
   /// startExceptionTable - When we finished JITing the function, if exception
   /// handling is set, we emit the exception table.
-  virtual unsigned char* startExceptionTable(const Function* F,
-                                             uintptr_t &ActualSize) = 0;
+  virtual uint8_t* startExceptionTable(const Function* F,
+                                       uintptr_t &ActualSize) = 0;
   
   /// endExceptionTable - This method is called when the JIT is done emitting
   /// the exception table.
-  virtual void endExceptionTable(const Function *F, unsigned char *TableStart,
-                                 unsigned char *TableEnd, 
-                                 unsigned char* FrameRegister) = 0;
+  virtual void endExceptionTable(const Function *F, uint8_t *TableStart,
+                                 uint8_t *TableEnd, uint8_t* FrameRegister) = 0;
 };
 
 } // end namespace llvm.

Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp?rev=72821&r1=72820&r2=72821&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Wed Jun  3 19:15:51 2009
@@ -551,7 +551,7 @@
 
     // When outputting a function stub in the context of some other function, we
     // save BufferBegin/BufferEnd/CurBufferPtr here.
-    unsigned char *SavedBufferBegin, *SavedBufferEnd, *SavedCurBufferPtr;
+    uint8_t *SavedBufferBegin, *SavedBufferEnd, *SavedCurBufferPtr;
 
     /// Relocations - These are the relocations that the function needs, as
     /// emitted.
@@ -1056,11 +1056,11 @@
   
   // FnStart is the start of the text, not the start of the constant pool and
   // other per-function data.
-  unsigned char *FnStart =
-    (unsigned char *)TheJIT->getPointerToGlobalIfAvailable(F.getFunction());
+  uint8_t *FnStart =
+    (uint8_t *)TheJIT->getPointerToGlobalIfAvailable(F.getFunction());
 
   // FnEnd is the end of the function's machine code.
-  unsigned char *FnEnd = CurBufferPtr;
+  uint8_t *FnEnd = CurBufferPtr;
 
   if (!Relocations.empty()) {
     CurFn = F.getFunction();
@@ -1183,7 +1183,7 @@
     } else {
       DOUT << "JIT: Binary code:\n";
       DOUT << std::hex;
-      unsigned char* q = FnStart;
+      uint8_t* q = FnStart;
       for (int i = 0; q < FnEnd; q += 4, ++i) {
         if (i == 4)
           i = 0;
@@ -1221,7 +1221,7 @@
     BufferBegin = CurBufferPtr = MemMgr->startExceptionTable(F.getFunction(),
                                                              ActualSize);
     BufferEnd = BufferBegin+ActualSize;
-    unsigned char* FrameRegister = DE->EmitDwarfTable(F, *this, FnStart, FnEnd);
+    uint8_t* FrameRegister = DE->EmitDwarfTable(F, *this, FnStart, FnEnd);
     MemMgr->endExceptionTable(F.getFunction(), BufferBegin, CurBufferPtr,
                               FrameRegister);
     BufferBegin = SavedBufferBegin;
@@ -1416,7 +1416,7 @@
   SavedBufferEnd = BufferEnd;
   SavedCurBufferPtr = CurBufferPtr;
   
-  BufferBegin = CurBufferPtr = (unsigned char *)Buffer;
+  BufferBegin = CurBufferPtr = (uint8_t *)Buffer;
   BufferEnd = BufferBegin+StubSize+1;
 }
 

Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITMemoryManager.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITMemoryManager.cpp?rev=72821&r1=72820&r2=72821&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JITMemoryManager.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JITMemoryManager.cpp Wed Jun  3 19:15:51 2009
@@ -257,9 +257,9 @@
     // When emitting code into a memory block, this is the block.
     MemoryRangeHeader *CurBlock;
     
-    unsigned char *CurStubPtr, *StubBase;
-    unsigned char *GOTBase;      // Target Specific reserved memory
-    void *DlsymTable;            // Stub external symbol information
+    uint8_t *CurStubPtr, *StubBase;
+    uint8_t *GOTBase;     // Target Specific reserved memory
+    void *DlsymTable;     // Stub external symbol information
 
     // Centralize memory block allocation.
     sys::MemoryBlock getNewMemoryBlock(unsigned size);
@@ -273,12 +273,12 @@
     void AllocateGOT();
     void SetDlsymTable(void *);
     
-    unsigned char *allocateStub(const GlobalValue* F, unsigned StubSize,
-                                unsigned Alignment);
+    uint8_t *allocateStub(const GlobalValue* F, unsigned StubSize,
+                          unsigned Alignment);
     
     /// startFunctionBody - When a function starts, allocate a block of free
     /// executable memory, returning a pointer to it and its actual size.
-    unsigned char *startFunctionBody(const Function *F, uintptr_t &ActualSize) {
+    uint8_t *startFunctionBody(const Function *F, uintptr_t &ActualSize) {
       
       FreeRangeHeader* candidateBlock = FreeMemoryList;
       FreeRangeHeader* head = FreeMemoryList;
@@ -301,18 +301,18 @@
       // Allocate the entire memory block.
       FreeMemoryList = candidateBlock->AllocateBlock();
       ActualSize = CurBlock->BlockSize-sizeof(MemoryRangeHeader);
-      return (unsigned char *)(CurBlock+1);
+      return (uint8_t *)(CurBlock+1);
     }
     
     /// endFunctionBody - The function F is now allocated, and takes the memory
     /// in the range [FunctionStart,FunctionEnd).
-    void endFunctionBody(const Function *F, unsigned char *FunctionStart,
-                         unsigned char *FunctionEnd) {
+    void endFunctionBody(const Function *F, uint8_t *FunctionStart,
+                         uint8_t *FunctionEnd) {
       assert(FunctionEnd > FunctionStart);
-      assert(FunctionStart == (unsigned char *)(CurBlock+1) &&
+      assert(FunctionStart == (uint8_t *)(CurBlock+1) &&
              "Mismatched function start/end!");
 
-      uintptr_t BlockSize = FunctionEnd - (unsigned char *)CurBlock;
+      uintptr_t BlockSize = FunctionEnd - (uint8_t *)CurBlock;
       FunctionBlocks[F] = CurBlock;
 
       // Release the memory at the end of this block that isn't needed.
@@ -320,17 +320,17 @@
     }
 
     /// allocateSpace - Allocate a memory block of the given size.
-    unsigned char *allocateSpace(intptr_t Size, unsigned Alignment) {
+    uint8_t *allocateSpace(intptr_t Size, unsigned Alignment) {
       CurBlock = FreeMemoryList;
       FreeMemoryList = FreeMemoryList->AllocateBlock();
 
-      unsigned char *result = (unsigned char *)CurBlock+1;
+      uint8_t *result = (uint8_t *)CurBlock+1;
 
       if (Alignment == 0) Alignment = 1;
-      result = (unsigned char*)(((intptr_t)result+Alignment-1) &
+      result = (uint8_t*)(((intptr_t)result+Alignment-1) &
                ~(intptr_t)(Alignment-1));
 
-      uintptr_t BlockSize = result + Size - (unsigned char *)CurBlock;
+      uintptr_t BlockSize = result + Size - (uint8_t *)CurBlock;
       FreeMemoryList =CurBlock->TrimAllocationToSize(FreeMemoryList, BlockSize);
 
       return result;
@@ -338,28 +338,26 @@
 
     /// startExceptionTable - Use startFunctionBody to allocate memory for the 
     /// function's exception table.
-    unsigned char* startExceptionTable(const Function* F, 
-                                       uintptr_t &ActualSize) {
+    uint8_t* startExceptionTable(const Function* F, uintptr_t &ActualSize) {
       return startFunctionBody(F, ActualSize);
     }
 
     /// endExceptionTable - The exception table of F is now allocated, 
     /// and takes the memory in the range [TableStart,TableEnd).
-    void endExceptionTable(const Function *F, unsigned char *TableStart,
-                           unsigned char *TableEnd, 
-                           unsigned char* FrameRegister) {
+    void endExceptionTable(const Function *F, uint8_t *TableStart,
+                           uint8_t *TableEnd, uint8_t* FrameRegister) {
       assert(TableEnd > TableStart);
-      assert(TableStart == (unsigned char *)(CurBlock+1) &&
+      assert(TableStart == (uint8_t *)(CurBlock+1) &&
              "Mismatched table start/end!");
       
-      uintptr_t BlockSize = TableEnd - (unsigned char *)CurBlock;
+      uintptr_t BlockSize = TableEnd - (uint8_t *)CurBlock;
       TableBlocks[F] = CurBlock;
 
       // Release the memory at the end of this block that isn't needed.
       FreeMemoryList =CurBlock->TrimAllocationToSize(FreeMemoryList, BlockSize);
     }
     
-    unsigned char *getGOTBase() const {
+    uint8_t *getGOTBase() const {
       return GOTBase;
     }
     
@@ -433,7 +431,7 @@
   sys::MemoryBlock MemBlock = getNewMemoryBlock(16 << 20);
 #endif
 
-  unsigned char *MemBase = static_cast(MemBlock.base());
+  uint8_t *MemBase = static_cast(MemBlock.base());
 
   // Allocate stubs backwards from the base, allocate functions forward
   // from the base.
@@ -492,7 +490,7 @@
 
 void DefaultJITMemoryManager::AllocateGOT() {
   assert(GOTBase == 0 && "Cannot allocate the got multiple times");
-  GOTBase = new unsigned char[sizeof(void*) * 8192];
+  GOTBase = new uint8_t[sizeof(void*) * 8192];
   HasGOT = true;
 }
 
@@ -508,12 +506,12 @@
   Blocks.clear();
 }
 
-unsigned char *DefaultJITMemoryManager::allocateStub(const GlobalValue* F,
+uint8_t *DefaultJITMemoryManager::allocateStub(const GlobalValue* F,
                                                      unsigned StubSize,
                                                      unsigned Alignment) {
   CurStubPtr -= StubSize;
-  CurStubPtr = (unsigned char*)(((intptr_t)CurStubPtr) &
-                                ~(intptr_t)(Alignment-1));
+  CurStubPtr = (uint8_t*)(((intptr_t)CurStubPtr) &
+                          ~(intptr_t)(Alignment-1));
   if (CurStubPtr < StubBase) {
     // FIXME: allocate a new block
     fprintf(stderr, "JIT ran out of memory for function stubs!\n");




From kledzik at apple.com  Wed Jun  3 19:28:45 2009
From: kledzik at apple.com (Nick Kledzik)
Date: Thu, 04 Jun 2009 00:28:45 -0000
Subject: [llvm-commits] [llvm] r72823 - in /llvm/trunk: include/llvm-c/lto.h
 tools/lto/LTOCodeGenerator.cpp tools/lto/LTOCodeGenerator.h
 tools/lto/lto.cpp tools/lto/lto.exports
Message-ID: <200906040028.n540SjMq003489@zion.cs.uiuc.edu>

Author: kledzik
Date: Wed Jun  3 19:28:45 2009
New Revision: 72823

URL: http://llvm.org/viewvc/llvm-project?rev=72823&view=rev
Log:
 libLTO.dylib needs to let linker specify path to assembler
Add lto_codegen_set_assembler_path() API which allows the linker to specify the
path to the assembler tool to run.  When assembler is used (instead of compiler)
different command line options are used.
Add LTO_API_VERSION #define so clients (linkers) can conditionalize use of new APIs.

Modified:
    llvm/trunk/include/llvm-c/lto.h
    llvm/trunk/tools/lto/LTOCodeGenerator.cpp
    llvm/trunk/tools/lto/LTOCodeGenerator.h
    llvm/trunk/tools/lto/lto.cpp
    llvm/trunk/tools/lto/lto.exports

Modified: llvm/trunk/include/llvm-c/lto.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/lto.h?rev=72823&r1=72822&r2=72823&view=diff

==============================================================================
--- llvm/trunk/include/llvm-c/lto.h (original)
+++ llvm/trunk/include/llvm-c/lto.h Wed Jun  3 19:28:45 2009
@@ -19,6 +19,8 @@
 #include 
 #include 
 
+#define LTO_API_VERSION 3
+
 typedef enum {
     LTO_SYMBOL_ALIGNMENT_MASK         = 0x0000001F,    /* log2 of alignment */
     LTO_SYMBOL_PERMISSIONS_MASK       = 0x000000E0,    
@@ -208,6 +210,14 @@
 
 
 /**
+ * Sets the location of the assembler tool to run. If not set, libLTO
+ * will use gcc to invoke the assembler.
+ */
+extern void
+lto_codegen_set_assembler_path(lto_code_gen_t cg, const char* path);
+
+
+/**
  * Adds to a list of all global symbols that must exist in the final
  * generated code.  If a function is not listed, it might be
  * inlined into every usage and optimized away.

Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=72823&r1=72822&r2=72823&view=diff

==============================================================================
--- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original)
+++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Jun  3 19:28:45 2009
@@ -72,7 +72,7 @@
     : _linker("LinkTimeOptimizer", "ld-temp.o"), _target(NULL),
       _emitDwarfDebugInfo(false), _scopeRestrictionsDone(false),
       _codeModel(LTO_CODEGEN_PIC_MODEL_DYNAMIC),
-      _nativeObjectFile(NULL), _gccPath(NULL)
+      _nativeObjectFile(NULL), _gccPath(NULL), _assemblerPath(NULL)
 {
 
 }
@@ -128,6 +128,13 @@
     _gccPath = new sys::Path(path);
 }
 
+void LTOCodeGenerator::setAssemblerPath(const char* path)
+{
+    if ( _assemblerPath )
+        delete _assemblerPath;
+    _assemblerPath = new sys::Path(path);
+}
+
 void LTOCodeGenerator::addMustPreserveSymbol(const char* sym)
 {
     _mustPreserveSymbols[sym] = 1;
@@ -220,13 +227,18 @@
 bool LTOCodeGenerator::assemble(const std::string& asmPath, 
                                 const std::string& objPath, std::string& errMsg)
 {
-    sys::Path gcc;
-    if ( _gccPath ) {
-        gcc = *_gccPath;
+    sys::Path tool;
+    bool needsCompilerOptions = true;
+    if ( _assemblerPath ) {
+        tool = *_assemblerPath;
+        needsCompilerOptions = false;
+    }
+    else if ( _gccPath ) {
+        tool = *_gccPath;
     } else {
         // find compiler driver
-        gcc = sys::Program::FindProgramByName("gcc");
-        if ( gcc.isEmpty() ) {
+        tool = sys::Program::FindProgramByName("gcc");
+        if ( tool.isEmpty() ) {
             errMsg = "can't locate gcc";
             return true;
         }
@@ -235,7 +247,7 @@
     // build argument list
     std::vector args;
     std::string targetTriple = _linker.getModule()->getTargetTriple();
-    args.push_back(gcc.c_str());
+    args.push_back(tool.c_str());
     if ( targetTriple.find("darwin") != targetTriple.size() ) {
         if (strncmp(targetTriple.c_str(), "i386-apple-", 11) == 0) {
             args.push_back("-arch");
@@ -275,16 +287,18 @@
             args.push_back("armv6");
         }
     }
-    args.push_back("-c");
-    args.push_back("-x");
-    args.push_back("assembler");
+    if ( needsCompilerOptions ) {
+        args.push_back("-c");
+        args.push_back("-x");
+        args.push_back("assembler");
+    }
     args.push_back("-o");
     args.push_back(objPath.c_str());
     args.push_back(asmPath.c_str());
     args.push_back(0);
 
     // invoke assembler
-    if ( sys::Program::ExecuteAndWait(gcc, &args[0], 0, 0, 0, 0, &errMsg) ) {
+    if ( sys::Program::ExecuteAndWait(tool, &args[0], 0, 0, 0, 0, &errMsg) ) {
         errMsg = "error in assembly";    
         return true;
     }

Modified: llvm/trunk/tools/lto/LTOCodeGenerator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.h?rev=72823&r1=72822&r2=72823&view=diff

==============================================================================
--- llvm/trunk/tools/lto/LTOCodeGenerator.h (original)
+++ llvm/trunk/tools/lto/LTOCodeGenerator.h Wed Jun  3 19:28:45 2009
@@ -37,6 +37,7 @@
     bool                setDebugInfo(lto_debug_model, std::string& errMsg);
     bool                setCodePICModel(lto_codegen_model, std::string& errMsg);
     void                setGccPath(const char* path);
+    void                setAssemblerPath(const char* path);
     void                addMustPreserveSymbol(const char* sym);
     bool                writeMergedModules(const char* path, 
                                                            std::string& errMsg);
@@ -61,6 +62,7 @@
     llvm::MemoryBuffer*         _nativeObjectFile;
     std::vector    _codegenOptions;
     llvm::sys::Path*            _gccPath;
+    llvm::sys::Path*            _assemblerPath;
 };
 
 #endif // LTO_CODE_GENERATOR_H

Modified: llvm/trunk/tools/lto/lto.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/lto.cpp?rev=72823&r1=72822&r2=72823&view=diff

==============================================================================
--- llvm/trunk/tools/lto/lto.cpp (original)
+++ llvm/trunk/tools/lto/lto.cpp Wed Jun  3 19:28:45 2009
@@ -210,6 +210,14 @@
 }
 
 //
+// sets the path to the assembler tool
+//
+void lto_codegen_set_assembler_path(lto_code_gen_t cg, const char* path)
+{
+    cg->setAssemblerPath(path);
+}
+
+//
 // adds to a list of all global symbols that must exist in the final
 // generated code.  If a function is not listed there, it might be
 // inlined into every usage and optimized away.

Modified: llvm/trunk/tools/lto/lto.exports
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/lto.exports?rev=72823&r1=72822&r2=72823&view=diff

==============================================================================
--- llvm/trunk/tools/lto/lto.exports (original)
+++ llvm/trunk/tools/lto/lto.exports Wed Jun  3 19:28:45 2009
@@ -20,4 +20,5 @@
 _lto_codegen_set_pic_model
 _lto_codegen_write_merged_modules
 _lto_codegen_debug_options
+_lto_codegen_set_assembler_path
 




From lhames at gmail.com  Wed Jun  3 20:04:22 2009
From: lhames at gmail.com (Lang Hames)
Date: Thu, 04 Jun 2009 01:04:22 -0000
Subject: [llvm-commits] [llvm] r72825 -
	/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
Message-ID: <200906040104.n5414Mdh005621@zion.cs.uiuc.edu>

Author: lhames
Date: Wed Jun  3 20:04:22 2009
New Revision: 72825

URL: http://llvm.org/viewvc/llvm-project?rev=72825&view=rev
Log:
Removed more testing code that snuck in earlier.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=72825&r1=72824&r2=72825&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Jun  3 20:04:22 2009
@@ -1192,7 +1192,6 @@
   // The earliest start of a Spilled interval indicates up to where
   // in handled we need to roll back
   
-  unsigned earliestStart = cur->beginNumber();
   LiveInterval *earliestStartInterval = cur;
 
   // Spill live intervals of virtual regs mapped to the physical register we
@@ -1206,19 +1205,10 @@
     LiveInterval *sli = spillIs.back();
     spillIs.pop_back();
     DOUT << "\t\t\tspilling(a): " << *sli << '\n';
-    earliestStart = std::min(earliestStart, sli->beginNumber());
     earliestStartInterval =
       (earliestStartInterval->beginNumber() < sli->beginNumber()) ?
          earliestStartInterval : sli;
-    
-    if (earliestStartInterval->beginNumber()!=earliestStart) {
-      epicFail |= true;
-      std::cerr << "What the 1 - "
-      		<< "earliestStart = " << earliestStart
-      		<< "earliestStartInterval = " << earliestStartInterval->beginNumber()
-      		<< "\n";
-    }
-   
+       
     std::vector newIs;
     if (!NewSpillFramework) {
       newIs = li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_);
@@ -1229,20 +1219,12 @@
     std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
     spilled.insert(sli->reg);
 
-    if (earliestStartInterval->beginNumber()!=earliestStart) {
-      epicFail |= true;
-      std::cerr << "What the 2 - "
-      		<< "earliestStart = " << earliestStart
-      		<< "earliestStartInterval = " << earliestStartInterval->beginNumber()
-      		<< "\n";
-    }
-
     if (epicFail) {
       //abort();
     }
   }
 
-  earliestStart = earliestStartInterval->beginNumber();
+  unsigned earliestStart = earliestStartInterval->beginNumber();
 
   DOUT << "\t\trolling back to: " << earliestStart << '\n';
 




From aaronngray.lists at googlemail.com  Wed Jun  3 20:06:56 2009
From: aaronngray.lists at googlemail.com (Aaron Gray)
Date: Thu, 4 Jun 2009 02:06:56 +0100
Subject: [llvm-commits] [llvm] r72650 - in
	/llvm/trunk:include/llvm/CodeGen/JITCodeEmitter.hinclude/llvm/CodeGen/MachineCodeEmitter.hinclude/llvm/ExecutionEngine/JITMemoryManager.hlib/CodeGen/MachOWriter.cpp
	lib/CodeGen/MachOWriter.hlib/ExecutionEngi
References: <275e64e40906030958x5061eaf4l8854d665a3a8eb3d@mail.gmail.com>
Message-ID: 

It could be the main earlier patch r72631 rather than 72650. But AFAICS I 
really doubt it.

Aaron

----- Original Message ----- 
From: "Bruno Cardoso Lopes" 
To: "Julien Lerouge" ; "Commit Messages and Patches for 
LLVM" 
Sent: Wednesday, June 03, 2009 5:58 PM
Subject: Re: [llvm-commits] [llvm] r72650 - in 
/llvm/trunk:include/llvm/CodeGen/JITCodeEmitter.hinclude/llvm/CodeGen/MachineCodeEmitter.hinclude/llvm/ExecutionEngine/JITMemoryManager.hlib/CodeGen/MachOWriter.cpp 
lib/CodeGen/MachOWriter.hlib/ExecutionEngi


> Hi Julien,
>
>> Hello Bruno,
>>
>> I have a buildbot running some nightly tests here on MingW that started
>> to complain somewhere between r72618 and r72690.
>>
>> Some of the tests we are running with lli are triggering the following
>> assertion:
>> Assertion failed: Addr && "Code generation didn't add function to
>> GlobalAddress table!", file
>> c:/cygwin/home/jlerouge/buildbot/llvm-src/lib/ExecutionEngine/JIT/JIT.cpp,
>> line 603
>>
>> I realize this is very vague, but maybe you have any idea where that
>> could be coming from ? Those tests have been pretty stable for the last
>> couple month. I'll take a closer look in the coming days, but in the
>> meantime, I thought I'd give a heads up ;-)
>
> Could you provide me a test case so I can go further? I reverted 72650 for 
> now.
> Thanks,
>
> -- 
> Bruno Cardoso Lopes
> http://www.brunocardoso.cc
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits 



From evan.cheng at apple.com  Wed Jun  3 20:15:29 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 04 Jun 2009 01:15:29 -0000
Subject: [llvm-commits] [llvm] r72826 - in /llvm/trunk:
 lib/Target/ARM/ARMLoadStoreOptimizer.cpp test/CodeGen/ARM/str_pre-2.ll
Message-ID: <200906040115.n541FTxo006470@zion.cs.uiuc.edu>

Author: evancheng
Date: Wed Jun  3 20:15:28 2009
New Revision: 72826

URL: http://llvm.org/viewvc/llvm-project?rev=72826&view=rev
Log:
Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.

Modified:
    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    llvm/trunk/test/CodeGen/ARM/str_pre-2.ll

Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=72826&r1=72825&r2=72826&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed Jun  3 20:15:28 2009
@@ -530,7 +530,7 @@
     if (isAM2)
       // STR_PRE, STR_POST;
       BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
-        .addReg(MO.getReg(), getKillRegState(BaseKill))
+        .addReg(MO.getReg(), getKillRegState(MO.isKill()))
         .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
     else
       // FSTMS, FSTMD
@@ -709,6 +709,13 @@
 
         // RS may be pointing to an instruction that's deleted. 
         RS->skipTo(prior(MBBI));
+      } else if (NumMemOps == 1) {
+        // Try folding preceeding/trailing base inc/dec into the single
+        // load/store.
+        if (mergeBaseUpdateLoadStore(MBB, MemOps[0].MBBI, TII, Advance, MBBI)) {
+          ++NumMerges;
+          RS->forward(prior(MBBI));
+        }
       }
 
       CurrBase = 0;

Modified: llvm/trunk/test/CodeGen/ARM/str_pre-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/str_pre-2.ll?rev=72826&r1=72825&r2=72826&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/str_pre-2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/str_pre-2.ll Wed Jun  3 20:15:28 2009
@@ -1,6 +1,5 @@
 ; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu | grep {str.*\\!}
 ; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #+4}
-; XFAIL: *
 
 @b = external global i64*
 




From gohman at apple.com  Wed Jun  3 20:59:35 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 04 Jun 2009 01:59:35 -0000
Subject: [llvm-commits] [llvm] r72828 -
	/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
Message-ID: <200906040159.n541xall008563@zion.cs.uiuc.edu>

Author: djg
Date: Wed Jun  3 20:59:35 2009
New Revision: 72828

URL: http://llvm.org/viewvc/llvm-project?rev=72828&view=rev
Log:
Remove a #include of .

Modified:
    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=72828&r1=72827&r2=72828&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Jun  3 20:59:35 2009
@@ -40,7 +40,6 @@
 #include 
 #include 
 #include 
-#include 
 
 using namespace llvm;
 




From eli.friedman at gmail.com  Wed Jun  3 21:02:02 2009
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 04 Jun 2009 02:02:02 -0000
Subject: [llvm-commits] [llvm] r72830 - in /llvm/trunk:
 lib/Target/X86/X86RegisterInfo.cpp
 test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
Message-ID: <200906040202.n542223Z008664@zion.cs.uiuc.edu>

Author: efriedma
Date: Wed Jun  3 21:02:01 2009
New Revision: 72830

URL: http://llvm.org/viewvc/llvm-project?rev=72830&view=rev
Log:
PR3739, part 1: Disable the red zone on Win64.


Added:
    llvm/trunk/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
Modified:
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=72830&r1=72829&r2=72830&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Jun  3 21:02:01 2009
@@ -754,7 +754,8 @@
   if (Is64Bit && !DisableRedZone &&
       !needsStackRealignment(MF) &&
       !MFI->hasVarSizedObjects() &&                // No dynamic alloca.
-      !MFI->hasCalls()) {                          // No calls.
+      !MFI->hasCalls() &&                          // No calls.
+      !Subtarget->isTargetWin64()) {               // Win64 has no Red Zone
     uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
     if (hasFP(MF)) MinSize += SlotSize;
     StackSize = std::max(MinSize,

Added: llvm/trunk/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll?rev=72830&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll Wed Jun  3 21:02:01 2009
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc | grep "subq.*\\\$8, \\\%rsp"
+target triple = "x86_64-mingw64"
+
+define x86_fp80 @a(i64 %x) nounwind readnone {
+entry:
+	%conv = sitofp i64 %x to x86_fp80		;  [#uses=1]
+	ret x86_fp80 %conv
+}
+




From eli.friedman at gmail.com  Wed Jun  3 21:32:04 2009
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 04 Jun 2009 02:32:04 -0000
Subject: [llvm-commits] [llvm] r72836 - in /llvm/trunk:
 lib/Target/X86/X86InstrInfo.cpp
 test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
Message-ID: <200906040232.n542W4Xl009692@zion.cs.uiuc.edu>

Author: efriedma
Date: Wed Jun  3 21:32:04 2009
New Revision: 72836

URL: http://llvm.org/viewvc/llvm-project?rev=72836&view=rev
Log:
PR3739, part 2: Use an explicit store to spill XMM registers. (Previously,
the code tried to use "push", which doesn't exist for XMM registers.)


Added:
    llvm/trunk/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=72836&r1=72835&r2=72836&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Jun  3 21:32:04 2009
@@ -2009,16 +2009,24 @@
 
   MachineFunction &MF = *MBB.getParent();
   X86MachineFunctionInfo *X86FI = MF.getInfo();
-  X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
+  unsigned CalleeFrameSize = 0;
   
   unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
   for (unsigned i = CSI.size(); i != 0; --i) {
     unsigned Reg = CSI[i-1].getReg();
+    const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
     // Add the callee-saved register as live-in. It's killed at the spill.
     MBB.addLiveIn(Reg);
-    BuildMI(MBB, MI, DL, get(Opc))
-      .addReg(Reg, RegState::Kill);
+    if (RegClass != &X86::VR128RegClass) {
+      CalleeFrameSize += SlotSize;
+      BuildMI(MBB, MI, DL, get(Opc))
+        .addReg(Reg, RegState::Kill);
+    } else {
+      storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
+    }
   }
+
+  X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
   return true;
 }
 
@@ -2036,7 +2044,12 @@
   unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     unsigned Reg = CSI[i].getReg();
-    BuildMI(MBB, MI, DL, get(Opc), Reg);
+    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
+    if (RegClass != &X86::VR128RegClass) {
+      BuildMI(MBB, MI, DL, get(Opc), Reg);
+    } else {
+      loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
+    }
   }
   return true;
 }

Added: llvm/trunk/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll?rev=72836&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll Wed Jun  3 21:32:04 2009
@@ -0,0 +1,12 @@
+; RUN: llvm-as < %s | llc -o %t1 -f
+; RUN: grep "subq.*\\\$40, \\\%rsp" %t1
+; RUN: grep "movaps	\\\%xmm8, \\\(\\\%rsp\\\)" %t1
+; RUN: grep "movaps	\\\%xmm7, 16\\\(\\\%rsp\\\)" %t1
+target triple = "x86_64-mingw64"
+
+define i32 @a() nounwind {
+entry:
+	tail call void asm sideeffect "", "~{xmm7},~{xmm8},~{dirflag},~{fpsr},~{flags}"() nounwind
+	ret i32 undef
+}
+




From ofv at wanadoo.es  Wed Jun  3 21:46:08 2009
From: ofv at wanadoo.es (=?windows-1252?Q?=D3scar_Fuentes?=)
Date: Thu, 04 Jun 2009 04:46:08 +0200
Subject: [llvm-commits] LLVM on MinGW on XP
References: <9719867c0906031432w2eef1cd3s92ce5c4c9c9948fc@mail.gmail.com>
Message-ID: <87ljo8iumn.fsf@telefonica.net>

Aaron Gray 
writes:

> Is there anyway to run 'make test' on MinGW ?
>
> It requites dejaGNU and expect, but looking on the web there are only dead
> ends to getting them running on MinGW.

IIRC, mingw developers used to run 'make test' for mingw's gcc using
cygwin. Some people used to report build&test results for mingw to the
gcc and binutils mailing lists. Maybe asking on the mingw dev's mailing
list...

-- 
?scar



From nicholas at mxc.ca  Wed Jun  3 22:30:14 2009
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 03 Jun 2009 20:30:14 -0700
Subject: [llvm-commits] [PATCH] simplify OnlyCalledDirectly()
In-Reply-To: 
References: 
Message-ID: <4A273FC6.4090907@mxc.ca>

Jay Foad wrote:
> An obvious cleanup, I think. Passes "make check". OK to apply?

Looks good.

I'd rather it were a method on Function, I keep wanting to check this 
and forgetting the efficient method of doing it (most recently in 
CXAGuardElim).

Nick



From clattner at apple.com  Thu Jun  4 00:05:34 2009
From: clattner at apple.com (Chris Lattner)
Date: Wed, 3 Jun 2009 22:05:34 -0700
Subject: [llvm-commits] [llvm] r72811 - in /llvm/trunk:
	include/llvm/Support/StandardPasses.h
	tools/llvm-ld/Optimize.cpp tools/lto/LTOCodeGenerator.cpp
In-Reply-To: <200906032151.n53LpWET030337@zion.cs.uiuc.edu>
References: <200906032151.n53LpWET030337@zion.cs.uiuc.edu>
Message-ID: <135833FD-0E2C-467A-B6A3-AA8D7133D5B3@apple.com>


On Jun 3, 2009, at 2:51 PM, Daniel Dunbar wrote:

> Author: ddunbar
> Date: Wed Jun  3 16:51:32 2009
> New Revision: 72811
>
> URL: http://llvm.org/viewvc/llvm-project?rev=72811&view=rev
> Log:
> Change LTO to run the global opt pass twice.
> - This matches llvm-ld.
>
> It took a bit of archeology to figure out what the right thing to do  
> was
> (whether this was intentionally added or intentionally removed). My  
> final
> conclusion is that Chris added this intentionally here:
>  http://llvm.org/viewvc/llvm-project?view=rev&revision=16913
> but the changes weren't propogated to llvm-ld until here:
>  http://llvm.org/viewvc/llvm-project?view=rev&revision=34058
> which was after lto.cpp had been cloned off (of llvm-ld), here:
>  http://llvm.org/viewvc/llvm-project?view=rev&revision=29494
>
>> From the commit message, it looks like the motivation for running  
>> global opt
> again is because we ran it prior to inlining. Based on that I  
> updated the
> comment and also only run the pass if we actually ran the inliner.

Sounds fine to me! GlobalOpt is quite cheap.

-Chris


From baldrick at free.fr  Thu Jun  4 00:18:28 2009
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 04 Jun 2009 07:18:28 +0200
Subject: [llvm-commits] [llvm-gcc-4.2] r72804
	-	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
In-Reply-To: <200906032049.n53KnZVm027957@zion.cs.uiuc.edu>
References: <200906032049.n53KnZVm027957@zion.cs.uiuc.edu>
Message-ID: <4A275924.2070809@free.fr>

Hi Bill,

> Set the alignment of STRING_CSTs to be that which GCC expects it to be. We were
> setting it to a default that made the alignment much larger than it needed to
> be and wasting space.

I would have expected LLVM to give strings an alignment of 1.  Is that
not so?

Ciao,

Duncan.


From isanbard at gmail.com  Thu Jun  4 01:57:40 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 3 Jun 2009 23:57:40 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r72804
	-	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
In-Reply-To: <4A275924.2070809@free.fr>
References: <200906032049.n53KnZVm027957@zion.cs.uiuc.edu>
	<4A275924.2070809@free.fr>
Message-ID: 

On Jun 3, 2009, at 10:18 PM, Duncan Sands wrote:

> Hi Bill,
>
>> Set the alignment of STRING_CSTs to be that which GCC expects it to  
>> be. We were
>> setting it to a default that made the alignment much larger than it  
>> needed to
>> be and wasting space.
>
> I would have expected LLVM to give strings an alignment of 1.  Is that
> not so?
>
No. At this point, before my patch, the alignment wasn't being set.  
During code generation, it defaults (through a series of calls) to a  
"preferred alignment" of 16 bytes.

-bw


From clattner at apple.com  Thu Jun  4 02:00:34 2009
From: clattner at apple.com (Chris Lattner)
Date: Thu, 4 Jun 2009 00:00:34 -0700
Subject: [llvm-commits] [PATCH] ANSI colors for clang!
In-Reply-To: <4A241C07.20309@gmail.com>
References: <4A211D99.1050104@gmail.com>
	<6570BAAF-67FF-4033-B496-1A078CC65B61@apple.com>
	<4A22DE44.9010406@gmail.com> <4A241C07.20309@gmail.com>
Message-ID: <5E245E68-22A0-4217-9F7D-FDB5D6213777@apple.com>

On Jun 1, 2009, at 11:20 AM, T?r?k Edwin wrote:
>>> A lot of the complexity of the patch looks like it has to do with
>>> Windows support.  Please find someone with a real VC++ build to  
>>> verify
>>> that it actually works :)
>>>
>
> I've tested it myself on VC++2k8 Express, by generating a .sln using
> cmake-gui
> (Express edition didn't like the .sln in win32/, but worked fine with
> the one from cmake).
> Apart from a compilation failure in ilist.h (solved by the attached
> patch) everything went smoothly,
> and my (blindly) written color support for win32 consoles actually
> worked the first time I tried:
> it printed an error that it can't find string.h in color!

Ok, other questions:

+raw_ostream &raw_fd_ostream::resetColor() {
+  if (sys::Process::ColorNeedsFlush())
+    flush();
+  const char *colorcode = sys::Process::ResetColor();
+  if (colorcode) {
+    unsigned len = strlen(colorcode);
+    write(colorcode, len);
+    // don't account colors towards output characters
+    pos -= len;
+  }
+  return *this;

Is write followed by subtracting from "pos" really safe here?  What if  
write doesn't do a flush?  Does it matter?

+const char *Process::OutputColor(char code, bool bold, bool bg) {
+  const char *ret = colorcodes[bg?1:0][bold?1:0][code&7];
+  return ret;

How about "return colorcodes[..."


Otherwise, looks great!  Please apply after addressing the two things  
above (if needed).  Thanks Edwin,

-Chris


From edwintorok at gmail.com  Thu Jun  4 02:09:50 2009
From: edwintorok at gmail.com (Torok Edwin)
Date: Thu, 04 Jun 2009 07:09:50 -0000
Subject: [llvm-commits] [llvm] r72854 - in /llvm/trunk:
 include/llvm/Support/raw_ostream.h include/llvm/System/Process.h
 lib/Support/raw_ostream.cpp lib/System/Unix/Process.inc
 lib/System/Win32/Process.inc
Message-ID: <200906040709.n5479ods018533@zion.cs.uiuc.edu>

Author: edwin
Date: Thu Jun  4 02:09:50 2009
New Revision: 72854

URL: http://llvm.org/viewvc/llvm-project?rev=72854&view=rev
Log:
Add support for outputting ANSI colors to raw_fd_ostream.

Modified:
    llvm/trunk/include/llvm/Support/raw_ostream.h
    llvm/trunk/include/llvm/System/Process.h
    llvm/trunk/lib/Support/raw_ostream.cpp
    llvm/trunk/lib/System/Unix/Process.inc
    llvm/trunk/lib/System/Win32/Process.inc

Modified: llvm/trunk/include/llvm/Support/raw_ostream.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/raw_ostream.h?rev=72854&r1=72853&r2=72854&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/raw_ostream.h (original)
+++ llvm/trunk/include/llvm/Support/raw_ostream.h Thu Jun  4 02:09:50 2009
@@ -45,6 +45,19 @@
   bool Unbuffered;
 
 public:
+  // color order matches ANSI escape sequence, don't change
+  enum Colors {
+    BLACK=0,
+    RED,
+    GREEN,
+    YELLOW,
+    BLUE,
+    MAGENTA,
+    CYAN,
+    WHITE,
+    SAVEDCOLOR
+  };
+
   explicit raw_ostream(bool unbuffered=false) : Unbuffered(unbuffered) {
     // Start out ready to flush.
     OutBufStart = OutBufEnd = OutBufCur = 0;
@@ -167,6 +180,20 @@
   // Formatted output, see the format() function in Support/Format.h.
   raw_ostream &operator<<(const format_object_base &Fmt);
 
+  /// Changes the foreground color of text that will be output from this point
+  /// forward.
+  /// @param colors ANSI color to use, the special SAVEDCOLOR can be used to
+  /// change only the bold attribute, and keep colors untouched
+  /// @param bold bold/brighter text, default false
+  /// @param bg if true change the background, default: change foreground
+  /// @returns itself so it can be used within << invocations
+  virtual raw_ostream &changeColor(enum Colors colors, bool bold=false,
+                                   bool  bg=false) { return *this; }
+
+  /// Resets the colors to terminal defaults. Call this when you are done
+  /// outputting colored text, or before program exit.
+  virtual raw_ostream &resetColor() { return *this; }
+
   //===--------------------------------------------------------------------===//
   // Subclass Interface
   //===--------------------------------------------------------------------===//
@@ -243,6 +270,10 @@
   /// seek - Flushes the stream and repositions the underlying file descriptor
   ///  positition to the offset specified from the beginning of the file.
   uint64_t seek(uint64_t off);
+
+  virtual raw_ostream &changeColor(enum Colors colors, bool bold=false,
+                                   bool bg=false);
+  virtual raw_ostream &resetColor();
 };
 
 /// raw_stdout_ostream - This is a stream that always prints to stdout.

Modified: llvm/trunk/include/llvm/System/Process.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Process.h?rev=72854&r1=72853&r2=72854&view=diff

==============================================================================
--- llvm/trunk/include/llvm/System/Process.h (original)
+++ llvm/trunk/include/llvm/System/Process.h Thu Jun  4 02:09:50 2009
@@ -107,6 +107,35 @@
       /// console, or if the number of columns cannot be determined,
       /// this routine returns zero.
       static unsigned StandardErrColumns();
+
+      /// This function determines whether the terminal connected to standard
+      /// output supports colors. If standard output is not connected to a
+      /// terminal, this function returns false.
+      static bool StandardOutHasColors();
+
+      /// This function determines whether the terminal connected to standard
+      /// error supports colors. If standard error is not connected to a
+      /// terminal, this function returns false.
+      static bool StandardErrHasColors();
+
+      /// Whether changing colors requires the output to be flushed.
+      /// This is needed on systems that don't support escape sequences for
+      /// changing colors.
+      static bool ColorNeedsFlush();
+
+      /// This function returns the colorcode escape sequences, and sets Len to
+      /// the length of the escape sequence.
+      /// If ColorNeedsFlush() is true then this function will change the colors
+      /// and return an empty escape sequence. In that case it is the
+      /// responsibility of the client to flush the output stream prior to
+      /// calling this function.
+      static const char *OutputColor(char c, bool bold, bool bg);
+
+      /// Same as OutputColor, but only enables the bold attribute.
+      static const char *OutputBold(bool bg);
+
+      /// Resets the terminals colors, or returns an escape sequence to do so.
+      static const char *ResetColor();
     /// @}
   };
 }

Modified: llvm/trunk/lib/Support/raw_ostream.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/raw_ostream.cpp?rev=72854&r1=72853&r2=72854&view=diff

==============================================================================
--- llvm/trunk/lib/Support/raw_ostream.cpp (original)
+++ llvm/trunk/lib/Support/raw_ostream.cpp Thu Jun  4 02:09:50 2009
@@ -14,6 +14,7 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Support/Format.h"
 #include "llvm/System/Program.h"
+#include "llvm/System/Process.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Config/config.h"
 #include "llvm/Support/Compiler.h"
@@ -301,6 +302,35 @@
   return pos;  
 }
 
+raw_ostream &raw_fd_ostream::changeColor(enum Colors colors, bool bold,
+                                         bool bg) {
+  if (sys::Process::ColorNeedsFlush())
+    flush();
+  const char *colorcode =
+    (colors == SAVEDCOLOR) ? sys::Process::OutputBold(bg)
+    : sys::Process::OutputColor(colors, bold, bg);
+  if (colorcode) {
+    unsigned len = strlen(colorcode);
+    write(colorcode, len);
+    // don't account colors towards output characters
+    pos -= len;
+  }
+  return *this;
+}
+
+raw_ostream &raw_fd_ostream::resetColor() {
+  if (sys::Process::ColorNeedsFlush())
+    flush();
+  const char *colorcode = sys::Process::ResetColor();
+  if (colorcode) {
+    unsigned len = strlen(colorcode);
+    write(colorcode, len);
+    // don't account colors towards output characters
+    pos -= len;
+  }
+  return *this;
+}
+
 //===----------------------------------------------------------------------===//
 //  raw_stdout/err_ostream
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/System/Unix/Process.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Process.inc?rev=72854&r1=72853&r2=72854&view=diff

==============================================================================
--- llvm/trunk/lib/System/Unix/Process.inc (original)
+++ llvm/trunk/lib/System/Unix/Process.inc Thu Jun  4 02:09:50 2009
@@ -235,3 +235,62 @@
 
   return getColumns(2);
 }
+
+static bool terminalHasColors() {
+  if (const char *term = std::getenv("TERM")) {
+    // Most modern terminals support ANSI escape sequences for colors.
+    // We could check terminfo, or have a list of known terms that support
+    // colors, but that would be overkill.
+    // The user can always ask for no colors by setting TERM to dumb, or
+    // using a commandline flag.
+    return strcmp(term, "dumb") != 0;
+  }
+  return false;
+}
+
+bool Process::StandardOutHasColors() {
+  if (!StandardOutIsDisplayed())
+    return false;
+  return terminalHasColors();
+}
+
+bool Process::StandardErrHasColors() {
+  if (!StandardErrIsDisplayed())
+    return false;
+  return terminalHasColors();
+}
+
+bool Process::ColorNeedsFlush() {
+  // No, we use ANSI escape sequences.
+  return false;
+}
+
+#define COLOR(FGBG, CODE, BOLD) "\033[0;" BOLD FGBG CODE "m"
+
+#define ALLCOLORS(FGBG,BOLD) {\
+    COLOR(FGBG, "0", BOLD),\
+    COLOR(FGBG, "1", BOLD),\
+    COLOR(FGBG, "2", BOLD),\
+    COLOR(FGBG, "3", BOLD),\
+    COLOR(FGBG, "4", BOLD),\
+    COLOR(FGBG, "5", BOLD),\
+    COLOR(FGBG, "6", BOLD),\
+    COLOR(FGBG, "7", BOLD)\
+  }
+
+static const char* colorcodes[2][2][8] = {
+ { ALLCOLORS("3",""), ALLCOLORS("3","1;") },
+ { ALLCOLORS("4",""), ALLCOLORS("4","1;") }
+};
+
+const char *Process::OutputColor(char code, bool bold, bool bg) {
+  return colorcodes[bg?1:0][bold?1:0][code&7];
+}
+
+const char *Process::OutputBold(bool bg) {
+  return "\033[1m";
+}
+
+const char *Process::ResetColor() {
+  return "\033[0m";
+}

Modified: llvm/trunk/lib/System/Win32/Process.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Process.inc?rev=72854&r1=72853&r2=72854&view=diff

==============================================================================
--- llvm/trunk/lib/System/Win32/Process.inc (original)
+++ llvm/trunk/lib/System/Win32/Process.inc Thu Jun  4 02:09:50 2009
@@ -147,4 +147,70 @@
   return Columns;
 }
 
+// it always has colors
+bool Process::StandardErrHasColors() {
+  return StandardErrIsDisplayed();
+}
+
+bool Process::StandardOutHasColors() {
+  return StandardOutIsDisplayed();
+}
+namespace {
+class DefaultColors
+{
+  private:
+    WORD defaultColor;
+  public:
+    DefaultColors()
+     :defaultColor(GetCurrentColor()) {}
+    static unsigned GetCurrentColor() {
+      CONSOLE_SCREEN_BUFFER_INFO csbi;
+      if (GetConsoleScreenBufferInfo(GetStdHandle(STD_OUTPUT_HANDLE), &csbi))
+        return csbi.wAttributes;
+      return 0;
+    }
+    WORD operator()() const { return defaultColor; }
+};
+
+DefaultColors defaultColors;
+}
+
+bool Process::ColorNeedsFlush() {
+  return true;
+}
+
+const char *Process::OutputBold(bool bg) {
+  WORD colors = DefaultColors::GetCurrentColor();
+  if (bg)
+    colors |= BACKGROUND_INTENSITY;
+  else
+    colors |= FOREGROUND_INTENSITY;
+  SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), colors);
+  return 0;
+}
+
+const char *Process::OutputColor(char code, bool bold, bool bg) {
+  WORD colors;
+  if (bg) {
+    colors = ((code&1) ? BACKGROUND_RED : 0) |
+      ((code&2) ? BACKGROUND_GREEN : 0 ) |
+      ((code&4) ? BACKGROUND_BLUE : 0);
+    if (bold)
+      colors |= BACKGROUND_INTENSITY;
+  } else {
+    colors = ((code&1) ? FOREGROUND_RED : 0) |
+      ((code&2) ? FOREGROUND_GREEN : 0 ) |
+      ((code&4) ? FOREGROUND_BLUE : 0);
+    if (bold)
+      colors |= FOREGROUND_INTENSITY;
+  }
+  SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), colors);
+  return 0;
+}
+
+const char *Process::ResetColor() {
+  SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), defaultColors());
+  return 0;
+}
+
 }




From edwintorok at gmail.com  Thu Jun  4 02:11:40 2009
From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=)
Date: Thu, 04 Jun 2009 10:11:40 +0300
Subject: [llvm-commits] [PATCH] ANSI colors for clang!
In-Reply-To: <5E245E68-22A0-4217-9F7D-FDB5D6213777@apple.com>
References: <4A211D99.1050104@gmail.com>
	<6570BAAF-67FF-4033-B496-1A078CC65B61@apple.com>
	<4A22DE44.9010406@gmail.com> <4A241C07.20309@gmail.com>
	<5E245E68-22A0-4217-9F7D-FDB5D6213777@apple.com>
Message-ID: <4A2773AC.3020903@gmail.com>

On 2009-06-04 10:00, Chris Lattner wrote:
> On Jun 1, 2009, at 11:20 AM, T?r?k Edwin wrote:
>>>> A lot of the complexity of the patch looks like it has to do with
>>>> Windows support.  Please find someone with a real VC++ build to verify
>>>> that it actually works :)
>>>>
>>
>> I've tested it myself on VC++2k8 Express, by generating a .sln using
>> cmake-gui
>> (Express edition didn't like the .sln in win32/, but worked fine with
>> the one from cmake).
>> Apart from a compilation failure in ilist.h (solved by the attached
>> patch) everything went smoothly,
>> and my (blindly) written color support for win32 consoles actually
>> worked the first time I tried:
>> it printed an error that it can't find string.h in color!
>
> Ok, other questions:
>
> +raw_ostream &raw_fd_ostream::resetColor() {
> +  if (sys::Process::ColorNeedsFlush())
> +    flush();
> +  const char *colorcode = sys::Process::ResetColor();
> +  if (colorcode) {
> +    unsigned len = strlen(colorcode);
> +    write(colorcode, len);
> +    // don't account colors towards output characters
> +    pos -= len;
> +  }
> +  return *this;
>
> Is write followed by subtracting from "pos" really safe here?  What if
> write doesn't do a flush?  

If it does a flush it is as if the write didn't happen at all, hence safe.
> Does it matter?

pos is not exposed publicly, its only exposed via tell(), which is pos +
numbytesinbuffer.
Even if pos wraps because there was no flush, tell() will still return
the correct result, and pos isn't used anywhere else.

>
> +const char *Process::OutputColor(char code, bool bold, bool bg) {
> +  const char *ret = colorcodes[bg?1:0][bold?1:0][code&7];
> +  return ret;
>
> How about "return colorcodes[..."

Yeah, I missed that while deleting a parameter ;)

>
>
> Otherwise, looks great!  Please apply after addressing the two things
> above (if needed).  Thanks Edwin,

Thanks, applied.

Best regards,
--Edwin


From baldrick at free.fr  Thu Jun  4 02:37:35 2009
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 04 Jun 2009 09:37:35 +0200
Subject: [llvm-commits] [llvm-gcc-4.2]
	r72804	-	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
In-Reply-To: 
References: <200906032049.n53KnZVm027957@zion.cs.uiuc.edu>	<4A275924.2070809@free.fr>
	
Message-ID: <4A2779BF.1020402@free.fr>

Hi Bill,

>> I would have expected LLVM to give strings an alignment of 1.  Is that
>> not so?
>>
> No. At this point, before my patch, the alignment wasn't being set.  
> During code generation, it defaults (through a series of calls) to a  
> "preferred alignment" of 16 bytes.

maybe that's a bug?  16 byte alignment seems an awful lot for a string.

Ciao,

Duncan.


From baldrick at free.fr  Thu Jun  4 02:49:14 2009
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 04 Jun 2009 09:49:14 +0200
Subject: [llvm-commits] [llvm] r72854 - in /llvm/trunk:
 include/llvm/Support/raw_ostream.h include/llvm/System/Process.h
 lib/Support/raw_ostream.cpp lib/System/Unix/Process.inc
 lib/System/Win32/Process.inc
In-Reply-To: <200906040709.n5479ods018533@zion.cs.uiuc.edu>
References: <200906040709.n5479ods018533@zion.cs.uiuc.edu>
Message-ID: <4A277C7A.8060406@free.fr>

Hi Edwin,

> +      /// This function returns the colorcode escape sequences, and sets Len to
> +      /// the length of the escape sequence.

what is Len?  It's not a parameter of OutputColor at least.

> +      static const char *OutputColor(char c, bool bold, bool bg);
> +
> +      /// Same as OutputColor, but only enables the bold attribute.
> +      static const char *OutputBold(bool bg);

I see that OutputColor takes the character 'c' but OutputBold doesn't.
Is that future proof?

> +// it always has colors

it -> It
Missing fullstop at end of comment.

> +bool Process::StandardOutHasColors() {
> +  return StandardOutIsDisplayed();
> +}
> +namespace {

Missing blank line before namespace.

Ciao,

Duncan.


From edwintorok at gmail.com  Thu Jun  4 03:18:25 2009
From: edwintorok at gmail.com (Torok Edwin)
Date: Thu, 04 Jun 2009 08:18:25 -0000
Subject: [llvm-commits] [llvm] r72858 - in /llvm/trunk:
 include/llvm/System/Process.h lib/System/Win32/Process.inc
Message-ID: <200906040818.n548IPYV031838@zion.cs.uiuc.edu>

Author: edwin
Date: Thu Jun  4 03:18:25 2009
New Revision: 72858

URL: http://llvm.org/viewvc/llvm-project?rev=72858&view=rev
Log:
Fix comments.

Modified:
    llvm/trunk/include/llvm/System/Process.h
    llvm/trunk/lib/System/Win32/Process.inc

Modified: llvm/trunk/include/llvm/System/Process.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Process.h?rev=72858&r1=72857&r2=72858&view=diff

==============================================================================
--- llvm/trunk/include/llvm/System/Process.h (original)
+++ llvm/trunk/include/llvm/System/Process.h Thu Jun  4 03:18:25 2009
@@ -123,8 +123,7 @@
       /// changing colors.
       static bool ColorNeedsFlush();
 
-      /// This function returns the colorcode escape sequences, and sets Len to
-      /// the length of the escape sequence.
+      /// This function returns the colorcode escape sequences.
       /// If ColorNeedsFlush() is true then this function will change the colors
       /// and return an empty escape sequence. In that case it is the
       /// responsibility of the client to flush the output stream prior to

Modified: llvm/trunk/lib/System/Win32/Process.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Process.inc?rev=72858&r1=72857&r2=72858&view=diff

==============================================================================
--- llvm/trunk/lib/System/Win32/Process.inc (original)
+++ llvm/trunk/lib/System/Win32/Process.inc Thu Jun  4 03:18:25 2009
@@ -147,7 +147,7 @@
   return Columns;
 }
 
-// it always has colors
+// It always has colors.
 bool Process::StandardErrHasColors() {
   return StandardErrIsDisplayed();
 }
@@ -155,6 +155,7 @@
 bool Process::StandardOutHasColors() {
   return StandardOutIsDisplayed();
 }
+
 namespace {
 class DefaultColors
 {




From edwintorok at gmail.com  Thu Jun  4 03:23:07 2009
From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=)
Date: Thu, 04 Jun 2009 11:23:07 +0300
Subject: [llvm-commits] [llvm] r72854 - in /llvm/trunk:
 include/llvm/Support/raw_ostream.h include/llvm/System/Process.h
 lib/Support/raw_ostream.cpp lib/System/Unix/Process.inc
 lib/System/Win32/Process.inc
In-Reply-To: <4A277C7A.8060406@free.fr>
References: <200906040709.n5479ods018533@zion.cs.uiuc.edu>
	<4A277C7A.8060406@free.fr>
Message-ID: <4A27846B.4020805@gmail.com>

On 2009-06-04 10:49, Duncan Sands wrote:
> Hi Edwin,
>
>   
>> +      /// This function returns the colorcode escape sequences, and sets Len to
>> +      /// the length of the escape sequence.
>>     
>
> what is Len?  It's not a parameter of OutputColor at least.
>   

It was removed, I updated the comment.

>   
>> +      static const char *OutputColor(char c, bool bold, bool bg);
>> +
>> +      /// Same as OutputColor, but only enables the bold attribute.
>> +      static const char *OutputBold(bool bg);
>>     
>
> I see that OutputColor takes the character 'c' but OutputBold doesn't.
> Is that future proof?
>   

OutputBold only changes the bold attribute and keeps the color intact, I
don't see what we could use
'c' for.
On Unix it simply outputs the escape sequence to turn bold on,
on Win32 queries the current attributes, turns intensity on, and changes
attributes.

>   
>> +// it always has colors
>>     
>
> it -> It
> Missing fullstop at end of comment.
>
>   
>> +bool Process::StandardOutHasColors() {
>> +  return StandardOutIsDisplayed();
>> +}
>> +namespace {
>>     
>
> Missing blank line before namespace.
>
>   

Thanks Duncan!

--Edwin


From sanjiv.gupta at microchip.com  Thu Jun  4 03:52:35 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Thu, 04 Jun 2009 08:52:35 -0000
Subject: [llvm-commits] [llvm] r72861 -
	/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
Message-ID: <200906040852.n548qaWU000502@zion.cs.uiuc.edu>

Author: sgupta
Date: Thu Jun  4 03:52:28 2009
New Revision: 72861

URL: http://llvm.org/viewvc/llvm-project?rev=72861&view=rev
Log:
Custom lower SUB with two register operands.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=72861&r1=72860&r2=72861&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Thu Jun  4 03:52:28 2009
@@ -105,6 +105,7 @@
   setOperationAction(ISD::ADDC,    MVT::i8,  Custom);
   setOperationAction(ISD::SUBE,    MVT::i8,  Custom);
   setOperationAction(ISD::SUBC,    MVT::i8,  Custom);
+  setOperationAction(ISD::SUB,    MVT::i8,  Custom);
   setOperationAction(ISD::ADD,    MVT::i8,  Custom);
   setOperationAction(ISD::ADD,    MVT::i16, Custom);
 




From ofv at wanadoo.es  Thu Jun  4 04:26:44 2009
From: ofv at wanadoo.es (Oscar Fuentes)
Date: Thu, 04 Jun 2009 09:26:44 -0000
Subject: [llvm-commits] [llvm] r72864 - in /llvm/trunk: CMakeLists.txt
	docs/CMake.html
Message-ID: <200906040926.n549QkeZ002311@zion.cs.uiuc.edu>

Author: ofv
Date: Thu Jun  4 04:26:16 2009
New Revision: 72864

URL: http://llvm.org/viewvc/llvm-project?rev=72864&view=rev
Log:
CMake: Renamed LLVM_ENABLE_ASSERTS to
LLVM_ENABLE_ASSERTIONS. Fine-tuned the logic that controls the
definition of NDEBUG and _DEBUG macros.

Thanks to Jay Foad for this suggestions.

Modified:
    llvm/trunk/CMakeLists.txt
    llvm/trunk/docs/CMake.html

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=72864&r1=72863&r2=72864&view=diff

==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Thu Jun  4 04:26:16 2009
@@ -58,13 +58,22 @@
 option(LLVM_ENABLE_THREADS "Use threads if available." ON)
 
 if( uppercase_CMAKE_BUILD_TYPE STREQUAL "RELEASE" )
-  option(LLVM_ENABLE_ASSERTS "Enable asserts" OFF)
+  option(LLVM_ENABLE_ASSERTIONS "Enable assertions" OFF)
 else()
-  option(LLVM_ENABLE_ASSERTS "Enable asserts" ON)
+  option(LLVM_ENABLE_ASSERTIONS "Enable assertions" ON)
 endif()
 
-if( LLVM_ENABLE_ASSERTS )
-  add_definitions( -D_DEBUG -UNDEBUG )
+if( LLVM_ENABLE_ASSERTIONS )
+  add_definitions( -D_DEBUG )
+  # On Release builds cmake automatically defines NDEBUG, so we
+  # explicitly undefine it:
+  if( uppercase_CMAKE_BUILD_TYPE STREQUAL "RELEASE" )
+    add_definitions( -UNDEBUG )
+  endif()
+else()
+  if( NOT uppercase_CMAKE_BUILD_TYPE STREQUAL "RELEASE" )
+    add_definitions( -DNDEBUG )
+  endif()
 endif()
 
 if( LLVM_TARGETS_TO_BUILD STREQUAL "all" )

Modified: llvm/trunk/docs/CMake.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CMake.html?rev=72864&r1=72863&r2=72864&view=diff

==============================================================================
--- llvm/trunk/docs/CMake.html (original)
+++ llvm/trunk/docs/CMake.html Thu Jun  4 04:26:16 2009
@@ -248,8 +248,8 @@
   
    LLVM_ENABLE_THREADS:BOOL
    
   
    Build with threads support, if available. Defaults to ON.
    
 
-  
    LLVM_ENABLE_ASSERTS:BOOL
    
-  
    Enables code asserts. Defaults to ON if and only if
+  
    LLVM_ENABLE_ASSERTIONS:BOOL
    
+  
    Enables code assertions. Defaults to ON if and only if
     CMAKE_BUILD_TYPE is Release.
    
 
   
    LLVM_ENABLE_PIC:BOOL
    




From espindola at google.com  Thu Jun  4 04:36:23 2009
From: espindola at google.com (Rafael Espindola)
Date: Thu, 4 Jun 2009 10:36:23 +0100
Subject: [llvm-commits] [llvm] r72773 - /llvm/trunk/docs/GoldPlugin.html
In-Reply-To: <4A26C628.5060709@gmail.com>
References: <200906031506.n53F6JOs014297@zion.cs.uiuc.edu>
	<38a0d8450906030911u6ece8f37jef8f887ef719c2c0@mail.gmail.com>
	<4A26A2E5.4@gmail.com>
	<38a0d8450906030928q5e5f8b51le17588675f3bf2cb@mail.gmail.com>
	<4A26A54A.3070201@gmail.com> <4A26C628.5060709@gmail.com>
Message-ID: <38a0d8450906040236m54557addx2ab47574a113f6c8@mail.gmail.com>

> plugin.c does this:
> if (ent->d_type != DT_REG && ent->d_type != DT_LNK)
> ? ?continue;
>
> I am using reiserfs for my /home, and IIRC it doesn't implement the
> d_type field and return DT_UNKNOWN for all files.
> If you get DT_UNKNOWN you should lstat(), and check the result.

Can you please try the attached patch?

> Best regards,
> --Edwin
>


Cheers,
-- 
Rafael Avila de Espindola

Google | Gordon House | Barrow Street | Dublin 4 | Ireland
Registered in Dublin, Ireland | Registration Number: 368047
-------------- next part --------------
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From anon at cs.uiuc.edu  Thu Jun  4 07:28:28 2009
From: anon at cs.uiuc.edu (anon at cs.uiuc.edu)
Date: Thu, 4 Jun 2009 07:28:28 -0500
Subject: [llvm-commits] CVS: llvm-www/demo/DemoInfo.html index.cgi
Message-ID: <200906041228.n54CSSDX009205@zion.cs.uiuc.edu>



Changes in directory llvm-www/demo:

DemoInfo.html updated: 1.2 -> 1.3
index.cgi updated: 1.100 -> 1.101
---
Log message:

Turn on nested function support for C.
Add an option to turn off optimization.
Boost the optimization level to -O3 when
optimizing.


---
Diffs of the changes:  (+42 -14)

 DemoInfo.html |   24 +++++++++++++++++++-----
 index.cgi     |   32 +++++++++++++++++++++++---------
 2 files changed, 42 insertions(+), 14 deletions(-)


Index: llvm-www/demo/DemoInfo.html
diff -u llvm-www/demo/DemoInfo.html:1.2 llvm-www/demo/DemoInfo.html:1.3
--- llvm-www/demo/DemoInfo.html:1.2	Mon Oct  1 17:44:25 2007
+++ llvm-www/demo/DemoInfo.html	Thu Jun  4 07:25:31 2009
@@ -39,19 +39,33 @@
 be easier to understand.
 
    
 
-
    Run link-time optimizer
    
+
    Optimization level
    
 
 
    
+
    
+
+  
    Standard: 
    
+
    
+Select this option to run a standard set of LLVM optimizations.
+
    
+
+  
    LTO: 
    
+
    
 Select this option to run the LLVM link-time optimizer, which is designed to
 optimize across files in your application.  Since the demo page doesn't allow
 you to upload multiple files at once, and does not link in any libraries, we
 configured the demo page optimizer to assume there are no calls 
 coming in from outside the source file, allowing it to optimize more 
-aggressively.
    
-
-
    Note that you have to define 'main' in your program for this 
+aggressively.
+Note that you have to define 'main' in your program for this 
 to make much of a difference.
-
    
+
    
+
+  
    None: 
    
+
    
+Select this option to turn off all optimizations.
+
    
+
    
 
 
    Show detailed pass statistics
    
 


Index: llvm-www/demo/index.cgi
diff -u llvm-www/demo/index.cgi:1.100 llvm-www/demo/index.cgi:1.101
--- llvm-www/demo/index.cgi:1.100	Tue Jun  2 09:59:04 2009
+++ llvm-www/demo/index.cgi	Thu Jun  4 07:25:32 2009
@@ -193,11 +193,12 @@
     -default => 'C'
   ), "
    ";
 
-print $c->checkbox(
-    -name  => 'linkopt',
-    -label => 'Run link-time optimizer',
-    -checked => 'checked'
-  ),' ?
    ';
+print "Optimization level: ",
+  $c->radio_group(
+    -name    => 'optlevel',
+    -values  => [ 'Standard', 'LTO', 'None' ],
+    -default => 'Standard'
+  ),' ?
    ', "
    ";
 
 print $c->checkbox(
     -name  => 'showstats',
@@ -310,6 +311,15 @@
     '.f'    => 'Fortran',
     '.f90'  => 'Fortran'
 );
+my %language_options = (
+    'Java'             => '',
+    'JO99'             => '',
+    'C'                => '-fnested-functions',
+    'C++'              => '',
+    'Fortran'          => '',
+    'preprocessed C'   => '-fnested-functions',
+    'preprocessed C++' => ''
+);
 
 my $uploaded_file_name = $c->param('uploaded_file');
 if ($uploaded_file_name) {
@@ -356,8 +366,12 @@
     #$stats = "-Wa,--stats,--time-passes,--info-output-file=$timerFile"
     $stats = "-ftime-report"
 	if ( $c->param('showstats') );
+
+    my $options = $language_options{ $c->param('language') };
+    $options .= " -O3" if $c->param('optlevel') ne "None";
+
     try_run( "llvm C/C++/Fortran front-end (llvm-gcc)",
-	"llvm-gcc -emit-llvm -msse3 -W -Wall -O2 $stats -o $bytecodeFile -c $inputFile > $outputFile 2>&1",
+	"llvm-gcc -emit-llvm -msse3 -W -Wall $options $stats -o $bytecodeFile -c $inputFile > $outputFile 2>&1",
       $outputFile );
 
     if ( $c->param('showstats') && -s $timerFile ) {
@@ -366,7 +380,7 @@
         print "$HtmlResult\n";
     }
 
-    if ( $c->param('linkopt') ) {
+    if ( $c->param('optlevel') eq 'LTO' ) {
         my $stats      = '';
         my $outputFile = getname(".gccld.out");
         my $timerFile  = getname(".gccld.time");
@@ -440,8 +454,8 @@
         "--- Query: ---\nFrom: ($ip) $host\nInput: $lines lines of $lg\n"
           . "C++ demangle = "
           . ( $c->param('cxxdemangle') ? 1 : 0 )
-          . ", Link opt = "
-          . ( $c->param('linkopt') ? 1 : 0 ) . "\n\n"
+          . ", Opt level = "
+          . ( $c->param('optlevel') ) . "\n\n"
           . ", Show stats = "
           . ( $c->param('showstats') ? 1 : 0 ) . "\n\n"
           . "--- Source: ---\n$source\n"





From sanjiv.gupta at microchip.com  Thu Jun  4 10:16:25 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Thu, 04 Jun 2009 15:16:25 -0000
Subject: [llvm-commits] [llvm] r72866 -
	/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
Message-ID: <200906041516.n54FGPuA015433@zion.cs.uiuc.edu>

Author: sgupta
Date: Thu Jun  4 10:16:24 2009
New Revision: 72866

URL: http://llvm.org/viewvc/llvm-project?rev=72866&view=rev
Log:
Remove unused code.

Modified:
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=72866&r1=72865&r2=72866&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Thu Jun  4 10:16:24 2009
@@ -355,21 +355,11 @@
   FrameIndexSDNode *FR = dyn_cast(SDValue(N,0));
   // FIXME there isn't really debug info here
   DebugLoc dl = FR->getDebugLoc();
-  // FIXME: Not used.
-  // int Index = FR->getIndex();
 
   // Expand FrameIndex like GlobalAddress and ExternalSymbol
   // Also use Offset field for lo and hi parts. The default 
   // offset is zero.
 
-  /*
-  SDValue Offset = DAG.getConstant(0, MVT::i8);
-  SDValue FI = DAG.getTargetFrameIndex(Index, MVT::i8);
-  SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, FI, Offset);
-  SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, FI, Offset);
-  return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
-  */
-
   SDValue ES;
   int FrameOffset;
   SDValue FI = SDValue(N,0);




From sanjiv.gupta at microchip.com  Thu Jun  4 10:14:01 2009
From: sanjiv.gupta at microchip.com (Sanjiv Gupta)
Date: Thu, 04 Jun 2009 20:44:01 +0530
Subject: [llvm-commits] [llvm] r72797
	-	/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
In-Reply-To: <16e5fdf90906031521n19d38455pd0baa2b760c6d989@mail.gmail.com>
References: <200906031907.n53J7kdM023977@zion.cs.uiuc.edu>
	<16e5fdf90906031521n19d38455pd0baa2b760c6d989@mail.gmail.com>
Message-ID: <4A27E4B9.7040007@microchip.com>

Bill Wendling wrote:
> On Wed, Jun 3, 2009 at 12:07 PM, Mike Stump  wrote:
>   
>> Author: mrs
>> Date: Wed Jun  3 14:07:46 2009
>> New Revision: 72797
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=72797&view=rev
>> Log:
>> Make the buildbot see green (to make it easier to spot the next person
>> that puts a new warning in).
>>
>> Modified:
>>    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
>>
>> Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=72797&r1=72796&r2=72797&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Wed Jun  3 14:07:46 2009
>> @@ -354,7 +354,8 @@
>>   FrameIndexSDNode *FR = dyn_cast(SDValue(N,0));
>>   // FIXME there isn't really debug info here
>>   DebugLoc dl = FR->getDebugLoc();
>> -  int Index = FR->getIndex();
>> +  // FIXME: Not used.
>> +  // int Index = FR->getIndex();
>>
>>     
> Hi Mike,
>
> If it's not used, please delete the line instead of commenting it out.
>
> Thanks!
>
> -bw
>
>   
I have deleted that.

- Sanjiv



From edwintorok at gmail.com  Thu Jun  4 11:08:10 2009
From: edwintorok at gmail.com (Torok Edwin)
Date: Thu, 04 Jun 2009 16:08:10 -0000
Subject: [llvm-commits] [llvm] r72867 - /llvm/trunk/docs/GoldPlugin.html
Message-ID: <200906041608.n54G8AsE017173@zion.cs.uiuc.edu>

Author: edwin
Date: Thu Jun  4 11:08:10 2009
New Revision: 72867

URL: http://llvm.org/viewvc/llvm-project?rev=72867&view=rev
Log:
--plugin is not needed for bfd anymore. Update docs.

Modified:
    llvm/trunk/docs/GoldPlugin.html

Modified: llvm/trunk/docs/GoldPlugin.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GoldPlugin.html?rev=72867&r1=72866&r2=72867&view=diff

==============================================================================
--- llvm/trunk/docs/GoldPlugin.html (original)
+++ llvm/trunk/docs/GoldPlugin.html Thu Jun  4 11:08:10 2009
@@ -153,12 +153,21 @@
     
     export CC="$PREFIX/bin/llvm-gcc -use-gold-plugin"
 export CXX="$PREFIX/bin/llvm-g++ -use-gold-plugin"
-export AR="$PREFIX/bin/ar --plugin libLLVMgold.so"
-export NM="$PREFIX/bin/nm --plugin libLLVMgold.so"
+export AR="$PREFIX/bin/ar"
+export NM="$PREFIX/bin/nm"
 export RANLIB=/bin/true #ranlib is not needed, and doesn't support .bc files in .a
 export CFLAGS="-O4"
      
    
      
+     
  • Or you can just set your path:
+    
    +export PATH="$PREFIX/bin:$PATH"
+export CC="llvm-gcc -use-gold-plugin"
+export CXX="llvm-g++ -use-gold-plugin"
+export RANLIB=/bin/true
+export CFLAGS="-O4"
+     
    
+     
    • 
      
  • Configure & build the project as usual: ./configure && make && make check 
    • 
    
    
     The environment variable settings may work for non-autotooled projects




From edwintorok at gmail.com  Thu Jun  4 11:09:59 2009
From: edwintorok at gmail.com (=?UTF-8?B?VMO2csO2ayBFZHdpbg==?=)
Date: Thu, 04 Jun 2009 19:09:59 +0300
Subject: [llvm-commits] [llvm] r72773 - /llvm/trunk/docs/GoldPlugin.html
In-Reply-To: <38a0d8450906040236m54557addx2ab47574a113f6c8@mail.gmail.com>
References: <200906031506.n53F6JOs014297@zion.cs.uiuc.edu>	
	<38a0d8450906030911u6ece8f37jef8f887ef719c2c0@mail.gmail.com>	
	<4A26A2E5.4@gmail.com>	
	<38a0d8450906030928q5e5f8b51le17588675f3bf2cb@mail.gmail.com>	
	<4A26A54A.3070201@gmail.com> <4A26C628.5060709@gmail.com>
	<38a0d8450906040236m54557addx2ab47574a113f6c8@mail.gmail.com>
Message-ID: <4A27F1D7.9010809@gmail.com>

On 2009-06-04 12:36, Rafael Espindola wrote:
>> plugin.c does this:
>> if (ent->d_type != DT_REG && ent->d_type != DT_LNK)
>>    continue;
>>
>> I am using reiserfs for my /home, and IIRC it doesn't implement the
>> d_type field and return DT_UNKNOWN for all files.
>> If you get DT_UNKNOWN you should lstat(), and check the result.
>>     
>
> Can you please try the attached patch?
>
>   

Thanks, it works now without --plugin too. Will this patch be committed
to binutils CVS?

I've updated the docs, you can now simply set just CC, CXX, CFLAGS and
RANLIB
and it'll just work ;)

Best regards,
--Edwin


From gohman at apple.com  Thu Jun  4 11:49:15 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 04 Jun 2009 16:49:15 -0000
Subject: [llvm-commits] [llvm] r72870 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Message-ID: <200906041649.n54GnFrT018622@zion.cs.uiuc.edu>

Author: djg
Date: Thu Jun  4 11:49:15 2009
New Revision: 72870

URL: http://llvm.org/viewvc/llvm-project?rev=72870&view=rev
Log:
Fix comments.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=72870&r1=72869&r2=72870&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jun  4 11:49:15 2009
@@ -154,7 +154,7 @@
   // Do not accept an all-undef vector.
   if (i == e) return false;
 
-  // Do not accept build_vectors that aren't all constants or which have non-~0
+  // Do not accept build_vectors that aren't all constants or which have non-0
   // elements.
   SDValue Zero = N->getOperand(i);
   if (isa(Zero)) {
@@ -166,7 +166,7 @@
   } else
     return false;
 
-  // Okay, we have at least one ~0 value, check to see if the rest match or are
+  // Okay, we have at least one 0 value, check to see if the rest match or are
   // undefs.
   for (++i; i != e; ++i)
     if (N->getOperand(i) != Zero &&




From gohman at apple.com  Thu Jun  4 12:12:13 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 04 Jun 2009 17:12:13 -0000
Subject: [llvm-commits] [llvm] r72872 - in /llvm/trunk/lib:
 CodeGen/SelectionDAG/DAGCombiner.cpp CodeGen/SelectionDAG/SelectionDAG.cpp
 Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200906041712.n54HCD13019349@zion.cs.uiuc.edu>

Author: djg
Date: Thu Jun  4 12:12:12 2009
New Revision: 72872

URL: http://llvm.org/viewvc/llvm-project?rev=72872&view=rev
Log:
Don't do the X * 0.0 -> 0.0 transformation in instcombine, because
instcombine doesn't know when it's safe. To partially compensate
for this, introduce new code to do this transformation in
dagcombine, which can use UnsafeFPMath.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=72872&r1=72871&r2=72872&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jun  4 12:12:12 2009
@@ -4019,6 +4019,9 @@
   // fold (fmul A, 0) -> 0
   if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
     return N1;
+  // fold (fmul A, 0) -> 0, vector edition.
+  if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
+    return N1;
   // fold (fmul X, 2.0) -> (fadd X, X)
   if (N1CFP && N1CFP->isExactlyValue(+2.0))
     return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=72872&r1=72871&r2=72872&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jun  4 12:12:12 2009
@@ -2807,16 +2807,19 @@
     case ISD::ADDC:
     case ISD::ADDE:
     case ISD::SUB:
-    case ISD::FADD:
-    case ISD::FSUB:
-    case ISD::FMUL:
-    case ISD::FDIV:
-    case ISD::FREM:
     case ISD::UDIV:
     case ISD::SDIV:
     case ISD::UREM:
     case ISD::SREM:
       return N2;       // fold op(arg1, undef) -> undef
+    case ISD::FADD:
+    case ISD::FSUB:
+    case ISD::FMUL:
+    case ISD::FDIV:
+    case ISD::FREM:
+      if (UnsafeFPMath)
+        return N2;
+      break;
     case ISD::MUL:
     case ISD::AND:
     case ISD::SRL:

Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=72872&r1=72871&r2=72872&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Thu Jun  4 12:12:12 2009
@@ -2585,7 +2585,9 @@
   bool Changed = SimplifyCommutative(I);
   Value *Op0 = I.getOperand(0);
 
-  if (isa(I.getOperand(1)))              // undef * X -> 0
+  // TODO: If Op1 is undef and Op0 is finite, return zero.
+  if (!I.getType()->isFPOrFPVector() &&
+      isa(I.getOperand(1)))              // undef * X -> 0
     return ReplaceInstUsesWith(I, Constant::getNullValue(I.getType()));
 
   // Simplify mul instructions with a constant RHS...
@@ -2612,16 +2614,14 @@
                  ConstantInt::get(Op0->getType(), Val.logBase2()));
       }
     } else if (ConstantFP *Op1F = dyn_cast(Op1)) {
-      if (Op1F->isNullValue())
-        return ReplaceInstUsesWith(I, Op1);
+      // TODO: If Op1 is zero and Op0 is finite, return zero.
 
       // "In IEEE floating point, x*1 is not equivalent to x for nans.  However,
       // ANSI says we can drop signals, so we can do this anyway." (from GCC)
       if (Op1F->isExactlyValue(1.0))
         return ReplaceInstUsesWith(I, Op0);  // Eliminate 'mul double %X, 1.0'
     } else if (isa(Op1->getType())) {
-      if (isa(Op1))
-        return ReplaceInstUsesWith(I, Op1);
+      // TODO: If Op1 is all zeros and Op0 is all finite, return all zeros.
 
       if (ConstantVector *Op1V = dyn_cast(Op1)) {
         if (Op1V->isAllOnesValue())              // X * -1 == 0 - X




From dgregor at apple.com  Thu Jun  4 12:22:52 2009
From: dgregor at apple.com (Douglas Gregor)
Date: Thu, 04 Jun 2009 17:22:52 -0000
Subject: [llvm-commits] [llvm] r72873 - in /llvm/trunk:
 cmake/config-ix.cmake include/llvm/Config/config.h.cmake
Message-ID: <200906041722.n54HMqH7019701@zion.cs.uiuc.edu>

Author: dgregor
Date: Thu Jun  4 12:22:52 2009
New Revision: 72873

URL: http://llvm.org/viewvc/llvm-project?rev=72873&view=rev
Log:
Properly detect malloc_zone_statistics in CMake build system

Modified:
    llvm/trunk/cmake/config-ix.cmake
    llvm/trunk/include/llvm/Config/config.h.cmake

Modified: llvm/trunk/cmake/config-ix.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=72873&r1=72872&r2=72873&view=diff

==============================================================================
--- llvm/trunk/cmake/config-ix.cmake (original)
+++ llvm/trunk/cmake/config-ix.cmake Thu Jun  4 12:22:52 2009
@@ -58,6 +58,8 @@
 check_symbol_exists(ceilf math.h HAVE_CEILF)
 check_symbol_exists(floorf math.h HAVE_FLOORF)
 check_symbol_exists(mallinfo malloc.h HAVE_MALLINFO)
+check_symbol_exists(malloc_zone_statistics malloc/malloc.h
+                    HAVE_MALLOC_ZONE_STATISTICS)
 check_symbol_exists(pthread_mutex_lock pthread.h HAVE_PTHREAD_MUTEX_LOCK)
 check_symbol_exists(strtoll stdlib.h HAVE_STRTOLL)
 

Modified: llvm/trunk/include/llvm/Config/config.h.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.cmake?rev=72873&r1=72872&r2=72873&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Config/config.h.cmake (original)
+++ llvm/trunk/include/llvm/Config/config.h.cmake Thu Jun  4 12:22:52 2009
@@ -228,7 +228,7 @@
 #cmakedefine HAVE_MALLOC_MALLOC_H ${HAVE_MALLOC_MALLOC_H}
 
 /* Define to 1 if you have the `malloc_zone_statistics' function. */
-#undef HAVE_MALLOC_ZONE_STATISTICS
+#cmakedefine HAVE_MALLOC_ZONE_STATISTICS ${HAVE_MALLOC_ZONE_STATISTICS}
 
 /* Define to 1 if you have the `memcpy' function. */
 #undef HAVE_MEMCPY




From isanbard at gmail.com  Thu Jun  4 13:11:50 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 4 Jun 2009 11:11:50 -0700
Subject: [llvm-commits] [llvm] r72872 - in /llvm/trunk/lib:
	CodeGen/SelectionDAG/DAGCombiner.cpp
	CodeGen/SelectionDAG/SelectionDAG.cpp
	Transforms/Scalar/InstructionCombining.cpp
In-Reply-To: <200906041712.n54HCD13019349@zion.cs.uiuc.edu>
References: <200906041712.n54HCD13019349@zion.cs.uiuc.edu>
Message-ID: <16e5fdf90906041111n540aed2bm91f00267c3b6fef7@mail.gmail.com>

Please look at this test which is now failing because of this change:

Running /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/test/Transforms/InstCombine/dg.exp
...
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/test/Transforms/InstCombine/mul.ll
for PR2642
Failed with exit(1) at line 1
while running:  llvm-as <
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore/test/Transforms/InstCombine/mul.ll
|  opt -instcombine |  llvm-dis | not /usr/bin/grep mul
	%3 = mul <4 x float> %2, zeroinitializer		; <<4 x float>> [#uses=1]
child process exited abnormally

-bw

On Thu, Jun 4, 2009 at 10:12 AM, Dan Gohman  wrote:
> Author: djg
> Date: Thu Jun ?4 12:12:12 2009
> New Revision: 72872
>
> URL: http://llvm.org/viewvc/llvm-project?rev=72872&view=rev
> Log:
> Don't do the X * 0.0 -> 0.0 transformation in instcombine, because
> instcombine doesn't know when it's safe. To partially compensate
> for this, introduce new code to do this transformation in
> dagcombine, which can use UnsafeFPMath.
>
> Modified:
> ? ?llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> ? ?llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> ? ?llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=72872&r1=72871&r2=72872&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jun ?4 12:12:12 2009
> @@ -4019,6 +4019,9 @@
> ? // fold (fmul A, 0) -> 0
> ? if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
> ? ? return N1;
> + ?// fold (fmul A, 0) -> 0, vector edition.
> + ?if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
> + ? ?return N1;
> ? // fold (fmul X, 2.0) -> (fadd X, X)
> ? if (N1CFP && N1CFP->isExactlyValue(+2.0))
> ? ? return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=72872&r1=72871&r2=72872&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jun ?4 12:12:12 2009
> @@ -2807,16 +2807,19 @@
> ? ? case ISD::ADDC:
> ? ? case ISD::ADDE:
> ? ? case ISD::SUB:
> - ? ?case ISD::FADD:
> - ? ?case ISD::FSUB:
> - ? ?case ISD::FMUL:
> - ? ?case ISD::FDIV:
> - ? ?case ISD::FREM:
> ? ? case ISD::UDIV:
> ? ? case ISD::SDIV:
> ? ? case ISD::UREM:
> ? ? case ISD::SREM:
> ? ? ? return N2; ? ? ? // fold op(arg1, undef) -> undef
> + ? ?case ISD::FADD:
> + ? ?case ISD::FSUB:
> + ? ?case ISD::FMUL:
> + ? ?case ISD::FDIV:
> + ? ?case ISD::FREM:
> + ? ? ?if (UnsafeFPMath)
> + ? ? ? ?return N2;
> + ? ? ?break;
> ? ? case ISD::MUL:
> ? ? case ISD::AND:
> ? ? case ISD::SRL:
>
> Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=72872&r1=72871&r2=72872&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
> +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Thu Jun ?4 12:12:12 2009
> @@ -2585,7 +2585,9 @@
> ? bool Changed = SimplifyCommutative(I);
> ? Value *Op0 = I.getOperand(0);
>
> - ?if (isa(I.getOperand(1))) ? ? ? ? ? ? ?// undef * X -> 0
> + ?// TODO: If Op1 is undef and Op0 is finite, return zero.
> + ?if (!I.getType()->isFPOrFPVector() &&
> + ? ? ?isa(I.getOperand(1))) ? ? ? ? ? ? ?// undef * X -> 0
> ? ? return ReplaceInstUsesWith(I, Constant::getNullValue(I.getType()));
>
> ? // Simplify mul instructions with a constant RHS...
> @@ -2612,16 +2614,14 @@
> ? ? ? ? ? ? ? ? ?ConstantInt::get(Op0->getType(), Val.logBase2()));
> ? ? ? }
> ? ? } else if (ConstantFP *Op1F = dyn_cast(Op1)) {
> - ? ? ?if (Op1F->isNullValue())
> - ? ? ? ?return ReplaceInstUsesWith(I, Op1);
> + ? ? ?// TODO: If Op1 is zero and Op0 is finite, return zero.
>
> ? ? ? // "In IEEE floating point, x*1 is not equivalent to x for nans. ?However,
> ? ? ? // ANSI says we can drop signals, so we can do this anyway." (from GCC)
> ? ? ? if (Op1F->isExactlyValue(1.0))
> ? ? ? ? return ReplaceInstUsesWith(I, Op0); ?// Eliminate 'mul double %X, 1.0'
> ? ? } else if (isa(Op1->getType())) {
> - ? ? ?if (isa(Op1))
> - ? ? ? ?return ReplaceInstUsesWith(I, Op1);
> + ? ? ?// TODO: If Op1 is all zeros and Op0 is all finite, return all zeros.
>
> ? ? ? if (ConstantVector *Op1V = dyn_cast(Op1)) {
> ? ? ? ? if (Op1V->isAllOnesValue()) ? ? ? ? ? ? ?// X * -1 == 0 - X
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



From isanbard at gmail.com  Thu Jun  4 13:14:35 2009
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 4 Jun 2009 11:14:35 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r72804 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
In-Reply-To: <4A2779BF.1020402@free.fr>
References: <200906032049.n53KnZVm027957@zion.cs.uiuc.edu>
	<4A275924.2070809@free.fr>
	
	<4A2779BF.1020402@free.fr>
Message-ID: <16e5fdf90906041114h572bf339ga8f8ddda138c9449@mail.gmail.com>

On Thu, Jun 4, 2009 at 12:37 AM, Duncan Sands  wrote:
> Hi Bill,
>
>>> I would have expected LLVM to give strings an alignment of 1. ?Is that
>>> not so?
>>>
>> No. At this point, before my patch, the alignment wasn't being set.
>> During code generation, it defaults (through a series of calls) to a
>> "preferred alignment" of 16 bytes.
>
> maybe that's a bug? ?16 byte alignment seems an awful lot for a string.
>
I agree. But the back end has no concept of what's a string and what's
an array of i8s. I think that my patch should fix this...

-bw



From gohman at apple.com  Thu Jun  4 13:22:31 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 04 Jun 2009 18:22:31 -0000
Subject: [llvm-commits] [llvm] r72875 - in /llvm/trunk/test:
 CodeGen/X86/fmul-zero.ll Transforms/InstCombine/mul.ll
Message-ID: <200906041822.n54IMVMS021682@zion.cs.uiuc.edu>

Author: djg
Date: Thu Jun  4 13:22:31 2009
New Revision: 72875

URL: http://llvm.org/viewvc/llvm-project?rev=72875&view=rev
Log:
Check in test changes that I accidentally left out of r72872.

Added:
    llvm/trunk/test/CodeGen/X86/fmul-zero.ll
Modified:
    llvm/trunk/test/Transforms/InstCombine/mul.ll

Added: llvm/trunk/test/CodeGen/X86/fmul-zero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fmul-zero.ll?rev=72875&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fmul-zero.ll (added)
+++ llvm/trunk/test/CodeGen/X86/fmul-zero.ll Thu Jun  4 13:22:31 2009
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc -march=x86-64 -enable-unsafe-fp-math | not grep mulps
+; RUN: llvm-as < %s | llc -march=x86-64 | grep mulps
+
+define void @test14(<4 x float>*) nounwind {
+        load <4 x float>* %0, align 1
+        mul <4 x float> %2, zeroinitializer
+        store <4 x float> %3, <4 x float>* %0, align 1
+        ret void
+}

Modified: llvm/trunk/test/Transforms/InstCombine/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/mul.ll?rev=72875&r1=72874&r2=72875&view=diff

==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/mul.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/mul.ll Thu Jun  4 13:22:31 2009
@@ -83,11 +83,3 @@
 	store <4 x float> %3, <4 x float>* %0, align 1
 	ret void
 }
-
-define internal void @test14(<4 x float>*) {
-	load <4 x float>* %0, align 1
-	mul <4 x float> %2, zeroinitializer
-	store <4 x float> %3, <4 x float>* %0, align 1
-	ret void
-}
-




From dalej at apple.com  Thu Jun  4 13:23:18 2009
From: dalej at apple.com (Dale Johannesen)
Date: Thu, 4 Jun 2009 11:23:18 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r72804 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
In-Reply-To: <16e5fdf90906041114h572bf339ga8f8ddda138c9449@mail.gmail.com>
References: <200906032049.n53KnZVm027957@zion.cs.uiuc.edu>
	<4A275924.2070809@free.fr>
	
	<4A2779BF.1020402@free.fr>
	<16e5fdf90906041114h572bf339ga8f8ddda138c9449@mail.gmail.com>
Message-ID: <1B9D06EC-A5A3-450A-AA90-73A3E3A2486B@apple.com>


On Jun 4, 2009, at 11:14 AMPDT, Bill Wendling wrote:

> On Thu, Jun 4, 2009 at 12:37 AM, Duncan Sands   
> wrote:
>> Hi Bill,
>>
>>>> I would have expected LLVM to give strings an alignment of 1.  Is  
>>>> that
>>>> not so?
>>>>
>>> No. At this point, before my patch, the alignment wasn't being set.
>>> During code generation, it defaults (through a series of calls) to a
>>> "preferred alignment" of 16 bytes.
>>
>> maybe that's a bug?  16 byte alignment seems an awful lot for a  
>> string.
>>
> I agree. But the back end has no concept of what's a string and what's
> an array of i8s. I think that my patch should fix this...

I don't know the history, but there are reasons you might want strings  
to have high alignment.  They cross fewer cache lines, and you can  
copy them with XMM (or Altivec) loads and stores.



From dalej at apple.com  Thu Jun  4 13:27:43 2009
From: dalej at apple.com (Dale Johannesen)
Date: Thu, 04 Jun 2009 18:27:43 -0000
Subject: [llvm-commits] [llvm] r72876 - in /llvm/trunk/test/FrontendC:
 2009-01-20-k8.c 2009-05-04-EnumInreg.c
Message-ID: <200906041827.n54IRh4Q021935@zion.cs.uiuc.edu>

Author: johannes
Date: Thu Jun  4 13:27:43 2009
New Revision: 72876

URL: http://llvm.org/viewvc/llvm-project?rev=72876&view=rev
Log:
For XTARGET to work on targets not in the list,
there must also be an XFAIL line.  Fix a couple
examples of this.


Modified:
    llvm/trunk/test/FrontendC/2009-01-20-k8.c
    llvm/trunk/test/FrontendC/2009-05-04-EnumInreg.c

Modified: llvm/trunk/test/FrontendC/2009-01-20-k8.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2009-01-20-k8.c?rev=72876&r1=72875&r2=72876&view=diff

==============================================================================
--- llvm/trunk/test/FrontendC/2009-01-20-k8.c (original)
+++ llvm/trunk/test/FrontendC/2009-01-20-k8.c Thu Jun  4 13:27:43 2009
@@ -1,3 +1,4 @@
 // RUN: %llvmgcc %s -S -march=k8
 // XTARGET: x86
+// XFAIL: *
 long double x;

Modified: llvm/trunk/test/FrontendC/2009-05-04-EnumInreg.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2009-05-04-EnumInreg.c?rev=72876&r1=72875&r2=72876&view=diff

==============================================================================
--- llvm/trunk/test/FrontendC/2009-05-04-EnumInreg.c (original)
+++ llvm/trunk/test/FrontendC/2009-05-04-EnumInreg.c Thu Jun  4 13:27:43 2009
@@ -1,4 +1,5 @@
 // RUN: %llvmgcc -S -m32 -mregparm=3 %s -emit-llvm -o - | grep {inreg %action}
+// XFAIL: *
 // XTARGET: x86
 // PR3967
 




From lhames at gmail.com  Thu Jun  4 13:45:36 2009
From: lhames at gmail.com (Lang Hames)
Date: Thu, 04 Jun 2009 18:45:36 -0000
Subject: [llvm-commits] [llvm] r72880 -
	/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp
Message-ID: <200906041845.n54Ijb6B022587@zion.cs.uiuc.edu>

Author: lhames
Date: Thu Jun  4 13:45:36 2009
New Revision: 72880

URL: http://llvm.org/viewvc/llvm-project?rev=72880&view=rev
Log:
Removed SimpleRewriter.

Modified:
    llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp

Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=72880&r1=72879&r2=72880&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Thu Jun  4 13:45:36 2009
@@ -33,99 +33,21 @@
 STATISTIC(NumModRefUnfold, "Number of modref unfolded");
 
 namespace {
-  enum RewriterName { simple, local, trivial };
+  enum RewriterName { local, trivial };
 }
 
 static cl::opt
 RewriterOpt("rewriter",
             cl::desc("Rewriter to use: (default: local)"),
             cl::Prefix,
-            cl::values(clEnumVal(simple,  "simple rewriter"),
-                       clEnumVal(local,   "local rewriter"),
+            cl::values(clEnumVal(local,   "local rewriter"),
                        clEnumVal(trivial, "trivial rewriter"),
                        clEnumValEnd),
             cl::init(local));
 
 VirtRegRewriter::~VirtRegRewriter() {}
 
- 
-// ****************************** //
-// Simple Spiller Implementation  //
-// ****************************** //
-
-struct VISIBILITY_HIDDEN SimpleRewriter : public VirtRegRewriter {
-
-  bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM,
-                            LiveIntervals* LIs) {
-    DOUT << "********** REWRITE MACHINE CODE **********\n";
-    DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
-    const TargetMachine &TM = MF.getTarget();
-    const TargetInstrInfo &TII = *TM.getInstrInfo();
-    const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
-
-
-    // LoadedRegs - Keep track of which vregs are loaded, so that we only load
-    // each vreg once (in the case where a spilled vreg is used by multiple
-    // operands).  This is always smaller than the number of operands to the
-    // current machine instr, so it should be small.
-    std::vector LoadedRegs;
-
-    for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
-         MBBI != E; ++MBBI) {
-      DOUT << MBBI->getBasicBlock()->getName() << ":\n";
-      MachineBasicBlock &MBB = *MBBI;
-      for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
-           MII != E; ++MII) {
-        MachineInstr &MI = *MII;
-        for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
-          MachineOperand &MO = MI.getOperand(i);
-          if (MO.isReg() && MO.getReg()) {
-            if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
-              unsigned VirtReg = MO.getReg();
-              unsigned SubIdx = MO.getSubReg();
-              unsigned PhysReg = VRM.getPhys(VirtReg);
-              unsigned RReg = SubIdx ? TRI.getSubReg(PhysReg, SubIdx) : PhysReg;
-              if (!VRM.isAssignedReg(VirtReg)) {
-                int StackSlot = VRM.getStackSlot(VirtReg);
-                const TargetRegisterClass* RC = 
-                                             MF.getRegInfo().getRegClass(VirtReg);
-                
-                if (MO.isUse() &&
-                    std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
-                             == LoadedRegs.end()) {
-                  TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
-                  MachineInstr *LoadMI = prior(MII);
-                  VRM.addSpillSlotUse(StackSlot, LoadMI);
-                  LoadedRegs.push_back(VirtReg);
-                  ++NumLoads;
-                  DOUT << '\t' << *LoadMI;
-                }
-
-                if (MO.isDef()) {
-                  TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true,   
-                                          StackSlot, RC);
-                  MachineInstr *StoreMI = next(MII);
-                  VRM.addSpillSlotUse(StackSlot, StoreMI);
-                  ++NumStores;
-                }
-              }
-              MF.getRegInfo().setPhysRegUsed(RReg);
-              MI.getOperand(i).setReg(RReg);
-              MI.getOperand(i).setSubReg(0);
-            } else {
-              MF.getRegInfo().setPhysRegUsed(MO.getReg());
-            }
-          }
-        }
-
-        DOUT << '\t' << MI;
-        LoadedRegs.clear();
-      }
-    }
-    return true;
-  }
 
-};
  
 /// This class is intended for use with the new spilling framework only. It
 /// rewrites vreg def/uses to use the assigned preg, but does not insert any
@@ -2231,8 +2153,6 @@
   default: assert(0 && "Unreachable!");
   case local:
     return new LocalRewriter();
-  case simple:
-    return new SimpleRewriter();
   case trivial:
     return new TrivialRewriter();
   }




From kledzik at apple.com  Thu Jun  4 14:14:10 2009
From: kledzik at apple.com (Nick Kledzik)
Date: Thu, 04 Jun 2009 19:14:10 -0000
Subject: [llvm-commits] [llvm] r72881 -
	/llvm/trunk/tools/lto/LTOCodeGenerator.cpp
Message-ID: <200906041914.n54JEAFX023604@zion.cs.uiuc.edu>

Author: kledzik
Date: Thu Jun  4 14:14:08 2009
New Revision: 72881

URL: http://llvm.org/viewvc/llvm-project?rev=72881&view=rev
Log:
 libLTO for darwin should add -static when assembling .s

Modified:
    llvm/trunk/tools/lto/LTOCodeGenerator.cpp

Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=72881&r1=72880&r2=72881&view=diff

==============================================================================
--- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original)
+++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Thu Jun  4 14:14:08 2009
@@ -249,6 +249,7 @@
     std::string targetTriple = _linker.getModule()->getTargetTriple();
     args.push_back(tool.c_str());
     if ( targetTriple.find("darwin") != targetTriple.size() ) {
+        // darwin specific command line options
         if (strncmp(targetTriple.c_str(), "i386-apple-", 11) == 0) {
             args.push_back("-arch");
             args.push_back("i386");
@@ -286,6 +287,9 @@
             args.push_back("-arch");
             args.push_back("armv6");
         }
+        // add -static to assembler command line when code model requires
+        if ( (_assemblerPath != NULL) && (_codeModel == LTO_CODEGEN_PIC_MODEL_STATIC) )
+            args.push_back("-static");
     }
     if ( needsCompilerOptions ) {
         args.push_back("-c");




From anon at cs.uiuc.edu  Thu Jun  4 14:41:04 2009
From: anon at cs.uiuc.edu (anon at cs.uiuc.edu)
Date: Thu, 4 Jun 2009 14:41:04 -0500
Subject: [llvm-commits] CVS: llvm-www/demo/index.cgi
Message-ID: <200906041941.n54Jf4Ia024634@zion.cs.uiuc.edu>



Changes in directory llvm-www/demo:

index.cgi updated: 1.101 -> 1.102
---
Log message:

Put the optimization levels in order of decreasing power.


---
Diffs of the changes:  (+1 -1)

 index.cgi |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-www/demo/index.cgi
diff -u llvm-www/demo/index.cgi:1.101 llvm-www/demo/index.cgi:1.102
--- llvm-www/demo/index.cgi:1.101	Thu Jun  4 07:25:32 2009
+++ llvm-www/demo/index.cgi	Thu Jun  4 14:38:38 2009
@@ -196,7 +196,7 @@
 print "Optimization level: ",
   $c->radio_group(
     -name    => 'optlevel',
-    -values  => [ 'Standard', 'LTO', 'None' ],
+    -values  => [ 'LTO', 'Standard', 'None' ],
     -default => 'Standard'
   ),' ?
    ', "
    ";
 





From dgregor at apple.com  Thu Jun  4 14:53:37 2009
From: dgregor at apple.com (Douglas Gregor)
Date: Thu, 04 Jun 2009 19:53:37 -0000
Subject: [llvm-commits] [llvm] r72883 - in /llvm/trunk: CMakeLists.txt
 cmake/modules/AddLLVM.cmake cmake/modules/AddPartiallyLinkedObject.cmake
 cmake/modules/LLVMConfig.cmake tools/CMakeLists.txt
Message-ID: <200906041953.n54JrcoJ025341@zion.cs.uiuc.edu>

Author: dgregor
Date: Thu Jun  4 14:53:37 2009
New Revision: 72883

URL: http://llvm.org/viewvc/llvm-project?rev=72883&view=rev
Log:
CMake: Use explicit dependencies for Xcode (as well as MSVC), to make
the CMake-generated Xcode project build properly.

Modified:
    llvm/trunk/CMakeLists.txt
    llvm/trunk/cmake/modules/AddLLVM.cmake
    llvm/trunk/cmake/modules/AddPartiallyLinkedObject.cmake
    llvm/trunk/cmake/modules/LLVMConfig.cmake
    llvm/trunk/tools/CMakeLists.txt

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=72883&r1=72882&r2=72883&view=diff

==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Thu Jun  4 14:53:37 2009
@@ -90,6 +90,24 @@
 
 set(llvm_builded_incs_dir ${LLVM_BINARY_DIR}/include/llvm)
 
+# The USE_EXPLICIT_DEPENDENCIES variable will be TRUE to indicate that
+# we should use the library dependencies explicitly specified in the
+# CMakeLists.txt files rather than those determined by
+# llvm-config. This value must be true for non-make and IDE
+# generators.
+if (MSVC_IDE)
+  set(DEFAULT_USE_EXPLICIT_DEPENDENCIES ON)
+elseif (XCODE)
+  set(DEFAULT_USE_EXPLICIT_DEPENDENCIES ON)
+else ()
+ set(DEFAULT_USE_EXPLICIT_DEPENDENCIES OFF)
+endif ()
+
+option(USE_EXPLICIT_DEPENDENCIES 
+  "Use explicit dependencies instead of llvm-config" 
+  ${DEFAULT_USE_EXPLICIT_DEPENDENCIES})
+mark_as_advanced(USE_EXPLICIT_DEPENDENCIES)
+
 # Add path for custom modules
 set(CMAKE_MODULE_PATH
   ${CMAKE_MODULE_PATH}

Modified: llvm/trunk/cmake/modules/AddLLVM.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=72883&r1=72882&r2=72883&view=diff

==============================================================================
--- llvm/trunk/cmake/modules/AddLLVM.cmake (original)
+++ llvm/trunk/cmake/modules/AddLLVM.cmake Thu Jun  4 14:53:37 2009
@@ -26,11 +26,11 @@
   if( LLVM_LINK_COMPONENTS )
     llvm_config(${name} ${LLVM_LINK_COMPONENTS})
   endif( LLVM_LINK_COMPONENTS )
-  if( MSVC )
+  if( USE_EXPLICIT_DEPENDENCIES )
     target_link_libraries(${name} ${llvm_libs})
-  else( MSVC )
+  else( )
     add_dependencies(${name} llvm-config.target)
-  endif( MSVC )
+  endif( )
   get_system_libs(llvm_system_libs)
   if( llvm_system_libs )
     target_link_libraries(${name} ${llvm_system_libs})

Modified: llvm/trunk/cmake/modules/AddPartiallyLinkedObject.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddPartiallyLinkedObject.cmake?rev=72883&r1=72882&r2=72883&view=diff

==============================================================================
--- llvm/trunk/cmake/modules/AddPartiallyLinkedObject.cmake (original)
+++ llvm/trunk/cmake/modules/AddPartiallyLinkedObject.cmake Thu Jun  4 14:53:37 2009
@@ -1,18 +1,18 @@
 include(LLVMProcessSources)
 
 macro(target_name_of_partially_linked_object lib var)
-  if( MSVC )
+  if( USE_EXPLICIT_DEPENDENCIES )
     set(${var} ${lib})
-  else( MSVC )
+  else( )
     set(${var} ${lib}_pll)
-  endif( MSVC )
+  endif( )
 endmacro(target_name_of_partially_linked_object lib var)
 
 
 macro(add_partially_linked_object lib)
-  if( MSVC )
+  if( USE_EXPLICIT_DEPENDENCIES )
     add_llvm_library( ${lib} ${ARGN})
-  else( MSVC )
+  else( )
     set(pll ${CMAKE_ARCHIVE_OUTPUT_DIRECTORY}/${CMAKE_CFG_INTDIR}/${lib}.o)
     set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/temp_lib)
     set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/temp_lib)
@@ -36,7 +36,7 @@
     add_custom_target(${tnplo} ALL DEPENDS ${pll})
     set( llvm_libs ${llvm_libs} ${pll} PARENT_SCOPE)
     set( llvm_lib_targets ${llvm_lib_targets} ${tnplo} PARENT_SCOPE )
-  endif( MSVC )
+  endif( )
   install(FILES ${pll}
     DESTINATION lib)
 endmacro(add_partially_linked_object lib)

Modified: llvm/trunk/cmake/modules/LLVMConfig.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMConfig.cmake?rev=72883&r1=72882&r2=72883&view=diff

==============================================================================
--- llvm/trunk/cmake/modules/LLVMConfig.cmake (original)
+++ llvm/trunk/cmake/modules/LLVMConfig.cmake Thu Jun  4 14:53:37 2009
@@ -21,36 +21,40 @@
 
 macro(llvm_config executable)
   # extra args is the list of link components.
-  if( MSVC )
-    msvc_llvm_config(${executable} ${ARGN})
-  else( MSVC )
+  if( USE_EXPLICIT_DEPENDENCIES )
+    explicit_llvm_config(${executable} ${ARGN})
+  else( )
     nix_llvm_config(${executable} ${ARGN})
-  endif( MSVC )
+  endif( )
 endmacro(llvm_config)
 
 
-function(msvc_llvm_config executable)
+function(explicit_llvm_config executable)
   set( link_components ${ARGN} )
-  if( CMAKE_CL_64 )
-    set(include_lflag "/INCLUDE:")
-  else( CMAKE_CL_64 )
-    set(include_lflag "/INCLUDE:_")
-  endif()
-  foreach(c ${link_components})
-    if( c STREQUAL "jit" )
-      set(lfgs "${lfgs} ${include_lflag}X86TargetMachineModule")
-    endif( c STREQUAL "jit" )
-    list(FIND LLVM_TARGETS_TO_BUILD ${c} idx)
-    if( NOT idx LESS 0 )
-      set(lfgs "${lfgs} ${include_lflag}${c}TargetMachineModule")
-      list(FIND LLVM_ASMPRINTERS_FORCE_LINK ${c} idx)
+
+  set(lfgs)
+  if (MSVC)
+    if( CMAKE_CL_64 )
+      set(include_lflag "/INCLUDE:")
+    else( CMAKE_CL_64 )
+      set(include_lflag "/INCLUDE:_")
+    endif()
+    foreach(c ${link_components})
+      if( c STREQUAL "jit" )
+        set(lfgs "${lfgs} ${include_lflag}X86TargetMachineModule")
+      endif( c STREQUAL "jit" )
+      list(FIND LLVM_TARGETS_TO_BUILD ${c} idx)
       if( NOT idx LESS 0 )
-	set(lfgs "${lfgs} ${include_lflag}${c}AsmPrinterForceLink")
+        set(lfgs "${lfgs} ${include_lflag}${c}TargetMachineModule")
+        list(FIND LLVM_ASMPRINTERS_FORCE_LINK ${c} idx)
+        if( NOT idx LESS 0 )
+	  set(lfgs "${lfgs} ${include_lflag}${c}AsmPrinterForceLink")
+        endif()
       endif()
-    endif()
-  endforeach(c)
+    endforeach(c)
+  endif ()
 
-  msvc_map_components_to_libraries(LIBRARIES ${link_components})
+  explicit_map_components_to_libraries(LIBRARIES ${link_components})
   target_link_libraries(${executable} ${LIBRARIES})
 
   if( lfgs )
@@ -58,10 +62,10 @@
       PROPERTIES
       LINK_FLAGS ${lfgs})
   endif()
-endfunction(msvc_llvm_config)
+endfunction(explicit_llvm_config)
 
 
-function(msvc_map_components_to_libraries out_libs)
+function(explicit_map_components_to_libraries out_libs)
   set( link_components ${ARGN} )
   foreach(c ${link_components})
     # add codegen/asmprinter
@@ -121,7 +125,7 @@
   endwhile( ${curr_idx} LESS ${lst_size} )
   list(REMOVE_DUPLICATES result)
   set(${out_libs} ${result} PARENT_SCOPE)
-endfunction(msvc_map_components_to_libraries)
+endfunction(explicit_map_components_to_libraries)
 
 
 macro(nix_llvm_config executable)

Modified: llvm/trunk/tools/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/CMakeLists.txt?rev=72883&r1=72882&r2=72883&view=diff

==============================================================================
--- llvm/trunk/tools/CMakeLists.txt (original)
+++ llvm/trunk/tools/CMakeLists.txt Thu Jun  4 14:53:37 2009
@@ -2,9 +2,9 @@
 # large and three small executables. This is done to minimize memory load
 # in parallel builds.  Please retain this ordering.
 
-if( NOT MSVC )
-  add_subdirectory(llvm-config)
-endif( NOT MSVC )
+if (NOT USE_EXPLICIT_DEPENDENCIES)
+ add_subdirectory(llvm-config)
+endif()
 
 add_subdirectory(opt)
 add_subdirectory(llvm-as)




From evan.cheng at apple.com  Thu Jun  4 15:25:50 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 04 Jun 2009 20:25:50 -0000
Subject: [llvm-commits] [llvm] r72888 -
	/llvm/trunk/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
Message-ID: <200906042025.n54KPo8h026576@zion.cs.uiuc.edu>

Author: evancheng
Date: Thu Jun  4 15:25:48 2009
New Revision: 72888

URL: http://llvm.org/viewvc/llvm-project?rev=72888&view=rev
Log:
A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB.

Added:
    llvm/trunk/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll

Added: llvm/trunk/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll?rev=72888&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll Thu Jun  4 15:25:48 2009
@@ -0,0 +1,263 @@
+; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -mattr=+v6
+
+	%struct.anon = type { i16, i16 }
+	%struct.cab_archive = type { i32, i16, i16, i16, i16, i8, %struct.cab_folder*, %struct.cab_file* }
+	%struct.cab_file = type { i32, i16, i64, i8*, i32, i32, i32, %struct.cab_folder*, %struct.cab_file*, %struct.cab_archive*, %struct.cab_state* }
+	%struct.cab_folder = type { i16, i16, %struct.cab_archive*, i64, %struct.cab_folder* }
+	%struct.cab_state = type { i8*, i8*, [38912 x i8], i16, i16, i8*, i16 }
+	%struct.qtm_model = type { i32, i32, %struct.anon* }
+	%struct.qtm_stream = type { i32, i32, i8, i8*, i32, i32, i32, i16, i16, i16, i8, i32, i8*, i8*, i8*, i8*, i8*, i32, i32, i8, [42 x i32], [42 x i8], [27 x i8], [27 x i8], %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [25 x %struct.anon], [37 x %struct.anon], [43 x %struct.anon], [28 x %struct.anon], [8 x %struct.anon], %struct.cab_file*, i32 (%struct.cab_file*, i8*, i32)* }
+
+declare fastcc i32 @qtm_read_input(%struct.qtm_stream* nocapture) nounwind
+
+define fastcc i32 @qtm_decompress(%struct.qtm_stream* %qtm, i64 %out_bytes) nounwind {
+entry:
+	br i1 undef, label %bb245, label %bb3
+
+bb3:		; preds = %entry
+	br i1 undef, label %bb5, label %bb4
+
+bb4:		; preds = %bb3
+	ret i32 undef
+
+bb5:		; preds = %bb3
+	br i1 undef, label %bb245, label %bb14
+
+bb14:		; preds = %bb5
+	br label %bb238
+
+bb28:		; preds = %bb215
+	br label %bb31
+
+bb29:		; preds = %bb31
+	br i1 undef, label %bb31, label %bb32
+
+bb31:		; preds = %bb29, %bb28
+	br i1 undef, label %bb29, label %bb32
+
+bb32:		; preds = %bb31, %bb29
+	br label %bb33
+
+bb33:		; preds = %bb33, %bb32
+	br i1 undef, label %bb34, label %bb33
+
+bb34:		; preds = %bb33
+	br i1 undef, label %bb35, label %bb36
+
+bb35:		; preds = %bb34
+	br label %bb36
+
+bb36:		; preds = %bb46, %bb35, %bb34
+	br i1 undef, label %bb40, label %bb37
+
+bb37:		; preds = %bb36
+	br i1 undef, label %bb77, label %bb60
+
+bb40:		; preds = %bb36
+	br i1 undef, label %bb46, label %bb41
+
+bb41:		; preds = %bb40
+	br i1 undef, label %bb45, label %bb42
+
+bb42:		; preds = %bb41
+	ret i32 undef
+
+bb45:		; preds = %bb41
+	br label %bb46
+
+bb46:		; preds = %bb45, %bb40
+	br label %bb36
+
+bb60:		; preds = %bb60, %bb37
+	br label %bb60
+
+bb77:		; preds = %bb37
+	switch i32 undef, label %bb197 [
+		i32 5, label %bb108
+		i32 6, label %bb138
+	]
+
+bb108:		; preds = %bb77
+	br label %bb111
+
+bb109:		; preds = %bb111
+	br i1 undef, label %bb111, label %bb112
+
+bb111:		; preds = %bb109, %bb108
+	br i1 undef, label %bb109, label %bb112
+
+bb112:		; preds = %bb111, %bb109
+	br label %bb113
+
+bb113:		; preds = %bb113, %bb112
+	br i1 undef, label %bb114, label %bb113
+
+bb114:		; preds = %bb113
+	br i1 undef, label %bb115, label %bb116
+
+bb115:		; preds = %bb114
+	br label %bb116
+
+bb116:		; preds = %bb115, %bb114
+	br i1 undef, label %bb120, label %bb117
+
+bb117:		; preds = %bb116
+	br label %bb136
+
+bb120:		; preds = %bb116
+	ret i32 undef
+
+bb128:		; preds = %bb136
+	br i1 undef, label %bb134, label %bb129
+
+bb129:		; preds = %bb128
+	br i1 undef, label %bb133, label %bb130
+
+bb130:		; preds = %bb129
+	br i1 undef, label %bb132, label %bb131
+
+bb131:		; preds = %bb130
+	ret i32 undef
+
+bb132:		; preds = %bb130
+	br label %bb133
+
+bb133:		; preds = %bb132, %bb129
+	br label %bb134
+
+bb134:		; preds = %bb133, %bb128
+	br label %bb136
+
+bb136:		; preds = %bb134, %bb117
+	br i1 undef, label %bb198, label %bb128
+
+bb138:		; preds = %bb77
+	%0 = trunc i32 undef to i16		;  [#uses=1]
+	br label %bb141
+
+bb139:		; preds = %bb141
+	%scevgep441442881 = load i16* undef		;  [#uses=1]
+	%1 = icmp ugt i16 %scevgep441442881, %0		;  [#uses=1]
+	br i1 %1, label %bb141, label %bb142
+
+bb141:		; preds = %bb139, %bb138
+	br i1 undef, label %bb139, label %bb142
+
+bb142:		; preds = %bb141, %bb139
+	br label %bb143
+
+bb143:		; preds = %bb143, %bb142
+	br i1 undef, label %bb144, label %bb143
+
+bb144:		; preds = %bb143
+	br i1 undef, label %bb145, label %bb146
+
+bb145:		; preds = %bb144
+	unreachable
+
+bb146:		; preds = %bb156, %bb144
+	br i1 undef, label %bb150, label %bb147
+
+bb147:		; preds = %bb146
+	br i1 undef, label %bb157, label %bb148
+
+bb148:		; preds = %bb147
+	br i1 undef, label %bb149, label %bb157
+
+bb149:		; preds = %bb148
+	br label %bb150
+
+bb150:		; preds = %bb149, %bb146
+	br i1 undef, label %bb156, label %bb152
+
+bb152:		; preds = %bb150
+	unreachable
+
+bb156:		; preds = %bb150
+	br label %bb146
+
+bb157:		; preds = %bb148, %bb147
+	br i1 undef, label %bb167, label %bb160
+
+bb160:		; preds = %bb157
+	ret i32 undef
+
+bb167:		; preds = %bb157
+	br label %bb170
+
+bb168:		; preds = %bb170
+	br i1 undef, label %bb170, label %bb171
+
+bb170:		; preds = %bb168, %bb167
+	br i1 undef, label %bb168, label %bb171
+
+bb171:		; preds = %bb170, %bb168
+	br label %bb172
+
+bb172:		; preds = %bb172, %bb171
+	br i1 undef, label %bb173, label %bb172
+
+bb173:		; preds = %bb172
+	br i1 undef, label %bb174, label %bb175
+
+bb174:		; preds = %bb173
+	unreachable
+
+bb175:		; preds = %bb179, %bb173
+	br i1 undef, label %bb179, label %bb176
+
+bb176:		; preds = %bb175
+	br i1 undef, label %bb186, label %bb177
+
+bb177:		; preds = %bb176
+	br i1 undef, label %bb178, label %bb186
+
+bb178:		; preds = %bb177
+	br label %bb179
+
+bb179:		; preds = %bb178, %bb175
+	br label %bb175
+
+bb186:		; preds = %bb177, %bb176
+	br label %bb195
+
+bb187:		; preds = %bb195
+	br i1 undef, label %bb193, label %bb189
+
+bb189:		; preds = %bb187
+	%2 = tail call fastcc i32 @qtm_read_input(%struct.qtm_stream* %qtm) nounwind		;  [#uses=0]
+	ret i32 undef
+
+bb193:		; preds = %bb187
+	br label %bb195
+
+bb195:		; preds = %bb193, %bb186
+	br i1 undef, label %bb198, label %bb187
+
+bb197:		; preds = %bb77
+	ret i32 -124
+
+bb198:		; preds = %bb195, %bb136
+	br i1 undef, label %bb211.preheader, label %bb214
+
+bb211.preheader:		; preds = %bb198
+	br label %bb211
+
+bb211:		; preds = %bb211, %bb211.preheader
+	br i1 undef, label %bb214, label %bb211
+
+bb214:		; preds = %bb211, %bb198
+	br label %bb215
+
+bb215:		; preds = %bb238, %bb214
+	br i1 undef, label %bb28, label %bb216
+
+bb216:		; preds = %bb215
+	br label %bb238
+
+bb238:		; preds = %bb216, %bb14
+	br label %bb215
+
+bb245:		; preds = %bb5, %entry
+	ret i32 undef
+}




From evan.cheng at apple.com  Thu Jun  4 15:28:23 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 04 Jun 2009 20:28:23 -0000
Subject: [llvm-commits] [llvm] r72889 -
	/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
Message-ID: <200906042028.n54KSNQB026661@zion.cs.uiuc.edu>

Author: evancheng
Date: Thu Jun  4 15:28:22 2009
New Revision: 72889

URL: http://llvm.org/viewvc/llvm-project?rev=72889&view=rev
Log:
A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=72889&r1=72888&r2=72889&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Thu Jun  4 15:28:22 2009
@@ -542,6 +542,24 @@
     // Ignore splited live intervals.
     if (!isPhys && vrm_->getPreSplitReg(cur.reg))
       continue;
+
+    // A register defined by an implicit_def can be liveout the def BB and livein
+    // to a use BB. Add it to the livein set of the use BB's.
+    if (!isPhys && cur.empty()) {
+      if (MachineInstr *DefMI = mri_->getVRegDef(cur.reg)) {
+        assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
+        MachineBasicBlock *DefMBB = DefMI->getParent();
+        SmallPtrSet Seen;
+        Seen.insert(DefMBB);
+        for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(cur.reg),
+               re = mri_->reg_end(); ri != re; ++ri) {
+          MachineInstr *UseMI = &*ri;
+          MachineBasicBlock *UseMBB = UseMI->getParent();
+          if (Seen.insert(UseMBB))
+            UseMBB->addLiveIn(Reg);
+        }
+      }
+    }
     for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
          I != E; ++I) {
       const LiveRange &LR = *I;




From baldrick at free.fr  Thu Jun  4 15:34:43 2009
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 04 Jun 2009 22:34:43 +0200
Subject: [llvm-commits] CVS: llvm-www/demo/index.cgi
In-Reply-To: <5be2d90906020228v2b1707afh968accf7d89067a4@mail.gmail.com>
References: <200906020919.n529JArG006285@zion.cs.uiuc.edu>
	<5be2d90906020228v2b1707afh968accf7d89067a4@mail.gmail.com>
Message-ID: <4A282FE3.3050207@free.fr>

> Would it be possible to also make optimizations optional?

I've turned nest function support on for C, and added the
possibility of compiling without optimization.

Ciao,

Duncan.


From evan.cheng at apple.com  Thu Jun  4 15:53:38 2009
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 04 Jun 2009 20:53:38 -0000
Subject: [llvm-commits] [llvm] r72890 - in /llvm/trunk:
 lib/CodeGen/RegAllocLinearScan.cpp
 test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll
Message-ID: <200906042053.n54KrcqT027457@zion.cs.uiuc.edu>

Author: evancheng
Date: Thu Jun  4 15:53:36 2009
New Revision: 72890

URL: http://llvm.org/viewvc/llvm-project?rev=72890&view=rev
Log:
RALinScan::attemptTrivialCoalescing() was returning a virtual register instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets.

Added:
    llvm/trunk/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll
Modified:
    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=72890&r1=72889&r2=72890&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Thu Jun  4 15:53:36 2009
@@ -398,7 +398,7 @@
     }
 
     ++NumCoalesce;
-    return SrcReg;
+    return PhysReg;
   }
 
   return Reg;
@@ -555,8 +555,11 @@
                re = mri_->reg_end(); ri != re; ++ri) {
           MachineInstr *UseMI = &*ri;
           MachineBasicBlock *UseMBB = UseMI->getParent();
-          if (Seen.insert(UseMBB))
+          if (Seen.insert(UseMBB)) {
+            assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
+                   "Adding a virtual register to livein set?");
             UseMBB->addLiveIn(Reg);
+          }
         }
       }
     }
@@ -565,8 +568,11 @@
       const LiveRange &LR = *I;
       if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
         for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
-          if (LiveInMBBs[i] != EntryMBB)
+          if (LiveInMBBs[i] != EntryMBB) {
+            assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
+                   "Adding a virtual register to livein set?");
             LiveInMBBs[i]->addLiveIn(Reg);
+          }
         LiveInMBBs.clear();
       }
     }

Added: llvm/trunk/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll?rev=72890&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll Thu Jun  4 15:53:36 2009
@@ -0,0 +1,48 @@
+; RUN: llvm-as < %s | llc -march=x86
+
+	type { %struct.GAP }		; type %0
+	type { i16, i8, i8 }		; type %1
+	type { [2 x i32], [2 x i32] }		; type %2
+	type { %struct.rec* }		; type %3
+	%struct.FILE_POS = type { i8, i8, i16, i32 }
+	%struct.FIRST_UNION = type { %struct.FILE_POS }
+	%struct.FOURTH_UNION = type { %struct.STYLE }
+	%struct.GAP = type { i8, i8, i16 }
+	%struct.LIST = type { %struct.rec*, %struct.rec* }
+	%struct.SECOND_UNION = type { %1 }
+	%struct.STYLE = type { %0, %0, i16, i16, i32 }
+	%struct.THIRD_UNION = type { %2 }
+	%struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, %3, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 }
+	%struct.rec = type { %struct.head_type }
+
+define fastcc void @MinSize(%struct.rec* %x) nounwind {
+entry:
+	%tmp13 = load i8* undef, align 4		;  [#uses=3]
+	%tmp14 = zext i8 %tmp13 to i32		;  [#uses=2]
+	switch i32 %tmp14, label %bb1109 [
+		i32 42, label %bb246
+	]
+
+bb246:		; preds = %entry, %entry
+	switch i8 %tmp13, label %bb249 [
+		i8 42, label %bb269
+		i8 44, label %bb269
+	]
+
+bb249:		; preds = %bb246
+	%tmp3240 = icmp eq i8 %tmp13, 0		;  [#uses=1]
+	br i1 %tmp3240, label %bb974, label %bb269
+
+bb269:
+	%tmp3424 = getelementptr %struct.rec* %x, i32 0, i32 0, i32 0, i32 0, i32 1		; <%struct.rec**> [#uses=0]
+	unreachable
+
+bb974:
+	unreachable
+
+bb1109:		; preds = %entry
+	call fastcc void @Image(i32 %tmp14) nounwind		;  [#uses=0]
+	unreachable
+}
+
+declare fastcc void @Image(i32) nounwind




From dalej at apple.com  Thu Jun  4 15:53:52 2009
From: dalej at apple.com (Dale Johannesen)
Date: Thu, 04 Jun 2009 20:53:52 -0000
Subject: [llvm-commits] [llvm] r72891 - in /llvm/trunk/lib:
 CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
 Target/PowerPC/PPCISelLowering.cpp Target/PowerPC/PPCISelLowering.h
Message-ID: <200906042053.n54KrqBt027477@zion.cs.uiuc.edu>

Author: johannes
Date: Thu Jun  4 15:53:52 2009
New Revision: 72891

URL: http://llvm.org/viewvc/llvm-project?rev=72891&view=rev
Log:
Fix FP_TO_UINT->i32 on ppc32 -mcpu=g5.  This was
using Promote which won't work because i64 isn't
a legal type.  It's easy enough to use Custom, but
then we have the problem that when the type
legalizer is promoting FP_TO_UINT->i16, it has no
way of telling it should prefer FP_TO_SINT->i32
to FP_TO_UINT->i32.  I have uncomfortably hacked
this by making the type legalizer choose FP_TO_SINT
when both are Custom.
This fixes several regressions in the testsuite.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=72891&r1=72890&r2=72891&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Thu Jun  4 15:53:52 2009
@@ -356,13 +356,12 @@
   unsigned NewOpc = N->getOpcode();
   DebugLoc dl = N->getDebugLoc();
 
-  // If we're promoting a UINT to a larger size, check to see if the new node
-  // will be legal.  If it isn't, check to see if FP_TO_SINT is legal, since
-  // we can use that instead.  This allows us to generate better code for
-  // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
-  // legal, such as PowerPC.
+  // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
+  // not Legal, check to see if we can use FP_TO_SINT instead.  (If both UINT
+  // and SINT conversions are Custom, there is no way to tell which is preferable.
+  // We choose SINT because that's the right thing on PPC.)  
   if (N->getOpcode() == ISD::FP_TO_UINT &&
-      !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
+      !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
       TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
     NewOpc = ISD::FP_TO_SINT;
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=72891&r1=72890&r2=72891&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Jun  4 15:53:52 2009
@@ -227,15 +227,14 @@
     setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
     setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
     setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
-    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
+    // This is just the low 32 bits of a (signed) fp->i64 conversion.
+    // We cannot do this with Promote because i64 is not a legal type.
+    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
 
     // FIXME: disable this lowered code.  This generates 64-bit register values,
     // and we don't model the fact that the top part is clobbered by calls.  We
     // need to flag these together so that the value isn't live across a call.
     //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
-
-    // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
-    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
   } else {
     // PowerPC does not have FP_TO_UINT on 32-bit implementations.
     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
@@ -2858,7 +2857,7 @@
 }
 
 // FIXME: Split this code up when LegalizeDAGTypes lands.
-SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
+SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
                                            DebugLoc dl) {
   assert(Op.getOperand(0).getValueType().isFloatingPoint());
   SDValue Src = Op.getOperand(0);
@@ -2867,9 +2866,11 @@
 
   SDValue Tmp;
   switch (Op.getValueType().getSimpleVT()) {
-  default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
+  default: assert(0 && "Unhandled FP_TO_INT type in custom expander!");
   case MVT::i32:
-    Tmp = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Src);
+    Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
+                                                         PPCISD::FCTIDZ, 
+                      dl, MVT::f64, Src);
     break;
   case MVT::i64:
     Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
@@ -3740,7 +3741,8 @@
     return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
 
   case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
-  case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG,
+  case ISD::FP_TO_UINT:
+  case ISD::FP_TO_SINT:         return LowerFP_TO_INT(Op, DAG,
                                                        Op.getDebugLoc());
   case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG);
   case ISD::FLT_ROUNDS_:        return LowerFLT_ROUNDS_(Op, DAG);
@@ -3834,7 +3836,7 @@
     return;
   }
   case ISD::FP_TO_SINT:
-    Results.push_back(LowerFP_TO_SINT(SDValue(N, 0), DAG, dl));
+    Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
     return;
   }
 }

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=72891&r1=72890&r2=72891&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Thu Jun  4 15:53:52 2009
@@ -377,7 +377,7 @@
     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
                                       const PPCSubtarget &Subtarget);
     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
-    SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
+    SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
     SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
     SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG);




From jlerouge at apple.com  Thu Jun  4 16:56:31 2009
From: jlerouge at apple.com (Julien Lerouge)
Date: Thu, 4 Jun 2009 14:56:31 -0700
Subject: [llvm-commits] [llvm] r72650 -
	in	/llvm/trunk:include/llvm/CodeGen/JITCodeEmitter.hinclude/llvm/CodeGe	n/MachineCodeEmitter.hinclude/llvm/ExecutionEngine/JITMemoryManager.	hlib/CodeGen/MachOWriter.cpp	lib/CodeGen/MachOWriter.hlib/ExecutionEngi
In-Reply-To: 
References: <275e64e40906030958x5061eaf4l8854d665a3a8eb3d@mail.gmail.com>
	
Message-ID: <20090604215630.GA79151@pom.apple.com>

So, in the end, it seems to be coming from 72620. Sorry for the noise.
I am still working on a test case...

On Thu, Jun 04, 2009 at 02:06:56AM +0100, Aaron Gray wrote:
> It could be the main earlier patch r72631 rather than 72650. But AFAICS I 
> really doubt it.
>
> Aaron
>
-- 
Julien Lerouge
PGP Key Id: 0xB1964A62
PGP Fingerprint: 392D 4BAD DB8B CE7F 4E5F FA3C 62DB 4AA7 B196 4A62
PGP Public Key from: keyserver.pgp.com


From dpatel at apple.com  Thu Jun  4 17:05:33 2009
From: dpatel at apple.com (Devang Patel)
Date: Thu, 04 Jun 2009 22:05:33 -0000
Subject: [llvm-commits] [llvm] r72894 - in /llvm/trunk:
 include/llvm/Attributes.h include/llvm/Target/TargetOptions.h
 lib/AsmParser/LLLexer.cpp lib/AsmParser/LLParser.cpp
 lib/AsmParser/LLToken.h lib/Target/PowerPC/PPCRegisterInfo.cpp
 lib/Target/TargetMachine.cpp lib/Target/X86/X86RegisterInfo.cpp
 lib/VMCore/Attributes.cpp test/CodeGen/X86/red-zone2.ll tools/llc/llc.cpp
Message-ID: <200906042205.n54M5Ytf029806@zion.cs.uiuc.edu>

Author: dpatel
Date: Thu Jun  4 17:05:33 2009
New Revision: 72894

URL: http://llvm.org/viewvc/llvm-project?rev=72894&view=rev
Log:
Add new function attribute - noredzone. 
Update code generator to use this attribute and remove DisableRedZone target option.
Update llc to set this attribute when -disable-red-zone command line option is used.

Added:
    llvm/trunk/test/CodeGen/X86/red-zone2.ll
Modified:
    llvm/trunk/include/llvm/Attributes.h
    llvm/trunk/include/llvm/Target/TargetOptions.h
    llvm/trunk/lib/AsmParser/LLLexer.cpp
    llvm/trunk/lib/AsmParser/LLParser.cpp
    llvm/trunk/lib/AsmParser/LLToken.h
    llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
    llvm/trunk/lib/Target/TargetMachine.cpp
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/lib/VMCore/Attributes.cpp
    llvm/trunk/tools/llc/llc.cpp

Modified: llvm/trunk/include/llvm/Attributes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Attributes.h?rev=72894&r1=72893&r2=72894&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Attributes.h (original)
+++ llvm/trunk/include/llvm/Attributes.h Thu Jun  4 17:05:33 2009
@@ -54,13 +54,15 @@
                                      // stored as log2 of alignment with +1 bias
                                      // 0 means unaligned different from align 1
 const Attributes NoCapture = 1<<21; ///< Function creates no aliases of pointer
+const Attributes NoRedZone = 1<<22; /// disable redzone
 
 /// @brief Attributes that only apply to function parameters.
 const Attributes ParameterOnly = ByVal | Nest | StructRet | NoCapture;
 
 /// @brief Attributes that only apply to function.
 const Attributes FunctionOnly = NoReturn | NoUnwind | ReadNone | ReadOnly | 
-  NoInline | AlwaysInline | OptimizeForSize | StackProtect | StackProtectReq;
+  NoInline | AlwaysInline | OptimizeForSize | StackProtect | StackProtectReq |
+  NoRedZone;
 
 /// @brief Parameter attributes that do not apply to vararg call arguments.
 const Attributes VarArgsIncompatible = StructRet;

Modified: llvm/trunk/include/llvm/Target/TargetOptions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=72894&r1=72893&r2=72894&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOptions.h (original)
+++ llvm/trunk/include/llvm/Target/TargetOptions.h Thu Jun  4 17:05:33 2009
@@ -117,10 +117,6 @@
   /// wth earlier copy coalescing.
   extern bool StrongPHIElim;
 
-  /// DisableRedZone - This flag disables use of the "Red Zone" on
-  /// targets which would otherwise have one.
-  extern bool DisableRedZone;
-
 } // End llvm namespace
 
 #endif

Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=72894&r1=72893&r2=72894&view=diff

==============================================================================
--- llvm/trunk/lib/AsmParser/LLLexer.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLLexer.cpp Thu Jun  4 17:05:33 2009
@@ -547,6 +547,7 @@
   KEYWORD(optsize);
   KEYWORD(ssp);
   KEYWORD(sspreq);
+  KEYWORD(noredzone);
 
   KEYWORD(type);
   KEYWORD(opaque);

Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=72894&r1=72893&r2=72894&view=diff

==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Thu Jun  4 17:05:33 2009
@@ -730,7 +730,7 @@
     case lltok::kw_optsize:      Attrs |= Attribute::OptimizeForSize; break;
     case lltok::kw_ssp:          Attrs |= Attribute::StackProtect; break;
     case lltok::kw_sspreq:       Attrs |= Attribute::StackProtectReq; break;
-
+    case lltok::kw_noredzone:    Attrs |= Attribute::NoRedZone; break;
         
     case lltok::kw_align: {
       unsigned Alignment;

Modified: llvm/trunk/lib/AsmParser/LLToken.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=72894&r1=72893&r2=72894&view=diff

==============================================================================
--- llvm/trunk/lib/AsmParser/LLToken.h (original)
+++ llvm/trunk/lib/AsmParser/LLToken.h Thu Jun  4 17:05:33 2009
@@ -80,6 +80,7 @@
     kw_optsize,
     kw_ssp,
     kw_sspreq,
+    kw_noredzone,
 
     kw_type,
     kw_opaque,

Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=72894&r1=72893&r2=72894&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Jun  4 17:05:33 2009
@@ -908,6 +908,7 @@
   // If we are a leaf function, and use up to 224 bytes of stack space,
   // don't have a frame pointer, calls, or dynamic alloca then we do not need
   // to adjust the stack pointer (we fit in the Red Zone).
+  bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone);
   if (!DisableRedZone &&
       FrameSize <= 224 &&                          // Fits in red zone.
       !MFI->hasVarSizedObjects() &&                // No dynamic alloca.

Modified: llvm/trunk/lib/Target/TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=72894&r1=72893&r2=72894&view=diff

==============================================================================
--- llvm/trunk/lib/Target/TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/TargetMachine.cpp Thu Jun  4 17:05:33 2009
@@ -41,7 +41,6 @@
   bool RealignStack;
   bool DisableJumpTables;
   bool StrongPHIElim;
-  bool DisableRedZone;
   bool AsmVerbosityDefault(false);
 }
 
@@ -163,11 +162,6 @@
   cl::desc("Use strong PHI elimination."),
   cl::location(StrongPHIElim),
   cl::init(false));
-static cl::opt
-DisableRedZoneOption("disable-red-zone",
-  cl::desc("Do not emit code that uses the red zone."),
-  cl::location(DisableRedZone),
-  cl::init(false));
 
 //---------------------------------------------------------------------------
 // TargetMachine Class

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=72894&r1=72893&r2=72894&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Jun  4 17:05:33 2009
@@ -751,6 +751,7 @@
   // function, and use up to 128 bytes of stack space, don't have a frame
   // pointer, calls, or dynamic alloca then we do not need to adjust the
   // stack pointer (we fit in the Red Zone).
+  bool DisableRedZone = Fn->hasFnAttr(Attribute::NoRedZone);
   if (Is64Bit && !DisableRedZone &&
       !needsStackRealignment(MF) &&
       !MFI->hasVarSizedObjects() &&                // No dynamic alloca.

Modified: llvm/trunk/lib/VMCore/Attributes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Attributes.cpp?rev=72894&r1=72893&r2=72894&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Attributes.cpp (original)
+++ llvm/trunk/lib/VMCore/Attributes.cpp Thu Jun  4 17:05:33 2009
@@ -59,6 +59,8 @@
     Result += "ssp ";
   if (Attrs & Attribute::StackProtectReq)
     Result += "sspreq ";
+  if (Attrs & Attribute::NoRedZone)
+    Result += "noredzone ";
   if (Attrs & Attribute::Alignment) {
     Result += "align ";
     Result += utostr(Attribute::getAlignmentFromAttrs(Attrs));

Added: llvm/trunk/test/CodeGen/X86/red-zone2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/red-zone2.ll?rev=72894&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/red-zone2.ll (added)
+++ llvm/trunk/test/CodeGen/X86/red-zone2.ll Thu Jun  4 17:05:33 2009
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: grep subq %t | count 1
+; RUN: grep addq %t | count 1
+
+define x86_fp80 @f0(float %f) nounwind readnone noredzone {
+entry:
+	%0 = fpext float %f to x86_fp80		;  [#uses=1]
+	ret x86_fp80 %0
+}

Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=72894&r1=72893&r2=72894&view=diff

==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Thu Jun  4 17:05:33 2009
@@ -100,6 +100,11 @@
                        cl::desc("Do not verify input module"));
 
 
+static cl::opt
+DisableRedZone("disable-red-zone",
+  cl::desc("Do not emit code that uses the red zone."),
+  cl::init(false));
+
 // GetFileNameRoot - Helper function to get the basename of a filename.
 static inline std::string
 GetFileNameRoot(const std::string &InputFilename) {
@@ -336,8 +341,11 @@
     // Run our queue of passes all at once now, efficiently.
     // TODO: this could lazily stream functions out of the module.
     for (Module::iterator I = mod.begin(), E = mod.end(); I != E; ++I)
-      if (!I->isDeclaration())
+      if (!I->isDeclaration()) {
+        if (DisableRedZone)
+          I->addFnAttr(Attribute::NoRedZone);
         Passes.run(*I);
+      }
 
     Passes.doFinalization();
   }




From dpatel at apple.com  Thu Jun  4 17:07:30 2009
From: dpatel at apple.com (Devang Patel)
Date: Thu, 04 Jun 2009 22:07:30 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r72895 - in /llvm-gcc-4.2/trunk/gcc:
 config/i386/llvm-i386-target.h llvm-backend.cpp
Message-ID: <200906042207.n54M7UcE029865@zion.cs.uiuc.edu>

Author: dpatel
Date: Thu Jun  4 17:07:30 2009
New Revision: 72895

URL: http://llvm.org/viewvc/llvm-project?rev=72895&view=rev
Log:
Set Attribute::NoRedZone attribute properly.

Modified:
    llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp

Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=72895&r1=72894&r2=72895&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original)
+++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Thu Jun  4 17:07:30 2009
@@ -89,9 +89,9 @@
     }                                                           \
   }
 
-#define LLVM_SET_ARCH_OPTIONS(argvec)                           \
+#define LLVM_SET_RED_ZONE_FLAG(disable_red_zone)                \
   if (TARGET_NO_RED_ZONE)                                       \
-    argvec.push_back("--disable-red-zone");
+    disable_red_zone = 1;
 
 #ifdef LLVM_ABI_H
 

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=72895&r1=72894&r2=72895&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Thu Jun  4 17:07:30 2009
@@ -78,6 +78,9 @@
 // Non-zero if libcalls should not be simplified.
 int flag_no_simplify_libcalls;
 
+// Non-zer if red-zone is disabled.
+static int flag_disable_red_zone = 0;
+
 // Global state for the LLVM backend.
 Module *TheModule = 0;
 DebugInfo *TheDebugInfo = 0;
@@ -327,8 +330,8 @@
 
   // Allow targets to specify PIC options and other stuff to the corresponding
   // LLVM backends.
-#ifdef LLVM_SET_ARCH_OPTIONS
-  LLVM_SET_ARCH_OPTIONS(Args);
+#ifdef LLVM_SET_RED_ZONE_FLAG
+  LLVM_SET_RED_ZONE_FLAG(flag_disable_red_zone)
 #endif
 #ifdef LLVM_SET_TARGET_OPTIONS
   LLVM_SET_TARGET_OPTIONS(Args);
@@ -456,6 +459,10 @@
 void performLateBackendInitialization(void) {
   // The Ada front-end sets flag_exceptions only after processing the file.
   ExceptionHandling = flag_exceptions;
+  for (Module::iterator I = TheModule->begin(), E = TheModule->end();
+       I != E; ++I)
+    if (!I->isDeclaration() && flag_disable_red_zone)
+      I->addFnAttr(Attribute::NoRedZone);
 }
 
 void llvm_lang_dependent_init(const char *Name) {




From dpatel at apple.com  Thu Jun  4 17:16:23 2009
From: dpatel at apple.com (Devang Patel)
Date: Thu, 04 Jun 2009 22:16:23 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r72896 -
	/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Message-ID: <200906042216.n54MGNnt030251@zion.cs.uiuc.edu>

Author: dpatel
Date: Thu Jun  4 17:16:22 2009
New Revision: 72896

URL: http://llvm.org/viewvc/llvm-project?rev=72896&view=rev
Log:
Fix typo.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=72896&r1=72895&r2=72896&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Thu Jun  4 17:16:22 2009
@@ -78,7 +78,7 @@
 // Non-zero if libcalls should not be simplified.
 int flag_no_simplify_libcalls;
 
-// Non-zer if red-zone is disabled.
+// Non-zero if red-zone is disabled.
 static int flag_disable_red_zone = 0;
 
 // Global state for the LLVM backend.




From jlerouge at apple.com  Thu Jun  4 17:18:16 2009
From: jlerouge at apple.com (Julien Lerouge)
Date: Thu, 4 Jun 2009 15:18:16 -0700
Subject: [llvm-commits] [llvm] r72650 -
	in	/llvm/trunk:include/llvm/CodeGen/JITCodeEmitter.hinclude/llvm/CodeGe	n/MachineCodeEmitter.hinclude/llvm/ExecutionEngine/JITMemoryManager.	hlib/CodeGen/MachOWriter.cpp	lib/CodeGen/MachOWriter.hlib/ExecutionEngi
In-Reply-To: <20090604215630.GA79151@pom.apple.com>
References: <275e64e40906030958x5061eaf4l8854d665a3a8eb3d@mail.gmail.com>
	
	<20090604215630.GA79151@pom.apple.com>
Message-ID: <20090604221816.GB79151@pom.apple.com>

On Thu, Jun 04, 2009 at 02:56:31PM -0700, Julien Lerouge wrote:
> So, in the end, it seems to be coming from 72620. Sorry for the noise.
> I am still working on a test case...
> 

Here is the test case:
$ cat t.c
#include 

int main() {
    return getchar();
}

$ llvm-gcc -c -emit-llvm -o t.bc t.c
$ lli t.bc
Assertion failed: Addr && "Code generation didn't add function to
GlobalAddress table!", file
c:/cygwin/home/jlerouge/buildbot/llvm-test-fixed-src/lib/ExecutionEngine/JIT/JIT.cpp,
line 603

This application has requested the Runtime to terminate it in an unusual
way.
Please contact the application's support team for more information.

The disassembly for the failing bytecode is attached (t.ll).

With 72618, where it's working as expected, the assembly looks like this:

------------------------------
; ModuleID = 't.bc'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
Should I file a PR ?

define i32 @main() nounwind {
entry:
        %retval = alloca i32            ;  [#uses=2]
        %0 = alloca i32         ;  [#uses=2]
        %"alloca point" = bitcast i32 0 to i32          ;  [#uses=0]
        %1 = call i32 @getchar() nounwind               ;  [#uses=1]
        store i32 %1, i32* %0, align 4
        %2 = load i32* %0, align 4              ;  [#uses=1]
        store i32 %2, i32* %retval, align 4
        br label %return

return:         ; preds = %entry
        %retval1 = load i32* %retval            ;  [#uses=1]
        ret i32 %retval1
}

declare i32 @getchar() nounwind
------------------------------

Duncan, it seems to be coming from 72619, any idea what's wrong ?

Thanks,
Julien

-- 
Julien Lerouge
PGP Key Id: 0xB1964A62
PGP Fingerprint: 392D 4BAD DB8B CE7F 4E5F FA3C 62DB 4AA7 B196 4A62
PGP Public Key from: keyserver.pgp.com
-------------- next part --------------
; ModuleID = 't.bc'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i386-pc-mingw32"
	%struct.FILE = type { i8*, i32, i8*, i32, i32, i32, i32, i8* }
@_iob = dllimport global [0 x %struct.FILE]		; <[0 x %struct.FILE]*> [#uses=3]

define i32 @main() nounwind {
entry:
	%retval = alloca i32		;  [#uses=2]
	%0 = alloca i32		;  [#uses=2]
	%"alloca point" = bitcast i32 0 to i32		;  [#uses=0]
	%1 = call i32 @getchar() nounwind		;  [#uses=1]
	store i32 %1, i32* %0, align 4
	%2 = load i32* %0, align 4		;  [#uses=1]
	store i32 %2, i32* %retval, align 4
	br label %return

return:		; preds = %entry
	%retval1 = load i32* %retval		;  [#uses=1]
	ret i32 %retval1
}

define available_externally i32 @getchar() nounwind {
entry:
	%retval = alloca i32		;  [#uses=2]
	%iftmp.2 = alloca i32		;  [#uses=3]
	%0 = alloca i32		;  [#uses=2]
	%"alloca point" = bitcast i32 0 to i32		;  [#uses=0]
	%1 = load i32* getelementptr ([0 x %struct.FILE]* @_iob, i32 0, i32 0, i32 1), align 4		;  [#uses=1]
	%2 = sub i32 %1, 1		;  [#uses=1]
	store i32 %2, i32* getelementptr ([0 x %struct.FILE]* @_iob, i32 0, i32 0, i32 1), align 4
	%3 = load i32* getelementptr ([0 x %struct.FILE]* @_iob, i32 0, i32 0, i32 1), align 4		;  [#uses=1]
	%4 = icmp sge i32 %3, 0		;  [#uses=1]
	br i1 %4, label %bb, label %bb1

bb:		; preds = %entry
	%5 = load i8** getelementptr ([0 x %struct.FILE]* @_iob, i32 0, i32 0, i32 0), align 4		;  [#uses=2]
	%6 = load i8* %5, align 1		;  [#uses=1]
	%7 = zext i8 %6 to i32		;  [#uses=1]
	store i32 %7, i32* %iftmp.2, align 4
	%8 = getelementptr i8* %5, i64 1		;  [#uses=1]
	store i8* %8, i8** getelementptr ([0 x %struct.FILE]* @_iob, i32 0, i32 0, i32 0), align 4
	br label %bb2

bb1:		; preds = %entry
	%9 = call i32 @_filbuf(%struct.FILE* getelementptr ([0 x %struct.FILE]* @_iob, i32 0, i32 0)) nounwind		;  [#uses=1]
	store i32 %9, i32* %iftmp.2, align 4
	br label %bb2

bb2:		; preds = %bb1, %bb
	%10 = load i32* %iftmp.2, align 4		;  [#uses=1]
	store i32 %10, i32* %0, align 4
	%11 = load i32* %0, align 4		;  [#uses=1]
	store i32 %11, i32* %retval, align 4
	br label %return

return:		; preds = %bb2
	%retval3 = load i32* %retval		;  [#uses=1]
	ret i32 %retval3
}

declare i32 @_filbuf(%struct.FILE*) nounwind

From gohman at apple.com  Thu Jun  4 17:49:07 2009
From: gohman at apple.com (Dan Gohman)
Date: Thu, 04 Jun 2009 22:49:07 -0000
Subject: [llvm-commits] [llvm] r72897 - in /llvm/trunk: docs/ include/llvm/
 include/llvm/Support/ lib/Analysis/ lib/AsmParser/ lib/Bitcode/Reader/
 lib/Bitcode/Writer/ lib/CodeGen/SelectionDAG/ lib/ExecutionEngine/
 lib/ExecutionEngine/Interpreter/ lib/ExecutionEngine/JIT/
 lib/Target/CBackend/ lib/Target/CppBackend/ lib/Target/MSIL/
 lib/Transforms/Scalar/ lib/Transforms/Utils/ lib/VMCore/
 test/Analysis/ScalarEvolution/ test/Assembler/ test/CodeGen/ARM/
 test/CodeGen/CBackend/ test/CodeGen/CellSPU/ test/CodeGen/Generic/
 test/CodeGe...
Message-ID: <200906042249.n54MnIDH031613@zion.cs.uiuc.edu>

Author: djg
Date: Thu Jun  4 17:49:04 2009
New Revision: 72897

URL: http://llvm.org/viewvc/llvm-project?rev=72897&view=rev
Log:
Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

Modified:
    llvm/trunk/docs/LangRef.html
    llvm/trunk/include/llvm/Constants.h
    llvm/trunk/include/llvm/InstrTypes.h
    llvm/trunk/include/llvm/Instruction.def
    llvm/trunk/include/llvm/Support/ConstantFolder.h
    llvm/trunk/include/llvm/Support/IRBuilder.h
    llvm/trunk/include/llvm/Support/NoFolder.h
    llvm/trunk/include/llvm/Support/PatternMatch.h
    llvm/trunk/include/llvm/Support/TargetFolder.h
    llvm/trunk/lib/Analysis/ValueTracking.cpp
    llvm/trunk/lib/AsmParser/LLLexer.cpp
    llvm/trunk/lib/AsmParser/LLParser.cpp
    llvm/trunk/lib/AsmParser/LLToken.h
    llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
    llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
    llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
    llvm/trunk/lib/ExecutionEngine/Interpreter/Execution.cpp
    llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp
    llvm/trunk/lib/Target/CBackend/CBackend.cpp
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
    llvm/trunk/lib/Transforms/Scalar/GVN.cpp
    llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
    llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
    llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/lib/VMCore/ConstantFold.cpp
    llvm/trunk/lib/VMCore/Constants.cpp
    llvm/trunk/lib/VMCore/Instruction.cpp
    llvm/trunk/lib/VMCore/Instructions.cpp
    llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-0.ll
    llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-1.ll
    llvm/trunk/test/Analysis/ScalarEvolution/trip-count4.ll
    llvm/trunk/test/Assembler/2002-04-07-HexFloatConstants.ll
    llvm/trunk/test/Assembler/2002-04-07-InfConstant.ll
    llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
    llvm/trunk/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
    llvm/trunk/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
    llvm/trunk/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
    llvm/trunk/test/CodeGen/ARM/cse-libcalls.ll
    llvm/trunk/test/CodeGen/ARM/fixunsdfdi.ll
    llvm/trunk/test/CodeGen/ARM/fnmul.ll
    llvm/trunk/test/CodeGen/ARM/fparith.ll
    llvm/trunk/test/CodeGen/ARM/fpmem.ll
    llvm/trunk/test/CodeGen/ARM/illegal-vector-bitcast.ll
    llvm/trunk/test/CodeGen/ARM/vfp.ll
    llvm/trunk/test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll
    llvm/trunk/test/CodeGen/CBackend/2008-10-21-PPCLongDoubleConstant.ll
    llvm/trunk/test/CodeGen/CBackend/vectors.ll
    llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll
    llvm/trunk/test/CodeGen/CellSPU/fneg-fabs.ll
    llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll
    llvm/trunk/test/CodeGen/Generic/2006-07-03-schedulers.ll
    llvm/trunk/test/CodeGen/Generic/2007-05-15-InfiniteRecursion.ll
    llvm/trunk/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll
    llvm/trunk/test/CodeGen/Generic/2008-02-25-NegateZero.ll
    llvm/trunk/test/CodeGen/Generic/2008-02-26-NegatableCrash.ll
    llvm/trunk/test/CodeGen/Generic/fneg-fabs.ll
    llvm/trunk/test/CodeGen/Generic/print-arith-fp.ll
    llvm/trunk/test/CodeGen/Generic/select.ll
    llvm/trunk/test/CodeGen/Generic/storetrunc-fp.ll
    llvm/trunk/test/CodeGen/Generic/v-split.ll
    llvm/trunk/test/CodeGen/Generic/vector.ll
    llvm/trunk/test/CodeGen/MSP430/2009-05-19-DoubleSplit.ll
    llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll
    llvm/trunk/test/CodeGen/Mips/2008-07-22-Cstpool.ll
    llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll
    llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll
    llvm/trunk/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll
    llvm/trunk/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll
    llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll
    llvm/trunk/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll
    llvm/trunk/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
    llvm/trunk/test/CodeGen/PowerPC/2008-07-15-Fabs.ll
    llvm/trunk/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
    llvm/trunk/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll
    llvm/trunk/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll
    llvm/trunk/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
    llvm/trunk/test/CodeGen/PowerPC/buildvec_canonicalize.ll
    llvm/trunk/test/CodeGen/PowerPC/fma.ll
    llvm/trunk/test/CodeGen/PowerPC/fnabs.ll
    llvm/trunk/test/CodeGen/PowerPC/fneg.ll
    llvm/trunk/test/CodeGen/PowerPC/int-fp-conv-1.ll
    llvm/trunk/test/CodeGen/PowerPC/itofp128.ll
    llvm/trunk/test/CodeGen/PowerPC/mem-rr-addr-mode.ll
    llvm/trunk/test/CodeGen/PowerPC/multiple-return-values.ll
    llvm/trunk/test/CodeGen/PowerPC/ppcf128-1-opt.ll
    llvm/trunk/test/CodeGen/PowerPC/ppcf128-1.ll
    llvm/trunk/test/CodeGen/PowerPC/ppcf128-2.ll
    llvm/trunk/test/CodeGen/PowerPC/ppcf128-4.ll
    llvm/trunk/test/CodeGen/PowerPC/return-val-i128.ll
    llvm/trunk/test/CodeGen/PowerPC/unsafe-math.ll
    llvm/trunk/test/CodeGen/PowerPC/vec_fneg.ll
    llvm/trunk/test/CodeGen/PowerPC/vec_splat.ll
    llvm/trunk/test/CodeGen/PowerPC/vec_zero.ll
    llvm/trunk/test/CodeGen/PowerPC/vector.ll
    llvm/trunk/test/CodeGen/SPARC/2006-01-22-BitConvertLegalize.ll
    llvm/trunk/test/CodeGen/X86/2005-05-08-FPStackifierPHI.ll
    llvm/trunk/test/CodeGen/X86/2006-05-25-CycleInDAG.ll
    llvm/trunk/test/CodeGen/X86/2007-01-08-InstrSched.ll
    llvm/trunk/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
    llvm/trunk/test/CodeGen/X86/2007-03-01-SpillerCrash.ll
    llvm/trunk/test/CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
    llvm/trunk/test/CodeGen/X86/2007-04-24-VectorCrash.ll
    llvm/trunk/test/CodeGen/X86/2007-06-29-VecFPConstantCSEBug.ll
    llvm/trunk/test/CodeGen/X86/2007-07-10-StackerAssert.ll
    llvm/trunk/test/CodeGen/X86/2007-09-18-ShuffleXformBug.ll
    llvm/trunk/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll
    llvm/trunk/test/CodeGen/X86/2007-11-02-BadAsm.ll
    llvm/trunk/test/CodeGen/X86/2007-11-06-InstrSched.ll
    llvm/trunk/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
    llvm/trunk/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll
    llvm/trunk/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll
    llvm/trunk/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll
    llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll
    llvm/trunk/test/CodeGen/X86/2008-02-27-DeadSlotElimBug.ll
    llvm/trunk/test/CodeGen/X86/2008-02-27-PEICrash.ll
    llvm/trunk/test/CodeGen/X86/2008-03-18-CoalescerBug.ll
    llvm/trunk/test/CodeGen/X86/2008-03-25-TwoAddrPassBug.ll
    llvm/trunk/test/CodeGen/X86/2008-07-19-movups-spills.ll
    llvm/trunk/test/CodeGen/X86/2008-07-23-VSetCC.ll
    llvm/trunk/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
    llvm/trunk/test/CodeGen/X86/2008-10-27-CoalescerBug.ll
    llvm/trunk/test/CodeGen/X86/2008-11-03-F80VAARG.ll
    llvm/trunk/test/CodeGen/X86/2008-12-05-SpillerCrash.ll
    llvm/trunk/test/CodeGen/X86/2009-01-16-UIntToFP.ll
    llvm/trunk/test/CodeGen/X86/2009-02-12-SpillerBug.ll
    llvm/trunk/test/CodeGen/X86/2009-02-25-CommuteBug.ll
    llvm/trunk/test/CodeGen/X86/2009-03-03-BitcastLongDouble.ll
    llvm/trunk/test/CodeGen/X86/2009-03-09-SpillerBug.ll
    llvm/trunk/test/CodeGen/X86/2009-03-12-CPAlignBug.ll
    llvm/trunk/test/CodeGen/X86/break-anti-dependencies.ll
    llvm/trunk/test/CodeGen/X86/coalescer-commute1.ll
    llvm/trunk/test/CodeGen/X86/coalescer-commute2.ll
    llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll
    llvm/trunk/test/CodeGen/X86/complex-fca.ll
    llvm/trunk/test/CodeGen/X86/constant-pool-remat-0.ll
    llvm/trunk/test/CodeGen/X86/extract-combine.ll
    llvm/trunk/test/CodeGen/X86/fabs.ll
    llvm/trunk/test/CodeGen/X86/fast-isel.ll
    llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll
    llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-2.ll
    llvm/trunk/test/CodeGen/X86/fp-in-intregs.ll
    llvm/trunk/test/CodeGen/X86/fp-stack-compare.ll
    llvm/trunk/test/CodeGen/X86/fp_constant_op.ll
    llvm/trunk/test/CodeGen/X86/fp_load_fold.ll
    llvm/trunk/test/CodeGen/X86/fsxor-alignment.ll
    llvm/trunk/test/CodeGen/X86/full-lsr.ll
    llvm/trunk/test/CodeGen/X86/illegal-vector-args-return.ll
    llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll
    llvm/trunk/test/CodeGen/X86/inline-asm-mrv.ll
    llvm/trunk/test/CodeGen/X86/inline-asm-x-scalar.ll
    llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll
    llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll
    llvm/trunk/test/CodeGen/X86/masked-iv-unsafe.ll
    llvm/trunk/test/CodeGen/X86/multiple-return-values.ll
    llvm/trunk/test/CodeGen/X86/neg_fp.ll
    llvm/trunk/test/CodeGen/X86/negate-add-zero.ll
    llvm/trunk/test/CodeGen/X86/negative-sin.ll
    llvm/trunk/test/CodeGen/X86/peep-test-0.ll
    llvm/trunk/test/CodeGen/X86/peep-test-1.ll
    llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce.ll
    llvm/trunk/test/CodeGen/X86/pr2656.ll
    llvm/trunk/test/CodeGen/X86/pr3154.ll
    llvm/trunk/test/CodeGen/X86/pr3457.ll
    llvm/trunk/test/CodeGen/X86/pre-split1.ll
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    llvm/trunk/test/CodeGen/X86/pre-split4.ll
    llvm/trunk/test/CodeGen/X86/pre-split5.ll
    llvm/trunk/test/CodeGen/X86/pre-split6.ll
    llvm/trunk/test/CodeGen/X86/pre-split7.ll
    llvm/trunk/test/CodeGen/X86/pre-split8.ll
    llvm/trunk/test/CodeGen/X86/pre-split9.ll
    llvm/trunk/test/CodeGen/X86/shrink-fp-const1.ll
    llvm/trunk/test/CodeGen/X86/small-byval-memcpy.ll
    llvm/trunk/test/CodeGen/X86/soft-fp.ll
    llvm/trunk/test/CodeGen/X86/sse-align-0.ll
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    llvm/trunk/test/CodeGen/X86/sse-fcopysign.ll
    llvm/trunk/test/CodeGen/X86/sse41-extractps-bitcast-1.ll
    llvm/trunk/test/CodeGen/X86/stack-align.ll
    llvm/trunk/test/CodeGen/X86/storetrunc-fp.ll
    llvm/trunk/test/CodeGen/X86/stride-reuse.ll
    llvm/trunk/test/CodeGen/X86/twoaddr-coalesce-2.ll
    llvm/trunk/test/CodeGen/X86/vec_extract.ll
    llvm/trunk/test/CodeGen/X86/vec_fneg.ll
    llvm/trunk/test/CodeGen/X86/vec_ins_extract.ll
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    llvm/trunk/test/CodeGen/X86/vec_logical.ll
    llvm/trunk/test/CodeGen/X86/vec_select.ll
    llvm/trunk/test/CodeGen/X86/vec_shuffle-27.ll
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    llvm/trunk/test/CodeGen/X86/vec_zero.ll
    llvm/trunk/test/CodeGen/X86/vector.ll
    llvm/trunk/test/CodeGen/X86/widen_arith-6.ll
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    llvm/trunk/test/CodeGen/XCore/2009-01-14-Remat-Crash.ll
    llvm/trunk/test/CodeGen/XCore/fneg.ll
    llvm/trunk/test/ExecutionEngine/2003-01-10-FUCOM.ll
    llvm/trunk/test/ExecutionEngine/test-fp.ll
    llvm/trunk/test/ExecutionEngine/test-setcond-fp.ll
    llvm/trunk/test/Feature/ppcld.ll
    llvm/trunk/test/Feature/sparcld.ll
    llvm/trunk/test/Feature/x86ld.ll
    llvm/trunk/test/Other/2004-08-16-PackedSelect.ll
    llvm/trunk/test/Other/2004-08-16-PackedSimple.ll
    llvm/trunk/test/Other/2004-08-20-PackedControlFlow.ll
    llvm/trunk/test/Transforms/ConstProp/calls.ll
    llvm/trunk/test/Transforms/DeadStoreElimination/2006-06-27-AST-Remove.ll
    llvm/trunk/test/Transforms/GVNPRE/2007-06-18-ConstantInPhi.ll
    llvm/trunk/test/Transforms/GlobalOpt/2008-01-29-VolatileGlobal.ll
    llvm/trunk/test/Transforms/GlobalOpt/2008-04-26-SROA-Global-Align.ll
    llvm/trunk/test/Transforms/GlobalOpt/constantexpr-dangle.ll
    llvm/trunk/test/Transforms/IndVarSimplify/2006-12-10-BitCast.ll
    llvm/trunk/test/Transforms/IndVarSimplify/2008-11-03-Floating.ll
    llvm/trunk/test/Transforms/IndVarSimplify/2008-11-17-Floating.ll
    llvm/trunk/test/Transforms/IndVarSimplify/2008-11-25-APFloatAssert.ll
    llvm/trunk/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll
    llvm/trunk/test/Transforms/IndVarSimplify/iv-zext.ll
    llvm/trunk/test/Transforms/InstCombine/2006-10-26-VectorReassoc.ll
    llvm/trunk/test/Transforms/InstCombine/2006-12-01-BadFPVectorXform.ll
    llvm/trunk/test/Transforms/InstCombine/2008-07-16-fsub.ll
    llvm/trunk/test/Transforms/InstCombine/add-sitofp.ll
    llvm/trunk/test/Transforms/InstCombine/dce-iterate.ll
    llvm/trunk/test/Transforms/InstCombine/fpextend.ll
    llvm/trunk/test/Transforms/InstCombine/mul.ll
    llvm/trunk/test/Transforms/InstCombine/multi-use-or.ll
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    llvm/trunk/test/Transforms/InstCombine/sitofp.ll
    llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts.ll
    llvm/trunk/test/Transforms/InstCombine/vec_narrow.ll
    llvm/trunk/test/Transforms/InstCombine/zero-point-zero-add.ll
    llvm/trunk/test/Transforms/LCSSA/2007-07-12-LICM-2.ll
    llvm/trunk/test/Transforms/LCSSA/2007-07-12-LICM-3.ll
    llvm/trunk/test/Transforms/LCSSA/2007-07-12-LICM.ll
    llvm/trunk/test/Transforms/LoopIndexSplit/2007-09-24-UpdateIterationSpace.ll
    llvm/trunk/test/Transforms/LoopIndexSplit/2007-09-25-UpdateIterationSpace-2.ll
    llvm/trunk/test/Transforms/Mem2Reg/PromoteMemToRegister.ll
    llvm/trunk/test/Transforms/MemCpyOpt/memcpy.ll
    llvm/trunk/test/Transforms/MemCpyOpt/sret.ll
    llvm/trunk/test/Transforms/PruneEH/2008-09-05-CGUpdate.ll
    llvm/trunk/test/Transforms/Reassociate/2006-04-27-ReassociateVector.ll
    llvm/trunk/test/Transforms/SCCP/2006-12-04-PackedType.ll
    llvm/trunk/test/Transforms/SCCP/apint-ipsccp4.ll
    llvm/trunk/test/Transforms/ScalarRepl/2009-03-17-CleanUp.ll
    llvm/trunk/test/Transforms/ScalarRepl/copy-aggregate.ll
    llvm/trunk/test/Transforms/ScalarRepl/memcpy-from-global.ll
    llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll
    llvm/trunk/test/Transforms/SimplifyCFG/2006-10-29-InvokeCrash.ll
    llvm/trunk/test/Transforms/SimplifyCFG/2008-01-02-hoist-fp-add.ll
    llvm/trunk/test/Transforms/SimplifyCFG/2008-04-27-MultipleReturnCrash.ll
    llvm/trunk/test/Transforms/SimplifyCFG/2009-05-12-externweak.ll
    llvm/trunk/test/Transforms/SimplifyLibCalls/half-powr.ll
    llvm/trunk/utils/llvm.grm
    llvm/trunk/utils/vim/llvm.vim

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Thu Jun  4 17:49:04 2009
@@ -89,8 +89,11 @@
       
  • Binary Operations
         
      
           
    1. 'add' Instruction
      2. 
+          
    2. 'fadd' Instruction
      3. 
           
    3. 'sub' Instruction
      4. 
+          
    4. 'fsub' Instruction
      5. 
           
    5. 'mul' Instruction
      6. 
+          
    6. 'fmul' Instruction
      7. 
           
    7. 'udiv' Instruction
      8. 
           
    8. 'sdiv' Instruction
      9. 
           
    9. 'fdiv' Instruction
      10. 
@@ -2503,16 +2506,15 @@
 
      Arguments:
      
 
 
      The two arguments to the 'add' instruction must be integer, floating point, or
- vector values. Both arguments must have identical
- types.
      
+ href="#t_integer">integer or
+ vector of integer values. Both arguments must
+ have identical types.
      
 
 
      Semantics:
      
 
-
      The value produced is the integer or floating point sum of the two
-operands.
      
+
      The value produced is the integer sum of the two operands.
      
 
-
      If an integer sum has unsigned overflow, the result returned is the
+
      If the sum has unsigned overflow, the result returned is the
 mathematical result modulo 2n, where n is the bit width of
 the result.
      
 
@@ -2527,6 +2529,39 @@
 
    • 
 
 
    
+  'fadd' Instruction
+
    
+
+
    
+
+
    Syntax:
    
+
+
    +  <result> = fadd <ty> <op1>, <op2>   ; yields {ty}:result
+
    
+
+
    Overview:
    
+
+
    The 'fadd' instruction returns the sum of its two operands.
    
+
+
    Arguments:
    
+
+
    The two arguments to the 'fadd' instruction must be
+floating point or vector of
+floating point values. Both arguments must have identical types.
    
+
+
    Semantics:
    
+
+
    The value produced is the floating point sum of the two operands.
    
+
+
    Example:
    
+
+
    +  <result> = fadd float 4.0, %var          ; yields {float}:result = 4.0 + %var
+
    
+
    
+
+
    
    'sub' Instruction
 
    
 
@@ -2550,16 +2585,14 @@
 
    Arguments:
    
 
 
    The two arguments to the 'sub' instruction must be integer, floating point,
- or vector values.  Both arguments must have identical
- types.
    
+ href="#t_integer">integer or vector of
+ integer values.  Both arguments must have identical types.
    
 
 
    Semantics:
    
 
-
    The value produced is the integer or floating point difference of
-the two operands.
    
+
    The value produced is the integer difference of the two operands.
    
 
-
    If an integer difference has unsigned overflow, the result returned is the
+
    If the difference has unsigned overflow, the result returned is the
 mathematical result modulo 2n, where n is the bit width of
 the result.
    
 
@@ -2575,6 +2608,45 @@
 
 
 
    
+   'fsub' Instruction
+
    
+
+
    
+
+
    Syntax:
    
+
+
    +  <result> = fsub <ty> <op1>, <op2>   ; yields {ty}:result
+
    
+
+
    Overview:
    
+
+
    The 'fsub' instruction returns the difference of its two
+operands.
    
+
+
    Note that the 'fsub' instruction is used to represent the
+'fneg' instruction present in most other intermediate
+representations.
    
+
+
    Arguments:
    
+
+
    The two arguments to the 'fsub' instruction must be floating point or vector
+ of floating point values.  Both arguments must have identical types.
    
+
+
    Semantics:
    
+
+
    The value produced is the floating point difference of the two operands.
    
+
+
    Example:
    
+
    +  <result> = fsub float 4.0, %var           ; yields {float}:result = 4.0 - %var
+  <result> = fsub float -0.0, %val          ; yields {float}:result = -%var
+
    
+
    
+
+
+
    
   'mul' Instruction
 
    
 
@@ -2590,16 +2662,14 @@
 
    Arguments:
    
 
 
    The two arguments to the 'mul' instruction must be integer, floating point,
-or vector values.  Both arguments must have identical
-types.
    
+href="#t_integer">integer or vector of integer
+values.  Both arguments must have identical types.
    
  
 
    Semantics:
    
 
-
    The value produced is the integer or floating point product of the
-two operands.
    
+
    The value produced is the integer product of the two operands.
    
 
-
    If the result of an integer multiplication has unsigned overflow,
+
    If the result of the multiplication has unsigned overflow,
 the result returned is the mathematical result modulo 
 2n, where n is the bit width of the result.
    
 
    Because LLVM integers use a two's complement representation, and the
@@ -2614,6 +2684,35 @@
 
 
 
+
    
+  'fmul' Instruction
+
    
+
+
    
+
+
    Syntax:
    
+
      <result> = fmul <ty> <op1>, <op2>   ; yields {ty}:result
+
    
+
    Overview:
    
+
    The  'fmul' instruction returns the product of its two
+operands.
    
+
+
    Arguments:
    
+
+
    The two arguments to the 'fmul' instruction must be
+floating point or vector
+of floating point values.  Both arguments must have identical types.
    
+
+
    Semantics:
    
+
+
    The value produced is the floating point product of the two operands.
    
+
+
    Example:
    
+
      <result> = fmul float 4.0, %var          ; yields {float}:result = 4.0 * %var
+
    
+
    
+
+
 
     'udiv' Instruction
 
    
 
    

Modified: llvm/trunk/include/llvm/Constants.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Constants.h (original)
+++ llvm/trunk/include/llvm/Constants.h Thu Jun  4 17:49:04 2009
@@ -704,10 +704,14 @@
   /// specify the full Instruction::OPCODE identifier.
   ///
   static Constant *getNeg(Constant *C);
+  static Constant *getFNeg(Constant *C);
   static Constant *getNot(Constant *C);
   static Constant *getAdd(Constant *C1, Constant *C2);
+  static Constant *getFAdd(Constant *C1, Constant *C2);
   static Constant *getSub(Constant *C1, Constant *C2);
+  static Constant *getFSub(Constant *C1, Constant *C2);
   static Constant *getMul(Constant *C1, Constant *C2);
+  static Constant *getFMul(Constant *C1, Constant *C2);
   static Constant *getUDiv(Constant *C1, Constant *C2);
   static Constant *getSDiv(Constant *C1, Constant *C2);
   static Constant *getFDiv(Constant *C1, Constant *C2);

Modified: llvm/trunk/include/llvm/InstrTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InstrTypes.h?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/include/llvm/InstrTypes.h (original)
+++ llvm/trunk/include/llvm/InstrTypes.h Thu Jun  4 17:49:04 2009
@@ -204,21 +204,30 @@
                                    Instruction *InsertBefore = 0);
   static BinaryOperator *CreateNeg(Value *Op, const std::string &Name,
                                    BasicBlock *InsertAtEnd);
+  static BinaryOperator *CreateFNeg(Value *Op, const std::string &Name = "",
+                                    Instruction *InsertBefore = 0);
+  static BinaryOperator *CreateFNeg(Value *Op, const std::string &Name,
+                                    BasicBlock *InsertAtEnd);
   static BinaryOperator *CreateNot(Value *Op, const std::string &Name = "",
                                    Instruction *InsertBefore = 0);
   static BinaryOperator *CreateNot(Value *Op, const std::string &Name,
                                    BasicBlock *InsertAtEnd);
 
-  /// isNeg, isNot - Check if the given Value is a NEG or NOT instruction.
+  /// isNeg, isFNeg, isNot - Check if the given Value is a
+  /// NEG, FNeg, or NOT instruction.
   ///
   static bool isNeg(const Value *V);
+  static bool isFNeg(const Value *V);
   static bool isNot(const Value *V);
 
   /// getNegArgument, getNotArgument - Helper functions to extract the
-  ///     unary argument of a NEG or NOT operation implemented via Sub or Xor.
+  ///     unary argument of a NEG, FNEG or NOT operation implemented via
+  ///     Sub, FSub, or Xor.
   ///
   static const Value *getNegArgument(const Value *BinOp);
   static       Value *getNegArgument(      Value *BinOp);
+  static const Value *getFNegArgument(const Value *BinOp);
+  static       Value *getFNegArgument(      Value *BinOp);
   static const Value *getNotArgument(const Value *BinOp);
   static       Value *getNotArgument(      Value *BinOp);
 

Modified: llvm/trunk/include/llvm/Instruction.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instruction.def?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Instruction.def (original)
+++ llvm/trunk/include/llvm/Instruction.def Thu Jun  4 17:49:04 2009
@@ -105,71 +105,74 @@
 // Standard binary operators...
  FIRST_BINARY_INST( 7)
 HANDLE_BINARY_INST( 7, Add  , BinaryOperator)
-HANDLE_BINARY_INST( 8, Sub  , BinaryOperator)
-HANDLE_BINARY_INST( 9, Mul  , BinaryOperator)
-HANDLE_BINARY_INST(10, UDiv , BinaryOperator)
-HANDLE_BINARY_INST(11, SDiv , BinaryOperator)
-HANDLE_BINARY_INST(12, FDiv , BinaryOperator)
-HANDLE_BINARY_INST(13, URem , BinaryOperator)
-HANDLE_BINARY_INST(14, SRem , BinaryOperator)
-HANDLE_BINARY_INST(15, FRem , BinaryOperator)
+HANDLE_BINARY_INST( 8, FAdd  , BinaryOperator)
+HANDLE_BINARY_INST( 9, Sub  , BinaryOperator)
+HANDLE_BINARY_INST(10, FSub  , BinaryOperator)
+HANDLE_BINARY_INST(11, Mul  , BinaryOperator)
+HANDLE_BINARY_INST(12, FMul  , BinaryOperator)
+HANDLE_BINARY_INST(13, UDiv , BinaryOperator)
+HANDLE_BINARY_INST(14, SDiv , BinaryOperator)
+HANDLE_BINARY_INST(15, FDiv , BinaryOperator)
+HANDLE_BINARY_INST(16, URem , BinaryOperator)
+HANDLE_BINARY_INST(17, SRem , BinaryOperator)
+HANDLE_BINARY_INST(18, FRem , BinaryOperator)
 
 // Logical operators (integer operands)
-HANDLE_BINARY_INST(16, Shl  , BinaryOperator) // Shift left  (logical)
-HANDLE_BINARY_INST(17, LShr , BinaryOperator) // Shift right (logical) 
-HANDLE_BINARY_INST(18, AShr , BinaryOperator) // Shift right (arithmetic)
-HANDLE_BINARY_INST(19, And  , BinaryOperator)
-HANDLE_BINARY_INST(20, Or   , BinaryOperator)
-HANDLE_BINARY_INST(21, Xor  , BinaryOperator)
-  LAST_BINARY_INST(21)
+HANDLE_BINARY_INST(19, Shl  , BinaryOperator) // Shift left  (logical)
+HANDLE_BINARY_INST(20, LShr , BinaryOperator) // Shift right (logical)
+HANDLE_BINARY_INST(21, AShr , BinaryOperator) // Shift right (arithmetic)
+HANDLE_BINARY_INST(22, And  , BinaryOperator)
+HANDLE_BINARY_INST(23, Or   , BinaryOperator)
+HANDLE_BINARY_INST(24, Xor  , BinaryOperator)
+  LAST_BINARY_INST(24)
 
 // Memory operators...
- FIRST_MEMORY_INST(22)
-HANDLE_MEMORY_INST(22, Malloc, MallocInst)  // Heap management instructions
-HANDLE_MEMORY_INST(23, Free  , FreeInst  )
-HANDLE_MEMORY_INST(24, Alloca, AllocaInst)  // Stack management
-HANDLE_MEMORY_INST(25, Load  , LoadInst  )  // Memory manipulation instrs
-HANDLE_MEMORY_INST(26, Store , StoreInst )
-HANDLE_MEMORY_INST(27, GetElementPtr, GetElementPtrInst)
-  LAST_MEMORY_INST(27)
+ FIRST_MEMORY_INST(25)
+HANDLE_MEMORY_INST(25, Malloc, MallocInst)  // Heap management instructions
+HANDLE_MEMORY_INST(26, Free  , FreeInst  )
+HANDLE_MEMORY_INST(27, Alloca, AllocaInst)  // Stack management
+HANDLE_MEMORY_INST(28, Load  , LoadInst  )  // Memory manipulation instrs
+HANDLE_MEMORY_INST(29, Store , StoreInst )
+HANDLE_MEMORY_INST(30, GetElementPtr, GetElementPtrInst)
+  LAST_MEMORY_INST(30)
 
 // Cast operators ...
 // NOTE: The order matters here because CastInst::isEliminableCastPair 
 // NOTE: (see Instructions.cpp) encodes a table based on this ordering.
- FIRST_CAST_INST(28)
-HANDLE_CAST_INST(28, Trunc   , TruncInst   )  // Truncate integers
-HANDLE_CAST_INST(29, ZExt    , ZExtInst    )  // Zero extend integers
-HANDLE_CAST_INST(30, SExt    , SExtInst    )  // Sign extend integers
-HANDLE_CAST_INST(31, FPToUI  , FPToUIInst  )  // floating point -> UInt
-HANDLE_CAST_INST(32, FPToSI  , FPToSIInst  )  // floating point -> SInt
-HANDLE_CAST_INST(33, UIToFP  , UIToFPInst  )  // UInt -> floating point
-HANDLE_CAST_INST(34, SIToFP  , SIToFPInst  )  // SInt -> floating point
-HANDLE_CAST_INST(35, FPTrunc , FPTruncInst )  // Truncate floating point
-HANDLE_CAST_INST(36, FPExt   , FPExtInst   )  // Extend floating point
-HANDLE_CAST_INST(37, PtrToInt, PtrToIntInst)  // Pointer -> Integer
-HANDLE_CAST_INST(38, IntToPtr, IntToPtrInst)  // Integer -> Pointer
-HANDLE_CAST_INST(39, BitCast , BitCastInst )  // Type cast
-  LAST_CAST_INST(39)
+ FIRST_CAST_INST(31)
+HANDLE_CAST_INST(31, Trunc   , TruncInst   )  // Truncate integers
+HANDLE_CAST_INST(32, ZExt    , ZExtInst    )  // Zero extend integers
+HANDLE_CAST_INST(33, SExt    , SExtInst    )  // Sign extend integers
+HANDLE_CAST_INST(34, FPToUI  , FPToUIInst  )  // floating point -> UInt
+HANDLE_CAST_INST(35, FPToSI  , FPToSIInst  )  // floating point -> SInt
+HANDLE_CAST_INST(36, UIToFP  , UIToFPInst  )  // UInt -> floating point
+HANDLE_CAST_INST(37, SIToFP  , SIToFPInst  )  // SInt -> floating point
+HANDLE_CAST_INST(38, FPTrunc , FPTruncInst )  // Truncate floating point
+HANDLE_CAST_INST(39, FPExt   , FPExtInst   )  // Extend floating point
+HANDLE_CAST_INST(40, PtrToInt, PtrToIntInst)  // Pointer -> Integer
+HANDLE_CAST_INST(41, IntToPtr, IntToPtrInst)  // Integer -> Pointer
+HANDLE_CAST_INST(42, BitCast , BitCastInst )  // Type cast
+  LAST_CAST_INST(42)
 
 // Other operators...
- FIRST_OTHER_INST(40)
-HANDLE_OTHER_INST(40, ICmp   , ICmpInst   )  // Integer comparison instruction
-HANDLE_OTHER_INST(41, FCmp   , FCmpInst   )  // Floating point comparison instr.
-HANDLE_OTHER_INST(42, PHI    , PHINode    )  // PHI node instruction
-HANDLE_OTHER_INST(43, Call   , CallInst   )  // Call a function
-HANDLE_OTHER_INST(44, Select , SelectInst )  // select instruction
-HANDLE_OTHER_INST(45, UserOp1, Instruction)  // May be used internally in a pass
-HANDLE_OTHER_INST(46, UserOp2, Instruction)  // Internal to passes only
-HANDLE_OTHER_INST(47, VAArg  , VAArgInst  )  // vaarg instruction
-HANDLE_OTHER_INST(48, ExtractElement, ExtractElementInst)// extract from vector
-HANDLE_OTHER_INST(49, InsertElement, InsertElementInst)  // insert into vector
-HANDLE_OTHER_INST(50, ShuffleVector, ShuffleVectorInst)  // shuffle two vectors.
-HANDLE_OTHER_INST(51, ExtractValue, ExtractValueInst)// extract from aggregate
-HANDLE_OTHER_INST(52, InsertValue, InsertValueInst)  // insert into aggregate
-HANDLE_OTHER_INST(53, VICmp  , VICmpInst  )  // Vec Int comparison instruction.
-HANDLE_OTHER_INST(54, VFCmp  , VFCmpInst  )  // Vec FP point comparison instr.
+ FIRST_OTHER_INST(43)
+HANDLE_OTHER_INST(43, ICmp   , ICmpInst   )  // Integer comparison instruction
+HANDLE_OTHER_INST(44, FCmp   , FCmpInst   )  // Floating point comparison instr.
+HANDLE_OTHER_INST(45, PHI    , PHINode    )  // PHI node instruction
+HANDLE_OTHER_INST(46, Call   , CallInst   )  // Call a function
+HANDLE_OTHER_INST(47, Select , SelectInst )  // select instruction
+HANDLE_OTHER_INST(48, UserOp1, Instruction)  // May be used internally in a pass
+HANDLE_OTHER_INST(49, UserOp2, Instruction)  // Internal to passes only
+HANDLE_OTHER_INST(50, VAArg  , VAArgInst  )  // vaarg instruction
+HANDLE_OTHER_INST(51, ExtractElement, ExtractElementInst)// extract from vector
+HANDLE_OTHER_INST(52, InsertElement, InsertElementInst)  // insert into vector
+HANDLE_OTHER_INST(53, ShuffleVector, ShuffleVectorInst)  // shuffle two vectors.
+HANDLE_OTHER_INST(54, ExtractValue, ExtractValueInst)// extract from aggregate
+HANDLE_OTHER_INST(55, InsertValue, InsertValueInst)  // insert into aggregate
+HANDLE_OTHER_INST(56, VICmp  , VICmpInst  )  // Vec Int comparison instruction.
+HANDLE_OTHER_INST(57, VFCmp  , VFCmpInst  )  // Vec FP point comparison instr.
 
-  LAST_OTHER_INST(55)
+  LAST_OTHER_INST(57)
 
 #undef  FIRST_TERM_INST
 #undef HANDLE_TERM_INST

Modified: llvm/trunk/include/llvm/Support/ConstantFolder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ConstantFolder.h?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/ConstantFolder.h (original)
+++ llvm/trunk/include/llvm/Support/ConstantFolder.h Thu Jun  4 17:49:04 2009
@@ -32,12 +32,21 @@
   Constant *CreateAdd(Constant *LHS, Constant *RHS) const {
     return ConstantExpr::getAdd(LHS, RHS);
   }
+  Constant *CreateFAdd(Constant *LHS, Constant *RHS) const {
+    return ConstantExpr::getFAdd(LHS, RHS);
+  }
   Constant *CreateSub(Constant *LHS, Constant *RHS) const {
     return ConstantExpr::getSub(LHS, RHS);
   }
+  Constant *CreateFSub(Constant *LHS, Constant *RHS) const {
+    return ConstantExpr::getFSub(LHS, RHS);
+  }
   Constant *CreateMul(Constant *LHS, Constant *RHS) const {
     return ConstantExpr::getMul(LHS, RHS);
   }
+  Constant *CreateFMul(Constant *LHS, Constant *RHS) const {
+    return ConstantExpr::getFMul(LHS, RHS);
+  }
   Constant *CreateUDiv(Constant *LHS, Constant *RHS) const {
     return ConstantExpr::getUDiv(LHS, RHS);
   }
@@ -87,6 +96,9 @@
   Constant *CreateNeg(Constant *C) const {
     return ConstantExpr::getNeg(C);
   }
+  Constant *CreateFNeg(Constant *C) const {
+    return ConstantExpr::getFNeg(C);
+  }
   Constant *CreateNot(Constant *C) const {
     return ConstantExpr::getNot(C);
   }

Modified: llvm/trunk/include/llvm/Support/IRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/IRBuilder.h (original)
+++ llvm/trunk/include/llvm/Support/IRBuilder.h Thu Jun  4 17:49:04 2009
@@ -175,18 +175,36 @@
         return Folder.CreateAdd(LC, RC);
     return Insert(BinaryOperator::CreateAdd(LHS, RHS), Name);
   }
+  Value *CreateFAdd(Value *LHS, Value *RHS, const char *Name = "") {
+    if (Constant *LC = dyn_cast(LHS))
+      if (Constant *RC = dyn_cast(RHS))
+        return Folder.CreateFAdd(LC, RC);
+    return Insert(BinaryOperator::CreateFAdd(LHS, RHS), Name);
+  }
   Value *CreateSub(Value *LHS, Value *RHS, const char *Name = "") {
     if (Constant *LC = dyn_cast(LHS))
       if (Constant *RC = dyn_cast(RHS))
         return Folder.CreateSub(LC, RC);
     return Insert(BinaryOperator::CreateSub(LHS, RHS), Name);
   }
+  Value *CreateFSub(Value *LHS, Value *RHS, const char *Name = "") {
+    if (Constant *LC = dyn_cast(LHS))
+      if (Constant *RC = dyn_cast(RHS))
+        return Folder.CreateFSub(LC, RC);
+    return Insert(BinaryOperator::CreateFSub(LHS, RHS), Name);
+  }
   Value *CreateMul(Value *LHS, Value *RHS, const char *Name = "") {
     if (Constant *LC = dyn_cast(LHS))
       if (Constant *RC = dyn_cast(RHS))
         return Folder.CreateMul(LC, RC);
     return Insert(BinaryOperator::CreateMul(LHS, RHS), Name);
   }
+  Value *CreateFMul(Value *LHS, Value *RHS, const char *Name = "") {
+    if (Constant *LC = dyn_cast(LHS))
+      if (Constant *RC = dyn_cast(RHS))
+        return Folder.CreateMul(LC, RC);
+    return Insert(BinaryOperator::CreateFMul(LHS, RHS), Name);
+  }
   Value *CreateUDiv(Value *LHS, Value *RHS, const char *Name = "") {
     if (Constant *LC = dyn_cast(LHS))
       if (Constant *RC = dyn_cast(RHS))

Modified: llvm/trunk/include/llvm/Support/NoFolder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/NoFolder.h?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/NoFolder.h (original)
+++ llvm/trunk/include/llvm/Support/NoFolder.h Thu Jun  4 17:49:04 2009
@@ -39,12 +39,21 @@
   Value *CreateAdd(Constant *LHS, Constant *RHS) const {
     return BinaryOperator::CreateAdd(LHS, RHS);
   }
+  Value *CreateFAdd(Constant *LHS, Constant *RHS) const {
+    return BinaryOperator::CreateFAdd(LHS, RHS);
+  }
   Value *CreateSub(Constant *LHS, Constant *RHS) const {
     return BinaryOperator::CreateSub(LHS, RHS);
   }
+  Value *CreateFSub(Constant *LHS, Constant *RHS) const {
+    return BinaryOperator::CreateFSub(LHS, RHS);
+  }
   Value *CreateMul(Constant *LHS, Constant *RHS) const {
     return BinaryOperator::CreateMul(LHS, RHS);
   }
+  Value *CreateFMul(Constant *LHS, Constant *RHS) const {
+    return BinaryOperator::CreateFMul(LHS, RHS);
+  }
   Value *CreateUDiv(Constant *LHS, Constant *RHS) const {
     return BinaryOperator::CreateUDiv(LHS, RHS);
   }

Modified: llvm/trunk/include/llvm/Support/PatternMatch.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/PatternMatch.h?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/PatternMatch.h (original)
+++ llvm/trunk/include/llvm/Support/PatternMatch.h Thu Jun  4 17:49:04 2009
@@ -157,18 +157,36 @@
 }
 
 template
+inline BinaryOp_match m_FAdd(const LHS &L,
+                                                          const RHS &R) {
+  return BinaryOp_match(L, R);
+}
+
+template
 inline BinaryOp_match m_Sub(const LHS &L,
                                                         const RHS &R) {
   return BinaryOp_match(L, R);
 }
 
 template
+inline BinaryOp_match m_FSub(const LHS &L,
+                                                          const RHS &R) {
+  return BinaryOp_match(L, R);
+}
+
+template
 inline BinaryOp_match m_Mul(const LHS &L,
                                                         const RHS &R) {
   return BinaryOp_match(L, R);
 }
 
 template
+inline BinaryOp_match m_FMul(const LHS &L,
+                                                          const RHS &R) {
+  return BinaryOp_match(L, R);
+}
+
+template
 inline BinaryOp_match m_UDiv(const LHS &L,
                                                         const RHS &R) {
   return BinaryOp_match(L, R);
@@ -494,6 +512,35 @@
 inline neg_match m_Neg(const LHS &L) { return L; }
 
 
+template
+struct fneg_match {
+  LHS_t L;
+
+  fneg_match(const LHS_t &LHS) : L(LHS) {}
+
+  template
+  bool match(OpTy *V) {
+    if (Instruction *I = dyn_cast(V))
+      if (I->getOpcode() == Instruction::FSub)
+        return matchIfFNeg(I->getOperand(0), I->getOperand(1));
+    if (ConstantExpr *CE = dyn_cast(V))
+      if (CE->getOpcode() == Instruction::FSub)
+        return matchIfFNeg(CE->getOperand(0), CE->getOperand(1));
+    if (ConstantFP *CF = dyn_cast(V))
+      return L.match(ConstantExpr::getFNeg(CF));
+    return false;
+  }
+private:
+  bool matchIfFNeg(Value *LHS, Value *RHS) {
+    return LHS == ConstantExpr::getZeroValueForNegationExpr(LHS->getType()) &&
+           L.match(RHS);
+  }
+};
+
+template
+inline fneg_match m_FNeg(const LHS &L) { return L; }
+
+
 //===----------------------------------------------------------------------===//
 // Matchers for control flow
 //

Modified: llvm/trunk/include/llvm/Support/TargetFolder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetFolder.h?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Support/TargetFolder.h (original)
+++ llvm/trunk/include/llvm/Support/TargetFolder.h Thu Jun  4 17:49:04 2009
@@ -48,12 +48,21 @@
   Constant *CreateAdd(Constant *LHS, Constant *RHS) const {
     return Fold(ConstantExpr::getAdd(LHS, RHS));
   }
+  Constant *CreateFAdd(Constant *LHS, Constant *RHS) const {
+    return Fold(ConstantExpr::getFAdd(LHS, RHS));
+  }
   Constant *CreateSub(Constant *LHS, Constant *RHS) const {
     return Fold(ConstantExpr::getSub(LHS, RHS));
   }
+  Constant *CreateFSub(Constant *LHS, Constant *RHS) const {
+    return Fold(ConstantExpr::getFSub(LHS, RHS));
+  }
   Constant *CreateMul(Constant *LHS, Constant *RHS) const {
     return Fold(ConstantExpr::getMul(LHS, RHS));
   }
+  Constant *CreateFMul(Constant *LHS, Constant *RHS) const {
+    return Fold(ConstantExpr::getFMul(LHS, RHS));
+  }
   Constant *CreateUDiv(Constant *LHS, Constant *RHS) const {
     return Fold(ConstantExpr::getUDiv(LHS, RHS));
   }
@@ -103,6 +112,9 @@
   Constant *CreateNeg(Constant *C) const {
     return Fold(ConstantExpr::getNeg(C));
   }
+  Constant *CreateFNeg(Constant *C) const {
+    return Fold(ConstantExpr::getFNeg(C));
+  }
   Constant *CreateNot(Constant *C) const {
     return Fold(ConstantExpr::getNot(C));
   }

Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Thu Jun  4 17:49:04 2009
@@ -771,7 +771,7 @@
   if (I == 0) return false;
   
   // (add x, 0.0) is guaranteed to return +0.0, not -0.0.
-  if (I->getOpcode() == Instruction::Add &&
+  if (I->getOpcode() == Instruction::FAdd &&
       isa(I->getOperand(1)) && 
       cast(I->getOperand(1))->isNullValue())
     return true;

Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/AsmParser/LLLexer.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLLexer.cpp Thu Jun  4 17:49:04 2009
@@ -591,7 +591,9 @@
   if (Len == strlen(#STR) && !memcmp(StartChar, #STR, strlen(#STR))) { \
     UIntVal = Instruction::Enum; return lltok::kw_##STR; }
 
-  INSTKEYWORD(add,   Add);  INSTKEYWORD(sub,   Sub);  INSTKEYWORD(mul,   Mul);
+  INSTKEYWORD(add,   Add);  INSTKEYWORD(fadd,   FAdd);
+  INSTKEYWORD(sub,   Sub);  INSTKEYWORD(fsub,   FSub);
+  INSTKEYWORD(mul,   Mul);  INSTKEYWORD(fmul,   FMul);
   INSTKEYWORD(udiv,  UDiv); INSTKEYWORD(sdiv,  SDiv); INSTKEYWORD(fdiv,  FDiv);
   INSTKEYWORD(urem,  URem); INSTKEYWORD(srem,  SRem); INSTKEYWORD(frem,  FRem);
   INSTKEYWORD(shl,   Shl);  INSTKEYWORD(lshr,  LShr); INSTKEYWORD(ashr,  AShr);

Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Thu Jun  4 17:49:04 2009
@@ -1835,8 +1835,11 @@
       
   // Binary Operators.
   case lltok::kw_add:
+  case lltok::kw_fadd:
   case lltok::kw_sub:
+  case lltok::kw_fsub:
   case lltok::kw_mul:
+  case lltok::kw_fmul:
   case lltok::kw_udiv:
   case lltok::kw_sdiv:
   case lltok::kw_fdiv:
@@ -2400,8 +2403,13 @@
   // Binary Operators.
   case lltok::kw_add:
   case lltok::kw_sub:
-  case lltok::kw_mul:    return ParseArithmetic(Inst, PFS, KeywordVal, 0);
-      
+  case lltok::kw_mul:
+    // API compatibility: Accept either integer or floating-point types.
+    return ParseArithmetic(Inst, PFS, KeywordVal, 0);
+  case lltok::kw_fadd:
+  case lltok::kw_fsub:
+  case lltok::kw_fmul:    return ParseArithmetic(Inst, PFS, KeywordVal, 2);
+
   case lltok::kw_udiv:
   case lltok::kw_sdiv:
   case lltok::kw_urem:

Modified: llvm/trunk/lib/AsmParser/LLToken.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/AsmParser/LLToken.h (original)
+++ llvm/trunk/lib/AsmParser/LLToken.h Thu Jun  4 17:49:04 2009
@@ -90,7 +90,8 @@
     kw_ueq, kw_une,
 
     // Instruction Opcodes (Opcode in UIntVal).
-    kw_add,  kw_sub,  kw_mul,  kw_udiv, kw_sdiv, kw_fdiv,
+    kw_add,  kw_fadd, kw_sub,  kw_fsub, kw_mul,  kw_fmul,
+    kw_udiv, kw_sdiv, kw_fdiv,
     kw_urem, kw_srem, kw_frem, kw_shl,  kw_lshr, kw_ashr,
     kw_and,  kw_or,   kw_xor,  kw_icmp, kw_fcmp, kw_vicmp, kw_vfcmp,
 

Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Thu Jun  4 17:49:04 2009
@@ -104,9 +104,12 @@
 static int GetDecodedBinaryOpcode(unsigned Val, const Type *Ty) {
   switch (Val) {
   default: return -1;
-  case bitc::BINOP_ADD:  return Instruction::Add;
-  case bitc::BINOP_SUB:  return Instruction::Sub;
-  case bitc::BINOP_MUL:  return Instruction::Mul;
+  case bitc::BINOP_ADD:
+    return Ty->isFPOrFPVector() ? Instruction::FAdd : Instruction::Add;
+  case bitc::BINOP_SUB:
+    return Ty->isFPOrFPVector() ? Instruction::FSub : Instruction::Sub;
+  case bitc::BINOP_MUL:
+    return Ty->isFPOrFPVector() ? Instruction::FMul : Instruction::Mul;
   case bitc::BINOP_UDIV: return Instruction::UDiv;
   case bitc::BINOP_SDIV:
     return Ty->isFPOrFPVector() ? Instruction::FDiv : Instruction::SDiv;

Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Thu Jun  4 17:49:04 2009
@@ -77,9 +77,12 @@
 static unsigned GetEncodedBinaryOpcode(unsigned Opcode) {
   switch (Opcode) {
   default: assert(0 && "Unknown binary instruction!");
-  case Instruction::Add:  return bitc::BINOP_ADD;
-  case Instruction::Sub:  return bitc::BINOP_SUB;
-  case Instruction::Mul:  return bitc::BINOP_MUL;
+  case Instruction::Add:
+  case Instruction::FAdd: return bitc::BINOP_ADD;
+  case Instruction::Sub:
+  case Instruction::FSub: return bitc::BINOP_SUB;
+  case Instruction::Mul:
+  case Instruction::FMul: return bitc::BINOP_MUL;
   case Instruction::UDiv: return bitc::BINOP_UDIV;
   case Instruction::FDiv:
   case Instruction::SDiv: return bitc::BINOP_SDIV;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Jun  4 17:49:04 2009
@@ -639,18 +639,18 @@
 bool
 FastISel::SelectOperator(User *I, unsigned Opcode) {
   switch (Opcode) {
-  case Instruction::Add: {
-    ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
-    return SelectBinaryOp(I, Opc);
-  }
-  case Instruction::Sub: {
-    ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
-    return SelectBinaryOp(I, Opc);
-  }
-  case Instruction::Mul: {
-    ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
-    return SelectBinaryOp(I, Opc);
-  }
+  case Instruction::Add:
+    return SelectBinaryOp(I, ISD::ADD);
+  case Instruction::FAdd:
+    return SelectBinaryOp(I, ISD::FADD);
+  case Instruction::Sub:
+    return SelectBinaryOp(I, ISD::SUB);
+  case Instruction::FSub:
+    return SelectBinaryOp(I, ISD::FSUB);
+  case Instruction::Mul:
+    return SelectBinaryOp(I, ISD::MUL);
+  case Instruction::FMul:
+    return SelectBinaryOp(I, ISD::FMUL);
   case Instruction::SDiv:
     return SelectBinaryOp(I, ISD::SDIV);
   case Instruction::UDiv:

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Thu Jun  4 17:49:04 2009
@@ -842,20 +842,6 @@
   }
 }
 
-void SelectionDAGLowering::visitAdd(User &I) {
-  if (I.getType()->isFPOrFPVector())
-    visitBinary(I, ISD::FADD);
-  else
-    visitBinary(I, ISD::ADD);
-}
-
-void SelectionDAGLowering::visitMul(User &I) {
-  if (I.getType()->isFPOrFPVector())
-    visitBinary(I, ISD::FMUL);
-  else
-    visitBinary(I, ISD::MUL);
-}
-
 SDValue SelectionDAGLowering::getValue(const Value *V) {
   SDValue &N = NodeMap[V];
   if (N.getNode()) return N;
@@ -2161,37 +2147,33 @@
 }
 
 
-void SelectionDAGLowering::visitSub(User &I) {
+void SelectionDAGLowering::visitFSub(User &I) {
   // -0.0 - X --> fneg
   const Type *Ty = I.getType();
   if (isa(Ty)) {
     if (ConstantVector *CV = dyn_cast(I.getOperand(0))) {
       const VectorType *DestTy = cast(I.getType());
       const Type *ElTy = DestTy->getElementType();
-      if (ElTy->isFloatingPoint()) {
-        unsigned VL = DestTy->getNumElements();
-        std::vector NZ(VL, ConstantFP::getNegativeZero(ElTy));
-        Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
-        if (CV == CNZ) {
-          SDValue Op2 = getValue(I.getOperand(1));
-          setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
-                                   Op2.getValueType(), Op2));
-          return;
-        }
-      }
-    }
-  }
-  if (Ty->isFloatingPoint()) {
-    if (ConstantFP *CFP = dyn_cast(I.getOperand(0)))
-      if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
+      unsigned VL = DestTy->getNumElements();
+      std::vector NZ(VL, ConstantFP::getNegativeZero(ElTy));
+      Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
+      if (CV == CNZ) {
         SDValue Op2 = getValue(I.getOperand(1));
         setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
                                  Op2.getValueType(), Op2));
         return;
       }
+    }
   }
+  if (ConstantFP *CFP = dyn_cast(I.getOperand(0)))
+    if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
+      SDValue Op2 = getValue(I.getOperand(1));
+      setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
+                               Op2.getValueType(), Op2));
+      return;
+    }
 
-  visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
+  visitBinary(I, ISD::FSUB);
 }
 
 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Thu Jun  4 17:49:04 2009
@@ -469,9 +469,12 @@
 
   void visitBinary(User &I, unsigned OpCode);
   void visitShift(User &I, unsigned Opcode);
-  void visitAdd(User &I);
-  void visitSub(User &I);
-  void visitMul(User &I);
+  void visitAdd(User &I)  { visitBinary(I, ISD::ADD); }
+  void visitFAdd(User &I) { visitBinary(I, ISD::FADD); }
+  void visitSub(User &I)  { visitBinary(I, ISD::SUB); }
+  void visitFSub(User &I);
+  void visitMul(User &I)  { visitBinary(I, ISD::MUL); }
+  void visitFMul(User &I) { visitBinary(I, ISD::FMUL); }
   void visitURem(User &I) { visitBinary(I, ISD::UREM); }
   void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
   void visitFRem(User &I) { visitBinary(I, ISD::FREM); }

Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Thu Jun  4 17:49:04 2009
@@ -573,8 +573,11 @@
       return GV;
     }
     case Instruction::Add:
+    case Instruction::FAdd:
     case Instruction::Sub:
+    case Instruction::FSub:
     case Instruction::Mul:
+    case Instruction::FMul:
     case Instruction::UDiv:
     case Instruction::SDiv:
     case Instruction::URem:
@@ -605,11 +608,11 @@
       case Type::FloatTyID:
         switch (CE->getOpcode()) {
           default: assert(0 && "Invalid float opcode"); abort();
-          case Instruction::Add:  
+          case Instruction::FAdd:
             GV.FloatVal = LHS.FloatVal + RHS.FloatVal; break;
-          case Instruction::Sub:  
+          case Instruction::FSub:
             GV.FloatVal = LHS.FloatVal - RHS.FloatVal; break;
-          case Instruction::Mul:  
+          case Instruction::FMul:
             GV.FloatVal = LHS.FloatVal * RHS.FloatVal; break;
           case Instruction::FDiv: 
             GV.FloatVal = LHS.FloatVal / RHS.FloatVal; break;
@@ -620,11 +623,11 @@
       case Type::DoubleTyID:
         switch (CE->getOpcode()) {
           default: assert(0 && "Invalid double opcode"); abort();
-          case Instruction::Add:  
+          case Instruction::FAdd:
             GV.DoubleVal = LHS.DoubleVal + RHS.DoubleVal; break;
-          case Instruction::Sub:  
+          case Instruction::FSub:
             GV.DoubleVal = LHS.DoubleVal - RHS.DoubleVal; break;
-          case Instruction::Mul:  
+          case Instruction::FMul:
             GV.DoubleVal = LHS.DoubleVal * RHS.DoubleVal; break;
           case Instruction::FDiv: 
             GV.DoubleVal = LHS.DoubleVal / RHS.DoubleVal; break;
@@ -638,15 +641,15 @@
         APFloat apfLHS = APFloat(LHS.IntVal);
         switch (CE->getOpcode()) {
           default: assert(0 && "Invalid long double opcode"); abort();
-          case Instruction::Add:  
+          case Instruction::FAdd:
             apfLHS.add(APFloat(RHS.IntVal), APFloat::rmNearestTiesToEven);
             GV.IntVal = apfLHS.bitcastToAPInt();
             break;
-          case Instruction::Sub:  
+          case Instruction::FSub:
             apfLHS.subtract(APFloat(RHS.IntVal), APFloat::rmNearestTiesToEven);
             GV.IntVal = apfLHS.bitcastToAPInt();
             break;
-          case Instruction::Mul:  
+          case Instruction::FMul:
             apfLHS.multiply(APFloat(RHS.IntVal), APFloat::rmNearestTiesToEven);
             GV.IntVal = apfLHS.bitcastToAPInt();
             break;

Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Execution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Execution.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/Interpreter/Execution.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/Interpreter/Execution.cpp Thu Jun  4 17:49:04 2009
@@ -64,45 +64,35 @@
      Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
      break
 
-#define IMPLEMENT_INTEGER_BINOP1(OP, TY) \
-   case Type::IntegerTyID: { \
-     Dest.IntVal = Src1.IntVal OP Src2.IntVal; \
-     break; \
-   }
-
-
-static void executeAddInst(GenericValue &Dest, GenericValue Src1, 
-                           GenericValue Src2, const Type *Ty) {
+static void executeFAddInst(GenericValue &Dest, GenericValue Src1,
+                            GenericValue Src2, const Type *Ty) {
   switch (Ty->getTypeID()) {
-    IMPLEMENT_INTEGER_BINOP1(+, Ty);
     IMPLEMENT_BINARY_OPERATOR(+, Float);
     IMPLEMENT_BINARY_OPERATOR(+, Double);
   default:
-    cerr << "Unhandled type for Add instruction: " << *Ty << "\n";
+    cerr << "Unhandled type for FAdd instruction: " << *Ty << "\n";
     abort();
   }
 }
 
-static void executeSubInst(GenericValue &Dest, GenericValue Src1, 
-                           GenericValue Src2, const Type *Ty) {
+static void executeFSubInst(GenericValue &Dest, GenericValue Src1,
+                            GenericValue Src2, const Type *Ty) {
   switch (Ty->getTypeID()) {
-    IMPLEMENT_INTEGER_BINOP1(-, Ty);
     IMPLEMENT_BINARY_OPERATOR(-, Float);
     IMPLEMENT_BINARY_OPERATOR(-, Double);
   default:
-    cerr << "Unhandled type for Sub instruction: " << *Ty << "\n";
+    cerr << "Unhandled type for FSub instruction: " << *Ty << "\n";
     abort();
   }
 }
 
-static void executeMulInst(GenericValue &Dest, GenericValue Src1, 
-                           GenericValue Src2, const Type *Ty) {
+static void executeFMulInst(GenericValue &Dest, GenericValue Src1,
+                            GenericValue Src2, const Type *Ty) {
   switch (Ty->getTypeID()) {
-    IMPLEMENT_INTEGER_BINOP1(*, Ty);
     IMPLEMENT_BINARY_OPERATOR(*, Float);
     IMPLEMENT_BINARY_OPERATOR(*, Double);
   default:
-    cerr << "Unhandled type for Mul instruction: " << *Ty << "\n";
+    cerr << "Unhandled type for FMul instruction: " << *Ty << "\n";
     abort();
   }
 }
@@ -550,11 +540,14 @@
   GenericValue R;   // Result
 
   switch (I.getOpcode()) {
-  case Instruction::Add:   executeAddInst  (R, Src1, Src2, Ty); break;
-  case Instruction::Sub:   executeSubInst  (R, Src1, Src2, Ty); break;
-  case Instruction::Mul:   executeMulInst  (R, Src1, Src2, Ty); break;
-  case Instruction::FDiv:  executeFDivInst (R, Src1, Src2, Ty); break;
-  case Instruction::FRem:  executeFRemInst (R, Src1, Src2, Ty); break;
+  case Instruction::Add:   R.IntVal = Src1.IntVal + Src2.IntVal; break;
+  case Instruction::Sub:   R.IntVal = Src1.IntVal - Src2.IntVal; break;
+  case Instruction::Mul:   R.IntVal = Src1.IntVal * Src2.IntVal; break;
+  case Instruction::FAdd:  executeFAddInst(R, Src1, Src2, Ty); break;
+  case Instruction::FSub:  executeFSubInst(R, Src1, Src2, Ty); break;
+  case Instruction::FMul:  executeFMulInst(R, Src1, Src2, Ty); break;
+  case Instruction::FDiv:  executeFDivInst(R, Src1, Src2, Ty); break;
+  case Instruction::FRem:  executeFRemInst(R, Src1, Src2, Ty); break;
   case Instruction::UDiv:  R.IntVal = Src1.IntVal.udiv(Src2.IntVal); break;
   case Instruction::SDiv:  R.IntVal = Src1.IntVal.sdiv(Src2.IntVal); break;
   case Instruction::URem:  R.IntVal = Src1.IntVal.urem(Src2.IntVal); break;
@@ -1258,18 +1251,21 @@
   GenericValue Dest;
   const Type * Ty = CE->getOperand(0)->getType();
   switch (CE->getOpcode()) {
-  case Instruction::Add:  executeAddInst (Dest, Op0, Op1, Ty); break;
-  case Instruction::Sub:  executeSubInst (Dest, Op0, Op1, Ty); break;
-  case Instruction::Mul:  executeMulInst (Dest, Op0, Op1, Ty); break;
+  case Instruction::Add:  Dest.IntVal = Op0.IntVal + Op1.IntVal; break;
+  case Instruction::Sub:  Dest.IntVal = Op0.IntVal - Op1.IntVal; break;
+  case Instruction::Mul:  Dest.IntVal = Op0.IntVal * Op1.IntVal; break;
+  case Instruction::FAdd: executeFAddInst(Dest, Op0, Op1, Ty); break;
+  case Instruction::FSub: executeFSubInst(Dest, Op0, Op1, Ty); break;
+  case Instruction::FMul: executeFMulInst(Dest, Op0, Op1, Ty); break;
   case Instruction::FDiv: executeFDivInst(Dest, Op0, Op1, Ty); break;
   case Instruction::FRem: executeFRemInst(Dest, Op0, Op1, Ty); break;
   case Instruction::SDiv: Dest.IntVal = Op0.IntVal.sdiv(Op1.IntVal); break;
   case Instruction::UDiv: Dest.IntVal = Op0.IntVal.udiv(Op1.IntVal); break;
   case Instruction::URem: Dest.IntVal = Op0.IntVal.urem(Op1.IntVal); break;
   case Instruction::SRem: Dest.IntVal = Op0.IntVal.srem(Op1.IntVal); break;
-  case Instruction::And:  Dest.IntVal = Op0.IntVal.And(Op1.IntVal); break;
-  case Instruction::Or:   Dest.IntVal = Op0.IntVal.Or(Op1.IntVal); break;
-  case Instruction::Xor:  Dest.IntVal = Op0.IntVal.Xor(Op1.IntVal); break;
+  case Instruction::And:  Dest.IntVal = Op0.IntVal & Op1.IntVal; break;
+  case Instruction::Or:   Dest.IntVal = Op0.IntVal | Op1.IntVal; break;
+  case Instruction::Xor:  Dest.IntVal = Op0.IntVal ^ Op1.IntVal; break;
   case Instruction::Shl:  
     Dest.IntVal = Op0.IntVal.shl(Op1.IntVal.getZExtValue());
     break;

Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Thu Jun  4 17:49:04 2009
@@ -891,8 +891,11 @@
       break;
     }
     case Instruction::Add:
+    case Instruction::FAdd:
     case Instruction::Sub:
+    case Instruction::FSub:
     case Instruction::Mul:
+    case Instruction::FMul:
     case Instruction::UDiv:
     case Instruction::SDiv:
     case Instruction::URem:

Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
+++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Thu Jun  4 17:49:04 2009
@@ -1000,8 +1000,11 @@
       Out << ')';
       return;
     case Instruction::Add:
+    case Instruction::FAdd:
     case Instruction::Sub:
+    case Instruction::FSub:
     case Instruction::Mul:
+    case Instruction::FMul:
     case Instruction::SDiv:
     case Instruction::UDiv:
     case Instruction::FDiv:
@@ -1020,9 +1023,12 @@
       bool NeedsClosingParens = printConstExprCast(CE, Static); 
       printConstantWithCast(CE->getOperand(0), CE->getOpcode());
       switch (CE->getOpcode()) {
-      case Instruction::Add: Out << " + "; break;
-      case Instruction::Sub: Out << " - "; break;
-      case Instruction::Mul: Out << " * "; break;
+      case Instruction::Add:
+      case Instruction::FAdd: Out << " + "; break;
+      case Instruction::Sub:
+      case Instruction::FSub: Out << " - "; break;
+      case Instruction::Mul:
+      case Instruction::FMul: Out << " * "; break;
       case Instruction::URem:
       case Instruction::SRem: 
       case Instruction::FRem: Out << " % "; break;
@@ -1322,8 +1328,6 @@
   case Instruction::Mul:
     // We need to cast integer arithmetic so that it is always performed
     // as unsigned, to avoid undefined behavior on overflow.
-    if (!Ty->isIntOrIntVector()) break;
-    // FALL THROUGH
   case Instruction::LShr:
   case Instruction::URem: 
   case Instruction::UDiv: NeedsExplicitCast = true; break;
@@ -1387,8 +1391,6 @@
     case Instruction::Mul:
       // We need to cast integer arithmetic so that it is always performed
       // as unsigned, to avoid undefined behavior on overflow.
-      if (!OpTy->isIntOrIntVector()) break;
-      // FALL THROUGH
     case Instruction::LShr:
     case Instruction::UDiv:
     case Instruction::URem:
@@ -1505,8 +1507,6 @@
   case Instruction::Mul:
     // We need to cast integer arithmetic so that it is always performed
     // as unsigned, to avoid undefined behavior on overflow.
-    if (!Ty->isIntOrIntVector()) break;
-    // FALL THROUGH
   case Instruction::LShr:
   case Instruction::URem: 
   case Instruction::UDiv: 
@@ -1552,8 +1552,6 @@
     case Instruction::Mul:
       // We need to cast integer arithmetic so that it is always performed
       // as unsigned, to avoid undefined behavior on overflow.
-      if (!OpTy->isIntOrIntVector()) break;
-      // FALL THROUGH
     case Instruction::LShr:
     case Instruction::UDiv:
     case Instruction::URem: // Cast to unsigned first
@@ -2602,10 +2600,14 @@
 
   // If this is a negation operation, print it out as such.  For FP, we don't
   // want to print "-0.0 - X".
-  if (BinaryOperator::isNeg(&I)) {
+  if (BinaryOperator::isNeg(&I) || BinaryOperator::isFNeg(&I)) {
     Out << "-(";
     writeOperand(BinaryOperator::getNegArgument(cast(&I)));
     Out << ")";
+  } else if (BinaryOperator::isFNeg(&I)) {
+    Out << "-(";
+    writeOperand(BinaryOperator::getFNegArgument(cast(&I)));
+    Out << ")";
   } else if (I.getOpcode() == Instruction::FRem) {
     // Output a call to fmod/fmodf instead of emitting a%b
     if (I.getType() == Type::FloatTy)
@@ -2630,9 +2632,12 @@
     writeOperandWithCast(I.getOperand(0), I.getOpcode());
 
     switch (I.getOpcode()) {
-    case Instruction::Add:  Out << " + "; break;
-    case Instruction::Sub:  Out << " - "; break;
-    case Instruction::Mul:  Out << " * "; break;
+    case Instruction::Add:
+    case Instruction::FAdd: Out << " + "; break;
+    case Instruction::Sub:
+    case Instruction::FSub: Out << " - "; break;
+    case Instruction::Mul:
+    case Instruction::FMul: Out << " * "; break;
     case Instruction::URem:
     case Instruction::SRem:
     case Instruction::FRem: Out << " % "; break;

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Thu Jun  4 17:49:04 2009
@@ -865,8 +865,11 @@
         Out << "Constant* " << constName << " = ConstantExpr::";
         switch (CE->getOpcode()) {
         case Instruction::Add:    Out << "getAdd(";  break;
+        case Instruction::FAdd:   Out << "getFAdd(";  break;
         case Instruction::Sub:    Out << "getSub("; break;
+        case Instruction::FSub:   Out << "getFSub("; break;
         case Instruction::Mul:    Out << "getMul("; break;
+        case Instruction::FMul:   Out << "getFMul("; break;
         case Instruction::UDiv:   Out << "getUDiv("; break;
         case Instruction::SDiv:   Out << "getSDiv("; break;
         case Instruction::FDiv:   Out << "getFDiv("; break;
@@ -1159,8 +1162,11 @@
       break;
     }
     case Instruction::Add:
+    case Instruction::FAdd:
     case Instruction::Sub:
+    case Instruction::FSub:
     case Instruction::Mul:
+    case Instruction::FMul:
     case Instruction::UDiv:
     case Instruction::SDiv:
     case Instruction::FDiv:
@@ -1176,8 +1182,11 @@
       Out << "BinaryOperator* " << iName << " = BinaryOperator::Create(";
       switch (I->getOpcode()) {
       case Instruction::Add: Out << "Instruction::Add"; break;
+      case Instruction::FAdd: Out << "Instruction::FAdd"; break;
       case Instruction::Sub: Out << "Instruction::Sub"; break;
+      case Instruction::FSub: Out << "Instruction::FSub"; break;
       case Instruction::Mul: Out << "Instruction::Mul"; break;
+      case Instruction::FMul: Out << "Instruction::FMul"; break;
       case Instruction::UDiv:Out << "Instruction::UDiv"; break;
       case Instruction::SDiv:Out << "Instruction::SDiv"; break;
       case Instruction::FDiv:Out << "Instruction::FDiv"; break;

Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
+++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Thu Jun  4 17:49:04 2009
@@ -1060,12 +1060,15 @@
     break;
   // Binary
   case Instruction::Add:
+  case Instruction::FAdd:
     printBinaryInstruction("add",Left,Right);
     break;
   case Instruction::Sub:
+  case Instruction::FSub:
     printBinaryInstruction("sub",Left,Right);
     break;
-  case Instruction::Mul:  
+  case Instruction::Mul:
+  case Instruction::FMul:
     printBinaryInstruction("mul",Left,Right);
     break;
   case Instruction::UDiv:
@@ -1322,12 +1325,15 @@
     printSelectInstruction(CE->getOperand(0),CE->getOperand(1),CE->getOperand(2));
     break;
   case Instruction::Add:
+  case Instruction::FAdd:
     printBinaryInstruction("add",left,right);
     break;
   case Instruction::Sub:
+  case Instruction::FSub:
     printBinaryInstruction("sub",left,right);
     break;
   case Instruction::Mul:
+  case Instruction::FMul:
     printBinaryInstruction("mul",left,right);
     break;
   case Instruction::UDiv:

Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Thu Jun  4 17:49:04 2009
@@ -59,7 +59,8 @@
 /// two values.
 namespace {
   struct VISIBILITY_HIDDEN Expression {
-    enum ExpressionOpcode { ADD, SUB, MUL, UDIV, SDIV, FDIV, UREM, SREM, 
+    enum ExpressionOpcode { ADD, FADD, SUB, FSUB, MUL, FMUL,
+                            UDIV, SDIV, FDIV, UREM, SREM,
                             FREM, SHL, LSHR, ASHR, AND, OR, XOR, ICMPEQ, 
                             ICMPNE, ICMPUGT, ICMPUGE, ICMPULT, ICMPULE, 
                             ICMPSGT, ICMPSGE, ICMPSLT, ICMPSLE, FCMPOEQ, 
@@ -200,8 +201,11 @@
   default: // THIS SHOULD NEVER HAPPEN
     assert(0 && "Binary operator with unknown opcode?");
   case Instruction::Add:  return Expression::ADD;
+  case Instruction::FAdd: return Expression::FADD;
   case Instruction::Sub:  return Expression::SUB;
+  case Instruction::FSub: return Expression::FSUB;
   case Instruction::Mul:  return Expression::MUL;
+  case Instruction::FMul: return Expression::FMUL;
   case Instruction::UDiv: return Expression::UDIV;
   case Instruction::SDiv: return Expression::SDIV;
   case Instruction::FDiv: return Expression::FDIV;

Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Thu Jun  4 17:49:04 2009
@@ -55,7 +55,8 @@
 /// two values.
 
 struct Expression {
-  enum ExpressionOpcode { ADD, SUB, MUL, UDIV, SDIV, FDIV, UREM, SREM, 
+  enum ExpressionOpcode { ADD, FADD, SUB, FSUB, MUL, FMUL,
+                          UDIV, SDIV, FDIV, UREM, SREM,
                           FREM, SHL, LSHR, ASHR, AND, OR, XOR, ICMPEQ, 
                           ICMPNE, ICMPUGT, ICMPUGE, ICMPULT, ICMPULE, 
                           ICMPSGT, ICMPSGE, ICMPSLT, ICMPSLE, FCMPOEQ, 
@@ -202,10 +203,16 @@
   switch(BO->getOpcode()) {
     case Instruction::Add:
       return Expression::ADD;
+    case Instruction::FAdd:
+      return Expression::FADD;
     case Instruction::Sub:
       return Expression::SUB;
+    case Instruction::FSub:
+      return Expression::FSUB;
     case Instruction::Mul:
       return Expression::MUL;
+    case Instruction::FMul:
+      return Expression::FMUL;
     case Instruction::UDiv:
       return Expression::UDIV;
     case Instruction::SDiv:

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Thu Jun  4 17:49:04 2009
@@ -754,7 +754,7 @@
   BinaryOperator *Incr =
     dyn_cast(PH->getIncomingValue(BackEdge));
   if (!Incr) return;
-  if (Incr->getOpcode() != Instruction::Add) return;
+  if (Incr->getOpcode() != Instruction::FAdd) return;
   ConstantFP *IncrValue = NULL;
   unsigned IncrVIndex = 1;
   if (Incr->getOperand(1) == PH)

Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Thu Jun  4 17:49:04 2009
@@ -167,8 +167,11 @@
     //   otherwise    - Change was made, replace I with returned instruction
     //
     Instruction *visitAdd(BinaryOperator &I);
+    Instruction *visitFAdd(BinaryOperator &I);
     Instruction *visitSub(BinaryOperator &I);
+    Instruction *visitFSub(BinaryOperator &I);
     Instruction *visitMul(BinaryOperator &I);
+    Instruction *visitFMul(BinaryOperator &I);
     Instruction *visitURem(BinaryOperator &I);
     Instruction *visitSRem(BinaryOperator &I);
     Instruction *visitFRem(BinaryOperator &I);
@@ -403,7 +406,8 @@
 //   0 -> undef, 1 -> Const, 2 -> Other, 3 -> Arg, 3 -> Unary, 4 -> OtherInst
 static unsigned getComplexity(Value *V) {
   if (isa(V)) {
-    if (BinaryOperator::isNeg(V) || BinaryOperator::isNot(V))
+    if (BinaryOperator::isNeg(V) || BinaryOperator::isFNeg(V) ||
+        BinaryOperator::isNot(V))
       return 3;
     return 4;
   }
@@ -576,6 +580,25 @@
   return 0;
 }
 
+// dyn_castFNegVal - Given a 'fsub' instruction, return the RHS of the
+// instruction if the LHS is a constant negative zero (which is the 'negate'
+// form).
+//
+static inline Value *dyn_castFNegVal(Value *V) {
+  if (BinaryOperator::isFNeg(V))
+    return BinaryOperator::getFNegArgument(V);
+
+  // Constants can be considered to be negated values if they can be folded.
+  if (ConstantFP *C = dyn_cast(V))
+    return ConstantExpr::getFNeg(C);
+
+  if (ConstantVector *C = dyn_cast(V))
+    if (C->getType()->getElementType()->isFloatingPoint())
+      return ConstantExpr::getFNeg(C);
+
+  return 0;
+}
+
 static inline Value *dyn_castNotVal(Value *V) {
   if (BinaryOperator::isNot(V))
     return BinaryOperator::getNotArgument(V);
@@ -1733,12 +1756,12 @@
           default: assert(0 && "Case stmts out of sync!");
           case Intrinsic::x86_sse_sub_ss:
           case Intrinsic::x86_sse2_sub_sd:
-            TmpV = InsertNewInstBefore(BinaryOperator::CreateSub(LHS, RHS,
+            TmpV = InsertNewInstBefore(BinaryOperator::CreateFSub(LHS, RHS,
                                                         II->getName()), *II);
             break;
           case Intrinsic::x86_sse_mul_ss:
           case Intrinsic::x86_sse2_mul_sd:
-            TmpV = InsertNewInstBefore(BinaryOperator::CreateMul(LHS, RHS,
+            TmpV = InsertNewInstBefore(BinaryOperator::CreateFMul(LHS, RHS,
                                                          II->getName()), *II);
             break;
           }
@@ -2052,14 +2075,8 @@
       return ReplaceInstUsesWith(I, RHS);
 
     // X + 0 --> X
-    if (!I.getType()->isFPOrFPVector()) { // NOTE: -0 + +0 = +0.
-      if (RHSC->isNullValue())
-        return ReplaceInstUsesWith(I, LHS);
-    } else if (ConstantFP *CFP = dyn_cast(RHSC)) {
-      if (CFP->isExactlyValue(ConstantFP::getNegativeZero
-                              (I.getType())->getValueAPF()))
-        return ReplaceInstUsesWith(I, LHS);
-    }
+    if (RHSC->isNullValue())
+      return ReplaceInstUsesWith(I, LHS);
 
     if (ConstantInt *CI = dyn_cast(RHSC)) {
       // X + (signbit) --> X ^ signbit
@@ -2317,11 +2334,6 @@
         return SelectInst::Create(SI->getCondition(), A, N);
     }
   }
-  
-  // Check for X+0.0.  Simplify it to X if we know X is not -0.0.
-  if (ConstantFP *CFP = dyn_cast(RHS))
-    if (CFP->getValueAPF().isPosZero() && CannotBeNegativeZero(LHS))
-      return ReplaceInstUsesWith(I, LHS);
 
   // Check for (add (sext x), y), see if we can merge this into an
   // integer add followed by a sext.
@@ -2359,7 +2371,42 @@
       }
     }
   }
-  
+
+  return Changed ? &I : 0;
+}
+
+Instruction *InstCombiner::visitFAdd(BinaryOperator &I) {
+  bool Changed = SimplifyCommutative(I);
+  Value *LHS = I.getOperand(0), *RHS = I.getOperand(1);
+
+  if (Constant *RHSC = dyn_cast(RHS)) {
+    // X + 0 --> X
+    if (ConstantFP *CFP = dyn_cast(RHSC)) {
+      if (CFP->isExactlyValue(ConstantFP::getNegativeZero
+                              (I.getType())->getValueAPF()))
+        return ReplaceInstUsesWith(I, LHS);
+    }
+
+    if (isa(LHS))
+      if (Instruction *NV = FoldOpIntoPhi(I))
+        return NV;
+  }
+
+  // -A + B  -->  B - A
+  // -A + -B  -->  -(A + B)
+  if (Value *LHSV = dyn_castFNegVal(LHS))
+    return BinaryOperator::CreateFSub(RHS, LHSV);
+
+  // A + -B  -->  A - B
+  if (!isa(RHS))
+    if (Value *V = dyn_castFNegVal(RHS))
+      return BinaryOperator::CreateFSub(LHS, V);
+
+  // Check for X+0.0.  Simplify it to X if we know X is not -0.0.
+  if (ConstantFP *CFP = dyn_cast(RHS))
+    if (CFP->getValueAPF().isPosZero() && CannotBeNegativeZero(LHS))
+      return ReplaceInstUsesWith(I, LHS);
+
   // Check for (add double (sitofp x), y), see if we can merge this into an
   // integer add followed by a promotion.
   if (SIToFPInst *LHSConv = dyn_cast(LHS)) {
@@ -2407,8 +2454,7 @@
 Instruction *InstCombiner::visitSub(BinaryOperator &I) {
   Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
 
-  if (Op0 == Op1 &&                        // sub X, X  -> 0
-      !I.getType()->isFPOrFPVector())
+  if (Op0 == Op1)                        // sub X, X  -> 0
     return ReplaceInstUsesWith(I, Constant::getNullValue(I.getType()));
 
   // If this is a 'B = x-(-A)', change to B = x+A...
@@ -2469,8 +2515,7 @@
     return BinaryOperator::CreateXor(Op0, Op1);
 
   if (BinaryOperator *Op1I = dyn_cast(Op1)) {
-    if (Op1I->getOpcode() == Instruction::Add &&
-        !Op0->getType()->isFPOrFPVector()) {
+    if (Op1I->getOpcode() == Instruction::Add) {
       if (Op1I->getOperand(0) == Op0)              // X-(X+Y) == -Y
         return BinaryOperator::CreateNeg(Op1I->getOperand(1), I.getName());
       else if (Op1I->getOperand(1) == Op0)         // X-(Y+X) == -Y
@@ -2487,8 +2532,7 @@
       // Replace (x - (y - z)) with (x + (z - y)) if the (y - z) subexpression
       // is not used by anyone else...
       //
-      if (Op1I->getOpcode() == Instruction::Sub &&
-          !Op1I->getType()->isFPOrFPVector()) {
+      if (Op1I->getOpcode() == Instruction::Sub) {
         // Swap the two operands of the subexpr...
         Value *IIOp0 = Op1I->getOperand(0), *IIOp1 = Op1I->getOperand(1);
         Op1I->setOperand(0, IIOp1);
@@ -2526,18 +2570,17 @@
     }
   }
 
-  if (!Op0->getType()->isFPOrFPVector())
-    if (BinaryOperator *Op0I = dyn_cast(Op0)) {
-      if (Op0I->getOpcode() == Instruction::Add) {
-        if (Op0I->getOperand(0) == Op1)             // (Y+X)-Y == X
-          return ReplaceInstUsesWith(I, Op0I->getOperand(1));
-        else if (Op0I->getOperand(1) == Op1)        // (X+Y)-Y == X
-          return ReplaceInstUsesWith(I, Op0I->getOperand(0));
-      } else if (Op0I->getOpcode() == Instruction::Sub) {
-        if (Op0I->getOperand(0) == Op1)             // (X-Y)-X == -Y
-          return BinaryOperator::CreateNeg(Op0I->getOperand(1), I.getName());
-      }
+  if (BinaryOperator *Op0I = dyn_cast(Op0)) {
+    if (Op0I->getOpcode() == Instruction::Add) {
+      if (Op0I->getOperand(0) == Op1)             // (Y+X)-Y == X
+        return ReplaceInstUsesWith(I, Op0I->getOperand(1));
+      else if (Op0I->getOperand(1) == Op1)        // (X+Y)-Y == X
+        return ReplaceInstUsesWith(I, Op0I->getOperand(0));
+    } else if (Op0I->getOpcode() == Instruction::Sub) {
+      if (Op0I->getOperand(0) == Op1)             // (X-Y)-X == -Y
+        return BinaryOperator::CreateNeg(Op0I->getOperand(1), I.getName());
     }
+  }
 
   ConstantInt *C1;
   if (Value *X = dyn_castFoldableMul(Op0, C1)) {
@@ -2551,6 +2594,40 @@
   return 0;
 }
 
+Instruction *InstCombiner::visitFSub(BinaryOperator &I) {
+  Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
+
+  // If this is a 'B = x-(-A)', change to B = x+A...
+  if (Value *V = dyn_castFNegVal(Op1))
+    return BinaryOperator::CreateFAdd(Op0, V);
+
+  if (BinaryOperator *Op1I = dyn_cast(Op1)) {
+    if (Op1I->getOpcode() == Instruction::FAdd) {
+      if (Op1I->getOperand(0) == Op0)              // X-(X+Y) == -Y
+        return BinaryOperator::CreateFNeg(Op1I->getOperand(1), I.getName());
+      else if (Op1I->getOperand(1) == Op0)         // X-(Y+X) == -Y
+        return BinaryOperator::CreateFNeg(Op1I->getOperand(0), I.getName());
+    }
+
+    if (Op1I->hasOneUse()) {
+      // Replace (x - (y - z)) with (x + (z - y)) if the (y - z) subexpression
+      // is not used by anyone else...
+      //
+      if (Op1I->getOpcode() == Instruction::FSub) {
+        // Swap the two operands of the subexpr...
+        Value *IIOp0 = Op1I->getOperand(0), *IIOp1 = Op1I->getOperand(1);
+        Op1I->setOperand(0, IIOp1);
+        Op1I->setOperand(1, IIOp0);
+
+        // Create the new top level fadd instruction...
+        return BinaryOperator::CreateFAdd(Op0, Op1);
+      }
+    }
+  }
+
+  return 0;
+}
+
 /// isSignBitCheck - Given an exploded icmp instruction, return true if the
 /// comparison only checks the sign bit.  If it only checks the sign bit, set
 /// TrueIfSigned if the result of the comparison is true when the input value is
@@ -2613,13 +2690,6 @@
         return BinaryOperator::CreateShl(Op0,
                  ConstantInt::get(Op0->getType(), Val.logBase2()));
       }
-    } else if (ConstantFP *Op1F = dyn_cast(Op1)) {
-      // TODO: If Op1 is zero and Op0 is finite, return zero.
-
-      // "In IEEE floating point, x*1 is not equivalent to x for nans.  However,
-      // ANSI says we can drop signals, so we can do this anyway." (from GCC)
-      if (Op1F->isExactlyValue(1.0))
-        return ReplaceInstUsesWith(I, Op0);  // Eliminate 'mul double %X, 1.0'
     } else if (isa(Op1->getType())) {
       // TODO: If Op1 is all zeros and Op0 is all finite, return all zeros.
 
@@ -2629,9 +2699,6 @@
 
         // As above, vector X*splat(1.0) -> X in all defined cases.
         if (Constant *Splat = Op1V->getSplatValue()) {
-          if (ConstantFP *F = dyn_cast(Splat))
-            if (F->isExactlyValue(1.0))
-              return ReplaceInstUsesWith(I, Op0);
           if (ConstantInt *CI = dyn_cast(Splat))
             if (CI->equalsInt(1))
               return ReplaceInstUsesWith(I, Op0);
@@ -2755,6 +2822,45 @@
   return Changed ? &I : 0;
 }
 
+Instruction *InstCombiner::visitFMul(BinaryOperator &I) {
+  bool Changed = SimplifyCommutative(I);
+  Value *Op0 = I.getOperand(0);
+
+  // Simplify mul instructions with a constant RHS...
+  if (Constant *Op1 = dyn_cast(I.getOperand(1))) {
+    if (ConstantFP *Op1F = dyn_cast(Op1)) {
+      // "In IEEE floating point, x*1 is not equivalent to x for nans.  However,
+      // ANSI says we can drop signals, so we can do this anyway." (from GCC)
+      if (Op1F->isExactlyValue(1.0))
+        return ReplaceInstUsesWith(I, Op0);  // Eliminate 'mul double %X, 1.0'
+    } else if (isa(Op1->getType())) {
+      if (ConstantVector *Op1V = dyn_cast(Op1)) {
+        // As above, vector X*splat(1.0) -> X in all defined cases.
+        if (Constant *Splat = Op1V->getSplatValue()) {
+          if (ConstantFP *F = dyn_cast(Splat))
+            if (F->isExactlyValue(1.0))
+              return ReplaceInstUsesWith(I, Op0);
+        }
+      }
+    }
+
+    // Try to fold constant mul into select arguments.
+    if (SelectInst *SI = dyn_cast(Op0))
+      if (Instruction *R = FoldOpIntoSelect(I, SI, this))
+        return R;
+
+    if (isa(Op0))
+      if (Instruction *NV = FoldOpIntoPhi(I))
+        return NV;
+  }
+
+  if (Value *Op0v = dyn_castFNegVal(Op0))     // -X * -Y = X*Y
+    if (Value *Op1v = dyn_castFNegVal(I.getOperand(1)))
+      return BinaryOperator::CreateFMul(Op0v, Op1v);
+
+  return Changed ? &I : 0;
+}
+
 /// SimplifyDivRemOfSelect - Try to fold a divide or remainder of a select
 /// instruction.
 bool InstCombiner::SimplifyDivRemOfSelect(BinaryOperator &I) {
@@ -8562,17 +8668,17 @@
   if (Instruction *I = commonCastTransforms(CI))
     return I;
   
-  // If we have fptrunc(add (fpextend x), (fpextend y)), where x and y are
+  // If we have fptrunc(fadd (fpextend x), (fpextend y)), where x and y are
   // smaller than the destination type, we can eliminate the truncate by doing
-  // the add as the smaller type.  This applies to add/sub/mul/div as well as
+  // the add as the smaller type.  This applies to fadd/fsub/fmul/fdiv as well as
   // many builtins (sqrt, etc).
   BinaryOperator *OpI = dyn_cast(CI.getOperand(0));
   if (OpI && OpI->hasOneUse()) {
     switch (OpI->getOpcode()) {
     default: break;
-    case Instruction::Add:
-    case Instruction::Sub:
-    case Instruction::Mul:
+    case Instruction::FAdd:
+    case Instruction::FSub:
+    case Instruction::FMul:
     case Instruction::FDiv:
     case Instruction::FRem:
       const Type *SrcTy = OpI->getType();
@@ -9322,11 +9428,15 @@
 
         // Turn select C, (X+Y), (X-Y) --> (X+(select C, Y, (-Y))).  This is
         // even legal for FP.
-        if (TI->getOpcode() == Instruction::Sub &&
-            FI->getOpcode() == Instruction::Add) {
+        if ((TI->getOpcode() == Instruction::Sub &&
+             FI->getOpcode() == Instruction::Add) ||
+            (TI->getOpcode() == Instruction::FSub &&
+             FI->getOpcode() == Instruction::FAdd)) {
           AddOp = FI; SubOp = TI;
-        } else if (FI->getOpcode() == Instruction::Sub &&
-                   TI->getOpcode() == Instruction::Add) {
+        } else if ((FI->getOpcode() == Instruction::Sub &&
+                    TI->getOpcode() == Instruction::Add) ||
+                   (FI->getOpcode() == Instruction::FSub &&
+                    TI->getOpcode() == Instruction::FAdd)) {
           AddOp = TI; SubOp = FI;
         }
 

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Thu Jun  4 17:49:04 2009
@@ -2268,7 +2268,8 @@
       /* create new increment. '++d' in above example. */
       ConstantFP *CFP = ConstantFP::get(DestTy, C->getZExtValue());
       BinaryOperator *NewIncr = 
-        BinaryOperator::Create(Incr->getOpcode(),
+        BinaryOperator::Create(Incr->getOpcode() == Instruction::Add ?
+                                 Instruction::FAdd : Instruction::FSub,
                                NewPH, CFP, "IV.S.next.", Incr);
 
       NewPH->addIncoming(NewInit, PH->getIncomingBlock(Entry));

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Thu Jun  4 17:49:04 2009
@@ -1009,7 +1009,7 @@
     if (Op2C->isExactlyValue(1.0))  // pow(x, 1.0) -> x
       return Op1;
     if (Op2C->isExactlyValue(2.0))  // pow(x, 2.0) -> x*x
-      return B.CreateMul(Op1, Op1, "pow2");
+      return B.CreateFMul(Op1, Op1, "pow2");
     if (Op2C->isExactlyValue(-1.0)) // pow(x, -1.0) -> 1.0/x
       return B.CreateFDiv(ConstantFP::get(CI->getType(), 1.0), Op1, "powrecip");
     return 0;

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Thu Jun  4 17:49:04 2009
@@ -419,9 +419,6 @@
       case Instruction::LShr:
       case Instruction::AShr:
       case Instruction::ICmp:
-      case Instruction::FCmp:
-        if (I->getOperand(0)->getType()->isFPOrFPVector())
-          return false;  // FP arithmetic might trap.
         break;   // These are all cheap and non-trapping instructions.
       }
 
@@ -1012,9 +1009,8 @@
   default: return false;  // Not safe / profitable to hoist.
   case Instruction::Add:
   case Instruction::Sub:
-    // FP arithmetic might trap. Not worth doing for vector ops.
-    if (HInst->getType()->isFloatingPoint() 
-        || isa(HInst->getType()))
+    // Not worth doing for vector ops.
+    if (isa(HInst->getType()))
       return false;
     break;
   case Instruction::And:

Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/ConstantFold.cpp (original)
+++ llvm/trunk/lib/VMCore/ConstantFold.cpp Thu Jun  4 17:49:04 2009
@@ -602,10 +602,8 @@
       return Constant::getNullValue(C1->getType());
     case Instruction::UDiv:
     case Instruction::SDiv:
-    case Instruction::FDiv:
     case Instruction::URem:
     case Instruction::SRem:
-    case Instruction::FRem:
       if (!isa(C2))                    // undef / X -> 0
         return Constant::getNullValue(C1->getType());
       return const_cast(C2);            // X / undef -> undef
@@ -783,13 +781,13 @@
       switch (Opcode) {
       default:                   
         break;
-      case Instruction::Add:
+      case Instruction::FAdd:
         (void)C3V.add(C2V, APFloat::rmNearestTiesToEven);
         return ConstantFP::get(C3V);
-      case Instruction::Sub:     
+      case Instruction::FSub:
         (void)C3V.subtract(C2V, APFloat::rmNearestTiesToEven);
         return ConstantFP::get(C3V);
-      case Instruction::Mul:
+      case Instruction::FMul:
         (void)C3V.multiply(C2V, APFloat::rmNearestTiesToEven);
         return ConstantFP::get(C3V);
       case Instruction::FDiv:
@@ -808,12 +806,18 @@
       switch (Opcode) {
       default:
         break;
-      case Instruction::Add: 
+      case Instruction::Add:
         return EvalVectorOp(CP1, CP2, VTy, ConstantExpr::getAdd);
-      case Instruction::Sub: 
+      case Instruction::FAdd:
+        return EvalVectorOp(CP1, CP2, VTy, ConstantExpr::getFAdd);
+      case Instruction::Sub:
         return EvalVectorOp(CP1, CP2, VTy, ConstantExpr::getSub);
-      case Instruction::Mul: 
+      case Instruction::FSub:
+        return EvalVectorOp(CP1, CP2, VTy, ConstantExpr::getFSub);
+      case Instruction::Mul:
         return EvalVectorOp(CP1, CP2, VTy, ConstantExpr::getMul);
+      case Instruction::FMul:
+        return EvalVectorOp(CP1, CP2, VTy, ConstantExpr::getFMul);
       case Instruction::UDiv:
         return EvalVectorOp(CP1, CP2, VTy, ConstantExpr::getUDiv);
       case Instruction::SDiv:
@@ -851,7 +855,9 @@
     // other way if possible.
     switch (Opcode) {
     case Instruction::Add:
+    case Instruction::FAdd:
     case Instruction::Mul:
+    case Instruction::FMul:
     case Instruction::And:
     case Instruction::Or:
     case Instruction::Xor:
@@ -862,6 +868,7 @@
     case Instruction::LShr:
     case Instruction::AShr:
     case Instruction::Sub:
+    case Instruction::FSub:
     case Instruction::SDiv:
     case Instruction::UDiv:
     case Instruction::FDiv:

Modified: llvm/trunk/lib/VMCore/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Constants.cpp (original)
+++ llvm/trunk/lib/VMCore/Constants.cpp Thu Jun  4 17:49:04 2009
@@ -775,26 +775,46 @@
 /// specify the full Instruction::OPCODE identifier.
 ///
 Constant *ConstantExpr::getNeg(Constant *C) {
+  // API compatibility: Adjust integer opcodes to floating-point opcodes.
+  if (C->getType()->isFPOrFPVector())
+    return getFNeg(C);
+  assert(C->getType()->isIntOrIntVector() &&
+         "Cannot NEG a nonintegral value!");
   return get(Instruction::Sub,
              ConstantExpr::getZeroValueForNegationExpr(C->getType()),
              C);
 }
+Constant *ConstantExpr::getFNeg(Constant *C) {
+  assert(C->getType()->isFPOrFPVector() &&
+         "Cannot FNEG a non-floating-point value!");
+  return get(Instruction::FSub,
+             ConstantExpr::getZeroValueForNegationExpr(C->getType()),
+             C);
+}
 Constant *ConstantExpr::getNot(Constant *C) {
-  assert((isa(C->getType()) ||
-            cast(C->getType())->getElementType()->isInteger()) &&
-          "Cannot NOT a nonintegral value!");
+  assert(C->getType()->isIntOrIntVector() &&
+         "Cannot NOT a nonintegral value!");
   return get(Instruction::Xor, C,
              Constant::getAllOnesValue(C->getType()));
 }
 Constant *ConstantExpr::getAdd(Constant *C1, Constant *C2) {
   return get(Instruction::Add, C1, C2);
 }
+Constant *ConstantExpr::getFAdd(Constant *C1, Constant *C2) {
+  return get(Instruction::FAdd, C1, C2);
+}
 Constant *ConstantExpr::getSub(Constant *C1, Constant *C2) {
   return get(Instruction::Sub, C1, C2);
 }
+Constant *ConstantExpr::getFSub(Constant *C1, Constant *C2) {
+  return get(Instruction::FSub, C1, C2);
+}
 Constant *ConstantExpr::getMul(Constant *C1, Constant *C2) {
   return get(Instruction::Mul, C1, C2);
 }
+Constant *ConstantExpr::getFMul(Constant *C1, Constant *C2) {
+  return get(Instruction::FMul, C1, C2);
+}
 Constant *ConstantExpr::getUDiv(Constant *C1, Constant *C2) {
   return get(Instruction::UDiv, C1, C2);
 }
@@ -2142,15 +2162,28 @@
 }
 
 Constant *ConstantExpr::get(unsigned Opcode, Constant *C1, Constant *C2) {
+  // API compatibility: Adjust integer opcodes to floating-point opcodes.
+  if (C1->getType()->isFPOrFPVector()) {
+    if (Opcode == Instruction::Add) Opcode = Instruction::FAdd;
+    else if (Opcode == Instruction::Sub) Opcode = Instruction::FSub;
+    else if (Opcode == Instruction::Mul) Opcode = Instruction::FMul;
+  }
 #ifndef NDEBUG
   switch (Opcode) {
-  case Instruction::Add: 
+  case Instruction::Add:
   case Instruction::Sub:
-  case Instruction::Mul: 
+  case Instruction::Mul:
     assert(C1->getType() == C2->getType() && "Op types should be identical!");
-    assert((C1->getType()->isInteger() || C1->getType()->isFloatingPoint() ||
-            isa(C1->getType())) &&
-           "Tried to create an arithmetic operation on a non-arithmetic type!");
+    assert(C1->getType()->isIntOrIntVector() &&
+           "Tried to create an integer operation on a non-integer type!");
+    break;
+  case Instruction::FAdd:
+  case Instruction::FSub:
+  case Instruction::FMul:
+    assert(C1->getType() == C2->getType() && "Op types should be identical!");
+    assert(C1->getType()->isFPOrFPVector() &&
+           "Tried to create a floating-point operation on a "
+           "non-floating-point type!");
     break;
   case Instruction::UDiv: 
   case Instruction::SDiv: 

Modified: llvm/trunk/lib/VMCore/Instruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Instruction.cpp (original)
+++ llvm/trunk/lib/VMCore/Instruction.cpp Thu Jun  4 17:49:04 2009
@@ -101,8 +101,11 @@
 
   // Standard binary operators...
   case Add: return "add";
+  case FAdd: return "fadd";
   case Sub: return "sub";
+  case FSub: return "fsub";
   case Mul: return "mul";
+  case FMul: return "fmul";
   case UDiv: return "udiv";
   case SDiv: return "sdiv";
   case FDiv: return "fdiv";
@@ -330,19 +333,13 @@
 
 /// isAssociative - Return true if the instruction is associative:
 ///
-///   Associative operators satisfy:  x op (y op z) === (x op y) op z)
+///   Associative operators satisfy:  x op (y op z) === (x op y) op z
 ///
-/// In LLVM, the Add, Mul, And, Or, and Xor operators are associative, when not
-/// applied to floating point types.
+/// In LLVM, the Add, Mul, And, Or, and Xor operators are associative.
 ///
 bool Instruction::isAssociative(unsigned Opcode, const Type *Ty) {
-  if (Opcode == And || Opcode == Or || Opcode == Xor)
-    return true;
-
-  // Add/Mul reassociate unless they are FP or FP vectors.
-  if (Opcode == Add || Opcode == Mul)
-    return !Ty->isFPOrFPVector();
-  return 0;
+  return Opcode == And || Opcode == Or || Opcode == Xor ||
+         Opcode == Add || Opcode == Mul;
 }
 
 /// isCommutative - Return true if the instruction is commutative:
@@ -355,7 +352,9 @@
 bool Instruction::isCommutative(unsigned op) {
   switch (op) {
   case Add:
+  case FAdd:
   case Mul:
+  case FMul:
   case And:
   case Or:
   case Xor:

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Thu Jun  4 17:49:04 2009
@@ -1502,29 +1502,43 @@
 //                             BinaryOperator Class
 //===----------------------------------------------------------------------===//
 
+/// AdjustIType - Map Add, Sub, and Mul to FAdd, FSub, and FMul when the
+/// type is floating-point, to help provide compatibility with an older API.
+///
+static BinaryOperator::BinaryOps AdjustIType(BinaryOperator::BinaryOps iType,
+                                             const Type *Ty) {
+  // API compatibility: Adjust integer opcodes to floating-point opcodes.
+  if (Ty->isFPOrFPVector()) {
+    if (iType == BinaryOperator::Add) iType = BinaryOperator::FAdd;
+    else if (iType == BinaryOperator::Sub) iType = BinaryOperator::FSub;
+    else if (iType == BinaryOperator::Mul) iType = BinaryOperator::FMul;
+  }
+  return iType;
+}
+
 BinaryOperator::BinaryOperator(BinaryOps iType, Value *S1, Value *S2,
                                const Type *Ty, const std::string &Name,
                                Instruction *InsertBefore)
-  : Instruction(Ty, iType,
+  : Instruction(Ty, AdjustIType(iType, Ty),
                 OperandTraits::op_begin(this),
                 OperandTraits::operands(this),
                 InsertBefore) {
   Op<0>() = S1;
   Op<1>() = S2;
-  init(iType);
+  init(AdjustIType(iType, Ty));
   setName(Name);
 }
 
 BinaryOperator::BinaryOperator(BinaryOps iType, Value *S1, Value *S2, 
                                const Type *Ty, const std::string &Name,
                                BasicBlock *InsertAtEnd)
-  : Instruction(Ty, iType,
+  : Instruction(Ty, AdjustIType(iType, Ty),
                 OperandTraits::op_begin(this),
                 OperandTraits::operands(this),
                 InsertAtEnd) {
   Op<0>() = S1;
   Op<1>() = S2;
-  init(iType);
+  init(AdjustIType(iType, Ty));
   setName(Name);
 }
 
@@ -1537,12 +1551,19 @@
 #ifndef NDEBUG
   switch (iType) {
   case Add: case Sub:
-  case Mul: 
+  case Mul:
+    assert(getType() == LHS->getType() &&
+           "Arithmetic operation should return same type as operands!");
+    assert(getType()->isIntOrIntVector() &&
+           "Tried to create an integer operation on a non-integer type!");
+    break;
+  case FAdd: case FSub:
+  case FMul:
     assert(getType() == LHS->getType() &&
            "Arithmetic operation should return same type as operands!");
-    assert((getType()->isInteger() || getType()->isFloatingPoint() ||
-            isa(getType())) &&
-          "Tried to create an arithmetic operation on a non-arithmetic type!");
+    assert(getType()->isFPOrFPVector() &&
+           "Tried to create a floating-point operation on a "
+           "non-floating-point type!");
     break;
   case UDiv: 
   case SDiv: 
@@ -1631,6 +1652,22 @@
                             Op->getType(), Name, InsertAtEnd);
 }
 
+BinaryOperator *BinaryOperator::CreateFNeg(Value *Op, const std::string &Name,
+                                           Instruction *InsertBefore) {
+  Value *zero = ConstantExpr::getZeroValueForNegationExpr(Op->getType());
+  return new BinaryOperator(Instruction::FSub,
+                            zero, Op,
+                            Op->getType(), Name, InsertBefore);
+}
+
+BinaryOperator *BinaryOperator::CreateFNeg(Value *Op, const std::string &Name,
+                                           BasicBlock *InsertAtEnd) {
+  Value *zero = ConstantExpr::getZeroValueForNegationExpr(Op->getType());
+  return new BinaryOperator(Instruction::FSub,
+                            zero, Op,
+                            Op->getType(), Name, InsertAtEnd);
+}
+
 BinaryOperator *BinaryOperator::CreateNot(Value *Op, const std::string &Name,
                                           Instruction *InsertBefore) {
   Constant *C;
@@ -1679,6 +1716,14 @@
   return false;
 }
 
+bool BinaryOperator::isFNeg(const Value *V) {
+  if (const BinaryOperator *Bop = dyn_cast(V))
+    if (Bop->getOpcode() == Instruction::FSub)
+      return Bop->getOperand(0) ==
+             ConstantExpr::getZeroValueForNegationExpr(Bop->getType());
+  return false;
+}
+
 bool BinaryOperator::isNot(const Value *V) {
   if (const BinaryOperator *Bop = dyn_cast(V))
     return (Bop->getOpcode() == Instruction::Xor &&
@@ -1696,6 +1741,15 @@
   return getNegArgument(const_cast(BinOp));
 }
 
+Value *BinaryOperator::getFNegArgument(Value *BinOp) {
+  assert(isFNeg(BinOp) && "getFNegArgument from non-'fneg' instruction!");
+  return cast(BinOp)->getOperand(1);
+}
+
+const Value *BinaryOperator::getFNegArgument(const Value *BinOp) {
+  return getFNegArgument(const_cast(BinOp));
+}
+
 Value *BinaryOperator::getNotArgument(Value *BinOp) {
   assert(isNot(BinOp) && "getNotArgument on non-'not' instruction!");
   BinaryOperator *BO = cast(BinOp);

Modified: llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-0.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-0.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-0.ll Thu Jun  4 17:49:04 2009
@@ -18,7 +18,7 @@
 	%2 = sext i9 %1 to i64		;  [#uses=1]
 	%3 = getelementptr double* %x, i64 %2		;  [#uses=1]
 	%4 = load double* %3, align 8		;  [#uses=1]
-	%5 = mul double %4, 3.900000e+00		;  [#uses=1]
+	%5 = fmul double %4, 3.900000e+00		;  [#uses=1]
 	%6 = sext i8 %0 to i64		;  [#uses=1]
 	%7 = getelementptr double* %x, i64 %6		;  [#uses=1]
 	store double %5, double* %7, align 8

Modified: llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-1.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-1.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/sext-iv-1.ll Thu Jun  4 17:49:04 2009
@@ -18,7 +18,7 @@
 	%2 = sext i9 %1 to i64		;  [#uses=1]
 	%3 = getelementptr double* %x, i64 %2		;  [#uses=1]
 	%4 = load double* %3, align 8		;  [#uses=1]
-	%5 = mul double %4, 3.900000e+00		;  [#uses=1]
+	%5 = fmul double %4, 3.900000e+00		;  [#uses=1]
 	%6 = sext i7 %0 to i64		;  [#uses=1]
 	%7 = getelementptr double* %x, i64 %6		;  [#uses=1]
 	store double %5, double* %7, align 8
@@ -41,7 +41,7 @@
 	%2 = sext i9 %1 to i64		;  [#uses=1]
 	%3 = getelementptr double* %x, i64 %2		;  [#uses=1]
 	%4 = load double* %3, align 8		;  [#uses=1]
-	%5 = mul double %4, 3.900000e+00		;  [#uses=1]
+	%5 = fmul double %4, 3.900000e+00		;  [#uses=1]
 	%6 = sext i8 %0 to i64		;  [#uses=1]
 	%7 = getelementptr double* %x, i64 %6		;  [#uses=1]
 	store double %5, double* %7, align 8
@@ -64,7 +64,7 @@
 	%2 = sext i9 %1 to i64		;  [#uses=1]
 	%3 = getelementptr double* %x, i64 %2		;  [#uses=1]
 	%4 = load double* %3, align 8		;  [#uses=1]
-	%5 = mul double %4, 3.900000e+00		;  [#uses=1]
+	%5 = fmul double %4, 3.900000e+00		;  [#uses=1]
 	%6 = sext i8 %0 to i64		;  [#uses=1]
 	%7 = getelementptr double* %x, i64 %6		;  [#uses=1]
 	store double %5, double* %7, align 8
@@ -87,7 +87,7 @@
 	%2 = sext i9 %1 to i64		;  [#uses=1]
 	%3 = getelementptr double* %x, i64 %2		;  [#uses=1]
 	%4 = load double* %3, align 8		;  [#uses=1]
-	%5 = mul double %4, 3.900000e+00		;  [#uses=1]
+	%5 = fmul double %4, 3.900000e+00		;  [#uses=1]
 	%6 = sext i8 %0 to i64		;  [#uses=1]
 	%7 = getelementptr double* %x, i64 %6		;  [#uses=1]
 	store double %5, double* %7, align 8

Modified: llvm/trunk/test/Analysis/ScalarEvolution/trip-count4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/trip-count4.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/trip-count4.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/trip-count4.ll Thu Jun  4 17:49:04 2009
@@ -13,7 +13,7 @@
 	%indvar.i8 = ashr i64 %s0, 8		;  [#uses=1]
 	%t0 = getelementptr double* %d, i64 %indvar.i8		;  [#uses=2]
 	%t1 = load double* %t0		;  [#uses=1]
-	%t2 = mul double %t1, 1.000000e-01		;  [#uses=1]
+	%t2 = fmul double %t1, 1.000000e-01		;  [#uses=1]
 	store double %t2, double* %t0
 	%indvar.next = sub i64 %indvar, 1		;  [#uses=2]
 	%exitcond = icmp eq i64 %indvar.next, 10		;  [#uses=1]

Modified: llvm/trunk/test/Assembler/2002-04-07-HexFloatConstants.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2002-04-07-HexFloatConstants.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/Assembler/2002-04-07-HexFloatConstants.ll (original)
+++ llvm/trunk/test/Assembler/2002-04-07-HexFloatConstants.ll Thu Jun  4 17:49:04 2009
@@ -11,6 +11,6 @@
 ; RUN: diff %t.1 %t.2
 
 define double @test() {
-        %tmp = mul double 7.200000e+101, 0x427F4000             ;  [#uses=1]
+        %tmp = fmul double 7.200000e+101, 0x427F4000             ;  [#uses=1]
         ret double %tmp
 }

Modified: llvm/trunk/test/Assembler/2002-04-07-InfConstant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/2002-04-07-InfConstant.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/Assembler/2002-04-07-InfConstant.ll (original)
+++ llvm/trunk/test/Assembler/2002-04-07-InfConstant.ll Thu Jun  4 17:49:04 2009
@@ -3,7 +3,7 @@
 ; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | grep 0x7FF0000000000000
 
 define float @test() {
-        %tmp = mul float 0x7FF0000000000000, 1.000000e+01               ;  [#uses=1]
+        %tmp = fmul float 0x7FF0000000000000, 1.000000e+01               ;  [#uses=1]
         ret float %tmp
 }
 

Modified: llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll Thu Jun  4 17:49:04 2009
@@ -35,8 +35,8 @@
 	%tmp612 = load i32* null		;  [#uses=1]
 	%tmp629 = load i32* null		;  [#uses=1]
 	%tmp629a = sitofp i32 %tmp629 to double		;  [#uses=1]
-	%tmp631 = mul double %tmp629a, 0.000000e+00		;  [#uses=1]
-	%tmp632 = add double 0.000000e+00, %tmp631		;  [#uses=1]
+	%tmp631 = fmul double %tmp629a, 0.000000e+00		;  [#uses=1]
+	%tmp632 = fadd double 0.000000e+00, %tmp631		;  [#uses=1]
 	%tmp642 = call fastcc i32 @sign( i32 %tmp576, i32 %tmp561 )		;  [#uses=1]
 	%tmp650 = mul i32 %tmp606, %tmp642		;  [#uses=1]
 	%tmp656 = mul i32 %tmp650, %tmp612		;  [#uses=1]
@@ -46,8 +46,8 @@
 	%tmp666 = sub i32 %tmp660, %tmp496		;  [#uses=1]
 	%tmp667 = sitofp i32 %tmp666 to double		;  [#uses=2]
 	call void @levrun_linfo_inter( i32 %tmp576, i32 0, i32* null, i32* null )
-	%tmp671 = mul double %tmp667, %tmp667		;  [#uses=1]
-	%tmp675 = add double %tmp671, 0.000000e+00		;  [#uses=1]
+	%tmp671 = fmul double %tmp667, %tmp667		;  [#uses=1]
+	%tmp675 = fadd double %tmp671, 0.000000e+00		;  [#uses=1]
 	%tmp678 = fcmp oeq double %tmp632, %tmp675		;  [#uses=1]
 	br i1 %tmp678, label %cond_true679, label %cond_false693
 

Modified: llvm/trunk/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-02-27-SpillerBug.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-02-27-SpillerBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-02-27-SpillerBug.ll Thu Jun  4 17:49:04 2009
@@ -11,7 +11,7 @@
 	br label %bb52
 
 bb32:		; preds = %bb52
-	%0 = add double 0.000000e+00, 0.000000e+00		;  [#uses=1]
+	%0 = fadd double 0.000000e+00, 0.000000e+00		;  [#uses=1]
 	%1 = add i32 %j.1, 1		;  [#uses=1]
 	br label %bb52
 
@@ -29,14 +29,14 @@
 
 bb55:		; preds = %bb53
 	%4 = load double* @a, align 4		;  [#uses=10]
-	%5 = add double %4, 0.000000e+00		;  [#uses=16]
+	%5 = fadd double %4, 0.000000e+00		;  [#uses=16]
 	%6 = fcmp ogt double %k.4, 0.000000e+00		;  [#uses=1]
-	%.pn404 = mul double %4, %4		;  [#uses=4]
-	%.pn402 = mul double %5, %5		;  [#uses=5]
+	%.pn404 = fmul double %4, %4		;  [#uses=4]
+	%.pn402 = fmul double %5, %5		;  [#uses=5]
 	%.pn165.in = load double* @N		;  [#uses=5]
-	%.pn198 = mul double 0.000000e+00, %5		;  [#uses=1]
-	%.pn185 = sub double -0.000000e+00, 0.000000e+00		;  [#uses=1]
-	%.pn147 = sub double -0.000000e+00, 0.000000e+00		;  [#uses=1]
+	%.pn198 = fmul double 0.000000e+00, %5		;  [#uses=1]
+	%.pn185 = fsub double -0.000000e+00, 0.000000e+00		;  [#uses=1]
+	%.pn147 = fsub double -0.000000e+00, 0.000000e+00		;  [#uses=1]
 	%.pn141 = fdiv double 0.000000e+00, %4		;  [#uses=1]
 	%.pn142 = fdiv double 0.000000e+00, %5		;  [#uses=1]
 	%.pn136 = fdiv double 0.000000e+00, 0.000000e+00		;  [#uses=1]
@@ -47,178 +47,178 @@
 	%.pn117 = fdiv double 0.000000e+00, %4		;  [#uses=1]
 	%.pn118 = fdiv double %.pn185, %5		;  [#uses=1]
 	%.pn88 = fdiv double %.pn147, %5		;  [#uses=1]
-	%.pn81 = sub double %.pn141, %.pn142		;  [#uses=1]
-	%.pn77 = sub double 0.000000e+00, %.pn136		;  [#uses=1]
-	%.pn75 = sub double 0.000000e+00, %.pn132		;  [#uses=1]
-	%.pn69 = sub double %.pn123, %.pn124		;  [#uses=1]
-	%.pn67 = sub double 0.000000e+00, %.pn120		;  [#uses=1]
-	%.pn56 = sub double %.pn117, %.pn118		;  [#uses=1]
-	%.pn42 = sub double 0.000000e+00, %.pn88		;  [#uses=1]
-	%.pn60 = mul double %.pn81, 0.000000e+00		;  [#uses=1]
-	%.pn57 = add double %.pn77, 0.000000e+00		;  [#uses=1]
-	%.pn58 = mul double %.pn75, %.pn165.in		;  [#uses=1]
-	%.pn32 = add double %.pn69, 0.000000e+00		;  [#uses=1]
-	%.pn33 = mul double %.pn67, %.pn165.in		;  [#uses=1]
-	%.pn17 = sub double 0.000000e+00, %.pn60		;  [#uses=1]
-	%.pn9 = add double %.pn57, %.pn58		;  [#uses=1]
-	%.pn30 = mul double 0.000000e+00, %.pn56		;  [#uses=1]
-	%.pn24 = mul double 0.000000e+00, %.pn42		;  [#uses=1]
-	%.pn1 = add double %.pn32, %.pn33		;  [#uses=1]
-	%.pn28 = sub double %.pn30, 0.000000e+00		;  [#uses=1]
-	%.pn26 = add double %.pn28, 0.000000e+00		;  [#uses=1]
-	%.pn22 = sub double %.pn26, 0.000000e+00		;  [#uses=1]
-	%.pn20 = sub double %.pn24, 0.000000e+00		;  [#uses=1]
-	%.pn18 = add double %.pn22, 0.000000e+00		;  [#uses=1]
-	%.pn16 = add double %.pn20, 0.000000e+00		;  [#uses=1]
-	%.pn14 = sub double %.pn18, 0.000000e+00		;  [#uses=1]
-	%.pn12 = sub double %.pn16, %.pn17		;  [#uses=1]
-	%.pn10 = add double %.pn14, 0.000000e+00		;  [#uses=1]
-	%.pn8 = add double %.pn12, 0.000000e+00		;  [#uses=1]
-	%.pn6 = sub double %.pn10, 0.000000e+00		;  [#uses=1]
-	%.pn4 = sub double %.pn8, %.pn9		;  [#uses=1]
-	%.pn2 = add double %.pn6, 0.000000e+00		;  [#uses=1]
-	%.pn = add double %.pn4, 0.000000e+00		;  [#uses=1]
-	%N1.0 = sub double %.pn2, 0.000000e+00		;  [#uses=2]
-	%D1.0 = sub double %.pn, %.pn1		;  [#uses=2]
+	%.pn81 = fsub double %.pn141, %.pn142		;  [#uses=1]
+	%.pn77 = fsub double 0.000000e+00, %.pn136		;  [#uses=1]
+	%.pn75 = fsub double 0.000000e+00, %.pn132		;  [#uses=1]
+	%.pn69 = fsub double %.pn123, %.pn124		;  [#uses=1]
+	%.pn67 = fsub double 0.000000e+00, %.pn120		;  [#uses=1]
+	%.pn56 = fsub double %.pn117, %.pn118		;  [#uses=1]
+	%.pn42 = fsub double 0.000000e+00, %.pn88		;  [#uses=1]
+	%.pn60 = fmul double %.pn81, 0.000000e+00		;  [#uses=1]
+	%.pn57 = fadd double %.pn77, 0.000000e+00		;  [#uses=1]
+	%.pn58 = fmul double %.pn75, %.pn165.in		;  [#uses=1]
+	%.pn32 = fadd double %.pn69, 0.000000e+00		;  [#uses=1]
+	%.pn33 = fmul double %.pn67, %.pn165.in		;  [#uses=1]
+	%.pn17 = fsub double 0.000000e+00, %.pn60		;  [#uses=1]
+	%.pn9 = fadd double %.pn57, %.pn58		;  [#uses=1]
+	%.pn30 = fmul double 0.000000e+00, %.pn56		;  [#uses=1]
+	%.pn24 = fmul double 0.000000e+00, %.pn42		;  [#uses=1]
+	%.pn1 = fadd double %.pn32, %.pn33		;  [#uses=1]
+	%.pn28 = fsub double %.pn30, 0.000000e+00		;  [#uses=1]
+	%.pn26 = fadd double %.pn28, 0.000000e+00		;  [#uses=1]
+	%.pn22 = fsub double %.pn26, 0.000000e+00		;  [#uses=1]
+	%.pn20 = fsub double %.pn24, 0.000000e+00		;  [#uses=1]
+	%.pn18 = fadd double %.pn22, 0.000000e+00		;  [#uses=1]
+	%.pn16 = fadd double %.pn20, 0.000000e+00		;  [#uses=1]
+	%.pn14 = fsub double %.pn18, 0.000000e+00		;  [#uses=1]
+	%.pn12 = fsub double %.pn16, %.pn17		;  [#uses=1]
+	%.pn10 = fadd double %.pn14, 0.000000e+00		;  [#uses=1]
+	%.pn8 = fadd double %.pn12, 0.000000e+00		;  [#uses=1]
+	%.pn6 = fsub double %.pn10, 0.000000e+00		;  [#uses=1]
+	%.pn4 = fsub double %.pn8, %.pn9		;  [#uses=1]
+	%.pn2 = fadd double %.pn6, 0.000000e+00		;  [#uses=1]
+	%.pn = fadd double %.pn4, 0.000000e+00		;  [#uses=1]
+	%N1.0 = fsub double %.pn2, 0.000000e+00		;  [#uses=2]
+	%D1.0 = fsub double %.pn, %.pn1		;  [#uses=2]
 	br i1 %6, label %bb62, label %bb64
 
 bb62:		; preds = %bb55
-	%7 = mul double 0.000000e+00, %4		;  [#uses=1]
-	%8 = sub double -0.000000e+00, %7		;  [#uses=3]
-	%9 = mul double 0.000000e+00, %5		;  [#uses=1]
-	%10 = sub double -0.000000e+00, %9		;  [#uses=3]
-	%11 = mul double %.pn404, %4		;  [#uses=5]
-	%12 = mul double %.pn402, %5		;  [#uses=5]
-	%13 = mul double 0.000000e+00, -2.000000e+00		;  [#uses=1]
+	%7 = fmul double 0.000000e+00, %4		;  [#uses=1]
+	%8 = fsub double -0.000000e+00, %7		;  [#uses=3]
+	%9 = fmul double 0.000000e+00, %5		;  [#uses=1]
+	%10 = fsub double -0.000000e+00, %9		;  [#uses=3]
+	%11 = fmul double %.pn404, %4		;  [#uses=5]
+	%12 = fmul double %.pn402, %5		;  [#uses=5]
+	%13 = fmul double 0.000000e+00, -2.000000e+00		;  [#uses=1]
 	%14 = fdiv double 0.000000e+00, %.pn402		;  [#uses=1]
-	%15 = sub double 0.000000e+00, %14		;  [#uses=1]
-	%16 = mul double 0.000000e+00, %15		;  [#uses=1]
-	%17 = add double %13, %16		;  [#uses=1]
-	%18 = mul double %.pn165.in, -2.000000e+00		;  [#uses=5]
-	%19 = mul double %18, 0.000000e+00		;  [#uses=1]
-	%20 = add double %17, %19		;  [#uses=1]
-	%21 = mul double 0.000000e+00, %20		;  [#uses=1]
-	%22 = add double 0.000000e+00, %21		;  [#uses=1]
+	%15 = fsub double 0.000000e+00, %14		;  [#uses=1]
+	%16 = fmul double 0.000000e+00, %15		;  [#uses=1]
+	%17 = fadd double %13, %16		;  [#uses=1]
+	%18 = fmul double %.pn165.in, -2.000000e+00		;  [#uses=5]
+	%19 = fmul double %18, 0.000000e+00		;  [#uses=1]
+	%20 = fadd double %17, %19		;  [#uses=1]
+	%21 = fmul double 0.000000e+00, %20		;  [#uses=1]
+	%22 = fadd double 0.000000e+00, %21		;  [#uses=1]
 	%23 = fdiv double 0.000000e+00, %12		;  [#uses=1]
-	%24 = sub double 0.000000e+00, %23		;  [#uses=0]
-	%25 = mul double %18, 0.000000e+00		;  [#uses=1]
-	%26 = add double 0.000000e+00, %25		;  [#uses=1]
-	%27 = mul double 0.000000e+00, %26		;  [#uses=1]
-	%28 = sub double %22, %27		;  [#uses=1]
-	%29 = mul double %11, %4		;  [#uses=1]
-	%30 = mul double %12, %5		;  [#uses=3]
-	%31 = mul double %.pn165.in, -4.000000e+00		;  [#uses=1]
-	%32 = mul double %.pn165.in, 0x3FF5555555555555		;  [#uses=1]
-	%33 = mul double %32, 0.000000e+00		;  [#uses=2]
-	%34 = add double %28, 0.000000e+00		;  [#uses=1]
-	%35 = sub double -0.000000e+00, 0.000000e+00		;  [#uses=1]
+	%24 = fsub double 0.000000e+00, %23		;  [#uses=0]
+	%25 = fmul double %18, 0.000000e+00		;  [#uses=1]
+	%26 = fadd double 0.000000e+00, %25		;  [#uses=1]
+	%27 = fmul double 0.000000e+00, %26		;  [#uses=1]
+	%28 = fsub double %22, %27		;  [#uses=1]
+	%29 = fmul double %11, %4		;  [#uses=1]
+	%30 = fmul double %12, %5		;  [#uses=3]
+	%31 = fmul double %.pn165.in, -4.000000e+00		;  [#uses=1]
+	%32 = fmul double %.pn165.in, 0x3FF5555555555555		;  [#uses=1]
+	%33 = fmul double %32, 0.000000e+00		;  [#uses=2]
+	%34 = fadd double %28, 0.000000e+00		;  [#uses=1]
+	%35 = fsub double -0.000000e+00, 0.000000e+00		;  [#uses=1]
 	%36 = fdiv double %35, %11		;  [#uses=1]
 	%37 = fdiv double 0.000000e+00, %12		;  [#uses=1]
-	%38 = sub double %36, %37		;  [#uses=1]
-	%39 = mul double 0.000000e+00, %38		;  [#uses=1]
-	%40 = add double 0.000000e+00, %39		;  [#uses=1]
-	%41 = add double %40, 0.000000e+00		;  [#uses=1]
-	%42 = add double %41, 0.000000e+00		;  [#uses=1]
-	%43 = mul double %42, 0.000000e+00		;  [#uses=1]
-	%44 = sub double %34, %43		;  [#uses=1]
+	%38 = fsub double %36, %37		;  [#uses=1]
+	%39 = fmul double 0.000000e+00, %38		;  [#uses=1]
+	%40 = fadd double 0.000000e+00, %39		;  [#uses=1]
+	%41 = fadd double %40, 0.000000e+00		;  [#uses=1]
+	%42 = fadd double %41, 0.000000e+00		;  [#uses=1]
+	%43 = fmul double %42, 0.000000e+00		;  [#uses=1]
+	%44 = fsub double %34, %43		;  [#uses=1]
 	%45 = tail call double @llvm.exp.f64(double %8) nounwind		;  [#uses=1]
-	%46 = sub double -0.000000e+00, %45		;  [#uses=2]
+	%46 = fsub double -0.000000e+00, %45		;  [#uses=2]
 	%47 = fdiv double %46, 0.000000e+00		;  [#uses=1]
-	%48 = mul double %30, %5		;  [#uses=1]
+	%48 = fmul double %30, %5		;  [#uses=1]
 	%49 = fdiv double 0.000000e+00, %48		;  [#uses=1]
-	%50 = sub double %47, %49		;  [#uses=1]
-	%51 = mul double %50, -4.000000e+00		;  [#uses=1]
-	%52 = add double %51, 0.000000e+00		;  [#uses=1]
+	%50 = fsub double %47, %49		;  [#uses=1]
+	%51 = fmul double %50, -4.000000e+00		;  [#uses=1]
+	%52 = fadd double %51, 0.000000e+00		;  [#uses=1]
 	%53 = fdiv double %46, %11		;  [#uses=1]
-	%54 = sub double %53, 0.000000e+00		;  [#uses=1]
-	%55 = mul double %31, %54		;  [#uses=1]
-	%56 = add double %52, %55		;  [#uses=1]
-	%57 = add double %56, 0.000000e+00		;  [#uses=1]
-	%58 = add double %44, %57		;  [#uses=1]
-	%59 = sub double %58, 0.000000e+00		;  [#uses=1]
+	%54 = fsub double %53, 0.000000e+00		;  [#uses=1]
+	%55 = fmul double %31, %54		;  [#uses=1]
+	%56 = fadd double %52, %55		;  [#uses=1]
+	%57 = fadd double %56, 0.000000e+00		;  [#uses=1]
+	%58 = fadd double %44, %57		;  [#uses=1]
+	%59 = fsub double %58, 0.000000e+00		;  [#uses=1]
 	%60 = tail call double @llvm.exp.f64(double 0.000000e+00) nounwind		;  [#uses=1]
-	%61 = sub double -0.000000e+00, %60		;  [#uses=1]
+	%61 = fsub double -0.000000e+00, %60		;  [#uses=1]
 	%62 = fdiv double 0.000000e+00, -6.000000e+00		;  [#uses=1]
 	%63 = fdiv double %61, %5		;  [#uses=1]
-	%64 = sub double 0.000000e+00, %63		;  [#uses=1]
-	%65 = mul double %62, %64		;  [#uses=1]
-	%66 = sub double 0.000000e+00, %65		;  [#uses=1]
-	%67 = sub double -0.000000e+00, 0.000000e+00		;  [#uses=2]
+	%64 = fsub double 0.000000e+00, %63		;  [#uses=1]
+	%65 = fmul double %62, %64		;  [#uses=1]
+	%66 = fsub double 0.000000e+00, %65		;  [#uses=1]
+	%67 = fsub double -0.000000e+00, 0.000000e+00		;  [#uses=2]
 	%68 = tail call double @llvm.exp.f64(double %10) nounwind		;  [#uses=1]
-	%69 = sub double -0.000000e+00, %68		;  [#uses=2]
+	%69 = fsub double -0.000000e+00, %68		;  [#uses=2]
 	%70 = fdiv double %67, %.pn404		;  [#uses=1]
 	%71 = fdiv double %69, %.pn402		;  [#uses=1]
-	%72 = sub double %70, %71		;  [#uses=1]
-	%73 = mul double %72, -5.000000e-01		;  [#uses=1]
+	%72 = fsub double %70, %71		;  [#uses=1]
+	%73 = fmul double %72, -5.000000e-01		;  [#uses=1]
 	%74 = fdiv double %67, %4		;  [#uses=1]
 	%75 = fdiv double %69, %5		;  [#uses=1]
-	%76 = sub double %74, %75		;  [#uses=1]
-	%77 = mul double %76, 0.000000e+00		;  [#uses=1]
-	%78 = add double %73, %77		;  [#uses=1]
-	%79 = mul double 0.000000e+00, %78		;  [#uses=1]
-	%80 = add double %66, %79		;  [#uses=1]
+	%76 = fsub double %74, %75		;  [#uses=1]
+	%77 = fmul double %76, 0.000000e+00		;  [#uses=1]
+	%78 = fadd double %73, %77		;  [#uses=1]
+	%79 = fmul double 0.000000e+00, %78		;  [#uses=1]
+	%80 = fadd double %66, %79		;  [#uses=1]
 	%81 = fdiv double 0.000000e+00, %.pn404		;  [#uses=1]
 	%82 = fdiv double 0.000000e+00, %.pn402		;  [#uses=1]
-	%83 = sub double %81, %82		;  [#uses=1]
-	%84 = mul double %83, -5.000000e-01		;  [#uses=1]
+	%83 = fsub double %81, %82		;  [#uses=1]
+	%84 = fmul double %83, -5.000000e-01		;  [#uses=1]
 	%85 = fdiv double 0.000000e+00, %4		;  [#uses=1]
 	%86 = fdiv double 0.000000e+00, %5		;  [#uses=1]
-	%87 = sub double %85, %86		;  [#uses=1]
-	%88 = mul double %87, 0.000000e+00		;  [#uses=1]
-	%89 = add double %84, %88		;  [#uses=1]
-	%90 = mul double 0.000000e+00, %89		;  [#uses=1]
-	%91 = sub double %80, %90		;  [#uses=1]
+	%87 = fsub double %85, %86		;  [#uses=1]
+	%88 = fmul double %87, 0.000000e+00		;  [#uses=1]
+	%89 = fadd double %84, %88		;  [#uses=1]
+	%90 = fmul double 0.000000e+00, %89		;  [#uses=1]
+	%91 = fsub double %80, %90		;  [#uses=1]
 	%92 = tail call double @llvm.exp.f64(double %8) nounwind		;  [#uses=1]
-	%93 = sub double -0.000000e+00, %92		;  [#uses=1]
+	%93 = fsub double -0.000000e+00, %92		;  [#uses=1]
 	%94 = tail call double @llvm.exp.f64(double %10) nounwind		;  [#uses=1]
-	%95 = sub double -0.000000e+00, %94		;  [#uses=3]
+	%95 = fsub double -0.000000e+00, %94		;  [#uses=3]
 	%96 = fdiv double %95, %.pn402		;  [#uses=1]
-	%97 = sub double 0.000000e+00, %96		;  [#uses=1]
-	%98 = mul double 0.000000e+00, %97		;  [#uses=1]
+	%97 = fsub double 0.000000e+00, %96		;  [#uses=1]
+	%98 = fmul double 0.000000e+00, %97		;  [#uses=1]
 	%99 = fdiv double %93, %11		;  [#uses=1]
 	%100 = fdiv double %95, %12		;  [#uses=1]
-	%101 = sub double %99, %100		;  [#uses=1]
-	%102 = sub double %98, %101		;  [#uses=1]
+	%101 = fsub double %99, %100		;  [#uses=1]
+	%102 = fsub double %98, %101		;  [#uses=1]
 	%103 = fdiv double %95, %5		;  [#uses=1]
-	%104 = sub double 0.000000e+00, %103		;  [#uses=1]
-	%105 = mul double %18, %104		;  [#uses=1]
-	%106 = add double %102, %105		;  [#uses=1]
-	%107 = mul double %106, %k.4		;  [#uses=1]
-	%108 = add double %91, %107		;  [#uses=1]
-	%109 = sub double %108, 0.000000e+00		;  [#uses=1]
+	%104 = fsub double 0.000000e+00, %103		;  [#uses=1]
+	%105 = fmul double %18, %104		;  [#uses=1]
+	%106 = fadd double %102, %105		;  [#uses=1]
+	%107 = fmul double %106, %k.4		;  [#uses=1]
+	%108 = fadd double %91, %107		;  [#uses=1]
+	%109 = fsub double %108, 0.000000e+00		;  [#uses=1]
 	%110 = tail call double @llvm.exp.f64(double %8) nounwind		;  [#uses=1]
-	%111 = sub double -0.000000e+00, %110		;  [#uses=2]
+	%111 = fsub double -0.000000e+00, %110		;  [#uses=2]
 	%112 = tail call double @llvm.exp.f64(double %10) nounwind		;  [#uses=1]
-	%113 = sub double -0.000000e+00, %112		;  [#uses=2]
+	%113 = fsub double -0.000000e+00, %112		;  [#uses=2]
 	%114 = fdiv double %111, %11		;  [#uses=1]
 	%115 = fdiv double %113, %12		;  [#uses=1]
-	%116 = sub double %114, %115		;  [#uses=1]
-	%117 = mul double 0.000000e+00, %116		;  [#uses=1]
+	%116 = fsub double %114, %115		;  [#uses=1]
+	%117 = fmul double 0.000000e+00, %116		;  [#uses=1]
 	%118 = fdiv double %111, %29		;  [#uses=1]
 	%119 = fdiv double %113, %30		;  [#uses=1]
-	%120 = sub double %118, %119		;  [#uses=1]
-	%121 = sub double %117, %120		;  [#uses=1]
-	%122 = mul double %18, 0.000000e+00		;  [#uses=1]
-	%123 = add double %121, %122		;  [#uses=1]
-	%124 = mul double %33, 0.000000e+00		;  [#uses=1]
-	%125 = add double %123, %124		;  [#uses=1]
-	%126 = add double %109, %125		;  [#uses=1]
+	%120 = fsub double %118, %119		;  [#uses=1]
+	%121 = fsub double %117, %120		;  [#uses=1]
+	%122 = fmul double %18, 0.000000e+00		;  [#uses=1]
+	%123 = fadd double %121, %122		;  [#uses=1]
+	%124 = fmul double %33, 0.000000e+00		;  [#uses=1]
+	%125 = fadd double %123, %124		;  [#uses=1]
+	%126 = fadd double %109, %125		;  [#uses=1]
 	%127 = tail call double @llvm.exp.f64(double 0.000000e+00) nounwind		;  [#uses=1]
-	%128 = sub double -0.000000e+00, %127		;  [#uses=2]
+	%128 = fsub double -0.000000e+00, %127		;  [#uses=2]
 	%129 = fdiv double %128, %30		;  [#uses=1]
-	%130 = sub double 0.000000e+00, %129		;  [#uses=1]
-	%131 = sub double 0.000000e+00, %130		;  [#uses=1]
+	%130 = fsub double 0.000000e+00, %129		;  [#uses=1]
+	%131 = fsub double 0.000000e+00, %130		;  [#uses=1]
 	%132 = fdiv double 0.000000e+00, %.pn404		;  [#uses=1]
-	%133 = sub double %132, 0.000000e+00		;  [#uses=1]
-	%134 = mul double %18, %133		;  [#uses=1]
-	%135 = add double %131, %134		;  [#uses=1]
+	%133 = fsub double %132, 0.000000e+00		;  [#uses=1]
+	%134 = fmul double %18, %133		;  [#uses=1]
+	%135 = fadd double %131, %134		;  [#uses=1]
 	%136 = fdiv double %128, %5		;  [#uses=1]
-	%137 = sub double 0.000000e+00, %136		;  [#uses=1]
-	%138 = mul double %33, %137		;  [#uses=1]
-	%139 = add double %135, %138		;  [#uses=1]
-	%140 = sub double %126, %139		;  [#uses=1]
-	%141 = add double %N1.0, %59		;  [#uses=1]
-	%142 = add double %D1.0, %140		;  [#uses=1]
+	%137 = fsub double 0.000000e+00, %136		;  [#uses=1]
+	%138 = fmul double %33, %137		;  [#uses=1]
+	%139 = fadd double %135, %138		;  [#uses=1]
+	%140 = fsub double %126, %139		;  [#uses=1]
+	%141 = fadd double %N1.0, %59		;  [#uses=1]
+	%142 = fadd double %D1.0, %140		;  [#uses=1]
 	br label %bb64
 
 bb64:		; preds = %bb62, %bb55

Modified: llvm/trunk/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-03-07-SpillerBug.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-03-07-SpillerBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-03-07-SpillerBug.ll Thu Jun  4 17:49:04 2009
@@ -26,39 +26,39 @@
 
 bb3:		; preds = %entry
 	%2 = fdiv double 1.000000e+00, 0.000000e+00		;  [#uses=1]
-	%3 = mul double 0.000000e+00, %2		;  [#uses=2]
+	%3 = fmul double 0.000000e+00, %2		;  [#uses=2]
 	%4 = call double @llvm.sqrt.f64(double 0.000000e+00) nounwind		;  [#uses=1]
 	%5 = fdiv double 1.000000e+00, %4		;  [#uses=2]
-	%6 = mul double %3, %5		;  [#uses=2]
-	%7 = mul double 0.000000e+00, %5		;  [#uses=2]
-	%8 = mul double %3, %7		;  [#uses=1]
-	%9 = sub double %8, 0.000000e+00		;  [#uses=1]
-	%10 = mul double 0.000000e+00, %6		;  [#uses=1]
-	%11 = sub double 0.000000e+00, %10		;  [#uses=1]
-	%12 = sub double -0.000000e+00, %11		;  [#uses=1]
-	%13 = mul double %0, %0		;  [#uses=2]
-	%14 = sub double %13, 0.000000e+00		;  [#uses=1]
+	%6 = fmul double %3, %5		;  [#uses=2]
+	%7 = fmul double 0.000000e+00, %5		;  [#uses=2]
+	%8 = fmul double %3, %7		;  [#uses=1]
+	%9 = fsub double %8, 0.000000e+00		;  [#uses=1]
+	%10 = fmul double 0.000000e+00, %6		;  [#uses=1]
+	%11 = fsub double 0.000000e+00, %10		;  [#uses=1]
+	%12 = fsub double -0.000000e+00, %11		;  [#uses=1]
+	%13 = fmul double %0, %0		;  [#uses=2]
+	%14 = fsub double %13, 0.000000e+00		;  [#uses=1]
 	%15 = call double @llvm.sqrt.f64(double %14)		;  [#uses=1]
-	%16 = mul double 0.000000e+00, %15		;  [#uses=1]
+	%16 = fmul double 0.000000e+00, %15		;  [#uses=1]
 	%17 = fdiv double %16, %0		;  [#uses=1]
-	%18 = add double 0.000000e+00, %17		;  [#uses=1]
+	%18 = fadd double 0.000000e+00, %17		;  [#uses=1]
 	%19 = call double @acos(double %18) nounwind readonly		;  [#uses=1]
 	%20 = load double* null, align 4		;  [#uses=1]
-	%21 = mul double %20, 0x401921FB54442D18		;  [#uses=1]
+	%21 = fmul double %20, 0x401921FB54442D18		;  [#uses=1]
 	%22 = call double @sin(double %19) nounwind readonly		;  [#uses=2]
-	%23 = mul double %22, 0.000000e+00		;  [#uses=2]
-	%24 = mul double %6, %23		;  [#uses=1]
-	%25 = mul double %7, %23		;  [#uses=1]
+	%23 = fmul double %22, 0.000000e+00		;  [#uses=2]
+	%24 = fmul double %6, %23		;  [#uses=1]
+	%25 = fmul double %7, %23		;  [#uses=1]
 	%26 = call double @sin(double %21) nounwind readonly		;  [#uses=1]
-	%27 = mul double %22, %26		;  [#uses=2]
-	%28 = mul double %9, %27		;  [#uses=1]
-	%29 = mul double %27, %12		;  [#uses=1]
-	%30 = add double %24, %28		;  [#uses=1]
-	%31 = add double 0.000000e+00, %29		;  [#uses=1]
-	%32 = add double %25, 0.000000e+00		;  [#uses=1]
-	%33 = add double %30, 0.000000e+00		;  [#uses=1]
-	%34 = add double %31, 0.000000e+00		;  [#uses=1]
-	%35 = add double %32, 0.000000e+00		;  [#uses=1]
+	%27 = fmul double %22, %26		;  [#uses=2]
+	%28 = fmul double %9, %27		;  [#uses=1]
+	%29 = fmul double %27, %12		;  [#uses=1]
+	%30 = fadd double %24, %28		;  [#uses=1]
+	%31 = fadd double 0.000000e+00, %29		;  [#uses=1]
+	%32 = fadd double %25, 0.000000e+00		;  [#uses=1]
+	%33 = fadd double %30, 0.000000e+00		;  [#uses=1]
+	%34 = fadd double %31, 0.000000e+00		;  [#uses=1]
+	%35 = fadd double %32, 0.000000e+00		;  [#uses=1]
 	%36 = bitcast %struct.ggPoint3* %x to i8*		;  [#uses=1]
 	call void @llvm.memcpy.i32(i8* null, i8* %36, i32 24, i32 4) nounwind
 	store double %33, double* null, align 8
@@ -68,9 +68,9 @@
 	unreachable
 
 _Z20ggRaySphereIntersectRK6ggRay3RK8ggSphereddRd.exit:		; preds = %bb3
-	%37 = sub double %13, 0.000000e+00		;  [#uses=0]
-	%38 = sub double -0.000000e+00, %34		;  [#uses=0]
-	%39 = sub double -0.000000e+00, %35		;  [#uses=0]
+	%37 = fsub double %13, 0.000000e+00		;  [#uses=0]
+	%38 = fsub double -0.000000e+00, %34		;  [#uses=0]
+	%39 = fsub double -0.000000e+00, %35		;  [#uses=0]
 	ret i32 1
 
 bb7:		; preds = %entry

Modified: llvm/trunk/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-04-08-FloatUndef.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-04-08-FloatUndef.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-04-08-FloatUndef.ll Thu Jun  4 17:49:04 2009
@@ -4,8 +4,8 @@
 entry:
 	%input2 = load <4 x float>* null, align 16		; <<4 x float>> [#uses=2]
 	%shuffle7 = shufflevector <4 x float> %input2, <4 x float> , <4 x i32> 		; <<4 x float>> [#uses=1]
-	%mul1 = mul <4 x float> %shuffle7, zeroinitializer		; <<4 x float>> [#uses=1]
-	%add2 = add <4 x float> %mul1, %input2		; <<4 x float>> [#uses=1]
+	%mul1 = fmul <4 x float> %shuffle7, zeroinitializer		; <<4 x float>> [#uses=1]
+	%add2 = fadd <4 x float> %mul1, %input2		; <<4 x float>> [#uses=1]
 	store <4 x float> %add2, <4 x float>* null, align 16
 	ret void
 }

Modified: llvm/trunk/test/CodeGen/ARM/cse-libcalls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/cse-libcalls.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/cse-libcalls.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/cse-libcalls.ll Thu Jun  4 17:49:04 2009
@@ -16,7 +16,7 @@
 	br i1 false, label %bb502.loopexit.i, label %bb28.i
 
 bb.nph53.i:		; preds = %bb502.loopexit.i
-	%tmp354.i = sub double -0.000000e+00, %tmp10.i4		;  [#uses=0]
+	%tmp354.i = fsub double -0.000000e+00, %tmp10.i4		;  [#uses=0]
 	br label %bb244.i
 
 bb244.i:		; preds = %bb244.i, %bb.nph53.i

Modified: llvm/trunk/test/CodeGen/ARM/fixunsdfdi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fixunsdfdi.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fixunsdfdi.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fixunsdfdi.ll Thu Jun  4 17:49:04 2009
@@ -13,7 +13,7 @@
 	%u.in.mask = and i64 %x14, -4294967296		;  [#uses=1]
 	%.ins = or i64 0, %u.in.mask		;  [#uses=1]
 	%0 = bitcast i64 %.ins to double		;  [#uses=1]
-	%1 = sub double %x, %0		;  [#uses=1]
+	%1 = fsub double %x, %0		;  [#uses=1]
 	%2 = fptosi double %1 to i32		;  [#uses=1]
 	%3 = add i32 %2, 0		;  [#uses=1]
 	%4 = zext i32 %3 to i64		;  [#uses=1]

Modified: llvm/trunk/test/CodeGen/ARM/fnmul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fnmul.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fnmul.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fnmul.ll Thu Jun  4 17:49:04 2009
@@ -4,8 +4,8 @@
 
 define double @t1(double %a, double %b) {
 entry:
-        %tmp2 = sub double -0.000000e+00, %a            ;  [#uses=1]
-        %tmp4 = mul double %tmp2, %b            ;  [#uses=1]
+        %tmp2 = fsub double -0.000000e+00, %a            ;  [#uses=1]
+        %tmp4 = fmul double %tmp2, %b            ;  [#uses=1]
         ret double %tmp4
 }
 

Modified: llvm/trunk/test/CodeGen/ARM/fparith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fparith.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fparith.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fparith.ll Thu Jun  4 17:49:04 2009
@@ -10,49 +10,49 @@
 
 define float @f1(float %a, float %b) {
 entry:
-	%tmp = add float %a, %b		;  [#uses=1]
+	%tmp = fadd float %a, %b		;  [#uses=1]
 	ret float %tmp
 }
 
 define double @f2(double %a, double %b) {
 entry:
-	%tmp = add double %a, %b		;  [#uses=1]
+	%tmp = fadd double %a, %b		;  [#uses=1]
 	ret double %tmp
 }
 
 define float @f3(float %a, float %b) {
 entry:
-	%tmp = mul float %a, %b		;  [#uses=1]
+	%tmp = fmul float %a, %b		;  [#uses=1]
 	ret float %tmp
 }
 
 define double @f4(double %a, double %b) {
 entry:
-	%tmp = mul double %a, %b		;  [#uses=1]
+	%tmp = fmul double %a, %b		;  [#uses=1]
 	ret double %tmp
 }
 
 define float @f5(float %a, float %b) {
 entry:
-	%tmp = sub float %a, %b		;  [#uses=1]
+	%tmp = fsub float %a, %b		;  [#uses=1]
 	ret float %tmp
 }
 
 define double @f6(double %a, double %b) {
 entry:
-	%tmp = sub double %a, %b		;  [#uses=1]
+	%tmp = fsub double %a, %b		;  [#uses=1]
 	ret double %tmp
 }
 
 define float @f7(float %a) {
 entry:
-	%tmp1 = sub float -0.000000e+00, %a		;  [#uses=1]
+	%tmp1 = fsub float -0.000000e+00, %a		;  [#uses=1]
 	ret float %tmp1
 }
 
 define double @f8(double %a) {
 entry:
-	%tmp1 = sub double -0.000000e+00, %a		;  [#uses=1]
+	%tmp1 = fsub double -0.000000e+00, %a		;  [#uses=1]
 	ret double %tmp1
 }
 

Modified: llvm/trunk/test/CodeGen/ARM/fpmem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpmem.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fpmem.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fpmem.ll Thu Jun  4 17:49:04 2009
@@ -11,12 +11,12 @@
 
 define float @f2(float* %v, float %u) {
         %tmp = load float* %v           ;  [#uses=1]
-        %tmp1 = add float %tmp, %u              ;  [#uses=1]
+        %tmp1 = fadd float %tmp, %u              ;  [#uses=1]
         ret float %tmp1
 }
 
 define void @f3(float %a, float %b, float* %v) {
-        %tmp = add float %a, %b         ;  [#uses=1]
+        %tmp = fadd float %a, %b         ;  [#uses=1]
         store float %tmp, float* %v
         ret void
 }

Modified: llvm/trunk/test/CodeGen/ARM/illegal-vector-bitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/illegal-vector-bitcast.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/illegal-vector-bitcast.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/illegal-vector-bitcast.ll Thu Jun  4 17:49:04 2009
@@ -3,7 +3,7 @@
 define void @foo(<8 x float>* %f, <8 x float>* %g, <4 x i64>* %y)
 {
   %h = load <8 x float>* %f
-  %i = mul <8 x float> %h, 
+  %i = fmul <8 x float> %h, 
   %m = bitcast <8 x float> %i to <4 x i64>
   %z = load <4 x i64>* %y
   %n = mul <4 x i64> %z, %m

Modified: llvm/trunk/test/CodeGen/ARM/vfp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vfp.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vfp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vfp.ll Thu Jun  4 17:49:04 2009
@@ -39,10 +39,10 @@
 
 define void @test_add(float* %P, double* %D) {
 	%a = load float* %P		;  [#uses=2]
-	%b = add float %a, %a		;  [#uses=1]
+	%b = fadd float %a, %a		;  [#uses=1]
 	store float %b, float* %P
 	%A = load double* %D		;  [#uses=2]
-	%B = add double %A, %A		;  [#uses=1]
+	%B = fadd double %A, %A		;  [#uses=1]
 	store double %B, double* %D
 	ret void
 }
@@ -61,8 +61,8 @@
 	%a1 = load float* %P1		;  [#uses=1]
 	%a2 = load float* %P2		;  [#uses=1]
 	%a3 = load float* %P3		;  [#uses=1]
-	%X = mul float %a1, %a2		;  [#uses=1]
-	%Y = sub float %X, %a3		;  [#uses=1]
+	%X = fmul float %a1, %a2		;  [#uses=1]
+	%Y = fsub float %X, %a3		;  [#uses=1]
 	store float %Y, float* %P1
 	ret void
 }

Modified: llvm/trunk/test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll (original)
+++ llvm/trunk/test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll Thu Jun  4 17:49:04 2009
@@ -23,7 +23,7 @@
 
 define double @test5(double %D) {
         %X = bitcast double %D to double                ;  [#uses=1]
-        %Y = add double %X, 2.000000e+00                ;  [#uses=1]
+        %Y = fadd double %X, 2.000000e+00                ;  [#uses=1]
         %Z = bitcast double %Y to i64           ;  [#uses=1]
         %res = bitcast i64 %Z to double         ;  [#uses=1]
         ret double %res
@@ -31,7 +31,7 @@
 
 define float @test6(float %F) {
         %X = bitcast float %F to float          ;  [#uses=1]
-        %Y = add float %X, 2.000000e+00         ;  [#uses=1]
+        %Y = fadd float %X, 2.000000e+00         ;  [#uses=1]
         %Z = bitcast float %Y to i32            ;  [#uses=1]
         %res = bitcast i32 %Z to float          ;  [#uses=1]
         ret float %res

Modified: llvm/trunk/test/CodeGen/CBackend/2008-10-21-PPCLongDoubleConstant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/2008-10-21-PPCLongDoubleConstant.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/CBackend/2008-10-21-PPCLongDoubleConstant.ll (original)
+++ llvm/trunk/test/CodeGen/CBackend/2008-10-21-PPCLongDoubleConstant.ll Thu Jun  4 17:49:04 2009
@@ -20,7 +20,7 @@
 	br label %bb4
 
 bb4:		; preds = %bb5.split, %bb4, %entry
-	%0 = fcmp ogt ppc_fp128 0xM00000000000000000000000000000000, select (i1 fcmp olt (ppc_fp128 fpext (double 0x3C447AE147AE147B to ppc_fp128), ppc_fp128 mul (ppc_fp128 0xM00000000000000010000000000000000, ppc_fp128 0xM40140000000000000000000000000000)), ppc_fp128 mul (ppc_fp128 0xM00000000000000010000000000000000, ppc_fp128 0xM40140000000000000000000000000000), ppc_fp128 fpext (double 0x3C447AE147AE147B to ppc_fp128))		;  [#uses=1]
+	%0 = fcmp ogt ppc_fp128 0xM00000000000000000000000000000000, select (i1 fcmp olt (ppc_fp128 fpext (double 0x3C447AE147AE147B to ppc_fp128), ppc_fp128 fmul (ppc_fp128 0xM00000000000000010000000000000000, ppc_fp128 0xM40140000000000000000000000000000)), ppc_fp128 fmul (ppc_fp128 0xM00000000000000010000000000000000, ppc_fp128 0xM40140000000000000000000000000000), ppc_fp128 fpext (double 0x3C447AE147AE147B to ppc_fp128))		;  [#uses=1]
 	br i1 %0, label %bb4, label %bb5.split
 
 bb5.split:		; preds = %bb4

Modified: llvm/trunk/test/CodeGen/CBackend/vectors.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/vectors.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/CBackend/vectors.ll (original)
+++ llvm/trunk/test/CodeGen/CBackend/vectors.ll Thu Jun  4 17:49:04 2009
@@ -14,7 +14,7 @@
 }
 
 define <4 x float> @test3(<4 x float> %Y) {
-	%Z = add <4 x float> %Y, %Y
+	%Z = fadd <4 x float> %Y, %Y
 	%X = shufflevector <4 x float> zeroinitializer, <4 x float> %Z, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >
 	ret <4 x float> %X
 }

Modified: llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll Thu Jun  4 17:49:04 2009
@@ -11,88 +11,88 @@
 target triple = "spu"
 
 define double @fadd(double %arg1, double %arg2) {
-        %A = add double %arg1, %arg2
+        %A = fadd double %arg1, %arg2
         ret double %A
 }
 
 define <2 x double> @fadd_vec(<2 x double> %arg1, <2 x double> %arg2) {
-        %A = add <2 x double> %arg1, %arg2
+        %A = fadd <2 x double> %arg1, %arg2
         ret <2 x double> %A
 }
 
 define double @fsub(double %arg1, double %arg2) {
-        %A = sub double %arg1,  %arg2
+        %A = fsub double %arg1,  %arg2
         ret double %A
 }
 
 define <2 x double> @fsub_vec(<2 x double> %arg1, <2 x double> %arg2) {
-        %A = sub <2 x double> %arg1,  %arg2
+        %A = fsub <2 x double> %arg1,  %arg2
         ret <2 x double> %A
 }
 
 define double @fmul(double %arg1, double %arg2) {
-        %A = mul double %arg1,  %arg2
+        %A = fmul double %arg1,  %arg2
         ret double %A
 }
 
 define <2 x double> @fmul_vec(<2 x double> %arg1, <2 x double> %arg2) {
-        %A = mul <2 x double> %arg1,  %arg2
+        %A = fmul <2 x double> %arg1,  %arg2
         ret <2 x double> %A
 }
 
 define double @fma(double %arg1, double %arg2, double %arg3) {
-        %A = mul double %arg1,  %arg2
-        %B = add double %A, %arg3
+        %A = fmul double %arg1,  %arg2
+        %B = fadd double %A, %arg3
         ret double %B
 }
 
 define <2 x double> @fma_vec(<2 x double> %arg1, <2 x double> %arg2, <2 x double> %arg3) {
-        %A = mul <2 x double> %arg1,  %arg2
-        %B = add <2 x double> %A, %arg3
+        %A = fmul <2 x double> %arg1,  %arg2
+        %B = fadd <2 x double> %A, %arg3
         ret <2 x double> %B
 }
 
 define double @fms(double %arg1, double %arg2, double %arg3) {
-        %A = mul double %arg1,  %arg2
-        %B = sub double %A, %arg3
+        %A = fmul double %arg1,  %arg2
+        %B = fsub double %A, %arg3
         ret double %B
 }
 
 define <2 x double> @fms_vec(<2 x double> %arg1, <2 x double> %arg2, <2 x double> %arg3) {
-        %A = mul <2 x double> %arg1,  %arg2
-        %B = sub <2 x double> %A, %arg3
+        %A = fmul <2 x double> %arg1,  %arg2
+        %B = fsub <2 x double> %A, %arg3
         ret <2 x double> %B
 }
 
 ; - (a * b - c)
 define double @d_fnms_1(double %arg1, double %arg2, double %arg3) {
-        %A = mul double %arg1,  %arg2
-        %B = sub double %A, %arg3
-        %C = sub double -0.000000e+00, %B               ;  [#uses=1]
+        %A = fmul double %arg1,  %arg2
+        %B = fsub double %A, %arg3
+        %C = fsub double -0.000000e+00, %B               ;  [#uses=1]
         ret double %C
 }
 
 ; Annother way of getting fnms
 ; - ( a * b ) + c => c - (a * b)
 define double @d_fnms_2(double %arg1, double %arg2, double %arg3) {
-        %A = mul double %arg1,  %arg2
-        %B = sub double %arg3, %A
+        %A = fmul double %arg1,  %arg2
+        %B = fsub double %arg3, %A
         ret double %B
 }
 
 ; FNMS: - (a * b - c) => c - (a * b)
 define <2 x double> @d_fnms_vec_1(<2 x double> %arg1, <2 x double> %arg2, <2 x double> %arg3) {
-        %A = mul <2 x double> %arg1,  %arg2
-        %B = sub <2 x double> %arg3, %A ;
+        %A = fmul <2 x double> %arg1,  %arg2
+        %B = fsub <2 x double> %arg3, %A ;
         ret <2 x double> %B
 }
 
 ; Another way to get fnms using a constant vector
 ; - ( a * b - c)
 define <2 x double> @d_fnms_vec_2(<2 x double> %arg1, <2 x double> %arg2, <2 x double> %arg3) {
-        %A = mul <2 x double> %arg1,  %arg2     ; <<2 x double>> [#uses=1]
-        %B = sub <2 x double> %A, %arg3 ; <<2 x double>> [#uses=1]
-        %C = sub <2 x double> < double -0.00000e+00, double -0.00000e+00 >, %B
+        %A = fmul <2 x double> %arg1,  %arg2     ; <<2 x double>> [#uses=1]
+        %B = fsub <2 x double> %A, %arg3 ; <<2 x double>> [#uses=1]
+        %C = fsub <2 x double> < double -0.00000e+00, double -0.00000e+00 >, %B
         ret <2 x double> %C
 }
 

Modified: llvm/trunk/test/CodeGen/CellSPU/fneg-fabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/fneg-fabs.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/fneg-fabs.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/fneg-fabs.ll Thu Jun  4 17:49:04 2009
@@ -7,22 +7,22 @@
 target triple = "spu"
 
 define double @fneg_dp(double %X) {
-        %Y = sub double -0.000000e+00, %X
+        %Y = fsub double -0.000000e+00, %X
         ret double %Y
 }
 
 define <2 x double> @fneg_dp_vec(<2 x double> %X) {
-        %Y = sub <2 x double> < double -0.0000e+00, double -0.0000e+00 >, %X
+        %Y = fsub <2 x double> < double -0.0000e+00, double -0.0000e+00 >, %X
         ret <2 x double> %Y
 }
 
 define float @fneg_sp(float %X) {
-        %Y = sub float -0.000000e+00, %X
+        %Y = fsub float -0.000000e+00, %X
         ret float %Y
 }
 
 define <4 x float> @fneg_sp_vec(<4 x float> %X) {
-        %Y = sub <4 x float>  , %X
         ret <4 x float> %Y
 }

Modified: llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll Thu Jun  4 17:49:04 2009
@@ -12,79 +12,79 @@
 target triple = "spu"
 
 define float @fp_add(float %arg1, float %arg2) {
-        %A = add float %arg1, %arg2     ;  [#uses=1]
+        %A = fadd float %arg1, %arg2     ;  [#uses=1]
         ret float %A
 }
 
 define <4 x float> @fp_add_vec(<4 x float> %arg1, <4 x float> %arg2) {
-        %A = add <4 x float> %arg1, %arg2       ; <<4 x float>> [#uses=1]
+        %A = fadd <4 x float> %arg1, %arg2       ; <<4 x float>> [#uses=1]
         ret <4 x float> %A
 }
 
 define float @fp_sub(float %arg1, float %arg2) {
-        %A = sub float %arg1,  %arg2    ;  [#uses=1]
+        %A = fsub float %arg1,  %arg2    ;  [#uses=1]
         ret float %A
 }
 
 define <4 x float> @fp_sub_vec(<4 x float> %arg1, <4 x float> %arg2) {
-        %A = sub <4 x float> %arg1,  %arg2      ; <<4 x float>> [#uses=1]
+        %A = fsub <4 x float> %arg1,  %arg2      ; <<4 x float>> [#uses=1]
         ret <4 x float> %A
 }
 
 define float @fp_mul(float %arg1, float %arg2) {
-        %A = mul float %arg1,  %arg2    ;  [#uses=1]
+        %A = fmul float %arg1,  %arg2    ;  [#uses=1]
         ret float %A
 }
 
 define <4 x float> @fp_mul_vec(<4 x float> %arg1, <4 x float> %arg2) {
-        %A = mul <4 x float> %arg1,  %arg2      ; <<4 x float>> [#uses=1]
+        %A = fmul <4 x float> %arg1,  %arg2      ; <<4 x float>> [#uses=1]
         ret <4 x float> %A
 }
 
 define float @fp_mul_add(float %arg1, float %arg2, float %arg3) {
-        %A = mul float %arg1,  %arg2    ;  [#uses=1]
-        %B = add float %A, %arg3        ;  [#uses=1]
+        %A = fmul float %arg1,  %arg2    ;  [#uses=1]
+        %B = fadd float %A, %arg3        ;  [#uses=1]
         ret float %B
 }
 
 define <4 x float> @fp_mul_add_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) {
-        %A = mul <4 x float> %arg1,  %arg2      ; <<4 x float>> [#uses=1]
-        %B = add <4 x float> %A, %arg3  ; <<4 x float>> [#uses=1]
+        %A = fmul <4 x float> %arg1,  %arg2      ; <<4 x float>> [#uses=1]
+        %B = fadd <4 x float> %A, %arg3  ; <<4 x float>> [#uses=1]
         ret <4 x float> %B
 }
 
 define float @fp_mul_sub(float %arg1, float %arg2, float %arg3) {
-        %A = mul float %arg1,  %arg2    ;  [#uses=1]
-        %B = sub float %A, %arg3        ;  [#uses=1]
+        %A = fmul float %arg1,  %arg2    ;  [#uses=1]
+        %B = fsub float %A, %arg3        ;  [#uses=1]
         ret float %B
 }
 
 define <4 x float> @fp_mul_sub_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) {
-        %A = mul <4 x float> %arg1,  %arg2      ; <<4 x float>> [#uses=1]
-        %B = sub <4 x float> %A, %arg3  ; <<4 x float>> [#uses=1]
+        %A = fmul <4 x float> %arg1,  %arg2      ; <<4 x float>> [#uses=1]
+        %B = fsub <4 x float> %A, %arg3  ; <<4 x float>> [#uses=1]
         ret <4 x float> %B
 }
 
 ; Test the straightforward way of getting fnms
 ; c - a * b
 define float @fp_neg_mul_sub_1(float %arg1, float %arg2, float %arg3) {
-        %A = mul float %arg1,  %arg2
-        %B = sub float %arg3, %A
+        %A = fmul float %arg1,  %arg2
+        %B = fsub float %arg3, %A
         ret float %B
 }
 
 ; Test another way of getting fnms
 ; - ( a *b -c ) = c - a * b
 define float @fp_neg_mul_sub_2(float %arg1, float %arg2, float %arg3) {
-        %A = mul float %arg1,  %arg2
-        %B = sub float %A, %arg3 
-        %C = sub float -0.0, %B
+        %A = fmul float %arg1,  %arg2
+        %B = fsub float %A, %arg3
+        %C = fsub float -0.0, %B
         ret float %C
 }
 
 define <4 x float> @fp_neg_mul_sub_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) {
-        %A = mul <4 x float> %arg1,  %arg2
-        %B = sub <4 x float> %A, %arg3
-        %D = sub <4 x float> < float -0.0, float -0.0, float -0.0, float -0.0 >, %B
+        %A = fmul <4 x float> %arg1,  %arg2
+        %B = fsub <4 x float> %A, %arg3
+        %D = fsub <4 x float> < float -0.0, float -0.0, float -0.0, float -0.0 >, %B
         ret <4 x float> %D
 }

Modified: llvm/trunk/test/CodeGen/Generic/2006-07-03-schedulers.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-07-03-schedulers.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2006-07-03-schedulers.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2006-07-03-schedulers.ll Thu Jun  4 17:49:04 2009
@@ -12,13 +12,13 @@
 	br label %bb1
 
 bb1:		; preds = %bb1, %0
-	%x1 = mul float %x, %y		;  [#uses=1]
-	%y1 = mul float %y, 7.500000e-01		;  [#uses=1]
-	%z1 = add float %x1, %y1		;  [#uses=1]
-	%x2 = mul float %x, 5.000000e-01		;  [#uses=1]
-	%y2 = mul float %y, 0x3FECCCCCC0000000		;  [#uses=1]
-	%z2 = add float %x2, %y2		;  [#uses=1]
-	%z3 = add float %z1, %z2		;  [#uses=1]
+	%x1 = fmul float %x, %y		;  [#uses=1]
+	%y1 = fmul float %y, 7.500000e-01		;  [#uses=1]
+	%z1 = fadd float %x1, %y1		;  [#uses=1]
+	%x2 = fmul float %x, 5.000000e-01		;  [#uses=1]
+	%y2 = fmul float %y, 0x3FECCCCCC0000000		;  [#uses=1]
+	%z2 = fadd float %x2, %y2		;  [#uses=1]
+	%z3 = fadd float %z1, %z2		;  [#uses=1]
 	%i1 = shl i32 %i, 3		;  [#uses=1]
 	%j1 = add i32 %i, 7		;  [#uses=1]
 	%m1 = add i32 %i1, %j1		;  [#uses=2]

Modified: llvm/trunk/test/CodeGen/Generic/2007-05-15-InfiniteRecursion.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2007-05-15-InfiniteRecursion.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2007-05-15-InfiniteRecursion.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2007-05-15-InfiniteRecursion.ll Thu Jun  4 17:49:04 2009
@@ -71,10 +71,10 @@
 	%tmp178.i = add i32 %tmp116117.i, -128		;  [#uses=2]
 	%tmp181.i = mul i32 %tmp178.i, %tmp178.i		;  [#uses=1]
 	%tmp181182.i = sitofp i32 %tmp181.i to float		;  [#uses=1]
-	%tmp199200.pn.in.i = mul float %tmp181182.i, 0.000000e+00		;  [#uses=1]
+	%tmp199200.pn.in.i = fmul float %tmp181182.i, 0.000000e+00		;  [#uses=1]
 	%tmp199200.pn.i = fpext float %tmp199200.pn.in.i to double		;  [#uses=1]
-	%tmp201.pn.i = sub double 1.000000e+00, %tmp199200.pn.i		;  [#uses=1]
-	%factor.2.in.i = mul double 0.000000e+00, %tmp201.pn.i		;  [#uses=1]
+	%tmp201.pn.i = fsub double 1.000000e+00, %tmp199200.pn.i		;  [#uses=1]
+	%factor.2.in.i = fmul double 0.000000e+00, %tmp201.pn.i		;  [#uses=1]
 	%factor.2.i = fptrunc double %factor.2.in.i to float		;  [#uses=1]
 	br i1 false, label %cond_next312.i, label %cond_false222.i
 

Modified: llvm/trunk/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll Thu Jun  4 17:49:04 2009
@@ -5,7 +5,7 @@
 	br label %bb15
 
 bb15:		; preds = %bb15, %entry
-	%tmp21 = add <8 x double> zeroinitializer, zeroinitializer		; <<8 x double>> [#uses=1]
+	%tmp21 = fadd <8 x double> zeroinitializer, zeroinitializer		; <<8 x double>> [#uses=1]
 	br i1 false, label %bb30, label %bb15
 
 bb30:		; preds = %bb15

Modified: llvm/trunk/test/CodeGen/Generic/2008-02-25-NegateZero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2008-02-25-NegateZero.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2008-02-25-NegateZero.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2008-02-25-NegateZero.ll Thu Jun  4 17:49:04 2009
@@ -5,8 +5,8 @@
 entry:
 	%tmp98 = load float* null, align 4		;  [#uses=1]
 	%tmp106 = load float* null, align 4		;  [#uses=1]
-	%tmp113 = add float %tmp98, %tmp106		;  [#uses=1]
-	%tmp119 = sub float %tmp113, 0.000000e+00		;  [#uses=1]
+	%tmp113 = fadd float %tmp98, %tmp106		;  [#uses=1]
+	%tmp119 = fsub float %tmp113, 0.000000e+00		;  [#uses=1]
 	call void (i32, ...)* @foo( i32 0, float 0.000000e+00, float %tmp119 ) nounwind 
 	ret void
 }

Modified: llvm/trunk/test/CodeGen/Generic/2008-02-26-NegatableCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2008-02-26-NegatableCrash.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2008-02-26-NegatableCrash.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2008-02-26-NegatableCrash.ll Thu Jun  4 17:49:04 2009
@@ -30,16 +30,16 @@
 	br i1 false, label %bb471, label %bb505
 
 bb471:		; preds = %bb471, %bb.nph1770
-	%tmp487 = add double 0.000000e+00, 0.000000e+00		;  [#uses=1]
+	%tmp487 = fadd double 0.000000e+00, 0.000000e+00		;  [#uses=1]
 	br i1 false, label %bb505, label %bb471
 
 bb505:		; preds = %bb471, %bb.nph1770
 	%xy.0.lcssa = phi double [ 0.000000e+00, %bb.nph1770 ], [ %tmp487, %bb471 ]		;  [#uses=1]
-	%tmp507 = sub double -0.000000e+00, %xy.0.lcssa		;  [#uses=1]
+	%tmp507 = fsub double -0.000000e+00, %xy.0.lcssa		;  [#uses=1]
 	%tmp509 = fdiv double %tmp507, 0.000000e+00		;  [#uses=1]
-	%tmp510 = mul double %tmp509, 1.024000e+03		;  [#uses=1]
+	%tmp510 = fmul double %tmp509, 1.024000e+03		;  [#uses=1]
 	%tmp516 = fdiv double %tmp510, 0.000000e+00		;  [#uses=1]
-	%tmp517 = add double %tmp516, 5.000000e-01		;  [#uses=1]
+	%tmp517 = fadd double %tmp516, 5.000000e-01		;  [#uses=1]
 	%tmp518 = tail call double @floor( double %tmp517 ) nounwind readnone 		;  [#uses=0]
 	ret i32 0
 

Modified: llvm/trunk/test/CodeGen/Generic/fneg-fabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/fneg-fabs.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/fneg-fabs.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/fneg-fabs.ll Thu Jun  4 17:49:04 2009
@@ -1,12 +1,12 @@
 ; RUN: llvm-as < %s | llc
 
 define double @fneg(double %X) {
-        %Y = sub double -0.000000e+00, %X               ;  [#uses=1]
+        %Y = fsub double -0.000000e+00, %X               ;  [#uses=1]
         ret double %Y
 }
 
 define float @fnegf(float %X) {
-        %Y = sub float -0.000000e+00, %X                ;  [#uses=1]
+        %Y = fsub float -0.000000e+00, %X                ;  [#uses=1]
         ret float %Y
 }
 

Modified: llvm/trunk/test/CodeGen/Generic/print-arith-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/print-arith-fp.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/print-arith-fp.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/print-arith-fp.ll Thu Jun  4 17:49:04 2009
@@ -24,9 +24,9 @@
 	%b_s = getelementptr [8 x i8]* @b_str, i64 0, i64 0		;  [#uses=1]
 	call i32 (i8*, ...)* @printf( i8* %a_s, double %a )		; :1 [#uses=0]
 	call i32 (i8*, ...)* @printf( i8* %b_s, double %b )		; :2 [#uses=0]
-	%add_r = add double %a, %b		;  [#uses=1]
-	%sub_r = sub double %a, %b		;  [#uses=1]
-	%mul_r = mul double %a, %b		;  [#uses=1]
+	%add_r = fadd double %a, %b		;  [#uses=1]
+	%sub_r = fsub double %a, %b		;  [#uses=1]
+	%mul_r = fmul double %a, %b		;  [#uses=1]
 	%div_r = fdiv double %b, %a		;  [#uses=1]
 	%rem_r = frem double %b, %a		;  [#uses=1]
 	%add_s = getelementptr [12 x i8]* @add_str, i64 0, i64 0		;  [#uses=1]

Modified: llvm/trunk/test/CodeGen/Generic/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/select.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/select.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/select.ll Thu Jun  4 17:49:04 2009
@@ -9,8 +9,8 @@
         %a = add i32 %N, 1              ;  [#uses=0]
         %i = add i32 %N, 12345678               ;  [#uses=0]
         %b = add i16 4, 3               ;  [#uses=0]
-        %c = add float %X, 0.000000e+00         ;  [#uses=0]
-        %d = add float %X, 0x400921CAC0000000           ;  [#uses=0]
+        %c = fadd float %X, 0.000000e+00         ;  [#uses=0]
+        %d = fadd float %X, 0x400921CAC0000000           ;  [#uses=0]
         %f = add i32 -1, 10             ;  [#uses=0]
         %g = add i16 20, -1             ;  [#uses=0]
         %j = add i16 -1, 30             ;  [#uses=0]
@@ -126,8 +126,8 @@
         br label %Top
 
 Top:            ; preds = %Top, %0
-        %p = add float %x, %y           ;  [#uses=1]
-        %z = sub float %x, %y           ;  [#uses=1]
+        %p = fadd float %x, %y           ;  [#uses=1]
+        %z = fsub float %x, %y           ;  [#uses=1]
         %b = fcmp ole float %p, %z              ;  [#uses=2]
         %c = xor i1 %b, true            ;  [#uses=0]
         br i1 %b, label %Top, label %goon

Modified: llvm/trunk/test/CodeGen/Generic/storetrunc-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/storetrunc-fp.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/storetrunc-fp.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/storetrunc-fp.ll Thu Jun  4 17:49:04 2009
@@ -1,7 +1,7 @@
 ; RUN: llvm-as < %s | llc
 
 define void @foo(double %a, double %b, float* %fp) {
-	%c = add double %a, %b
+	%c = fadd double %a, %b
 	%d = fptrunc double %c to float
 	store float %d, float* %fp
 	ret void

Modified: llvm/trunk/test/CodeGen/Generic/v-split.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/v-split.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/v-split.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/v-split.ll Thu Jun  4 17:49:04 2009
@@ -4,7 +4,7 @@
 define void @test_f8(%f8 *%P, %f8* %Q, %f8 *%S) {
   %p = load %f8* %P
   %q = load %f8* %Q
-  %R = add %f8 %p, %q
+  %R = fadd %f8 %p, %q
   store %f8 %R, %f8 *%S
   ret void
 }

Modified: llvm/trunk/test/CodeGen/Generic/vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/vector.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Generic/vector.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/vector.ll Thu Jun  4 17:49:04 2009
@@ -14,7 +14,7 @@
 define void @test_f1(%f1* %P, %f1* %Q, %f1* %S) {
 	%p = load %f1* %P		; <%f1> [#uses=1]
 	%q = load %f1* %Q		; <%f1> [#uses=1]
-	%R = add %f1 %p, %q		; <%f1> [#uses=1]
+	%R = fadd %f1 %p, %q		; <%f1> [#uses=1]
 	store %f1 %R, %f1* %S
 	ret void
 }
@@ -22,7 +22,7 @@
 define void @test_f2(%f2* %P, %f2* %Q, %f2* %S) {
 	%p = load %f2* %P		; <%f2> [#uses=1]
 	%q = load %f2* %Q		; <%f2> [#uses=1]
-	%R = add %f2 %p, %q		; <%f2> [#uses=1]
+	%R = fadd %f2 %p, %q		; <%f2> [#uses=1]
 	store %f2 %R, %f2* %S
 	ret void
 }
@@ -30,7 +30,7 @@
 define void @test_f4(%f4* %P, %f4* %Q, %f4* %S) {
 	%p = load %f4* %P		; <%f4> [#uses=1]
 	%q = load %f4* %Q		; <%f4> [#uses=1]
-	%R = add %f4 %p, %q		; <%f4> [#uses=1]
+	%R = fadd %f4 %p, %q		; <%f4> [#uses=1]
 	store %f4 %R, %f4* %S
 	ret void
 }
@@ -38,7 +38,7 @@
 define void @test_f8(%f8* %P, %f8* %Q, %f8* %S) {
 	%p = load %f8* %P		; <%f8> [#uses=1]
 	%q = load %f8* %Q		; <%f8> [#uses=1]
-	%R = add %f8 %p, %q		; <%f8> [#uses=1]
+	%R = fadd %f8 %p, %q		; <%f8> [#uses=1]
 	store %f8 %R, %f8* %S
 	ret void
 }
@@ -46,7 +46,7 @@
 define void @test_fmul(%f8* %P, %f8* %Q, %f8* %S) {
 	%p = load %f8* %P		; <%f8> [#uses=1]
 	%q = load %f8* %Q		; <%f8> [#uses=1]
-	%R = mul %f8 %p, %q		; <%f8> [#uses=1]
+	%R = fmul %f8 %p, %q		; <%f8> [#uses=1]
 	store %f8 %R, %f8* %S
 	ret void
 }
@@ -64,21 +64,21 @@
 
 define void @test_cst(%f4* %P, %f4* %S) {
 	%p = load %f4* %P		; <%f4> [#uses=1]
-	%R = add %f4 %p, < float 0x3FB99999A0000000, float 1.000000e+00, float 2.000000e+00, float 4.500000e+00 >		; <%f4> [#uses=1]
+	%R = fadd %f4 %p, < float 0x3FB99999A0000000, float 1.000000e+00, float 2.000000e+00, float 4.500000e+00 >		; <%f4> [#uses=1]
 	store %f4 %R, %f4* %S
 	ret void
 }
 
 define void @test_zero(%f4* %P, %f4* %S) {
 	%p = load %f4* %P		; <%f4> [#uses=1]
-	%R = add %f4 %p, zeroinitializer		; <%f4> [#uses=1]
+	%R = fadd %f4 %p, zeroinitializer		; <%f4> [#uses=1]
 	store %f4 %R, %f4* %S
 	ret void
 }
 
 define void @test_undef(%f4* %P, %f4* %S) {
 	%p = load %f4* %P		; <%f4> [#uses=1]
-	%R = add %f4 %p, undef		; <%f4> [#uses=1]
+	%R = fadd %f4 %p, undef		; <%f4> [#uses=1]
 	store %f4 %R, %f4* %S
 	ret void
 }
@@ -115,7 +115,7 @@
 
 define void @test_cast_1(%f4* %b, %i4* %a) {
 	%tmp = load %f4* %b		; <%f4> [#uses=1]
-	%tmp2 = add %f4 %tmp, < float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 >		; <%f4> [#uses=1]
+	%tmp2 = fadd %f4 %tmp, < float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 >		; <%f4> [#uses=1]
 	%tmp3 = bitcast %f4 %tmp2 to %i4		; <%i4> [#uses=1]
 	%tmp4 = add %i4 %tmp3, < i32 1, i32 2, i32 3, i32 4 >		; <%i4> [#uses=1]
 	store %i4 %tmp4, %i4* %a
@@ -137,7 +137,7 @@
 	%tmp4 = insertelement %f4 %tmp2, float %X, i32 2		; <%f4> [#uses=1]
 	%tmp6 = insertelement %f4 %tmp4, float %X, i32 3		; <%f4> [#uses=1]
 	%q = load %f4* %Q		; <%f4> [#uses=1]
-	%R = add %f4 %q, %tmp6		; <%f4> [#uses=1]
+	%R = fadd %f4 %q, %tmp6		; <%f4> [#uses=1]
 	store %f4 %R, %f4* %P
 	ret void
 }

Modified: llvm/trunk/test/CodeGen/MSP430/2009-05-19-DoubleSplit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/2009-05-19-DoubleSplit.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/2009-05-19-DoubleSplit.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/2009-05-19-DoubleSplit.ll Thu Jun  4 17:49:04 2009
@@ -2,7 +2,7 @@
 
 define i16 @test(double %d) nounwind {
 entry:
-        %add = add double %d, 1.000000e+00
+        %add = fadd double %d, 1.000000e+00
         %call = tail call i16 @funct(double %add) nounwind
         ret i16 %call
 }

Modified: llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll Thu Jun  4 17:49:04 2009
@@ -5,6 +5,6 @@
 
 define double @dofloat(double %a, double %b) nounwind {
 entry:
-	add double %a, %b		; :0 [#uses=1]
+	fadd double %a, %b		; :0 [#uses=1]
 	ret double %0
 }

Modified: llvm/trunk/test/CodeGen/Mips/2008-07-22-Cstpool.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-22-Cstpool.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-07-22-Cstpool.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-07-22-Cstpool.ll Thu Jun  4 17:49:04 2009
@@ -6,7 +6,7 @@
 
 define float @F(float %a) nounwind {
 entry:
-	add float %a, 0x4011333340000000		; :0 [#uses=1]
-	add float %0, 0x4010666660000000		; :1 [#uses=1]
+	fadd float %a, 0x4011333340000000		; :0 [#uses=1]
+	fadd float %0, 0x4010666660000000		; :1 [#uses=1]
 	ret float %1
 }

Modified: llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll Thu Jun  4 17:49:04 2009
@@ -11,7 +11,7 @@
 	br i1 %0, label %bb, label %bb2
 
 bb:		; preds = %entry
-	add float %a, 1.000000e+00		; :1 [#uses=1]
+	fadd float %a, 1.000000e+00		; :1 [#uses=1]
 	ret float %1
 
 bb2:		; preds = %entry

Modified: llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll Thu Jun  4 17:49:04 2009
@@ -9,7 +9,7 @@
 entry:
 	tail call double @fabs( double %c ) nounwind readnone 		; :0 [#uses=1]
 	tail call double @fabs( double %d ) nounwind readnone 		; :0 [#uses=1]
-  add double %0, %1
+  fadd double %0, %1
   ret double %2
 }
 

Modified: llvm/trunk/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll Thu Jun  4 17:49:04 2009
@@ -21,12 +21,12 @@
 	load i16* %3, align 2		; :4 [#uses=1]
 	uitofp i16 %4 to double		; :5 [#uses=1]
 	tail call double @ldexp( double %5, i32 -32 ) nounwind		; :6 [#uses=1]
-	add double %2, %6		; :7 [#uses=1]
+	fadd double %2, %6		; :7 [#uses=1]
 	getelementptr i16* %xseed, i32 2		; :8 [#uses=1]
 	load i16* %8, align 2		; :9 [#uses=1]
 	uitofp i16 %9 to double		; :10 [#uses=1]
 	tail call double @ldexp( double %10, i32 -16 ) nounwind		; :11 [#uses=1]
-	add double %7, %11		; :12 [#uses=1]
+	fadd double %7, %11		; :12 [#uses=1]
 	ret double %12
 }
 
@@ -45,11 +45,11 @@
 	load i16* %4, align 2		; :5 [#uses=1]
 	uitofp i16 %5 to double		; :6 [#uses=1]
 	tail call double @ldexp( double %6, i32 -32 ) nounwind		; :7 [#uses=1]
-	add double %3, %7		; :8 [#uses=1]
+	fadd double %3, %7		; :8 [#uses=1]
 	getelementptr i16* %xseed, i32 2		; :9 [#uses=1]
 	load i16* %9, align 2		; :10 [#uses=1]
 	uitofp i16 %10 to double		; :11 [#uses=1]
 	tail call double @ldexp( double %11, i32 -16 ) nounwind		; :12 [#uses=1]
-	add double %8, %12		; :13 [#uses=1]
+	fadd double %8, %12		; :13 [#uses=1]
 	ret double %13
 }

Modified: llvm/trunk/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll Thu Jun  4 17:49:04 2009
@@ -5,6 +5,6 @@
 
 ; Dead argument should reserve an FP register.
 define double @bar(double %DEAD, double %X, double %Y) {
-        %tmp.2 = add double %X, %Y              ;  [#uses=1]
+        %tmp.2 = fadd double %X, %Y              ;  [#uses=1]
         ret double %tmp.2
 }

Modified: llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll Thu Jun  4 17:49:04 2009
@@ -9,15 +9,15 @@
 entry:
         %tmp = getelementptr %struct.Point* %pt, i32 0, i32 0           ;  [#uses=2]
         %tmp.upgrd.1 = load double* %tmp                ;  [#uses=1]
-        %tmp2 = add double %tmp.upgrd.1, %x             ;  [#uses=1]
+        %tmp2 = fadd double %tmp.upgrd.1, %x             ;  [#uses=1]
         store double %tmp2, double* %tmp
         %tmp6 = getelementptr %struct.Point* %pt, i32 0, i32 1          ;  [#uses=2]
         %tmp7 = load double* %tmp6              ;  [#uses=1]
-        %tmp9 = add double %tmp7, %y            ;  [#uses=1]
+        %tmp9 = fadd double %tmp7, %y            ;  [#uses=1]
         store double %tmp9, double* %tmp6
         %tmp13 = getelementptr %struct.Point* %pt, i32 0, i32 2         ;  [#uses=2]
         %tmp14 = load double* %tmp13            ;  [#uses=1]
-        %tmp16 = add double %tmp14, %z          ;  [#uses=1]
+        %tmp16 = fadd double %tmp14, %z          ;  [#uses=1]
         store double %tmp16, double* %tmp13
         ret void
 }

Modified: llvm/trunk/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll?rev=72897&r1=72896&r2=72897&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll Thu Jun  4 17:49:04 2009
@@ -604,10 +604,10 @@
 	shufflevector <4 x float> %583, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >		; <<4 x float>>:589 [#uses=1]
 	shufflevector <4 x float> %585, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >		; <<4 x float>>:590 [#uses=1]
 	shufflevector <4 x float> %588, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >		; <<4 x float>>:591 [#uses=1]
-	mul <4 x float> zeroinitializer, %589		; <<4 x float>>:592 [#uses=0]
-	mul <4 x float> zeroinitializer, %590		; <<4 x float>>:593 [#uses=0]
-	mul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:594 [#uses=1]
-	mul <4 x float> zeroinitializer, %591		; <<4 x float>>:595 [#uses=0]
+	fmul <4 x float> zeroinitializer, %589		; <<4 x float>>:592 [#uses=0]
+	fmul <4 x float> zeroinitializer, %590		; <<4 x float>>:593 [#uses=0]
+	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:594 [#uses=1]
+	fmul <4 x float> zeroinitializer, %591		; <<4 x float>>:595 [#uses=0]
 	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0		; <<4 x float>*>:596 [#uses=2]
 	load <4 x float>* %596		; <<4 x float>>:597 [#uses=0]
 	store <4 x float> zeroinitializer, <4 x float>* %596
@@ -621,8 +621,8 @@
 	load <4 x float>* null		; <<4 x float>>:604 [#uses=1]
 	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:605 [#uses=1]
 	load <4 x float>* %605		; <<4 x float>>:606 [#uses=1]
-	sub <4 x float> zeroinitializer, %604		; <<4 x float>>:607 [#uses=2]
-	sub <4 x float> zeroinitializer, %606		; <<4 x float>>:608 [#uses=2]
+	fsub <4 x float> zeroinitializer, %604		; <<4 x float>>:607 [#uses=2]
+	fsub <4 x float> zeroinitializer, %606		; <<4 x float>>:608 [#uses=2]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; :609 [#uses=0]
 	br i1 false, label %617, label %610
 
@@ -672,21 +672,21 @@
 	load <4 x float>* null		; <<4 x float>>:638 [#uses=2]
 	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2		; <<4 x float>*>:639 [#uses=0]
 	load <4 x float>* null		; <<4 x float>>:640 [#uses=2]
-	mul <4 x float> %638, %638		; <<4 x float>>:641 [#uses=1]
-	mul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:642 [#uses=0]
-	mul <4 x float> %640, %640		; <<4 x float>>:643 [#uses=2]
+	fmul <4 x float> %638, %638		; <<4 x float>>:641 [#uses=1]
+	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:642 [#uses=0]
+	fmul <4 x float> %640, %640		; <<4 x float>>:643 [#uses=2]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >		; <<4 x float>>:644 [#uses=0]
 	shufflevector <4 x float> %643, <4 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >		; <<4 x float>>:645 [#uses=1]
-	add <4 x float> %645, %643		; <<4 x float>>:646 [#uses=0]
+	fadd <4 x float> %645, %643		; <<4 x float>>:646 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 >		; <<4 x float>>:647 [#uses=1]
 	shufflevector <4 x float> %641, <4 x float> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 >		; <<4 x float>>:648 [#uses=1]
-	add <4 x float> zeroinitializer, %647		; <<4 x float>>:649 [#uses=2]
-	add <4 x float> zeroinitializer, %648		; <<4 x float>>:650 [#uses=0]
-	add <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:651 [#uses=2]
+	fadd <4 x float> zeroinitializer, %647		; <<4 x float>>:649 [#uses=2]
+	fadd <4 x float> zeroinitializer, %648		; <<4 x float>>:650 [#uses=0]
+	fadd <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:651 [#uses=2]
 	call <4 x float> @llvm.ppc.altivec.vrsqrtefp( <4 x float> %649 )		; <<4 x float>>:652 [#uses=1]
-	mul <4 x float> %652, %649		; <<4 x float>>:653 [#uses=1]
+	fmul <4 x float> %652, %649		; <<4 x float>>:653 [#uses=1]
 	call <4 x float> @llvm.ppc.altivec.vrsqrtefp( <4 x float> %651 )		; <<4 x float>>:654 [#uses=1]
-	mul <4 x float> %654, %651		; <<4 x float>>:655 [#uses=0]
+	fmul <4 x float> %654, %651		; <<4 x float>>:655 [#uses=0]
 	icmp eq i32 0, 0		; :656 [#uses=1]
 	br i1 %656, label %665, label %657
 
@@ -721,9 +721,9 @@
 	load <4 x float>* null		; <<4 x float>>:676 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:677 [#uses=1]
 	shufflevector <4 x float> %675, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:678 [#uses=1]
-	mul <4 x float> zeroinitializer, %677		; <<4 x float>>:679 [#uses=0]
-	mul <4 x float> zeroinitializer, %678		; <<4 x float>>:680 [#uses=0]
-	mul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:681 [#uses=1]
+	fmul <4 x float> zeroinitializer, %677		; <<4 x float>>:679 [#uses=0]
+	fmul <4 x float> zeroinitializer, %678		; <<4 x float>>:680 [#uses=0]
+	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:681 [#uses=1]
 	icmp eq i32 0, 0		; :682 [#uses=1]
 	br i1 %682, label %689, label %683
 
@@ -750,7 +750,7 @@
 	load <4 x float>* null		; <<4 x float>>:698 [#uses=0]
 	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2		; <<4 x float>*>:699 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:700 [#uses=1]
-	add <4 x float> zeroinitializer, %700		; <<4 x float>>:701 [#uses=0]
+	fadd <4 x float> zeroinitializer, %700		; <<4 x float>>:701 [#uses=0]
 	load <4 x i32>* %.sub7896		; <<4 x i32>>:702 [#uses=1]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %702, <4 x i32> zeroinitializer )		; :703 [#uses=0]
 	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1		; <<4 x float>*>:704 [#uses=2]
@@ -769,7 +769,7 @@
 	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2		; <<4 x float>*>:714 [#uses=1]
 	load <4 x float>* %714		; <<4 x float>>:715 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:716 [#uses=0]
-	mul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:717 [#uses=1]
+	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:717 [#uses=1]
 	load <4 x i32>* %.sub7896		; <<4 x i32>>:718 [#uses=0]
 	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 0		; <<4 x float>*>:719 [#uses=1]
 	store <4 x float> zeroinitializer, <4 x float>* %719
@@ -791,10 +791,10 @@
 	load <4 x float>* %732		; <<4 x float>>:733 [#uses=0]
 	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:734 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:735 [#uses=1]
-	mul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:736 [#uses=1]
-	mul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:737 [#uses=1]
-	mul <4 x float> zeroinitializer, %735		; <<4 x float>>:738 [#uses=1]
-	mul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:739 [#uses=1]
+	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:736 [#uses=1]
+	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:737 [#uses=1]
+	fmul <4 x float> zeroinitializer, %735		; <<4 x float>>:738 [#uses=1]
+	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:739 [#uses=1]
 	call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer )		; :740 [#uses=1]
 	icmp eq i32 %740, 0		; :741 [#uses=0]
 	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0		; <<4 x float>*>:742 [#uses=2]
@@ -821,9 +821,9 @@
 	getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3		; <<4 x float>*>:761 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:762 [#uses=0]
 	shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer		; <<4 x float>>:763 [#uses=1]
-	add <4 x float> %757, zeroinitializer		; <<4 x float>>:764 [#uses=0]
-	add <4 x float> %758, %763		; <<4 x float>>:765 [#uses=0]
-	mul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:766 [#uses=1]
+	fadd <4 x float> %757, zeroinitializer		; <<4 x float>>:764 [#uses=0]
+	fadd <4 x float> %758, %763		; <<4 x float>>:765 [#uses=0]
+	fmul <4 x float> zeroinitializer, zeroinitializer		; <<4 x float>>:766 [#uses=1]
 	br i1 false, label %773, label %767
 
 ;
    to column one to avoid an extra line of spaces in the example. Modified: llvm/trunk/docs/GoldPlugin.html Modified: llvm/trunk/docs/GoldPlugin.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GoldPlugin.html?rev=73003&r1=73002&r2=73003&view=diff ============================================================================== --- llvm/trunk/docs/GoldPlugin.html (original) +++ llvm/trunk/docs/GoldPlugin.html Sat Jun 6 13:14:04 2009 @@ -157,7 +157,7 @@ export NM="$PREFIX/bin/nm" export RANLIB=/bin/true #ranlib is not needed, and doesn't support .bc files in .a export CFLAGS="-O4" - +
  • Or you can just set your path: 
    @@ -166,7 +166,7 @@
 export CXX="llvm-g++ -use-gold-plugin"
 export RANLIB=/bin/true
 export CFLAGS="-O4"
-
    +
  • Configure & build the project as usual: ./configure && make && make check
    • From eli.friedman at gmail.com Sat Jun 6 15:08:04 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Sat, 06 Jun 2009 20:08:04 -0000 Subject: [llvm-commits] [llvm] r73006 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/vec_demanded_elts-3.ll Message-ID: <200906062008.n56K847F019782@zion.cs.uiuc.edu> Author: efriedma Date: Sat Jun 6 15:08:03 2009 New Revision: 73006 URL: http://llvm.org/viewvc/llvm-project?rev=73006&view=rev Log: PR4340: Run SimplifyDemandedVectorElts on insertelement instructions; sometimes it can find simplifications that won't be found otherwise. Added: llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-3.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=73006&r1=73005&r2=73006&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Sat Jun 6 15:08:03 2009 @@ -12579,6 +12579,12 @@ } } + unsigned VWidth = cast(VecOp->getType())->getNumElements(); + APInt UndefElts(VWidth, 0); + APInt AllOnesEltMask(APInt::getAllOnesValue(VWidth)); + if (SimplifyDemandedVectorElts(&IE, AllOnesEltMask, UndefElts)) + return &IE; + return 0; } Added: llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-3.ll?rev=73006&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-3.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-3.ll Sat Jun 6 15:08:03 2009 @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep load +; PR4340 + +define void @vac(<4 x float>* nocapture %a) nounwind { +entry: + %tmp1 = load <4 x float>* %a ; <<4 x float>> [#uses=1] + %vecins = insertelement <4 x float> %tmp1, float 0.000000e+00, i32 0 ; <<4 x float>> [#uses=1] + %vecins4 = insertelement <4 x float> %vecins, float 0.000000e+00, i32 1; <<4 x float>> [#uses=1] + %vecins6 = insertelement <4 x float> %vecins4, float 0.000000e+00, i32 2; <<4 x float>> [#uses=1] + %vecins8 = insertelement <4 x float> %vecins6, float 0.000000e+00, i32 3; <<4 x float>> [#uses=1] + store <4 x float> %vecins8, <4 x float>* %a + ret void +} + From nicholas at mxc.ca Sat Jun 6 18:13:08 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Sat, 06 Jun 2009 23:13:08 -0000 Subject: [llvm-commits] [llvm] r73007 - /llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Message-ID: <200906062313.n56ND9Po025569@zion.cs.uiuc.edu> Author: nicholas Date: Sat Jun 6 18:13:08 2009 New Revision: 73007 URL: http://llvm.org/viewvc/llvm-project?rev=73007&view=rev Log: Don't crash on multiple return value with no obvious inserted value. Fixes PR4314. Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=73007&r1=73006&r2=73007&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Sat Jun 6 18:13:08 2009 @@ -639,8 +639,8 @@ DenseMap, LatticeVal>::iterator It = TrackedMultipleRetVals.find(std::make_pair(F, i)); if (It == TrackedMultipleRetVals.end()) break; - Value *Val = FindInsertedValue(I.getOperand(0), i); - mergeInValue(It->second, F, getValueState(Val)); + if (Value *Val = FindInsertedValue(I.getOperand(0), i)) + mergeInValue(It->second, F, getValueState(Val)); } } } From nicholas at mxc.ca Sat Jun 6 19:50:47 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 07 Jun 2009 00:50:47 -0000 Subject: [llvm-commits] [llvm] r73008 - /llvm/trunk/tools/gold/gold-plugin.cpp Message-ID: <200906070050.n570olqB028745@zion.cs.uiuc.edu> Author: nicholas Date: Sat Jun 6 19:50:45 2009 New Revision: 73008 URL: http://llvm.org/viewvc/llvm-project?rev=73008&view=rev Log: Add option for specifying the path to assembler, "as". This overrides the path to gcc. Modified: llvm/trunk/tools/gold/gold-plugin.cpp Modified: llvm/trunk/tools/gold/gold-plugin.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/gold-plugin.cpp?rev=73008&r1=73007&r2=73008&view=diff ============================================================================== --- llvm/trunk/tools/gold/gold-plugin.cpp (original) +++ llvm/trunk/tools/gold/gold-plugin.cpp Sat Jun 6 19:50:45 2009 @@ -45,6 +45,7 @@ bool generate_api_file = false; const char *gcc_path = NULL; + const char *as_path = NULL; struct claimed_file { lto_module_t M; @@ -109,6 +110,13 @@ } else { gcc_path = strdup(tv->tv_u.tv_string + 4); } + } else if (strncmp("as=", tv->tv_u.tv_string, 3) == 0) { + if (as_path) { + (*message)(LDPL_WARNING, "Path to as specified twice. " + "Discarding %s", tv->tv_u.tv_string); + } else { + as_path = strdup(tv->tv_u.tv_string + 3); + } } else { (*message)(LDPL_WARNING, "Ignoring flag %s", tv->tv_u.tv_string); } @@ -346,6 +354,8 @@ lto_codegen_set_debug_model(cg, LTO_DEBUG_MODEL_DWARF); if (gcc_path) lto_codegen_set_gcc_path(cg, gcc_path); + if (as_path) + lto_codegen_set_assembler_path(cg, as_path); size_t bufsize = 0; const char *buffer = static_cast(lto_codegen_compile(cg, From eli.friedman at gmail.com Sat Jun 6 20:07:56 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Sun, 07 Jun 2009 01:07:56 -0000 Subject: [llvm-commits] [llvm] r73009 - in /llvm/trunk: lib/Target/PowerPC/PPCInstrAltivec.td test/CodeGen/PowerPC/vec_shift.ll Message-ID: <200906070107.n5717uPV029219@zion.cs.uiuc.edu> Author: efriedma Date: Sat Jun 6 20:07:55 2009 New Revision: 73009 URL: http://llvm.org/viewvc/llvm-project?rev=73009&view=rev Log: PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec instructions. Added: llvm/trunk/test/CodeGen/PowerPC/vec_shift.ll Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=73009&r1=73008&r2=73009&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Sat Jun 6 20:07:55 2009 @@ -666,3 +666,25 @@ def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC), (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC)>; + +// Vector shifts +def : Pat<(v16i8 (shl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), + (v16i8 (VSLB VRRC:$vA, VRRC:$vB))>; +def : Pat<(v8i16 (shl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), + (v8i16 (VSLH VRRC:$vA, VRRC:$vB))>; +def : Pat<(v4i32 (shl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), + (v4i32 (VSLW VRRC:$vA, VRRC:$vB))>; + +def : Pat<(v16i8 (srl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), + (v16i8 (VSRB VRRC:$vA, VRRC:$vB))>; +def : Pat<(v8i16 (srl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), + (v8i16 (VSRH VRRC:$vA, VRRC:$vB))>; +def : Pat<(v4i32 (srl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), + (v4i32 (VSRW VRRC:$vA, VRRC:$vB))>; + +def : Pat<(v16i8 (sra (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), + (v16i8 (VSRAB VRRC:$vA, VRRC:$vB))>; +def : Pat<(v8i16 (sra (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), + (v8i16 (VSRAH VRRC:$vA, VRRC:$vB))>; +def : Pat<(v4i32 (sra (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), + (v4i32 (VSRAW VRRC:$vA, VRRC:$vB))>; Added: llvm/trunk/test/CodeGen/PowerPC/vec_shift.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_shift.ll?rev=73009&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/vec_shift.ll (added) +++ llvm/trunk/test/CodeGen/PowerPC/vec_shift.ll Sat Jun 6 20:07:55 2009 @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 +; PR3628 + +define void @update(<4 x i32> %val, <4 x i32>* %dst) nounwind { +entry: + %shl = shl <4 x i32> %val, < i32 4, i32 3, i32 2, i32 1 > + %shr = ashr <4 x i32> %shl, < i32 1, i32 2, i32 3, i32 4 > + store <4 x i32> %shr, <4 x i32>* %dst + ret void +} From nicholas at mxc.ca Sat Jun 6 20:45:11 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 07 Jun 2009 01:45:11 -0000 Subject: [llvm-commits] [llvm] r73010 - /llvm/trunk/lib/AsmParser/LLParser.cpp Message-ID: <200906070145.n571jB6x030368@zion.cs.uiuc.edu> Author: nicholas Date: Sat Jun 6 20:45:11 2009 New Revision: 73010 URL: http://llvm.org/viewvc/llvm-project?rev=73010&view=rev Log: Refuse metadata* type for function arguments. Modified: llvm/trunk/lib/AsmParser/LLParser.cpp Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=73010&r1=73009&r2=73010&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Sat Jun 6 20:45:11 2009 @@ -1149,7 +1149,9 @@ Lex.Lex(); } - if (!ArgTy->isFirstClassType() && !isa(ArgTy)) + if ((!ArgTy->isFirstClassType() && !isa(ArgTy)) || + (isa(ArgTy) && + cast(ArgTy)->getElementType() == Type::MetadataTy)) return Error(TypeLoc, "invalid type for function argument"); ArgList.push_back(ArgInfo(TypeLoc, ArgTy, Attrs, Name)); From nicholas at mxc.ca Sat Jun 6 23:03:02 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 07 Jun 2009 04:03:02 -0000 Subject: [llvm-commits] [llvm] r73011 - /llvm/trunk/lib/VMCore/Verifier.cpp Message-ID: <200906070403.n57432FU001800@zion.cs.uiuc.edu> Author: nicholas Date: Sat Jun 6 23:03:01 2009 New Revision: 73011 URL: http://llvm.org/viewvc/llvm-project?rev=73011&view=rev Log: Remove cyclic MDNode detection. Any attempt to create a cyclic MDNode will crash LLVM first. Modified: llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=73011&r1=73010&r2=73011&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Sat Jun 6 23:03:01 2009 @@ -280,7 +280,6 @@ bool isReturnValue, const Value *V); void VerifyFunctionAttrs(const FunctionType *FT, const AttrListPtr &Attrs, const Value *V); - bool VerifyMDNode(const MDNode *N); void WriteValue(const Value *V) { if (!V) return; @@ -380,24 +379,22 @@ // Verify that any metadata used in a global initializer points only to // other globals. if (MDNode *FirstNode = dyn_cast(GV.getInitializer())) { - if (VerifyMDNode(FirstNode)) { - SmallVector NodesToAnalyze; - NodesToAnalyze.push_back(FirstNode); - while (!NodesToAnalyze.empty()) { - const MDNode *N = NodesToAnalyze.back(); - NodesToAnalyze.pop_back(); - - for (MDNode::const_elem_iterator I = N->elem_begin(), - E = N->elem_end(); I != E; ++I) - if (const Value *V = *I) { - if (const MDNode *Next = dyn_cast(V)) - NodesToAnalyze.push_back(Next); - else - Assert3(isa(V), - "reference to instruction from global metadata node", - &GV, N, V); - } - } + SmallVector NodesToAnalyze; + NodesToAnalyze.push_back(FirstNode); + while (!NodesToAnalyze.empty()) { + const MDNode *N = NodesToAnalyze.back(); + NodesToAnalyze.pop_back(); + + for (MDNode::const_elem_iterator I = N->elem_begin(), + E = N->elem_end(); I != E; ++I) + if (const Value *V = *I) { + if (const MDNode *Next = dyn_cast(V)) + NodesToAnalyze.push_back(Next); + else + Assert3(isa(V), + "reference to instruction from global metadata node", + &GV, N, V); + } } } } else { @@ -1708,44 +1705,6 @@ "Intrinsic has wrong parameter attributes!", F); } -/// Verify that an MDNode is not cyclic. -bool Verifier::VerifyMDNode(const MDNode *N) { - if (N->elem_empty()) return true; - - // The current DFS path through the nodes. Node and element number. - typedef std::pair Edge; - SmallVector Path; - - Path.push_back(std::make_pair(N, N->elem_begin())); - while (!Path.empty()) { - Edge &e = Path.back(); - const MDNode *&e_N = e.first; - MDNode::const_elem_iterator &e_I = e.second; - - if (e_N->elem_end() == e_I) { - Path.pop_back(); - continue; - } - - for (MDNode::const_elem_iterator e_E = e_N->elem_end(); e_I != e_E; ++e_I) { - if (const MDNode *C = dyn_cast_or_null(e_I->operator Value*())) { - // Is child MDNode C already in the Path? - for (SmallVectorImpl::iterator I = Path.begin(), E = Path.end(); - I != E; ++I) { - if (I->first != C) { - CheckFailed("MDNode is cyclic.", C); - return false; - } - } - - Path.push_back(std::make_pair(C, C->elem_begin())); - break; - } - } - } - return true; -} - //===----------------------------------------------------------------------===// // Implement the public interfaces to this file... From eli.friedman at gmail.com Sun Jun 7 01:52:45 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Sun, 07 Jun 2009 06:52:45 -0000 Subject: [llvm-commits] [llvm] r73012 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/vec_loadsingles.ll test/CodeGen/X86/vec_set-5.ll test/CodeGen/X86/vec_set-6.ll Message-ID: <200906070652.n576qjEL006861@zion.cs.uiuc.edu> Author: efriedma Date: Sun Jun 7 01:52:44 2009 New Revision: 73012 URL: http://llvm.org/viewvc/llvm-project?rev=73012&view=rev Log: Slightly generalize the code that handles shuffles of consecutive loads on x86 to handle more cases. Fix a bug in said code that would cause it to read past the end of an object. Rewrite the code in SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. Remove PerformBuildVectorCombine, which is no longer necessary with these changes. In addition to simplifying the code, with this change, we can now catch a few more cases of consecutive loads. Added: llvm/trunk/test/CodeGen/X86/vec_loadsingles.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/vec_set-5.ll llvm/trunk/test/CodeGen/X86/vec_set-6.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=73012&r1=73011&r2=73012&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Jun 7 01:52:44 2009 @@ -1785,48 +1785,41 @@ /// support the operation, but do support the resultant vector type. SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { unsigned NumElems = Node->getNumOperands(); - SDValue SplatValue = Node->getOperand(0); + SDValue Value1, Value2; DebugLoc dl = Node->getDebugLoc(); MVT VT = Node->getValueType(0); - MVT OpVT = SplatValue.getValueType(); + MVT OpVT = Node->getOperand(0).getValueType(); MVT EltVT = VT.getVectorElementType(); // If the only non-undef value is the low element, turn this into a // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. bool isOnlyLowElement = true; - - // FIXME: it would be far nicer to change this into map - // and use a bitmask instead of a list of elements. - // FIXME: this doesn't treat <0, u, 0, u> for example, as a splat. - std::map > Values; - Values[SplatValue].push_back(0); + bool MoreThanTwoValues = false; bool isConstant = true; - if (!isa(SplatValue) && !isa(SplatValue) && - SplatValue.getOpcode() != ISD::UNDEF) - isConstant = false; - - for (unsigned i = 1; i < NumElems; ++i) { + for (unsigned i = 0; i < NumElems; ++i) { SDValue V = Node->getOperand(i); - Values[V].push_back(i); - if (V.getOpcode() != ISD::UNDEF) + if (V.getOpcode() == ISD::UNDEF) + continue; + if (i > 0) isOnlyLowElement = false; - if (SplatValue != V) - SplatValue = SDValue(0, 0); - - // If this isn't a constant element or an undef, we can't use a constant - // pool load. - if (!isa(V) && !isa(V) && - V.getOpcode() != ISD::UNDEF) + if (!isa(V) && !isa(V)) isConstant = false; + + if (!Value1.getNode()) { + Value1 = V; + } else if (!Value2.getNode()) { + if (V != Value1) + Value2 = V; + } else if (V != Value1 && V != Value2) { + MoreThanTwoValues = true; + } } - if (isOnlyLowElement) { - // If the low element is an undef too, then this whole things is an undef. - if (Node->getOperand(0).getOpcode() == ISD::UNDEF) - return DAG.getUNDEF(VT); - // Otherwise, turn this into a scalar_to_vector node. + if (!Value1.getNode()) + return DAG.getUNDEF(VT); + + if (isOnlyLowElement) return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); - } // If all elements are constants, create a load from the constant pool. if (isConstant) { @@ -1852,59 +1845,25 @@ false, Alignment); } - if (SplatValue.getNode()) { // Splat of one value? - // Build the shuffle constant vector: <0, 0, 0, 0> - SmallVector ZeroVec(NumElems, 0); - - // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. - if (TLI.isShuffleMaskLegal(ZeroVec, Node->getValueType(0))) { + if (!MoreThanTwoValues) { + SmallVector ShuffleVec(NumElems, -1); + for (unsigned i = 0; i < NumElems; ++i) { + SDValue V = Node->getOperand(i); + if (V.getOpcode() == ISD::UNDEF) + continue; + ShuffleVec[i] = V == Value1 ? 0 : NumElems; + } + if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { // Get the splatted value into the low element of a vector register. - SDValue LowValVec = - DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, SplatValue); + SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); + SDValue Vec2; + if (Value2.getNode()) + Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); + else + Vec2 = DAG.getUNDEF(VT); // Return shuffle(LowValVec, undef, <0,0,0,0>) - return DAG.getVectorShuffle(VT, dl, LowValVec, DAG.getUNDEF(VT), - &ZeroVec[0]); - } - } - - // If there are only two unique elements, we may be able to turn this into a - // vector shuffle. - if (Values.size() == 2) { - // Get the two values in deterministic order. - SDValue Val1 = Node->getOperand(1); - SDValue Val2; - std::map >::iterator MI = Values.begin(); - if (MI->first != Val1) - Val2 = MI->first; - else - Val2 = (++MI)->first; - - // If Val1 is an undef, make sure it ends up as Val2, to ensure that our - // vector shuffle has the undef vector on the RHS. - if (Val1.getOpcode() == ISD::UNDEF) - std::swap(Val1, Val2); - - // Build the shuffle constant vector: e.g. <0, 4, 0, 4> - SmallVector ShuffleMask(NumElems, -1); - - // Set elements of the shuffle mask for Val1. - std::vector &Val1Elts = Values[Val1]; - for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) - ShuffleMask[Val1Elts[i]] = 0; - - // Set elements of the shuffle mask for Val2. - std::vector &Val2Elts = Values[Val2]; - for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) - if (Val2.getOpcode() != ISD::UNDEF) - ShuffleMask[Val2Elts[i]] = NumElems; - - // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. - if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, VT) && - TLI.isShuffleMaskLegal(ShuffleMask, VT)) { - Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val1); - Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val2); - return DAG.getVectorShuffle(VT, dl, Val1, Val2, &ShuffleMask[0]); + return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); } } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=73012&r1=73011&r2=73012&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Jun 7 01:52:44 2009 @@ -7691,13 +7691,15 @@ } static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems, - MVT EVT, SDNode *&Base, + MVT EVT, LoadSDNode *&LDBase, + unsigned &LastLoadedElt, SelectionDAG &DAG, MachineFrameInfo *MFI, const TargetLowering &TLI) { - Base = NULL; + LDBase = NULL; + LastLoadedElt = -1; for (unsigned i = 0; i < NumElems; ++i) { if (N->getMaskElt(i) < 0) { - if (!Base) + if (!LDBase) return false; continue; } @@ -7706,19 +7708,20 @@ if (!Elt.getNode() || (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) return false; - if (!Base) { - Base = Elt.getNode(); - if (Base->getOpcode() == ISD::UNDEF) + if (!LDBase) { + if (Elt.getNode()->getOpcode() == ISD::UNDEF) return false; + LDBase = cast(Elt.getNode()); + LastLoadedElt = i; continue; } if (Elt.getOpcode() == ISD::UNDEF) continue; LoadSDNode *LD = cast(Elt); - LoadSDNode *LDBase = cast(Base); if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI)) return false; + LastLoadedElt = i; } return true; } @@ -7737,6 +7740,9 @@ ShuffleVectorSDNode *SVN = cast(N); unsigned NumElems = VT.getVectorNumElements(); + if (VT.getSizeInBits() != 128) + return SDValue(); + // For x86-32 machines, if we see an insert and then a shuffle in a v2i64 // where the upper half is 0, it is advantageous to rewrite it as a build // vector of (0, val) so it can use movq. @@ -7764,107 +7770,24 @@ // Try to combine a vector_shuffle into a 128-bit load. MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); - SDNode *Base = NULL; - if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, Base, DAG, MFI, TLI)) + LoadSDNode *LD = NULL; + unsigned LastLoadedElt; + if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG, + MFI, TLI)) return SDValue(); - LoadSDNode *LD = cast(Base); - if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI)) + if (LastLoadedElt == NumElems - 1) { + if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI)) + return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), + LD->getSrcValue(), LD->getSrcValueOffset(), + LD->isVolatile()); return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), LD->getSrcValueOffset(), - LD->isVolatile()); - return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), - LD->getSrcValue(), LD->getSrcValueOffset(), - LD->isVolatile(), LD->getAlignment()); -} - -/// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd. -static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG, - TargetLowering::DAGCombinerInfo &DCI, - const X86Subtarget *Subtarget, - const TargetLowering &TLI) { - unsigned NumOps = N->getNumOperands(); - DebugLoc dl = N->getDebugLoc(); - - // Ignore single operand BUILD_VECTOR. - if (NumOps == 1) - return SDValue(); - - MVT VT = N->getValueType(0); - MVT EVT = VT.getVectorElementType(); - - // Before or during type legalization, we want to try and convert a - // build_vector of an i64 load and a zero value into vzext_movl before the - // legalizer can break it up. - // FIXME: does the case below remove the need to do this? - if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) { - if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit()) - return SDValue(); - - // This must be an insertion into a zero vector. - SDValue HighElt = N->getOperand(1); - if (!isZeroNode(HighElt)) - return SDValue(); - - // Value must be a load. - SDNode *Base = N->getOperand(0).getNode(); - if (!isa(Base)) { - if (Base->getOpcode() != ISD::BIT_CONVERT) - return SDValue(); - Base = Base->getOperand(0).getNode(); - if (!isa(Base)) - return SDValue(); - } - - // Transform it into VZEXT_LOAD addr. - LoadSDNode *LD = cast(Base); - - // Load must not be an extload. - if (LD->getExtensionType() != ISD::NON_EXTLOAD) - return SDValue(); - - // Load type should legal type so we don't have to legalize it. - if (!TLI.isTypeLegal(VT)) - return SDValue(); - - SDVTList Tys = DAG.getVTList(VT, MVT::Other); - SDValue Ops[] = { LD->getChain(), LD->getBasePtr() }; - SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); - TargetLowering::TargetLoweringOpt TLO(DAG); - TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1)); - DCI.CommitTargetLoweringOpt(TLO); - return ResNode; - } - - // The type legalizer will have broken apart v2i64 build_vector created during - // widening before the code which handles that case is run. Look for build - // vector (load, load + 4, 0/undef, 0/undef) - if (VT == MVT::v4i32 || VT == MVT::v4f32) { - LoadSDNode *LD0 = dyn_cast(N->getOperand(0)); - LoadSDNode *LD1 = dyn_cast(N->getOperand(1)); - if (!LD0 || !LD1) - return SDValue(); - if (LD0->getExtensionType() != ISD::NON_EXTLOAD || - LD1->getExtensionType() != ISD::NON_EXTLOAD) - return SDValue(); - // Make sure the second elt is a consecutive load. - if (!TLI.isConsecutiveLoad(LD1, LD0, EVT.getSizeInBits()/8, 1, - DAG.getMachineFunction().getFrameInfo())) - return SDValue(); - - SDValue N2 = N->getOperand(2); - SDValue N3 = N->getOperand(3); - if (!isZeroNode(N2) && N2.getOpcode() != ISD::UNDEF) - return SDValue(); - if (!isZeroNode(N3) && N3.getOpcode() != ISD::UNDEF) - return SDValue(); - + LD->isVolatile(), LD->getAlignment()); + } else if (NumElems == 4 && LastLoadedElt == 1) { SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); - SDValue Ops[] = { LD0->getChain(), LD0->getBasePtr() }; + SDValue Ops[] = { LD->getChain(), LD->getBasePtr() }; SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); - TargetLowering::TargetLoweringOpt TLO(DAG); - TLO.CombineTo(SDValue(LD0, 1), ResNode.getValue(1)); - DCI.CommitTargetLoweringOpt(TLO); return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode); } return SDValue(); @@ -8466,14 +8389,25 @@ return SDValue(); } +static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { + SDValue Op = N->getOperand(0); + if (Op.getOpcode() == ISD::BIT_CONVERT) + Op = Op.getOperand(0); + MVT VT = N->getValueType(0), OpVT = Op.getValueType(); + if (Op.getOpcode() == X86ISD::VZEXT_LOAD && + VT.getVectorElementType().getSizeInBits() == + OpVT.getVectorElementType().getSizeInBits()) { + return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); + } + return SDValue(); +} + SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { SelectionDAG &DAG = DCI.DAG; switch (N->getOpcode()) { default: break; case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); - case ISD::BUILD_VECTOR: - return PerformBuildVectorCombine(N, DAG, DCI, Subtarget, *this); case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); case ISD::MUL: return PerformMulCombine(N, DAG, DCI); @@ -8485,6 +8419,7 @@ case X86ISD::FOR: return PerformFORCombine(N, DAG); case X86ISD::FAND: return PerformFANDCombine(N, DAG); case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); + case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); } return SDValue(); Added: llvm/trunk/test/CodeGen/X86/vec_loadsingles.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_loadsingles.ll?rev=73012&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_loadsingles.ll (added) +++ llvm/trunk/test/CodeGen/X86/vec_loadsingles.ll Sun Jun 7 01:52:44 2009 @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movq + +define <4 x float> @a(<4 x float> %a, float* nocapture %p) nounwind readonly { +entry: + %tmp1 = load float* %p + %vecins = insertelement <4 x float> undef, float %tmp1, i32 0 + %add.ptr = getelementptr float* %p, i32 1 + %tmp5 = load float* %add.ptr + %vecins7 = insertelement <4 x float> %vecins, float %tmp5, i32 1 + ret <4 x float> %vecins7 +} + Modified: llvm/trunk/test/CodeGen/X86/vec_set-5.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-5.ll?rev=73012&r1=73011&r2=73012&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_set-5.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_set-5.ll Sun Jun 7 01:52:44 2009 @@ -1,7 +1,6 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t -f ; RUN: grep movlhps %t | count 1 -; RUN: grep movq %t | count 1 -; RUN: grep movsd %t | count 1 +; RUN: grep movq %t | count 2 define <4 x float> @test1(float %a, float %b) nounwind { %tmp = insertelement <4 x float> zeroinitializer, float %a, i32 0 ; <<4 x float>> [#uses=1] Modified: llvm/trunk/test/CodeGen/X86/vec_set-6.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-6.ll?rev=73012&r1=73011&r2=73012&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_set-6.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_set-6.ll Sun Jun 7 01:52:44 2009 @@ -1,6 +1,6 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t -f ; RUN: grep movss %t | count 1 -; RUN: grep movups %t | count 1 +; RUN: grep movq %t | count 1 ; RUN: grep shufps %t | count 1 define <4 x float> @test(float %a, float %b, float %c) nounwind { From foldr at codedgers.com Sun Jun 7 02:08:02 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Sun, 07 Jun 2009 07:08:02 -0000 Subject: [llvm-commits] [llvm] r73013 - in /llvm/trunk/tools/llvmc/example/mcc16: ./ Makefile README driver/ driver/Main.cpp driver/Makefile plugins/ plugins/Makefile plugins/PIC16Base/ plugins/PIC16Base/Makefile plugins/PIC16Base/PIC16Base.td plugins/PIC16Base/PluginMain.cpp Message-ID: <200906070708.n57782kc007383@zion.cs.uiuc.edu> Author: foldr Date: Sun Jun 7 02:08:01 2009 New Revision: 73013 URL: http://llvm.org/viewvc/llvm-project?rev=73013&view=rev Log: A basic PIC16 toolchain driver. Nice addition to the examples and also a starting point for Sanjiv to work on. Added: llvm/trunk/tools/llvmc/example/mcc16/ llvm/trunk/tools/llvmc/example/mcc16/Makefile llvm/trunk/tools/llvmc/example/mcc16/README llvm/trunk/tools/llvmc/example/mcc16/driver/ llvm/trunk/tools/llvmc/example/mcc16/driver/Main.cpp llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile llvm/trunk/tools/llvmc/example/mcc16/plugins/ llvm/trunk/tools/llvmc/example/mcc16/plugins/Makefile llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/ llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/Makefile llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PIC16Base.td llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp Added: llvm/trunk/tools/llvmc/example/mcc16/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/mcc16/Makefile?rev=73013&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/example/mcc16/Makefile (added) +++ llvm/trunk/tools/llvmc/example/mcc16/Makefile Sun Jun 7 02:08:01 2009 @@ -0,0 +1,24 @@ +##===- llvmc/example/mcc16/Makefile ------------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open +# Source License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +# Change this so that $(BASE_LEVEL)/Makefile.common refers to +# $LLVM_DIR/Makefile.common. +export LLVMC_BASE_LEVEL = ../../../.. + +# Change this to the name of your LLVMC-based driver. +export LLVMC_BASED_DRIVER_NAME = mcc16 + +# List your plugin names here +export LLVMC_BUILTIN_PLUGINS = PIC16Base + +LEVEL = $(LLVMC_BASE_LEVEL) + +DIRS = plugins driver + +include $(LEVEL)/Makefile.common Added: llvm/trunk/tools/llvmc/example/mcc16/README URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/mcc16/README?rev=73013&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/example/mcc16/README (added) +++ llvm/trunk/tools/llvmc/example/mcc16/README Sun Jun 7 02:08:01 2009 @@ -0,0 +1,75 @@ +This is a basic compiler driver for the PIC16 toolchain that shows how to create +your own llvmc-based drivers. It is based on the example/Skeleton template. + +The PIC16 toolchain looks like this: + +clang-cc (FE) -> llvm-ld (optimizer) -> llc (codegen) -> native-as -> native-ld + +Following features were requested by Sanjiv: + +From: Sanjiv Gupta microchip.com> +Subject: Re: llvmc for PIC16 +Newsgroups: gmane.comp.compilers.llvm.devel +Date: 2009-06-05 06:51:14 GMT + +The salient features that we want to have in the driver are: +1. llvm-ld will be used as "The Optimizer". +2. If the user has specified to generate the final executable, then +llvm-ld should run on all the .bc files generated by clang and create a +single optimized .bc file for further tools. +3. -Wo - pass optimizations to the llvm-ld +4. mcc16 -Wl - pass options to native linker. +5. mcc16 -Wa - pass options to native assembler. + +Here are some example command lines and sample command invocations as to +what should be done. + +$ mcc16 -S foo.c +// [clang-cc foo.c] -> foo.bc +// [llvm-ld foo.bc] -> foo.opt.bc +// [llc foo.opt.bc] -> foo.s + +$ mcc16 -S foo.c bar.c +// [clang-cc foo.c] -> foo.bc +// [llvm-ld foo.bc] -> foo.opt.bc +// [llc foo.opt.bc] -> foo.s +// [clang-cc bar.c] -> bar.bc +// [llvm-ld bar.bc] -> bar.opt.bc +// [llc bar.opt.bc] -> bar.s + +** Use of -g causes llvm-ld to run with -disable-opt +$ mcc16 -S -g foo.c +// [clang-cc foo.c] -> foo.bc +// [llvm-ld -disable-opt foo.bc] -> foo.opt.bc +// [llc foo.opt.bc] -> foo.s + +** -I is passed to clang-cc, -pre-RA-sched=list-burr to llc. +$ mcc16 -S -g -I ../include -pre-RA-sched=list-burr foo.c +// [clang-cc -I ../include foo.c] -> foo.bc +// [llvm-ld -disable-opt foo.bc] -> foo.opt.bc +// [llc -pre-RA-sched=list-burr foo.opt.bc] -> foo.s + +** -Wo passes options to llvm-ld +$ mcc16 -Wo=opt1,opt2 -S -I ../include -pre-RA-sched=list-burr foo.c +// [clang-cc -I ../include foo.c] -> foo.bc +// [llvm-ld -opt1 -opt2 foo.bc] -> foo.opt.bc +// [llc -pre-RA-sched=list-burr foo.opt.bc] -> foo.s + +** -Wa passes options to native as. +$ mcc16 -c foo.c -Wa=opt1 +// [clang-cc foo.c] -> foo.bc +// [llvm-ld foo.bc] -> foo.opt.bc +// [llc foo.opt.bc] -> foo.s +// [native-as -opt1 foo.s] -> foo.o + +$ mcc16 -Wo=opt1 -Wl=opt2 -Wa=opt3 foo.c bar.c +// [clang-cc foo.c] -> foo.bc +// [clang-cc bar.c] -> bar.bc +// [llvm-ld -opt1 foo.bc bar.bc] -> a.out.bc +// [llc a.out.bc] -> a.out.s +// [native-as -opt3 a.out.s] -> a.out.o +// [native-ld -opt2 a.out.o] -> a.out + +Is this achievable by a tablegen based driver ? + +- Sanjiv Added: llvm/trunk/tools/llvmc/example/mcc16/driver/Main.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/mcc16/driver/Main.cpp?rev=73013&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/example/mcc16/driver/Main.cpp (added) +++ llvm/trunk/tools/llvmc/example/mcc16/driver/Main.cpp Sun Jun 7 02:08:01 2009 @@ -0,0 +1,14 @@ +//===--- Main.cpp - The LLVM Compiler Driver -------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open +// Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Just include CompilerDriver/Main.inc. +// +//===----------------------------------------------------------------------===// + +#include "llvm/CompilerDriver/Main.inc" Added: llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile?rev=73013&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile (added) +++ llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile Sun Jun 7 02:08:01 2009 @@ -0,0 +1,22 @@ +##===- llvmc/example/mcc16/driver/Makefile -----------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open +# Source License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = $(LLVMC_BASE_LEVEL)/.. + +TOOLNAME = $(LLVMC_BASED_DRIVER_NAME) +LLVMLIBS = CompilerDriver + +ifneq ($(LLVMC_BUILTIN_PLUGINS),) +USEDLIBS += $(patsubst %,plugin_llvmc_%,$(LLVMC_BUILTIN_PLUGINS)) +endif + +LINK_COMPONENTS = support system +REQUIRES_EH := 1 + +include $(LEVEL)/Makefile.common Added: llvm/trunk/tools/llvmc/example/mcc16/plugins/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/mcc16/plugins/Makefile?rev=73013&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/example/mcc16/plugins/Makefile (added) +++ llvm/trunk/tools/llvmc/example/mcc16/plugins/Makefile Sun Jun 7 02:08:01 2009 @@ -0,0 +1,18 @@ +##===- llvmc/example/Skeleton/plugins/Makefile -------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open +# Source License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = $(LLVMC_BASE_LEVEL)/.. + +ifneq ($(LLVMC_BUILTIN_PLUGINS),) +DIRS = $(LLVMC_BUILTIN_PLUGINS) +endif + +export LLVMC_BUILTIN_PLUGIN=1 + +include $(LEVEL)/Makefile.common Added: llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/Makefile?rev=73013&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/Makefile (added) +++ llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/Makefile Sun Jun 7 02:08:01 2009 @@ -0,0 +1,17 @@ +##===- llvmc/example/Skeleton/plugins/Plugin/Makefile ------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = $(LLVMC_BASE_LEVEL)/../.. + +# Change this to the name of your plugin. +LLVMC_PLUGIN = PIC16Base + +BUILT_SOURCES = AutoGenerated.inc + +include $(LEVEL)/Makefile.common Added: llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PIC16Base.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PIC16Base.td?rev=73013&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PIC16Base.td (added) +++ llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PIC16Base.td Sun Jun 7 02:08:01 2009 @@ -0,0 +1,116 @@ +//===- PIC16Base.td - PIC16 toolchain driver ---------------*- tablegen -*-===// +// +// A basic driver for the PIC16 toolchain. +// +//===----------------------------------------------------------------------===// + +include "llvm/CompilerDriver/Common.td" + +// Options + +def OptionList : OptionList<[ + (switch_option "g", + (help "Disable optimizations")), + (switch_option "S", + (help "Stop after compilation, do not assemble")), + (parameter_option "I", + (help "Add a directory to include path")), + (parameter_option "pre-RA-sched", + (help "Example of an option that is passed to llc")), + (prefix_list_option "Wa,", + (help "Pass options to native assembler")), + (prefix_list_option "Wl,", + (help "Pass options to native linker")), + (prefix_list_option "Wllc,", + (help "Pass options to llc")), + (prefix_list_option "Wo,", + (help "Pass options to llvm-ld")) +]>; + +// Tools + +def clang_cc : Tool<[ + (in_language "c"), + (out_language "llvm-bitcode"), + (output_suffix "bc"), + (cmd_line "clang-cc $INFILE -o $OUTFILE"), + (actions (case + (not_empty "I"), (forward "I"))), + (sink) +]>; + +def llvm_ld : Tool<[ + (in_language "llvm-bitcode"), + (out_language "llvm-bitcode"), + (output_suffix "bc"), + (cmd_line "llvm-ld $INFILE -o $OUTFILE"), + (actions (case + (switch_on "g"), (append_cmd "-disable-opt"), + (not_empty "Wo,"), (unpack_values "Wo,"))) +]>; + +def llvm_ld_lto : Tool<[ + (in_language "llvm-bitcode"), + (out_language "llvm-bitcode"), + (output_suffix "bc"), + (cmd_line "llvm-ld $INFILE -o $OUTFILE"), + (actions (case + (switch_on "g"), (append_cmd "-disable-opt"), + (not_empty "Wo,"), (unpack_values "Wo,"))), + (join) +]>; + +def llc : Tool<[ + (in_language "llvm-bitcode"), + (out_language "assembler"), + (output_suffix "s"), + (cmd_line "llc -f $INFILE -o $OUTFILE"), + (actions (case + (switch_on "S"), (stop_compilation), + (not_empty "Wllc,"), (unpack_values "Wllc,"), + (not_empty "pre-RA-sched"), (forward "pre-RA-sched"))) +]>; + +def native_as : Tool<[ + (in_language "assembler"), + (out_language "object-code"), + (output_suffix "o"), + (cmd_line "native-as $INFILE -o $OUTFILE"), + (actions (case + (not_empty "Wa,"), (unpack_values "Wa,"))) +]>; + +def native_ld : Tool<[ + (in_language "object-code"), + (out_language "executable"), + (output_suffix "out"), + (cmd_line "native-ld $INFILE -o $OUTFILE"), + (actions (case + (not_empty "Wl,"), (unpack_values "Wl,"))), + (join) +]>; + +// Language map + +def LanguageMap : LanguageMap<[ + LangToSuffixes<"c", ["c"]>, + LangToSuffixes<"c-cpp-output", ["i"]>, + LangToSuffixes<"assembler", ["s"]>, + LangToSuffixes<"assembler-with-cpp", ["S"]>, + LangToSuffixes<"llvm-assembler", ["ll"]>, + LangToSuffixes<"llvm-bitcode", ["bc"]>, + LangToSuffixes<"object-code", ["o"]>, + LangToSuffixes<"executable", ["out"]> +]>; + +// Compilation graph + +def CompilationGraph : CompilationGraph<[ + Edge<"root", "clang_cc">, + Edge<"clang_cc", "llvm_ld_lto">, + Edge<"llvm_ld_lto", "llc">, + OptionalEdge<"clang_cc", "llvm_ld", (case (switch_on "S"), (inc_weight))>, + Edge<"llvm_ld", "llc">, + Edge<"llc", "native_as">, + Edge<"native_as", "native_ld"> +]>; Added: llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp?rev=73013&view=auto ============================================================================== --- llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp (added) +++ llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp Sun Jun 7 02:08:01 2009 @@ -0,0 +1 @@ +#include "AutoGenerated.inc" From nicholas at mxc.ca Sun Jun 7 02:26:47 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 07 Jun 2009 07:26:47 -0000 Subject: [llvm-commits] [llvm] r73016 - in /llvm/trunk: include/llvm/DerivedTypes.h include/llvm/Type.h lib/AsmParser/LLParser.cpp lib/VMCore/Type.cpp Message-ID: <200906070726.n577QlPO007988@zion.cs.uiuc.edu> Author: nicholas Date: Sun Jun 7 02:26:46 2009 New Revision: 73016 URL: http://llvm.org/viewvc/llvm-project?rev=73016&view=rev Log: Create FunctionType::isValidArgumentType to go along with isValidReturnType. Also create isValidElementType for ArrayType, PointerType, StructType and VectorType. Make LLParser use them. This closes up some holes like an assertion failure on: %x = type {label} but largely doesn't change any semantics. The only thing we accept now which we didn't before is vectors of opaque type such as "<4 x opaque>". The opaque can be resolved to an int or float when linking. Modified: llvm/trunk/include/llvm/DerivedTypes.h llvm/trunk/include/llvm/Type.h llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/VMCore/Type.cpp Modified: llvm/trunk/include/llvm/DerivedTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DerivedTypes.h?rev=73016&r1=73015&r2=73016&view=diff ============================================================================== --- llvm/trunk/include/llvm/DerivedTypes.h (original) +++ llvm/trunk/include/llvm/DerivedTypes.h Sun Jun 7 02:26:46 2009 @@ -159,6 +159,10 @@ /// type. static bool isValidReturnType(const Type *RetTy); + /// isValidArgumentType - Return true if the specified type is valid as an + /// argument type. + static bool isValidArgumentType(const Type *ArgTy); + inline bool isVarArg() const { return isVarArgs; } inline const Type *getReturnType() const { return ContainedTys[0]; } @@ -232,6 +236,10 @@ /// an empty struct, pass NULL, NULL. static StructType *get(const Type *type, ...) END_WITH_NULL; + /// isValidElementType - Return true if the specified type is valid as a + /// element type. + static bool isValidElementType(const Type *ElemTy); + // Iterator access to the elements typedef Type::subtype_iterator element_iterator; element_iterator element_begin() const { return ContainedTys; } @@ -331,6 +339,10 @@ /// static ArrayType *get(const Type *ElementType, uint64_t NumElements); + /// isValidElementType - Return true if the specified type is valid as a + /// element type. + static bool isValidElementType(const Type *ElemTy); + inline uint64_t getNumElements() const { return NumElements; } // Implement the AbstractTypeUser interface. @@ -391,6 +403,10 @@ return VectorType::get(EltTy, VTy->getNumElements()); } + /// isValidElementType - Return true if the specified type is valid as a + /// element type. + static bool isValidElementType(const Type *ElemTy); + /// @brief Return the number of elements in the Vector type. inline unsigned getNumElements() const { return NumElements; } @@ -431,6 +447,10 @@ return PointerType::get(ElementType, 0); } + /// isValidElementType - Return true if the specified type is valid as a + /// element type. + static bool isValidElementType(const Type *ElemTy); + /// @brief Return the address space of the Pointer type. inline unsigned getAddressSpace() const { return AddressSpace; } Modified: llvm/trunk/include/llvm/Type.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=73016&r1=73015&r2=73016&view=diff ============================================================================== --- llvm/trunk/include/llvm/Type.h (original) +++ llvm/trunk/include/llvm/Type.h Sun Jun 7 02:26:46 2009 @@ -205,7 +205,7 @@ inline bool isAbstract() const { return Abstract; } /// canLosslesslyBitCastTo - Return true if this type could be converted - /// with a lossless BitCast to type 'Ty'. For example, uint to int. BitCasts + /// with a lossless BitCast to type 'Ty'. For example, i8* to i32*. BitCasts /// are valid for types of the same size only where no re-interpretation of /// the bits is done. /// @brief Determine if this type could be losslessly bitcast to Ty Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=73016&r1=73015&r2=73016&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Sun Jun 7 02:26:46 2009 @@ -1043,6 +1043,8 @@ return TokError("basic block pointers are invalid"); if (Result.get() == Type::VoidTy) return TokError("pointers to void are invalid; use i8* instead"); + if (!PointerType::isValidElementType(Result.get())) + return TokError("pointer to this type is invalid"); Result = HandleUpRefs(PointerType::getUnqual(Result.get())); Lex.Lex(); break; @@ -1053,6 +1055,8 @@ return TokError("basic block pointers are invalid"); if (Result.get() == Type::VoidTy) return TokError("pointers to void are invalid; use i8* instead"); + if (!PointerType::isValidElementType(Result.get())) + return TokError("pointer to this type is invalid"); unsigned AddrSpace; if (ParseOptionalAddrSpace(AddrSpace) || ParseToken(lltok::star, "expected '*' in address space")) @@ -1149,9 +1153,7 @@ Lex.Lex(); } - if ((!ArgTy->isFirstClassType() && !isa(ArgTy)) || - (isa(ArgTy) && - cast(ArgTy)->getElementType() == Type::MetadataTy)) + if (!FunctionType::isValidArgumentType(ArgTy)) return Error(TypeLoc, "invalid type for function argument"); ArgList.push_back(ArgInfo(TypeLoc, ArgTy, Attrs, Name)); @@ -1247,6 +1249,8 @@ if (Result == Type::VoidTy) return Error(EltTyLoc, "struct element can not have void type"); + if (!StructType::isValidElementType(Result)) + return Error(EltTyLoc, "invalid element type for struct"); while (EatIfPresent(lltok::comma)) { EltTyLoc = Lex.getLoc(); @@ -1254,6 +1258,8 @@ if (Result == Type::VoidTy) return Error(EltTyLoc, "struct element can not have void type"); + if (!StructType::isValidElementType(Result)) + return Error(EltTyLoc, "invalid element type for struct"); ParamsList.push_back(Result); } @@ -1301,11 +1307,11 @@ return Error(SizeLoc, "zero element vector is illegal"); if ((unsigned)Size != Size) return Error(SizeLoc, "size too large for vector"); - if (!EltTy->isFloatingPoint() && !EltTy->isInteger()) + if (!VectorType::isValidElementType(EltTy)) return Error(TypeLoc, "vector element type must be fp or integer"); Result = VectorType::get(EltTy, unsigned(Size)); } else { - if (!EltTy->isFirstClassType() && !isa(EltTy)) + if (!ArrayType::isValidElementType(EltTy)) return Error(TypeLoc, "invalid array element type"); Result = HandleUpRefs(ArrayType::get(EltTy, Size)); } Modified: llvm/trunk/lib/VMCore/Type.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=73016&r1=73015&r2=73016&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Type.cpp (original) +++ llvm/trunk/lib/VMCore/Type.cpp Sun Jun 7 02:26:46 2009 @@ -135,8 +135,8 @@ return cast(this)->getElementType()->isFloatingPoint(); } -// canLosslesllyBitCastTo - Return true if this type can be converted to -// 'Ty' without any reinterpretation of bits. For example, uint to int. +// canLosslesslyBitCastTo - Return true if this type can be converted to +// 'Ty' without any reinterpretation of bits. For example, i8* to i32*. // bool Type::canLosslesslyBitCastTo(const Type *Ty) const { // Identity cast means no change so return true @@ -318,6 +318,17 @@ return true; } +/// isValidArgumentType - Return true if the specified type is valid as an +/// argument type. +bool FunctionType::isValidArgumentType(const Type *ArgTy) { + if ((!ArgTy->isFirstClassType() && !isa(ArgTy)) || + (isa(ArgTy) && + cast(ArgTy)->getElementType() == Type::MetadataTy)) + return false; + + return true; +} + FunctionType::FunctionType(const Type *Result, const std::vector &Params, bool IsVarArgs) @@ -331,11 +342,8 @@ new (&ContainedTys[0]) PATypeHandle(Result, this); for (unsigned i = 0; i != Params.size(); ++i) { - assert((Params[i]->isFirstClassType() || isa(Params[i])) && - "Function arguments must be value types!"); - assert((!isa(Params[i]) || - cast(Params[i])->getElementType() != Type::MetadataTy) - && "Attempt to use metadata* as function argument type!"); + assert(isValidArgumentType(Params[i]) && + "Not a valid type for function argument!"); new (&ContainedTys[i+1]) PATypeHandle(Params[i], this); isAbstract |= Params[i]->isAbstract(); } @@ -352,12 +360,8 @@ bool isAbstract = false; for (unsigned i = 0; i < Types.size(); ++i) { assert(Types[i] && " type for structure field!"); - assert(Types[i] != Type::VoidTy && "Void type for structure field!"); - assert(Types[i] != Type::LabelTy && "Label type for structure field!"); - assert(Types[i] != Type::MetadataTy && "Metadata type for structure field"); - assert((!isa(Types[i]) || - cast(Types[i])->getElementType() != Type::MetadataTy) - && "Type 'metadata*' is invalid for structure field."); + assert(isValidElementType(Types[i]) && + "Invalid type for structure element!"); new (&ContainedTys[i]) PATypeHandle(Types[i], this); isAbstract |= Types[i]->isAbstract(); } @@ -379,8 +383,7 @@ NumElements = NumEl; setAbstract(ElType->isAbstract()); assert(NumEl > 0 && "NumEl of a VectorType must be greater than 0"); - assert((ElType->isInteger() || ElType->isFloatingPoint() || - isa(ElType)) && + assert(isValidElementType(ElType) && "Elements of a VectorType must be a primitive type"); } @@ -1051,12 +1054,7 @@ ArrayType *ArrayType::get(const Type *ElementType, uint64_t NumElements) { assert(ElementType && "Can't get array of types!"); - assert(ElementType != Type::VoidTy && "Array of void is not valid!"); - assert(ElementType != Type::LabelTy && "Array of labels is not valid!"); - assert(ElementType != Type::MetadataTy && "Array of metadata is not valid!"); - assert((!isa(ElementType) || - cast(ElementType)->getElementType() != Type::MetadataTy) - && "Array of metadata* is not valid!"); + assert(isValidElementType(ElementType) && "Invalid type for array element!"); ArrayValType AVT(ElementType, NumElements); ArrayType *AT = ArrayTypes->get(AVT); @@ -1071,6 +1069,18 @@ return AT; } +bool ArrayType::isValidElementType(const Type *ElemTy) { + if (ElemTy == Type::VoidTy || ElemTy == Type::LabelTy || + ElemTy == Type::MetadataTy) + return false; + + if (const PointerType *PTy = dyn_cast(ElemTy)) + if (PTy->getElementType() == Type::MetadataTy) + return false; + + return true; +} + //===----------------------------------------------------------------------===// // Vector Type Factory... @@ -1115,6 +1125,14 @@ return PT; } +bool VectorType::isValidElementType(const Type *ElemTy) { + if (ElemTy->isInteger() || ElemTy->isFloatingPoint() || + isa(ElemTy)) + return true; + + return false; +} + //===----------------------------------------------------------------------===// // Struct Type Factory... // @@ -1181,6 +1199,17 @@ return llvm::StructType::get(StructFields); } +bool StructType::isValidElementType(const Type *ElemTy) { + if (ElemTy == Type::VoidTy || ElemTy == Type::LabelTy || + ElemTy == Type::MetadataTy) + return false; + + if (const PointerType *PTy = dyn_cast(ElemTy)) + if (PTy->getElementType() == Type::MetadataTy) + return false; + + return true; +} //===----------------------------------------------------------------------===// @@ -1217,10 +1246,7 @@ assert(ValueType && "Can't get a pointer to type!"); assert(ValueType != Type::VoidTy && "Pointer to void is not valid, use i8* instead!"); - assert(ValueType != Type::LabelTy && "Pointer to label is not valid!"); - assert((!isa(ValueType) || - cast(ValueType)->getElementType() != Type::MetadataTy) - && "Pointer to metadata* is not valid!"); + assert(isValidElementType(ValueType) && "Invalid type for pointer element!"); PointerValType PVT(ValueType, AddressSpace); PointerType *PT = PointerTypes->get(PVT); @@ -1239,6 +1265,18 @@ return PointerType::get(this, addrs); } +bool PointerType::isValidElementType(const Type *ElemTy) { + if (ElemTy == Type::VoidTy || ElemTy == Type::LabelTy) + return false; + + if (const PointerType *PTy = dyn_cast(ElemTy)) + if (PTy->getElementType() == Type::MetadataTy) + return false; + + return true; +} + + //===----------------------------------------------------------------------===// // Derived Type Refinement Functions //===----------------------------------------------------------------------===// From eli.friedman at gmail.com Sun Jun 7 02:28:45 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Sun, 07 Jun 2009 07:28:45 -0000 Subject: [llvm-commits] [llvm] r73017 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200906070728.n577SjYW008064@zion.cs.uiuc.edu> Author: efriedma Date: Sun Jun 7 02:28:45 2009 New Revision: 73017 URL: http://llvm.org/viewvc/llvm-project?rev=73017&view=rev Log: Get rid of some unnecessary code. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: