From sabre at nondot.org Mon Jun 22 00:51:26 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 22 Jun 2009 05:51:26 -0000 Subject: [llvm-commits] [llvm] r73875 - in /llvm/trunk/tools/llvm-mc: AsmParser.cpp AsmParser.h Message-ID: <200906220551.n5M5pQ1v011482@zion.cs.uiuc.edu> Author: lattner Date: Mon Jun 22 00:51:26 2009 New Revision: 73875 URL: http://llvm.org/viewvc/llvm-project?rev=73875&view=rev Log: implement memory operand parsing. Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp llvm/trunk/tools/llvm-mc/AsmParser.h Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=73875&r1=73874&r2=73875&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Mon Jun 22 00:51:26 2009 @@ -48,10 +48,12 @@ Lexer.Lex(); } + struct AsmParser::X86Operand { enum { Register, - Immediate + Immediate, + Memory } Kind; union { @@ -63,6 +65,14 @@ // FIXME: Should be a general expression. int64_t Val; } Imm; + + struct { + unsigned SegReg; + int64_t Disp; // FIXME: Should be a general expression. + unsigned BaseReg; + unsigned Scale; + unsigned ScaleReg; + } Mem; }; static X86Operand CreateReg(unsigned RegNo) { @@ -77,33 +87,39 @@ Res.Imm.Val = Val; return Res; } + static X86Operand CreateMem(unsigned SegReg, int64_t Disp, unsigned BaseReg, + unsigned Scale, unsigned ScaleReg) { + X86Operand Res; + Res.Kind = Memory; + Res.Mem.SegReg = SegReg; + Res.Mem.Disp = Disp; + Res.Mem.BaseReg = BaseReg; + Res.Mem.Scale = Scale; + Res.Mem.ScaleReg = ScaleReg; + return Res; + } }; bool AsmParser::ParseX86Operand(X86Operand &Op) { switch (Lexer.getKind()) { default: - return TokError("unknown token at start of instruction operand"); + return ParseX86MemOperand(Op); case asmtok::Register: // FIXME: Decode reg #. + // FIXME: if a segment register, this could either be just the seg reg, or + // the start of a memory operand. Op = X86Operand::CreateReg(0); Lexer.Lex(); // Eat register. return false; - case asmtok::Dollar: + case asmtok::Dollar: { // $42 -> immediate. Lexer.Lex(); - // FIXME: Parse an arbitrary expression here, like $(4+5) - if (Lexer.isNot(asmtok::IntVal)) + int64_t Val; + if (ParseExpression(Val)) return TokError("expected integer constant"); - - Op = X86Operand::CreateReg(Lexer.getCurIntVal()); - Lexer.Lex(); // Eat register. - return false; - case asmtok::Identifier: - // This is a label, this should be parsed as part of an expression, to - // handle things like LFOO+4 - Op = X86Operand::CreateImm(0); // FIXME. - Lexer.Lex(); // Eat identifier. + Op = X86Operand::CreateReg(Val); return false; + } //case asmtok::Star: // * %eax @@ -112,7 +128,107 @@ } } +/// ParseX86MemOperand: segment: disp(basereg, indexreg, scale) +bool AsmParser::ParseX86MemOperand(X86Operand &Op) { + // FIXME: If SegReg ':' (e.g. %gs:), eat and remember. + unsigned SegReg = 0; + + + // We have to disambiguate a parenthesized expression "(4+5)" from the start + // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The + // only way to do this without lookahead is to eat the ( and see what is after + // it. + int64_t Disp = 0; + if (Lexer.isNot(asmtok::LParen)) { + if (ParseExpression(Disp)) return true; + + // After parsing the base expression we could either have a parenthesized + // memory address or not. If not, return now. If so, eat the (. + if (Lexer.isNot(asmtok::LParen)) { + Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0); + return false; + } + + // Eat the '('. + Lexer.Lex(); + } else { + // Okay, we have a '('. We don't know if this is an expression or not, but + // so we have to eat the ( to see beyond it. + Lexer.Lex(); // Eat the '('. + + if (Lexer.is(asmtok::Register) || Lexer.is(asmtok::Comma)) { + // Nothing to do here, fall into the code below with the '(' part of the + // memory operand consumed. + } else { + // FIXME: Call ParseParenExpression with the leading ( consumed. + return TokError("FIXME: Paren expr not implemented yet!"); + } + } + + // If we reached here, then we just ate the ( of the memory operand. Process + // the rest of the memory operand. + unsigned BaseReg = 0, ScaleReg = 0, Scale = 0; + + if (Lexer.is(asmtok::Register)) { + BaseReg = 123; // FIXME: decode reg # + Lexer.Lex(); // eat the register. + } + + if (Lexer.is(asmtok::Comma)) { + Lexer.Lex(); // eat the comma. + + if (Lexer.is(asmtok::Register)) { + ScaleReg = 123; // FIXME: decode reg # + Lexer.Lex(); // eat the register. + Scale = 1; // If not specified, the scale defaults to 1. + } + + if (Lexer.is(asmtok::Comma)) { + Lexer.Lex(); // eat the comma. + + // If present, get and validate scale amount. + if (Lexer.is(asmtok::IntVal)) { + int64_t ScaleVal = Lexer.getCurIntVal(); + if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8) + return TokError("scale factor in address must be 1, 2, 4 or 8"); + Lexer.Lex(); // eat the scale. + Scale = (unsigned)ScaleVal; + } + } + } + + // Ok, we've eaten the memory operand, verify we have a ')' and eat it too. + if (Lexer.isNot(asmtok::RParen)) + return TokError("unexpected token in memory operand"); + Lexer.Lex(); // Eat the ')'. + + Op = X86Operand::CreateMem(SegReg, Disp, BaseReg, Scale, ScaleReg); + return false; +} + +/// ParseExpression - Parse an expression and return it. +/// FIXME: This should handle real expressions, we do something trivial for now. +bool AsmParser::ParseExpression(int64_t &Res) { + switch (Lexer.getKind()) { + default: + return TokError("unknown token in expression"); + case asmtok::Identifier: + // This is a label, this should be parsed as part of an expression, to + // handle things like LFOO+4 + Res = 0; // FIXME. + Lexer.Lex(); // Eat identifier. + return false; + case asmtok::IntVal: + Res = Lexer.getCurIntVal(); + Lexer.Lex(); // Eat identifier. + return false; + } +} + + + + /// ParseStatement: /// ::= EndOfStatement /// ::= Label* Directive ...Operands... EndOfStatement Modified: llvm/trunk/tools/llvm-mc/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.h?rev=73875&r1=73874&r2=73875&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.h (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.h Mon Jun 22 00:51:26 2009 @@ -37,6 +37,8 @@ void EatToEndOfStatement(); bool ParseX86Operand(X86Operand &Op); + bool ParseX86MemOperand(X86Operand &Op); + bool ParseExpression(int64_t &Res); }; } // end namespace llvm From sabre at nondot.org Mon Jun 22 01:02:13 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 22 Jun 2009 06:02:13 -0000 Subject: [llvm-commits] [llvm] r73876 - /llvm/trunk/tools/llvm-mc/AsmParser.cpp Message-ID: <200906220602.n5M62D1D011772@zion.cs.uiuc.edu> Author: lattner Date: Mon Jun 22 01:02:13 2009 New Revision: 73876 URL: http://llvm.org/viewvc/llvm-project?rev=73876&view=rev Log: implement parser support for '*' operands, as in "call *%eax". Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=73876&r1=73875&r2=73876&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Mon Jun 22 01:02:13 2009 @@ -108,7 +108,7 @@ // FIXME: Decode reg #. // FIXME: if a segment register, this could either be just the seg reg, or // the start of a memory operand. - Op = X86Operand::CreateReg(0); + Op = X86Operand::CreateReg(123); Lexer.Lex(); // Eat register. return false; case asmtok::Dollar: { @@ -119,12 +119,19 @@ return TokError("expected integer constant"); Op = X86Operand::CreateReg(Val); return false; + case asmtok::Star: + Lexer.Lex(); // Eat the star. + + if (Lexer.is(asmtok::Register)) { + Op = X86Operand::CreateReg(123); + Lexer.Lex(); // Eat register. + } else if (ParseX86MemOperand(Op)) + return true; + + // FIXME: Note that these are 'dereferenced' so that clients know the '*' is + // there. + return false; } - - //case asmtok::Star: - // * %eax - // * - // Note that these are both "dereferenced". } } From sabre at nondot.org Mon Jun 22 01:32:03 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 22 Jun 2009 06:32:03 -0000 Subject: [llvm-commits] [llvm] r73877 - in /llvm/trunk/tools/llvm-mc: AsmLexer.cpp AsmLexer.h AsmParser.cpp AsmParser.h llvm-mc.cpp Message-ID: <200906220632.n5M6W3LC012581@zion.cs.uiuc.edu> Author: lattner Date: Mon Jun 22 01:32:03 2009 New Revision: 73877 URL: http://llvm.org/viewvc/llvm-project?rev=73877&view=rev Log: Implement full support for parsing primary expressions. We can now parse all of health and voronoi (ignoring directives). We only get 409 lines into 176.gcc though because we don't have binary operators yet: Parsing 176.gcc.llc.s:409: unexpected token in operand list movsbl _arityvec+1(,%edi,8), %eax ^ Modified: llvm/trunk/tools/llvm-mc/AsmLexer.cpp llvm/trunk/tools/llvm-mc/AsmLexer.h llvm/trunk/tools/llvm-mc/AsmParser.cpp llvm/trunk/tools/llvm-mc/AsmParser.h llvm/trunk/tools/llvm-mc/llvm-mc.cpp Modified: llvm/trunk/tools/llvm-mc/AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmLexer.cpp?rev=73877&r1=73876&r2=73877&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmLexer.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmLexer.cpp Mon Jun 22 01:32:03 2009 @@ -235,6 +235,7 @@ case ':': return asmtok::Colon; case '+': return asmtok::Plus; case '-': return asmtok::Minus; + case '~': return asmtok::Tilde; case '(': return asmtok::LParen; case ')': return asmtok::RParen; case '*': return asmtok::Star; Modified: llvm/trunk/tools/llvm-mc/AsmLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmLexer.h?rev=73877&r1=73876&r2=73877&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmLexer.h (original) +++ llvm/trunk/tools/llvm-mc/AsmLexer.h Mon Jun 22 01:32:03 2009 @@ -39,8 +39,7 @@ // No-value. EndOfStatement, Colon, - Plus, - Minus, + Plus, Minus, Tilde, Slash, // '/' LParen, RParen, Star, Comma, Dollar Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=73877&r1=73876&r2=73877&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Mon Jun 22 01:32:03 2009 @@ -213,10 +213,25 @@ return false; } +/// ParseParenExpr - Parse a paren expression and return it. +/// NOTE: This assumes the leading '(' has already been consumed. +/// +/// parenexpr ::= expr) +/// +bool AsmParser::ParseParenExpr(int64_t &Res) { + if (ParseExpression(Res)) return true; + if (Lexer.isNot(asmtok::RParen)) + return TokError("expected ')' in parentheses expression"); + Lexer.Lex(); + return false; +} -/// ParseExpression - Parse an expression and return it. -/// FIXME: This should handle real expressions, we do something trivial for now. -bool AsmParser::ParseExpression(int64_t &Res) { +/// ParsePrimaryExpr - Parse a primary expression and return it. +/// primaryexpr ::= (parenexpr +/// primaryexpr ::= symbol +/// primaryexpr ::= number +/// primaryexpr ::= ~,+,- primaryexpr +bool AsmParser::ParsePrimaryExpr(int64_t &Res) { switch (Lexer.getKind()) { default: return TokError("unknown token in expression"); @@ -230,8 +245,27 @@ Res = Lexer.getCurIntVal(); Lexer.Lex(); // Eat identifier. return false; + case asmtok::LParen: + Lexer.Lex(); // Eat the '('. + return ParseParenExpr(Res); + case asmtok::Tilde: + case asmtok::Plus: + case asmtok::Minus: + Lexer.Lex(); // Eat the operator. + return ParsePrimaryExpr(Res); } } + +/// ParseExpression - Parse an expression and return it. +/// +/// expr ::= expr +,- expr -> lowest. +/// expr ::= expr |,^,&,! expr -> middle. +/// expr ::= expr *,/,%,<<,>> expr -> highest. +/// expr ::= primaryexpr +/// +bool AsmParser::ParseExpression(int64_t &Res) { + return ParsePrimaryExpr(Res); +} Modified: llvm/trunk/tools/llvm-mc/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.h?rev=73877&r1=73876&r2=73877&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.h (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.h Mon Jun 22 01:32:03 2009 @@ -39,6 +39,8 @@ bool ParseX86Operand(X86Operand &Op); bool ParseX86MemOperand(X86Operand &Op); bool ParseExpression(int64_t &Res); + bool ParsePrimaryExpr(int64_t &Res); + bool ParseParenExpr(int64_t &Res); }; } // end namespace llvm Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=73877&r1=73876&r2=73877&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Mon Jun 22 01:32:03 2009 @@ -99,6 +99,7 @@ case asmtok::Colon: outs() << "Colon\n"; break; case asmtok::Plus: outs() << "Plus\n"; break; case asmtok::Minus: outs() << "Minus\n"; break; + case asmtok::Tilde: outs() << "Tilde\n"; break; case asmtok::Slash: outs() << "Slash\n"; break; case asmtok::LParen: outs() << "LParen\n"; break; case asmtok::RParen: outs() << "RParen\n"; break; From sabre at nondot.org Mon Jun 22 01:35:59 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 22 Jun 2009 06:35:59 -0000 Subject: [llvm-commits] [llvm] r73878 - /llvm/trunk/tools/llvm-mc/AsmParser.cpp Message-ID: <200906220635.n5M6ZxLW012691@zion.cs.uiuc.edu> Author: lattner Date: Mon Jun 22 01:35:58 2009 New Revision: 73878 URL: http://llvm.org/viewvc/llvm-project?rev=73878&view=rev Log: process memory operands with a parenthesized expression for a displacement, like "(4+5)(%eax)". Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=73878&r1=73877&r2=73878&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Mon Jun 22 01:35:58 2009 @@ -167,8 +167,18 @@ // Nothing to do here, fall into the code below with the '(' part of the // memory operand consumed. } else { - // FIXME: Call ParseParenExpression with the leading ( consumed. - return TokError("FIXME: Paren expr not implemented yet!"); + // It must be an parenthesized expression, parse it now. + if (ParseParenExpr(Disp)) return true; + + // After parsing the base expression we could either have a parenthesized + // memory address or not. If not, return now. If so, eat the (. + if (Lexer.isNot(asmtok::LParen)) { + Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0); + return false; + } + + // Eat the '('. + Lexer.Lex(); } } From howard0su at gmail.com Mon Jun 22 01:40:38 2009 From: howard0su at gmail.com (Howard Su) Date: Mon, 22 Jun 2009 14:40:38 +0800 Subject: [llvm-commits] [llvm] r73855 - in /llvm/trunk/tools/llvm-mc: AsmLexer.cpp AsmLexer.h llvm-mc.cpp In-Reply-To: References: <200906211921.n5LJLQtY025612@zion.cs.uiuc.edu> Message-ID: the magic is that TGLexer include config.h. there is a definition:/* Define to a function implementing strtoull */ #define strtoull _strtoui64 On Mon, Jun 22, 2009 at 12:57 PM, Chris Lattner wrote: > > On Jun 21, 2009, at 8:33 PM, Howard Su wrote: > > no strtoll in windows + VC. > D:\llvm-ng\tools\llvm-mc\AsmLexer.cpp(143) : error C3861: 'strtoll': > identifier not found > D:\llvm-ng\tools\llvm-mc\AsmLexer.cpp(156) : error C3861: 'strtoll': > identifier not found > D:\llvm-ng\tools\llvm-mc\AsmLexer.cpp(171) : error C3861: 'strtoll': > identifier not found > D:\llvm-ng\tools\llvm-mc\AsmLexer.cpp(176) : error C3861: 'strtoull': > identifier not found > D:\llvm-ng\tools\llvm-mc\AsmLexer.cpp(188) : error C3861: 'strtoll': > identifier not found > > > Did my subsequent #include of fix this? If not, > llvm/utils/TableGen/TGLexer.cpp uses strtoull, do you know what magic does > it? > > -Chris > > > On Mon, Jun 22, 2009 at 3:21 AM, Chris Lattner wrote: > >> Author: lattner >> Date: Sun Jun 21 14:21:25 2009 >> New Revision: 73855 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=73855&view=rev >> Log: >> implement enough of a lexer to get through >> Olden/health/Output/health.llc.s >> without errors. >> >> >> Modified: >> llvm/trunk/tools/llvm-mc/AsmLexer.cpp >> llvm/trunk/tools/llvm-mc/AsmLexer.h >> llvm/trunk/tools/llvm-mc/llvm-mc.cpp >> >> Modified: llvm/trunk/tools/llvm-mc/AsmLexer.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmLexer.cpp?rev=73855&r1=73854&r2=73855&view=diff >> >> >> ============================================================================== >> --- llvm/trunk/tools/llvm-mc/AsmLexer.cpp (original) >> +++ llvm/trunk/tools/llvm-mc/AsmLexer.cpp Sun Jun 21 14:21:25 2009 >> @@ -14,6 +14,7 @@ >> #include "AsmLexer.h" >> #include "llvm/Support/SourceMgr.h" >> #include "llvm/Support/MemoryBuffer.h" >> +#include >> using namespace llvm; >> >> AsmLexer::AsmLexer(SourceMgr &SM) : SrcMgr(SM) { >> @@ -23,6 +24,10 @@ >> TokStart = 0; >> } >> >> +SMLoc AsmLexer::getLoc() const { >> + return SMLoc::getFromPointer(TokStart); >> +} >> + >> void AsmLexer::PrintError(const char *Loc, const std::string &Msg) const >> { >> SrcMgr.PrintError(SMLoc::getFromPointer(Loc), Msg); >> } >> @@ -31,6 +36,13 @@ >> SrcMgr.PrintError(Loc, Msg); >> } >> >> +/// ReturnError - Set the error to the specified string at the specified >> +/// location. This is defined to always return asmtok::Error. >> +asmtok::TokKind AsmLexer::ReturnError(const char *Loc, const std::string >> &Msg) { >> + PrintError(Loc, Msg); >> + return asmtok::Error; >> +} >> + >> int AsmLexer::getNextChar() { >> char CurChar = *CurPtr++; >> switch (CurChar) { >> @@ -59,6 +71,129 @@ >> } >> } >> >> +/// LexIdentifier: [a-zA-Z_.][a-zA-Z0-9_$.@]* >> +asmtok::TokKind AsmLexer::LexIdentifier() { >> + while (isalnum(*CurPtr) || *CurPtr == '_' || *CurPtr == '$' || >> + *CurPtr == '.' || *CurPtr == '@') >> + ++CurPtr; >> + CurStrVal.assign(TokStart, CurPtr); // Skip % >> + return asmtok::Identifier; >> +} >> + >> +/// LexPercent: Register: %[a-zA-Z0-9]+ >> +asmtok::TokKind AsmLexer::LexPercent() { >> + if (!isalnum(*CurPtr)) >> + return asmtok::Error; // Must have at least one character. >> + while (isalnum(*CurPtr)) >> + ++CurPtr; >> + CurStrVal.assign(TokStart, CurPtr); // Skip % >> + return asmtok::Register; >> +} >> + >> +/// LexSlash: Slash: / >> +/// C-Style Comment: /* ... */ >> +asmtok::TokKind AsmLexer::LexSlash() { >> + if (*CurPtr != '*') >> + return asmtok::Slash; >> + >> + // C Style comment. >> + ++CurPtr; // skip the star. >> + while (1) { >> + int CurChar = getNextChar(); >> + switch (CurChar) { >> + case EOF: >> + PrintError(TokStart, "Unterminated comment!"); >> + return asmtok::Error; >> + case '*': >> + // End of the comment? >> + if (CurPtr[0] != '/') break; >> + >> + ++CurPtr; // End the */. >> + return LexToken(); >> + } >> + } >> +} >> + >> +/// LexHash: Comment: #[^\n]* >> +asmtok::TokKind AsmLexer::LexHash() { >> + int CurChar = getNextChar(); >> + while (CurChar != '\n' && CurChar != '\n' && CurChar != EOF) >> + CurChar = getNextChar(); >> + >> + if (CurChar == EOF) >> + return asmtok::Eof; >> + return asmtok::EndOfStatement; >> +} >> + >> + >> +/// LexDigit: First character is [0-9]. >> +/// Local Label: [0-9][:] >> +/// Forward/Backward Label: [0-9][fb] >> +/// Binary integer: 0b[01]+ >> +/// Octal integer: 0[0-7]+ >> +/// Hex integer: 0x[0-9a-fA-F]+ >> +/// Decimal integer: [1-9][0-9]* >> +/// TODO: FP literal. >> +asmtok::TokKind AsmLexer::LexDigit() { >> + if (*CurPtr == ':') >> + return asmtok::Error; // FIXME LOCAL LABEL. >> + if (*CurPtr == 'f' || *CurPtr == 'b') >> + return asmtok::Error; // FIXME FORWARD/BACKWARD LABEL. >> + >> + // Decimal integer: [1-9][0-9]* >> + if (CurPtr[-1] != '0') { >> + while (isdigit(*CurPtr)) >> + ++CurPtr; >> + CurIntVal = strtoll(TokStart, 0, 10); >> + return asmtok::IntVal; >> + } >> + >> + if (*CurPtr == 'b') { >> + ++CurPtr; >> + const char *NumStart = CurPtr; >> + while (CurPtr[0] == '0' || CurPtr[0] == '1') >> + ++CurPtr; >> + >> + // Requires at least one binary digit. >> + if (CurPtr == NumStart) >> + return ReturnError(CurPtr-2, "Invalid binary number"); >> + CurIntVal = strtoll(NumStart, 0, 2); >> + return asmtok::IntVal; >> + } >> + >> + if (*CurPtr == 'x') { >> + ++CurPtr; >> + const char *NumStart = CurPtr; >> + while (isxdigit(CurPtr[0])) >> + ++CurPtr; >> + >> + // Requires at least one hex digit. >> + if (CurPtr == NumStart) >> + return ReturnError(CurPtr-2, "Invalid hexadecimal number"); >> + >> + errno = 0; >> + CurIntVal = strtoll(NumStart, 0, 16); >> + if (errno == EINVAL) >> + return ReturnError(CurPtr-2, "Invalid hexadecimal number"); >> + if (errno == ERANGE) { >> + errno = 0; >> + CurIntVal = (int64_t)strtoull(NumStart, 0, 16); >> + if (errno == EINVAL) >> + return ReturnError(CurPtr-2, "Invalid hexadecimal number"); >> + if (errno == ERANGE) >> + return ReturnError(CurPtr-2, "Hexadecimal number out of range"); >> + } >> + return asmtok::IntVal; >> + } >> + >> + // Must be an octal number, it starts with 0. >> + while (*CurPtr >= '0' && *CurPtr <= '7') >> + ++CurPtr; >> + CurIntVal = strtoll(TokStart, 0, 8); >> + return asmtok::IntVal; >> +} >> + >> + >> asmtok::TokKind AsmLexer::LexToken() { >> TokStart = CurPtr; >> // This always consumes at least one character. >> @@ -66,9 +201,9 @@ >> >> switch (CurChar) { >> default: >> - // Handle letters: [a-zA-Z_] >> -// if (isalpha(CurChar) || CurChar == '_' || CurChar == '#') >> -// return LexIdentifier(); >> + // Handle identifier: [a-zA-Z_.][a-zA-Z0-9_$.@]* >> + if (isalpha(CurChar) || CurChar == '_' || CurChar == '.') >> + return LexIdentifier(); >> >> // Unknown character, emit an error. >> return asmtok::Error; >> @@ -76,12 +211,29 @@ >> case 0: >> case ' ': >> case '\t': >> - case '\n': >> - case '\r': >> // Ignore whitespace. >> return LexToken(); >> + case '\n': // FALL THROUGH. >> + case '\r': // FALL THROUGH. >> + case ';': return asmtok::EndOfStatement; >> case ':': return asmtok::Colon; >> case '+': return asmtok::Plus; >> case '-': return asmtok::Minus; >> + case '(': return asmtok::LParen; >> + case ')': return asmtok::RParen; >> + case '*': return asmtok::Star; >> + case ',': return asmtok::Comma; >> + case '$': return asmtok::Dollar; >> + case '%': return LexPercent(); >> + case '/': return LexSlash(); >> + case '#': return LexHash(); >> + case '0': case '1': case '2': case '3': case '4': >> + case '5': case '6': case '7': case '8': case '9': >> + return LexDigit(); >> + >> + // TODO: Quoted identifiers (objc methods etc) >> + // local labels: [0-9][:] >> + // Forward/backward labels: [0-9][fb] >> + // Integers, fp constants, character constants. >> } >> } >> \ No newline at end of file >> >> Modified: llvm/trunk/tools/llvm-mc/AsmLexer.h >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmLexer.h?rev=73855&r1=73854&r2=73855&view=diff >> >> >> ============================================================================== >> --- llvm/trunk/tools/llvm-mc/AsmLexer.h (original) >> +++ llvm/trunk/tools/llvm-mc/AsmLexer.h Sun Jun 21 14:21:25 2009 >> @@ -29,12 +29,16 @@ >> Eof, Error, >> >> Identifier, >> + Register, >> IntVal, >> >> - >> + EndOfStatement, >> Colon, >> Plus, >> - Minus >> + Minus, >> + Slash, // '/' >> + LParen, RParen, >> + Star, Comma, Dollar >> }; >> } >> >> @@ -66,7 +70,7 @@ >> asmtok::TokKind getKind() const { return CurKind; } >> >> const std::string &getCurStrVal() const { >> - assert(CurKind == asmtok::Identifier && >> + assert((CurKind == asmtok::Identifier || CurKind == asmtok::Register) >> && >> "This token doesn't have a string value"); >> return CurStrVal; >> } >> @@ -82,9 +86,15 @@ >> >> private: >> int getNextChar(); >> + asmtok::TokKind ReturnError(const char *Loc, const std::string &Msg); >> >> /// LexToken - Read the next token and return its code. >> asmtok::TokKind LexToken(); >> + asmtok::TokKind LexIdentifier(); >> + asmtok::TokKind LexPercent(); >> + asmtok::TokKind LexSlash(); >> + asmtok::TokKind LexHash(); >> + asmtok::TokKind LexDigit(); >> }; >> >> } // end namespace llvm >> >> Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=73855&r1=73854&r2=73855&view=diff >> >> >> ============================================================================== >> --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) >> +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Sun Jun 21 14:21:25 2009 >> @@ -72,17 +72,29 @@ >> asmtok::TokKind Tok = Lexer.Lex(); >> while (Tok != asmtok::Eof) { >> switch (Tok) { >> - default: outs() << "<>\n"; break; >> - case asmtok::Error: outs() << "<>\n"; break; >> + default: Lexer.PrintError(Lexer.getLoc(), "driver: unknown token"); >> break; >> + case asmtok::Error: >> + Lexer.PrintError(Lexer.getLoc(), "error, bad token"); >> + break; >> case asmtok::Identifier: >> outs() << "identifier: " << Lexer.getCurStrVal() << '\n'; >> break; >> + case asmtok::Register: >> + outs() << "register: " << Lexer.getCurStrVal() << '\n'; >> + break; >> case asmtok::IntVal: >> outs() << "int: " << Lexer.getCurIntVal() << '\n'; >> break; >> + case asmtok::EndOfStatement: outs() << "EndOfStatement\n"; break; >> case asmtok::Colon: outs() << "Colon\n"; break; >> case asmtok::Plus: outs() << "Plus\n"; break; >> case asmtok::Minus: outs() << "Minus\n"; break; >> + case asmtok::Slash: outs() << "Slash\n"; break; >> + case asmtok::LParen: outs() << "LParen\n"; break; >> + case asmtok::RParen: outs() << "RParen\n"; break; >> + case asmtok::Star: outs() << "Star\n"; break; >> + case asmtok::Comma: outs() << "Comma\n"; break; >> + case asmtok::Dollar: outs() << "Dollar\n"; break; >> } >> >> Tok = Lexer.Lex(); >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > > > -- > -Howard > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > -- -Howard -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090622/84876bd0/attachment.html From baldrick at free.fr Mon Jun 22 01:59:32 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 22 Jun 2009 06:59:32 -0000 Subject: [llvm-commits] [llvm] r73879 - /llvm/trunk/tools/llvm-mc/AsmLexer.cpp Message-ID: <200906220659.n5M6xW9B013342@zion.cs.uiuc.edu> Author: baldrick Date: Mon Jun 22 01:59:32 2009 New Revision: 73879 URL: http://llvm.org/viewvc/llvm-project?rev=73879&view=rev Log: Include cstdio to get EOF, needed with gcc-4.4. Modified: llvm/trunk/tools/llvm-mc/AsmLexer.cpp Modified: llvm/trunk/tools/llvm-mc/AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmLexer.cpp?rev=73879&r1=73878&r2=73879&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmLexer.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmLexer.cpp Mon Jun 22 01:59:32 2009 @@ -15,6 +15,7 @@ #include "llvm/Support/SourceMgr.h" #include "llvm/Support/MemoryBuffer.h" #include +#include #include using namespace llvm; @@ -254,4 +255,4 @@ // Forward/backward labels: [0-9][fb] // Integers, fp constants, character constants. } -} \ No newline at end of file +} From baldrick at free.fr Mon Jun 22 02:54:01 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 22 Jun 2009 09:54:01 +0200 Subject: [llvm-commits] [llvm] r73866 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/trip-count5.ll In-Reply-To: <200906220032.n5M0W3ic002321@zion.cs.uiuc.edu> References: <200906220032.n5M0W3ic002321@zion.cs.uiuc.edu> Message-ID: <4A3F3899.3030808@free.fr> Hi Dan, > Teach ScalarEvolution how to analyze loops with multiple exit > blocks, and also exit blocks with multiple conditions (combined > with (bitwise) ands and ors). It's often infeasible to compute an > exact trip count in such cases, but a useful upper bound can often > be found. thanks for doing this. Does the loop unroller make any use of it? The loop in PR2624 is still not unrolled for example. > + // We couldn't compute an exact value for this exit, so > + // we don't be able to compute an exact value for the loop. we don't -> we won't This occurs again later. Ciao, Duncan. From gohman at apple.com Mon Jun 22 10:03:32 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 22 Jun 2009 15:03:32 -0000 Subject: [llvm-commits] [llvm] r73883 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp Message-ID: <200906221503.n5MF3aW8007852@zion.cs.uiuc.edu> Author: djg Date: Mon Jun 22 10:03:27 2009 New Revision: 73883 URL: http://llvm.org/viewvc/llvm-project?rev=73883&view=rev Log: Add a getUMinFromMismatchedTypes helper function. Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=73883&r1=73882&r2=73883&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Mon Jun 22 10:03:27 2009 @@ -553,6 +553,12 @@ SCEVHandle getUMaxFromMismatchedTypes(const SCEVHandle &LHS, const SCEVHandle &RHS); + /// getUMinFromMismatchedTypes - Promote the operands to the wider of + /// the types using zero-extension, and then perform a umin operation + /// with them. + SCEVHandle getUMinFromMismatchedTypes(const SCEVHandle &LHS, + const SCEVHandle &RHS); + /// hasSCEV - Return true if the SCEV for this value has already been /// computed. bool hasSCEV(Value *V) const; Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=73883&r1=73882&r2=73883&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Jun 22 10:03:27 2009 @@ -2156,6 +2156,22 @@ return getUMaxExpr(PromotedLHS, PromotedRHS); } +/// getUMinFromMismatchedTypes - Promote the operands to the wider of +/// the types using zero-extension, and then perform a umin operation +/// with them. +SCEVHandle ScalarEvolution::getUMinFromMismatchedTypes(const SCEVHandle &LHS, + const SCEVHandle &RHS) { + SCEVHandle PromotedLHS = LHS; + SCEVHandle PromotedRHS = RHS; + + if (getTypeSizeInBits(LHS->getType()) > getTypeSizeInBits(RHS->getType())) + PromotedRHS = getZeroExtendExpr(RHS, LHS->getType()); + else + PromotedLHS = getNoopOrZeroExtend(LHS, RHS->getType()); + + return getUMinExpr(PromotedLHS, PromotedRHS); +} + /// ReplaceSymbolicValueWithConcrete - This looks up the computed SCEV value for /// the specified instruction and replaces any references to the symbolic value /// SymName with the specified value. This is used during PHI resolution. From gohman at apple.com Mon Jun 22 10:09:28 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 22 Jun 2009 15:09:28 -0000 Subject: [llvm-commits] [llvm] r73884 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <200906221509.n5MF9TjU008035@zion.cs.uiuc.edu> Author: djg Date: Mon Jun 22 10:09:28 2009 New Revision: 73884 URL: http://llvm.org/viewvc/llvm-project?rev=73884&view=rev Log: Make use of getUMinFromMismatchedTypes when computing backedge-taken counts for loops with multiple exits, replacing more conservative code which only handled constants. This is derived from a patch by Nick Lewycky. This also fixes llc aborts in ClamAV and others, as getUMinFromMismatchedTypes takes care of balancing the types before working with them. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=73884&r1=73883&r2=73884&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Jun 22 10:09:28 2009 @@ -2958,18 +2958,18 @@ if (L->contains(TBB)) { // Both conditions must be true for the loop to continue executing. // Choose the less conservative count. - // TODO: Take the minimum of the exact counts. - if (BTI0.Exact == BTI1.Exact) + if (BTI0.Exact == CouldNotCompute) + BECount = BTI1.Exact; + else if (BTI1.Exact == CouldNotCompute) BECount = BTI0.Exact; - // TODO: Take the minimum of the maximum counts. + else + BECount = getUMinFromMismatchedTypes(BTI0.Exact, BTI1.Exact); if (BTI0.Max == CouldNotCompute) MaxBECount = BTI1.Max; else if (BTI1.Max == CouldNotCompute) MaxBECount = BTI0.Max; - else if (const SCEVConstant *C0 = dyn_cast(BTI0.Max)) - if (const SCEVConstant *C1 = dyn_cast(BTI1.Max)) - MaxBECount = getConstant(APIntOps::umin(C0->getValue()->getValue(), - C1->getValue()->getValue())); + else + MaxBECount = getUMinFromMismatchedTypes(BTI0.Max, BTI1.Max); } else { // Both conditions must be true for the loop to exit. assert(L->contains(FBB) && "Loop block has no successor in loop!"); @@ -2992,18 +2992,18 @@ if (L->contains(FBB)) { // Both conditions must be false for the loop to continue executing. // Choose the less conservative count. - // TODO: Take the minimum of the exact counts. - if (BTI0.Exact == BTI1.Exact) + if (BTI0.Exact == CouldNotCompute) + BECount = BTI1.Exact; + else if (BTI1.Exact == CouldNotCompute) BECount = BTI0.Exact; - // TODO: Take the minimum of the maximum counts. + else + BECount = getUMinFromMismatchedTypes(BTI0.Exact, BTI1.Exact); if (BTI0.Max == CouldNotCompute) MaxBECount = BTI1.Max; else if (BTI1.Max == CouldNotCompute) MaxBECount = BTI0.Max; - else if (const SCEVConstant *C0 = dyn_cast(BTI0.Max)) - if (const SCEVConstant *C1 = dyn_cast(BTI1.Max)) - MaxBECount = getConstant(APIntOps::umin(C0->getValue()->getValue(), - C1->getValue()->getValue())); + else + MaxBECount = getUMinFromMismatchedTypes(BTI0.Max, BTI1.Max); } else { // Both conditions must be false for the loop to exit. assert(L->contains(TBB) && "Loop block has no successor in loop!"); From bob.wilson at apple.com Mon Jun 22 12:29:28 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 22 Jun 2009 17:29:28 -0000 Subject: [llvm-commits] [llvm] r73887 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Message-ID: <200906221729.n5MHTYc0025261@zion.cs.uiuc.edu> Author: bwilson Date: Mon Jun 22 12:29:13 2009 New Revision: 73887 URL: http://llvm.org/viewvc/llvm-project?rev=73887&view=rev Log: Fix llvm-gcc build for armv6t2 and later architectures. The hasV6T2Ops predicate does not check if Thumb mode is enabled, and when in ARM mode there are still some checks for constant-pool use that need to run. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=73887&r1=73886&r2=73887&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Jun 22 12:29:13 2009 @@ -579,17 +579,18 @@ switch (N->getOpcode()) { default: break; case ISD::Constant: { - // ARMv6T2 and later should materialize imms via MOV / MOVT pair. - if (Subtarget->hasV6T2Ops() || Subtarget->hasThumb2()) - break; - unsigned Val = cast(N)->getZExtValue(); bool UseCP = true; - if (Subtarget->isThumb()) - UseCP = (Val > 255 && // MOV - ~Val > 255 && // MOV + MVN - !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL - else + if (Subtarget->isThumb()) { + if (Subtarget->hasThumb2()) + // Thumb2 has the MOVT instruction, so all immediates can + // be done with MOV + MOVT, at worst. + UseCP = 0; + else + UseCP = (Val > 255 && // MOV + ~Val > 255 && // MOV + MVN + !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL + } else UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV ARM_AM::getSOImmVal(~Val) == -1 && // MVN !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs. From bob.wilson at apple.com Mon Jun 22 13:01:44 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 22 Jun 2009 18:01:44 -0000 Subject: [llvm-commits] [llvm] r73889 - /llvm/trunk/tools/lto/LTOCodeGenerator.cpp Message-ID: <200906221801.n5MI1kZh026424@zion.cs.uiuc.edu> Author: bwilson Date: Mon Jun 22 13:01:28 2009 New Revision: 73889 URL: http://llvm.org/viewvc/llvm-project?rev=73889&view=rev Log: Recognize and handle ARM v7 target triples for Darwin. Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=73889&r1=73888&r2=73889&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Mon Jun 22 13:01:28 2009 @@ -290,6 +290,11 @@ args.push_back("-arch"); args.push_back("armv6"); } + else if ((strncmp(targetTriple.c_str(), "armv7-apple-", 12) == 0) || + (strncmp(targetTriple.c_str(), "thumbv7-apple-", 14) == 0)) { + args.push_back("-arch"); + args.push_back("armv7"); + } // add -static to assembler command line when code model requires if ( (_assemblerPath != NULL) && (_codeModel == LTO_CODEGEN_PIC_MODEL_STATIC) ) args.push_back("-static"); From dalej at apple.com Mon Jun 22 13:05:17 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 22 Jun 2009 18:05:17 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r73890 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200906221805.n5MI5IY6026619@zion.cs.uiuc.edu> Author: johannes Date: Mon Jun 22 13:05:17 2009 New Revision: 73890 URL: http://llvm.org/viewvc/llvm-project?rev=73890&view=rev Log: Resurrect arithmetic on integer complex types. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=73890&r1=73889&r2=73890&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Jun 22 13:05:17 2009 @@ -5774,7 +5774,7 @@ EmitStoreToComplex(*DestLoc, Real, Imag); } -// EmitComplexBinOp - Note that this operands on binops like ==/!=, which return +// EmitComplexBinOp - Note that this operates on binops like ==/!=, which return // a bool, not a complex value. Value *TreeToLLVM::EmitComplexBinOp(tree exp, const MemRef *DestLoc) { const Type *ComplexTy = ConvertType(TREE_TYPE(TREE_OPERAND(exp, 0))); @@ -5793,24 +5793,46 @@ switch (TREE_CODE(exp)) { default: TODO(exp); case PLUS_EXPR: // (a+ib) + (c+id) = (a+c) + i(b+d) - DSTr = Builder.CreateFAdd(LHSr, RHSr, "tmpr"); - DSTi = Builder.CreateFAdd(LHSi, RHSi, "tmpi"); + if (LHSr->getType()->isFloatingPoint()) { + DSTr = Builder.CreateFAdd(LHSr, RHSr, "tmpr"); + DSTi = Builder.CreateFAdd(LHSi, RHSi, "tmpi"); + } else { + DSTr = Builder.CreateAdd(LHSr, RHSr, "tmpr"); + DSTi = Builder.CreateAdd(LHSi, RHSi, "tmpi"); + } break; case MINUS_EXPR: // (a+ib) - (c+id) = (a-c) + i(b-d) - DSTr = Builder.CreateFSub(LHSr, RHSr, "tmpr"); - DSTi = Builder.CreateFSub(LHSi, RHSi, "tmpi"); + if (LHSr->getType()->isFloatingPoint()) { + DSTr = Builder.CreateFSub(LHSr, RHSr, "tmpr"); + DSTi = Builder.CreateFSub(LHSi, RHSi, "tmpi"); + } else { + DSTr = Builder.CreateSub(LHSr, RHSr, "tmpr"); + DSTi = Builder.CreateSub(LHSi, RHSi, "tmpi"); + } break; case MULT_EXPR: { // (a+ib) * (c+id) = (ac-bd) + i(ad+cb) - Value *Tmp1 = Builder.CreateFMul(LHSr, RHSr); // a*c - Value *Tmp2 = Builder.CreateFMul(LHSi, RHSi); // b*d - DSTr = Builder.CreateFSub(Tmp1, Tmp2); // ac-bd - - Value *Tmp3 = Builder.CreateFMul(LHSr, RHSi); // a*d - Value *Tmp4 = Builder.CreateFMul(RHSr, LHSi); // c*b - DSTi = Builder.CreateFAdd(Tmp3, Tmp4); // ad+cb + if (LHSr->getType()->isFloatingPoint()) { + Value *Tmp1 = Builder.CreateFMul(LHSr, RHSr); // a*c + Value *Tmp2 = Builder.CreateFMul(LHSi, RHSi); // b*d + DSTr = Builder.CreateFSub(Tmp1, Tmp2); // ac-bd + + Value *Tmp3 = Builder.CreateFMul(LHSr, RHSi); // a*d + Value *Tmp4 = Builder.CreateFMul(RHSr, LHSi); // c*b + DSTi = Builder.CreateFAdd(Tmp3, Tmp4); // ad+cb + } else { + Value *Tmp1 = Builder.CreateMul(LHSr, RHSr); // a*c + Value *Tmp2 = Builder.CreateMul(LHSi, RHSi); // b*d + DSTr = Builder.CreateSub(Tmp1, Tmp2); // ac-bd + + Value *Tmp3 = Builder.CreateMul(LHSr, RHSi); // a*d + Value *Tmp4 = Builder.CreateMul(RHSr, LHSi); // c*b + DSTi = Builder.CreateAdd(Tmp3, Tmp4); // ad+cb + } break; } case RDIV_EXPR: { // (a+ib) / (c+id) = ((ac+bd)/(cc+dd)) + i((bc-ad)/(cc+dd)) + // RDIV_EXPR should always be floating point. + assert (LHSr->getType()->isFloatingPoint()); Value *Tmp1 = Builder.CreateFMul(LHSr, RHSr); // a*c Value *Tmp2 = Builder.CreateFMul(LHSi, RHSi); // b*d Value *Tmp3 = Builder.CreateFAdd(Tmp1, Tmp2); // ac+bd @@ -5818,7 +5840,6 @@ Value *Tmp4 = Builder.CreateFMul(RHSr, RHSr); // c*c Value *Tmp5 = Builder.CreateFMul(RHSi, RHSi); // d*d Value *Tmp6 = Builder.CreateFAdd(Tmp4, Tmp5); // cc+dd - // FIXME: What about integer complex? DSTr = Builder.CreateFDiv(Tmp3, Tmp6); Value *Tmp7 = Builder.CreateFMul(LHSi, RHSr); // b*c From resistor at mac.com Mon Jun 22 13:25:59 2009 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Jun 2009 18:25:59 -0000 Subject: [llvm-commits] [llvm] r73892 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h include/llvm/Analysis/ScalarEvolutionExpressions.h lib/Analysis/ScalarEvolution.cpp Message-ID: <200906221826.n5MIQ0oT027484@zion.cs.uiuc.edu> Author: resistor Date: Mon Jun 22 13:25:46 2009 New Revision: 73892 URL: http://llvm.org/viewvc/llvm-project?rev=73892&view=rev Log: Banish global state from ScalarEvolution! SCEV uniquing is now done by tables attached to the ScalarEvolution pass. This also throws out the SCEV reference counting scheme, as the the SCEVs now have a lifetime controlled by the ScalarEvolution pass. Note that SCEVHandle is now a no-op, and will be remove in a future commit. Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=73892&r1=73891&r2=73892&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Mon Jun 22 13:25:46 2009 @@ -35,6 +35,14 @@ class SCEVHandle; class ScalarEvolution; class TargetData; + class SCEVConstant; + class SCEVTruncateExpr; + class SCEVZeroExtendExpr; + class SCEVCommutativeExpr; + class SCEVUDivExpr; + class SCEVSignExtendExpr; + class SCEVAddRecExpr; + class SCEVUnknown; template<> struct DenseMapInfo; /// SCEV - This class represents an analyzed expression in the program. These @@ -43,15 +51,9 @@ /// class SCEV { const unsigned SCEVType; // The SCEV baseclass this node corresponds to - mutable unsigned RefCount; friend class SCEVHandle; friend class DenseMapInfo; - void addRef() const { ++RefCount; } - void dropRef() const { - if (--RefCount == 0) - delete this; - } const ScalarEvolution* parent; @@ -61,7 +63,7 @@ virtual ~SCEV(); public: explicit SCEV(unsigned SCEVTy, const ScalarEvolution* p) : - SCEVType(SCEVTy), RefCount(0), parent(p) {} + SCEVType(SCEVTy), parent(p) {} unsigned getSCEVType() const { return SCEVType; } @@ -159,12 +161,9 @@ public: SCEVHandle(const SCEV *s) : S(s) { assert(S && "Cannot create a handle to a null SCEV!"); - S->addRef(); - } - SCEVHandle(const SCEVHandle &RHS) : S(RHS.S) { - S->addRef(); } - ~SCEVHandle() { S->dropRef(); } + SCEVHandle(const SCEVHandle &RHS) : S(RHS.S) { } + ~SCEVHandle() { } operator const SCEV*() const { return S; } @@ -176,18 +175,14 @@ const SCEVHandle &operator=(SCEV *RHS) { if (S != RHS) { - S->dropRef(); S = RHS; - S->addRef(); } return *this; } const SCEVHandle &operator=(const SCEVHandle &RHS) { if (S != RHS.S) { - S->dropRef(); S = RHS.S; - S->addRef(); } return *this; } @@ -209,14 +204,10 @@ struct DenseMapInfo { static inline SCEVHandle getEmptyKey() { static SCEVCouldNotCompute Empty(0); - if (Empty.RefCount == 0) - Empty.addRef(); return &Empty; } static inline SCEVHandle getTombstoneKey() { static SCEVCouldNotCompute Tombstone(0); - if (Tombstone.RefCount == 0) - Tombstone.addRef(); return &Tombstone; } static unsigned getHashValue(const SCEVHandle &Val) { @@ -639,6 +630,23 @@ void print(std::ostream *OS, const Module* M = 0) const { if (OS) print(*OS, M); } + + private: + // Uniquing tables. + std::map SCEVConstants; + std::map, + SCEVTruncateExpr*> SCEVTruncates; + std::map, + SCEVZeroExtendExpr*> SCEVZeroExtends; + std::map >, + SCEVCommutativeExpr*> SCEVCommExprs; + std::map, + SCEVUDivExpr*> SCEVUDivs; + std::map, + SCEVSignExtendExpr*> SCEVSignExtends; + std::map >, + SCEVAddRecExpr*> SCEVAddRecExprs; + std::map SCEVUnknowns; }; } Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h?rev=73892&r1=73891&r2=73892&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h Mon Jun 22 13:25:46 2009 @@ -38,8 +38,6 @@ ConstantInt *V; explicit SCEVConstant(ConstantInt *v, const ScalarEvolution* p) : SCEV(scConstant, p), V(v) {} - - virtual ~SCEVConstant(); public: ConstantInt *getValue() const { return V; } @@ -116,7 +114,6 @@ SCEVTruncateExpr(const SCEVHandle &op, const Type *ty, const ScalarEvolution* p); - virtual ~SCEVTruncateExpr(); public: SCEVHandle replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, @@ -146,7 +143,6 @@ SCEVZeroExtendExpr(const SCEVHandle &op, const Type *ty, const ScalarEvolution* p); - virtual ~SCEVZeroExtendExpr(); public: SCEVHandle replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, @@ -176,7 +172,6 @@ SCEVSignExtendExpr(const SCEVHandle &op, const Type *ty, const ScalarEvolution* p); - virtual ~SCEVSignExtendExpr(); public: SCEVHandle replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, @@ -269,7 +264,6 @@ const SmallVectorImpl &ops, const ScalarEvolution* p) : SCEVNAryExpr(T, ops, p) {} - ~SCEVCommutativeExpr(); public: SCEVHandle replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, @@ -345,7 +339,6 @@ const ScalarEvolution* p) : SCEV(scUDivExpr, p), LHS(lhs), RHS(rhs) {} - virtual ~SCEVUDivExpr(); public: const SCEVHandle &getLHS() const { return LHS; } const SCEVHandle &getRHS() const { return RHS; } @@ -405,7 +398,6 @@ assert(Operands[i]->isLoopInvariant(l) && "Operands of AddRec must be loop-invariant!"); } - ~SCEVAddRecExpr(); public: const SCEVHandle &getStart() const { return Operands[0]; } @@ -524,9 +516,7 @@ Value *V; explicit SCEVUnknown(Value *v, const ScalarEvolution* p) : SCEV(scUnknown, p), V(v) {} - - protected: - ~SCEVUnknown(); + public: Value *getValue() const { return V; } Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=73892&r1=73891&r2=73892&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Jun 22 13:25:46 2009 @@ -171,15 +171,9 @@ // SCEVConstants - Only allow the creation of one SCEVConstant for any // particular value. Don't use a SCEVHandle here, or else the object will // never be deleted! -static ManagedStatic > SCEVConstants; - - -SCEVConstant::~SCEVConstant() { - SCEVConstants->erase(V); -} SCEVHandle ScalarEvolution::getConstant(ConstantInt *V) { - SCEVConstant *&R = (*SCEVConstants)[V]; + SCEVConstant *&R = SCEVConstants[V]; if (R == 0) R = new SCEVConstant(V, this); return R; } @@ -213,8 +207,6 @@ // SCEVTruncates - Only allow the creation of one SCEVTruncateExpr for any // particular input. Don't use a SCEVHandle here, or else the object will // never be deleted! -static ManagedStatic, - SCEVTruncateExpr*> > SCEVTruncates; SCEVTruncateExpr::SCEVTruncateExpr(const SCEVHandle &op, const Type *ty, const ScalarEvolution* p) @@ -224,9 +216,6 @@ "Cannot truncate non-integer value!"); } -SCEVTruncateExpr::~SCEVTruncateExpr() { - SCEVTruncates->erase(std::make_pair(Op, Ty)); -} void SCEVTruncateExpr::print(raw_ostream &OS) const { OS << "(trunc " << *Op->getType() << " " << *Op << " to " << *Ty << ")"; @@ -235,8 +224,6 @@ // SCEVZeroExtends - Only allow the creation of one SCEVZeroExtendExpr for any // particular input. Don't use a SCEVHandle here, or else the object will never // be deleted! -static ManagedStatic, - SCEVZeroExtendExpr*> > SCEVZeroExtends; SCEVZeroExtendExpr::SCEVZeroExtendExpr(const SCEVHandle &op, const Type *ty, const ScalarEvolution* p) @@ -246,10 +233,6 @@ "Cannot zero extend non-integer value!"); } -SCEVZeroExtendExpr::~SCEVZeroExtendExpr() { - SCEVZeroExtends->erase(std::make_pair(Op, Ty)); -} - void SCEVZeroExtendExpr::print(raw_ostream &OS) const { OS << "(zext " << *Op->getType() << " " << *Op << " to " << *Ty << ")"; } @@ -257,8 +240,6 @@ // SCEVSignExtends - Only allow the creation of one SCEVSignExtendExpr for any // particular input. Don't use a SCEVHandle here, or else the object will never // be deleted! -static ManagedStatic, - SCEVSignExtendExpr*> > SCEVSignExtends; SCEVSignExtendExpr::SCEVSignExtendExpr(const SCEVHandle &op, const Type *ty, const ScalarEvolution* p) @@ -268,10 +249,6 @@ "Cannot sign extend non-integer value!"); } -SCEVSignExtendExpr::~SCEVSignExtendExpr() { - SCEVSignExtends->erase(std::make_pair(Op, Ty)); -} - void SCEVSignExtendExpr::print(raw_ostream &OS) const { OS << "(sext " << *Op->getType() << " " << *Op << " to " << *Ty << ")"; } @@ -279,13 +256,6 @@ // SCEVCommExprs - Only allow the creation of one SCEVCommutativeExpr for any // particular input. Don't use a SCEVHandle here, or else the object will never // be deleted! -static ManagedStatic >, - SCEVCommutativeExpr*> > SCEVCommExprs; - -SCEVCommutativeExpr::~SCEVCommutativeExpr() { - std::vector SCEVOps(Operands.begin(), Operands.end()); - SCEVCommExprs->erase(std::make_pair(getSCEVType(), SCEVOps)); -} void SCEVCommutativeExpr::print(raw_ostream &OS) const { assert(Operands.size() > 1 && "This plus expr shouldn't exist!"); @@ -340,12 +310,6 @@ // SCEVUDivs - Only allow the creation of one SCEVUDivExpr for any particular // input. Don't use a SCEVHandle here, or else the object will never be // deleted! -static ManagedStatic, - SCEVUDivExpr*> > SCEVUDivs; - -SCEVUDivExpr::~SCEVUDivExpr() { - SCEVUDivs->erase(std::make_pair(LHS, RHS)); -} bool SCEVUDivExpr::dominates(BasicBlock *BB, DominatorTree *DT) const { return LHS->dominates(BB, DT) && RHS->dominates(BB, DT); @@ -367,14 +331,6 @@ // SCEVAddRecExprs - Only allow the creation of one SCEVAddRecExpr for any // particular input. Don't use a SCEVHandle here, or else the object will never // be deleted! -static ManagedStatic >, - SCEVAddRecExpr*> > SCEVAddRecExprs; - -SCEVAddRecExpr::~SCEVAddRecExpr() { - std::vector SCEVOps(Operands.begin(), Operands.end()); - SCEVAddRecExprs->erase(std::make_pair(L, SCEVOps)); -} SCEVHandle SCEVAddRecExpr:: replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, @@ -420,9 +376,6 @@ // SCEVUnknowns - Only allow the creation of one SCEVUnknown for any particular // value. Don't use a SCEVHandle here, or else the object will never be // deleted! -static ManagedStatic > SCEVUnknowns; - -SCEVUnknown::~SCEVUnknown() { SCEVUnknowns->erase(V); } bool SCEVUnknown::isLoopInvariant(const Loop *L) const { // All non-instruction values are loop invariant. All instructions are loop @@ -791,7 +744,7 @@ return getAddRecExpr(Operands, AddRec->getLoop()); } - SCEVTruncateExpr *&Result = (*SCEVTruncates)[std::make_pair(Op, Ty)]; + SCEVTruncateExpr *&Result = SCEVTruncates[std::make_pair(Op, Ty)]; if (Result == 0) Result = new SCEVTruncateExpr(Op, Ty, this); return Result; } @@ -879,7 +832,7 @@ } } - SCEVZeroExtendExpr *&Result = (*SCEVZeroExtends)[std::make_pair(Op, Ty)]; + SCEVZeroExtendExpr *&Result = SCEVZeroExtends[std::make_pair(Op, Ty)]; if (Result == 0) Result = new SCEVZeroExtendExpr(Op, Ty, this); return Result; } @@ -951,7 +904,7 @@ } } - SCEVSignExtendExpr *&Result = (*SCEVSignExtends)[std::make_pair(Op, Ty)]; + SCEVSignExtendExpr *&Result = SCEVSignExtends[std::make_pair(Op, Ty)]; if (Result == 0) Result = new SCEVSignExtendExpr(Op, Ty, this); return Result; } @@ -1412,7 +1365,7 @@ // Okay, it looks like we really DO need an add expr. Check to see if we // already have one, otherwise create a new one. std::vector SCEVOps(Ops.begin(), Ops.end()); - SCEVCommutativeExpr *&Result = (*SCEVCommExprs)[std::make_pair(scAddExpr, + SCEVCommutativeExpr *&Result = SCEVCommExprs[std::make_pair(scAddExpr, SCEVOps)]; if (Result == 0) Result = new SCEVAddExpr(Ops, this); return Result; @@ -1577,7 +1530,7 @@ // Okay, it looks like we really DO need an mul expr. Check to see if we // already have one, otherwise create a new one. std::vector SCEVOps(Ops.begin(), Ops.end()); - SCEVCommutativeExpr *&Result = (*SCEVCommExprs)[std::make_pair(scMulExpr, + SCEVCommutativeExpr *&Result = SCEVCommExprs[std::make_pair(scMulExpr, SCEVOps)]; if (Result == 0) Result = new SCEVMulExpr(Ops, this); @@ -1670,7 +1623,7 @@ } } - SCEVUDivExpr *&Result = (*SCEVUDivs)[std::make_pair(LHS, RHS)]; + SCEVUDivExpr *&Result = SCEVUDivs[std::make_pair(LHS, RHS)]; if (Result == 0) Result = new SCEVUDivExpr(LHS, RHS, this); return Result; } @@ -1724,7 +1677,7 @@ } std::vector SCEVOps(Operands.begin(), Operands.end()); - SCEVAddRecExpr *&Result = (*SCEVAddRecExprs)[std::make_pair(L, SCEVOps)]; + SCEVAddRecExpr *&Result = SCEVAddRecExprs[std::make_pair(L, SCEVOps)]; if (Result == 0) Result = new SCEVAddRecExpr(Operands, L, this); return Result; } @@ -1810,7 +1763,7 @@ // Okay, it looks like we really DO need an smax expr. Check to see if we // already have one, otherwise create a new one. std::vector SCEVOps(Ops.begin(), Ops.end()); - SCEVCommutativeExpr *&Result = (*SCEVCommExprs)[std::make_pair(scSMaxExpr, + SCEVCommutativeExpr *&Result = SCEVCommExprs[std::make_pair(scSMaxExpr, SCEVOps)]; if (Result == 0) Result = new SCEVSMaxExpr(Ops, this); return Result; @@ -1897,7 +1850,7 @@ // Okay, it looks like we really DO need a umax expr. Check to see if we // already have one, otherwise create a new one. std::vector SCEVOps(Ops.begin(), Ops.end()); - SCEVCommutativeExpr *&Result = (*SCEVCommExprs)[std::make_pair(scUMaxExpr, + SCEVCommutativeExpr *&Result = SCEVCommExprs[std::make_pair(scUMaxExpr, SCEVOps)]; if (Result == 0) Result = new SCEVUMaxExpr(Ops, this); return Result; @@ -1920,7 +1873,7 @@ return getConstant(CI); if (isa(V)) return getIntegerSCEV(0, V->getType()); - SCEVUnknown *&Result = (*SCEVUnknowns)[V]; + SCEVUnknown *&Result = SCEVUnknowns[V]; if (Result == 0) Result = new SCEVUnknown(V, this); return Result; } @@ -4324,6 +4277,45 @@ BackedgeTakenCounts.clear(); ConstantEvolutionLoopExitValue.clear(); ValuesAtScopes.clear(); + + for (std::map::iterator + I = SCEVConstants.begin(), E = SCEVConstants.end(); I != E; ++I) + delete I->second; + for (std::map, + SCEVTruncateExpr*>::iterator I = SCEVTruncates.begin(), + E = SCEVTruncates.end(); I != E; ++I) + delete I->second; + for (std::map, + SCEVZeroExtendExpr*>::iterator I = SCEVZeroExtends.begin(), + E = SCEVZeroExtends.end(); I != E; ++I) + delete I->second; + for (std::map >, + SCEVCommutativeExpr*>::iterator I = SCEVCommExprs.begin(), + E = SCEVCommExprs.end(); I != E; ++I) + delete I->second; + for (std::map, SCEVUDivExpr*>::iterator + I = SCEVUDivs.begin(), E = SCEVUDivs.end(); I != E; ++I) + delete I->second; + for (std::map, + SCEVSignExtendExpr*>::iterator I = SCEVSignExtends.begin(), + E = SCEVSignExtends.end(); I != E; ++I) + delete I->second; + for (std::map >, + SCEVAddRecExpr*>::iterator I = SCEVAddRecExprs.begin(), + E = SCEVAddRecExprs.end(); I != E; ++I) + delete I->second; + for (std::map::iterator I = SCEVUnknowns.begin(), + E = SCEVUnknowns.end(); I != E; ++I) + delete I->second; + + SCEVConstants.clear(); + SCEVTruncates.clear(); + SCEVZeroExtends.clear(); + SCEVCommExprs.clear(); + SCEVUDivs.clear(); + SCEVSignExtends.clear(); + SCEVAddRecExprs.clear(); + SCEVUnknowns.clear(); } void ScalarEvolution::getAnalysisUsage(AnalysisUsage &AU) const { From edwintorok at gmail.com Mon Jun 22 13:36:11 2009 From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=) Date: Mon, 22 Jun 2009 21:36:11 +0300 Subject: [llvm-commits] [llvm] r73892 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h include/llvm/Analysis/ScalarEvolutionExpressions.h lib/Analysis/ScalarEvolution.cpp In-Reply-To: <200906221826.n5MIQ0oT027484@zion.cs.uiuc.edu> References: <200906221826.n5MIQ0oT027484@zion.cs.uiuc.edu> Message-ID: <4A3FCF1B.3000207@gmail.com> On 2009-06-22 21:25, Owen Anderson wrote: > Author: resistor > Date: Mon Jun 22 13:25:46 2009 > New Revision: 73892 > > URL: http://llvm.org/viewvc/llvm-project?rev=73892&view=rev > Log: > Banish global state from ScalarEvolution! SCEV uniquing is now done by tables attached to the ScalarEvolution pass. > This also throws out the SCEV reference counting scheme, as the the SCEVs now have a lifetime controlled by the > ScalarEvolution pass. > > Note that SCEVHandle is now a no-op, and will be remove in a future commit. > Hi Owen, What if somebody wants to do interprocedural analysis using SCEV expressions? Will there be a way to clone SCEV* objects, so that they can live longer than the current function being analyzed? Best regards, --Edwin From evan.cheng at apple.com Mon Jun 22 13:38:49 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 22 Jun 2009 18:38:49 -0000 Subject: [llvm-commits] [llvm] r73893 - in /llvm/trunk: lib/Target/ARM/ARMRegisterInfo.cpp test/CodeGen/ARM/arm-frameaddr.ll Message-ID: <200906221838.n5MIcnxm027913@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jun 22 13:38:48 2009 New Revision: 73893 URL: http://llvm.org/viewvc/llvm-project?rev=73893&view=rev Log: hasFP should return true if frame address is taken. Added: llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=73893&r1=73892&r2=73893&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Mon Jun 22 13:38:48 2009 @@ -497,7 +497,9 @@ /// bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); - return NoFramePointerElim || MFI->hasVarSizedObjects(); + return (NoFramePointerElim || + MFI->hasVarSizedObjects() || + MFI->isFrameAddressTaken()); } // hasReservedCallFrame - Under normal circumstances, when a frame pointer is Added: llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll?rev=73893&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll (added) +++ llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll Mon Jun 22 13:38:48 2009 @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep mov | grep r7 +; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi | grep mov | grep r11 +; PR4344 +; PR4416 + +define arm_aapcscc i8* @t() nounwind { +entry: + %0 = call i8* @llvm.frameaddress(i32 0) + ret i8* %0 +} + +declare i8* @llvm.frameaddress(i32) nounwind readnone From bruno.cardoso at gmail.com Mon Jun 22 14:16:16 2009 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 22 Jun 2009 19:16:16 -0000 Subject: [llvm-commits] [llvm] r73894 - in /llvm/trunk: include/llvm/CodeGen/BinaryObject.h include/llvm/Target/TargetELFWriterInfo.h lib/CodeGen/ELF.h lib/CodeGen/ELFCodeEmitter.cpp lib/CodeGen/ELFWriter.cpp lib/CodeGen/ELFWriter.h lib/Target/X86/X86ELFWriterInfo.cpp lib/Target/X86/X86ELFWriterInfo.h Message-ID: <200906221916.n5MJGGGR029104@zion.cs.uiuc.edu> Author: bruno Date: Mon Jun 22 14:16:16 2009 New Revision: 73894 URL: http://llvm.org/viewvc/llvm-project?rev=73894&view=rev Log: Add more methods to gather target specific elf stuff Support for .text relocations, implementing TargetELFWriter overloaded methods for x86/x86_64. Use a map to track global values to their symbol table indexes Code cleanup and small fixes Modified: llvm/trunk/include/llvm/CodeGen/BinaryObject.h llvm/trunk/include/llvm/Target/TargetELFWriterInfo.h llvm/trunk/lib/CodeGen/ELF.h llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp llvm/trunk/lib/CodeGen/ELFWriter.cpp llvm/trunk/lib/CodeGen/ELFWriter.h llvm/trunk/lib/Target/X86/X86ELFWriterInfo.cpp llvm/trunk/lib/Target/X86/X86ELFWriterInfo.h Modified: llvm/trunk/include/llvm/CodeGen/BinaryObject.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/BinaryObject.h?rev=73894&r1=73893&r2=73894&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/BinaryObject.h (original) +++ llvm/trunk/include/llvm/CodeGen/BinaryObject.h Mon Jun 22 14:16:16 2009 @@ -61,6 +61,11 @@ return Relocations; } + /// hasRelocations - Return true if 'Relocations' is not empty + bool hasRelocations() const { + return !Relocations.empty(); + } + /// emitByte - This callback is invoked when a byte needs to be /// written to the data stream. inline void emitByte(uint8_t B) { @@ -317,6 +322,7 @@ void addRelocation(const MachineRelocation& relocation) { Relocations.push_back(relocation); } + }; } // end namespace llvm Modified: llvm/trunk/include/llvm/Target/TargetELFWriterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetELFWriterInfo.h?rev=73894&r1=73893&r2=73894&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetELFWriterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetELFWriterInfo.h Mon Jun 22 14:16:16 2009 @@ -78,11 +78,32 @@ /// Symbol Table Info unsigned getSymTabEntrySize() const { return is64Bit ? 24 : 16; } - unsigned getSymTabAlignment() const { return is64Bit ? 8 : 4; } + + /// getPrefELFAlignment - Returns the preferred alignment for ELF. This + /// is used to align some sections. + unsigned getPrefELFAlignment() const { return is64Bit ? 8 : 4; } + + /// getRelocationEntrySize - Entry size used in the relocation section + unsigned getRelocationEntrySize() const { + return is64Bit ? (hasRelocationAddend() ? 24 : 16) + : (hasRelocationAddend() ? 12 : 8); + } /// getFunctionAlignment - Returns the alignment for function 'F', targets /// with different alignment constraints should overload this method virtual unsigned getFunctionAlignment(const Function *F) const; + + /// getRelocationType - Returns the target specific ELF Relocation type. + /// 'MachineRelTy' contains the object code independent relocation type + virtual unsigned getRelocationType(unsigned MachineRelTy) const = 0; + + /// hasRelocationAddend - True if the target uses an addend in the + /// ELF relocation entry. + virtual bool hasRelocationAddend() const = 0; + + /// getAddendForRelTy - Gets the addend value for an ELF relocation entry + /// based on the target relocation type. If addend is not used returns 0. + virtual long int getAddendForRelTy(unsigned RelTy) const = 0; }; } // end llvm namespace Modified: llvm/trunk/lib/CodeGen/ELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELF.h?rev=73894&r1=73893&r2=73894&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELF.h (original) +++ llvm/trunk/lib/CodeGen/ELF.h Mon Jun 22 14:16:16 2009 @@ -128,7 +128,13 @@ /// added to logical symbol table for the module. This is eventually /// turned into a real symbol table in the file. struct ELFSym { - const GlobalValue *GV; // The global value this corresponds to. + // The global value this corresponds to. Global symbols can be on of the + // 3 types : if this symbol has a zero initializer, it is common or should + // be placed in bss section otherwise it's a constant. + const GlobalValue *GV; + bool IsCommon; + bool IsBss; + bool IsConstant; // ELF specific fields unsigned NameIdx; // Index in .strtab of name, once emitted. @@ -159,8 +165,9 @@ STV_PROTECTED = 3 // Visible in other components but not preemptable }; - ELFSym(const GlobalValue *gv) : GV(gv), NameIdx(0), Value(0), - Size(0), Info(0), Other(0), + ELFSym(const GlobalValue *gv) : GV(gv), IsCommon(false), IsBss(false), + IsConstant(false), NameIdx(0), Value(0), + Size(0), Info(0), Other(STV_DEFAULT), SectionIdx(ELFSection::SHN_UNDEF) { if (!GV) return; @@ -180,16 +187,47 @@ } } - void SetBind(unsigned X) { + unsigned getBind() { + return (Info >> 4) & 0xf; + } + + void setBind(unsigned X) { assert(X == (X & 0xF) && "Bind value out of range!"); Info = (Info & 0x0F) | (X << 4); } - void SetType(unsigned X) { + void setType(unsigned X) { assert(X == (X & 0xF) && "Type value out of range!"); Info = (Info & 0xF0) | X; } }; + /// ELFRelocation - This class contains all the information necessary to + /// to generate any 32-bit or 64-bit ELF relocation entry. + class ELFRelocation { + uint64_t r_offset; // offset in the section of the object this applies to + uint32_t r_symidx; // symbol table index of the symbol to use + uint32_t r_type; // machine specific relocation type + int64_t r_add; // explicit relocation addend + bool r_rela; // if true then the addend is part of the entry + // otherwise the addend is at the location specified + // by r_offset + public: + uint64_t getInfo(bool is64Bit) const { + if (is64Bit) + return ((uint64_t)r_symidx << 32) + ((uint64_t)r_type & 0xFFFFFFFFL); + else + return (r_symidx << 8) + (r_type & 0xFFL); + } + + uint64_t getOffset() const { return r_offset; } + int64_t getAddend() const { return r_add; } + + ELFRelocation(uint64_t off, uint32_t sym, uint32_t type, + bool rela = true, int64_t addend = 0) : + r_offset(off), r_symidx(sym), r_type(type), + r_add(addend), r_rela(rela) {} + }; + } // end namespace llvm #endif Modified: llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp?rev=73894&r1=73893&r2=73894&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp (original) +++ llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp Mon Jun 22 14:16:16 2009 @@ -71,39 +71,38 @@ // Update Section Size ES->Size = CurBufferPtr - BufferBegin; + // Set the symbol type as a function + FnSym.setType(ELFSym::STT_FUNC); + FnSym.SectionIdx = ES->SectionIdx; + FnSym.Size = CurBufferPtr-FnStartPtr; + + // Offset from start of Section + FnSym.Value = FnStartPtr-BufferBegin; + // Figure out the binding (linkage) of the symbol. switch (MF.getFunction()->getLinkage()) { default: // appending linkage is illegal for functions. assert(0 && "Unknown linkage type!"); case GlobalValue::ExternalLinkage: - FnSym.SetBind(ELFSym::STB_GLOBAL); + FnSym.setBind(ELFSym::STB_GLOBAL); + EW.SymbolList.push_back(FnSym); break; case GlobalValue::LinkOnceAnyLinkage: case GlobalValue::LinkOnceODRLinkage: case GlobalValue::WeakAnyLinkage: case GlobalValue::WeakODRLinkage: - FnSym.SetBind(ELFSym::STB_WEAK); + FnSym.setBind(ELFSym::STB_WEAK); + EW.SymbolList.push_back(FnSym); break; case GlobalValue::PrivateLinkage: assert (0 && "PrivateLinkage should not be in the symbol table."); case GlobalValue::InternalLinkage: - FnSym.SetBind(ELFSym::STB_LOCAL); + FnSym.setBind(ELFSym::STB_LOCAL); + EW.SymbolList.push_front(FnSym); break; } - // Set the symbol type as a function - FnSym.SetType(ELFSym::STT_FUNC); - - FnSym.SectionIdx = ES->SectionIdx; - FnSym.Size = CurBufferPtr-FnStartPtr; - - // Offset from start of Section - FnSym.Value = FnStartPtr-BufferBegin; - - // Finally, add it to the symtab. - EW.SymbolList.push_back(FnSym); - // Relocations // ----------- // If we have emitted any relocations to function-specific objects such as @@ -113,7 +112,6 @@ for (unsigned i = 0, e = Relocations.size(); i != e; ++i) { MachineRelocation &MR = Relocations[i]; intptr_t Addr; - if (MR.isBasicBlock()) { Addr = getMachineBasicBlockAddress(MR.getBasicBlock()); MR.setConstantVal(ES->SectionIdx); Modified: llvm/trunk/lib/CodeGen/ELFWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.cpp?rev=73894&r1=73893&r2=73894&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.cpp Mon Jun 22 14:16:16 2009 @@ -136,105 +136,41 @@ ElfHdr.emitWord16(0); // Placeholder // Add the null section, which is required to be first in the file. - getSection("", ELFSection::SHT_NULL, 0); - - // Start up the symbol table. The first entry in the symtab is the null - // entry. - SymbolList.push_back(ELFSym(0)); + getNullSection(); return false; } -void ELFWriter::EmitGlobal(GlobalVariable *GV) { +unsigned ELFWriter::getGlobalELFLinkage(const GlobalVariable *GV) { + if (GV->hasInternalLinkage()) + return ELFSym::STB_LOCAL; - // XXX: put local symbols *before* global ones! - const Section *S = TAI->SectionForGlobal(GV); - DOUT << "Section " << S->getName() << " for global " << GV->getName() << "\n"; + if (GV->hasWeakLinkage()) + return ELFSym::STB_WEAK; - // If this is an external global, emit it now. TODO: Note that it would be - // better to ignore the symbol here and only add it to the symbol table if - // referenced. - if (!GV->hasInitializer()) { - ELFSym ExternalSym(GV); - ExternalSym.SetBind(ELFSym::STB_GLOBAL); - ExternalSym.SetType(ELFSym::STT_NOTYPE); - ExternalSym.SectionIdx = ELFSection::SHN_UNDEF; - SymbolList.push_back(ExternalSym); - return; - } + return ELFSym::STB_GLOBAL; +} +// For global symbols without a section, return the Null section as a +// placeholder +ELFSection &ELFWriter::getGlobalSymELFSection(const GlobalVariable *GV, + ELFSym &Sym) { + const Section *S = TAI->SectionForGlobal(GV); + unsigned Flags = S->getFlags(); + unsigned SectionType = ELFSection::SHT_PROGBITS; + unsigned SHdrFlags = ELFSection::SHF_ALLOC; const TargetData *TD = TM.getTargetData(); unsigned Align = TD->getPreferredAlignment(GV); Constant *CV = GV->getInitializer(); - unsigned Size = TD->getTypeAllocSize(CV->getType()); - - // If this global has a zero initializer, go to .bss or common section. - if (CV->isNullValue() || isa(CV)) { - // If this global is part of the common block, add it now. Variables are - // part of the common block if they are zero initialized and allowed to be - // merged with other symbols. - if (GV->hasLinkOnceLinkage() || GV->hasWeakLinkage() || - GV->hasCommonLinkage()) { - ELFSym CommonSym(GV); - // Value for common symbols is the alignment required. - CommonSym.Value = Align; - CommonSym.Size = Size; - CommonSym.SetBind(ELFSym::STB_GLOBAL); - CommonSym.SetType(ELFSym::STT_OBJECT); - CommonSym.SectionIdx = ELFSection::SHN_COMMON; - SymbolList.push_back(CommonSym); - getSection(S->getName(), ELFSection::SHT_NOBITS, - ELFSection::SHF_WRITE | ELFSection::SHF_ALLOC, 1); - return; - } - // Otherwise, this symbol is part of the .bss section. Emit it now. - // Handle alignment. Ensure section is aligned at least as much as required - // by this symbol. - ELFSection &BSSSection = getBSSSection(); - BSSSection.Align = std::max(BSSSection.Align, Align); - - // Within the section, emit enough virtual padding to get us to an alignment - // boundary. - if (Align) - BSSSection.Size = (BSSSection.Size + Align - 1) & ~(Align-1); - - ELFSym BSSSym(GV); - BSSSym.Value = BSSSection.Size; - BSSSym.Size = Size; - BSSSym.SetType(ELFSym::STT_OBJECT); - - switch (GV->getLinkage()) { - default: // weak/linkonce/common handled above - assert(0 && "Unexpected linkage type!"); - case GlobalValue::AppendingLinkage: // FIXME: This should be improved! - case GlobalValue::ExternalLinkage: - BSSSym.SetBind(ELFSym::STB_GLOBAL); - break; - case GlobalValue::InternalLinkage: - BSSSym.SetBind(ELFSym::STB_LOCAL); - break; - } - - // Set the idx of the .bss section - BSSSym.SectionIdx = BSSSection.SectionIdx; - if (!GV->hasPrivateLinkage()) - SymbolList.push_back(BSSSym); + DOUT << "Section " << S->getName() << " for global " << GV->getName() << "\n"; - // Reserve space in the .bss section for this symbol. - BSSSection.Size += Size; - return; + // If this is an external global, the symbol does not have a section. + if (!GV->hasInitializer()) { + Sym.SectionIdx = ELFSection::SHN_UNDEF; + return getNullSection(); } - /// Emit the Global symbol to the right ELF section - ELFSym GblSym(GV); - GblSym.Size = Size; - GblSym.SetType(ELFSym::STT_OBJECT); - GblSym.SetBind(ELFSym::STB_GLOBAL); - unsigned Flags = S->getFlags(); - unsigned SectType = ELFSection::SHT_PROGBITS; - unsigned SHdrFlags = ELFSection::SHF_ALLOC; - if (Flags & SectionFlags::Code) SHdrFlags |= ELFSection::SHF_EXECINSTR; if (Flags & SectionFlags::Writeable) @@ -246,29 +182,78 @@ if (Flags & SectionFlags::Strings) SHdrFlags |= ELFSection::SHF_STRINGS; - // Remove tab from section name prefix - std::string SectionName(S->getName()); - size_t Pos = SectionName.find("\t"); - if (Pos != std::string::npos) - SectionName.erase(Pos, 1); - - // The section alignment should be bound to the element with - // the largest alignment - ELFSection &ElfS = getSection(SectionName, SectType, SHdrFlags); - GblSym.SectionIdx = ElfS.SectionIdx; - if (Align > ElfS.Align) - ElfS.Align = Align; - - // S.Value should contain the symbol index inside the section, - // and all symbols should start on their required alignment boundary - GblSym.Value = (ElfS.size() + (Align-1)) & (-Align); - ElfS.emitAlignment(Align); - - // Emit the constant symbol to its section - EmitGlobalConstant(CV, ElfS); + // If this global has a zero initializer, go to .bss or common section. + // Variables are part of the common block if they are zero initialized + // and allowed to be merged with other symbols. + if (CV->isNullValue() || isa(CV)) { + SectionType = ELFSection::SHT_NOBITS; + ELFSection &ElfS = getSection(S->getName(), SectionType, SHdrFlags); + if (GV->hasLinkOnceLinkage() || GV->hasWeakLinkage() || + GV->hasCommonLinkage()) { + Sym.SectionIdx = ELFSection::SHN_COMMON; + Sym.IsCommon = true; + return ElfS; + } + Sym.IsBss = true; + Sym.SectionIdx = ElfS.SectionIdx; + if (Align) ElfS.Size = (ElfS.Size + Align-1) & ~(Align-1); + ElfS.Align = std::max(ElfS.Align, Align); + return ElfS; + } + + Sym.IsConstant = true; + ELFSection &ElfS = getSection(S->getName(), SectionType, SHdrFlags); + Sym.SectionIdx = ElfS.SectionIdx; + ElfS.Align = std::max(ElfS.Align, Align); + return ElfS; +} + +void ELFWriter::EmitFunctionDeclaration(const Function *F) { + ELFSym GblSym(F); + GblSym.setBind(ELFSym::STB_GLOBAL); + GblSym.setType(ELFSym::STT_NOTYPE); + GblSym.SectionIdx = ELFSection::SHN_UNDEF; SymbolList.push_back(GblSym); } +void ELFWriter::EmitGlobalVar(const GlobalVariable *GV) { + unsigned SymBind = getGlobalELFLinkage(GV); + ELFSym GblSym(GV); + GblSym.setBind(SymBind); + + if (GV->hasInitializer()) + GblSym.setType(ELFSym::STT_OBJECT); + else + GblSym.setType(ELFSym::STT_NOTYPE); + + ELFSection &GblSection = getGlobalSymELFSection(GV, GblSym); + const TargetData *TD = TM.getTargetData(); + unsigned Align = TD->getPreferredAlignment(GV); + unsigned Size = TD->getTypeAllocSize(GV->getInitializer()->getType()); + GblSym.Size = Size; + + if (GblSym.IsCommon) { + GblSym.Value = Align; + } else if (GblSym.IsBss) { + GblSym.Value = GblSection.Size; + GblSection.Size += Size; + } else if (GblSym.IsConstant){ + // GblSym.Value should contain the symbol index inside the section, + // and all symbols should start on their required alignment boundary + GblSym.Value = (GblSection.size() + (Align-1)) & (-Align); + GblSection.emitAlignment(Align); + EmitGlobalConstant(GV->getInitializer(), GblSection); + } + + // Local symbols should come first on the symbol table. + if (!GV->hasPrivateLinkage()) { + if (SymBind == ELFSym::STB_LOCAL) + SymbolList.push_front(GblSym); + else + SymbolList.push_back(GblSym); + } +} + void ELFWriter::EmitGlobalConstantStruct(const ConstantStruct *CVS, ELFSection &GblS) { @@ -306,6 +291,7 @@ if (const ConstantArray *CVA = dyn_cast(CV)) { if (CVA->isString()) { std::string GblStr = CVA->getAsString(); + GblStr.resize(GblStr.size()-1); GblS.emitString(GblStr); } else { // Not a string. Print the values in successive locations for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i) @@ -370,8 +356,31 @@ // Build and emit data, bss and "common" sections. for (Module::global_iterator I = M.global_begin(), E = M.global_end(); - I != E; ++I) - EmitGlobal(I); + I != E; ++I) { + EmitGlobalVar(I); + GblSymLookup[I] = 0; + } + + // Emit all pending globals + // TODO: this should be done only for referenced symbols + for (SetVector::const_iterator I = PendingGlobals.begin(), + E = PendingGlobals.end(); I != E; ++I) { + + // No need to emit the symbol again + if (GblSymLookup.find(*I) != GblSymLookup.end()) + continue; + + if (GlobalVariable *GV = dyn_cast(*I)) { + EmitGlobalVar(GV); + } else if (Function *F = dyn_cast(*I)) { + // If function is not in GblSymLookup, it doesn't have a body, + // so emit the symbol as a function declaration (no section associated) + EmitFunctionDeclaration(F); + } else { + assert("unknown howto handle pending global"); + } + GblSymLookup[*I] = 0; + } // Emit non-executable stack note if (TAI->getNonexecutableStackDirective()) @@ -400,6 +409,67 @@ /// EmitRelocations - Emit relocations void ELFWriter::EmitRelocations() { + + // Create Relocation sections for each section which needs it. + for (std::list::iterator I = SectionList.begin(), + E = SectionList.end(); I != E; ++I) { + + // This section does not have relocations + if (!I->hasRelocations()) continue; + + // Get the relocation section for section 'I' + bool HasRelA = TEW->hasRelocationAddend(); + ELFSection &RelSec = getRelocSection(I->getName(), HasRelA); + + // 'Link' - Section hdr idx of the associated symbol table + // 'Info' - Section hdr idx of the section to which the relocation applies + ELFSection &SymTab = getSymbolTableSection(); + RelSec.Link = SymTab.SectionIdx; + RelSec.Info = I->SectionIdx; + RelSec.EntSize = TEW->getRelocationEntrySize(); + + // Get the relocations from Section + std::vector Relos = I->getRelocations(); + for (std::vector::iterator MRI = Relos.begin(), + MRE = Relos.end(); MRI != MRE; ++MRI) { + MachineRelocation &MR = *MRI; + + // Offset from the start of the section containing the symbol + unsigned Offset = MR.getMachineCodeOffset(); + + // Symbol index in the symbol table + unsigned SymIdx = 0; + + // Target specific ELF relocation type + unsigned RelType = TEW->getRelocationType(MR.getRelocationType()); + + // Constant addend used to compute the value to be stored + // into the relocatable field + int64_t Addend = TEW->getAddendForRelTy(RelType); + + // There are several machine relocations types, and each one of + // them needs a different approach to retrieve the symbol table index. + if (MR.isGlobalValue()) { + const GlobalValue *G = MR.getGlobalValue(); + SymIdx = GblSymLookup[G]; + } else { + assert(0 && "dunno how to handle other relocation types"); + } + + // Get the relocation entry and emit to the relocation section + ELFRelocation Rel(Offset, SymIdx, RelType, HasRelA, Addend); + EmitRelocation(RelSec, Rel, HasRelA); + } + } +} + +/// EmitRelocation - Write relocation 'Rel' to the relocation section 'Rel' +void ELFWriter::EmitRelocation(BinaryObject &RelSec, ELFRelocation &Rel, + bool HasRelA) { + RelSec.emitWord(Rel.getOffset()); + RelSec.emitWord(Rel.getInfo(is64Bit)); + if (HasRelA) + RelSec.emitWord(Rel.getAddend()); } /// EmitSymbol - Write symbol 'Sym' to the symbol table 'SymbolTable' @@ -451,25 +521,27 @@ /// EmitSymbolTable - If the current symbol table is non-empty, emit the string /// table for it and then the symbol table itself. void ELFWriter::EmitSymbolTable() { - if (SymbolList.size() == 1) return; // Only the null entry. + if (!SymbolList.size()) return; // Empty symbol table. - // FIXME: compact all local symbols to the start of the symtab. unsigned FirstNonLocalSymbol = 1; - ELFSection &StrTab = getStringTableSection(); // Set the zero'th symbol to a null byte, as required. StrTab.emitByte(0); + // Walk on the symbol list and write symbol names into the + // string table. unsigned Index = 1; - for (unsigned i = 1, e = SymbolList.size(); i != e; ++i) { + for (std::list::iterator I = SymbolList.begin(), + E = SymbolList.end(); I != E; ++I) { + // Use the name mangler to uniquify the LLVM symbol. - std::string Name = Mang->getValueName(SymbolList[i].GV); + std::string Name = Mang->getValueName(I->GV); if (Name.empty()) { - SymbolList[i].NameIdx = 0; + I->NameIdx = 0; } else { - SymbolList[i].NameIdx = Index; + I->NameIdx = Index; StrTab.emitString(Name); // Keep track of the number of bytes emitted to this section. @@ -482,16 +554,33 @@ // Now that we have emitted the string table and know the offset into the // string table of each symbol, emit the symbol table itself. ELFSection &SymTab = getSymbolTableSection(); - SymTab.Align = TEW->getSymTabAlignment(); + SymTab.Align = TEW->getPrefELFAlignment(); SymTab.Link = StrTab.SectionIdx; // Section Index of .strtab. - SymTab.Info = FirstNonLocalSymbol; // First non-STB_LOCAL symbol. // Size of each symtab entry. SymTab.EntSize = TEW->getSymTabEntrySize(); - for (unsigned i = 0, e = SymbolList.size(); i != e; ++i) - EmitSymbol(SymTab, SymbolList[i]); + // The first entry in the symtab is the null symbol + ELFSym NullSym = ELFSym(0); + EmitSymbol(SymTab, NullSym); + + // Emit all the symbols to the symbol table. Skip the null + // symbol, cause it's emitted already + Index = 1; + for (std::list::iterator I = SymbolList.begin(), + E = SymbolList.end(); I != E; ++I, ++Index) { + // Keep track of the first non-local symbol + if (I->getBind() == ELFSym::STB_LOCAL) + FirstNonLocalSymbol++; + + // Emit symbol to the symbol table + EmitSymbol(SymTab, *I); + + // Record the symbol table index for each global value + GblSymLookup[I->GV] = Index; + } + SymTab.Info = FirstNonLocalSymbol; SymTab.Size = SymTab.size(); } @@ -559,7 +648,7 @@ } // Align Section Header. - unsigned TableAlign = is64Bit ? 8 : 4; + unsigned TableAlign = TEW->getPrefELFAlignment(); FileOff = (FileOff+TableAlign-1) & ~(TableAlign-1); // Now that we know where all of the sections will be emitted, set the e_shnum Modified: llvm/trunk/lib/CodeGen/ELFWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.h?rev=73894&r1=73893&r2=73894&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.h (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.h Mon Jun 22 14:16:16 2009 @@ -16,7 +16,7 @@ #include "llvm/ADT/SetVector.h" #include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/Support/OutputBuffer.h" +#include "llvm/Support/Debug.h" #include "llvm/Target/TargetAsmInfo.h" #include "llvm/Target/TargetELFWriterInfo.h" #include "ELF.h" @@ -89,7 +89,7 @@ bool doFinalization(Module &M); private: - // Blob containing the Elf header + /// Blob containing the Elf header BinaryObject ElfHdr; /// SectionList - This is the list of sections that we have emitted to the @@ -102,14 +102,35 @@ /// the SectionList. std::map SectionLookup; + /// GblSymLookup - This is a mapping from global value to a symbol index + /// in the symbol table. This is useful since relocations symbol references + /// must be quickly mapped to a symbol table index + std::map GblSymLookup; + + /// SymbolList - This is the list of symbols emitted to the symbol table + /// Local symbols go to the front and Globals to the back. + std::list SymbolList; + + /// PendingGlobals - List of externally defined symbols that we have been + /// asked to emit, but have not seen a reference to. When a reference + /// is seen, the symbol will move from this list to the SymbolList. + SetVector PendingGlobals; + /// getSection - Return the section with the specified name, creating a new /// section if one does not already exist. - ELFSection &getSection(const std::string &Name, unsigned Type, + ELFSection &getSection(const std::string &Name, unsigned Type, unsigned Flags = 0, unsigned Align = 0) { ELFSection *&SN = SectionLookup[Name]; if (SN) return *SN; - SectionList.push_back(ELFSection(Name, isLittleEndian, is64Bit)); + // Remove tab from section name prefix. This is necessary becase TAI + // sometimes return a section name prefixed with a "\t" char. + std::string SectionName(Name); + size_t Pos = SectionName.find("\t"); + if (Pos != std::string::npos) + SectionName.erase(Pos, 1); + + SectionList.push_back(ELFSection(SectionName, isLittleEndian, is64Bit)); SN = &SectionList.back(); SN->SectionIdx = NumSections++; SN->Type = Type; @@ -119,11 +140,25 @@ return *SN; } + /// TODO: support mangled names here to emit the right .text section + /// for c++ object files. ELFSection &getTextSection() { return getSection(".text", ELFSection::SHT_PROGBITS, ELFSection::SHF_EXECINSTR | ELFSection::SHF_ALLOC); } + /// Return the relocation section of section 'S'. 'RelA' is true + /// if the relocation section contains entries with addends. + ELFSection &getRelocSection(std::string SName, bool RelA) { + std::string RelSName(".rel"); + unsigned SHdrTy = RelA ? ELFSection::SHT_RELA : ELFSection::SHT_REL; + + if (RelA) RelSName.append("a"); + RelSName.append(SName); + + return getSection(RelSName, SHdrTy, 0, TEW->getPrefELFAlignment()); + } + ELFSection &getNonExecStackSection() { return getSection(".note.GNU-stack", ELFSection::SHT_PROGBITS, 0, 1); } @@ -146,15 +181,9 @@ ELFSection::SHF_WRITE | ELFSection::SHF_ALLOC); } - /// SymbolList - This is the list of symbols we have emitted to the file. - /// This actually gets rearranged before emission to the file (to put the - /// local symbols first in the list). - std::vector SymbolList; - - /// PendingGlobals - List of externally defined symbols that we have been - /// asked to emit, but have not seen a reference to. When a reference - /// is seen, the symbol will move from this list to the SymbolList. - SetVector PendingGlobals; + ELFSection &getNullSection() { + return getSection("", ELFSection::SHT_NULL, 0); + } // As we complete the ELF file, we need to update fields in the ELF header // (e.g. the location of the section table). These members keep track of @@ -165,11 +194,15 @@ unsigned ELFHdr_e_shnum_Offset; // e_shnum in ELF header. private: - void EmitGlobal(GlobalVariable *GV); + void EmitFunctionDeclaration(const Function *F); + void EmitGlobalVar(const GlobalVariable *GV); void EmitGlobalConstant(const Constant *C, ELFSection &GblS); void EmitGlobalConstantStruct(const ConstantStruct *CVS, ELFSection &GblS); + unsigned getGlobalELFLinkage(const GlobalVariable *GV); + ELFSection &getGlobalSymELFSection(const GlobalVariable *GV, ELFSym &Sym); void EmitRelocations(); + void EmitRelocation(BinaryObject &RelSec, ELFRelocation &Rel, bool HasRelA); void EmitSectionHeader(BinaryObject &SHdrTab, const ELFSection &SHdr); void EmitSectionTableStringTable(); void EmitSymbol(BinaryObject &SymbolTable, ELFSym &Sym); Modified: llvm/trunk/lib/Target/X86/X86ELFWriterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ELFWriterInfo.cpp?rev=73894&r1=73893&r2=73894&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ELFWriterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ELFWriterInfo.cpp Mon Jun 22 14:16:16 2009 @@ -12,11 +12,17 @@ //===----------------------------------------------------------------------===// #include "X86ELFWriterInfo.h" +#include "X86Relocations.h" #include "llvm/Function.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" + using namespace llvm; +//===----------------------------------------------------------------------===// +// Implementation of the X86ELFWriterInfo class +//===----------------------------------------------------------------------===// + X86ELFWriterInfo::X86ELFWriterInfo(TargetMachine &TM) : TargetELFWriterInfo(TM) { bool is64Bit = TM.getTargetData()->getPointerSizeInBits() == 64; @@ -25,6 +31,34 @@ X86ELFWriterInfo::~X86ELFWriterInfo() {} +unsigned X86ELFWriterInfo::getRelocationType(unsigned MachineRelTy) const { + if (is64Bit) { + switch(MachineRelTy) { + case X86::reloc_pcrel_word: + return R_X86_64_PC32; + case X86::reloc_absolute_word: + return R_X86_64_32; + case X86::reloc_absolute_dword: + return R_X86_64_64; + case X86::reloc_picrel_word: + default: + assert(0 && "unknown relocation type"); + } + } else { + switch(MachineRelTy) { + case X86::reloc_pcrel_word: + return R_386_PC32; + case X86::reloc_absolute_word: + return R_386_32; + case X86::reloc_absolute_dword: + case X86::reloc_picrel_word: + default: + assert(0 && "unknown relocation type"); + } + } + return 0; +} + unsigned X86ELFWriterInfo::getFunctionAlignment(const Function *F) const { unsigned FnAlign = 4; @@ -36,3 +70,15 @@ return (1 << FnAlign); } + +long int X86ELFWriterInfo::getAddendForRelTy(unsigned RelTy) const { + if (is64Bit) { + switch(RelTy) { + case R_X86_64_PC32: return -4; + break; + default: + assert(0 && "unknown x86 relocation type"); + } + } + return 0; +} Modified: llvm/trunk/lib/Target/X86/X86ELFWriterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ELFWriterInfo.h?rev=73894&r1=73893&r2=73894&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ELFWriterInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86ELFWriterInfo.h Mon Jun 22 14:16:16 2009 @@ -19,11 +19,43 @@ namespace llvm { class X86ELFWriterInfo : public TargetELFWriterInfo { + + // ELF Relocation types for X86 + enum X86RelocationType { + R_386_NONE = 0, + R_386_32 = 1, + R_386_PC32 = 2 + }; + + // ELF Relocation types for X86_64 + enum X86_64RelocationType { + R_X86_64_NONE = 0, + R_X86_64_64 = 1, + R_X86_64_PC32 = 2, + R_X86_64_32 = 10, + R_X86_64_32S = 11, + R_X86_64_PC64 = 24 + }; + public: X86ELFWriterInfo(TargetMachine &TM); virtual ~X86ELFWriterInfo(); + /// getFunctionAlignment - Returns the alignment for function 'F', targets + /// with different alignment constraints should overload this method virtual unsigned getFunctionAlignment(const Function *F) const; + + /// getRelocationType - Returns the target specific ELF Relocation type. + /// 'MachineRelTy' contains the object code independent relocation type + virtual unsigned getRelocationType(unsigned MachineRelTy) const; + + /// hasRelocationAddend - True if the target uses an addend in the + /// ELF relocation entry. + virtual bool hasRelocationAddend() const { return is64Bit ? true : false; } + + /// getAddendForRelTy - Gets the addend value for an ELF relocation entry + /// based on the target relocation type + virtual long int getAddendForRelTy(unsigned RelTy) const; }; } // end llvm namespace From bruno.cardoso at gmail.com Mon Jun 22 14:29:57 2009 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 22 Jun 2009 19:29:57 -0000 Subject: [llvm-commits] [llvm] r73895 - in /llvm/trunk/lib/CodeGen: ELFWriter.cpp ELFWriter.h Message-ID: <200906221929.n5MJTvWW029676@zion.cs.uiuc.edu> Author: bruno Date: Mon Jun 22 14:29:56 2009 New Revision: 73895 URL: http://llvm.org/viewvc/llvm-project?rev=73895&view=rev Log: Use different functions to emit the string and symbol tables. Modified: llvm/trunk/lib/CodeGen/ELFWriter.cpp llvm/trunk/lib/CodeGen/ELFWriter.h Modified: llvm/trunk/lib/CodeGen/ELFWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.cpp?rev=73895&r1=73894&r2=73895&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.cpp Mon Jun 22 14:29:56 2009 @@ -386,6 +386,9 @@ if (TAI->getNonexecutableStackDirective()) getNonExecStackSection(); + // Emit string table + EmitStringTable(); + // Emit the symbol table now, if non-empty. EmitSymbolTable(); @@ -518,12 +521,10 @@ } } -/// EmitSymbolTable - If the current symbol table is non-empty, emit the string -/// table for it and then the symbol table itself. -void ELFWriter::EmitSymbolTable() { +/// EmitStringTable - If the current symbol table is non-empty, emit the string +/// table for it +void ELFWriter::EmitStringTable() { if (!SymbolList.size()) return; // Empty symbol table. - - unsigned FirstNonLocalSymbol = 1; ELFSection &StrTab = getStringTableSection(); // Set the zero'th symbol to a null byte, as required. @@ -550,12 +551,20 @@ } assert(Index == StrTab.size()); StrTab.Size = Index; +} +/// EmitSymbolTable - Emit the symbol table itself. +void ELFWriter::EmitSymbolTable() { + if (!SymbolList.size()) return; // Empty symbol table. + + unsigned FirstNonLocalSymbol = 1; // Now that we have emitted the string table and know the offset into the // string table of each symbol, emit the symbol table itself. ELFSection &SymTab = getSymbolTableSection(); SymTab.Align = TEW->getPrefELFAlignment(); - SymTab.Link = StrTab.SectionIdx; // Section Index of .strtab. + + // Section Index of .strtab. + SymTab.Link = getStringTableSection().SectionIdx; // Size of each symtab entry. SymTab.EntSize = TEW->getSymTabEntrySize(); @@ -566,7 +575,7 @@ // Emit all the symbols to the symbol table. Skip the null // symbol, cause it's emitted already - Index = 1; + unsigned Index = 1; for (std::list::iterator I = SymbolList.begin(), E = SymbolList.end(); I != E; ++I, ++Index) { // Keep track of the first non-local symbol Modified: llvm/trunk/lib/CodeGen/ELFWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.h?rev=73895&r1=73894&r2=73895&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.h (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.h Mon Jun 22 14:29:56 2009 @@ -207,6 +207,7 @@ void EmitSectionTableStringTable(); void EmitSymbol(BinaryObject &SymbolTable, ELFSym &Sym); void EmitSymbolTable(); + void EmitStringTable(); void OutputSectionsAndSectionTable(); }; } From resistor at mac.com Mon Jun 22 15:15:47 2009 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Jun 2009 13:15:47 -0700 Subject: [llvm-commits] [llvm] r73892 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h include/llvm/Analysis/ScalarEvolutionExpressions.h lib/Analysis/ScalarEvolution.cpp In-Reply-To: <4A3FCF1B.3000207@gmail.com> References: <200906221826.n5MIQ0oT027484@zion.cs.uiuc.edu> <4A3FCF1B.3000207@gmail.com> Message-ID: <8378718F-363C-4909-8C07-63492D8E29AF@mac.com> On Jun 22, 2009, at 11:36 AM, T?r?k Edwin wrote: > On 2009-06-22 21:25, Owen Anderson wrote: >> Author: resistor >> Date: Mon Jun 22 13:25:46 2009 >> New Revision: 73892 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=73892&view=rev >> Log: >> Banish global state from ScalarEvolution! SCEV uniquing is now >> done by tables attached to the ScalarEvolution pass. >> This also throws out the SCEV reference counting scheme, as the the >> SCEVs now have a lifetime controlled by the >> ScalarEvolution pass. >> >> Note that SCEVHandle is now a no-op, and will be remove in a future >> commit. >> > > Hi Owen, > > What if somebody wants to do interprocedural analysis using SCEV > expressions? > Will there be a way to clone SCEV* objects, so that they can live > longer > than the current function being analyzed? Then they need to implement their own ownership model for SCEVs. The owned-by-ScalarEvolution model isn't hardwired into the SCEVs themselves, but rather into the getXXX methods of ScalarEvolution that create them. --Owen From evan.cheng at apple.com Mon Jun 22 15:49:32 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 22 Jun 2009 20:49:32 -0000 Subject: [llvm-commits] [llvm] r73898 - in /llvm/trunk: lib/CodeGen/SimpleRegisterCoalescing.cpp test/CodeGen/ARM/2009-06-22-CoalescerBug.ll Message-ID: <200906222049.n5MKnWQ3032559@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jun 22 15:49:32 2009 New Revision: 73898 URL: http://llvm.org/viewvc/llvm-project?rev=73898&view=rev Log: Fix another register coalescer crash: forgot to check if the instruction being updated has already been coalesced. Added: llvm/trunk/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=73898&r1=73897&r2=73898&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon Jun 22 15:49:32 2009 @@ -739,6 +739,9 @@ // After updating the operand, check if the machine instruction has // become a copy. If so, update its val# information. + if (JoinedCopies.count(UseMI)) + continue; + const TargetInstrDesc &TID = UseMI->getDesc(); unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx; if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 && @@ -749,9 +752,10 @@ allocatableRegs_[CopyDstReg])) { LiveInterval &LI = li_->getInterval(CopyDstReg); unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(UseMI)); - const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx); - if (DLR->valno->def == DefIdx) - DLR->valno->copy = UseMI; + if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) { + if (DLR->valno->def == DefIdx) + DLR->valno->copy = UseMI; + } } } } Added: llvm/trunk/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll?rev=73898&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll Mon Jun 22 15:49:32 2009 @@ -0,0 +1,43 @@ +; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin + + %struct.rtunion = type { i64 } + %struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] } + +define arm_apcscc void @simplify_unary_real(i8* nocapture %p) nounwind { +entry: + %tmp121 = load i64* null, align 4 ; [#uses=1] + %0 = getelementptr %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0 ; [#uses=1] + %tmp122 = load i64* %0, align 4 ; [#uses=1] + %1 = zext i64 undef to i192 ; [#uses=2] + %2 = zext i64 %tmp121 to i192 ; [#uses=1] + %3 = shl i192 %2, 64 ; [#uses=2] + %4 = zext i64 %tmp122 to i192 ; [#uses=1] + %5 = shl i192 %4, 128 ; [#uses=1] + %6 = or i192 %3, %1 ; [#uses=1] + %7 = or i192 %6, %5 ; [#uses=2] + switch i32 undef, label %bb82 [ + i32 77, label %bb38 + i32 129, label %bb21 + i32 130, label %bb20 + ] + +bb20: ; preds = %entry + ret void + +bb21: ; preds = %entry + br i1 undef, label %bb82, label %bb29 + +bb29: ; preds = %bb21 + %tmp18.i = and i192 %3, 1208907372870555465154560 ; [#uses=1] + %mask.i = or i192 %tmp18.i, %1 ; [#uses=1] + %mask41.i = or i192 %mask.i, 0 ; [#uses=1] + br label %bb82 + +bb38: ; preds = %entry + br label %bb82 + +bb82: ; preds = %bb38, %bb29, %bb21, %entry + %d.0 = phi i192 [ %mask41.i, %bb29 ], [ undef, %bb38 ], [ %7, %entry ], [ %7, %bb21 ] ; [#uses=1] + %tmp51 = trunc i192 %d.0 to i64 ; [#uses=0] + ret void +} From dalej at apple.com Mon Jun 22 15:59:08 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 22 Jun 2009 20:59:08 -0000 Subject: [llvm-commits] [llvm] r73900 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200906222059.n5MKx8ch000455@zion.cs.uiuc.edu> Author: johannes Date: Mon Jun 22 15:59:07 2009 New Revision: 73900 URL: http://llvm.org/viewvc/llvm-project?rev=73900&view=rev Log: Fix memcpy expansion so it won't generate invalid types for the target (I think). This was breaking the PPC32 calling sequence. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=73900&r1=73899&r2=73900&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 22 15:59:07 2009 @@ -3121,6 +3121,8 @@ VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); VTSize = VT.getSizeInBits() / 8; } else { + // This can result in a type that is not legal on the target, e.g. + // 1 or 2 bytes on PPC. VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); VTSize >>= 1; } @@ -3177,12 +3179,29 @@ getMemBasePlusOffset(Dst, DstOff, DAG), DstSV, DstSVOff + DstOff, false, DstAlign); } else { - Value = DAG.getLoad(VT, dl, Chain, - getMemBasePlusOffset(Src, SrcOff, DAG), - SrcSV, SrcSVOff + SrcOff, false, Align); - Store = DAG.getStore(Chain, dl, Value, - getMemBasePlusOffset(Dst, DstOff, DAG), - DstSV, DstSVOff + DstOff, false, DstAlign); + // The type might not be legal for the target. This should only happen + // if the type is smaller than a legal type, as on PPC, so the right + // thing to do is generate a LoadExt/StoreTrunc pair. + // FIXME does the case above also need this? + if (TLI.isTypeLegal(VT)) { + Value = DAG.getLoad(VT, dl, Chain, + getMemBasePlusOffset(Src, SrcOff, DAG), + SrcSV, SrcSVOff + SrcOff, false, Align); + Store = DAG.getStore(Chain, dl, Value, + getMemBasePlusOffset(Dst, DstOff, DAG), + DstSV, DstSVOff + DstOff, false, DstAlign); + } else { + MVT NVT = VT; + while (!TLI.isTypeLegal(NVT)) { + NVT = (MVT::SimpleValueType(NVT.getSimpleVT() + 1)); + } + Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain, + getMemBasePlusOffset(Src, SrcOff, DAG), + SrcSV, SrcSVOff + SrcOff, VT, false, Align); + Store = DAG.getTruncStore(Chain, dl, Value, + getMemBasePlusOffset(Dst, DstOff, DAG), + DstSV, DstSVOff + DstOff, VT, false, DstAlign); + } } OutChains.push_back(Store); SrcOff += VTSize; From bob.wilson at apple.com Mon Jun 22 16:01:46 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 22 Jun 2009 21:01:46 -0000 Subject: [llvm-commits] [llvm] r73901 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMRegisterInfo.cpp lib/Target/ARM/ARMRegisterInfo.td lib/Target/ARM/ARMSubtarget.cpp test/CodeGen/ARM/2007-03-13-InstrSched.ll Message-ID: <200906222101.n5ML1l2X000565@zion.cs.uiuc.edu> Author: bwilson Date: Mon Jun 22 16:01:46 2009 New Revision: 73901 URL: http://llvm.org/viewvc/llvm-project?rev=73901&view=rev Log: For Darwin on ARMv6 and newer, make register r9 available for use as a caller-saved register. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/test/CodeGen/ARM/2007-03-13-InstrSched.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=73901&r1=73900&r2=73901&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jun 22 16:01:46 2009 @@ -96,6 +96,8 @@ def IsThumb : Predicate<"Subtarget->isThumb()">; def HasThumb2 : Predicate<"Subtarget->hasThumb2()">; def IsARM : Predicate<"!Subtarget->isThumb()">; +def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; +def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; //===----------------------------------------------------------------------===// // ARM Flag Definitions. @@ -539,21 +541,22 @@ LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1", []>; +// On non-Darwin platforms R9 is callee-saved. let isCall = 1, Itinerary = IIC_Br, Defs = [R0, R1, R2, R3, R12, LR, D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), "bl ${func:call}", - [(ARMcall tglobaladdr:$func)]>; + [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>; def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), "bl", " ${func:call}", - [(ARMcall_pred tglobaladdr:$func)]>; + [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsNotDarwin]>; // ARMv5T and above def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, "blx $func", - [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]> { + [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsNotDarwin]> { let Inst{7-4} = 0b0011; let Inst{19-8} = 0b111111111111; let Inst{27-20} = 0b00010010; @@ -563,7 +566,36 @@ // ARMv4T def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops), "mov lr, pc\n\tbx $func", - [(ARMcall_nolink GPR:$func)]>; + [(ARMcall_nolink GPR:$func)]>, Requires<[IsNotDarwin]>; + } +} + +// On Darwin R9 is call-clobbered. +let isCall = 1, Itinerary = IIC_Br, + Defs = [R0, R1, R2, R3, R9, R12, LR, + D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { + def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), + "bl ${func:call}", + [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>; + + def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), + "bl", " ${func:call}", + [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsDarwin]>; + + // ARMv5T and above + def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, + "blx $func", + [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> { + let Inst{7-4} = 0b0011; + let Inst{19-8} = 0b111111111111; + let Inst{27-20} = 0b00010010; + } + + let Uses = [LR] in { + // ARMv4T + def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops), + "mov lr, pc\n\tbx $func", + [(ARMcall_nolink GPR:$func)]>, Requires<[IsDarwin]>; } } @@ -1321,7 +1353,10 @@ // Direct calls -def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; +def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>, + Requires<[IsNotDarwin]>; +def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>, + Requires<[IsDarwin]>; // zextload i1 -> zextload i8 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=73901&r1=73900&r2=73901&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Mon Jun 22 16:01:46 2009 @@ -235,8 +235,10 @@ }; static const unsigned DarwinCalleeSavedRegs[] = { + // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved + // register. ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, - ARM::R11, ARM::R10, ARM::R9, ARM::R8, + ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, @@ -256,6 +258,7 @@ &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 0 }; + static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = { &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass, @@ -265,7 +268,33 @@ &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 0 }; - return STI.isThumb() ? ThumbCalleeSavedRegClasses : CalleeSavedRegClasses; + + static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = { + &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, + &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, + &ARM::GPRRegClass, &ARM::GPRRegClass, + + &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, + &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, + 0 + }; + + static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={ + &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass, + &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass, + &ARM::GPRRegClass, &ARM::GPRRegClass, + + &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, + &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, + 0 + }; + + if (STI.isThumb()) { + return STI.isTargetDarwin() + ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses; + } + return STI.isTargetDarwin() + ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses; } BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=73901&r1=73900&r2=73901&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Mon Jun 22 16:01:46 2009 @@ -87,6 +87,7 @@ // sp == Stack Pointer // r12 == ip (scratch) // r7 == Frame Pointer (thumb-style backtraces) +// r9 == May be reserved as Thread Register // r11 == Frame Pointer (arm-style backtraces) // r10 == Stack Limit // @@ -115,13 +116,13 @@ ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R10, ARM::R11 }; - // FP is R7, R9 is available. + // FP is R7, R9 is available as non-callee-saved register. + // This is used by Darwin. static const unsigned ARM_GPR_AO_3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, - ARM::R12,ARM::LR, + ARM::R9, ARM::R12,ARM::LR, ARM::R4, ARM::R5, ARM::R6, - ARM::R8, ARM::R9, ARM::R10,ARM::R11, - ARM::R7 }; + ARM::R8, ARM::R10,ARM::R11,ARM::R7 }; // FP is R7, R9 is not available. static const unsigned ARM_GPR_AO_4[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, @@ -155,17 +156,15 @@ GPRClass::iterator I; if (Subtarget.isTargetDarwin()) { - if (Subtarget.isR9Reserved()) { + if (Subtarget.isR9Reserved()) I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned)); - } else { + else I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned)); - } } else { - if (Subtarget.isR9Reserved()) { + if (Subtarget.isR9Reserved()) I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned)); - } else { + else I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned)); - } } // Mac OS X requires FP not to be clobbered for backtracing purpose. Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=73901&r1=73900&r2=73901&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Jun 22 16:01:46 2009 @@ -16,15 +16,20 @@ #include "llvm/Module.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/Support/CommandLine.h" using namespace llvm; +static cl::opt +ReserveR9("arm-reserve-r9", cl::Hidden, + cl::desc("Reserve R9, making it unavailable as GPR")); + ARMSubtarget::ARMSubtarget(const Module &M, const std::string &FS, bool isThumb) : ARMArchVersion(V4T) , ARMFPUType(None) , IsThumb(isThumb) , ThumbMode(Thumb1) - , IsR9Reserved(false) + , IsR9Reserved(ReserveR9) , stackAlignment(4) , CPUString("generic") , TargetType(isELF) // Default to ELF unless otherwise specified. @@ -83,5 +88,5 @@ stackAlignment = 8; if (isTargetDarwin()) - IsR9Reserved = true; + IsR9Reserved = ReserveR9 | (ARMArchVersion < V6); } Modified: llvm/trunk/test/CodeGen/ARM/2007-03-13-InstrSched.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-03-13-InstrSched.ll?rev=73901&r1=73900&r2=73901&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2007-03-13-InstrSched.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2007-03-13-InstrSched.ll Mon Jun 22 16:01:46 2009 @@ -1,5 +1,8 @@ ; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -relocation-model=pic \ -; RUN: -mattr=+v6 -ifcvt-limit=0 -stats |& grep asm-printer | grep 35 +; RUN: -mattr=+v6 | grep r9 +; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -relocation-model=pic \ +; RUN: -mattr=+v6 -arm-reserve-r9 -ifcvt-limit=0 -stats |& grep asm-printer +; | grep 35 define void @test(i32 %tmp56222, i32 %tmp36224, i32 %tmp46223, i32 %i.0196.0.ph, i32 %tmp8, i32* %tmp1011, i32** %tmp1, i32* %d2.1.out, i32* %d3.1.out, i32* %d0.1.out, i32* %d1.1.out) { newFuncRoot: From evan.cheng at apple.com Mon Jun 22 16:09:17 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 22 Jun 2009 21:09:17 -0000 Subject: [llvm-commits] [llvm] r73902 - in /llvm/trunk/test/CodeGen/ARM: 2008-09-14-CoalescerBug.ll 2008-09-14-CoaleserBug.ll Message-ID: <200906222109.n5ML9HrN000799@zion.cs.uiuc.edu> Author: evancheng Date: Mon Jun 22 16:09:17 2009 New Revision: 73902 URL: http://llvm.org/viewvc/llvm-project?rev=73902&view=rev Log: It's coalescer, not coaleser. Added: llvm/trunk/test/CodeGen/ARM/2008-09-14-CoalescerBug.ll - copied unchanged from r73888, llvm/trunk/test/CodeGen/ARM/2008-09-14-CoaleserBug.ll Removed: llvm/trunk/test/CodeGen/ARM/2008-09-14-CoaleserBug.ll Removed: llvm/trunk/test/CodeGen/ARM/2008-09-14-CoaleserBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2008-09-14-CoaleserBug.ll?rev=73901&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2008-09-14-CoaleserBug.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2008-09-14-CoaleserBug.ll (removed) @@ -1,29 +0,0 @@ -; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin - -@"\01LC1" = external constant [288 x i8] ; <[288 x i8]*> [#uses=1] - -declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind - -define i32 @main(i32 %argc, i8** %argv) nounwind { -entry: - br label %bb.i - -bb.i: ; preds = %bb.i, %entry - %i.01.i = phi i32 [ 0, %entry ], [ %indvar.next52, %bb.i ] ; [#uses=1] - %indvar.next52 = add i32 %i.01.i, 1 ; [#uses=2] - %exitcond53 = icmp eq i32 %indvar.next52, 15 ; [#uses=1] - br i1 %exitcond53, label %bb.i33.loopexit, label %bb.i - -bb.i33.loopexit: ; preds = %bb.i - %0 = malloc [347 x i8] ; <[347 x i8]*> [#uses=2] - %.sub = getelementptr [347 x i8]* %0, i32 0, i32 0 ; [#uses=1] - call void @llvm.memcpy.i32( i8* %.sub, i8* getelementptr ([288 x i8]* @"\01LC1", i32 0, i32 0), i32 287, i32 1 ) nounwind - br label %bb.i28 - -bb.i28: ; preds = %bb.i28, %bb.i33.loopexit - br i1 false, label %repeat_fasta.exit, label %bb.i28 - -repeat_fasta.exit: ; preds = %bb.i28 - free [347 x i8]* %0 - unreachable -} From gohman at apple.com Mon Jun 22 16:10:22 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 22 Jun 2009 21:10:22 -0000 Subject: [llvm-commits] [llvm] r73903 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <200906222110.n5MLANk5000849@zion.cs.uiuc.edu> Author: djg Date: Mon Jun 22 16:10:22 2009 New Revision: 73903 URL: http://llvm.org/viewvc/llvm-project?rev=73903&view=rev Log: Fix some typos that Duncan noticed. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=73903&r1=73902&r2=73903&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Jun 22 16:10:22 2009 @@ -2791,7 +2791,7 @@ if (NewBTI.Exact == CouldNotCompute) { // We couldn't compute an exact value for this exit, so - // we don't be able to compute an exact value for the loop. + // we won't be able to compute an exact value for the loop. CouldNotComputeBECount = true; BECount = CouldNotCompute; } else if (!CouldNotComputeBECount) { @@ -2807,7 +2807,7 @@ } if (NewBTI.Max == CouldNotCompute) { // We couldn't compute an maximum value for this exit, so - // we don't be able to compute an maximum value for the loop. + // we won't be able to compute an maximum value for the loop. CouldNotComputeMaxBECount = true; MaxBECount = CouldNotCompute; } else if (!CouldNotComputeMaxBECount) { From xerxes at zafena.se Mon Jun 22 16:16:16 2009 From: xerxes at zafena.se (=?ISO-8859-1?Q?Xerxes_R=E5nby?=) Date: Mon, 22 Jun 2009 23:16:16 +0200 Subject: [llvm-commits] [patch] Fix for PR4427 compiler/buildsystem platform arch defines breaks LLVM_NATIVE_ARCH in config.h Message-ID: <4A3FF4A0.7000301@zafena.se> http://llvm.org/bugs/show_bug.cgi?id=4427 The problem are that projects who depends on simple arch defines like #define X86 cant include TargetSelect.h and use InitializeNativeTarget() since the macro will unfold to InitializeTarget() instead of InitializeX86Target() and break the compilation. patch: http://llvm.org/bugs/attachment.cgi?id=3115 comments are welcome Cheers Xerxes From dalej at apple.com Mon Jun 22 16:22:16 2009 From: dalej at apple.com (Dale Johannesen) Date: Mon, 22 Jun 2009 21:22:16 -0000 Subject: [llvm-commits] [test-suite] r73904 - /test-suite/trunk/External/HMMER/Makefile Message-ID: <200906222122.n5MLMGCi001304@zion.cs.uiuc.edu> Author: johannes Date: Mon Jun 22 16:22:15 2009 New Revision: 73904 URL: http://llvm.org/viewvc/llvm-project?rev=73904&view=rev Log: Cause -faltivec -maltivec to be passed on PPC target. Don't ask me why -DSSE2 causes Altivec code to be generated on this target, but it does. Modified: test-suite/trunk/External/HMMER/Makefile Modified: test-suite/trunk/External/HMMER/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/HMMER/Makefile?rev=73904&r1=73903&r2=73904&view=diff ============================================================================== --- test-suite/trunk/External/HMMER/Makefile (original) +++ test-suite/trunk/External/HMMER/Makefile Mon Jun 22 16:22:15 2009 @@ -9,6 +9,11 @@ LIBS += -lpthread LDFLAGS += -lpthread +ifeq ($(ARCH),PowerPC) +TARGET_FLAGS += -maltivec -faltivec +LCCFLAGS += -maltivec -faltivec +endif + ifdef LARGE_PROBLEM_SIZE RUN_OPTIONS = --fixed 400 --cpu 1 --num 200000 --seed 1158818515 $(HMMER_ROOT)/globin.hmm else From gohman at apple.com Mon Jun 22 16:26:03 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 22 Jun 2009 14:26:03 -0700 Subject: [llvm-commits] [llvm] r73892 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h include/llvm/Analysis/ScalarEvolutionExpressions.h lib/Analysis/ScalarEvolution.cpp In-Reply-To: <4A3FCF1B.3000207@gmail.com> References: <200906221826.n5MIQ0oT027484@zion.cs.uiuc.edu> <4A3FCF1B.3000207@gmail.com> Message-ID: <906D3F87-341B-4265-BD72-A0CA8ACBCA7E@apple.com> On Jun 22, 2009, at 11:36 AM, T?r?k Edwin wrote: > On 2009-06-22 21:25, Owen Anderson wrote: > >> Author: resistor >> >> Date: Mon Jun 22 13:25:46 2009 >> >> New Revision: 73892 >> >> >> >> URL: http://llvm.org/viewvc/llvm-project?rev=73892&view=rev >> >> Log: >> >> Banish global state from ScalarEvolution! SCEV uniquing is now >> done by tables attached to the ScalarEvolution pass. >> >> This also throws out the SCEV reference counting scheme, as the the >> SCEVs now have a lifetime controlled by the >> >> ScalarEvolution pass. >> >> >> >> Note that SCEVHandle is now a no-op, and will be remove in a future >> commit. >> >> >> > > Hi Owen, > > What if somebody wants to do interprocedural analysis using SCEV > expressions? ScalarEvolution is a FunctionPass only because the PassManager framework doesn't have anything that fits its needs better. There's nothing Function-oriented about it. ScalarEvolution could easily be a ModulePass, except that JIT codegen wouldn't like it, and that it depends on LoopInfo, which is a FunctionPass. LoopInfo itself could be a ModulePass, except it depends on DominatorTree, which, finally, is actually fairly Function-oriented. One option might be to split ScalarEvolution into a base ScalarEvolution class that manages SCEV objects and does all the analysis, and a separate ScalarEvolutionFunctionPass class which inherits from FunctionPass and exposes ScalarEvolution functionality. Then, as long as there's a way to make it use on-the-fly passes to get at LoopInfo and/or DominatorTree, there could be a ScalarEvolutionModulePass. > Will there be a way to clone SCEV* objects, so that they can live > longer > than the current function being analyzed? SCEV objects are uniquified so that they can be compared by pointer. Dan From xerxes at zafena.se Mon Jun 22 16:27:40 2009 From: xerxes at zafena.se (=?ISO-8859-1?Q?Xerxes_R=E5nby?=) Date: Mon, 22 Jun 2009 23:27:40 +0200 Subject: [llvm-commits] [patch] Fix for PR4429 cmake builds fails .so linking for symbols in ExecutionEngine JIT and Interpreter .o files. Message-ID: <4A3FF74C.2040700@zafena.se> http://llvm.org/bugs/show_bug.cgi?id=4429 When building with cmake ExecutionEngine JIT and Interpreter are still generated as .o files. This causes internal linking errors for icedtea6 libjvm.so when linking launchers. The patch solves this issue by letting cmake generate .a library files instead for ExecutionEngine JIT and Interpreter. configure builds already generates .a files so only cmake builds needs to be fixed. patch: http://llvm.org/bugs/attachment.cgi?id=3112 Cheers Xerxes From bob.wilson at apple.com Mon Jun 22 16:28:22 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 22 Jun 2009 21:28:22 -0000 Subject: [llvm-commits] [llvm] r73905 - /llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Message-ID: <200906222128.n5MLSMeF001528@zion.cs.uiuc.edu> Author: bwilson Date: Mon Jun 22 16:28:22 2009 New Revision: 73905 URL: http://llvm.org/viewvc/llvm-project?rev=73905&view=rev Log: Use thumb2 for ARM architectures V6T2 and later. Fix a bug in checking for "thumb" and add a check for V6T2. Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=73905&r1=73904&r2=73905&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Jun 22 16:28:22 2009 @@ -51,7 +51,7 @@ if (Len >= 5 && TT.substr(0, 4) == "armv") Idx = 4; - else if (Len >= 6 && TT.substr(0, 6) == "thumb") { + else if (Len >= 6 && TT.substr(0, 5) == "thumb") { IsThumb = true; if (Len >= 7 && TT[5] == 'v') Idx = 6; @@ -59,15 +59,19 @@ if (Idx) { unsigned SubVer = TT[Idx]; if (SubVer > '4' && SubVer <= '9') { - if (SubVer >= '7') + if (SubVer >= '7') { ARMArchVersion = V7A; - else if (SubVer == '6') + } else if (SubVer == '6') { ARMArchVersion = V6; - else if (SubVer == '5') { + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') + ARMArchVersion = V6T2; + } else if (SubVer == '5') { ARMArchVersion = V5T; if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') ARMArchVersion = V5TE; } + if (ARMArchVersion >= V6T2) + ThumbMode = Thumb2; } } From gohman at apple.com Mon Jun 22 16:24:20 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 22 Jun 2009 14:24:20 -0700 Subject: [llvm-commits] [llvm] r73866 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/trip-count5.ll In-Reply-To: <4A3F3899.3030808@free.fr> References: <200906220032.n5M0W3ic002321@zion.cs.uiuc.edu> <4A3F3899.3030808@free.fr> Message-ID: <68CA9891-6478-4C94-B124-9E39BF54B381@apple.com> On Jun 22, 2009, at 12:54 AM, Duncan Sands wrote: > Hi Dan, > > >> Teach ScalarEvolution how to analyze loops with multiple exit >> >> blocks, and also exit blocks with multiple conditions (combined >> >> with (bitwise) ands and ors). It's often infeasible to compute an >> >> exact trip count in such cases, but a useful upper bound can often >> >> be found. >> > > thanks for doing this. Does the loop unroller make any use of it? > The loop in PR2624 is still not unrolled for example. I believe LLVM's current loop unroller only works if an exact trip count is known. If ScalarEvolution finds the trip count is either 1 or 2, the loop won't be unrolled. There is more work to be done in ScalarEvolution to analyze loops like the one in that testcase also. > > >> + // We couldn't compute an exact value for this exit, so >> >> + // we don't be able to compute an exact value for the loop. >> > > we don't -> we won't > > This occurs again later. Fixed, thanks. Dan From nicolas.geoffray at lip6.fr Mon Jun 22 16:38:17 2009 From: nicolas.geoffray at lip6.fr (Nicolas Geoffray) Date: Mon, 22 Jun 2009 23:38:17 +0200 Subject: [llvm-commits] [llvm] r73884 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp In-Reply-To: <200906221509.n5MF9TjU008035@zion.cs.uiuc.edu> References: <200906221509.n5MF9TjU008035@zion.cs.uiuc.edu> Message-ID: <4A3FF9C9.4050308@lip6.fr> Hi Dan, I believe this patch is responsible for the bug highlighted by the attached (bugpoint reduced) test-case. Older revisions compile the test case correclty. FYI, here's what I get when llc'ing the file (arch=x86 OS=linux): llc: /home/ngeoffray/project/llvm-svn/llvm/include/llvm/ADT/APInt.h:216: llvm::APInt::APInt(unsigned int, uint64_t, bool): Assertion `BitWidth && "bitwidth too small"' failed. 0 llc 0x08beb5c8 Stack dump: 0. Program arguments: ../llvm/Release/bin/llc -march=x86 bugpoint-reduced-simplified.bc 1. Running pass 'Loop Pass Manager' on function '@JnJVM_antlr_CSharpCodeGenerator_genBitSet__Lantlr_collections_impl_BitSet_2I' 2. Running pass 'Loop Strength Reduction' on basic block '%"GOTO or IF*6"' Would you like me to open a PR? Nicolas Dan Gohman wrote: > Author: djg > Date: Mon Jun 22 10:09:28 2009 > New Revision: 73884 > > URL: http://llvm.org/viewvc/llvm-project?rev=73884&view=rev > Log: > Make use of getUMinFromMismatchedTypes when computing backedge-taken > counts for loops with multiple exits, replacing more conservative code > which only handled constants. This is derived from a patch by > Nick Lewycky. > > This also fixes llc aborts in ClamAV and others, as > getUMinFromMismatchedTypes takes care of balancing the types before > working with them. > > Modified: > llvm/trunk/lib/Analysis/ScalarEvolution.cpp > > Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=73884&r1=73883&r2=73884&view=diff > > ============================================================================== > --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) > +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Jun 22 10:09:28 2009 > @@ -2958,18 +2958,18 @@ > if (L->contains(TBB)) { > // Both conditions must be true for the loop to continue executing. > // Choose the less conservative count. > - // TODO: Take the minimum of the exact counts. > - if (BTI0.Exact == BTI1.Exact) > + if (BTI0.Exact == CouldNotCompute) > + BECount = BTI1.Exact; > + else if (BTI1.Exact == CouldNotCompute) > BECount = BTI0.Exact; > - // TODO: Take the minimum of the maximum counts. > + else > + BECount = getUMinFromMismatchedTypes(BTI0.Exact, BTI1.Exact); > if (BTI0.Max == CouldNotCompute) > MaxBECount = BTI1.Max; > else if (BTI1.Max == CouldNotCompute) > MaxBECount = BTI0.Max; > - else if (const SCEVConstant *C0 = dyn_cast(BTI0.Max)) > - if (const SCEVConstant *C1 = dyn_cast(BTI1.Max)) > - MaxBECount = getConstant(APIntOps::umin(C0->getValue()->getValue(), > - C1->getValue()->getValue())); > + else > + MaxBECount = getUMinFromMismatchedTypes(BTI0.Max, BTI1.Max); > } else { > // Both conditions must be true for the loop to exit. > assert(L->contains(FBB) && "Loop block has no successor in loop!"); > @@ -2992,18 +2992,18 @@ > if (L->contains(FBB)) { > // Both conditions must be false for the loop to continue executing. > // Choose the less conservative count. > - // TODO: Take the minimum of the exact counts. > - if (BTI0.Exact == BTI1.Exact) > + if (BTI0.Exact == CouldNotCompute) > + BECount = BTI1.Exact; > + else if (BTI1.Exact == CouldNotCompute) > BECount = BTI0.Exact; > - // TODO: Take the minimum of the maximum counts. > + else > + BECount = getUMinFromMismatchedTypes(BTI0.Exact, BTI1.Exact); > if (BTI0.Max == CouldNotCompute) > MaxBECount = BTI1.Max; > else if (BTI1.Max == CouldNotCompute) > MaxBECount = BTI0.Max; > - else if (const SCEVConstant *C0 = dyn_cast(BTI0.Max)) > - if (const SCEVConstant *C1 = dyn_cast(BTI1.Max)) > - MaxBECount = getConstant(APIntOps::umin(C0->getValue()->getValue(), > - C1->getValue()->getValue())); > + else > + MaxBECount = getUMinFromMismatchedTypes(BTI0.Max, BTI1.Max); > } else { > // Both conditions must be false for the loop to exit. > assert(L->contains(TBB) && "Loop block has no successor in loop!"); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: bugpoint-reduced-simplified.ll Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090622/46b16999/attachment.pl From anton at korobeynikov.info Mon Jun 22 16:39:19 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 23 Jun 2009 01:39:19 +0400 Subject: [llvm-commits] [llvm] r73887 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp In-Reply-To: <200906221729.n5MHTYc0025261@zion.cs.uiuc.edu> References: <200906221729.n5MHTYc0025261@zion.cs.uiuc.edu> Message-ID: Hi, Bob > Fix llvm-gcc build for armv6t2 and later architectures. ?The hasV6T2Ops > predicate does not check if Thumb mode is enabled, and when in ARM mode > there are still some checks for constant-pool use that need to run. What's the reason for this? 1. movt is available both in thumb and arm modes, there is no need to check for thumb here. 2. ARM's compiler writing guide explicitly suggests not using constant pool and materialize constants using pair of movw / movt. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From resistor at mac.com Mon Jun 22 16:39:50 2009 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Jun 2009 21:39:50 -0000 Subject: [llvm-commits] [llvm] r73906 - in /llvm/trunk: include/llvm/Analysis/IVUsers.h include/llvm/Analysis/LoopVR.h include/llvm/Analysis/ScalarEvolution.h include/llvm/Analysis/ScalarEvolutionExpander.h include/llvm/Analysis/ScalarEvolutionExpressions.h lib/Analysis/IVUsers.cpp lib/Analysis/LoopVR.cpp lib/Analysis/ScalarEvolution.cpp lib/Analysis/ScalarEvolutionExpander.cpp lib/Transforms/Scalar/IndVarSimplify.cpp lib/Transforms/Scalar/LoopDeletion.cpp lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <200906222139.n5MLdpeN001941@zion.cs.uiuc.edu> Author: resistor Date: Mon Jun 22 16:39:50 2009 New Revision: 73906 URL: http://llvm.org/viewvc/llvm-project?rev=73906&view=rev Log: SCEVHandle is no more! Modified: llvm/trunk/include/llvm/Analysis/IVUsers.h llvm/trunk/include/llvm/Analysis/LoopVR.h llvm/trunk/include/llvm/Analysis/ScalarEvolution.h llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h llvm/trunk/lib/Analysis/IVUsers.cpp llvm/trunk/lib/Analysis/LoopVR.cpp llvm/trunk/lib/Analysis/ScalarEvolution.cpp llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/include/llvm/Analysis/IVUsers.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/IVUsers.h?rev=73906&r1=73905&r2=73906&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/IVUsers.h (original) +++ llvm/trunk/include/llvm/Analysis/IVUsers.h Mon Jun 22 16:39:50 2009 @@ -34,7 +34,7 @@ class IVStrideUse : public CallbackVH, public ilist_node { public: IVStrideUse(IVUsersOfOneStride *parent, - const SCEVHandle &offset, + const SCEV* offset, Instruction* U, Value *O) : CallbackVH(U), Parent(parent), Offset(offset), OperandValToReplace(O), @@ -58,10 +58,10 @@ /// getOffset - Return the offset to add to a theoeretical induction /// variable that starts at zero and counts up by the stride to compute /// the value for the use. This always has the same type as the stride. - SCEVHandle getOffset() const { return Offset; } + const SCEV* getOffset() const { return Offset; } /// setOffset - Assign a new offset to this use. - void setOffset(SCEVHandle Val) { + void setOffset(const SCEV* Val) { Offset = Val; } @@ -96,7 +96,7 @@ IVUsersOfOneStride *Parent; /// Offset - The offset to add to the base induction expression. - SCEVHandle Offset; + const SCEV* Offset; /// OperandValToReplace - The Value of the operand in the user instruction /// that this IVStrideUse is representing. @@ -158,7 +158,7 @@ /// initial value and the operand that uses the IV. ilist Users; - void addUser(const SCEVHandle &Offset, Instruction *User, Value *Operand) { + void addUser(const SCEV* Offset, Instruction *User, Value *Operand) { Users.push_back(new IVStrideUse(this, Offset, User, Operand)); } }; @@ -178,12 +178,12 @@ /// IVUsesByStride - A mapping from the strides in StrideOrder to the /// uses in IVUses. - std::map IVUsesByStride; + std::map IVUsesByStride; /// StrideOrder - An ordering of the keys in IVUsesByStride that is stable: /// We use this to iterate over the IVUsesByStride collection without being /// dependent on random ordering of pointers in the process. - SmallVector StrideOrder; + SmallVector StrideOrder; private: virtual void getAnalysisUsage(AnalysisUsage &AU) const; @@ -203,7 +203,7 @@ /// getReplacementExpr - Return a SCEV expression which computes the /// value of the OperandValToReplace of the given IVStrideUse. - SCEVHandle getReplacementExpr(const IVStrideUse &U) const; + const SCEV* getReplacementExpr(const IVStrideUse &U) const; void print(raw_ostream &OS, const Module* = 0) const; virtual void print(std::ostream &OS, const Module* = 0) const; Modified: llvm/trunk/include/llvm/Analysis/LoopVR.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopVR.h?rev=73906&r1=73905&r2=73906&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopVR.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopVR.h Mon Jun 22 16:39:50 2009 @@ -78,9 +78,9 @@ private: ConstantRange compute(Value *V); - ConstantRange getRange(SCEVHandle S, Loop *L, ScalarEvolution &SE); + ConstantRange getRange(const SCEV* S, Loop *L, ScalarEvolution &SE); - ConstantRange getRange(SCEVHandle S, SCEVHandle T, ScalarEvolution &SE); + ConstantRange getRange(const SCEV* S, const SCEV* T, ScalarEvolution &SE); std::map Map; }; Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=73906&r1=73905&r2=73906&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Mon Jun 22 16:39:50 2009 @@ -32,7 +32,6 @@ class APInt; class ConstantInt; class Type; - class SCEVHandle; class ScalarEvolution; class TargetData; class SCEVConstant; @@ -43,7 +42,6 @@ class SCEVSignExtendExpr; class SCEVAddRecExpr; class SCEVUnknown; - template<> struct DenseMapInfo; /// SCEV - This class represents an analyzed expression in the program. These /// are reference-counted opaque objects that the client is not allowed to @@ -52,9 +50,6 @@ class SCEV { const unsigned SCEVType; // The SCEV baseclass this node corresponds to - friend class SCEVHandle; - friend class DenseMapInfo; - const ScalarEvolution* parent; SCEV(const SCEV &); // DO NOT IMPLEMENT @@ -94,9 +89,9 @@ /// the same value, but which uses the concrete value Conc instead of the /// symbolic value. If this SCEV does not use the symbolic value, it /// returns itself. - virtual SCEVHandle - replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, - const SCEVHandle &Conc, + virtual const SCEV* + replaceSymbolicValuesWithConcrete(const SCEV* Sym, + const SCEV* Conc, ScalarEvolution &SE) const = 0; /// dominates - Return true if elements that makes up this SCEV dominates @@ -139,9 +134,9 @@ virtual const Type *getType() const; virtual bool hasComputableLoopEvolution(const Loop *L) const; virtual void print(raw_ostream &OS) const; - virtual SCEVHandle - replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, - const SCEVHandle &Conc, + virtual const SCEV* + replaceSymbolicValuesWithConcrete(const SCEV* Sym, + const SCEV* Conc, ScalarEvolution &SE) const; virtual bool dominates(BasicBlock *BB, DominatorTree *DT) const { @@ -153,72 +148,6 @@ static bool classof(const SCEV *S); }; - /// SCEVHandle - This class is used to maintain the SCEV object's refcounts, - /// freeing the objects when the last reference is dropped. - class SCEVHandle { - const SCEV *S; - SCEVHandle(); // DO NOT IMPLEMENT - public: - SCEVHandle(const SCEV *s) : S(s) { - assert(S && "Cannot create a handle to a null SCEV!"); - } - SCEVHandle(const SCEVHandle &RHS) : S(RHS.S) { } - ~SCEVHandle() { } - - operator const SCEV*() const { return S; } - - const SCEV &operator*() const { return *S; } - const SCEV *operator->() const { return S; } - - bool operator==(const SCEV *RHS) const { return S == RHS; } - bool operator!=(const SCEV *RHS) const { return S != RHS; } - - const SCEVHandle &operator=(SCEV *RHS) { - if (S != RHS) { - S = RHS; - } - return *this; - } - - const SCEVHandle &operator=(const SCEVHandle &RHS) { - if (S != RHS.S) { - S = RHS.S; - } - return *this; - } - }; - - template struct simplify_type; - template<> struct simplify_type { - typedef const SCEV* SimpleType; - static SimpleType getSimplifiedValue(const SCEVHandle &Node) { - return Node; - } - }; - template<> struct simplify_type - : public simplify_type {}; - - // Specialize DenseMapInfo for SCEVHandle so that SCEVHandle may be used - // as a key in DenseMaps. - template<> - struct DenseMapInfo { - static inline SCEVHandle getEmptyKey() { - static SCEVCouldNotCompute Empty(0); - return &Empty; - } - static inline SCEVHandle getTombstoneKey() { - static SCEVCouldNotCompute Tombstone(0); - return &Tombstone; - } - static unsigned getHashValue(const SCEVHandle &Val) { - return DenseMapInfo::getHashValue(Val); - } - static bool isEqual(const SCEVHandle &LHS, const SCEVHandle &RHS) { - return LHS == RHS; - } - static bool isPod() { return false; } - }; - /// ScalarEvolution - This class is the main scalar evolution driver. Because /// client code (intentionally) can't do much with the SCEV objects directly, /// they must ask this class for services. @@ -251,11 +180,11 @@ /// CouldNotCompute - This SCEV is used to represent unknown trip /// counts and things. - SCEVHandle CouldNotCompute; + const SCEV* CouldNotCompute; /// Scalars - This is a cache of the scalars we have analyzed so far. /// - std::map Scalars; + std::map Scalars; /// BackedgeTakenInfo - Information about the backedge-taken count /// of a loop. This currently inclues an exact count and a maximum count. @@ -263,19 +192,16 @@ struct BackedgeTakenInfo { /// Exact - An expression indicating the exact backedge-taken count of /// the loop if it is known, or a SCEVCouldNotCompute otherwise. - SCEVHandle Exact; + const SCEV* Exact; /// Exact - An expression indicating the least maximum backedge-taken /// count of the loop that is known, or a SCEVCouldNotCompute. - SCEVHandle Max; - - /*implicit*/ BackedgeTakenInfo(SCEVHandle exact) : - Exact(exact), Max(exact) {} + const SCEV* Max; - /*implicit*/ BackedgeTakenInfo(const SCEV *exact) : + /*implicit*/ BackedgeTakenInfo(const SCEV* exact) : Exact(exact), Max(exact) {} - BackedgeTakenInfo(SCEVHandle exact, SCEVHandle max) : + BackedgeTakenInfo(const SCEV* exact, const SCEV* max) : Exact(exact), Max(max) {} /// hasAnyInfo - Test whether this BackedgeTakenInfo contains any @@ -305,30 +231,30 @@ /// createSCEV - We know that there is no SCEV for the specified value. /// Analyze the expression. - SCEVHandle createSCEV(Value *V); + const SCEV* createSCEV(Value *V); /// createNodeForPHI - Provide the special handling we need to analyze PHI /// SCEVs. - SCEVHandle createNodeForPHI(PHINode *PN); + const SCEV* createNodeForPHI(PHINode *PN); /// createNodeForGEP - Provide the special handling we need to analyze GEP /// SCEVs. - SCEVHandle createNodeForGEP(User *GEP); + const SCEV* createNodeForGEP(User *GEP); /// ReplaceSymbolicValueWithConcrete - This looks up the computed SCEV value /// for the specified instruction and replaces any references to the /// symbolic value SymName with the specified value. This is used during /// PHI resolution. void ReplaceSymbolicValueWithConcrete(Instruction *I, - const SCEVHandle &SymName, - const SCEVHandle &NewVal); + const SCEV* SymName, + const SCEV* NewVal); /// getBECount - Subtract the end and start values and divide by the step, /// rounding up, to get the number of times the backedge is executed. Return /// CouldNotCompute if an intermediate computation overflows. - SCEVHandle getBECount(const SCEVHandle &Start, - const SCEVHandle &End, - const SCEVHandle &Step); + const SCEV* getBECount(const SCEV* Start, + const SCEV* End, + const SCEV* Step); /// getBackedgeTakenInfo - Return the BackedgeTakenInfo for the given /// loop, lazily computing new values if the loop hasn't been analyzed @@ -366,7 +292,7 @@ /// ComputeLoadConstantCompareBackedgeTakenCount - Given an exit condition /// of 'icmp op load X, cst', try to see if we can compute the trip count. - SCEVHandle + const SCEV* ComputeLoadConstantCompareBackedgeTakenCount(LoadInst *LI, Constant *RHS, const Loop *L, @@ -377,18 +303,18 @@ /// try to evaluate a few iterations of the loop until we get the exit /// condition gets a value of ExitWhen (true or false). If we cannot /// evaluate the trip count of the loop, return CouldNotCompute. - SCEVHandle ComputeBackedgeTakenCountExhaustively(const Loop *L, Value *Cond, + const SCEV* ComputeBackedgeTakenCountExhaustively(const Loop *L, Value *Cond, bool ExitWhen); /// HowFarToZero - Return the number of times a backedge comparing the /// specified value to zero will execute. If not computable, return /// CouldNotCompute. - SCEVHandle HowFarToZero(const SCEV *V, const Loop *L); + const SCEV* HowFarToZero(const SCEV *V, const Loop *L); /// HowFarToNonZero - Return the number of times a backedge checking the /// specified value for nonzero will execute. If not computable, return /// CouldNotCompute. - SCEVHandle HowFarToNonZero(const SCEV *V, const Loop *L); + const SCEV* HowFarToNonZero(const SCEV *V, const Loop *L); /// HowManyLessThans - Return the number of times a backedge containing the /// specified less-than comparison will execute. If not computable, return @@ -440,115 +366,115 @@ /// getSCEV - Return a SCEV expression handle for the full generality of the /// specified expression. - SCEVHandle getSCEV(Value *V); + const SCEV* getSCEV(Value *V); - SCEVHandle getConstant(ConstantInt *V); - SCEVHandle getConstant(const APInt& Val); - SCEVHandle getConstant(const Type *Ty, uint64_t V, bool isSigned = false); - SCEVHandle getTruncateExpr(const SCEVHandle &Op, const Type *Ty); - SCEVHandle getZeroExtendExpr(const SCEVHandle &Op, const Type *Ty); - SCEVHandle getSignExtendExpr(const SCEVHandle &Op, const Type *Ty); - SCEVHandle getAnyExtendExpr(const SCEVHandle &Op, const Type *Ty); - SCEVHandle getAddExpr(SmallVectorImpl &Ops); - SCEVHandle getAddExpr(const SCEVHandle &LHS, const SCEVHandle &RHS) { - SmallVector Ops; + const SCEV* getConstant(ConstantInt *V); + const SCEV* getConstant(const APInt& Val); + const SCEV* getConstant(const Type *Ty, uint64_t V, bool isSigned = false); + const SCEV* getTruncateExpr(const SCEV* Op, const Type *Ty); + const SCEV* getZeroExtendExpr(const SCEV* Op, const Type *Ty); + const SCEV* getSignExtendExpr(const SCEV* Op, const Type *Ty); + const SCEV* getAnyExtendExpr(const SCEV* Op, const Type *Ty); + const SCEV* getAddExpr(SmallVectorImpl &Ops); + const SCEV* getAddExpr(const SCEV* LHS, const SCEV* RHS) { + SmallVector Ops; Ops.push_back(LHS); Ops.push_back(RHS); return getAddExpr(Ops); } - SCEVHandle getAddExpr(const SCEVHandle &Op0, const SCEVHandle &Op1, - const SCEVHandle &Op2) { - SmallVector Ops; + const SCEV* getAddExpr(const SCEV* Op0, const SCEV* Op1, + const SCEV* Op2) { + SmallVector Ops; Ops.push_back(Op0); Ops.push_back(Op1); Ops.push_back(Op2); return getAddExpr(Ops); } - SCEVHandle getMulExpr(SmallVectorImpl &Ops); - SCEVHandle getMulExpr(const SCEVHandle &LHS, const SCEVHandle &RHS) { - SmallVector Ops; + const SCEV* getMulExpr(SmallVectorImpl &Ops); + const SCEV* getMulExpr(const SCEV* LHS, const SCEV* RHS) { + SmallVector Ops; Ops.push_back(LHS); Ops.push_back(RHS); return getMulExpr(Ops); } - SCEVHandle getUDivExpr(const SCEVHandle &LHS, const SCEVHandle &RHS); - SCEVHandle getAddRecExpr(const SCEVHandle &Start, const SCEVHandle &Step, + const SCEV* getUDivExpr(const SCEV* LHS, const SCEV* RHS); + const SCEV* getAddRecExpr(const SCEV* Start, const SCEV* Step, const Loop *L); - SCEVHandle getAddRecExpr(SmallVectorImpl &Operands, + const SCEV* getAddRecExpr(SmallVectorImpl &Operands, const Loop *L); - SCEVHandle getAddRecExpr(const SmallVectorImpl &Operands, + const SCEV* getAddRecExpr(const SmallVectorImpl &Operands, const Loop *L) { - SmallVector NewOp(Operands.begin(), Operands.end()); + SmallVector NewOp(Operands.begin(), Operands.end()); return getAddRecExpr(NewOp, L); } - SCEVHandle getSMaxExpr(const SCEVHandle &LHS, const SCEVHandle &RHS); - SCEVHandle getSMaxExpr(SmallVectorImpl &Operands); - SCEVHandle getUMaxExpr(const SCEVHandle &LHS, const SCEVHandle &RHS); - SCEVHandle getUMaxExpr(SmallVectorImpl &Operands); - SCEVHandle getSMinExpr(const SCEVHandle &LHS, const SCEVHandle &RHS); - SCEVHandle getUMinExpr(const SCEVHandle &LHS, const SCEVHandle &RHS); - SCEVHandle getUnknown(Value *V); - SCEVHandle getCouldNotCompute(); + const SCEV* getSMaxExpr(const SCEV* LHS, const SCEV* RHS); + const SCEV* getSMaxExpr(SmallVectorImpl &Operands); + const SCEV* getUMaxExpr(const SCEV* LHS, const SCEV* RHS); + const SCEV* getUMaxExpr(SmallVectorImpl &Operands); + const SCEV* getSMinExpr(const SCEV* LHS, const SCEV* RHS); + const SCEV* getUMinExpr(const SCEV* LHS, const SCEV* RHS); + const SCEV* getUnknown(Value *V); + const SCEV* getCouldNotCompute(); /// getNegativeSCEV - Return the SCEV object corresponding to -V. /// - SCEVHandle getNegativeSCEV(const SCEVHandle &V); + const SCEV* getNegativeSCEV(const SCEV* V); /// getNotSCEV - Return the SCEV object corresponding to ~V. /// - SCEVHandle getNotSCEV(const SCEVHandle &V); + const SCEV* getNotSCEV(const SCEV* V); /// getMinusSCEV - Return LHS-RHS. /// - SCEVHandle getMinusSCEV(const SCEVHandle &LHS, - const SCEVHandle &RHS); + const SCEV* getMinusSCEV(const SCEV* LHS, + const SCEV* RHS); /// getTruncateOrZeroExtend - Return a SCEV corresponding to a conversion /// of the input value to the specified type. If the type must be /// extended, it is zero extended. - SCEVHandle getTruncateOrZeroExtend(const SCEVHandle &V, const Type *Ty); + const SCEV* getTruncateOrZeroExtend(const SCEV* V, const Type *Ty); /// getTruncateOrSignExtend - Return a SCEV corresponding to a conversion /// of the input value to the specified type. If the type must be /// extended, it is sign extended. - SCEVHandle getTruncateOrSignExtend(const SCEVHandle &V, const Type *Ty); + const SCEV* getTruncateOrSignExtend(const SCEV* V, const Type *Ty); /// getNoopOrZeroExtend - Return a SCEV corresponding to a conversion of /// the input value to the specified type. If the type must be extended, /// it is zero extended. The conversion must not be narrowing. - SCEVHandle getNoopOrZeroExtend(const SCEVHandle &V, const Type *Ty); + const SCEV* getNoopOrZeroExtend(const SCEV* V, const Type *Ty); /// getNoopOrSignExtend - Return a SCEV corresponding to a conversion of /// the input value to the specified type. If the type must be extended, /// it is sign extended. The conversion must not be narrowing. - SCEVHandle getNoopOrSignExtend(const SCEVHandle &V, const Type *Ty); + const SCEV* getNoopOrSignExtend(const SCEV* V, const Type *Ty); /// getNoopOrAnyExtend - Return a SCEV corresponding to a conversion of /// the input value to the specified type. If the type must be extended, /// it is extended with unspecified bits. The conversion must not be /// narrowing. - SCEVHandle getNoopOrAnyExtend(const SCEVHandle &V, const Type *Ty); + const SCEV* getNoopOrAnyExtend(const SCEV* V, const Type *Ty); /// getTruncateOrNoop - Return a SCEV corresponding to a conversion of the /// input value to the specified type. The conversion must not be /// widening. - SCEVHandle getTruncateOrNoop(const SCEVHandle &V, const Type *Ty); + const SCEV* getTruncateOrNoop(const SCEV* V, const Type *Ty); /// getIntegerSCEV - Given an integer or FP type, create a constant for the /// specified signed integer value and return a SCEV for the constant. - SCEVHandle getIntegerSCEV(int Val, const Type *Ty); + const SCEV* getIntegerSCEV(int Val, const Type *Ty); /// getUMaxFromMismatchedTypes - Promote the operands to the wider of /// the types using zero-extension, and then perform a umax operation /// with them. - SCEVHandle getUMaxFromMismatchedTypes(const SCEVHandle &LHS, - const SCEVHandle &RHS); + const SCEV* getUMaxFromMismatchedTypes(const SCEV* LHS, + const SCEV* RHS); /// getUMinFromMismatchedTypes - Promote the operands to the wider of /// the types using zero-extension, and then perform a umin operation /// with them. - SCEVHandle getUMinFromMismatchedTypes(const SCEVHandle &LHS, - const SCEVHandle &RHS); + const SCEV* getUMinFromMismatchedTypes(const SCEV* LHS, + const SCEV* RHS); /// hasSCEV - Return true if the SCEV for this value has already been /// computed. @@ -556,7 +482,7 @@ /// setSCEV - Insert the specified SCEV into the map of current SCEVs for /// the specified value. - void setSCEV(Value *V, const SCEVHandle &H); + void setSCEV(Value *V, const SCEV* H); /// getSCEVAtScope - Return a SCEV expression handle for the specified value /// at the specified scope in the program. The L value specifies a loop @@ -568,11 +494,11 @@ /// /// In the case that a relevant loop exit value cannot be computed, the /// original value V is returned. - SCEVHandle getSCEVAtScope(const SCEV *S, const Loop *L); + const SCEV* getSCEVAtScope(const SCEV *S, const Loop *L); /// getSCEVAtScope - This is a convenience function which does /// getSCEVAtScope(getSCEV(V), L). - SCEVHandle getSCEVAtScope(Value *V, const Loop *L); + const SCEV* getSCEVAtScope(Value *V, const Loop *L); /// isLoopGuardedByCond - Test whether entry to the loop is protected by /// a conditional between LHS and RHS. This is used to help avoid max @@ -591,12 +517,12 @@ /// loop-invariant backedge-taken count (see /// hasLoopInvariantBackedgeTakenCount). /// - SCEVHandle getBackedgeTakenCount(const Loop *L); + const SCEV* getBackedgeTakenCount(const Loop *L); /// getMaxBackedgeTakenCount - Similar to getBackedgeTakenCount, except /// return the least SCEV value that is known never to be less than the /// actual backedge taken count. - SCEVHandle getMaxBackedgeTakenCount(const Loop *L); + const SCEV* getMaxBackedgeTakenCount(const Loop *L); /// hasLoopInvariantBackedgeTakenCount - Return true if the specified loop /// has an analyzable loop-invariant backedge-taken count. @@ -612,15 +538,15 @@ /// guaranteed to end in (at every loop iteration). It is, at the same time, /// the minimum number of times S is divisible by 2. For example, given {4,+,8} /// it returns 2. If S is guaranteed to be 0, it returns the bitwidth of S. - uint32_t GetMinTrailingZeros(const SCEVHandle &S); + uint32_t GetMinTrailingZeros(const SCEV* S); /// GetMinLeadingZeros - Determine the minimum number of zero bits that S is /// guaranteed to begin with (at every loop iteration). - uint32_t GetMinLeadingZeros(const SCEVHandle &S); + uint32_t GetMinLeadingZeros(const SCEV* S); /// GetMinSignBits - Determine the minimum number of sign bits that S is /// guaranteed to begin with. - uint32_t GetMinSignBits(const SCEVHandle &S); + uint32_t GetMinSignBits(const SCEV* S); virtual bool runOnFunction(Function &F); virtual void releaseMemory(); Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h?rev=73906&r1=73905&r2=73906&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h Mon Jun 22 16:39:50 2009 @@ -28,7 +28,7 @@ /// memory. struct SCEVExpander : public SCEVVisitor { ScalarEvolution &SE; - std::map > InsertedExpressions; + std::map > InsertedExpressions; std::set InsertedValues; BasicBlock::iterator InsertPt; @@ -77,12 +77,12 @@ /// expression into the program. The inserted code is inserted into the /// SCEVExpander's current insertion point. If a type is specified, the /// result will be expanded to have that type, with a cast if necessary. - Value *expandCodeFor(SCEVHandle SH, const Type *Ty = 0); + Value *expandCodeFor(const SCEV* SH, const Type *Ty = 0); /// expandCodeFor - Insert code to directly compute the specified SCEV /// expression into the program. The inserted code is inserted into the /// specified block. - Value *expandCodeFor(SCEVHandle SH, const Type *Ty, + Value *expandCodeFor(const SCEV* SH, const Type *Ty, BasicBlock::iterator IP) { setInsertionPoint(IP); return expandCodeFor(SH, Ty); @@ -105,7 +105,8 @@ private: /// expandAddToGEP - Expand a SCEVAddExpr with a pointer type into a GEP /// instead of using ptrtoint+arithmetic+inttoptr. - Value *expandAddToGEP(const SCEVHandle *op_begin, const SCEVHandle *op_end, + Value *expandAddToGEP(const SCEV* const *op_begin, + const SCEV* const *op_end, const PointerType *PTy, const Type *Ty, Value *V); Value *expand(const SCEV *S); Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h?rev=73906&r1=73905&r2=73906&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h Mon Jun 22 16:39:50 2009 @@ -51,8 +51,8 @@ virtual const Type *getType() const; - SCEVHandle replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, - const SCEVHandle &Conc, + const SCEV* replaceSymbolicValuesWithConcrete(const SCEV* Sym, + const SCEV* Conc, ScalarEvolution &SE) const { return this; } @@ -75,15 +75,15 @@ /// class SCEVCastExpr : public SCEV { protected: - SCEVHandle Op; + const SCEV* Op; const Type *Ty; - SCEVCastExpr(unsigned SCEVTy, const SCEVHandle &op, const Type *ty, + SCEVCastExpr(unsigned SCEVTy, const SCEV* op, const Type *ty, const ScalarEvolution* p); virtual ~SCEVCastExpr(); public: - const SCEVHandle &getOperand() const { return Op; } + const SCEV* getOperand() const { return Op; } virtual const Type *getType() const { return Ty; } virtual bool isLoopInvariant(const Loop *L) const { @@ -112,14 +112,14 @@ class SCEVTruncateExpr : public SCEVCastExpr { friend class ScalarEvolution; - SCEVTruncateExpr(const SCEVHandle &op, const Type *ty, + SCEVTruncateExpr(const SCEV* op, const Type *ty, const ScalarEvolution* p); public: - SCEVHandle replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, - const SCEVHandle &Conc, + const SCEV* replaceSymbolicValuesWithConcrete(const SCEV* Sym, + const SCEV* Conc, ScalarEvolution &SE) const { - SCEVHandle H = Op->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); + const SCEV* H = Op->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); if (H == Op) return this; return SE.getTruncateExpr(H, Ty); @@ -141,14 +141,14 @@ class SCEVZeroExtendExpr : public SCEVCastExpr { friend class ScalarEvolution; - SCEVZeroExtendExpr(const SCEVHandle &op, const Type *ty, + SCEVZeroExtendExpr(const SCEV* op, const Type *ty, const ScalarEvolution* p); public: - SCEVHandle replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, - const SCEVHandle &Conc, + const SCEV* replaceSymbolicValuesWithConcrete(const SCEV* Sym, + const SCEV* Conc, ScalarEvolution &SE) const { - SCEVHandle H = Op->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); + const SCEV* H = Op->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); if (H == Op) return this; return SE.getZeroExtendExpr(H, Ty); @@ -170,14 +170,14 @@ class SCEVSignExtendExpr : public SCEVCastExpr { friend class ScalarEvolution; - SCEVSignExtendExpr(const SCEVHandle &op, const Type *ty, + SCEVSignExtendExpr(const SCEV* op, const Type *ty, const ScalarEvolution* p); public: - SCEVHandle replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, - const SCEVHandle &Conc, + const SCEV* replaceSymbolicValuesWithConcrete(const SCEV* Sym, + const SCEV* Conc, ScalarEvolution &SE) const { - SCEVHandle H = Op->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); + const SCEV* H = Op->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); if (H == Op) return this; return SE.getSignExtendExpr(H, Ty); @@ -199,22 +199,22 @@ /// class SCEVNAryExpr : public SCEV { protected: - SmallVector Operands; + SmallVector Operands; - SCEVNAryExpr(enum SCEVTypes T, const SmallVectorImpl &ops, + SCEVNAryExpr(enum SCEVTypes T, const SmallVectorImpl &ops, const ScalarEvolution* p) : SCEV(T, p), Operands(ops.begin(), ops.end()) {} virtual ~SCEVNAryExpr() {} public: unsigned getNumOperands() const { return (unsigned)Operands.size(); } - const SCEVHandle &getOperand(unsigned i) const { + const SCEV* getOperand(unsigned i) const { assert(i < Operands.size() && "Operand index out of range!"); return Operands[i]; } - const SmallVectorImpl &getOperands() const { return Operands; } - typedef SmallVectorImpl::const_iterator op_iterator; + const SmallVectorImpl &getOperands() const { return Operands; } + typedef SmallVectorImpl::const_iterator op_iterator; op_iterator op_begin() const { return Operands.begin(); } op_iterator op_end() const { return Operands.end(); } @@ -261,13 +261,13 @@ class SCEVCommutativeExpr : public SCEVNAryExpr { protected: SCEVCommutativeExpr(enum SCEVTypes T, - const SmallVectorImpl &ops, + const SmallVectorImpl &ops, const ScalarEvolution* p) : SCEVNAryExpr(T, ops, p) {} public: - SCEVHandle replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, - const SCEVHandle &Conc, + const SCEV* replaceSymbolicValuesWithConcrete(const SCEV* Sym, + const SCEV* Conc, ScalarEvolution &SE) const; virtual const char *getOperationStr() const = 0; @@ -291,7 +291,7 @@ class SCEVAddExpr : public SCEVCommutativeExpr { friend class ScalarEvolution; - explicit SCEVAddExpr(const SmallVectorImpl &ops, + explicit SCEVAddExpr(const SmallVectorImpl &ops, const ScalarEvolution* p) : SCEVCommutativeExpr(scAddExpr, ops, p) { } @@ -312,7 +312,7 @@ class SCEVMulExpr : public SCEVCommutativeExpr { friend class ScalarEvolution; - explicit SCEVMulExpr(const SmallVectorImpl &ops, + explicit SCEVMulExpr(const SmallVectorImpl &ops, const ScalarEvolution* p) : SCEVCommutativeExpr(scMulExpr, ops, p) { } @@ -334,14 +334,15 @@ class SCEVUDivExpr : public SCEV { friend class ScalarEvolution; - SCEVHandle LHS, RHS; - SCEVUDivExpr(const SCEVHandle &lhs, const SCEVHandle &rhs, + const SCEV* LHS; + const SCEV* RHS; + SCEVUDivExpr(const SCEV* lhs, const SCEV* rhs, const ScalarEvolution* p) : SCEV(scUDivExpr, p), LHS(lhs), RHS(rhs) {} public: - const SCEVHandle &getLHS() const { return LHS; } - const SCEVHandle &getRHS() const { return RHS; } + const SCEV* getLHS() const { return LHS; } + const SCEV* getRHS() const { return RHS; } virtual bool isLoopInvariant(const Loop *L) const { return LHS->isLoopInvariant(L) && RHS->isLoopInvariant(L); @@ -352,11 +353,11 @@ RHS->hasComputableLoopEvolution(L); } - SCEVHandle replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, - const SCEVHandle &Conc, + const SCEV* replaceSymbolicValuesWithConcrete(const SCEV* Sym, + const SCEV* Conc, ScalarEvolution &SE) const { - SCEVHandle L = LHS->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); - SCEVHandle R = RHS->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); + const SCEV* L = LHS->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); + const SCEV* R = RHS->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); if (L == LHS && R == RHS) return this; else @@ -391,7 +392,7 @@ const Loop *L; - SCEVAddRecExpr(const SmallVectorImpl &ops, const Loop *l, + SCEVAddRecExpr(const SmallVectorImpl &ops, const Loop *l, const ScalarEvolution* p) : SCEVNAryExpr(scAddRecExpr, ops, p), L(l) { for (size_t i = 0, e = Operands.size(); i != e; ++i) @@ -400,15 +401,15 @@ } public: - const SCEVHandle &getStart() const { return Operands[0]; } + const SCEV* getStart() const { return Operands[0]; } const Loop *getLoop() const { return L; } /// getStepRecurrence - This method constructs and returns the recurrence /// indicating how much this expression steps by. If this is a polynomial /// of degree N, it returns a chrec of degree N-1. - SCEVHandle getStepRecurrence(ScalarEvolution &SE) const { + const SCEV* getStepRecurrence(ScalarEvolution &SE) const { if (isAffine()) return getOperand(1); - return SE.getAddRecExpr(SmallVector(op_begin()+1,op_end()), + return SE.getAddRecExpr(SmallVector(op_begin()+1,op_end()), getLoop()); } @@ -436,7 +437,7 @@ /// evaluateAtIteration - Return the value of this chain of recurrences at /// the specified iteration number. - SCEVHandle evaluateAtIteration(SCEVHandle It, ScalarEvolution &SE) const; + const SCEV* evaluateAtIteration(const SCEV* It, ScalarEvolution &SE) const; /// getNumIterationsInRange - Return the number of iterations of this loop /// that produce values in the specified constant range. Another way of @@ -444,11 +445,11 @@ /// value is not in the condition, thus computing the exit count. If the /// iteration count can't be computed, an instance of SCEVCouldNotCompute is /// returned. - SCEVHandle getNumIterationsInRange(ConstantRange Range, + const SCEV* getNumIterationsInRange(ConstantRange Range, ScalarEvolution &SE) const; - SCEVHandle replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, - const SCEVHandle &Conc, + const SCEV* replaceSymbolicValuesWithConcrete(const SCEV* Sym, + const SCEV* Conc, ScalarEvolution &SE) const; virtual void print(raw_ostream &OS) const; @@ -467,7 +468,7 @@ class SCEVSMaxExpr : public SCEVCommutativeExpr { friend class ScalarEvolution; - explicit SCEVSMaxExpr(const SmallVectorImpl &ops, + explicit SCEVSMaxExpr(const SmallVectorImpl &ops, const ScalarEvolution* p) : SCEVCommutativeExpr(scSMaxExpr, ops, p) { } @@ -489,7 +490,7 @@ class SCEVUMaxExpr : public SCEVCommutativeExpr { friend class ScalarEvolution; - explicit SCEVUMaxExpr(const SmallVectorImpl &ops, + explicit SCEVUMaxExpr(const SmallVectorImpl &ops, const ScalarEvolution* p) : SCEVCommutativeExpr(scUMaxExpr, ops, p) { } @@ -525,8 +526,8 @@ return false; // not computable } - SCEVHandle replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, - const SCEVHandle &Conc, + const SCEV* replaceSymbolicValuesWithConcrete(const SCEV* Sym, + const SCEV* Conc, ScalarEvolution &SE) const { if (&*Sym == this) return Conc; return this; Modified: llvm/trunk/lib/Analysis/IVUsers.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IVUsers.cpp?rev=73906&r1=73905&r2=73906&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IVUsers.cpp (original) +++ llvm/trunk/lib/Analysis/IVUsers.cpp Mon Jun 22 16:39:50 2009 @@ -39,7 +39,7 @@ /// containsAddRecFromDifferentLoop - Determine whether expression S involves a /// subexpression that is an AddRec from a loop other than L. An outer loop /// of L is OK, but not an inner loop nor a disjoint loop. -static bool containsAddRecFromDifferentLoop(SCEVHandle S, Loop *L) { +static bool containsAddRecFromDifferentLoop(const SCEV* S, Loop *L) { // This is very common, put it first. if (isa(S)) return false; @@ -80,10 +80,10 @@ /// a mix of loop invariant and loop variant expressions. The start cannot, /// however, contain an AddRec from a different loop, unless that loop is an /// outer loop of the current loop. -static bool getSCEVStartAndStride(const SCEVHandle &SH, Loop *L, Loop *UseLoop, - SCEVHandle &Start, SCEVHandle &Stride, +static bool getSCEVStartAndStride(const SCEV* &SH, Loop *L, Loop *UseLoop, + const SCEV* &Start, const SCEV* &Stride, ScalarEvolution *SE, DominatorTree *DT) { - SCEVHandle TheAddRec = Start; // Initialize to zero. + const SCEV* TheAddRec = Start; // Initialize to zero. // If the outer level is an AddExpr, the operands are all start values except // for a nested AddRecExpr. @@ -109,9 +109,9 @@ // Use getSCEVAtScope to attempt to simplify other loops out of // the picture. - SCEVHandle AddRecStart = AddRec->getStart(); + const SCEV* AddRecStart = AddRec->getStart(); AddRecStart = SE->getSCEVAtScope(AddRecStart, UseLoop); - SCEVHandle AddRecStride = AddRec->getStepRecurrence(*SE); + const SCEV* AddRecStride = AddRec->getStepRecurrence(*SE); // FIXME: If Start contains an SCEVAddRecExpr from a different loop, other // than an outer loop of the current loop, reject it. LSR has no concept of @@ -196,13 +196,13 @@ return true; // Instruction already handled. // Get the symbolic expression for this instruction. - SCEVHandle ISE = SE->getSCEV(I); + const SCEV* ISE = SE->getSCEV(I); if (isa(ISE)) return false; // Get the start and stride for this expression. Loop *UseLoop = LI->getLoopFor(I->getParent()); - SCEVHandle Start = SE->getIntegerSCEV(0, ISE->getType()); - SCEVHandle Stride = Start; + const SCEV* Start = SE->getIntegerSCEV(0, ISE->getType()); + const SCEV* Stride = Start; if (!getSCEVStartAndStride(ISE, L, UseLoop, Start, Stride, SE, DT)) return false; // Non-reducible symbolic expression, bail out. @@ -254,7 +254,7 @@ if (IVUseShouldUsePostIncValue(User, I, L, LI, DT, this)) { // The value used will be incremented by the stride more than we are // expecting, so subtract this off. - SCEVHandle NewStart = SE->getMinusSCEV(Start, Stride); + const SCEV* NewStart = SE->getMinusSCEV(Start, Stride); StrideUses->addUser(NewStart, User, I); StrideUses->Users.back().setIsUseOfPostIncrementedValue(true); DOUT << " USING POSTINC SCEV, START=" << *NewStart<< "\n"; @@ -295,9 +295,9 @@ /// getReplacementExpr - Return a SCEV expression which computes the /// value of the OperandValToReplace of the given IVStrideUse. -SCEVHandle IVUsers::getReplacementExpr(const IVStrideUse &U) const { +const SCEV* IVUsers::getReplacementExpr(const IVStrideUse &U) const { // Start with zero. - SCEVHandle RetVal = SE->getIntegerSCEV(0, U.getParent()->Stride->getType()); + const SCEV* RetVal = SE->getIntegerSCEV(0, U.getParent()->Stride->getType()); // Create the basic add recurrence. RetVal = SE->getAddRecExpr(RetVal, U.getParent()->Stride, L); // Add the offset in a separate step, because it may be loop-variant. @@ -308,7 +308,7 @@ RetVal = SE->getAddExpr(RetVal, U.getParent()->Stride); // Evaluate the expression out of the loop, if possible. if (!L->contains(U.getUser()->getParent())) { - SCEVHandle ExitVal = SE->getSCEVAtScope(RetVal, L->getParentLoop()); + const SCEV* ExitVal = SE->getSCEVAtScope(RetVal, L->getParentLoop()); if (ExitVal->isLoopInvariant(L)) RetVal = ExitVal; } @@ -325,7 +325,7 @@ OS << ":\n"; for (unsigned Stride = 0, e = StrideOrder.size(); Stride != e; ++Stride) { - std::map::const_iterator SI = + std::map::const_iterator SI = IVUsesByStride.find(StrideOrder[Stride]); assert(SI != IVUsesByStride.end() && "Stride doesn't exist!"); OS << " Stride " << *SI->first->getType() << " " << *SI->first << ":\n"; Modified: llvm/trunk/lib/Analysis/LoopVR.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopVR.cpp?rev=73906&r1=73905&r2=73906&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LoopVR.cpp (original) +++ llvm/trunk/lib/Analysis/LoopVR.cpp Mon Jun 22 16:39:50 2009 @@ -26,8 +26,8 @@ static RegisterPass X("loopvr", "Loop Value Ranges", false, true); /// getRange - determine the range for a particular SCEV within a given Loop -ConstantRange LoopVR::getRange(SCEVHandle S, Loop *L, ScalarEvolution &SE) { - SCEVHandle T = SE.getBackedgeTakenCount(L); +ConstantRange LoopVR::getRange(const SCEV* S, Loop *L, ScalarEvolution &SE) { + const SCEV* T = SE.getBackedgeTakenCount(L); if (isa(T)) return ConstantRange(cast(S->getType())->getBitWidth(), true); @@ -36,7 +36,7 @@ } /// getRange - determine the range for a particular SCEV with a given trip count -ConstantRange LoopVR::getRange(SCEVHandle S, SCEVHandle T, ScalarEvolution &SE){ +ConstantRange LoopVR::getRange(const SCEV* S, const SCEV* T, ScalarEvolution &SE){ if (const SCEVConstant *C = dyn_cast(S)) return ConstantRange(C->getValue()->getValue()); @@ -182,8 +182,8 @@ if (!Trip) return FullSet; if (AddRec->isAffine()) { - SCEVHandle StartHandle = AddRec->getStart(); - SCEVHandle StepHandle = AddRec->getOperand(1); + const SCEV* StartHandle = AddRec->getStart(); + const SCEV* StepHandle = AddRec->getOperand(1); const SCEVConstant *Step = dyn_cast(StepHandle); if (!Step) return FullSet; @@ -194,7 +194,7 @@ if ((TripExt * StepExt).ugt(APInt::getLowBitsSet(ExWidth, ExWidth >> 1))) return FullSet; - SCEVHandle EndHandle = SE.getAddExpr(StartHandle, + const SCEV* EndHandle = SE.getAddExpr(StartHandle, SE.getMulExpr(T, StepHandle)); const SCEVConstant *Start = dyn_cast(StartHandle); const SCEVConstant *End = dyn_cast(EndHandle); @@ -254,7 +254,7 @@ ScalarEvolution &SE = getAnalysis(); - SCEVHandle S = SE.getSCEV(I); + const SCEV* S = SE.getSCEV(I); if (isa(S) || isa(S)) return ConstantRange(cast(V->getType())->getBitWidth(), false); Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=73906&r1=73905&r2=73906&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Jun 22 16:39:50 2009 @@ -14,7 +14,7 @@ // There are several aspects to this library. First is the representation of // scalar expressions, which are represented as subclasses of the SCEV class. // These classes are used to represent certain types of subexpressions that we -// can handle. These classes are reference counted, managed by the SCEVHandle +// can handle. These classes are reference counted, managed by the const SCEV* // class. We only create one SCEV of a particular shape, so pointer-comparisons // for equality are legal. // @@ -152,9 +152,9 @@ return false; } -SCEVHandle SCEVCouldNotCompute:: -replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, - const SCEVHandle &Conc, +const SCEV* SCEVCouldNotCompute:: +replaceSymbolicValuesWithConcrete(const SCEV* Sym, + const SCEV* Conc, ScalarEvolution &SE) const { return this; } @@ -169,20 +169,20 @@ // SCEVConstants - Only allow the creation of one SCEVConstant for any -// particular value. Don't use a SCEVHandle here, or else the object will +// particular value. Don't use a const SCEV* here, or else the object will // never be deleted! -SCEVHandle ScalarEvolution::getConstant(ConstantInt *V) { +const SCEV* ScalarEvolution::getConstant(ConstantInt *V) { SCEVConstant *&R = SCEVConstants[V]; if (R == 0) R = new SCEVConstant(V, this); return R; } -SCEVHandle ScalarEvolution::getConstant(const APInt& Val) { +const SCEV* ScalarEvolution::getConstant(const APInt& Val) { return getConstant(ConstantInt::get(Val)); } -SCEVHandle +const SCEV* ScalarEvolution::getConstant(const Type *Ty, uint64_t V, bool isSigned) { return getConstant(ConstantInt::get(cast(Ty), V, isSigned)); } @@ -194,7 +194,7 @@ } SCEVCastExpr::SCEVCastExpr(unsigned SCEVTy, - const SCEVHandle &op, const Type *ty, + const SCEV* op, const Type *ty, const ScalarEvolution* p) : SCEV(SCEVTy, p), Op(op), Ty(ty) {} @@ -205,10 +205,10 @@ } // SCEVTruncates - Only allow the creation of one SCEVTruncateExpr for any -// particular input. Don't use a SCEVHandle here, or else the object will +// particular input. Don't use a const SCEV* here, or else the object will // never be deleted! -SCEVTruncateExpr::SCEVTruncateExpr(const SCEVHandle &op, const Type *ty, +SCEVTruncateExpr::SCEVTruncateExpr(const SCEV* op, const Type *ty, const ScalarEvolution* p) : SCEVCastExpr(scTruncate, op, ty, p) { assert((Op->getType()->isInteger() || isa(Op->getType())) && @@ -222,10 +222,10 @@ } // SCEVZeroExtends - Only allow the creation of one SCEVZeroExtendExpr for any -// particular input. Don't use a SCEVHandle here, or else the object will never +// particular input. Don't use a const SCEV* here, or else the object will never // be deleted! -SCEVZeroExtendExpr::SCEVZeroExtendExpr(const SCEVHandle &op, const Type *ty, +SCEVZeroExtendExpr::SCEVZeroExtendExpr(const SCEV* op, const Type *ty, const ScalarEvolution* p) : SCEVCastExpr(scZeroExtend, op, ty, p) { assert((Op->getType()->isInteger() || isa(Op->getType())) && @@ -238,10 +238,10 @@ } // SCEVSignExtends - Only allow the creation of one SCEVSignExtendExpr for any -// particular input. Don't use a SCEVHandle here, or else the object will never +// particular input. Don't use a const SCEV* here, or else the object will never // be deleted! -SCEVSignExtendExpr::SCEVSignExtendExpr(const SCEVHandle &op, const Type *ty, +SCEVSignExtendExpr::SCEVSignExtendExpr(const SCEV* op, const Type *ty, const ScalarEvolution* p) : SCEVCastExpr(scSignExtend, op, ty, p) { assert((Op->getType()->isInteger() || isa(Op->getType())) && @@ -254,7 +254,7 @@ } // SCEVCommExprs - Only allow the creation of one SCEVCommutativeExpr for any -// particular input. Don't use a SCEVHandle here, or else the object will never +// particular input. Don't use a const SCEV* here, or else the object will never // be deleted! void SCEVCommutativeExpr::print(raw_ostream &OS) const { @@ -266,15 +266,15 @@ OS << ")"; } -SCEVHandle SCEVCommutativeExpr:: -replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, - const SCEVHandle &Conc, +const SCEV* SCEVCommutativeExpr:: +replaceSymbolicValuesWithConcrete(const SCEV* Sym, + const SCEV* Conc, ScalarEvolution &SE) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { - SCEVHandle H = + const SCEV* H = getOperand(i)->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); if (H != getOperand(i)) { - SmallVector NewOps; + SmallVector NewOps; NewOps.reserve(getNumOperands()); for (unsigned j = 0; j != i; ++j) NewOps.push_back(getOperand(j)); @@ -308,7 +308,7 @@ // SCEVUDivs - Only allow the creation of one SCEVUDivExpr for any particular -// input. Don't use a SCEVHandle here, or else the object will never be +// input. Don't use a const SCEV* here, or else the object will never be // deleted! bool SCEVUDivExpr::dominates(BasicBlock *BB, DominatorTree *DT) const { @@ -329,18 +329,18 @@ } // SCEVAddRecExprs - Only allow the creation of one SCEVAddRecExpr for any -// particular input. Don't use a SCEVHandle here, or else the object will never +// particular input. Don't use a const SCEV* here, or else the object will never // be deleted! -SCEVHandle SCEVAddRecExpr:: -replaceSymbolicValuesWithConcrete(const SCEVHandle &Sym, - const SCEVHandle &Conc, +const SCEV* SCEVAddRecExpr:: +replaceSymbolicValuesWithConcrete(const SCEV* Sym, + const SCEV* Conc, ScalarEvolution &SE) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { - SCEVHandle H = + const SCEV* H = getOperand(i)->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); if (H != getOperand(i)) { - SmallVector NewOps; + SmallVector NewOps; NewOps.reserve(getNumOperands()); for (unsigned j = 0; j != i; ++j) NewOps.push_back(getOperand(j)); @@ -374,7 +374,7 @@ } // SCEVUnknowns - Only allow the creation of one SCEVUnknown for any particular -// value. Don't use a SCEVHandle here, or else the object will never be +// value. Don't use a const SCEV* here, or else the object will never be // deleted! bool SCEVUnknown::isLoopInvariant(const Loop *L) const { @@ -531,7 +531,7 @@ /// this to depend on where the addresses of various SCEV objects happened to /// land in memory. /// -static void GroupByComplexity(SmallVectorImpl &Ops, +static void GroupByComplexity(SmallVectorImpl &Ops, LoopInfo *LI) { if (Ops.size() < 2) return; // Noop if (Ops.size() == 2) { @@ -574,7 +574,7 @@ /// BinomialCoefficient - Compute BC(It, K). The result has width W. /// Assume, K > 0. -static SCEVHandle BinomialCoefficient(SCEVHandle It, unsigned K, +static const SCEV* BinomialCoefficient(const SCEV* It, unsigned K, ScalarEvolution &SE, const Type* ResultTy) { // Handle the simplest case efficiently. @@ -667,15 +667,15 @@ // Calculate the product, at width T+W const IntegerType *CalculationTy = IntegerType::get(CalculationBits); - SCEVHandle Dividend = SE.getTruncateOrZeroExtend(It, CalculationTy); + const SCEV* Dividend = SE.getTruncateOrZeroExtend(It, CalculationTy); for (unsigned i = 1; i != K; ++i) { - SCEVHandle S = SE.getMinusSCEV(It, SE.getIntegerSCEV(i, It->getType())); + const SCEV* S = SE.getMinusSCEV(It, SE.getIntegerSCEV(i, It->getType())); Dividend = SE.getMulExpr(Dividend, SE.getTruncateOrZeroExtend(S, CalculationTy)); } // Divide by 2^T - SCEVHandle DivResult = SE.getUDivExpr(Dividend, SE.getConstant(DivFactor)); + const SCEV* DivResult = SE.getUDivExpr(Dividend, SE.getConstant(DivFactor)); // Truncate the result, and divide by K! / 2^T. @@ -692,14 +692,14 @@ /// /// where BC(It, k) stands for binomial coefficient. /// -SCEVHandle SCEVAddRecExpr::evaluateAtIteration(SCEVHandle It, +const SCEV* SCEVAddRecExpr::evaluateAtIteration(const SCEV* It, ScalarEvolution &SE) const { - SCEVHandle Result = getStart(); + const SCEV* Result = getStart(); for (unsigned i = 1, e = getNumOperands(); i != e; ++i) { // The computation is correct in the face of overflow provided that the // multiplication is performed _after_ the evaluation of the binomial // coefficient. - SCEVHandle Coeff = BinomialCoefficient(It, i, SE, getType()); + const SCEV* Coeff = BinomialCoefficient(It, i, SE, getType()); if (isa(Coeff)) return Coeff; @@ -712,7 +712,7 @@ // SCEV Expression folder implementations //===----------------------------------------------------------------------===// -SCEVHandle ScalarEvolution::getTruncateExpr(const SCEVHandle &Op, +const SCEV* ScalarEvolution::getTruncateExpr(const SCEV* Op, const Type *Ty) { assert(getTypeSizeInBits(Op->getType()) > getTypeSizeInBits(Ty) && "This is not a truncating conversion!"); @@ -738,7 +738,7 @@ // If the input value is a chrec scev, truncate the chrec's operands. if (const SCEVAddRecExpr *AddRec = dyn_cast(Op)) { - SmallVector Operands; + SmallVector Operands; for (unsigned i = 0, e = AddRec->getNumOperands(); i != e; ++i) Operands.push_back(getTruncateExpr(AddRec->getOperand(i), Ty)); return getAddRecExpr(Operands, AddRec->getLoop()); @@ -749,7 +749,7 @@ return Result; } -SCEVHandle ScalarEvolution::getZeroExtendExpr(const SCEVHandle &Op, +const SCEV* ScalarEvolution::getZeroExtendExpr(const SCEV* Op, const Type *Ty) { assert(getTypeSizeInBits(Op->getType()) < getTypeSizeInBits(Ty) && "This is not an extending conversion!"); @@ -782,28 +782,28 @@ // in infinite recursion. In the later case, the analysis code will // cope with a conservative value, and it will take care to purge // that value once it has finished. - SCEVHandle MaxBECount = getMaxBackedgeTakenCount(AR->getLoop()); + const SCEV* MaxBECount = getMaxBackedgeTakenCount(AR->getLoop()); if (!isa(MaxBECount)) { // Manually compute the final value for AR, checking for // overflow. - SCEVHandle Start = AR->getStart(); - SCEVHandle Step = AR->getStepRecurrence(*this); + const SCEV* Start = AR->getStart(); + const SCEV* Step = AR->getStepRecurrence(*this); // Check whether the backedge-taken count can be losslessly casted to // the addrec's type. The count is always unsigned. - SCEVHandle CastedMaxBECount = + const SCEV* CastedMaxBECount = getTruncateOrZeroExtend(MaxBECount, Start->getType()); - SCEVHandle RecastedMaxBECount = + const SCEV* RecastedMaxBECount = getTruncateOrZeroExtend(CastedMaxBECount, MaxBECount->getType()); if (MaxBECount == RecastedMaxBECount) { const Type *WideTy = IntegerType::get(getTypeSizeInBits(Start->getType()) * 2); // Check whether Start+Step*MaxBECount has no unsigned overflow. - SCEVHandle ZMul = + const SCEV* ZMul = getMulExpr(CastedMaxBECount, getTruncateOrZeroExtend(Step, Start->getType())); - SCEVHandle Add = getAddExpr(Start, ZMul); - SCEVHandle OperandExtendedAdd = + const SCEV* Add = getAddExpr(Start, ZMul); + const SCEV* OperandExtendedAdd = getAddExpr(getZeroExtendExpr(Start, WideTy), getMulExpr(getZeroExtendExpr(CastedMaxBECount, WideTy), getZeroExtendExpr(Step, WideTy))); @@ -815,7 +815,7 @@ // Similar to above, only this time treat the step value as signed. // This covers loops that count down. - SCEVHandle SMul = + const SCEV* SMul = getMulExpr(CastedMaxBECount, getTruncateOrSignExtend(Step, Start->getType())); Add = getAddExpr(Start, SMul); @@ -837,7 +837,7 @@ return Result; } -SCEVHandle ScalarEvolution::getSignExtendExpr(const SCEVHandle &Op, +const SCEV* ScalarEvolution::getSignExtendExpr(const SCEV* Op, const Type *Ty) { assert(getTypeSizeInBits(Op->getType()) < getTypeSizeInBits(Ty) && "This is not an extending conversion!"); @@ -870,28 +870,28 @@ // in infinite recursion. In the later case, the analysis code will // cope with a conservative value, and it will take care to purge // that value once it has finished. - SCEVHandle MaxBECount = getMaxBackedgeTakenCount(AR->getLoop()); + const SCEV* MaxBECount = getMaxBackedgeTakenCount(AR->getLoop()); if (!isa(MaxBECount)) { // Manually compute the final value for AR, checking for // overflow. - SCEVHandle Start = AR->getStart(); - SCEVHandle Step = AR->getStepRecurrence(*this); + const SCEV* Start = AR->getStart(); + const SCEV* Step = AR->getStepRecurrence(*this); // Check whether the backedge-taken count can be losslessly casted to // the addrec's type. The count is always unsigned. - SCEVHandle CastedMaxBECount = + const SCEV* CastedMaxBECount = getTruncateOrZeroExtend(MaxBECount, Start->getType()); - SCEVHandle RecastedMaxBECount = + const SCEV* RecastedMaxBECount = getTruncateOrZeroExtend(CastedMaxBECount, MaxBECount->getType()); if (MaxBECount == RecastedMaxBECount) { const Type *WideTy = IntegerType::get(getTypeSizeInBits(Start->getType()) * 2); // Check whether Start+Step*MaxBECount has no signed overflow. - SCEVHandle SMul = + const SCEV* SMul = getMulExpr(CastedMaxBECount, getTruncateOrSignExtend(Step, Start->getType())); - SCEVHandle Add = getAddExpr(Start, SMul); - SCEVHandle OperandExtendedAdd = + const SCEV* Add = getAddExpr(Start, SMul); + const SCEV* OperandExtendedAdd = getAddExpr(getSignExtendExpr(Start, WideTy), getMulExpr(getZeroExtendExpr(CastedMaxBECount, WideTy), getSignExtendExpr(Step, WideTy))); @@ -912,7 +912,7 @@ /// getAnyExtendExpr - Return a SCEV for the given operand extended with /// unspecified bits out to the given type. /// -SCEVHandle ScalarEvolution::getAnyExtendExpr(const SCEVHandle &Op, +const SCEV* ScalarEvolution::getAnyExtendExpr(const SCEV* Op, const Type *Ty) { assert(getTypeSizeInBits(Op->getType()) < getTypeSizeInBits(Ty) && "This is not an extending conversion!"); @@ -927,19 +927,19 @@ // Peel off a truncate cast. if (const SCEVTruncateExpr *T = dyn_cast(Op)) { - SCEVHandle NewOp = T->getOperand(); + const SCEV* NewOp = T->getOperand(); if (getTypeSizeInBits(NewOp->getType()) < getTypeSizeInBits(Ty)) return getAnyExtendExpr(NewOp, Ty); return getTruncateOrNoop(NewOp, Ty); } // Next try a zext cast. If the cast is folded, use it. - SCEVHandle ZExt = getZeroExtendExpr(Op, Ty); + const SCEV* ZExt = getZeroExtendExpr(Op, Ty); if (!isa(ZExt)) return ZExt; // Next try a sext cast. If the cast is folded, use it. - SCEVHandle SExt = getSignExtendExpr(Op, Ty); + const SCEV* SExt = getSignExtendExpr(Op, Ty); if (!isa(SExt)) return SExt; @@ -977,10 +977,10 @@ /// is also used as a check to avoid infinite recursion. /// static bool -CollectAddOperandsWithScales(DenseMap &M, - SmallVector &NewOps, +CollectAddOperandsWithScales(DenseMap &M, + SmallVector &NewOps, APInt &AccumulatedConstant, - const SmallVectorImpl &Ops, + const SmallVectorImpl &Ops, const APInt &Scale, ScalarEvolution &SE) { bool Interesting = false; @@ -1001,9 +1001,9 @@ } else { // A multiplication of a constant with some other value. Update // the map. - SmallVector MulOps(Mul->op_begin()+1, Mul->op_end()); - SCEVHandle Key = SE.getMulExpr(MulOps); - std::pair::iterator, bool> Pair = + SmallVector MulOps(Mul->op_begin()+1, Mul->op_end()); + const SCEV* Key = SE.getMulExpr(MulOps); + std::pair::iterator, bool> Pair = M.insert(std::make_pair(Key, APInt())); if (Pair.second) { Pair.first->second = NewScale; @@ -1022,7 +1022,7 @@ AccumulatedConstant += Scale * C->getValue()->getValue(); } else { // An ordinary operand. Update the map. - std::pair::iterator, bool> Pair = + std::pair::iterator, bool> Pair = M.insert(std::make_pair(Ops[i], APInt())); if (Pair.second) { Pair.first->second = Scale; @@ -1049,7 +1049,7 @@ /// getAddExpr - Get a canonical add expression, or something simpler if /// possible. -SCEVHandle ScalarEvolution::getAddExpr(SmallVectorImpl &Ops) { +const SCEV* ScalarEvolution::getAddExpr(SmallVectorImpl &Ops) { assert(!Ops.empty() && "Cannot get empty add!"); if (Ops.size() == 1) return Ops[0]; #ifndef NDEBUG @@ -1093,8 +1093,8 @@ if (Ops[i] == Ops[i+1]) { // X + Y + Y --> X + Y*2 // Found a match, merge the two values into a multiply, and add any // remaining values to the result. - SCEVHandle Two = getIntegerSCEV(2, Ty); - SCEVHandle Mul = getMulExpr(Ops[i], Two); + const SCEV* Two = getIntegerSCEV(2, Ty); + const SCEV* Mul = getMulExpr(Ops[i], Two); if (Ops.size() == 2) return Mul; Ops.erase(Ops.begin()+i, Ops.begin()+i+2); @@ -1110,7 +1110,7 @@ const SCEVTruncateExpr *Trunc = cast(Ops[Idx]); const Type *DstType = Trunc->getType(); const Type *SrcType = Trunc->getOperand()->getType(); - SmallVector LargeOps; + SmallVector LargeOps; bool Ok = true; // Check all the operands to see if they can be represented in the // source type of the truncate. @@ -1126,7 +1126,7 @@ // is much more likely to be foldable here. LargeOps.push_back(getSignExtendExpr(C, SrcType)); } else if (const SCEVMulExpr *M = dyn_cast(Ops[i])) { - SmallVector LargeMulOps; + SmallVector LargeMulOps; for (unsigned j = 0, f = M->getNumOperands(); j != f && Ok; ++j) { if (const SCEVTruncateExpr *T = dyn_cast(M->getOperand(j))) { @@ -1154,7 +1154,7 @@ } if (Ok) { // Evaluate the expression in the larger type. - SCEVHandle Fold = getAddExpr(LargeOps); + const SCEV* Fold = getAddExpr(LargeOps); // If it folds to something simple, use it. Otherwise, don't. if (isa(Fold) || isa(Fold)) return getTruncateExpr(Fold, DstType); @@ -1191,23 +1191,23 @@ // operands multiplied by constant values. if (Idx < Ops.size() && isa(Ops[Idx])) { uint64_t BitWidth = getTypeSizeInBits(Ty); - DenseMap M; - SmallVector NewOps; + DenseMap M; + SmallVector NewOps; APInt AccumulatedConstant(BitWidth, 0); if (CollectAddOperandsWithScales(M, NewOps, AccumulatedConstant, Ops, APInt(BitWidth, 1), *this)) { // Some interesting folding opportunity is present, so its worthwhile to // re-generate the operands list. Group the operands by constant scale, // to avoid multiplying by the same constant scale multiple times. - std::map, APIntCompare> MulOpLists; - for (SmallVector::iterator I = NewOps.begin(), + std::map, APIntCompare> MulOpLists; + for (SmallVector::iterator I = NewOps.begin(), E = NewOps.end(); I != E; ++I) MulOpLists[M.find(*I)->second].push_back(*I); // Re-generate the operands list. Ops.clear(); if (AccumulatedConstant != 0) Ops.push_back(getConstant(AccumulatedConstant)); - for (std::map, APIntCompare>::iterator I = + for (std::map, APIntCompare>::iterator I = MulOpLists.begin(), E = MulOpLists.end(); I != E; ++I) if (I->first != 0) Ops.push_back(getMulExpr(getConstant(I->first), getAddExpr(I->second))); @@ -1229,17 +1229,17 @@ for (unsigned AddOp = 0, e = Ops.size(); AddOp != e; ++AddOp) if (MulOpSCEV == Ops[AddOp] && !isa(Ops[AddOp])) { // Fold W + X + (X * Y * Z) --> W + (X * ((Y*Z)+1)) - SCEVHandle InnerMul = Mul->getOperand(MulOp == 0); + const SCEV* InnerMul = Mul->getOperand(MulOp == 0); if (Mul->getNumOperands() != 2) { // If the multiply has more than two operands, we must get the // Y*Z term. - SmallVector MulOps(Mul->op_begin(), Mul->op_end()); + SmallVector MulOps(Mul->op_begin(), Mul->op_end()); MulOps.erase(MulOps.begin()+MulOp); InnerMul = getMulExpr(MulOps); } - SCEVHandle One = getIntegerSCEV(1, Ty); - SCEVHandle AddOne = getAddExpr(InnerMul, One); - SCEVHandle OuterMul = getMulExpr(AddOne, Ops[AddOp]); + const SCEV* One = getIntegerSCEV(1, Ty); + const SCEV* AddOne = getAddExpr(InnerMul, One); + const SCEV* OuterMul = getMulExpr(AddOne, Ops[AddOp]); if (Ops.size() == 2) return OuterMul; if (AddOp < Idx) { Ops.erase(Ops.begin()+AddOp); @@ -1263,21 +1263,21 @@ OMulOp != e; ++OMulOp) if (OtherMul->getOperand(OMulOp) == MulOpSCEV) { // Fold X + (A*B*C) + (A*D*E) --> X + (A*(B*C+D*E)) - SCEVHandle InnerMul1 = Mul->getOperand(MulOp == 0); + const SCEV* InnerMul1 = Mul->getOperand(MulOp == 0); if (Mul->getNumOperands() != 2) { - SmallVector MulOps(Mul->op_begin(), Mul->op_end()); + SmallVector MulOps(Mul->op_begin(), Mul->op_end()); MulOps.erase(MulOps.begin()+MulOp); InnerMul1 = getMulExpr(MulOps); } - SCEVHandle InnerMul2 = OtherMul->getOperand(OMulOp == 0); + const SCEV* InnerMul2 = OtherMul->getOperand(OMulOp == 0); if (OtherMul->getNumOperands() != 2) { - SmallVector MulOps(OtherMul->op_begin(), + SmallVector MulOps(OtherMul->op_begin(), OtherMul->op_end()); MulOps.erase(MulOps.begin()+OMulOp); InnerMul2 = getMulExpr(MulOps); } - SCEVHandle InnerMulSum = getAddExpr(InnerMul1,InnerMul2); - SCEVHandle OuterMul = getMulExpr(MulOpSCEV, InnerMulSum); + const SCEV* InnerMulSum = getAddExpr(InnerMul1,InnerMul2); + const SCEV* OuterMul = getMulExpr(MulOpSCEV, InnerMulSum); if (Ops.size() == 2) return OuterMul; Ops.erase(Ops.begin()+Idx); Ops.erase(Ops.begin()+OtherMulIdx-1); @@ -1298,7 +1298,7 @@ for (; Idx < Ops.size() && isa(Ops[Idx]); ++Idx) { // Scan all of the other operands to this add and add them to the vector if // they are loop invariant w.r.t. the recurrence. - SmallVector LIOps; + SmallVector LIOps; const SCEVAddRecExpr *AddRec = cast(Ops[Idx]); for (unsigned i = 0, e = Ops.size(); i != e; ++i) if (Ops[i]->isLoopInvariant(AddRec->getLoop())) { @@ -1312,11 +1312,11 @@ // NLI + LI + {Start,+,Step} --> NLI + {LI+Start,+,Step} LIOps.push_back(AddRec->getStart()); - SmallVector AddRecOps(AddRec->op_begin(), + SmallVector AddRecOps(AddRec->op_begin(), AddRec->op_end()); AddRecOps[0] = getAddExpr(LIOps); - SCEVHandle NewRec = getAddRecExpr(AddRecOps, AddRec->getLoop()); + const SCEV* NewRec = getAddRecExpr(AddRecOps, AddRec->getLoop()); // If all of the other operands were loop invariant, we are done. if (Ops.size() == 1) return NewRec; @@ -1338,7 +1338,7 @@ const SCEVAddRecExpr *OtherAddRec = cast(Ops[OtherIdx]); if (AddRec->getLoop() == OtherAddRec->getLoop()) { // Other + {A,+,B} + {C,+,D} --> Other + {A+C,+,B+D} - SmallVector NewOps(AddRec->op_begin(), AddRec->op_end()); + SmallVector NewOps(AddRec->op_begin(), AddRec->op_end()); for (unsigned i = 0, e = OtherAddRec->getNumOperands(); i != e; ++i) { if (i >= NewOps.size()) { NewOps.insert(NewOps.end(), OtherAddRec->op_begin()+i, @@ -1347,7 +1347,7 @@ } NewOps[i] = getAddExpr(NewOps[i], OtherAddRec->getOperand(i)); } - SCEVHandle NewAddRec = getAddRecExpr(NewOps, AddRec->getLoop()); + const SCEV* NewAddRec = getAddRecExpr(NewOps, AddRec->getLoop()); if (Ops.size() == 2) return NewAddRec; @@ -1374,7 +1374,7 @@ /// getMulExpr - Get a canonical multiply expression, or something simpler if /// possible. -SCEVHandle ScalarEvolution::getMulExpr(SmallVectorImpl &Ops) { +const SCEV* ScalarEvolution::getMulExpr(SmallVectorImpl &Ops) { assert(!Ops.empty() && "Cannot get empty mul!"); #ifndef NDEBUG for (unsigned i = 1, e = Ops.size(); i != e; ++i) @@ -1455,7 +1455,7 @@ for (; Idx < Ops.size() && isa(Ops[Idx]); ++Idx) { // Scan all of the other operands to this mul and add them to the vector if // they are loop invariant w.r.t. the recurrence. - SmallVector LIOps; + SmallVector LIOps; const SCEVAddRecExpr *AddRec = cast(Ops[Idx]); for (unsigned i = 0, e = Ops.size(); i != e; ++i) if (Ops[i]->isLoopInvariant(AddRec->getLoop())) { @@ -1467,7 +1467,7 @@ // If we found some loop invariants, fold them into the recurrence. if (!LIOps.empty()) { // NLI * LI * {Start,+,Step} --> NLI * {LI*Start,+,LI*Step} - SmallVector NewOps; + SmallVector NewOps; NewOps.reserve(AddRec->getNumOperands()); if (LIOps.size() == 1) { const SCEV *Scale = LIOps[0]; @@ -1475,13 +1475,13 @@ NewOps.push_back(getMulExpr(Scale, AddRec->getOperand(i))); } else { for (unsigned i = 0, e = AddRec->getNumOperands(); i != e; ++i) { - SmallVector MulOps(LIOps.begin(), LIOps.end()); + SmallVector MulOps(LIOps.begin(), LIOps.end()); MulOps.push_back(AddRec->getOperand(i)); NewOps.push_back(getMulExpr(MulOps)); } } - SCEVHandle NewRec = getAddRecExpr(NewOps, AddRec->getLoop()); + const SCEV* NewRec = getAddRecExpr(NewOps, AddRec->getLoop()); // If all of the other operands were loop invariant, we are done. if (Ops.size() == 1) return NewRec; @@ -1505,14 +1505,14 @@ if (AddRec->getLoop() == OtherAddRec->getLoop()) { // F * G --> {A,+,B} * {C,+,D} --> {A*C,+,F*D + G*B + B*D} const SCEVAddRecExpr *F = AddRec, *G = OtherAddRec; - SCEVHandle NewStart = getMulExpr(F->getStart(), + const SCEV* NewStart = getMulExpr(F->getStart(), G->getStart()); - SCEVHandle B = F->getStepRecurrence(*this); - SCEVHandle D = G->getStepRecurrence(*this); - SCEVHandle NewStep = getAddExpr(getMulExpr(F, D), + const SCEV* B = F->getStepRecurrence(*this); + const SCEV* D = G->getStepRecurrence(*this); + const SCEV* NewStep = getAddExpr(getMulExpr(F, D), getMulExpr(G, B), getMulExpr(B, D)); - SCEVHandle NewAddRec = getAddRecExpr(NewStart, NewStep, + const SCEV* NewAddRec = getAddRecExpr(NewStart, NewStep, F->getLoop()); if (Ops.size() == 2) return NewAddRec; @@ -1539,8 +1539,8 @@ /// getUDivExpr - Get a canonical multiply expression, or something simpler if /// possible. -SCEVHandle ScalarEvolution::getUDivExpr(const SCEVHandle &LHS, - const SCEVHandle &RHS) { +const SCEV* ScalarEvolution::getUDivExpr(const SCEV* LHS, + const SCEV* RHS) { assert(getEffectiveSCEVType(LHS->getType()) == getEffectiveSCEVType(RHS->getType()) && "SCEVUDivExpr operand types don't match!"); @@ -1573,24 +1573,24 @@ getAddRecExpr(getZeroExtendExpr(AR->getStart(), ExtTy), getZeroExtendExpr(Step, ExtTy), AR->getLoop())) { - SmallVector Operands; + SmallVector Operands; for (unsigned i = 0, e = AR->getNumOperands(); i != e; ++i) Operands.push_back(getUDivExpr(AR->getOperand(i), RHS)); return getAddRecExpr(Operands, AR->getLoop()); } // (A*B)/C --> A*(B/C) if safe and B/C can be folded. if (const SCEVMulExpr *M = dyn_cast(LHS)) { - SmallVector Operands; + SmallVector Operands; for (unsigned i = 0, e = M->getNumOperands(); i != e; ++i) Operands.push_back(getZeroExtendExpr(M->getOperand(i), ExtTy)); if (getZeroExtendExpr(M, ExtTy) == getMulExpr(Operands)) // Find an operand that's safely divisible. for (unsigned i = 0, e = M->getNumOperands(); i != e; ++i) { - SCEVHandle Op = M->getOperand(i); - SCEVHandle Div = getUDivExpr(Op, RHSC); + const SCEV* Op = M->getOperand(i); + const SCEV* Div = getUDivExpr(Op, RHSC); if (!isa(Div) && getMulExpr(Div, RHSC) == Op) { - const SmallVectorImpl &MOperands = M->getOperands(); - Operands = SmallVector(MOperands.begin(), + const SmallVectorImpl &MOperands = M->getOperands(); + Operands = SmallVector(MOperands.begin(), MOperands.end()); Operands[i] = Div; return getMulExpr(Operands); @@ -1599,13 +1599,13 @@ } // (A+B)/C --> (A/C + B/C) if safe and A/C and B/C can be folded. if (const SCEVAddRecExpr *A = dyn_cast(LHS)) { - SmallVector Operands; + SmallVector Operands; for (unsigned i = 0, e = A->getNumOperands(); i != e; ++i) Operands.push_back(getZeroExtendExpr(A->getOperand(i), ExtTy)); if (getZeroExtendExpr(A, ExtTy) == getAddExpr(Operands)) { Operands.clear(); for (unsigned i = 0, e = A->getNumOperands(); i != e; ++i) { - SCEVHandle Op = getUDivExpr(A->getOperand(i), RHS); + const SCEV* Op = getUDivExpr(A->getOperand(i), RHS); if (isa(Op) || getMulExpr(Op, RHS) != A->getOperand(i)) break; Operands.push_back(Op); @@ -1631,9 +1631,9 @@ /// getAddRecExpr - Get an add recurrence expression for the specified loop. /// Simplify the expression as much as possible. -SCEVHandle ScalarEvolution::getAddRecExpr(const SCEVHandle &Start, - const SCEVHandle &Step, const Loop *L) { - SmallVector Operands; +const SCEV* ScalarEvolution::getAddRecExpr(const SCEV* Start, + const SCEV* Step, const Loop *L) { + SmallVector Operands; Operands.push_back(Start); if (const SCEVAddRecExpr *StepChrec = dyn_cast(Step)) if (StepChrec->getLoop() == L) { @@ -1648,7 +1648,7 @@ /// getAddRecExpr - Get an add recurrence expression for the specified loop. /// Simplify the expression as much as possible. -SCEVHandle ScalarEvolution::getAddRecExpr(SmallVectorImpl &Operands, +const SCEV* ScalarEvolution::getAddRecExpr(SmallVectorImpl &Operands, const Loop *L) { if (Operands.size() == 1) return Operands[0]; #ifndef NDEBUG @@ -1667,9 +1667,8 @@ if (const SCEVAddRecExpr *NestedAR = dyn_cast(Operands[0])) { const Loop* NestedLoop = NestedAR->getLoop(); if (L->getLoopDepth() < NestedLoop->getLoopDepth()) { - SmallVector NestedOperands(NestedAR->op_begin(), + SmallVector NestedOperands(NestedAR->op_begin(), NestedAR->op_end()); - SCEVHandle NestedARHandle(NestedAR); Operands[0] = NestedAR->getStart(); NestedOperands[0] = getAddRecExpr(Operands, L); return getAddRecExpr(NestedOperands, NestedLoop); @@ -1682,16 +1681,16 @@ return Result; } -SCEVHandle ScalarEvolution::getSMaxExpr(const SCEVHandle &LHS, - const SCEVHandle &RHS) { - SmallVector Ops; +const SCEV* ScalarEvolution::getSMaxExpr(const SCEV* LHS, + const SCEV* RHS) { + SmallVector Ops; Ops.push_back(LHS); Ops.push_back(RHS); return getSMaxExpr(Ops); } -SCEVHandle -ScalarEvolution::getSMaxExpr(SmallVectorImpl &Ops) { +const SCEV* +ScalarEvolution::getSMaxExpr(SmallVectorImpl &Ops) { assert(!Ops.empty() && "Cannot get empty smax!"); if (Ops.size() == 1) return Ops[0]; #ifndef NDEBUG @@ -1769,16 +1768,16 @@ return Result; } -SCEVHandle ScalarEvolution::getUMaxExpr(const SCEVHandle &LHS, - const SCEVHandle &RHS) { - SmallVector Ops; +const SCEV* ScalarEvolution::getUMaxExpr(const SCEV* LHS, + const SCEV* RHS) { + SmallVector Ops; Ops.push_back(LHS); Ops.push_back(RHS); return getUMaxExpr(Ops); } -SCEVHandle -ScalarEvolution::getUMaxExpr(SmallVectorImpl &Ops) { +const SCEV* +ScalarEvolution::getUMaxExpr(SmallVectorImpl &Ops) { assert(!Ops.empty() && "Cannot get empty umax!"); if (Ops.size() == 1) return Ops[0]; #ifndef NDEBUG @@ -1856,19 +1855,19 @@ return Result; } -SCEVHandle ScalarEvolution::getSMinExpr(const SCEVHandle &LHS, - const SCEVHandle &RHS) { +const SCEV* ScalarEvolution::getSMinExpr(const SCEV* LHS, + const SCEV* RHS) { // ~smax(~x, ~y) == smin(x, y). return getNotSCEV(getSMaxExpr(getNotSCEV(LHS), getNotSCEV(RHS))); } -SCEVHandle ScalarEvolution::getUMinExpr(const SCEVHandle &LHS, - const SCEVHandle &RHS) { +const SCEV* ScalarEvolution::getUMinExpr(const SCEV* LHS, + const SCEV* RHS) { // ~umax(~x, ~y) == umin(x, y) return getNotSCEV(getUMaxExpr(getNotSCEV(LHS), getNotSCEV(RHS))); } -SCEVHandle ScalarEvolution::getUnknown(Value *V) { +const SCEV* ScalarEvolution::getUnknown(Value *V) { if (ConstantInt *CI = dyn_cast(V)) return getConstant(CI); if (isa(V)) @@ -1928,7 +1927,7 @@ return TD->getIntPtrType(); } -SCEVHandle ScalarEvolution::getCouldNotCompute() { +const SCEV* ScalarEvolution::getCouldNotCompute() { return CouldNotCompute; } @@ -1940,19 +1939,19 @@ /// getSCEV - Return an existing SCEV if it exists, otherwise analyze the /// expression and create a new one. -SCEVHandle ScalarEvolution::getSCEV(Value *V) { +const SCEV* ScalarEvolution::getSCEV(Value *V) { assert(isSCEVable(V->getType()) && "Value is not SCEVable!"); - std::map::iterator I = Scalars.find(V); + std::map::iterator I = Scalars.find(V); if (I != Scalars.end()) return I->second; - SCEVHandle S = createSCEV(V); + const SCEV* S = createSCEV(V); Scalars.insert(std::make_pair(SCEVCallbackVH(V, this), S)); return S; } /// getIntegerSCEV - Given an integer or FP type, create a constant for the /// specified signed integer value and return a SCEV for the constant. -SCEVHandle ScalarEvolution::getIntegerSCEV(int Val, const Type *Ty) { +const SCEV* ScalarEvolution::getIntegerSCEV(int Val, const Type *Ty) { Ty = getEffectiveSCEVType(Ty); Constant *C; if (Val == 0) @@ -1967,7 +1966,7 @@ /// getNegativeSCEV - Return a SCEV corresponding to -V = -1*V /// -SCEVHandle ScalarEvolution::getNegativeSCEV(const SCEVHandle &V) { +const SCEV* ScalarEvolution::getNegativeSCEV(const SCEV* V) { if (const SCEVConstant *VC = dyn_cast(V)) return getUnknown(ConstantExpr::getNeg(VC->getValue())); @@ -1977,20 +1976,20 @@ } /// getNotSCEV - Return a SCEV corresponding to ~V = -1-V -SCEVHandle ScalarEvolution::getNotSCEV(const SCEVHandle &V) { +const SCEV* ScalarEvolution::getNotSCEV(const SCEV* V) { if (const SCEVConstant *VC = dyn_cast(V)) return getUnknown(ConstantExpr::getNot(VC->getValue())); const Type *Ty = V->getType(); Ty = getEffectiveSCEVType(Ty); - SCEVHandle AllOnes = getConstant(ConstantInt::getAllOnesValue(Ty)); + const SCEV* AllOnes = getConstant(ConstantInt::getAllOnesValue(Ty)); return getMinusSCEV(AllOnes, V); } /// getMinusSCEV - Return a SCEV corresponding to LHS - RHS. /// -SCEVHandle ScalarEvolution::getMinusSCEV(const SCEVHandle &LHS, - const SCEVHandle &RHS) { +const SCEV* ScalarEvolution::getMinusSCEV(const SCEV* LHS, + const SCEV* RHS) { // X - Y --> X + -Y return getAddExpr(LHS, getNegativeSCEV(RHS)); } @@ -1998,8 +1997,8 @@ /// getTruncateOrZeroExtend - Return a SCEV corresponding to a conversion of the /// input value to the specified type. If the type must be extended, it is zero /// extended. -SCEVHandle -ScalarEvolution::getTruncateOrZeroExtend(const SCEVHandle &V, +const SCEV* +ScalarEvolution::getTruncateOrZeroExtend(const SCEV* V, const Type *Ty) { const Type *SrcTy = V->getType(); assert((SrcTy->isInteger() || (TD && isa(SrcTy))) && @@ -2015,8 +2014,8 @@ /// getTruncateOrSignExtend - Return a SCEV corresponding to a conversion of the /// input value to the specified type. If the type must be extended, it is sign /// extended. -SCEVHandle -ScalarEvolution::getTruncateOrSignExtend(const SCEVHandle &V, +const SCEV* +ScalarEvolution::getTruncateOrSignExtend(const SCEV* V, const Type *Ty) { const Type *SrcTy = V->getType(); assert((SrcTy->isInteger() || (TD && isa(SrcTy))) && @@ -2032,8 +2031,8 @@ /// getNoopOrZeroExtend - Return a SCEV corresponding to a conversion of the /// input value to the specified type. If the type must be extended, it is zero /// extended. The conversion must not be narrowing. -SCEVHandle -ScalarEvolution::getNoopOrZeroExtend(const SCEVHandle &V, const Type *Ty) { +const SCEV* +ScalarEvolution::getNoopOrZeroExtend(const SCEV* V, const Type *Ty) { const Type *SrcTy = V->getType(); assert((SrcTy->isInteger() || (TD && isa(SrcTy))) && (Ty->isInteger() || (TD && isa(Ty))) && @@ -2048,8 +2047,8 @@ /// getNoopOrSignExtend - Return a SCEV corresponding to a conversion of the /// input value to the specified type. If the type must be extended, it is sign /// extended. The conversion must not be narrowing. -SCEVHandle -ScalarEvolution::getNoopOrSignExtend(const SCEVHandle &V, const Type *Ty) { +const SCEV* +ScalarEvolution::getNoopOrSignExtend(const SCEV* V, const Type *Ty) { const Type *SrcTy = V->getType(); assert((SrcTy->isInteger() || (TD && isa(SrcTy))) && (Ty->isInteger() || (TD && isa(Ty))) && @@ -2065,8 +2064,8 @@ /// the input value to the specified type. If the type must be extended, /// it is extended with unspecified bits. The conversion must not be /// narrowing. -SCEVHandle -ScalarEvolution::getNoopOrAnyExtend(const SCEVHandle &V, const Type *Ty) { +const SCEV* +ScalarEvolution::getNoopOrAnyExtend(const SCEV* V, const Type *Ty) { const Type *SrcTy = V->getType(); assert((SrcTy->isInteger() || (TD && isa(SrcTy))) && (Ty->isInteger() || (TD && isa(Ty))) && @@ -2080,8 +2079,8 @@ /// getTruncateOrNoop - Return a SCEV corresponding to a conversion of the /// input value to the specified type. The conversion must not be widening. -SCEVHandle -ScalarEvolution::getTruncateOrNoop(const SCEVHandle &V, const Type *Ty) { +const SCEV* +ScalarEvolution::getTruncateOrNoop(const SCEV* V, const Type *Ty) { const Type *SrcTy = V->getType(); assert((SrcTy->isInteger() || (TD && isa(SrcTy))) && (Ty->isInteger() || (TD && isa(Ty))) && @@ -2096,10 +2095,10 @@ /// getUMaxFromMismatchedTypes - Promote the operands to the wider of /// the types using zero-extension, and then perform a umax operation /// with them. -SCEVHandle ScalarEvolution::getUMaxFromMismatchedTypes(const SCEVHandle &LHS, - const SCEVHandle &RHS) { - SCEVHandle PromotedLHS = LHS; - SCEVHandle PromotedRHS = RHS; +const SCEV* ScalarEvolution::getUMaxFromMismatchedTypes(const SCEV* LHS, + const SCEV* RHS) { + const SCEV* PromotedLHS = LHS; + const SCEV* PromotedRHS = RHS; if (getTypeSizeInBits(LHS->getType()) > getTypeSizeInBits(RHS->getType())) PromotedRHS = getZeroExtendExpr(RHS, LHS->getType()); @@ -2112,10 +2111,10 @@ /// getUMinFromMismatchedTypes - Promote the operands to the wider of /// the types using zero-extension, and then perform a umin operation /// with them. -SCEVHandle ScalarEvolution::getUMinFromMismatchedTypes(const SCEVHandle &LHS, - const SCEVHandle &RHS) { - SCEVHandle PromotedLHS = LHS; - SCEVHandle PromotedRHS = RHS; +const SCEV* ScalarEvolution::getUMinFromMismatchedTypes(const SCEV* LHS, + const SCEV* RHS) { + const SCEV* PromotedLHS = LHS; + const SCEV* PromotedRHS = RHS; if (getTypeSizeInBits(LHS->getType()) > getTypeSizeInBits(RHS->getType())) PromotedRHS = getZeroExtendExpr(RHS, LHS->getType()); @@ -2129,13 +2128,13 @@ /// the specified instruction and replaces any references to the symbolic value /// SymName with the specified value. This is used during PHI resolution. void ScalarEvolution:: -ReplaceSymbolicValueWithConcrete(Instruction *I, const SCEVHandle &SymName, - const SCEVHandle &NewVal) { - std::map::iterator SI = +ReplaceSymbolicValueWithConcrete(Instruction *I, const SCEV* SymName, + const SCEV* NewVal) { + std::map::iterator SI = Scalars.find(SCEVCallbackVH(I, this)); if (SI == Scalars.end()) return; - SCEVHandle NV = + const SCEV* NV = SI->second->replaceSymbolicValuesWithConcrete(SymName, NewVal, *this); if (NV == SI->second) return; // No change. @@ -2151,7 +2150,7 @@ /// createNodeForPHI - PHI nodes have two cases. Either the PHI node exists in /// a loop header, making it a potential recurrence, or it doesn't. /// -SCEVHandle ScalarEvolution::createNodeForPHI(PHINode *PN) { +const SCEV* ScalarEvolution::createNodeForPHI(PHINode *PN) { if (PN->getNumIncomingValues() == 2) // The loops have been canonicalized. if (const Loop *L = LI->getLoopFor(PN->getParent())) if (L->getHeader() == PN->getParent()) { @@ -2161,14 +2160,14 @@ unsigned BackEdge = IncomingEdge^1; // While we are analyzing this PHI node, handle its value symbolically. - SCEVHandle SymbolicName = getUnknown(PN); + const SCEV* SymbolicName = getUnknown(PN); assert(Scalars.find(PN) == Scalars.end() && "PHI node already processed?"); Scalars.insert(std::make_pair(SCEVCallbackVH(PN, this), SymbolicName)); // Using this symbolic name for the PHI, analyze the value coming around // the back-edge. - SCEVHandle BEValue = getSCEV(PN->getIncomingValue(BackEdge)); + const SCEV* BEValue = getSCEV(PN->getIncomingValue(BackEdge)); // NOTE: If BEValue is loop invariant, we know that the PHI node just // has a special value for the first iteration of the loop. @@ -2188,19 +2187,19 @@ if (FoundIndex != Add->getNumOperands()) { // Create an add with everything but the specified operand. - SmallVector Ops; + SmallVector Ops; for (unsigned i = 0, e = Add->getNumOperands(); i != e; ++i) if (i != FoundIndex) Ops.push_back(Add->getOperand(i)); - SCEVHandle Accum = getAddExpr(Ops); + const SCEV* Accum = getAddExpr(Ops); // This is not a valid addrec if the step amount is varying each // loop iteration, but is not itself an addrec in this loop. if (Accum->isLoopInvariant(L) || (isa(Accum) && cast(Accum)->getLoop() == L)) { - SCEVHandle StartVal = getSCEV(PN->getIncomingValue(IncomingEdge)); - SCEVHandle PHISCEV = getAddRecExpr(StartVal, Accum, L); + const SCEV* StartVal = getSCEV(PN->getIncomingValue(IncomingEdge)); + const SCEV* PHISCEV = getAddRecExpr(StartVal, Accum, L); // Okay, for the entire analysis of this edge we assumed the PHI // to be symbolic. We now need to go back and update all of the @@ -2219,13 +2218,13 @@ // Because the other in-value of i (0) fits the evolution of BEValue // i really is an addrec evolution. if (AddRec->getLoop() == L && AddRec->isAffine()) { - SCEVHandle StartVal = getSCEV(PN->getIncomingValue(IncomingEdge)); + const SCEV* StartVal = getSCEV(PN->getIncomingValue(IncomingEdge)); // If StartVal = j.start - j.stride, we can use StartVal as the // initial step of the addrec evolution. if (StartVal == getMinusSCEV(AddRec->getOperand(0), AddRec->getOperand(1))) { - SCEVHandle PHISCEV = + const SCEV* PHISCEV = getAddRecExpr(StartVal, AddRec->getOperand(1), L); // Okay, for the entire analysis of this edge we assumed the PHI @@ -2249,14 +2248,14 @@ /// createNodeForGEP - Expand GEP instructions into add and multiply /// operations. This allows them to be analyzed by regular SCEV code. /// -SCEVHandle ScalarEvolution::createNodeForGEP(User *GEP) { +const SCEV* ScalarEvolution::createNodeForGEP(User *GEP) { const Type *IntPtrTy = TD->getIntPtrType(); Value *Base = GEP->getOperand(0); // Don't attempt to analyze GEPs over unsized objects. if (!cast(Base->getType())->getElementType()->isSized()) return getUnknown(GEP); - SCEVHandle TotalOffset = getIntegerSCEV(0, IntPtrTy); + const SCEV* TotalOffset = getIntegerSCEV(0, IntPtrTy); gep_type_iterator GTI = gep_type_begin(GEP); for (GetElementPtrInst::op_iterator I = next(GEP->op_begin()), E = GEP->op_end(); @@ -2272,7 +2271,7 @@ getIntegerSCEV(Offset, IntPtrTy)); } else { // For an array, add the element offset, explicitly scaled. - SCEVHandle LocalOffset = getSCEV(Index); + const SCEV* LocalOffset = getSCEV(Index); if (!isa(LocalOffset->getType())) // Getelementptr indicies are signed. LocalOffset = getTruncateOrSignExtend(LocalOffset, @@ -2292,7 +2291,7 @@ /// the minimum number of times S is divisible by 2. For example, given {4,+,8} /// it returns 2. If S is guaranteed to be 0, it returns the bitwidth of S. uint32_t -ScalarEvolution::GetMinTrailingZeros(const SCEVHandle &S) { +ScalarEvolution::GetMinTrailingZeros(const SCEV* S) { if (const SCEVConstant *C = dyn_cast(S)) return C->getValue()->getValue().countTrailingZeros(); @@ -2369,7 +2368,7 @@ } uint32_t -ScalarEvolution::GetMinLeadingZeros(const SCEVHandle &S) { +ScalarEvolution::GetMinLeadingZeros(const SCEV* S) { // TODO: Handle other SCEV expression types here. if (const SCEVConstant *C = dyn_cast(S)) @@ -2395,7 +2394,7 @@ } uint32_t -ScalarEvolution::GetMinSignBits(const SCEVHandle &S) { +ScalarEvolution::GetMinSignBits(const SCEV* S) { // TODO: Handle other SCEV expression types here. if (const SCEVConstant *C = dyn_cast(S)) { @@ -2422,7 +2421,7 @@ /// createSCEV - We know that there is no SCEV for the specified value. /// Analyze the expression. /// -SCEVHandle ScalarEvolution::createSCEV(Value *V) { +const SCEV* ScalarEvolution::createSCEV(Value *V) { if (!isSCEVable(V->getType())) return getUnknown(V); @@ -2486,7 +2485,7 @@ // In order for this transformation to be safe, the LHS must be of the // form X*(2^n) and the Or constant must be less than 2^n. if (ConstantInt *CI = dyn_cast(U->getOperand(1))) { - SCEVHandle LHS = getSCEV(U->getOperand(0)); + const SCEV* LHS = getSCEV(U->getOperand(0)); const APInt &CIVal = CI->getValue(); if (GetMinTrailingZeros(LHS) >= (CIVal.getBitWidth() - CIVal.countLeadingZeros())) @@ -2516,7 +2515,7 @@ if (const SCEVZeroExtendExpr *Z = dyn_cast(getSCEV(U->getOperand(0)))) { const Type *UTy = U->getType(); - SCEVHandle Z0 = Z->getOperand(); + const SCEV* Z0 = Z->getOperand(); const Type *Z0Ty = Z0->getType(); unsigned Z0TySize = getTypeSizeInBits(Z0Ty); @@ -2685,14 +2684,14 @@ /// loop-invariant backedge-taken count (see /// hasLoopInvariantBackedgeTakenCount). /// -SCEVHandle ScalarEvolution::getBackedgeTakenCount(const Loop *L) { +const SCEV* ScalarEvolution::getBackedgeTakenCount(const Loop *L) { return getBackedgeTakenInfo(L).Exact; } /// getMaxBackedgeTakenCount - Similar to getBackedgeTakenCount, except /// return the least SCEV value that is known never to be less than the /// actual backedge taken count. -SCEVHandle ScalarEvolution::getMaxBackedgeTakenCount(const Loop *L) { +const SCEV* ScalarEvolution::getMaxBackedgeTakenCount(const Loop *L) { return getBackedgeTakenInfo(L).Max; } @@ -2759,7 +2758,7 @@ SmallVector Worklist; for (BasicBlock::iterator I = Header->begin(); PHINode *PN = dyn_cast(I); ++I) { - std::map::iterator It = Scalars.find((Value*)I); + std::map::iterator It = Scalars.find((Value*)I); if (It != Scalars.end() && !isa(It->second)) Worklist.push_back(PN); } @@ -2781,8 +2780,8 @@ L->getExitingBlocks(ExitingBlocks); // Examine all exits and pick the most conservative values. - SCEVHandle BECount = CouldNotCompute; - SCEVHandle MaxBECount = CouldNotCompute; + const SCEV* BECount = CouldNotCompute; + const SCEV* MaxBECount = CouldNotCompute; bool CouldNotComputeBECount = false; bool CouldNotComputeMaxBECount = false; for (unsigned i = 0, e = ExitingBlocks.size(); i != e; ++i) { @@ -2906,8 +2905,8 @@ ComputeBackedgeTakenCountFromExitCond(L, BO->getOperand(0), TBB, FBB); BackedgeTakenInfo BTI1 = ComputeBackedgeTakenCountFromExitCond(L, BO->getOperand(1), TBB, FBB); - SCEVHandle BECount = CouldNotCompute; - SCEVHandle MaxBECount = CouldNotCompute; + const SCEV* BECount = CouldNotCompute; + const SCEV* MaxBECount = CouldNotCompute; if (L->contains(TBB)) { // Both conditions must be true for the loop to continue executing. // Choose the less conservative count. @@ -2940,8 +2939,8 @@ ComputeBackedgeTakenCountFromExitCond(L, BO->getOperand(0), TBB, FBB); BackedgeTakenInfo BTI1 = ComputeBackedgeTakenCountFromExitCond(L, BO->getOperand(1), TBB, FBB); - SCEVHandle BECount = CouldNotCompute; - SCEVHandle MaxBECount = CouldNotCompute; + const SCEV* BECount = CouldNotCompute; + const SCEV* MaxBECount = CouldNotCompute; if (L->contains(FBB)) { // Both conditions must be false for the loop to continue executing. // Choose the less conservative count. @@ -2998,7 +2997,7 @@ // Handle common loops like: for (X = "string"; *X; ++X) if (LoadInst *LI = dyn_cast(ExitCond->getOperand(0))) if (Constant *RHS = dyn_cast(ExitCond->getOperand(1))) { - SCEVHandle ItCnt = + const SCEV* ItCnt = ComputeLoadConstantCompareBackedgeTakenCount(LI, RHS, L, Cond); if (!isa(ItCnt)) { unsigned BitWidth = getTypeSizeInBits(ItCnt->getType()); @@ -3008,8 +3007,8 @@ } } - SCEVHandle LHS = getSCEV(ExitCond->getOperand(0)); - SCEVHandle RHS = getSCEV(ExitCond->getOperand(1)); + const SCEV* LHS = getSCEV(ExitCond->getOperand(0)); + const SCEV* RHS = getSCEV(ExitCond->getOperand(1)); // Try to evaluate any dependencies out of the loop. LHS = getSCEVAtScope(LHS, L); @@ -3032,20 +3031,20 @@ ConstantRange CompRange( ICmpInst::makeConstantRange(Cond, RHSC->getValue()->getValue())); - SCEVHandle Ret = AddRec->getNumIterationsInRange(CompRange, *this); + const SCEV* Ret = AddRec->getNumIterationsInRange(CompRange, *this); if (!isa(Ret)) return Ret; } switch (Cond) { case ICmpInst::ICMP_NE: { // while (X != Y) // Convert to: while (X-Y != 0) - SCEVHandle TC = HowFarToZero(getMinusSCEV(LHS, RHS), L); + const SCEV* TC = HowFarToZero(getMinusSCEV(LHS, RHS), L); if (!isa(TC)) return TC; break; } case ICmpInst::ICMP_EQ: { // Convert to: while (X-Y == 0) // while (X == Y) - SCEVHandle TC = HowFarToNonZero(getMinusSCEV(LHS, RHS), L); + const SCEV* TC = HowFarToNonZero(getMinusSCEV(LHS, RHS), L); if (!isa(TC)) return TC; break; } @@ -3089,8 +3088,8 @@ static ConstantInt * EvaluateConstantChrecAtConstant(const SCEVAddRecExpr *AddRec, ConstantInt *C, ScalarEvolution &SE) { - SCEVHandle InVal = SE.getConstant(C); - SCEVHandle Val = AddRec->evaluateAtIteration(InVal, SE); + const SCEV* InVal = SE.getConstant(C); + const SCEV* Val = AddRec->evaluateAtIteration(InVal, SE); assert(isa(Val) && "Evaluation of SCEV at constant didn't fold correctly?"); return cast(Val)->getValue(); @@ -3133,7 +3132,7 @@ /// ComputeLoadConstantCompareBackedgeTakenCount - Given an exit condition of /// 'icmp op load X, cst', try to see if we can compute the backedge /// execution count. -SCEVHandle ScalarEvolution:: +const SCEV* ScalarEvolution:: ComputeLoadConstantCompareBackedgeTakenCount(LoadInst *LI, Constant *RHS, const Loop *L, ICmpInst::Predicate predicate) { @@ -3167,7 +3166,7 @@ // Okay, we know we have a (load (gep GV, 0, X)) comparison with a constant. // Check to see if X is a loop variant variable value now. - SCEVHandle Idx = getSCEV(VarIdx); + const SCEV* Idx = getSCEV(VarIdx); Idx = getSCEVAtScope(Idx, L); // We can only recognize very limited forms of loop index expressions, in @@ -3343,7 +3342,7 @@ /// try to evaluate a few iterations of the loop until we get the exit /// condition gets a value of ExitWhen (true or false). If we cannot /// evaluate the trip count of the loop, return CouldNotCompute. -SCEVHandle ScalarEvolution:: +const SCEV* ScalarEvolution:: ComputeBackedgeTakenCountExhaustively(const Loop *L, Value *Cond, bool ExitWhen) { PHINode *PN = getConstantEvolvingPHI(Cond, L); if (PN == 0) return CouldNotCompute; @@ -3400,7 +3399,7 @@ /// /// In the case that a relevant loop exit value cannot be computed, the /// original value V is returned. -SCEVHandle ScalarEvolution::getSCEVAtScope(const SCEV *V, const Loop *L) { +const SCEV* ScalarEvolution::getSCEVAtScope(const SCEV *V, const Loop *L) { // FIXME: this should be turned into a virtual method on SCEV! if (isa(V)) return V; @@ -3417,7 +3416,7 @@ // to see if the loop that contains it has a known backedge-taken // count. If so, we may be able to force computation of the exit // value. - SCEVHandle BackedgeTakenCount = getBackedgeTakenCount(LI); + const SCEV* BackedgeTakenCount = getBackedgeTakenCount(LI); if (const SCEVConstant *BTCC = dyn_cast(BackedgeTakenCount)) { // Okay, we know how many times the containing loop executes. If @@ -3455,7 +3454,7 @@ if (!isSCEVable(Op->getType())) return V; - SCEVHandle OpV = getSCEVAtScope(getSCEV(Op), L); + const SCEV* OpV = getSCEVAtScope(getSCEV(Op), L); if (const SCEVConstant *SC = dyn_cast(OpV)) { Constant *C = SC->getValue(); if (C->getType() != Op->getType()) @@ -3501,11 +3500,11 @@ // Avoid performing the look-up in the common case where the specified // expression has no loop-variant portions. for (unsigned i = 0, e = Comm->getNumOperands(); i != e; ++i) { - SCEVHandle OpAtScope = getSCEVAtScope(Comm->getOperand(i), L); + const SCEV* OpAtScope = getSCEVAtScope(Comm->getOperand(i), L); if (OpAtScope != Comm->getOperand(i)) { // Okay, at least one of these operands is loop variant but might be // foldable. Build a new instance of the folded commutative expression. - SmallVector NewOps(Comm->op_begin(), Comm->op_begin()+i); + SmallVector NewOps(Comm->op_begin(), Comm->op_begin()+i); NewOps.push_back(OpAtScope); for (++i; i != e; ++i) { @@ -3528,8 +3527,8 @@ } if (const SCEVUDivExpr *Div = dyn_cast(V)) { - SCEVHandle LHS = getSCEVAtScope(Div->getLHS(), L); - SCEVHandle RHS = getSCEVAtScope(Div->getRHS(), L); + const SCEV* LHS = getSCEVAtScope(Div->getLHS(), L); + const SCEV* RHS = getSCEVAtScope(Div->getRHS(), L); if (LHS == Div->getLHS() && RHS == Div->getRHS()) return Div; // must be loop invariant return getUDivExpr(LHS, RHS); @@ -3541,7 +3540,7 @@ if (!L || !AddRec->getLoop()->contains(L->getHeader())) { // To evaluate this recurrence, we need to know how many times the AddRec // loop iterates. Compute this now. - SCEVHandle BackedgeTakenCount = getBackedgeTakenCount(AddRec->getLoop()); + const SCEV* BackedgeTakenCount = getBackedgeTakenCount(AddRec->getLoop()); if (BackedgeTakenCount == CouldNotCompute) return AddRec; // Then, evaluate the AddRec. @@ -3551,21 +3550,21 @@ } if (const SCEVZeroExtendExpr *Cast = dyn_cast(V)) { - SCEVHandle Op = getSCEVAtScope(Cast->getOperand(), L); + const SCEV* Op = getSCEVAtScope(Cast->getOperand(), L); if (Op == Cast->getOperand()) return Cast; // must be loop invariant return getZeroExtendExpr(Op, Cast->getType()); } if (const SCEVSignExtendExpr *Cast = dyn_cast(V)) { - SCEVHandle Op = getSCEVAtScope(Cast->getOperand(), L); + const SCEV* Op = getSCEVAtScope(Cast->getOperand(), L); if (Op == Cast->getOperand()) return Cast; // must be loop invariant return getSignExtendExpr(Op, Cast->getType()); } if (const SCEVTruncateExpr *Cast = dyn_cast(V)) { - SCEVHandle Op = getSCEVAtScope(Cast->getOperand(), L); + const SCEV* Op = getSCEVAtScope(Cast->getOperand(), L); if (Op == Cast->getOperand()) return Cast; // must be loop invariant return getTruncateExpr(Op, Cast->getType()); @@ -3577,7 +3576,7 @@ /// getSCEVAtScope - This is a convenience function which does /// getSCEVAtScope(getSCEV(V), L). -SCEVHandle ScalarEvolution::getSCEVAtScope(Value *V, const Loop *L) { +const SCEV* ScalarEvolution::getSCEVAtScope(Value *V, const Loop *L) { return getSCEVAtScope(getSCEV(V), L); } @@ -3590,7 +3589,7 @@ /// A and B isn't important. /// /// If the equation does not have a solution, SCEVCouldNotCompute is returned. -static SCEVHandle SolveLinEquationWithOverflow(const APInt &A, const APInt &B, +static const SCEV* SolveLinEquationWithOverflow(const APInt &A, const APInt &B, ScalarEvolution &SE) { uint32_t BW = A.getBitWidth(); assert(BW == B.getBitWidth() && "Bit widths must be the same."); @@ -3633,7 +3632,7 @@ /// given quadratic chrec {L,+,M,+,N}. This returns either the two roots (which /// might be the same) or two SCEVCouldNotCompute objects. /// -static std::pair +static std::pair SolveQuadraticEquation(const SCEVAddRecExpr *AddRec, ScalarEvolution &SE) { assert(AddRec->getNumOperands() == 3 && "This is not a quadratic chrec!"); const SCEVConstant *LC = dyn_cast(AddRec->getOperand(0)); @@ -3692,7 +3691,7 @@ /// HowFarToZero - Return the number of times a backedge comparing the specified /// value to zero will execute. If not computable, return CouldNotCompute. -SCEVHandle ScalarEvolution::HowFarToZero(const SCEV *V, const Loop *L) { +const SCEV* ScalarEvolution::HowFarToZero(const SCEV *V, const Loop *L) { // If the value is a constant if (const SCEVConstant *C = dyn_cast(V)) { // If the value is already zero, the branch will execute zero times. @@ -3717,8 +3716,8 @@ // where BW is the common bit width of Start and Step. // Get the initial value for the loop. - SCEVHandle Start = getSCEVAtScope(AddRec->getStart(), L->getParentLoop()); - SCEVHandle Step = getSCEVAtScope(AddRec->getOperand(1), L->getParentLoop()); + const SCEV* Start = getSCEVAtScope(AddRec->getStart(), L->getParentLoop()); + const SCEV* Step = getSCEVAtScope(AddRec->getOperand(1), L->getParentLoop()); if (const SCEVConstant *StepC = dyn_cast(Step)) { // For now we handle only constant steps. @@ -3738,7 +3737,7 @@ } else if (AddRec->isQuadratic() && AddRec->getType()->isInteger()) { // If this is a quadratic (3-term) AddRec {L,+,M,+,N}, find the roots of // the quadratic equation to solve it. - std::pair Roots = SolveQuadraticEquation(AddRec, + std::pair Roots = SolveQuadraticEquation(AddRec, *this); const SCEVConstant *R1 = dyn_cast(Roots.first); const SCEVConstant *R2 = dyn_cast(Roots.second); @@ -3757,7 +3756,7 @@ // We can only use this value if the chrec ends up with an exact zero // value at this index. When solving for "X*X != 5", for example, we // should not accept a root of 2. - SCEVHandle Val = AddRec->evaluateAtIteration(R1, *this); + const SCEV* Val = AddRec->evaluateAtIteration(R1, *this); if (Val->isZero()) return R1; // We found a quadratic root! } @@ -3770,7 +3769,7 @@ /// HowFarToNonZero - Return the number of times a backedge checking the /// specified value for nonzero will execute. If not computable, return /// CouldNotCompute -SCEVHandle ScalarEvolution::HowFarToNonZero(const SCEV *V, const Loop *L) { +const SCEV* ScalarEvolution::HowFarToNonZero(const SCEV *V, const Loop *L) { // Loops that look like: while (X == 0) are very strange indeed. We don't // handle them yet except for the trivial case. This could be expanded in the // future as needed. @@ -3831,7 +3830,7 @@ /// more general, since a front-end may have replicated the controlling /// expression. /// -static bool HasSameValue(const SCEVHandle &A, const SCEVHandle &B) { +static bool HasSameValue(const SCEV* A, const SCEV* B) { // Quick check to see if they are the same SCEV. if (A == B) return true; @@ -3946,8 +3945,8 @@ if (!PreCondLHS->getType()->isInteger()) continue; - SCEVHandle PreCondLHSSCEV = getSCEV(PreCondLHS); - SCEVHandle PreCondRHSSCEV = getSCEV(PreCondRHS); + const SCEV* PreCondLHSSCEV = getSCEV(PreCondLHS); + const SCEV* PreCondRHSSCEV = getSCEV(PreCondRHS); if ((HasSameValue(LHS, PreCondLHSSCEV) && HasSameValue(RHS, PreCondRHSSCEV)) || (HasSameValue(LHS, getNotSCEV(PreCondRHSSCEV)) && @@ -3961,22 +3960,22 @@ /// getBECount - Subtract the end and start values and divide by the step, /// rounding up, to get the number of times the backedge is executed. Return /// CouldNotCompute if an intermediate computation overflows. -SCEVHandle ScalarEvolution::getBECount(const SCEVHandle &Start, - const SCEVHandle &End, - const SCEVHandle &Step) { +const SCEV* ScalarEvolution::getBECount(const SCEV* Start, + const SCEV* End, + const SCEV* Step) { const Type *Ty = Start->getType(); - SCEVHandle NegOne = getIntegerSCEV(-1, Ty); - SCEVHandle Diff = getMinusSCEV(End, Start); - SCEVHandle RoundUp = getAddExpr(Step, NegOne); + const SCEV* NegOne = getIntegerSCEV(-1, Ty); + const SCEV* Diff = getMinusSCEV(End, Start); + const SCEV* RoundUp = getAddExpr(Step, NegOne); // Add an adjustment to the difference between End and Start so that // the division will effectively round up. - SCEVHandle Add = getAddExpr(Diff, RoundUp); + const SCEV* Add = getAddExpr(Diff, RoundUp); // Check Add for unsigned overflow. // TODO: More sophisticated things could be done here. const Type *WideTy = IntegerType::get(getTypeSizeInBits(Ty) + 1); - SCEVHandle OperandExtendedAdd = + const SCEV* OperandExtendedAdd = getAddExpr(getZeroExtendExpr(Diff, WideTy), getZeroExtendExpr(RoundUp, WideTy)); if (getZeroExtendExpr(Add, WideTy) != OperandExtendedAdd) @@ -4001,7 +4000,7 @@ if (AddRec->isAffine()) { // FORNOW: We only support unit strides. unsigned BitWidth = getTypeSizeInBits(AddRec->getType()); - SCEVHandle Step = AddRec->getStepRecurrence(*this); + const SCEV* Step = AddRec->getStepRecurrence(*this); // TODO: handle non-constant strides. const SCEVConstant *CStep = dyn_cast(Step); @@ -4037,10 +4036,10 @@ // treat m-n as signed nor unsigned due to overflow possibility. // First, we get the value of the LHS in the first iteration: n - SCEVHandle Start = AddRec->getOperand(0); + const SCEV* Start = AddRec->getOperand(0); // Determine the minimum constant start value. - SCEVHandle MinStart = isa(Start) ? Start : + const SCEV* MinStart = isa(Start) ? Start : getConstant(isSigned ? APInt::getSignedMinValue(BitWidth) : APInt::getMinValue(BitWidth)); @@ -4048,7 +4047,7 @@ // then we know that it will run exactly (m-n)/s times. Otherwise, we // only know that it will execute (max(m,n)-n)/s times. In both cases, // the division must round up. - SCEVHandle End = RHS; + const SCEV* End = RHS; if (!isLoopGuardedByCond(L, isSigned ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT, getMinusSCEV(Start, Step), RHS)) @@ -4056,7 +4055,7 @@ : getUMaxExpr(RHS, Start); // Determine the maximum constant end value. - SCEVHandle MaxEnd = + const SCEV* MaxEnd = isa(End) ? End : getConstant(isSigned ? APInt::getSignedMaxValue(BitWidth) .ashr(GetMinSignBits(End) - 1) : @@ -4065,11 +4064,11 @@ // Finally, we subtract these two values and divide, rounding up, to get // the number of times the backedge is executed. - SCEVHandle BECount = getBECount(Start, End, Step); + const SCEV* BECount = getBECount(Start, End, Step); // The maximum backedge count is similar, except using the minimum start // value and the maximum end value. - SCEVHandle MaxBECount = getBECount(MinStart, MaxEnd, Step);; + const SCEV* MaxBECount = getBECount(MinStart, MaxEnd, Step);; return BackedgeTakenInfo(BECount, MaxBECount); } @@ -4082,7 +4081,7 @@ /// this is that it returns the first iteration number where the value is not in /// the condition, thus computing the exit count. If the iteration count can't /// be computed, an instance of SCEVCouldNotCompute is returned. -SCEVHandle SCEVAddRecExpr::getNumIterationsInRange(ConstantRange Range, +const SCEV* SCEVAddRecExpr::getNumIterationsInRange(ConstantRange Range, ScalarEvolution &SE) const { if (Range.isFullSet()) // Infinite loop. return SE.getCouldNotCompute(); @@ -4090,9 +4089,9 @@ // If the start is a non-zero constant, shift the range to simplify things. if (const SCEVConstant *SC = dyn_cast(getStart())) if (!SC->getValue()->isZero()) { - SmallVector Operands(op_begin(), op_end()); + SmallVector Operands(op_begin(), op_end()); Operands[0] = SE.getIntegerSCEV(0, SC->getType()); - SCEVHandle Shifted = SE.getAddRecExpr(Operands, getLoop()); + const SCEV* Shifted = SE.getAddRecExpr(Operands, getLoop()); if (const SCEVAddRecExpr *ShiftedAddRec = dyn_cast(Shifted)) return ShiftedAddRec->getNumIterationsInRange( @@ -4151,12 +4150,12 @@ // quadratic equation to solve it. To do this, we must frame our problem in // terms of figuring out when zero is crossed, instead of when // Range.getUpper() is crossed. - SmallVector NewOps(op_begin(), op_end()); + SmallVector NewOps(op_begin(), op_end()); NewOps[0] = SE.getNegativeSCEV(SE.getConstant(Range.getUpper())); - SCEVHandle NewAddRec = SE.getAddRecExpr(NewOps, getLoop()); + const SCEV* NewAddRec = SE.getAddRecExpr(NewOps, getLoop()); // Next, solve the constructed addrec - std::pair Roots = + std::pair Roots = SolveQuadraticEquation(cast(NewAddRec), SE); const SCEVConstant *R1 = dyn_cast(Roots.first); const SCEVConstant *R2 = dyn_cast(Roots.second); @@ -4363,12 +4362,12 @@ if (isSCEVable(I->getType())) { OS << *I; OS << " --> "; - SCEVHandle SV = SE.getSCEV(&*I); + const SCEV* SV = SE.getSCEV(&*I); SV->print(OS); const Loop *L = LI->getLoopFor((*I).getParent()); - SCEVHandle AtUse = SE.getSCEVAtScope(SV, L); + const SCEV* AtUse = SE.getSCEVAtScope(SV, L); if (AtUse != SV) { OS << " --> "; AtUse->print(OS); @@ -4376,7 +4375,7 @@ if (L) { OS << "\t\t" "Exits: "; - SCEVHandle ExitValue = SE.getSCEVAtScope(SV, L->getParentLoop()); + const SCEV* ExitValue = SE.getSCEVAtScope(SV, L->getParentLoop()); if (!ExitValue->isLoopInvariant(L)) { OS << "<>"; } else { Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=73906&r1=73905&r2=73906&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Mon Jun 22 16:39:50 2009 @@ -152,8 +152,8 @@ /// TODO: When ScalarEvolution gets a SCEVSDivExpr, this can be made /// unnecessary; in its place, just signed-divide Ops[i] by the scale and /// check to see if the divide was folded. -static bool FactorOutConstant(SCEVHandle &S, - SCEVHandle &Remainder, +static bool FactorOutConstant(const SCEV* &S, + const SCEV* &Remainder, const APInt &Factor, ScalarEvolution &SE) { // Everything is divisible by one. @@ -168,7 +168,7 @@ // the value at this scale. It will be considered for subsequent // smaller scales. if (C->isZero() || !CI->isZero()) { - SCEVHandle Div = SE.getConstant(CI); + const SCEV* Div = SE.getConstant(CI); S = Div; Remainder = SE.getAddExpr(Remainder, @@ -182,8 +182,8 @@ if (const SCEVMulExpr *M = dyn_cast(S)) if (const SCEVConstant *C = dyn_cast(M->getOperand(0))) if (!C->getValue()->getValue().srem(Factor)) { - const SmallVectorImpl &MOperands = M->getOperands(); - SmallVector NewMulOps(MOperands.begin(), MOperands.end()); + const SmallVectorImpl &MOperands = M->getOperands(); + SmallVector NewMulOps(MOperands.begin(), MOperands.end()); NewMulOps[0] = SE.getConstant(C->getValue()->getValue().sdiv(Factor)); S = SE.getMulExpr(NewMulOps); @@ -192,13 +192,13 @@ // In an AddRec, check if both start and step are divisible. if (const SCEVAddRecExpr *A = dyn_cast(S)) { - SCEVHandle Step = A->getStepRecurrence(SE); - SCEVHandle StepRem = SE.getIntegerSCEV(0, Step->getType()); + const SCEV* Step = A->getStepRecurrence(SE); + const SCEV* StepRem = SE.getIntegerSCEV(0, Step->getType()); if (!FactorOutConstant(Step, StepRem, Factor, SE)) return false; if (!StepRem->isZero()) return false; - SCEVHandle Start = A->getStart(); + const SCEV* Start = A->getStart(); if (!FactorOutConstant(Start, Remainder, Factor, SE)) return false; S = SE.getAddRecExpr(Start, Step, A->getLoop()); @@ -233,14 +233,14 @@ /// loop-invariant portions of expressions, after considering what /// can be folded using target addressing modes. /// -Value *SCEVExpander::expandAddToGEP(const SCEVHandle *op_begin, - const SCEVHandle *op_end, +Value *SCEVExpander::expandAddToGEP(const SCEV* const *op_begin, + const SCEV* const *op_end, const PointerType *PTy, const Type *Ty, Value *V) { const Type *ElTy = PTy->getElementType(); SmallVector GepIndices; - SmallVector Ops(op_begin, op_end); + SmallVector Ops(op_begin, op_end); bool AnyNonZeroIndices = false; // Decend down the pointer's type and attempt to convert the other @@ -251,14 +251,14 @@ for (;;) { APInt ElSize = APInt(SE.getTypeSizeInBits(Ty), ElTy->isSized() ? SE.TD->getTypeAllocSize(ElTy) : 0); - SmallVector NewOps; - SmallVector ScaledOps; + SmallVector NewOps; + SmallVector ScaledOps; for (unsigned i = 0, e = Ops.size(); i != e; ++i) { // Split AddRecs up into parts as either of the parts may be usable // without the other. if (const SCEVAddRecExpr *A = dyn_cast(Ops[i])) if (!A->getStart()->isZero()) { - SCEVHandle Start = A->getStart(); + const SCEV* Start = A->getStart(); Ops.push_back(SE.getAddRecExpr(SE.getIntegerSCEV(0, A->getType()), A->getStepRecurrence(SE), A->getLoop())); @@ -267,8 +267,8 @@ } // If the scale size is not 0, attempt to factor out a scale. if (ElSize != 0) { - SCEVHandle Op = Ops[i]; - SCEVHandle Remainder = SE.getIntegerSCEV(0, Op->getType()); + const SCEV* Op = Ops[i]; + const SCEV* Remainder = SE.getIntegerSCEV(0, Op->getType()); if (FactorOutConstant(Op, Remainder, ElSize, SE)) { ScaledOps.push_back(Op); // Op now has ElSize factored out. NewOps.push_back(Remainder); @@ -364,7 +364,7 @@ // comments on expandAddToGEP for details. if (SE.TD) if (const PointerType *PTy = dyn_cast(V->getType())) { - const SmallVectorImpl &Ops = S->getOperands(); + const SmallVectorImpl &Ops = S->getOperands(); return expandAddToGEP(&Ops[0], &Ops[Ops.size() - 1], PTy, Ty, V); } @@ -420,7 +420,7 @@ /// Move parts of Base into Rest to leave Base with the minimal /// expression that provides a pointer operand suitable for a /// GEP expansion. -static void ExposePointerBase(SCEVHandle &Base, SCEVHandle &Rest, +static void ExposePointerBase(const SCEV* &Base, const SCEV* &Rest, ScalarEvolution &SE) { while (const SCEVAddRecExpr *A = dyn_cast(Base)) { Base = A->getStart(); @@ -431,7 +431,7 @@ } if (const SCEVAddExpr *A = dyn_cast(Base)) { Base = A->getOperand(A->getNumOperands()-1); - SmallVector NewAddOps(A->op_begin(), A->op_end()); + SmallVector NewAddOps(A->op_begin(), A->op_end()); NewAddOps.back() = Rest; Rest = SE.getAddExpr(NewAddOps); ExposePointerBase(Base, Rest, SE); @@ -455,9 +455,9 @@ if (CanonicalIV && SE.getTypeSizeInBits(CanonicalIV->getType()) > SE.getTypeSizeInBits(Ty)) { - SCEVHandle Start = SE.getAnyExtendExpr(S->getStart(), + const SCEV* Start = SE.getAnyExtendExpr(S->getStart(), CanonicalIV->getType()); - SCEVHandle Step = SE.getAnyExtendExpr(S->getStepRecurrence(SE), + const SCEV* Step = SE.getAnyExtendExpr(S->getStepRecurrence(SE), CanonicalIV->getType()); Value *V = expand(SE.getAddRecExpr(Start, Step, S->getLoop())); BasicBlock::iterator SaveInsertPt = getInsertionPoint(); @@ -472,16 +472,16 @@ // {X,+,F} --> X + {0,+,F} if (!S->getStart()->isZero()) { - const SmallVectorImpl &SOperands = S->getOperands(); - SmallVector NewOps(SOperands.begin(), SOperands.end()); + const SmallVectorImpl &SOperands = S->getOperands(); + SmallVector NewOps(SOperands.begin(), SOperands.end()); NewOps[0] = SE.getIntegerSCEV(0, Ty); - SCEVHandle Rest = SE.getAddRecExpr(NewOps, L); + const SCEV* Rest = SE.getAddRecExpr(NewOps, L); // Turn things like ptrtoint+arithmetic+inttoptr into GEP. See the // comments on expandAddToGEP for details. if (SE.TD) { - SCEVHandle Base = S->getStart(); - SCEVHandle RestArray[1] = { Rest }; + const SCEV* Base = S->getStart(); + const SCEV* RestArray[1] = { Rest }; // Dig into the expression to find the pointer base for a GEP. ExposePointerBase(Base, RestArray[0], SE); // If we found a pointer, expand the AddRec with a GEP. @@ -581,19 +581,19 @@ // folders, then expandCodeFor the closed form. This allows the folders to // simplify the expression without having to build a bunch of special code // into this folder. - SCEVHandle IH = SE.getUnknown(I); // Get I as a "symbolic" SCEV. + const SCEV* IH = SE.getUnknown(I); // Get I as a "symbolic" SCEV. // Promote S up to the canonical IV type, if the cast is foldable. - SCEVHandle NewS = S; - SCEVHandle Ext = SE.getNoopOrAnyExtend(S, I->getType()); + const SCEV* NewS = S; + const SCEV* Ext = SE.getNoopOrAnyExtend(S, I->getType()); if (isa(Ext)) NewS = Ext; - SCEVHandle V = cast(NewS)->evaluateAtIteration(IH, SE); + const SCEV* V = cast(NewS)->evaluateAtIteration(IH, SE); //cerr << "Evaluated: " << *this << "\n to: " << *V << "\n"; // Truncate the result down to the original type, if needed. - SCEVHandle T = SE.getTruncateOrNoop(V, Ty); + const SCEV* T = SE.getTruncateOrNoop(V, Ty); return expand(V); } @@ -654,7 +654,7 @@ return LHS; } -Value *SCEVExpander::expandCodeFor(SCEVHandle SH, const Type *Ty) { +Value *SCEVExpander::expandCodeFor(const SCEV* SH, const Type *Ty) { // Expand the code for this SCEV. Value *V = expand(SH); if (Ty) { @@ -667,7 +667,7 @@ Value *SCEVExpander::expand(const SCEV *S) { // Check to see if we already expanded this. - std::map >::iterator I = + std::map >::iterator I = InsertedExpressions.find(S); if (I != InsertedExpressions.end()) return I->second; @@ -685,7 +685,7 @@ SCEVExpander::getOrInsertCanonicalInductionVariable(const Loop *L, const Type *Ty) { assert(Ty->isInteger() && "Can only insert integer induction variables!"); - SCEVHandle H = SE.getAddRecExpr(SE.getIntegerSCEV(0, Ty), + const SCEV* H = SE.getAddRecExpr(SE.getIntegerSCEV(0, Ty), SE.getIntegerSCEV(1, Ty), L); return expand(H); } Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=73906&r1=73905&r2=73906&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Mon Jun 22 16:39:50 2009 @@ -96,7 +96,7 @@ void RewriteNonIntegerIVs(Loop *L); - ICmpInst *LinearFunctionTestReplace(Loop *L, SCEVHandle BackedgeTakenCount, + ICmpInst *LinearFunctionTestReplace(Loop *L, const SCEV* BackedgeTakenCount, Value *IndVar, BasicBlock *ExitingBlock, BranchInst *BI, @@ -128,7 +128,7 @@ /// SCEV analysis can determine a loop-invariant trip count of the loop, which /// is actually a much broader range than just linear tests. ICmpInst *IndVarSimplify::LinearFunctionTestReplace(Loop *L, - SCEVHandle BackedgeTakenCount, + const SCEV* BackedgeTakenCount, Value *IndVar, BasicBlock *ExitingBlock, BranchInst *BI, @@ -137,13 +137,13 @@ // against the preincremented value, otherwise we prefer to compare against // the post-incremented value. Value *CmpIndVar; - SCEVHandle RHS = BackedgeTakenCount; + const SCEV* RHS = BackedgeTakenCount; if (ExitingBlock == L->getLoopLatch()) { // Add one to the "backedge-taken" count to get the trip count. // If this addition may overflow, we have to be more pessimistic and // cast the induction variable before doing the add. - SCEVHandle Zero = SE->getIntegerSCEV(0, BackedgeTakenCount->getType()); - SCEVHandle N = + const SCEV* Zero = SE->getIntegerSCEV(0, BackedgeTakenCount->getType()); + const SCEV* N = SE->getAddExpr(BackedgeTakenCount, SE->getIntegerSCEV(1, BackedgeTakenCount->getType())); if ((isa(N) && !N->isZero()) || @@ -278,7 +278,7 @@ // Okay, this instruction has a user outside of the current loop // and varies predictably *inside* the loop. Evaluate the value it // contains when the loop exits, if possible. - SCEVHandle ExitValue = SE->getSCEVAtScope(Inst, L->getParentLoop()); + const SCEV* ExitValue = SE->getSCEVAtScope(Inst, L->getParentLoop()); if (!ExitValue->isLoopInvariant(L)) continue; @@ -348,7 +348,7 @@ BasicBlock *Header = L->getHeader(); BasicBlock *ExitingBlock = L->getExitingBlock(); // may be null - SCEVHandle BackedgeTakenCount = SE->getBackedgeTakenCount(L); + const SCEV* BackedgeTakenCount = SE->getBackedgeTakenCount(L); // Check to see if this loop has a computable loop-invariant execution count. // If so, this means that we can compute the final value of any expressions @@ -373,14 +373,14 @@ NeedCannIV = true; } for (unsigned i = 0, e = IU->StrideOrder.size(); i != e; ++i) { - SCEVHandle Stride = IU->StrideOrder[i]; + const SCEV* Stride = IU->StrideOrder[i]; const Type *Ty = SE->getEffectiveSCEVType(Stride->getType()); if (!LargestType || SE->getTypeSizeInBits(Ty) > SE->getTypeSizeInBits(LargestType)) LargestType = Ty; - std::map::iterator SI = + std::map::iterator SI = IU->IVUsesByStride.find(IU->StrideOrder[i]); assert(SI != IU->IVUsesByStride.end() && "Stride doesn't exist!"); @@ -473,21 +473,21 @@ // the need for the code evaluation methods to insert induction variables // of different sizes. for (unsigned i = 0, e = IU->StrideOrder.size(); i != e; ++i) { - SCEVHandle Stride = IU->StrideOrder[i]; + const SCEV* Stride = IU->StrideOrder[i]; - std::map::iterator SI = + std::map::iterator SI = IU->IVUsesByStride.find(IU->StrideOrder[i]); assert(SI != IU->IVUsesByStride.end() && "Stride doesn't exist!"); ilist &List = SI->second->Users; for (ilist::iterator UI = List.begin(), E = List.end(); UI != E; ++UI) { - SCEVHandle Offset = UI->getOffset(); + const SCEV* Offset = UI->getOffset(); Value *Op = UI->getOperandValToReplace(); const Type *UseTy = Op->getType(); Instruction *User = UI->getUser(); // Compute the final addrec to expand into code. - SCEVHandle AR = IU->getReplacementExpr(*UI); + const SCEV* AR = IU->getReplacementExpr(*UI); Value *NewVal = 0; if (AR->isLoopInvariant(L)) { Modified: llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp?rev=73906&r1=73905&r2=73906&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp Mon Jun 22 16:39:50 2009 @@ -187,7 +187,7 @@ // Don't remove loops for which we can't solve the trip count. // They could be infinite, in which case we'd be changing program behavior. ScalarEvolution& SE = getAnalysis(); - SCEVHandle S = SE.getBackedgeTakenCount(L); + const SCEV* S = SE.getBackedgeTakenCount(L); if (isa(S)) return false; Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=73906&r1=73905&r2=73906&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Mon Jun 22 16:39:50 2009 @@ -64,11 +64,11 @@ /// StrengthReduceStridedIVUsers. It contains the stride, the common base, as /// well as the PHI node and increment value created for rewrite. struct VISIBILITY_HIDDEN IVExpr { - SCEVHandle Stride; - SCEVHandle Base; + const SCEV* Stride; + const SCEV* Base; PHINode *PHI; - IVExpr(const SCEVHandle &stride, const SCEVHandle &base, PHINode *phi) + IVExpr(const SCEV* const stride, const SCEV* const base, PHINode *phi) : Stride(stride), Base(base), PHI(phi) {} }; @@ -77,7 +77,7 @@ struct VISIBILITY_HIDDEN IVsOfOneStride { std::vector IVs; - void addIV(const SCEVHandle &Stride, const SCEVHandle &Base, PHINode *PHI) { + void addIV(const SCEV* const Stride, const SCEV* const Base, PHINode *PHI) { IVs.push_back(IVExpr(Stride, Base, PHI)); } }; @@ -91,11 +91,11 @@ /// IVsByStride - Keep track of all IVs that have been inserted for a /// particular stride. - std::map IVsByStride; + std::map IVsByStride; /// StrideNoReuse - Keep track of all the strides whose ivs cannot be /// reused (nor should they be rewritten to reuse other strides). - SmallSet StrideNoReuse; + SmallSet StrideNoReuse; /// DeadInsts - Keep track of instructions we may have made dead, so that /// we can remove them after we are done working. @@ -133,7 +133,7 @@ private: ICmpInst *ChangeCompareStride(Loop *L, ICmpInst *Cond, IVStrideUse* &CondUse, - const SCEVHandle* &CondStride); + const SCEV* const * &CondStride); void OptimizeIndvars(Loop *L); void OptimizeLoopCountIV(Loop *L); @@ -149,16 +149,16 @@ IVStrideUse* &CondUse); bool FindIVUserForCond(ICmpInst *Cond, IVStrideUse *&CondUse, - const SCEVHandle *&CondStride); + const SCEV* const * &CondStride); bool RequiresTypeConversion(const Type *Ty, const Type *NewTy); - SCEVHandle CheckForIVReuse(bool, bool, bool, const SCEVHandle&, + const SCEV* CheckForIVReuse(bool, bool, bool, const SCEV* const&, IVExpr&, const Type*, const std::vector& UsersToProcess); bool ValidScale(bool, int64_t, const std::vector& UsersToProcess); bool ValidOffset(bool, int64_t, int64_t, const std::vector& UsersToProcess); - SCEVHandle CollectIVUsers(const SCEVHandle &Stride, + const SCEV* CollectIVUsers(const SCEV* const &Stride, IVUsersOfOneStride &Uses, Loop *L, bool &AllUsesAreAddresses, @@ -168,11 +168,11 @@ const std::vector &UsersToProcess, const Loop *L, bool AllUsesAreAddresses, - SCEVHandle Stride); + const SCEV* Stride); void PrepareToStrengthReduceFully( std::vector &UsersToProcess, - SCEVHandle Stride, - SCEVHandle CommonExprs, + const SCEV* Stride, + const SCEV* CommonExprs, const Loop *L, SCEVExpander &PreheaderRewriter); void PrepareToStrengthReduceFromSmallerStride( @@ -182,13 +182,13 @@ Instruction *PreInsertPt); void PrepareToStrengthReduceWithNewPhi( std::vector &UsersToProcess, - SCEVHandle Stride, - SCEVHandle CommonExprs, + const SCEV* Stride, + const SCEV* CommonExprs, Value *CommonBaseV, Instruction *IVIncInsertPt, const Loop *L, SCEVExpander &PreheaderRewriter); - void StrengthReduceStridedIVUsers(const SCEVHandle &Stride, + void StrengthReduceStridedIVUsers(const SCEV* const &Stride, IVUsersOfOneStride &Uses, Loop *L); void DeleteTriviallyDeadInstructions(); @@ -232,7 +232,7 @@ /// containsAddRecFromDifferentLoop - Determine whether expression S involves a /// subexpression that is an AddRec from a loop other than L. An outer loop /// of L is OK, but not an inner loop nor a disjoint loop. -static bool containsAddRecFromDifferentLoop(SCEVHandle S, Loop *L) { +static bool containsAddRecFromDifferentLoop(const SCEV* S, Loop *L) { // This is very common, put it first. if (isa(S)) return false; @@ -327,7 +327,7 @@ /// this use. As the use is processed, information gets moved from this /// field to the Imm field (below). BasedUser values are sorted by this /// field. - SCEVHandle Base; + const SCEV* Base; /// Inst - The instruction using the induction variable. Instruction *Inst; @@ -340,7 +340,7 @@ /// before Inst, because it will be folded into the imm field of the /// instruction. This is also sometimes used for loop-variant values that /// must be added inside the loop. - SCEVHandle Imm; + const SCEV* Imm; /// Phi - The induction variable that performs the striding that /// should be used for this user. @@ -362,13 +362,13 @@ // Once we rewrite the code to insert the new IVs we want, update the // operands of Inst to use the new expression 'NewBase', with 'Imm' added // to it. - void RewriteInstructionToUseNewBase(const SCEVHandle &NewBase, + void RewriteInstructionToUseNewBase(const SCEV* const &NewBase, Instruction *InsertPt, SCEVExpander &Rewriter, Loop *L, Pass *P, LoopInfo &LI, SmallVectorImpl &DeadInsts); - Value *InsertCodeForBaseAtPosition(const SCEVHandle &NewBase, + Value *InsertCodeForBaseAtPosition(const SCEV* const &NewBase, const Type *Ty, SCEVExpander &Rewriter, Instruction *IP, Loop *L, @@ -383,7 +383,7 @@ cerr << " Inst: " << *Inst; } -Value *BasedUser::InsertCodeForBaseAtPosition(const SCEVHandle &NewBase, +Value *BasedUser::InsertCodeForBaseAtPosition(const SCEV* const &NewBase, const Type *Ty, SCEVExpander &Rewriter, Instruction *IP, Loop *L, @@ -407,7 +407,7 @@ Value *Base = Rewriter.expandCodeFor(NewBase, 0, BaseInsertPt); - SCEVHandle NewValSCEV = SE->getUnknown(Base); + const SCEV* NewValSCEV = SE->getUnknown(Base); // If there is no immediate value, skip the next part. if (!Imm->isZero()) { @@ -430,7 +430,7 @@ // value of NewBase in the case that it's a diffferent instruction from // the PHI that NewBase is computed from, or null otherwise. // -void BasedUser::RewriteInstructionToUseNewBase(const SCEVHandle &NewBase, +void BasedUser::RewriteInstructionToUseNewBase(const SCEV* const &NewBase, Instruction *NewBasePt, SCEVExpander &Rewriter, Loop *L, Pass *P, LoopInfo &LI, @@ -542,7 +542,7 @@ /// fitsInAddressMode - Return true if V can be subsumed within an addressing /// mode, and does not need to be put in a register first. -static bool fitsInAddressMode(const SCEVHandle &V, const Type *AccessTy, +static bool fitsInAddressMode(const SCEV* const &V, const Type *AccessTy, const TargetLowering *TLI, bool HasBaseReg) { if (const SCEVConstant *SC = dyn_cast(V)) { int64_t VC = SC->getValue()->getSExtValue(); @@ -574,12 +574,12 @@ /// MoveLoopVariantsToImmediateField - Move any subexpressions from Val that are /// loop varying to the Imm operand. -static void MoveLoopVariantsToImmediateField(SCEVHandle &Val, SCEVHandle &Imm, +static void MoveLoopVariantsToImmediateField(const SCEV* &Val, const SCEV* &Imm, Loop *L, ScalarEvolution *SE) { if (Val->isLoopInvariant(L)) return; // Nothing to do. if (const SCEVAddExpr *SAE = dyn_cast(Val)) { - SmallVector NewOps; + SmallVector NewOps; NewOps.reserve(SAE->getNumOperands()); for (unsigned i = 0; i != SAE->getNumOperands(); ++i) @@ -597,10 +597,10 @@ Val = SE->getAddExpr(NewOps); } else if (const SCEVAddRecExpr *SARE = dyn_cast(Val)) { // Try to pull immediates out of the start value of nested addrec's. - SCEVHandle Start = SARE->getStart(); + const SCEV* Start = SARE->getStart(); MoveLoopVariantsToImmediateField(Start, Imm, L, SE); - SmallVector Ops(SARE->op_begin(), SARE->op_end()); + SmallVector Ops(SARE->op_begin(), SARE->op_end()); Ops[0] = Start; Val = SE->getAddRecExpr(Ops, SARE->getLoop()); } else { @@ -616,15 +616,15 @@ /// Accumulate these immediate values into the Imm value. static void MoveImmediateValues(const TargetLowering *TLI, const Type *AccessTy, - SCEVHandle &Val, SCEVHandle &Imm, + const SCEV* &Val, const SCEV* &Imm, bool isAddress, Loop *L, ScalarEvolution *SE) { if (const SCEVAddExpr *SAE = dyn_cast(Val)) { - SmallVector NewOps; + SmallVector NewOps; NewOps.reserve(SAE->getNumOperands()); for (unsigned i = 0; i != SAE->getNumOperands(); ++i) { - SCEVHandle NewOp = SAE->getOperand(i); + const SCEV* NewOp = SAE->getOperand(i); MoveImmediateValues(TLI, AccessTy, NewOp, Imm, isAddress, L, SE); if (!NewOp->isLoopInvariant(L)) { @@ -643,11 +643,11 @@ return; } else if (const SCEVAddRecExpr *SARE = dyn_cast(Val)) { // Try to pull immediates out of the start value of nested addrec's. - SCEVHandle Start = SARE->getStart(); + const SCEV* Start = SARE->getStart(); MoveImmediateValues(TLI, AccessTy, Start, Imm, isAddress, L, SE); if (Start != SARE->getStart()) { - SmallVector Ops(SARE->op_begin(), SARE->op_end()); + SmallVector Ops(SARE->op_begin(), SARE->op_end()); Ops[0] = Start; Val = SE->getAddRecExpr(Ops, SARE->getLoop()); } @@ -658,8 +658,8 @@ fitsInAddressMode(SME->getOperand(0), AccessTy, TLI, false) && SME->getNumOperands() == 2 && SME->isLoopInvariant(L)) { - SCEVHandle SubImm = SE->getIntegerSCEV(0, Val->getType()); - SCEVHandle NewOp = SME->getOperand(1); + const SCEV* SubImm = SE->getIntegerSCEV(0, Val->getType()); + const SCEV* NewOp = SME->getOperand(1); MoveImmediateValues(TLI, AccessTy, NewOp, SubImm, isAddress, L, SE); // If we extracted something out of the subexpressions, see if we can @@ -694,7 +694,7 @@ static void MoveImmediateValues(const TargetLowering *TLI, Instruction *User, - SCEVHandle &Val, SCEVHandle &Imm, + const SCEV* &Val, const SCEV* &Imm, bool isAddress, Loop *L, ScalarEvolution *SE) { const Type *AccessTy = getAccessType(User); @@ -704,19 +704,19 @@ /// SeparateSubExprs - Decompose Expr into all of the subexpressions that are /// added together. This is used to reassociate common addition subexprs /// together for maximal sharing when rewriting bases. -static void SeparateSubExprs(SmallVector &SubExprs, - SCEVHandle Expr, +static void SeparateSubExprs(SmallVector &SubExprs, + const SCEV* Expr, ScalarEvolution *SE) { if (const SCEVAddExpr *AE = dyn_cast(Expr)) { for (unsigned j = 0, e = AE->getNumOperands(); j != e; ++j) SeparateSubExprs(SubExprs, AE->getOperand(j), SE); } else if (const SCEVAddRecExpr *SARE = dyn_cast(Expr)) { - SCEVHandle Zero = SE->getIntegerSCEV(0, Expr->getType()); + const SCEV* Zero = SE->getIntegerSCEV(0, Expr->getType()); if (SARE->getOperand(0) == Zero) { SubExprs.push_back(Expr); } else { // Compute the addrec with zero as its base. - SmallVector Ops(SARE->op_begin(), SARE->op_end()); + SmallVector Ops(SARE->op_begin(), SARE->op_end()); Ops[0] = Zero; // Start with zero base. SubExprs.push_back(SE->getAddRecExpr(Ops, SARE->getLoop())); @@ -740,7 +740,7 @@ /// not remove anything. This looks for things like (a+b+c) and /// (a+c+d) and computes the common (a+c) subexpression. The common expression /// is *removed* from the Bases and returned. -static SCEVHandle +static const SCEV* RemoveCommonExpressionsFromUseBases(std::vector &Uses, ScalarEvolution *SE, Loop *L, const TargetLowering *TLI) { @@ -748,9 +748,9 @@ // Only one use? This is a very common case, so we handle it specially and // cheaply. - SCEVHandle Zero = SE->getIntegerSCEV(0, Uses[0].Base->getType()); - SCEVHandle Result = Zero; - SCEVHandle FreeResult = Zero; + const SCEV* Zero = SE->getIntegerSCEV(0, Uses[0].Base->getType()); + const SCEV* Result = Zero; + const SCEV* FreeResult = Zero; if (NumUses == 1) { // If the use is inside the loop, use its base, regardless of what it is: // it is clearly shared across all the IV's. If the use is outside the loop @@ -766,13 +766,13 @@ // Also track whether all uses of each expression can be moved into an // an addressing mode "for free"; such expressions are left within the loop. // struct SubExprUseData { unsigned Count; bool notAllUsesAreFree; }; - std::map SubExpressionUseData; + std::map SubExpressionUseData; // UniqueSubExprs - Keep track of all of the subexpressions we see in the // order we see them. - SmallVector UniqueSubExprs; + SmallVector UniqueSubExprs; - SmallVector SubExprs; + SmallVector SubExprs; unsigned NumUsesInsideLoop = 0; for (unsigned i = 0; i != NumUses; ++i) { // If the user is outside the loop, just ignore it for base computation. @@ -816,7 +816,7 @@ // Now that we know how many times each is used, build Result. Iterate over // UniqueSubexprs so that we have a stable ordering. for (unsigned i = 0, e = UniqueSubExprs.size(); i != e; ++i) { - std::map::iterator I = + std::map::iterator I = SubExpressionUseData.find(UniqueSubExprs[i]); assert(I != SubExpressionUseData.end() && "Entry not found?"); if (I->second.Count == NumUsesInsideLoop) { // Found CSE! @@ -860,7 +860,7 @@ if (FreeResult != Zero) { SeparateSubExprs(SubExprs, FreeResult, SE); for (unsigned j = 0, e = SubExprs.size(); j != e; ++j) { - std::map::iterator I = + std::map::iterator I = SubExpressionUseData.find(SubExprs[j]); SubExpressionUseData.erase(I); } @@ -989,10 +989,10 @@ /// be folded into the addressing mode, nor even that the factor be constant; /// a multiply (executed once) outside the loop is better than another IV /// within. Well, usually. -SCEVHandle LoopStrengthReduce::CheckForIVReuse(bool HasBaseReg, +const SCEV* LoopStrengthReduce::CheckForIVReuse(bool HasBaseReg, bool AllUsesAreAddresses, bool AllUsesAreOutsideLoop, - const SCEVHandle &Stride, + const SCEV* const &Stride, IVExpr &IV, const Type *Ty, const std::vector& UsersToProcess) { if (StrideNoReuse.count(Stride)) @@ -1002,7 +1002,7 @@ int64_t SInt = SC->getValue()->getSExtValue(); for (unsigned NewStride = 0, e = IU->StrideOrder.size(); NewStride != e; ++NewStride) { - std::map::iterator SI = + std::map::iterator SI = IVsByStride.find(IU->StrideOrder[NewStride]); if (SI == IVsByStride.end() || !isa(SI->first) || StrideNoReuse.count(SI->first)) @@ -1055,7 +1055,7 @@ // an existing IV if we can. for (unsigned NewStride = 0, e = IU->StrideOrder.size(); NewStride != e; ++NewStride) { - std::map::iterator SI = + std::map::iterator SI = IVsByStride.find(IU->StrideOrder[NewStride]); if (SI == IVsByStride.end() || !isa(SI->first)) continue; @@ -1075,7 +1075,7 @@ // -1*old. for (unsigned NewStride = 0, e = IU->StrideOrder.size(); NewStride != e; ++NewStride) { - std::map::iterator SI = + std::map::iterator SI = IVsByStride.find(IU->StrideOrder[NewStride]); if (SI == IVsByStride.end()) continue; @@ -1104,7 +1104,7 @@ /// isNonConstantNegative - Return true if the specified scev is negated, but /// not a constant. -static bool isNonConstantNegative(const SCEVHandle &Expr) { +static bool isNonConstantNegative(const SCEV* const &Expr) { const SCEVMulExpr *Mul = dyn_cast(Expr); if (!Mul) return false; @@ -1121,7 +1121,7 @@ /// of the strided accesses, as well as the old information from Uses. We /// progressively move information from the Base field to the Imm field, until /// we eventually have the full access expression to rewrite the use. -SCEVHandle LoopStrengthReduce::CollectIVUsers(const SCEVHandle &Stride, +const SCEV* LoopStrengthReduce::CollectIVUsers(const SCEV* const &Stride, IVUsersOfOneStride &Uses, Loop *L, bool &AllUsesAreAddresses, @@ -1152,7 +1152,7 @@ // for the strides (e.g. if we have "A+C+B" and "A+B+D" as our bases, find // "A+B"), emit it to the preheader, then remove the expression from the // UsersToProcess base values. - SCEVHandle CommonExprs = + const SCEV* CommonExprs = RemoveCommonExpressionsFromUseBases(UsersToProcess, SE, L, TLI); // Next, figure out what we can represent in the immediate fields of @@ -1218,7 +1218,7 @@ const std::vector &UsersToProcess, const Loop *L, bool AllUsesAreAddresses, - SCEVHandle Stride) { + const SCEV* Stride) { if (!EnableFullLSRMode) return false; @@ -1255,7 +1255,7 @@ if (!Imm) Imm = SE->getIntegerSCEV(0, Stride->getType()); const Instruction *Inst = UsersToProcess[i].Inst; const Type *AccessTy = getAccessType(Inst); - SCEVHandle Diff = SE->getMinusSCEV(UsersToProcess[i].Imm, Imm); + const SCEV* Diff = SE->getMinusSCEV(UsersToProcess[i].Imm, Imm); if (!Diff->isZero() && (!AllUsesAreAddresses || !fitsInAddressMode(Diff, AccessTy, TLI, /*HasBaseReg=*/true))) @@ -1289,7 +1289,7 @@ /// /// Return the created phi node. /// -static PHINode *InsertAffinePhi(SCEVHandle Start, SCEVHandle Step, +static PHINode *InsertAffinePhi(const SCEV* Start, const SCEV* Step, Instruction *IVIncInsertPt, const Loop *L, SCEVExpander &Rewriter) { @@ -1309,7 +1309,7 @@ // If the stride is negative, insert a sub instead of an add for the // increment. bool isNegative = isNonConstantNegative(Step); - SCEVHandle IncAmount = Step; + const SCEV* IncAmount = Step; if (isNegative) IncAmount = Rewriter.SE.getNegativeSCEV(Step); @@ -1348,13 +1348,13 @@ // loop before users outside of the loop with a particular base. // // We would like to use stable_sort here, but we can't. The problem is that - // SCEVHandle's don't have a deterministic ordering w.r.t to each other, so + // const SCEV*'s don't have a deterministic ordering w.r.t to each other, so // we don't have anything to do a '<' comparison on. Because we think the // number of uses is small, do a horrible bubble sort which just relies on // ==. for (unsigned i = 0, e = UsersToProcess.size(); i != e; ++i) { // Get a base value. - SCEVHandle Base = UsersToProcess[i].Base; + const SCEV* Base = UsersToProcess[i].Base; // Compact everything with this base to be consecutive with this one. for (unsigned j = i+1; j != e; ++j) { @@ -1373,8 +1373,8 @@ void LoopStrengthReduce::PrepareToStrengthReduceFully( std::vector &UsersToProcess, - SCEVHandle Stride, - SCEVHandle CommonExprs, + const SCEV* Stride, + const SCEV* CommonExprs, const Loop *L, SCEVExpander &PreheaderRewriter) { DOUT << " Fully reducing all users\n"; @@ -1386,9 +1386,9 @@ // TODO: The uses are grouped by base, but not sorted. We arbitrarily // pick the first Imm value here to start with, and adjust it for the // other uses. - SCEVHandle Imm = UsersToProcess[i].Imm; - SCEVHandle Base = UsersToProcess[i].Base; - SCEVHandle Start = SE->getAddExpr(CommonExprs, Base, Imm); + const SCEV* Imm = UsersToProcess[i].Imm; + const SCEV* Base = UsersToProcess[i].Base; + const SCEV* Start = SE->getAddExpr(CommonExprs, Base, Imm); PHINode *Phi = InsertAffinePhi(Start, Stride, IVIncInsertPt, L, PreheaderRewriter); // Loop over all the users with the same base. @@ -1420,8 +1420,8 @@ void LoopStrengthReduce::PrepareToStrengthReduceWithNewPhi( std::vector &UsersToProcess, - SCEVHandle Stride, - SCEVHandle CommonExprs, + const SCEV* Stride, + const SCEV* CommonExprs, Value *CommonBaseV, Instruction *IVIncInsertPt, const Loop *L, @@ -1497,7 +1497,7 @@ /// StrengthReduceStridedIVUsers - Strength reduce all of the users of a single /// stride of IV. All of the users may have different starting values, and this /// may not be the only stride. -void LoopStrengthReduce::StrengthReduceStridedIVUsers(const SCEVHandle &Stride, +void LoopStrengthReduce::StrengthReduceStridedIVUsers(const SCEV* const &Stride, IVUsersOfOneStride &Uses, Loop *L) { // If all the users are moved to another stride, then there is nothing to do. @@ -1520,7 +1520,7 @@ // move information from the Base field to the Imm field, until we eventually // have the full access expression to rewrite the use. std::vector UsersToProcess; - SCEVHandle CommonExprs = CollectIVUsers(Stride, Uses, L, AllUsesAreAddresses, + const SCEV* CommonExprs = CollectIVUsers(Stride, Uses, L, AllUsesAreAddresses, AllUsesAreOutsideLoop, UsersToProcess); @@ -1538,8 +1538,8 @@ // If all uses are addresses, consider sinking the immediate part of the // common expression back into uses if they can fit in the immediate fields. if (TLI && HaveCommonExprs && AllUsesAreAddresses) { - SCEVHandle NewCommon = CommonExprs; - SCEVHandle Imm = SE->getIntegerSCEV(0, ReplacedTy); + const SCEV* NewCommon = CommonExprs; + const SCEV* Imm = SE->getIntegerSCEV(0, ReplacedTy); MoveImmediateValues(TLI, Type::VoidTy, NewCommon, Imm, true, L, SE); if (!Imm->isZero()) { bool DoSink = true; @@ -1585,7 +1585,7 @@ Value *CommonBaseV = Constant::getNullValue(ReplacedTy); - SCEVHandle RewriteFactor = SE->getIntegerSCEV(0, ReplacedTy); + const SCEV* RewriteFactor = SE->getIntegerSCEV(0, ReplacedTy); IVExpr ReuseIV(SE->getIntegerSCEV(0, Type::Int32Ty), SE->getIntegerSCEV(0, Type::Int32Ty), 0); @@ -1625,7 +1625,7 @@ // strength-reduced forms. This outer loop handles all bases, the inner // loop handles all users of a particular base. while (!UsersToProcess.empty()) { - SCEVHandle Base = UsersToProcess.back().Base; + const SCEV* Base = UsersToProcess.back().Base; Instruction *Inst = UsersToProcess.back().Inst; // Emit the code for Base into the preheader. @@ -1679,7 +1679,7 @@ User.Inst->moveBefore(IVIncInsertPt); } - SCEVHandle RewriteExpr = SE->getUnknown(RewriteOp); + const SCEV* RewriteExpr = SE->getUnknown(RewriteOp); if (SE->getEffectiveSCEVType(RewriteOp->getType()) != SE->getEffectiveSCEVType(ReplacedTy)) { @@ -1711,7 +1711,7 @@ // The base has been used to initialize the PHI node but we don't want // it here. if (!ReuseIV.Base->isZero()) { - SCEVHandle typedBase = ReuseIV.Base; + const SCEV* typedBase = ReuseIV.Base; if (SE->getEffectiveSCEVType(RewriteExpr->getType()) != SE->getEffectiveSCEVType(ReuseIV.Base->getType())) { // It's possible the original IV is a larger type than the new IV, @@ -1776,10 +1776,10 @@ /// set the IV user and stride information and return true, otherwise return /// false. bool LoopStrengthReduce::FindIVUserForCond(ICmpInst *Cond, IVStrideUse *&CondUse, - const SCEVHandle *&CondStride) { + const SCEV* const * &CondStride) { for (unsigned Stride = 0, e = IU->StrideOrder.size(); Stride != e && !CondUse; ++Stride) { - std::map::iterator SI = + std::map::iterator SI = IU->IVUsesByStride.find(IU->StrideOrder[Stride]); assert(SI != IU->IVUsesByStride.end() && "Stride doesn't exist!"); @@ -1806,7 +1806,7 @@ const ScalarEvolution *SE; explicit StrideCompare(const ScalarEvolution *se) : SE(se) {} - bool operator()(const SCEVHandle &LHS, const SCEVHandle &RHS) { + bool operator()(const SCEV* const &LHS, const SCEV* const &RHS) { const SCEVConstant *LHSC = dyn_cast(LHS); const SCEVConstant *RHSC = dyn_cast(RHS); if (LHSC && RHSC) { @@ -1849,14 +1849,14 @@ /// if (v1 < 30) goto loop ICmpInst *LoopStrengthReduce::ChangeCompareStride(Loop *L, ICmpInst *Cond, IVStrideUse* &CondUse, - const SCEVHandle* &CondStride) { + const SCEV* const* &CondStride) { // If there's only one stride in the loop, there's nothing to do here. if (IU->StrideOrder.size() < 2) return Cond; // If there are other users of the condition's stride, don't bother // trying to change the condition because the stride will still // remain. - std::map::iterator I = + std::map::iterator I = IU->IVUsesByStride.find(*CondStride); if (I == IU->IVUsesByStride.end() || I->second->Users.size() != 1) @@ -1873,11 +1873,11 @@ const Type *NewCmpTy = NULL; unsigned TyBits = SE->getTypeSizeInBits(CmpTy); unsigned NewTyBits = 0; - SCEVHandle *NewStride = NULL; + const SCEV* *NewStride = NULL; Value *NewCmpLHS = NULL; Value *NewCmpRHS = NULL; int64_t Scale = 1; - SCEVHandle NewOffset = SE->getIntegerSCEV(0, CmpTy); + const SCEV* NewOffset = SE->getIntegerSCEV(0, CmpTy); if (ConstantInt *C = dyn_cast(Cond->getOperand(1))) { int64_t CmpVal = C->getValue().getSExtValue(); @@ -1889,7 +1889,7 @@ // Look for a suitable stride / iv as replacement. for (unsigned i = 0, e = IU->StrideOrder.size(); i != e; ++i) { - std::map::iterator SI = + std::map::iterator SI = IU->IVUsesByStride.find(IU->StrideOrder[i]); if (!isa(SI->first)) continue; @@ -1969,7 +1969,7 @@ bool AllUsesAreAddresses = true; bool AllUsesAreOutsideLoop = true; std::vector UsersToProcess; - SCEVHandle CommonExprs = CollectIVUsers(SI->first, *SI->second, L, + const SCEV* CommonExprs = CollectIVUsers(SI->first, *SI->second, L, AllUsesAreAddresses, AllUsesAreOutsideLoop, UsersToProcess); @@ -2104,13 +2104,13 @@ SelectInst *Sel = dyn_cast(Cond->getOperand(1)); if (!Sel || !Sel->hasOneUse()) return Cond; - SCEVHandle BackedgeTakenCount = SE->getBackedgeTakenCount(L); + const SCEV* BackedgeTakenCount = SE->getBackedgeTakenCount(L); if (isa(BackedgeTakenCount)) return Cond; - SCEVHandle One = SE->getIntegerSCEV(1, BackedgeTakenCount->getType()); + const SCEV* One = SE->getIntegerSCEV(1, BackedgeTakenCount->getType()); // Add one to the backedge-taken count to get the trip count. - SCEVHandle IterationCount = SE->getAddExpr(BackedgeTakenCount, One); + const SCEV* IterationCount = SE->getAddExpr(BackedgeTakenCount, One); // Check for a max calculation that matches the pattern. if (!isa(IterationCount) && !isa(IterationCount)) @@ -2123,13 +2123,13 @@ if (Max->getNumOperands() != 2) return Cond; - SCEVHandle MaxLHS = Max->getOperand(0); - SCEVHandle MaxRHS = Max->getOperand(1); + const SCEV* MaxLHS = Max->getOperand(0); + const SCEV* MaxRHS = Max->getOperand(1); if (!MaxLHS || MaxLHS != One) return Cond; // Check the relevant induction variable for conformance to // the pattern. - SCEVHandle IV = SE->getSCEV(Cond->getOperand(0)); + const SCEV* IV = SE->getSCEV(Cond->getOperand(0)); const SCEVAddRecExpr *AR = dyn_cast(IV); if (!AR || !AR->isAffine() || AR->getStart() != One || @@ -2175,13 +2175,13 @@ /// inside the loop then try to eliminate the cast opeation. void LoopStrengthReduce::OptimizeShadowIV(Loop *L) { - SCEVHandle BackedgeTakenCount = SE->getBackedgeTakenCount(L); + const SCEV* BackedgeTakenCount = SE->getBackedgeTakenCount(L); if (isa(BackedgeTakenCount)) return; for (unsigned Stride = 0, e = IU->StrideOrder.size(); Stride != e; ++Stride) { - std::map::iterator SI = + std::map::iterator SI = IU->IVUsesByStride.find(IU->StrideOrder[Stride]); assert(SI != IU->IVUsesByStride.end() && "Stride doesn't exist!"); if (!isa(SI->first)) @@ -2311,7 +2311,7 @@ // Search IVUsesByStride to find Cond's IVUse if there is one. IVStrideUse *CondUse = 0; - const SCEVHandle *CondStride = 0; + const SCEV* const *CondStride = 0; ICmpInst *Cond = cast(TermBr->getCondition()); if (!FindIVUserForCond(Cond, CondUse, CondStride)) return; // setcc doesn't use the IV. @@ -2341,7 +2341,7 @@ int64_t SInt = SC->getValue()->getSExtValue(); for (unsigned NewStride = 0, ee = IU->StrideOrder.size(); NewStride != ee; ++NewStride) { - std::map::iterator SI = + std::map::iterator SI = IU->IVUsesByStride.find(IU->StrideOrder[NewStride]); if (!isa(SI->first) || SI->first == *CondStride) continue; @@ -2355,7 +2355,7 @@ bool AllUsesAreAddresses = true; bool AllUsesAreOutsideLoop = true; std::vector UsersToProcess; - SCEVHandle CommonExprs = CollectIVUsers(SI->first, *SI->second, L, + const SCEV* CommonExprs = CollectIVUsers(SI->first, *SI->second, L, AllUsesAreAddresses, AllUsesAreOutsideLoop, UsersToProcess); @@ -2416,7 +2416,7 @@ void LoopStrengthReduce::OptimizeLoopCountIV(Loop *L) { // If the number of times the loop is executed isn't computable, give up. - SCEVHandle BackedgeTakenCount = SE->getBackedgeTakenCount(L); + const SCEV* BackedgeTakenCount = SE->getBackedgeTakenCount(L); if (isa(BackedgeTakenCount)) return; @@ -2445,9 +2445,9 @@ // Handle only tests for equality for the moment, and only stride 1. if (Cond->getPredicate() != CmpInst::ICMP_EQ) return; - SCEVHandle IV = SE->getSCEV(Cond->getOperand(0)); + const SCEV* IV = SE->getSCEV(Cond->getOperand(0)); const SCEVAddRecExpr *AR = dyn_cast(IV); - SCEVHandle One = SE->getIntegerSCEV(1, BackedgeTakenCount->getType()); + const SCEV* One = SE->getIntegerSCEV(1, BackedgeTakenCount->getType()); if (!AR || !AR->isAffine() || AR->getStepRecurrence(*SE) != One) return; // If the RHS of the comparison is defined inside the loop, the rewrite @@ -2563,7 +2563,7 @@ // strides deterministic - not dependent on map order. for (unsigned Stride = 0, e = IU->StrideOrder.size(); Stride != e; ++Stride) { - std::map::iterator SI = + std::map::iterator SI = IU->IVUsesByStride.find(IU->StrideOrder[Stride]); assert(SI != IU->IVUsesByStride.end() && "Stride doesn't exist!"); // FIXME: Generalize to non-affine IV's. From bob.wilson at apple.com Mon Jun 22 16:50:41 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 22 Jun 2009 14:50:41 -0700 Subject: [llvm-commits] [llvm] r73887 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp In-Reply-To: References: <200906221729.n5MHTYc0025261@zion.cs.uiuc.edu> Message-ID: <2279D270-7B9F-49AA-BC96-77E52F5EF4E7@apple.com> On Jun 22, 2009, at 2:39 PM, Anton Korobeynikov wrote: > Hi, Bob > >> Fix llvm-gcc build for armv6t2 and later architectures. The >> hasV6T2Ops >> predicate does not check if Thumb mode is enabled, and when in ARM >> mode >> there are still some checks for constant-pool use that need to run. > What's the reason for this? > > 1. movt is available both in thumb and arm modes, there is no need to > check for thumb here. > 2. ARM's compiler writing guide explicitly suggests not using constant > pool and materialize constants using pair of movw / movt. Yes, I wondered about that, too. It surprised me that a constant pool entry would be needed in ARM mode, but not in Thumb mode. I'm in the middle of merging some changes and discovered that the llvm-gcc build failed compiling libgcc for ARM v7. (The error message was "cannot select -1023" or something like that.) I had not seen this before so I replaced this check with the corresponding code that I had been using before. It is definitely something that should be investigated. Feel free to take a look; otherwise, I'll check it out later. --Bob From resistor at mac.com Mon Jun 22 16:57:23 2009 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Jun 2009 21:57:23 -0000 Subject: [llvm-commits] [llvm] r73907 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h include/llvm/Analysis/ScalarEvolutionExpressions.h lib/Analysis/ScalarEvolution.cpp Message-ID: <200906222157.n5MLvOdB002557@zion.cs.uiuc.edu> Author: resistor Date: Mon Jun 22 16:57:23 2009 New Revision: 73907 URL: http://llvm.org/viewvc/llvm-project?rev=73907&view=rev Log: Remove the parent pointer from SCEV, since it did not end up being needed. Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=73907&r1=73906&r2=73907&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Mon Jun 22 16:57:23 2009 @@ -50,15 +50,13 @@ class SCEV { const unsigned SCEVType; // The SCEV baseclass this node corresponds to - const ScalarEvolution* parent; - SCEV(const SCEV &); // DO NOT IMPLEMENT void operator=(const SCEV &); // DO NOT IMPLEMENT protected: virtual ~SCEV(); public: - explicit SCEV(unsigned SCEVTy, const ScalarEvolution* p) : - SCEVType(SCEVTy), parent(p) {} + explicit SCEV(unsigned SCEVTy) : + SCEVType(SCEVTy) {} unsigned getSCEVType() const { return SCEVType; } @@ -126,8 +124,7 @@ /// None of the standard SCEV operations are valid on this class, it is just a /// marker. struct SCEVCouldNotCompute : public SCEV { - SCEVCouldNotCompute(const ScalarEvolution* p); - ~SCEVCouldNotCompute(); + SCEVCouldNotCompute(); // None of these methods are valid for this object. virtual bool isLoopInvariant(const Loop *L) const; Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h?rev=73907&r1=73906&r2=73907&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h Mon Jun 22 16:57:23 2009 @@ -36,8 +36,8 @@ friend class ScalarEvolution; ConstantInt *V; - explicit SCEVConstant(ConstantInt *v, const ScalarEvolution* p) : - SCEV(scConstant, p), V(v) {} + explicit SCEVConstant(ConstantInt *v) : + SCEV(scConstant), V(v) {} public: ConstantInt *getValue() const { return V; } @@ -78,9 +78,7 @@ const SCEV* Op; const Type *Ty; - SCEVCastExpr(unsigned SCEVTy, const SCEV* op, const Type *ty, - const ScalarEvolution* p); - virtual ~SCEVCastExpr(); + SCEVCastExpr(unsigned SCEVTy, const SCEV* op, const Type *ty); public: const SCEV* getOperand() const { return Op; } @@ -112,8 +110,7 @@ class SCEVTruncateExpr : public SCEVCastExpr { friend class ScalarEvolution; - SCEVTruncateExpr(const SCEV* op, const Type *ty, - const ScalarEvolution* p); + SCEVTruncateExpr(const SCEV* op, const Type *ty); public: const SCEV* replaceSymbolicValuesWithConcrete(const SCEV* Sym, @@ -141,8 +138,7 @@ class SCEVZeroExtendExpr : public SCEVCastExpr { friend class ScalarEvolution; - SCEVZeroExtendExpr(const SCEV* op, const Type *ty, - const ScalarEvolution* p); + SCEVZeroExtendExpr(const SCEV* op, const Type *ty); public: const SCEV* replaceSymbolicValuesWithConcrete(const SCEV* Sym, @@ -170,8 +166,7 @@ class SCEVSignExtendExpr : public SCEVCastExpr { friend class ScalarEvolution; - SCEVSignExtendExpr(const SCEV* op, const Type *ty, - const ScalarEvolution* p); + SCEVSignExtendExpr(const SCEV* op, const Type *ty); public: const SCEV* replaceSymbolicValuesWithConcrete(const SCEV* Sym, @@ -201,10 +196,8 @@ protected: SmallVector Operands; - SCEVNAryExpr(enum SCEVTypes T, const SmallVectorImpl &ops, - const ScalarEvolution* p) - : SCEV(T, p), Operands(ops.begin(), ops.end()) {} - virtual ~SCEVNAryExpr() {} + SCEVNAryExpr(enum SCEVTypes T, const SmallVectorImpl &ops) + : SCEV(T), Operands(ops.begin(), ops.end()) {} public: unsigned getNumOperands() const { return (unsigned)Operands.size(); } @@ -261,9 +254,8 @@ class SCEVCommutativeExpr : public SCEVNAryExpr { protected: SCEVCommutativeExpr(enum SCEVTypes T, - const SmallVectorImpl &ops, - const ScalarEvolution* p) - : SCEVNAryExpr(T, ops, p) {} + const SmallVectorImpl &ops) + : SCEVNAryExpr(T, ops) {} public: const SCEV* replaceSymbolicValuesWithConcrete(const SCEV* Sym, @@ -291,9 +283,8 @@ class SCEVAddExpr : public SCEVCommutativeExpr { friend class ScalarEvolution; - explicit SCEVAddExpr(const SmallVectorImpl &ops, - const ScalarEvolution* p) - : SCEVCommutativeExpr(scAddExpr, ops, p) { + explicit SCEVAddExpr(const SmallVectorImpl &ops) + : SCEVCommutativeExpr(scAddExpr, ops) { } public: @@ -312,9 +303,8 @@ class SCEVMulExpr : public SCEVCommutativeExpr { friend class ScalarEvolution; - explicit SCEVMulExpr(const SmallVectorImpl &ops, - const ScalarEvolution* p) - : SCEVCommutativeExpr(scMulExpr, ops, p) { + explicit SCEVMulExpr(const SmallVectorImpl &ops) + : SCEVCommutativeExpr(scMulExpr, ops) { } public: @@ -336,9 +326,8 @@ const SCEV* LHS; const SCEV* RHS; - SCEVUDivExpr(const SCEV* lhs, const SCEV* rhs, - const ScalarEvolution* p) - : SCEV(scUDivExpr, p), LHS(lhs), RHS(rhs) {} + SCEVUDivExpr(const SCEV* lhs, const SCEV* rhs) + : SCEV(scUDivExpr), LHS(lhs), RHS(rhs) {} public: const SCEV* getLHS() const { return LHS; } @@ -392,9 +381,8 @@ const Loop *L; - SCEVAddRecExpr(const SmallVectorImpl &ops, const Loop *l, - const ScalarEvolution* p) - : SCEVNAryExpr(scAddRecExpr, ops, p), L(l) { + SCEVAddRecExpr(const SmallVectorImpl &ops, const Loop *l) + : SCEVNAryExpr(scAddRecExpr, ops), L(l) { for (size_t i = 0, e = Operands.size(); i != e; ++i) assert(Operands[i]->isLoopInvariant(l) && "Operands of AddRec must be loop-invariant!"); @@ -468,9 +456,8 @@ class SCEVSMaxExpr : public SCEVCommutativeExpr { friend class ScalarEvolution; - explicit SCEVSMaxExpr(const SmallVectorImpl &ops, - const ScalarEvolution* p) - : SCEVCommutativeExpr(scSMaxExpr, ops, p) { + explicit SCEVSMaxExpr(const SmallVectorImpl &ops) + : SCEVCommutativeExpr(scSMaxExpr, ops) { } public: @@ -490,9 +477,8 @@ class SCEVUMaxExpr : public SCEVCommutativeExpr { friend class ScalarEvolution; - explicit SCEVUMaxExpr(const SmallVectorImpl &ops, - const ScalarEvolution* p) - : SCEVCommutativeExpr(scUMaxExpr, ops, p) { + explicit SCEVUMaxExpr(const SmallVectorImpl &ops) + : SCEVCommutativeExpr(scUMaxExpr, ops) { } public: @@ -515,8 +501,8 @@ friend class ScalarEvolution; Value *V; - explicit SCEVUnknown(Value *v, const ScalarEvolution* p) : - SCEV(scUnknown, p), V(v) {} + explicit SCEVUnknown(Value *v) : + SCEV(scUnknown), V(v) {} public: Value *getValue() const { return V; } Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=73907&r1=73906&r2=73907&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Jun 22 16:57:23 2009 @@ -76,7 +76,6 @@ #include "llvm/Support/ConstantRange.h" #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/InstIterator.h" -#include "llvm/Support/ManagedStatic.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/Statistic.h" @@ -133,9 +132,8 @@ return false; } -SCEVCouldNotCompute::SCEVCouldNotCompute(const ScalarEvolution* p) : - SCEV(scCouldNotCompute, p) {} -SCEVCouldNotCompute::~SCEVCouldNotCompute() {} +SCEVCouldNotCompute::SCEVCouldNotCompute() : + SCEV(scCouldNotCompute) {} bool SCEVCouldNotCompute::isLoopInvariant(const Loop *L) const { assert(0 && "Attempt to use a SCEVCouldNotCompute object!"); @@ -174,7 +172,7 @@ const SCEV* ScalarEvolution::getConstant(ConstantInt *V) { SCEVConstant *&R = SCEVConstants[V]; - if (R == 0) R = new SCEVConstant(V, this); + if (R == 0) R = new SCEVConstant(V); return R; } @@ -194,11 +192,8 @@ } SCEVCastExpr::SCEVCastExpr(unsigned SCEVTy, - const SCEV* op, const Type *ty, - const ScalarEvolution* p) - : SCEV(SCEVTy, p), Op(op), Ty(ty) {} - -SCEVCastExpr::~SCEVCastExpr() {} + const SCEV* op, const Type *ty) + : SCEV(SCEVTy), Op(op), Ty(ty) {} bool SCEVCastExpr::dominates(BasicBlock *BB, DominatorTree *DT) const { return Op->dominates(BB, DT); @@ -208,9 +203,8 @@ // particular input. Don't use a const SCEV* here, or else the object will // never be deleted! -SCEVTruncateExpr::SCEVTruncateExpr(const SCEV* op, const Type *ty, - const ScalarEvolution* p) - : SCEVCastExpr(scTruncate, op, ty, p) { +SCEVTruncateExpr::SCEVTruncateExpr(const SCEV* op, const Type *ty) + : SCEVCastExpr(scTruncate, op, ty) { assert((Op->getType()->isInteger() || isa(Op->getType())) && (Ty->isInteger() || isa(Ty)) && "Cannot truncate non-integer value!"); @@ -225,9 +219,8 @@ // particular input. Don't use a const SCEV* here, or else the object will never // be deleted! -SCEVZeroExtendExpr::SCEVZeroExtendExpr(const SCEV* op, const Type *ty, - const ScalarEvolution* p) - : SCEVCastExpr(scZeroExtend, op, ty, p) { +SCEVZeroExtendExpr::SCEVZeroExtendExpr(const SCEV* op, const Type *ty) + : SCEVCastExpr(scZeroExtend, op, ty) { assert((Op->getType()->isInteger() || isa(Op->getType())) && (Ty->isInteger() || isa(Ty)) && "Cannot zero extend non-integer value!"); @@ -241,9 +234,8 @@ // particular input. Don't use a const SCEV* here, or else the object will never // be deleted! -SCEVSignExtendExpr::SCEVSignExtendExpr(const SCEV* op, const Type *ty, - const ScalarEvolution* p) - : SCEVCastExpr(scSignExtend, op, ty, p) { +SCEVSignExtendExpr::SCEVSignExtendExpr(const SCEV* op, const Type *ty) + : SCEVCastExpr(scSignExtend, op, ty) { assert((Op->getType()->isInteger() || isa(Op->getType())) && (Ty->isInteger() || isa(Ty)) && "Cannot sign extend non-integer value!"); @@ -745,7 +737,7 @@ } SCEVTruncateExpr *&Result = SCEVTruncates[std::make_pair(Op, Ty)]; - if (Result == 0) Result = new SCEVTruncateExpr(Op, Ty, this); + if (Result == 0) Result = new SCEVTruncateExpr(Op, Ty); return Result; } @@ -833,7 +825,7 @@ } SCEVZeroExtendExpr *&Result = SCEVZeroExtends[std::make_pair(Op, Ty)]; - if (Result == 0) Result = new SCEVZeroExtendExpr(Op, Ty, this); + if (Result == 0) Result = new SCEVZeroExtendExpr(Op, Ty); return Result; } @@ -905,7 +897,7 @@ } SCEVSignExtendExpr *&Result = SCEVSignExtends[std::make_pair(Op, Ty)]; - if (Result == 0) Result = new SCEVSignExtendExpr(Op, Ty, this); + if (Result == 0) Result = new SCEVSignExtendExpr(Op, Ty); return Result; } @@ -1367,7 +1359,7 @@ std::vector SCEVOps(Ops.begin(), Ops.end()); SCEVCommutativeExpr *&Result = SCEVCommExprs[std::make_pair(scAddExpr, SCEVOps)]; - if (Result == 0) Result = new SCEVAddExpr(Ops, this); + if (Result == 0) Result = new SCEVAddExpr(Ops); return Result; } @@ -1533,7 +1525,7 @@ SCEVCommutativeExpr *&Result = SCEVCommExprs[std::make_pair(scMulExpr, SCEVOps)]; if (Result == 0) - Result = new SCEVMulExpr(Ops, this); + Result = new SCEVMulExpr(Ops); return Result; } @@ -1624,7 +1616,7 @@ } SCEVUDivExpr *&Result = SCEVUDivs[std::make_pair(LHS, RHS)]; - if (Result == 0) Result = new SCEVUDivExpr(LHS, RHS, this); + if (Result == 0) Result = new SCEVUDivExpr(LHS, RHS); return Result; } @@ -1677,7 +1669,7 @@ std::vector SCEVOps(Operands.begin(), Operands.end()); SCEVAddRecExpr *&Result = SCEVAddRecExprs[std::make_pair(L, SCEVOps)]; - if (Result == 0) Result = new SCEVAddRecExpr(Operands, L, this); + if (Result == 0) Result = new SCEVAddRecExpr(Operands, L); return Result; } @@ -1764,7 +1756,7 @@ std::vector SCEVOps(Ops.begin(), Ops.end()); SCEVCommutativeExpr *&Result = SCEVCommExprs[std::make_pair(scSMaxExpr, SCEVOps)]; - if (Result == 0) Result = new SCEVSMaxExpr(Ops, this); + if (Result == 0) Result = new SCEVSMaxExpr(Ops); return Result; } @@ -1851,7 +1843,7 @@ std::vector SCEVOps(Ops.begin(), Ops.end()); SCEVCommutativeExpr *&Result = SCEVCommExprs[std::make_pair(scUMaxExpr, SCEVOps)]; - if (Result == 0) Result = new SCEVUMaxExpr(Ops, this); + if (Result == 0) Result = new SCEVUMaxExpr(Ops); return Result; } @@ -1873,7 +1865,7 @@ if (isa(V)) return getIntegerSCEV(0, V->getType()); SCEVUnknown *&Result = SCEVUnknowns[V]; - if (Result == 0) Result = new SCEVUnknown(V, this); + if (Result == 0) Result = new SCEVUnknown(V); return Result; } @@ -4261,7 +4253,7 @@ //===----------------------------------------------------------------------===// ScalarEvolution::ScalarEvolution() - : FunctionPass(&ID), CouldNotCompute(new SCEVCouldNotCompute(0)) { + : FunctionPass(&ID), CouldNotCompute(new SCEVCouldNotCompute()) { } bool ScalarEvolution::runOnFunction(Function &F) { From gohman at apple.com Mon Jun 22 17:02:32 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 22 Jun 2009 22:02:32 -0000 Subject: [llvm-commits] [llvm] r73908 - in /llvm/trunk: lib/Analysis/ValueTracking.cpp test/Analysis/ScalarEvolution/pointer-sign-bits.ll Message-ID: <200906222202.n5MM2WTK002788@zion.cs.uiuc.edu> Author: djg Date: Mon Jun 22 17:02:32 2009 New Revision: 73908 URL: http://llvm.org/viewvc/llvm-project?rev=73908&view=rev Log: Fix llvm::ComputeNumSignBits to handle pointer types conservatively correctly, instead of aborting. Added: llvm/trunk/test/Analysis/ScalarEvolution/pointer-sign-bits.ll Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=73908&r1=73907&r2=73908&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Mon Jun 22 17:02:32 2009 @@ -624,8 +624,12 @@ /// 'Op' must have a scalar integer type. /// unsigned llvm::ComputeNumSignBits(Value *V, TargetData *TD, unsigned Depth) { + assert((TD || V->getType()->isIntOrIntVector()) && + "ComputeNumSignBits requires a TargetData object to operate " + "on non-integer values!"); const Type *Ty = V->getType(); - unsigned TyBits = Ty->getScalarSizeInBits(); + unsigned TyBits = TD ? TD->getTypeSizeInBits(V->getType()->getScalarType()) : + Ty->getScalarSizeInBits(); unsigned Tmp, Tmp2; unsigned FirstAnswer = 1; Added: llvm/trunk/test/Analysis/ScalarEvolution/pointer-sign-bits.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/pointer-sign-bits.ll?rev=73908&view=auto ============================================================================== --- llvm/trunk/test/Analysis/ScalarEvolution/pointer-sign-bits.ll (added) +++ llvm/trunk/test/Analysis/ScalarEvolution/pointer-sign-bits.ll Mon Jun 22 17:02:32 2009 @@ -0,0 +1,220 @@ +; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" + %JavaObject = type { [0 x i32 (...)*]*, i8* } + +define void @JnJVM_antlr_CSharpCodeGenerator_genBitSet__Lantlr_collections_impl_BitSet_2I(%JavaObject*, %JavaObject*, i32) { +start: + br i1 undef, label %"stack overflow", label %"no stack overflow" + +"GOTO or IF*2": ; preds = %"true verifyAndComputePtr89", %verifyNullCont84 + unreachable + +"GOTO or IF*5": ; preds = %"true verifyAndComputePtr127", %"GOTO or IF*6" + unreachable + +"GOTO or IF*6": ; preds = %"true verifyAndComputePtr131.GOTO or IF*6_crit_edge", %"true verifyAndComputePtr89" + %indvar = phi i32 [ %indvar.next, %"true verifyAndComputePtr131.GOTO or IF*6_crit_edge" ], [ 0, %"true verifyAndComputePtr89" ] ; [#uses=2] + %.0.in = add i32 %indvar, 0 ; [#uses=1] + %.0 = add i32 %.0.in, 1 ; [#uses=1] + %3 = icmp slt i32 %.0, %4 ; [#uses=1] + br i1 %3, label %verifyNullCont126, label %"GOTO or IF*5" + +end: ; preds = %"no exception block35" + ret void + +"stack overflow": ; preds = %start + ret void + +"no stack overflow": ; preds = %start + br i1 undef, label %verifyNullCont, label %"no stack overflow.end_crit_edge" + +"no stack overflow.end_crit_edge": ; preds = %"no stack overflow" + ret void + +verifyNullCont: ; preds = %"no stack overflow" + br i1 undef, label %verifyNullCont9, label %verifyNullCont.end_crit_edge + +verifyNullCont.end_crit_edge: ; preds = %verifyNullCont + ret void + +verifyNullCont9: ; preds = %verifyNullCont + br i1 undef, label %verifyNullCont12, label %verifyNullCont9.end_crit_edge + +verifyNullCont9.end_crit_edge: ; preds = %verifyNullCont9 + ret void + +verifyNullCont12: ; preds = %verifyNullCont9 + br i1 undef, label %"no exception block13", label %verifyNullCont12.end_crit_edge + +verifyNullCont12.end_crit_edge: ; preds = %verifyNullCont12 + ret void + +"no exception block13": ; preds = %verifyNullCont12 + br i1 undef, label %verifyNullExit14, label %verifyNullCont15 + +verifyNullExit14: ; preds = %"no exception block13" + ret void + +verifyNullCont15: ; preds = %"no exception block13" + br i1 undef, label %"no exception block16", label %verifyNullCont15.end_crit_edge + +verifyNullCont15.end_crit_edge: ; preds = %verifyNullCont15 + ret void + +"no exception block16": ; preds = %verifyNullCont15 + br i1 undef, label %verifyNullExit17, label %verifyNullCont18 + +verifyNullExit17: ; preds = %"no exception block16" + ret void + +verifyNullCont18: ; preds = %"no exception block16" + br i1 undef, label %"no exception block19", label %verifyNullCont18.end_crit_edge + +verifyNullCont18.end_crit_edge: ; preds = %verifyNullCont18 + ret void + +"no exception block19": ; preds = %verifyNullCont18 + br i1 undef, label %verifyNullExit20, label %verifyNullCont21 + +verifyNullExit20: ; preds = %"no exception block19" + ret void + +verifyNullCont21: ; preds = %"no exception block19" + br i1 undef, label %verifyNullCont24, label %verifyNullCont21.end_crit_edge + +verifyNullCont21.end_crit_edge: ; preds = %verifyNullCont21 + ret void + +verifyNullCont24: ; preds = %verifyNullCont21 + br i1 undef, label %verifyNullCont27, label %verifyNullCont24.end_crit_edge + +verifyNullCont24.end_crit_edge: ; preds = %verifyNullCont24 + ret void + +verifyNullCont27: ; preds = %verifyNullCont24 + br i1 undef, label %verifyNullCont32, label %verifyNullCont27.end_crit_edge + +verifyNullCont27.end_crit_edge: ; preds = %verifyNullCont27 + ret void + +verifyNullCont32: ; preds = %verifyNullCont27 + br i1 undef, label %verifyNullExit33, label %verifyNullCont34 + +verifyNullExit33: ; preds = %verifyNullCont32 + ret void + +verifyNullCont34: ; preds = %verifyNullCont32 + br i1 undef, label %"no exception block35", label %verifyNullCont34.end_crit_edge + +verifyNullCont34.end_crit_edge: ; preds = %verifyNullCont34 + ret void + +"no exception block35": ; preds = %verifyNullCont34 + br i1 undef, label %end, label %verifyNullCont60 + +verifyNullCont60: ; preds = %"no exception block35" + br i1 undef, label %verifyNullCont63, label %verifyNullCont60.end_crit_edge + +verifyNullCont60.end_crit_edge: ; preds = %verifyNullCont60 + ret void + +verifyNullCont63: ; preds = %verifyNullCont60 + br i1 undef, label %"no exception block64", label %verifyNullCont63.end_crit_edge + +verifyNullCont63.end_crit_edge: ; preds = %verifyNullCont63 + ret void + +"no exception block64": ; preds = %verifyNullCont63 + br i1 undef, label %verifyNullExit65, label %verifyNullCont66 + +verifyNullExit65: ; preds = %"no exception block64" + ret void + +verifyNullCont66: ; preds = %"no exception block64" + br i1 undef, label %"no exception block67", label %verifyNullCont66.end_crit_edge + +verifyNullCont66.end_crit_edge: ; preds = %verifyNullCont66 + ret void + +"no exception block67": ; preds = %verifyNullCont66 + br i1 undef, label %verifyNullExit68, label %verifyNullCont69 + +verifyNullExit68: ; preds = %"no exception block67" + ret void + +verifyNullCont69: ; preds = %"no exception block67" + br i1 undef, label %"no exception block70", label %verifyNullCont69.end_crit_edge + +verifyNullCont69.end_crit_edge: ; preds = %verifyNullCont69 + ret void + +"no exception block70": ; preds = %verifyNullCont69 + br i1 undef, label %verifyNullExit71, label %verifyNullCont72 + +verifyNullExit71: ; preds = %"no exception block70" + ret void + +verifyNullCont72: ; preds = %"no exception block70" + br i1 undef, label %verifyNullCont75, label %verifyNullCont72.end_crit_edge + +verifyNullCont72.end_crit_edge: ; preds = %verifyNullCont72 + ret void + +verifyNullCont75: ; preds = %verifyNullCont72 + br i1 undef, label %verifyNullCont78, label %verifyNullCont75.end_crit_edge + +verifyNullCont75.end_crit_edge: ; preds = %verifyNullCont75 + ret void + +verifyNullCont78: ; preds = %verifyNullCont75 + br i1 undef, label %"verifyNullCont78.GOTO or IF*4_crit_edge", label %verifyNullCont78.end_crit_edge + +"verifyNullCont78.GOTO or IF*4_crit_edge": ; preds = %verifyNullCont78 + br i1 undef, label %verifyNullExit80, label %verifyNullCont81 + +verifyNullCont78.end_crit_edge: ; preds = %verifyNullCont78 + ret void + +verifyNullExit80: ; preds = %"verifyNullCont78.GOTO or IF*4_crit_edge" + ret void + +verifyNullCont81: ; preds = %"verifyNullCont78.GOTO or IF*4_crit_edge" + %4 = ptrtoint i8* undef to i32 ; [#uses=2] + %5 = icmp slt i32 0, %4 ; [#uses=1] + br i1 %5, label %verifyNullCont84, label %verifyNullCont172 + +verifyNullCont84: ; preds = %verifyNullCont81 + br i1 undef, label %"GOTO or IF*2", label %verifyNullCont86 + +verifyNullCont86: ; preds = %verifyNullCont84 + br i1 undef, label %"true verifyAndComputePtr", label %"false verifyAndComputePtr" + +"true verifyAndComputePtr": ; preds = %verifyNullCont86 + br i1 undef, label %"true verifyAndComputePtr89", label %"false verifyAndComputePtr90" + +"false verifyAndComputePtr": ; preds = %verifyNullCont86 + ret void + +"true verifyAndComputePtr89": ; preds = %"true verifyAndComputePtr" + br i1 undef, label %"GOTO or IF*6", label %"GOTO or IF*2" + +"false verifyAndComputePtr90": ; preds = %"true verifyAndComputePtr" + ret void + +verifyNullCont126: ; preds = %"GOTO or IF*6" + br i1 undef, label %"true verifyAndComputePtr127", label %"false verifyAndComputePtr128" + +"true verifyAndComputePtr127": ; preds = %verifyNullCont126 + br i1 undef, label %"true verifyAndComputePtr131.GOTO or IF*6_crit_edge", label %"GOTO or IF*5" + +"false verifyAndComputePtr128": ; preds = %verifyNullCont126 + ret void + +"true verifyAndComputePtr131.GOTO or IF*6_crit_edge": ; preds = %"true verifyAndComputePtr127" + %indvar.next = add i32 %indvar, 1 ; [#uses=1] + br label %"GOTO or IF*6" + +verifyNullCont172: ; preds = %verifyNullCont81 + unreachable +} From anton at korobeynikov.info Mon Jun 22 17:03:32 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 23 Jun 2009 02:03:32 +0400 Subject: [llvm-commits] [llvm] r73887 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp In-Reply-To: <2279D270-7B9F-49AA-BC96-77E52F5EF4E7@apple.com> References: <200906221729.n5MHTYc0025261@zion.cs.uiuc.edu> <2279D270-7B9F-49AA-BC96-77E52F5EF4E7@apple.com> Message-ID: Hello, Bob > Yes, I wondered about that, too. ?It surprised me that a constant pool > entry would be needed in ARM mode, but not in Thumb mode. ?I'm in the > middle of merging some changes and discovered that the llvm-gcc build > failed compiling libgcc for ARM v7. ?(The error message was "cannot > select -1023" or something like that.) I had not seen this before so I > replaced this check with the corresponding code that I had been using > before. ?It is definitely something that should be investigated. ?Feel > free to take a look; otherwise, I'll check it out later. Ah, right. Currently movt is provided only for Thumb2 targets. We need to add this entry to ARM side too. If seems we cannot "merge" these two definitions: different encodings, in ARM mode movt can be predicated. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From gohman at apple.com Mon Jun 22 17:03:27 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 22 Jun 2009 15:03:27 -0700 Subject: [llvm-commits] [llvm] r73884 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp In-Reply-To: <4A3FF9C9.4050308@lip6.fr> References: <200906221509.n5MF9TjU008035@zion.cs.uiuc.edu> <4A3FF9C9.4050308@lip6.fr> Message-ID: <4C2B85B9-3509-478D-B758-D479B949E079@apple.com> Hi Nicholas, Thanks for the report. I submitted a fix in r73908. Dan On Jun 22, 2009, at 2:38 PM, Nicolas Geoffray wrote: > Hi Dan, > > I believe this patch is responsible for the bug highlighted by the > attached (bugpoint reduced) test-case. Older revisions compile the > test case correclty. > > FYI, here's what I get when llc'ing the file (arch=x86 OS=linux): > > > llc: /home/ngeoffray/project/llvm-svn/llvm/include/llvm/ADT/APInt.h: > 216: llvm::APInt::APInt(unsigned int, uint64_t, bool): Assertion > `BitWidth && "bitwidth too small"' failed. > 0 llc 0x08beb5c8 > Stack dump: > 0. Program arguments: ../llvm/Release/bin/llc -march=x86 bugpoint- > reduced-simplified.bc > 1. Running pass 'Loop Pass Manager' on function > '@JnJVM_antlr_CSharpCodeGenerator_genBitSet__Lantlr_collections_impl_BitSet_2I > ' > 2. Running pass 'Loop Strength Reduction' on basic block '%"GOTO > or IF*6"' > > Would you like me to open a PR? > > Nicolas > From bob.wilson at apple.com Mon Jun 22 17:08:30 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 22 Jun 2009 22:08:30 -0000 Subject: [llvm-commits] [llvm] r73909 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrThumb.td Message-ID: <200906222208.n5MM8U7o003088@zion.cs.uiuc.edu> Author: bwilson Date: Mon Jun 22 17:08:29 2009 New Revision: 73909 URL: http://llvm.org/viewvc/llvm-project?rev=73909&view=rev Log: Add explicit types for shift count constants. This is in preparation for another change that makes the types ambiguous (at least as far as tablegen is concerned). Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=73909&r1=73908&r2=73909&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jun 22 17:08:29 2009 @@ -855,9 +855,9 @@ defm UXTB16 : AI_unary_rrot<0b01101100, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; -def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF), +def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), (UXTB16r_rot GPR:$Src, 24)>; -def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF), +def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), (UXTB16r_rot GPR:$Src, 8)>; defm UXTAB : AI_bin_rrot<0b01101110, "uxtab", @@ -1038,7 +1038,7 @@ def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), !strconcat(opc, "bt"), " $dst, $a, $b", [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), - (sra GPR:$b, 16)))]>, + (sra GPR:$b, (i32 16))))]>, Requires<[IsARM, HasV5TE]> { let Inst{5} = 0; let Inst{6} = 1; @@ -1046,7 +1046,7 @@ def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), !strconcat(opc, "tb"), " $dst, $a, $b", - [(set GPR:$dst, (opnode (sra GPR:$a, 16), + [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), (sext_inreg GPR:$b, i16)))]>, Requires<[IsARM, HasV5TE]> { let Inst{5} = 1; @@ -1055,8 +1055,8 @@ def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), !strconcat(opc, "tt"), " $dst, $a, $b", - [(set GPR:$dst, (opnode (sra GPR:$a, 16), - (sra GPR:$b, 16)))]>, + [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), + (sra GPR:$b, (i32 16))))]>, Requires<[IsARM, HasV5TE]> { let Inst{5} = 1; let Inst{6} = 1; @@ -1065,7 +1065,7 @@ def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), !strconcat(opc, "wb"), " $dst, $a, $b", [(set GPR:$dst, (sra (opnode GPR:$a, - (sext_inreg GPR:$b, i16)), 16))]>, + (sext_inreg GPR:$b, i16)), (i32 16)))]>, Requires<[IsARM, HasV5TE]> { let Inst{5} = 1; let Inst{6} = 0; @@ -1074,7 +1074,7 @@ def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), !strconcat(opc, "wt"), " $dst, $a, $b", [(set GPR:$dst, (sra (opnode GPR:$a, - (sra GPR:$b, 16)), 16))]>, + (sra GPR:$b, (i32 16))), (i32 16)))]>, Requires<[IsARM, HasV5TE]> { let Inst{5} = 1; let Inst{6} = 1; @@ -1096,7 +1096,7 @@ def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), !strconcat(opc, "bt"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), - (sra GPR:$b, 16))))]>, + (sra GPR:$b, (i32 16)))))]>, Requires<[IsARM, HasV5TE]> { let Inst{5} = 0; let Inst{6} = 1; @@ -1104,7 +1104,7 @@ def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), !strconcat(opc, "tb"), " $dst, $a, $b, $acc", - [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), + [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), (sext_inreg GPR:$b, i16))))]>, Requires<[IsARM, HasV5TE]> { let Inst{5} = 1; @@ -1113,8 +1113,8 @@ def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), !strconcat(opc, "tt"), " $dst, $a, $b, $acc", - [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), - (sra GPR:$b, 16))))]>, + [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), + (sra GPR:$b, (i32 16)))))]>, Requires<[IsARM, HasV5TE]> { let Inst{5} = 1; let Inst{6} = 1; @@ -1123,7 +1123,7 @@ def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), !strconcat(opc, "wb"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, - (sext_inreg GPR:$b, i16)), 16)))]>, + (sext_inreg GPR:$b, i16)), (i32 16))))]>, Requires<[IsARM, HasV5TE]> { let Inst{5} = 0; let Inst{6} = 0; @@ -1132,7 +1132,7 @@ def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), !strconcat(opc, "wt"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, - (sra GPR:$b, 16)), 16)))]>, + (sra GPR:$b, (i32 16))), (i32 16))))]>, Requires<[IsARM, HasV5TE]> { let Inst{5} = 0; let Inst{6} = 1; @@ -1168,10 +1168,10 @@ def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), "rev16", " $dst, $src", [(set GPR:$dst, - (or (and (srl GPR:$src, 8), 0xFF), - (or (and (shl GPR:$src, 8), 0xFF00), - (or (and (srl GPR:$src, 8), 0xFF0000), - (and (shl GPR:$src, 8), 0xFF000000)))))]>, + (or (and (srl GPR:$src, (i32 8)), 0xFF), + (or (and (shl GPR:$src, (i32 8)), 0xFF00), + (or (and (srl GPR:$src, (i32 8)), 0xFF0000), + (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>, Requires<[IsARM, HasV6]> { let Inst{7-4} = 0b1011; let Inst{11-8} = 0b1111; @@ -1182,8 +1182,8 @@ "revsh", " $dst, $src", [(set GPR:$dst, (sext_inreg - (or (srl (and GPR:$src, 0xFF00), 8), - (shl GPR:$src, 8)), i16))]>, + (or (srl (and GPR:$src, 0xFF00), (i32 8)), + (shl GPR:$src, (i32 8))), i16))]>, Requires<[IsARM, HasV6]> { let Inst{7-4} = 0b1011; let Inst{11-8} = 0b1111; @@ -1218,7 +1218,7 @@ // Alternate cases for PKHTB where identities eliminate some nodes. Note that // a shift amount of 0 is *not legal* here, it is PKHBT instead. -def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)), +def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))), (PKHTB GPR:$src1, GPR:$src2, 16)>; def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), @@ -1370,47 +1370,54 @@ def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; // smul* and smla* -def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)), +def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), + (sra (shl GPR:$b, (i32 16)), (i32 16))), (SMULBB GPR:$a, GPR:$b)>; def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), (SMULBB GPR:$a, GPR:$b)>; -def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)), +def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), + (sra GPR:$b, (i32 16))), (SMULBT GPR:$a, GPR:$b)>; -def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)), +def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), (SMULBT GPR:$a, GPR:$b)>; -def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)), +def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), + (sra (shl GPR:$b, (i32 16)), (i32 16))), (SMULTB GPR:$a, GPR:$b)>; -def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b), +def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), (SMULTB GPR:$a, GPR:$b)>; -def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16), +def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), + (i32 16)), (SMULWB GPR:$a, GPR:$b)>; -def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16), +def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)), (SMULWB GPR:$a, GPR:$b)>; def : ARMV5TEPat<(add GPR:$acc, - (mul (sra (shl GPR:$a, 16), 16), - (sra (shl GPR:$b, 16), 16))), + (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), + (sra (shl GPR:$b, (i32 16)), (i32 16)))), (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; def : ARMV5TEPat<(add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b)), (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; def : ARMV5TEPat<(add GPR:$acc, - (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))), + (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), + (sra GPR:$b, (i32 16)))), (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; def : ARMV5TEPat<(add GPR:$acc, - (mul sext_16_node:$a, (sra GPR:$b, 16))), + (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; def : ARMV5TEPat<(add GPR:$acc, - (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))), + (mul (sra GPR:$a, (i32 16)), + (sra (shl GPR:$b, (i32 16)), (i32 16)))), (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; def : ARMV5TEPat<(add GPR:$acc, - (mul (sra GPR:$a, 16), sext_16_node:$b)), + (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; def : ARMV5TEPat<(add GPR:$acc, - (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)), + (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), + (i32 16))), (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; def : ARMV5TEPat<(add GPR:$acc, - (sra (mul GPR:$a, sext_16_node:$b), 16)), + (sra (mul GPR:$a, sext_16_node:$b), (i32 16))), (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=73909&r1=73908&r2=73909&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Jun 22 17:08:29 2009 @@ -319,7 +319,7 @@ def tASRri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "asr $dst, $lhs, $rhs", - [(set tGPR:$dst, (sra tGPR:$lhs, imm:$rhs))]>; + [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>; def tASRrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "asr $dst, $rhs", @@ -367,7 +367,7 @@ def tLSLri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "lsl $dst, $lhs, $rhs", - [(set tGPR:$dst, (shl tGPR:$lhs, imm:$rhs))]>; + [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>; def tLSLrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "lsl $dst, $rhs", @@ -375,7 +375,7 @@ def tLSRri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "lsr $dst, $lhs, $rhs", - [(set tGPR:$dst, (srl tGPR:$lhs, imm:$rhs))]>; + [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>; def tLSRrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "lsr $dst, $rhs", @@ -429,18 +429,18 @@ def tREV16 : TI<(outs tGPR:$dst), (ins tGPR:$src), "rev16 $dst, $src", [(set tGPR:$dst, - (or (and (srl tGPR:$src, 8), 0xFF), - (or (and (shl tGPR:$src, 8), 0xFF00), - (or (and (srl tGPR:$src, 8), 0xFF0000), - (and (shl tGPR:$src, 8), 0xFF000000)))))]>, + (or (and (srl tGPR:$src, (i32 8)), 0xFF), + (or (and (shl tGPR:$src, (i32 8)), 0xFF00), + (or (and (srl tGPR:$src, (i32 8)), 0xFF0000), + (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>, Requires<[IsThumb, HasV6]>; def tREVSH : TI<(outs tGPR:$dst), (ins tGPR:$src), "revsh $dst, $src", [(set tGPR:$dst, (sext_inreg - (or (srl (and tGPR:$src, 0xFFFF), 8), - (shl tGPR:$src, 8)), i16))]>, + (or (srl (and tGPR:$src, 0xFFFF), (i32 8)), + (shl tGPR:$src, (i32 8))), i16))]>, Requires<[IsThumb, HasV6]>; def tROR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), From gohman at apple.com Mon Jun 22 17:08:45 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 22 Jun 2009 22:08:45 -0000 Subject: [llvm-commits] [llvm] r73910 - in /llvm/trunk/lib: Analysis/ScalarEvolutionExpander.cpp Transforms/Scalar/IndVarSimplify.cpp Message-ID: <200906222208.n5MM8jmF003110@zion.cs.uiuc.edu> Author: djg Date: Mon Jun 22 17:08:45 2009 New Revision: 73910 URL: http://llvm.org/viewvc/llvm-project?rev=73910&view=rev Log: Fix a few minor issues that were exposed by the removal of SCEVHandle. Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=73910&r1=73909&r2=73910&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Mon Jun 22 17:08:45 2009 @@ -594,7 +594,7 @@ // Truncate the result down to the original type, if needed. const SCEV* T = SE.getTruncateOrNoop(V, Ty); - return expand(V); + return expand(T); } Value *SCEVExpander::visitTruncateExpr(const SCEVTruncateExpr *S) { Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=73910&r1=73909&r2=73910&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Mon Jun 22 17:08:45 2009 @@ -481,7 +481,6 @@ ilist &List = SI->second->Users; for (ilist::iterator UI = List.begin(), E = List.end(); UI != E; ++UI) { - const SCEV* Offset = UI->getOffset(); Value *Op = UI->getOperandValToReplace(); const Type *UseTy = Op->getType(); Instruction *User = UI->getUser(); From resistor at mac.com Mon Jun 22 17:09:07 2009 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Jun 2009 22:09:07 -0000 Subject: [llvm-commits] [llvm] r73911 - /llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <200906222209.n5MM977v003131@zion.cs.uiuc.edu> Author: resistor Date: Mon Jun 22 17:09:07 2009 New Revision: 73911 URL: http://llvm.org/viewvc/llvm-project?rev=73911&view=rev Log: Remove unneeded #include. Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=73911&r1=73910&r2=73911&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Mon Jun 22 17:09:07 2009 @@ -28,7 +28,6 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/GetElementPtrTypeIterator.h" -#include "llvm/Support/ManagedStatic.h" #include using namespace llvm; From resistor at mac.com Mon Jun 22 17:30:58 2009 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Jun 2009 22:30:58 -0000 Subject: [llvm-commits] [llvm] r73912 - /llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Message-ID: <200906222230.n5MMUwVd003837@zion.cs.uiuc.edu> Author: resistor Date: Mon Jun 22 17:30:56 2009 New Revision: 73912 URL: http://llvm.org/viewvc/llvm-project?rev=73912&view=rev Log: Add locking around the external function lookup table for the interpreter. Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp?rev=73912&r1=73911&r2=73912&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Mon Jun 22 17:30:56 2009 @@ -27,6 +27,7 @@ #include "llvm/System/DynamicLibrary.h" #include "llvm/Target/TargetData.h" #include "llvm/Support/ManagedStatic.h" +#include "llvm/System/Mutex.h" #include #include #include @@ -45,6 +46,8 @@ using namespace llvm; +static ManagedStatic FunctionsLock; + typedef GenericValue (*ExFunc)(const FunctionType *, const std::vector &); static ManagedStatic > ExportedFunctions; @@ -94,6 +97,7 @@ ExtName += getTypeID(FT->getContainedType(i)); ExtName += "_" + F->getName(); + sys::ScopedLock Writer(&*FunctionsLock); ExFunc FnPtr = FuncNames[ExtName]; if (FnPtr == 0) FnPtr = FuncNames["lle_X_"+F->getName()]; @@ -246,12 +250,16 @@ const std::vector &ArgVals) { TheInterpreter = this; + FunctionsLock->acquire(); + // Do a lookup to see if the function is in our cache... this should just be a // deferred annotation! std::map::iterator FI = ExportedFunctions->find(F); if (ExFunc Fn = (FI == ExportedFunctions->end()) ? lookupFunction(F) - : FI->second) + : FI->second) { + FunctionsLock->release(); return Fn(F->getFunctionType(), ArgVals); + } #ifdef USE_LIBFFI std::map::iterator RF = RawFunctions->find(F); @@ -264,6 +272,8 @@ } else { RawFn = RF->second; } + + FunctionsLock->release(); GenericValue Result; if (RawFn != 0 && ffiInvoke(RawFn, F, ArgVals, getTargetData(), Result)) @@ -529,6 +539,7 @@ void Interpreter::initializeExternalFunctions() { + sys::ScopedLock Writer(&*FunctionsLock); FuncNames["lle_X_atexit"] = lle_X_atexit; FuncNames["lle_X_exit"] = lle_X_exit; FuncNames["lle_X_abort"] = lle_X_abort; From resistor at mac.com Mon Jun 22 17:44:16 2009 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Jun 2009 22:44:16 -0000 Subject: [llvm-commits] [llvm] r73913 - /llvm/trunk/lib/Support/Annotation.cpp Message-ID: <200906222244.n5MMiGMg004278@zion.cs.uiuc.edu> Author: resistor Date: Mon Jun 22 17:44:15 2009 New Revision: 73913 URL: http://llvm.org/viewvc/llvm-project?rev=73913&view=rev Log: Guard the global annotation tables. Modified: llvm/trunk/lib/Support/Annotation.cpp Modified: llvm/trunk/lib/Support/Annotation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Annotation.cpp?rev=73913&r1=73912&r2=73913&view=diff ============================================================================== --- llvm/trunk/lib/Support/Annotation.cpp (original) +++ llvm/trunk/lib/Support/Annotation.cpp Mon Jun 22 17:44:15 2009 @@ -13,6 +13,7 @@ #include "llvm/Support/Annotation.h" #include "llvm/Support/ManagedStatic.h" +#include "llvm/System/RWMutex.h" #include #include using namespace llvm; @@ -42,31 +43,33 @@ // Static member to ensure initialiation on demand. static ManagedStatic IDMap; +static ManagedStatic > AnnotationsLock; // On demand annotation creation support... typedef Annotation *(*AnnFactory)(AnnotationID, const Annotable *, void *); typedef std::map > FactMapType; -static FactMapType *TheFactMap = 0; +static ManagedStatic TheFactMap; static FactMapType &getFactMap() { - if (TheFactMap == 0) - TheFactMap = new FactMapType(); return *TheFactMap; } static void eraseFromFactMap(unsigned ID) { - assert(TheFactMap && "No entries found!"); + sys::SmartScopedWriter Writer(&*AnnotationsLock); TheFactMap->erase(ID); - if (TheFactMap->empty()) { // Delete when empty - delete TheFactMap; - TheFactMap = 0; - } } AnnotationID AnnotationManager::getID(const char *Name) { // Name -> ID + AnnotationsLock->reader_acquire(); IDMapType::iterator I = IDMap->find(Name); - if (I == IDMap->end()) { - (*IDMap)[Name] = IDCounter++; // Add a new element + IDMapType::iterator E = IDMap->end(); + AnnotationsLock->reader_release(); + + if (I == E) { + sys::SmartScopedWriter Writer(&*AnnotationsLock); + I = IDMap->find(Name); + if (I == IDMap->end()) + (*IDMap)[Name] = IDCounter++; // Add a new element return AnnotationID(IDCounter-1); } return AnnotationID(I->second); @@ -85,6 +88,7 @@ // only be used for debugging. // const char *AnnotationManager::getName(AnnotationID ID) { // ID -> Name + sys::SmartScopedReader Reader(&*AnnotationsLock); IDMapType &TheMap = *IDMap; for (IDMapType::iterator I = TheMap.begin(); ; ++I) { assert(I != TheMap.end() && "Annotation ID is unknown!"); @@ -98,10 +102,12 @@ // void AnnotationManager::registerAnnotationFactory(AnnotationID ID, AnnFactory F, void *ExtraData) { - if (F) + if (F) { + sys::SmartScopedWriter Writer(&*AnnotationsLock); getFactMap()[ID.ID] = std::make_pair(F, ExtraData); - else + } else { eraseFromFactMap(ID.ID); + } } // createAnnotation - Create an annotation of the specified ID for the @@ -109,7 +115,13 @@ // Annotation *AnnotationManager::createAnnotation(AnnotationID ID, const Annotable *Obj) { + AnnotationsLock->reader_acquire(); FactMapType::iterator I = getFactMap().find(ID.ID); - if (I == getFactMap().end()) return 0; + if (I == getFactMap().end()) { + AnnotationsLock->reader_release(); + return 0; + } + + AnnotationsLock->reader_release(); return I->second.first(ID, Obj, I->second.second); } From resistor at mac.com Mon Jun 22 18:08:27 2009 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Jun 2009 23:08:27 -0000 Subject: [llvm-commits] [llvm] r73916 - /llvm/trunk/lib/Support/Statistic.cpp Message-ID: <200906222308.n5MN8RRj005166@zion.cs.uiuc.edu> Author: resistor Date: Mon Jun 22 18:08:27 2009 New Revision: 73916 URL: http://llvm.org/viewvc/llvm-project?rev=73916&view=rev Log: Guard the statistics table. Modified: llvm/trunk/lib/Support/Statistic.cpp Modified: llvm/trunk/lib/Support/Statistic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Statistic.cpp?rev=73916&r1=73915&r2=73916&view=diff ============================================================================== --- llvm/trunk/lib/Support/Statistic.cpp (original) +++ llvm/trunk/lib/Support/Statistic.cpp Mon Jun 22 18:08:27 2009 @@ -25,6 +25,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/Streams.h" +#include "llvm/System/Mutex.h" #include "llvm/ADT/StringExtras.h" #include #include @@ -57,13 +58,14 @@ } static ManagedStatic StatInfo; - +static ManagedStatic StatLock; /// RegisterStatistic - The first time a statistic is bumped, this method is /// called. void Statistic::RegisterStatistic() { // If stats are enabled, inform StatInfo that this statistic should be // printed. + sys::ScopedLock Writer(&*StatLock); if (Enabled) StatInfo->addStatistic(this); // Remember we have been registered. From bob.wilson at apple.com Mon Jun 22 18:27:03 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 22 Jun 2009 23:27:03 -0000 Subject: [llvm-commits] [llvm] r73919 - in /llvm/trunk: include/llvm/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ test/CodeGen/ARM/ Message-ID: <200906222327.n5MNR6TB005894@zion.cs.uiuc.edu> Author: bwilson Date: Mon Jun 22 18:27:02 2009 New Revision: 73919 URL: http://llvm.org/viewvc/llvm-project?rev=73919&view=rev Log: Add support for ARM's Advanced SIMD (NEON) instruction set. This is still a work in progress but most of the NEON instruction set is supported. Added: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/CodeGen/ARM/2009-06-02-ISelCrash.ll llvm/trunk/test/CodeGen/ARM/neon_arith1.ll llvm/trunk/test/CodeGen/ARM/neon_ld1.ll llvm/trunk/test/CodeGen/ARM/neon_ld2.ll llvm/trunk/test/CodeGen/ARM/vaba.ll llvm/trunk/test/CodeGen/ARM/vabal.ll llvm/trunk/test/CodeGen/ARM/vabd.ll llvm/trunk/test/CodeGen/ARM/vabdl.ll llvm/trunk/test/CodeGen/ARM/vabs.ll llvm/trunk/test/CodeGen/ARM/vacge.ll llvm/trunk/test/CodeGen/ARM/vacgt.ll llvm/trunk/test/CodeGen/ARM/vadd.ll llvm/trunk/test/CodeGen/ARM/vaddhn.ll llvm/trunk/test/CodeGen/ARM/vaddl.ll llvm/trunk/test/CodeGen/ARM/vaddw.ll llvm/trunk/test/CodeGen/ARM/vand.ll llvm/trunk/test/CodeGen/ARM/vbic.ll llvm/trunk/test/CodeGen/ARM/vbsl.ll llvm/trunk/test/CodeGen/ARM/vceq.ll llvm/trunk/test/CodeGen/ARM/vcge.ll llvm/trunk/test/CodeGen/ARM/vcgt.ll llvm/trunk/test/CodeGen/ARM/vcls.ll llvm/trunk/test/CodeGen/ARM/vclz.ll llvm/trunk/test/CodeGen/ARM/vcnt.ll llvm/trunk/test/CodeGen/ARM/vcvt.ll llvm/trunk/test/CodeGen/ARM/vcvt_n.ll llvm/trunk/test/CodeGen/ARM/vdup.ll llvm/trunk/test/CodeGen/ARM/vdup_lane.ll llvm/trunk/test/CodeGen/ARM/veor.ll llvm/trunk/test/CodeGen/ARM/vfcmp.ll llvm/trunk/test/CodeGen/ARM/vget_lane.ll llvm/trunk/test/CodeGen/ARM/vhadd.ll llvm/trunk/test/CodeGen/ARM/vhsub.ll llvm/trunk/test/CodeGen/ARM/vicmp.ll llvm/trunk/test/CodeGen/ARM/vmax.ll llvm/trunk/test/CodeGen/ARM/vmin.ll llvm/trunk/test/CodeGen/ARM/vmla.ll llvm/trunk/test/CodeGen/ARM/vmlal.ll llvm/trunk/test/CodeGen/ARM/vmls.ll llvm/trunk/test/CodeGen/ARM/vmlsl.ll llvm/trunk/test/CodeGen/ARM/vmov.ll llvm/trunk/test/CodeGen/ARM/vmovl.ll llvm/trunk/test/CodeGen/ARM/vmovn.ll llvm/trunk/test/CodeGen/ARM/vmul.ll llvm/trunk/test/CodeGen/ARM/vmull.ll llvm/trunk/test/CodeGen/ARM/vmvn.ll llvm/trunk/test/CodeGen/ARM/vneg.ll llvm/trunk/test/CodeGen/ARM/vorn.ll llvm/trunk/test/CodeGen/ARM/vorr.ll llvm/trunk/test/CodeGen/ARM/vpadal.ll llvm/trunk/test/CodeGen/ARM/vpadd.ll llvm/trunk/test/CodeGen/ARM/vpaddl.ll llvm/trunk/test/CodeGen/ARM/vpmax.ll llvm/trunk/test/CodeGen/ARM/vpmin.ll llvm/trunk/test/CodeGen/ARM/vqabs.ll llvm/trunk/test/CodeGen/ARM/vqadd.ll llvm/trunk/test/CodeGen/ARM/vqdmlal.ll llvm/trunk/test/CodeGen/ARM/vqdmlsl.ll llvm/trunk/test/CodeGen/ARM/vqdmulh.ll llvm/trunk/test/CodeGen/ARM/vqdmull.ll llvm/trunk/test/CodeGen/ARM/vqmovn.ll llvm/trunk/test/CodeGen/ARM/vqneg.ll llvm/trunk/test/CodeGen/ARM/vqrshl.ll llvm/trunk/test/CodeGen/ARM/vqrshrn.ll llvm/trunk/test/CodeGen/ARM/vqshl.ll llvm/trunk/test/CodeGen/ARM/vqshrn.ll llvm/trunk/test/CodeGen/ARM/vqsub.ll llvm/trunk/test/CodeGen/ARM/vraddhn.ll llvm/trunk/test/CodeGen/ARM/vrecpe.ll llvm/trunk/test/CodeGen/ARM/vrecps.ll llvm/trunk/test/CodeGen/ARM/vrhadd.ll llvm/trunk/test/CodeGen/ARM/vrshl.ll llvm/trunk/test/CodeGen/ARM/vrshrn.ll llvm/trunk/test/CodeGen/ARM/vrsqrte.ll llvm/trunk/test/CodeGen/ARM/vrsqrts.ll llvm/trunk/test/CodeGen/ARM/vrsubhn.ll llvm/trunk/test/CodeGen/ARM/vset_lane.ll llvm/trunk/test/CodeGen/ARM/vshift.ll llvm/trunk/test/CodeGen/ARM/vshiftins.ll llvm/trunk/test/CodeGen/ARM/vshl.ll llvm/trunk/test/CodeGen/ARM/vshll.ll llvm/trunk/test/CodeGen/ARM/vshrn.ll llvm/trunk/test/CodeGen/ARM/vsra.ll llvm/trunk/test/CodeGen/ARM/vsub.ll llvm/trunk/test/CodeGen/ARM/vsubhn.ll llvm/trunk/test/CodeGen/ARM/vsubl.ll llvm/trunk/test/CodeGen/ARM/vsubw.ll llvm/trunk/test/CodeGen/ARM/vtst.ll Modified: llvm/trunk/include/llvm/Intrinsics.td llvm/trunk/include/llvm/IntrinsicsARM.td llvm/trunk/lib/Target/ARM/ARMCallingConv.td llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/README.txt Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=73919&r1=73918&r2=73919&view=diff ============================================================================== --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Mon Jun 22 18:27:02 2009 @@ -116,6 +116,7 @@ def llvm_v2i32_ty : LLVMType; // 2 x i32 def llvm_v1i64_ty : LLVMType; // 1 x i64 def llvm_v4i32_ty : LLVMType; // 4 x i32 +def llvm_v2f32_ty : LLVMType; // 2 x float def llvm_v4f32_ty : LLVMType; // 4 x float def llvm_v2f64_ty : LLVMType; // 2 x double Modified: llvm/trunk/include/llvm/IntrinsicsARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsARM.td?rev=73919&r1=73918&r2=73919&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsARM.td (original) +++ llvm/trunk/include/llvm/IntrinsicsARM.td Mon Jun 22 18:27:02 2009 @@ -19,3 +19,298 @@ def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">, Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>; } + +//===----------------------------------------------------------------------===// +// Advanced SIMD (NEON) + +let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". + + // The following classes do not correspond directly to GCC builtins. + class Neon_1Arg_Intrinsic + : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>; + class Neon_1Arg_Float_Intrinsic + : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; + class Neon_1Arg_Narrow_Intrinsic + : Intrinsic<[llvm_anyint_ty], + [LLVMExtendedElementVectorType<0>], [IntrNoMem]>; + class Neon_1Arg_Long_Intrinsic + : Intrinsic<[llvm_anyint_ty], + [LLVMTruncatedElementVectorType<0>], [IntrNoMem]>; + class Neon_2Arg_Intrinsic + : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], + [IntrNoMem]>; + class Neon_2Arg_Float_Intrinsic + : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], + [IntrNoMem]>; + class Neon_2Arg_Narrow_Intrinsic + : Intrinsic<[llvm_anyint_ty], + [LLVMExtendedElementVectorType<0>, + LLVMExtendedElementVectorType<0>], + [IntrNoMem]>; + class Neon_2Arg_Long_Intrinsic + : Intrinsic<[llvm_anyint_ty], + [LLVMTruncatedElementVectorType<0>, + LLVMTruncatedElementVectorType<0>], + [IntrNoMem]>; + class Neon_2Arg_Wide_Intrinsic + : Intrinsic<[llvm_anyint_ty], + [LLVMMatchType<0>, LLVMTruncatedElementVectorType<0>], + [IntrNoMem]>; + class Neon_3Arg_Intrinsic + : Intrinsic<[llvm_anyint_ty], + [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], + [IntrNoMem]>; + class Neon_3Arg_Long_Intrinsic + : Intrinsic<[llvm_anyint_ty], + [LLVMMatchType<0>, + LLVMTruncatedElementVectorType<0>, + LLVMTruncatedElementVectorType<0>], + [IntrNoMem]>; + class Neon_CvtFxToFP_Intrinsic + : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>; + class Neon_CvtFPToFx_Intrinsic + : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>; +} + +// Arithmetic ops + +let Properties = [IntrNoMem, Commutative] in { + + // Vector Add. + def int_arm_neon_vhadds : Neon_2Arg_Intrinsic; + def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic; + def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic; + def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic; + def int_arm_neon_vqadds : Neon_2Arg_Intrinsic; + def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic; + def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic; + def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic; + def int_arm_neon_vaddls : Neon_2Arg_Long_Intrinsic; + def int_arm_neon_vaddlu : Neon_2Arg_Long_Intrinsic; + def int_arm_neon_vaddws : Neon_2Arg_Wide_Intrinsic; + def int_arm_neon_vaddwu : Neon_2Arg_Wide_Intrinsic; + + // Vector Multiply. + def int_arm_neon_vmulp : Neon_2Arg_Intrinsic; + def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic; + def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic; + def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic; + def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic; + def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic; + def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic; + + // Vector Multiply and Accumulate/Subtract. + def int_arm_neon_vmlals : Neon_3Arg_Long_Intrinsic; + def int_arm_neon_vmlalu : Neon_3Arg_Long_Intrinsic; + def int_arm_neon_vmlsls : Neon_3Arg_Long_Intrinsic; + def int_arm_neon_vmlslu : Neon_3Arg_Long_Intrinsic; + def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic; + def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic; + + // Vector Maximum. + def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic; + def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic; + def int_arm_neon_vmaxf : Neon_2Arg_Float_Intrinsic; + + // Vector Minimum. + def int_arm_neon_vmins : Neon_2Arg_Intrinsic; + def int_arm_neon_vminu : Neon_2Arg_Intrinsic; + def int_arm_neon_vminf : Neon_2Arg_Float_Intrinsic; + + // Vector Reciprocal Step. + def int_arm_neon_vrecps : Neon_2Arg_Float_Intrinsic; + + // Vector Reciprocal Square Root Step. + def int_arm_neon_vrsqrts : Neon_2Arg_Float_Intrinsic; +} + +// Vector Subtract. +def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic; +def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic; +def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic; +def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic; +def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic; +def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic; +def int_arm_neon_vsubls : Neon_2Arg_Long_Intrinsic; +def int_arm_neon_vsublu : Neon_2Arg_Long_Intrinsic; +def int_arm_neon_vsubws : Neon_2Arg_Wide_Intrinsic; +def int_arm_neon_vsubwu : Neon_2Arg_Wide_Intrinsic; + +// Vector Absolute Compare. +let TargetPrefix = "arm" in { + def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty], + [llvm_v2f32_ty, llvm_v2f32_ty], + [IntrNoMem]>; + def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty], + [llvm_v4f32_ty, llvm_v4f32_ty], + [IntrNoMem]>; + def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty], + [llvm_v2f32_ty, llvm_v2f32_ty], + [IntrNoMem]>; + def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty], + [llvm_v4f32_ty, llvm_v4f32_ty], + [IntrNoMem]>; +} + +// Vector Absolute Differences. +def int_arm_neon_vabds : Neon_2Arg_Intrinsic; +def int_arm_neon_vabdu : Neon_2Arg_Intrinsic; +def int_arm_neon_vabdf : Neon_2Arg_Float_Intrinsic; +def int_arm_neon_vabdls : Neon_2Arg_Long_Intrinsic; +def int_arm_neon_vabdlu : Neon_2Arg_Long_Intrinsic; + +// Vector Absolute Difference and Accumulate. +def int_arm_neon_vabas : Neon_3Arg_Intrinsic; +def int_arm_neon_vabau : Neon_3Arg_Intrinsic; +def int_arm_neon_vabals : Neon_3Arg_Long_Intrinsic; +def int_arm_neon_vabalu : Neon_3Arg_Long_Intrinsic; + +// Vector Pairwise Add. +def int_arm_neon_vpaddi : Neon_2Arg_Intrinsic; +def int_arm_neon_vpaddf : Neon_2Arg_Float_Intrinsic; + +// Vector Pairwise Add Long. +// Note: This is different than the other "long" NEON intrinsics because +// the result vector has half as many elements as the source vector. +// The source and destination vector types must be specified separately. +let TargetPrefix = "arm" in { + def int_arm_neon_vpaddls : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], + [IntrNoMem]>; + def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], + [IntrNoMem]>; +} + +// Vector Pairwise Add and Accumulate Long. +// Note: This is similar to vpaddl but the destination vector also appears +// as the first argument. +let TargetPrefix = "arm" in { + def int_arm_neon_vpadals : Intrinsic<[llvm_anyint_ty], + [LLVMMatchType<0>, llvm_anyint_ty], + [IntrNoMem]>; + def int_arm_neon_vpadalu : Intrinsic<[llvm_anyint_ty], + [LLVMMatchType<0>, llvm_anyint_ty], + [IntrNoMem]>; +} + +// Vector Pairwise Maximum and Minimum. +def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic; +def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic; +def int_arm_neon_vpmaxf : Neon_2Arg_Float_Intrinsic; +def int_arm_neon_vpmins : Neon_2Arg_Intrinsic; +def int_arm_neon_vpminu : Neon_2Arg_Intrinsic; +def int_arm_neon_vpminf : Neon_2Arg_Float_Intrinsic; + +// Vector Shifts: +// +// The various saturating and rounding vector shift operations need to be +// represented by intrinsics in LLVM, and even the basic VSHL variable shift +// operation cannot be safely translated to LLVM's shift operators. VSHL can +// be used for both left and right shifts, or even combinations of the two, +// depending on the signs of the shift amounts. It also has well-defined +// behavior for shift amounts that LLVM leaves undefined. Only basic shifts +// by constants can be represented with LLVM's shift operators. +// +// The shift counts for these intrinsics are always vectors, even for constant +// shifts, where the constant is replicated. For consistency with VSHL (and +// other variable shift instructions), left shifts have positive shift counts +// and right shifts have negative shift counts. This convention is also used +// for constant right shift intrinsics, and to help preserve sanity, the +// intrinsic names use "shift" instead of either "shl" or "shr". Where +// applicable, signed and unsigned versions of the intrinsics are +// distinguished with "s" and "u" suffixes. A few NEON shift instructions, +// such as VQSHLU, take signed operands but produce unsigned results; these +// use a "su" suffix. + +// Vector Shift. +def int_arm_neon_vshifts : Neon_2Arg_Intrinsic; +def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic; +def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic; +def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic; +def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic; + +// Vector Rounding Shift. +def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic; +def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic; +def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic; + +// Vector Saturating Shift. +def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic; +def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic; +def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic; +def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic; +def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic; +def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic; + +// Vector Saturating Rounding Shift. +def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic; +def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic; +def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic; +def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic; +def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic; + +// Vector Shift and Insert. +def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic; + +// Vector Absolute Value and Saturating Absolute Value. +def int_arm_neon_vabs : Neon_1Arg_Intrinsic; +def int_arm_neon_vabsf : Neon_1Arg_Float_Intrinsic; +def int_arm_neon_vqabs : Neon_1Arg_Intrinsic; + +// Vector Saturating Negate. +def int_arm_neon_vqneg : Neon_1Arg_Intrinsic; + +// Vector Count Leading Sign/Zero Bits. +def int_arm_neon_vcls : Neon_1Arg_Intrinsic; +def int_arm_neon_vclz : Neon_1Arg_Intrinsic; + +// Vector Count One Bits. +def int_arm_neon_vcnt : Neon_1Arg_Intrinsic; + +// Vector Reciprocal Estimate. +def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic; +def int_arm_neon_vrecpef : Neon_1Arg_Float_Intrinsic; + +// Vector Reciprocal Square Root Estimate. +def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic; +def int_arm_neon_vrsqrtef : Neon_1Arg_Float_Intrinsic; + +// Vector Conversions Between Floating-point and Fixed-point. +def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic; +def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic; +def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic; +def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic; + +// Narrowing and Lengthening Vector Moves. +def int_arm_neon_vmovn : Neon_1Arg_Narrow_Intrinsic; +def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic; +def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic; +def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic; +def int_arm_neon_vmovls : Neon_1Arg_Long_Intrinsic; +def int_arm_neon_vmovlu : Neon_1Arg_Long_Intrinsic; + +let TargetPrefix = "arm" in { + + // De-interleaving vector loads from N-element structures. + def int_arm_neon_vld3i : Intrinsic<[llvm_anyint_ty], + [llvm_ptr_ty], [IntrReadArgMem]>; + def int_arm_neon_vld3f : Intrinsic<[llvm_anyfloat_ty], + [llvm_ptr_ty], [IntrReadArgMem]>; + def int_arm_neon_vld4i : Intrinsic<[llvm_anyint_ty], + [llvm_ptr_ty], [IntrReadArgMem]>; + def int_arm_neon_vld4f : Intrinsic<[llvm_anyfloat_ty], + [llvm_ptr_ty], [IntrReadArgMem]>; + + // Interleaving vector stores from N-element structures. + def int_arm_neon_vst3i : Intrinsic<[llvm_void_ty], + [llvm_anyint_ty, llvm_ptr_ty], + [IntrWriteArgMem]>; + def int_arm_neon_vst3f : Intrinsic<[llvm_void_ty], + [llvm_anyfloat_ty, llvm_ptr_ty], + [IntrWriteArgMem]>; + def int_arm_neon_vst4i : Intrinsic<[llvm_void_ty], + [llvm_anyint_ty, llvm_ptr_ty], + [IntrWriteArgMem]>; + def int_arm_neon_vst4f : Intrinsic<[llvm_void_ty], + [llvm_anyfloat_ty, llvm_ptr_ty], + [IntrWriteArgMem]>; +} Modified: llvm/trunk/lib/Target/ARM/ARMCallingConv.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallingConv.td?rev=73919&r1=73918&r2=73919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCallingConv.td (original) +++ llvm/trunk/lib/Target/ARM/ARMCallingConv.td Mon Jun 22 18:27:02 2009 @@ -24,19 +24,29 @@ CCIfType<[i8, i16], CCPromoteToType>, - // f64 is passed in pairs of GPRs, possibly split onto the stack - CCIfType<[f64], CCCustom<"CC_ARM_APCS_Custom_f64">>, + // Handle all vector types as either f64 or v2f64. + CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, + CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType>, + + // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack + CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>, CCIfType<[f32], CCBitConvertToType>, CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, CCIfType<[i32], CCAssignToStack<4, 4>>, - CCIfType<[f64], CCAssignToStack<8, 4>> + CCIfType<[f64], CCAssignToStack<8, 4>>, + CCIfType<[v2f64], CCAssignToStack<16, 4>> ]>; def RetCC_ARM_APCS : CallingConv<[ CCIfType<[f32], CCBitConvertToType>, - CCIfType<[f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>, + + // Handle all vector types as either f64 or v2f64. + CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, + CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType>, + + CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>, CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> @@ -59,7 +69,8 @@ CCAssignToReg<[R0, R1, R2, R3]>>>, CCIfType<[i32, f32], CCAssignToStack<4, 4>>, - CCIfType<[f64], CCAssignToStack<8, 8>> + CCIfType<[f64], CCAssignToStack<8, 8>>, + CCIfType<[v2f64], CCAssignToStack<16, 8>> ]>; def RetCC_ARM_AAPCS_Common : CallingConv<[ @@ -72,13 +83,21 @@ //===----------------------------------------------------------------------===// def CC_ARM_AAPCS : CallingConv<[ - CCIfType<[f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>, + // Handle all vector types as either f64 or v2f64. + CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, + CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType>, + + CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>, CCIfType<[f32], CCBitConvertToType>, CCDelegateTo ]>; def RetCC_ARM_AAPCS : CallingConv<[ - CCIfType<[f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>, + // Handle all vector types as either f64 or v2f64. + CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, + CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType>, + + CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>, CCIfType<[f32], CCBitConvertToType>, CCDelegateTo ]>; @@ -88,6 +107,10 @@ //===----------------------------------------------------------------------===// def CC_ARM_AAPCS_VFP : CallingConv<[ + // Handle all vector types as either f64 or v2f64. + CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, + CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType>, + CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15]>>, @@ -95,6 +118,10 @@ ]>; def RetCC_ARM_AAPCS_VFP : CallingConv<[ + // Handle all vector types as either f64 or v2f64. + CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, + CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType>, + CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15]>>, Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=73919&r1=73918&r2=73919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Jun 22 18:27:02 2009 @@ -32,6 +32,9 @@ #include "llvm/Support/Debug.h" using namespace llvm; +static const unsigned arm_dsubreg_0 = 5; +static const unsigned arm_dsubreg_1 = 6; + //===--------------------------------------------------------------------===// /// ARMDAGToDAGISel - ARM specific code to select ARM machine /// instructions for SelectionDAG operations. @@ -918,6 +921,65 @@ return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl, MVT::Other, Ops, 3); } + + case ISD::CONCAT_VECTORS: { + MVT VT = Op.getValueType(); + assert(VT.is128BitVector() && Op.getNumOperands() == 2 && + "unexpected CONCAT_VECTORS"); + SDValue N0 = Op.getOperand(0); + SDValue N1 = Op.getOperand(1); + SDNode *Result = + CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT); + if (N0.getOpcode() != ISD::UNDEF) + Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT, + SDValue(Result, 0), N0, + CurDAG->getTargetConstant(arm_dsubreg_0, + MVT::i32)); + if (N1.getOpcode() != ISD::UNDEF) + Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT, + SDValue(Result, 0), N1, + CurDAG->getTargetConstant(arm_dsubreg_1, + MVT::i32)); + return Result; + } + + case ISD::VECTOR_SHUFFLE: { + MVT VT = Op.getValueType(); + + // Match 128-bit splat to VDUPLANEQ. (This could be done with a Pat in + // ARMInstrNEON.td but it is awkward because the shuffle mask needs to be + // transformed first into a lane number and then to both a subregister + // index and an adjusted lane number.) If the source operand is a + // SCALAR_TO_VECTOR, leave it so it will be matched later as a VDUP. + ShuffleVectorSDNode *SVOp = cast(N); + if (VT.is128BitVector() && SVOp->isSplat() && + Op.getOperand(0).getOpcode() != ISD::SCALAR_TO_VECTOR && + Op.getOperand(1).getOpcode() == ISD::UNDEF) { + unsigned LaneVal = SVOp->getSplatIndex(); + + MVT HalfVT; + unsigned Opc = 0; + switch (VT.getVectorElementType().getSimpleVT()) { + default: assert(false && "unhandled VDUP splat type"); + case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break; + case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break; + case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break; + case MVT::f32: Opc = ARM::VDUPLNfq; HalfVT = MVT::v2f32; break; + } + + // The source operand needs to be changed to a subreg of the original + // 128-bit operand, and the lane number needs to be adjusted accordingly. + unsigned NumElts = VT.getVectorNumElements() / 2; + unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1); + SDValue SR = CurDAG->getTargetConstant(SRVal, MVT::i32); + SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, MVT::i32); + SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG, + dl, HalfVT, N->getOperand(0), SR); + return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane); + } + + break; + } } return SelectCode(Op); Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=73919&r1=73918&r2=73919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Jun 22 18:27:02 2009 @@ -56,6 +56,52 @@ ISD::ArgFlagsTy &ArgFlags, CCState &State); +void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, + MVT PromotedBitwiseVT) { + if (VT != PromotedLdStVT) { + setOperationAction(ISD::LOAD, VT, Promote); + AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); + + setOperationAction(ISD::STORE, VT, Promote); + AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); + } + + MVT ElemTy = VT.getVectorElementType(); + if (ElemTy != MVT::i64 && ElemTy != MVT::f64) + setOperationAction(ISD::VSETCC, VT, Custom); + if (ElemTy == MVT::i8 || ElemTy == MVT::i16) + setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); + setOperationAction(ISD::BUILD_VECTOR, VT, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); + setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); + setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); + if (VT.isInteger()) { + setOperationAction(ISD::SHL, VT, Custom); + setOperationAction(ISD::SRA, VT, Custom); + setOperationAction(ISD::SRL, VT, Custom); + } + + // Promote all bit-wise operations. + if (VT.isInteger() && VT != PromotedBitwiseVT) { + setOperationAction(ISD::AND, VT, Promote); + AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT); + setOperationAction(ISD::OR, VT, Promote); + AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT); + setOperationAction(ISD::XOR, VT, Promote); + AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT); + } +} + +void ARMTargetLowering::addDRTypeForNEON(MVT VT) { + addRegisterClass(VT, ARM::DPRRegisterClass); + addTypeForNEON(VT, MVT::f64, MVT::v2i32); +} + +void ARMTargetLowering::addQRTypeForNEON(MVT VT) { + addRegisterClass(VT, ARM::QPRRegisterClass); + addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); +} + ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) : TargetLowering(TM), ARMPCLabelIndex(0) { Subtarget = &TM.getSubtarget(); @@ -152,6 +198,30 @@ setTruncStoreAction(MVT::f64, MVT::f32, Expand); } + + if (Subtarget->hasNEON()) { + addDRTypeForNEON(MVT::v2f32); + addDRTypeForNEON(MVT::v8i8); + addDRTypeForNEON(MVT::v4i16); + addDRTypeForNEON(MVT::v2i32); + addDRTypeForNEON(MVT::v1i64); + + addQRTypeForNEON(MVT::v4f32); + addQRTypeForNEON(MVT::v2f64); + addQRTypeForNEON(MVT::v16i8); + addQRTypeForNEON(MVT::v8i16); + addQRTypeForNEON(MVT::v4i32); + addQRTypeForNEON(MVT::v2i64); + + setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); + setTargetDAGCombine(ISD::SHL); + setTargetDAGCombine(ISD::SRL); + setTargetDAGCombine(ISD::SRA); + setTargetDAGCombine(ISD::SIGN_EXTEND); + setTargetDAGCombine(ISD::ZERO_EXTEND); + setTargetDAGCombine(ISD::ANY_EXTEND); + } + computeRegisterProperties(); // ARM does not have f32 extending load. @@ -352,6 +422,36 @@ case ARMISD::FMDRR: return "ARMISD::FMDRR"; case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; + + case ARMISD::VCEQ: return "ARMISD::VCEQ"; + case ARMISD::VCGE: return "ARMISD::VCGE"; + case ARMISD::VCGEU: return "ARMISD::VCGEU"; + case ARMISD::VCGT: return "ARMISD::VCGT"; + case ARMISD::VCGTU: return "ARMISD::VCGTU"; + case ARMISD::VTST: return "ARMISD::VTST"; + + case ARMISD::VSHL: return "ARMISD::VSHL"; + case ARMISD::VSHRs: return "ARMISD::VSHRs"; + case ARMISD::VSHRu: return "ARMISD::VSHRu"; + case ARMISD::VSHLLs: return "ARMISD::VSHLLs"; + case ARMISD::VSHLLu: return "ARMISD::VSHLLu"; + case ARMISD::VSHLLi: return "ARMISD::VSHLLi"; + case ARMISD::VSHRN: return "ARMISD::VSHRN"; + case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; + case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; + case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; + case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; + case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; + case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; + case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; + case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; + case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; + case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; + case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; + case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; + case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; + case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; + case ARMISD::VDUPLANEQ: return "ARMISD::VDUPLANEQ"; } } @@ -423,63 +523,93 @@ #include "ARMGenCallingConv.inc" // APCS f64 is in register pairs, possibly split to stack -static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State) { - static const unsigned HiRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; - static const unsigned LoRegList[] = { ARM::R1, - ARM::R2, - ARM::R3, - ARM::NoRegister }; - - unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 4); - if (Reg == 0) - return false; // we didn't handle it +static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, + CCValAssign::LocInfo &LocInfo, + CCState &State, bool CanFail) { + static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; + + // Try to get the first register. + if (unsigned Reg = State.AllocateReg(RegList, 4)) + State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + else { + // For the 2nd half of a v2f64, do not fail. + if (CanFail) + return false; - unsigned i; - for (i = 0; i < 4; ++i) - if (HiRegList[i] == Reg) - break; + // Put the whole thing on the stack. + State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, + State.AllocateStack(8, 4), + LocVT, LocInfo)); + return true; + } - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo)); - if (LoRegList[i] != ARM::NoRegister) - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], - MVT::i32, LocInfo)); + // Try to get the second register. + if (unsigned Reg = State.AllocateReg(RegList, 4)) + State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); else State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, State.AllocateStack(4, 4), - MVT::i32, LocInfo)); + LocVT, LocInfo)); + return true; +} + +static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, + CCValAssign::LocInfo &LocInfo, + ISD::ArgFlagsTy &ArgFlags, + CCState &State) { + if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) + return false; + if (LocVT == MVT::v2f64 && + !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) + return false; return true; // we handled it } // AAPCS f64 is in aligned register pairs -static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State) { +static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, + CCValAssign::LocInfo &LocInfo, + CCState &State, bool CanFail) { static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); - if (Reg == 0) - return false; // we didn't handle it + if (Reg == 0) { + // For the 2nd half of a v2f64, do not just fail. + if (CanFail) + return false; + + // Put the whole thing on the stack. + State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, + State.AllocateStack(8, 8), + LocVT, LocInfo)); + return true; + } unsigned i; for (i = 0; i < 2; ++i) if (HiRegList[i] == Reg) break; - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo)); + State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], - MVT::i32, LocInfo)); + LocVT, LocInfo)); + return true; +} + +static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, + CCValAssign::LocInfo &LocInfo, + ISD::ArgFlagsTy &ArgFlags, + CCState &State) { + if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) + return false; + if (LocVT == MVT::v2f64 && + !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) + return false; return true; // we handled it } -static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State) { +static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT, + CCValAssign::LocInfo &LocInfo, CCState &State) { static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; @@ -492,9 +622,20 @@ if (HiRegList[i] == Reg) break; - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo)); + State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], - MVT::i32, LocInfo)); + LocVT, LocInfo)); + return true; +} + +static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, + CCValAssign::LocInfo &LocInfo, + ISD::ArgFlagsTy &ArgFlags, + CCState &State) { + if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) + return false; + if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) + return false; return true; // we handled it } @@ -558,7 +699,7 @@ SDValue Val; if (VA.needsCustom()) { - // Handle f64 as custom. + // Handle f64 or half of a v2f64. SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); Chain = Lo.getValue(1); @@ -569,6 +710,24 @@ Chain = Hi.getValue(1); InFlag = Hi.getValue(2); Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi); + + if (VA.getLocVT() == MVT::v2f64) { + SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); + Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, + DAG.getConstant(0, MVT::i32)); + + VA = RVLocs[++i]; // skip ahead to next loc + Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); + Chain = Lo.getValue(1); + InFlag = Lo.getValue(2); + VA = RVLocs[++i]; // skip ahead to next loc + Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); + Chain = Hi.getValue(1); + InFlag = Hi.getValue(2); + Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi); + Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, + DAG.getConstant(1, MVT::i32)); + } } else { Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), InFlag); @@ -625,6 +784,31 @@ PseudoSourceValue::getStack(), LocMemOffset); } +void ARMTargetLowering::PassF64ArgInRegs(CallSDNode *TheCall, SelectionDAG &DAG, + SDValue Chain, SDValue &Arg, + RegsToPassVector &RegsToPass, + CCValAssign &VA, CCValAssign &NextVA, + SDValue &StackPtr, + SmallVector &MemOpChains, + ISD::ArgFlagsTy Flags) { + DebugLoc dl = TheCall->getDebugLoc(); + + SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl, + DAG.getVTList(MVT::i32, MVT::i32), Arg); + RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); + + if (NextVA.isRegLoc()) + RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); + else { + assert(NextVA.isMemLoc()); + if (StackPtr.getNode() == 0) + StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); + + MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, NextVA, + Chain, fmrrd.getValue(1), Flags)); + } +} + /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <- /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter /// nodes. @@ -651,7 +835,7 @@ SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32); - SmallVector, 8> RegsToPass; + RegsToPassVector RegsToPass; SmallVector MemOpChains; // Walk the register/memloc assignments, inserting copies/loads. In the case @@ -681,22 +865,32 @@ break; } - // f64 is passed in i32 pairs and must be combined + // f64 and v2f64 are passed in i32 pairs and must be split into pieces if (VA.needsCustom()) { - SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl, - DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); - RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); - VA = ArgLocs[++i]; // skip ahead to next loc - if (VA.isRegLoc()) - RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(1))); - else { - assert(VA.isMemLoc()); - if (StackPtr.getNode() == 0) - StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); - - MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA, - Chain, fmrrd.getValue(1), - Flags)); + if (VA.getLocVT() == MVT::v2f64) { + SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, + DAG.getConstant(0, MVT::i32)); + SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, + DAG.getConstant(1, MVT::i32)); + + PassF64ArgInRegs(TheCall, DAG, Chain, Op0, RegsToPass, + VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); + + VA = ArgLocs[++i]; // skip ahead to next loc + if (VA.isRegLoc()) { + PassF64ArgInRegs(TheCall, DAG, Chain, Op1, RegsToPass, + VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); + } else { + assert(VA.isMemLoc()); + if (StackPtr.getNode() == 0) + StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); + + MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA, + Chain, Op1, Flags)); + } + } else { + PassF64ArgInRegs(TheCall, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], + StackPtr, MemOpChains, Flags); } } else if (VA.isRegLoc()) { RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); @@ -864,9 +1058,28 @@ break; } - // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is - // available. if (VA.needsCustom()) { + if (VA.getLocVT() == MVT::v2f64) { + // Extract the first half and return it in two registers. + SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, + DAG.getConstant(0, MVT::i32)); + SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl, + DAG.getVTList(MVT::i32, MVT::i32), Half); + + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); + Flag = Chain.getValue(1); + VA = RVLocs[++i]; // skip ahead to next loc + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), + HalfGPRs.getValue(1), Flag); + Flag = Chain.getValue(1); + VA = RVLocs[++i]; // skip ahead to next loc + + // Extract the 2nd half and fall through to handle it as an f64 value. + Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, + DAG.getConstant(1, MVT::i32)); + } + // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is + // available. SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); @@ -1117,6 +1330,40 @@ } SDValue +ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, + SDValue &Root, SelectionDAG &DAG, + DebugLoc dl) { + MachineFunction &MF = DAG.getMachineFunction(); + ARMFunctionInfo *AFI = MF.getInfo(); + + TargetRegisterClass *RC; + if (AFI->isThumbFunction()) + RC = ARM::tGPRRegisterClass; + else + RC = ARM::GPRRegisterClass; + + // Transform the arguments stored in physical registers into virtual ones. + unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); + SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); + + SDValue ArgValue2; + if (NextVA.isMemLoc()) { + unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8; + MachineFrameInfo *MFI = MF.getFrameInfo(); + int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset()); + + // Create load node to retrieve arguments from the stack. + SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); + ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0); + } else { + Reg = MF.addLiveIn(NextVA.getLocReg(), RC); + ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); + } + + return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2); +} + +SDValue ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -1141,47 +1388,45 @@ // Arguments stored in registers. if (VA.isRegLoc()) { MVT RegVT = VA.getLocVT(); - TargetRegisterClass *RC; - if (AFI->isThumbFunction()) - RC = ARM::tGPRRegisterClass; - else - RC = ARM::GPRRegisterClass; - if (FloatABIType == FloatABI::Hard) { - if (RegVT == MVT::f32) - RC = ARM::SPRRegisterClass; - else if (RegVT == MVT::f64) - RC = ARM::DPRRegisterClass; - } else if (RegVT == MVT::f64) { - // f64 is passed in pairs of GPRs and must be combined. + SDValue ArgValue; + if (VA.needsCustom()) { + // f64 and vector types are split up into multiple registers or + // combinations of registers and stack slots. RegVT = MVT::i32; - } else if (!((RegVT == MVT::i32) || (RegVT == MVT::f32))) - assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering"); - - // Transform the arguments stored in physical registers into virtual ones. - unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); - SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT); - // f64 is passed in i32 pairs and must be combined. - if (VA.needsCustom()) { - SDValue ArgValue2; + if (VA.getLocVT() == MVT::v2f64) { + SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], + Root, DAG, dl); + VA = ArgLocs[++i]; // skip ahead to next loc + SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], + Root, DAG, dl); + ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); + ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, + ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); + ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, + ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); + } else + ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Root, DAG, dl); - VA = ArgLocs[++i]; // skip ahead to next loc - if (VA.isMemLoc()) { - // must be APCS to split like this - unsigned ArgSize = VA.getLocVT().getSizeInBits()/8; - int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset()); - - // Create load node to retrieve arguments from the stack. - SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); - ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0); - } else { - Reg = MF.addLiveIn(VA.getLocReg(), RC); - ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); - } + } else { + TargetRegisterClass *RC; + if (FloatABIType == FloatABI::Hard && RegVT == MVT::f32) + RC = ARM::SPRRegisterClass; + else if (FloatABIType == FloatABI::Hard && RegVT == MVT::f64) + RC = ARM::DPRRegisterClass; + else if (AFI->isThumbFunction()) + RC = ARM::tGPRRegisterClass; + else + RC = ARM::GPRRegisterClass; - ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, - ArgValue, ArgValue2); + assert((RegVT == MVT::i32 || RegVT == MVT::f32 || + (FloatABIType == FloatABI::Hard && RegVT == MVT::f64)) && + "RegVT not supported by FORMAL_ARGUMENTS Lowering"); + + // Transform the arguments in physical registers into virtual ones. + unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); + ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT); } // If this is an 8 or 16-bit value, it is really passed promoted @@ -1638,8 +1883,78 @@ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); } -static SDValue ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { - assert(N->getValueType(0) == MVT::i64 && +/// getZeroVector - Returns a vector of specified type with all zero elements. +/// +static SDValue getZeroVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) { + assert(VT.isVector() && "Expected a vector type"); + + // Zero vectors are used to represent vector negation and in those cases + // will be implemented with the NEON VNEG instruction. However, VNEG does + // not support i64 elements, so sometimes the zero vectors will need to be + // explicitly constructed. For those cases, and potentially other uses in + // the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted + // to their dest type. This ensures they get CSE'd. + SDValue Vec; + SDValue Cst = DAG.getTargetConstant(0, MVT::i32); + if (VT.getSizeInBits() == 64) + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); + else + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); + + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); +} + +/// getOnesVector - Returns a vector of specified type with all bits set. +/// +static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) { + assert(VT.isVector() && "Expected a vector type"); + + // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest + // type. This ensures they get CSE'd. + SDValue Vec; + SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); + if (VT.getSizeInBits() == 64) + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); + else + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); + + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); +} + +static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, + const ARMSubtarget *ST) { + MVT VT = N->getValueType(0); + DebugLoc dl = N->getDebugLoc(); + + // Lower vector shifts on NEON to use VSHL. + if (VT.isVector()) { + assert(ST->hasNEON() && "unexpected vector shift"); + + // Left shifts translate directly to the vshiftu intrinsic. + if (N->getOpcode() == ISD::SHL) + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, + DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), + N->getOperand(0), N->getOperand(1)); + + assert((N->getOpcode() == ISD::SRA || + N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"); + + // NEON uses the same intrinsics for both left and right shifts. For + // right shifts, the shift amounts are negative, so negate the vector of + // shift amounts. + MVT ShiftVT = N->getOperand(1).getValueType(); + SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, + getZeroVector(ShiftVT, DAG, dl), + N->getOperand(1)); + Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ? + Intrinsic::arm_neon_vshifts : + Intrinsic::arm_neon_vshiftu); + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, + DAG.getConstant(vshiftInt, MVT::i32), + N->getOperand(0), NegatedCount); + } + + assert(VT == MVT::i64 && (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && "Unknown shift to lower!"); @@ -1652,7 +1967,6 @@ if (ST->isThumb()) return SDValue(); // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. - DebugLoc dl = N->getDebugLoc(); SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(0, MVT::i32)); SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), @@ -1670,6 +1984,273 @@ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); } +static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { + SDValue TmpOp0, TmpOp1; + bool Invert = false; + bool Swap = false; + unsigned Opc = 0; + + SDValue Op0 = Op.getOperand(0); + SDValue Op1 = Op.getOperand(1); + SDValue CC = Op.getOperand(2); + MVT VT = Op.getValueType(); + ISD::CondCode SetCCOpcode = cast(CC)->get(); + DebugLoc dl = Op.getDebugLoc(); + + if (Op.getOperand(1).getValueType().isFloatingPoint()) { + switch (SetCCOpcode) { + default: assert(0 && "Illegal FP comparison"); break; + case ISD::SETUNE: + case ISD::SETNE: Invert = true; // Fallthrough + case ISD::SETOEQ: + case ISD::SETEQ: Opc = ARMISD::VCEQ; break; + case ISD::SETOLT: + case ISD::SETLT: Swap = true; // Fallthrough + case ISD::SETOGT: + case ISD::SETGT: Opc = ARMISD::VCGT; break; + case ISD::SETOLE: + case ISD::SETLE: Swap = true; // Fallthrough + case ISD::SETOGE: + case ISD::SETGE: Opc = ARMISD::VCGE; break; + case ISD::SETUGE: Swap = true; // Fallthrough + case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; + case ISD::SETUGT: Swap = true; // Fallthrough + case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; + case ISD::SETUEQ: Invert = true; // Fallthrough + case ISD::SETONE: + // Expand this to (OLT | OGT). + TmpOp0 = Op0; + TmpOp1 = Op1; + Opc = ISD::OR; + Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); + Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1); + break; + case ISD::SETUO: Invert = true; // Fallthrough + case ISD::SETO: + // Expand this to (OLT | OGE). + TmpOp0 = Op0; + TmpOp1 = Op1; + Opc = ISD::OR; + Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); + Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); + break; + } + } else { + // Integer comparisons. + switch (SetCCOpcode) { + default: assert(0 && "Illegal integer comparison"); break; + case ISD::SETNE: Invert = true; + case ISD::SETEQ: Opc = ARMISD::VCEQ; break; + case ISD::SETLT: Swap = true; + case ISD::SETGT: Opc = ARMISD::VCGT; break; + case ISD::SETLE: Swap = true; + case ISD::SETGE: Opc = ARMISD::VCGE; break; + case ISD::SETULT: Swap = true; + case ISD::SETUGT: Opc = ARMISD::VCGTU; break; + case ISD::SETULE: Swap = true; + case ISD::SETUGE: Opc = ARMISD::VCGEU; break; + } + + // Detect VTST (Vector Test Bits) = vicmp ne (and (op0, op1), zero). + if (Opc == ARMISD::VCEQ) { + + SDValue AndOp; + if (ISD::isBuildVectorAllZeros(Op1.getNode())) + AndOp = Op0; + else if (ISD::isBuildVectorAllZeros(Op0.getNode())) + AndOp = Op1; + + // Ignore bitconvert. + if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT) + AndOp = AndOp.getOperand(0); + + if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { + Opc = ARMISD::VTST; + Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0)); + Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1)); + Invert = !Invert; + } + } + } + + if (Swap) + std::swap(Op0, Op1); + + SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); + + if (Invert) + Result = DAG.getNOT(dl, Result, VT); + + return Result; +} + +/// isVMOVSplat - Check if the specified splat value corresponds to an immediate +/// VMOV instruction, and if so, return the constant being splatted. +static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef, + unsigned SplatBitSize, SelectionDAG &DAG) { + switch (SplatBitSize) { + case 8: + // Any 1-byte value is OK. + assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); + return DAG.getTargetConstant(SplatBits, MVT::i8); + + case 16: + // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. + if ((SplatBits & ~0xff) == 0 || + (SplatBits & ~0xff00) == 0) + return DAG.getTargetConstant(SplatBits, MVT::i16); + break; + + case 32: + // NEON's 32-bit VMOV supports splat values where: + // * only one byte is nonzero, or + // * the least significant byte is 0xff and the second byte is nonzero, or + // * the least significant 2 bytes are 0xff and the third is nonzero. + if ((SplatBits & ~0xff) == 0 || + (SplatBits & ~0xff00) == 0 || + (SplatBits & ~0xff0000) == 0 || + (SplatBits & ~0xff000000) == 0) + return DAG.getTargetConstant(SplatBits, MVT::i32); + + if ((SplatBits & ~0xffff) == 0 && + ((SplatBits | SplatUndef) & 0xff) == 0xff) + return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32); + + if ((SplatBits & ~0xffffff) == 0 && + ((SplatBits | SplatUndef) & 0xffff) == 0xffff) + return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32); + + // Note: there are a few 32-bit splat values (specifically: 00ffff00, + // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not + // VMOV.I32. A (very) minor optimization would be to replicate the value + // and fall through here to test for a valid 64-bit splat. But, then the + // caller would also need to check and handle the change in size. + break; + + case 64: { + // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. + uint64_t BitMask = 0xff; + uint64_t Val = 0; + for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { + if (((SplatBits | SplatUndef) & BitMask) == BitMask) + Val |= BitMask; + else if ((SplatBits & BitMask) != 0) + return SDValue(); + BitMask <<= 8; + } + return DAG.getTargetConstant(Val, MVT::i64); + } + + default: + assert(0 && "unexpected size for isVMOVSplat"); + break; + } + + return SDValue(); +} + +/// getVMOVImm - If this is a build_vector of constants which can be +/// formed by using a VMOV instruction of the specified element size, +/// return the constant being splatted. The ByteSize field indicates the +/// number of bytes of each element [1248]. +SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { + BuildVectorSDNode *BVN = dyn_cast(N); + APInt SplatBits, SplatUndef; + unsigned SplatBitSize; + bool HasAnyUndefs; + if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, + HasAnyUndefs, ByteSize * 8)) + return SDValue(); + + if (SplatBitSize > ByteSize * 8) + return SDValue(); + + return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(), + SplatBitSize, DAG); +} + +static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) { + // Canonicalize all-zeros and all-ones vectors. + ConstantSDNode *ConstVal = dyn_cast(Val.getNode()); + if (ConstVal->isNullValue()) + return getZeroVector(VT, DAG, dl); + if (ConstVal->isAllOnesValue()) + return getOnesVector(VT, DAG, dl); + + MVT CanonicalVT; + if (VT.is64BitVector()) { + switch (Val.getValueType().getSizeInBits()) { + case 8: CanonicalVT = MVT::v8i8; break; + case 16: CanonicalVT = MVT::v4i16; break; + case 32: CanonicalVT = MVT::v2i32; break; + case 64: CanonicalVT = MVT::v1i64; break; + default: assert(0 && "unexpected splat element type"); break; + } + } else { + assert(VT.is128BitVector() && "unknown splat vector size"); + switch (Val.getValueType().getSizeInBits()) { + case 8: CanonicalVT = MVT::v16i8; break; + case 16: CanonicalVT = MVT::v8i16; break; + case 32: CanonicalVT = MVT::v4i32; break; + case 64: CanonicalVT = MVT::v2i64; break; + default: assert(0 && "unexpected splat element type"); break; + } + } + + // Build a canonical splat for this value. + SmallVector Ops; + Ops.assign(CanonicalVT.getVectorNumElements(), Val); + SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0], + Ops.size()); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res); +} + +// If this is a case we can't handle, return null and let the default +// expansion code take care of it. +static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { + BuildVectorSDNode *BVN = dyn_cast(Op.getNode()); + assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); + DebugLoc dl = Op.getDebugLoc(); + + APInt SplatBits, SplatUndef; + unsigned SplatBitSize; + bool HasAnyUndefs; + if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { + SDValue Val = isVMOVSplat(SplatBits.getZExtValue(), + SplatUndef.getZExtValue(), SplatBitSize, DAG); + if (Val.getNode()) + return BuildSplat(Val, Op.getValueType(), DAG, dl); + } + + return SDValue(); +} + +static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { + return Op; +} + +static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { + return Op; +} + +static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { + MVT VT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); + assert((VT == MVT::i8 || VT == MVT::i16) && + "unexpected type for custom-lowering vector extract"); + SDValue Vec = Op.getOperand(0); + SDValue Lane = Op.getOperand(1); + Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); + Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT)); + return DAG.getNode(ISD::TRUNCATE, dl, VT, Op); +} + +static SDValue LowerCONCAT_VECTORS(SDValue Op) { + if (Op.getValueType().is128BitVector() && Op.getNumOperands() == 2) + return Op; + return SDValue(); +} + SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Don't know how to custom lower this!"); abort(); @@ -1695,8 +2276,15 @@ case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG); + case ISD::SHL: case ISD::SRL: - case ISD::SRA: return ExpandSRx(Op.getNode(), DAG,Subtarget); + case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); + case ISD::VSETCC: return LowerVSETCC(Op, DAG); + case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); + case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); + case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); + case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); + case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op); } return SDValue(); } @@ -1715,7 +2303,7 @@ return; case ISD::SRL: case ISD::SRA: { - SDValue Res = ExpandSRx(N, DAG, Subtarget); + SDValue Res = LowerShift(N, DAG, Subtarget); if (Res.getNode()) Results.push_back(Res); return; @@ -1900,6 +2488,294 @@ return SDValue(); } +/// getVShiftImm - Check if this is a valid build_vector for the immediate +/// operand of a vector shift operation, where all the elements of the +/// build_vector must have the same constant integer value. +static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { + // Ignore bit_converts. + while (Op.getOpcode() == ISD::BIT_CONVERT) + Op = Op.getOperand(0); + BuildVectorSDNode *BVN = dyn_cast(Op.getNode()); + APInt SplatBits, SplatUndef; + unsigned SplatBitSize; + bool HasAnyUndefs; + if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, + HasAnyUndefs, ElementBits) || + SplatBitSize > ElementBits) + return false; + Cnt = SplatBits.getSExtValue(); + return true; +} + +/// isVShiftLImm - Check if this is a valid build_vector for the immediate +/// operand of a vector shift left operation. That value must be in the range: +/// 0 <= Value < ElementBits for a left shift; or +/// 0 <= Value <= ElementBits for a long left shift. +static bool isVShiftLImm(SDValue Op, MVT VT, bool isLong, int64_t &Cnt) { + assert(VT.isVector() && "vector shift count is not a vector type"); + unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); + if (! getVShiftImm(Op, ElementBits, Cnt)) + return false; + return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits); +} + +/// isVShiftRImm - Check if this is a valid build_vector for the immediate +/// operand of a vector shift right operation. For a shift opcode, the value +/// is positive, but for an intrinsic the value count must be negative. The +/// absolute value must be in the range: +/// 1 <= |Value| <= ElementBits for a right shift; or +/// 1 <= |Value| <= ElementBits/2 for a narrow right shift. +static bool isVShiftRImm(SDValue Op, MVT VT, bool isNarrow, bool isIntrinsic, + int64_t &Cnt) { + assert(VT.isVector() && "vector shift count is not a vector type"); + unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); + if (! getVShiftImm(Op, ElementBits, Cnt)) + return false; + if (isIntrinsic) + Cnt = -Cnt; + return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits)); +} + +/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. +static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { + unsigned IntNo = cast(N->getOperand(0))->getZExtValue(); + switch (IntNo) { + default: + // Don't do anything for most intrinsics. + break; + + // Vector shifts: check for immediate versions and lower them. + // Note: This is done during DAG combining instead of DAG legalizing because + // the build_vectors for 64-bit vector element shift counts are generally + // not legal, and it is hard to see their values after they get legalized to + // loads from a constant pool. + case Intrinsic::arm_neon_vshifts: + case Intrinsic::arm_neon_vshiftu: + case Intrinsic::arm_neon_vshiftls: + case Intrinsic::arm_neon_vshiftlu: + case Intrinsic::arm_neon_vshiftn: + case Intrinsic::arm_neon_vrshifts: + case Intrinsic::arm_neon_vrshiftu: + case Intrinsic::arm_neon_vrshiftn: + case Intrinsic::arm_neon_vqshifts: + case Intrinsic::arm_neon_vqshiftu: + case Intrinsic::arm_neon_vqshiftsu: + case Intrinsic::arm_neon_vqshiftns: + case Intrinsic::arm_neon_vqshiftnu: + case Intrinsic::arm_neon_vqshiftnsu: + case Intrinsic::arm_neon_vqrshiftns: + case Intrinsic::arm_neon_vqrshiftnu: + case Intrinsic::arm_neon_vqrshiftnsu: { + MVT VT = N->getOperand(1).getValueType(); + int64_t Cnt; + unsigned VShiftOpc = 0; + + switch (IntNo) { + case Intrinsic::arm_neon_vshifts: + case Intrinsic::arm_neon_vshiftu: + if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { + VShiftOpc = ARMISD::VSHL; + break; + } + if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { + VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ? + ARMISD::VSHRs : ARMISD::VSHRu); + break; + } + return SDValue(); + + case Intrinsic::arm_neon_vshiftls: + case Intrinsic::arm_neon_vshiftlu: + if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) + break; + assert(0 && "invalid shift count for vshll intrinsic"); + abort(); + + case Intrinsic::arm_neon_vrshifts: + case Intrinsic::arm_neon_vrshiftu: + if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) + break; + return SDValue(); + + case Intrinsic::arm_neon_vqshifts: + case Intrinsic::arm_neon_vqshiftu: + if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) + break; + return SDValue(); + + case Intrinsic::arm_neon_vqshiftsu: + if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) + break; + assert(0 && "invalid shift count for vqshlu intrinsic"); + abort(); + + case Intrinsic::arm_neon_vshiftn: + case Intrinsic::arm_neon_vrshiftn: + case Intrinsic::arm_neon_vqshiftns: + case Intrinsic::arm_neon_vqshiftnu: + case Intrinsic::arm_neon_vqshiftnsu: + case Intrinsic::arm_neon_vqrshiftns: + case Intrinsic::arm_neon_vqrshiftnu: + case Intrinsic::arm_neon_vqrshiftnsu: + // Narrowing shifts require an immediate right shift. + if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) + break; + assert(0 && "invalid shift count for narrowing vector shift intrinsic"); + abort(); + + default: + assert(0 && "unhandled vector shift"); + } + + switch (IntNo) { + case Intrinsic::arm_neon_vshifts: + case Intrinsic::arm_neon_vshiftu: + // Opcode already set above. + break; + case Intrinsic::arm_neon_vshiftls: + case Intrinsic::arm_neon_vshiftlu: + if (Cnt == VT.getVectorElementType().getSizeInBits()) + VShiftOpc = ARMISD::VSHLLi; + else + VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ? + ARMISD::VSHLLs : ARMISD::VSHLLu); + break; + case Intrinsic::arm_neon_vshiftn: + VShiftOpc = ARMISD::VSHRN; break; + case Intrinsic::arm_neon_vrshifts: + VShiftOpc = ARMISD::VRSHRs; break; + case Intrinsic::arm_neon_vrshiftu: + VShiftOpc = ARMISD::VRSHRu; break; + case Intrinsic::arm_neon_vrshiftn: + VShiftOpc = ARMISD::VRSHRN; break; + case Intrinsic::arm_neon_vqshifts: + VShiftOpc = ARMISD::VQSHLs; break; + case Intrinsic::arm_neon_vqshiftu: + VShiftOpc = ARMISD::VQSHLu; break; + case Intrinsic::arm_neon_vqshiftsu: + VShiftOpc = ARMISD::VQSHLsu; break; + case Intrinsic::arm_neon_vqshiftns: + VShiftOpc = ARMISD::VQSHRNs; break; + case Intrinsic::arm_neon_vqshiftnu: + VShiftOpc = ARMISD::VQSHRNu; break; + case Intrinsic::arm_neon_vqshiftnsu: + VShiftOpc = ARMISD::VQSHRNsu; break; + case Intrinsic::arm_neon_vqrshiftns: + VShiftOpc = ARMISD::VQRSHRNs; break; + case Intrinsic::arm_neon_vqrshiftnu: + VShiftOpc = ARMISD::VQRSHRNu; break; + case Intrinsic::arm_neon_vqrshiftnsu: + VShiftOpc = ARMISD::VQRSHRNsu; break; + } + + return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), + N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); + } + + case Intrinsic::arm_neon_vshiftins: { + MVT VT = N->getOperand(1).getValueType(); + int64_t Cnt; + unsigned VShiftOpc = 0; + + if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) + VShiftOpc = ARMISD::VSLI; + else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) + VShiftOpc = ARMISD::VSRI; + else { + assert(0 && "invalid shift count for vsli/vsri intrinsic"); + abort(); + } + + return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), + N->getOperand(1), N->getOperand(2), + DAG.getConstant(Cnt, MVT::i32)); + } + + case Intrinsic::arm_neon_vqrshifts: + case Intrinsic::arm_neon_vqrshiftu: + // No immediate versions of these to check for. + break; + } + + return SDValue(); +} + +/// PerformShiftCombine - Checks for immediate versions of vector shifts and +/// lowers them. As with the vector shift intrinsics, this is done during DAG +/// combining instead of DAG legalizing because the build_vectors for 64-bit +/// vector element shift counts are generally not legal, and it is hard to see +/// their values after they get legalized to loads from a constant pool. +static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, + const ARMSubtarget *ST) { + MVT VT = N->getValueType(0); + + // Nothing to be done for scalar shifts. + if (! VT.isVector()) + return SDValue(); + + assert(ST->hasNEON() && "unexpected vector shift"); + int64_t Cnt; + + switch (N->getOpcode()) { + default: assert(0 && "unexpected shift opcode"); + + case ISD::SHL: + if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) + return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), + DAG.getConstant(Cnt, MVT::i32)); + break; + + case ISD::SRA: + case ISD::SRL: + if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { + unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? + ARMISD::VSHRs : ARMISD::VSHRu); + return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), + DAG.getConstant(Cnt, MVT::i32)); + } + } + return SDValue(); +} + +/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, +/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. +static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, + const ARMSubtarget *ST) { + SDValue N0 = N->getOperand(0); + + // Check for sign- and zero-extensions of vector extract operations of 8- + // and 16-bit vector elements. NEON supports these directly. They are + // handled during DAG combining because type legalization will promote them + // to 32-bit types and it is messy to recognize the operations after that. + if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { + SDValue Vec = N0.getOperand(0); + SDValue Lane = N0.getOperand(1); + MVT VT = N->getValueType(0); + MVT EltVT = N0.getValueType(); + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + + if (VT == MVT::i32 && + (EltVT == MVT::i8 || EltVT == MVT::i16) && + TLI.isTypeLegal(Vec.getValueType())) { + + unsigned Opc = 0; + switch (N->getOpcode()) { + default: assert(0 && "unexpected opcode"); + case ISD::SIGN_EXTEND: + Opc = ARMISD::VGETLANEs; + break; + case ISD::ZERO_EXTEND: + case ISD::ANY_EXTEND: + Opc = ARMISD::VGETLANEu; + break; + } + return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane); + } + } + + return SDValue(); +} + SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { switch (N->getOpcode()) { @@ -1907,8 +2783,17 @@ case ISD::ADD: return PerformADDCombine(N, DCI); case ISD::SUB: return PerformSUBCombine(N, DCI); case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI); + case ISD::INTRINSIC_WO_CHAIN: + return PerformIntrinsicCombine(N, DCI.DAG); + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: + return PerformShiftCombine(N, DCI.DAG, Subtarget); + case ISD::SIGN_EXTEND: + case ISD::ZERO_EXTEND: + case ISD::ANY_EXTEND: + return PerformExtendCombine(N, DCI.DAG, Subtarget); } - return SDValue(); } Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=73919&r1=73918&r2=73919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Jun 22 18:27:02 2009 @@ -67,10 +67,65 @@ EH_SJLJ_SETJMP, // SjLj exception handling setjmp EH_SJLJ_LONGJMP, // SjLj exception handling longjmp - THREAD_POINTER + THREAD_POINTER, + + VCEQ, // Vector compare equal. + VCGE, // Vector compare greater than or equal. + VCGEU, // Vector compare unsigned greater than or equal. + VCGT, // Vector compare greater than. + VCGTU, // Vector compare unsigned greater than. + VTST, // Vector test bits. + + // Vector shift by immediate: + VSHL, // ...left + VSHRs, // ...right (signed) + VSHRu, // ...right (unsigned) + VSHLLs, // ...left long (signed) + VSHLLu, // ...left long (unsigned) + VSHLLi, // ...left long (with maximum shift count) + VSHRN, // ...right narrow + + // Vector rounding shift by immediate: + VRSHRs, // ...right (signed) + VRSHRu, // ...right (unsigned) + VRSHRN, // ...right narrow + + // Vector saturating shift by immediate: + VQSHLs, // ...left (signed) + VQSHLu, // ...left (unsigned) + VQSHLsu, // ...left (signed to unsigned) + VQSHRNs, // ...right narrow (signed) + VQSHRNu, // ...right narrow (unsigned) + VQSHRNsu, // ...right narrow (signed to unsigned) + + // Vector saturating rounding shift by immediate: + VQRSHRNs, // ...right narrow (signed) + VQRSHRNu, // ...right narrow (unsigned) + VQRSHRNsu, // ...right narrow (signed to unsigned) + + // Vector shift and insert: + VSLI, // ...left + VSRI, // ...right + + // Vector get lane (VMOV scalar to ARM core register) + // (These are used for 8- and 16-bit element types only.) + VGETLANEu, // zero-extend vector extract element + VGETLANEs, // sign-extend vector extract element + + // Vector duplicate lane (128-bit result only; 64-bit is a shuffle) + VDUPLANEQ // splat a lane from a 64-bit vector to a 128-bit vector }; } + /// Define some predicates that are used for node matching. + namespace ARM { + /// getVMOVImm - If this is a build_vector of constants which can be + /// formed by using a VMOV instruction of the specified element size, + /// return the constant being splatted. The ByteSize field indicates the + /// number of bytes of each element [1248]. + SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); + } + //===--------------------------------------------------------------------===// // ARMTargetLowering - ARM Implementation of the TargetLowering interface @@ -151,6 +206,21 @@ /// unsigned ARMPCLabelIndex; + void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); + void addDRTypeForNEON(MVT VT); + void addQRTypeForNEON(MVT VT); + + typedef SmallVector, 8> RegsToPassVector; + void PassF64ArgInRegs(CallSDNode *TheCall, SelectionDAG &DAG, + SDValue Chain, SDValue &Arg, + RegsToPassVector &RegsToPass, + CCValAssign &VA, CCValAssign &NextVA, + SDValue &StackPtr, + SmallVector &MemOpChains, + ISD::ArgFlagsTy Flags); + SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, + SDValue &Root, SelectionDAG &DAG, DebugLoc dl); + CCAssignFn *CCAssignFnForNode(unsigned CC, bool Return) const; SDValue LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG, const SDValue &StackPtr, const CCValAssign &VA, Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=73919&r1=73918&r2=73919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Jun 22 18:27:02 2009 @@ -49,6 +49,11 @@ def ThumbFrm : Format<23>; +def NEONFrm : Format<24>; +def NEONGetLnFrm : Format<25>; +def NEONSetLnFrm : Format<26>; +def NEONDupFrm : Format<27>; + // Misc flag for data processing instructions that indicates whether // the instruction has a Rn register operand. class UnaryDP { bit isUnaryDataProc = 1; } @@ -737,6 +742,14 @@ class TJTI pattern> : ThumbI; +// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode. +class ThumbPat : Pat { + list Predicates = [IsThumb]; +} + +class ThumbV5Pat : Pat { + list Predicates = [IsThumb, HasV5T]; +} //===----------------------------------------------------------------------===// @@ -857,12 +870,102 @@ //===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// +// ARM NEON Instruction templates. +// -// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode. -class ThumbPat : Pat { - list Predicates = [IsThumb]; +class NeonI pattern> + : InstARM { + let OutOperandList = oops; + let InOperandList = iops; + let AsmString = asm; + let Pattern = pattern; + list Predicates = [HasNEON]; } -class ThumbV5Pat : Pat { - list Predicates = [IsThumb, HasV5T]; +class NI pattern> + : NeonI { } + +class NDataI pattern> + : NeonI { + let Inst{31-25} = 0b1111001; +} + +// NEON "one register and a modified immediate" format. +class N1ModImm op21_19, bits<4> op11_8, bit op7, bit op6, + bit op5, bit op4, + dag oops, dag iops, string asm, string cstr, list pattern> + : NDataI { + let Inst{23} = op23; + let Inst{21-19} = op21_19; + let Inst{11-8} = op11_8; + let Inst{7} = op7; + let Inst{6} = op6; + let Inst{5} = op5; + let Inst{4} = op4; +} + +// NEON 2 vector register format. +class N2V op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, + bits<5> op11_7, bit op6, bit op4, + dag oops, dag iops, string asm, string cstr, list pattern> + : NDataI { + let Inst{24-23} = op24_23; + let Inst{21-20} = op21_20; + let Inst{19-18} = op19_18; + let Inst{17-16} = op17_16; + let Inst{11-7} = op11_7; + let Inst{6} = op6; + let Inst{4} = op4; +} + +// NEON 2 vector register with immediate. +class N2VImm op21_16, bits<4> op11_8, bit op7, + bit op6, bit op4, + dag oops, dag iops, string asm, string cstr, list pattern> + : NDataI { + let Inst{24} = op24; + let Inst{23} = op23; + let Inst{21-16} = op21_16; + let Inst{11-8} = op11_8; + let Inst{7} = op7; + let Inst{6} = op6; + let Inst{4} = op4; +} + +// NEON 3 vector register format. +class N3V op21_20, bits<4> op11_8, bit op6, bit op4, + dag oops, dag iops, string asm, string cstr, list pattern> + : NDataI { + let Inst{24} = op24; + let Inst{23} = op23; + let Inst{21-20} = op21_20; + let Inst{11-8} = op11_8; + let Inst{6} = op6; + let Inst{4} = op4; +} + +// NEON VMOVs between scalar and core registers. +class NVLaneOp opcod1, bits<4> opcod2, bits<2> opcod3, + dag oops, dag iops, Format f, string opc, string asm, + list pattern> + : AI { + let Inst{27-20} = opcod1; + let Inst{11-8} = opcod2; + let Inst{6-5} = opcod3; + let Inst{4} = 1; + list Predicates = [HasNEON]; +} +class NVGetLane opcod1, bits<4> opcod2, bits<2> opcod3, + dag oops, dag iops, string opc, string asm, list pattern> + : NVLaneOp; +class NVSetLane opcod1, bits<4> opcod2, bits<2> opcod3, + dag oops, dag iops, string opc, string asm, list pattern> + : NVLaneOp; +class NVDup opcod1, bits<4> opcod2, bits<2> opcod3, + dag oops, dag iops, string opc, string asm, list pattern> + : NVLaneOp; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=73919&r1=73918&r2=73919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Mon Jun 22 18:27:02 2009 @@ -59,6 +59,8 @@ return false; case ARM::FCPYS: case ARM::FCPYD: + case ARM::VMOVD: + case ARM::VMOVQ: SrcReg = MI.getOperand(1).getReg(); DstReg = MI.getOperand(0).getReg(); return true; @@ -528,6 +530,8 @@ else if (DestRC == ARM::DPRRegisterClass) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg) .addReg(SrcReg)); + else if (DestRC == ARM::QPRRegisterClass) + BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg); else return false; @@ -844,6 +848,10 @@ case ARM::FCPYS: case ARM::FCPYD: return true; + + case ARM::VMOVD: + case ARM::VMOVQ: + return false; // FIXME } return false; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=73919&r1=73918&r2=73919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Mon Jun 22 18:27:02 2009 @@ -114,6 +114,12 @@ // Thumb format ThumbFrm = 23 << FormShift, + // NEON format + NEONFrm = 24 << FormShift, + NEONGetLnFrm = 25 << FormShift, + NEONSetLnFrm = 26 << FormShift, + NEONDupFrm = 27 << FormShift, + //===------------------------------------------------------------------===// // Field shifts - such shifts are used to set field while generating // machine instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=73919&r1=73918&r2=73919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jun 22 18:27:02 2009 @@ -93,6 +93,10 @@ def HasV5T : Predicate<"Subtarget->hasV5TOps()">; def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">; def HasV6 : Predicate<"Subtarget->hasV6Ops()">; +def HasV7 : Predicate<"Subtarget->hasV7Ops()">; +def HasVFP2 : Predicate<"Subtarget->hasVFP2()">; +def HasVFP3 : Predicate<"Subtarget->hasVFP3()">; +def HasNEON : Predicate<"Subtarget->hasNEON()">; def IsThumb : Predicate<"Subtarget->isThumb()">; def HasThumb2 : Predicate<"Subtarget->hasThumb2()">; def IsARM : Predicate<"!Subtarget->isThumb()">; @@ -1437,3 +1441,9 @@ // include "ARMInstrVFP.td" + +//===----------------------------------------------------------------------===// +// Advanced SIMD (NEON) Support +// + +include "ARMInstrNEON.td" Added: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=73919&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (added) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Jun 22 18:27:02 2009 @@ -0,0 +1,1665 @@ +//===- ARMInstrNEON.td - NEON support for ARM -----------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the ARM NEON instruction set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// NEON-specific DAG Nodes. +//===----------------------------------------------------------------------===// + +def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>; + +def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>; +def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>; +def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>; +def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>; +def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>; +def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>; + +// Types for vector shift by immediates. The "SHX" version is for long and +// narrow operations where the source and destination vectors have different +// types. The "SHINS" version is for shift and insert operations. +def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, + SDTCisVT<2, i32>]>; +def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, + SDTCisVT<2, i32>]>; +def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, + SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; + +def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>; +def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>; +def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>; +def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>; +def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>; +def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>; +def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>; + +def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>; +def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>; +def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>; + +def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>; +def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>; +def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>; +def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>; +def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>; +def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>; + +def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>; +def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>; +def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>; + +def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>; +def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>; + +def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>]>; +def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; +def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; + +def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ", + SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>; + +//===----------------------------------------------------------------------===// +// NEON operand definitions +//===----------------------------------------------------------------------===// + +// addrmode_neonldstm := reg +// +/* TODO: Take advantage of vldm. +def addrmode_neonldstm : Operand, + ComplexPattern { + let PrintMethod = "printAddrNeonLdStMOperand"; + let MIOperandInfo = (ops GPR, i32imm); +} +*/ + +//===----------------------------------------------------------------------===// +// NEON load / store instructions +//===----------------------------------------------------------------------===// + +/* TODO: Take advantage of vldm. +let mayLoad = 1 in { +def VLDMD : NI<(outs), + (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), + "vldm${addr:submode} ${addr:base}, $dst1", + []>; + +def VLDMS : NI<(outs), + (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), + "vldm${addr:submode} ${addr:base}, $dst1", + []>; +} +*/ + +// Use vldmia to load a Q register as a D register pair. +def VLDRQ : NI<(outs QPR:$dst), (ins GPR:$addr), + "vldmia $addr, ${dst:dregpair}", + [(set QPR:$dst, (v2f64 (load GPR:$addr)))]>; + +// Use vstmia to store a Q register as a D register pair. +def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr), + "vstmia $addr, ${src:dregpair}", + [(store (v2f64 QPR:$src), GPR:$addr)]>; + + +//===----------------------------------------------------------------------===// +// NEON pattern fragments +//===----------------------------------------------------------------------===// + +// Extract D sub-registers of Q registers. +// (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6) +def SubReg_i8_reg : SDNodeXFormgetTargetConstant(5 + N->getZExtValue() / 8, MVT::i32); +}]>; +def SubReg_i16_reg : SDNodeXFormgetTargetConstant(5 + N->getZExtValue() / 4, MVT::i32); +}]>; +def SubReg_i32_reg : SDNodeXFormgetTargetConstant(5 + N->getZExtValue() / 2, MVT::i32); +}]>; +def SubReg_f64_reg : SDNodeXFormgetTargetConstant(5 + N->getZExtValue(), MVT::i32); +}]>; + +// Translate lane numbers from Q registers to D subregs. +def SubReg_i8_lane : SDNodeXFormgetTargetConstant(N->getZExtValue() & 7, MVT::i32); +}]>; +def SubReg_i16_lane : SDNodeXFormgetTargetConstant(N->getZExtValue() & 3, MVT::i32); +}]>; +def SubReg_i32_lane : SDNodeXFormgetTargetConstant(N->getZExtValue() & 1, MVT::i32); +}]>; + +//===----------------------------------------------------------------------===// +// Instruction Classes +//===----------------------------------------------------------------------===// + +// Basic 2-register operations, both double- and quad-register. +class N2VD op24_23, bits<2> op21_20, bits<2> op19_18, + bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, + ValueType ResTy, ValueType OpTy, SDNode OpNode> + : N2V; +class N2VQ op24_23, bits<2> op21_20, bits<2> op19_18, + bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, + ValueType ResTy, ValueType OpTy, SDNode OpNode> + : N2V; + +// Basic 2-register intrinsics, both double- and quad-register. +class N2VDInt op24_23, bits<2> op21_20, bits<2> op19_18, + bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, + ValueType ResTy, ValueType OpTy, Intrinsic IntOp> + : N2V; +class N2VQInt op24_23, bits<2> op21_20, bits<2> op19_18, + bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, + ValueType ResTy, ValueType OpTy, Intrinsic IntOp> + : N2V; + +// Narrow 2-register intrinsics. +class N2VNInt op24_23, bits<2> op21_20, bits<2> op19_18, + bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, + string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp> + : N2V; + +// Long 2-register intrinsics. (This is currently only used for VMOVL and is +// derived from N2VImm instead of N2V because of the way the size is encoded.) +class N2VLInt op21_16, bits<4> op11_8, bit op7, + bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD, + Intrinsic IntOp> + : N2VImm; + +// Basic 3-register operations, both double- and quad-register. +class N3VD op21_20, bits<4> op11_8, bit op4, + string OpcodeStr, ValueType ResTy, ValueType OpTy, + SDNode OpNode, bit Commutable> + : N3V { + let isCommutable = Commutable; +} +class N3VQ op21_20, bits<4> op11_8, bit op4, + string OpcodeStr, ValueType ResTy, ValueType OpTy, + SDNode OpNode, bit Commutable> + : N3V { + let isCommutable = Commutable; +} + +// Basic 3-register intrinsics, both double- and quad-register. +class N3VDInt op21_20, bits<4> op11_8, bit op4, + string OpcodeStr, ValueType ResTy, ValueType OpTy, + Intrinsic IntOp, bit Commutable> + : N3V { + let isCommutable = Commutable; +} +class N3VQInt op21_20, bits<4> op11_8, bit op4, + string OpcodeStr, ValueType ResTy, ValueType OpTy, + Intrinsic IntOp, bit Commutable> + : N3V { + let isCommutable = Commutable; +} + +// Multiply-Add/Sub operations, both double- and quad-register. +class N3VDMulOp op21_20, bits<4> op11_8, bit op4, + string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode> + : N3V; +class N3VQMulOp op21_20, bits<4> op11_8, bit op4, + string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode> + : N3V; + +// Neon 3-argument intrinsics, both double- and quad-register. +// The destination register is also used as the first source operand register. +class N3VDInt3 op21_20, bits<4> op11_8, bit op4, + string OpcodeStr, ValueType ResTy, ValueType OpTy, + Intrinsic IntOp> + : N3V; +class N3VQInt3 op21_20, bits<4> op11_8, bit op4, + string OpcodeStr, ValueType ResTy, ValueType OpTy, + Intrinsic IntOp> + : N3V; + +// Neon Long 3-argument intrinsic. The destination register is +// a quad-register and is also used as the first source operand register. +class N3VLInt3 op21_20, bits<4> op11_8, bit op4, + string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp> + : N3V; + +// Narrowing 3-register intrinsics. +class N3VNInt op21_20, bits<4> op11_8, bit op4, + string OpcodeStr, ValueType TyD, ValueType TyQ, + Intrinsic IntOp, bit Commutable> + : N3V { + let isCommutable = Commutable; +} + +// Long 3-register intrinsics. +class N3VLInt op21_20, bits<4> op11_8, bit op4, + string OpcodeStr, ValueType TyQ, ValueType TyD, + Intrinsic IntOp, bit Commutable> + : N3V { + let isCommutable = Commutable; +} + +// Wide 3-register intrinsics. +class N3VWInt op21_20, bits<4> op11_8, bit op4, + string OpcodeStr, ValueType TyQ, ValueType TyD, + Intrinsic IntOp, bit Commutable> + : N3V { + let isCommutable = Commutable; +} + +// Pairwise long 2-register intrinsics, both double- and quad-register. +class N2VDPLInt op24_23, bits<2> op21_20, bits<2> op19_18, + bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, + ValueType ResTy, ValueType OpTy, Intrinsic IntOp> + : N2V; +class N2VQPLInt op24_23, bits<2> op21_20, bits<2> op19_18, + bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, + ValueType ResTy, ValueType OpTy, Intrinsic IntOp> + : N2V; + +// Pairwise long 2-register accumulate intrinsics, +// both double- and quad-register. +// The destination register is also used as the first source operand register. +class N2VDPLInt2 op24_23, bits<2> op21_20, bits<2> op19_18, + bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, + ValueType ResTy, ValueType OpTy, Intrinsic IntOp> + : N2V; +class N2VQPLInt2 op24_23, bits<2> op21_20, bits<2> op19_18, + bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, + ValueType ResTy, ValueType OpTy, Intrinsic IntOp> + : N2V; + +// Shift by immediate, +// both double- and quad-register. +class N2VDSh op21_16, bits<4> op11_8, bit op7, + bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode> + : N2VImm; +class N2VQSh op21_16, bits<4> op11_8, bit op7, + bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode> + : N2VImm; + +// Long shift by immediate. +class N2VLSh op21_16, bits<4> op11_8, bit op7, + bit op6, bit op4, string OpcodeStr, ValueType ResTy, + ValueType OpTy, SDNode OpNode> + : N2VImm; + +// Narrow shift by immediate. +class N2VNSh op21_16, bits<4> op11_8, bit op7, + bit op6, bit op4, string OpcodeStr, ValueType ResTy, + ValueType OpTy, SDNode OpNode> + : N2VImm; + +// Shift right by immediate and accumulate, +// both double- and quad-register. +class N2VDShAdd op21_16, bits<4> op11_8, bit op7, + bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> + : N2VImm; +class N2VQShAdd op21_16, bits<4> op11_8, bit op7, + bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> + : N2VImm; + +// Shift by immediate and insert, +// both double- and quad-register. +class N2VDShIns op21_16, bits<4> op11_8, bit op7, + bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> + : N2VImm; +class N2VQShIns op21_16, bits<4> op11_8, bit op7, + bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> + : N2VImm; + +// Convert, with fractional bits immediate, +// both double- and quad-register. +class N2VCvtD op21_16, bits<4> op11_8, bit op7, + bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy, + Intrinsic IntOp> + : N2VImm; +class N2VCvtQ op21_16, bits<4> op11_8, bit op7, + bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy, + Intrinsic IntOp> + : N2VImm; + +//===----------------------------------------------------------------------===// +// Multiclasses +//===----------------------------------------------------------------------===// + +// Neon 3-register vector operations. + +// First with only element sizes of 8, 16 and 32 bits: +multiclass N3V_QHS op11_8, bit op4, + string OpcodeStr, SDNode OpNode, bit Commutable = 0> { + // 64-bit vector types. + def v8i8 : N3VD; + def v4i16 : N3VD; + def v2i32 : N3VD; + + // 128-bit vector types. + def v16i8 : N3VQ; + def v8i16 : N3VQ; + def v4i32 : N3VQ; +} + +// ....then also with element size 64 bits: +multiclass N3V_QHSD op11_8, bit op4, + string OpcodeStr, SDNode OpNode, bit Commutable = 0> + : N3V_QHS { + def v1i64 : N3VD; + def v2i64 : N3VQ; +} + + +// Neon Narrowing 2-register vector intrinsics, +// source operand element sizes of 16, 32 and 64 bits: +multiclass N2VNInt_HSD op24_23, bits<2> op21_20, bits<2> op17_16, + bits<5> op11_7, bit op6, bit op4, string OpcodeStr, + Intrinsic IntOp> { + def v8i8 : N2VNInt; + def v4i16 : N2VNInt; + def v2i32 : N2VNInt; +} + + +// Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL). +// source operand element sizes of 16, 32 and 64 bits: +multiclass N2VLInt_QHS op11_8, bit op7, bit op6, + bit op4, string OpcodeStr, Intrinsic IntOp> { + def v8i16 : N2VLInt; + def v4i32 : N2VLInt; + def v2i64 : N2VLInt; +} + + +// Neon 3-register vector intrinsics. + +// First with only element sizes of 16 and 32 bits: +multiclass N3VInt_HS op11_8, bit op4, + string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { + // 64-bit vector types. + def v4i16 : N3VDInt; + def v2i32 : N3VDInt; + + // 128-bit vector types. + def v8i16 : N3VQInt; + def v4i32 : N3VQInt; +} + +// ....then also with element size of 8 bits: +multiclass N3VInt_QHS op11_8, bit op4, + string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> + : N3VInt_HS { + def v8i8 : N3VDInt; + def v16i8 : N3VQInt; +} + +// ....then also with element size of 64 bits: +multiclass N3VInt_QHSD op11_8, bit op4, + string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> + : N3VInt_QHS { + def v1i64 : N3VDInt; + def v2i64 : N3VQInt; +} + + +// Neon Narrowing 3-register vector intrinsics, +// source operand element sizes of 16, 32 and 64 bits: +multiclass N3VNInt_HSD op11_8, bit op4, + string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { + def v8i8 : N3VNInt; + def v4i16 : N3VNInt; + def v2i32 : N3VNInt; +} + + +// Neon Long 3-register vector intrinsics. + +// First with only element sizes of 16 and 32 bits: +multiclass N3VLInt_HS op11_8, bit op4, + string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { + def v4i32 : N3VLInt; + def v2i64 : N3VLInt; +} + +// ....then also with element size of 8 bits: +multiclass N3VLInt_QHS op11_8, bit op4, + string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> + : N3VLInt_HS { + def v8i16 : N3VLInt; +} + + +// Neon Wide 3-register vector intrinsics, +// source operand element sizes of 8, 16 and 32 bits: +multiclass N3VWInt_QHS op11_8, bit op4, + string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { + def v8i16 : N3VWInt; + def v4i32 : N3VWInt; + def v2i64 : N3VWInt; +} + + +// Neon Multiply-Op vector operations, +// element sizes of 8, 16 and 32 bits: +multiclass N3VMulOp_QHS op11_8, bit op4, + string OpcodeStr, SDNode OpNode> { + // 64-bit vector types. + def v8i8 : N3VDMulOp; + def v4i16 : N3VDMulOp; + def v2i32 : N3VDMulOp; + + // 128-bit vector types. + def v16i8 : N3VQMulOp; + def v8i16 : N3VQMulOp; + def v4i32 : N3VQMulOp; +} + + +// Neon 3-argument intrinsics, +// element sizes of 8, 16 and 32 bits: +multiclass N3VInt3_QHS op11_8, bit op4, + string OpcodeStr, Intrinsic IntOp> { + // 64-bit vector types. + def v8i8 : N3VDInt3; + def v4i16 : N3VDInt3; + def v2i32 : N3VDInt3; + + // 128-bit vector types. + def v16i8 : N3VQInt3; + def v8i16 : N3VQInt3; + def v4i32 : N3VQInt3; +} + + +// Neon Long 3-argument intrinsics. + +// First with only element sizes of 16 and 32 bits: +multiclass N3VLInt3_HS op11_8, bit op4, + string OpcodeStr, Intrinsic IntOp> { + def v4i32 : N3VLInt3; + def v2i64 : N3VLInt3; +} + +// ....then also with element size of 8 bits: +multiclass N3VLInt3_QHS op11_8, bit op4, + string OpcodeStr, Intrinsic IntOp> + : N3VLInt3_HS { + def v8i16 : N3VLInt3; +} + + +// Neon 2-register vector intrinsics, +// element sizes of 8, 16 and 32 bits: +multiclass N2VInt_QHS op24_23, bits<2> op21_20, bits<2> op17_16, + bits<5> op11_7, bit op4, string OpcodeStr, + Intrinsic IntOp> { + // 64-bit vector types. + def v8i8 : N2VDInt; + def v4i16 : N2VDInt; + def v2i32 : N2VDInt; + + // 128-bit vector types. + def v16i8 : N2VQInt; + def v8i16 : N2VQInt; + def v4i32 : N2VQInt; +} + + +// Neon Pairwise long 2-register intrinsics, +// element sizes of 8, 16 and 32 bits: +multiclass N2VPLInt_QHS op24_23, bits<2> op21_20, bits<2> op17_16, + bits<5> op11_7, bit op4, + string OpcodeStr, Intrinsic IntOp> { + // 64-bit vector types. + def v8i8 : N2VDPLInt; + def v4i16 : N2VDPLInt; + def v2i32 : N2VDPLInt; + + // 128-bit vector types. + def v16i8 : N2VQPLInt; + def v8i16 : N2VQPLInt; + def v4i32 : N2VQPLInt; +} + + +// Neon Pairwise long 2-register accumulate intrinsics, +// element sizes of 8, 16 and 32 bits: +multiclass N2VPLInt2_QHS op24_23, bits<2> op21_20, bits<2> op17_16, + bits<5> op11_7, bit op4, + string OpcodeStr, Intrinsic IntOp> { + // 64-bit vector types. + def v8i8 : N2VDPLInt2; + def v4i16 : N2VDPLInt2; + def v2i32 : N2VDPLInt2; + + // 128-bit vector types. + def v16i8 : N2VQPLInt2; + def v8i16 : N2VQPLInt2; + def v4i32 : N2VQPLInt2; +} + + +// Neon 2-register vector shift by immediate, +// element sizes of 8, 16, 32 and 64 bits: +multiclass N2VSh_QHSD op11_8, bit op4, + string OpcodeStr, SDNode OpNode> { + // 64-bit vector types. + def v8i8 : N2VDSh; + def v4i16 : N2VDSh; + def v2i32 : N2VDSh; + def v1i64 : N2VDSh; + + // 128-bit vector types. + def v16i8 : N2VQSh; + def v8i16 : N2VQSh; + def v4i32 : N2VQSh; + def v2i64 : N2VQSh; +} + + +// Neon Shift-Accumulate vector operations, +// element sizes of 8, 16, 32 and 64 bits: +multiclass N2VShAdd_QHSD op11_8, bit op4, + string OpcodeStr, SDNode ShOp> { + // 64-bit vector types. + def v8i8 : N2VDShAdd; + def v4i16 : N2VDShAdd; + def v2i32 : N2VDShAdd; + def v1i64 : N2VDShAdd; + + // 128-bit vector types. + def v16i8 : N2VQShAdd; + def v8i16 : N2VQShAdd; + def v4i32 : N2VQShAdd; + def v2i64 : N2VQShAdd; +} + + +// Neon Shift-Insert vector operations, +// element sizes of 8, 16, 32 and 64 bits: +multiclass N2VShIns_QHSD op11_8, bit op4, + string OpcodeStr, SDNode ShOp> { + // 64-bit vector types. + def v8i8 : N2VDShIns; + def v4i16 : N2VDShIns; + def v2i32 : N2VDShIns; + def v1i64 : N2VDShIns; + + // 128-bit vector types. + def v16i8 : N2VQShIns; + def v8i16 : N2VQShIns; + def v4i32 : N2VQShIns; + def v2i64 : N2VQShIns; +} + +//===----------------------------------------------------------------------===// +// Instruction Definitions. +//===----------------------------------------------------------------------===// + +// Vector Add Operations. + +// VADD : Vector Add (integer and floating-point) +defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>; +def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>; +def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>; +// VADDL : Vector Add Long (Q = D + D) +defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>; +defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>; +// VADDW : Vector Add Wide (Q = Q + D) +defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>; +defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>; +// VHADD : Vector Halving Add +defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>; +defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>; +// VRHADD : Vector Rounding Halving Add +defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>; +defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>; +// VQADD : Vector Saturating Add +defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>; +defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>; +// VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q) +defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>; +// VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q) +defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>; + +// Vector Multiply Operations. + +// VMUL : Vector Multiply (integer, polynomial and floating-point) +defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>; +def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8, + int_arm_neon_vmulp, 1>; +def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8, + int_arm_neon_vmulp, 1>; +def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>; +def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>; +// VQDMULH : Vector Saturating Doubling Multiply Returning High Half +defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>; +// VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half +defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>; +// VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D) +defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>; +defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>; +def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8, + int_arm_neon_vmullp, 1>; +// VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D) +defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>; + +// Vector Multiply-Accumulate and Multiply-Subtract Operations. + +// VMLA : Vector Multiply Accumulate (integer and floating-point) +defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>; +def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>; +def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>; +// VMLAL : Vector Multiply Accumulate Long (Q += D * D) +defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>; +defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>; +// VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D) +defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>; +// VMLS : Vector Multiply Subtract (integer and floating-point) +defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>; +def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>; +def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>; +// VMLSL : Vector Multiply Subtract Long (Q -= D * D) +defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>; +defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>; +// VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D) +defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>; + +// Vector Subtract Operations. + +// VSUB : Vector Subtract (integer and floating-point) +defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>; +def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>; +def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>; +// VSUBL : Vector Subtract Long (Q = D - D) +defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>; +defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>; +// VSUBW : Vector Subtract Wide (Q = Q - D) +defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>; +defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>; +// VHSUB : Vector Halving Subtract +defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>; +defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>; +// VQSUB : Vector Saturing Subtract +defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>; +defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>; +// VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q) +defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>; +// VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q) +defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>; + +// Vector Comparisons. + +// VCEQ : Vector Compare Equal +defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>; +def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>; +def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>; +// VCGE : Vector Compare Greater Than or Equal +defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>; +defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>; +def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>; +def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>; +// VCGT : Vector Compare Greater Than +defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>; +defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>; +def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>; +def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>; +// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE) +def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32, + int_arm_neon_vacged, 0>; +def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32, + int_arm_neon_vacgeq, 0>; +// VACGT : Vector Absolute Compare Greater Than (aka VCAGT) +def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32, + int_arm_neon_vacgtd, 0>; +def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32, + int_arm_neon_vacgtq, 0>; +// VTST : Vector Test Bits +defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>; + +// Vector Bitwise Operations. + +// VAND : Vector Bitwise AND +def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>; +def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>; + +// VEOR : Vector Bitwise Exclusive OR +def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>; +def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>; + +// VORR : Vector Bitwise OR +def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>; +def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>; + +// VBIC : Vector Bitwise Bit Clear (AND NOT) +def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), + (ins DPR:$src1, DPR:$src2), "vbic\t$dst, $src1, $src2", "", + [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>; +def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), + (ins QPR:$src1, QPR:$src2), "vbic\t$dst, $src1, $src2", "", + [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>; + +// VORN : Vector Bitwise OR NOT +def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst), + (ins DPR:$src1, DPR:$src2), "vorn\t$dst, $src1, $src2", "", + [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>; +def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst), + (ins QPR:$src1, QPR:$src2), "vorn\t$dst, $src1, $src2", "", + [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>; + +// VMVN : Vector Bitwise NOT +def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0, + (outs DPR:$dst), (ins DPR:$src), "vmvn\t$dst, $src", "", + [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>; +def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0, + (outs QPR:$dst), (ins QPR:$src), "vmvn\t$dst, $src", "", + [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>; +def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>; +def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>; + +// VBSL : Vector Bitwise Select +def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), + (ins DPR:$src1, DPR:$src2, DPR:$src3), + "vbsl\t$dst, $src2, $src3", "$src1 = $dst", + [(set DPR:$dst, + (v2i32 (or (and DPR:$src2, DPR:$src1), + (and DPR:$src3, (vnot DPR:$src1)))))]>; +def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), + (ins QPR:$src1, QPR:$src2, QPR:$src3), + "vbsl\t$dst, $src2, $src3", "$src1 = $dst", + [(set QPR:$dst, + (v4i32 (or (and QPR:$src2, QPR:$src1), + (and QPR:$src3, (vnot QPR:$src1)))))]>; + +// VBIF : Vector Bitwise Insert if False +// like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst", +// VBIT : Vector Bitwise Insert if True +// like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst", +// These are not yet implemented. The TwoAddress pass will not go looking +// for equivalent operations with different register constraints; it just +// inserts copies. + +// Vector Absolute Differences. + +// VABD : Vector Absolute Difference +defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>; +defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>; +def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32, + int_arm_neon_vabdf, 0>; +def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32, + int_arm_neon_vabdf, 0>; + +// VABDL : Vector Absolute Difference Long (Q = | D - D |) +defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>; +defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>; + +// VABA : Vector Absolute Difference and Accumulate +defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>; +defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>; + +// VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |) +defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>; +defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>; + +// Vector Maximum and Minimum. + +// VMAX : Vector Maximum +defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>; +defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>; +def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32, + int_arm_neon_vmaxf, 1>; +def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32, + int_arm_neon_vmaxf, 1>; + +// VMIN : Vector Minimum +defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>; +defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>; +def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32, + int_arm_neon_vminf, 1>; +def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32, + int_arm_neon_vminf, 1>; + +// Vector Pairwise Operations. + +// VPADD : Vector Pairwise Add +def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8, + int_arm_neon_vpaddi, 0>; +def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16, + int_arm_neon_vpaddi, 0>; +def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32, + int_arm_neon_vpaddi, 0>; +def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32, + int_arm_neon_vpaddf, 0>; + +// VPADDL : Vector Pairwise Add Long +defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s", + int_arm_neon_vpaddls>; +defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u", + int_arm_neon_vpaddlu>; + +// VPADAL : Vector Pairwise Add and Accumulate Long +defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s", + int_arm_neon_vpadals>; +defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u", + int_arm_neon_vpadalu>; + +// VPMAX : Vector Pairwise Maximum +def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8, + int_arm_neon_vpmaxs, 0>; +def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16, + int_arm_neon_vpmaxs, 0>; +def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32, + int_arm_neon_vpmaxs, 0>; +def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8, + int_arm_neon_vpmaxu, 0>; +def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16, + int_arm_neon_vpmaxu, 0>; +def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32, + int_arm_neon_vpmaxu, 0>; +def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32, + int_arm_neon_vpmaxf, 0>; + +// VPMIN : Vector Pairwise Minimum +def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8, + int_arm_neon_vpmins, 0>; +def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16, + int_arm_neon_vpmins, 0>; +def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32, + int_arm_neon_vpmins, 0>; +def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8, + int_arm_neon_vpminu, 0>; +def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16, + int_arm_neon_vpminu, 0>; +def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32, + int_arm_neon_vpminu, 0>; +def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32, + int_arm_neon_vpminf, 0>; + +// Vector Reciprocal and Reciprocal Square Root Estimate and Step. + +// VRECPE : Vector Reciprocal Estimate +def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32", + v2i32, v2i32, int_arm_neon_vrecpe>; +def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32", + v4i32, v4i32, int_arm_neon_vrecpe>; +def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32", + v2f32, v2f32, int_arm_neon_vrecpef>; +def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32", + v4f32, v4f32, int_arm_neon_vrecpef>; + +// VRECPS : Vector Reciprocal Step +def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32, + int_arm_neon_vrecps, 1>; +def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32, + int_arm_neon_vrecps, 1>; + +// VRSQRTE : Vector Reciprocal Square Root Estimate +def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32", + v2i32, v2i32, int_arm_neon_vrsqrte>; +def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32", + v4i32, v4i32, int_arm_neon_vrsqrte>; +def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32", + v2f32, v2f32, int_arm_neon_vrsqrtef>; +def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32", + v4f32, v4f32, int_arm_neon_vrsqrtef>; + +// VRSQRTS : Vector Reciprocal Square Root Step +def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32, + int_arm_neon_vrsqrts, 1>; +def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32, + int_arm_neon_vrsqrts, 1>; + +// Vector Shifts. + +// VSHL : Vector Shift +defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>; +defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>; +// VSHL : Vector Shift Left (Immediate) +defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>; +// VSHR : Vector Shift Right (Immediate) +defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>; +defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>; + +// VSHLL : Vector Shift Left Long +def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8", + v8i16, v8i8, NEONvshlls>; +def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16", + v4i32, v4i16, NEONvshlls>; +def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32", + v2i64, v2i32, NEONvshlls>; +def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8", + v8i16, v8i8, NEONvshllu>; +def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16", + v4i32, v4i16, NEONvshllu>; +def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32", + v2i64, v2i32, NEONvshllu>; + +// VSHLL : Vector Shift Left Long (with maximum shift count) +def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8", + v8i16, v8i8, NEONvshlli>; +def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16", + v4i32, v4i16, NEONvshlli>; +def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32", + v2i64, v2i32, NEONvshlli>; + +// VSHRN : Vector Shift Right and Narrow +def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16", + v8i8, v8i16, NEONvshrn>; +def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32", + v4i16, v4i32, NEONvshrn>; +def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64", + v2i32, v2i64, NEONvshrn>; + +// VRSHL : Vector Rounding Shift +defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>; +defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>; +// VRSHR : Vector Rounding Shift Right +defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>; +defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>; + +// VRSHRN : Vector Rounding Shift Right and Narrow +def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16", + v8i8, v8i16, NEONvrshrn>; +def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32", + v4i16, v4i32, NEONvrshrn>; +def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64", + v2i32, v2i64, NEONvrshrn>; + +// VQSHL : Vector Saturating Shift +defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>; +defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>; +// VQSHL : Vector Saturating Shift Left (Immediate) +defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>; +defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>; +// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned) +defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>; + +// VQSHRN : Vector Saturating Shift Right and Narrow +def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16", + v8i8, v8i16, NEONvqshrns>; +def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32", + v4i16, v4i32, NEONvqshrns>; +def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64", + v2i32, v2i64, NEONvqshrns>; +def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16", + v8i8, v8i16, NEONvqshrnu>; +def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32", + v4i16, v4i32, NEONvqshrnu>; +def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64", + v2i32, v2i64, NEONvqshrnu>; + +// VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned) +def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16", + v8i8, v8i16, NEONvqshrnsu>; +def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32", + v4i16, v4i32, NEONvqshrnsu>; +def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64", + v2i32, v2i64, NEONvqshrnsu>; + +// VQRSHL : Vector Saturating Rounding Shift +defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s", + int_arm_neon_vqrshifts, 0>; +defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u", + int_arm_neon_vqrshiftu, 0>; + +// VQRSHRN : Vector Saturating Rounding Shift Right and Narrow +def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16", + v8i8, v8i16, NEONvqrshrns>; +def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32", + v4i16, v4i32, NEONvqrshrns>; +def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64", + v2i32, v2i64, NEONvqrshrns>; +def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16", + v8i8, v8i16, NEONvqrshrnu>; +def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32", + v4i16, v4i32, NEONvqrshrnu>; +def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64", + v2i32, v2i64, NEONvqrshrnu>; + +// VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned) +def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16", + v8i8, v8i16, NEONvqrshrnsu>; +def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32", + v4i16, v4i32, NEONvqrshrnsu>; +def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64", + v2i32, v2i64, NEONvqrshrnsu>; + +// VSRA : Vector Shift Right and Accumulate +defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>; +defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>; +// VRSRA : Vector Rounding Shift Right and Accumulate +defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>; +defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>; + +// VSLI : Vector Shift Left and Insert +defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>; +// VSRI : Vector Shift Right and Insert +defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>; + +// Vector Absolute and Saturating Absolute. + +// VABS : Vector Absolute Value +defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s", + int_arm_neon_vabs>; +def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32", + v2f32, v2f32, int_arm_neon_vabsf>; +def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32", + v4f32, v4f32, int_arm_neon_vabsf>; + +// VQABS : Vector Saturating Absolute Value +defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s", + int_arm_neon_vqabs>; + +// Vector Negate. + +def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>; +def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>; + +class VNEGD size, string OpcodeStr, ValueType Ty> + : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src), + !strconcat(OpcodeStr, "\t$dst, $src"), "", + [(set DPR:$dst, (Ty (vneg DPR:$src)))]>; +class VNEGQ size, string OpcodeStr, ValueType Ty> + : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src), + !strconcat(OpcodeStr, "\t$dst, $src"), "", + [(set QPR:$dst, (Ty (vneg QPR:$src)))]>; + +// VNEG : Vector Negate +def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>; +def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>; +def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>; +def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>; +def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>; +def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>; + +// VNEG : Vector Negate (floating-point) +def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0, + (outs DPR:$dst), (ins DPR:$src), "vneg.f32\t$dst, $src", "", + [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>; +def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0, + (outs QPR:$dst), (ins QPR:$src), "vneg.f32\t$dst, $src", "", + [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>; + +def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>; +def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>; +def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>; +def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>; +def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>; +def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>; + +// VQNEG : Vector Saturating Negate +defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s", + int_arm_neon_vqneg>; + +// Vector Bit Counting Operations. + +// VCLS : Vector Count Leading Sign Bits +defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s", + int_arm_neon_vcls>; +// VCLZ : Vector Count Leading Zeros +defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i", + int_arm_neon_vclz>; +// VCNT : Vector Count One Bits +def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8", + v8i8, v8i8, int_arm_neon_vcnt>; +def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8", + v16i8, v16i8, int_arm_neon_vcnt>; + +// Vector Move Operations. + +// VMOV : Vector Move (Register) + +def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src), + "vmov\t$dst, $src", "", []>; +def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src), + "vmov\t$dst, $src", "", []>; + +// VMOV : Vector Move (Immediate) + +// VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm. +def VMOV_get_imm8 : SDNodeXForm; +def vmovImm8 : PatLeaf<(build_vector), [{ + return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0; +}], VMOV_get_imm8>; + +// VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm. +def VMOV_get_imm16 : SDNodeXForm; +def vmovImm16 : PatLeaf<(build_vector), [{ + return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0; +}], VMOV_get_imm16>; + +// VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm. +def VMOV_get_imm32 : SDNodeXForm; +def vmovImm32 : PatLeaf<(build_vector), [{ + return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0; +}], VMOV_get_imm32>; + +// VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm. +def VMOV_get_imm64 : SDNodeXForm; +def vmovImm64 : PatLeaf<(build_vector), [{ + return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0; +}], VMOV_get_imm64>; + +// Note: Some of the cmode bits in the following VMOV instructions need to +// be encoded based on the immed values. + +def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst), + (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "", + [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>; +def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst), + (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "", + [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>; + +def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst), + (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "", + [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>; +def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst), + (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "", + [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>; + +def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst), + (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "", + [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>; +def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst), + (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "", + [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>; + +def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst), + (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "", + [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>; +def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst), + (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "", + [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>; + +// VMOV : Vector Get Lane (move scalar to ARM core register) + +def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00, + (outs GPR:$dst), (ins DPR:$src, i32imm:$lane), + "vmov", ".s8\t$dst, $src[$lane]", + [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src), + imm:$lane))]>; +def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01, + (outs GPR:$dst), (ins DPR:$src, i32imm:$lane), + "vmov", ".s16\t$dst, $src[$lane]", + [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src), + imm:$lane))]>; +def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00, + (outs GPR:$dst), (ins DPR:$src, i32imm:$lane), + "vmov", ".u8\t$dst, $src[$lane]", + [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src), + imm:$lane))]>; +def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01, + (outs GPR:$dst), (ins DPR:$src, i32imm:$lane), + "vmov", ".u16\t$dst, $src[$lane]", + [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src), + imm:$lane))]>; +def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00, + (outs GPR:$dst), (ins DPR:$src, i32imm:$lane), + "vmov", ".32\t$dst, $src[$lane]", + [(set GPR:$dst, (extractelt (v2i32 DPR:$src), + imm:$lane))]>; +// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td +def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane), + (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src, + (SubReg_i8_reg imm:$lane))), + (SubReg_i8_lane imm:$lane))>; +def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane), + (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src, + (SubReg_i16_reg imm:$lane))), + (SubReg_i16_lane imm:$lane))>; +def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane), + (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src, + (SubReg_i8_reg imm:$lane))), + (SubReg_i8_lane imm:$lane))>; +def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane), + (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src, + (SubReg_i16_reg imm:$lane))), + (SubReg_i16_lane imm:$lane))>; +def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane), + (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src, + (SubReg_i32_reg imm:$lane))), + (SubReg_i32_lane imm:$lane))>; +//def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2), +// (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>; +def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2), + (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>; + + +// VMOV : Vector Set Lane (move ARM core register to scalar) + +let Constraints = "$src1 = $dst" in { +def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst), + (ins DPR:$src1, GPR:$src2, i32imm:$lane), + "vmov", ".8\t$dst[$lane], $src2", + [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1), + GPR:$src2, imm:$lane))]>; +def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst), + (ins DPR:$src1, GPR:$src2, i32imm:$lane), + "vmov", ".16\t$dst[$lane], $src2", + [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1), + GPR:$src2, imm:$lane))]>; +def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst), + (ins DPR:$src1, GPR:$src2, i32imm:$lane), + "vmov", ".32\t$dst[$lane], $src2", + [(set DPR:$dst, (insertelt (v2i32 DPR:$src1), + GPR:$src2, imm:$lane))]>; +} +def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane), + (v16i8 (INSERT_SUBREG QPR:$src1, + (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1, + (SubReg_i8_reg imm:$lane))), + GPR:$src2, (SubReg_i8_lane imm:$lane)), + (SubReg_i8_reg imm:$lane)))>; +def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane), + (v8i16 (INSERT_SUBREG QPR:$src1, + (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1, + (SubReg_i16_reg imm:$lane))), + GPR:$src2, (SubReg_i16_lane imm:$lane)), + (SubReg_i16_reg imm:$lane)))>; +def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane), + (v4i32 (INSERT_SUBREG QPR:$src1, + (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1, + (SubReg_i32_reg imm:$lane))), + GPR:$src2, (SubReg_i32_lane imm:$lane)), + (SubReg_i32_reg imm:$lane)))>; + +//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), +// (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>; +def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), + (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>; + +// VDUP : Vector Duplicate (from ARM core register to all elements) + +def splat_lo : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + ShuffleVectorSDNode *SVOp = cast(N); + return SVOp->isSplat() && SVOp->getSplatIndex() == 0; +}]>; + +class VDUPD opcod1, bits<2> opcod3, string asmSize, ValueType Ty> + : NVDup; +class VDUPQ opcod1, bits<2> opcod3, string asmSize, ValueType Ty> + : NVDup; + +def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>; +def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>; +def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>; +def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>; +def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>; +def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>; + +def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src), + "vdup", ".32\t$dst, $src", + [(set DPR:$dst, (v2f32 (splat_lo + (scalar_to_vector + (f32 (bitconvert GPR:$src))), + undef)))]>; +def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src), + "vdup", ".32\t$dst, $src", + [(set QPR:$dst, (v4f32 (splat_lo + (scalar_to_vector + (f32 (bitconvert GPR:$src))), + undef)))]>; + +// VDUP : Vector Duplicate Lane (from scalar to all elements) + +def SHUFFLE_get_splat_lane : SDNodeXForm(N); + return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32); +}]>; + +def splat_lane : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + ShuffleVectorSDNode *SVOp = cast(N); + return SVOp->isSplat(); +}], SHUFFLE_get_splat_lane>; + +class VDUPLND op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty> + : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0, + (outs DPR:$dst), (ins DPR:$src, i32imm:$lane), + !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", + [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>; + +// vector_shuffle requires that the source and destination types match, so +// VDUP to a 128-bit result uses a target-specific VDUPLANEQ node. +class VDUPLNQ op19_18, bits<2> op17_16, string OpcodeStr, + ValueType ResTy, ValueType OpTy> + : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0, + (outs QPR:$dst), (ins DPR:$src, i32imm:$lane), + !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", + [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>; + +def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>; +def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>; +def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>; +def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>; +def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>; +def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>; +def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>; +def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>; + +// VMOVN : Vector Narrowing Move +defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i", + int_arm_neon_vmovn>; +// VQMOVN : Vector Saturating Narrowing Move +defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s", + int_arm_neon_vqmovns>; +defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u", + int_arm_neon_vqmovnu>; +defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s", + int_arm_neon_vqmovnsu>; +// VMOVL : Vector Lengthening Move +defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>; +defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>; + +// Vector Conversions. + +// VCVT : Vector Convert Between Floating-Point and Integers +def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32", + v2i32, v2f32, fp_to_sint>; +def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32", + v2i32, v2f32, fp_to_uint>; +def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32", + v2f32, v2i32, sint_to_fp>; +def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32", + v2f32, v2i32, uint_to_fp>; + +def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32", + v4i32, v4f32, fp_to_sint>; +def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32", + v4i32, v4f32, fp_to_uint>; +def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32", + v4f32, v4i32, sint_to_fp>; +def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32", + v4f32, v4i32, uint_to_fp>; + +// VCVT : Vector Convert Between Floating-Point and Fixed-Point. +// Note: Some of the opcode bits in the following VCVT instructions need to +// be encoded based on the immed values. +def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32", + v2i32, v2f32, int_arm_neon_vcvtfp2fxs>; +def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32", + v2i32, v2f32, int_arm_neon_vcvtfp2fxu>; +def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32", + v2f32, v2i32, int_arm_neon_vcvtfxs2fp>; +def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32", + v2f32, v2i32, int_arm_neon_vcvtfxu2fp>; + +def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32", + v4i32, v4f32, int_arm_neon_vcvtfp2fxs>; +def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32", + v4i32, v4f32, int_arm_neon_vcvtfp2fxu>; +def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32", + v4f32, v4i32, int_arm_neon_vcvtfxs2fp>; +def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32", + v4f32, v4i32, int_arm_neon_vcvtfxu2fp>; + +//===----------------------------------------------------------------------===// +// Non-Instruction Patterns +//===----------------------------------------------------------------------===// + +// bit_convert +def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>; +def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>; +def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>; +def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>; +def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>; +def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>; +def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>; +def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>; +def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>; +def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>; +def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>; +def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>; +def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>; +def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>; +def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>; +def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>; +def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>; +def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>; +def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>; +def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>; +def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>; +def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>; +def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>; +def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>; +def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>; +def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>; +def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>; +def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>; +def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>; +def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>; + +def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>; +def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>; +def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>; +def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>; +def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>; +def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>; +def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>; +def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>; +def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>; +def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>; +def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>; +def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>; +def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>; +def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>; +def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>; +def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>; +def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>; +def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>; +def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>; +def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>; +def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>; +def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>; +def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>; +def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>; +def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>; +def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>; +def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>; +def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>; +def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>; +def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>; Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=73919&r1=73918&r2=73919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Mon Jun 22 18:27:02 2009 @@ -77,6 +77,34 @@ def D14 : ARMReg<14, "d14", [S28, S29]>; def D15 : ARMReg<15, "d15", [S30, S31]>; +// VFP3 defines 16 additional double registers +def D16 : ARMFReg<16, "d16">; def D17 : ARMFReg<17, "d16">; +def D18 : ARMFReg<18, "d16">; def D19 : ARMFReg<19, "d16">; +def D20 : ARMFReg<20, "d16">; def D21 : ARMFReg<21, "d16">; +def D22 : ARMFReg<22, "d16">; def D23 : ARMFReg<23, "d16">; +def D24 : ARMFReg<24, "d16">; def D25 : ARMFReg<25, "d16">; +def D26 : ARMFReg<26, "d16">; def D27 : ARMFReg<27, "d16">; +def D28 : ARMFReg<28, "d16">; def D29 : ARMFReg<29, "d16">; +def D30 : ARMFReg<30, "d16">; def D31 : ARMFReg<31, "d16">; + +// Advanced SIMD (NEON) defines 16 quad-word aliases +def Q0 : ARMReg< 0, "q0", [D0, D1]>; +def Q1 : ARMReg< 1, "q1", [D2, D3]>; +def Q2 : ARMReg< 2, "q2", [D4, D5]>; +def Q3 : ARMReg< 3, "q3", [D6, D7]>; +def Q4 : ARMReg< 4, "q4", [D8, D9]>; +def Q5 : ARMReg< 5, "q5", [D10, D11]>; +def Q6 : ARMReg< 6, "q6", [D12, D13]>; +def Q7 : ARMReg< 7, "q7", [D14, D15]>; +def Q8 : ARMReg< 8, "q8", [D16, D17]>; +def Q9 : ARMReg< 9, "q9", [D18, D19]>; +def Q10 : ARMReg<10, "q10", [D20, D21]>; +def Q11 : ARMReg<11, "q11", [D22, D23]>; +def Q12 : ARMReg<12, "q12", [D24, D25]>; +def Q13 : ARMReg<13, "q13", [D26, D27]>; +def Q14 : ARMReg<14, "q14", [D28, D29]>; +def Q15 : ARMReg<15, "q15", [D30, D31]>; + // Current Program Status Register. def CPSR : ARMReg<0, "cpsr">; @@ -207,14 +235,67 @@ }]; } +// Scalar single precision floating point register class.. def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31]>; +// Scalar double precision floating point / generic 64-bit vector register +// class. // ARM requires only word alignment for double. It's more performant if it // is double-word alignment though. -def DPR : RegisterClass<"ARM", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7, D8, - D9, D10, D11, D12, D13, D14, D15]>; +def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64, + [D0, D1, D2, D3, D4, D5, D6, D7, + D8, D9, D10, D11, D12, D13, D14, D15]> { + let SubRegClassList = [SPR, SPR]; + let MethodProtos = [{ + iterator allocation_order_begin(const MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + // VFP2 + static const unsigned ARM_DPR_VFP2[] = { + ARM::D0, ARM::D1, ARM::D2, ARM::D3, + ARM::D4, ARM::D5, ARM::D6, ARM::D7, + ARM::D8, ARM::D9, ARM::D10, ARM::D11, + ARM::D12, ARM::D13, ARM::D14, ARM::D15 }; + // VFP3 + static const unsigned ARM_DPR_VFP3[] = { + ARM::D0, ARM::D1, ARM::D2, ARM::D3, + ARM::D4, ARM::D5, ARM::D6, ARM::D7, + ARM::D8, ARM::D9, ARM::D10, ARM::D11, + ARM::D12, ARM::D13, ARM::D14, ARM::D15, + ARM::D16, ARM::D17, ARM::D18, ARM::D15, + ARM::D20, ARM::D21, ARM::D22, ARM::D23, + ARM::D24, ARM::D25, ARM::D26, ARM::D27, + ARM::D28, ARM::D29, ARM::D30, ARM::D31 }; + DPRClass::iterator + DPRClass::allocation_order_begin(const MachineFunction &MF) const { + const TargetMachine &TM = MF.getTarget(); + const ARMSubtarget &Subtarget = TM.getSubtarget(); + if (Subtarget.hasVFP3()) + return ARM_DPR_VFP3; + return ARM_DPR_VFP2; + } + + DPRClass::iterator + DPRClass::allocation_order_end(const MachineFunction &MF) const { + const TargetMachine &TM = MF.getTarget(); + const ARMSubtarget &Subtarget = TM.getSubtarget(); + if (Subtarget.hasVFP3()) + return ARM_DPR_VFP3 + (sizeof(ARM_DPR_VFP3)/sizeof(unsigned)); + else + return ARM_DPR_VFP2 + (sizeof(ARM_DPR_VFP2)/sizeof(unsigned)); + } + }]; +} + +// Generic 128-bit vector register class. +def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128, + [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, + Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15]> { + let SubRegClassList = [SPR, SPR, SPR, SPR, DPR, DPR]; +} // Condition code registers. def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>; @@ -224,12 +305,40 @@ // sub registers for each register. // -def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7, - D8, D9, D10, D11, D12, D13, D14, D15], - [S0, S2, S4, S6, S8, S10, S12, S14, +def arm_ssubreg_0 : PatLeaf<(i32 1)>; +def arm_ssubreg_1 : PatLeaf<(i32 2)>; +def arm_ssubreg_2 : PatLeaf<(i32 3)>; +def arm_ssubreg_3 : PatLeaf<(i32 4)>; +def arm_dsubreg_0 : PatLeaf<(i32 5)>; +def arm_dsubreg_1 : PatLeaf<(i32 6)>; + +// S sub-registers of D registers. +def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7, + D8, D9, D10, D11, D12, D13, D14, D15], + [S0, S2, S4, S6, S8, S10, S12, S14, S16, S18, S20, S22, S24, S26, S28, S30]>; - -def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7, - D8, D9, D10, D11, D12, D13, D14, D15], - [S1, S3, S5, S7, S9, S11, S13, S15, +def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7, + D8, D9, D10, D11, D12, D13, D14, D15], + [S1, S3, S5, S7, S9, S11, S13, S15, S17, S19, S21, S23, S25, S27, S29, S31]>; + +// S sub-registers of Q registers. +def : SubRegSet<1, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7], + [S0, S4, S8, S12, S16, S20, S24, S28]>; +def : SubRegSet<2, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7], + [S1, S5, S9, S13, S17, S21, S25, S29]>; +def : SubRegSet<3, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7], + [S2, S6, S10, S14, S18, S22, S26, S30]>; +def : SubRegSet<4, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7], + [S3, S7, S11, S15, S19, S23, S27, S31]>; + +// D sub-registers of Q registers. +def : SubRegSet<5, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, + Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15], + [D0, D2, D4, D6, D8, D10, D12, D14, + D16, D18, D20, D22, D24, D26, D28, D30]>; +def : SubRegSet<6, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, + Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15], + [D1, D3, D5, D7, D9, D11, D13, D15, + D17, D19, D21, D23, D25, D27, D29, D31]>; + Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=73919&r1=73918&r2=73919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Mon Jun 22 18:27:02 2009 @@ -285,12 +285,22 @@ const char *Modifier) { const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { - case MachineOperand::MO_Register: - if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) - O << TM.getRegisterInfo()->get(MO.getReg()).AsmName; - else + case MachineOperand::MO_Register: { + unsigned Reg = MO.getReg(); + if (TargetRegisterInfo::isPhysicalRegister(Reg)) { + if (Modifier && strcmp(Modifier, "dregpair") == 0) { + unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0 + unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1 + O << '{' + << TRI->getAsmName(DRegLo) << "-" << TRI->getAsmName(DRegHi) + << '}'; + } else { + O << TRI->getAsmName(Reg); + } + } else assert(0 && "not implemented"); break; + } case MachineOperand::MO_Immediate: { if (!Modifier || strcmp(Modifier, "no_hash") != 0) O << "#"; Modified: llvm/trunk/lib/Target/ARM/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README.txt?rev=73919&r1=73918&r2=73919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/README.txt (original) +++ llvm/trunk/lib/Target/ARM/README.txt Mon Jun 22 18:27:02 2009 @@ -552,3 +552,23 @@ //===---------------------------------------------------------------------===// +Some of the NEON intrinsics may be appropriate for more general use, either +as target-independent intrinsics or perhaps elsewhere in the ARM backend. +Some of them may also be lowered to target-independent SDNodes, and perhaps +some new SDNodes could be added. + +For example, maximum, minimum, and absolute value operations are well-defined +and standard operations, both for vector and scalar types. + +The current NEON-specific intrinsics for count leading zeros and count one +bits could perhaps be replaced by the target-independent ctlz and ctpop +intrinsics. It may also make sense to add a target-independent "ctls" +intrinsic for "count leading sign bits". Likewise, the backend could use +the target-independent SDNodes for these operations. + +ARMv6 has scalar saturating and halving adds and subtracts. The same +intrinsics could possibly be used for both NEON's vector implementations of +those operations and the ARMv6 scalar versions. + +//===---------------------------------------------------------------------===// + Added: llvm/trunk/test/CodeGen/ARM/2009-06-02-ISelCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-06-02-ISelCrash.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-06-02-ISelCrash.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2009-06-02-ISelCrash.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,62 @@ +; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6,+vfp2 + +@"\01LC" = external constant [15 x i8] ; <[15 x i8]*> [#uses=1] + +declare i32 @printf(i8* nocapture, ...) nounwind + +define i32 @main() nounwind { +entry: + br label %bb.i1.i + +bb.i1.i: ; preds = %Cos.exit.i.i, %entry + br label %bb.i.i.i + +bb.i.i.i: ; preds = %bb.i.i.i, %bb.i1.i + br i1 undef, label %Cos.exit.i.i, label %bb.i.i.i + +Cos.exit.i.i: ; preds = %bb.i.i.i + br i1 undef, label %bb2.i.i, label %bb.i1.i + +bb2.i.i: ; preds = %Cos.exit.i.i + br label %bb3.i.i + +bb3.i.i: ; preds = %bb5.i.i, %bb2.i.i + br label %bb4.i.i + +bb4.i.i: ; preds = %bb4.i.i, %bb3.i.i + br i1 undef, label %bb5.i.i, label %bb4.i.i + +bb5.i.i: ; preds = %bb4.i.i + br i1 undef, label %bb.i, label %bb3.i.i + +bb.i: ; preds = %bb.i, %bb5.i.i + br i1 undef, label %bb1.outer2.i.i.outer, label %bb.i + +bb1.outer2.i.i.outer: ; preds = %Fft.exit.i, %bb5.i12.i, %bb.i + br label %bb1.outer2.i.i + +bb1.outer2.i.i: ; preds = %bb2.i9.i, %bb1.outer2.i.i.outer + br label %bb1.i.i + +bb1.i.i: ; preds = %bb1.i.i, %bb1.outer2.i.i + br i1 undef, label %bb2.i9.i, label %bb1.i.i + +bb2.i9.i: ; preds = %bb1.i.i + br i1 undef, label %bb4.i11.i, label %bb1.outer2.i.i + +bb4.i11.i: ; preds = %bb4.i11.i, %bb2.i9.i + br i1 undef, label %bb5.i12.i, label %bb4.i11.i + +bb5.i12.i: ; preds = %bb4.i11.i + br i1 undef, label %bb7.i.i, label %bb1.outer2.i.i.outer + +bb7.i.i: ; preds = %bb7.i.i, %bb5.i12.i + br i1 undef, label %Fft.exit.i, label %bb7.i.i + +Fft.exit.i: ; preds = %bb7.i.i + br i1 undef, label %bb5.i, label %bb1.outer2.i.i.outer + +bb5.i: ; preds = %Fft.exit.i + %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([15 x i8]* @"\01LC", i32 0, i32 0), double undef, double undef) nounwind ; [#uses=0] + unreachable +} Added: llvm/trunk/test/CodeGen/ARM/neon_arith1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/neon_arith1.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/neon_arith1.ll (added) +++ llvm/trunk/test/CodeGen/ARM/neon_arith1.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep vadd + +define <8 x i8> @t_i8x8(<8 x i8> %a, <8 x i8> %b) nounwind { +entry: + %0 = add <8 x i8> %a, %b + ret <8 x i8> %0 +} Added: llvm/trunk/test/CodeGen/ARM/neon_ld1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/neon_ld1.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/neon_ld1.ll (added) +++ llvm/trunk/test/CodeGen/ARM/neon_ld1.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fldd | count 4 +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fstd +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fmrrd + +define void @t1(<2 x i32>* %r, <4 x i16>* %a, <4 x i16>* %b) nounwind { +entry: + %0 = load <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1] + %1 = load <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1] + %2 = add <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1] + %3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1] + store <2 x i32> %3, <2 x i32>* %r, align 8 + ret void +} + +define <2 x i32> @t2(<4 x i16>* %a, <4 x i16>* %b) nounwind readonly { +entry: + %0 = load <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1] + %1 = load <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1] + %2 = sub <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1] + %3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1] + ret <2 x i32> %3 +} Added: llvm/trunk/test/CodeGen/ARM/neon_ld2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/neon_ld2.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/neon_ld2.ll (added) +++ llvm/trunk/test/CodeGen/ARM/neon_ld2.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,23 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep vldmia | count 4 +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep vstmia | count 1 +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fmrrd | count 2 + +define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind { +entry: + %0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1] + %1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1] + %2 = add <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1] + %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1] + store <4 x i32> %3, <4 x i32>* %r, align 16 + ret void +} + +define <4 x i32> @t2(<2 x i64>* %a, <2 x i64>* %b) nounwind readonly { +entry: + %0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1] + %1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1] + %2 = sub <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1] + %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1] + ret <4 x i32> %3 +} + Added: llvm/trunk/test/CodeGen/ARM/vaba.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vaba.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vaba.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vaba.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,119 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vaba\\.s8} %t | count 2 +; RUN: grep {vaba\\.s16} %t | count 2 +; RUN: grep {vaba\\.s32} %t | count 2 +; RUN: grep {vaba\\.u8} %t | count 2 +; RUN: grep {vaba\\.u16} %t | count 2 +; RUN: grep {vaba\\.u32} %t | count 2 + +define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = load <8 x i8>* %C + %tmp4 = call <8 x i8> @llvm.arm.neon.vabas.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) + ret <8 x i8> %tmp4 +} + +define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = call <4 x i16> @llvm.arm.neon.vabas.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) + ret <4 x i16> %tmp4 +} + +define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = call <2 x i32> @llvm.arm.neon.vabas.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) + ret <2 x i32> %tmp4 +} + +define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = load <8 x i8>* %C + %tmp4 = call <8 x i8> @llvm.arm.neon.vabau.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) + ret <8 x i8> %tmp4 +} + +define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = call <4 x i16> @llvm.arm.neon.vabau.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) + ret <4 x i16> %tmp4 +} + +define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = call <2 x i32> @llvm.arm.neon.vabau.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) + ret <2 x i32> %tmp4 +} + +define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = load <16 x i8>* %C + %tmp4 = call <16 x i8> @llvm.arm.neon.vabas.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> %tmp3) + ret <16 x i8> %tmp4 +} + +define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = load <8 x i16>* %C + %tmp4 = call <8 x i16> @llvm.arm.neon.vabas.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> %tmp3) + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = load <4 x i32>* %C + %tmp4 = call <4 x i32> @llvm.arm.neon.vabas.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> %tmp3) + ret <4 x i32> %tmp4 +} + +define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = load <16 x i8>* %C + %tmp4 = call <16 x i8> @llvm.arm.neon.vabau.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> %tmp3) + ret <16 x i8> %tmp4 +} + +define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = load <8 x i16>* %C + %tmp4 = call <8 x i16> @llvm.arm.neon.vabau.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> %tmp3) + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vabaQu32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = load <4 x i32>* %C + %tmp4 = call <4 x i32> @llvm.arm.neon.vabau.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> %tmp3) + ret <4 x i32> %tmp4 +} + +declare <8 x i8> @llvm.arm.neon.vabas.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vabas.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vabas.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vabau.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vabau.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vabau.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vabas.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vabas.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vabas.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vabau.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vabau.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vabau.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vabal.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vabal.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vabal.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vabal.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,63 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vabal\\.s8} %t | count 1 +; RUN: grep {vabal\\.s16} %t | count 1 +; RUN: grep {vabal\\.s32} %t | count 1 +; RUN: grep {vabal\\.u8} %t | count 1 +; RUN: grep {vabal\\.u16} %t | count 1 +; RUN: grep {vabal\\.u32} %t | count 1 + +define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = load <8 x i8>* %C + %tmp4 = call <8 x i16> @llvm.arm.neon.vabals.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = call <4 x i32> @llvm.arm.neon.vabals.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = call <2 x i64> @llvm.arm.neon.vabals.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) + ret <2 x i64> %tmp4 +} + +define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = load <8 x i8>* %C + %tmp4 = call <8 x i16> @llvm.arm.neon.vabalu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = call <4 x i32> @llvm.arm.neon.vabalu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = call <2 x i64> @llvm.arm.neon.vabalu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) + ret <2 x i64> %tmp4 +} + +declare <8 x i16> @llvm.arm.neon.vabals.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vabals.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vabals.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vabalu.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vabalu.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vabalu.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vabd.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vabd.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vabd.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vabd.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,126 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vabd\\.s8} %t | count 2 +; RUN: grep {vabd\\.s16} %t | count 2 +; RUN: grep {vabd\\.s32} %t | count 2 +; RUN: grep {vabd\\.u8} %t | count 2 +; RUN: grep {vabd\\.u16} %t | count 2 +; RUN: grep {vabd\\.u32} %t | count 2 +; RUN: grep {vabd\\.f32} %t | count 2 + +define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = call <2 x float> @llvm.arm.neon.vabdf.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) + ret <2 x float> %tmp3 +} + +define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <4 x float> @vabdQf32(<4 x float>* %A, <4 x float>* %B) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = call <4 x float> @llvm.arm.neon.vabdf.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) + ret <4 x float> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <2 x float> @llvm.arm.neon.vabdf.v2f32(<2 x float>, <2 x float>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone + +declare <4 x float> @llvm.arm.neon.vabdf.v4f32(<4 x float>, <4 x float>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vabdl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vabdl.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vabdl.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vabdl.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,57 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vabdl\\.s8} %t | count 1 +; RUN: grep {vabdl\\.s16} %t | count 1 +; RUN: grep {vabdl\\.s32} %t | count 1 +; RUN: grep {vabdl\\.u8} %t | count 1 +; RUN: grep {vabdl\\.u16} %t | count 1 +; RUN: grep {vabdl\\.u32} %t | count 1 + +define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vabdls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vabdls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vabdls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vabdlu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vabdlu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vabdlu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +declare <8 x i16> @llvm.arm.neon.vabdls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vabdls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vabdls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vabdlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vabdlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vabdlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vabs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vabs.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vabs.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vabs.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,64 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vabs\\.s8} %t | count 2 +; RUN: grep {vabs\\.s16} %t | count 2 +; RUN: grep {vabs\\.s32} %t | count 2 +; RUN: grep {vabs\\.f32} %t | count 2 + +define <8 x i8> @vabss8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vabss16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vabss32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1) + ret <2 x i32> %tmp2 +} + +define <2 x float> @vabsf32(<2 x float>* %A) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = call <2 x float> @llvm.arm.neon.vabsf.v2f32(<2 x float> %tmp1) + ret <2 x float> %tmp2 +} + +define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1) + ret <4 x i32> %tmp2 +} + +define <4 x float> @vabsQf32(<4 x float>* %A) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = call <4 x float> @llvm.arm.neon.vabsf.v4f32(<4 x float> %tmp1) + ret <4 x float> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32>) nounwind readnone +declare <2 x float> @llvm.arm.neon.vabsf.v2f32(<2 x float>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) nounwind readnone +declare <4 x float> @llvm.arm.neon.vabsf.v4f32(<4 x float>) nounwind readnone + Added: llvm/trunk/test/CodeGen/ARM/vacge.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vacge.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vacge.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vacge.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vacge\\.f32} %t | count 2 + +define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vacged(<2 x float> %tmp1, <2 x float> %tmp2) + ret <2 x i32> %tmp3 +} + +define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vacgeq(<4 x float> %tmp1, <4 x float> %tmp2) + ret <4 x i32> %tmp3 +} + +declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vacgt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vacgt.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vacgt.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vacgt.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vacgt\\.f32} %t | count 2 + +define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vacgtd(<2 x float> %tmp1, <2 x float> %tmp2) + ret <2 x i32> %tmp3 +} + +define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vacgtq(<4 x float> %tmp1, <4 x float> %tmp2) + ret <4 x i32> %tmp3 +} + +declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vadd.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vadd.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vadd.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vadd.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,76 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vadd\\.i8} %t | count 2 +; RUN: grep {vadd\\.i16} %t | count 2 +; RUN: grep {vadd\\.i32} %t | count 2 +; RUN: grep {vadd\\.i64} %t | count 2 +; RUN: grep {vadd\\.f32} %t | count 2 + +define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = add <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = add <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = add <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = add <1 x i64> %tmp1, %tmp2 + ret <1 x i64> %tmp3 +} + +define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = add <2 x float> %tmp1, %tmp2 + ret <2 x float> %tmp3 +} + +define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = add <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = add <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = add <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = add <2 x i64> %tmp1, %tmp2 + ret <2 x i64> %tmp3 +} + +define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = add <4 x float> %tmp1, %tmp2 + ret <4 x float> %tmp3 +} Added: llvm/trunk/test/CodeGen/ARM/vaddhn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vaddhn.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vaddhn.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vaddhn.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,29 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vaddhn\\.i16} %t | count 1 +; RUN: grep {vaddhn\\.i32} %t | count 1 +; RUN: grep {vaddhn\\.i64} %t | count 1 + +define <8 x i8> @vaddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vaddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vaddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vaddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i32> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vaddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vaddl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vaddl.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vaddl.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vaddl.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,57 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vaddl\\.s8} %t | count 1 +; RUN: grep {vaddl\\.s16} %t | count 1 +; RUN: grep {vaddl\\.s32} %t | count 1 +; RUN: grep {vaddl\\.u8} %t | count 1 +; RUN: grep {vaddl\\.u16} %t | count 1 +; RUN: grep {vaddl\\.u32} %t | count 1 + +define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vaddls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vaddls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vaddls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vaddlu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vaddlu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vaddlu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +declare <8 x i16> @llvm.arm.neon.vaddls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vaddls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vaddls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vaddlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vaddlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vaddlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vaddw.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vaddw.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vaddw.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vaddw.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,57 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vaddw\\.s8} %t | count 1 +; RUN: grep {vaddw\\.s16} %t | count 1 +; RUN: grep {vaddw\\.s32} %t | count 1 +; RUN: grep {vaddw\\.u8} %t | count 1 +; RUN: grep {vaddw\\.u16} %t | count 1 +; RUN: grep {vaddw\\.u32} %t | count 1 + +define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vaddws.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vaddws.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vaddws.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vaddwu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vaddwu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vaddwu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +declare <8 x i16> @llvm.arm.neon.vaddws.v8i16(<8 x i16>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vaddws.v4i32(<4 x i32>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vaddws.v2i64(<2 x i64>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vaddwu.v8i16(<8 x i16>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vaddwu.v4i32(<4 x i32>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vaddwu.v2i64(<2 x i64>, <2 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vand.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vand.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vand.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vand.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,59 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep vand %t | count 8 +; Note: function names do not include "vand" to allow simple grep for opcodes + +define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = and <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = and <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = and <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = and <1 x i64> %tmp1, %tmp2 + ret <1 x i64> %tmp3 +} + +define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = and <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = and <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = and <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = and <2 x i64> %tmp1, %tmp2 + ret <2 x i64> %tmp3 +} Added: llvm/trunk/test/CodeGen/ARM/vbic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbic.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vbic.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vbic.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,67 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep vbic %t | count 8 +; Note: function names do not include "vbic" to allow simple grep for opcodes + +define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > + %tmp4 = and <8 x i8> %tmp1, %tmp3 + ret <8 x i8> %tmp4 +} + +define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 > + %tmp4 = and <4 x i16> %tmp1, %tmp3 + ret <4 x i16> %tmp4 +} + +define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 > + %tmp4 = and <2 x i32> %tmp1, %tmp3 + ret <2 x i32> %tmp4 +} + +define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = xor <1 x i64> %tmp2, < i64 -1 > + %tmp4 = and <1 x i64> %tmp1, %tmp3 + ret <1 x i64> %tmp4 +} + +define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > + %tmp4 = and <16 x i8> %tmp1, %tmp3 + ret <16 x i8> %tmp4 +} + +define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > + %tmp4 = and <8 x i16> %tmp1, %tmp3 + ret <8 x i16> %tmp4 +} + +define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 > + %tmp4 = and <4 x i32> %tmp1, %tmp3 + ret <4 x i32> %tmp4 +} + +define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 > + %tmp4 = and <2 x i64> %tmp1, %tmp3 + ret <2 x i64> %tmp4 +} Added: llvm/trunk/test/CodeGen/ARM/vbsl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbsl.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vbsl.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vbsl.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,91 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep vbsl %t | count 8 +; Note: function names do not include "vbsl" to allow simple grep for opcodes + +define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = load <8 x i8>* %C + %tmp4 = and <8 x i8> %tmp1, %tmp2 + %tmp5 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > + %tmp6 = and <8 x i8> %tmp5, %tmp3 + %tmp7 = or <8 x i8> %tmp4, %tmp6 + ret <8 x i8> %tmp7 +} + +define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = and <4 x i16> %tmp1, %tmp2 + %tmp5 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 > + %tmp6 = and <4 x i16> %tmp5, %tmp3 + %tmp7 = or <4 x i16> %tmp4, %tmp6 + ret <4 x i16> %tmp7 +} + +define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = and <2 x i32> %tmp1, %tmp2 + %tmp5 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 > + %tmp6 = and <2 x i32> %tmp5, %tmp3 + %tmp7 = or <2 x i32> %tmp4, %tmp6 + ret <2 x i32> %tmp7 +} + +define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = load <1 x i64>* %C + %tmp4 = and <1 x i64> %tmp1, %tmp2 + %tmp5 = xor <1 x i64> %tmp1, < i64 -1 > + %tmp6 = and <1 x i64> %tmp5, %tmp3 + %tmp7 = or <1 x i64> %tmp4, %tmp6 + ret <1 x i64> %tmp7 +} + +define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = load <16 x i8>* %C + %tmp4 = and <16 x i8> %tmp1, %tmp2 + %tmp5 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > + %tmp6 = and <16 x i8> %tmp5, %tmp3 + %tmp7 = or <16 x i8> %tmp4, %tmp6 + ret <16 x i8> %tmp7 +} + +define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = load <8 x i16>* %C + %tmp4 = and <8 x i16> %tmp1, %tmp2 + %tmp5 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > + %tmp6 = and <8 x i16> %tmp5, %tmp3 + %tmp7 = or <8 x i16> %tmp4, %tmp6 + ret <8 x i16> %tmp7 +} + +define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = load <4 x i32>* %C + %tmp4 = and <4 x i32> %tmp1, %tmp2 + %tmp5 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 > + %tmp6 = and <4 x i32> %tmp5, %tmp3 + %tmp7 = or <4 x i32> %tmp4, %tmp6 + ret <4 x i32> %tmp7 +} + +define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = load <2 x i64>* %C + %tmp4 = and <2 x i64> %tmp1, %tmp2 + %tmp5 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 > + %tmp6 = and <2 x i64> %tmp5, %tmp3 + %tmp7 = or <2 x i64> %tmp4, %tmp6 + ret <2 x i64> %tmp7 +} Added: llvm/trunk/test/CodeGen/ARM/vceq.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vceq.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vceq.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vceq.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,61 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vceq\\.i8} %t | count 2 +; RUN: grep {vceq\\.i16} %t | count 2 +; RUN: grep {vceq\\.i32} %t | count 2 +; RUN: grep {vceq\\.f32} %t | count 2 + +define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = vicmp eq <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = vicmp eq <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = vicmp eq <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp oeq <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = vicmp eq <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = vicmp eq <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = vicmp eq <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = vfcmp oeq <4 x float> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} Added: llvm/trunk/test/CodeGen/ARM/vcge.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcge.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vcge.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vcge.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,106 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vcge\\.s8} %t | count 2 +; RUN: grep {vcge\\.s16} %t | count 2 +; RUN: grep {vcge\\.s32} %t | count 2 +; RUN: grep {vcge\\.u8} %t | count 2 +; RUN: grep {vcge\\.u16} %t | count 2 +; RUN: grep {vcge\\.u32} %t | count 2 +; RUN: grep {vcge\\.f32} %t | count 2 + +define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = vicmp sge <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = vicmp sge <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = vicmp sge <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = vicmp uge <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = vicmp uge <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = vicmp uge <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp oge <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = vicmp sge <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = vicmp sge <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = vicmp sge <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = vicmp uge <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = vicmp uge <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = vicmp uge <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = vfcmp oge <4 x float> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} Added: llvm/trunk/test/CodeGen/ARM/vcgt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcgt.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vcgt.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vcgt.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,106 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vcgt\\.s8} %t | count 2 +; RUN: grep {vcgt\\.s16} %t | count 2 +; RUN: grep {vcgt\\.s32} %t | count 2 +; RUN: grep {vcgt\\.u8} %t | count 2 +; RUN: grep {vcgt\\.u16} %t | count 2 +; RUN: grep {vcgt\\.u32} %t | count 2 +; RUN: grep {vcgt\\.f32} %t | count 2 + +define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = vicmp sgt <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = vicmp sgt <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = vicmp sgt <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = vicmp ugt <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = vicmp ugt <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = vicmp ugt <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp ogt <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = vicmp sgt <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = vicmp sgt <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = vicmp sgt <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = vicmp ugt <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = vicmp ugt <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = vicmp ugt <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = vfcmp ogt <4 x float> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} Added: llvm/trunk/test/CodeGen/ARM/vcls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcls.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vcls.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vcls.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,48 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vcls\\.s8} %t | count 2 +; RUN: grep {vcls\\.s16} %t | count 2 +; RUN: grep {vcls\\.s32} %t | count 2 + +define <8 x i8> @vclss8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vclss16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vclss32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1) + ret <2 x i32> %tmp2 +} + +define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1) + ret <4 x i32> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vclz.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vclz.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vclz.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vclz.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,48 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vclz\\.i8} %t | count 2 +; RUN: grep {vclz\\.i16} %t | count 2 +; RUN: grep {vclz\\.i32} %t | count 2 + +define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vclz.v8i8(<8 x i8> %tmp1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vclz32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vclz.v2i32(<2 x i32> %tmp1) + ret <2 x i32> %tmp2 +} + +define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vclz.v16i8(<16 x i8> %tmp1) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16> %tmp1) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vclz.v4i32(<4 x i32> %tmp1) + ret <4 x i32> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vclz.v8i8(<8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vclz.v2i32(<2 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vclz.v16i8(<16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vclz.v4i32(<4 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vcnt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcnt.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vcnt.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vcnt.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vcnt\\.8} %t | count 2 + +define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1) + ret <8 x i8> %tmp2 +} + +define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8> %tmp1) + ret <16 x i8> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone +declare <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vcvt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcvt.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vcvt.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vcvt.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,53 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vcvt\\.s32\\.f32} %t | count 2 +; RUN: grep {vcvt\\.u32\\.f32} %t | count 2 +; RUN: grep {vcvt\\.f32\\.s32} %t | count 2 +; RUN: grep {vcvt\\.f32\\.u32} %t | count 2 + +define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = fptosi <2 x float> %tmp1 to <2 x i32> + ret <2 x i32> %tmp2 +} + +define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = fptoui <2 x float> %tmp1 to <2 x i32> + ret <2 x i32> %tmp2 +} + +define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = sitofp <2 x i32> %tmp1 to <2 x float> + ret <2 x float> %tmp2 +} + +define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = uitofp <2 x i32> %tmp1 to <2 x float> + ret <2 x float> %tmp2 +} + +define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = fptosi <4 x float> %tmp1 to <4 x i32> + ret <4 x i32> %tmp2 +} + +define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = fptoui <4 x float> %tmp1 to <4 x i32> + ret <4 x i32> %tmp2 +} + +define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = sitofp <4 x i32> %tmp1 to <4 x float> + ret <4 x float> %tmp2 +} + +define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = uitofp <4 x i32> %tmp1 to <4 x float> + ret <4 x float> %tmp2 +} Added: llvm/trunk/test/CodeGen/ARM/vcvt_n.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcvt_n.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vcvt_n.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vcvt_n.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,64 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vcvt\\.s32\\.f32} %t | count 2 +; RUN: grep {vcvt\\.u32\\.f32} %t | count 2 +; RUN: grep {vcvt\\.f32\\.s32} %t | count 2 +; RUN: grep {vcvt\\.f32\\.u32} %t | count 2 + +define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1) + ret <2 x i32> %tmp2 +} + +define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1) + ret <2 x i32> %tmp2 +} + +define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1) + ret <2 x float> %tmp2 +} + +define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1) + ret <2 x float> %tmp2 +} + +declare <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone +declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone +declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone + +define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1) + ret <4 x i32> %tmp2 +} + +define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1) + ret <4 x i32> %tmp2 +} + +define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1) + ret <4 x float> %tmp2 +} + +define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1) + ret <4 x float> %tmp2 +} + +declare <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone +declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone +declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone + Added: llvm/trunk/test/CodeGen/ARM/vdup.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vdup.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vdup.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vdup.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,134 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep vdup.8 %t | count 4 +; RUN: grep vdup.16 %t | count 4 +; RUN: grep vdup.32 %t | count 8 + +define <8 x i8> @v_dup8(i8 %A) nounwind { + %tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0 + %tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1 + %tmp3 = insertelement <8 x i8> %tmp2, i8 %A, i32 2 + %tmp4 = insertelement <8 x i8> %tmp3, i8 %A, i32 3 + %tmp5 = insertelement <8 x i8> %tmp4, i8 %A, i32 4 + %tmp6 = insertelement <8 x i8> %tmp5, i8 %A, i32 5 + %tmp7 = insertelement <8 x i8> %tmp6, i8 %A, i32 6 + %tmp8 = insertelement <8 x i8> %tmp7, i8 %A, i32 7 + ret <8 x i8> %tmp8 +} + +define <4 x i16> @v_dup16(i16 %A) nounwind { + %tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0 + %tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1 + %tmp3 = insertelement <4 x i16> %tmp2, i16 %A, i32 2 + %tmp4 = insertelement <4 x i16> %tmp3, i16 %A, i32 3 + ret <4 x i16> %tmp4 +} + +define <2 x i32> @v_dup32(i32 %A) nounwind { + %tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0 + %tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1 + ret <2 x i32> %tmp2 +} + +define <2 x float> @v_dupfloat(float %A) nounwind { + %tmp1 = insertelement <2 x float> zeroinitializer, float %A, i32 0 + %tmp2 = insertelement <2 x float> %tmp1, float %A, i32 1 + ret <2 x float> %tmp2 +} + +define <16 x i8> @v_dupQ8(i8 %A) nounwind { + %tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0 + %tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1 + %tmp3 = insertelement <16 x i8> %tmp2, i8 %A, i32 2 + %tmp4 = insertelement <16 x i8> %tmp3, i8 %A, i32 3 + %tmp5 = insertelement <16 x i8> %tmp4, i8 %A, i32 4 + %tmp6 = insertelement <16 x i8> %tmp5, i8 %A, i32 5 + %tmp7 = insertelement <16 x i8> %tmp6, i8 %A, i32 6 + %tmp8 = insertelement <16 x i8> %tmp7, i8 %A, i32 7 + %tmp9 = insertelement <16 x i8> %tmp8, i8 %A, i32 8 + %tmp10 = insertelement <16 x i8> %tmp9, i8 %A, i32 9 + %tmp11 = insertelement <16 x i8> %tmp10, i8 %A, i32 10 + %tmp12 = insertelement <16 x i8> %tmp11, i8 %A, i32 11 + %tmp13 = insertelement <16 x i8> %tmp12, i8 %A, i32 12 + %tmp14 = insertelement <16 x i8> %tmp13, i8 %A, i32 13 + %tmp15 = insertelement <16 x i8> %tmp14, i8 %A, i32 14 + %tmp16 = insertelement <16 x i8> %tmp15, i8 %A, i32 15 + ret <16 x i8> %tmp16 +} + +define <8 x i16> @v_dupQ16(i16 %A) nounwind { + %tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0 + %tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1 + %tmp3 = insertelement <8 x i16> %tmp2, i16 %A, i32 2 + %tmp4 = insertelement <8 x i16> %tmp3, i16 %A, i32 3 + %tmp5 = insertelement <8 x i16> %tmp4, i16 %A, i32 4 + %tmp6 = insertelement <8 x i16> %tmp5, i16 %A, i32 5 + %tmp7 = insertelement <8 x i16> %tmp6, i16 %A, i32 6 + %tmp8 = insertelement <8 x i16> %tmp7, i16 %A, i32 7 + ret <8 x i16> %tmp8 +} + +define <4 x i32> @v_dupQ32(i32 %A) nounwind { + %tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0 + %tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1 + %tmp3 = insertelement <4 x i32> %tmp2, i32 %A, i32 2 + %tmp4 = insertelement <4 x i32> %tmp3, i32 %A, i32 3 + ret <4 x i32> %tmp4 +} + +define <4 x float> @v_dupQfloat(float %A) nounwind { + %tmp1 = insertelement <4 x float> zeroinitializer, float %A, i32 0 + %tmp2 = insertelement <4 x float> %tmp1, float %A, i32 1 + %tmp3 = insertelement <4 x float> %tmp2, float %A, i32 2 + %tmp4 = insertelement <4 x float> %tmp3, float %A, i32 3 + ret <4 x float> %tmp4 +} + +; Check to make sure it works with shuffles, too. + +define <8 x i8> @v_shuffledup8(i8 %A) nounwind { + %tmp1 = insertelement <8 x i8> undef, i8 %A, i32 0 + %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer + ret <8 x i8> %tmp2 +} + +define <4 x i16> @v_shuffledup16(i16 %A) nounwind { + %tmp1 = insertelement <4 x i16> undef, i16 %A, i32 0 + %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer + ret <4 x i16> %tmp2 +} + +define <2 x i32> @v_shuffledup32(i32 %A) nounwind { + %tmp1 = insertelement <2 x i32> undef, i32 %A, i32 0 + %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer + ret <2 x i32> %tmp2 +} + +define <2 x float> @v_shuffledupfloat(float %A) nounwind { + %tmp1 = insertelement <2 x float> undef, float %A, i32 0 + %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer + ret <2 x float> %tmp2 +} + +define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind { + %tmp1 = insertelement <16 x i8> undef, i8 %A, i32 0 + %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> zeroinitializer + ret <16 x i8> %tmp2 +} + +define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind { + %tmp1 = insertelement <8 x i16> undef, i16 %A, i32 0 + %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> zeroinitializer + ret <8 x i16> %tmp2 +} + +define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind { + %tmp1 = insertelement <4 x i32> undef, i32 %A, i32 0 + %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer + ret <4 x i32> %tmp2 +} + +define <4 x float> @v_shuffledupQfloat(float %A) nounwind { + %tmp1 = insertelement <4 x float> undef, float %A, i32 0 + %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer + ret <4 x float> %tmp2 +} Added: llvm/trunk/test/CodeGen/ARM/vdup_lane.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vdup_lane.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vdup_lane.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vdup_lane.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,52 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep vdup.8 %t | count 2 +; RUN: grep vdup.16 %t | count 2 +; RUN: grep vdup.32 %t | count 4 + +define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 > + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 > + ret <2 x i32> %tmp2 +} + +define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 > + ret <2 x float> %tmp2 +} + +define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 > + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 > + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > + ret <4 x i32> %tmp2 +} + +define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > + ret <4 x float> %tmp2 +} Added: llvm/trunk/test/CodeGen/ARM/veor.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/veor.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/veor.ll (added) +++ llvm/trunk/test/CodeGen/ARM/veor.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,59 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep veor %t | count 8 +; Note: function names do not include "veor" to allow simple grep for opcodes + +define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = xor <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = xor <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = xor <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = xor <1 x i64> %tmp1, %tmp2 + ret <1 x i64> %tmp3 +} + +define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = xor <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = xor <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = xor <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = xor <2 x i64> %tmp1, %tmp2 + ret <2 x i64> %tmp3 +} Added: llvm/trunk/test/CodeGen/ARM/vfcmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vfcmp.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vfcmp.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vfcmp.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,96 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vceq\\.f32} %t | count 1 +; RUN: grep {vcgt\\.f32} %t | count 9 +; RUN: grep {vcge\\.f32} %t | count 5 +; RUN: grep vorr %t | count 4 +; RUN: grep vmvn %t | count 7 + +; This tests vfcmp operations that do not map directly to NEON instructions. + +; une is implemented with VCEQ/VMVN +define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp une <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +; olt is implemented with VCGT +define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp olt <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +; ole is implemented with VCGE +define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp ole <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +; uge is implemented with VCGT/VMVN +define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp uge <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +; ule is implemented with VCGT/VMVN +define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp ule <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +; ugt is implemented with VCGE/VMVN +define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp ugt <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +; ult is implemented with VCGE/VMVN +define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp ult <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +; ueq is implemented with VCGT/VCGT/VORR/VMVN +define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp ueq <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +; one is implemented with VCGT/VCGT/VORR +define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp one <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +; uno is implemented with VCGT/VCGE/VORR/VMVN +define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp uno <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +; ord is implemented with VCGT/VCGE/VORR +define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = vfcmp ord <2 x float> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} Added: llvm/trunk/test/CodeGen/ARM/vget_lane.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vget_lane.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vget_lane.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vget_lane.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,78 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vmov\\.s8} %t | count 2 +; RUN: grep {vmov\\.s16} %t | count 2 +; RUN: grep {vmov\\.u8} %t | count 2 +; RUN: grep {vmov\\.u16} %t | count 2 +; RUN: grep {vmov\\.32} %t | count 2 + +define i32 @vget_lanes8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = extractelement <8 x i8> %tmp1, i32 1 + %tmp3 = sext i8 %tmp2 to i32 + ret i32 %tmp3 +} + +define i32 @vget_lanes16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = extractelement <4 x i16> %tmp1, i32 1 + %tmp3 = sext i16 %tmp2 to i32 + ret i32 %tmp3 +} + +define i32 @vget_laneu8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = extractelement <8 x i8> %tmp1, i32 1 + %tmp3 = zext i8 %tmp2 to i32 + ret i32 %tmp3 +} + +define i32 @vget_laneu16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = extractelement <4 x i16> %tmp1, i32 1 + %tmp3 = zext i16 %tmp2 to i32 + ret i32 %tmp3 +} + +; Do a vector add to keep the extraction from being done directly from memory. +define i32 @vget_lanei32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = add <2 x i32> %tmp1, %tmp1 + %tmp3 = extractelement <2 x i32> %tmp2, i32 1 + ret i32 %tmp3 +} + +define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = extractelement <16 x i8> %tmp1, i32 1 + %tmp3 = sext i8 %tmp2 to i32 + ret i32 %tmp3 +} + +define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = extractelement <8 x i16> %tmp1, i32 1 + %tmp3 = sext i16 %tmp2 to i32 + ret i32 %tmp3 +} + +define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = extractelement <16 x i8> %tmp1, i32 1 + %tmp3 = zext i8 %tmp2 to i32 + ret i32 %tmp3 +} + +define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = extractelement <8 x i16> %tmp1, i32 1 + %tmp3 = zext i16 %tmp2 to i32 + ret i32 %tmp3 +} + +; Do a vector add to keep the extraction from being done directly from memory. +define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = add <4 x i32> %tmp1, %tmp1 + %tmp3 = extractelement <4 x i32> %tmp2, i32 1 + ret i32 %tmp3 +} Added: llvm/trunk/test/CodeGen/ARM/vhadd.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vhadd.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vhadd.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vhadd.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,107 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vhadd\\.s8} %t | count 2 +; RUN: grep {vhadd\\.s16} %t | count 2 +; RUN: grep {vhadd\\.s32} %t | count 2 +; RUN: grep {vhadd\\.u8} %t | count 2 +; RUN: grep {vhadd\\.u16} %t | count 2 +; RUN: grep {vhadd\\.u32} %t | count 2 + +define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vhsub.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vhsub.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vhsub.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vhsub.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,107 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vhsub\\.s8} %t | count 2 +; RUN: grep {vhsub\\.s16} %t | count 2 +; RUN: grep {vhsub\\.s32} %t | count 2 +; RUN: grep {vhsub\\.u8} %t | count 2 +; RUN: grep {vhsub\\.u16} %t | count 2 +; RUN: grep {vhsub\\.u32} %t | count 2 + +define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vhsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vicmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vicmp.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vicmp.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vicmp.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,85 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vceq\\.i8} %t | count 2 +; RUN: grep {vceq\\.i16} %t | count 2 +; RUN: grep {vceq\\.i32} %t | count 2 +; RUN: grep vmvn %t | count 6 +; RUN: grep {vcgt\\.s8} %t | count 1 +; RUN: grep {vcge\\.s16} %t | count 1 +; RUN: grep {vcgt\\.u16} %t | count 1 +; RUN: grep {vcge\\.u32} %t | count 1 + +; This tests vicmp operations that do not map directly to NEON instructions. +; Not-equal (ne) operations are implemented by VCEQ/VMVN. Less-than (lt/ult) +; and less-than-or-equal (le/ule) are implemented by swapping the arguments +; to VCGT and VCGE. Test all the operand types for not-equal but only sample +; the other operations. + +define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = vicmp ne <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = vicmp ne <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = vicmp ne <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = vicmp ne <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = vicmp ne <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = vicmp ne <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = vicmp slt <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = vicmp sle <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = vicmp ult <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <4 x i32> @vcleQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = vicmp ule <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} Added: llvm/trunk/test/CodeGen/ARM/vmax.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmax.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmax.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vmax.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,126 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vmax\\.s8} %t | count 2 +; RUN: grep {vmax\\.s16} %t | count 2 +; RUN: grep {vmax\\.s32} %t | count 2 +; RUN: grep {vmax\\.u8} %t | count 2 +; RUN: grep {vmax\\.u16} %t | count 2 +; RUN: grep {vmax\\.u32} %t | count 2 +; RUN: grep {vmax\\.f32} %t | count 2 + +define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = call <2 x float> @llvm.arm.neon.vmaxf.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) + ret <2 x float> %tmp3 +} + +define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <4 x float> @vmaxQf32(<4 x float>* %A, <4 x float>* %B) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = call <4 x float> @llvm.arm.neon.vmaxf.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) + ret <4 x float> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <2 x float> @llvm.arm.neon.vmaxf.v2f32(<2 x float>, <2 x float>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone + +declare <4 x float> @llvm.arm.neon.vmaxf.v4f32(<4 x float>, <4 x float>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vmin.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmin.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmin.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vmin.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,126 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vmin\\.s8} %t | count 2 +; RUN: grep {vmin\\.s16} %t | count 2 +; RUN: grep {vmin\\.s32} %t | count 2 +; RUN: grep {vmin\\.u8} %t | count 2 +; RUN: grep {vmin\\.u16} %t | count 2 +; RUN: grep {vmin\\.u32} %t | count 2 +; RUN: grep {vmin\\.f32} %t | count 2 + +define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = call <2 x float> @llvm.arm.neon.vminf.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) + ret <2 x float> %tmp3 +} + +define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <4 x float> @vminQf32(<4 x float>* %A, <4 x float>* %B) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = call <4 x float> @llvm.arm.neon.vminf.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) + ret <4 x float> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <2 x float> @llvm.arm.neon.vminf.v2f32(<2 x float>, <2 x float>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32>, <4 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone + +declare <4 x float> @llvm.arm.neon.vminf.v4f32(<4 x float>, <4 x float>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vmla.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmla.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmla.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vmla.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,77 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vmla\\.i8} %t | count 2 +; RUN: grep {vmla\\.i16} %t | count 2 +; RUN: grep {vmla\\.i32} %t | count 2 +; RUN: grep {vmla\\.f32} %t | count 2 + +define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = load <8 x i8>* %C + %tmp4 = mul <8 x i8> %tmp2, %tmp3 + %tmp5 = add <8 x i8> %tmp1, %tmp4 + ret <8 x i8> %tmp5 +} + +define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = mul <4 x i16> %tmp2, %tmp3 + %tmp5 = add <4 x i16> %tmp1, %tmp4 + ret <4 x i16> %tmp5 +} + +define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = mul <2 x i32> %tmp2, %tmp3 + %tmp5 = add <2 x i32> %tmp1, %tmp4 + ret <2 x i32> %tmp5 +} + +define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = load <2 x float>* %C + %tmp4 = mul <2 x float> %tmp2, %tmp3 + %tmp5 = add <2 x float> %tmp1, %tmp4 + ret <2 x float> %tmp5 +} + +define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = load <16 x i8>* %C + %tmp4 = mul <16 x i8> %tmp2, %tmp3 + %tmp5 = add <16 x i8> %tmp1, %tmp4 + ret <16 x i8> %tmp5 +} + +define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = load <8 x i16>* %C + %tmp4 = mul <8 x i16> %tmp2, %tmp3 + %tmp5 = add <8 x i16> %tmp1, %tmp4 + ret <8 x i16> %tmp5 +} + +define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = load <4 x i32>* %C + %tmp4 = mul <4 x i32> %tmp2, %tmp3 + %tmp5 = add <4 x i32> %tmp1, %tmp4 + ret <4 x i32> %tmp5 +} + +define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = load <4 x float>* %C + %tmp4 = mul <4 x float> %tmp2, %tmp3 + %tmp5 = add <4 x float> %tmp1, %tmp4 + ret <4 x float> %tmp5 +} Added: llvm/trunk/test/CodeGen/ARM/vmlal.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmlal.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmlal.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vmlal.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,63 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vmlal\\.s8} %t | count 1 +; RUN: grep {vmlal\\.s16} %t | count 1 +; RUN: grep {vmlal\\.s32} %t | count 1 +; RUN: grep {vmlal\\.u8} %t | count 1 +; RUN: grep {vmlal\\.u16} %t | count 1 +; RUN: grep {vmlal\\.u32} %t | count 1 + +define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = load <8 x i8>* %C + %tmp4 = call <8 x i16> @llvm.arm.neon.vmlals.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = call <4 x i32> @llvm.arm.neon.vmlals.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = call <2 x i64> @llvm.arm.neon.vmlals.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) + ret <2 x i64> %tmp4 +} + +define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = load <8 x i8>* %C + %tmp4 = call <8 x i16> @llvm.arm.neon.vmlalu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = call <4 x i32> @llvm.arm.neon.vmlalu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = call <2 x i64> @llvm.arm.neon.vmlalu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) + ret <2 x i64> %tmp4 +} + +declare <8 x i16> @llvm.arm.neon.vmlals.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vmlals.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vmlals.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vmlalu.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vmlalu.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vmlalu.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vmls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmls.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmls.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vmls.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,77 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vmls\\.i8} %t | count 2 +; RUN: grep {vmls\\.i16} %t | count 2 +; RUN: grep {vmls\\.i32} %t | count 2 +; RUN: grep {vmls\\.f32} %t | count 2 + +define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = load <8 x i8>* %C + %tmp4 = mul <8 x i8> %tmp2, %tmp3 + %tmp5 = sub <8 x i8> %tmp1, %tmp4 + ret <8 x i8> %tmp5 +} + +define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = mul <4 x i16> %tmp2, %tmp3 + %tmp5 = sub <4 x i16> %tmp1, %tmp4 + ret <4 x i16> %tmp5 +} + +define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = mul <2 x i32> %tmp2, %tmp3 + %tmp5 = sub <2 x i32> %tmp1, %tmp4 + ret <2 x i32> %tmp5 +} + +define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = load <2 x float>* %C + %tmp4 = mul <2 x float> %tmp2, %tmp3 + %tmp5 = sub <2 x float> %tmp1, %tmp4 + ret <2 x float> %tmp5 +} + +define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = load <16 x i8>* %C + %tmp4 = mul <16 x i8> %tmp2, %tmp3 + %tmp5 = sub <16 x i8> %tmp1, %tmp4 + ret <16 x i8> %tmp5 +} + +define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = load <8 x i16>* %C + %tmp4 = mul <8 x i16> %tmp2, %tmp3 + %tmp5 = sub <8 x i16> %tmp1, %tmp4 + ret <8 x i16> %tmp5 +} + +define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = load <4 x i32>* %C + %tmp4 = mul <4 x i32> %tmp2, %tmp3 + %tmp5 = sub <4 x i32> %tmp1, %tmp4 + ret <4 x i32> %tmp5 +} + +define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = load <4 x float>* %C + %tmp4 = mul <4 x float> %tmp2, %tmp3 + %tmp5 = sub <4 x float> %tmp1, %tmp4 + ret <4 x float> %tmp5 +} Added: llvm/trunk/test/CodeGen/ARM/vmlsl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmlsl.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmlsl.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vmlsl.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,63 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vmlsl\\.s8} %t | count 1 +; RUN: grep {vmlsl\\.s16} %t | count 1 +; RUN: grep {vmlsl\\.s32} %t | count 1 +; RUN: grep {vmlsl\\.u8} %t | count 1 +; RUN: grep {vmlsl\\.u16} %t | count 1 +; RUN: grep {vmlsl\\.u32} %t | count 1 + +define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = load <8 x i8>* %C + %tmp4 = call <8 x i16> @llvm.arm.neon.vmlsls.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = call <4 x i32> @llvm.arm.neon.vmlsls.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = call <2 x i64> @llvm.arm.neon.vmlsls.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) + ret <2 x i64> %tmp4 +} + +define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = load <8 x i8>* %C + %tmp4 = call <8 x i16> @llvm.arm.neon.vmlslu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = call <4 x i32> @llvm.arm.neon.vmlslu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = call <2 x i64> @llvm.arm.neon.vmlslu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) + ret <2 x i64> %tmp4 +} + +declare <8 x i16> @llvm.arm.neon.vmlsls.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vmlsls.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vmlsls.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vmlslu.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vmlslu.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vmlslu.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vmov.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmov.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmov.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vmov.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,101 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep vmov.i8 %t | count 2 +; RUN: grep vmov.i16 %t | count 4 +; RUN: grep vmov.i32 %t | count 12 +; RUN: grep vmov.i64 %t | count 2 +; Note: function names do not include "vmov" to allow simple grep for opcodes + +define <8 x i8> @v_movi8() nounwind { + ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > +} + +define <4 x i16> @v_movi16a() nounwind { + ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 > +} + +; 0x1000 = 4096 +define <4 x i16> @v_movi16b() nounwind { + ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 > +} + +define <2 x i32> @v_movi32a() nounwind { + ret <2 x i32> < i32 32, i32 32 > +} + +; 0x2000 = 8192 +define <2 x i32> @v_movi32b() nounwind { + ret <2 x i32> < i32 8192, i32 8192 > +} + +; 0x200000 = 2097152 +define <2 x i32> @v_movi32c() nounwind { + ret <2 x i32> < i32 2097152, i32 2097152 > +} + +; 0x20000000 = 536870912 +define <2 x i32> @v_movi32d() nounwind { + ret <2 x i32> < i32 536870912, i32 536870912 > +} + +; 0x20ff = 8447 +define <2 x i32> @v_movi32e() nounwind { + ret <2 x i32> < i32 8447, i32 8447 > +} + +; 0x20ffff = 2162687 +define <2 x i32> @v_movi32f() nounwind { + ret <2 x i32> < i32 2162687, i32 2162687 > +} + +; 0xff0000ff0000ffff = 18374687574888349695 +define <1 x i64> @v_movi64() nounwind { + ret <1 x i64> < i64 18374687574888349695 > +} + +define <16 x i8> @v_movQi8() nounwind { + ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > +} + +define <8 x i16> @v_movQi16a() nounwind { + ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > +} + +; 0x1000 = 4096 +define <8 x i16> @v_movQi16b() nounwind { + ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 > +} + +define <4 x i32> @v_movQi32a() nounwind { + ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 > +} + +; 0x2000 = 8192 +define <4 x i32> @v_movQi32b() nounwind { + ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 > +} + +; 0x200000 = 2097152 +define <4 x i32> @v_movQi32c() nounwind { + ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 > +} + +; 0x20000000 = 536870912 +define <4 x i32> @v_movQi32d() nounwind { + ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 > +} + +; 0x20ff = 8447 +define <4 x i32> @v_movQi32e() nounwind { + ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 > +} + +; 0x20ffff = 2162687 +define <4 x i32> @v_movQi32f() nounwind { + ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 > +} + +; 0xff0000ff0000ffff = 18374687574888349695 +define <2 x i64> @v_movQi64() nounwind { + ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 > +} + Added: llvm/trunk/test/CodeGen/ARM/vmovl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmovl.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmovl.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vmovl.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,51 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vmovl\\.s8} %t | count 1 +; RUN: grep {vmovl\\.s16} %t | count 1 +; RUN: grep {vmovl\\.s32} %t | count 1 +; RUN: grep {vmovl\\.u8} %t | count 1 +; RUN: grep {vmovl\\.u16} %t | count 1 +; RUN: grep {vmovl\\.u32} %t | count 1 + +define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vmovls.v8i16(<8 x i8> %tmp1) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16> %tmp1) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vmovls.v2i64(<2 x i32> %tmp1) + ret <2 x i64> %tmp2 +} + +define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vmovlu.v8i16(<8 x i8> %tmp1) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vmovlu.v4i32(<4 x i16> %tmp1) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vmovlu.v2i64(<2 x i32> %tmp1) + ret <2 x i64> %tmp2 +} + +declare <8 x i16> @llvm.arm.neon.vmovls.v8i16(<8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vmovls.v2i64(<2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vmovlu.v8i16(<8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vmovlu.v4i32(<4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vmovlu.v2i64(<2 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vmovn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmovn.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmovn.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vmovn.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,26 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vmovn\\.i16} %t | count 1 +; RUN: grep {vmovn\\.i32} %t | count 1 +; RUN: grep {vmovn\\.i64} %t | count 1 + +define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vmovn.v8i8(<8 x i16> %tmp1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vmovn.v4i16(<4 x i32> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vmovn.v2i32(<2 x i64> %tmp1) + ret <2 x i32> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vmovn.v8i8(<8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vmovn.v4i16(<4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vmovn.v2i32(<2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vmul.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmul.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmul.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vmul.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,79 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vmul\\.i8} %t | count 2 +; RUN: grep {vmul\\.i16} %t | count 2 +; RUN: grep {vmul\\.i32} %t | count 2 +; RUN: grep {vmul\\.f32} %t | count 2 +; RUN: grep {vmul\\.p8} %t | count 2 + +define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = mul <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = mul <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = mul <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = mul <2 x float> %tmp1, %tmp2 + ret <2 x float> %tmp3 +} + +define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = mul <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = mul <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = mul <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = mul <4 x float> %tmp1, %tmp2 + ret <4 x float> %tmp3 +} + +define <16 x i8> @vmulQp8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vmull.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmull.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmull.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vmull.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,67 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vmull\\.s8} %t | count 1 +; RUN: grep {vmull\\.s16} %t | count 1 +; RUN: grep {vmull\\.s32} %t | count 1 +; RUN: grep {vmull\\.u8} %t | count 1 +; RUN: grep {vmull\\.u16} %t | count 1 +; RUN: grep {vmull\\.u32} %t | count 1 +; RUN: grep {vmull\\.p8} %t | count 1 + +define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +declare <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8>, <8 x i8>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vmvn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmvn.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmvn.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vmvn.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,51 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep vmvn %t | count 8 +; Note: function names do not include "vmvn" to allow simple grep for opcodes + +define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > + ret <8 x i8> %tmp2 +} + +define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 > + ret <4 x i16> %tmp2 +} + +define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 > + ret <2 x i32> %tmp2 +} + +define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = xor <1 x i64> %tmp1, < i64 -1 > + ret <1 x i64> %tmp2 +} + +define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > + ret <16 x i8> %tmp2 +} + +define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > + ret <8 x i16> %tmp2 +} + +define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 > + ret <4 x i32> %tmp2 +} + +define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 > + ret <2 x i64> %tmp2 +} Added: llvm/trunk/test/CodeGen/ARM/vneg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vneg.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vneg.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vneg.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,53 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vneg\\.s8} %t | count 2 +; RUN: grep {vneg\\.s16} %t | count 2 +; RUN: grep {vneg\\.s32} %t | count 2 +; RUN: grep {vneg\\.f32} %t | count 2 + +define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = sub <8 x i8> zeroinitializer, %tmp1 + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = sub <4 x i16> zeroinitializer, %tmp1 + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = sub <2 x i32> zeroinitializer, %tmp1 + ret <2 x i32> %tmp2 +} + +define <2 x float> @vnegf32(<2 x float>* %A) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = sub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1 + ret <2 x float> %tmp2 +} + +define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = sub <16 x i8> zeroinitializer, %tmp1 + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = sub <8 x i16> zeroinitializer, %tmp1 + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = sub <4 x i32> zeroinitializer, %tmp1 + ret <4 x i32> %tmp2 +} + +define <4 x float> @vnegQf32(<4 x float>* %A) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = sub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1 + ret <4 x float> %tmp2 +} Added: llvm/trunk/test/CodeGen/ARM/vorn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vorn.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vorn.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vorn.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,67 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep vorn %t | count 8 +; Note: function names do not include "vorn" to allow simple grep for opcodes + +define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > + %tmp4 = or <8 x i8> %tmp1, %tmp3 + ret <8 x i8> %tmp4 +} + +define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 > + %tmp4 = or <4 x i16> %tmp1, %tmp3 + ret <4 x i16> %tmp4 +} + +define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 > + %tmp4 = or <2 x i32> %tmp1, %tmp3 + ret <2 x i32> %tmp4 +} + +define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = xor <1 x i64> %tmp2, < i64 -1 > + %tmp4 = or <1 x i64> %tmp1, %tmp3 + ret <1 x i64> %tmp4 +} + +define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > + %tmp4 = or <16 x i8> %tmp1, %tmp3 + ret <16 x i8> %tmp4 +} + +define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > + %tmp4 = or <8 x i16> %tmp1, %tmp3 + ret <8 x i16> %tmp4 +} + +define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 > + %tmp4 = or <4 x i32> %tmp1, %tmp3 + ret <4 x i32> %tmp4 +} + +define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 > + %tmp4 = or <2 x i64> %tmp1, %tmp3 + ret <2 x i64> %tmp4 +} Added: llvm/trunk/test/CodeGen/ARM/vorr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vorr.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vorr.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vorr.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,59 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep vorr %t | count 8 +; Note: function names do not include "vorr" to allow simple grep for opcodes + +define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = or <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = or <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = or <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = or <1 x i64> %tmp1, %tmp2 + ret <1 x i64> %tmp3 +} + +define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = or <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = or <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = or <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = or <2 x i64> %tmp1, %tmp2 + ret <2 x i64> %tmp3 +} Added: llvm/trunk/test/CodeGen/ARM/vpadal.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vpadal.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vpadal.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vpadal.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,107 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vpadal\\.s8} %t | count 2 +; RUN: grep {vpadal\\.s16} %t | count 2 +; RUN: grep {vpadal\\.s32} %t | count 2 +; RUN: grep {vpadal\\.u8} %t | count 2 +; RUN: grep {vpadal\\.u16} %t | count 2 +; RUN: grep {vpadal\\.u32} %t | count 2 + +define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2) + ret <1 x i64> %tmp3 +} + +define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2) + ret <1 x i64> %tmp3 +} + +define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +declare <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone + +declare <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vpadd.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vpadd.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vpadd.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vpadd.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,39 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vpadd\\.i8} %t | count 1 +; RUN: grep {vpadd\\.i16} %t | count 1 +; RUN: grep {vpadd\\.i32} %t | count 1 +; RUN: grep {vpadd\\.f32} %t | count 1 + +define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vpaddi.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vpaddi.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vpaddi.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = call <2 x float> @llvm.arm.neon.vpaddf.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) + ret <2 x float> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vpaddi.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vpaddi.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vpaddi.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <2 x float> @llvm.arm.neon.vpaddf.v2f32(<2 x float>, <2 x float>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vpaddl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vpaddl.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vpaddl.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vpaddl.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,95 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vpaddl\\.s8} %t | count 2 +; RUN: grep {vpaddl\\.s16} %t | count 2 +; RUN: grep {vpaddl\\.s32} %t | count 2 +; RUN: grep {vpaddl\\.u8} %t | count 2 +; RUN: grep {vpaddl\\.u16} %t | count 2 +; RUN: grep {vpaddl\\.u32} %t | count 2 + +define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1) + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1) + ret <1 x i64> %tmp2 +} + +define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1) + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1) + ret <1 x i64> %tmp2 +} + +define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1) + ret <2 x i64> %tmp2 +} + +define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1) + ret <2 x i64> %tmp2 +} + +declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) nounwind readnone + +declare <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vpmax.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vpmax.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vpmax.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vpmax.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,67 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vpmax\\.s8} %t | count 1 +; RUN: grep {vpmax\\.s16} %t | count 1 +; RUN: grep {vpmax\\.s32} %t | count 1 +; RUN: grep {vpmax\\.u8} %t | count 1 +; RUN: grep {vpmax\\.u16} %t | count 1 +; RUN: grep {vpmax\\.u32} %t | count 1 +; RUN: grep {vpmax\\.f32} %t | count 1 + +define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <2 x float> @vpmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = call <2 x float> @llvm.arm.neon.vpmaxf.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) + ret <2 x float> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <2 x float> @llvm.arm.neon.vpmaxf.v2f32(<2 x float>, <2 x float>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vpmin.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vpmin.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vpmin.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vpmin.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,67 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vpmin\\.s8} %t | count 1 +; RUN: grep {vpmin\\.s16} %t | count 1 +; RUN: grep {vpmin\\.s32} %t | count 1 +; RUN: grep {vpmin\\.u8} %t | count 1 +; RUN: grep {vpmin\\.u16} %t | count 1 +; RUN: grep {vpmin\\.u32} %t | count 1 +; RUN: grep {vpmin\\.f32} %t | count 1 + +define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <2 x float> @vpminf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = call <2 x float> @llvm.arm.neon.vpminf.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) + ret <2 x float> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <2 x float> @llvm.arm.neon.vpminf.v2f32(<2 x float>, <2 x float>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vqabs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqabs.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vqabs.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vqabs.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,48 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqabs\\.s8} %t | count 2 +; RUN: grep {vqabs\\.s16} %t | count 2 +; RUN: grep {vqabs\\.s32} %t | count 2 + +define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1) + ret <2 x i32> %tmp2 +} + +define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1) + ret <4 x i32> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vqadd.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqadd.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vqadd.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vqadd.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,141 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqadd\\.s8} %t | count 2 +; RUN: grep {vqadd\\.s16} %t | count 2 +; RUN: grep {vqadd\\.s32} %t | count 2 +; RUN: grep {vqadd\\.s64} %t | count 2 +; RUN: grep {vqadd\\.u8} %t | count 2 +; RUN: grep {vqadd\\.u16} %t | count 2 +; RUN: grep {vqadd\\.u32} %t | count 2 +; RUN: grep {vqadd\\.u64} %t | count 2 + +define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) + ret <1 x i64> %tmp3 +} + +define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) + ret <1 x i64> %tmp3 +} + +define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i64> %tmp3 +} + +define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vqaddQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i64> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64>, <2 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vqdmlal.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqdmlal.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vqdmlal.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vqdmlal.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqdmlal\\.s16} %t | count 1 +; RUN: grep {vqdmlal\\.s32} %t | count 1 + +define <4 x i32> @vqdmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmlal.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vqdmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) + ret <2 x i64> %tmp4 +} + +declare <4 x i32> @llvm.arm.neon.vqdmlal.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vqdmlsl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqdmlsl.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vqdmlsl.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vqdmlsl.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqdmlsl\\.s16} %t | count 1 +; RUN: grep {vqdmlsl\\.s32} %t | count 1 + +define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vqdmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) + ret <2 x i64> %tmp4 +} + +declare <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vqdmulh.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqdmulh.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vqdmulh.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vqdmulh.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,73 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqdmulh\\.s16} %t | count 2 +; RUN: grep {vqdmulh\\.s32} %t | count 2 +; RUN: grep {vqrdmulh\\.s16} %t | count 2 +; RUN: grep {vqrdmulh\\.s32} %t | count 2 + +define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vqdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +declare <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone + +define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vqrdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vqdmull.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqdmull.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vqdmull.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vqdmull.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqdmull\\.s16} %t | count 1 +; RUN: grep {vqdmull\\.s32} %t | count 1 + +define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vqdmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +declare <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vqmovn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqmovn.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vqmovn.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vqmovn.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,76 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqmovn\\.s16} %t | count 1 +; RUN: grep {vqmovn\\.s32} %t | count 1 +; RUN: grep {vqmovn\\.s64} %t | count 1 +; RUN: grep {vqmovn\\.u16} %t | count 1 +; RUN: grep {vqmovn\\.u32} %t | count 1 +; RUN: grep {vqmovn\\.u64} %t | count 1 +; RUN: grep {vqmovun\\.s16} %t | count 1 +; RUN: grep {vqmovun\\.s32} %t | count 1 +; RUN: grep {vqmovun\\.s64} %t | count 1 + +define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1) + ret <2 x i32> %tmp2 +} + +define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1) + ret <2 x i32> %tmp2 +} + +define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1) + ret <2 x i32> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vqneg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqneg.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vqneg.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vqneg.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,48 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqneg\\.s8} %t | count 2 +; RUN: grep {vqneg\\.s16} %t | count 2 +; RUN: grep {vqneg\\.s32} %t | count 2 + +define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1) + ret <2 x i32> %tmp2 +} + +define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1) + ret <4 x i32> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vqrshl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqrshl.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vqrshl.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vqrshl.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,141 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqrshl\\.s8} %t | count 2 +; RUN: grep {vqrshl\\.s16} %t | count 2 +; RUN: grep {vqrshl\\.s32} %t | count 2 +; RUN: grep {vqrshl\\.s64} %t | count 2 +; RUN: grep {vqrshl\\.u8} %t | count 2 +; RUN: grep {vqrshl\\.u16} %t | count 2 +; RUN: grep {vqrshl\\.u32} %t | count 2 +; RUN: grep {vqrshl\\.u64} %t | count 2 + +define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) + ret <1 x i64> %tmp3 +} + +define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) + ret <1 x i64> %tmp3 +} + +define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i64> %tmp3 +} + +define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vqrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i64> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vqrshrn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqrshrn.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vqrshrn.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vqrshrn.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,76 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqrshrn\\.s16} %t | count 1 +; RUN: grep {vqrshrn\\.s32} %t | count 1 +; RUN: grep {vqrshrn\\.s64} %t | count 1 +; RUN: grep {vqrshrn\\.u16} %t | count 1 +; RUN: grep {vqrshrn\\.u32} %t | count 1 +; RUN: grep {vqrshrn\\.u64} %t | count 1 +; RUN: grep {vqrshrun\\.s16} %t | count 1 +; RUN: grep {vqrshrun\\.s32} %t | count 1 +; RUN: grep {vqrshrun\\.s64} %t | count 1 + +define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) + ret <2 x i32> %tmp2 +} + +define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) + ret <2 x i32> %tmp2 +} + +define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) + ret <2 x i32> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vqshl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqshl.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vqshl.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vqshl.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,307 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqshl\\.s8} %t | count 4 +; RUN: grep {vqshl\\.s16} %t | count 4 +; RUN: grep {vqshl\\.s32} %t | count 4 +; RUN: grep {vqshl\\.s64} %t | count 4 +; RUN: grep {vqshl\\.u8} %t | count 4 +; RUN: grep {vqshl\\.u16} %t | count 4 +; RUN: grep {vqshl\\.u32} %t | count 4 +; RUN: grep {vqshl\\.u64} %t | count 4 +; RUN: grep {vqshl\\.s8.*#7} %t | count 2 +; RUN: grep {vqshl\\.s16.*#15} %t | count 2 +; RUN: grep {vqshl\\.s32.*#31} %t | count 2 +; RUN: grep {vqshl\\.s64.*#63} %t | count 2 +; RUN: grep {vqshl\\.u8.*#7} %t | count 2 +; RUN: grep {vqshl\\.u16.*#15} %t | count 2 +; RUN: grep {vqshl\\.u32.*#31} %t | count 2 +; RUN: grep {vqshl\\.u64.*#63} %t | count 2 +; RUN: grep {vqshlu\\.s8} %t | count 2 +; RUN: grep {vqshlu\\.s16} %t | count 2 +; RUN: grep {vqshlu\\.s32} %t | count 2 +; RUN: grep {vqshlu\\.s64} %t | count 2 + +define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) + ret <1 x i64> %tmp3 +} + +define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) + ret <1 x i64> %tmp3 +} + +define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i64> %tmp3 +} + +define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i64> %tmp3 +} + +define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >) + ret <1 x i64> %tmp2 +} + +define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >) + ret <1 x i64> %tmp2 +} + +define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >) + ret <1 x i64> %tmp2 +} + +define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >) + ret <2 x i64> %tmp2 +} + +define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >) + ret <2 x i64> %tmp2 +} + +define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vqshlQsu_n64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >) + ret <2 x i64> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vqshrn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqshrn.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vqshrn.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vqshrn.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,76 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqshrn\\.s16} %t | count 1 +; RUN: grep {vqshrn\\.s32} %t | count 1 +; RUN: grep {vqshrn\\.s64} %t | count 1 +; RUN: grep {vqshrn\\.u16} %t | count 1 +; RUN: grep {vqshrn\\.u32} %t | count 1 +; RUN: grep {vqshrn\\.u64} %t | count 1 +; RUN: grep {vqshrun\\.s16} %t | count 1 +; RUN: grep {vqshrun\\.s32} %t | count 1 +; RUN: grep {vqshrun\\.s64} %t | count 1 + +define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) + ret <2 x i32> %tmp2 +} + +define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) + ret <2 x i32> %tmp2 +} + +define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) + ret <2 x i32> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vqsub.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vqsub.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vqsub.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vqsub.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,141 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqsub\\.s8} %t | count 2 +; RUN: grep {vqsub\\.s16} %t | count 2 +; RUN: grep {vqsub\\.s32} %t | count 2 +; RUN: grep {vqsub\\.s64} %t | count 2 +; RUN: grep {vqsub\\.u8} %t | count 2 +; RUN: grep {vqsub\\.u16} %t | count 2 +; RUN: grep {vqsub\\.u32} %t | count 2 +; RUN: grep {vqsub\\.u64} %t | count 2 + +define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) + ret <1 x i64> %tmp3 +} + +define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) + ret <1 x i64> %tmp3 +} + +define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i64> %tmp3 +} + +define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vqsubQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i64> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64>, <2 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vraddhn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vraddhn.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vraddhn.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vraddhn.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,29 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vraddhn\\.i16} %t | count 1 +; RUN: grep {vraddhn\\.i32} %t | count 1 +; RUN: grep {vraddhn\\.i64} %t | count 1 + +define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vraddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i32> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vrecpe.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrecpe.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vrecpe.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vrecpe.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,33 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vrecpe\\.u32} %t | count 2 +; RUN: grep {vrecpe\\.f32} %t | count 2 + +define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1) + ret <2 x i32> %tmp2 +} + +define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1) + ret <4 x i32> %tmp2 +} + +define <2 x float> @vrecpef32(<2 x float>* %A) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = call <2 x float> @llvm.arm.neon.vrecpef.v2f32(<2 x float> %tmp1) + ret <2 x float> %tmp2 +} + +define <4 x float> @vrecpeQf32(<4 x float>* %A) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = call <4 x float> @llvm.arm.neon.vrecpef.v4f32(<4 x float> %tmp1) + ret <4 x float> %tmp2 +} + +declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone + +declare <2 x float> @llvm.arm.neon.vrecpef.v2f32(<2 x float>) nounwind readnone +declare <4 x float> @llvm.arm.neon.vrecpef.v4f32(<4 x float>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vrecps.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrecps.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vrecps.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vrecps.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vrecps\\.f32} %t | count 2 + +define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = call <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) + ret <2 x float> %tmp3 +} + +define <4 x float> @vrecpsQf32(<4 x float>* %A, <4 x float>* %B) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) + ret <4 x float> %tmp3 +} + +declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>) nounwind readnone +declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vrhadd.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrhadd.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vrhadd.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vrhadd.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,107 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vrhadd\\.s8} %t | count 2 +; RUN: grep {vrhadd\\.s16} %t | count 2 +; RUN: grep {vrhadd\\.s32} %t | count 2 +; RUN: grep {vrhadd\\.u8} %t | count 2 +; RUN: grep {vrhadd\\.u16} %t | count 2 +; RUN: grep {vrhadd\\.u32} %t | count 2 + +define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vrhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vrshl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrshl.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vrshl.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vrshl.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,245 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vrshl\\.s8} %t | count 2 +; RUN: grep {vrshl\\.s16} %t | count 2 +; RUN: grep {vrshl\\.s32} %t | count 2 +; RUN: grep {vrshl\\.s64} %t | count 2 +; RUN: grep {vrshl\\.u8} %t | count 2 +; RUN: grep {vrshl\\.u16} %t | count 2 +; RUN: grep {vrshl\\.u32} %t | count 2 +; RUN: grep {vrshl\\.u64} %t | count 2 +; RUN: grep {vrshr\\.s8} %t | count 2 +; RUN: grep {vrshr\\.s16} %t | count 2 +; RUN: grep {vrshr\\.s32} %t | count 2 +; RUN: grep {vrshr\\.s64} %t | count 2 +; RUN: grep {vrshr\\.u8} %t | count 2 +; RUN: grep {vrshr\\.u16} %t | count 2 +; RUN: grep {vrshr\\.u32} %t | count 2 +; RUN: grep {vrshr\\.u64} %t | count 2 + +define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) + ret <1 x i64> %tmp3 +} + +define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) + ret <1 x i64> %tmp3 +} + +define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i64> %tmp3 +} + +define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i64> %tmp3 +} + +define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) + ret <1 x i64> %tmp2 +} + +define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) + ret <1 x i64> %tmp2 +} + +define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) + ret <2 x i64> %tmp2 +} + +define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vrshrQu64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) + ret <2 x i64> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vrshrn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrshrn.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vrshrn.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vrshrn.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,26 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vrshrn\\.i16} %t | count 1 +; RUN: grep {vrshrn\\.i32} %t | count 1 +; RUN: grep {vrshrn\\.i64} %t | count 1 + +define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vrshrns32(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) + ret <2 x i32> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vrsqrte.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrsqrte.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vrsqrte.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vrsqrte.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,33 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vrsqrte\\.u32} %t | count 2 +; RUN: grep {vrsqrte\\.f32} %t | count 2 + +define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1) + ret <2 x i32> %tmp2 +} + +define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1) + ret <4 x i32> %tmp2 +} + +define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = call <2 x float> @llvm.arm.neon.vrsqrtef.v2f32(<2 x float> %tmp1) + ret <2 x float> %tmp2 +} + +define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = call <4 x float> @llvm.arm.neon.vrsqrtef.v4f32(<4 x float> %tmp1) + ret <4 x float> %tmp2 +} + +declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone + +declare <2 x float> @llvm.arm.neon.vrsqrtef.v2f32(<2 x float>) nounwind readnone +declare <4 x float> @llvm.arm.neon.vrsqrtef.v4f32(<4 x float>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vrsqrts.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrsqrts.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vrsqrts.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vrsqrts.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vrsqrts\\.f32} %t | count 2 + +define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) + ret <2 x float> %tmp3 +} + +define <4 x float> @vrsqrtsQf32(<4 x float>* %A, <4 x float>* %B) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) + ret <4 x float> %tmp3 +} + +declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone +declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vrsubhn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrsubhn.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vrsubhn.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vrsubhn.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,29 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vrsubhn\\.i16} %t | count 1 +; RUN: grep {vrsubhn\\.i32} %t | count 1 +; RUN: grep {vrsubhn\\.i64} %t | count 1 + +define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vrsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i32> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vset_lane.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vset_lane.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vset_lane.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vset_lane.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,40 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vmov\\.8} %t | count 2 +; RUN: grep {vmov\\.16} %t | count 2 +; RUN: grep {vmov\\.32} %t | count 2 + +define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1 + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1 + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1 + ret <2 x i32> %tmp2 +} + +define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1 + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1 + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1 + ret <4 x i32> %tmp2 +} Added: llvm/trunk/test/CodeGen/ARM/vshift.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vshift.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vshift.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vshift.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,337 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vshl\\.s8} %t | count 2 +; RUN: grep {vshl\\.s16} %t | count 2 +; RUN: grep {vshl\\.s32} %t | count 2 +; RUN: grep {vshl\\.s64} %t | count 2 +; RUN: grep {vshl\\.u8} %t | count 4 +; RUN: grep {vshl\\.u16} %t | count 4 +; RUN: grep {vshl\\.u32} %t | count 4 +; RUN: grep {vshl\\.u64} %t | count 4 +; RUN: grep {vshl\\.i8} %t | count 2 +; RUN: grep {vshl\\.i16} %t | count 2 +; RUN: grep {vshl\\.i32} %t | count 2 +; RUN: grep {vshl\\.i64} %t | count 2 +; RUN: grep {vshr\\.u8} %t | count 2 +; RUN: grep {vshr\\.u16} %t | count 2 +; RUN: grep {vshr\\.u32} %t | count 2 +; RUN: grep {vshr\\.u64} %t | count 2 +; RUN: grep {vshr\\.s8} %t | count 2 +; RUN: grep {vshr\\.s16} %t | count 2 +; RUN: grep {vshr\\.s32} %t | count 2 +; RUN: grep {vshr\\.s64} %t | count 2 +; RUN: grep {vneg\\.s8} %t | count 4 +; RUN: grep {vneg\\.s16} %t | count 4 +; RUN: grep {vneg\\.s32} %t | count 4 +; RUN: grep {vsub\\.i64} %t | count 4 + +define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = shl <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = shl <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = shl <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = shl <1 x i64> %tmp1, %tmp2 + ret <1 x i64> %tmp3 +} + +define <8 x i8> @vshli8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vshli16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 > + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vshli32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 > + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vshli64(<1 x i64>* %A) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = shl <1 x i64> %tmp1, < i64 63 > + ret <1 x i64> %tmp2 +} + +define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shl <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = shl <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = shl <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = shl <2 x i64> %tmp1, %tmp2 + ret <2 x i64> %tmp3 +} + +define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 > + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 > + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 > + ret <2 x i64> %tmp2 +} + +define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = lshr <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = lshr <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = lshr <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = lshr <1 x i64> %tmp1, %tmp2 + ret <1 x i64> %tmp3 +} + +define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = lshr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = lshr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 > + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = lshr <2 x i32> %tmp1, < i32 32, i32 32 > + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = lshr <1 x i64> %tmp1, < i64 64 > + ret <1 x i64> %tmp2 +} + +define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = lshr <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = lshr <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = lshr <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = lshr <2 x i64> %tmp1, %tmp2 + ret <2 x i64> %tmp3 +} + +define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = lshr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = lshr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = lshr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 > + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vlshrQi64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = lshr <2 x i64> %tmp1, < i64 64, i64 64 > + ret <2 x i64> %tmp2 +} + +define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = ashr <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = ashr <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = ashr <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = ashr <1 x i64> %tmp1, %tmp2 + ret <1 x i64> %tmp3 +} + +define <8 x i8> @vashri8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vashri16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 > + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vashri32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 > + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vashri64(<1 x i64>* %A) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = ashr <1 x i64> %tmp1, < i64 64 > + ret <1 x i64> %tmp2 +} + +define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = ashr <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = ashr <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = ashr <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = ashr <2 x i64> %tmp1, %tmp2 + ret <2 x i64> %tmp3 +} + +define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = ashr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = ashr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = ashr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 > + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vashrQi64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = ashr <2 x i64> %tmp1, < i64 64, i64 64 > + ret <2 x i64> %tmp2 +} Added: llvm/trunk/test/CodeGen/ARM/vshiftins.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vshiftins.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vshiftins.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vshiftins.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,131 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vsli\\.8} %t | count 2 +; RUN: grep {vsli\\.16} %t | count 2 +; RUN: grep {vsli\\.32} %t | count 2 +; RUN: grep {vsli\\.64} %t | count 2 +; RUN: grep {vsri\\.8} %t | count 2 +; RUN: grep {vsri\\.16} %t | count 2 +; RUN: grep {vsri\\.32} %t | count 2 +; RUN: grep {vsri\\.64} %t | count 2 + +define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 31, i32 31 >) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 63 >) + ret <1 x i64> %tmp3 +} + +define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >) + ret <2 x i64> %tmp3 +} + +define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 -64 >) + ret <1 x i64> %tmp3 +} + +define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >) + ret <2 x i64> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64>, <1 x i64>, <1 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vshl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vshl.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vshl.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vshl.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,302 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vshl\\.s8} %t | count 2 +; RUN: grep {vshl\\.s16} %t | count 2 +; RUN: grep {vshl\\.s32} %t | count 2 +; RUN: grep {vshl\\.s64} %t | count 2 +; RUN: grep {vshl\\.u8} %t | count 2 +; RUN: grep {vshl\\.u16} %t | count 2 +; RUN: grep {vshl\\.u32} %t | count 2 +; RUN: grep {vshl\\.u64} %t | count 2 +; RUN: grep {vshl\\.i8} %t | count 2 +; RUN: grep {vshl\\.i16} %t | count 2 +; RUN: grep {vshl\\.i32} %t | count 2 +; RUN: grep {vshl\\.i64} %t | count 2 +; RUN: grep {vshr\\.s8} %t | count 2 +; RUN: grep {vshr\\.s16} %t | count 2 +; RUN: grep {vshr\\.s32} %t | count 2 +; RUN: grep {vshr\\.s64} %t | count 2 +; RUN: grep {vshr\\.u8} %t | count 2 +; RUN: grep {vshr\\.u16} %t | count 2 +; RUN: grep {vshr\\.u32} %t | count 2 +; RUN: grep {vshr\\.u64} %t | count 2 + +define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) + ret <1 x i64> %tmp3 +} + +define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) + ret <1 x i64> %tmp3 +} + +define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i64> %tmp3 +} + +define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i64> %tmp3 +} + +; For left shifts by immediates, the signedness is irrelevant. +; Test a mix of both signed and unsigned intrinsics. + +define <8 x i8> @vshli8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vshli16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vshli32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vshli64(<1 x i64>* %A) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >) + ret <1 x i64> %tmp2 +} + +define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >) + ret <2 x i64> %tmp2 +} + +; Right shift by immediate: + +define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) + ret <1 x i64> %tmp2 +} + +define <8 x i8> @vshru8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vshru16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vshru32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vshru64(<1 x i64>* %A) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) + ret <1 x i64> %tmp2 +} + +define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) + ret <2 x i64> %tmp2 +} + +define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vshrQu64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) + ret <2 x i64> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vshll.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vshll.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vshll.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vshll.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,74 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vshll\\.s8} %t | count 1 +; RUN: grep {vshll\\.s16} %t | count 1 +; RUN: grep {vshll\\.s32} %t | count 1 +; RUN: grep {vshll\\.u8} %t | count 1 +; RUN: grep {vshll\\.u16} %t | count 1 +; RUN: grep {vshll\\.u32} %t | count 1 +; RUN: grep {vshll\\.i8} %t | count 1 +; RUN: grep {vshll\\.i16} %t | count 1 +; RUN: grep {vshll\\.i32} %t | count 1 + +define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) + ret <2 x i64> %tmp2 +} + +define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) + ret <2 x i64> %tmp2 +} + +; The following tests use the maximum shift count, so the signedness is +; irrelevant. Test both signed and unsigned versions. +define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, i16 16, i16 16 >) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >) + ret <2 x i64> %tmp2 +} + +declare <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vshrn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vshrn.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vshrn.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vshrn.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,26 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vshrn\\.i16} %t | count 1 +; RUN: grep {vshrn\\.i32} %t | count 1 +; RUN: grep {vshrn\\.i64} %t | count 1 + +define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vshrns32(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = call <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) + ret <2 x i32> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vsra.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vsra.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vsra.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vsra.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,293 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vsra\\.s8} %t | count 2 +; RUN: grep {vsra\\.s16} %t | count 2 +; RUN: grep {vsra\\.s32} %t | count 2 +; RUN: grep {vsra\\.s64} %t | count 2 +; RUN: grep {vsra\\.u8} %t | count 2 +; RUN: grep {vsra\\.u16} %t | count 2 +; RUN: grep {vsra\\.u32} %t | count 2 +; RUN: grep {vsra\\.u64} %t | count 2 +; RUN: grep {vrsra\\.s8} %t | count 2 +; RUN: grep {vrsra\\.s16} %t | count 2 +; RUN: grep {vrsra\\.s32} %t | count 2 +; RUN: grep {vrsra\\.s64} %t | count 2 +; RUN: grep {vrsra\\.u8} %t | count 2 +; RUN: grep {vrsra\\.u16} %t | count 2 +; RUN: grep {vrsra\\.u32} %t | count 2 +; RUN: grep {vrsra\\.u64} %t | count 2 + +define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = ashr <8 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > + %tmp4 = add <8 x i8> %tmp1, %tmp3 + ret <8 x i8> %tmp4 +} + +define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = ashr <4 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16 > + %tmp4 = add <4 x i16> %tmp1, %tmp3 + ret <4 x i16> %tmp4 +} + +define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = ashr <2 x i32> %tmp2, < i32 32, i32 32 > + %tmp4 = add <2 x i32> %tmp1, %tmp3 + ret <2 x i32> %tmp4 +} + +define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = ashr <1 x i64> %tmp2, < i64 64 > + %tmp4 = add <1 x i64> %tmp1, %tmp3 + ret <1 x i64> %tmp4 +} + +define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = ashr <16 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > + %tmp4 = add <16 x i8> %tmp1, %tmp3 + ret <16 x i8> %tmp4 +} + +define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = ashr <8 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > + %tmp4 = add <8 x i16> %tmp1, %tmp3 + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = ashr <4 x i32> %tmp2, < i32 32, i32 32, i32 32, i32 32 > + %tmp4 = add <4 x i32> %tmp1, %tmp3 + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = ashr <2 x i64> %tmp2, < i64 64, i64 64 > + %tmp4 = add <2 x i64> %tmp1, %tmp3 + ret <2 x i64> %tmp4 +} + +define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = lshr <8 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > + %tmp4 = add <8 x i8> %tmp1, %tmp3 + ret <8 x i8> %tmp4 +} + +define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = lshr <4 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16 > + %tmp4 = add <4 x i16> %tmp1, %tmp3 + ret <4 x i16> %tmp4 +} + +define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = lshr <2 x i32> %tmp2, < i32 32, i32 32 > + %tmp4 = add <2 x i32> %tmp1, %tmp3 + ret <2 x i32> %tmp4 +} + +define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = lshr <1 x i64> %tmp2, < i64 64 > + %tmp4 = add <1 x i64> %tmp1, %tmp3 + ret <1 x i64> %tmp4 +} + +define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = lshr <16 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > + %tmp4 = add <16 x i8> %tmp1, %tmp3 + ret <16 x i8> %tmp4 +} + +define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = lshr <8 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > + %tmp4 = add <8 x i16> %tmp1, %tmp3 + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = lshr <4 x i32> %tmp2, < i32 32, i32 32, i32 32, i32 32 > + %tmp4 = add <4 x i32> %tmp1, %tmp3 + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = lshr <2 x i64> %tmp2, < i64 64, i64 64 > + %tmp4 = add <2 x i64> %tmp1, %tmp3 + ret <2 x i64> %tmp4 +} + +define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + %tmp4 = add <8 x i8> %tmp1, %tmp3 + ret <8 x i8> %tmp4 +} + +define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) + %tmp4 = add <4 x i16> %tmp1, %tmp3 + ret <4 x i16> %tmp4 +} + +define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >) + %tmp4 = add <2 x i32> %tmp1, %tmp3 + ret <2 x i32> %tmp4 +} + +define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >) + %tmp4 = add <1 x i64> %tmp1, %tmp3 + ret <1 x i64> %tmp4 +} + +define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + %tmp4 = add <8 x i8> %tmp1, %tmp3 + ret <8 x i8> %tmp4 +} + +define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) + %tmp4 = add <4 x i16> %tmp1, %tmp3 + ret <4 x i16> %tmp4 +} + +define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >) + %tmp4 = add <2 x i32> %tmp1, %tmp3 + ret <2 x i32> %tmp4 +} + +define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >) + %tmp4 = add <1 x i64> %tmp1, %tmp3 + ret <1 x i64> %tmp4 +} + +define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + %tmp4 = add <16 x i8> %tmp1, %tmp3 + ret <16 x i8> %tmp4 +} + +define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) + %tmp4 = add <8 x i16> %tmp1, %tmp3 + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) + %tmp4 = add <4 x i32> %tmp1, %tmp3 + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >) + %tmp4 = add <2 x i64> %tmp1, %tmp3 + ret <2 x i64> %tmp4 +} + +define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) + %tmp4 = add <16 x i8> %tmp1, %tmp3 + ret <16 x i8> %tmp4 +} + +define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) + %tmp4 = add <8 x i16> %tmp1, %tmp3 + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) + %tmp4 = add <4 x i32> %tmp1, %tmp3 + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vrsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >) + %tmp4 = add <2 x i64> %tmp1, %tmp3 + ret <2 x i64> %tmp4 +} + +declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vsub.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vsub.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vsub.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vsub.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,76 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vsub\\.i8} %t | count 2 +; RUN: grep {vsub\\.i16} %t | count 2 +; RUN: grep {vsub\\.i32} %t | count 2 +; RUN: grep {vsub\\.i64} %t | count 2 +; RUN: grep {vsub\\.f32} %t | count 2 + +define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = sub <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = sub <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = sub <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = sub <1 x i64> %tmp1, %tmp2 + ret <1 x i64> %tmp3 +} + +define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = sub <2 x float> %tmp1, %tmp2 + ret <2 x float> %tmp3 +} + +define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = sub <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = sub <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = sub <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = sub <2 x i64> %tmp1, %tmp2 + ret <2 x i64> %tmp3 +} + +define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = sub <4 x float> %tmp1, %tmp2 + ret <4 x float> %tmp3 +} Added: llvm/trunk/test/CodeGen/ARM/vsubhn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vsubhn.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vsubhn.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vsubhn.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,29 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vsubhn\\.i16} %t | count 1 +; RUN: grep {vsubhn\\.i32} %t | count 1 +; RUN: grep {vsubhn\\.i64} %t | count 1 + +define <8 x i8> @vsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = call <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = call <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = call <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) + ret <2 x i32> %tmp3 +} + +declare <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vsubl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vsubl.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vsubl.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vsubl.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,57 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vsubl\\.s8} %t | count 1 +; RUN: grep {vsubl\\.s16} %t | count 1 +; RUN: grep {vsubl\\.s32} %t | count 1 +; RUN: grep {vsubl\\.u8} %t | count 1 +; RUN: grep {vsubl\\.u16} %t | count 1 +; RUN: grep {vsubl\\.u32} %t | count 1 + +define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vsubls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vsubls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vsubls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vsublu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vsublu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vsublu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +declare <8 x i16> @llvm.arm.neon.vsubls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vsubls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vsubls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vsublu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vsublu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vsublu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vsubw.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vsubw.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vsubw.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vsubw.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,57 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vsubw\\.s8} %t | count 1 +; RUN: grep {vsubw\\.s16} %t | count 1 +; RUN: grep {vsubw\\.s32} %t | count 1 +; RUN: grep {vsubw\\.u8} %t | count 1 +; RUN: grep {vsubw\\.u16} %t | count 1 +; RUN: grep {vsubw\\.u32} %t | count 1 + +define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vsubws.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vsubws.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vsubws.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vsubwu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vsubwu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + +define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vsubwu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + +declare <8 x i16> @llvm.arm.neon.vsubws.v8i16(<8 x i16>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vsubws.v4i32(<4 x i32>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vsubws.v2i64(<2 x i64>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vsubwu.v8i16(<8 x i16>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vsubwu.v4i32(<4 x i32>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vsubwu.v2i64(<2 x i64>, <2 x i32>) nounwind readnone Added: llvm/trunk/test/CodeGen/ARM/vtst.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vtst.ll?rev=73919&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vtst.ll (added) +++ llvm/trunk/test/CodeGen/ARM/vtst.ll Mon Jun 22 18:27:02 2009 @@ -0,0 +1,52 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vtst\\.i8} %t | count 2 +; RUN: grep {vtst\\.i16} %t | count 2 +; RUN: grep {vtst\\.i32} %t | count 2 + +define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = and <8 x i8> %tmp1, %tmp2 + %tmp4 = vicmp ne <8 x i8> %tmp3, zeroinitializer + ret <8 x i8> %tmp4 +} + +define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = and <4 x i16> %tmp1, %tmp2 + %tmp4 = vicmp ne <4 x i16> %tmp3, zeroinitializer + ret <4 x i16> %tmp4 +} + +define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = and <2 x i32> %tmp1, %tmp2 + %tmp4 = vicmp ne <2 x i32> %tmp3, zeroinitializer + ret <2 x i32> %tmp4 +} + +define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = and <16 x i8> %tmp1, %tmp2 + %tmp4 = vicmp ne <16 x i8> %tmp3, zeroinitializer + ret <16 x i8> %tmp4 +} + +define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = and <8 x i16> %tmp1, %tmp2 + %tmp4 = vicmp ne <8 x i16> %tmp3, zeroinitializer + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = and <4 x i32> %tmp1, %tmp2 + %tmp4 = vicmp ne <4 x i32> %tmp3, zeroinitializer + ret <4 x i32> %tmp4 +} From gohman at apple.com Mon Jun 22 18:28:56 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 22 Jun 2009 23:28:56 -0000 Subject: [llvm-commits] [llvm] r73920 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/trip-count7.ll Message-ID: <200906222328.n5MNSvhv005966@zion.cs.uiuc.edu> Author: djg Date: Mon Jun 22 18:28:56 2009 New Revision: 73920 URL: http://llvm.org/viewvc/llvm-project?rev=73920&view=rev Log: Fix a bug in the trip-count computation with And/Or. If either of the sides is CouldNotCompute, the resulting exact count must be CouldNotCompute. Added: llvm/trunk/test/Analysis/ScalarEvolution/trip-count7.ll Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=73920&r1=73919&r2=73920&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Jun 22 18:28:56 2009 @@ -2902,10 +2902,8 @@ if (L->contains(TBB)) { // Both conditions must be true for the loop to continue executing. // Choose the less conservative count. - if (BTI0.Exact == CouldNotCompute) - BECount = BTI1.Exact; - else if (BTI1.Exact == CouldNotCompute) - BECount = BTI0.Exact; + if (BTI0.Exact == CouldNotCompute || BTI1.Exact == CouldNotCompute) + BECount = CouldNotCompute; else BECount = getUMinFromMismatchedTypes(BTI0.Exact, BTI1.Exact); if (BTI0.Max == CouldNotCompute) @@ -2936,10 +2934,8 @@ if (L->contains(FBB)) { // Both conditions must be false for the loop to continue executing. // Choose the less conservative count. - if (BTI0.Exact == CouldNotCompute) - BECount = BTI1.Exact; - else if (BTI1.Exact == CouldNotCompute) - BECount = BTI0.Exact; + if (BTI0.Exact == CouldNotCompute || BTI1.Exact == CouldNotCompute) + BECount = CouldNotCompute; else BECount = getUMinFromMismatchedTypes(BTI0.Exact, BTI1.Exact); if (BTI0.Max == CouldNotCompute) Added: llvm/trunk/test/Analysis/ScalarEvolution/trip-count7.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/trip-count7.ll?rev=73920&view=auto ============================================================================== --- llvm/trunk/test/Analysis/ScalarEvolution/trip-count7.ll (added) +++ llvm/trunk/test/Analysis/ScalarEvolution/trip-count7.ll Mon Jun 22 18:28:56 2009 @@ -0,0 +1,150 @@ +; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \ +; RUN: | grep {Loop bb7.i: Unpredictable backedge-taken count\\.} + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" + + %struct.complex = type { float, float } + %struct.element = type { i32, i32 } + %struct.node = type { %struct.node*, %struct.node*, i32 } + at seed = external global i64 ; [#uses=0] + at _2E_str = external constant [18 x i8], align 1 ; <[18 x i8]*> [#uses=0] + at _2E_str1 = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=0] + at value = external global float ; [#uses=0] + at fixed = external global float ; [#uses=0] + at floated = external global float ; [#uses=0] + at permarray = external global [11 x i32], align 32 ; <[11 x i32]*> [#uses=0] + at pctr = external global i32 ; [#uses=0] + at tree = external global %struct.node* ; <%struct.node**> [#uses=0] + at stack = external global [4 x i32], align 16 ; <[4 x i32]*> [#uses=0] + at cellspace = external global [19 x %struct.element], align 32 ; <[19 x %struct.element]*> [#uses=0] + at freelist = external global i32 ; [#uses=0] + at movesdone = external global i32 ; [#uses=0] + at ima = external global [41 x [41 x i32]], align 32 ; <[41 x [41 x i32]]*> [#uses=0] + at imb = external global [41 x [41 x i32]], align 32 ; <[41 x [41 x i32]]*> [#uses=0] + at imr = external global [41 x [41 x i32]], align 32 ; <[41 x [41 x i32]]*> [#uses=0] + at rma = external global [41 x [41 x float]], align 32 ; <[41 x [41 x float]]*> [#uses=0] + at rmb = external global [41 x [41 x float]], align 32 ; <[41 x [41 x float]]*> [#uses=0] + at rmr = external global [41 x [41 x float]], align 32 ; <[41 x [41 x float]]*> [#uses=0] + at piececount = external global [4 x i32], align 16 ; <[4 x i32]*> [#uses=0] + at class = external global [13 x i32], align 32 ; <[13 x i32]*> [#uses=0] + at piecemax = external global [13 x i32], align 32 ; <[13 x i32]*> [#uses=0] + at puzzl = external global [512 x i32], align 32 ; <[512 x i32]*> [#uses=0] + at p = external global [13 x [512 x i32]], align 32 ; <[13 x [512 x i32]]*> [#uses=0] + at n = external global i32 ; [#uses=0] + at kount = external global i32 ; [#uses=0] + at sortlist = external global [5001 x i32], align 32 ; <[5001 x i32]*> [#uses=0] + at biggest = external global i32 ; [#uses=0] + at littlest = external global i32 ; [#uses=0] + at top = external global i32 ; [#uses=0] + at z = external global [257 x %struct.complex], align 32 ; <[257 x %struct.complex]*> [#uses=0] + at w = external global [257 x %struct.complex], align 32 ; <[257 x %struct.complex]*> [#uses=0] + at e = external global [130 x %struct.complex], align 32 ; <[130 x %struct.complex]*> [#uses=0] + at zr = external global float ; [#uses=0] + at zi = external global float ; [#uses=0] + +declare void @Initrand() nounwind + +declare i32 @Rand() nounwind + +declare void @Try(i32, i32*, i32*, i32*, i32*, i32*) nounwind + +declare i32 @puts(i8* nocapture) nounwind + +declare void @Queens(i32) nounwind + +declare i32 @printf(i8* nocapture, ...) nounwind + +declare i32 @main() nounwind + +declare void @Doit() nounwind + +declare void @Doit_bb7([15 x i32]*, [17 x i32]*, [9 x i32]*) nounwind + +define void @Doit_bb7_2E_i([9 x i32]* %x1, [15 x i32]* %c, [17 x i32]* %b, [9 x i32]* %a, i32* %q, i32* %x1.sub, i32* %b9, i32* %a10, i32* %c11) nounwind { +newFuncRoot: + br label %bb7.i + +Try.exit.exitStub: ; preds = %bb7.i + ret void + +bb.i: ; preds = %bb7.i + %tmp = add i32 %j.0.i, 1 ; [#uses=5] + store i32 0, i32* %q, align 4 + %tmp1 = sext i32 %tmp to i64 ; [#uses=1] + %tmp2 = getelementptr [9 x i32]* %a, i64 0, i64 %tmp1 ; [#uses=1] + %tmp3 = load i32* %tmp2, align 4 ; [#uses=1] + %tmp4 = icmp eq i32 %tmp3, 0 ; [#uses=1] + br i1 %tmp4, label %bb.i.bb7.i.backedge_crit_edge, label %bb1.i + +bb1.i: ; preds = %bb.i + %tmp5 = add i32 %j.0.i, 2 ; [#uses=1] + %tmp6 = sext i32 %tmp5 to i64 ; [#uses=1] + %tmp7 = getelementptr [17 x i32]* %b, i64 0, i64 %tmp6 ; [#uses=1] + %tmp8 = load i32* %tmp7, align 4 ; [#uses=1] + %tmp9 = icmp eq i32 %tmp8, 0 ; [#uses=1] + br i1 %tmp9, label %bb1.i.bb7.i.backedge_crit_edge, label %bb2.i + +bb2.i: ; preds = %bb1.i + %tmp10 = sub i32 7, %j.0.i ; [#uses=1] + %tmp11 = sext i32 %tmp10 to i64 ; [#uses=1] + %tmp12 = getelementptr [15 x i32]* %c, i64 0, i64 %tmp11 ; [#uses=1] + %tmp13 = load i32* %tmp12, align 4 ; [#uses=1] + %tmp14 = icmp eq i32 %tmp13, 0 ; [#uses=1] + br i1 %tmp14, label %bb2.i.bb7.i.backedge_crit_edge, label %bb3.i + +bb3.i: ; preds = %bb2.i + %tmp15 = getelementptr [9 x i32]* %x1, i64 0, i64 1 ; [#uses=1] + store i32 %tmp, i32* %tmp15, align 4 + %tmp16 = sext i32 %tmp to i64 ; [#uses=1] + %tmp17 = getelementptr [9 x i32]* %a, i64 0, i64 %tmp16 ; [#uses=1] + store i32 0, i32* %tmp17, align 4 + %tmp18 = add i32 %j.0.i, 2 ; [#uses=1] + %tmp19 = sext i32 %tmp18 to i64 ; [#uses=1] + %tmp20 = getelementptr [17 x i32]* %b, i64 0, i64 %tmp19 ; [#uses=1] + store i32 0, i32* %tmp20, align 4 + %tmp21 = sub i32 7, %j.0.i ; [#uses=1] + %tmp22 = sext i32 %tmp21 to i64 ; [#uses=1] + %tmp23 = getelementptr [15 x i32]* %c, i64 0, i64 %tmp22 ; [#uses=1] + store i32 0, i32* %tmp23, align 4 + call void @Try(i32 2, i32* %q, i32* %b9, i32* %a10, i32* %c11, i32* %x1.sub) nounwind + %tmp24 = load i32* %q, align 4 ; [#uses=1] + %tmp25 = icmp eq i32 %tmp24, 0 ; [#uses=1] + br i1 %tmp25, label %bb5.i, label %bb3.i.bb7.i.backedge_crit_edge + +bb5.i: ; preds = %bb3.i + %tmp26 = sext i32 %tmp to i64 ; [#uses=1] + %tmp27 = getelementptr [9 x i32]* %a, i64 0, i64 %tmp26 ; [#uses=1] + store i32 1, i32* %tmp27, align 4 + %tmp28 = add i32 %j.0.i, 2 ; [#uses=1] + %tmp29 = sext i32 %tmp28 to i64 ; [#uses=1] + %tmp30 = getelementptr [17 x i32]* %b, i64 0, i64 %tmp29 ; [#uses=1] + store i32 1, i32* %tmp30, align 4 + %tmp31 = sub i32 7, %j.0.i ; [#uses=1] + %tmp32 = sext i32 %tmp31 to i64 ; [#uses=1] + %tmp33 = getelementptr [15 x i32]* %c, i64 0, i64 %tmp32 ; [#uses=1] + store i32 1, i32* %tmp33, align 4 + br label %bb7.i.backedge + +bb7.i.backedge: ; preds = %bb3.i.bb7.i.backedge_crit_edge, %bb2.i.bb7.i.backedge_crit_edge, %bb1.i.bb7.i.backedge_crit_edge, %bb.i.bb7.i.backedge_crit_edge, %bb5.i + br label %bb7.i + +bb7.i: ; preds = %bb7.i.backedge, %newFuncRoot + %j.0.i = phi i32 [ 0, %newFuncRoot ], [ %tmp, %bb7.i.backedge ] ; [#uses=8] + %tmp34 = load i32* %q, align 4 ; [#uses=1] + %tmp35 = icmp eq i32 %tmp34, 0 ; [#uses=1] + %tmp36 = icmp ne i32 %j.0.i, 8 ; [#uses=1] + %tmp37 = and i1 %tmp35, %tmp36 ; [#uses=1] + br i1 %tmp37, label %bb.i, label %Try.exit.exitStub + +bb.i.bb7.i.backedge_crit_edge: ; preds = %bb.i + br label %bb7.i.backedge + +bb1.i.bb7.i.backedge_crit_edge: ; preds = %bb1.i + br label %bb7.i.backedge + +bb2.i.bb7.i.backedge_crit_edge: ; preds = %bb2.i + br label %bb7.i.backedge + +bb3.i.bb7.i.backedge_crit_edge: ; preds = %bb3.i + br label %bb7.i.backedge +} From resistor at mac.com Mon Jun 22 18:37:06 2009 From: resistor at mac.com (Owen Anderson) Date: Mon, 22 Jun 2009 23:37:06 -0000 Subject: [llvm-commits] [llvm] r73923 - in /llvm/trunk: include/llvm/Support/Timer.h lib/Support/Timer.cpp Message-ID: <200906222337.n5MNb6BE006248@zion.cs.uiuc.edu> Author: resistor Date: Mon Jun 22 18:37:06 2009 New Revision: 73923 URL: http://llvm.org/viewvc/llvm-project?rev=73923&view=rev Log: Add guards around timer groups, which can be shared. Modified: llvm/trunk/include/llvm/Support/Timer.h llvm/trunk/lib/Support/Timer.cpp Modified: llvm/trunk/include/llvm/Support/Timer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Timer.h?rev=73923&r1=73922&r2=73923&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Timer.h (original) +++ llvm/trunk/include/llvm/Support/Timer.h Mon Jun 22 18:37:06 2009 @@ -152,6 +152,7 @@ unsigned NumTimers; std::vector TimersToPrint; public: + TimerGroup() : Name("Miscellaneous Ungrouped Timers"), NumTimers(0) {} explicit TimerGroup(const std::string &name) : Name(name), NumTimers(0) {} ~TimerGroup() { assert(NumTimers == 0 && Modified: llvm/trunk/lib/Support/Timer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=73923&r1=73922&r2=73923&view=diff ============================================================================== --- llvm/trunk/lib/Support/Timer.cpp (original) +++ llvm/trunk/lib/Support/Timer.cpp Mon Jun 22 18:37:06 2009 @@ -15,6 +15,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/Streams.h" +#include "llvm/System/Mutex.h" #include "llvm/System/Process.h" #include #include @@ -50,25 +51,28 @@ cl::Hidden, cl::location(getLibSupportInfoOutputFilename())); } -static TimerGroup *DefaultTimerGroup = 0; +static ManagedStatic > TimerLock; +static ManagedStatic DefaultTimerGroup; static TimerGroup *getDefaultTimerGroup() { - if (DefaultTimerGroup) return DefaultTimerGroup; - return DefaultTimerGroup = new TimerGroup("Miscellaneous Ungrouped Timers"); + return &*DefaultTimerGroup; } Timer::Timer(const std::string &N) : Elapsed(0), UserTime(0), SystemTime(0), MemUsed(0), PeakMem(0), Name(N), Started(false), TG(getDefaultTimerGroup()) { + sys::SmartScopedLock Lock(&*TimerLock); TG->addTimer(); } Timer::Timer(const std::string &N, TimerGroup &tg) : Elapsed(0), UserTime(0), SystemTime(0), MemUsed(0), PeakMem(0), Name(N), Started(false), TG(&tg) { + sys::SmartScopedLock Lock(&*TimerLock); TG->addTimer(); } Timer::Timer(const Timer &T) { + sys::SmartScopedLock Lock(&*TimerLock); TG = T.TG; if (TG) TG->addTimer(); operator=(T); @@ -77,6 +81,7 @@ // Copy ctor, initialize with no TG member. Timer::Timer(bool, const Timer &T) { + sys::SmartScopedLock Lock(&*TimerLock); TG = T.TG; // Avoid assertion in operator= operator=(T); // Copy contents TG = 0; @@ -84,6 +89,7 @@ Timer::~Timer() { + sys::SmartScopedLock Lock(&*TimerLock); if (TG) { if (Started) { Started = false; @@ -129,8 +135,10 @@ } static ManagedStatic > ActiveTimers; +static ManagedStatic > ActiveTimerLock; void Timer::startTimer() { + sys::SmartScopedLock Lock(&*ActiveTimerLock); Started = true; ActiveTimers->push_back(this); TimeRecord TR = getTimeRecord(true); @@ -142,6 +150,7 @@ } void Timer::stopTimer() { + sys::SmartScopedLock Lock(&*ActiveTimerLock); TimeRecord TR = getTimeRecord(false); Elapsed += TR.Elapsed; UserTime += TR.UserTime; @@ -171,6 +180,7 @@ /// currently active timers, which will be printed when the timer group prints /// void Timer::addPeakMemoryMeasurement() { + sys::SmartScopedLock Lock(&*ActiveTimerLock); size_t MemUsed = getMemUsage(); for (std::vector::iterator I = ActiveTimers->begin(), @@ -193,7 +203,10 @@ static ManagedStatic NamedGroupedTimers; +static ManagedStatic > NamedTimerLock; + static Timer &getNamedRegionTimer(const std::string &Name) { + sys::SmartScopedLock Lock(&*NamedTimerLock); Name2Timer::iterator I = NamedTimers->find(Name); if (I != NamedTimers->end()) return I->second; @@ -203,6 +216,7 @@ static Timer &getNamedRegionTimer(const std::string &Name, const std::string &GroupName) { + sys::SmartScopedLock Lock(&*NamedTimerLock); Name2Pair::iterator I = NamedGroupedTimers->find(GroupName); if (I == NamedGroupedTimers->end()) { @@ -340,7 +354,7 @@ // If this is not an collection of ungrouped times, print the total time. // Ungrouped timers don't really make sense to add up. We still print the // TOTAL line to make the percentages make sense. - if (this != DefaultTimerGroup) { + if (this != &*DefaultTimerGroup) { *OutStream << " Total Execution Time: "; printAlignedFP(Total.getProcessTime(), 4, 5, *OutStream); @@ -377,11 +391,5 @@ if (OutStream != cerr.stream() && OutStream != cout.stream()) delete OutStream; // Close the file... } - - // Delete default timer group! - if (NumTimers == 0 && this == DefaultTimerGroup) { - delete DefaultTimerGroup; - DefaultTimerGroup = 0; - } } From resistor at mac.com Mon Jun 22 19:02:39 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 00:02:39 -0000 Subject: [llvm-commits] [llvm] r73925 - /llvm/trunk/lib/Support/PluginLoader.cpp Message-ID: <200906230002.n5N02dP0007066@zion.cs.uiuc.edu> Author: resistor Date: Mon Jun 22 19:02:39 2009 New Revision: 73925 URL: http://llvm.org/viewvc/llvm-project?rev=73925&view=rev Log: Guard the plugin loader. Modified: llvm/trunk/lib/Support/PluginLoader.cpp Modified: llvm/trunk/lib/Support/PluginLoader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/PluginLoader.cpp?rev=73925&r1=73924&r2=73925&view=diff ============================================================================== --- llvm/trunk/lib/Support/PluginLoader.cpp (original) +++ llvm/trunk/lib/Support/PluginLoader.cpp Mon Jun 22 19:02:39 2009 @@ -16,13 +16,16 @@ #include "llvm/Support/PluginLoader.h" #include "llvm/Support/Streams.h" #include "llvm/System/DynamicLibrary.h" +#include "llvm/System/Mutex.h" #include #include using namespace llvm; static ManagedStatic > Plugins; +static ManagedStatic > PluginsLock; void PluginLoader::operator=(const std::string &Filename) { + sys::SmartScopedLock Lock(&*PluginsLock); std::string Error; if (sys::DynamicLibrary::LoadLibraryPermanently(Filename.c_str(), &Error)) { cerr << "Error opening '" << Filename << "': " << Error @@ -33,10 +36,12 @@ } unsigned PluginLoader::getNumPlugins() { + sys::SmartScopedLock Lock(&*PluginsLock); return Plugins.isConstructed() ? Plugins->size() : 0; } std::string &PluginLoader::getPlugin(unsigned num) { + sys::SmartScopedLock Lock(&*PluginsLock); assert(Plugins.isConstructed() && num < Plugins->size() && "Asking for an out of bounds plugin"); return (*Plugins)[num]; From deeppatel1987 at gmail.com Mon Jun 22 19:15:21 2009 From: deeppatel1987 at gmail.com (Sandeep Patel) Date: Mon, 22 Jun 2009 17:15:21 -0700 Subject: [llvm-commits] [llvm] r73919 - in /llvm/trunk: include/llvm/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ test/CodeGen/ARM/ In-Reply-To: <200906222327.n5MNR6TB005894@zion.cs.uiuc.edu> References: <200906222327.n5MNR6TB005894@zion.cs.uiuc.edu> Message-ID: <305d6f60906221715r1adfafd6rde652f7d4df0c68f@mail.gmail.com> This is excellent! At first glance, I notice that the AAPCS-VFP case is wrong in ARMCallingConv.td. It needs a CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>> in there for both calls and rets. deep -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090622/66a6dc7b/attachment.html From resistor at mac.com Mon Jun 22 19:21:15 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 00:21:15 -0000 Subject: [llvm-commits] [llvm] r73928 - /llvm/trunk/lib/Target/TargetData.cpp Message-ID: <200906230021.n5N0LFmd007646@zion.cs.uiuc.edu> Author: resistor Date: Mon Jun 22 19:21:15 2009 New Revision: 73928 URL: http://llvm.org/viewvc/llvm-project?rev=73928&view=rev Log: Guard the layout info object. Modified: llvm/trunk/lib/Target/TargetData.cpp Modified: llvm/trunk/lib/Target/TargetData.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetData.cpp?rev=73928&r1=73927&r2=73928&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetData.cpp (original) +++ llvm/trunk/lib/Target/TargetData.cpp Mon Jun 22 19:21:15 2009 @@ -23,6 +23,7 @@ #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/ManagedStatic.h" +#include "llvm/System/Mutex.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/StringExtras.h" #include @@ -345,11 +346,13 @@ } static ManagedStatic LayoutInfo; +static ManagedStatic > LayoutLock; TargetData::~TargetData() { if (!LayoutInfo.isConstructed()) return; + sys::SmartScopedLock Lock(&*LayoutLock); // Remove any layouts for this TD. LayoutInfoTy &TheMap = *LayoutInfo; for (LayoutInfoTy::iterator I = TheMap.begin(), E = TheMap.end(); I != E; ) { @@ -366,6 +369,7 @@ const StructLayout *TargetData::getStructLayout(const StructType *Ty) const { LayoutInfoTy &TheMap = *LayoutInfo; + sys::SmartScopedLock Lock(&*LayoutLock); StructLayout *&SL = TheMap[LayoutKey(this, Ty)]; if (SL) return SL; @@ -390,6 +394,7 @@ void TargetData::InvalidateStructLayoutInfo(const StructType *Ty) const { if (!LayoutInfo.isConstructed()) return; // No cache. + sys::SmartScopedLock Lock(&*LayoutLock); LayoutInfoTy::iterator I = LayoutInfo->find(LayoutKey(this, Ty)); if (I == LayoutInfo->end()) return; From sabre at nondot.org Mon Jun 22 19:24:36 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 23 Jun 2009 00:24:36 -0000 Subject: [llvm-commits] [llvm] r73929 - /llvm/trunk/tools/llvm-mc/AsmLexer.cpp Message-ID: <200906230024.n5N0Oa9K007754@zion.cs.uiuc.edu> Author: lattner Date: Mon Jun 22 19:24:36 2009 New Revision: 73929 URL: http://llvm.org/viewvc/llvm-project?rev=73929&view=rev Log: get a definition of strull on windows, thanks to Howard Su. Modified: llvm/trunk/tools/llvm-mc/AsmLexer.cpp Modified: llvm/trunk/tools/llvm-mc/AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmLexer.cpp?rev=73929&r1=73928&r2=73929&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmLexer.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmLexer.cpp Mon Jun 22 19:24:36 2009 @@ -14,6 +14,7 @@ #include "AsmLexer.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/MemoryBuffer.h" +#include "llvm/Config/config.h" // for strtoull. #include #include #include From clattner at apple.com Mon Jun 22 19:24:48 2009 From: clattner at apple.com (Chris Lattner) Date: Mon, 22 Jun 2009 17:24:48 -0700 Subject: [llvm-commits] [llvm] r73855 - in /llvm/trunk/tools/llvm-mc: AsmLexer.cpp AsmLexer.h llvm-mc.cpp In-Reply-To: References: <200906211921.n5LJLQtY025612@zion.cs.uiuc.edu> Message-ID: On Jun 21, 2009, at 11:40 PM, Howard Su wrote: > the magic is that TGLexer include config.h. there is a definition: > /* Define to a function implementing strtoull */ > #define strtoull _strtoui64 Fixed in r73929, thanks! -Chris From bob.wilson at apple.com Mon Jun 22 20:47:27 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 22 Jun 2009 18:47:27 -0700 Subject: [llvm-commits] [llvm] r73919 - in /llvm/trunk: include/llvm/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ test/CodeGen/ARM/ In-Reply-To: <305d6f60906221715r1adfafd6rde652f7d4df0c68f@mail.gmail.com> References: <200906222327.n5MNR6TB005894@zion.cs.uiuc.edu> <305d6f60906221715r1adfafd6rde652f7d4df0c68f@mail.gmail.com> Message-ID: Yes, I hadn't gotten to that yet. I wanted to get this change committed anyway so that it will be possible to collaborate on things like that. If you have time to review the calling convention changes, I would appreciate it. I had to rework things a bit to handle vector arguments and return values. Sent from my iPhone On Jun 22, 2009, at 5:15 PM, Sandeep Patel wrote: > This is excellent! > > At first glance, I notice that the AAPCS-VFP case is wrong in > ARMCallingConv.td. It needs a CCIfType<[v2f64], CCAssignToReg<[Q0, > Q1, Q2, Q3]>> in there for both calls and rets. > > deep > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Mon Jun 22 23:19:40 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 23 Jun 2009 04:19:40 -0000 Subject: [llvm-commits] [llvm] r73942 - /llvm/tags/Apple/llvmCore-2114/ Message-ID: <200906230419.n5N4JeGL015845@zion.cs.uiuc.edu> Author: void Date: Mon Jun 22 23:19:39 2009 New Revision: 73942 URL: http://llvm.org/viewvc/llvm-project?rev=73942&view=rev Log: Creating llvmCore-2114 branch Added: llvm/tags/Apple/llvmCore-2114/ - copied from r73941, llvm/branches/Apple/Bender/ From isanbard at gmail.com Mon Jun 22 23:19:49 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 23 Jun 2009 04:19:49 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r73943 - /llvm-gcc-4.2/tags/Apple/llvmgcc42-2114/ Message-ID: <200906230419.n5N4JnO5015865@zion.cs.uiuc.edu> Author: void Date: Mon Jun 22 23:19:48 2009 New Revision: 73943 URL: http://llvm.org/viewvc/llvm-project?rev=73943&view=rev Log: Creating llvmgcc42-2114 branch Added: llvm-gcc-4.2/tags/Apple/llvmgcc42-2114/ - copied from r73942, llvm-gcc-4.2/branches/Apple/Bender/ From bruno.cardoso at gmail.com Mon Jun 22 23:39:27 2009 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 23 Jun 2009 04:39:27 -0000 Subject: [llvm-commits] [llvm] r73944 - in /llvm/trunk/lib/CodeGen: ELFWriter.cpp ELFWriter.h Message-ID: <200906230439.n5N4dRF9016491@zion.cs.uiuc.edu> Author: bruno Date: Mon Jun 22 23:39:27 2009 New Revision: 73944 URL: http://llvm.org/viewvc/llvm-project?rev=73944&view=rev Log: Use a default alignment for data and bss sections. Only pad when the section size > 0 and move the code that deals with globals initializers to a place we know for sure the global is initialized. Modified: llvm/trunk/lib/CodeGen/ELFWriter.cpp llvm/trunk/lib/CodeGen/ELFWriter.h Modified: llvm/trunk/lib/CodeGen/ELFWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.cpp?rev=73944&r1=73943&r2=73944&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.cpp Mon Jun 22 23:39:27 2009 @@ -159,10 +159,6 @@ unsigned Flags = S->getFlags(); unsigned SectionType = ELFSection::SHT_PROGBITS; unsigned SHdrFlags = ELFSection::SHF_ALLOC; - const TargetData *TD = TM.getTargetData(); - unsigned Align = TD->getPreferredAlignment(GV); - Constant *CV = GV->getInitializer(); - DOUT << "Section " << S->getName() << " for global " << GV->getName() << "\n"; // If this is an external global, the symbol does not have a section. @@ -171,6 +167,10 @@ return getNullSection(); } + const TargetData *TD = TM.getTargetData(); + unsigned Align = TD->getPreferredAlignment(GV); + Constant *CV = GV->getInitializer(); + if (Flags & SectionFlags::Code) SHdrFlags |= ELFSection::SHF_EXECINSTR; if (Flags & SectionFlags::Writeable) @@ -192,6 +192,7 @@ GV->hasCommonLinkage()) { Sym.SectionIdx = ELFSection::SHN_COMMON; Sym.IsCommon = true; + ElfS.Align = 1; return ElfS; } Sym.IsBss = true; @@ -218,19 +219,21 @@ void ELFWriter::EmitGlobalVar(const GlobalVariable *GV) { unsigned SymBind = getGlobalELFLinkage(GV); + unsigned Align=0, Size=0; ELFSym GblSym(GV); GblSym.setBind(SymBind); - if (GV->hasInitializer()) + if (GV->hasInitializer()) { GblSym.setType(ELFSym::STT_OBJECT); - else + const TargetData *TD = TM.getTargetData(); + Align = TD->getPreferredAlignment(GV); + Size = TD->getTypeAllocSize(GV->getInitializer()->getType()); + GblSym.Size = Size; + } else { GblSym.setType(ELFSym::STT_NOTYPE); + } ELFSection &GblSection = getGlobalSymELFSection(GV, GblSym); - const TargetData *TD = TM.getTargetData(); - unsigned Align = TD->getPreferredAlignment(GV); - unsigned Size = TD->getTypeAllocSize(GV->getInitializer()->getType()); - GblSym.Size = Size; if (GblSym.IsCommon) { GblSym.Value = Align; @@ -598,7 +601,7 @@ /// section names. void ELFWriter::EmitSectionTableStringTable() { // First step: add the section for the string table to the list of sections: - ELFSection &SHStrTab = getSection(".shstrtab", ELFSection::SHT_STRTAB, 0); + ELFSection &SHStrTab = getSectionHeaderStringTableSection(); // Now that we know which section number is the .shstrtab section, update the // e_shstrndx entry in the ELF header. @@ -684,13 +687,12 @@ << ", SectionData Size: " << S.size() << "\n"; // Align FileOff to whatever the alignment restrictions of the section are. - if (S.Align) { - for (size_t NewFileOff = (FileOff+S.Align-1) & ~(S.Align-1); - FileOff != NewFileOff; ++FileOff) - O << (char)0xAB; - } - if (S.size()) { + if (S.Align) { + for (size_t NewFileOff = (FileOff+S.Align-1) & ~(S.Align-1); + FileOff != NewFileOff; ++FileOff) + O << (char)0xAB; + } O.write((char *)&S.getData()[0], S.Size); FileOff += S.Size; } Modified: llvm/trunk/lib/CodeGen/ELFWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.h?rev=73944&r1=73943&r2=73944&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.h (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.h Mon Jun 22 23:39:27 2009 @@ -171,14 +171,18 @@ return getSection(".strtab", ELFSection::SHT_STRTAB, 0, 1); } + ELFSection &getSectionHeaderStringTableSection() { + return getSection(".shstrtab", ELFSection::SHT_STRTAB, 0, 1); + } + ELFSection &getDataSection() { return getSection(".data", ELFSection::SHT_PROGBITS, - ELFSection::SHF_WRITE | ELFSection::SHF_ALLOC); + ELFSection::SHF_WRITE | ELFSection::SHF_ALLOC, 4); } ELFSection &getBSSSection() { return getSection(".bss", ELFSection::SHT_NOBITS, - ELFSection::SHF_WRITE | ELFSection::SHF_ALLOC); + ELFSection::SHF_WRITE | ELFSection::SHF_ALLOC, 4); } ELFSection &getNullSection() { From evan.cheng at apple.com Tue Jun 23 00:23:49 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 05:23:49 -0000 Subject: [llvm-commits] [llvm] r73947 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <200906230523.n5N5NnVn017929@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jun 23 00:23:49 2009 New Revision: 73947 URL: http://llvm.org/viewvc/llvm-project?rev=73947&view=rev Log: Replace isTwoAddress with operand constraint. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=73947&r1=73946&r2=73947&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jun 23 00:23:49 2009 @@ -160,7 +160,7 @@ [(set GPR:$dst, imm0_65535:$src)]>, Requires<[HasThumb2]>; -let isTwoAddress = 1 in +let Constraints = "$src = $dst" in def tMOVTi16 : PseudoInst<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), "movt $dst, $imm", [(set GPR:$dst, (or (and GPR:$src, 0xffff), From evan.cheng at apple.com Tue Jun 23 00:25:29 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 05:25:29 -0000 Subject: [llvm-commits] [llvm] r73948 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <200906230525.n5N5PTJG017989@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jun 23 00:25:29 2009 New Revision: 73948 URL: http://llvm.org/viewvc/llvm-project?rev=73948&view=rev Log: Minor reorg. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=73948&r1=73947&r2=73948&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jun 23 00:25:29 2009 @@ -524,6 +524,24 @@ } } // isNotDuplicable = 1 + +// LEApcrel - Load a pc-relative address into a register without offending the +// assembler. +def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo, + !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", + "${:private}PCRELL${:uid}+8))\n"), + !strconcat("${:private}PCRELL${:uid}:\n\t", + "add$p $dst, pc, #PCRELV${:uid}")), + []>; + +def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p), + Pseudo, + !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", + "${:private}PCRELL${:uid}+8))\n"), + !strconcat("${:private}PCRELL${:uid}:\n\t", + "add$p $dst, pc, #PCRELV${:uid}")), + []>; + //===----------------------------------------------------------------------===// // Control Flow Instructions. // @@ -1276,23 +1294,6 @@ RegConstraint<"$false = $dst">, UnaryDP; -// LEApcrel - Load a pc-relative address into a register without offending the -// assembler. -def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo, - !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", - "${:private}PCRELL${:uid}+8))\n"), - !strconcat("${:private}PCRELL${:uid}:\n\t", - "add$p $dst, pc, #PCRELV${:uid}")), - []>; - -def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p), - Pseudo, - !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", - "${:private}PCRELL${:uid}+8))\n"), - !strconcat("${:private}PCRELL${:uid}:\n\t", - "add$p $dst, pc, #PCRELV${:uid}")), - []>; - //===----------------------------------------------------------------------===// // TLS Instructions // From nicholas at mxc.ca Tue Jun 23 00:42:33 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 22 Jun 2009 22:42:33 -0700 Subject: [llvm-commits] [llvm] r73906 - in /llvm/trunk: include/llvm/Analysis/IVUsers.h include/llvm/Analysis/LoopVR.h include/llvm/Analysis/ScalarEvolution.h include/llvm/Analysis/ScalarEvolutionExpander.h include/llvm/Analysis/ScalarEvolutionExpressions.h lib/Analysis/IVUsers.cpp lib/Analysis/LoopVR.cpp lib/Analysis/ScalarEvolution.cpp lib/Analysis/ScalarEvolutionExpander.cpp lib/Transforms/Scalar/IndVarSimplify.cpp lib/Transforms/Scalar/LoopDeletion.cpp lib/Transforms/Scalar/LoopStrengthReduce.cpp In-Reply-To: <200906222139.n5MLdpeN001941@zion.cs.uiuc.edu> References: <200906222139.n5MLdpeN001941@zion.cs.uiuc.edu> Message-ID: <4A406B49.7050404@mxc.ca> Owen Anderson wrote: > Author: resistor > Date: Mon Jun 22 16:39:50 2009 > New Revision: 73906 > > URL: http://llvm.org/viewvc/llvm-project?rev=73906&view=rev > Log: > SCEVHandle is no more! Yay!! Thank you, Owen! Nick > > Modified: > llvm/trunk/include/llvm/Analysis/IVUsers.h > llvm/trunk/include/llvm/Analysis/LoopVR.h > llvm/trunk/include/llvm/Analysis/ScalarEvolution.h > llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h > llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpressions.h > llvm/trunk/lib/Analysis/IVUsers.cpp > llvm/trunk/lib/Analysis/LoopVR.cpp > llvm/trunk/lib/Analysis/ScalarEvolution.cpp > llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp > llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp > llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp > llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp > > Modified: llvm/trunk/include/llvm/Analysis/IVUsers.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/IVUsers.h?rev=73906&r1=73905&r2=73906&view=diff From sabre at nondot.org Tue Jun 23 00:57:07 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 23 Jun 2009 05:57:07 -0000 Subject: [llvm-commits] [llvm] r73950 - in /llvm/trunk/tools/llvm-mc: AsmLexer.cpp AsmLexer.h AsmParser.cpp AsmParser.h Message-ID: <200906230557.n5N5v8He018982@zion.cs.uiuc.edu> Author: lattner Date: Tue Jun 23 00:57:07 2009 New Revision: 73950 URL: http://llvm.org/viewvc/llvm-project?rev=73950&view=rev Log: implement a trivial binary expression parser, we can now parse all of 176.gcc.llc.s Modified: llvm/trunk/tools/llvm-mc/AsmLexer.cpp llvm/trunk/tools/llvm-mc/AsmLexer.h llvm/trunk/tools/llvm-mc/AsmParser.cpp llvm/trunk/tools/llvm-mc/AsmParser.h Modified: llvm/trunk/tools/llvm-mc/AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmLexer.cpp?rev=73950&r1=73949&r2=73950&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmLexer.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmLexer.cpp Tue Jun 23 00:57:07 2009 @@ -75,17 +75,18 @@ while (isalnum(*CurPtr) || *CurPtr == '_' || *CurPtr == '$' || *CurPtr == '.' || *CurPtr == '@') ++CurPtr; - CurStrVal.assign(TokStart, CurPtr); // Include % + CurStrVal.assign(TokStart, CurPtr); return asmtok::Identifier; } /// LexPercent: Register: %[a-zA-Z0-9]+ asmtok::TokKind AsmLexer::LexPercent() { if (!isalnum(*CurPtr)) - return ReturnError(TokStart, "invalid register name"); + return asmtok::Percent; // Single %. + while (isalnum(*CurPtr)) ++CurPtr; - CurStrVal.assign(TokStart, CurPtr); // Skip % + CurStrVal.assign(TokStart, CurPtr); // Include % return asmtok::Register; } @@ -243,6 +244,10 @@ case '*': return asmtok::Star; case ',': return asmtok::Comma; case '$': return asmtok::Dollar; + case '|': return asmtok::Pipe; + case '^': return asmtok::Caret; + case '&': return asmtok::Amp; + case '!': return asmtok::Exclaim; case '%': return LexPercent(); case '/': return LexSlash(); case '#': return LexHash(); @@ -250,6 +255,20 @@ case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': return LexDigit(); + case '<': + if (*CurPtr == '<') { + ++CurPtr; + return asmtok::LessLess; + } + // Don't have any use for bare '<' yet. + return ReturnError(TokStart, "invalid character in input"); + case '>': + if (*CurPtr == '>') { + ++CurPtr; + return asmtok::GreaterGreater; + } + // Don't have any use for bare '>' yet. + return ReturnError(TokStart, "invalid character in input"); // TODO: Quoted identifiers (objc methods etc) // local labels: [0-9][:] Modified: llvm/trunk/tools/llvm-mc/AsmLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmLexer.h?rev=73950&r1=73949&r2=73950&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmLexer.h (original) +++ llvm/trunk/tools/llvm-mc/AsmLexer.h Tue Jun 23 00:57:07 2009 @@ -42,7 +42,10 @@ Plus, Minus, Tilde, Slash, // '/' LParen, RParen, - Star, Comma, Dollar + Star, Comma, Dollar, + + Pipe, Caret, Amp, Exclaim, + Percent, LessLess, GreaterGreater }; } Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=73950&r1=73949&r2=73950&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Tue Jun 23 00:57:07 2009 @@ -168,7 +168,9 @@ // memory operand consumed. } else { // It must be an parenthesized expression, parse it now. - if (ParseParenExpr(Disp)) return true; + if (ParseParenExpr(Disp) || + ParseBinOpRHS(1, Disp)) + return true; // After parsing the base expression we could either have a parenthesized // memory address or not. If not, return now. If so, eat the (. @@ -274,9 +276,61 @@ /// expr ::= primaryexpr /// bool AsmParser::ParseExpression(int64_t &Res) { - return ParsePrimaryExpr(Res); + return ParsePrimaryExpr(Res) || + ParseBinOpRHS(1, Res); } - + +static unsigned getBinOpPrecedence(asmtok::TokKind K) { + switch (K) { + default: return 0; // not a binop. + case asmtok::Plus: + case asmtok::Minus: + return 1; + case asmtok::Pipe: + case asmtok::Caret: + case asmtok::Amp: + case asmtok::Exclaim: + return 2; + case asmtok::Star: + case asmtok::Slash: + case asmtok::Percent: + case asmtok::LessLess: + case asmtok::GreaterGreater: + return 3; + } +} + + +/// ParseBinOpRHS - Parse all binary operators with precedence >= 'Precedence'. +/// Res contains the LHS of the expression on input. +bool AsmParser::ParseBinOpRHS(unsigned Precedence, int64_t &Res) { + while (1) { + unsigned TokPrec = getBinOpPrecedence(Lexer.getKind()); + + // If the next token is lower precedence than we are allowed to eat, return + // successfully with what we ate already. + if (TokPrec < Precedence) + return false; + + //asmtok::TokKind BinOp = Lexer.getKind(); + Lexer.Lex(); + + // Eat the next primary expression. + int64_t RHS; + if (ParsePrimaryExpr(RHS)) return true; + + // If BinOp binds less tightly with RHS than the operator after RHS, let + // the pending operator take RHS as its LHS. + unsigned NextTokPrec = getBinOpPrecedence(Lexer.getKind()); + if (TokPrec < NextTokPrec) { + if (ParseBinOpRHS(Precedence+1, RHS)) return true; + } + + // Merge LHS/RHS: fixme use the right operator etc. + Res += RHS; + } +} + Modified: llvm/trunk/tools/llvm-mc/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.h?rev=73950&r1=73949&r2=73950&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.h (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.h Tue Jun 23 00:57:07 2009 @@ -40,6 +40,7 @@ bool ParseX86MemOperand(X86Operand &Op); bool ParseExpression(int64_t &Res); bool ParsePrimaryExpr(int64_t &Res); + bool ParseBinOpRHS(unsigned Precedence, int64_t &Res); bool ParseParenExpr(int64_t &Res); }; From anton at korobeynikov.info Tue Jun 23 01:08:13 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 23 Jun 2009 10:08:13 +0400 Subject: [llvm-commits] [llvm] r73947 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td In-Reply-To: <200906230523.n5N5NnVn017929@zion.cs.uiuc.edu> References: <200906230523.n5N5NnVn017929@zion.cs.uiuc.edu> Message-ID: Hello, Evan > Replace isTwoAddress with operand constraint. I thought we tend to use instruction flags, but not operand constraints, no? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From evan.cheng at apple.com Tue Jun 23 01:24:15 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 22 Jun 2009 23:24:15 -0700 Subject: [llvm-commits] [llvm] r73947 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td In-Reply-To: References: <200906230523.n5N5NnVn017929@zion.cs.uiuc.edu> Message-ID: <0DABE55A-4149-4982-8A3F-629D10C7001C@apple.com> On Jun 22, 2009, at 11:08 PM, Anton Korobeynikov wrote: > Hello, Evan > >> Replace isTwoAddress with operand constraint. > I thought we tend to use instruction flags, but not operand > constraints, no? I am not sure what you mean. isTwoAddress is an operand constraint that's deprecated. It's tying up operands 0 and 1. Evan > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State > University > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Tue Jun 23 01:26:46 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 22 Jun 2009 23:26:46 -0700 Subject: [llvm-commits] [llvm] r73622 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp test/CodeGen/ARM/thumb2-add.ll test/CodeGen/ARM/thumb2-mov.ll test/CodeGen/ARM/thumb2-mov2.ll test/CodeGen/ARM/thumb2-shifter.ll In-Reply-To: <200906171814.n5HIE08Q030499@zion.cs.uiuc.edu> References: <200906171814.n5HIE08Q030499@zion.cs.uiuc.edu> Message-ID: <9C82CDEC-DAA6-4976-8F84-9CEB9D10C74A@apple.com> On Jun 17, 2009, at 11:13 AM, Anton Korobeynikov wrote: > > +// > = > = > = > ----------------------------------------------------------------------= > ==// > +// Move Instructions. > +// > +def tMOVi16 : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), > + "mov $dst, $src", > + [(set GPR:$dst, imm0_65535:$src)]>, > + Requires<[HasThumb2]>; > + > +let isTwoAddress = 1 in > +def tMOVTi16 : PseudoInst<(outs GPR:$dst), (ins GPR:$src, i32imm: > $imm), > + "movt $dst, $imm", > + [(set GPR:$dst, (or (and GPR:$src, 0xffff), > + imm16high:$imm))]>, > + Requires<[HasThumb2]>; > + > +def : Pat<(and (or GPR:$src, imm16high:$imm1), imm16high0xffff: > $imm2), > + (tMOVTi16 GPR:$src, (HI16 imm16high:$imm1))>, > + Requires<[HasThumb2]>; I don't get this pattern. Can you explain? Evan > + > +def : Pat<(i32 imm:$imm), > + (tMOVTi16 (tMOVi16 (LO16 imm:$imm)),(HI16 imm:$imm))>, > + Requires<[HasThumb2]>; > + > +// > = > = > = > ----------------------------------------------------------------------= > ==// > +// Arithmetic Instructions. > +// > +defm t2ADD : T2I_bin_irs <"add", BinOpFrag<(add node:$LHS, node: > $RHS)>>; > +defm t2SUB : T2I_bin_irs <"sub", BinOpFrag<(sub node:$LHS, node: > $RHS)>>; > + > +def tADDri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm: > $rhs), > + "add $dst, $lhs, $rhs", > + [(set GPR:$dst, (add GPR:$lhs, > imm0_4095:$rhs))]>, > + Requires<[HasThumb2]>; > +def tSUBri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm: > $rhs), > + "sub $dst, $lhs, $rhs", > + [(set GPR:$dst, (add GPR:$lhs, > imm0_4095_neg:$rhs))]>, > + Requires<[HasThumb2]>; > + > +defm t2ADDS : T2I_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node: > $RHS)>>; > +defm t2SUBS : T2I_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node: > $RHS)>>; > + > +defm t2ADC : T2I_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node: > $RHS)>>; > +defm t2SBC : T2I_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node: > $RHS)>>; > + > + > +def tMLS : PseudoInst<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), > + "mls $dst, $a, $b, $c", > + [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR: > $b)))]>, > + Requires<[HasThumb2]>; > + > +def tORNrs : PseudoInst<(outs GPR:$dst), (ins GPR:$src1, t2_so_reg: > $src2), > + "orn $dst, $src1, $src2", > + [(set GPR:$dst, (or GPR:$src1, (not > t2_so_reg: $src2)))]>, > + Requires<[HasThumb2]>; > > Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=73622&r1=73621&r2=73622&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Wed Jun > 17 13:13:58 2009 > @@ -97,6 +97,7 @@ > const char *Modifier = 0); > void printSOImmOperand(const MachineInstr *MI, int opNum); > void printSOImm2PartOperand(const MachineInstr *MI, int opNum); > + void printSOOperand(const MachineInstr *MI, int OpNum); > void printSORegOperand(const MachineInstr *MI, int opNum); > void printAddrMode2Operand(const MachineInstr *MI, int OpNo); > void printAddrMode2OffsetOperand(const MachineInstr *MI, int > OpNo); > @@ -396,6 +397,28 @@ > printSOImm(O, ARM_AM::getSOImmVal(V2), VerboseAsm, TAI); > } > > +// Constant shifts so_reg is a 3-operand unit corresponding to > register forms of > +// the A5.1 "Addressing Mode 1 - Data-processing operands" forms. > This > +// includes: > +// REG 0 - e.g. R5 > +// REG IMM, SH_OPC - e.g. R5, LSL #3 > +void ARMAsmPrinter::printSOOperand(const MachineInstr *MI, int > OpNum) { > + const MachineOperand &MO1 = MI->getOperand(OpNum); > + const MachineOperand &MO2 = MI->getOperand(OpNum+1); > + > + unsigned Reg = MO1.getReg(); > + assert(TargetRegisterInfo::isPhysicalRegister(Reg)); > + O << TM.getRegisterInfo()->getAsmName(Reg); > + > + // Print the shift opc. > + O << ", " > + << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())) > + << " "; > + > + assert(MO2.isImm() && "Not a valid t2_so_reg value!"); > + O << "#" << ARM_AM::getSORegOffset(MO2.getImm()); > +} > + > // so_reg is a 4-operand unit corresponding to register forms of the > A5.1 > // "Addressing Mode 1 - Data-processing operands" forms. This > includes: > // REG 0 0 - e.g. R5 > > Added: llvm/trunk/test/CodeGen/ARM/thumb2-add.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-add.ll?rev=73622&view=auto > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/test/CodeGen/ARM/thumb2-add.ll (added) > +++ llvm/trunk/test/CodeGen/ARM/thumb2-add.ll Wed Jun 17 13:13:58 2009 > @@ -0,0 +1,50 @@ > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | > grep #255 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | > grep #256 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | > grep #257 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | > grep #4094 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | > grep #4095 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | > grep #4096 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | > grep lsl | grep #8 > + > +define i32 @t2ADDrc_255(i32 %lhs) { > + %Rd = add i32 %lhs, 255; > + ret i32 %Rd > +} > + > +define i32 @t2ADDrc_256(i32 %lhs) { > + %Rd = add i32 %lhs, 256; > + ret i32 %Rd > +} > + > +define i32 @t2ADDrc_257(i32 %lhs) { > + %Rd = add i32 %lhs, 257; > + ret i32 %Rd > +} > + > +define i32 @t2ADDrc_4094(i32 %lhs) { > + %Rd = add i32 %lhs, 4094; > + ret i32 %Rd > +} > + > +define i32 @t2ADDrc_4095(i32 %lhs) { > + %Rd = add i32 %lhs, 4095; > + ret i32 %Rd > +} > + > +define i32 @t2ADDrc_4096(i32 %lhs) { > + %Rd = add i32 %lhs, 4096; > + ret i32 %Rd > +} > + > +define i32 @t2ADDrr(i32 %lhs, i32 %rhs) { > + %Rd = add i32 %lhs, %rhs; > + ret i32 %Rd > +} > + > +define i32 @t2ADDrs(i32 %lhs, i32 %rhs) { > + %tmp = shl i32 %rhs, 8 > + %Rd = add i32 %lhs, %tmp; > + ret i32 %Rd > +} > + > > Added: llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll?rev=73622&view=auto > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll (added) > +++ llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll Wed Jun 17 13:13:58 2009 > @@ -0,0 +1,127 @@ > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep > #11206827 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep > #2868947712 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep > #2880154539 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep > #251658240 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #3948544 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #258 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep > #4026531840 > + > +; Test # > + > +; var 2.1 - 0x00ab00ab > +define i32 @t2_const_var2_1_ok_1(i32 %lhs) { > + %ret = add i32 %lhs, 11206827 ; 0x00ab00ab > + ret i32 %ret > +} > + > +define i32 @t2_const_var2_1_fail_1(i32 %lhs) { > + %ret = add i32 %lhs, 11206843 ; 0x00ab00bb > + ret i32 %ret > +} > + > +define i32 @t2_const_var2_1_fail_2(i32 %lhs) { > + %ret = add i32 %lhs, 27984043 ; 0x01ab00ab > + ret i32 %ret > +} > + > +define i32 @t2_const_var2_1_fail_3(i32 %lhs) { > + %ret = add i32 %lhs, 27984299 ; 0x01ab01ab > + ret i32 %ret > +} > + > +define i32 @t2_const_var2_1_fail_4(i32 %lhs) { > + %ret = add i32 %lhs, 28027649 ; 0x01abab01 > + ret i32 %ret > +} > + > +; var 2.2 - 0xab00ab00 > +define i32 @t2_const_var2_2_ok_1(i32 %lhs) { > + %ret = add i32 %lhs, 2868947712 ; 0xab00ab00 > + ret i32 %ret > +} > + > +define i32 @t2_const_var2_2_fail_1(i32 %lhs) { > + %ret = add i32 %lhs, 2868951552 ; 0xab00ba00 > + ret i32 %ret > +} > + > +define i32 @t2_const_var2_2_fail_2(i32 %lhs) { > + %ret = add i32 %lhs, 2868947728 ; 0xab00ab10 > + ret i32 %ret > +} > + > +define i32 @t2_const_var2_2_fail_3(i32 %lhs) { > + %ret = add i32 %lhs, 2869996304 ; 0xab10ab10 > + ret i32 %ret > +} > + > +define i32 @t2_const_var2_2_fail_4(i32 %lhs) { > + %ret = add i32 %lhs, 279685904 ; 0x10abab10 > + ret i32 %ret > +} > + > +; var 2.3 - 0xabababab > +define i32 @t2_const_var2_3_ok_1(i32 %lhs) { > + %ret = add i32 %lhs, 2880154539 ; 0xabababab > + ret i32 %ret > +} > + > +define i32 @t2_const_var2_3_fail_1(i32 %lhs) { > + %ret = add i32 %lhs, 2880154554 ; 0xabababba > + ret i32 %ret > +} > + > +define i32 @t2_const_var2_3_fail_2(i32 %lhs) { > + %ret = add i32 %lhs, 2880158379 ; 0xababbaab > + ret i32 %ret > +} > + > +define i32 @t2_const_var2_3_fail_3(i32 %lhs) { > + %ret = add i32 %lhs, 2881137579 ; 0xabbaabab > + ret i32 %ret > +} > + > +define i32 @t2_const_var2_3_fail_4(i32 %lhs) { > + %ret = add i32 %lhs, 3131812779 ; 0xbaababab > + ret i32 %ret > +} > + > +; var 3 - 0x0F000000 > +define i32 @t2_const_var3_1_ok_1(i32 %lhs) { > + %ret = add i32 %lhs, 251658240 ; 0x0F000000 > + ret i32 %ret > +} > + > +define i32 @t2_const_var3_2_ok_1(i32 %lhs) { > + %ret = add i32 %lhs, 3948544 ; 0b00000000001111000100000000000000 > + ret i32 %ret > +} > + > +define i32 @t2_const_var3_2_fail_1(i32 %lhs) { > + %ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000 > + ret i32 %ret > +} > + > +define i32 @t2_const_var3_3_ok_1(i32 %lhs) { > + %ret = add i32 %lhs, 258 ; 0b00000000000000000000000100000010 > + ret i32 %ret > +} > + > +define i32 @t2_const_var3_4_ok_1(i32 %lhs) { > + %ret = add i32 %lhs, 4026531840 ; 0xF0000000 > + ret i32 %ret > +} > + > > Added: llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll?rev=73622&view=auto > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll (added) > +++ llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll Wed Jun 17 13:13:58 > 2009 > @@ -0,0 +1,65 @@ > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | > grep #1234 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | > grep #1234 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | > grep #1234 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | > grep #1234 > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | > grep movt > + > +define i32 @t2MOVTi16_ok_1(i32 %a) { > + %1 = and i32 %a, 65535 > + %2 = shl i32 1234, 16 > + %3 = or i32 %1, %2 > + > + ret i32 %3 > +} > + > +define i32 @t2MOVTi16_test_1(i32 %a) { > + %1 = shl i32 255, 8 > + %2 = shl i32 1234, 8 > + %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 > + %4 = shl i32 %2, 8 ; This gives us (1234 << 16) in %4 > + %5 = and i32 %a, %3 > + %6 = or i32 %4, %5 > + > + ret i32 %6 > +} > + > +define i32 @t2MOVTi16_test_2(i32 %a) { > + %1 = shl i32 255, 8 > + %2 = shl i32 1234, 8 > + %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 > + %4 = shl i32 %2, 6 > + %5 = and i32 %a, %3 > + %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6 > + %7 = or i32 %5, %6 > + > + ret i32 %7 > +} > + > +define i32 @t2MOVTi16_test_3(i32 %a) { > + %1 = shl i32 255, 8 > + %2 = shl i32 1234, 8 > + %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 > + %4 = shl i32 %2, 6 > + %5 = and i32 %a, %3 > + %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6 > + %7 = lshr i32 %6, 6 > + %8 = shl i32 %7, 6 > + %9 = or i32 %5, %8 > + > + ret i32 %9 > +} > + > +define i32 @t2MOVTi16_test_nomatch_1(i32 %a) { > + %1 = shl i32 255, 8 > + %2 = shl i32 1234, 8 > + %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 > + %4 = shl i32 %2, 6 > + %5 = and i32 %a, %3 > + %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6 > + %7 = lshr i32 %6, 3 > + %8 = or i32 %5, %7 > + > + ret i32 %8 > +} > + > + > > Added: llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll?rev=73622&view=auto > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll (added) > +++ llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll Wed Jun 17 > 13:13:58 2009 > @@ -0,0 +1,40 @@ > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsl > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsr > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep asr > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ror > +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov > + > +define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) { > + %A = shl i32 %Y, 16 > + %B = add i32 %X, %A > + ret i32 %B > +} > + > +define i32 @t2ADDrs_lsr(i32 %X, i32 %Y) { > + %A = lshr i32 %Y, 16 > + %B = add i32 %X, %A > + ret i32 %B > +} > + > +define i32 @t2ADDrs_asr(i32 %X, i32 %Y) { > + %A = ashr i32 %Y, 16 > + %B = add i32 %X, %A > + ret i32 %B > +} > + > +; i32 ror(n) = (x >> n) | (x << (32 - n)) > +define i32 @t2ADDrs_ror(i32 %X, i32 %Y) { > + %A = lshr i32 %Y, 16 > + %B = shl i32 %Y, 16 > + %C = or i32 %B, %A > + %R = add i32 %X, %C > + ret i32 %R > +} > + > +define i32 @t2ADDrs_noRegShift(i32 %X, i32 %Y, i8 %sh) { > + %shift.upgrd.1 = zext i8 %sh to i32 > + %A = shl i32 %Y, %shift.upgrd.1 > + %B = add i32 %X, %A > + ret i32 %B > +} > + > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From anton at korobeynikov.info Tue Jun 23 01:36:11 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 23 Jun 2009 10:36:11 +0400 Subject: [llvm-commits] [llvm] r73622 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp test/CodeGen/ARM/thumb2-add.ll test/CodeGen/ARM/thumb2-m Message-ID: Hi Evan >> +def : Pat<(and (or GPR:$src, imm16high:$imm1), imm16high0xffff: >> $imm2), >> + ? ? ? ? ?(tMOVTi16 GPR:$src, (HI16 imm16high:$imm1))>, >> + ? ? ? ? Requires<[HasThumb2]>; > > I don't get this pattern. Can you explain? Dag combiner replaces the original operation sequence (or (and reg, 0xFFFF), (shl imm, 16)) with (and (or reg, (shl imm, 16)), (or 0xFFFF, (shl imm16, 16))). We're catching this case here. There are movt tests there. Try to disable the pattern and see, what will happen. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From nicolas.geoffray at lip6.fr Tue Jun 23 01:46:23 2009 From: nicolas.geoffray at lip6.fr (Nicolas Geoffray) Date: Tue, 23 Jun 2009 08:46:23 +0200 Subject: [llvm-commits] [llvm] r73884 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp In-Reply-To: <4C2B85B9-3509-478D-B758-D479B949E079@apple.com> References: <200906221509.n5MF9TjU008035@zion.cs.uiuc.edu> <4A3FF9C9.4050308@lip6.fr> <4C2B85B9-3509-478D-B758-D479B949E079@apple.com> Message-ID: <4A407A3F.1080404@lip6.fr> It works, thanks very much Dan! Nicolas Dan Gohman wrote: > Hi Nicholas, > > Thanks for the report. I submitted a fix in r73908. > > Dan > > On Jun 22, 2009, at 2:38 PM, Nicolas Geoffray wrote: > > > >> Hi Dan, >> >> I believe this patch is responsible for the bug highlighted by the >> attached (bugpoint reduced) test-case. Older revisions compile the >> test case correclty. >> >> FYI, here's what I get when llc'ing the file (arch=x86 OS=linux): >> >> >> llc: /home/ngeoffray/project/llvm-svn/llvm/include/llvm/ADT/APInt.h: >> 216: llvm::APInt::APInt(unsigned int, uint64_t, bool): Assertion >> `BitWidth && "bitwidth too small"' failed. >> 0 llc 0x08beb5c8 >> Stack dump: >> 0. Program arguments: ../llvm/Release/bin/llc -march=x86 bugpoint- >> reduced-simplified.bc >> 1. Running pass 'Loop Pass Manager' on function >> '@JnJVM_antlr_CSharpCodeGenerator_genBitSet__Lantlr_collections_impl_BitSet_2I >> ' >> 2. Running pass 'Loop Strength Reduction' on basic block '%"GOTO >> or IF*6"' >> >> Would you like me to open a PR? >> >> Nicolas >> >> > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From evan.cheng at apple.com Tue Jun 23 02:03:47 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 00:03:47 -0700 Subject: [llvm-commits] [llvm] r73622 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp test/CodeGen/ARM/thumb2-add.ll test/CodeGen/ARM/thumb2-m In-Reply-To: References: Message-ID: On Jun 22, 2009, at 11:36 PM, Anton Korobeynikov wrote: > Hi Evan > >>> +def : Pat<(and (or GPR:$src, imm16high:$imm1), imm16high0xffff: >>> $imm2), >>> + (tMOVTi16 GPR:$src, (HI16 imm16high:$imm1))>, >>> + Requires<[HasThumb2]>; >> >> I don't get this pattern. Can you explain? > Dag combiner replaces the original operation sequence (or (and reg, > 0xFFFF), (shl imm, 16)) with (and (or reg, (shl imm, 16)), (or 0xFFFF, > (shl imm16, 16))). We're catching this case here. There are movt tests > there. Try to disable the pattern and see, what will happen. Sorry, I am being dense. What are the relationships between imm1 and imm2? How come the result instruction doesn't use imm2 at all? Evan > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State > University > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sanjiv.gupta at microchip.com Tue Jun 23 02:10:20 2009 From: sanjiv.gupta at microchip.com (Sanjiv Gupta) Date: Tue, 23 Jun 2009 07:10:20 -0000 Subject: [llvm-commits] [llvm] r73953 - /llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Message-ID: <200906230710.n5N7AKrE021356@zion.cs.uiuc.edu> Author: sgupta Date: Tue Jun 23 02:10:19 2009 New Revision: 73953 URL: http://llvm.org/viewvc/llvm-project?rev=73953&view=rev Log: Fold the add (ptr, offset) into ptr[offset] only if the offset is small enough. movwi and moviw allow value of 5-bits only (i.e. 32). Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=73953&r1=73952&r2=73953&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Tue Jun 23 02:10:19 2009 @@ -702,10 +702,12 @@ if (Ptr.getOpcode() == ISD::ADD) { SDValue OperLeft = Ptr.getOperand(0); SDValue OperRight = Ptr.getOperand(1); - if (OperLeft.getOpcode() == ISD::Constant) { + if ((OperLeft.getOpcode() == ISD::Constant) && + (dyn_cast(OperLeft)->getZExtValue() < 32 )) { Offset = dyn_cast(OperLeft)->getZExtValue(); Ptr = OperRight; - } else if (OperRight.getOpcode() == ISD::Constant) { + } else if ((OperRight.getOpcode() == ISD::Constant) && + (dyn_cast(OperRight)->getZExtValue() < 32 )){ Offset = dyn_cast(OperRight)->getZExtValue(); Ptr = OperLeft; } From anton at korobeynikov.info Tue Jun 23 02:12:02 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 23 Jun 2009 11:12:02 +0400 Subject: [llvm-commits] [llvm] r73622 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp test/CodeGen/ARM/thumb2-add.ll test/CodeGen/ARM/thumb2-m In-Reply-To: References: Message-ID: Hi, Evan >>>> +def : Pat<(and (or GPR:$src, imm16high:$imm1), imm16high0xffff: >>>> $imm2), >>>> + ? ? ? ? ?(tMOVTi16 GPR:$src, (HI16 imm16high:$imm1))>, >>>> + ? ? ? ? Requires<[HasThumb2]>; >>> >>> I don't get this pattern. Can you explain? >> Dag combiner replaces the original operation sequence (or (and reg, >> 0xFFFF), (shl imm, 16)) with (and (or reg, (shl imm, 16)), (or 0xFFFF, >> (shl imm16, 16))). We're catching this case here. There are movt tests >> there. Try to disable the pattern and see, what will happen. > > Sorry, I am being dense. What are the relationships between imm1 and > imm2? How come the result instruction doesn't use imm2 at all? Imm's are just imm parts of the op sequence I mentioned before. imm1 is actually (shl imm, 16) and imm2 is (or 0xFFFF, (shl imm, 16)). We don't need both since we can recover the imm from top 16 bits either imm1 or imm2. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From evan.cheng at apple.com Tue Jun 23 02:15:09 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 00:15:09 -0700 Subject: [llvm-commits] [llvm] r73622 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp test/CodeGen/ARM/thumb2-add.ll test/CodeGen/ARM/thumb2-m In-Reply-To: References: Message-ID: On Jun 23, 2009, at 12:12 AM, Anton Korobeynikov wrote: > Hi, Evan > >>>>> +def : Pat<(and (or GPR:$src, imm16high:$imm1), imm16high0xffff: >>>>> $imm2), >>>>> + (tMOVTi16 GPR:$src, (HI16 imm16high:$imm1))>, >>>>> + Requires<[HasThumb2]>; >>>> >>>> I don't get this pattern. Can you explain? >>> Dag combiner replaces the original operation sequence (or (and reg, >>> 0xFFFF), (shl imm, 16)) with (and (or reg, (shl imm, 16)), (or >>> 0xFFFF, >>> (shl imm16, 16))). We're catching this case here. There are movt >>> tests >>> there. Try to disable the pattern and see, what will happen. >> >> Sorry, I am being dense. What are the relationships between imm1 and >> imm2? How come the result instruction doesn't use imm2 at all? > Imm's are just imm parts of the op sequence I mentioned before. imm1 > is actually (shl imm, 16) and imm2 is (or 0xFFFF, (shl imm, 16)). We > don't need both since we can recover the imm from top 16 bits either > imm1 or imm2. While this pattern is no doubt matching what you have in mind, it seems like it will match a lot more then it's intended. It can match imm2 that's any immediate with low 16-bits all one. It doesn't have to have any connection with the other immediate. Evan > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State > University > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From anton at korobeynikov.info Tue Jun 23 02:18:47 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 23 Jun 2009 11:18:47 +0400 Subject: [llvm-commits] [llvm] r73622 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp test/CodeGen/ARM/thumb2-add.ll test/CodeGen/ARM/thumb2-m In-Reply-To: References: Message-ID: Hi, Evan > While this pattern is no doubt matching what you have in mind, it > seems like it will match a lot more then it's intended. It can match > imm2 that's any immediate with low 16-bits all one. It doesn't have to > have any connection with the other immediate. Nice catch, right! How one would match the mentioned case then? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From evan.cheng at apple.com Tue Jun 23 02:21:09 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 00:21:09 -0700 Subject: [llvm-commits] [llvm] r73622 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp test/CodeGen/ARM/thumb2-add.ll test/CodeGen/ARM/thumb2-m In-Reply-To: References: Message-ID: <83A2FBA7-029D-460D-8673-46B9B134BB67@apple.com> On Jun 23, 2009, at 12:18 AM, Anton Korobeynikov wrote: > Hi, Evan > >> While this pattern is no doubt matching what you have in mind, it >> seems like it will match a lot more then it's intended. It can match >> imm2 that's any immediate with low 16-bits all one. It doesn't have >> to >> have any connection with the other immediate. > Nice catch, right! How one would match the mentioned case then? Let's not worry about missing cases now. I'll try to fix up these as much as I can. I'm trying to get the basic stuff right first. Evan > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State > University > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From anton at korobeynikov.info Tue Jun 23 02:27:21 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 23 Jun 2009 11:27:21 +0400 Subject: [llvm-commits] [llvm] r73622 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp test/CodeGen/ARM/thumb2-add.ll test/CodeGen/ARM/thumb2-m In-Reply-To: <83A2FBA7-029D-460D-8673-46B9B134BB67@apple.com> References: <83A2FBA7-029D-460D-8673-46B9B134BB67@apple.com> Message-ID: Hi, Evan > Let's not worry about missing cases now. I'll try to fix up these as > much as I can. I'm trying to get the basic stuff right first. Ok. Then it would make sense to disable this pattern. Since primary use of movt is constants... -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From evan.cheng at apple.com Tue Jun 23 02:30:13 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 00:30:13 -0700 Subject: [llvm-commits] [llvm] r73622 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp test/CodeGen/ARM/thumb2-add.ll test/CodeGen/ARM/thumb2-m In-Reply-To: References: <83A2FBA7-029D-460D-8673-46B9B134BB67@apple.com> Message-ID: I am doing a round of fix up and consolidation. I'll xfail patterns that fail and then move on from there. Evan On Jun 23, 2009, at 12:27 AM, Anton Korobeynikov wrote: > Hi, Evan > >> Let's not worry about missing cases now. I'll try to fix up these as >> much as I can. I'm trying to get the basic stuff right first. > Ok. Then it would make sense to disable this pattern. Since primary > use of movt is constants... > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State > University > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Tue Jun 23 03:39:00 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 23 Jun 2009 10:39:00 +0200 Subject: [llvm-commits] [llvm] r73900 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp In-Reply-To: <200906222059.n5MKx8ch000455@zion.cs.uiuc.edu> References: <200906222059.n5MKx8ch000455@zion.cs.uiuc.edu> Message-ID: <4A4094A4.2050502@free.fr> Hi Dale, > + if (TLI.isTypeLegal(VT)) { > + Value = DAG.getLoad(VT, dl, Chain, > + getMemBasePlusOffset(Src, SrcOff, DAG), > + SrcSV, SrcSVOff + SrcOff, false, Align); > + Store = DAG.getStore(Chain, dl, Value, > + getMemBasePlusOffset(Dst, DstOff, DAG), > + DstSV, DstSVOff + DstOff, false, DstAlign); > + } else { > + MVT NVT = VT; > + while (!TLI.isTypeLegal(NVT)) { > + NVT = (MVT::SimpleValueType(NVT.getSimpleVT() + 1)); > + } > + Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain, > + getMemBasePlusOffset(Src, SrcOff, DAG), > + SrcSV, SrcSVOff + SrcOff, VT, false, Align); > + Store = DAG.getTruncStore(Chain, dl, Value, > + getMemBasePlusOffset(Dst, DstOff, DAG), > + DstSV, DstSVOff + DstOff, VT, false, DstAlign); > + } rather than looping over simple value types, how about using getTypeToTransformTo? This also allows you to unify the two cases: if VT is legal then NVT = getTypeToTransformTo(VT) will return VT, and in this case getExtLoad and getTruncStore will create an ordinary load and store. I think you should also add an assertion that NVT.bitsGE(VT). Ciao, Duncan. From baldrick at free.fr Tue Jun 23 03:42:33 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 23 Jun 2009 10:42:33 +0200 Subject: [llvm-commits] [llvm] r73866 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/trip-count5.ll In-Reply-To: <68CA9891-6478-4C94-B124-9E39BF54B381@apple.com> References: <200906220032.n5M0W3ic002321@zion.cs.uiuc.edu> <4A3F3899.3030808@free.fr> <68CA9891-6478-4C94-B124-9E39BF54B381@apple.com> Message-ID: <4A409579.5090207@free.fr> Hi Dan, >> thanks for doing this. Does the loop unroller make any use of it? >> The loop in PR2624 is still not unrolled for example. > > I believe LLVM's current loop unroller only works if an > exact trip count is known. If ScalarEvolution finds the > trip count is either 1 or 2, the loop won't be unrolled. in the testcase scalar evolution finds that the trip count is 3 for the backedge. Perhaps the unroller skips loops with more than one exit. Ciao, Duncan. From edwintorok at gmail.com Tue Jun 23 10:18:22 2009 From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=) Date: Tue, 23 Jun 2009 18:18:22 +0300 Subject: [llvm-commits] [llvm] r73892 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h include/llvm/Analysis/ScalarEvolutionExpressions.h lib/Analysis/ScalarEvolution.cpp In-Reply-To: <906D3F87-341B-4265-BD72-A0CA8ACBCA7E@apple.com> References: <200906221826.n5MIQ0oT027484@zion.cs.uiuc.edu> <4A3FCF1B.3000207@gmail.com> <906D3F87-341B-4265-BD72-A0CA8ACBCA7E@apple.com> Message-ID: <4A40F23E.6080406@gmail.com> On 2009-06-23 00:26, Dan Gohman wrote: > On Jun 22, 2009, at 11:36 AM, T?r?k Edwin wrote: > > > >> On 2009-06-22 21:25, Owen Anderson wrote: >> >> >>> Author: resistor >>> >>> Date: Mon Jun 22 13:25:46 2009 >>> >>> New Revision: 73892 >>> >>> >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=73892&view=rev >>> >>> Log: >>> >>> Banish global state from ScalarEvolution! SCEV uniquing is now >>> done by tables attached to the ScalarEvolution pass. >>> >>> This also throws out the SCEV reference counting scheme, as the the >>> SCEVs now have a lifetime controlled by the >>> >>> ScalarEvolution pass. >>> >>> >>> >>> Note that SCEVHandle is now a no-op, and will be remove in a future >>> commit. >>> >>> >>> >>> >> Hi Owen, >> >> What if somebody wants to do interprocedural analysis using SCEV >> expressions? >> > > ScalarEvolution is a FunctionPass only because the PassManager > framework doesn't have anything that fits its needs better. > There's nothing Function-oriented about it. > > ScalarEvolution could easily be a ModulePass, except that > JIT codegen wouldn't like it, and that it depends on LoopInfo, > which is a FunctionPass. LoopInfo itself could be a ModulePass, > except it depends on DominatorTree, which, finally, is actually > fairly Function-oriented. > > One option might be to split ScalarEvolution into a base > ScalarEvolution class that manages SCEV objects and does all the > analysis, and a separate ScalarEvolutionFunctionPass class which > inherits from FunctionPass and exposes ScalarEvolution functionality. > Then, as long as there's a way to make it use on-the-fly passes to > get at LoopInfo and/or DominatorTree, there could be a > ScalarEvolutionModulePass. > I was experimenting with an interprocedural SCEV analysis, and it seemed to mostly work, as long as: - I explicitly incremented the refcount to make sure its not going away next time SCEV is rerun (adding SCEVHandle to a vector in my class took care of this) - Make sure there are no stale references in SCEV, for example because LoopInfo was rerun, and SCEV wasn't yet. This was mostly taken care of by the releaseMemory() call on each runFunction() - Doing operations on a SCEVHandle obtained from a previous SCEV run was kind of tricky, since SCEV could easily get confused that I was trying to do operations on something from a previous run To sum up, before the removal of SCEVHandle doing interprocedural analysis with SCEV wasn't easy, and it isn't any easier/harder after the removal of SCEVHandle. I would certainly welcome an easier way to do IPA with SCEVs, but I don't know what the solution for that would be. Having SCEV be a ModulePass would probably solve my problems, but would create problems for those who want to use SCEV from a functionpass, AFAIK mixing modulepasses with functionpasses is not very efficient. > >> Will there be a way to clone SCEV* objects, so that they can live >> longer >> than the current function being analyzed? >> > > SCEV objects are uniquified so that they can be compared by pointer. > Indeed, cloning doesn't make sense then. Best regards, --Edwin From resistor at mac.com Tue Jun 23 11:36:12 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 16:36:12 -0000 Subject: [llvm-commits] [llvm] r73957 - in /llvm/trunk: include/llvm/Support/Timer.h lib/Support/Timer.cpp Message-ID: <200906231636.n5NGaCDm024830@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 23 11:36:10 2009 New Revision: 73957 URL: http://llvm.org/viewvc/llvm-project?rev=73957&view=rev Log: Revert r73923, which broke clang. Modified: llvm/trunk/include/llvm/Support/Timer.h llvm/trunk/lib/Support/Timer.cpp Modified: llvm/trunk/include/llvm/Support/Timer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Timer.h?rev=73957&r1=73956&r2=73957&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Timer.h (original) +++ llvm/trunk/include/llvm/Support/Timer.h Tue Jun 23 11:36:10 2009 @@ -152,7 +152,6 @@ unsigned NumTimers; std::vector TimersToPrint; public: - TimerGroup() : Name("Miscellaneous Ungrouped Timers"), NumTimers(0) {} explicit TimerGroup(const std::string &name) : Name(name), NumTimers(0) {} ~TimerGroup() { assert(NumTimers == 0 && Modified: llvm/trunk/lib/Support/Timer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=73957&r1=73956&r2=73957&view=diff ============================================================================== --- llvm/trunk/lib/Support/Timer.cpp (original) +++ llvm/trunk/lib/Support/Timer.cpp Tue Jun 23 11:36:10 2009 @@ -15,7 +15,6 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/Streams.h" -#include "llvm/System/Mutex.h" #include "llvm/System/Process.h" #include #include @@ -51,28 +50,25 @@ cl::Hidden, cl::location(getLibSupportInfoOutputFilename())); } -static ManagedStatic > TimerLock; -static ManagedStatic DefaultTimerGroup; +static TimerGroup *DefaultTimerGroup = 0; static TimerGroup *getDefaultTimerGroup() { - return &*DefaultTimerGroup; + if (DefaultTimerGroup) return DefaultTimerGroup; + return DefaultTimerGroup = new TimerGroup("Miscellaneous Ungrouped Timers"); } Timer::Timer(const std::string &N) : Elapsed(0), UserTime(0), SystemTime(0), MemUsed(0), PeakMem(0), Name(N), Started(false), TG(getDefaultTimerGroup()) { - sys::SmartScopedLock Lock(&*TimerLock); TG->addTimer(); } Timer::Timer(const std::string &N, TimerGroup &tg) : Elapsed(0), UserTime(0), SystemTime(0), MemUsed(0), PeakMem(0), Name(N), Started(false), TG(&tg) { - sys::SmartScopedLock Lock(&*TimerLock); TG->addTimer(); } Timer::Timer(const Timer &T) { - sys::SmartScopedLock Lock(&*TimerLock); TG = T.TG; if (TG) TG->addTimer(); operator=(T); @@ -81,7 +77,6 @@ // Copy ctor, initialize with no TG member. Timer::Timer(bool, const Timer &T) { - sys::SmartScopedLock Lock(&*TimerLock); TG = T.TG; // Avoid assertion in operator= operator=(T); // Copy contents TG = 0; @@ -89,7 +84,6 @@ Timer::~Timer() { - sys::SmartScopedLock Lock(&*TimerLock); if (TG) { if (Started) { Started = false; @@ -135,10 +129,8 @@ } static ManagedStatic > ActiveTimers; -static ManagedStatic > ActiveTimerLock; void Timer::startTimer() { - sys::SmartScopedLock Lock(&*ActiveTimerLock); Started = true; ActiveTimers->push_back(this); TimeRecord TR = getTimeRecord(true); @@ -150,7 +142,6 @@ } void Timer::stopTimer() { - sys::SmartScopedLock Lock(&*ActiveTimerLock); TimeRecord TR = getTimeRecord(false); Elapsed += TR.Elapsed; UserTime += TR.UserTime; @@ -180,7 +171,6 @@ /// currently active timers, which will be printed when the timer group prints /// void Timer::addPeakMemoryMeasurement() { - sys::SmartScopedLock Lock(&*ActiveTimerLock); size_t MemUsed = getMemUsage(); for (std::vector::iterator I = ActiveTimers->begin(), @@ -203,10 +193,7 @@ static ManagedStatic NamedGroupedTimers; -static ManagedStatic > NamedTimerLock; - static Timer &getNamedRegionTimer(const std::string &Name) { - sys::SmartScopedLock Lock(&*NamedTimerLock); Name2Timer::iterator I = NamedTimers->find(Name); if (I != NamedTimers->end()) return I->second; @@ -216,7 +203,6 @@ static Timer &getNamedRegionTimer(const std::string &Name, const std::string &GroupName) { - sys::SmartScopedLock Lock(&*NamedTimerLock); Name2Pair::iterator I = NamedGroupedTimers->find(GroupName); if (I == NamedGroupedTimers->end()) { @@ -354,7 +340,7 @@ // If this is not an collection of ungrouped times, print the total time. // Ungrouped timers don't really make sense to add up. We still print the // TOTAL line to make the percentages make sense. - if (this != &*DefaultTimerGroup) { + if (this != DefaultTimerGroup) { *OutStream << " Total Execution Time: "; printAlignedFP(Total.getProcessTime(), 4, 5, *OutStream); @@ -391,5 +377,11 @@ if (OutStream != cerr.stream() && OutStream != cout.stream()) delete OutStream; // Close the file... } + + // Delete default timer group! + if (NumTimers == 0 && this == DefaultTimerGroup) { + delete DefaultTimerGroup; + DefaultTimerGroup = 0; + } } From bob.wilson at apple.com Tue Jun 23 12:03:39 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 23 Jun 2009 17:03:39 -0000 Subject: [llvm-commits] [llvm] r73959 - /llvm/trunk/CREDITS.TXT Message-ID: <200906231703.n5NH3gTm025927@zion.cs.uiuc.edu> Author: bwilson Date: Tue Jun 23 12:03:23 2009 New Revision: 73959 URL: http://llvm.org/viewvc/llvm-project?rev=73959&view=rev Log: Add myself to the list. Modified: llvm/trunk/CREDITS.TXT Modified: llvm/trunk/CREDITS.TXT URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CREDITS.TXT?rev=73959&r1=73958&r2=73959&view=diff ============================================================================== --- llvm/trunk/CREDITS.TXT (original) +++ llvm/trunk/CREDITS.TXT Tue Jun 23 12:03:23 2009 @@ -302,3 +302,7 @@ N: Bill Wendling E: isanbard at gmail.com D: Bunches of stuff + +N: Bob Wilson +E: bob.wilson at acm.org +D: Advanced SIMD (NEON) support in the ARM backend From dgregor at apple.com Tue Jun 23 12:21:48 2009 From: dgregor at apple.com (Douglas Gregor) Date: Tue, 23 Jun 2009 17:21:48 -0000 Subject: [llvm-commits] [llvm] r73961 - in /llvm/trunk: autoconf/configure.ac include/llvm/Config/config.h.cmake include/llvm/Target/TargetSelect.h Message-ID: <200906231721.n5NHLp6w026473@zion.cs.uiuc.edu> Author: dgregor Date: Tue Jun 23 12:21:35 2009 New Revision: 73961 URL: http://llvm.org/viewvc/llvm-project?rev=73961&view=rev Log: Work around build problem with OpenJDK, which defines X86 as a macro. Fixes PR 4427. Patch by Xerxes R?nby! Modified: llvm/trunk/autoconf/configure.ac llvm/trunk/include/llvm/Config/config.h.cmake llvm/trunk/include/llvm/Target/TargetSelect.h Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=73961&r1=73960&r2=73961&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Tue Jun 23 12:21:35 2009 @@ -447,7 +447,8 @@ # If so, define LLVM_NATIVE_ARCH to that LLVM target. for a_target in $TARGETS_TO_BUILD; do if test "$a_target" = "$LLVM_NATIVE_ARCH"; then - AC_DEFINE_UNQUOTED(LLVM_NATIVE_ARCH,$LLVM_NATIVE_ARCH, + LLVM_NATIVE_ARCHTARGET="${LLVM_NATIVE_ARCH}Target" + AC_DEFINE_UNQUOTED(LLVM_NATIVE_ARCH,$LLVM_NATIVE_ARCHTARGET, [LLVM architecture name for the native architecture, if available]) fi done Modified: llvm/trunk/include/llvm/Config/config.h.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.cmake?rev=73961&r1=73960&r2=73961&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.cmake (original) +++ llvm/trunk/include/llvm/Config/config.h.cmake Tue Jun 23 12:21:35 2009 @@ -582,4 +582,4 @@ #cmakedefine strdup ${strdup} /* Native LLVM architecture */ -#cmakedefine LLVM_NATIVE_ARCH ${LLVM_NATIVE_ARCH} +#cmakedefine LLVM_NATIVE_ARCH ${LLVM_NATIVE_ARCH}Target Modified: llvm/trunk/include/llvm/Target/TargetSelect.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelect.h?rev=73961&r1=73960&r2=73961&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSelect.h (original) +++ llvm/trunk/include/llvm/Target/TargetSelect.h Tue Jun 23 12:21:35 2009 @@ -50,9 +50,9 @@ inline bool InitializeNativeTarget() { // If we have a native target, initialize it to ensure it is linked in. #ifdef LLVM_NATIVE_ARCH -#define DoInit2(TARG, MOD) llvm::Initialize ## TARG ## MOD() -#define DoInit(T, M) DoInit2(T, M) - DoInit(LLVM_NATIVE_ARCH, Target); +#define DoInit2(TARG) llvm::Initialize ## TARG () +#define DoInit(T) DoInit2(T) + DoInit(LLVM_NATIVE_ARCH); return false; #undef DoInit #undef DoInit2 From dgregor at apple.com Tue Jun 23 12:22:06 2009 From: dgregor at apple.com (Douglas Gregor) Date: Tue, 23 Jun 2009 17:22:06 -0000 Subject: [llvm-commits] [llvm] r73962 - /llvm/trunk/configure Message-ID: <200906231722.n5NHMANP026494@zion.cs.uiuc.edu> Author: dgregor Date: Tue Jun 23 12:22:05 2009 New Revision: 73962 URL: http://llvm.org/viewvc/llvm-project?rev=73962&view=rev Log: Regenerate configure script Modified: llvm/trunk/configure Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=73962&r1=73961&r2=73962&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Tue Jun 23 12:22:05 2009 @@ -4972,9 +4972,10 @@ # If so, define LLVM_NATIVE_ARCH to that LLVM target. for a_target in $TARGETS_TO_BUILD; do if test "$a_target" = "$LLVM_NATIVE_ARCH"; then + LLVM_NATIVE_ARCHTARGET="${LLVM_NATIVE_ARCH}Target" cat >>confdefs.h <<_ACEOF -#define LLVM_NATIVE_ARCH $LLVM_NATIVE_ARCH +#define LLVM_NATIVE_ARCH $LLVM_NATIVE_ARCHTARGET _ACEOF fi @@ -10628,7 +10629,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext + echo '#line 12776 "configure"' > conftest.$ac_ext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 (eval $ac_compile) 2>&5 ac_status=$? @@ -14490,11 +14491,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:14493: $lt_compile\"" >&5) + (eval echo "\"\$as_me:14494: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:14497: \$? = $ac_status" >&5 + echo "$as_me:14498: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -14758,11 +14759,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:14761: $lt_compile\"" >&5) + (eval echo "\"\$as_me:14762: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:14765: \$? = $ac_status" >&5 + echo "$as_me:14766: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -14862,11 +14863,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:14865: $lt_compile\"" >&5) + (eval echo "\"\$as_me:14866: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:14869: \$? = $ac_status" >&5 + echo "$as_me:14870: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -17314,7 +17315,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5) + (eval echo "\"\$as_me:19786: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:19789: \$? = $ac_status" >&5 + echo "$as_me:19790: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -19886,11 +19887,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:19889: $lt_compile\"" >&5) + (eval echo "\"\$as_me:19890: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:19893: \$? = $ac_status" >&5 + echo "$as_me:19894: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -21456,11 +21457,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21459: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21460: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:21463: \$? = $ac_status" >&5 + echo "$as_me:21464: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -21560,11 +21561,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21563: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21564: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:21567: \$? = $ac_status" >&5 + echo "$as_me:21568: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -23795,11 +23796,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:23798: $lt_compile\"" >&5) + (eval echo "\"\$as_me:23799: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:23802: \$? = $ac_status" >&5 + echo "$as_me:23803: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -24063,11 +24064,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:24066: $lt_compile\"" >&5) + (eval echo "\"\$as_me:24067: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:24070: \$? = $ac_status" >&5 + echo "$as_me:24071: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -24167,11 +24168,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:24170: $lt_compile\"" >&5) + (eval echo "\"\$as_me:24171: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:24174: \$? = $ac_status" >&5 + echo "$as_me:24175: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized From isanbard at gmail.com Tue Jun 23 12:28:44 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 23 Jun 2009 10:28:44 -0700 Subject: [llvm-commits] [llvm] r73959 - /llvm/trunk/CREDITS.TXT In-Reply-To: <200906231703.n5NH3gTm025927@zion.cs.uiuc.edu> References: <200906231703.n5NH3gTm025927@zion.cs.uiuc.edu> Message-ID: <16e5fdf90906231028i5c9f2860g1eb578b54662eb92@mail.gmail.com> NOOOOOOOO!!!!!! How could I lose the coveted last place in the CREDITS file?!?!?!?!!!! ;-) -bw On Tue, Jun 23, 2009 at 10:03 AM, Bob Wilson wrote: > Author: bwilson > Date: Tue Jun 23 12:03:23 2009 > New Revision: 73959 > > URL: http://llvm.org/viewvc/llvm-project?rev=73959&view=rev > Log: > Add myself to the list. > > Modified: > ? ?llvm/trunk/CREDITS.TXT > > Modified: llvm/trunk/CREDITS.TXT > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CREDITS.TXT?rev=73959&r1=73958&r2=73959&view=diff > > ============================================================================== > --- llvm/trunk/CREDITS.TXT (original) > +++ llvm/trunk/CREDITS.TXT Tue Jun 23 12:03:23 2009 > @@ -302,3 +302,7 @@ > ?N: Bill Wendling > ?E: isanbard at gmail.com > ?D: Bunches of stuff > + > +N: Bob Wilson > +E: bob.wilson at acm.org > +D: Advanced SIMD (NEON) support in the ARM backend > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From echristo at apple.com Tue Jun 23 12:29:44 2009 From: echristo at apple.com (Eric Christopher) Date: Tue, 23 Jun 2009 10:29:44 -0700 Subject: [llvm-commits] [llvm] r73959 - /llvm/trunk/CREDITS.TXT In-Reply-To: <16e5fdf90906231028i5c9f2860g1eb578b54662eb92@mail.gmail.com> References: <200906231703.n5NH3gTm025927@zion.cs.uiuc.edu> <16e5fdf90906231028i5c9f2860g1eb578b54662eb92@mail.gmail.com> Message-ID: On Jun 23, 2009, at 10:28 AM, Bill Wendling wrote: > NOOOOOOOO!!!!!! How could I lose the coveted last place in the CREDITS > file?!?!?!?!!!! > > ;-) > You haven't changed your last name to Zapeda yet? :) -eric From resistor at mac.com Tue Jun 23 12:33:45 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 17:33:45 -0000 Subject: [llvm-commits] [llvm] r73963 - /llvm/trunk/lib/Support/Timer.cpp Message-ID: <200906231733.n5NHXkAl026860@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 23 12:33:37 2009 New Revision: 73963 URL: http://llvm.org/viewvc/llvm-project?rev=73963&view=rev Log: Make the lazy initialization of DefaultTimerGroup threadsafe. Modified: llvm/trunk/lib/Support/Timer.cpp Modified: llvm/trunk/lib/Support/Timer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=73963&r1=73962&r2=73963&view=diff ============================================================================== --- llvm/trunk/lib/Support/Timer.cpp (original) +++ llvm/trunk/lib/Support/Timer.cpp Tue Jun 23 12:33:37 2009 @@ -52,8 +52,20 @@ static TimerGroup *DefaultTimerGroup = 0; static TimerGroup *getDefaultTimerGroup() { - if (DefaultTimerGroup) return DefaultTimerGroup; - return DefaultTimerGroup = new TimerGroup("Miscellaneous Ungrouped Timers"); + TimerGroup* tmp = DefaultTimerGroup; + sys::MemoryFence(); + if (!tmp) { + llvm_acquire_global_lock(); + tmp = DefaultTimerGroup; + if (!tmp) { + tmp = new TimerGroup("Miscellaneous Ungrouped Timers"); + sys::MemoryFence(); + DefaultTimerGroup = tmp; + } + llvm_release_global_lock(); + } + + return tmp; } Timer::Timer(const std::string &N) @@ -377,11 +389,5 @@ if (OutStream != cerr.stream() && OutStream != cout.stream()) delete OutStream; // Close the file... } - - // Delete default timer group! - if (NumTimers == 0 && this == DefaultTimerGroup) { - delete DefaultTimerGroup; - DefaultTimerGroup = 0; - } } From isanbard at gmail.com Tue Jun 23 12:35:05 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 23 Jun 2009 10:35:05 -0700 Subject: [llvm-commits] [llvm] r73959 - /llvm/trunk/CREDITS.TXT In-Reply-To: References: <200906231703.n5NH3gTm025927@zion.cs.uiuc.edu> <16e5fdf90906231028i5c9f2860g1eb578b54662eb92@mail.gmail.com> Message-ID: <16e5fdf90906231035k3e716e49u833e14a234e8250a@mail.gmail.com> On Tue, Jun 23, 2009 at 10:29 AM, Eric Christopher wrote: > > On Jun 23, 2009, at 10:28 AM, Bill Wendling wrote: > >> NOOOOOOOO!!!!!! How could I lose the coveted last place in the CREDITS >> file?!?!?!?!!!! >> >> ;-) >> > > You haven't changed your last name to Zapeda yet? :) > Thinking of Zzzandar...Just to be safe. -bw From resistor at mac.com Tue Jun 23 12:39:34 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 17:39:34 -0000 Subject: [llvm-commits] [llvm] r73964 - in /llvm/trunk: include/llvm/System/Atomic.h lib/System/Atomic.cpp Message-ID: <200906231739.n5NHdYKG027045@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 23 12:39:31 2009 New Revision: 73964 URL: http://llvm.org/viewvc/llvm-project?rev=73964&view=rev Log: Add an atomic add operation. Modified: llvm/trunk/include/llvm/System/Atomic.h llvm/trunk/lib/System/Atomic.cpp Modified: llvm/trunk/include/llvm/System/Atomic.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Atomic.h?rev=73964&r1=73963&r2=73964&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Atomic.h (original) +++ llvm/trunk/include/llvm/System/Atomic.h Tue Jun 23 12:39:31 2009 @@ -26,6 +26,7 @@ cas_flag old_value); cas_flag AtomicIncrement(volatile cas_flag* ptr); cas_flag AtomicDecrement(volatile cas_flag* ptr); + cas_flag AtomicAdd(volatile cas_flag* ptr, cas_flag val); } } Modified: llvm/trunk/lib/System/Atomic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Atomic.cpp?rev=73964&r1=73963&r2=73964&view=diff ============================================================================== --- llvm/trunk/lib/System/Atomic.cpp (original) +++ llvm/trunk/lib/System/Atomic.cpp Tue Jun 23 12:39:31 2009 @@ -78,4 +78,17 @@ #endif } +sys::cas_flag sys::AtomicAdd(volatile sys::cas_flag* ptr, sys::cas_flag val) { +#if LLVM_MULTITHREADED==0 + *ptr += val; + return *ptr; +#elif defined(__GNUC__) + return __sync_add_and_fetch(ptr, val); +#elif defined(_MSC_VER) + return InterlockedAdd(ptr, val); +#else +# error No atomic add implementation for your platform! +#endif +} + From evan.cheng at apple.com Tue Jun 23 12:48:56 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 17:48:56 -0000 Subject: [llvm-commits] [llvm] r73965 - in /llvm/trunk/lib/Target/ARM: ARMAddressingModes.h ARMInstrFormats.td ARMInstrInfo.td ARMInstrThumb2.td AsmPrinter/ARMAsmPrinter.cpp Message-ID: <200906231748.n5NHmwcK027338@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jun 23 12:48:47 2009 New Revision: 73965 URL: http://llvm.org/viewvc/llvm-project?rev=73965&view=rev Log: Initial Thumb2 support. Majority of the work is done by David Goodwin. There are also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng. I've done my best to consolidate the patches with those that were done by Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed anything. I've completely reorganized the thumb2 td file, made more extensive uses of multiclass, etc. Test cases will be contributed later after I re-organize what's in svn first. Modified: llvm/trunk/lib/Target/ARM/ARMAddressingModes.h llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAddressingModes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAddressingModes.h?rev=73965&r1=73964&r2=73965&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAddressingModes.h (original) +++ llvm/trunk/lib/Target/ARM/ARMAddressingModes.h Tue Jun 23 12:48:47 2009 @@ -248,12 +248,122 @@ return V == 0; } + /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed + /// by a left shift. Returns the shift amount to use. + static inline unsigned getThumbImm16ValShift(unsigned Imm) { + // 16-bit (or less) immediates are trivially immediate operand with a shift + // of zero. + if ((Imm & ~65535U) == 0) return 0; + + // Use CTZ to compute the shift amount. + return CountTrailingZeros_32(Imm); + } + + /// isThumbImm16ShiftedVal - Return true if the specified value can be + /// obtained by left shifting a 16-bit immediate. + static inline bool isThumbImm16ShiftedVal(unsigned V) { + // If this can be handled with + V = (~65535U << getThumbImm16ValShift(V)) & V; + return V == 0; + } + /// getThumbImmNonShiftedVal - If V is a value that satisfies /// isThumbImmShiftedVal, return the non-shiftd value. static inline unsigned getThumbImmNonShiftedVal(unsigned V) { return V >> getThumbImmValShift(V); } + /// getT2SOImmValDecode - Given a 12-bit encoded Thumb-2 modified immediate, + /// return the corresponding 32-bit immediate value. + /// See ARM Reference Manual A6.3.2. + static inline unsigned getT2SOImmValDecode(unsigned Imm) { + unsigned Base = Imm & 0xff; + switch ((Imm >> 8) & 0xf) { + case 0: + return Base; + case 1: + return Base | (Base << 16); + case 2: + return (Base << 8) | (Base << 24); + case 3: + return Base | (Base << 8) | (Base << 16) | (Base << 24); + default: + break; + } + + // shifted immediate + unsigned RotAmount = ((Imm >> 7) & 0x1f) - 8; + return (Base | 0x80) << (24 - RotAmount); + } + + /// getT2SOImmValSplat - Return the 12-bit encoded representation + /// if the specified value can be obtained by splatting the low 8 bits + /// into every other byte or every byte of a 32-bit value. i.e., + /// 00000000 00000000 00000000 abcdefgh control = 0 + /// 00000000 abcdefgh 00000000 abcdefgh control = 1 + /// abcdefgh 00000000 abcdefgh 00000000 control = 2 + /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3 + /// Return -1 if none of the above apply. + /// See ARM Reference Manual A6.3.2. + static inline int getT2SOImmValSplat (unsigned V) { + unsigned u, Vs, Imm; + // control = 0 + if ((V & 0xffffff00) == 0) + return V; + + // If the value is zeroes in the first byte, just shift those off + Vs = ((V & 0xff) == 0) ? V >> 8 : V; + // Any passing value only has 8 bits of payload, splatted across the word + Imm = Vs & 0xff; + // Likewise, any passing values have the payload splatted into the 3rd byte + u = Imm | (Imm << 16); + + // control = 1 or 2 + if (Vs == u) + return (((Vs == V) ? 1 : 2) << 8) | Imm; + + // control = 3 + if (Vs == (u | (u << 8))) + return (3 << 8) | Imm; + + return -1; + } + + /// getT2SOImmValRotate - Return the 12-bit encoded representation if the + /// specified value is a rotated 8-bit value. Return -1 if no rotation + /// encoding is possible. + /// See ARM Reference Manual A6.3.2. + static inline int getT2SOImmValRotate (unsigned V) { + unsigned RotAmt = CountLeadingZeros_32(V); + if (RotAmt >= 24) + return -1; + + // If 'Arg' can be handled with a single shifter_op return the value. + if ((rotr32(0xff000000U, RotAmt) & V) == V) + return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7); + + return -1; + } + + /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit + /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit + /// encoding for it. If not, return -1. + /// See ARM Reference Manual A6.3.2. + static inline int getT2SOImmVal(unsigned Arg) { + // If 'Arg' is an 8-bit splat, then get the encoded value. + int Splat = getT2SOImmValSplat(Arg); + if (Splat != -1) + return Splat; + + // If 'Arg' can be handled with a single shifter_op return the value. + int Rot = getT2SOImmValRotate(Arg); + if (Rot != -1) + return Rot; + + return -1; + } + + //===--------------------------------------------------------------------===// // Addressing Mode #2 //===--------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=73965&r1=73964&r2=73965&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Jun 23 12:48:47 2009 @@ -751,6 +751,26 @@ list Predicates = [IsThumb, HasV5T]; } +// T2I - Thumb2 instruction. + +class Thumb2I pattern> + : InstARM { + let OutOperandList = outs; + let InOperandList = ins; + let AsmString = asm; + let Pattern = pattern; + list Predicates = [IsThumb, HasThumb2]; +} + +class T2I pattern> + : Thumb2I; + +// Thumb2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. +class Thumb2Pat : Pat { + list Predicates = [IsThumb, HasThumb2]; +} + //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=73965&r1=73964&r2=73965&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jun 23 12:48:47 2009 @@ -98,6 +98,7 @@ def HasVFP3 : Predicate<"Subtarget->hasVFP3()">; def HasNEON : Predicate<"Subtarget->hasNEON()">; def IsThumb : Predicate<"Subtarget->isThumb()">; +def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; def HasThumb2 : Predicate<"Subtarget->hasThumb2()">; def IsARM : Predicate<"!Subtarget->isThumb()">; def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=73965&r1=73964&r2=73965&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jun 23 12:48:47 2009 @@ -20,131 +20,233 @@ let MIOperandInfo = (ops GPR, i32imm); } -def LO16 : SDNodeXFormgetZExtValue()); +// t2_so_imm_XFORM - Return a t2_so_imm value packed into the format +// described for t2_so_imm def below. +def t2_so_imm_XFORM : SDNodeXFormgetTargetConstant( + ARM_AM::getT2SOImmVal(N->getZExtValue()), MVT::i32); }]>; -def HI16 : SDNodeXFormgetZExtValue() >> 16); +// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value +def t2_so_imm_not_XFORM : SDNodeXFormgetTargetConstant( + ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())), MVT::i32); }]>; -def imm16high : PatLeaf<(i32 imm), [{ - // Returns true if all bits out of the [31..16] range are 0. - return ((N->getZExtValue() & 0xFFFF0000ULL) == N->getZExtValue()); -}], HI16>; +// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value +def t2_so_imm_neg_XFORM : SDNodeXFormgetTargetConstant( + ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())), MVT::i32); +}]>; + +// t2_so_imm - Match a 32-bit immediate operand, which is an +// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit +// immediate splatted into multiple bytes of the word. t2_so_imm values are +// represented in the imm field in the same 12-bit form that they are encoded +// into t2_so_imm instructions: the 8-bit immediate is the least significant bits +// [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11]. +def t2_so_imm : Operand, + PatLeaf<(imm), [{ + return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1; + }], t2_so_imm_XFORM> { + let PrintMethod = "printT2SOImmOperand"; +} -def imm16high0xffff : PatLeaf<(i32 imm), [{ - // Returns true if lo 16 bits are set and this is a 32-bit value. - return ((N->getZExtValue() & 0x0000FFFFULL) == 0xFFFFULL); -}], HI16>; +// t2_so_imm_not - Match an immediate that is a complement +// of a t2_so_imm. +def t2_so_imm_not : Operand, + PatLeaf<(imm), [{ + return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; + }], t2_so_imm_not_XFORM> { + let PrintMethod = "printT2SOImmOperand"; +} -def imm0_4095 : PatLeaf<(i32 imm), [{ - return (uint32_t)N->getZExtValue() < 4096; -}]>; +// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. +def t2_so_imm_neg : Operand, + PatLeaf<(imm), [{ + return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1; + }], t2_so_imm_neg_XFORM> { + let PrintMethod = "printT2SOImmOperand"; +} + +/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. +def imm0_4095 : PatLeaf<(i32 imm), [{ + return (uint32_t)N->getZExtValue() < 4096; +}]>; def imm0_4095_neg : PatLeaf<(i32 imm), [{ - return (uint32_t)-N->getZExtValue() < 4096; + return (uint32_t)(-N->getZExtValue()) < 4096; }], imm_neg_XFORM>; -def imm0_65535 : PatLeaf<(i32 imm), [{ - return N->getZExtValue() < 65536; -}]>; +/// imm0_65535 predicate - True if the 32-bit immediate is in the range +/// [0.65535]. +def imm0_65535 : PatLeaf<(i32 imm), [{ + return (uint32_t)N->getZExtValue() < 65536; +}]>; -// A6.3.2 Modified immediate constants in Thumb instructions (#) -// FIXME: Move it the the addrmode matcher code. -def t2_so_imm : PatLeaf<(i32 imm), [{ - uint64_t v = N->getZExtValue(); - if (v == 0 || v > 0xffffffffUL) return false; - // variant1 - 0b0000x - 8-bit which could be zero (not supported for now) - // variant2 - 0b00nnx - 8-bit repeated inside the 32-bit room - unsigned hi16 = (unsigned)(v >> 16); - unsigned lo16 = (unsigned)(v & 0xffffUL); - bool valid = (hi16 == lo16) && ( - (v & 0x00ff00ffUL) == 0 || // type 0001x - (v & 0xff00ff00UL) == 0 || // type 0010x - ((lo16 >> 8) == (lo16 & 0xff))); // type 0011x - if (valid) return true; +/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield +/// e.g., 0xf000ffff +def bf_inv_mask_imm : Operand, + PatLeaf<(imm), [{ + uint32_t v = (uint32_t)N->getZExtValue(); + if (v == 0xffffffff) + return 0; + // naive checker. should do better, but simple is best for now since it's + // more likely to be correct. + while (v & 1) v >>= 1; // shift off the leading 1's + if (v) + { + while (!(v & 1)) v >>=1; // shift off the mask + while (v & 1) v >>= 1; // shift off the trailing 1's + } + // if this is a mask for clearing a bitfield, what's left should be zero. + return (v == 0); +}] > { + let PrintMethod = "printBitfieldInvMaskImmOperand"; +} + +/// Split a 32-bit immediate into two 16 bit parts. +def t2_lo16 : SDNodeXFormgetTargetConstant((uint32_t)N->getZExtValue() & 0xffff, + MVT::i32); +}]>; - // variant3 - 0b01000..0b11111 - 8-bit shifted inside the 32-bit room - unsigned shift = CountLeadingZeros_32(v); - uint64_t mask = (0xff000000ULL >> shift); - // If valid, it is type 01000 + shift - return ((shift < 24) && (v & mask) > 0) && ((v & (~mask)) == 0); +def t2_hi16 : SDNodeXFormgetTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); }]>; +def t2_lo16AllZero : PatLeaf<(i32 imm), [{ + // Returns true if all low 16-bits are 0. + return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; + }], t2_hi16>; //===----------------------------------------------------------------------===// -// Thumb-2 to cover the functionality of the ARM instruction set. +// Thumb2 to cover the functionality of the ARM instruction set. // -/// T2I_bin_irs - Defines a set of (op reg, {so_imm|reg|so_reg}) patterns for a +/// T2I_bin_is - Defines a set of (op reg, {so_imm|so_reg}) patterns for a // binary operation that produces a value. -multiclass T2I_bin_irs { +multiclass T2I_bin_is { // shifted imm - def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), - !strconcat(opc, " $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, - Requires<[HasThumb2]>; - // register - def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), - !strconcat(opc, " $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, - Requires<[HasThumb2]>; - // shifted register - def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), - !strconcat(opc, " $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, - Requires<[HasThumb2]>; + def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), + !strconcat(opc, " $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; + // shifted register + def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), + !strconcat(opc, " $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; +} + +/// T2I_2bin_is - Same as T2I_bin_is except the order of operands are reversed. +multiclass T2I_rbin_is { + // shifted imm + def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), + !strconcat(opc, " $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; + // shifted register + def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), + !strconcat(opc, " $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; } -/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the +/// T2I_bin_s_is - Similar to T2I_bin_is except it sets the 's' bit so the /// instruction modifies the CPSR register. let Defs = [CPSR] in { -multiclass T2I_bin_s_irs { +multiclass T2I_bin_s_is { // shifted imm - def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), - !strconcat(opc, "s $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, - Requires<[HasThumb2]>; + def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), + !strconcat(opc, "s $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; - // register - def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), - !strconcat(opc, "s $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, - Requires<[HasThumb2]>; + // shifted register + def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), + !strconcat(opc, "s $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; +} +} + +/// T2I_rbin_s_is - Same as T2I_bin_s_is except the order of operands are +/// reversed. +let Defs = [CPSR] in { +multiclass T2I_rbin_s_is { + // shifted imm + def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), + !strconcat(opc, "s $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; // shifted register - def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), - !strconcat(opc, "s $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, - Requires<[HasThumb2]>; + def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), + !strconcat(opc, "s $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; } } -/// T2I_bin_c_irs - Similar to T2I_bin_irs except it uses the 's' bit. Also the -/// instruction can optionally set the CPSR register. +/// T2I_bin_ii12s - Defines a set of (op reg, {so_imm|imm0_4095|so_reg}) patterns +/// for a binary operation that produces a value. +multiclass T2I_bin_ii12s { + // shifted imm + def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), + !strconcat(opc, " $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; + // 12-bit imm + def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), + !strconcat(opc, "w $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>; + // shifted register + def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), + !strconcat(opc, " $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; +} + +/// T2I_bin_c_is - Defines a set of (op reg, {so_imm|reg}) patterns for a +// binary operation that produces a value and set the carry bit. It can also +/// optionally set CPSR. +let Uses = [CPSR] in { +multiclass T2I_bin_c_is { + // shifted imm + def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs, cc_out:$s), + !strconcat(opc, "${s} $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; + + // shifted register + def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s), + !strconcat(opc, "${s} $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; +} +} + +/// T2I_rbin_c_is - Same as T2I_bin_c_is except the order of operands are +/// reversed. let Uses = [CPSR] in { -multiclass T2I_bin_c_irs { +multiclass T2I_rbin_c_is { // shifted imm - def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, - Requires<[HasThumb2]>; - - // register - def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, - Requires<[HasThumb2]>; - - // shifted register - def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, - Requires<[HasThumb2]>; + def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), + !strconcat(opc, "${s} $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; + + // shifted register + def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), + !strconcat(opc, "${s} $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; +} +} + + +/// T21_cmp_irs - Defines a set of (op r, {so_imm|so_reg}) cmp / test +/// patterns. Similar to T2I_bin_is except the instruction does not produce +/// a explicit result, only implicitly set CPSR. +let Uses = [CPSR] in { +multiclass T2I_cmp_is { + // shifted imm + def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), + !strconcat(opc, " $lhs, $rhs"), + [(opnode GPR:$lhs, t2_so_imm:$rhs)]>; + + // shifted register + def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), + !strconcat(opc, " $lhs, $rhs"), + [(opnode GPR:$lhs, t2_so_reg:$rhs)]>; } } @@ -155,54 +257,184 @@ //===----------------------------------------------------------------------===// // Move Instructions. // -def tMOVi16 : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), - "movw $dst, $src", - [(set GPR:$dst, imm0_65535:$src)]>, - Requires<[HasThumb2]>; +let neverHasSideEffects = 1 in +def t2MOVr : T2I<(outs GPR:$dst), (ins GPR:$src), + "mov $dst, $src", []>; + +def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), + "movw $dst, $src", + [(set GPR:$dst, imm0_65535:$src)]>; + + +// FIXME: Move (shifted register) is a pseudo-instruction for ASR, LSL, LSR, +// ROR, and RRX. Consider splitting into multiple instructions. +def t2MOVs : T2I<(outs GPR:$dst), (ins so_reg:$src), + "mov $dst, $src", + [(set GPR:$dst, so_reg:$src)]>; +def t2MOVrx : T2I<(outs GPR:$dst), (ins GPR:$src), + "mov $dst, $src, rrx", + [(set GPR:$dst, (ARMrrx GPR:$src))]>; + + +// FIXME: Also available in ARM mode. let Constraints = "$src = $dst" in -def tMOVTi16 : PseudoInst<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), - "movt $dst, $imm", - [(set GPR:$dst, (or (and GPR:$src, 0xffff), - imm16high:$imm))]>, - Requires<[HasThumb2]>; - -def : Pat<(and (or GPR:$src, imm16high:$imm1), imm16high0xffff:$imm2), - (tMOVTi16 GPR:$src, (HI16 imm16high:$imm1))>, - Requires<[HasThumb2]>; - -def : Pat<(i32 imm:$imm), - (tMOVTi16 (tMOVi16 (LO16 imm:$imm)),(HI16 imm:$imm))>, - Requires<[HasThumb2]>; +def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), + "movt $dst, $imm", + [(set GPR:$dst, + (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>; //===----------------------------------------------------------------------===// // Arithmetic Instructions. // -defm t2ADD : T2I_bin_irs <"add", BinOpFrag<(add node:$LHS, node:$RHS)>>; -defm t2SUB : T2I_bin_irs <"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; -def tADDri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), - "add $dst, $lhs, $rhs", - [(set GPR:$dst, (add GPR:$lhs, imm0_4095:$rhs))]>, - Requires<[HasThumb2]>; -def tSUBri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), - "sub $dst, $lhs, $rhs", - [(set GPR:$dst, (add GPR:$lhs, imm0_4095_neg:$rhs))]>, - Requires<[HasThumb2]>; - -defm t2ADDS : T2I_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>; -defm t2SUBS : T2I_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; - -defm t2ADC : T2I_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>; -defm t2SBC : T2I_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; - - -def tMLS : PseudoInst<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), - "mls $dst, $a, $b, $c", - [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>, - Requires<[HasThumb2]>; - -def tORNrs : PseudoInst<(outs GPR:$dst), (ins GPR:$src1, t2_so_reg:$src2), - "orn $dst, $src1, $src2", - [(set GPR:$dst, (or GPR:$src1, (not t2_so_reg: $src2)))]>, - Requires<[HasThumb2]>; +defm t2ADD : T2I_bin_ii12s<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>; +defm t2SUB : T2I_bin_ii12s<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; + +// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. +defm t2ADDS : T2I_bin_s_is<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>; +defm t2SUBS : T2I_bin_s_is<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; + +// FIXME: predication support +defm t2ADC : T2I_bin_c_is<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>; +defm t2SBC : T2I_bin_c_is<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; + +// RSB, RSC +defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>; +defm t2RSBS : T2I_rbin_c_is<"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>; +defm t2RSC : T2I_rbin_s_is<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; + +// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. +def : Thumb2Pat<(add GPR:$src, t2_so_imm_neg:$imm), + (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; +def : Thumb2Pat<(add GPR:$src, imm0_4095_neg:$imm), + (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; + + +//===----------------------------------------------------------------------===// +// Bitwise Instructions. +// + +defm t2AND : T2I_bin_is <"and", BinOpFrag<(and node:$LHS, node:$RHS)>>; +defm t2ORR : T2I_bin_is <"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>; +defm t2EOR : T2I_bin_is <"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>; + +defm t2BIC : T2I_bin_is <"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; + +def : Thumb2Pat<(and GPR:$src, t2_so_imm_not:$imm), + (t2BICri GPR:$src, t2_so_imm_not:$imm)>; + +defm t2ORN : T2I_bin_is <"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>; + +def : Thumb2Pat<(or GPR:$src, t2_so_imm_not:$imm), + (t2ORNri GPR:$src, t2_so_imm_not:$imm)>; + + +def t2MVNr : T2I<(outs GPR:$dst), (ins t2_so_reg:$rhs), + "mvn $dst, $rhs", + [(set GPR:$dst, (not t2_so_reg:$rhs))]>; +let isReMaterializable = 1, isAsCheapAsAMove = 1 in +def t2MVNi : T2I<(outs GPR:$dst), (ins t2_so_imm_not:$rhs), + "mvn $dst, $rhs", + [(set GPR:$dst, t2_so_imm_not:$rhs)]>; + +// A8.6.17 BFC - Bitfield clear +// FIXME: Also available in ARM mode. +let Constraints = "$src = $dst" in +def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), + "bfc $dst, $imm", + [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>; + +// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1) + +//===----------------------------------------------------------------------===// +// Multiply Instructions. +// +def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), + "mul $dst, $a, $b", + [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; + +def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), + "mla $dst, $a, $b, $c", + [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; + +def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), + "mls $dst, $a, $b, $c", + [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>; + +// FIXME: SMULL, etc. + +//===----------------------------------------------------------------------===// +// Misc. Arithmetic Instructions. +// + +///// +/// A8.6.31 CLZ +///// +// FIXME not firing? but ARM version does... +def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), + "clz $dst, $src", + [(set GPR:$dst, (ctlz GPR:$src))]>; + +def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), + "rev $dst, $src", + [(set GPR:$dst, (bswap GPR:$src))]>; + +def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), + "rev16 $dst, $src", + [(set GPR:$dst, + (or (and (srl GPR:$src, (i32 8)), 0xFF), + (or (and (shl GPR:$src, (i32 8)), 0xFF00), + (or (and (srl GPR:$src, (i32 8)), 0xFF0000), + (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>; + +///// +/// A8.6.137 REVSH +///// +def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), + "revsh $dst, $src", + [(set GPR:$dst, + (sext_inreg + (or (srl (and GPR:$src, 0xFFFF), (i32 8)), + (shl GPR:$src, (i32 8))), i16))]>; + +// FIXME: PKHxx etc. + +//===----------------------------------------------------------------------===// +// Comparison Instructions... +// + +defm t2CMP : T2I_cmp_is<"cmp", + BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; +defm t2CMPnz : T2I_cmp_is<"cmp", + BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>; + +defm t2CMN : T2I_cmp_is<"cmn", + BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; +defm t2CMNnz : T2I_cmp_is<"cmn", + BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>; + +def : Thumb2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), + (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; + +def : Thumb2Pat<(ARMcmpNZ GPR:$src, t2_so_imm_neg:$imm), + (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; + +// FIXME: TST, TEQ, etc. + +// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero. +// Short range conditional branch. Looks awesome for loops. Need to figure +// out how to use this one. + +// FIXME: Conditional moves + + +//===----------------------------------------------------------------------===// +// Non-Instruction Patterns +// + +// Large immediate handling. + +def : Thumb2Pat<(i32 imm:$src), + (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), + (t2_hi16 imm:$src))>; Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=73965&r1=73964&r2=73965&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Tue Jun 23 12:48:47 2009 @@ -98,6 +98,7 @@ void printSOImm2PartOperand(const MachineInstr *MI, int opNum); void printSOOperand(const MachineInstr *MI, int OpNum); void printSORegOperand(const MachineInstr *MI, int opNum); + void printT2SOImmOperand(const MachineInstr *MI, int opNum); void printAddrMode2Operand(const MachineInstr *MI, int OpNo); void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNo); void printAddrMode3Operand(const MachineInstr *MI, int OpNo); @@ -108,6 +109,7 @@ const char *Modifier = 0); void printAddrModePCOperand(const MachineInstr *MI, int OpNo, const char *Modifier = 0); + void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNo); void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNo); void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNo, unsigned Scale); @@ -455,6 +457,24 @@ } } +static void printT2SOImm(raw_ostream &O, int64_t V) { + unsigned Imm = ARM_AM::getT2SOImmValDecode(V); + + // Always print the immediate directly, as the "rotate" form + // is deprecated in some contexts. + O << "#" << Imm; +} + +/// printT2SOImmOperand - T2SOImm is: +/// 1. a 4-bit splat control value and 8 bit immediate value +/// 2. a 5-bit rotate amount and a non-zero 8-bit immediate value +/// represented by a normalizedin 7-bit value (msb is always 1) +void ARMAsmPrinter::printT2SOImmOperand(const MachineInstr *MI, int OpNum) { + const MachineOperand &MO = MI->getOperand(OpNum); + assert(MO.isImm() && "Not a valid so_imm value!"); + printT2SOImm(O, MO.getImm()); +} + void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); @@ -620,6 +640,16 @@ } void +ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) { + const MachineOperand &MO = MI->getOperand(Op); + uint32_t v = ~MO.getImm(); + int32_t lsb = ffs (v) - 1; + int32_t width = fls (v) - lsb; + assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); + O << "#" << lsb << ", #" << width; +} + +void ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); From sabre at nondot.org Tue Jun 23 12:50:34 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 23 Jun 2009 17:50:34 -0000 Subject: [llvm-commits] [llvm] r73966 - /llvm/trunk/include/llvm/MC/MCInst.h Message-ID: <200906231750.n5NHoYUM027399@zion.cs.uiuc.edu> Author: lattner Date: Tue Jun 23 12:50:34 2009 New Revision: 73966 URL: http://llvm.org/viewvc/llvm-project?rev=73966&view=rev Log: add an accessor. Modified: llvm/trunk/include/llvm/MC/MCInst.h Modified: llvm/trunk/include/llvm/MC/MCInst.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInst.h?rev=73966&r1=73965&r2=73966&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInst.h (original) +++ llvm/trunk/include/llvm/MC/MCInst.h Tue Jun 23 12:50:34 2009 @@ -112,6 +112,7 @@ const MCOperand &getOperand(unsigned i) const { return Operands[i]; } MCOperand &getOperand(unsigned i) { return Operands[i]; } + unsigned getNumOperands() const { return Operands.size(); } void addOperand(const MCOperand &Op) { Operands.push_back(Op); From evan.cheng at apple.com Tue Jun 23 12:54:35 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 17:54:35 -0000 Subject: [llvm-commits] [llvm] r73967 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <200906231754.n5NHsaPS027531@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jun 23 12:54:26 2009 New Revision: 73967 URL: http://llvm.org/viewvc/llvm-project?rev=73967&view=rev Log: Obvious typo. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=73967&r1=73966&r2=73967&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jun 23 12:54:26 2009 @@ -269,9 +269,9 @@ // FIXME: Move (shifted register) is a pseudo-instruction for ASR, LSL, LSR, // ROR, and RRX. Consider splitting into multiple instructions. -def t2MOVs : T2I<(outs GPR:$dst), (ins so_reg:$src), +def t2MOVs : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), "mov $dst, $src", - [(set GPR:$dst, so_reg:$src)]>; + [(set GPR:$dst, t2_so_reg:$src)]>; def t2MOVrx : T2I<(outs GPR:$dst), (ins GPR:$src), "mov $dst, $src, rrx", [(set GPR:$dst, (ARMrrx GPR:$src))]>; From dgregor at apple.com Tue Jun 23 12:57:36 2009 From: dgregor at apple.com (Douglas Gregor) Date: Tue, 23 Jun 2009 17:57:36 -0000 Subject: [llvm-commits] [llvm] r73969 - in /llvm/trunk: ./ cmake/modules/ lib/ExecutionEngine/ lib/ExecutionEngine/Interpreter/ lib/ExecutionEngine/JIT/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/AsmPrinter/ lib/Target/CellSPU/AsmPrinter/ lib/Target/IA64/AsmPrinter/ lib/Target/Mips/AsmPrinter/ lib/Target/PowerPC/AsmPrinter/ lib/Target/Sparc/AsmPrinter/ lib/Target/X86/AsmPrinter/ Message-ID: <200906231757.n5NHvb6T027685@zion.cs.uiuc.edu> Author: dgregor Date: Tue Jun 23 12:57:35 2009 New Revision: 73969 URL: http://llvm.org/viewvc/llvm-project?rev=73969&view=rev Log: Eliminate object-relinking support from CMake. Fixes PR 4429 and cleans up the CMake-based build system a bit. Started by a patch from Xerxes R?nby. Removed: llvm/trunk/cmake/modules/AddPartiallyLinkedObject.cmake Modified: llvm/trunk/CMakeLists.txt llvm/trunk/cmake/modules/AddLLVM.cmake llvm/trunk/lib/ExecutionEngine/CMakeLists.txt llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/Alpha/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/CellSPU/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/IA64/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/Mips/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/Sparc/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt Modified: llvm/trunk/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=73969&r1=73968&r2=73969&view=diff ============================================================================== --- llvm/trunk/CMakeLists.txt (original) +++ llvm/trunk/CMakeLists.txt Tue Jun 23 12:57:35 2009 @@ -180,9 +180,6 @@ add_llvm_definitions( -D__STDC_LIMIT_MACROS ) add_llvm_definitions( -D__STDC_CONSTANT_MACROS ) -set(LLVM_PLO_FLAGS "" CACHE - STRING "Flags for creating partially linked objects.") - if( CMAKE_SIZEOF_VOID_P EQUAL 8 AND NOT WIN32 ) # TODO: support other platforms and toolchains. option(LLVM_BUILD_32_BITS "Build 32 bits executables and libraries." OFF) @@ -221,7 +218,6 @@ include_directories( ${LLVM_BINARY_DIR}/include ${LLVM_MAIN_INCLUDE_DIR}) include(AddLLVM) -include(AddPartiallyLinkedObject) include(TableGen) add_subdirectory(lib/Support) Modified: llvm/trunk/cmake/modules/AddLLVM.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=73969&r1=73968&r2=73969&view=diff ============================================================================== --- llvm/trunk/cmake/modules/AddLLVM.cmake (original) +++ llvm/trunk/cmake/modules/AddLLVM.cmake Tue Jun 23 12:57:35 2009 @@ -61,8 +61,10 @@ add_dependencies(${target_name}Table_gen ${LLVM_COMMON_DEPENDS}) endif( TABLEGEN_OUTPUT ) include_directories(BEFORE ${CMAKE_CURRENT_BINARY_DIR}) - add_partially_linked_object(LLVM${target_name} ${ARGN}) + add_llvm_library(LLVM${target_name} ${ARGN} ${TABLEGEN_OUTPUT}) + if (FALSE) if( TABLEGEN_OUTPUT ) add_dependencies(LLVM${target_name} ${target_name}Table_gen) endif( TABLEGEN_OUTPUT ) + endif () endmacro(add_llvm_target) Removed: llvm/trunk/cmake/modules/AddPartiallyLinkedObject.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddPartiallyLinkedObject.cmake?rev=73968&view=auto ============================================================================== --- llvm/trunk/cmake/modules/AddPartiallyLinkedObject.cmake (original) +++ llvm/trunk/cmake/modules/AddPartiallyLinkedObject.cmake (removed) @@ -1,42 +0,0 @@ -include(LLVMProcessSources) - -macro(target_name_of_partially_linked_object lib var) - if( USE_EXPLICIT_DEPENDENCIES ) - set(${var} ${lib}) - else( ) - set(${var} ${lib}_pll) - endif( ) -endmacro(target_name_of_partially_linked_object lib var) - - -macro(add_partially_linked_object lib) - if( USE_EXPLICIT_DEPENDENCIES ) - add_llvm_library( ${lib} ${ARGN}) - else( ) - set(pll ${CMAKE_ARCHIVE_OUTPUT_DIRECTORY}/${CMAKE_CFG_INTDIR}/${lib}.o) - set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/temp_lib) - set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/temp_lib) - llvm_process_sources( ALL_FILES ${ARGN} ) - if( BUILD_SHARED_LIBS AND SUPPORTS_FPIC_FLAG ) - add_definitions(-fPIC) - endif() - add_library( ${lib} STATIC ${ALL_FILES}) - if( LLVM_COMMON_DEPENDS ) - add_dependencies( ${lib} ${LLVM_COMMON_DEPENDS} ) - endif( LLVM_COMMON_DEPENDS ) - add_custom_command(OUTPUT ${pll} - COMMENT "Building ${lib}.o..." - DEPENDS ${lib} - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/temp_lib/${CMAKE_CFG_INTDIR} - COMMAND ar x ${CMAKE_STATIC_LIBRARY_PREFIX}${lib}${CMAKE_STATIC_LIBRARY_SUFFIX} - COMMAND ${CMAKE_LINKER} "${LLVM_PLO_FLAGS}" -r "*${CMAKE_CXX_OUTPUT_EXTENSION}" -o ${pll} - COMMAND ${CMAKE_COMMAND} -E remove -f *${CMAKE_CXX_OUTPUT_EXTENSION} - ) - target_name_of_partially_linked_object(${lib} tnplo) - add_custom_target(${tnplo} ALL DEPENDS ${pll}) - set( llvm_libs ${llvm_libs} ${pll} PARENT_SCOPE) - set( llvm_lib_targets ${llvm_lib_targets} ${tnplo} PARENT_SCOPE ) - endif( ) - install(FILES ${pll} - DESTINATION lib${LLVM_LIBDIR_SUFFIX}) -endmacro(add_partially_linked_object lib) Modified: llvm/trunk/lib/ExecutionEngine/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/CMakeLists.txt?rev=73969&r1=73968&r2=73969&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/CMakeLists.txt (original) +++ llvm/trunk/lib/ExecutionEngine/CMakeLists.txt Tue Jun 23 12:57:35 2009 @@ -1,4 +1,4 @@ -add_partially_linked_object(LLVMExecutionEngine +add_llvm_library(LLVMExecutionEngine ExecutionEngine.cpp ExecutionEngineBindings.cpp ) Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt?rev=73969&r1=73968&r2=73969&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt (original) +++ llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt Tue Jun 23 12:57:35 2009 @@ -1,4 +1,4 @@ -add_partially_linked_object(LLVMInterpreter +add_llvm_library(LLVMInterpreter Execution.cpp ExternalFunctions.cpp Interpreter.cpp Modified: llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt?rev=73969&r1=73968&r2=73969&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt Tue Jun 23 12:57:35 2009 @@ -1,7 +1,7 @@ # TODO: Support other architectures. See Makefile. add_definitions(-DENABLE_X86_JIT) -add_partially_linked_object(LLVMJIT +add_llvm_library(LLVMJIT Intercept.cpp JIT.cpp JITDwarfEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt?rev=73969&r1=73968&r2=73969&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt Tue Jun 23 12:57:35 2009 @@ -1,9 +1,5 @@ include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) -add_partially_linked_object(LLVMARMAsmPrinter +add_llvm_library(LLVMARMAsmPrinter ARMAsmPrinter.cpp ) - -target_name_of_partially_linked_object(LLVMARMCodeGen n) - -add_dependencies(LLVMARMAsmPrinter ${n}) Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/CMakeLists.txt?rev=73969&r1=73968&r2=73969&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/CMakeLists.txt Tue Jun 23 12:57:35 2009 @@ -1,9 +1,5 @@ include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) -add_partially_linked_object(LLVMAlphaAsmPrinter +add_llvm_library(LLVMAlphaAsmPrinter AlphaAsmPrinter.cpp ) - -target_name_of_partially_linked_object(LLVMAlphaCodeGen n) - -add_dependencies(LLVMAlphaAsmPrinter ${n}) Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/CMakeLists.txt?rev=73969&r1=73968&r2=73969&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/CMakeLists.txt Tue Jun 23 12:57:35 2009 @@ -3,10 +3,6 @@ ${CMAKE_CURRENT_SOURCE_DIR}/.. ) -add_partially_linked_object(LLVMCellSPUAsmPrinter +add_llvm_library(LLVMCellSPUAsmPrinter SPUAsmPrinter.cpp ) - -target_name_of_partially_linked_object(LLVMCellSPUCodeGen n) - -add_dependencies(LLVMCellSPUAsmPrinter ${n}) Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/CMakeLists.txt?rev=73969&r1=73968&r2=73969&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/IA64/AsmPrinter/CMakeLists.txt Tue Jun 23 12:57:35 2009 @@ -3,10 +3,6 @@ ${CMAKE_CURRENT_SOURCE_DIR}/.. ) -add_partially_linked_object(LLVMIA64AsmPrinter +add_llvm_library(LLVMIA64AsmPrinter IA64AsmPrinter.cpp ) - -target_name_of_partially_linked_object(LLVMIA64CodeGen n) - -add_dependencies(LLVMIA64AsmPrinter ${n}) Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/CMakeLists.txt?rev=73969&r1=73968&r2=73969&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/AsmPrinter/CMakeLists.txt Tue Jun 23 12:57:35 2009 @@ -3,10 +3,6 @@ ${CMAKE_CURRENT_SOURCE_DIR}/.. ) -add_partially_linked_object(LLVMMipsAsmPrinter +add_llvm_library(LLVMMipsAsmPrinter MipsAsmPrinter.cpp ) - -target_name_of_partially_linked_object(LLVMMipsCodeGen n) - -add_dependencies(LLVMMipsAsmPrinter ${n}) Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/CMakeLists.txt?rev=73969&r1=73968&r2=73969&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/CMakeLists.txt Tue Jun 23 12:57:35 2009 @@ -1,9 +1,5 @@ include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) -add_partially_linked_object(LLVMPowerPCAsmPrinter +add_llvm_library(LLVMPowerPCAsmPrinter PPCAsmPrinter.cpp ) - -target_name_of_partially_linked_object(LLVMPowerPCCodeGen n) - -add_dependencies(LLVMPowerPCAsmPrinter ${n}) Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/CMakeLists.txt?rev=73969&r1=73968&r2=73969&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Sparc/AsmPrinter/CMakeLists.txt Tue Jun 23 12:57:35 2009 @@ -1,9 +1,5 @@ include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) -add_partially_linked_object(LLVMSparcAsmPrinter +add_llvm_library(LLVMSparcAsmPrinter SparcAsmPrinter.cpp ) - -target_name_of_partially_linked_object(LLVMSparcCodeGen n) - -add_dependencies(LLVMSparcAsmPrinter ${n}) Modified: llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt?rev=73969&r1=73968&r2=73969&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt Tue Jun 23 12:57:35 2009 @@ -1,12 +1,8 @@ include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) -add_partially_linked_object(LLVMX86AsmPrinter +add_llvm_library(LLVMX86AsmPrinter X86ATTAsmPrinter.cpp X86ATTInstPrinter.cpp X86AsmPrinter.cpp X86IntelAsmPrinter.cpp ) - -target_name_of_partially_linked_object(LLVMX86CodeGen n) - -add_dependencies(LLVMX86AsmPrinter ${n}) From dgregor at apple.com Tue Jun 23 12:58:52 2009 From: dgregor at apple.com (Douglas Gregor) Date: Tue, 23 Jun 2009 17:58:52 -0000 Subject: [llvm-commits] [llvm] r73970 - /llvm/trunk/cmake/modules/AddLLVM.cmake Message-ID: <200906231758.n5NHwq57027739@zion.cs.uiuc.edu> Author: dgregor Date: Tue Jun 23 12:58:51 2009 New Revision: 73970 URL: http://llvm.org/viewvc/llvm-project?rev=73970&view=rev Log: Eliminate some unused code in CMa'e add_llvm_target. No functionality change. Modified: llvm/trunk/cmake/modules/AddLLVM.cmake Modified: llvm/trunk/cmake/modules/AddLLVM.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=73970&r1=73969&r2=73970&view=diff ============================================================================== --- llvm/trunk/cmake/modules/AddLLVM.cmake (original) +++ llvm/trunk/cmake/modules/AddLLVM.cmake Tue Jun 23 12:58:51 2009 @@ -62,9 +62,4 @@ endif( TABLEGEN_OUTPUT ) include_directories(BEFORE ${CMAKE_CURRENT_BINARY_DIR}) add_llvm_library(LLVM${target_name} ${ARGN} ${TABLEGEN_OUTPUT}) - if (FALSE) - if( TABLEGEN_OUTPUT ) - add_dependencies(LLVM${target_name} ${target_name}Table_gen) - endif( TABLEGEN_OUTPUT ) - endif () endmacro(add_llvm_target) From resistor at mac.com Tue Jun 23 13:01:05 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 18:01:05 -0000 Subject: [llvm-commits] [llvm] r73971 - in /llvm/trunk: include/llvm/System/Atomic.h include/llvm/Type.h lib/System/Atomic.cpp lib/VMCore/Mangler.cpp Message-ID: <200906231801.n5NI16ZK027826@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 23 13:01:04 2009 New Revision: 73971 URL: http://llvm.org/viewvc/llvm-project?rev=73971&view=rev Log: Label the existing atomic functions as 32-bit specific, and add a 64-bit one that will be useful in the near future. Modified: llvm/trunk/include/llvm/System/Atomic.h llvm/trunk/include/llvm/Type.h llvm/trunk/lib/System/Atomic.cpp llvm/trunk/lib/VMCore/Mangler.cpp Modified: llvm/trunk/include/llvm/System/Atomic.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Atomic.h?rev=73971&r1=73970&r2=73971&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Atomic.h (original) +++ llvm/trunk/include/llvm/System/Atomic.h Tue Jun 23 13:01:04 2009 @@ -20,13 +20,14 @@ namespace sys { void MemoryFence(); - typedef uint32_t cas_flag; - cas_flag CompareAndSwap(volatile cas_flag* ptr, - cas_flag new_value, - cas_flag old_value); - cas_flag AtomicIncrement(volatile cas_flag* ptr); - cas_flag AtomicDecrement(volatile cas_flag* ptr); - cas_flag AtomicAdd(volatile cas_flag* ptr, cas_flag val); + uint32_t CompareAndSwap32(volatile uint32_t* ptr, + uint32_t new_value, + uint32_t old_value); + uint32_t AtomicIncrement32(volatile uint32_t* ptr); + uint32_t AtomicDecrement32(volatile uint32_t* ptr); + uint32_t AtomicAdd32(volatile uint32_t* ptr, uint32_t val); + + uint64_t AtomicAdd64(volatile uint64_t* ptr, uint64_t val); } } Modified: llvm/trunk/include/llvm/Type.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=73971&r1=73970&r2=73971&view=diff ============================================================================== --- llvm/trunk/include/llvm/Type.h (original) +++ llvm/trunk/include/llvm/Type.h Tue Jun 23 13:01:04 2009 @@ -103,7 +103,7 @@ /// has no AbstractTypeUsers, the type is deleted. This is only sensical for /// derived types. /// - mutable sys::cas_flag RefCount; + mutable uint32_t RefCount; const Type *getForwardedTypeInternal() const; @@ -338,7 +338,7 @@ void addRef() const { assert(isAbstract() && "Cannot add a reference to a non-abstract type!"); - sys::AtomicIncrement(&RefCount); + sys::AtomicIncrement32(&RefCount); } void dropRef() const { @@ -347,8 +347,8 @@ // If this is the last PATypeHolder using this object, and there are no // PATypeHandles using it, the type is dead, delete it now. - sys::cas_flag OldCount = sys::AtomicDecrement(&RefCount); - if (OldCount == 0 && AbstractTypeUsers.empty()) + uint32_t Count = sys::AtomicDecrement32(&RefCount); + if (Count == 0 && AbstractTypeUsers.empty()) this->destroy(); } Modified: llvm/trunk/lib/System/Atomic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Atomic.cpp?rev=73971&r1=73970&r2=73971&view=diff ============================================================================== --- llvm/trunk/lib/System/Atomic.cpp (original) +++ llvm/trunk/lib/System/Atomic.cpp Tue Jun 23 13:01:04 2009 @@ -35,11 +35,11 @@ #endif } -sys::cas_flag sys::CompareAndSwap(volatile sys::cas_flag* ptr, - sys::cas_flag new_value, - sys::cas_flag old_value) { +uint32_t sys::CompareAndSwap32(volatile uint32_t* ptr, + uint32_t new_value, + uint32_t old_value) { #if LLVM_MULTITHREADED==0 - sys::cas_flag result = *ptr; + uint32_t result = *ptr; if (result == old_value) *ptr = new_value; return result; @@ -52,7 +52,7 @@ #endif } -sys::cas_flag sys::AtomicIncrement(volatile sys::cas_flag* ptr) { +uint32_t sys::AtomicIncrement32(volatile uint32_t* ptr) { #if LLVM_MULTITHREADED==0 ++(*ptr); return *ptr; @@ -65,7 +65,7 @@ #endif } -sys::cas_flag sys::AtomicDecrement(volatile sys::cas_flag* ptr) { +uint32_t sys::AtomicDecrement32(volatile uint32_t* ptr) { #if LLVM_MULTITHREADED==0 --(*ptr); return *ptr; @@ -78,7 +78,7 @@ #endif } -sys::cas_flag sys::AtomicAdd(volatile sys::cas_flag* ptr, sys::cas_flag val) { +uint32_t sys::AtomicAdd32(volatile uint32_t* ptr, uint32_t val) { #if LLVM_MULTITHREADED==0 *ptr += val; return *ptr; @@ -91,4 +91,16 @@ #endif } +uint64_t sys::AtomicAdd64(volatile uint64_t* ptr, uint64_t val) { +#if LLVM_MULTITHREADED==0 + *ptr += val; + return *ptr; +#elif defined(__GNUC__) + return __sync_add_and_fetch(ptr, val); +#elif defined(_MSC_VER) + return InterlockedAdd64(ptr, val); +#else +# error No atomic add implementation for your platform! +#endif +} Modified: llvm/trunk/lib/VMCore/Mangler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Mangler.cpp?rev=73971&r1=73970&r2=73971&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Mangler.cpp (original) +++ llvm/trunk/lib/VMCore/Mangler.cpp Tue Jun 23 13:01:04 2009 @@ -168,7 +168,7 @@ static uint32_t GlobalID = 0; unsigned OldID = GlobalID; - sys::AtomicIncrement(&GlobalID); + sys::AtomicIncrement32(&GlobalID); Name = "__unnamed_" + utostr(TypeUniqueID) + "_" + utostr(OldID); } else { From dalej at apple.com Tue Jun 23 13:03:49 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 23 Jun 2009 18:03:49 -0000 Subject: [llvm-commits] [llvm] r73972 - /llvm/trunk/test/FrontendC/2007-05-07-PaddingElements.c Message-ID: <200906231803.n5NI3oPo027908@zion.cs.uiuc.edu> Author: johannes Date: Tue Jun 23 13:03:49 2009 New Revision: 73972 URL: http://llvm.org/viewvc/llvm-project?rev=73972&view=rev Log: See test. Judging from PR 1278, at the time the test was committed, the generated code was apparently doing stores directly into the return value aggregate; now, it's doing a copy from a compiler-generated static object. That object is initialized using [4 x i8] which breaks the test. I believe this change preserves the original point of the test. Of course it would be better for the code to do stores directly into the return aggregate, but that is not what happens at -O0; the llvm optimizers seem to do that on x86 but not on ppc32, possibly because of the explicit padding (which is unavoidable). I think it must have been being done by a gcc optimizer pass before. Modified: llvm/trunk/test/FrontendC/2007-05-07-PaddingElements.c Modified: llvm/trunk/test/FrontendC/2007-05-07-PaddingElements.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2007-05-07-PaddingElements.c?rev=73972&r1=73971&r2=73972&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/2007-05-07-PaddingElements.c (original) +++ llvm/trunk/test/FrontendC/2007-05-07-PaddingElements.c Tue Jun 23 13:03:49 2009 @@ -1,5 +1,5 @@ // PR 1278 -// RUN: %llvmgcc %s -S -emit-llvm -O0 -o - | not grep "4 x i8] zeroinitializer" +// RUN: %llvmgcc %s -S -emit-llvm -O0 -o - | grep {struct.s} | not grep "4 x i8] zeroinitializer" // RUN: %llvmgcc %s -S -emit-llvm -O0 -o - | not grep "i32 0, i32 2" struct s { double d1; From resistor at mac.com Tue Jun 23 13:12:42 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 18:12:42 -0000 Subject: [llvm-commits] [llvm] r73974 - in /llvm/trunk: include/llvm/Support/Timer.h lib/Support/Timer.cpp Message-ID: <200906231812.n5NICh3m028211@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 23 13:12:30 2009 New Revision: 73974 URL: http://llvm.org/viewvc/llvm-project?rev=73974&view=rev Log: Use 64-bit integer counters for tracking time, rather than doubles. This will be more atomic op friendly. Modified: llvm/trunk/include/llvm/Support/Timer.h llvm/trunk/lib/Support/Timer.cpp Modified: llvm/trunk/include/llvm/Support/Timer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Timer.h?rev=73974&r1=73973&r2=73974&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Timer.h (original) +++ llvm/trunk/include/llvm/Support/Timer.h Tue Jun 23 13:12:30 2009 @@ -34,12 +34,12 @@ /// if they are never started. /// class Timer { - double Elapsed; // Wall clock time elapsed in seconds - double UserTime; // User time elapsed - double SystemTime; // System time elapsed - ssize_t MemUsed; // Memory allocated (in bytes) - size_t PeakMem; // Peak memory used - size_t PeakMemBase; // Temporary for peak calculation... + uint64_t Elapsed; // Wall clock time elapsed in seconds + uint64_t UserTime; // User time elapsed + uint64_t SystemTime; // System time elapsed + uint64_t MemUsed; // Memory allocated (in bytes) + uint64_t PeakMem; // Peak memory used + uint64_t PeakMemBase; // Temporary for peak calculation... std::string Name; // The name of this time variable bool Started; // Has this time variable ever been started? TimerGroup *TG; // The TimerGroup this Timer is in. @@ -49,10 +49,10 @@ Timer(const Timer &T); ~Timer(); - double getProcessTime() const { return UserTime+SystemTime; } - double getWallTime() const { return Elapsed; } - ssize_t getMemUsed() const { return MemUsed; } - size_t getPeakMem() const { return PeakMem; } + uint64_t getProcessTime() const { return UserTime+SystemTime; } + uint64_t getWallTime() const { return Elapsed; } + uint64_t getMemUsed() const { return MemUsed; } + uint64_t getPeakMem() const { return PeakMem; } std::string getName() const { return Name; } const Timer &operator=(const Timer &T) { Modified: llvm/trunk/lib/Support/Timer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=73974&r1=73973&r2=73974&view=diff ============================================================================== --- llvm/trunk/lib/Support/Timer.cpp (original) +++ llvm/trunk/lib/Support/Timer.cpp Tue Jun 23 13:12:30 2009 @@ -112,8 +112,7 @@ } struct TimeRecord { - double Elapsed, UserTime, SystemTime; - ssize_t MemUsed; + uint64_t Elapsed, UserTime, SystemTime, MemUsed; }; static TimeRecord getTimeRecord(bool Start) { @@ -123,7 +122,7 @@ sys::TimeValue user(0,0); sys::TimeValue sys(0,0); - ssize_t MemUsed = 0; + uint64_t MemUsed = 0; if (Start) { MemUsed = getMemUsage(); sys::Process::GetTimeUsage(now,user,sys); @@ -132,9 +131,9 @@ MemUsed = getMemUsage(); } - Result.Elapsed = now.seconds() + now.microseconds() / 1000000.0; - Result.UserTime = user.seconds() + user.microseconds() / 1000000.0; - Result.SystemTime = sys.seconds() + sys.microseconds() / 1000000.0; + Result.Elapsed = now.seconds() * 1000000 + now.microseconds(); + Result.UserTime = user.seconds() * 1000000 + user.microseconds(); + Result.SystemTime = sys.seconds() * 1000000 + sys.microseconds(); Result.MemUsed = MemUsed; return Result; @@ -277,12 +276,13 @@ void Timer::print(const Timer &Total, std::ostream &OS) { if (Total.UserTime) - printVal(UserTime, Total.UserTime, OS); + printVal(UserTime / 1000000.0, Total.UserTime / 1000000.0, OS); if (Total.SystemTime) - printVal(SystemTime, Total.SystemTime, OS); + printVal(SystemTime / 1000000.0, Total.SystemTime / 1000000.0, OS); if (Total.getProcessTime()) - printVal(getProcessTime(), Total.getProcessTime(), OS); - printVal(Elapsed, Total.Elapsed, OS); + printVal(getProcessTime() / 1000000.0, + Total.getProcessTime() / 1000000.0, OS); + printVal(Elapsed / 1000000.0, Total.Elapsed / 1000000.0, OS); OS << " "; @@ -355,23 +355,23 @@ if (this != DefaultTimerGroup) { *OutStream << " Total Execution Time: "; - printAlignedFP(Total.getProcessTime(), 4, 5, *OutStream); + printAlignedFP(Total.getProcessTime() / 1000000.0, 4, 5, *OutStream); *OutStream << " seconds ("; - printAlignedFP(Total.getWallTime(), 4, 5, *OutStream); + printAlignedFP(Total.getWallTime() / 1000000.0, 4, 5, *OutStream); *OutStream << " wall clock)\n"; } *OutStream << "\n"; - if (Total.UserTime) + if (Total.UserTime / 1000000.0) *OutStream << " ---User Time---"; - if (Total.SystemTime) + if (Total.SystemTime / 1000000.0) *OutStream << " --System Time--"; - if (Total.getProcessTime()) + if (Total.getProcessTime() / 1000000.0) *OutStream << " --User+System--"; *OutStream << " ---Wall Time---"; - if (Total.getMemUsed()) + if (Total.getMemUsed() / 1000000.0) *OutStream << " ---Mem---"; - if (Total.getPeakMem()) + if (Total.getPeakMem() / 1000000.0) *OutStream << " -PeakMem-"; *OutStream << " --- Name ---\n"; From evan.cheng at apple.com Tue Jun 23 13:14:38 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 18:14:38 -0000 Subject: [llvm-commits] [llvm] r73975 - in /llvm/trunk/lib/Target/ARM: ARMISelDAGToDAG.cpp ARMInstrThumb2.td Message-ID: <200906231814.n5NIEdGT028296@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jun 23 13:14:38 2009 New Revision: 73975 URL: http://llvm.org/viewvc/llvm-project?rev=73975&view=rev Log: Rename SelectShifterOperand to SelectThumb2ShifterOperandReg. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=73975&r1=73974&r2=73975&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Jun 23 13:14:38 2009 @@ -92,8 +92,8 @@ bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base, SDValue &OffImm); - bool SelectShifterOperand(SDValue Op, SDValue N, - SDValue &BaseReg, SDValue &Opc); + bool SelectThumb2ShifterOperandReg(SDValue Op, SDValue N, + SDValue &BaseReg, SDValue &Opc); bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A, SDValue &B, SDValue &C); @@ -520,10 +520,10 @@ return false; } -bool ARMDAGToDAGISel::SelectShifterOperand(SDValue Op, - SDValue N, - SDValue &BaseReg, - SDValue &Opc) { +bool ARMDAGToDAGISel::SelectThumb2ShifterOperandReg(SDValue Op, + SDValue N, + SDValue &BaseReg, + SDValue &Opc) { ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); // Don't match base register only case. That is matched to a separate Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=73975&r1=73974&r2=73975&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jun 23 13:14:38 2009 @@ -14,7 +14,7 @@ // Shifted operands. No register controlled shifts for Thumb2. // Note: We do not support rrx shifted operands yet. def t2_so_reg : Operand, // reg imm - ComplexPattern { let PrintMethod = "printSOOperand"; let MIOperandInfo = (ops GPR, i32imm); From resistor at mac.com Tue Jun 23 13:21:19 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 18:21:19 -0000 Subject: [llvm-commits] [llvm] r73978 - in /llvm/trunk: include/llvm/Support/Timer.h lib/Support/Timer.cpp Message-ID: <200906231821.n5NILLbh028617@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 23 13:21:13 2009 New Revision: 73978 URL: http://llvm.org/viewvc/llvm-project?rev=73978&view=rev Log: Actually, these need to be signed integers, not unsigned. Modified: llvm/trunk/include/llvm/Support/Timer.h llvm/trunk/lib/Support/Timer.cpp Modified: llvm/trunk/include/llvm/Support/Timer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Timer.h?rev=73978&r1=73977&r2=73978&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Timer.h (original) +++ llvm/trunk/include/llvm/Support/Timer.h Tue Jun 23 13:21:13 2009 @@ -34,12 +34,12 @@ /// if they are never started. /// class Timer { - uint64_t Elapsed; // Wall clock time elapsed in seconds - uint64_t UserTime; // User time elapsed - uint64_t SystemTime; // System time elapsed - uint64_t MemUsed; // Memory allocated (in bytes) - uint64_t PeakMem; // Peak memory used - uint64_t PeakMemBase; // Temporary for peak calculation... + int64_t Elapsed; // Wall clock time elapsed in seconds + int64_t UserTime; // User time elapsed + int64_t SystemTime; // System time elapsed + int64_t MemUsed; // Memory allocated (in bytes) + int64_t PeakMem; // Peak memory used + int64_t PeakMemBase; // Temporary for peak calculation... std::string Name; // The name of this time variable bool Started; // Has this time variable ever been started? TimerGroup *TG; // The TimerGroup this Timer is in. @@ -49,10 +49,10 @@ Timer(const Timer &T); ~Timer(); - uint64_t getProcessTime() const { return UserTime+SystemTime; } - uint64_t getWallTime() const { return Elapsed; } - uint64_t getMemUsed() const { return MemUsed; } - uint64_t getPeakMem() const { return PeakMem; } + int64_t getProcessTime() const { return UserTime+SystemTime; } + int64_t getWallTime() const { return Elapsed; } + int64_t getMemUsed() const { return MemUsed; } + int64_t getPeakMem() const { return PeakMem; } std::string getName() const { return Name; } const Timer &operator=(const Timer &T) { Modified: llvm/trunk/lib/Support/Timer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=73978&r1=73977&r2=73978&view=diff ============================================================================== --- llvm/trunk/lib/Support/Timer.cpp (original) +++ llvm/trunk/lib/Support/Timer.cpp Tue Jun 23 13:21:13 2009 @@ -112,7 +112,7 @@ } struct TimeRecord { - uint64_t Elapsed, UserTime, SystemTime, MemUsed; + int64_t Elapsed, UserTime, SystemTime, MemUsed; }; static TimeRecord getTimeRecord(bool Start) { @@ -122,7 +122,7 @@ sys::TimeValue user(0,0); sys::TimeValue sys(0,0); - uint64_t MemUsed = 0; + int64_t MemUsed = 0; if (Start) { MemUsed = getMemUsage(); sys::Process::GetTimeUsage(now,user,sys); From dgregor at apple.com Tue Jun 23 13:30:17 2009 From: dgregor at apple.com (Douglas Gregor) Date: Tue, 23 Jun 2009 18:30:17 -0000 Subject: [llvm-commits] [llvm] r73979 - in /llvm/trunk: CMakeLists.txt cmake/modules/AddLLVM.cmake cmake/modules/LLVMConfig.cmake tools/CMakeLists.txt Message-ID: <200906231830.n5NIUI6S028929@zion.cs.uiuc.edu> Author: dgregor Date: Tue Jun 23 13:30:17 2009 New Revision: 73979 URL: http://llvm.org/viewvc/llvm-project?rev=73979&view=rev Log: CMake: remove support for llvm-config-generated dependencies in the build Modified: llvm/trunk/CMakeLists.txt llvm/trunk/cmake/modules/AddLLVM.cmake llvm/trunk/cmake/modules/LLVMConfig.cmake llvm/trunk/tools/CMakeLists.txt Modified: llvm/trunk/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=73979&r1=73978&r2=73979&view=diff ============================================================================== --- llvm/trunk/CMakeLists.txt (original) +++ llvm/trunk/CMakeLists.txt Tue Jun 23 13:30:17 2009 @@ -100,24 +100,6 @@ set(llvm_builded_incs_dir ${LLVM_BINARY_DIR}/include/llvm) -# The USE_EXPLICIT_DEPENDENCIES variable will be TRUE to indicate that -# we should use the library dependencies explicitly specified in the -# CMakeLists.txt files rather than those determined by -# llvm-config. This value must be true for non-make and IDE -# generators. -if (MSVC_IDE) - set(DEFAULT_USE_EXPLICIT_DEPENDENCIES ON) -elseif (XCODE) - set(DEFAULT_USE_EXPLICIT_DEPENDENCIES ON) -else () - set(DEFAULT_USE_EXPLICIT_DEPENDENCIES OFF) -endif () - -option(USE_EXPLICIT_DEPENDENCIES - "Use explicit dependencies instead of llvm-config" - ${DEFAULT_USE_EXPLICIT_DEPENDENCIES}) -mark_as_advanced(USE_EXPLICIT_DEPENDENCIES) - # Add path for custom modules set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} Modified: llvm/trunk/cmake/modules/AddLLVM.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=73979&r1=73978&r2=73979&view=diff ============================================================================== --- llvm/trunk/cmake/modules/AddLLVM.cmake (original) +++ llvm/trunk/cmake/modules/AddLLVM.cmake Tue Jun 23 13:30:17 2009 @@ -26,11 +26,7 @@ if( LLVM_LINK_COMPONENTS ) llvm_config(${name} ${LLVM_LINK_COMPONENTS}) endif( LLVM_LINK_COMPONENTS ) - if( USE_EXPLICIT_DEPENDENCIES ) - target_link_libraries(${name} ${llvm_libs}) - else( ) - add_dependencies(${name} llvm-config.target) - endif( ) + target_link_libraries(${name} ${llvm_libs}) get_system_libs(llvm_system_libs) if( llvm_system_libs ) target_link_libraries(${name} ${llvm_system_libs}) Modified: llvm/trunk/cmake/modules/LLVMConfig.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMConfig.cmake?rev=73979&r1=73978&r2=73979&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMConfig.cmake (original) +++ llvm/trunk/cmake/modules/LLVMConfig.cmake Tue Jun 23 13:30:17 2009 @@ -20,12 +20,7 @@ macro(llvm_config executable) - # extra args is the list of link components. - if( USE_EXPLICIT_DEPENDENCIES ) - explicit_llvm_config(${executable} ${ARGN}) - else( ) - nix_llvm_config(${executable} ${ARGN}) - endif( ) + explicit_llvm_config(${executable} ${ARGN}) endmacro(llvm_config) @@ -127,44 +122,7 @@ set(${out_libs} ${result} PARENT_SCOPE) endfunction(explicit_map_components_to_libraries) - -macro(nix_llvm_config executable) - set(lc "") - foreach(c ${ARGN}) - set(lc "${lc} ${c}") - endforeach(c) - if( NOT HAVE_LLVM_CONFIG ) - target_link_libraries(${executable} - "`${LLVM_TOOLS_BINARY_DIR}/llvm-config --libs ${lc}`") - else( NOT HAVE_LLVM_CONFIG ) - # tbi: Error handling. - if( NOT PERL_EXECUTABLE ) - message(FATAL_ERROR "Perl required but not found!") - endif( NOT PERL_EXECUTABLE ) - execute_process( - COMMAND sh -c "${PERL_EXECUTABLE} ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/llvm-config --libs ${lc}" - RESULT_VARIABLE rv - OUTPUT_VARIABLE libs - OUTPUT_STRIP_TRAILING_WHITESPACE) - if(NOT rv EQUAL 0) - message(FATAL_ERROR "llvm-config failed for executable ${executable}") - endif(NOT rv EQUAL 0) - string(REPLACE " " ";" libs ${libs}) - foreach(c ${libs}) - if(c MATCHES ".*\\.o") - get_filename_component(fn ${c} NAME) - target_link_libraries(${executable} - ${CMAKE_ARCHIVE_OUTPUT_DIRECTORY}/${CMAKE_CFG_INTDIR}/${fn}) - else(c MATCHES ".*\\.o") - string(REPLACE "-l" "" fn ${c}) - target_link_libraries(${executable} ${fn}) - endif(c MATCHES ".*\\.o") - endforeach(c) - endif( NOT HAVE_LLVM_CONFIG ) -endmacro(nix_llvm_config) - - -# This data is used on MSVC for stablishing executable/library +# This data is used to establish executable/library # dependencies. Comes from the llvm-config script, which is built and # installed on the bin directory for MinGW or Linux. At the end of the # script, you'll see lines like this: Modified: llvm/trunk/tools/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/CMakeLists.txt?rev=73979&r1=73978&r2=73979&view=diff ============================================================================== --- llvm/trunk/tools/CMakeLists.txt (original) +++ llvm/trunk/tools/CMakeLists.txt Tue Jun 23 13:30:17 2009 @@ -2,7 +2,9 @@ # large and three small executables. This is done to minimize memory load # in parallel builds. Please retain this ordering. -if (NOT USE_EXPLICIT_DEPENDENCIES) +# FIXME: We don't yet have the ability to build llvm-config with CMake +# based on explicit dependencies. +if (FALSE) add_subdirectory(llvm-config) endif() From resistor at mac.com Tue Jun 23 13:30:27 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 18:30:27 -0000 Subject: [llvm-commits] [llvm] r73980 - in /llvm/trunk: include/llvm/System/Atomic.h include/llvm/Type.h lib/System/Atomic.cpp lib/VMCore/Mangler.cpp Message-ID: <200906231830.n5NIUSqc028952@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 23 13:30:27 2009 New Revision: 73980 URL: http://llvm.org/viewvc/llvm-project?rev=73980&view=rev Log: Atomic ops that do arithmetic use signed arithmetic. Modified: llvm/trunk/include/llvm/System/Atomic.h llvm/trunk/include/llvm/Type.h llvm/trunk/lib/System/Atomic.cpp llvm/trunk/lib/VMCore/Mangler.cpp Modified: llvm/trunk/include/llvm/System/Atomic.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Atomic.h?rev=73980&r1=73979&r2=73980&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Atomic.h (original) +++ llvm/trunk/include/llvm/System/Atomic.h Tue Jun 23 13:30:27 2009 @@ -23,11 +23,11 @@ uint32_t CompareAndSwap32(volatile uint32_t* ptr, uint32_t new_value, uint32_t old_value); - uint32_t AtomicIncrement32(volatile uint32_t* ptr); - uint32_t AtomicDecrement32(volatile uint32_t* ptr); - uint32_t AtomicAdd32(volatile uint32_t* ptr, uint32_t val); + int32_t AtomicIncrement32(volatile int32_t* ptr); + int32_t AtomicDecrement32(volatile int32_t* ptr); + int32_t AtomicAdd32(volatile int32_t* ptr, int32_t val); - uint64_t AtomicAdd64(volatile uint64_t* ptr, uint64_t val); + int64_t AtomicAdd64(volatile int64_t* ptr, int64_t val); } } Modified: llvm/trunk/include/llvm/Type.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=73980&r1=73979&r2=73980&view=diff ============================================================================== --- llvm/trunk/include/llvm/Type.h (original) +++ llvm/trunk/include/llvm/Type.h Tue Jun 23 13:30:27 2009 @@ -103,7 +103,7 @@ /// has no AbstractTypeUsers, the type is deleted. This is only sensical for /// derived types. /// - mutable uint32_t RefCount; + mutable int32_t RefCount; const Type *getForwardedTypeInternal() const; @@ -347,7 +347,7 @@ // If this is the last PATypeHolder using this object, and there are no // PATypeHandles using it, the type is dead, delete it now. - uint32_t Count = sys::AtomicDecrement32(&RefCount); + int32_t Count = sys::AtomicDecrement32(&RefCount); if (Count == 0 && AbstractTypeUsers.empty()) this->destroy(); } Modified: llvm/trunk/lib/System/Atomic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Atomic.cpp?rev=73980&r1=73979&r2=73980&view=diff ============================================================================== --- llvm/trunk/lib/System/Atomic.cpp (original) +++ llvm/trunk/lib/System/Atomic.cpp Tue Jun 23 13:30:27 2009 @@ -52,7 +52,7 @@ #endif } -uint32_t sys::AtomicIncrement32(volatile uint32_t* ptr) { +int32_t sys::AtomicIncrement32(volatile int32_t* ptr) { #if LLVM_MULTITHREADED==0 ++(*ptr); return *ptr; @@ -65,7 +65,7 @@ #endif } -uint32_t sys::AtomicDecrement32(volatile uint32_t* ptr) { +int32_t sys::AtomicDecrement32(volatile int32_t* ptr) { #if LLVM_MULTITHREADED==0 --(*ptr); return *ptr; @@ -78,7 +78,7 @@ #endif } -uint32_t sys::AtomicAdd32(volatile uint32_t* ptr, uint32_t val) { +int32_t sys::AtomicAdd32(volatile int32_t* ptr, int32_t val) { #if LLVM_MULTITHREADED==0 *ptr += val; return *ptr; @@ -91,7 +91,7 @@ #endif } -uint64_t sys::AtomicAdd64(volatile uint64_t* ptr, uint64_t val) { +int64_t sys::AtomicAdd64(volatile int64_t* ptr, int64_t val) { #if LLVM_MULTITHREADED==0 *ptr += val; return *ptr; Modified: llvm/trunk/lib/VMCore/Mangler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Mangler.cpp?rev=73980&r1=73979&r2=73980&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Mangler.cpp (original) +++ llvm/trunk/lib/VMCore/Mangler.cpp Tue Jun 23 13:30:27 2009 @@ -165,9 +165,9 @@ } else if (!GV->hasName()) { // Must mangle the global into a unique ID. unsigned TypeUniqueID = getTypeID(GV->getType()); - static uint32_t GlobalID = 0; + static int32_t GlobalID = 0; - unsigned OldID = GlobalID; + int32_t OldID = GlobalID; sys::AtomicIncrement32(&GlobalID); Name = "__unnamed_" + utostr(TypeUniqueID) + "_" + utostr(OldID); From dalej at apple.com Tue Jun 23 13:34:41 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 23 Jun 2009 18:34:41 -0000 Subject: [llvm-commits] [llvm] r73981 - /llvm/trunk/test/FrontendC/2008-03-24-BitField-And-Alloca.c Message-ID: <200906231834.n5NIYgKO029120@zion.cs.uiuc.edu> Author: johannes Date: Tue Jun 23 13:34:37 2009 New Revision: 73981 URL: http://llvm.org/viewvc/llvm-project?rev=73981&view=rev Log: This test only works on ppc32 if some optimization is done before generating LLVM IR; it is correct in the code as written to use 8-byte-aligned operations to copy Key in bar. Formerly the gcc inliner was run, now it isn't. I don't think it's possible to preserve this as a pure FE test. Adding -O2 lets the llvm optimizers get rid of the 8-byte-aligned stores, at least. Modified: llvm/trunk/test/FrontendC/2008-03-24-BitField-And-Alloca.c Modified: llvm/trunk/test/FrontendC/2008-03-24-BitField-And-Alloca.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2008-03-24-BitField-And-Alloca.c?rev=73981&r1=73980&r2=73981&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/2008-03-24-BitField-And-Alloca.c (original) +++ llvm/trunk/test/FrontendC/2008-03-24-BitField-And-Alloca.c Tue Jun 23 13:34:37 2009 @@ -1,5 +1,5 @@ // RUN: %llvmgcc -O2 -S %s -o - | not grep alloca -// RUN: %llvmgcc -m32 -S %s -o - | grep store | not grep {align 8} +// RUN: %llvmgcc -m32 -O2 -S %s -o - | grep store | not grep {align 8} enum { PP_C, From sabre at nondot.org Tue Jun 23 13:41:44 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 23 Jun 2009 18:41:44 -0000 Subject: [llvm-commits] [llvm] r73982 - in /llvm/trunk/tools/llvm-mc: AsmParser.cpp AsmParser.h CMakeLists.txt MC-X86Specific.cpp Message-ID: <200906231841.n5NIfkTc029378@zion.cs.uiuc.edu> Author: lattner Date: Tue Jun 23 13:41:30 2009 New Revision: 73982 URL: http://llvm.org/viewvc/llvm-project?rev=73982&view=rev Log: refactor a bunch of X86 specific stuff out to its own file. Added: llvm/trunk/tools/llvm-mc/MC-X86Specific.cpp Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp llvm/trunk/tools/llvm-mc/AsmParser.h llvm/trunk/tools/llvm-mc/CMakeLists.txt Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=73982&r1=73981&r2=73982&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Tue Jun 23 13:41:30 2009 @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "AsmParser.h" +#include "llvm/MC/MCInst.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -49,182 +50,6 @@ } -struct AsmParser::X86Operand { - enum { - Register, - Immediate, - Memory - } Kind; - - union { - struct { - unsigned RegNo; - } Reg; - - struct { - // FIXME: Should be a general expression. - int64_t Val; - } Imm; - - struct { - unsigned SegReg; - int64_t Disp; // FIXME: Should be a general expression. - unsigned BaseReg; - unsigned Scale; - unsigned ScaleReg; - } Mem; - }; - - static X86Operand CreateReg(unsigned RegNo) { - X86Operand Res; - Res.Kind = Register; - Res.Reg.RegNo = RegNo; - return Res; - } - static X86Operand CreateImm(int64_t Val) { - X86Operand Res; - Res.Kind = Immediate; - Res.Imm.Val = Val; - return Res; - } - static X86Operand CreateMem(unsigned SegReg, int64_t Disp, unsigned BaseReg, - unsigned Scale, unsigned ScaleReg) { - X86Operand Res; - Res.Kind = Memory; - Res.Mem.SegReg = SegReg; - Res.Mem.Disp = Disp; - Res.Mem.BaseReg = BaseReg; - Res.Mem.Scale = Scale; - Res.Mem.ScaleReg = ScaleReg; - return Res; - } -}; - -bool AsmParser::ParseX86Operand(X86Operand &Op) { - switch (Lexer.getKind()) { - default: - return ParseX86MemOperand(Op); - case asmtok::Register: - // FIXME: Decode reg #. - // FIXME: if a segment register, this could either be just the seg reg, or - // the start of a memory operand. - Op = X86Operand::CreateReg(123); - Lexer.Lex(); // Eat register. - return false; - case asmtok::Dollar: { - // $42 -> immediate. - Lexer.Lex(); - int64_t Val; - if (ParseExpression(Val)) - return TokError("expected integer constant"); - Op = X86Operand::CreateReg(Val); - return false; - case asmtok::Star: - Lexer.Lex(); // Eat the star. - - if (Lexer.is(asmtok::Register)) { - Op = X86Operand::CreateReg(123); - Lexer.Lex(); // Eat register. - } else if (ParseX86MemOperand(Op)) - return true; - - // FIXME: Note that these are 'dereferenced' so that clients know the '*' is - // there. - return false; - } - } -} - -/// ParseX86MemOperand: segment: disp(basereg, indexreg, scale) -bool AsmParser::ParseX86MemOperand(X86Operand &Op) { - // FIXME: If SegReg ':' (e.g. %gs:), eat and remember. - unsigned SegReg = 0; - - - // We have to disambiguate a parenthesized expression "(4+5)" from the start - // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The - // only way to do this without lookahead is to eat the ( and see what is after - // it. - int64_t Disp = 0; - if (Lexer.isNot(asmtok::LParen)) { - if (ParseExpression(Disp)) return true; - - // After parsing the base expression we could either have a parenthesized - // memory address or not. If not, return now. If so, eat the (. - if (Lexer.isNot(asmtok::LParen)) { - Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0); - return false; - } - - // Eat the '('. - Lexer.Lex(); - } else { - // Okay, we have a '('. We don't know if this is an expression or not, but - // so we have to eat the ( to see beyond it. - Lexer.Lex(); // Eat the '('. - - if (Lexer.is(asmtok::Register) || Lexer.is(asmtok::Comma)) { - // Nothing to do here, fall into the code below with the '(' part of the - // memory operand consumed. - } else { - // It must be an parenthesized expression, parse it now. - if (ParseParenExpr(Disp) || - ParseBinOpRHS(1, Disp)) - return true; - - // After parsing the base expression we could either have a parenthesized - // memory address or not. If not, return now. If so, eat the (. - if (Lexer.isNot(asmtok::LParen)) { - Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0); - return false; - } - - // Eat the '('. - Lexer.Lex(); - } - } - - // If we reached here, then we just ate the ( of the memory operand. Process - // the rest of the memory operand. - unsigned BaseReg = 0, ScaleReg = 0, Scale = 0; - - if (Lexer.is(asmtok::Register)) { - BaseReg = 123; // FIXME: decode reg # - Lexer.Lex(); // eat the register. - } - - if (Lexer.is(asmtok::Comma)) { - Lexer.Lex(); // eat the comma. - - if (Lexer.is(asmtok::Register)) { - ScaleReg = 123; // FIXME: decode reg # - Lexer.Lex(); // eat the register. - Scale = 1; // If not specified, the scale defaults to 1. - } - - if (Lexer.is(asmtok::Comma)) { - Lexer.Lex(); // eat the comma. - - // If present, get and validate scale amount. - if (Lexer.is(asmtok::IntVal)) { - int64_t ScaleVal = Lexer.getCurIntVal(); - if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8) - return TokError("scale factor in address must be 1, 2, 4 or 8"); - Lexer.Lex(); // eat the scale. - Scale = (unsigned)ScaleVal; - } - } - } - - // Ok, we've eaten the memory operand, verify we have a ')' and eat it too. - if (Lexer.isNot(asmtok::RParen)) - return TokError("unexpected token in memory operand"); - Lexer.Lex(); // Eat the ')'. - - Op = X86Operand::CreateMem(SegReg, Disp, BaseReg, Scale, ScaleReg); - return false; -} - /// ParseParenExpr - Parse a paren expression and return it. /// NOTE: This assumes the leading '(' has already been consumed. /// @@ -368,27 +193,10 @@ return false; } - // If it's an instruction, parse an operand list. - std::vector Operands; - - // Read the first operand, if present. Note that we require a newline at the - // end of file, so we don't have to worry about Eof here. - if (Lexer.isNot(asmtok::EndOfStatement)) { - X86Operand Op; - if (ParseX86Operand(Op)) - return true; - Operands.push_back(Op); - } - while (Lexer.is(asmtok::Comma)) { - Lexer.Lex(); // Eat the comma. - - // Parse and remember the operand. - X86Operand Op; - if (ParseX86Operand(Op)) - return true; - Operands.push_back(Op); - } + MCInst Inst; + if (ParseX86InstOperands(Inst)) + return true; if (Lexer.isNot(asmtok::EndOfStatement)) return TokError("unexpected token in operand list"); @@ -397,7 +205,7 @@ Lexer.Lex(); // Instruction is good, process it. - outs() << "Found instruction: " << IDVal << " with " << Operands.size() + outs() << "Found instruction: " << IDVal << " with " << Inst.getNumOperands() << " operands.\n"; // Skip to end of line for now. Modified: llvm/trunk/tools/llvm-mc/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.h?rev=73982&r1=73981&r2=73982&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.h (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.h Tue Jun 23 13:41:30 2009 @@ -17,6 +17,7 @@ #include "AsmLexer.h" namespace llvm { +class MCInst; class AsmParser { AsmLexer Lexer; @@ -36,12 +37,15 @@ void EatToEndOfStatement(); - bool ParseX86Operand(X86Operand &Op); - bool ParseX86MemOperand(X86Operand &Op); bool ParseExpression(int64_t &Res); bool ParsePrimaryExpr(int64_t &Res); bool ParseBinOpRHS(unsigned Precedence, int64_t &Res); bool ParseParenExpr(int64_t &Res); + + // X86 specific. + bool ParseX86InstOperands(MCInst &Inst); + bool ParseX86Operand(X86Operand &Op); + bool ParseX86MemOperand(X86Operand &Op); }; } // end namespace llvm Modified: llvm/trunk/tools/llvm-mc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/CMakeLists.txt?rev=73982&r1=73981&r2=73982&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-mc/CMakeLists.txt Tue Jun 23 13:41:30 2009 @@ -4,4 +4,5 @@ llvm-mc.cpp AsmLexer.cpp AsmParser.cpp + MC-X86Specific.cpp ) Added: llvm/trunk/tools/llvm-mc/MC-X86Specific.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/MC-X86Specific.cpp?rev=73982&view=auto ============================================================================== --- llvm/trunk/tools/llvm-mc/MC-X86Specific.cpp (added) +++ llvm/trunk/tools/llvm-mc/MC-X86Specific.cpp Tue Jun 23 13:41:30 2009 @@ -0,0 +1,222 @@ +//===- MC-X86Specific.cpp - X86-Specific code for MC ----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements X86-specific parsing, encoding and decoding stuff for +// MC. +// +//===----------------------------------------------------------------------===// + +#include "AsmParser.h" +#include "llvm/MC/MCInst.h" +using namespace llvm; + +/// X86Operand - Instances of this class represent one X86 machine instruction. +struct AsmParser::X86Operand { + enum { + Register, + Immediate, + Memory + } Kind; + + union { + struct { + unsigned RegNo; + } Reg; + + struct { + // FIXME: Should be a general expression. + int64_t Val; + } Imm; + + struct { + unsigned SegReg; + int64_t Disp; // FIXME: Should be a general expression. + unsigned BaseReg; + unsigned Scale; + unsigned ScaleReg; + } Mem; + }; + + static X86Operand CreateReg(unsigned RegNo) { + X86Operand Res; + Res.Kind = Register; + Res.Reg.RegNo = RegNo; + return Res; + } + static X86Operand CreateImm(int64_t Val) { + X86Operand Res; + Res.Kind = Immediate; + Res.Imm.Val = Val; + return Res; + } + static X86Operand CreateMem(unsigned SegReg, int64_t Disp, unsigned BaseReg, + unsigned Scale, unsigned ScaleReg) { + X86Operand Res; + Res.Kind = Memory; + Res.Mem.SegReg = SegReg; + Res.Mem.Disp = Disp; + Res.Mem.BaseReg = BaseReg; + Res.Mem.Scale = Scale; + Res.Mem.ScaleReg = ScaleReg; + return Res; + } + + void AddToMCInst(MCInst &I) { + // FIXME: Add in x86 order here. + } +}; + +bool AsmParser::ParseX86Operand(X86Operand &Op) { + switch (Lexer.getKind()) { + default: + return ParseX86MemOperand(Op); + case asmtok::Register: + // FIXME: Decode reg #. + // FIXME: if a segment register, this could either be just the seg reg, or + // the start of a memory operand. + Op = X86Operand::CreateReg(123); + Lexer.Lex(); // Eat register. + return false; + case asmtok::Dollar: { + // $42 -> immediate. + Lexer.Lex(); + int64_t Val; + if (ParseExpression(Val)) + return TokError("expected integer constant"); + Op = X86Operand::CreateReg(Val); + return false; + case asmtok::Star: + Lexer.Lex(); // Eat the star. + + if (Lexer.is(asmtok::Register)) { + Op = X86Operand::CreateReg(123); + Lexer.Lex(); // Eat register. + } else if (ParseX86MemOperand(Op)) + return true; + + // FIXME: Note that these are 'dereferenced' so that clients know the '*' is + // there. + return false; + } + } +} + +/// ParseX86MemOperand: segment: disp(basereg, indexreg, scale) +bool AsmParser::ParseX86MemOperand(X86Operand &Op) { + // FIXME: If SegReg ':' (e.g. %gs:), eat and remember. + unsigned SegReg = 0; + + // We have to disambiguate a parenthesized expression "(4+5)" from the start + // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The + // only way to do this without lookahead is to eat the ( and see what is after + // it. + int64_t Disp = 0; + if (Lexer.isNot(asmtok::LParen)) { + if (ParseExpression(Disp)) return true; + + // After parsing the base expression we could either have a parenthesized + // memory address or not. If not, return now. If so, eat the (. + if (Lexer.isNot(asmtok::LParen)) { + Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0); + return false; + } + + // Eat the '('. + Lexer.Lex(); + } else { + // Okay, we have a '('. We don't know if this is an expression or not, but + // so we have to eat the ( to see beyond it. + Lexer.Lex(); // Eat the '('. + + if (Lexer.is(asmtok::Register) || Lexer.is(asmtok::Comma)) { + // Nothing to do here, fall into the code below with the '(' part of the + // memory operand consumed. + } else { + // It must be an parenthesized expression, parse it now. + if (ParseParenExpr(Disp) || + ParseBinOpRHS(1, Disp)) + return true; + + // After parsing the base expression we could either have a parenthesized + // memory address or not. If not, return now. If so, eat the (. + if (Lexer.isNot(asmtok::LParen)) { + Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0); + return false; + } + + // Eat the '('. + Lexer.Lex(); + } + } + + // If we reached here, then we just ate the ( of the memory operand. Process + // the rest of the memory operand. + unsigned BaseReg = 0, ScaleReg = 0, Scale = 0; + + if (Lexer.is(asmtok::Register)) { + BaseReg = 123; // FIXME: decode reg # + Lexer.Lex(); // eat the register. + } + + if (Lexer.is(asmtok::Comma)) { + Lexer.Lex(); // eat the comma. + + if (Lexer.is(asmtok::Register)) { + ScaleReg = 123; // FIXME: decode reg # + Lexer.Lex(); // eat the register. + Scale = 1; // If not specified, the scale defaults to 1. + } + + if (Lexer.is(asmtok::Comma)) { + Lexer.Lex(); // eat the comma. + + // If present, get and validate scale amount. + if (Lexer.is(asmtok::IntVal)) { + int64_t ScaleVal = Lexer.getCurIntVal(); + if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8) + return TokError("scale factor in address must be 1, 2, 4 or 8"); + Lexer.Lex(); // eat the scale. + Scale = (unsigned)ScaleVal; + } + } + } + + // Ok, we've eaten the memory operand, verify we have a ')' and eat it too. + if (Lexer.isNot(asmtok::RParen)) + return TokError("unexpected token in memory operand"); + Lexer.Lex(); // Eat the ')'. + + Op = X86Operand::CreateMem(SegReg, Disp, BaseReg, Scale, ScaleReg); + return false; +} + +/// ParseX86InstOperands - Parse the operands of an X86 instruction and return +/// them as the operands of an MCInst. +bool AsmParser::ParseX86InstOperands(MCInst &Inst) { + // If no operands are present, just return. + if (Lexer.is(asmtok::EndOfStatement)) + return false; + + // Read the first operand. + X86Operand Op; + if (ParseX86Operand(Op)) + return true; + Op.AddToMCInst(Inst); + + while (Lexer.is(asmtok::Comma)) { + Lexer.Lex(); // Eat the comma. + + // Parse and remember the operand. + Op = X86Operand(); + if (ParseX86Operand(Op)) + return true; + Op.AddToMCInst(Inst); + } + return false; +} From dalej at apple.com Tue Jun 23 13:42:27 2009 From: dalej at apple.com (Dale Johannesen) Date: Tue, 23 Jun 2009 18:42:27 -0000 Subject: [llvm-commits] [llvm] r73983 - in /llvm/trunk/test/FrontendC: 2009-02-13-zerosize-union-field-ppc.c 2009-02-13-zerosize-union-field.c Message-ID: <200906231842.n5NIgSJc029427@zion.cs.uiuc.edu> Author: johannes Date: Tue Jun 23 13:42:26 2009 New Revision: 73983 URL: http://llvm.org/viewvc/llvm-project?rev=73983&view=rev Log: The correct values here (as defined by gcc-4.2) are different for ppc; add another version of the test. Added: llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field-ppc.c Modified: llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field.c Added: llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field-ppc.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field-ppc.c?rev=73983&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field-ppc.c (added) +++ llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field-ppc.c Tue Jun 23 13:42:26 2009 @@ -0,0 +1,14 @@ +// RUN: %llvmgcc %s -m32 -S -o - | grep {i32 32} | count 3 +// XFAIL: * +// XTARGET: powerpc +// Every printf has 'i32 0' for the GEP of the string; no point counting those. +typedef unsigned int Foo __attribute__((aligned(32))); +typedef union{Foo:0;}a; +typedef union{int x; Foo:0;}b; +extern int printf(const char*, ...); +main() { + printf("%ld\n", sizeof(a)); + printf("%ld\n", __alignof__(a)); + printf("%ld\n", sizeof(b)); + printf("%ld\n", __alignof__(b)); +} Modified: llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field.c?rev=73983&r1=73982&r2=73983&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field.c (original) +++ llvm/trunk/test/FrontendC/2009-02-13-zerosize-union-field.c Tue Jun 23 13:42:26 2009 @@ -1,5 +1,6 @@ // RUN: %llvmgcc %s -m32 -S -o - | grep {i32 1} | count 1 // RUN: %llvmgcc %s -m32 -S -o - | grep {i32 4} | count 2 +// XFAIL: powerpc // Every printf has 'i32 0' for the GEP of the string; no point counting those. typedef unsigned int Foo __attribute__((aligned(32))); typedef union{Foo:0;}a; From sabre at nondot.org Tue Jun 23 13:58:02 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 23 Jun 2009 18:58:02 -0000 Subject: [llvm-commits] [llvm] r73984 - in /llvm/trunk/include/llvm/MC: MCImm.h MCInst.h Message-ID: <200906231858.n5NIw227029893@zion.cs.uiuc.edu> Author: lattner Date: Tue Jun 23 13:58:00 2009 New Revision: 73984 URL: http://llvm.org/viewvc/llvm-project?rev=73984&view=rev Log: add a simple MCImm class. Added: llvm/trunk/include/llvm/MC/MCImm.h Modified: llvm/trunk/include/llvm/MC/MCInst.h Added: llvm/trunk/include/llvm/MC/MCImm.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCImm.h?rev=73984&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCImm.h (added) +++ llvm/trunk/include/llvm/MC/MCImm.h Tue Jun 23 13:58:00 2009 @@ -0,0 +1,55 @@ +//===-- llvm/MC/MCImm.h - MCImm class ---------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of the MCInst and MCOperand classes, which +// is the basic representation used to represent low-level machine code +// instructions. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCIMM_H +#define LLVM_MC_MCIMM_H + +namespace llvm { +class MCSymbol; + +/// MCImm - This represents an "assembler immediate". In its most general form, +/// this can hold "SymbolA - SymbolB + imm64". Not all targets supports +/// relocations of this general form, but we need to represent this anyway. +class MCImm { + MCSymbol *SymA, *SymB; + int64_t Cst; +public: + + int64_t getCst() const { return Cst; } + MCSymbol *getSymA() const { return SymA; } + MCSymbol *getSymB() const { return SymB; } + + + static MCImm get(MCSymbol *SymA, MCSymbol *SymB = 0, int64_t Val = 0) { + MCImm R; + R.Cst = Val; + R.SymA = SymA; + R.SymB = SymB; + return R; + } + + static MCImm get(int64_t Val) { + MCImm R; + R.Cst = Val; + R.SymA = 0; + R.SymB = 0; + return R; + } + +}; + +} // end namespace llvm + +#endif Modified: llvm/trunk/include/llvm/MC/MCInst.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInst.h?rev=73984&r1=73983&r2=73984&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInst.h (original) +++ llvm/trunk/include/llvm/MC/MCInst.h Tue Jun 23 13:58:00 2009 @@ -13,10 +13,10 @@ // //===----------------------------------------------------------------------===// - #ifndef LLVM_MC_MCINST_H #define LLVM_MC_MCINST_H +#include "llvm/MC/MCImm.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/DataTypes.h" #include "llvm/Support/DebugLoc.h" @@ -30,13 +30,15 @@ kInvalid, ///< Uninitialized. kRegister, ///< Register operand. kImmediate, ///< Immediate operand. - kMBBLabel ///< Basic block label. + kMBBLabel, ///< Basic block label. + kMCImm }; unsigned char Kind; union { unsigned RegVal; int64_t ImmVal; + MCImm MCImmVal; struct { unsigned FunctionNo; unsigned BlockNo; From evan.cheng at apple.com Tue Jun 23 14:38:13 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 19:38:13 -0000 Subject: [llvm-commits] [llvm] r73985 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrThumb.td Message-ID: <200906231938.n5NJcD0n031182@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jun 23 14:38:13 2009 New Revision: 73985 URL: http://llvm.org/viewvc/llvm-project?rev=73985&view=rev Log: Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=73985&r1=73984&r2=73985&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Jun 23 14:38:13 2009 @@ -751,6 +751,28 @@ list Predicates = [IsThumb, HasV5T]; } +// Thumb1 only +class Thumb1I pattern> + : InstARM { + let OutOperandList = outs; + let InOperandList = ins; + let AsmString = asm; + let Pattern = pattern; + list Predicates = [IsThumb1Only]; +} + +class T1I pattern> + : Thumb1I; + +// Two-address instructions +class T1It pattern> + : Thumb1I; + +class Thumb1Pat : Pat { + list Predicates = [IsThumb1Only]; +} + // T2I - Thumb2 instruction. class Thumb2I; -def tADDS : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tADDS : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "add $dst, $lhs, $rhs", [(set tGPR:$dst, (addc tGPR:$lhs, tGPR:$rhs))]>; -def tADDi3 : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), +def tADDi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "add $dst, $lhs, $rhs", [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>; -def tADDi8 : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), +def tADDi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "add $dst, $rhs", [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>; -def tADDrr : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tADDrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "add $dst, $lhs, $rhs", [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>; let neverHasSideEffects = 1 in -def tADDhirr : TIt<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tADDhirr : T1It<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs), "add $dst, $rhs @ addhirr", []>; -def tADDrPCi : TI<(outs tGPR:$dst), (ins i32imm:$rhs), +def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), "add $dst, pc, $rhs * 4", []>; -def tADDrSPi : TI<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), +def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), "add $dst, $sp, $rhs * 4 @ addrspi", []>; -def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), +def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), "add $dst, $rhs * 4", []>; let isCommutable = 1 in -def tAND : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tAND : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "and $dst, $rhs", [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>; -def tASRri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), +def tASRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "asr $dst, $lhs, $rhs", [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>; -def tASRrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tASRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "asr $dst, $rhs", [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>; -def tBIC : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tBIC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "bic $dst, $rhs", [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>; -def tCMN : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs), +def tCMN : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs), "cmn $lhs, $rhs", [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; -def tCMPi8 : TI<(outs), (ins tGPR:$lhs, i32imm:$rhs), +def tCMPi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs), "cmp $lhs, $rhs", [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>; -def tCMPr : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs), +def tCMPr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs), "cmp $lhs, $rhs", [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>; -def tTST : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs), +def tTST : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs), "tst $lhs, $rhs", [(ARMcmpNZ (and tGPR:$lhs, tGPR:$rhs), 0)]>; -def tCMNNZ : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs), +def tCMNNZ : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs), "cmn $lhs, $rhs", [(ARMcmpNZ tGPR:$lhs, (ineg tGPR:$rhs))]>; -def tCMPNZi8 : TI<(outs), (ins tGPR:$lhs, i32imm:$rhs), +def tCMPNZi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs), "cmp $lhs, $rhs", [(ARMcmpNZ tGPR:$lhs, imm0_255:$rhs)]>; -def tCMPNZr : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs), +def tCMPNZr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs), "cmp $lhs, $rhs", [(ARMcmpNZ tGPR:$lhs, tGPR:$rhs)]>; // TODO: A7-37: CMP(3) - cmp hi regs let isCommutable = 1 in -def tEOR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tEOR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "eor $dst, $rhs", [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>; -def tLSLri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), +def tLSLri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "lsl $dst, $lhs, $rhs", [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>; -def tLSLrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tLSLrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "lsl $dst, $rhs", [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>; -def tLSRri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), +def tLSRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "lsr $dst, $lhs, $rhs", [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>; -def tLSRrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tLSRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "lsr $dst, $rhs", [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>; // FIXME: This is not rematerializable because mov changes the condition code. -def tMOVi8 : TI<(outs tGPR:$dst), (ins i32imm:$src), +def tMOVi8 : T1I<(outs tGPR:$dst), (ins i32imm:$src), "mov $dst, $src", [(set tGPR:$dst, imm0_255:$src)]>; @@ -392,41 +392,41 @@ // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy', // which is MOV(3). This also supports high registers. let neverHasSideEffects = 1 in { -def tMOVr : TI<(outs tGPR:$dst), (ins tGPR:$src), +def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), "cpy $dst, $src", []>; -def tMOVhir2lor : TI<(outs tGPR:$dst), (ins GPR:$src), +def tMOVhir2lor : T1I<(outs tGPR:$dst), (ins GPR:$src), "cpy $dst, $src\t@ hir2lor", []>; -def tMOVlor2hir : TI<(outs GPR:$dst), (ins tGPR:$src), +def tMOVlor2hir : T1I<(outs GPR:$dst), (ins tGPR:$src), "cpy $dst, $src\t@ lor2hir", []>; -def tMOVhir2hir : TI<(outs GPR:$dst), (ins GPR:$src), +def tMOVhir2hir : T1I<(outs GPR:$dst), (ins GPR:$src), "cpy $dst, $src\t@ hir2hir", []>; } // neverHasSideEffects let isCommutable = 1 in -def tMUL : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tMUL : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "mul $dst, $rhs", [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>; -def tMVN : TI<(outs tGPR:$dst), (ins tGPR:$src), +def tMVN : T1I<(outs tGPR:$dst), (ins tGPR:$src), "mvn $dst, $src", [(set tGPR:$dst, (not tGPR:$src))]>; -def tNEG : TI<(outs tGPR:$dst), (ins tGPR:$src), +def tNEG : T1I<(outs tGPR:$dst), (ins tGPR:$src), "neg $dst, $src", [(set tGPR:$dst, (ineg tGPR:$src))]>; let isCommutable = 1 in -def tORR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tORR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "orr $dst, $rhs", [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>; -def tREV : TI<(outs tGPR:$dst), (ins tGPR:$src), +def tREV : T1I<(outs tGPR:$dst), (ins tGPR:$src), "rev $dst, $src", [(set tGPR:$dst, (bswap tGPR:$src))]>, Requires<[IsThumb, HasV6]>; -def tREV16 : TI<(outs tGPR:$dst), (ins tGPR:$src), +def tREV16 : T1I<(outs tGPR:$dst), (ins tGPR:$src), "rev16 $dst, $src", [(set tGPR:$dst, (or (and (srl tGPR:$src, (i32 8)), 0xFF), @@ -435,7 +435,7 @@ (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>, Requires<[IsThumb, HasV6]>; -def tREVSH : TI<(outs tGPR:$dst), (ins tGPR:$src), +def tREVSH : T1I<(outs tGPR:$dst), (ins tGPR:$src), "revsh $dst, $src", [(set tGPR:$dst, (sext_inreg @@ -443,53 +443,53 @@ (shl tGPR:$src, (i32 8))), i16))]>, Requires<[IsThumb, HasV6]>; -def tROR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tROR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "ror $dst, $rhs", [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>; // Subtract with carry -def tSBC : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tSBC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "sbc $dst, $rhs", [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>; -def tSUBS : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tSUBS : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "sub $dst, $lhs, $rhs", [(set tGPR:$dst, (subc tGPR:$lhs, tGPR:$rhs))]>; // TODO: A7-96: STMIA - store multiple. -def tSUBi3 : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), +def tSUBi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "sub $dst, $lhs, $rhs", [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>; -def tSUBi8 : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), +def tSUBi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "sub $dst, $rhs", [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>; -def tSUBrr : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +def tSUBrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "sub $dst, $lhs, $rhs", [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>; -def tSUBspi : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), +def tSUBspi : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "sub $dst, $rhs * 4", []>; -def tSXTB : TI<(outs tGPR:$dst), (ins tGPR:$src), +def tSXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src), "sxtb $dst, $src", [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>, Requires<[IsThumb, HasV6]>; -def tSXTH : TI<(outs tGPR:$dst), (ins tGPR:$src), +def tSXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src), "sxth $dst, $src", [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>, Requires<[IsThumb, HasV6]>; -def tUXTB : TI<(outs tGPR:$dst), (ins tGPR:$src), +def tUXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src), "uxtb $dst, $src", [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>, Requires<[IsThumb, HasV6]>; -def tUXTH : TI<(outs tGPR:$dst), (ins tGPR:$src), +def tUXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src), "uxth $dst, $src", [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>, Requires<[IsThumb, HasV6]>; @@ -562,9 +562,9 @@ // Large immediate handling. // Two piece imms. -def : ThumbPat<(i32 thumb_immshifted:$src), - (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), - (thumb_immshifted_shamt imm:$src))>; +def : Thumb1Pat<(i32 thumb_immshifted:$src), + (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), + (thumb_immshifted_shamt imm:$src))>; -def : ThumbPat<(i32 imm0_255_comp:$src), - (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; +def : Thumb1Pat<(i32 imm0_255_comp:$src), + (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; From evan.cheng at apple.com Tue Jun 23 14:38:34 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 19:38:34 -0000 Subject: [llvm-commits] [llvm] r73986 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Message-ID: <200906231938.n5NJcZuk031207@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jun 23 14:38:34 2009 New Revision: 73986 URL: http://llvm.org/viewvc/llvm-project?rev=73986&view=rev Log: Code clean up. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=73986&r1=73985&r2=73986&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Jun 23 14:38:34 2009 @@ -532,14 +532,13 @@ BaseReg = N.getOperand(0); unsigned ShImmVal = 0; - if (ConstantSDNode *RHS = dyn_cast(N.getOperand(1))) + if (ConstantSDNode *RHS = dyn_cast(N.getOperand(1))) { ShImmVal = RHS->getZExtValue() & 31; - else - return false; - - Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal)); + Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal)); + return true; + } - return true; + return false; } bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op, From evan.cheng at apple.com Tue Jun 23 14:39:13 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 19:39:13 -0000 Subject: [llvm-commits] [llvm] r73987 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/thumb2-shifter.ll Message-ID: <200906231939.n5NJdDeb031234@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jun 23 14:39:13 2009 New Revision: 73987 URL: http://llvm.org/viewvc/llvm-project?rev=73987&view=rev Log: Proper patterns for thumb2 shift and rotate instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=73987&r1=73986&r2=73987&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jun 23 14:39:13 2009 @@ -69,6 +69,11 @@ let PrintMethod = "printT2SOImmOperand"; } +/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31]. +def imm1_31 : PatLeaf<(i32 imm), [{ + return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32; +}]>; + /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. def imm0_4095 : PatLeaf<(i32 imm), [{ return (uint32_t)N->getZExtValue() < 4096; @@ -125,40 +130,71 @@ // Thumb2 to cover the functionality of the ARM instruction set. // -/// T2I_bin_is - Defines a set of (op reg, {so_imm|so_reg}) patterns for a +/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a +// unary operation that produces a value. +multiclass T2I_un_irs{ + // shifted imm + def i : T2I<(outs GPR:$dst), (ins t2_so_imm:$src), + !strconcat(opc, " $dst, $src"), + [(set GPR:$dst, (opnode t2_so_imm:$src))]> { + let isAsCheapAsAMove = Cheap; + let isReMaterializable = ReMat; + } + // register + def r : T2I<(outs GPR:$dst), (ins GPR:$src), + !strconcat(opc, " $dst, $src"), + [(set GPR:$dst, (opnode GPR:$src))]>; + // shifted register + def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), + !strconcat(opc, " $dst, $src"), + [(set GPR:$dst, (opnode t2_so_reg:$src))]>; +} + +/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a // binary operation that produces a value. -multiclass T2I_bin_is { +multiclass T2I_bin_irs { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), !strconcat(opc, " $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; + // register + def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), + !strconcat(opc, " $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), !strconcat(opc, " $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; } -/// T2I_2bin_is - Same as T2I_bin_is except the order of operands are reversed. -multiclass T2I_rbin_is { +/// T2I_2bin_is - Same as T2I_bin_irs except the order of operands are reversed. +multiclass T2I_rbin_irs { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), !strconcat(opc, " $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; + // register + def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs), + !strconcat(opc, " $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), !strconcat(opc, " $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; } -/// T2I_bin_s_is - Similar to T2I_bin_is except it sets the 's' bit so the +/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the /// instruction modifies the CPSR register. let Defs = [CPSR] in { -multiclass T2I_bin_s_is { +multiclass T2I_bin_s_irs { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), !strconcat(opc, "s $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; - + // register + def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), + !strconcat(opc, " $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), !strconcat(opc, "s $dst, $lhs, $rhs"), @@ -166,15 +202,18 @@ } } -/// T2I_rbin_s_is - Same as T2I_bin_s_is except the order of operands are +/// T2I_rbin_s_irs - Same as T2I_bin_s_irs except the order of operands are /// reversed. let Defs = [CPSR] in { -multiclass T2I_rbin_s_is { +multiclass T2I_rbin_s_irs { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), !strconcat(opc, "s $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; - + // register + def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs), + !strconcat(opc, " $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), !strconcat(opc, "s $dst, $lhs, $rhs"), @@ -182,9 +221,9 @@ } } -/// T2I_bin_ii12s - Defines a set of (op reg, {so_imm|imm0_4095|so_reg}) patterns -/// for a binary operation that produces a value. -multiclass T2I_bin_ii12s { +/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) +/// patterns for a binary operation that produces a value. +multiclass T2I_bin_ii12rs { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), !strconcat(opc, " $dst, $lhs, $rhs"), @@ -193,22 +232,29 @@ def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), !strconcat(opc, "w $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>; + // register + def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), + !strconcat(opc, " $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), !strconcat(opc, " $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; } -/// T2I_bin_c_is - Defines a set of (op reg, {so_imm|reg}) patterns for a +/// T2I_bin_c_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a // binary operation that produces a value and set the carry bit. It can also /// optionally set CPSR. let Uses = [CPSR] in { -multiclass T2I_bin_c_is { +multiclass T2I_bin_c_irs { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs, cc_out:$s), !strconcat(opc, "${s} $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; - + // register + def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s), + !strconcat(opc, "${s} $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s), !strconcat(opc, "${s} $dst, $lhs, $rhs"), @@ -216,15 +262,18 @@ } } -/// T2I_rbin_c_is - Same as T2I_bin_c_is except the order of operands are +/// T2I_rbin_c_irs - Same as T2I_bin_c_irs except the order of operands are /// reversed. let Uses = [CPSR] in { -multiclass T2I_rbin_c_is { +multiclass T2I_rbin_c_irs { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), !strconcat(opc, "${s} $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; - + // register + def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs, cc_out:$s), + !strconcat(opc, "${s} $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), !strconcat(opc, "${s} $dst, $lhs, $rhs"), @@ -232,9 +281,21 @@ } } +/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / +// rotate operation that produces a value. +multiclass T2I_sh_ir { + // 5-bit imm + def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), + !strconcat(opc, " $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>; + // register + def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), + !strconcat(opc, " $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; +} -/// T21_cmp_irs - Defines a set of (op r, {so_imm|so_reg}) cmp / test -/// patterns. Similar to T2I_bin_is except the instruction does not produce +/// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test +/// patterns. Similar to T2I_bin_irs except the instruction does not produce /// a explicit result, only implicitly set CPSR. let Uses = [CPSR] in { multiclass T2I_cmp_is { @@ -242,7 +303,10 @@ def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), !strconcat(opc, " $lhs, $rhs"), [(opnode GPR:$lhs, t2_so_imm:$rhs)]>; - + // register + def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), + !strconcat(opc, " $lhs, $rhs"), + [(opnode GPR:$lhs, GPR:$rhs)]>; // shifted register def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), !strconcat(opc, " $lhs, $rhs"), @@ -262,21 +326,11 @@ def t2MOVr : T2I<(outs GPR:$dst), (ins GPR:$src), "mov $dst, $src", []>; +let isReMaterializable = 1, isAsCheapAsAMove = 1 in def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), "movw $dst, $src", [(set GPR:$dst, imm0_65535:$src)]>; - -// FIXME: Move (shifted register) is a pseudo-instruction for ASR, LSL, LSR, -// ROR, and RRX. Consider splitting into multiple instructions. -def t2MOVs : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), - "mov $dst, $src", - [(set GPR:$dst, t2_so_reg:$src)]>; -def t2MOVrx : T2I<(outs GPR:$dst), (ins GPR:$src), - "mov $dst, $src, rrx", - [(set GPR:$dst, (ARMrrx GPR:$src))]>; - - // FIXME: Also available in ARM mode. let Constraints = "$src = $dst" in def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), @@ -288,21 +342,21 @@ // Arithmetic Instructions. // -defm t2ADD : T2I_bin_ii12s<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>; -defm t2SUB : T2I_bin_ii12s<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; +defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>; +defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. -defm t2ADDS : T2I_bin_s_is<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>; -defm t2SUBS : T2I_bin_s_is<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; +defm t2ADDS : T2I_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>; +defm t2SUBS : T2I_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; // FIXME: predication support -defm t2ADC : T2I_bin_c_is<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>; -defm t2SBC : T2I_bin_c_is<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; +defm t2ADC : T2I_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>; +defm t2SBC : T2I_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; // RSB, RSC -defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>; -defm t2RSBS : T2I_rbin_c_is<"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>; -defm t2RSC : T2I_rbin_s_is<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; +defm t2RSB : T2I_rbin_irs <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>; +defm t2RSBS : T2I_rbin_c_irs<"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>; +defm t2RSC : T2I_rbin_s_irs<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. def : Thumb2Pat<(add GPR:$src, t2_so_imm_neg:$imm), @@ -312,31 +366,37 @@ //===----------------------------------------------------------------------===// +// Shift and rotate Instructions. +// + +defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>; +defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>; +defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; +defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; + +def t2MOVrx : T2I<(outs GPR:$dst), (ins GPR:$src), + "mov $dst, $src, rrx", + [(set GPR:$dst, (ARMrrx GPR:$src))]>; + +//===----------------------------------------------------------------------===// // Bitwise Instructions. // -defm t2AND : T2I_bin_is <"and", BinOpFrag<(and node:$LHS, node:$RHS)>>; -defm t2ORR : T2I_bin_is <"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>; -defm t2EOR : T2I_bin_is <"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>; +defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>; +defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>; +defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>; -defm t2BIC : T2I_bin_is <"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; +defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; def : Thumb2Pat<(and GPR:$src, t2_so_imm_not:$imm), (t2BICri GPR:$src, t2_so_imm_not:$imm)>; -defm t2ORN : T2I_bin_is <"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>; +defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>; def : Thumb2Pat<(or GPR:$src, t2_so_imm_not:$imm), (t2ORNri GPR:$src, t2_so_imm_not:$imm)>; - -def t2MVNr : T2I<(outs GPR:$dst), (ins t2_so_reg:$rhs), - "mvn $dst, $rhs", - [(set GPR:$dst, (not t2_so_reg:$rhs))]>; -let isReMaterializable = 1, isAsCheapAsAMove = 1 in -def t2MVNi : T2I<(outs GPR:$dst), (ins t2_so_imm_not:$rhs), - "mvn $dst, $rhs", - [(set GPR:$dst, t2_so_imm_not:$rhs)]>; +defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>; // A8.6.17 BFC - Bitfield clear // FIXME: Also available in ARM mode. Modified: llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll?rev=73987&r1=73986&r2=73987&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll (original) +++ llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll Tue Jun 23 14:39:13 2009 @@ -2,7 +2,7 @@ ; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsr ; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep asr ; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ror -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep mov define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) { %A = shl i32 %Y, 16 From lhames at gmail.com Tue Jun 23 14:49:24 2009 From: lhames at gmail.com (Lang Hames) Date: Tue, 23 Jun 2009 19:49:24 -0000 Subject: [llvm-commits] [llvm] r73988 - /llvm/trunk/lib/Support/Timer.cpp Message-ID: <200906231949.n5NJnOVF031633@zion.cs.uiuc.edu> Author: lhames Date: Tue Jun 23 14:49:23 2009 New Revision: 73988 URL: http://llvm.org/viewvc/llvm-project?rev=73988&view=rev Log: Switched size_t to int64_t to prevent type mismatch in call to max. Modified: llvm/trunk/lib/Support/Timer.cpp Modified: llvm/trunk/lib/Support/Timer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=73988&r1=73987&r2=73988&view=diff ============================================================================== --- llvm/trunk/lib/Support/Timer.cpp (original) +++ llvm/trunk/lib/Support/Timer.cpp Tue Jun 23 14:49:23 2009 @@ -182,11 +182,11 @@ /// currently active timers, which will be printed when the timer group prints /// void Timer::addPeakMemoryMeasurement() { - size_t MemUsed = getMemUsage(); + int64_t MemUsed = getMemUsage(); for (std::vector::iterator I = ActiveTimers->begin(), E = ActiveTimers->end(); I != E; ++I) - (*I)->PeakMem = std::max((*I)->PeakMem, MemUsed-(*I)->PeakMemBase); + (*I)->PeakMem = std::max((*I)->PeakMem, (int64_t)MemUsed-(*I)->PeakMemBase); } //===----------------------------------------------------------------------===// From isanbard at gmail.com Tue Jun 23 14:53:00 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 23 Jun 2009 19:53:00 -0000 Subject: [llvm-commits] [llvm] r73989 - /llvm/trunk/lib/Target/X86/X86InstrMMX.td Message-ID: <200906231953.n5NJr1Yp031887@zion.cs.uiuc.edu> Author: void Date: Tue Jun 23 14:52:59 2009 New Revision: 73989 URL: http://llvm.org/viewvc/llvm-project?rev=73989&view=rev Log: "The MMX_MASKMOVQ and MMX_MASKMOVQ64 instructions are labeled as MRMDestMem instructions, which implies that there is an explicit memory operand. There is (however) no explicit memory operand; although this is a store, the only memory operand is implicit, indicated by DS:EDI. This causes the table-generation code for the disassembler to report an error." Patch by Sean Callanan! Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=73989&r1=73988&r2=73989&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Tue Jun 23 14:52:59 2009 @@ -481,11 +481,11 @@ // Misc. let Uses = [EDI] in -def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask), +def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), "maskmovq\t{$mask, $src|$src, $mask}", [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>; let Uses = [RDI] in -def MMX_MASKMOVQ64: MMXI64<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask), +def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), "maskmovq\t{$mask, $src|$src, $mask}", [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>; From evan.cheng at apple.com Tue Jun 23 14:56:37 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 19:56:37 -0000 Subject: [llvm-commits] [llvm] r73990 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <200906231956.n5NJucoQ032000@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jun 23 14:56:37 2009 New Revision: 73990 URL: http://llvm.org/viewvc/llvm-project?rev=73990&view=rev Log: Test instructions operands were printed in the wrong order. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=73990&r1=73989&r2=73990&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jun 23 14:56:37 2009 @@ -167,19 +167,19 @@ [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; } -/// T2I_2bin_is - Same as T2I_bin_irs except the order of operands are reversed. +/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are reversed. multiclass T2I_rbin_irs { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), - !strconcat(opc, " $dst, $lhs, $rhs"), + !strconcat(opc, " $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; // register def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs), - !strconcat(opc, " $dst, $lhs, $rhs"), + !strconcat(opc, " $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), - !strconcat(opc, " $dst, $lhs, $rhs"), + !strconcat(opc, " $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; } @@ -208,15 +208,15 @@ multiclass T2I_rbin_s_irs { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), - !strconcat(opc, "s $dst, $lhs, $rhs"), + !strconcat(opc, "s $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; // register def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs), - !strconcat(opc, " $dst, $lhs, $rhs"), + !strconcat(opc, " $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), - !strconcat(opc, "s $dst, $lhs, $rhs"), + !strconcat(opc, "s $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; } } @@ -268,15 +268,15 @@ multiclass T2I_rbin_c_irs { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $lhs, $rhs"), + !strconcat(opc, "${s} $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; // register def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $lhs, $rhs"), + !strconcat(opc, "${s} $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $lhs, $rhs"), + !strconcat(opc, "${s} $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; } } From isanbard at gmail.com Tue Jun 23 15:02:00 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 23 Jun 2009 20:02:00 -0000 Subject: [llvm-commits] [llvm] r73991 - /llvm/trunk/include/llvm/MC/MCImm.h Message-ID: <200906232002.n5NK20Th032325@zion.cs.uiuc.edu> Author: void Date: Tue Jun 23 15:02:00 2009 New Revision: 73991 URL: http://llvm.org/viewvc/llvm-project?rev=73991&view=rev Log: Add include file to get the type for in64_t. Modified: llvm/trunk/include/llvm/MC/MCImm.h Modified: llvm/trunk/include/llvm/MC/MCImm.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCImm.h?rev=73991&r1=73990&r2=73991&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCImm.h (original) +++ llvm/trunk/include/llvm/MC/MCImm.h Tue Jun 23 15:02:00 2009 @@ -16,6 +16,8 @@ #ifndef LLVM_MC_MCIMM_H #define LLVM_MC_MCIMM_H +#include "llvm/Support/DataTypes.h" + namespace llvm { class MCSymbol; From resistor at mac.com Tue Jun 23 15:17:23 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 20:17:23 -0000 Subject: [llvm-commits] [llvm] r73993 - in /llvm/trunk: include/llvm/Support/Timer.h include/llvm/System/Atomic.h include/llvm/Type.h lib/Support/Timer.cpp lib/System/Atomic.cpp lib/VMCore/Mangler.cpp Message-ID: <200906232017.n5NKHNPu000565@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 23 15:17:22 2009 New Revision: 73993 URL: http://llvm.org/viewvc/llvm-project?rev=73993&view=rev Log: Revert my last series of commits related to Timer and 64-bit atomics. Not all the targets we care about are capable of supporting it. Modified: llvm/trunk/include/llvm/Support/Timer.h llvm/trunk/include/llvm/System/Atomic.h llvm/trunk/include/llvm/Type.h llvm/trunk/lib/Support/Timer.cpp llvm/trunk/lib/System/Atomic.cpp llvm/trunk/lib/VMCore/Mangler.cpp Modified: llvm/trunk/include/llvm/Support/Timer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Timer.h?rev=73993&r1=73992&r2=73993&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Timer.h (original) +++ llvm/trunk/include/llvm/Support/Timer.h Tue Jun 23 15:17:22 2009 @@ -34,12 +34,12 @@ /// if they are never started. /// class Timer { - int64_t Elapsed; // Wall clock time elapsed in seconds - int64_t UserTime; // User time elapsed - int64_t SystemTime; // System time elapsed - int64_t MemUsed; // Memory allocated (in bytes) - int64_t PeakMem; // Peak memory used - int64_t PeakMemBase; // Temporary for peak calculation... + double Elapsed; // Wall clock time elapsed in seconds + double UserTime; // User time elapsed + double SystemTime; // System time elapsed + ssize_t MemUsed; // Memory allocated (in bytes) + size_t PeakMem; // Peak memory used + size_t PeakMemBase; // Temporary for peak calculation... std::string Name; // The name of this time variable bool Started; // Has this time variable ever been started? TimerGroup *TG; // The TimerGroup this Timer is in. @@ -49,10 +49,10 @@ Timer(const Timer &T); ~Timer(); - int64_t getProcessTime() const { return UserTime+SystemTime; } - int64_t getWallTime() const { return Elapsed; } - int64_t getMemUsed() const { return MemUsed; } - int64_t getPeakMem() const { return PeakMem; } + double getProcessTime() const { return UserTime+SystemTime; } + double getWallTime() const { return Elapsed; } + ssize_t getMemUsed() const { return MemUsed; } + size_t getPeakMem() const { return PeakMem; } std::string getName() const { return Name; } const Timer &operator=(const Timer &T) { Modified: llvm/trunk/include/llvm/System/Atomic.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Atomic.h?rev=73993&r1=73992&r2=73993&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Atomic.h (original) +++ llvm/trunk/include/llvm/System/Atomic.h Tue Jun 23 15:17:22 2009 @@ -20,14 +20,13 @@ namespace sys { void MemoryFence(); - uint32_t CompareAndSwap32(volatile uint32_t* ptr, - uint32_t new_value, - uint32_t old_value); - int32_t AtomicIncrement32(volatile int32_t* ptr); - int32_t AtomicDecrement32(volatile int32_t* ptr); - int32_t AtomicAdd32(volatile int32_t* ptr, int32_t val); - - int64_t AtomicAdd64(volatile int64_t* ptr, int64_t val); + typedef uint32_t cas_flag; + cas_flag CompareAndSwap(volatile cas_flag* ptr, + cas_flag new_value, + cas_flag old_value); + cas_flag AtomicIncrement(volatile cas_flag* ptr); + cas_flag AtomicDecrement(volatile cas_flag* ptr); + cas_flag AtomicAdd(volatile cas_flag* ptr, cas_flag val); } } Modified: llvm/trunk/include/llvm/Type.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=73993&r1=73992&r2=73993&view=diff ============================================================================== --- llvm/trunk/include/llvm/Type.h (original) +++ llvm/trunk/include/llvm/Type.h Tue Jun 23 15:17:22 2009 @@ -103,7 +103,7 @@ /// has no AbstractTypeUsers, the type is deleted. This is only sensical for /// derived types. /// - mutable int32_t RefCount; + mutable sys::cas_flag RefCount; const Type *getForwardedTypeInternal() const; @@ -338,7 +338,7 @@ void addRef() const { assert(isAbstract() && "Cannot add a reference to a non-abstract type!"); - sys::AtomicIncrement32(&RefCount); + sys::AtomicIncrement(&RefCount); } void dropRef() const { @@ -347,8 +347,8 @@ // If this is the last PATypeHolder using this object, and there are no // PATypeHandles using it, the type is dead, delete it now. - int32_t Count = sys::AtomicDecrement32(&RefCount); - if (Count == 0 && AbstractTypeUsers.empty()) + sys::cas_flag OldCount = sys::AtomicDecrement(&RefCount); + if (OldCount == 0 && AbstractTypeUsers.empty()) this->destroy(); } Modified: llvm/trunk/lib/Support/Timer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=73993&r1=73992&r2=73993&view=diff ============================================================================== --- llvm/trunk/lib/Support/Timer.cpp (original) +++ llvm/trunk/lib/Support/Timer.cpp Tue Jun 23 15:17:22 2009 @@ -112,7 +112,8 @@ } struct TimeRecord { - int64_t Elapsed, UserTime, SystemTime, MemUsed; + double Elapsed, UserTime, SystemTime; + ssize_t MemUsed; }; static TimeRecord getTimeRecord(bool Start) { @@ -122,7 +123,7 @@ sys::TimeValue user(0,0); sys::TimeValue sys(0,0); - int64_t MemUsed = 0; + ssize_t MemUsed = 0; if (Start) { MemUsed = getMemUsage(); sys::Process::GetTimeUsage(now,user,sys); @@ -131,9 +132,9 @@ MemUsed = getMemUsage(); } - Result.Elapsed = now.seconds() * 1000000 + now.microseconds(); - Result.UserTime = user.seconds() * 1000000 + user.microseconds(); - Result.SystemTime = sys.seconds() * 1000000 + sys.microseconds(); + Result.Elapsed = now.seconds() + now.microseconds() / 1000000.0; + Result.UserTime = user.seconds() + user.microseconds() / 1000000.0; + Result.SystemTime = sys.seconds() + sys.microseconds() / 1000000.0; Result.MemUsed = MemUsed; return Result; @@ -182,11 +183,11 @@ /// currently active timers, which will be printed when the timer group prints /// void Timer::addPeakMemoryMeasurement() { - int64_t MemUsed = getMemUsage(); + size_t MemUsed = getMemUsage(); for (std::vector::iterator I = ActiveTimers->begin(), E = ActiveTimers->end(); I != E; ++I) - (*I)->PeakMem = std::max((*I)->PeakMem, (int64_t)MemUsed-(*I)->PeakMemBase); + (*I)->PeakMem = std::max((*I)->PeakMem, MemUsed-(*I)->PeakMemBase); } //===----------------------------------------------------------------------===// @@ -276,13 +277,12 @@ void Timer::print(const Timer &Total, std::ostream &OS) { if (Total.UserTime) - printVal(UserTime / 1000000.0, Total.UserTime / 1000000.0, OS); + printVal(UserTime, Total.UserTime, OS); if (Total.SystemTime) - printVal(SystemTime / 1000000.0, Total.SystemTime / 1000000.0, OS); + printVal(SystemTime, Total.SystemTime, OS); if (Total.getProcessTime()) - printVal(getProcessTime() / 1000000.0, - Total.getProcessTime() / 1000000.0, OS); - printVal(Elapsed / 1000000.0, Total.Elapsed / 1000000.0, OS); + printVal(getProcessTime(), Total.getProcessTime(), OS); + printVal(Elapsed, Total.Elapsed, OS); OS << " "; @@ -355,23 +355,23 @@ if (this != DefaultTimerGroup) { *OutStream << " Total Execution Time: "; - printAlignedFP(Total.getProcessTime() / 1000000.0, 4, 5, *OutStream); + printAlignedFP(Total.getProcessTime(), 4, 5, *OutStream); *OutStream << " seconds ("; - printAlignedFP(Total.getWallTime() / 1000000.0, 4, 5, *OutStream); + printAlignedFP(Total.getWallTime(), 4, 5, *OutStream); *OutStream << " wall clock)\n"; } *OutStream << "\n"; - if (Total.UserTime / 1000000.0) + if (Total.UserTime) *OutStream << " ---User Time---"; - if (Total.SystemTime / 1000000.0) + if (Total.SystemTime) *OutStream << " --System Time--"; - if (Total.getProcessTime() / 1000000.0) + if (Total.getProcessTime()) *OutStream << " --User+System--"; *OutStream << " ---Wall Time---"; - if (Total.getMemUsed() / 1000000.0) + if (Total.getMemUsed()) *OutStream << " ---Mem---"; - if (Total.getPeakMem() / 1000000.0) + if (Total.getPeakMem()) *OutStream << " -PeakMem-"; *OutStream << " --- Name ---\n"; Modified: llvm/trunk/lib/System/Atomic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Atomic.cpp?rev=73993&r1=73992&r2=73993&view=diff ============================================================================== --- llvm/trunk/lib/System/Atomic.cpp (original) +++ llvm/trunk/lib/System/Atomic.cpp Tue Jun 23 15:17:22 2009 @@ -35,11 +35,11 @@ #endif } -uint32_t sys::CompareAndSwap32(volatile uint32_t* ptr, - uint32_t new_value, - uint32_t old_value) { +sys::cas_flag sys::CompareAndSwap(volatile sys::cas_flag* ptr, + sys::cas_flag new_value, + sys::cas_flag old_value) { #if LLVM_MULTITHREADED==0 - uint32_t result = *ptr; + sys::cas_flag result = *ptr; if (result == old_value) *ptr = new_value; return result; @@ -52,7 +52,7 @@ #endif } -int32_t sys::AtomicIncrement32(volatile int32_t* ptr) { +sys::cas_flag sys::AtomicIncrement(volatile sys::cas_flag* ptr) { #if LLVM_MULTITHREADED==0 ++(*ptr); return *ptr; @@ -65,7 +65,7 @@ #endif } -int32_t sys::AtomicDecrement32(volatile int32_t* ptr) { +sys::cas_flag sys::AtomicDecrement(volatile sys::cas_flag* ptr) { #if LLVM_MULTITHREADED==0 --(*ptr); return *ptr; @@ -78,7 +78,7 @@ #endif } -int32_t sys::AtomicAdd32(volatile int32_t* ptr, int32_t val) { +sys::cas_flag sys::AtomicAdd(volatile sys::cas_flag* ptr, sys::cas_flag val) { #if LLVM_MULTITHREADED==0 *ptr += val; return *ptr; @@ -91,16 +91,4 @@ #endif } -int64_t sys::AtomicAdd64(volatile int64_t* ptr, int64_t val) { -#if LLVM_MULTITHREADED==0 - *ptr += val; - return *ptr; -#elif defined(__GNUC__) - return __sync_add_and_fetch(ptr, val); -#elif defined(_MSC_VER) - return InterlockedAdd64(ptr, val); -#else -# error No atomic add implementation for your platform! -#endif -} Modified: llvm/trunk/lib/VMCore/Mangler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Mangler.cpp?rev=73993&r1=73992&r2=73993&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Mangler.cpp (original) +++ llvm/trunk/lib/VMCore/Mangler.cpp Tue Jun 23 15:17:22 2009 @@ -165,10 +165,10 @@ } else if (!GV->hasName()) { // Must mangle the global into a unique ID. unsigned TypeUniqueID = getTypeID(GV->getType()); - static int32_t GlobalID = 0; + static uint32_t GlobalID = 0; - int32_t OldID = GlobalID; - sys::AtomicIncrement32(&GlobalID); + unsigned OldID = GlobalID; + sys::AtomicIncrement(&GlobalID); Name = "__unnamed_" + utostr(TypeUniqueID) + "_" + utostr(OldID); } else { From daniel at zuster.org Tue Jun 23 15:24:18 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 23 Jun 2009 20:24:18 -0000 Subject: [llvm-commits] [llvm] r73994 - in /llvm/trunk/include/llvm/MC: MCContext.h MCStreamer.h Message-ID: <200906232024.n5NKOIRT000866@zion.cs.uiuc.edu> Author: ddunbar Date: Tue Jun 23 15:24:17 2009 New Revision: 73994 URL: http://llvm.org/viewvc/llvm-project?rev=73994&view=rev Log: Start sketching MCStreamer interface. Added: llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/include/llvm/MC/MCStreamer.h Added: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=73994&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (added) +++ llvm/trunk/include/llvm/MC/MCContext.h Tue Jun 23 15:24:17 2009 @@ -0,0 +1,41 @@ +//===- MCContext.h - Machine Code Context -----------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCCONTEXT_H +#define LLVM_MC_MCCONTEXT_H + +namespace llvm { + class MCAtom; + class MCImm; + class MCSection; + class MCSymbol; + + /// MCContext - Context object for machine code objects. + class MCContext { + MCContext(const MCContext&); // DO NOT IMPLEMENT + MCContext &operator=(const MCContext&); // DO NOT IMPLEMENT + + public: + MCContext(); + ~MCContext(); + + MCSection *GetSection(const char *Name); + MCAtom *CreateAtom(MCSection *Section); + MCSymbol *CreateSymbol(MCAtom *Atom, + const char *Name, + bool IsTemporary); + MCSymbol *LookupSymbol(const char *Name) const; + + void SetSymbolValue(MCSymbol *Sym, const MCImm &Value); + const MCImm &GetSymbolValue(MCSymbol *Sym) const; + }; + +} // end namespace llvm + +#endif Added: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=73994&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (added) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Tue Jun 23 15:24:17 2009 @@ -0,0 +1,61 @@ +//===- MCStreamer.h - High-level Streaming Machine Code Output --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCSTREAMER_H +#define LLVM_MC_MCSTREAMER_H + +namespace llvm { + class MCAtom; + class MCContext; + class MCImm; + class MCInst; + class MCSection; + class MCSymbol; + class raw_ostream; + + /// MCStreamer - Streaming machine code generation interface. + class MCStreamer { + public: + enum SymbolAttr { + Global, + Weak, + PrivateExtern + }; + + private: + MCContext &Context; + + MCStreamer(const MCStreamer&); // DO NOT IMPLEMENT + MCStreamer &operator=(const MCStreamer&); // DO NOT IMPLEMENT + + public: + MCStreamer(MCContext &Ctx); + virtual ~MCStreamer(); + + MCContext &getContext() const { return Context; } + + virtual void SwitchSection(MCSection *Sect) = 0; + + virtual void EmitSymbol(MCSymbol *Sym); + virtual void EmitSymbolAssignment(MCSymbol *Sym, const MCImm &Value) = 0; + virtual void EmitSymbolAttribute(MCSymbol *Sym, + SymbolAttr Attr) = 0; + + virtual void EmitBytes(const char *Data, unsigned Length) = 0; + virtual void EmitValue(const MCImm &Value, unsigned Size) = 0; + virtual void EmitInstruction(const MCInst &Inst) = 0; + }; + + MCStreamer *createAsmStreamer(MCContext &Ctx, raw_ostream &OS); + MCStreamer *createMachOStreamer(MCContext &Ctx, raw_ostream &OS); + MCStreamer *createELFStreamer(MCContext &Ctx, raw_ostream &OS); + +} // end namespace llvm + +#endif From foldr at codedgers.com Tue Jun 23 15:45:07 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 23 Jun 2009 20:45:07 -0000 Subject: [llvm-commits] [llvm] r73997 - /llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Message-ID: <200906232045.n5NKj7xt001625@zion.cs.uiuc.edu> Author: foldr Date: Tue Jun 23 15:45:07 2009 New Revision: 73997 URL: http://llvm.org/viewvc/llvm-project?rev=73997&view=rev Log: Typo. Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp?rev=73997&r1=73996&r2=73997&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Tue Jun 23 15:45:07 2009 @@ -1652,11 +1652,11 @@ } -/// EmitOptionDefintions - Iterate over a list of option descriptions +/// EmitOptionDefinitions - Iterate over a list of option descriptions /// and emit registration code. -void EmitOptionDefintions (const OptionDescriptions& descs, - bool HasSink, bool HasExterns, - std::ostream& O) +void EmitOptionDefinitions (const OptionDescriptions& descs, + bool HasSink, bool HasExterns, + std::ostream& O) { std::vector Aliases; @@ -2081,7 +2081,7 @@ EmitIncludes(O); // Emit global option registration code. - EmitOptionDefintions(Data.OptDescs, Data.HasSink, Data.HasExterns, O); + EmitOptionDefinitions(Data.OptDescs, Data.HasSink, Data.HasExterns, O); // Emit hook declarations. EmitHookDeclarations(Data.ToolDescs, O); From foldr at codedgers.com Tue Jun 23 15:45:31 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 23 Jun 2009 20:45:31 -0000 Subject: [llvm-commits] [llvm] r73998 - /llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Message-ID: <200906232045.n5NKjWii001654@zion.cs.uiuc.edu> Author: foldr Date: Tue Jun 23 15:45:31 2009 New Revision: 73998 URL: http://llvm.org/viewvc/llvm-project?rev=73998&view=rev Log: A little bit nicer formatting. Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp?rev=73998&r1=73997&r2=73998&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Tue Jun 23 15:45:31 2009 @@ -1681,7 +1681,7 @@ continue; } - O << "(\"" << val.Name << '\"'; + O << "(\"" << val.Name << "\"\n"; if (val.Type == OptionType::Prefix || val.Type == OptionType::PrefixList) O << ", cl::Prefix"; @@ -1712,7 +1712,7 @@ if (!val.Help.empty()) O << ", cl::desc(\"" << val.Help << "\")"; - O << ");\n"; + O << ");\n\n"; } // Emit the aliases (they should go after all the 'proper' options). From foldr at codedgers.com Tue Jun 23 15:46:00 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 23 Jun 2009 20:46:00 -0000 Subject: [llvm-commits] [llvm] r73999 - /llvm/trunk/include/llvm/CompilerDriver/Main.inc Message-ID: <200906232046.n5NKk0PQ001678@zion.cs.uiuc.edu> Author: foldr Date: Tue Jun 23 15:46:00 2009 New Revision: 73999 URL: http://llvm.org/viewvc/llvm-project?rev=73999&view=rev Log: Typo. Modified: llvm/trunk/include/llvm/CompilerDriver/Main.inc Modified: llvm/trunk/include/llvm/CompilerDriver/Main.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CompilerDriver/Main.inc?rev=73999&r1=73998&r2=73999&view=diff ============================================================================== --- llvm/trunk/include/llvm/CompilerDriver/Main.inc (original) +++ llvm/trunk/include/llvm/CompilerDriver/Main.inc Tue Jun 23 15:46:00 2009 @@ -12,8 +12,6 @@ // supported please refer to the tools' manual page or run the tool // with the --help option. // -// This -// //===----------------------------------------------------------------------===// #ifndef LLVM_INCLUDE_COMPILER_DRIVER_MAIN_INC From foldr at codedgers.com Tue Jun 23 15:46:48 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 23 Jun 2009 20:46:48 -0000 Subject: [llvm-commits] [llvm] r74000 - in /llvm/trunk: Makefile.rules include/llvm/CompilerDriver/ForceLinkage.h include/llvm/CompilerDriver/ForceLinkageMacros.h include/llvm/CompilerDriver/Main.inc tools/llvmc/driver/Makefile utils/TableGen/LLVMCConfigurationEmitter.cpp Message-ID: <200906232046.n5NKknpK001717@zion.cs.uiuc.edu> Author: foldr Date: Tue Jun 23 15:46:48 2009 New Revision: 74000 URL: http://llvm.org/viewvc/llvm-project?rev=74000&view=rev Log: Make llvmc work again. Chris recently broke llvmc with his Makefile changes (r75379). That patch made the global change .o -> .a, which caused built-in llvmc plugins to stop working since plugin initialization in llvmc is based on static variables not referenced from the main executable. This patch implements auto-generated forced references to the plugin libraries. Added: llvm/trunk/include/llvm/CompilerDriver/ForceLinkage.h llvm/trunk/include/llvm/CompilerDriver/ForceLinkageMacros.h Modified: llvm/trunk/Makefile.rules llvm/trunk/include/llvm/CompilerDriver/Main.inc llvm/trunk/tools/llvmc/driver/Makefile llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=74000&r1=73999&r2=74000&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Tue Jun 23 15:46:48 2009 @@ -198,6 +198,7 @@ ifdef LLVMC_PLUGIN LIBRARYNAME := $(patsubst %,plugin_llvmc_%,$(LLVMC_PLUGIN)) +CPP.Flags += -DLLVMC_PLUGIN_NAME=$(LLVMC_PLUGIN) REQUIRES_EH := 1 # Build a dynamic library if the user runs `make` directly from the plugin Added: llvm/trunk/include/llvm/CompilerDriver/ForceLinkage.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CompilerDriver/ForceLinkage.h?rev=74000&view=auto ============================================================================== --- llvm/trunk/include/llvm/CompilerDriver/ForceLinkage.h (added) +++ llvm/trunk/include/llvm/CompilerDriver/ForceLinkage.h Tue Jun 23 15:46:48 2009 @@ -0,0 +1,82 @@ +//===--- ForceLinkage.h - The LLVM Compiler Driver --------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open +// Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// A bit of preprocessor magic to force references to static libraries. Needed +// because plugin initialization is done via static variables. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_INCLUDE_COMPILER_DRIVER_FORCE_LINKAGE_H +#define LLVM_INCLUDE_COMPILER_DRIVER_FORCE_LINKAGE_H + +#include "llvm/CompilerDriver/ForceLinkageMacros.h" + +namespace llvmc { + +// Declare all ForceLinkage$(PluginName) functions. + +#ifdef LLVMC_BUILTIN_PLUGIN_1 + LLVMC_FORCE_LINKAGE_DECL(LLVMC_BUILTIN_PLUGIN_1); +#endif + +#ifdef LLVMC_BUILTIN_PLUGIN_2 + LLVMC_FORCE_LINKAGE_DECL(LLVMC_BUILTIN_PLUGIN_2); +#endif + +#ifdef LLVMC_BUILTIN_PLUGIN_3 + LLVMC_FORCE_LINKAGE_DECL(LLVMC_BUILTIN_PLUGIN_3); +#endif + +#ifdef LLVMC_BUILTIN_PLUGIN_4 + LLVMC_FORCE_LINKAGE_DECL(LLVMC_BUILTIN_PLUGIN_4); +#endif + +#ifdef LLVMC_BUILTIN_PLUGIN_5 + LLVMC_FORCE_LINKAGE_DECL(LLVMC_BUILTIN_PLUGIN_5); +#endif + +namespace force_linkage { + + struct LinkageForcer { + + LinkageForcer() { + +// Call all ForceLinkage$(PluginName) functions. +#ifdef LLVMC_BUILTIN_PLUGIN_1 + LLVMC_FORCE_LINKAGE_CALL(LLVMC_BUILTIN_PLUGIN_1); +#endif + +#ifdef LLVMC_BUILTIN_PLUGIN_2 + LLVMC_FORCE_LINKAGE_CALL(LLVMC_BUILTIN_PLUGIN_2); +#endif + +#ifdef LLVMC_BUILTIN_PLUGIN_3 + LLVMC_FORCE_LINKAGE_CALL(LLVMC_BUILTIN_PLUGIN_3); +#endif + +#ifdef LLVMC_BUILTIN_PLUGIN_4 + LLVMC_FORCE_LINKAGE_CALL(LLVMC_BUILTIN_PLUGIN_4); +#endif + +#ifdef LLVMC_BUILTIN_PLUGIN_5 + LLVMC_FORCE_LINKAGE_CALL(LLVMC_BUILTIN_PLUGIN_5); +#endif + + } + }; +} // End namespace force_linkage. + +// The only externally used bit. +void ForceLinkage() { + force_linkage::LinkageForcer dummy; +} + +} // End namespace llvmc. + +#endif // LLVM_INCLUDE_COMPILER_DRIVER_FORCE_LINKAGE_H Added: llvm/trunk/include/llvm/CompilerDriver/ForceLinkageMacros.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CompilerDriver/ForceLinkageMacros.h?rev=74000&view=auto ============================================================================== --- llvm/trunk/include/llvm/CompilerDriver/ForceLinkageMacros.h (added) +++ llvm/trunk/include/llvm/CompilerDriver/ForceLinkageMacros.h Tue Jun 23 15:46:48 2009 @@ -0,0 +1,29 @@ +//===--- ForceLinkageMacros.h - The LLVM Compiler Driver --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open +// Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Preprocessor magic that forces references to static libraries - common +// macros used by both driver and plugins. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_INCLUDE_COMPILER_DRIVER_FORCE_LINKAGE_MACROS_H +#define LLVM_INCLUDE_COMPILER_DRIVER_FORCE_LINKAGE_MACROS_H + +#define LLVMC_FORCE_LINKAGE_PREFIX(PluginName) ForceLinkage ## PluginName + +#define LLVMC_FORCE_LINKAGE_FUN(PluginName) \ + LLVMC_FORCE_LINKAGE_PREFIX(PluginName) + +#define LLVMC_FORCE_LINKAGE_DECL(PluginName) \ + void LLVMC_FORCE_LINKAGE_FUN(PluginName) () + +#define LLVMC_FORCE_LINKAGE_CALL(PluginName) \ + LLVMC_FORCE_LINKAGE_FUN(PluginName) () + +#endif // LLVM_INCLUDE_COMPILER_DRIVER_FORCE_LINKAGE_MACROS_H Modified: llvm/trunk/include/llvm/CompilerDriver/Main.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CompilerDriver/Main.inc?rev=74000&r1=73999&r2=74000&view=diff ============================================================================== --- llvm/trunk/include/llvm/CompilerDriver/Main.inc (original) +++ llvm/trunk/include/llvm/CompilerDriver/Main.inc Tue Jun 23 15:46:48 2009 @@ -19,6 +19,7 @@ #include "llvm/CompilerDriver/CompilationGraph.h" #include "llvm/CompilerDriver/Error.h" +#include "llvm/CompilerDriver/ForceLinkage.h" #include "llvm/CompilerDriver/Plugin.h" #include "llvm/System/Path.h" @@ -85,6 +86,8 @@ int main(int argc, char** argv) { try { + ForceLinkage(); + LanguageMap langMap; CompilationGraph graph; Modified: llvm/trunk/tools/llvmc/driver/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/driver/Makefile?rev=74000&r1=73999&r2=74000&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/driver/Makefile (original) +++ llvm/trunk/tools/llvmc/driver/Makefile Tue Jun 23 15:46:48 2009 @@ -8,15 +8,46 @@ ##===----------------------------------------------------------------------===## LEVEL = ../../.. +include $(LEVEL)/Makefile.config TOOLNAME = $(LLVMC_BASED_DRIVER_NAME) LLVMLIBS = CompilerDriver.a +LINK_COMPONENTS = support system +REQUIRES_EH := 1 +# Preprocessor magic that generates references to static variables in built-in +# plugins. +# TODO: Move this to Makefile.rules? (also used by examples/{Skeleton, mcc16}) ifneq ($(LLVMC_BUILTIN_PLUGINS),) + USEDLIBS += $(patsubst %,plugin_llvmc_%.a,$(LLVMC_BUILTIN_PLUGINS)) + +LLVMC_BUILTIN_PLUGIN_1 = $(word 1, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_2 = $(word 2, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_3 = $(word 3, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_4 = $(word 4, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_5 = $(word 5, $(LLVMC_BUILTIN_PLUGINS)) + +ifneq ($(LLVMC_BUILTIN_PLUGIN_1),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_1=$(LLVMC_BUILTIN_PLUGIN_1) endif -LINK_COMPONENTS = support system -REQUIRES_EH := 1 +ifneq ($(LLVMC_BUILTIN_PLUGIN_2),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_2=$(LLVMC_BUILTIN_PLUGIN_2) +endif + +ifneq ($(LLVMC_BUILTIN_PLUGIN_3),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_3=$(LLVMC_BUILTIN_PLUGIN_3) +endif + +ifneq ($(LLVMC_BUILTIN_PLUGIN_4),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_4=$(LLVMC_BUILTIN_PLUGIN_4) +endif + +ifneq ($(LLVMC_BUILTIN_PLUGIN_5),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_5=$(LLVMC_BUILTIN_PLUGIN_5) +endif + +endif include $(LEVEL)/Makefile.common Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp?rev=74000&r1=73999&r2=74000&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Tue Jun 23 15:46:48 2009 @@ -1984,6 +1984,7 @@ /// additional declarations. void EmitIncludes(std::ostream& O) { O << "#include \"llvm/CompilerDriver/CompilationGraph.h\"\n" + << "#include \"llvm/CompilerDriver/ForceLinkageMacros.h\"\n" << "#include \"llvm/CompilerDriver/Plugin.h\"\n" << "#include \"llvm/CompilerDriver/Tool.h\"\n\n" @@ -2106,7 +2107,13 @@ // Emit code for plugin registration. EmitRegisterPlugin(Data.Priority, O); - O << "} // End anonymous namespace.\n"; + O << "} // End anonymous namespace.\n\n"; + + // Force linkage magic. + O << "namespace llvmc {\n"; + O << "LLVMC_FORCE_LINKAGE_DECL(LLVMC_PLUGIN_NAME) {}\n"; + O << "}\n"; + // EOF } From foldr at codedgers.com Tue Jun 23 15:47:24 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 23 Jun 2009 20:47:24 -0000 Subject: [llvm-commits] [llvm] r74001 - in /llvm/trunk/tools/llvmc/example: Skeleton/driver/Makefile mcc16/driver/Makefile Message-ID: <200906232047.n5NKlOuP001776@zion.cs.uiuc.edu> Author: foldr Date: Tue Jun 23 15:47:24 2009 New Revision: 74001 URL: http://llvm.org/viewvc/llvm-project?rev=74001&view=rev Log: Temporary copy-pasto to make examples compile. Modified: llvm/trunk/tools/llvmc/example/Skeleton/driver/Makefile llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile Modified: llvm/trunk/tools/llvmc/example/Skeleton/driver/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/Skeleton/driver/Makefile?rev=74001&r1=74000&r2=74001&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/example/Skeleton/driver/Makefile (original) +++ llvm/trunk/tools/llvmc/example/Skeleton/driver/Makefile Tue Jun 23 15:47:24 2009 @@ -8,15 +8,46 @@ ##===----------------------------------------------------------------------===## LEVEL = $(LLVMC_BASE_LEVEL)/.. +include $(LEVEL)/Makefile.config TOOLNAME = $(LLVMC_BASED_DRIVER_NAME) -LLVMLIBS = CompilerDriver +LLVMLIBS = CompilerDriver.a +LINK_COMPONENTS = support system +REQUIRES_EH := 1 +# Preprocessor magic that generates references to static variables in built-in +# plugins. +# TODO: Move this to Makefile.rules? (also used by examples/{Skeleton, mcc16}) ifneq ($(LLVMC_BUILTIN_PLUGINS),) -USEDLIBS += $(patsubst %,plugin_llvmc_%,$(LLVMC_BUILTIN_PLUGINS)) + +USEDLIBS += $(patsubst %,plugin_llvmc_%.a,$(LLVMC_BUILTIN_PLUGINS)) + +LLVMC_BUILTIN_PLUGIN_1 = $(word 1, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_2 = $(word 2, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_3 = $(word 3, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_4 = $(word 4, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_5 = $(word 5, $(LLVMC_BUILTIN_PLUGINS)) + +ifneq ($(LLVMC_BUILTIN_PLUGIN_1),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_1=$(LLVMC_BUILTIN_PLUGIN_1) endif -LINK_COMPONENTS = support system -REQUIRES_EH := 1 +ifneq ($(LLVMC_BUILTIN_PLUGIN_2),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_2=$(LLVMC_BUILTIN_PLUGIN_2) +endif + +ifneq ($(LLVMC_BUILTIN_PLUGIN_3),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_3=$(LLVMC_BUILTIN_PLUGIN_3) +endif + +ifneq ($(LLVMC_BUILTIN_PLUGIN_4),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_4=$(LLVMC_BUILTIN_PLUGIN_4) +endif + +ifneq ($(LLVMC_BUILTIN_PLUGIN_5),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_5=$(LLVMC_BUILTIN_PLUGIN_5) +endif + +endif include $(LEVEL)/Makefile.common Modified: llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile?rev=74001&r1=74000&r2=74001&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile (original) +++ llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile Tue Jun 23 15:47:24 2009 @@ -8,15 +8,46 @@ ##===----------------------------------------------------------------------===## LEVEL = $(LLVMC_BASE_LEVEL)/.. +include $(LEVEL)/Makefile.config TOOLNAME = $(LLVMC_BASED_DRIVER_NAME) -LLVMLIBS = CompilerDriver +LLVMLIBS = CompilerDriver.a +LINK_COMPONENTS = support system +REQUIRES_EH := 1 +# Preprocessor magic that generates references to static variables in built-in +# plugins. +# TODO: Move this to Makefile.rules? (also used by examples/{Skeleton, mcc16}) ifneq ($(LLVMC_BUILTIN_PLUGINS),) -USEDLIBS += $(patsubst %,plugin_llvmc_%,$(LLVMC_BUILTIN_PLUGINS)) + +USEDLIBS += $(patsubst %,plugin_llvmc_%.a,$(LLVMC_BUILTIN_PLUGINS)) + +LLVMC_BUILTIN_PLUGIN_1 = $(word 1, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_2 = $(word 2, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_3 = $(word 3, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_4 = $(word 4, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_5 = $(word 5, $(LLVMC_BUILTIN_PLUGINS)) + +ifneq ($(LLVMC_BUILTIN_PLUGIN_1),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_1=$(LLVMC_BUILTIN_PLUGIN_1) endif -LINK_COMPONENTS = support system -REQUIRES_EH := 1 +ifneq ($(LLVMC_BUILTIN_PLUGIN_2),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_2=$(LLVMC_BUILTIN_PLUGIN_2) +endif + +ifneq ($(LLVMC_BUILTIN_PLUGIN_3),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_3=$(LLVMC_BUILTIN_PLUGIN_3) +endif + +ifneq ($(LLVMC_BUILTIN_PLUGIN_4),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_4=$(LLVMC_BUILTIN_PLUGIN_4) +endif + +ifneq ($(LLVMC_BUILTIN_PLUGIN_5),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_5=$(LLVMC_BUILTIN_PLUGIN_5) +endif + +endif include $(LEVEL)/Makefile.common From resistor at mac.com Tue Jun 23 15:52:29 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 20:52:29 -0000 Subject: [llvm-commits] [llvm] r74002 - in /llvm/trunk: include/llvm/Support/Timer.h lib/Support/Timer.cpp Message-ID: <200906232052.n5NKqTiS001953@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 23 15:52:29 2009 New Revision: 74002 URL: http://llvm.org/viewvc/llvm-project?rev=74002&view=rev Log: Make timers threadsafe again. This isn't quite as nice as I'd hoped (it uses locking rather than atomic arithmetic), but should work on all the platforms we care about. I might revisit this if a totally awesome way to do it occurs to me. Modified: llvm/trunk/include/llvm/Support/Timer.h llvm/trunk/lib/Support/Timer.cpp Modified: llvm/trunk/include/llvm/Support/Timer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Timer.h?rev=74002&r1=74001&r2=74002&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Timer.h (original) +++ llvm/trunk/include/llvm/Support/Timer.h Tue Jun 23 15:52:29 2009 @@ -16,6 +16,7 @@ #define LLVM_SUPPORT_TIMER_H #include "llvm/Support/DataTypes.h" +#include "llvm/System/Mutex.h" #include #include #include @@ -43,6 +44,7 @@ std::string Name; // The name of this time variable bool Started; // Has this time variable ever been started? TimerGroup *TG; // The TimerGroup this Timer is in. + mutable sys::SmartMutex Lock; // Mutex for the contents of this Timer. public: explicit Timer(const std::string &N); Timer(const std::string &N, TimerGroup &tg); @@ -56,6 +58,14 @@ std::string getName() const { return Name; } const Timer &operator=(const Timer &T) { + if (&T < this) { + T.Lock.acquire(); + Lock.acquire(); + } else { + Lock.acquire(); + T.Lock.acquire(); + } + Elapsed = T.Elapsed; UserTime = T.UserTime; SystemTime = T.SystemTime; @@ -65,6 +75,15 @@ Name = T.Name; Started = T.Started; assert(TG == T.TG && "Can only assign timers in the same TimerGroup!"); + + if (&T < this) { + T.Lock.release(); + Lock.release(); + } else { + Lock.release(); + T.Lock.release(); + } + return *this; } @@ -160,11 +179,9 @@ private: friend class Timer; - void addTimer() { ++NumTimers; } + void addTimer(); void removeTimer(); - void addTimerToPrint(const Timer &T) { - TimersToPrint.push_back(Timer(true, T)); - } + void addTimerToPrint(const Timer &T); }; } // End llvm namespace Modified: llvm/trunk/lib/Support/Timer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=74002&r1=74001&r2=74002&view=diff ============================================================================== --- llvm/trunk/lib/Support/Timer.cpp (original) +++ llvm/trunk/lib/Support/Timer.cpp Tue Jun 23 15:52:29 2009 @@ -38,6 +38,8 @@ return *LibSupportInfoOutputFilename; } +static ManagedStatic > TimerLock; + namespace { static cl::opt TrackSpace("track-memory", cl::desc("Enable -time-passes memory " @@ -143,6 +145,7 @@ static ManagedStatic > ActiveTimers; void Timer::startTimer() { + sys::SmartScopedLock L(&Lock); Started = true; ActiveTimers->push_back(this); TimeRecord TR = getTimeRecord(true); @@ -154,6 +157,7 @@ } void Timer::stopTimer() { + sys::SmartScopedLock L(&Lock); TimeRecord TR = getTimeRecord(false); Elapsed += TR.Elapsed; UserTime += TR.UserTime; @@ -171,11 +175,27 @@ } void Timer::sum(const Timer &T) { + if (&T < this) { + T.Lock.acquire(); + Lock.acquire(); + } else { + Lock.acquire(); + T.Lock.acquire(); + } + Elapsed += T.Elapsed; UserTime += T.UserTime; SystemTime += T.SystemTime; MemUsed += T.MemUsed; PeakMem += T.PeakMem; + + if (&T < this) { + T.Lock.release(); + Lock.release(); + } else { + Lock.release(); + T.Lock.release(); + } } /// addPeakMemoryMeasurement - This method should be called whenever memory @@ -186,8 +206,11 @@ size_t MemUsed = getMemUsage(); for (std::vector::iterator I = ActiveTimers->begin(), - E = ActiveTimers->end(); I != E; ++I) + E = ActiveTimers->end(); I != E; ++I) { + (*I)->Lock.acquire(); (*I)->PeakMem = std::max((*I)->PeakMem, MemUsed-(*I)->PeakMemBase); + (*I)->Lock.release(); + } } //===----------------------------------------------------------------------===// @@ -206,6 +229,7 @@ static ManagedStatic NamedGroupedTimers; static Timer &getNamedRegionTimer(const std::string &Name) { + sys::SmartScopedLock L(&*TimerLock); Name2Timer::iterator I = NamedTimers->find(Name); if (I != NamedTimers->end()) return I->second; @@ -215,6 +239,7 @@ static Timer &getNamedRegionTimer(const std::string &Name, const std::string &GroupName) { + sys::SmartScopedLock L(&*TimerLock); Name2Pair::iterator I = NamedGroupedTimers->find(GroupName); if (I == NamedGroupedTimers->end()) { @@ -276,6 +301,14 @@ } void Timer::print(const Timer &Total, std::ostream &OS) { + if (&Total < this) { + Total.Lock.acquire(); + Lock.acquire(); + } else { + Lock.acquire(); + Total.Lock.acquire(); + } + if (Total.UserTime) printVal(UserTime, Total.UserTime, OS); if (Total.SystemTime) @@ -300,6 +333,14 @@ OS << Name << "\n"; Started = false; // Once printed, don't print again + + if (&Total < this) { + Total.Lock.release(); + Lock.release(); + } else { + Lock.release(); + Total.Lock.release(); + } } // GetLibSupportInfoOutputFile - Return a file stream to print our output on... @@ -324,6 +365,7 @@ void TimerGroup::removeTimer() { + sys::SmartScopedLock L(&*TimerLock); if (--NumTimers == 0 && !TimersToPrint.empty()) { // Print timing report... // Sort the timers in descending order by amount of time taken... std::sort(TimersToPrint.begin(), TimersToPrint.end(), @@ -391,3 +433,13 @@ } } +void TimerGroup::addTimer() { + sys::SmartScopedLock L(&*TimerLock); + ++NumTimers; +} + +void TimerGroup::addTimerToPrint(const Timer &T) { + sys::SmartScopedLock L(&*TimerLock); + TimersToPrint.push_back(Timer(true, T)); +} + From foldr at codedgers.com Tue Jun 23 16:00:34 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 23 Jun 2009 21:00:34 +0000 (UTC) Subject: [llvm-commits] [llvm] r74000 - in /llvm/trunk: Makefile.rules include/llvm/CompilerDriver/ForceLinkage.h include/llvm/CompilerDriver/ForceLinkageMacros.h include/llvm/CompilerDriver/Main.inc tools/llvmc/driver/Makefile utils/TableGen/LLVMCConfigurationEmitter.cpp References: <200906232046.n5NKknpK001717@zion.cs.uiuc.edu> Message-ID: Mikhail Glushenkov writes: > Chris recently broke llvmc with his Makefile changes (r75379). Oops, this really should be r73579. From dgregor at apple.com Tue Jun 23 16:05:22 2009 From: dgregor at apple.com (Douglas Gregor) Date: Tue, 23 Jun 2009 21:05:22 -0000 Subject: [llvm-commits] [llvm] r74003 - /llvm/trunk/cmake/modules/AddLLVM.cmake Message-ID: <200906232105.n5NL5MOA002429@zion.cs.uiuc.edu> Author: dgregor Date: Tue Jun 23 16:05:21 2009 New Revision: 74003 URL: http://llvm.org/viewvc/llvm-project?rev=74003&view=rev Log: Reinstate target dependencies on Table_gen targets in CMake Modified: llvm/trunk/cmake/modules/AddLLVM.cmake Modified: llvm/trunk/cmake/modules/AddLLVM.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=74003&r1=74002&r2=74003&view=diff ============================================================================== --- llvm/trunk/cmake/modules/AddLLVM.cmake (original) +++ llvm/trunk/cmake/modules/AddLLVM.cmake Tue Jun 23 16:05:21 2009 @@ -58,4 +58,7 @@ endif( TABLEGEN_OUTPUT ) include_directories(BEFORE ${CMAKE_CURRENT_BINARY_DIR}) add_llvm_library(LLVM${target_name} ${ARGN} ${TABLEGEN_OUTPUT}) + if ( TABLEGEN_OUTPUT ) + add_dependencies(LLVM${target_name} ${target_name}Table_gen) + endif (TABLEGEN_OUTPUT) endmacro(add_llvm_target) From resistor at mac.com Tue Jun 23 16:19:04 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 21:19:04 -0000 Subject: [llvm-commits] [llvm] r74004 - in /llvm/trunk: include/llvm/System/Atomic.h lib/System/Atomic.cpp Message-ID: <200906232119.n5NLJ4Tv002949@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 23 16:19:04 2009 New Revision: 74004 URL: http://llvm.org/viewvc/llvm-project?rev=74004&view=rev Log: Add atomic multiply and divide operations, built on top of CompareAndSwap. Modified: llvm/trunk/include/llvm/System/Atomic.h llvm/trunk/lib/System/Atomic.cpp Modified: llvm/trunk/include/llvm/System/Atomic.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Atomic.h?rev=74004&r1=74003&r2=74004&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Atomic.h (original) +++ llvm/trunk/include/llvm/System/Atomic.h Tue Jun 23 16:19:04 2009 @@ -27,6 +27,8 @@ cas_flag AtomicIncrement(volatile cas_flag* ptr); cas_flag AtomicDecrement(volatile cas_flag* ptr); cas_flag AtomicAdd(volatile cas_flag* ptr, cas_flag val); + cas_flag AtomicMul(volatile cas_flag* ptr, cas_flag val); + cas_flag AtomicDiv(volatile cas_flag* ptr, cas_flag val); } } Modified: llvm/trunk/lib/System/Atomic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Atomic.cpp?rev=74004&r1=74003&r2=74004&view=diff ============================================================================== --- llvm/trunk/lib/System/Atomic.cpp (original) +++ llvm/trunk/lib/System/Atomic.cpp Tue Jun 23 16:19:04 2009 @@ -91,4 +91,22 @@ #endif } +sys::cas_flag sys::AtomicMul(volatile sys::cas_flag* ptr, sys::cas_flag val) { + sys::cas_flag original, result; + do { + original = *ptr; + result = original * val; + } while (sys::CompareAndSwap(ptr, result, original) != original); + return result; +} + +sys::cas_flag sys::AtomicDiv(volatile sys::cas_flag* ptr, sys::cas_flag val) { + sys::cas_flag original, result; + do { + original = *ptr; + result = original / val; + } while (sys::CompareAndSwap(ptr, result, original) != original); + + return result; +} From resistor at mac.com Tue Jun 23 16:19:38 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 21:19:38 -0000 Subject: [llvm-commits] [llvm] r74005 - in /llvm/trunk: include/llvm/ADT/Statistic.h lib/Support/Statistic.cpp Message-ID: <200906232119.n5NLJdHb002981@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 23 16:19:38 2009 New Revision: 74005 URL: http://llvm.org/viewvc/llvm-project?rev=74005&view=rev Log: Use atomic operations when accessing statistics, and make the lazy initialization of statistics actually threadsafe. Modified: llvm/trunk/include/llvm/ADT/Statistic.h llvm/trunk/lib/Support/Statistic.cpp Modified: llvm/trunk/include/llvm/ADT/Statistic.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Statistic.h?rev=74005&r1=74004&r2=74005&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/Statistic.h (original) +++ llvm/trunk/include/llvm/ADT/Statistic.h Tue Jun 23 16:19:38 2009 @@ -26,14 +26,16 @@ #ifndef LLVM_ADT_STATISTIC_H #define LLVM_ADT_STATISTIC_H +#include "llvm/System/Atomic.h" + namespace llvm { class Statistic { public: const char *Name; const char *Desc; - unsigned Value : 31; - bool Initialized : 1; + unsigned Value; + bool Initialized; unsigned getValue() const { return Value; } const char *getName() const { return Name; } @@ -47,19 +49,60 @@ // Allow use of this class as the value itself. operator unsigned() const { return Value; } - const Statistic &operator=(unsigned Val) { Value = Val; return init(); } - const Statistic &operator++() { ++Value; return init(); } - unsigned operator++(int) { init(); return Value++; } - const Statistic &operator--() { --Value; return init(); } - unsigned operator--(int) { init(); return Value--; } - const Statistic &operator+=(const unsigned &V) { Value += V; return init(); } - const Statistic &operator-=(const unsigned &V) { Value -= V; return init(); } - const Statistic &operator*=(const unsigned &V) { Value *= V; return init(); } - const Statistic &operator/=(const unsigned &V) { Value /= V; return init(); } + const Statistic &operator=(unsigned Val) { + Value = Val; + return init(); + } + + const Statistic &operator++() { + sys::AtomicIncrement(&Value); + return init(); + } + + unsigned operator++(int) { + init(); + unsigned OldValue = Value; + sys::AtomicIncrement(&Value); + return OldValue; + } + + const Statistic &operator--() { + sys::AtomicDecrement(&Value); + return init(); + } + + unsigned operator--(int) { + init(); + unsigned OldValue = Value; + sys::AtomicDecrement(&Value); + return OldValue; + } + + const Statistic &operator+=(const unsigned &V) { + sys::AtomicAdd(&Value, V); + return init(); + } + + const Statistic &operator-=(const unsigned &V) { + sys::AtomicAdd(&Value, -V); + return init(); + } + + const Statistic &operator*=(const unsigned &V) { + sys::AtomicMul(&Value, V); + return init(); + } + + const Statistic &operator/=(const unsigned &V) { + sys::AtomicDiv(&Value, V); + return init(); + } protected: Statistic &init() { - if (!Initialized) RegisterStatistic(); + bool tmp = Initialized; + sys::MemoryFence(); + if (!tmp) RegisterStatistic(); return *this; } void RegisterStatistic(); Modified: llvm/trunk/lib/Support/Statistic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Statistic.cpp?rev=74005&r1=74004&r2=74005&view=diff ============================================================================== --- llvm/trunk/lib/Support/Statistic.cpp (original) +++ llvm/trunk/lib/Support/Statistic.cpp Tue Jun 23 16:19:38 2009 @@ -66,10 +66,14 @@ // If stats are enabled, inform StatInfo that this statistic should be // printed. sys::ScopedLock Writer(&*StatLock); - if (Enabled) - StatInfo->addStatistic(this); - // Remember we have been registered. - Initialized = true; + if (!Initialized) { + if (Enabled) + StatInfo->addStatistic(this); + + sys::MemoryFence(); + // Remember we have been registered. + Initialized = true; + } } namespace { From daniel at zuster.org Tue Jun 23 16:55:46 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 23 Jun 2009 21:55:46 -0000 Subject: [llvm-commits] [llvm] r74010 - /llvm/trunk/include/llvm/Config/ Message-ID: <200906232155.n5NLtkPS004209@zion.cs.uiuc.edu> Author: ddunbar Date: Tue Jun 23 16:55:46 2009 New Revision: 74010 URL: http://llvm.org/viewvc/llvm-project?rev=74010&view=rev Log: Set svn:ignore for {llvm/Config/AsmPrinters,Targets}.def Modified: llvm/trunk/include/llvm/Config/ (props changed) Propchange: llvm/trunk/include/llvm/Config/ ------------------------------------------------------------------------------ --- svn:ignore (original) +++ svn:ignore Tue Jun 23 16:55:46 2009 @@ -1,2 +1,4 @@ config.h .cvsignore +AsmPrinters.def +Targets.def From daniel at zuster.org Tue Jun 23 17:01:43 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 23 Jun 2009 22:01:43 -0000 Subject: [llvm-commits] [llvm] r74013 - in /llvm/trunk: CMakeLists.txt include/llvm/MC/MCAtom.h include/llvm/MC/MCContext.h include/llvm/MC/MCSection.h include/llvm/MC/MCSymbol.h lib/MC/ lib/MC/CMakeLists.txt lib/MC/MCContext.cpp lib/MC/Makefile lib/Makefile tools/llvm-mc/ tools/llvm-mc/AsmParser.cpp Message-ID: <200906232201.n5NM1iD9004444@zion.cs.uiuc.edu> Author: ddunbar Date: Tue Jun 23 17:01:43 2009 New Revision: 74013 URL: http://llvm.org/viewvc/llvm-project?rev=74013&view=rev Log: Start flushing out MCContext. - Lives inside new library lib/MC (LLVMMC.a) Added: llvm/trunk/include/llvm/MC/MCAtom.h llvm/trunk/include/llvm/MC/MCSection.h llvm/trunk/include/llvm/MC/MCSymbol.h llvm/trunk/lib/MC/ (with props) llvm/trunk/lib/MC/CMakeLists.txt llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/lib/MC/Makefile Modified: llvm/trunk/CMakeLists.txt llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/lib/Makefile llvm/trunk/tools/llvm-mc/ (props changed) llvm/trunk/tools/llvm-mc/AsmParser.cpp Modified: llvm/trunk/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=74013&r1=74012&r2=74013&view=diff ============================================================================== --- llvm/trunk/CMakeLists.txt (original) +++ llvm/trunk/CMakeLists.txt Tue Jun 23 17:01:43 2009 @@ -236,6 +236,7 @@ add_subdirectory(lib/Linker) add_subdirectory(lib/Analysis) add_subdirectory(lib/Analysis/IPA) +add_subdirectory(lib/MC) set(LLVM_ENUM_ASM_PRINTERS "") foreach(t ${LLVM_TARGETS_TO_BUILD}) Added: llvm/trunk/include/llvm/MC/MCAtom.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAtom.h?rev=74013&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCAtom.h (added) +++ llvm/trunk/include/llvm/MC/MCAtom.h Tue Jun 23 17:01:43 2009 @@ -0,0 +1,24 @@ +//===- MCAtom.h - Machine Code Atoms ----------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCATOM_H +#define LLVM_MC_MCATOM_H + +namespace llvm { + + class MCAtom { + MCSection *Section; + + public: + MCAtom(MCSection *_Section) : Section(_Section) {} + }; + +} // end namespace llvm + +#endif Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=74013&r1=74012&r2=74013&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Tue Jun 23 17:01:43 2009 @@ -10,6 +10,10 @@ #ifndef LLVM_MC_MCCONTEXT_H #define LLVM_MC_MCCONTEXT_H +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/StringMap.h" +#include "llvm/Support/Allocator.h" + namespace llvm { class MCAtom; class MCImm; @@ -21,21 +25,140 @@ MCContext(const MCContext&); // DO NOT IMPLEMENT MCContext &operator=(const MCContext&); // DO NOT IMPLEMENT + /// Sections - Bindings of names to allocated sections. + StringMap Sections; + + /// Symbols - Bindings of names to symbols. + StringMap Symbols; + + /// SymbolValues - Bindings of symbols to values. + DenseMap SymbolValues; + + /// Allocator - Allocator object used for creating machine code objects. + /// + /// We use a bump pointer allocator to avoid the need to track all allocated + /// objects. + BumpPtrAllocator Allocator; + public: MCContext(); ~MCContext(); + /// GetSection - Get or create a new section with the given @param Name. MCSection *GetSection(const char *Name); + + /// CreateAtom - Create a new atom inside @param Section. MCAtom *CreateAtom(MCSection *Section); - MCSymbol *CreateSymbol(MCAtom *Atom, - const char *Name, - bool IsTemporary); + + /// CreateSymbol - Create a new symbol inside @param Atom with the specified + /// @param Name. + /// + /// @param Name - The symbol name, which must be unique across all symbols. + MCSymbol *CreateSymbol(MCAtom *Atom, const char *Name); + + /// CreateTemporarySymbol - Create a new temporary symbol inside @param Atom + /// with the specified @param Name. + /// + /// @param Name - The symbol name, for debugging purposes only, temporary + /// symbols do not surive assembly. If non-empty the name must be unique + /// across all symbols. + MCSymbol *CreateTemporarySymbol(MCAtom *Atom, const char *Name = ""); + + /// LookupSymbol - Get the symbol for @param Name, or null. MCSymbol *LookupSymbol(const char *Name) const; - void SetSymbolValue(MCSymbol *Sym, const MCImm &Value); - const MCImm &GetSymbolValue(MCSymbol *Sym) const; + /// ClearSymbolValue - Erase a value binding for @param Symbol, if one + /// exists. + void ClearSymbolValue(MCSymbol *Symbol); + + /// SetSymbolValue - Set the value binding for @param Symbol to @param + /// Value. + void SetSymbolValue(MCSymbol *Symbol, const MCImm &Value); + + /// GetSymbolValue - Return the current value for @param Symbol, or null if + /// none exists. + const MCImm *GetSymbolValue(MCSymbol *Symbol) const; + + void *Allocate(unsigned Size, unsigned Align = 8) { + return Allocator.Allocate(Size, Align); + } + void Deallocate(void *Ptr) { + } }; } // end namespace llvm +// operator new and delete aren't allowed inside namespaces. +// The throw specifications are mandated by the standard. +/// @brief Placement new for using the MCContext's allocator. +/// +/// This placement form of operator new uses the MCContext's allocator for +/// obtaining memory. It is a non-throwing new, which means that it returns +/// null on error. (If that is what the allocator does. The current does, so if +/// this ever changes, this operator will have to be changed, too.) +/// Usage looks like this (assuming there's an MCContext 'Context' in scope): +/// @code +/// // Default alignment (16) +/// IntegerLiteral *Ex = new (Context) IntegerLiteral(arguments); +/// // Specific alignment +/// IntegerLiteral *Ex2 = new (Context, 8) IntegerLiteral(arguments); +/// @endcode +/// Please note that you cannot use delete on the pointer; it must be +/// deallocated using an explicit destructor call followed by +/// @c Context.Deallocate(Ptr). +/// +/// @param Bytes The number of bytes to allocate. Calculated by the compiler. +/// @param C The MCContext that provides the allocator. +/// @param Alignment The alignment of the allocated memory (if the underlying +/// allocator supports it). +/// @return The allocated memory. Could be NULL. +inline void *operator new(size_t Bytes, llvm::MCContext &C, + size_t Alignment) throw () { + return C.Allocate(Bytes, Alignment); +} +/// @brief Placement delete companion to the new above. +/// +/// This operator is just a companion to the new above. There is no way of +/// invoking it directly; see the new operator for more details. This operator +/// is called implicitly by the compiler if a placement new expression using +/// the MCContext throws in the object constructor. +inline void operator delete(void *Ptr, llvm::MCContext &C, size_t) + throw () { + C.Deallocate(Ptr); +} + +/// This placement form of operator new[] uses the MCContext's allocator for +/// obtaining memory. It is a non-throwing new[], which means that it returns +/// null on error. +/// Usage looks like this (assuming there's an MCContext 'Context' in scope): +/// @code +/// // Default alignment (16) +/// char *data = new (Context) char[10]; +/// // Specific alignment +/// char *data = new (Context, 8) char[10]; +/// @endcode +/// Please note that you cannot use delete on the pointer; it must be +/// deallocated using an explicit destructor call followed by +/// @c Context.Deallocate(Ptr). +/// +/// @param Bytes The number of bytes to allocate. Calculated by the compiler. +/// @param C The MCContext that provides the allocator. +/// @param Alignment The alignment of the allocated memory (if the underlying +/// allocator supports it). +/// @return The allocated memory. Could be NULL. +inline void *operator new[](size_t Bytes, llvm::MCContext& C, + size_t Alignment = 16) throw () { + return C.Allocate(Bytes, Alignment); +} + +/// @brief Placement delete[] companion to the new[] above. +/// +/// This operator is just a companion to the new[] above. There is no way of +/// invoking it directly; see the new[] operator for more details. This operator +/// is called implicitly by the compiler if a placement new[] expression using +/// the MCContext throws in the object constructor. +inline void operator delete[](void *Ptr, llvm::MCContext &C) throw () { + C.Deallocate(Ptr); +} + #endif Added: llvm/trunk/include/llvm/MC/MCSection.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSection.h?rev=74013&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCSection.h (added) +++ llvm/trunk/include/llvm/MC/MCSection.h Tue Jun 23 17:01:43 2009 @@ -0,0 +1,26 @@ +//===- MCSection.h - Machine Code Sections ----------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCSECTION_H +#define LLVM_MC_MCSECTION_H + +#include + +namespace llvm { + + class MCSection { + std::string Name; + + public: + MCSection(const char *_Name) : Name(_Name) {} + }; + +} // end namespace llvm + +#endif Added: llvm/trunk/include/llvm/MC/MCSymbol.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSymbol.h?rev=74013&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCSymbol.h (added) +++ llvm/trunk/include/llvm/MC/MCSymbol.h Tue Jun 23 17:01:43 2009 @@ -0,0 +1,30 @@ +//===- MCSymbol.h - Machine Code Symbols ------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCSYMBOL_H +#define LLVM_MC_MCSYMBOL_H + +#include + +namespace llvm { + class MCAtom; + + class MCSymbol { + MCAtom *Atom; + std::string Name; + unsigned IsTemporary : 1; + + public: + MCSymbol(MCAtom *_Atom, const char *_Name, bool _IsTemporary) + : Atom(_Atom), Name(_Name), IsTemporary(_IsTemporary) {} + }; + +} // end namespace llvm + +#endif Propchange: llvm/trunk/lib/MC/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Tue Jun 23 17:01:43 2009 @@ -0,0 +1,3 @@ +Debug +Release-Asserts +Release Added: llvm/trunk/lib/MC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/CMakeLists.txt?rev=74013&view=auto ============================================================================== --- llvm/trunk/lib/MC/CMakeLists.txt (added) +++ llvm/trunk/lib/MC/CMakeLists.txt Tue Jun 23 17:01:43 2009 @@ -0,0 +1,3 @@ +add_llvm_library(LLVMMC + MCContext.cpp + ) Added: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=74013&view=auto ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (added) +++ llvm/trunk/lib/MC/MCContext.cpp Tue Jun 23 17:01:43 2009 @@ -0,0 +1,77 @@ +//===- lib/MachineCode/MCContext.cpp - Machine Code Context ---------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCContext.h" + +#include "llvm/MC/MCAtom.h" +#include "llvm/MC/MCImm.h" +#include "llvm/MC/MCSection.h" +#include "llvm/MC/MCSymbol.h" +using namespace llvm; + +MCContext::MCContext() +{ +} + +MCContext::~MCContext() { +} + +MCSection *MCContext::GetSection(const char *Name) { + MCSection *&Entry = Sections[Name]; + + if (!Entry) + Entry = new (this) MCSection(Name); + + return Entry; +} + +MCAtom *MCContext::CreateAtom(MCSection *Section) { + return new (this) MCAtom(Section); +} + +MCSymbol *MCContext::CreateSymbol(MCAtom *Atom, const char *Name) { + assert(Name[0] != '\0' && "Normal symbols cannot be unnamed!"); + + // Create and bind the symbol, and ensure that names are unique. + MCSymbol *&Entry = Symbols[Name]; + assert(!Entry && "Duplicate symbol definition!"); + return Entry = new (this) MCSymbol(Atom, Name, false); +} + +MCSymbol *MCContext::CreateTemporarySymbol(MCAtom *Atom, const char *Name) { + // If unnamed, just create a symbol. + if (Name[0] == '\0') + new (this) MCSymbol(Atom, "", true); + + // Otherwise create as usual. + MCSymbol *&Entry = Symbols[Name]; + assert(!Entry && "Duplicate symbol definition!"); + return Entry = new (this) MCSymbol(Atom, Name, true); +} + +MCSymbol *MCContext::LookupSymbol(const char *Name) const { + return Symbols.lookup(Name); +} + +void MCContext::ClearSymbolValue(MCSymbol *Sym) { + SymbolValues.erase(Sym); +} + +void MCContext::SetSymbolValue(MCSymbol *Sym, const MCImm &Value) { + SymbolValues[Sym] = Value; +} + +const MCImm *MCContext::GetSymbolValue(MCSymbol *Sym) const { + DenseMap::iterator it = SymbolValues.find(Sym); + + if (it == SymbolValues.end()) + return 0; + + return &it->second; +} Added: llvm/trunk/lib/MC/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/Makefile?rev=74013&view=auto ============================================================================== --- llvm/trunk/lib/MC/Makefile (added) +++ llvm/trunk/lib/MC/Makefile Tue Jun 23 17:01:43 2009 @@ -0,0 +1,15 @@ +##===- lib/MC/Makefile -------------------------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../.. +LIBRARYNAME = LLVMMC +BUILD_ARCHIVE := 1 + +include $(LEVEL)/Makefile.common + Modified: llvm/trunk/lib/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Makefile?rev=74013&r1=74012&r2=74013&view=diff ============================================================================== --- llvm/trunk/lib/Makefile (original) +++ llvm/trunk/lib/Makefile Tue Jun 23 17:01:43 2009 @@ -9,7 +9,7 @@ LEVEL = .. PARALLEL_DIRS = VMCore AsmParser Bitcode Archive Analysis Transforms CodeGen \ - Target ExecutionEngine Debugger Linker CompilerDriver + Target ExecutionEngine Debugger Linker CompilerDriver MC include $(LEVEL)/Makefile.common Propchange: llvm/trunk/tools/llvm-mc/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Tue Jun 23 17:01:43 2009 @@ -0,0 +1,3 @@ +Debug +Release-Asserts +Release Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=74013&r1=74012&r2=74013&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Tue Jun 23 17:01:43 2009 @@ -12,7 +12,9 @@ //===----------------------------------------------------------------------===// #include "AsmParser.h" +#include "llvm/MC/MCContext.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCStreamer.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; From dpatel at apple.com Tue Jun 23 17:07:48 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 23 Jun 2009 22:07:48 -0000 Subject: [llvm-commits] [llvm] r74015 - /llvm/trunk/include/llvm/Analysis/DebugInfo.h Message-ID: <200906232207.n5NM7nqN004652@zion.cs.uiuc.edu> Author: dpatel Date: Tue Jun 23 17:07:48 2009 New Revision: 74015 URL: http://llvm.org/viewvc/llvm-project?rev=74015&view=rev Log: Add DISubprogram::getReturnTypeName() Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=74015&r1=74014&r2=74015&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Tue Jun 23 17:07:48 2009 @@ -330,6 +330,19 @@ DICompositeType getType() const { return getFieldAs(8); } + /// getReturnTypeName - Subprogram return types are encoded either as + /// DIType or as DICompositeType. + const std::string &getReturnTypeName(std::string &F) const { + DICompositeType DCT(getFieldAs(8)); + if (!DCT.isNull()) { + DIArray A = DCT.getTypeArray(); + DIType T(A.getElement(0).getGV()); + return T.getName(F); + } + DIType T(getFieldAs(8)); + return T.getName(F); + } + /// Verify - Verify that a subprogram descriptor is well formed. bool Verify() const; From dpatel at apple.com Tue Jun 23 17:11:38 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 23 Jun 2009 22:11:38 -0000 Subject: [llvm-commits] [llvm] r74016 - /llvm/trunk/test/DebugInfo/printdbginfo.ll Message-ID: <200906232211.n5NMBcYb004791@zion.cs.uiuc.edu> Author: dpatel Date: Tue Jun 23 17:11:37 2009 New Revision: 74016 URL: http://llvm.org/viewvc/llvm-project?rev=74016&view=rev Log: upgrade Modified: llvm/trunk/test/DebugInfo/printdbginfo.ll Modified: llvm/trunk/test/DebugInfo/printdbginfo.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/printdbginfo.ll?rev=74016&r1=74015&r2=74016&view=diff ============================================================================== --- llvm/trunk/test/DebugInfo/printdbginfo.ll (original) +++ llvm/trunk/test/DebugInfo/printdbginfo.ll Tue Jun 23 17:11:37 2009 @@ -11,58 +11,58 @@ %llvm.dbg.variable.type = type { i32, { }*, i8*, { }*, i32, { }* } %struct.Bar = type { %struct.Foo, i32 } %struct.Foo = type { i32 } - at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type { i32 393262, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* getelementptr ([9 x i8]* @.str4, i32 0, i32 0), i8* getelementptr ([14 x i8]* @.str5, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] - at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { i32 393216, i32 46 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] - at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 393233, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 4, i8* getelementptr ([8 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([13 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([52 x i8]* @.str2, i32 0, i32 0) }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] - at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 393216, i32 17 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* getelementptr ([9 x i8]* @.str4, i32 0, i32 0), i8* getelementptr ([14 x i8]* @.str5, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { i32 45872, i32 46 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] + at llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 4, i8* getelementptr ([8 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([13 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([52 x i8]* @.str2, i32 0, i32 0) }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1] + at llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 45872, i32 17 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1] @.str = internal constant [8 x i8] c"tst.cpp\00", section "llvm.metadata" ; <[8 x i8]*> [#uses=1] @.str1 = internal constant [13 x i8] c"/home/edwin/\00", section "llvm.metadata" ; <[13 x i8]*> [#uses=1] @.str2 = internal constant [52 x i8] c"4.2.1 (Based on Apple Inc. build 5623) (LLVM build)\00", section "llvm.metadata" ; <[52 x i8]*> [#uses=1] @.str3 = internal constant [4 x i8] c"bar\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] @.str4 = internal constant [9 x i8] c"Bar::bar\00", section "llvm.metadata" ; <[9 x i8]*> [#uses=1] @.str5 = internal constant [14 x i8] c"_ZN3Bar3barEv\00", section "llvm.metadata" ; <[14 x i8]*> [#uses=1] - at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 393252, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str6, i32 0, i32 0), { }* null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] + at llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str6, i32 0, i32 0), { }* null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1] @.str6 = internal constant [4 x i8] c"int\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] - at llvm.dbg.variable = internal constant %llvm.dbg.variable.type { i32 393473, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([5 x i8]* @.str7, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=0] + at llvm.dbg.variable = internal constant %llvm.dbg.variable.type { i32 459009, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([5 x i8]* @.str7, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=0] @.str7 = internal constant [5 x i8] c"this\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1] - at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 393231, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 64, i64 64, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] - at llvm.dbg.compositetype = internal constant %llvm.dbg.compositetype.type { i32 393235, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str8, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 5, i64 64, i64 32, i64 0, i32 0, { }* null, { }* bitcast ([5 x { }*]* @llvm.dbg.array36 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] + at llvm.dbg.derivedtype = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 64, i64 64, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.compositetype = internal constant %llvm.dbg.compositetype.type { i32 458771, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str8, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 5, i64 64, i64 32, i64 0, i32 0, { }* null, { }* bitcast ([5 x { }*]* @llvm.dbg.array36 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] @.str8 = internal constant [4 x i8] c"Bar\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] - at llvm.dbg.derivedtype9 = internal constant %llvm.dbg.derivedtype.type { i32 393244, { }* null, i8* null, { }* null, i32 0, i64 0, i64 0, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype10 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] - at llvm.dbg.compositetype10 = internal constant %llvm.dbg.compositetype.type { i32 393235, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str11, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 1, i64 32, i64 32, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array22 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] + at llvm.dbg.derivedtype9 = internal constant %llvm.dbg.derivedtype.type { i32 458780, { }* null, i8* null, { }* null, i32 0, i64 0, i64 0, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype10 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.compositetype10 = internal constant %llvm.dbg.compositetype.type { i32 458771, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str11, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 1, i64 32, i64 32, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array22 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] @.str11 = internal constant [4 x i8] c"Foo\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] - at llvm.dbg.derivedtype12 = internal constant %llvm.dbg.derivedtype.type { i32 393229, { }* null, i8* getelementptr ([7 x i8]* @.str13, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype12 = internal constant %llvm.dbg.derivedtype.type { i32 458765, { }* null, i8* getelementptr ([7 x i8]* @.str13, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 2, i64 32, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] @.str13 = internal constant [7 x i8] c"FooVar\00", section "llvm.metadata" ; <[7 x i8]*> [#uses=1] - at llvm.dbg.subprogram14 = internal constant %llvm.dbg.subprogram.type { i32 393262, { }* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str11, i32 0, i32 0), i8* getelementptr ([9 x i8]* @.str15, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype16 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.subprogram14 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str11, i32 0, i32 0), i8* getelementptr ([9 x i8]* @.str15, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype16 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] @.str15 = internal constant [9 x i8] c"Foo::Foo\00", section "llvm.metadata" ; <[9 x i8]*> [#uses=1] - at llvm.dbg.compositetype16 = internal constant %llvm.dbg.compositetype.type { i32 393237, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 8, i64 8, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] - at llvm.dbg.derivedtype17 = internal constant %llvm.dbg.derivedtype.type { i32 393231, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 64, i64 64, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype10 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] - at llvm.dbg.derivedtype18 = internal constant %llvm.dbg.derivedtype.type { i32 393232, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 64, i64 64, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype10 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.compositetype16 = internal constant %llvm.dbg.compositetype.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 8, i64 8, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] + at llvm.dbg.derivedtype17 = internal constant %llvm.dbg.derivedtype.type { i32 458767, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 64, i64 64, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype10 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype18 = internal constant %llvm.dbg.derivedtype.type { i32 458768, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 64, i64 64, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype10 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] @llvm.dbg.array = internal constant [3 x { }*] [ { }* null, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype17 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype18 to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] - at llvm.dbg.subprogram19 = internal constant %llvm.dbg.subprogram.type { i32 393262, { }* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str11, i32 0, i32 0), i8* getelementptr ([9 x i8]* @.str15, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype20 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] - at llvm.dbg.compositetype20 = internal constant %llvm.dbg.compositetype.type { i32 393237, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 8, i64 8, i64 0, i32 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array21 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] + at llvm.dbg.subprogram19 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str11, i32 0, i32 0), i8* getelementptr ([9 x i8]* @.str15, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype20 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.compositetype20 = internal constant %llvm.dbg.compositetype.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 8, i64 8, i64 0, i32 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array21 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] @llvm.dbg.array21 = internal constant [2 x { }*] [ { }* null, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype17 to { }*) ], section "llvm.metadata" ; <[2 x { }*]*> [#uses=1] @llvm.dbg.array22 = internal constant [3 x { }*] [ { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype12 to { }*), { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram14 to { }*), { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram19 to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] - at llvm.dbg.derivedtype23 = internal constant %llvm.dbg.derivedtype.type { i32 393229, { }* null, i8* getelementptr ([7 x i8]* @.str24, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 6, i64 32, i64 32, i64 32, i32 1, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.derivedtype23 = internal constant %llvm.dbg.derivedtype.type { i32 458765, { }* null, i8* getelementptr ([7 x i8]* @.str24, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 6, i64 32, i64 32, i64 32, i32 1, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] @.str24 = internal constant [7 x i8] c"BarVar\00", section "llvm.metadata" ; <[7 x i8]*> [#uses=1] - at llvm.dbg.subprogram25 = internal constant %llvm.dbg.subprogram.type { i32 393262, { }* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str8, i32 0, i32 0), i8* getelementptr ([9 x i8]* @.str26, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype27 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.subprogram25 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str8, i32 0, i32 0), i8* getelementptr ([9 x i8]* @.str26, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype27 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] @.str26 = internal constant [9 x i8] c"Bar::Bar\00", section "llvm.metadata" ; <[9 x i8]*> [#uses=1] - at llvm.dbg.compositetype27 = internal constant %llvm.dbg.compositetype.type { i32 393237, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 8, i64 8, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array29 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] - at llvm.dbg.derivedtype28 = internal constant %llvm.dbg.derivedtype.type { i32 393232, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 64, i64 64, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] + at llvm.dbg.compositetype27 = internal constant %llvm.dbg.compositetype.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 8, i64 8, i64 0, i32 0, { }* null, { }* bitcast ([3 x { }*]* @llvm.dbg.array29 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] + at llvm.dbg.derivedtype28 = internal constant %llvm.dbg.derivedtype.type { i32 458768, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 64, i64 64, i64 0, i32 0, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.derivedtype.type*> [#uses=1] @llvm.dbg.array29 = internal constant [3 x { }*] [ { }* null, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype28 to { }*) ], section "llvm.metadata" ; <[3 x { }*]*> [#uses=1] - at llvm.dbg.subprogram30 = internal constant %llvm.dbg.subprogram.type { i32 393262, { }* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str8, i32 0, i32 0), i8* getelementptr ([9 x i8]* @.str26, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype31 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] - at llvm.dbg.compositetype31 = internal constant %llvm.dbg.compositetype.type { i32 393237, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 8, i64 8, i64 0, i32 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array32 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] + at llvm.dbg.subprogram30 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str8, i32 0, i32 0), i8* getelementptr ([9 x i8]* @.str26, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype31 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.compositetype31 = internal constant %llvm.dbg.compositetype.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 8, i64 8, i64 0, i32 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array32 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] @llvm.dbg.array32 = internal constant [2 x { }*] [ { }* null, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) ], section "llvm.metadata" ; <[2 x { }*]*> [#uses=1] - at llvm.dbg.subprogram33 = internal constant %llvm.dbg.subprogram.type { i32 393262, { }* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* getelementptr ([9 x i8]* @.str4, i32 0, i32 0), i8* getelementptr ([14 x i8]* @.str5, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype34 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] - at llvm.dbg.compositetype34 = internal constant %llvm.dbg.compositetype.type { i32 393237, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 8, i64 8, i64 0, i32 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array35 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] + at llvm.dbg.subprogram33 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), i8* getelementptr ([9 x i8]* @.str4, i32 0, i32 0), i8* getelementptr ([14 x i8]* @.str5, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 12, { }* bitcast (%llvm.dbg.compositetype.type* @llvm.dbg.compositetype34 to { }*), i1 false, i1 false }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.compositetype34 = internal constant %llvm.dbg.compositetype.type { i32 458773, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 8, i64 8, i64 0, i32 0, { }* null, { }* bitcast ([2 x { }*]* @llvm.dbg.array35 to { }*) }, section "llvm.metadata" ; <%llvm.dbg.compositetype.type*> [#uses=1] @llvm.dbg.array35 = internal constant [2 x { }*] [ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) ], section "llvm.metadata" ; <[2 x { }*]*> [#uses=1] @llvm.dbg.array36 = internal constant [5 x { }*] [ { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype9 to { }*), { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype23 to { }*), { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram25 to { }*), { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram30 to { }*), { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram33 to { }*) ], section "llvm.metadata" ; <[5 x { }*]*> [#uses=1] - at llvm.dbg.variable37 = internal constant %llvm.dbg.variable.type { i32 393472, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([4 x i8]* @.str38, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 15, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=0] + at llvm.dbg.variable37 = internal constant %llvm.dbg.variable.type { i32 459008, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([4 x i8]* @.str38, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 15, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=0] @.str38 = internal constant [4 x i8] c"tmp\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] - at llvm.dbg.subprogram39 = internal constant %llvm.dbg.subprogram.type { i32 393262, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([7 x i8]* @.str40, i32 0, i32 0), i8* getelementptr ([7 x i8]* @.str40, i32 0, i32 0), i8* getelementptr ([11 x i8]* @.str41, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 21, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] + at llvm.dbg.subprogram39 = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([7 x i8]* @.str40, i32 0, i32 0), i8* getelementptr ([7 x i8]* @.str40, i32 0, i32 0), i8* getelementptr ([11 x i8]* @.str41, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 21, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1] @.str40 = internal constant [7 x i8] c"foobar\00", section "llvm.metadata" ; <[7 x i8]*> [#uses=1] @.str41 = internal constant [11 x i8] c"_Z6foobarv\00", section "llvm.metadata" ; <[11 x i8]*> [#uses=1] - at llvm.dbg.variable42 = internal constant %llvm.dbg.variable.type { i32 393472, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram39 to { }*), i8* getelementptr ([4 x i8]* @.str38, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 23, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=0] + at llvm.dbg.variable42 = internal constant %llvm.dbg.variable.type { i32 459008, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram39 to { }*), i8* getelementptr ([4 x i8]* @.str38, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 23, { }* bitcast (%llvm.dbg.derivedtype.type* @llvm.dbg.derivedtype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=0] define i32 @_ZN3Bar3barEv(%struct.Bar* %this1) nounwind { entry: From dpatel at apple.com Tue Jun 23 17:23:13 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 23 Jun 2009 22:23:13 -0000 Subject: [llvm-commits] [llvm] r74017 - /llvm/trunk/lib/Analysis/DbgInfoPrinter.cpp Message-ID: <200906232223.n5NMNDkM005214@zion.cs.uiuc.edu> Author: dpatel Date: Tue Jun 23 17:23:13 2009 New Revision: 74017 URL: http://llvm.org/viewvc/llvm-project?rev=74017&view=rev Log: Use getReturnTypeName() to print return type. Modified: llvm/trunk/lib/Analysis/DbgInfoPrinter.cpp Modified: llvm/trunk/lib/Analysis/DbgInfoPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DbgInfoPrinter.cpp?rev=74017&r1=74016&r2=74017&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DbgInfoPrinter.cpp (original) +++ llvm/trunk/lib/Analysis/DbgInfoPrinter.cpp Tue Jun 23 17:23:13 2009 @@ -93,7 +93,7 @@ DISubprogram Subprogram(cast(FS->getSubprogram())); std::string Res1, Res2; Out << "; fully qualified function name: " << Subprogram.getDisplayName(Res1) - << " return type: " << Subprogram.getType().getName(Res2) + << " return type: " << Subprogram.getReturnTypeName(Res2) << " at line " << Subprogram.getLineNumber() << "\n\n"; } From dpatel at apple.com Tue Jun 23 17:25:41 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 23 Jun 2009 22:25:41 -0000 Subject: [llvm-commits] [llvm] r74018 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/Analysis/DebugInfo.cpp Message-ID: <200906232225.n5NMPfKV005314@zion.cs.uiuc.edu> Author: dpatel Date: Tue Jun 23 17:25:41 2009 New Revision: 74018 URL: http://llvm.org/viewvc/llvm-project?rev=74018&view=rev Log: It is not a good idea to have data member's name match argument's name. In fact, it is a simple receipe to waste an hour or so. Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h llvm/trunk/lib/Analysis/DebugInfo.cpp Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=74018&r1=74017&r2=74018&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Tue Jun 23 17:25:41 2009 @@ -36,7 +36,7 @@ class DIDescriptor { protected: - GlobalVariable *GV; + GlobalVariable *DbgGV; /// DIDescriptor constructor. If the specified GV is non-null, this checks /// to make sure that the tag in the descriptor matches 'RequiredTag'. If @@ -58,12 +58,12 @@ GlobalVariable *getGlobalVariableField(unsigned Elt) const; public: - explicit DIDescriptor() : GV(0) {} - explicit DIDescriptor(GlobalVariable *gv) : GV(gv) {} + explicit DIDescriptor() : DbgGV(0) {} + explicit DIDescriptor(GlobalVariable *GV) : DbgGV(GV) {} - bool isNull() const { return GV == 0; } + bool isNull() const { return DbgGV == 0; } - GlobalVariable *getGV() const { return GV; } + GlobalVariable *getGV() const { return DbgGV; } unsigned getVersion() const { return getUnsignedField(0) & LLVMDebugVersionMask; @@ -245,7 +245,7 @@ explicit DIDerivedType(GlobalVariable *GV) : DIType(GV, true, true) { if (GV && !isDerivedType(getTag())) - GV = 0; + DbgGV = 0; } DIType getTypeDerivedFrom() const { return getFieldAs(9); } @@ -265,7 +265,7 @@ explicit DICompositeType(GlobalVariable *GV) : DIDerivedType(GV, true, true) { if (GV && !isCompositeType(getTag())) - GV = 0; + DbgGV = 0; } DIArray getTypeArray() const { return getFieldAs(10); } @@ -373,10 +373,10 @@ /// global etc). class DIVariable : public DIDescriptor { public: - explicit DIVariable(GlobalVariable *gv = 0) - : DIDescriptor(gv) { - if (gv && !isVariable(getTag())) - GV = 0; + explicit DIVariable(GlobalVariable *GV = 0) + : DIDescriptor(GV) { + if (GV && !isVariable(getTag())) + DbgGV = 0; } DIDescriptor getContext() const { return getDescriptorField(1); } Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=74018&r1=74017&r2=74018&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Tue Jun 23 17:25:41 2009 @@ -73,22 +73,22 @@ return true; } -DIDescriptor::DIDescriptor(GlobalVariable *gv, unsigned RequiredTag) { - GV = gv; +DIDescriptor::DIDescriptor(GlobalVariable *GV, unsigned RequiredTag) { + DbgGV = GV; // If this is non-null, check to see if the Tag matches. If not, set to null. if (GV && getTag() != RequiredTag) - GV = 0; + DbgGV = 0; } const std::string & DIDescriptor::getStringField(unsigned Elt, std::string &Result) const { - if (GV == 0) { + if (DbgGV == 0) { Result.clear(); return Result; } - Constant *C = GV->getInitializer(); + Constant *C = DbgGV->getInitializer(); if (C == 0 || Elt >= C->getNumOperands()) { Result.clear(); return Result; @@ -102,9 +102,9 @@ } uint64_t DIDescriptor::getUInt64Field(unsigned Elt) const { - if (GV == 0) return 0; + if (DbgGV == 0) return 0; - Constant *C = GV->getInitializer(); + Constant *C = DbgGV->getInitializer(); if (C == 0 || Elt >= C->getNumOperands()) return 0; @@ -114,9 +114,9 @@ } DIDescriptor DIDescriptor::getDescriptorField(unsigned Elt) const { - if (GV == 0) return DIDescriptor(); + if (DbgGV == 0) return DIDescriptor(); - Constant *C = GV->getInitializer(); + Constant *C = DbgGV->getInitializer(); if (C == 0 || Elt >= C->getNumOperands()) return DIDescriptor(); @@ -125,9 +125,9 @@ } GlobalVariable *DIDescriptor::getGlobalVariableField(unsigned Elt) const { - if (GV == 0) return 0; + if (DbgGV == 0) return 0; - Constant *C = GV->getInitializer(); + Constant *C = DbgGV->getInitializer(); if (C == 0 || Elt >= C->getNumOperands()) return 0; @@ -140,12 +140,12 @@ //===----------------------------------------------------------------------===// // Needed by DIVariable::getType(). -DIType::DIType(GlobalVariable *gv) : DIDescriptor(gv) { - if (!gv) return; +DIType::DIType(GlobalVariable *GV) : DIDescriptor(GV) { + if (!GV) return; unsigned tag = getTag(); if (tag != dwarf::DW_TAG_base_type && !DIDerivedType::isDerivedType(tag) && !DICompositeType::isCompositeType(tag)) - GV = 0; + DbgGV = 0; } /// isDerivedType - Return true if the specified tag is legal for @@ -198,8 +198,8 @@ } unsigned DIArray::getNumElements() const { - assert (GV && "Invalid DIArray"); - Constant *C = GV->getInitializer(); + assert (DbgGV && "Invalid DIArray"); + Constant *C = DbgGV->getInitializer(); assert (C && "Invalid DIArray initializer"); return C->getNumOperands(); } @@ -959,7 +959,7 @@ /// dump - Print descriptor. void DIDescriptor::dump() const { cerr << "[" << dwarf::TagString(getTag()) << "] "; - cerr << std::hex << "[GV:" << GV << "]" << std::dec; + cerr << std::hex << "[GV:" << DbgGV << "]" << std::dec; } /// dump - Print compile unit. @@ -1000,11 +1000,11 @@ cerr << " [fwd] "; if (isBasicType(Tag)) - DIBasicType(GV).dump(); + DIBasicType(DbgGV).dump(); else if (isDerivedType(Tag)) - DIDerivedType(GV).dump(); + DIDerivedType(DbgGV).dump(); else if (isCompositeType(Tag)) - DICompositeType(GV).dump(); + DICompositeType(DbgGV).dump(); else { cerr << "Invalid DIType\n"; return; @@ -1051,7 +1051,7 @@ cerr << " [def] "; if (isGlobalVariable(Tag)) - DIGlobalVariable(GV).dump(); + DIGlobalVariable(DbgGV).dump(); cerr << "\n"; } From daniel at zuster.org Tue Jun 23 18:02:45 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 23 Jun 2009 23:02:45 -0000 Subject: [llvm-commits] [llvm] r74019 - /llvm/trunk/include/llvm/MC/MCStreamer.h Message-ID: <200906232302.n5NN2mjV006787@zion.cs.uiuc.edu> Author: ddunbar Date: Tue Jun 23 18:02:31 2009 New Revision: 74019 URL: http://llvm.org/viewvc/llvm-project?rev=74019&view=rev Log: Add comments for the MCStreamer interface. Modified: llvm/trunk/include/llvm/MC/MCStreamer.h Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=74019&r1=74018&r2=74019&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Tue Jun 23 18:02:31 2009 @@ -34,26 +34,97 @@ MCStreamer(const MCStreamer&); // DO NOT IMPLEMENT MCStreamer &operator=(const MCStreamer&); // DO NOT IMPLEMENT - public: + protected: MCStreamer(MCContext &Ctx); + + public: virtual ~MCStreamer(); MCContext &getContext() const { return Context; } - virtual void SwitchSection(MCSection *Sect) = 0; - - virtual void EmitSymbol(MCSymbol *Sym); - virtual void EmitSymbolAssignment(MCSymbol *Sym, const MCImm &Value) = 0; - virtual void EmitSymbolAttribute(MCSymbol *Sym, - SymbolAttr Attr) = 0; - + /// SwitchSection - Set the current section where code is being emitted to + /// @param Section. + /// + /// This corresponds to assembler directives like .section, .text, etc. + virtual void SwitchSection(MCSection *Section) = 0; + + /// EmitLabel - Emit a label for @param Symbol into the current section. + /// + /// This corresponds to an assembler statement such as: + /// foo: + /// + /// @param Symbol - The symbol to emit. A given symbol should only be + /// emitted as a label once, and symbols emitted as a label should never be + /// used in an assignment. + // + // FIXME: What to do about the current section? Should we get rid of the + // symbol section in the constructor and initialize it here? + virtual void EmitLabel(MCSymbol *Symbol); + + /// EmitAssignment - Emit an assignment of @param Value to @param Symbol. + /// + /// This corresponds to an assembler statement such as: + /// symbol = value + /// + /// The assignment generates no code, but has the side effect of binding the + /// value in the current context. For the assembly streamer, this prints the + /// binding into the .s file. + /// + /// @param Symbol - The symbol being assigned to. + /// @param Value - The value for the symbol. + /// @param MakeAbsolute - If true, then the symbol should be given the + /// absolute value of @param Value, even if @param Value would be + /// relocatable expression. This corresponds to the ".set" directive. + virtual void EmitAssignment(MCSymbol *Symbol, const MCImm &Value, + bool MakeAbsolute = false) = 0; + + /// EmitSymbolAttribute - Add the given @param Attribute to @param Symbol. + // + // FIXME: This doesn't make much sense, could we just have attributes be on + // the symbol and make the printer smart enough to add the right symbols? + // This should work as long as the order of attributes in the file doesn't + // matter. + virtual void EmitSymbolAttribute(MCSymbol *Symbol, + SymbolAttr Attribute) = 0; + + /// EmitBytes - Emit @param Length bytes starting at @param Data into the + /// output. + /// + /// This is used to implement assembler directives such as .byte, .ascii, + /// etc. virtual void EmitBytes(const char *Data, unsigned Length) = 0; + + /// EmitValue - Emit the expression @param Value into the output as a native + /// integer of the given @param Size bytes. + /// + /// This is used to implement assembler directives such as .word, .quad, + /// etc. + /// + /// @param Value - The value to emit. + /// @param Size - The size of the integer (in bytes) to emit. This must + /// match a native machine width. virtual void EmitValue(const MCImm &Value, unsigned Size) = 0; + + /// EmitInstruction - Emit the given @param Instruction into the current + /// section. virtual void EmitInstruction(const MCInst &Inst) = 0; }; + /// createAsmStreamer - Create a machine code streamer which will print out + /// assembly for the native target, suitable for compiling with a native + /// assembler. MCStreamer *createAsmStreamer(MCContext &Ctx, raw_ostream &OS); + + // FIXME: These two may end up getting rolled into a single + // createObjectStreamer interface, which implements the assembler backend, and + // is parameterized on an output object file writer. + + /// createMachOStream - Create a machine code streamer which will generative + /// Mach-O format object files. MCStreamer *createMachOStreamer(MCContext &Ctx, raw_ostream &OS); + + /// createELFStreamer - Create a machine code streamer which will generative + /// ELF format object files. MCStreamer *createELFStreamer(MCContext &Ctx, raw_ostream &OS); } // end namespace llvm From clattner at apple.com Tue Jun 23 18:04:42 2009 From: clattner at apple.com (Chris Lattner) Date: Tue, 23 Jun 2009 16:04:42 -0700 Subject: [llvm-commits] [llvm] r74000 - in /llvm/trunk: Makefile.rules include/llvm/CompilerDriver/ForceLinkage.h include/llvm/CompilerDriver/ForceLinkageMacros.h include/llvm/CompilerDriver/Main.inc tools/llvmc/driver/Makefile utils/TableGen/LLVMCConfigurationEmitter.cpp In-Reply-To: <200906232046.n5NKknpK001717@zion.cs.uiuc.edu> References: <200906232046.n5NKknpK001717@zion.cs.uiuc.edu> Message-ID: <88054C81-2C4A-46FC-BF72-C51663E6F265@apple.com> On Jun 23, 2009, at 1:46 PM, Mikhail Glushenkov wrote: > Author: foldr > Date: Tue Jun 23 15:46:48 2009 > New Revision: 74000 > > URL: http://llvm.org/viewvc/llvm-project?rev=74000&view=rev > Log: > Make llvmc work again. > > Chris recently broke llvmc with his Makefile changes (r75379). That > patch made > the global change .o -> .a, which caused built-in llvmc plugins to > stop working > since plugin initialization in llvmc is based on static variables > not referenced > from the main executable. This patch implements auto-generated > forced references > to the plugin libraries. Thank you Mikhail! I'm sorry for the breakage, -Chris From sabre at nondot.org Tue Jun 23 18:31:52 2009 From: sabre at nondot.org (Chris Lattner) Date: Tue, 23 Jun 2009 23:31:52 -0000 Subject: [llvm-commits] [llvm] r74023 - in /llvm/trunk/include/llvm/MC: MCImm.h MCInst.h MCValue.h Message-ID: <200906232331.n5NNVqcU007793@zion.cs.uiuc.edu> Author: lattner Date: Tue Jun 23 18:31:52 2009 New Revision: 74023 URL: http://llvm.org/viewvc/llvm-project?rev=74023&view=rev Log: rename MCImm ->MCValue. Added: llvm/trunk/include/llvm/MC/MCValue.h - copied, changed from r74018, llvm/trunk/include/llvm/MC/MCImm.h Removed: llvm/trunk/include/llvm/MC/MCImm.h Modified: llvm/trunk/include/llvm/MC/MCInst.h Removed: llvm/trunk/include/llvm/MC/MCImm.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCImm.h?rev=74022&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCImm.h (original) +++ llvm/trunk/include/llvm/MC/MCImm.h (removed) @@ -1,57 +0,0 @@ -//===-- llvm/MC/MCImm.h - MCImm class ---------------------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the declaration of the MCInst and MCOperand classes, which -// is the basic representation used to represent low-level machine code -// instructions. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_MC_MCIMM_H -#define LLVM_MC_MCIMM_H - -#include "llvm/Support/DataTypes.h" - -namespace llvm { -class MCSymbol; - -/// MCImm - This represents an "assembler immediate". In its most general form, -/// this can hold "SymbolA - SymbolB + imm64". Not all targets supports -/// relocations of this general form, but we need to represent this anyway. -class MCImm { - MCSymbol *SymA, *SymB; - int64_t Cst; -public: - - int64_t getCst() const { return Cst; } - MCSymbol *getSymA() const { return SymA; } - MCSymbol *getSymB() const { return SymB; } - - - static MCImm get(MCSymbol *SymA, MCSymbol *SymB = 0, int64_t Val = 0) { - MCImm R; - R.Cst = Val; - R.SymA = SymA; - R.SymB = SymB; - return R; - } - - static MCImm get(int64_t Val) { - MCImm R; - R.Cst = Val; - R.SymA = 0; - R.SymB = 0; - return R; - } - -}; - -} // end namespace llvm - -#endif Modified: llvm/trunk/include/llvm/MC/MCInst.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInst.h?rev=74023&r1=74022&r2=74023&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInst.h (original) +++ llvm/trunk/include/llvm/MC/MCInst.h Tue Jun 23 18:31:52 2009 @@ -16,7 +16,7 @@ #ifndef LLVM_MC_MCINST_H #define LLVM_MC_MCINST_H -#include "llvm/MC/MCImm.h" +#include "llvm/MC/MCValue.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/DataTypes.h" #include "llvm/Support/DebugLoc.h" @@ -31,14 +31,14 @@ kRegister, ///< Register operand. kImmediate, ///< Immediate operand. kMBBLabel, ///< Basic block label. - kMCImm + kMCValue }; unsigned char Kind; union { unsigned RegVal; int64_t ImmVal; - MCImm MCImmVal; + MCValue MCValueVal; struct { unsigned FunctionNo; unsigned BlockNo; Copied: llvm/trunk/include/llvm/MC/MCValue.h (from r74018, llvm/trunk/include/llvm/MC/MCImm.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCValue.h?p2=llvm/trunk/include/llvm/MC/MCValue.h&p1=llvm/trunk/include/llvm/MC/MCImm.h&r1=74018&r2=74023&rev=74023&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCImm.h (original) +++ llvm/trunk/include/llvm/MC/MCValue.h Tue Jun 23 18:31:52 2009 @@ -1,4 +1,4 @@ -//===-- llvm/MC/MCImm.h - MCImm class ---------------------------*- C++ -*-===// +//===-- llvm/MC/MCValue.h - MCValue class -----------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,24 +7,25 @@ // //===----------------------------------------------------------------------===// // -// This file contains the declaration of the MCInst and MCOperand classes, which -// is the basic representation used to represent low-level machine code -// instructions. +// This file contains the declaration of the MCValue class. // //===----------------------------------------------------------------------===// -#ifndef LLVM_MC_MCIMM_H -#define LLVM_MC_MCIMM_H +#ifndef LLVM_MC_MCVALUE_H +#define LLVM_MC_MCVALUE_H #include "llvm/Support/DataTypes.h" namespace llvm { class MCSymbol; -/// MCImm - This represents an "assembler immediate". In its most general form, -/// this can hold "SymbolA - SymbolB + imm64". Not all targets supports +/// MCValue - This represents an "assembler immediate". In its most general +/// form, this can hold "SymbolA - SymbolB + imm64". Not all targets supports /// relocations of this general form, but we need to represent this anyway. -class MCImm { +/// +/// Note that this class must remain a simple POD value class, because we need +/// it to live in unions etc. +class MCValue { MCSymbol *SymA, *SymB; int64_t Cst; public: @@ -34,16 +35,16 @@ MCSymbol *getSymB() const { return SymB; } - static MCImm get(MCSymbol *SymA, MCSymbol *SymB = 0, int64_t Val = 0) { - MCImm R; + static MCValue get(MCSymbol *SymA, MCSymbol *SymB = 0, int64_t Val = 0) { + MCValue R; R.Cst = Val; R.SymA = SymA; R.SymB = SymB; return R; } - static MCImm get(int64_t Val) { - MCImm R; + static MCValue get(int64_t Val) { + MCValue R; R.Cst = Val; R.SymA = 0; R.SymB = 0; From eric.rannaud at gmail.com Tue Jun 23 13:42:11 2009 From: eric.rannaud at gmail.com (Eric Rannaud) Date: Tue, 23 Jun 2009 11:42:11 -0700 Subject: [llvm-commits] Compile error in lib/Support/Timer.cpp introduced by r73978 Message-ID: <20090623184211.GA19005@nc050> r73978 changes the type of Timer::PeakMemBase and Timer::PeakMem to signed int64_t in lib/Support/Timer.cpp: (*I)->PeakMem = std::max((*I)->PeakMem, MemUsed-(*I)->PeakMemBase); gives: Timer.cpp: In static member function ???static void llvm::Timer::addPeakMemoryMeasurement()???: Timer.cpp:189: error: no matching function for call to ???max(int64_t&, long unsigned int)??? as MemUsed is a size_t. Thanks, Eric. From eric.rannaud at gmail.com Tue Jun 23 13:44:49 2009 From: eric.rannaud at gmail.com (Eric Rannaud) Date: Tue, 23 Jun 2009 11:44:49 -0700 Subject: [llvm-commits] Compile error in lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp introduced by r73965 Message-ID: <20090623184449.GB19005@nc050> ARMAsmPrinter.cpp: In member function ???void::ARMAsmPrinter::printBitfieldInvMaskImmOperand(const llvm::MachineInstr*, int)???: ARMAsmPrinter.cpp:647: error: ???fls??? was not declared in this scope fls is nowhere to be found in LLVM. From andreas.bolka at gmx.net Tue Jun 23 17:51:33 2009 From: andreas.bolka at gmx.net (Andreas Bolka) Date: Wed, 24 Jun 2009 00:51:33 +0200 Subject: [llvm-commits] [PATCH] Scaffolding for LDA pass. Message-ID: <1245796690-sup-9594@strider> I am working on auto-vectorization/loop dependence analysis as part of Google's Summer of Code program. Here's a patch to add a minimal skeleton for a loop dependence analysis pass. While this pass currently does nothing, it allows future patches to be constrained to only modify the .h and .cpp, which should make them easier to review. Comments welcome! --- include/llvm/Analysis/LoopDependenceAnalysis.h | 52 ++++++++++++++++++++++++ include/llvm/Analysis/Passes.h | 8 ++++ include/llvm/LinkAllPasses.h | 1 + lib/Analysis/CMakeLists.txt | 1 + lib/Analysis/LoopDependenceAnalysis.cpp | 47 +++++++++++++++++++++ 5 files changed, 109 insertions(+), 0 deletions(-) create mode 100644 include/llvm/Analysis/LoopDependenceAnalysis.h create mode 100644 lib/Analysis/LoopDependenceAnalysis.cpp -- Andreas -------------- next part -------------- A non-text attachment was scrubbed... Name: 01-lda-scaffolding.patch Type: application/octet-stream Size: 5399 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090624/417707b7/attachment.obj From scallanan at apple.com Tue Jun 23 18:25:38 2009 From: scallanan at apple.com (Sean Callanan) Date: Tue, 23 Jun 2009 23:25:38 -0000 Subject: [llvm-commits] [llvm] r74022 - /llvm/trunk/lib/Target/X86/X86InstrInfo.td Message-ID: <200906232325.n5NNPcD4007589@zion.cs.uiuc.edu> Author: spyffe Date: Tue Jun 23 18:25:37 2009 New Revision: 74022 URL: http://llvm.org/viewvc/llvm-project?rev=74022&view=rev Log: Test commit: fixed spacing. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=74022&r1=74021&r2=74022&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Jun 23 18:25:37 2009 @@ -50,9 +50,9 @@ SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; -def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; -def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, - SDTCisVT<1, i32> ]>; +def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; +def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, + SDTCisVT<1, i32>]>; def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; From daniel at zuster.org Tue Jun 23 18:39:15 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 23 Jun 2009 23:39:15 -0000 Subject: [llvm-commits] [llvm] r74024 - in /llvm/trunk: include/llvm/MC/MCContext.h include/llvm/MC/MCStreamer.h lib/MC/MCContext.cpp Message-ID: <200906232339.n5NNdFjE008022@zion.cs.uiuc.edu> Author: ddunbar Date: Tue Jun 23 18:39:15 2009 New Revision: 74024 URL: http://llvm.org/viewvc/llvm-project?rev=74024&view=rev Log: Update for MCImm -> MCValue rename. Modified: llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/lib/MC/MCContext.cpp Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=74024&r1=74023&r2=74024&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Tue Jun 23 18:39:15 2009 @@ -16,7 +16,7 @@ namespace llvm { class MCAtom; - class MCImm; + class MCValue; class MCSection; class MCSymbol; @@ -32,7 +32,7 @@ StringMap Symbols; /// SymbolValues - Bindings of symbols to values. - DenseMap SymbolValues; + DenseMap SymbolValues; /// Allocator - Allocator object used for creating machine code objects. /// @@ -73,11 +73,11 @@ /// SetSymbolValue - Set the value binding for @param Symbol to @param /// Value. - void SetSymbolValue(MCSymbol *Symbol, const MCImm &Value); + void SetSymbolValue(MCSymbol *Symbol, const MCValue &Value); /// GetSymbolValue - Return the current value for @param Symbol, or null if /// none exists. - const MCImm *GetSymbolValue(MCSymbol *Symbol) const; + const MCValue *GetSymbolValue(MCSymbol *Symbol) const; void *Allocate(unsigned Size, unsigned Align = 8) { return Allocator.Allocate(Size, Align); Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=74024&r1=74023&r2=74024&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Tue Jun 23 18:39:15 2009 @@ -13,7 +13,7 @@ namespace llvm { class MCAtom; class MCContext; - class MCImm; + class MCValue; class MCInst; class MCSection; class MCSymbol; @@ -59,7 +59,7 @@ // // FIXME: What to do about the current section? Should we get rid of the // symbol section in the constructor and initialize it here? - virtual void EmitLabel(MCSymbol *Symbol); + virtual void EmitLabel(MCSymbol *Symbol) = 0; /// EmitAssignment - Emit an assignment of @param Value to @param Symbol. /// @@ -75,7 +75,7 @@ /// @param MakeAbsolute - If true, then the symbol should be given the /// absolute value of @param Value, even if @param Value would be /// relocatable expression. This corresponds to the ".set" directive. - virtual void EmitAssignment(MCSymbol *Symbol, const MCImm &Value, + virtual void EmitAssignment(MCSymbol *Symbol, const MCValue &Value, bool MakeAbsolute = false) = 0; /// EmitSymbolAttribute - Add the given @param Attribute to @param Symbol. @@ -103,11 +103,14 @@ /// @param Value - The value to emit. /// @param Size - The size of the integer (in bytes) to emit. This must /// match a native machine width. - virtual void EmitValue(const MCImm &Value, unsigned Size) = 0; + virtual void EmitValue(const MCValue &Value, unsigned Size) = 0; /// EmitInstruction - Emit the given @param Instruction into the current /// section. virtual void EmitInstruction(const MCInst &Inst) = 0; + + /// Finish - Finish emission of machine code and flush any output. + virtual void Finish() = 0; }; /// createAsmStreamer - Create a machine code streamer which will print out Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=74024&r1=74023&r2=74024&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Tue Jun 23 18:39:15 2009 @@ -1,4 +1,4 @@ -//===- lib/MachineCode/MCContext.cpp - Machine Code Context ---------------===// +//===- lib/MC/MCContext.cpp - Machine Code Context ------------------------===// // // The LLVM Compiler Infrastructure // @@ -10,9 +10,9 @@ #include "llvm/MC/MCContext.h" #include "llvm/MC/MCAtom.h" -#include "llvm/MC/MCImm.h" #include "llvm/MC/MCSection.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCValue.h" using namespace llvm; MCContext::MCContext() @@ -63,12 +63,12 @@ SymbolValues.erase(Sym); } -void MCContext::SetSymbolValue(MCSymbol *Sym, const MCImm &Value) { +void MCContext::SetSymbolValue(MCSymbol *Sym, const MCValue &Value) { SymbolValues[Sym] = Value; } -const MCImm *MCContext::GetSymbolValue(MCSymbol *Sym) const { - DenseMap::iterator it = SymbolValues.find(Sym); +const MCValue *MCContext::GetSymbolValue(MCSymbol *Sym) const { + DenseMap::iterator it = SymbolValues.find(Sym); if (it == SymbolValues.end()) return 0; From bob.wilson at apple.com Tue Jun 23 18:59:40 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 23 Jun 2009 23:59:40 -0000 Subject: [llvm-commits] [llvm] r74026 - in /llvm/trunk: include/llvm-c/ include/llvm/Config/ include/llvm/Target/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Alpha/AsmPrinter/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CellSPU/AsmPrinter/ lib/Target/CppBackend/ lib/Target/IA64/ lib/Target/IA64/AsmPrinter/ lib/Target/MSIL/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/Mips/AsmPrinter/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/PowerPC/AsmPrinter/ lib/Target/Sparc/ lib/Target/Sparc/AsmP... Message-ID: <200906232359.n5NNxfeG008666@zion.cs.uiuc.edu> Author: bwilson Date: Tue Jun 23 18:59:40 2009 New Revision: 74026 URL: http://llvm.org/viewvc/llvm-project?rev=74026&view=rev Log: Provide InitializeAllTargets and InitializeNativeTarget functions in the C bindings. Change all the backend "Initialize" functions to have C linkage. Change the "llvm/Config/Targets.def" header to use C-style comments to avoid compile warnings. Modified: llvm/trunk/include/llvm-c/Target.h llvm/trunk/include/llvm/Config/Targets.def.in llvm/trunk/include/llvm/Target/TargetSelect.h llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp llvm/trunk/lib/Target/CBackend/CBackend.cpp llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp llvm/trunk/lib/Target/MSIL/MSILWriter.cpp llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.cpp llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Modified: llvm/trunk/include/llvm-c/Target.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Target.h?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Target.h (original) +++ llvm/trunk/include/llvm-c/Target.h Tue Jun 23 18:59:40 2009 @@ -20,6 +20,7 @@ #define LLVM_C_TARGET_H #include "llvm-c/Core.h" +#include "llvm/Config/config.h" #ifdef __cplusplus extern "C" { @@ -31,6 +32,34 @@ typedef struct LLVMOpaqueTargetData *LLVMTargetDataRef; typedef struct LLVMStructLayout *LLVMStructLayoutRef; +/* Declare all of the target-initialization functions that are available. */ +#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##Target(); +#include "llvm/Config/Targets.def" + +/** LLVMInitializeAllTargets - The main program should call this function if it + wants to link in all available targets that LLVM is configured to + support. */ +static inline void LLVMInitializeAllTargets() { +#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##Target(); +#include "llvm/Config/Targets.def" +} + +/** LLVMInitializeNativeTarget - The main program should call this function to + initialize the native target corresponding to the host. This is useful + for JIT applications to ensure that the target gets linked in correctly. */ +static inline int LLVMInitializeNativeTarget() { + /* If we have a native target, initialize it to ensure it is linked in. */ +#ifdef LLVM_NATIVE_ARCH +#define DoInit2(TARG) LLVMInitialize ## TARG () +#define DoInit(T) DoInit2(T) + DoInit(LLVM_NATIVE_ARCH); + return 0; +#undef DoInit +#undef DoInit2 +#else + return 1; +#endif +} /*===-- Target Data -------------------------------------------------------===*/ Modified: llvm/trunk/include/llvm/Config/Targets.def.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/Targets.def.in?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/Targets.def.in (original) +++ llvm/trunk/include/llvm/Config/Targets.def.in Tue Jun 23 18:59:40 2009 @@ -1,23 +1,23 @@ -//===- llvm/Config/Targets.def - LLVM Target Architectures ------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file enumerates all of the target architectures supported by -// this build of LLVM. Clients of this file should define the -// LLVM_TARGET macro to be a function-like macro with a single -// parameter (the name of the target); including this file will then -// enumerate all of the targets. -// -// The set of targets supported by LLVM is generated at configuration -// time, at which point this header is generated. Do not modify this -// header directly. -// -//===----------------------------------------------------------------------===// +/*===- llvm/Config/Targets.def - LLVM Target Architectures ------*- C++ -*-===*\ +|* *| +|* The LLVM Compiler Infrastructure *| +|* *| +|* This file is distributed under the University of Illinois Open Source *| +|* License. See LICENSE.TXT for details. *| +|* *| +|*===----------------------------------------------------------------------===*| +|* *| +|* This file enumerates all of the target architectures supported by *| +|* this build of LLVM. Clients of this file should define the *| +|* LLVM_TARGET macro to be a function-like macro with a single *| +|* parameter (the name of the target); including this file will then *| +|* enumerate all of the targets. *| +|* *| +|* The set of targets supported by LLVM is generated at configuration *| +|* time, at which point this header is generated. Do not modify this *| +|* header directly. *| +|* *| +\*===----------------------------------------------------------------------===*/ #ifndef LLVM_TARGET # error Please define the macro LLVM_TARGET(TargetName) Modified: llvm/trunk/include/llvm/Target/TargetSelect.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelect.h?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSelect.h (original) +++ llvm/trunk/include/llvm/Target/TargetSelect.h Tue Jun 23 18:59:40 2009 @@ -18,20 +18,21 @@ #include "llvm/Config/config.h" -namespace llvm { +extern "C" { // Declare all of the target-initialization functions that are available. -#define LLVM_TARGET(TargetName) void Initialize##TargetName##Target(); +#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##Target(); #include "llvm/Config/Targets.def" // Declare all of the available asm-printer initialization functions. - // Declare all of the target-initialization functions. -#define LLVM_ASM_PRINTER(TargetName) void Initialize##TargetName##AsmPrinter(); +#define LLVM_ASM_PRINTER(TargetName) void LLVMInitialize##TargetName##AsmPrinter(); #include "llvm/Config/AsmPrinters.def" - +} + +namespace llvm { /// InitializeAllTargets - The main program should call this function if it /// wants to link in all available targets that LLVM is configured to support. inline void InitializeAllTargets() { -#define LLVM_TARGET(TargetName) llvm::Initialize##TargetName##Target(); +#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##Target(); #include "llvm/Config/Targets.def" } @@ -39,18 +40,17 @@ /// it wants all asm printers that LLVM is configured to support. This will /// cause them to be linked into its executable. inline void InitializeAllAsmPrinters() { -#define LLVM_ASM_PRINTER(TargetName) Initialize##TargetName##AsmPrinter(); +#define LLVM_ASM_PRINTER(TargetName) LLVMInitialize##TargetName##AsmPrinter(); #include "llvm/Config/AsmPrinters.def" } - /// InitializeNativeTarget - The main program should call this function to /// initialize the native target corresponding to the host. This is useful /// for JIT applications to ensure that the target gets linked in correctly. inline bool InitializeNativeTarget() { // If we have a native target, initialize it to ensure it is linked in. #ifdef LLVM_NATIVE_ARCH -#define DoInit2(TARG) llvm::Initialize ## TARG () +#define DoInit2(TARG) LLVMInitialize ## TARG () #define DoInit(T) DoInit2(T) DoInit(LLVM_NATIVE_ARCH); return false; Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Tue Jun 23 18:59:40 2009 @@ -39,10 +39,8 @@ static RegisterTarget X("arm", "ARM"); static RegisterTarget Y("thumb", "Thumb"); -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializeARMTarget() { } -} +// Force static initialization. +extern "C" void LLVMInitializeARMTarget() { } // No assembler printer by default ARMTargetMachine::AsmPrinterCtorFn ARMTargetMachine::AsmPrinterCtor = 0; Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Tue Jun 23 18:59:40 2009 @@ -1172,8 +1172,5 @@ } Registrator; } -// Force static initialization when called from -// llvm/InitializeAllAsmPrinters.h -namespace llvm { - void InitializeARMAsmPrinter() { } -} +// Force static initialization. +extern "C" void LLVMInitializeARMAsmPrinter() { } Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Tue Jun 23 18:59:40 2009 @@ -27,10 +27,8 @@ // No assembler printer by default AlphaTargetMachine::AsmPrinterCtorFn AlphaTargetMachine::AsmPrinterCtor = 0; -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializeAlphaTarget() { } -} +// Force static initialization. +extern "C" void LLVMInitializeAlphaTarget() { } const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const { return new AlphaTargetAsmInfo(*this); Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Tue Jun 23 18:59:40 2009 @@ -304,11 +304,8 @@ return false; } -// Force static initialization when called from -// llvm/InitializeAllAsmPrinters.h -namespace llvm { - void InitializeAlphaAsmPrinter() { } -} +// Force static initialization. +extern "C" void LLVMInitializeAlphaAsmPrinter() { } namespace { static struct Register { Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Tue Jun 23 18:59:40 2009 @@ -59,10 +59,8 @@ // Register the target. static RegisterTarget X("c", "C backend"); -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializeCBackendTarget() { } -} +// Force static initialization. +extern "C" void LLVMInitializeCBackendTarget() { } namespace { /// CBackendNameAllUsedStructsAndMergeFunctions - This pass inserts names for Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Tue Jun 23 18:59:40 2009 @@ -617,11 +617,8 @@ return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose); } -// Force static initialization when called from -// llvm/InitializeAllAsmPrinters.h -namespace llvm { - void InitializeCellSPUAsmPrinter() { } -} +// Force static initialization. +extern "C" void LLVMInitializeCellSPUAsmPrinter() { } namespace { static struct Register { Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Tue Jun 23 18:59:40 2009 @@ -32,10 +32,8 @@ // No assembler printer by default SPUTargetMachine::AsmPrinterCtorFn SPUTargetMachine::AsmPrinterCtor = 0; -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializeCellSPUTarget() { } -} +// Force static initialization. +extern "C" void LLVMInitializeCellSPUTarget() { } const std::pair * SPUFrameInfo::getCalleeSaveSpillSlots(unsigned &NumEntries) const { Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original) +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Tue Jun 23 18:59:40 2009 @@ -82,10 +82,8 @@ // Register the target. static RegisterTarget X("cpp", "C++ backend"); -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializeCppBackendTarget() { } -} +// Force static initialization. +extern "C" void LLVMInitializeCppBackendTarget() { } namespace { typedef std::vector TypeList; Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Tue Jun 23 18:59:40 2009 @@ -384,8 +384,5 @@ } -// Force static initialization when called from -// llvm/InitializeAllAsmPrinters.h -namespace llvm { - void InitializeIA64AsmPrinter() { } -} +// Force static initialization. +extern "C" void LLVMInitializeIA64AsmPrinter() { } Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Tue Jun 23 18:59:40 2009 @@ -26,10 +26,8 @@ // No assembler printer by default IA64TargetMachine::AsmPrinterCtorFn IA64TargetMachine::AsmPrinterCtor = 0; -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializeIA64Target() { } -} +// Force static initialization. +extern "C" void LLVMInitializeIA64Target() { } const TargetAsmInfo *IA64TargetMachine::createTargetAsmInfo() const { return new IA64TargetAsmInfo(*this); Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original) +++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Tue Jun 23 18:59:40 2009 @@ -55,10 +55,8 @@ static RegisterTarget X("msil", "MSIL backend"); -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializeMSILTarget() { } -} +// Force static initialization. +extern "C" void LLVMInitializeMSILTarget() { } bool MSILModule::runOnModule(Module &M) { ModulePtr = &M; Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Tue Jun 23 18:59:40 2009 @@ -35,10 +35,8 @@ static RegisterTarget X("msp430", "MSP430 [experimental]"); -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializeMSP430Target() { } -} +// Force static initialization. +extern "C" void LLVMInitializeMSP430Target() { } MSP430TargetMachine::MSP430TargetMachine(const Module &M, const std::string &FS) : Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Tue Jun 23 18:59:40 2009 @@ -587,8 +587,5 @@ } Registrator; } -// Force static initialization when called from -// llvm/InitializeAllAsmPrinters.h -namespace llvm { - void InitializeMipsAsmPrinter() { } -} +// Force static initialization. +extern "C" void LLVMInitializeMipsAsmPrinter() { } Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Tue Jun 23 18:59:40 2009 @@ -34,10 +34,8 @@ MipsTargetMachine::AsmPrinterCtorFn MipsTargetMachine::AsmPrinterCtor = 0; -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializeMipsTarget() { } -} +// Force static initialization. +extern "C" void LLVMInitializeMipsTarget() { } const TargetAsmInfo *MipsTargetMachine:: createTargetAsmInfo() const Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Tue Jun 23 18:59:40 2009 @@ -37,10 +37,8 @@ static RegisterTarget Y("cooper", "PIC16 Cooper [experimental]."); -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializePIC16Target() { } -} +// Force static initialization. +extern "C" void LLVMInitializePIC16Target() { } // PIC16TargetMachine - Traditional PIC16 Machine. PIC16TargetMachine::PIC16TargetMachine(const Module &M, const std::string &FS, Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Tue Jun 23 18:59:40 2009 @@ -1185,8 +1185,5 @@ extern "C" int PowerPCAsmPrinterForceLink; int PowerPCAsmPrinterForceLink = 0; -// Force static initialization when called from -// llvm/InitializeAllAsmPrinters.h -namespace llvm { - void InitializePowerPCAsmPrinter() { } -} +// Force static initialization. +extern "C" void LLVMInitializePowerPCAsmPrinter() { } Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Tue Jun 23 18:59:40 2009 @@ -35,10 +35,8 @@ static RegisterTarget Y("ppc64", "PowerPC 64"); -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializePowerPCTarget() { } -} +// Force static initialization. +extern "C" void LLVMInitializePowerPCTarget() { } // No assembler printer by default PPCTargetMachine::AsmPrinterCtorFn PPCTargetMachine::AsmPrinterCtor = 0; Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp Tue Jun 23 18:59:40 2009 @@ -362,8 +362,5 @@ } Registrator; } -// Force static initialization when called from -// llvm/InitializeAllAsmPrinters.h -namespace llvm { - void InitializeSparcAsmPrinter() { } -} +// Force static initialization. +extern "C" void LLVMInitializeSparcAsmPrinter() { } Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Tue Jun 23 18:59:40 2009 @@ -25,10 +25,8 @@ SparcTargetMachine::AsmPrinterCtorFn SparcTargetMachine::AsmPrinterCtor = 0; -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializeSparcTarget() { } -} +// Force static initialization. +extern "C" void LLVMInitializeSparcTarget() { } const TargetAsmInfo *SparcTargetMachine::createTargetAsmInfo() const { // FIXME: Handle Solaris subtarget someday :) Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Tue Jun 23 18:59:40 2009 @@ -47,8 +47,5 @@ extern "C" int X86AsmPrinterForceLink; int X86AsmPrinterForceLink = 0; -// Force static initialization when called from -// llvm/InitializeAllAsmPrinters.h -namespace llvm { - void InitializeX86AsmPrinter() { } -} +// Force static initialization. +extern "C" void LLVMInitializeX86AsmPrinter() { } Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Tue Jun 23 18:59:40 2009 @@ -36,10 +36,8 @@ static RegisterTarget Y("x86-64", "64-bit X86: EM64T and AMD64"); -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializeX86Target() { } -} +// Force static initialization. +extern "C" void LLVMInitializeX86Target() { } // No assembler printer by default X86TargetMachine::AsmPrinterCtorFn X86TargetMachine::AsmPrinterCtor = 0; Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Tue Jun 23 18:59:40 2009 @@ -31,10 +31,8 @@ RegisterTarget X("xcore", "XCore"); } -// Force static initialization when called from llvm/InitializeAllTargets.h -namespace llvm { - void InitializeXCoreTarget() { } -} +// Force static initialization. +extern "C" void LLVMInitializeXCoreTarget() { } const TargetAsmInfo *XCoreTargetMachine::createTargetAsmInfo() const { return new XCoreTargetAsmInfo(*this); From resistor at mac.com Tue Jun 23 19:17:11 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 23 Jun 2009 17:17:11 -0700 Subject: [llvm-commits] Compile error in lib/Support/Timer.cpp introduced by r73978 In-Reply-To: <20090623184211.GA19005@nc050> References: <20090623184211.GA19005@nc050> Message-ID: <1F82E9DE-5F86-4578-9A4E-5BACDB014404@mac.com> On Jun 23, 2009, at 11:42 AM, Eric Rannaud wrote: > r73978 changes the type of Timer::PeakMemBase and Timer::PeakMem to > signed int64_t Please update to TOT. This change has since been reverted. --Owen From resistor at mac.com Tue Jun 23 19:25:42 2009 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Jun 2009 00:25:42 -0000 Subject: [llvm-commits] [llvm] r74029 - /llvm/trunk/lib/VMCore/Pass.cpp Message-ID: <200906240025.n5O0PhFD009550@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 23 19:25:42 2009 New Revision: 74029 URL: http://llvm.org/viewvc/llvm-project?rev=74029&view=rev Log: Guard the listeners list. Unfortunately, this requires a real static rather than a managed static because other managed statics can (and do) access this list in their destructors. Yes, I know it's horrible. Modified: llvm/trunk/lib/VMCore/Pass.cpp Modified: llvm/trunk/lib/VMCore/Pass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Pass.cpp?rev=74029&r1=74028&r2=74029&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Pass.cpp (original) +++ llvm/trunk/lib/VMCore/Pass.cpp Tue Jun 23 19:25:42 2009 @@ -20,6 +20,7 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/System/Atomic.h" +#include "llvm/System/Mutex.h" #include "llvm/System/Threading.h" #include #include @@ -187,6 +188,7 @@ } static std::vector *Listeners = 0; +static sys::SmartMutex ListenersLock; // FIXME: This should use ManagedStatic to manage the pass registrar. // Unfortunately, we can't do this, because passes are registered with static @@ -231,6 +233,7 @@ getPassRegistrar()->RegisterPass(*this); // Notify any listeners. + sys::SmartScopedLock Lock(&ListenersLock); if (Listeners) for (std::vector::iterator I = Listeners->begin(), E = Listeners->end(); I != E; ++I) @@ -283,12 +286,14 @@ // PassRegistrationListener ctor - Add the current object to the list of // PassRegistrationListeners... PassRegistrationListener::PassRegistrationListener() { + sys::SmartScopedLock Lock(&ListenersLock); if (!Listeners) Listeners = new std::vector(); Listeners->push_back(this); } // dtor - Remove object from list of listeners... PassRegistrationListener::~PassRegistrationListener() { + sys::SmartScopedLock Lock(&ListenersLock); std::vector::iterator I = std::find(Listeners->begin(), Listeners->end(), this); assert(Listeners && I != Listeners->end() && From gohman at apple.com Tue Jun 23 19:29:00 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 00:29:00 -0000 Subject: [llvm-commits] [llvm] r74031 - /llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <200906240029.n5O0T0KJ009668@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 23 19:28:59 2009 New Revision: 74031 URL: http://llvm.org/viewvc/llvm-project?rev=74031&view=rev Log: Don't emit a redundant BitCastInst if the value to be defined in the preheader is already an instruction. Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=74031&r1=74030&r2=74031&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue Jun 23 19:28:59 2009 @@ -1642,7 +1642,8 @@ // the preheader, instead of being forward substituted into the uses. We // do this by forcing a BitCast (noop cast) to be inserted into the // preheader in this case. - if (!fitsInAddressMode(Base, getAccessType(Inst), TLI, false)) { + if (!fitsInAddressMode(Base, getAccessType(Inst), TLI, false) && + !isa(BaseV)) { // We want this constant emitted into the preheader! This is just // using cast as a copy so BitCast (no-op cast) is appropriate BaseV = new BitCastInst(BaseV, BaseV->getType(), "preheaderinsert", From gohman at apple.com Tue Jun 23 19:30:27 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 00:30:27 -0000 Subject: [llvm-commits] [llvm] r74032 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp Message-ID: <200906240030.n5O0URRC009724@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 23 19:30:26 2009 New Revision: 74032 URL: http://llvm.org/viewvc/llvm-project?rev=74032&view=rev Log: Add an isAllOnesValue utility function, similar to isZero and isOne. Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=74032&r1=74031&r2=74032&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Tue Jun 23 19:30:26 2009 @@ -82,6 +82,11 @@ /// bool isOne() const; + /// isAllOnesValue - Return true if the expression is a constant + /// all-ones value. + /// + bool isAllOnesValue() const; + /// replaceSymbolicValuesWithConcrete - If this SCEV internally references /// the symbolic value "Sym", construct and return a new SCEV that produces /// the same value, but which uses the concrete value Conc instead of the Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=74032&r1=74031&r2=74032&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Jun 23 19:30:26 2009 @@ -132,6 +132,12 @@ return false; } +bool SCEV::isAllOnesValue() const { + if (const SCEVConstant *SC = dyn_cast(this)) + return SC->getValue()->isAllOnesValue(); + return false; +} + SCEVCouldNotCompute::SCEVCouldNotCompute() : SCEV(scCouldNotCompute) {} From gohman at apple.com Tue Jun 23 19:33:17 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 00:33:17 -0000 Subject: [llvm-commits] [llvm] r74035 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <200906240033.n5O0XH3V009849@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 23 19:33:16 2009 New Revision: 74035 URL: http://llvm.org/viewvc/llvm-project?rev=74035&view=rev Log: Include the maximum trip count expression in ScalarEvolution's print output. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=74035&r1=74034&r2=74035&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Jun 23 19:33:16 2009 @@ -4340,6 +4340,15 @@ } OS << "\n"; + OS << "Loop " << L->getHeader()->getName() << ": "; + + if (!isa(SE->getMaxBackedgeTakenCount(L))) { + OS << "max backedge-taken count is " << *SE->getMaxBackedgeTakenCount(L); + } else { + OS << "Unpredictable max backedge-taken count. "; + } + + OS << "\n"; } void ScalarEvolution::print(raw_ostream &OS, const Module* ) const { From sabre at nondot.org Tue Jun 23 19:33:19 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 00:33:19 -0000 Subject: [llvm-commits] [llvm] r74036 - in /llvm/trunk/tools/llvm-mc: AsmLexer.cpp AsmLexer.h AsmParser.cpp Message-ID: <200906240033.n5O0XKmd009864@zion.cs.uiuc.edu> Author: lattner Date: Tue Jun 23 19:33:19 2009 New Revision: 74036 URL: http://llvm.org/viewvc/llvm-project?rev=74036&view=rev Log: make the lexer unique strings it lexes instead of passing them back as std::strings. Modified: llvm/trunk/tools/llvm-mc/AsmLexer.cpp llvm/trunk/tools/llvm-mc/AsmLexer.h llvm/trunk/tools/llvm-mc/AsmParser.cpp Modified: llvm/trunk/tools/llvm-mc/AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmLexer.cpp?rev=74036&r1=74035&r2=74036&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmLexer.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmLexer.cpp Tue Jun 23 19:33:19 2009 @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "AsmLexer.h" +#include "llvm/ADT/StringSet.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Config/config.h" // for strtoull. @@ -20,11 +21,21 @@ #include using namespace llvm; +static StringSet<> &getSS(void *TheSS) { + return *(StringSet<>*)TheSS; +} + AsmLexer::AsmLexer(SourceMgr &SM) : SrcMgr(SM) { CurBuffer = 0; CurBuf = SrcMgr.getMemoryBuffer(CurBuffer); CurPtr = CurBuf->getBufferStart(); TokStart = 0; + + TheStringSet = new StringSet<>(); +} + +AsmLexer::~AsmLexer() { + delete &getSS(TheStringSet); } SMLoc AsmLexer::getLoc() const { @@ -75,7 +86,9 @@ while (isalnum(*CurPtr) || *CurPtr == '_' || *CurPtr == '$' || *CurPtr == '.' || *CurPtr == '@') ++CurPtr; - CurStrVal.assign(TokStart, CurPtr); + // Unique string. + CurStrVal = + getSS(TheStringSet).GetOrCreateValue(TokStart, CurPtr, 0).getKeyData(); return asmtok::Identifier; } @@ -86,7 +99,10 @@ while (isalnum(*CurPtr)) ++CurPtr; - CurStrVal.assign(TokStart, CurPtr); // Include % + + // Unique string. + CurStrVal = + getSS(TheStringSet).GetOrCreateValue(TokStart, CurPtr, 0).getKeyData(); return asmtok::Register; } @@ -208,7 +224,9 @@ CurChar = getNextChar(); } - CurStrVal.assign(TokStart, CurPtr); // include quotes. + // Unique string, include quotes for now. + CurStrVal = + getSS(TheStringSet).GetOrCreateValue(TokStart, CurPtr, 0).getKeyData(); return asmtok::String; } Modified: llvm/trunk/tools/llvm-mc/AsmLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmLexer.h?rev=74036&r1=74035&r2=74036&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmLexer.h (original) +++ llvm/trunk/tools/llvm-mc/AsmLexer.h Tue Jun 23 19:33:19 2009 @@ -55,20 +55,24 @@ const char *CurPtr; const MemoryBuffer *CurBuf; + // A llvm::StringSet<>, which provides uniqued and null-terminated strings. + void *TheStringSet; // Information about the current token. const char *TokStart; asmtok::TokKind CurKind; - std::string CurStrVal; // This is valid for Identifier. + const char *CurStrVal; // This is valid for Identifier. int64_t CurIntVal; /// CurBuffer - This is the current buffer index we're lexing from as managed /// by the SourceMgr object. int CurBuffer; + void operator=(const AsmLexer&); // DO NOT IMPLEMENT + AsmLexer(const AsmLexer&); // DO NOT IMPLEMENT public: AsmLexer(SourceMgr &SrcMgr); - ~AsmLexer() {} + ~AsmLexer(); asmtok::TokKind Lex() { return CurKind = LexToken(); @@ -78,7 +82,7 @@ bool is(asmtok::TokKind K) const { return CurKind == K; } bool isNot(asmtok::TokKind K) const { return CurKind != K; } - const std::string &getCurStrVal() const { + const char *getCurStrVal() const { assert((CurKind == asmtok::Identifier || CurKind == asmtok::Register || CurKind == asmtok::String) && "This token doesn't have a string value"); Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=74036&r1=74035&r2=74036&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Tue Jun 23 19:33:19 2009 @@ -179,7 +179,7 @@ // If we have an identifier, handle it as the key symbol. SMLoc IDLoc = Lexer.getLoc(); - std::string IDVal = Lexer.getCurStrVal(); + const char *IDVal = Lexer.getCurStrVal(); // Consume the identifier, see what is after it. if (Lexer.Lex() == asmtok::Colon) { From gohman at apple.com Tue Jun 23 19:38:39 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 00:38:39 -0000 Subject: [llvm-commits] [llvm] r74037 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <200906240038.n5O0cdPM010027@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 23 19:38:39 2009 New Revision: 74037 URL: http://llvm.org/viewvc/llvm-project?rev=74037&view=rev Log: Use ScalarEvolution::getConstant instead of getUnknown to create SCEVConstants. This cleanup is a step toward letting getUnknown be simpler. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=74037&r1=74036&r2=74037&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Jun 23 19:38:39 2009 @@ -719,8 +719,8 @@ Ty = getEffectiveSCEVType(Ty); if (const SCEVConstant *SC = dyn_cast(Op)) - return getUnknown( - ConstantExpr::getTrunc(SC->getValue(), Ty)); + return getConstant( + cast(ConstantExpr::getTrunc(SC->getValue(), Ty))); // trunc(trunc(x)) --> trunc(x) if (const SCEVTruncateExpr *ST = dyn_cast(Op)) @@ -759,7 +759,7 @@ const Type *IntTy = getEffectiveSCEVType(Ty); Constant *C = ConstantExpr::getZExt(SC->getValue(), IntTy); if (IntTy != Ty) C = ConstantExpr::getIntToPtr(C, Ty); - return getUnknown(C); + return getConstant(cast(C)); } // zext(zext(x)) --> zext(x) @@ -847,7 +847,7 @@ const Type *IntTy = getEffectiveSCEVType(Ty); Constant *C = ConstantExpr::getSExt(SC->getValue(), IntTy); if (IntTy != Ty) C = ConstantExpr::getIntToPtr(C, Ty); - return getUnknown(C); + return getConstant(cast(C)); } // sext(sext(x)) --> sext(x) @@ -1617,7 +1617,8 @@ if (const SCEVConstant *LHSC = dyn_cast(LHS)) { Constant *LHSCV = LHSC->getValue(); Constant *RHSCV = RHSC->getValue(); - return getUnknown(ConstantExpr::getUDiv(LHSCV, RHSCV)); + return getConstant(cast(ConstantExpr::getUDiv(LHSCV, + RHSCV))); } } @@ -1966,7 +1967,7 @@ /// const SCEV* ScalarEvolution::getNegativeSCEV(const SCEV* V) { if (const SCEVConstant *VC = dyn_cast(V)) - return getUnknown(ConstantExpr::getNeg(VC->getValue())); + return getConstant(cast(ConstantExpr::getNeg(VC->getValue()))); const Type *Ty = V->getType(); Ty = getEffectiveSCEVType(Ty); @@ -1976,7 +1977,7 @@ /// getNotSCEV - Return a SCEV corresponding to ~V = -1-V const SCEV* ScalarEvolution::getNotSCEV(const SCEV* V) { if (const SCEVConstant *VC = dyn_cast(V)) - return getUnknown(ConstantExpr::getNot(VC->getValue())); + return getConstant(cast(ConstantExpr::getNot(VC->getValue()))); const Type *Ty = V->getType(); Ty = getEffectiveSCEVType(Ty); From sabre at nondot.org Tue Jun 23 19:51:35 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 00:51:35 -0000 Subject: [llvm-commits] [llvm] r74038 - /llvm/trunk/include/llvm/MC/MCStreamer.h Message-ID: <200906240051.n5O0pZGk010508@zion.cs.uiuc.edu> Author: lattner Date: Tue Jun 23 19:51:35 2009 New Revision: 74038 URL: http://llvm.org/viewvc/llvm-project?rev=74038&view=rev Log: stub out a trivial constructor method. Modified: llvm/trunk/include/llvm/MC/MCStreamer.h Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=74038&r1=74037&r2=74038&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Tue Jun 23 19:51:35 2009 @@ -116,7 +116,7 @@ /// createAsmStreamer - Create a machine code streamer which will print out /// assembly for the native target, suitable for compiling with a native /// assembler. - MCStreamer *createAsmStreamer(MCContext &Ctx, raw_ostream &OS); + inline MCStreamer *createAsmStreamer(MCContext &Ctx, raw_ostream &OS) { return 0; } // FIXME: These two may end up getting rolled into a single // createObjectStreamer interface, which implements the assembler backend, and From sabre at nondot.org Tue Jun 23 19:52:40 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 00:52:40 -0000 Subject: [llvm-commits] [llvm] r74039 - in /llvm/trunk/tools/llvm-mc: AsmParser.h CMakeLists.txt Makefile llvm-mc.cpp Message-ID: <200906240052.n5O0qe6M010552@zion.cs.uiuc.edu> Author: lattner Date: Tue Jun 23 19:52:40 2009 New Revision: 74039 URL: http://llvm.org/viewvc/llvm-project?rev=74039&view=rev Log: create an MCStreamer and provide it to AsmParser. Modified: llvm/trunk/tools/llvm-mc/AsmParser.h llvm/trunk/tools/llvm-mc/CMakeLists.txt llvm/trunk/tools/llvm-mc/Makefile llvm/trunk/tools/llvm-mc/llvm-mc.cpp Modified: llvm/trunk/tools/llvm-mc/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.h?rev=74039&r1=74038&r2=74039&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.h (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.h Tue Jun 23 19:52:40 2009 @@ -18,13 +18,16 @@ namespace llvm { class MCInst; +class MCStreamer; class AsmParser { AsmLexer Lexer; + MCStreamer &Out; + struct X86Operand; public: - AsmParser(SourceMgr &SM) : Lexer(SM) {} + AsmParser(SourceMgr &SM, MCStreamer &OutStr) : Lexer(SM), Out(OutStr) {} ~AsmParser() {} bool Run(); Modified: llvm/trunk/tools/llvm-mc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/CMakeLists.txt?rev=74039&r1=74038&r2=74039&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-mc/CMakeLists.txt Tue Jun 23 19:52:40 2009 @@ -1,4 +1,4 @@ -set(LLVM_LINK_COMPONENTS support) +set(LLVM_LINK_COMPONENTS support MC) add_llvm_tool(llvm-mc llvm-mc.cpp Modified: llvm/trunk/tools/llvm-mc/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/Makefile?rev=74039&r1=74038&r2=74039&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/Makefile (original) +++ llvm/trunk/tools/llvm-mc/Makefile Tue Jun 23 19:52:40 2009 @@ -9,7 +9,7 @@ LEVEL = ../.. TOOLNAME = llvm-mc -LINK_COMPONENTS := support +LINK_COMPONENTS := support MC # This tool has no plugins, optimize startup time. TOOL_NO_EXPORTS = 1 Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=74039&r1=74038&r2=74039&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Tue Jun 23 19:52:40 2009 @@ -12,6 +12,9 @@ // //===----------------------------------------------------------------------===// +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/ADT/OwningPtr.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/MemoryBuffer.h" @@ -136,7 +139,10 @@ // it later. SrcMgr.setIncludeDirs(IncludeDirs); - AsmParser Parser(SrcMgr); + // FIXME: don't leak streamer, own. + MCContext Ctx; + OwningPtr Str(createAsmStreamer(Ctx, outs())); + AsmParser Parser(SrcMgr, *Str.get()); return Parser.Run(); } From gohman at apple.com Tue Jun 23 19:54:58 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 00:54:58 -0000 Subject: [llvm-commits] [llvm] r74041 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Message-ID: <200906240054.n5O0swdp010645@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 23 19:54:57 2009 New Revision: 74041 URL: http://llvm.org/viewvc/llvm-project?rev=74041&view=rev Log: Move the special cases for constants out of getUnknown and into createSCEV. Also, recognize UndefValue in createSCEV. Change getIntegerSCEV's comment to avoid mentioning FP types, and re-implement it in terms of getConstant instead of getUnknown. Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h llvm/trunk/lib/Analysis/ScalarEvolution.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=74041&r1=74040&r2=74041&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Tue Jun 23 19:54:57 2009 @@ -462,7 +462,7 @@ /// widening. const SCEV* getTruncateOrNoop(const SCEV* V, const Type *Ty); - /// getIntegerSCEV - Given an integer or FP type, create a constant for the + /// getIntegerSCEV - Given a SCEVable type, create a constant for the /// specified signed integer value and return a SCEV for the constant. const SCEV* getIntegerSCEV(int Val, const Type *Ty); Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=74041&r1=74040&r2=74041&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Jun 23 19:54:57 2009 @@ -1867,10 +1867,11 @@ } const SCEV* ScalarEvolution::getUnknown(Value *V) { - if (ConstantInt *CI = dyn_cast(V)) - return getConstant(CI); - if (isa(V)) - return getIntegerSCEV(0, V->getType()); + // Don't attempt to do anything other than create a SCEVUnknown object + // here. createSCEV only calls getUnknown after checking for all other + // interesting possibilities, and any other code that calls getUnknown + // is doing so in order to hide a value from SCEV canonicalization. + SCEVUnknown *&Result = SCEVUnknowns[V]; if (Result == 0) Result = new SCEVUnknown(V); return Result; @@ -1948,19 +1949,11 @@ return S; } -/// getIntegerSCEV - Given an integer or FP type, create a constant for the +/// getIntegerSCEV - Given a SCEVable type, create a constant for the /// specified signed integer value and return a SCEV for the constant. const SCEV* ScalarEvolution::getIntegerSCEV(int Val, const Type *Ty) { - Ty = getEffectiveSCEVType(Ty); - Constant *C; - if (Val == 0) - C = Constant::getNullValue(Ty); - else if (Ty->isFloatingPoint()) - C = ConstantFP::get(APFloat(Ty==Type::FloatTy ? APFloat::IEEEsingle : - APFloat::IEEEdouble, Val)); - else - C = ConstantInt::get(Ty, Val); - return getUnknown(C); + const IntegerType *ITy = cast(getEffectiveSCEVType(Ty)); + return getConstant(ConstantInt::get(ITy, Val)); } /// getNegativeSCEV - Return a SCEV corresponding to -V = -1*V @@ -2429,6 +2422,12 @@ Opcode = I->getOpcode(); else if (ConstantExpr *CE = dyn_cast(V)) Opcode = CE->getOpcode(); + else if (ConstantInt *CI = dyn_cast(V)) + return getConstant(CI); + else if (isa(V)) + return getIntegerSCEV(0, V->getType()); + else if (isa(V)) + return getIntegerSCEV(0, V->getType()); else return getUnknown(V); Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=74041&r1=74040&r2=74041&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Tue Jun 23 19:54:57 2009 @@ -644,7 +644,7 @@ const MachineOperand &MO = MI->getOperand(Op); uint32_t v = ~MO.getImm(); int32_t lsb = ffs (v) - 1; - int32_t width = fls (v) - lsb; + int32_t width = ffs (v) - lsb; assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); O << "#" << lsb << ", #" << width; } From gohman at apple.com Tue Jun 23 19:55:55 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 00:55:55 -0000 Subject: [llvm-commits] [llvm] r74042 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Message-ID: <200906240055.n5O0ttBX010685@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 23 19:55:55 2009 New Revision: 74042 URL: http://llvm.org/viewvc/llvm-project?rev=74042&view=rev Log: Revert this accidental commit. Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=74042&r1=74041&r2=74042&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Tue Jun 23 19:55:55 2009 @@ -644,7 +644,7 @@ const MachineOperand &MO = MI->getOperand(Op); uint32_t v = ~MO.getImm(); int32_t lsb = ffs (v) - 1; - int32_t width = ffs (v) - lsb; + int32_t width = fls (v) - lsb; assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); O << "#" << lsb << ", #" << width; } From isanbard at gmail.com Tue Jun 23 19:55:48 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 23 Jun 2009 17:55:48 -0700 Subject: [llvm-commits] [llvm] r74038 - /llvm/trunk/include/llvm/MC/MCStreamer.h In-Reply-To: <200906240051.n5O0pZGk010508@zion.cs.uiuc.edu> References: <200906240051.n5O0pZGk010508@zion.cs.uiuc.edu> Message-ID: <9524349C-32B3-44E5-AAC2-335189CC182F@gmail.com> On Jun 23, 2009, at 5:51 PM, Chris Lattner wrote: > Author: lattner > Date: Tue Jun 23 19:51:35 2009 > New Revision: 74038 > > URL: http://llvm.org/viewvc/llvm-project?rev=74038&view=rev > Log: > stub out a trivial constructor method. > > Modified: > llvm/trunk/include/llvm/MC/MCStreamer.h > > Modified: llvm/trunk/include/llvm/MC/MCStreamer.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=74038&r1=74037&r2=74038&view=diff > > === > === > === > ===================================================================== > --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) > +++ llvm/trunk/include/llvm/MC/MCStreamer.h Tue Jun 23 19:51:35 2009 > @@ -116,7 +116,7 @@ > /// createAsmStreamer - Create a machine code streamer which will > print out > /// assembly for the native target, suitable for compiling with a > native > /// assembler. > - MCStreamer *createAsmStreamer(MCContext &Ctx, raw_ostream &OS); > + inline MCStreamer *createAsmStreamer(MCContext &Ctx, raw_ostream > &OS) { return 0; } > It's a good idea to omit parameter names if they aren't used. This prevents spurious warning in Release mode. :-) -bw > // FIXME: These two may end up getting rolled into a single > // createObjectStreamer interface, which implements the assembler > backend, and > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Tue Jun 23 19:57:19 2009 From: clattner at apple.com (Chris Lattner) Date: Tue, 23 Jun 2009 17:57:19 -0700 Subject: [llvm-commits] [llvm] r74038 - /llvm/trunk/include/llvm/MC/MCStreamer.h In-Reply-To: <9524349C-32B3-44E5-AAC2-335189CC182F@gmail.com> References: <200906240051.n5O0pZGk010508@zion.cs.uiuc.edu> <9524349C-32B3-44E5-AAC2-335189CC182F@gmail.com> Message-ID: <7D1CB24A-E48A-434E-AB24-55E7D44F8CDF@apple.com> >> native >> /// assembler. >> - MCStreamer *createAsmStreamer(MCContext &Ctx, raw_ostream &OS); >> + inline MCStreamer *createAsmStreamer(MCContext &Ctx, raw_ostream >> &OS) { return 0; } >> > It's a good idea to omit parameter names if they aren't used. This > prevents spurious warning in Release mode. :-) Daniel's about to commit an impl of this method. -Chris From daniel at zuster.org Tue Jun 23 20:03:07 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 24 Jun 2009 01:03:07 -0000 Subject: [llvm-commits] [llvm] r74044 - in /llvm/trunk: include/llvm/MC/MCAtom.h include/llvm/MC/MCContext.h include/llvm/MC/MCSection.h include/llvm/MC/MCStreamer.h include/llvm/MC/MCSymbol.h lib/MC/MCAsmStreamer.cpp lib/MC/MCContext.cpp lib/MC/MCStreamer.cpp unittests/MC/ unittests/MC/AsmStreamerTest.cpp unittests/MC/Makefile unittests/Makefile Message-ID: <200906240103.n5O137oI010947@zion.cs.uiuc.edu> Author: ddunbar Date: Tue Jun 23 20:03:06 2009 New Revision: 74044 URL: http://llvm.org/viewvc/llvm-project?rev=74044&view=rev Log: Start MCAsmStreamer implementation. Added: llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCStreamer.cpp llvm/trunk/unittests/MC/ (with props) llvm/trunk/unittests/MC/AsmStreamerTest.cpp llvm/trunk/unittests/MC/Makefile Modified: llvm/trunk/include/llvm/MC/MCAtom.h llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/include/llvm/MC/MCSection.h llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/include/llvm/MC/MCSymbol.h llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/unittests/Makefile Modified: llvm/trunk/include/llvm/MC/MCAtom.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAtom.h?rev=74044&r1=74043&r2=74044&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAtom.h (original) +++ llvm/trunk/include/llvm/MC/MCAtom.h Tue Jun 23 20:03:06 2009 @@ -17,6 +17,8 @@ public: MCAtom(MCSection *_Section) : Section(_Section) {} + + MCSection *getSection() { return Section; } }; } // end namespace llvm Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=74044&r1=74043&r2=74044&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Tue Jun 23 20:03:06 2009 @@ -113,7 +113,7 @@ /// allocator supports it). /// @return The allocated memory. Could be NULL. inline void *operator new(size_t Bytes, llvm::MCContext &C, - size_t Alignment) throw () { + size_t Alignment = 16) throw () { return C.Allocate(Bytes, Alignment); } /// @brief Placement delete companion to the new above. Modified: llvm/trunk/include/llvm/MC/MCSection.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSection.h?rev=74044&r1=74043&r2=74044&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSection.h (original) +++ llvm/trunk/include/llvm/MC/MCSection.h Tue Jun 23 20:03:06 2009 @@ -19,6 +19,8 @@ public: MCSection(const char *_Name) : Name(_Name) {} + + const std::string &getName() const { return Name; } }; } // end namespace llvm Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=74044&r1=74043&r2=74044&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Tue Jun 23 20:03:06 2009 @@ -84,7 +84,7 @@ // the symbol and make the printer smart enough to add the right symbols? // This should work as long as the order of attributes in the file doesn't // matter. - virtual void EmitSymbolAttribute(MCSymbol *Symbol, + virtual void EmitSymbolAttribute(MCSymbol *Symbol, SymbolAttr Attribute) = 0; /// EmitBytes - Emit @param Length bytes starting at @param Data into the @@ -116,7 +116,7 @@ /// createAsmStreamer - Create a machine code streamer which will print out /// assembly for the native target, suitable for compiling with a native /// assembler. - inline MCStreamer *createAsmStreamer(MCContext &Ctx, raw_ostream &OS) { return 0; } + MCStreamer *createAsmStreamer(MCContext &Ctx, raw_ostream &OS); // FIXME: These two may end up getting rolled into a single // createObjectStreamer interface, which implements the assembler backend, and Modified: llvm/trunk/include/llvm/MC/MCSymbol.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSymbol.h?rev=74044&r1=74043&r2=74044&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSymbol.h (original) +++ llvm/trunk/include/llvm/MC/MCSymbol.h Tue Jun 23 20:03:06 2009 @@ -23,6 +23,10 @@ public: MCSymbol(MCAtom *_Atom, const char *_Name, bool _IsTemporary) : Atom(_Atom), Name(_Name), IsTemporary(_IsTemporary) {} + + MCAtom *getAtom() { return Atom; } + + const std::string &getName() { return Name; } }; } // end namespace llvm Added: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=74044&view=auto ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (added) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Tue Jun 23 20:03:06 2009 @@ -0,0 +1,143 @@ +//===- lib/MC/MCAsmStreamer.cpp - Text Assembly Output --------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCStreamer.h" + +#include "llvm/MC/MCAtom.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCSection.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCValue.h" +#include "llvm/Support/raw_ostream.h" +using namespace llvm; + +namespace { + + class MCAsmStreamer : public MCStreamer { + raw_ostream &OS; + + MCSection *CurSection; + + public: + MCAsmStreamer(MCContext &Context, raw_ostream &_OS) + : MCStreamer(Context), OS(_OS) {} + ~MCAsmStreamer() {} + + /// @name MCStreamer Interface + /// @{ + + virtual void SwitchSection(MCSection *Section); + + virtual void EmitLabel(MCSymbol *Symbol); + + virtual void EmitAssignment(MCSymbol *Symbol, const MCValue &Value, + bool MakeAbsolute = false); + + virtual void EmitSymbolAttribute(MCSymbol *Symbol, SymbolAttr Attribute); + + virtual void EmitBytes(const char *Data, unsigned Length); + + virtual void EmitValue(const MCValue &Value, unsigned Size); + + virtual void EmitInstruction(const MCInst &Inst); + + virtual void Finish(); + + /// @} + }; + +} + +/// Allow printing values directly to a raw_ostream. +inline raw_ostream &operator<<(raw_ostream &os, const MCValue &Value) { + if (Value.getSymA()) { + os << Value.getSymA()->getName(); + if (Value.getSymB()) + os << " - " << Value.getSymB()->getName(); + if (Value.getCst()) + os << " + " << Value.getCst(); + } else { + assert(!Value.getSymB() && "Invalid machine code value!"); + os << Value.getCst(); + } + + return os; +} + +void MCAsmStreamer::SwitchSection(MCSection *Section) { + if (Section != CurSection) { + CurSection = Section; + + // FIXME: Really we would like the segment, flags, etc. to be separate + // values instead of embedded in the name. Not all assemblers understand all + // this stuff though. + OS << ".section " << Section->getName() << "\n"; + } +} + +void MCAsmStreamer::EmitLabel(MCSymbol *Symbol) { + // FIXME: We need to enforce that we aren't printing atoms which are more + // complicated than the assembler understands. + assert(Symbol->getAtom()->getSection() == CurSection && + "The label for a symbol must match its section!"); + OS << Symbol->getName() << ":\n"; +} + +void MCAsmStreamer::EmitAssignment(MCSymbol *Symbol, const MCValue &Value, + bool MakeAbsolute) { + if (MakeAbsolute) { + OS << ".set " << Symbol->getName() << ", " << Value << '\n'; + } else { + OS << Symbol->getName() << " = " << Value << '\n'; + } +} + +void MCAsmStreamer::EmitSymbolAttribute(MCSymbol *Symbol, + SymbolAttr Attribute) { + switch (Attribute) { + case Global: OS << ".globl"; break; + case Weak: OS << ".weak"; break; + case PrivateExtern: OS << ".private_extern"; break; + } + + OS << ' ' << Symbol->getName() << '\n'; +} + +void MCAsmStreamer::EmitBytes(const char *Data, unsigned Length) { + for (unsigned i = 0; i != Length; ++i) { + OS << ".byte " << (unsigned) Data[i] << '\n'; + } +} + +void MCAsmStreamer::EmitValue(const MCValue &Value, unsigned Size) { + // Need target hooks to know how to print this. + switch (Size) { + default: + assert(0 && "Invalid size for machine code value!"); + case 1: OS << ".byte"; break; + case 2: OS << ".hword"; break; + case 4: OS << ".long"; break; + case 8: OS << ".quad"; break; + } + + OS << ' ' << Value << '\n'; +} + +void MCAsmStreamer::EmitInstruction(const MCInst &Inst) { + // FIXME: Implement. + OS << "# FIXME: Implement instruction printing!\n"; +} + +void MCAsmStreamer::Finish() { + OS.flush(); +} + +MCStreamer *llvm::createAsmStreamer(MCContext &Context, raw_ostream &OS) { + return new MCAsmStreamer(Context, OS); +} Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=74044&r1=74043&r2=74044&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Tue Jun 23 20:03:06 2009 @@ -26,13 +26,13 @@ MCSection *&Entry = Sections[Name]; if (!Entry) - Entry = new (this) MCSection(Name); + Entry = new (*this) MCSection(Name); return Entry; } MCAtom *MCContext::CreateAtom(MCSection *Section) { - return new (this) MCAtom(Section); + return new (*this) MCAtom(Section); } MCSymbol *MCContext::CreateSymbol(MCAtom *Atom, const char *Name) { @@ -41,18 +41,18 @@ // Create and bind the symbol, and ensure that names are unique. MCSymbol *&Entry = Symbols[Name]; assert(!Entry && "Duplicate symbol definition!"); - return Entry = new (this) MCSymbol(Atom, Name, false); + return Entry = new (*this) MCSymbol(Atom, Name, false); } MCSymbol *MCContext::CreateTemporarySymbol(MCAtom *Atom, const char *Name) { // If unnamed, just create a symbol. if (Name[0] == '\0') - new (this) MCSymbol(Atom, "", true); + new (*this) MCSymbol(Atom, "", true); // Otherwise create as usual. MCSymbol *&Entry = Symbols[Name]; assert(!Entry && "Duplicate symbol definition!"); - return Entry = new (this) MCSymbol(Atom, Name, true); + return Entry = new (*this) MCSymbol(Atom, Name, true); } MCSymbol *MCContext::LookupSymbol(const char *Name) const { Added: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=74044&view=auto ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (added) +++ llvm/trunk/lib/MC/MCStreamer.cpp Tue Jun 23 20:03:06 2009 @@ -0,0 +1,18 @@ +//===- lib/MC/MCStreamer.cpp - Streaming Machine Code Output --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCStreamer.h" + +using namespace llvm; + +MCStreamer::MCStreamer(MCContext &_Context) : Context(_Context) { +} + +MCStreamer::~MCStreamer() { +} Propchange: llvm/trunk/unittests/MC/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Tue Jun 23 20:03:06 2009 @@ -0,0 +1 @@ +Debug Added: llvm/trunk/unittests/MC/AsmStreamerTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/MC/AsmStreamerTest.cpp?rev=74044&view=auto ============================================================================== --- llvm/trunk/unittests/MC/AsmStreamerTest.cpp (added) +++ llvm/trunk/unittests/MC/AsmStreamerTest.cpp Tue Jun 23 20:03:06 2009 @@ -0,0 +1,52 @@ +//===- AsmStreamerTest.cpp - Triple unit tests ----------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "gtest/gtest.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/Support/raw_ostream.h" +using namespace llvm; + +namespace { + +// Helper class. +class StringAsmStreamer { + std::string Str; + raw_string_ostream OS; + MCContext Context; + MCStreamer *Streamer; + +public: + StringAsmStreamer() : OS(Str), Streamer(createAsmStreamer(Context, OS)) {} + ~StringAsmStreamer() { + delete Streamer; + } + + MCContext &getContext() { return Context; } + MCStreamer &getStreamer() { return *Streamer; } + + const std::string &getString() { + Streamer->Finish(); + return Str; + } +}; + +TEST(AsmStreamer, EmptyOutput) { + StringAsmStreamer S; + EXPECT_EQ(S.getString(), ""); +} + +TEST(AsmStreamer, Sections) { + StringAsmStreamer S; + MCSection *Sec0 = S.getContext().GetSection("foo"); + S.getStreamer().SwitchSection(Sec0); + EXPECT_EQ(S.getString(), ".section foo\n"); +} + +} Added: llvm/trunk/unittests/MC/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/MC/Makefile?rev=74044&view=auto ============================================================================== --- llvm/trunk/unittests/MC/Makefile (added) +++ llvm/trunk/unittests/MC/Makefile Tue Jun 23 20:03:06 2009 @@ -0,0 +1,15 @@ +##===- unittests/MC/Makefile -------------------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../.. +TESTNAME = MC +LINK_COMPONENTS := core support mc + +include $(LEVEL)/Makefile.config +include $(LLVM_SRC_ROOT)/unittests/Makefile.unittest Modified: llvm/trunk/unittests/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Makefile?rev=74044&r1=74043&r2=74044&view=diff ============================================================================== --- llvm/trunk/unittests/Makefile (original) +++ llvm/trunk/unittests/Makefile Tue Jun 23 20:03:06 2009 @@ -16,7 +16,7 @@ CPP.Flags += -I$(LLVM_SRC_ROOT)/utils/unittest/googletest/include/ CPP.Flags += -Wno-variadic-macros -PARALLEL_DIRS = ADT Support VMCore +PARALLEL_DIRS = ADT Support VMCore MC include $(LEVEL)/Makefile.common From gohman at apple.com Tue Jun 23 20:05:09 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 01:05:09 -0000 Subject: [llvm-commits] [llvm] r74045 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <200906240105.n5O15Aq4011020@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 23 20:05:09 2009 New Revision: 74045 URL: http://llvm.org/viewvc/llvm-project?rev=74045&view=rev Log: Teach GetMinSignBits about SCEVAddExprs. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=74045&r1=74044&r2=74045&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Jun 23 20:05:09 2009 @@ -2402,6 +2402,38 @@ getTypeSizeInBits(C->getOperand()->getType())); } + if (const SCEVAddExpr *A = dyn_cast(S)) { + unsigned BitWidth = getTypeSizeInBits(A->getType()); + + // Special case decrementing a value (ADD X, -1): + if (const SCEVConstant *CRHS = dyn_cast(A->getOperand(0))) + if (CRHS->isAllOnesValue()) { + SmallVector OtherOps(A->op_begin() + 1, A->op_end()); + const SCEV *OtherOpsAdd = getAddExpr(OtherOps); + unsigned LZ = GetMinLeadingZeros(OtherOpsAdd); + + // If the input is known to be 0 or 1, the output is 0/-1, which is all + // sign bits set. + if (LZ == BitWidth - 1) + return BitWidth; + + // If we are subtracting one from a positive number, there is no carry + // out of the result. + if (LZ > 0) + return GetMinSignBits(OtherOpsAdd); + } + + // Add can have at most one carry bit. Thus we know that the output + // is, at worst, one more bit than the inputs. + unsigned Min = BitWidth; + for (unsigned i = 0, e = A->getNumOperands(); i != e; ++i) { + unsigned N = GetMinSignBits(A->getOperand(i)); + Min = std::min(Min, N) - 1; + if (Min == 0) return 1; + } + return 1; + } + if (const SCEVUnknown *U = dyn_cast(S)) { // For a SCEVUnknown, ask ValueTracking. return ComputeNumSignBits(U->getValue(), TD); From nicholas at mxc.ca Tue Jun 23 20:08:42 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 24 Jun 2009 01:08:42 -0000 Subject: [llvm-commits] [llvm] r74046 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Message-ID: <200906240108.n5O18giv011146@zion.cs.uiuc.edu> Author: nicholas Date: Tue Jun 23 20:08:42 2009 New Revision: 74046 URL: http://llvm.org/viewvc/llvm-project?rev=74046&view=rev Log: Unbreak build on Linux by removing Darwinism. Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=74046&r1=74045&r2=74046&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Tue Jun 23 20:08:42 2009 @@ -644,7 +644,7 @@ const MachineOperand &MO = MI->getOperand(Op); uint32_t v = ~MO.getImm(); int32_t lsb = ffs (v) - 1; - int32_t width = fls (v) - lsb; + int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb; assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); O << "#" << lsb << ", #" << width; } From gohman at apple.com Tue Jun 23 20:18:18 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 01:18:18 -0000 Subject: [llvm-commits] [llvm] r74048 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp lib/Analysis/ScalarEvolutionExpander.cpp lib/Transforms/Scalar/IndVarSimplify.cpp lib/Transforms/Scalar/LoopStrengthReduce.cpp test/CodeGen/X86/pr3495.ll Message-ID: <200906240118.n5O1IIMT011483@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 23 20:18:18 2009 New Revision: 74048 URL: http://llvm.org/viewvc/llvm-project?rev=74048&view=rev Log: Extend ScalarEvolution's multiple-exit support to compute exact trip counts in more cases. Generalize ScalarEvolution's isLoopGuardedByCond code to recognize And and Or conditions, splitting the code out into an isNecessaryCond helper function so that it can evaluate Ands and Ors recursively, and make SCEVExpander be much more aggressive about hoisting instructions out of loops. test/CodeGen/X86/pr3495.ll has an additional instruction now, but it appears to be due to an arbitrary register allocation difference. Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h llvm/trunk/lib/Analysis/ScalarEvolution.cpp llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp llvm/trunk/test/CodeGen/X86/pr3495.ll Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=74048&r1=74047&r2=74048&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Tue Jun 23 20:18:18 2009 @@ -334,6 +334,12 @@ /// found. BasicBlock* getPredecessorWithUniqueSuccessorForBB(BasicBlock *BB); + /// isNecessaryCond - Test whether the given CondValue value is a condition + /// which is at least as strict as the one described by Pred, LHS, and RHS. + bool isNecessaryCond(Value *Cond, ICmpInst::Predicate Pred, + const SCEV *LHS, const SCEV *RHS, + bool Inverse); + /// getConstantEvolutionLoopExitValue - If we know that the specified Phi is /// in the header of its containing loop, we know the loop executes a /// constant number of times, and the PHI node is just a recurrence Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=74048&r1=74047&r2=74048&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Jun 23 20:18:18 2009 @@ -2813,7 +2813,6 @@ const SCEV* BECount = CouldNotCompute; const SCEV* MaxBECount = CouldNotCompute; bool CouldNotComputeBECount = false; - bool CouldNotComputeMaxBECount = false; for (unsigned i = 0, e = ExitingBlocks.size(); i != e; ++i) { BackedgeTakenInfo NewBTI = ComputeBackedgeTakenCountFromExit(L, ExitingBlocks[i]); @@ -2826,25 +2825,13 @@ } else if (!CouldNotComputeBECount) { if (BECount == CouldNotCompute) BECount = NewBTI.Exact; - else { - // TODO: More analysis could be done here. For example, a - // loop with a short-circuiting && operator has an exact count - // of the min of both sides. - CouldNotComputeBECount = true; - BECount = CouldNotCompute; - } - } - if (NewBTI.Max == CouldNotCompute) { - // We couldn't compute an maximum value for this exit, so - // we won't be able to compute an maximum value for the loop. - CouldNotComputeMaxBECount = true; - MaxBECount = CouldNotCompute; - } else if (!CouldNotComputeMaxBECount) { - if (MaxBECount == CouldNotCompute) - MaxBECount = NewBTI.Max; else - MaxBECount = getUMaxFromMismatchedTypes(MaxBECount, NewBTI.Max); + BECount = getUMinFromMismatchedTypes(BECount, NewBTI.Exact); } + if (MaxBECount == CouldNotCompute) + MaxBECount = NewBTI.Max; + else if (NewBTI.Max != CouldNotCompute) + MaxBECount = getUMinFromMismatchedTypes(MaxBECount, NewBTI.Max); } return BackedgeTakenInfo(BECount, MaxBECount); @@ -2925,9 +2912,7 @@ Value *ExitCond, BasicBlock *TBB, BasicBlock *FBB) { - // Check if the controlling expression for this loop is an and or or. In - // such cases, an exact backedge-taken count may be infeasible, but a - // maximum count may still be feasible. + // Check if the controlling expression for this loop is an And or Or. if (BinaryOperator *BO = dyn_cast(ExitCond)) { if (BO->getOpcode() == Instruction::And) { // Recurse on the operands of the and. @@ -3899,88 +3884,111 @@ LoopEntryPredicate->isUnconditional()) continue; - ICmpInst *ICI = dyn_cast(LoopEntryPredicate->getCondition()); - if (!ICI) continue; + if (isNecessaryCond(LoopEntryPredicate->getCondition(), Pred, LHS, RHS, + LoopEntryPredicate->getSuccessor(0) != PredecessorDest)) + return true; + } - // Now that we found a conditional branch that dominates the loop, check to - // see if it is the comparison we are looking for. - Value *PreCondLHS = ICI->getOperand(0); - Value *PreCondRHS = ICI->getOperand(1); - ICmpInst::Predicate Cond; - if (LoopEntryPredicate->getSuccessor(0) == PredecessorDest) - Cond = ICI->getPredicate(); - else - Cond = ICI->getInversePredicate(); + return false; +} - if (Cond == Pred) - ; // An exact match. - else if (!ICmpInst::isTrueWhenEqual(Cond) && Pred == ICmpInst::ICMP_NE) - ; // The actual condition is beyond sufficient. - else - // Check a few special cases. - switch (Cond) { - case ICmpInst::ICMP_UGT: - if (Pred == ICmpInst::ICMP_ULT) { - std::swap(PreCondLHS, PreCondRHS); - Cond = ICmpInst::ICMP_ULT; - break; - } - continue; - case ICmpInst::ICMP_SGT: - if (Pred == ICmpInst::ICMP_SLT) { - std::swap(PreCondLHS, PreCondRHS); - Cond = ICmpInst::ICMP_SLT; - break; - } - continue; - case ICmpInst::ICMP_NE: - // Expressions like (x >u 0) are often canonicalized to (x != 0), - // so check for this case by checking if the NE is comparing against - // a minimum or maximum constant. - if (!ICmpInst::isTrueWhenEqual(Pred)) - if (ConstantInt *CI = dyn_cast(PreCondRHS)) { - const APInt &A = CI->getValue(); - switch (Pred) { - case ICmpInst::ICMP_SLT: - if (A.isMaxSignedValue()) break; - continue; - case ICmpInst::ICMP_SGT: - if (A.isMinSignedValue()) break; - continue; - case ICmpInst::ICMP_ULT: - if (A.isMaxValue()) break; - continue; - case ICmpInst::ICMP_UGT: - if (A.isMinValue()) break; - continue; - default: - continue; - } - Cond = ICmpInst::ICMP_NE; - // NE is symmetric but the original comparison may not be. Swap - // the operands if necessary so that they match below. - if (isa(LHS)) - std::swap(PreCondLHS, PreCondRHS); - break; - } - continue; - default: - // We weren't able to reconcile the condition. - continue; - } +/// isNecessaryCond - Test whether the given CondValue value is a condition +/// which is at least as strict as the one described by Pred, LHS, and RHS. +bool ScalarEvolution::isNecessaryCond(Value *CondValue, + ICmpInst::Predicate Pred, + const SCEV *LHS, const SCEV *RHS, + bool Inverse) { + // Recursivly handle And and Or conditions. + if (BinaryOperator *BO = dyn_cast(CondValue)) { + if (BO->getOpcode() == Instruction::And) { + if (!Inverse) + return isNecessaryCond(BO->getOperand(0), Pred, LHS, RHS, Inverse) || + isNecessaryCond(BO->getOperand(1), Pred, LHS, RHS, Inverse); + } else if (BO->getOpcode() == Instruction::Or) { + if (Inverse) + return isNecessaryCond(BO->getOperand(0), Pred, LHS, RHS, Inverse) || + isNecessaryCond(BO->getOperand(1), Pred, LHS, RHS, Inverse); + } + } - if (!PreCondLHS->getType()->isInteger()) continue; + ICmpInst *ICI = dyn_cast(CondValue); + if (!ICI) return false; + + // Now that we found a conditional branch that dominates the loop, check to + // see if it is the comparison we are looking for. + Value *PreCondLHS = ICI->getOperand(0); + Value *PreCondRHS = ICI->getOperand(1); + ICmpInst::Predicate Cond; + if (Inverse) + Cond = ICI->getInversePredicate(); + else + Cond = ICI->getPredicate(); - const SCEV* PreCondLHSSCEV = getSCEV(PreCondLHS); - const SCEV* PreCondRHSSCEV = getSCEV(PreCondRHS); - if ((HasSameValue(LHS, PreCondLHSSCEV) && - HasSameValue(RHS, PreCondRHSSCEV)) || - (HasSameValue(LHS, getNotSCEV(PreCondRHSSCEV)) && - HasSameValue(RHS, getNotSCEV(PreCondLHSSCEV)))) - return true; - } + if (Cond == Pred) + ; // An exact match. + else if (!ICmpInst::isTrueWhenEqual(Cond) && Pred == ICmpInst::ICMP_NE) + ; // The actual condition is beyond sufficient. + else + // Check a few special cases. + switch (Cond) { + case ICmpInst::ICMP_UGT: + if (Pred == ICmpInst::ICMP_ULT) { + std::swap(PreCondLHS, PreCondRHS); + Cond = ICmpInst::ICMP_ULT; + break; + } + return false; + case ICmpInst::ICMP_SGT: + if (Pred == ICmpInst::ICMP_SLT) { + std::swap(PreCondLHS, PreCondRHS); + Cond = ICmpInst::ICMP_SLT; + break; + } + return false; + case ICmpInst::ICMP_NE: + // Expressions like (x >u 0) are often canonicalized to (x != 0), + // so check for this case by checking if the NE is comparing against + // a minimum or maximum constant. + if (!ICmpInst::isTrueWhenEqual(Pred)) + if (ConstantInt *CI = dyn_cast(PreCondRHS)) { + const APInt &A = CI->getValue(); + switch (Pred) { + case ICmpInst::ICMP_SLT: + if (A.isMaxSignedValue()) break; + return false; + case ICmpInst::ICMP_SGT: + if (A.isMinSignedValue()) break; + return false; + case ICmpInst::ICMP_ULT: + if (A.isMaxValue()) break; + return false; + case ICmpInst::ICMP_UGT: + if (A.isMinValue()) break; + return false; + default: + return false; + } + Cond = ICmpInst::ICMP_NE; + // NE is symmetric but the original comparison may not be. Swap + // the operands if necessary so that they match below. + if (isa(LHS)) + std::swap(PreCondLHS, PreCondRHS); + break; + } + return false; + default: + // We weren't able to reconcile the condition. + return false; + } - return false; + if (!PreCondLHS->getType()->isInteger()) return false; + + const SCEV *PreCondLHSSCEV = getSCEV(PreCondLHS); + const SCEV *PreCondRHSSCEV = getSCEV(PreCondRHS); + return (HasSameValue(LHS, PreCondLHSSCEV) && + HasSameValue(RHS, PreCondRHSSCEV)) || + (HasSameValue(LHS, getNotSCEV(PreCondRHSSCEV)) && + HasSameValue(RHS, getNotSCEV(PreCondLHSSCEV))); } /// getBECount - Subtract the end and start values and divide by the step, Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=74048&r1=74047&r2=74048&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Tue Jun 23 20:18:18 2009 @@ -51,21 +51,26 @@ if (Argument *A = dyn_cast(V)) { // Check to see if there is already a cast! for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); - UI != E; ++UI) { + UI != E; ++UI) if ((*UI)->getType() == Ty) if (CastInst *CI = dyn_cast(cast(*UI))) if (CI->getOpcode() == opcode) { // If the cast isn't the first instruction of the function, move it. - if (BasicBlock::iterator(CI) != + if (BasicBlock::iterator(CI) != A->getParent()->getEntryBlock().begin()) { - // If the CastInst is the insert point, change the insert point. - if (CI == InsertPt) ++InsertPt; - // Splice the cast at the beginning of the entry block. - CI->moveBefore(A->getParent()->getEntryBlock().begin()); + // Recreate the cast at the beginning of the entry block. + // The old cast is left in place in case it is being used + // as an insert point. + Instruction *NewCI = + CastInst::Create(opcode, V, Ty, "", + A->getParent()->getEntryBlock().begin()); + NewCI->takeName(CI); + CI->replaceAllUsesWith(NewCI); + return NewCI; } return CI; } - } + Instruction *I = CastInst::Create(opcode, V, Ty, V->getName(), A->getParent()->getEntryBlock().begin()); InsertedValues.insert(I); @@ -85,10 +90,13 @@ It = cast(I)->getNormalDest()->begin(); while (isa(It)) ++It; if (It != BasicBlock::iterator(CI)) { - // If the CastInst is the insert point, change the insert point. - if (CI == InsertPt) ++InsertPt; - // Splice the cast immediately after the operand in question. - CI->moveBefore(It); + // Recreate the cast at the beginning of the entry block. + // The old cast is left in place in case it is being used + // as an insert point. + Instruction *NewCI = CastInst::Create(opcode, V, Ty, "", It); + NewCI->takeName(CI); + CI->replaceAllUsesWith(NewCI); + return NewCI; } return CI; } @@ -497,8 +505,9 @@ } } - Value *RestV = expand(Rest); - return expand(SE.getAddExpr(S->getStart(), SE.getUnknown(RestV))); + // Just do a normal add. Pre-expand the operands to suppress folding. + return expand(SE.getAddExpr(SE.getUnknown(expand(S->getStart())), + SE.getUnknown(expand(Rest)))); } // {0,+,1} --> Insert a canonical induction variable into the loop! @@ -546,36 +555,13 @@ getOrInsertCanonicalInductionVariable(L, Ty); // If this is a simple linear addrec, emit it now as a special case. - if (S->isAffine()) { // {0,+,F} --> i*F - Value *F = expandCodeFor(S->getOperand(1), Ty); - - // If the insert point is directly inside of the loop, emit the multiply at - // the insert point. Otherwise, L is a loop that is a parent of the insert - // point loop. If we can, move the multiply to the outer most loop that it - // is safe to be in. - BasicBlock::iterator MulInsertPt = getInsertionPoint(); - Loop *InsertPtLoop = SE.LI->getLoopFor(MulInsertPt->getParent()); - if (InsertPtLoop != L && InsertPtLoop && - L->contains(InsertPtLoop->getHeader())) { - do { - // If we cannot hoist the multiply out of this loop, don't. - if (!InsertPtLoop->isLoopInvariant(F)) break; - - BasicBlock *InsertPtLoopPH = InsertPtLoop->getLoopPreheader(); - - // If this loop hasn't got a preheader, we aren't able to hoist the - // multiply. - if (!InsertPtLoopPH) - break; - - // Otherwise, move the insert point to the preheader. - MulInsertPt = InsertPtLoopPH->getTerminator(); - InsertPtLoop = InsertPtLoop->getParentLoop(); - } while (InsertPtLoop != L); - } - - return InsertBinop(Instruction::Mul, I, F, MulInsertPt); - } + if (S->isAffine()) // {0,+,F} --> i*F + return + expand(SE.getTruncateOrNoop( + SE.getMulExpr(SE.getUnknown(I), + SE.getNoopOrAnyExtend(S->getOperand(1), + I->getType())), + Ty)); // If this is a chain of recurrences, turn it into a closed form, using the // folders, then expandCodeFor the closed form. This allows the folders to @@ -671,8 +657,31 @@ InsertedExpressions.find(S); if (I != InsertedExpressions.end()) return I->second; - + + // Compute an insertion point for this SCEV object. Hoist the instructions + // as far out in the loop nest as possible. + BasicBlock::iterator InsertPt = getInsertionPoint(); + BasicBlock::iterator SaveInsertPt = InsertPt; + for (Loop *L = SE.LI->getLoopFor(InsertPt->getParent()); ; + L = L->getParentLoop()) + if (S->isLoopInvariant(L)) { + if (!L) break; + if (BasicBlock *Preheader = L->getLoopPreheader()) + InsertPt = Preheader->getTerminator(); + } else { + // If the SCEV is computable at this level, insert it into the header + // after the PHIs (and after any other instructions that we've inserted + // there) so that it is guaranteed to dominate any user inside the loop. + if (L && S->hasComputableLoopEvolution(L)) + InsertPt = L->getHeader()->getFirstNonPHI(); + while (isInsertedInstruction(InsertPt)) ++InsertPt; + break; + } + setInsertionPoint(InsertPt); + Value *V = visit(S); + + setInsertionPoint(SaveInsertPt); InsertedExpressions[S] = V; return V; } @@ -686,6 +695,9 @@ const Type *Ty) { assert(Ty->isInteger() && "Can only insert integer induction variables!"); const SCEV* H = SE.getAddRecExpr(SE.getIntegerSCEV(0, Ty), - SE.getIntegerSCEV(1, Ty), L); - return expand(H); + SE.getIntegerSCEV(1, Ty), L); + BasicBlock::iterator SaveInsertPt = getInsertionPoint(); + Value *V = expandCodeFor(H, 0, L->getHeader()->begin()); + setInsertionPoint(SaveInsertPt); + return V; } Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=74048&r1=74047&r2=74048&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Jun 23 20:18:18 2009 @@ -104,7 +104,8 @@ void RewriteLoopExitValues(Loop *L, const SCEV *BackedgeTakenCount); void RewriteIVExpressions(Loop *L, const Type *LargestType, - SCEVExpander &Rewriter); + SCEVExpander &Rewriter, + BasicBlock::iterator InsertPt); void SinkUnusedInvariants(Loop *L, SCEVExpander &Rewriter); @@ -170,6 +171,8 @@ } // Expand the code for the iteration count into the preheader of the loop. + assert(RHS->isLoopInvariant(L) && + "Computed iteration count is not loop invariant!"); BasicBlock *Preheader = L->getLoopPreheader(); Value *ExitCnt = Rewriter.expandCodeFor(RHS, IndVar->getType(), Preheader->getTerminator()); @@ -434,10 +437,10 @@ ExitingBlock, BI, Rewriter); } - Rewriter.setInsertionPoint(Header->getFirstNonPHI()); + BasicBlock::iterator InsertPt = Header->getFirstNonPHI(); // Rewrite IV-derived expressions. Clears the rewriter cache. - RewriteIVExpressions(L, LargestType, Rewriter); + RewriteIVExpressions(L, LargestType, Rewriter, InsertPt); // The Rewriter may only be used for isInsertedInstruction queries from this // point on. @@ -462,7 +465,8 @@ } void IndVarSimplify::RewriteIVExpressions(Loop *L, const Type *LargestType, - SCEVExpander &Rewriter) { + SCEVExpander &Rewriter, + BasicBlock::iterator InsertPt) { SmallVector DeadInsts; // Rewrite all induction variable expressions in terms of the canonical @@ -488,29 +492,17 @@ // Compute the final addrec to expand into code. const SCEV* AR = IU->getReplacementExpr(*UI); - Value *NewVal = 0; - if (AR->isLoopInvariant(L)) { - BasicBlock::iterator I = Rewriter.getInsertionPoint(); - // Expand loop-invariant values in the loop preheader. They will - // be sunk to the exit block later, if possible. - NewVal = - Rewriter.expandCodeFor(AR, UseTy, - L->getLoopPreheader()->getTerminator()); - Rewriter.setInsertionPoint(I); - ++NumReplaced; - } else { - // FIXME: It is an extremely bad idea to indvar substitute anything more - // complex than affine induction variables. Doing so will put expensive - // polynomial evaluations inside of the loop, and the str reduction pass - // currently can only reduce affine polynomials. For now just disable - // indvar subst on anything more complex than an affine addrec, unless - // it can be expanded to a trivial value. - if (!Stride->isLoopInvariant(L)) - continue; + // FIXME: It is an extremely bad idea to indvar substitute anything more + // complex than affine induction variables. Doing so will put expensive + // polynomial evaluations inside of the loop, and the str reduction pass + // currently can only reduce affine polynomials. For now just disable + // indvar subst on anything more complex than an affine addrec, unless + // it can be expanded to a trivial value. + if (!AR->isLoopInvariant(L) && !Stride->isLoopInvariant(L)) + continue; - // Now expand it into actual Instructions and patch it into place. - NewVal = Rewriter.expandCodeFor(AR, UseTy); - } + // Now expand it into actual Instructions and patch it into place. + Value *NewVal = Rewriter.expandCodeFor(AR, UseTy, InsertPt); // Patch the new value into place. if (Op->hasName()) Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=74048&r1=74047&r2=74048&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue Jun 23 20:18:18 2009 @@ -409,16 +409,8 @@ const SCEV* NewValSCEV = SE->getUnknown(Base); - // If there is no immediate value, skip the next part. - if (!Imm->isZero()) { - // If we are inserting the base and imm values in the same block, make sure - // to adjust the IP position if insertion reused a result. - if (IP == BaseInsertPt) - IP = Rewriter.getInsertionPoint(); - - // Always emit the immediate (if non-zero) into the same block as the user. - NewValSCEV = SE->getAddExpr(NewValSCEV, Imm); - } + // Always emit the immediate into the same block as the user. + NewValSCEV = SE->getAddExpr(NewValSCEV, Imm); return Rewriter.expandCodeFor(NewValSCEV, Ty, IP); } Modified: llvm/trunk/test/CodeGen/X86/pr3495.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr3495.ll?rev=74048&r1=74047&r2=74048&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr3495.ll (original) +++ llvm/trunk/test/CodeGen/X86/pr3495.ll Tue Jun 23 20:18:18 2009 @@ -1,6 +1,6 @@ ; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of reloads omited} | grep 2 ; RUN: llvm-as < %s | llc -march=x86 -stats |& not grep {Number of available reloads turned into copies} -; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of machine instrs printed} | grep 38 +; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of machine instrs printed} | grep 39 ; PR3495 ; The loop reversal kicks in once here, resulting in one fewer instruction. From gohman at apple.com Tue Jun 23 20:22:30 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 01:22:30 -0000 Subject: [llvm-commits] [llvm] r74049 - /llvm/trunk/test/Analysis/ScalarEvolution/trip-count6.ll Message-ID: <200906240122.n5O1MUqj011617@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 23 20:22:30 2009 New Revision: 74049 URL: http://llvm.org/viewvc/llvm-project?rev=74049&view=rev Log: Add a testcase demoing some of ScalarEvolution's new trip count logic. Added: llvm/trunk/test/Analysis/ScalarEvolution/trip-count6.ll Added: llvm/trunk/test/Analysis/ScalarEvolution/trip-count6.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/trip-count6.ll?rev=74049&view=auto ============================================================================== --- llvm/trunk/test/Analysis/ScalarEvolution/trip-count6.ll (added) +++ llvm/trunk/test/Analysis/ScalarEvolution/trip-count6.ll Tue Jun 23 20:22:30 2009 @@ -0,0 +1,37 @@ +; RUN: llvm-as < %s | opt -analyze -disable-output -scalar-evolution \ +; RUN: | grep {max backedge-taken count is 1\$} + + at mode_table = global [4 x i32] zeroinitializer ; <[4 x i32]*> [#uses=1] + +define i8 @f() { +entry: + tail call i32 @fegetround( ) ; :0 [#uses=1] + br label %bb + +bb: ; preds = %bb4, %entry + %mode.0 = phi i8 [ 0, %entry ], [ %indvar.next, %bb4 ] ; [#uses=4] + zext i8 %mode.0 to i32 ; :1 [#uses=1] + getelementptr [4 x i32]* @mode_table, i32 0, i32 %1 ; :2 [#uses=1] + load i32* %2, align 4 ; :3 [#uses=1] + icmp eq i32 %3, %0 ; :4 [#uses=1] + br i1 %4, label %bb1, label %bb2 + +bb1: ; preds = %bb + ret i8 %mode.0 + +bb2: ; preds = %bb + icmp eq i8 %mode.0, 1 ; :5 [#uses=1] + br i1 %5, label %bb5, label %bb4 + +bb4: ; preds = %bb2 + %indvar.next = add i8 %mode.0, 1 ; [#uses=1] + br label %bb + +bb5: ; preds = %bb2 + tail call void @raise_exception( ) noreturn + unreachable +} + +declare i32 @fegetround() + +declare void @raise_exception() noreturn From dalej at apple.com Tue Jun 23 20:25:53 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 24 Jun 2009 01:25:53 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r74050 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Message-ID: <200906240125.n5O1PrxP011729@zion.cs.uiuc.edu> Author: johannes Date: Tue Jun 23 20:25:53 2009 New Revision: 74050 URL: http://llvm.org/viewvc/llvm-project?rev=74050&view=rev Log: Change initialization calls to understand new ABI, making llvm-gcc build again. It would not surprise me if this caused problems for other external clients as well. Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=74050&r1=74049&r2=74050&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Tue Jun 23 20:25:53 2009 @@ -332,7 +332,7 @@ #endif namespace llvm { -#define Declare2(TARG, MOD) void Initialize ## TARG ## MOD() +#define Declare2(TARG, MOD) extern "C" void LLVMInitialize ## TARG ## MOD() #define Declare(T, M) Declare2(T, M) Declare(LLVM_TARGET_NAME, Target); Declare(LLVM_TARGET_NAME, AsmPrinter); @@ -342,7 +342,7 @@ void llvm_initialize_backend(void) { // Initialize the LLVM backend. -#define DoInit2(TARG, MOD) llvm::Initialize ## TARG ## MOD() +#define DoInit2(TARG, MOD) LLVMInitialize ## TARG ## MOD() #define DoInit(T, M) DoInit2(T, M) DoInit(LLVM_TARGET_NAME, Target); DoInit(LLVM_TARGET_NAME, AsmPrinter); From evan.cheng at apple.com Tue Jun 23 21:05:51 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 24 Jun 2009 02:05:51 -0000 Subject: [llvm-commits] [llvm] r74053 - in /llvm/trunk: lib/CodeGen/MachineInstr.cpp test/CodeGen/X86/inline-asm-tied.ll Message-ID: <200906240205.n5O25qBA012932@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jun 23 21:05:51 2009 New Revision: 74053 URL: http://llvm.org/viewvc/llvm-project?rev=74053&view=rev Log: Fix support for inline asm input / output operand tying when operand spans across multiple registers (e.g. two i64 operands in 32-bit mode). Added: llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=74053&r1=74052&r2=74053&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Jun 23 21:05:51 2009 @@ -716,31 +716,37 @@ const MachineOperand &MO = getOperand(DefOpIdx); if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) return false; - // Determine the actual operand no corresponding to this index. + // Determine the actual operand index that corresponds to this index. unsigned DefNo = 0; + unsigned DefPart = 0; for (unsigned i = 1, e = getNumOperands(); i < e; ) { const MachineOperand &FMO = getOperand(i); assert(FMO.isImm()); // Skip over this def. - i += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1; - if (i > DefOpIdx) + unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm()); + unsigned PrevDef = i + 1; + i = PrevDef + NumOps; + if (i > DefOpIdx) { + DefPart = DefOpIdx - PrevDef; break; + } ++DefNo; } - for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { + for (unsigned i = 1, e = getNumOperands(); i != e; ++i) { const MachineOperand &FMO = getOperand(i); if (!FMO.isImm()) continue; if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse()) continue; unsigned Idx; - if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && + if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && Idx == DefNo) { if (UseOpIdx) - *UseOpIdx = (unsigned)i + 1; + *UseOpIdx = (unsigned)i + 1 + DefPart; return true; } } + return false; } assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); @@ -766,10 +772,16 @@ const MachineOperand &MO = getOperand(UseOpIdx); if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) return false; - assert(UseOpIdx > 0); - const MachineOperand &UFMO = getOperand(UseOpIdx-1); - if (!UFMO.isImm()) - return false; // Must be physreg uses. + int FlagIdx = UseOpIdx - 1; + if (FlagIdx < 1) + return false; + while (!getOperand(FlagIdx).isImm()) { + if (--FlagIdx == 0) + return false; + } + const MachineOperand &UFMO = getOperand(FlagIdx); + if (FlagIdx + InlineAsm::getNumOperandRegisters(UFMO.getImm()) < UseOpIdx) + return false; unsigned DefNo; if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) { if (!DefOpIdx) @@ -785,7 +797,7 @@ DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1; --DefNo; } - *DefOpIdx = DefIdx+1; + *DefOpIdx = DefIdx + UseOpIdx - FlagIdx; return true; } return false; Added: llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll?rev=74053&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll (added) +++ llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll Tue Jun 23 21:05:51 2009 @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 -O0 | grep {movl %edx, 4(%esp)} | count 2 +; rdar://6992609 + +target triple = "i386-apple-darwin9.0" + at llvm.used = appending global [1 x i8*] [i8* bitcast (i64 (i64)* @_OSSwapInt64 to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define i64 @_OSSwapInt64(i64 %_data) nounwind { +entry: + %retval = alloca i64 ; [#uses=2] + %_data.addr = alloca i64 ; [#uses=4] + store i64 %_data, i64* %_data.addr + %tmp = load i64* %_data.addr ; [#uses=1] + %0 = call i64 asm "bswap %eax\0A\09bswap %edx\0A\09xchgl %eax, %edx", "=A,0,~{dirflag},~{fpsr},~{flags}"(i64 %tmp) nounwind ; [#uses=1] + store i64 %0, i64* %_data.addr + %tmp1 = load i64* %_data.addr ; [#uses=1] + store i64 %tmp1, i64* %retval + %1 = load i64* %retval ; [#uses=1] + ret i64 %1 +} From lhames at gmail.com Tue Jun 23 21:17:32 2009 From: lhames at gmail.com (Lang Hames) Date: Wed, 24 Jun 2009 02:17:32 -0000 Subject: [llvm-commits] [llvm] r74054 - in /llvm/trunk/lib/CodeGen: LiveInterval.cpp VirtRegRewriter.h Message-ID: <200906240217.n5O2HWLX013328@zion.cs.uiuc.edu> Author: lhames Date: Tue Jun 23 21:17:32 2009 New Revision: 74054 URL: http://llvm.org/viewvc/llvm-project?rev=74054&view=rev Log: Fixed a bug in LiveInterval scaling (failure to scale VNI defs correctly), removed old TODO comments. Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp llvm/trunk/lib/CodeGen/VirtRegRewriter.h Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=74054&r1=74053&r2=74054&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Jun 23 21:17:32 2009 @@ -373,7 +373,8 @@ for (vni_iterator VNI = vni_begin(), VNIE = vni_end(); VNI != VNIE; ++VNI) { VNInfo *vni = *VNI; - vni->def = InstrSlots::scale(vni->def, factor); + if (vni->isDefAccurate()) + vni->def = InstrSlots::scale(vni->def, factor); for (unsigned i = 0; i < vni->kills.size(); ++i) { if (vni->kills[i] != 0) Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.h?rev=74054&r1=74053&r2=74054&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegRewriter.h (original) +++ llvm/trunk/lib/CodeGen/VirtRegRewriter.h Tue Jun 23 21:17:32 2009 @@ -32,11 +32,6 @@ #include "VirtRegMap.h" #include -// TODO: -// - Finish renaming Spiller -> Rewriter -// - SimpleSpiller -// - LocalSpiller - namespace llvm { /// VirtRegRewriter interface: Implementations of this interface assign From evan.cheng at apple.com Tue Jun 23 21:35:56 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 19:35:56 -0700 Subject: [llvm-commits] [llvm] r74026 - in /llvm/trunk: include/llvm-c/ include/llvm/Config/ include/llvm/Target/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Alpha/AsmPrinter/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CellSPU/AsmPrinter/ lib/Target/CppBackend/ lib/Target/IA64/ lib/Target/IA64/AsmPrinter/ lib/Target/MSIL/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/Mips/AsmPrinter/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/PowerPC/AsmPrinter/ lib/Target/Sparc/ lib/Target/Sparc/AsmP... In-Reply-To: <200906232359.n5NNxfeG008666@zion.cs.uiuc.edu> References: <200906232359.n5NNxfeG008666@zion.cs.uiuc.edu> Message-ID: <6C45A278-A8D3-4477-9ED9-E3E622BD6CE5@apple.com> Bob, I think this is breaking the llvm-gcc build: llvm::InitializeARMAsmPrinter()", referenced from: "llvm::InitializePowerPCTarget()", referenced from: "llvm::InitializeX86Target()", referenced from: "llvm::InitializeARMTarget()", referenced from: "llvm::InitializeX86AsmPrinter()", referenced from: "llvm::InitializePowerPCAsmPrinter()", referenced from: ld: symbol(s) not found collect2: ld returned 1 exit status make[4]: *** [libllvmgcc.dylib] Error 1 Evan On Jun 23, 2009, at 4:59 PM, Bob Wilson wrote: > Author: bwilson > Date: Tue Jun 23 18:59:40 2009 > New Revision: 74026 > > URL: http://llvm.org/viewvc/llvm-project?rev=74026&view=rev > Log: > Provide InitializeAllTargets and InitializeNativeTarget functions in > the > C bindings. Change all the backend "Initialize" functions to have C > linkage. > Change the "llvm/Config/Targets.def" header to use C-style comments > to avoid > compile warnings. > > Modified: > llvm/trunk/include/llvm-c/Target.h > llvm/trunk/include/llvm/Config/Targets.def.in > llvm/trunk/include/llvm/Target/TargetSelect.h > llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp > llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp > llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp > llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp > llvm/trunk/lib/Target/CBackend/CBackend.cpp > llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp > llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp > llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp > llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp > llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp > llvm/trunk/lib/Target/MSIL/MSILWriter.cpp > llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp > llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp > llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp > llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp > llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp > llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp > llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp > llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp > llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp > llvm/trunk/lib/Target/X86/X86TargetMachine.cpp > llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp > > Modified: llvm/trunk/include/llvm-c/Target.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Target.h?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm-c/Target.h (original) > +++ llvm/trunk/include/llvm-c/Target.h Tue Jun 23 18:59:40 2009 > @@ -20,6 +20,7 @@ > #define LLVM_C_TARGET_H > > #include "llvm-c/Core.h" > +#include "llvm/Config/config.h" > > #ifdef __cplusplus > extern "C" { > @@ -31,6 +32,34 @@ > typedef struct LLVMOpaqueTargetData *LLVMTargetDataRef; > typedef struct LLVMStructLayout *LLVMStructLayoutRef; > > +/* Declare all of the target-initialization functions that are > available. */ > +#define LLVM_TARGET(TargetName) void > LLVMInitialize##TargetName##Target(); > +#include "llvm/Config/Targets.def" > + > +/** LLVMInitializeAllTargets - The main program should call this > function if it > + wants to link in all available targets that LLVM is configured to > + support. */ > +static inline void LLVMInitializeAllTargets() { > +#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##Target(); > +#include "llvm/Config/Targets.def" > +} > + > +/** LLVMInitializeNativeTarget - The main program should call this > function to > + initialize the native target corresponding to the host. This > is useful > + for JIT applications to ensure that the target gets linked in > correctly. */ > +static inline int LLVMInitializeNativeTarget() { > + /* If we have a native target, initialize it to ensure it is > linked in. */ > +#ifdef LLVM_NATIVE_ARCH > +#define DoInit2(TARG) LLVMInitialize ## TARG () > +#define DoInit(T) DoInit2(T) > + DoInit(LLVM_NATIVE_ARCH); > + return 0; > +#undef DoInit > +#undef DoInit2 > +#else > + return 1; > +#endif > +} > > /*===-- Target Data > -------------------------------------------------------===*/ > > > Modified: llvm/trunk/include/llvm/Config/Targets.def.in > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/Targets.def.in?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Config/Targets.def.in (original) > +++ llvm/trunk/include/llvm/Config/Targets.def.in Tue Jun 23 > 18:59:40 2009 > @@ -1,23 +1,23 @@ > -//===- llvm/Config/Targets.def - LLVM Target Architectures ------*- > C++ -*-===// > -// > -// The LLVM Compiler Infrastructure > -// > -// This file is distributed under the University of Illinois Open > Source > -// License. See LICENSE.TXT for details. > -// > -// > = > = > = > ----------------------------------------------------------------------= > ==// > -// > -// This file enumerates all of the target architectures supported by > -// this build of LLVM. Clients of this file should define the > -// LLVM_TARGET macro to be a function-like macro with a single > -// parameter (the name of the target); including this file will then > -// enumerate all of the targets. > -// > -// The set of targets supported by LLVM is generated at configuration > -// time, at which point this header is generated. Do not modify this > -// header directly. > -// > -// > = > = > = > ----------------------------------------------------------------------= > ==// > +/*===- llvm/Config/Targets.def - LLVM Target Architectures ------*- > C++ -*-===*\ > +| > * *| > +|* The LLVM Compiler > Infrastructure *| > +| > * *| > +|* This file is distributed under the University of Illinois Open > Source *| > +|* License. See LICENSE.TXT for > details. *| > +| > * *| > +| > *= > = > = > ----------------------------------------------------------------------= > ==*| > +| > * *| > +|* This file enumerates all of the target architectures supported > by *| > +|* this build of LLVM. Clients of this file should define > the *| > +|* LLVM_TARGET macro to be a function-like macro with a > single *| > +|* parameter (the name of the target); including this file will > then *| > +|* enumerate all of the > targets. *| > +| > * *| > +|* The set of targets supported by LLVM is generated at > configuration *| > +|* time, at which point this header is generated. Do not modify > this *| > +|* header > directly. *| > +| > * *| > + > \*= > = > = > ----------------------------------------------------------------------= > ==*/ > > #ifndef LLVM_TARGET > # error Please define the macro LLVM_TARGET(TargetName) > > Modified: llvm/trunk/include/llvm/Target/TargetSelect.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelect.h?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Target/TargetSelect.h (original) > +++ llvm/trunk/include/llvm/Target/TargetSelect.h Tue Jun 23 > 18:59:40 2009 > @@ -18,20 +18,21 @@ > > #include "llvm/Config/config.h" > > -namespace llvm { > +extern "C" { > // Declare all of the target-initialization functions that are > available. > -#define LLVM_TARGET(TargetName) void > Initialize##TargetName##Target(); > +#define LLVM_TARGET(TargetName) void > LLVMInitialize##TargetName##Target(); > #include "llvm/Config/Targets.def" > > // Declare all of the available asm-printer initialization > functions. > - // Declare all of the target-initialization functions. > -#define LLVM_ASM_PRINTER(TargetName) void > Initialize##TargetName##AsmPrinter(); > +#define LLVM_ASM_PRINTER(TargetName) void > LLVMInitialize##TargetName##AsmPrinter(); > #include "llvm/Config/AsmPrinters.def" > - > +} > + > +namespace llvm { > /// InitializeAllTargets - The main program should call this > function if it > /// wants to link in all available targets that LLVM is configured > to support. > inline void InitializeAllTargets() { > -#define LLVM_TARGET(TargetName) > llvm::Initialize##TargetName##Target(); > +#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##Target(); > #include "llvm/Config/Targets.def" > } > > @@ -39,18 +40,17 @@ > /// it wants all asm printers that LLVM is configured to support. > This will > /// cause them to be linked into its executable. > inline void InitializeAllAsmPrinters() { > -#define LLVM_ASM_PRINTER(TargetName) > Initialize##TargetName##AsmPrinter(); > +#define LLVM_ASM_PRINTER(TargetName) > LLVMInitialize##TargetName##AsmPrinter(); > #include "llvm/Config/AsmPrinters.def" > } > > - > /// InitializeNativeTarget - The main program should call this > function to > /// initialize the native target corresponding to the host. This > is useful > /// for JIT applications to ensure that the target gets linked in > correctly. > inline bool InitializeNativeTarget() { > // If we have a native target, initialize it to ensure it is > linked in. > #ifdef LLVM_NATIVE_ARCH > -#define DoInit2(TARG) llvm::Initialize ## TARG () > +#define DoInit2(TARG) LLVMInitialize ## TARG () > #define DoInit(T) DoInit2(T) > DoInit(LLVM_NATIVE_ARCH); > return false; > > Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Tue Jun 23 > 18:59:40 2009 > @@ -39,10 +39,8 @@ > static RegisterTarget X("arm", "ARM"); > static RegisterTarget Y("thumb", "Thumb"); > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializeARMTarget() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeARMTarget() { } > > // No assembler printer by default > ARMTargetMachine::AsmPrinterCtorFn ARMTargetMachine::AsmPrinterCtor > = 0; > > Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Tue Jun > 23 18:59:40 2009 > @@ -1172,8 +1172,5 @@ > } Registrator; > } > > -// Force static initialization when called from > -// llvm/InitializeAllAsmPrinters.h > -namespace llvm { > - void InitializeARMAsmPrinter() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeARMAsmPrinter() { } > > Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Tue Jun 23 > 18:59:40 2009 > @@ -27,10 +27,8 @@ > // No assembler printer by default > AlphaTargetMachine::AsmPrinterCtorFn > AlphaTargetMachine::AsmPrinterCtor = 0; > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializeAlphaTarget() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeAlphaTarget() { } > > const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const { > return new AlphaTargetAsmInfo(*this); > > Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp > (original) > +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Tue > Jun 23 18:59:40 2009 > @@ -304,11 +304,8 @@ > return false; > } > > -// Force static initialization when called from > -// llvm/InitializeAllAsmPrinters.h > -namespace llvm { > - void InitializeAlphaAsmPrinter() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeAlphaAsmPrinter() { } > > namespace { > static struct Register { > > Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) > +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Tue Jun 23 18:59:40 > 2009 > @@ -59,10 +59,8 @@ > // Register the target. > static RegisterTarget X("c", "C backend"); > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializeCBackendTarget() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeCBackendTarget() { } > > namespace { > /// CBackendNameAllUsedStructsAndMergeFunctions - This pass > inserts names for > > Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp > (original) > +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Tue > Jun 23 18:59:40 2009 > @@ -617,11 +617,8 @@ > return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, > verbose); > } > > -// Force static initialization when called from > -// llvm/InitializeAllAsmPrinters.h > -namespace llvm { > - void InitializeCellSPUAsmPrinter() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeCellSPUAsmPrinter() { } > > namespace { > static struct Register { > > Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Tue Jun 23 > 18:59:40 2009 > @@ -32,10 +32,8 @@ > // No assembler printer by default > SPUTargetMachine::AsmPrinterCtorFn SPUTargetMachine::AsmPrinterCtor > = 0; > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializeCellSPUTarget() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeCellSPUTarget() { } > > const std::pair * > SPUFrameInfo::getCalleeSaveSpillSlots(unsigned &NumEntries) const { > > Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original) > +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Tue Jun 23 > 18:59:40 2009 > @@ -82,10 +82,8 @@ > // Register the target. > static RegisterTarget X("cpp", "C++ backend"); > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializeCppBackendTarget() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeCppBackendTarget() { } > > namespace { > typedef std::vector TypeList; > > Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp > (original) > +++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Tue Jun > 23 18:59:40 2009 > @@ -384,8 +384,5 @@ > } > > > -// Force static initialization when called from > -// llvm/InitializeAllAsmPrinters.h > -namespace llvm { > - void InitializeIA64AsmPrinter() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeIA64AsmPrinter() { } > > Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.cpp Tue Jun 23 > 18:59:40 2009 > @@ -26,10 +26,8 @@ > // No assembler printer by default > IA64TargetMachine::AsmPrinterCtorFn > IA64TargetMachine::AsmPrinterCtor = 0; > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializeIA64Target() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeIA64Target() { } > > const TargetAsmInfo *IA64TargetMachine::createTargetAsmInfo() const { > return new IA64TargetAsmInfo(*this); > > Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original) > +++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Tue Jun 23 18:59:40 2009 > @@ -55,10 +55,8 @@ > > static RegisterTarget X("msil", "MSIL backend"); > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializeMSILTarget() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeMSILTarget() { } > > bool MSILModule::runOnModule(Module &M) { > ModulePtr = &M; > > Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Tue Jun 23 > 18:59:40 2009 > @@ -35,10 +35,8 @@ > static RegisterTarget > X("msp430", "MSP430 [experimental]"); > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializeMSP430Target() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeMSP430Target() { } > > MSP430TargetMachine::MSP430TargetMachine(const Module &M, > const std::string &FS) : > > Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp > (original) > +++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Tue Jun > 23 18:59:40 2009 > @@ -587,8 +587,5 @@ > } Registrator; > } > > -// Force static initialization when called from > -// llvm/InitializeAllAsmPrinters.h > -namespace llvm { > - void InitializeMipsAsmPrinter() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeMipsAsmPrinter() { } > > Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Tue Jun 23 > 18:59:40 2009 > @@ -34,10 +34,8 @@ > MipsTargetMachine::AsmPrinterCtorFn > MipsTargetMachine::AsmPrinterCtor = 0; > > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializeMipsTarget() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeMipsTarget() { } > > const TargetAsmInfo *MipsTargetMachine:: > createTargetAsmInfo() const > > Modified: llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/PIC16/PIC16TargetMachine.cpp Tue Jun 23 > 18:59:40 2009 > @@ -37,10 +37,8 @@ > static RegisterTarget > Y("cooper", "PIC16 Cooper [experimental]."); > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializePIC16Target() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializePIC16Target() { } > > // PIC16TargetMachine - Traditional PIC16 Machine. > PIC16TargetMachine::PIC16TargetMachine(const Module &M, const > std::string &FS, > > Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp > (original) > +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Tue > Jun 23 18:59:40 2009 > @@ -1185,8 +1185,5 @@ > extern "C" int PowerPCAsmPrinterForceLink; > int PowerPCAsmPrinterForceLink = 0; > > -// Force static initialization when called from > -// llvm/InitializeAllAsmPrinters.h > -namespace llvm { > - void InitializePowerPCAsmPrinter() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializePowerPCAsmPrinter() { } > > Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Tue Jun 23 > 18:59:40 2009 > @@ -35,10 +35,8 @@ > static RegisterTarget > Y("ppc64", "PowerPC 64"); > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializePowerPCTarget() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializePowerPCTarget() { } > > // No assembler printer by default > PPCTargetMachine::AsmPrinterCtorFn PPCTargetMachine::AsmPrinterCtor > = 0; > > Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp > (original) > +++ llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp Tue > Jun 23 18:59:40 2009 > @@ -362,8 +362,5 @@ > } Registrator; > } > > -// Force static initialization when called from > -// llvm/InitializeAllAsmPrinters.h > -namespace llvm { > - void InitializeSparcAsmPrinter() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeSparcAsmPrinter() { } > > Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Tue Jun 23 > 18:59:40 2009 > @@ -25,10 +25,8 @@ > SparcTargetMachine::AsmPrinterCtorFn > SparcTargetMachine::AsmPrinterCtor = 0; > > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializeSparcTarget() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeSparcTarget() { } > > const TargetAsmInfo *SparcTargetMachine::createTargetAsmInfo() const { > // FIXME: Handle Solaris subtarget someday :) > > Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Tue Jun > 23 18:59:40 2009 > @@ -47,8 +47,5 @@ > extern "C" int X86AsmPrinterForceLink; > int X86AsmPrinterForceLink = 0; > > -// Force static initialization when called from > -// llvm/InitializeAllAsmPrinters.h > -namespace llvm { > - void InitializeX86AsmPrinter() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeX86AsmPrinter() { } > > Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Tue Jun 23 > 18:59:40 2009 > @@ -36,10 +36,8 @@ > static RegisterTarget > Y("x86-64", "64-bit X86: EM64T and AMD64"); > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializeX86Target() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeX86Target() { } > > // No assembler printer by default > X86TargetMachine::AsmPrinterCtorFn X86TargetMachine::AsmPrinterCtor > = 0; > > Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=74026&r1=74025&r2=74026&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original) > +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Tue Jun 23 > 18:59:40 2009 > @@ -31,10 +31,8 @@ > RegisterTarget X("xcore", "XCore"); > } > > -// Force static initialization when called from llvm/ > InitializeAllTargets.h > -namespace llvm { > - void InitializeXCoreTarget() { } > -} > +// Force static initialization. > +extern "C" void LLVMInitializeXCoreTarget() { } > > const TargetAsmInfo *XCoreTargetMachine::createTargetAsmInfo() const { > return new XCoreTargetAsmInfo(*this); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bob.wilson at apple.com Tue Jun 23 21:52:57 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 23 Jun 2009 19:52:57 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r74050 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp In-Reply-To: <200906240125.n5O1PrxP011729@zion.cs.uiuc.edu> References: <200906240125.n5O1PrxP011729@zion.cs.uiuc.edu> Message-ID: <26C17DB1-3F97-4E87-AF19-EE548DC29D32@apple.com> Thanks, Dale. Sorry for the breakage. On Jun 23, 2009, at 6:25 PM, Dale Johannesen wrote: > Author: johannes > Date: Tue Jun 23 20:25:53 2009 > New Revision: 74050 > > URL: http://llvm.org/viewvc/llvm-project?rev=74050&view=rev > Log: > Change initialization calls to understand new ABI, > making llvm-gcc build again. > > It would not surprise me if this caused problems > for other external clients as well. > > > Modified: > llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=74050&r1=74049&r2=74050&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Tue Jun 23 20:25:53 2009 > @@ -332,7 +332,7 @@ > #endif > > namespace llvm { > -#define Declare2(TARG, MOD) void Initialize ## TARG ## MOD() > +#define Declare2(TARG, MOD) extern "C" void LLVMInitialize ## > TARG ## MOD() > #define Declare(T, M) Declare2(T, M) > Declare(LLVM_TARGET_NAME, Target); > Declare(LLVM_TARGET_NAME, AsmPrinter); > @@ -342,7 +342,7 @@ > > void llvm_initialize_backend(void) { > // Initialize the LLVM backend. > -#define DoInit2(TARG, MOD) llvm::Initialize ## TARG ## MOD() > +#define DoInit2(TARG, MOD) LLVMInitialize ## TARG ## MOD() > #define DoInit(T, M) DoInit2(T, M) > DoInit(LLVM_TARGET_NAME, Target); > DoInit(LLVM_TARGET_NAME, AsmPrinter); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From nicholas at mxc.ca Tue Jun 23 22:18:40 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 23 Jun 2009 20:18:40 -0700 Subject: [llvm-commits] [llvm] r74029 - /llvm/trunk/lib/VMCore/Pass.cpp In-Reply-To: <200906240025.n5O0PhFD009550@zion.cs.uiuc.edu> References: <200906240025.n5O0PhFD009550@zion.cs.uiuc.edu> Message-ID: <4A419B10.2040203@mxc.ca> Owen Anderson wrote: > Author: resistor > Date: Tue Jun 23 19:25:42 2009 > New Revision: 74029 > > URL: http://llvm.org/viewvc/llvm-project?rev=74029&view=rev > Log: > Guard the listeners list. Unfortunately, this requires a real static rather > than a managed static because other managed statics can (and do) access this > list in their destructors. Yes, I know it's horrible. Then could you add that tidbit of information to a comment right before the variable declaration? Nick > Modified: > llvm/trunk/lib/VMCore/Pass.cpp > > Modified: llvm/trunk/lib/VMCore/Pass.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Pass.cpp?rev=74029&r1=74028&r2=74029&view=diff > > ============================================================================== > --- llvm/trunk/lib/VMCore/Pass.cpp (original) > +++ llvm/trunk/lib/VMCore/Pass.cpp Tue Jun 23 19:25:42 2009 > @@ -20,6 +20,7 @@ > #include "llvm/ADT/STLExtras.h" > #include "llvm/Support/ManagedStatic.h" > #include "llvm/System/Atomic.h" > +#include "llvm/System/Mutex.h" > #include "llvm/System/Threading.h" > #include > #include > @@ -187,6 +188,7 @@ > } > > static std::vector *Listeners = 0; > +static sys::SmartMutex ListenersLock; > > // FIXME: This should use ManagedStatic to manage the pass registrar. > // Unfortunately, we can't do this, because passes are registered with static > @@ -231,6 +233,7 @@ > getPassRegistrar()->RegisterPass(*this); > > // Notify any listeners. > + sys::SmartScopedLock Lock(&ListenersLock); > if (Listeners) > for (std::vector::iterator > I = Listeners->begin(), E = Listeners->end(); I != E; ++I) > @@ -283,12 +286,14 @@ > // PassRegistrationListener ctor - Add the current object to the list of > // PassRegistrationListeners... > PassRegistrationListener::PassRegistrationListener() { > + sys::SmartScopedLock Lock(&ListenersLock); > if (!Listeners) Listeners = new std::vector(); > Listeners->push_back(this); > } > > // dtor - Remove object from list of listeners... > PassRegistrationListener::~PassRegistrationListener() { > + sys::SmartScopedLock Lock(&ListenersLock); > std::vector::iterator I = > std::find(Listeners->begin(), Listeners->end(), this); > assert(Listeners && I != Listeners->end() && > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From rnk at mit.edu Tue Jun 23 18:59:39 2009 From: rnk at mit.edu (Reid Kleckner) Date: Tue, 23 Jun 2009 16:59:39 -0700 Subject: [llvm-commits] Patch to allow the JITMemoryManager to allocate more blocks of memory In-Reply-To: <9a9942200906231656r3fd098c6r9e3e53dffe7cf790@mail.gmail.com> References: <9a9942200906231656r3fd098c6r9e3e53dffe7cf790@mail.gmail.com> Message-ID: <9a9942200906231659x2b73f65ap51207eb5eef56129@mail.gmail.com> I meant to send this to llvm-commits at cs.uiuc.edu: On Tue, Jun 23, 2009 at 4:56 PM, Reid Kleckner wrote: > Hey all, > > I'm working on unladen-swallow, and our regression tests currently > fail halfway through because the DefaultJITMemoryManager doesn't > allocate more memory when it runs out of space. ?This patch fixes that > by retrying and asking for twice as much space, which the memory > manager uses to allocate a new slab of memory. > > I ran it by Jeff Yasskin and Nick Lewycky here: > http://codereview.appspot.com/71042 > > The patch is attached. > > Reid > From rnk at mit.edu Tue Jun 23 19:05:39 2009 From: rnk at mit.edu (Reid Kleckner) Date: Tue, 23 Jun 2009 17:05:39 -0700 Subject: [llvm-commits] Patch to allow the JITMemoryManager to allocate more blocks of memory In-Reply-To: <9a9942200906231659x2b73f65ap51207eb5eef56129@mail.gmail.com> References: <9a9942200906231656r3fd098c6r9e3e53dffe7cf790@mail.gmail.com> <9a9942200906231659x2b73f65ap51207eb5eef56129@mail.gmail.com> Message-ID: <9a9942200906231705m4ec42d3drabd014f740867f28@mail.gmail.com> And of course I meant to attach the patch, goshdurnit. Reid On Tue, Jun 23, 2009 at 4:59 PM, Reid Kleckner wrote: > I meant to send this to llvm-commits at cs.uiuc.edu: > > On Tue, Jun 23, 2009 at 4:56 PM, Reid Kleckner wrote: >> Hey all, >> >> I'm working on unladen-swallow, and our regression tests currently >> fail halfway through because the DefaultJITMemoryManager doesn't >> allocate more memory when it runs out of space. ?This patch fixes that >> by retrying and asking for twice as much space, which the memory >> manager uses to allocate a new slab of memory. >> >> I ran it by Jeff Yasskin and Nick Lewycky here: >> http://codereview.appspot.com/71042 >> >> The patch is attached. >> >> Reid >> > -------------- next part -------------- A non-text attachment was scrubbed... Name: JITMemoryManager.diff Type: text/x-diff Size: 29511 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090623/9036f073/attachment.bin From evan.cheng at apple.com Tue Jun 23 22:38:22 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 23 Jun 2009 20:38:22 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r74050 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp In-Reply-To: <26C17DB1-3F97-4E87-AF19-EE548DC29D32@apple.com> References: <200906240125.n5O1PrxP011729@zion.cs.uiuc.edu> <26C17DB1-3F97-4E87-AF19-EE548DC29D32@apple.com> Message-ID: <0DBE81A4-6F0C-4E90-AB86-C389AE80D2A3@apple.com> Still doesn't build for me: Undefined symbols: "_LLVMInitializeX86AsmPrinter", referenced from: _llvm_initialize_backend in libbackend.a(llvm-backend.o) "_LLVMInitializeX86Target", referenced from: _llvm_initialize_backend in libbackend.a(llvm-backend.o) Evan On Jun 23, 2009, at 7:52 PM, Bob Wilson wrote: > Thanks, Dale. Sorry for the breakage. > > On Jun 23, 2009, at 6:25 PM, Dale Johannesen wrote: > >> Author: johannes >> Date: Tue Jun 23 20:25:53 2009 >> New Revision: 74050 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=74050&view=rev >> Log: >> Change initialization calls to understand new ABI, >> making llvm-gcc build again. >> >> It would not surprise me if this caused problems >> for other external clients as well. >> >> >> Modified: >> llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp >> >> Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=74050&r1=74049&r2=74050&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) >> +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Tue Jun 23 20:25:53 2009 >> @@ -332,7 +332,7 @@ >> #endif >> >> namespace llvm { >> -#define Declare2(TARG, MOD) void Initialize ## TARG ## MOD() >> +#define Declare2(TARG, MOD) extern "C" void LLVMInitialize ## >> TARG ## MOD() >> #define Declare(T, M) Declare2(T, M) >> Declare(LLVM_TARGET_NAME, Target); >> Declare(LLVM_TARGET_NAME, AsmPrinter); >> @@ -342,7 +342,7 @@ >> >> void llvm_initialize_backend(void) { >> // Initialize the LLVM backend. >> -#define DoInit2(TARG, MOD) llvm::Initialize ## TARG ## MOD() >> +#define DoInit2(TARG, MOD) LLVMInitialize ## TARG ## MOD() >> #define DoInit(T, M) DoInit2(T, M) >> DoInit(LLVM_TARGET_NAME, Target); >> DoInit(LLVM_TARGET_NAME, AsmPrinter); >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Tue Jun 23 22:59:03 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 03:59:03 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r74056 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200906240359.n5O3x3i6016611@zion.cs.uiuc.edu> Author: lattner Date: Tue Jun 23 22:59:03 2009 New Revision: 74056 URL: http://llvm.org/viewvc/llvm-project?rev=74056&view=rev Log: Fix an array over-read problem that would sometimes manifest as a crash (when overreading a string would point to invalid data. The issue here is that TREE_STRING_LENGTH returns the length in bytes of a string, not in characters. This is different for a wide string. In cases when this didn't crash, this bug would not manifest as a codegen problem, because the code right below the overread would trim the length of the generated vector to the right length. This fixes rdar://6961178 Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=74056&r1=74055&r2=74056&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Jun 23 22:59:03 2009 @@ -6642,13 +6642,17 @@ for (unsigned i = 0; i != Len; ++i) Elts.push_back(ConstantInt::get(Type::Int8Ty, InStr[i])); } else if (ElTy == Type::Int16Ty) { + assert((Len&1) == 0 && + "Length in bytes should be a multiple of element size"); const unsigned short *InStr = (const unsigned short *)TREE_STRING_POINTER(exp); - for (unsigned i = 0; i != Len; ++i) + for (unsigned i = 0; i != Len/2; ++i) Elts.push_back(ConstantInt::get(Type::Int16Ty, InStr[i])); } else if (ElTy == Type::Int32Ty) { + assert((Len&3) == 0 && + "Length in bytes should be a multiple of element size"); const unsigned *InStr = (const unsigned *)TREE_STRING_POINTER(exp); - for (unsigned i = 0; i != Len; ++i) + for (unsigned i = 0; i != Len/4; ++i) Elts.push_back(ConstantInt::get(Type::Int32Ty, InStr[i])); } else { assert(0 && "Unknown character type!"); From sabre at nondot.org Tue Jun 23 23:31:50 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 04:31:50 -0000 Subject: [llvm-commits] [llvm] r74057 - in /llvm/trunk: include/llvm/MC/MCContext.h lib/MC/MCAsmStreamer.cpp lib/MC/MCContext.cpp tools/llvm-mc/AsmParser.cpp tools/llvm-mc/AsmParser.h tools/llvm-mc/llvm-mc.cpp Message-ID: <200906240431.n5O4VoJv017690@zion.cs.uiuc.edu> Author: lattner Date: Tue Jun 23 23:31:49 2009 New Revision: 74057 URL: http://llvm.org/viewvc/llvm-project?rev=74057&view=rev Log: add trivial support for passing label definitions through the MCStreamer. This is suboptimal in several aspects, see the commented out assertion. I need to talk to Daniel about this. Modified: llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/tools/llvm-mc/AsmParser.cpp llvm/trunk/tools/llvm-mc/AsmParser.h llvm/trunk/tools/llvm-mc/llvm-mc.cpp Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=74057&r1=74056&r2=74057&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Tue Jun 23 23:31:49 2009 @@ -56,6 +56,13 @@ /// @param Name - The symbol name, which must be unique across all symbols. MCSymbol *CreateSymbol(MCAtom *Atom, const char *Name); + /// GetOrCreateSymbol - Lookup the symbol inside with the specified + /// @param Name. If it exists, return it. If not, create a forward + /// reference and return it. + /// + /// @param Name - The symbol name, which must be unique across all symbols. + MCSymbol *GetOrCreateSymbol(const char *Name); + /// CreateTemporarySymbol - Create a new temporary symbol inside @param Atom /// with the specified @param Name. /// Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=74057&r1=74056&r2=74057&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Tue Jun 23 23:31:49 2009 @@ -84,8 +84,8 @@ void MCAsmStreamer::EmitLabel(MCSymbol *Symbol) { // FIXME: We need to enforce that we aren't printing atoms which are more // complicated than the assembler understands. - assert(Symbol->getAtom()->getSection() == CurSection && - "The label for a symbol must match its section!"); + //assert(Symbol->getAtom()->getSection() == CurSection && + // "The label for a symbol must match its section!"); OS << Symbol->getName() << ":\n"; } Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=74057&r1=74056&r2=74057&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Tue Jun 23 23:31:49 2009 @@ -44,6 +44,20 @@ return Entry = new (*this) MCSymbol(Atom, Name, false); } +/// GetOrCreateSymbol - Lookup the symbol inside with the specified +/// @param Name. If it exists, return it. If not, create a forward +/// reference and return it. +/// +/// @param Name - The symbol name, which must be unique across all symbols. +MCSymbol *MCContext::GetOrCreateSymbol(const char *Name) { + MCSymbol *&Entry = Symbols[Name]; + if (Entry) return Entry; + + // FIXME: is a null atom the right way to make a forward ref? + return Entry = new (*this) MCSymbol(0, Name, false); +} + + MCSymbol *MCContext::CreateTemporarySymbol(MCAtom *Atom, const char *Name) { // If unnamed, just create a symbol. if (Name[0] == '\0') Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=74057&r1=74056&r2=74057&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Tue Jun 23 23:31:49 2009 @@ -185,6 +185,12 @@ if (Lexer.Lex() == asmtok::Colon) { // identifier ':' -> Label. Lexer.Lex(); + + // Since we saw a label, create a symbol and emit it. + // FIXME: If the label starts with L it is an assembler temporary label. + // Why does the client of this api need to know this? + Out.EmitLabel(Ctx.GetOrCreateSymbol(IDVal)); + return ParseStatement(); } Modified: llvm/trunk/tools/llvm-mc/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.h?rev=74057&r1=74056&r2=74057&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.h (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.h Tue Jun 23 23:31:49 2009 @@ -17,17 +17,20 @@ #include "AsmLexer.h" namespace llvm { +class MCContext; class MCInst; class MCStreamer; class AsmParser { AsmLexer Lexer; + MCContext &Ctx; MCStreamer &Out; struct X86Operand; public: - AsmParser(SourceMgr &SM, MCStreamer &OutStr) : Lexer(SM), Out(OutStr) {} + AsmParser(SourceMgr &SM, MCContext &ctx, MCStreamer &OutStr) + : Lexer(SM), Ctx(ctx), Out(OutStr) {} ~AsmParser() {} bool Run(); Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=74057&r1=74056&r2=74057&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Tue Jun 23 23:31:49 2009 @@ -139,10 +139,9 @@ // it later. SrcMgr.setIncludeDirs(IncludeDirs); - // FIXME: don't leak streamer, own. MCContext Ctx; OwningPtr Str(createAsmStreamer(Ctx, outs())); - AsmParser Parser(SrcMgr, *Str.get()); + AsmParser Parser(SrcMgr, Ctx, *Str.get()); return Parser.Run(); } From sabre at nondot.org Tue Jun 23 23:43:34 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 04:43:34 -0000 Subject: [llvm-commits] [llvm] r74058 - in /llvm/trunk/tools/llvm-mc: AsmParser.cpp AsmParser.h Message-ID: <200906240443.n5O4hY9p018116@zion.cs.uiuc.edu> Author: lattner Date: Tue Jun 23 23:43:34 2009 New Revision: 74058 URL: http://llvm.org/viewvc/llvm-project?rev=74058&view=rev Log: add support for parsing and emitting .section directives. We can now parse things like: .section __TEXT,__cstring,cstring_literals Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp llvm/trunk/tools/llvm-mc/AsmParser.h Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=74058&r1=74057&r2=74058&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Tue Jun 23 23:43:34 2009 @@ -196,6 +196,10 @@ // Otherwise, we have a normal instruction or directive. if (IDVal[0] == '.') { + if (!strcmp(IDVal, ".section")) + return ParseDirectiveSection(); + + Lexer.PrintMessage(IDLoc, "warning: ignoring directive for now"); EatToEndOfStatement(); return false; @@ -207,7 +211,7 @@ return true; if (Lexer.isNot(asmtok::EndOfStatement)) - return TokError("unexpected token in operand list"); + return TokError("unexpected token in argument list"); // Eat the end of statement marker. Lexer.Lex(); @@ -219,3 +223,32 @@ // Skip to end of line for now. return false; } + +/// ParseDirectiveSection: +/// ::= .section identifier +bool AsmParser::ParseDirectiveSection() { + if (Lexer.isNot(asmtok::Identifier)) + return TokError("expected identifier after '.section' directive"); + + std::string Section = Lexer.getCurStrVal(); + Lexer.Lex(); + + // Accept a comma separated list of modifiers. + while (Lexer.is(asmtok::Comma)) { + Lexer.Lex(); + + if (Lexer.isNot(asmtok::Identifier)) + return TokError("expected identifier in '.section' directive"); + Section += ','; + Section += Lexer.getCurStrVal(); + Lexer.Lex(); + } + + if (Lexer.isNot(asmtok::EndOfStatement)) + return TokError("unexpected token in '.section' directive"); + Lexer.Lex(); + + Out.SwitchSection(Ctx.GetSection(Section.c_str())); + return false; +} + Modified: llvm/trunk/tools/llvm-mc/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.h?rev=74058&r1=74057&r2=74058&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.h (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.h Tue Jun 23 23:43:34 2009 @@ -52,6 +52,10 @@ bool ParseX86InstOperands(MCInst &Inst); bool ParseX86Operand(X86Operand &Op); bool ParseX86MemOperand(X86Operand &Op); + + // Directive Parsing. + bool ParseDirectiveSection(); + }; } // end namespace llvm From gohman at apple.com Tue Jun 23 23:47:54 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 04:47:54 -0000 Subject: [llvm-commits] [llvm] r74059 - /llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Message-ID: <200906240447.n5O4lsPY018233@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 23 23:47:54 2009 New Revision: 74059 URL: http://llvm.org/viewvc/llvm-project?rev=74059&view=rev Log: Remove an obsolete comment and fix some 80-column violations. Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=74059&r1=74058&r2=74059&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Tue Jun 23 23:47:54 2009 @@ -44,8 +44,8 @@ class SCEVUnknown; /// SCEV - This class represents an analyzed expression in the program. These - /// are reference-counted opaque objects that the client is not allowed to - /// do much with directly. + /// are opaque objects that the client is not allowed to do much with + /// directly. /// class SCEV { const unsigned SCEVType; // The SCEV baseclass this node corresponds to @@ -305,8 +305,9 @@ /// try to evaluate a few iterations of the loop until we get the exit /// condition gets a value of ExitWhen (true or false). If we cannot /// evaluate the trip count of the loop, return CouldNotCompute. - const SCEV* ComputeBackedgeTakenCountExhaustively(const Loop *L, Value *Cond, - bool ExitWhen); + const SCEV* ComputeBackedgeTakenCountExhaustively(const Loop *L, + Value *Cond, + bool ExitWhen); /// HowFarToZero - Return the number of times a backedge comparing the /// specified value to zero will execute. If not computable, return @@ -542,10 +543,11 @@ /// is deleted. void forgetLoopBackedgeTakenCount(const Loop *L); - /// GetMinTrailingZeros - Determine the minimum number of zero bits that S is - /// guaranteed to end in (at every loop iteration). It is, at the same time, - /// the minimum number of times S is divisible by 2. For example, given {4,+,8} - /// it returns 2. If S is guaranteed to be 0, it returns the bitwidth of S. + /// GetMinTrailingZeros - Determine the minimum number of zero bits that S + /// is guaranteed to end in (at every loop iteration). It is, at the same + /// time, the minimum number of times S is divisible by 2. For example, + /// given {4,+,8} it returns 2. If S is guaranteed to be 0, it returns the + /// bitwidth of S. uint32_t GetMinTrailingZeros(const SCEV* S); /// GetMinLeadingZeros - Determine the minimum number of zero bits that S is From gohman at apple.com Tue Jun 23 23:48:44 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 04:48:44 -0000 Subject: [llvm-commits] [llvm] r74060 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <200906240448.n5O4miCB018278@zion.cs.uiuc.edu> Author: djg Date: Tue Jun 23 23:48:43 2009 New Revision: 74060 URL: http://llvm.org/viewvc/llvm-project?rev=74060&view=rev Log: Delete some orphaned comments, fix some 80-column violations, and tidy up a few other formatting issues. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=74060&r1=74059&r2=74060&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Jun 23 23:48:43 2009 @@ -95,7 +95,8 @@ static cl::opt MaxBruteForceIterations("scalar-evolution-max-iterations", cl::ReallyHidden, cl::desc("Maximum number of iterations SCEV will " - "symbolically execute a constant derived loop"), + "symbolically execute a constant " + "derived loop"), cl::init(100)); static RegisterPass @@ -156,10 +157,11 @@ return false; } -const SCEV* SCEVCouldNotCompute:: -replaceSymbolicValuesWithConcrete(const SCEV* Sym, - const SCEV* Conc, - ScalarEvolution &SE) const { +const SCEV * +SCEVCouldNotCompute::replaceSymbolicValuesWithConcrete( + const SCEV *Sym, + const SCEV *Conc, + ScalarEvolution &SE) const { return this; } @@ -171,11 +173,6 @@ return S->getSCEVType() == scCouldNotCompute; } - -// SCEVConstants - Only allow the creation of one SCEVConstant for any -// particular value. Don't use a const SCEV* here, or else the object will -// never be deleted! - const SCEV* ScalarEvolution::getConstant(ConstantInt *V) { SCEVConstant *&R = SCEVConstants[V]; if (R == 0) R = new SCEVConstant(V); @@ -205,10 +202,6 @@ return Op->dominates(BB, DT); } -// SCEVTruncates - Only allow the creation of one SCEVTruncateExpr for any -// particular input. Don't use a const SCEV* here, or else the object will -// never be deleted! - SCEVTruncateExpr::SCEVTruncateExpr(const SCEV* op, const Type *ty) : SCEVCastExpr(scTruncate, op, ty) { assert((Op->getType()->isInteger() || isa(Op->getType())) && @@ -216,15 +209,10 @@ "Cannot truncate non-integer value!"); } - void SCEVTruncateExpr::print(raw_ostream &OS) const { OS << "(trunc " << *Op->getType() << " " << *Op << " to " << *Ty << ")"; } -// SCEVZeroExtends - Only allow the creation of one SCEVZeroExtendExpr for any -// particular input. Don't use a const SCEV* here, or else the object will never -// be deleted! - SCEVZeroExtendExpr::SCEVZeroExtendExpr(const SCEV* op, const Type *ty) : SCEVCastExpr(scZeroExtend, op, ty) { assert((Op->getType()->isInteger() || isa(Op->getType())) && @@ -236,10 +224,6 @@ OS << "(zext " << *Op->getType() << " " << *Op << " to " << *Ty << ")"; } -// SCEVSignExtends - Only allow the creation of one SCEVSignExtendExpr for any -// particular input. Don't use a const SCEV* here, or else the object will never -// be deleted! - SCEVSignExtendExpr::SCEVSignExtendExpr(const SCEV* op, const Type *ty) : SCEVCastExpr(scSignExtend, op, ty) { assert((Op->getType()->isInteger() || isa(Op->getType())) && @@ -251,10 +235,6 @@ OS << "(sext " << *Op->getType() << " " << *Op << " to " << *Ty << ")"; } -// SCEVCommExprs - Only allow the creation of one SCEVCommutativeExpr for any -// particular input. Don't use a const SCEV* here, or else the object will never -// be deleted! - void SCEVCommutativeExpr::print(raw_ostream &OS) const { assert(Operands.size() > 1 && "This plus expr shouldn't exist!"); const char *OpStr = getOperationStr(); @@ -264,10 +244,11 @@ OS << ")"; } -const SCEV* SCEVCommutativeExpr:: -replaceSymbolicValuesWithConcrete(const SCEV* Sym, - const SCEV* Conc, - ScalarEvolution &SE) const { +const SCEV * +SCEVCommutativeExpr::replaceSymbolicValuesWithConcrete( + const SCEV *Sym, + const SCEV *Conc, + ScalarEvolution &SE) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { const SCEV* H = getOperand(i)->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); @@ -304,11 +285,6 @@ return true; } - -// SCEVUDivs - Only allow the creation of one SCEVUDivExpr for any particular -// input. Don't use a const SCEV* here, or else the object will never be -// deleted! - bool SCEVUDivExpr::dominates(BasicBlock *BB, DominatorTree *DT) const { return LHS->dominates(BB, DT) && RHS->dominates(BB, DT); } @@ -326,14 +302,10 @@ return RHS->getType(); } -// SCEVAddRecExprs - Only allow the creation of one SCEVAddRecExpr for any -// particular input. Don't use a const SCEV* here, or else the object will never -// be deleted! - -const SCEV* SCEVAddRecExpr:: -replaceSymbolicValuesWithConcrete(const SCEV* Sym, - const SCEV* Conc, - ScalarEvolution &SE) const { +const SCEV * +SCEVAddRecExpr::replaceSymbolicValuesWithConcrete(const SCEV *Sym, + const SCEV *Conc, + ScalarEvolution &SE) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { const SCEV* H = getOperand(i)->replaceSymbolicValuesWithConcrete(Sym, Conc, SE); @@ -371,10 +343,6 @@ OS << "}<" << L->getHeader()->getName() + ">"; } -// SCEVUnknowns - Only allow the creation of one SCEVUnknown for any particular -// value. Don't use a const SCEV* here, or else the object will never be -// deleted! - bool SCEVUnknown::isLoopInvariant(const Loop *L) const { // All non-instruction values are loop invariant. All instructions are loop // invariant if they are not contained in the specified loop. @@ -589,7 +557,7 @@ // safe in modular arithmetic. // // However, this code doesn't use exactly that formula; the formula it uses - // is something like the following, where T is the number of factors of 2 in + // is something like the following, where T is the number of factors of 2 in // K! (i.e. trailing zeros in the binary representation of K!), and ^ is // exponentiation: // @@ -601,7 +569,7 @@ // arithmetic. To do exact division in modular arithmetic, all we have // to do is multiply by the inverse. Therefore, this step can be done at // width W. - // + // // The next issue is how to safely do the division by 2^T. The way this // is done is by doing the multiplication step at a width of at least W + T // bits. This way, the bottom W+T bits of the product are accurate. Then, @@ -1205,10 +1173,11 @@ Ops.clear(); if (AccumulatedConstant != 0) Ops.push_back(getConstant(AccumulatedConstant)); - for (std::map, APIntCompare>::iterator I = - MulOpLists.begin(), E = MulOpLists.end(); I != E; ++I) + for (std::map, APIntCompare>::iterator + I = MulOpLists.begin(), E = MulOpLists.end(); I != E; ++I) if (I->first != 0) - Ops.push_back(getMulExpr(getConstant(I->first), getAddExpr(I->second))); + Ops.push_back(getMulExpr(getConstant(I->first), + getAddExpr(I->second))); if (Ops.empty()) return getIntegerSCEV(0, Ty); if (Ops.size() == 1) @@ -1263,14 +1232,15 @@ // Fold X + (A*B*C) + (A*D*E) --> X + (A*(B*C+D*E)) const SCEV* InnerMul1 = Mul->getOperand(MulOp == 0); if (Mul->getNumOperands() != 2) { - SmallVector MulOps(Mul->op_begin(), Mul->op_end()); + SmallVector MulOps(Mul->op_begin(), + Mul->op_end()); MulOps.erase(MulOps.begin()+MulOp); InnerMul1 = getMulExpr(MulOps); } const SCEV* InnerMul2 = OtherMul->getOperand(OMulOp == 0); if (OtherMul->getNumOperands() != 2) { - SmallVector MulOps(OtherMul->op_begin(), - OtherMul->op_end()); + SmallVector MulOps(OtherMul->op_begin(), + OtherMul->op_end()); MulOps.erase(MulOps.begin()+OMulOp); InnerMul2 = getMulExpr(MulOps); } @@ -1336,7 +1306,8 @@ const SCEVAddRecExpr *OtherAddRec = cast(Ops[OtherIdx]); if (AddRec->getLoop() == OtherAddRec->getLoop()) { // Other + {A,+,B} + {C,+,D} --> Other + {A+C,+,B+D} - SmallVector NewOps(AddRec->op_begin(), AddRec->op_end()); + SmallVector NewOps(AddRec->op_begin(), + AddRec->op_end()); for (unsigned i = 0, e = OtherAddRec->getNumOperands(); i != e; ++i) { if (i >= NewOps.size()) { NewOps.insert(NewOps.end(), OtherAddRec->op_begin()+i, @@ -1400,7 +1371,7 @@ ++Idx; while (const SCEVConstant *RHSC = dyn_cast(Ops[Idx])) { // We found two constants, fold them together! - ConstantInt *Fold = ConstantInt::get(LHSC->getValue()->getValue() * + ConstantInt *Fold = ConstantInt::get(LHSC->getValue()->getValue() * RHSC->getValue()->getValue()); Ops[0] = getConstant(Fold); Ops.erase(Ops.begin()+1); // Erase the folded element @@ -1647,8 +1618,9 @@ /// getAddRecExpr - Get an add recurrence expression for the specified loop. /// Simplify the expression as much as possible. -const SCEV* ScalarEvolution::getAddRecExpr(SmallVectorImpl &Operands, - const Loop *L) { +const SCEV * +ScalarEvolution::getAddRecExpr(SmallVectorImpl &Operands, + const Loop *L) { if (Operands.size() == 1) return Operands[0]; #ifndef NDEBUG for (unsigned i = 1, e = Operands.size(); i != e; ++i) @@ -2119,9 +2091,10 @@ /// ReplaceSymbolicValueWithConcrete - This looks up the computed SCEV value for /// the specified instruction and replaces any references to the symbolic value /// SymName with the specified value. This is used during PHI resolution. -void ScalarEvolution:: -ReplaceSymbolicValueWithConcrete(Instruction *I, const SCEV* SymName, - const SCEV* NewVal) { +void +ScalarEvolution::ReplaceSymbolicValueWithConcrete(Instruction *I, + const SCEV *SymName, + const SCEV *NewVal) { std::map::iterator SI = Scalars.find(SCEVCallbackVH(I, this)); if (SI == Scalars.end()) return; @@ -2190,8 +2163,10 @@ if (Accum->isLoopInvariant(L) || (isa(Accum) && cast(Accum)->getLoop() == L)) { - const SCEV* StartVal = getSCEV(PN->getIncomingValue(IncomingEdge)); - const SCEV* PHISCEV = getAddRecExpr(StartVal, Accum, L); + const SCEV *StartVal = + getSCEV(PN->getIncomingValue(IncomingEdge)); + const SCEV *PHISCEV = + getAddRecExpr(StartVal, Accum, L); // Okay, for the entire analysis of this edge we assumed the PHI // to be symbolic. We now need to go back and update all of the @@ -2216,7 +2191,7 @@ // initial step of the addrec evolution. if (StartVal == getMinusSCEV(AddRec->getOperand(0), AddRec->getOperand(1))) { - const SCEV* PHISCEV = + const SCEV* PHISCEV = getAddRecExpr(StartVal, AddRec->getOperand(1), L); // Okay, for the entire analysis of this edge we assumed the PHI @@ -2788,7 +2763,8 @@ SmallVector Worklist; for (BasicBlock::iterator I = Header->begin(); PHINode *PN = dyn_cast(I); ++I) { - std::map::iterator It = Scalars.find((Value*)I); + std::map::iterator It = + Scalars.find((Value*)I); if (It != Scalars.end() && !isa(It->second)) Worklist.push_back(PN); } @@ -2850,7 +2826,7 @@ BranchInst *ExitBr = dyn_cast(ExitingBlock->getTerminator()); if (ExitBr == 0) return CouldNotCompute; assert(ExitBr->isConditional() && "If unconditional, it can't be in loop!"); - + // At this point, we know we have a conditional branch that determines whether // the loop is exited. However, we don't know if the branch is executed each // time through the loop. If not, then the execution count of the branch will @@ -3025,7 +3001,7 @@ LHS = getSCEVAtScope(LHS, L); RHS = getSCEVAtScope(RHS, L); - // At this point, we would like to compute how many iterations of the + // At this point, we would like to compute how many iterations of the // loop the predicate will return true for these inputs. if (LHS->isLoopInvariant(L) && !RHS->isLoopInvariant(L)) { // If there is a loop-invariant, force it into the RHS. @@ -3087,7 +3063,7 @@ if (ExitCond->getOperand(0)->getType()->isUnsigned()) errs() << "[unsigned] "; errs() << *LHS << " " - << Instruction::getOpcodeName(Instruction::ICmp) + << Instruction::getOpcodeName(Instruction::ICmp) << " " << *RHS << "\n"; #endif break; @@ -3143,10 +3119,12 @@ /// ComputeLoadConstantCompareBackedgeTakenCount - Given an exit condition of /// 'icmp op load X, cst', try to see if we can compute the backedge /// execution count. -const SCEV* ScalarEvolution:: -ComputeLoadConstantCompareBackedgeTakenCount(LoadInst *LI, Constant *RHS, - const Loop *L, - ICmpInst::Predicate predicate) { +const SCEV * +ScalarEvolution::ComputeLoadConstantCompareBackedgeTakenCount( + LoadInst *LI, + Constant *RHS, + const Loop *L, + ICmpInst::Predicate predicate) { if (LI->isVolatile()) return CouldNotCompute; // Check to see if the loaded pointer is a getelementptr of a global. @@ -3302,8 +3280,10 @@ /// in the header of its containing loop, we know the loop executes a /// constant number of times, and the PHI node is just a recurrence /// involving constants, fold it. -Constant *ScalarEvolution:: -getConstantEvolutionLoopExitValue(PHINode *PN, const APInt& BEs, const Loop *L){ +Constant * +ScalarEvolution::getConstantEvolutionLoopExitValue(PHINode *PN, + const APInt& BEs, + const Loop *L) { std::map::iterator I = ConstantEvolutionLoopExitValue.find(PN); if (I != ConstantEvolutionLoopExitValue.end()) @@ -3353,8 +3333,10 @@ /// try to evaluate a few iterations of the loop until we get the exit /// condition gets a value of ExitWhen (true or false). If we cannot /// evaluate the trip count of the loop, return CouldNotCompute. -const SCEV* ScalarEvolution:: -ComputeBackedgeTakenCountExhaustively(const Loop *L, Value *Cond, bool ExitWhen) { +const SCEV * +ScalarEvolution::ComputeBackedgeTakenCountExhaustively(const Loop *L, + Value *Cond, + bool ExitWhen) { PHINode *PN = getConstantEvolvingPHI(Cond, L); if (PN == 0) return CouldNotCompute; @@ -3490,7 +3472,7 @@ } } } - + Constant *C; if (const CmpInst *CI = dyn_cast(I)) C = ConstantFoldCompareInstOperands(CI->getPredicate(), @@ -3515,7 +3497,8 @@ if (OpAtScope != Comm->getOperand(i)) { // Okay, at least one of these operands is loop variant but might be // foldable. Build a new instance of the folded commutative expression. - SmallVector NewOps(Comm->op_begin(), Comm->op_begin()+i); + SmallVector NewOps(Comm->op_begin(), + Comm->op_begin()+i); NewOps.push_back(OpAtScope); for (++i; i != e; ++i) { @@ -3663,7 +3646,7 @@ APInt Two(BitWidth, 2); APInt Four(BitWidth, 4); - { + { using namespace APIntOps; const APInt& C = L; // Convert from chrec coefficients to polynomial coefficients AX^2+BX+C @@ -3683,7 +3666,7 @@ // integer value or else APInt::sqrt() will assert. APInt SqrtVal(SqrtTerm.sqrt()); - // Compute the two solutions for the quadratic formula. + // Compute the two solutions for the quadratic formula. // The divisions must be performed as signed divisions. APInt NegB(-B); APInt TwoA( A << 1 ); @@ -3695,7 +3678,7 @@ ConstantInt *Solution1 = ConstantInt::get((NegB + SqrtVal).sdiv(TwoA)); ConstantInt *Solution2 = ConstantInt::get((NegB - SqrtVal).sdiv(TwoA)); - return std::make_pair(SE.getConstant(Solution1), + return std::make_pair(SE.getConstant(Solution1), SE.getConstant(Solution2)); } // end APIntOps namespace } @@ -3727,8 +3710,10 @@ // where BW is the common bit width of Start and Step. // Get the initial value for the loop. - const SCEV* Start = getSCEVAtScope(AddRec->getStart(), L->getParentLoop()); - const SCEV* Step = getSCEVAtScope(AddRec->getOperand(1), L->getParentLoop()); + const SCEV *Start = getSCEVAtScope(AddRec->getStart(), + L->getParentLoop()); + const SCEV *Step = getSCEVAtScope(AddRec->getOperand(1), + L->getParentLoop()); if (const SCEVConstant *StepC = dyn_cast(Step)) { // For now we handle only constant steps. @@ -3759,7 +3744,7 @@ #endif // Pick the smallest positive root value. if (ConstantInt *CB = - dyn_cast(ConstantExpr::getICmp(ICmpInst::ICMP_ULT, + dyn_cast(ConstantExpr::getICmp(ICmpInst::ICMP_ULT, R1->getValue(), R2->getValue()))) { if (CB->getZExtValue() == false) std::swap(R1, R2); // R1 is the minimum root now. @@ -4021,9 +4006,9 @@ /// HowManyLessThans - Return the number of times a backedge containing the /// specified less-than comparison will execute. If not computable, return /// CouldNotCompute. -ScalarEvolution::BackedgeTakenInfo ScalarEvolution:: -HowManyLessThans(const SCEV *LHS, const SCEV *RHS, - const Loop *L, bool isSigned) { +ScalarEvolution::BackedgeTakenInfo +ScalarEvolution::HowManyLessThans(const SCEV *LHS, const SCEV *RHS, + const Loop *L, bool isSigned) { // Only handle: "ADDREC < LoopInvariant". if (!RHS->isLoopInvariant(L)) return CouldNotCompute; @@ -4073,7 +4058,7 @@ const SCEV* Start = AddRec->getOperand(0); // Determine the minimum constant start value. - const SCEV* MinStart = isa(Start) ? Start : + const SCEV *MinStart = isa(Start) ? Start : getConstant(isSigned ? APInt::getSignedMinValue(BitWidth) : APInt::getMinValue(BitWidth)); @@ -4116,7 +4101,7 @@ /// the condition, thus computing the exit count. If the iteration count can't /// be computed, an instance of SCEVCouldNotCompute is returned. const SCEV* SCEVAddRecExpr::getNumIterationsInRange(ConstantRange Range, - ScalarEvolution &SE) const { + ScalarEvolution &SE) const { if (Range.isFullSet()) // Infinite loop. return SE.getCouldNotCompute(); @@ -4175,7 +4160,7 @@ // Ensure that the previous value is in the range. This is a sanity check. assert(Range.contains( - EvaluateConstantChrecAtConstant(this, + EvaluateConstantChrecAtConstant(this, ConstantInt::get(ExitVal - One), SE)->getValue()) && "Linear scev computation is off in a bad way!"); return SE.getConstant(ExitValue); @@ -4196,7 +4181,7 @@ if (R1) { // Pick the smallest positive root value. if (ConstantInt *CB = - dyn_cast(ConstantExpr::getICmp(ICmpInst::ICMP_ULT, + dyn_cast(ConstantExpr::getICmp(ICmpInst::ICMP_ULT, R1->getValue(), R2->getValue()))) { if (CB->getZExtValue() == false) std::swap(R1, R2); // R1 is the minimum root now. @@ -4310,7 +4295,7 @@ BackedgeTakenCounts.clear(); ConstantEvolutionLoopExitValue.clear(); ValuesAtScopes.clear(); - + for (std::map::iterator I = SCEVConstants.begin(), E = SCEVConstants.end(); I != E; ++I) delete I->second; @@ -4340,7 +4325,7 @@ for (std::map::iterator I = SCEVUnknowns.begin(), E = SCEVUnknowns.end(); I != E; ++I) delete I->second; - + SCEVConstants.clear(); SCEVTruncates.clear(); SCEVZeroExtends.clear(); From sabre at nondot.org Wed Jun 24 00:13:15 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 05:13:15 -0000 Subject: [llvm-commits] [llvm] r74062 - in /llvm/trunk/tools/llvm-mc: AsmParser.cpp AsmParser.h Message-ID: <200906240513.n5O5DFQ3019168@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 00:13:15 2009 New Revision: 74062 URL: http://llvm.org/viewvc/llvm-project?rev=74062&view=rev Log: implement a bunch of synonyms for section switching. Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp llvm/trunk/tools/llvm-mc/AsmParser.h Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=74062&r1=74061&r2=74062&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Wed Jun 24 00:13:15 2009 @@ -196,8 +196,100 @@ // Otherwise, we have a normal instruction or directive. if (IDVal[0] == '.') { + // FIXME: This should be driven based on a hash lookup and callback. if (!strcmp(IDVal, ".section")) - return ParseDirectiveSection(); + return ParseDirectiveDarwinSection(); + if (!strcmp(IDVal, ".text")) + // FIXME: This changes behavior based on the -static flag to the + // assembler. + return ParseDirectiveSectionSwitch("__TEXT,__text", + "regular,pure_instructions"); + if (!strcmp(IDVal, ".const")) + return ParseDirectiveSectionSwitch("__TEXT,__const"); + if (!strcmp(IDVal, ".static_const")) + return ParseDirectiveSectionSwitch("__TEXT,__static_const"); + if (!strcmp(IDVal, ".cstring")) + return ParseDirectiveSectionSwitch("__TEXT,__cstring","cstring_literals"); + if (!strcmp(IDVal, ".literal4")) + return ParseDirectiveSectionSwitch("__TEXT,__literal4", "4byte_literals"); + if (!strcmp(IDVal, ".literal8")) + return ParseDirectiveSectionSwitch("__TEXT,__literal8", "8byte_literals"); + if (!strcmp(IDVal, ".literal16")) + return ParseDirectiveSectionSwitch("__TEXT,__literal16", + "16byte_literals"); + if (!strcmp(IDVal, ".constructor")) + return ParseDirectiveSectionSwitch("__TEXT,__constructor"); + if (!strcmp(IDVal, ".destructor")) + return ParseDirectiveSectionSwitch("__TEXT,__destructor"); + if (!strcmp(IDVal, ".fvmlib_init0")) + return ParseDirectiveSectionSwitch("__TEXT,__fvmlib_init0"); + if (!strcmp(IDVal, ".fvmlib_init1")) + return ParseDirectiveSectionSwitch("__TEXT,__fvmlib_init1"); + if (!strcmp(IDVal, ".symbol_stub")) // FIXME: Different on PPC. + return ParseDirectiveSectionSwitch("__IMPORT,__jump_table,symbol_stubs", + "self_modifying_code+pure_instructions,5"); + // FIXME: .picsymbol_stub on PPC. + if (!strcmp(IDVal, ".data")) + return ParseDirectiveSectionSwitch("__DATA,__data"); + if (!strcmp(IDVal, ".static_data")) + return ParseDirectiveSectionSwitch("__DATA,__static_data"); + if (!strcmp(IDVal, ".non_lazy_symbol_pointer")) + return ParseDirectiveSectionSwitch("__DATA,__nl_symbol_pointer", + "non_lazy_symbol_pointers"); + if (!strcmp(IDVal, ".lazy_symbol_pointer")) + return ParseDirectiveSectionSwitch("__DATA,__la_symbol_pointer", + "lazy_symbol_pointers"); + if (!strcmp(IDVal, ".dyld")) + return ParseDirectiveSectionSwitch("__DATA,__dyld"); + if (!strcmp(IDVal, ".mod_init_func")) + return ParseDirectiveSectionSwitch("__DATA,__mod_init_func", + "mod_init_funcs"); + if (!strcmp(IDVal, ".mod_term_func")) + return ParseDirectiveSectionSwitch("__DATA,__mod_term_func", + "mod_term_funcs"); + if (!strcmp(IDVal, ".const_data")) + return ParseDirectiveSectionSwitch("__DATA,__const", "regular"); + + + // FIXME: Verify attributes on sections. + if (!strcmp(IDVal, ".objc_class")) + return ParseDirectiveSectionSwitch("__OBJC,__class"); + if (!strcmp(IDVal, ".objc_meta_class")) + return ParseDirectiveSectionSwitch("__OBJC,__meta_class"); + if (!strcmp(IDVal, ".objc_cat_cls_meth")) + return ParseDirectiveSectionSwitch("__OBJC,__cat_cls_meth"); + if (!strcmp(IDVal, ".objc_cat_inst_meth")) + return ParseDirectiveSectionSwitch("__OBJC,__cat_inst_meth"); + if (!strcmp(IDVal, ".objc_protocol")) + return ParseDirectiveSectionSwitch("__OBJC,__protocol"); + if (!strcmp(IDVal, ".objc_string_object")) + return ParseDirectiveSectionSwitch("__OBJC,__string_object"); + if (!strcmp(IDVal, ".objc_cls_meth")) + return ParseDirectiveSectionSwitch("__OBJC,__cls_meth"); + if (!strcmp(IDVal, ".objc_inst_meth")) + return ParseDirectiveSectionSwitch("__OBJC,__inst_meth"); + if (!strcmp(IDVal, ".objc_cls_refs")) + return ParseDirectiveSectionSwitch("__OBJC,__cls_refs"); + if (!strcmp(IDVal, ".objc_message_refs")) + return ParseDirectiveSectionSwitch("__OBJC,__message_refs"); + if (!strcmp(IDVal, ".objc_symbols")) + return ParseDirectiveSectionSwitch("__OBJC,__symbols"); + if (!strcmp(IDVal, ".objc_category")) + return ParseDirectiveSectionSwitch("__OBJC,__category"); + if (!strcmp(IDVal, ".objc_class_vars")) + return ParseDirectiveSectionSwitch("__OBJC,__class_vars"); + if (!strcmp(IDVal, ".objc_instance_vars")) + return ParseDirectiveSectionSwitch("__OBJC,__instance_vars"); + if (!strcmp(IDVal, ".objc_module_info")) + return ParseDirectiveSectionSwitch("__OBJC,__module_info"); + if (!strcmp(IDVal, ".objc_class_names")) + return ParseDirectiveSectionSwitch("__TEXT,__cstring","cstring_literals"); + if (!strcmp(IDVal, ".objc_meth_var_types")) + return ParseDirectiveSectionSwitch("__TEXT,__cstring","cstring_literals"); + if (!strcmp(IDVal, ".objc_meth_var_names")) + return ParseDirectiveSectionSwitch("__TEXT,__cstring","cstring_literals"); + if (!strcmp(IDVal, ".objc_selector_strs")) + return ParseDirectiveSectionSwitch("__OBJC,__selector_strs"); Lexer.PrintMessage(IDLoc, "warning: ignoring directive for now"); @@ -225,8 +317,10 @@ } /// ParseDirectiveSection: -/// ::= .section identifier -bool AsmParser::ParseDirectiveSection() { +/// ::= .section identifier (',' identifier)* +/// FIXME: This should actually parse out the segment, section, attributes and +/// sizeof_stub fields. +bool AsmParser::ParseDirectiveDarwinSection() { if (Lexer.isNot(asmtok::Identifier)) return TokError("expected identifier after '.section' directive"); @@ -252,3 +346,18 @@ return false; } +bool AsmParser::ParseDirectiveSectionSwitch(const char *Section, + const char *Directives) { + if (Lexer.isNot(asmtok::EndOfStatement)) + return TokError("unexpected token in section switching directive"); + Lexer.Lex(); + + std::string SectionStr = Section; + if (Directives && Directives[0]) { + SectionStr += ","; + SectionStr += Directives; + } + + Out.SwitchSection(Ctx.GetSection(Section)); + return false; +} Modified: llvm/trunk/tools/llvm-mc/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.h?rev=74062&r1=74061&r2=74062&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.h (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.h Wed Jun 24 00:13:15 2009 @@ -54,7 +54,9 @@ bool ParseX86MemOperand(X86Operand &Op); // Directive Parsing. - bool ParseDirectiveSection(); + bool ParseDirectiveDarwinSection(); // Darwin specific ".section". + bool ParseDirectiveSectionSwitch(const char *Section, + const char *Directives = 0); }; From sabre at nondot.org Wed Jun 24 00:28:55 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 05:28:55 -0000 Subject: [llvm-commits] [llvm] r74064 - in /llvm/trunk/bindings/ocaml: analysis/Makefile bitreader/Makefile bitwriter/Makefile executionengine/Makefile llvm/Makefile target/Makefile Message-ID: <200906240528.n5O5StRQ019654@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 00:28:55 2009 New Revision: 74064 URL: http://llvm.org/viewvc/llvm-project?rev=74064&view=rev Log: remove dead makefile flags. Modified: llvm/trunk/bindings/ocaml/analysis/Makefile llvm/trunk/bindings/ocaml/bitreader/Makefile llvm/trunk/bindings/ocaml/bitwriter/Makefile llvm/trunk/bindings/ocaml/executionengine/Makefile llvm/trunk/bindings/ocaml/llvm/Makefile llvm/trunk/bindings/ocaml/target/Makefile Modified: llvm/trunk/bindings/ocaml/analysis/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/analysis/Makefile?rev=74064&r1=74063&r2=74064&view=diff ============================================================================== --- llvm/trunk/bindings/ocaml/analysis/Makefile (original) +++ llvm/trunk/bindings/ocaml/analysis/Makefile Wed Jun 24 00:28:55 2009 @@ -13,7 +13,6 @@ LEVEL := ../../.. LIBRARYNAME := llvm_analysis -DONT_BUILD_RELINKED := 1 UsedComponents := analysis UsedOcamlInterfaces := llvm Modified: llvm/trunk/bindings/ocaml/bitreader/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/bitreader/Makefile?rev=74064&r1=74063&r2=74064&view=diff ============================================================================== --- llvm/trunk/bindings/ocaml/bitreader/Makefile (original) +++ llvm/trunk/bindings/ocaml/bitreader/Makefile Wed Jun 24 00:28:55 2009 @@ -13,7 +13,6 @@ LEVEL := ../../.. LIBRARYNAME := llvm_bitreader -DONT_BUILD_RELINKED := 1 UsedComponents := bitreader UsedOcamlInterfaces := llvm Modified: llvm/trunk/bindings/ocaml/bitwriter/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/bitwriter/Makefile?rev=74064&r1=74063&r2=74064&view=diff ============================================================================== --- llvm/trunk/bindings/ocaml/bitwriter/Makefile (original) +++ llvm/trunk/bindings/ocaml/bitwriter/Makefile Wed Jun 24 00:28:55 2009 @@ -13,7 +13,6 @@ LEVEL := ../../.. LIBRARYNAME := llvm_bitwriter -DONT_BUILD_RELINKED := 1 UsedComponents := bitwriter UsedOcamlInterfaces := llvm Modified: llvm/trunk/bindings/ocaml/executionengine/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/executionengine/Makefile?rev=74064&r1=74063&r2=74064&view=diff ============================================================================== --- llvm/trunk/bindings/ocaml/executionengine/Makefile (original) +++ llvm/trunk/bindings/ocaml/executionengine/Makefile Wed Jun 24 00:28:55 2009 @@ -13,7 +13,6 @@ LEVEL := ../../.. LIBRARYNAME := llvm_executionengine -DONT_BUILD_RELINKED := 1 UsedComponents := executionengine jit interpreter native UsedOcamlInterfaces := llvm llvm_target Modified: llvm/trunk/bindings/ocaml/llvm/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/llvm/Makefile?rev=74064&r1=74063&r2=74064&view=diff ============================================================================== --- llvm/trunk/bindings/ocaml/llvm/Makefile (original) +++ llvm/trunk/bindings/ocaml/llvm/Makefile Wed Jun 24 00:28:55 2009 @@ -13,7 +13,6 @@ LEVEL := ../../.. LIBRARYNAME := llvm -DONT_BUILD_RELINKED := 1 UsedComponents := core UsedOcamLibs := llvm Modified: llvm/trunk/bindings/ocaml/target/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/target/Makefile?rev=74064&r1=74063&r2=74064&view=diff ============================================================================== --- llvm/trunk/bindings/ocaml/target/Makefile (original) +++ llvm/trunk/bindings/ocaml/target/Makefile Wed Jun 24 00:28:55 2009 @@ -13,7 +13,6 @@ LEVEL := ../../.. LIBRARYNAME := llvm_target -DONT_BUILD_RELINKED := 1 UsedComponents := target UsedOcamlInterfaces := llvm From sabre at nondot.org Wed Jun 24 00:29:56 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 05:29:56 -0000 Subject: [llvm-commits] [llvm] r74065 - in /llvm/trunk: lib/CodeGen/AsmPrinter/Makefile lib/CodeGen/SelectionDAG/Makefile projects/sample/lib/sample/Makefile tools/gold/Makefile tools/lto/Makefile Message-ID: <200906240529.n5O5TuZG019702@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 00:29:56 2009 New Revision: 74065 URL: http://llvm.org/viewvc/llvm-project?rev=74065&view=rev Log: remove dead makefile flags. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/Makefile llvm/trunk/lib/CodeGen/SelectionDAG/Makefile llvm/trunk/projects/sample/lib/sample/Makefile llvm/trunk/tools/gold/Makefile llvm/trunk/tools/lto/Makefile Modified: llvm/trunk/lib/CodeGen/AsmPrinter/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/Makefile?rev=74065&r1=74064&r2=74065&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/Makefile (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/Makefile Wed Jun 24 00:29:56 2009 @@ -9,7 +9,5 @@ LEVEL = ../../.. LIBRARYNAME = LLVMAsmPrinter PARALLEL_DIRS = -BUILD_ARCHIVE = 1 -DONT_BUILD_RELINKED = 1 include $(LEVEL)/Makefile.common Modified: llvm/trunk/lib/CodeGen/SelectionDAG/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/Makefile?rev=74065&r1=74064&r2=74065&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/Makefile (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/Makefile Wed Jun 24 00:29:56 2009 @@ -9,7 +9,5 @@ LEVEL = ../../.. LIBRARYNAME = LLVMSelectionDAG PARALLEL_DIRS = -BUILD_ARCHIVE = 1 -DONT_BUILD_RELINKED = 1 include $(LEVEL)/Makefile.common Modified: llvm/trunk/projects/sample/lib/sample/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/lib/sample/Makefile?rev=74065&r1=74064&r2=74065&view=diff ============================================================================== --- llvm/trunk/projects/sample/lib/sample/Makefile (original) +++ llvm/trunk/projects/sample/lib/sample/Makefile Wed Jun 24 00:29:56 2009 @@ -9,8 +9,6 @@ # Give the name of a library. This will build a dynamic version. # LIBRARYNAME=sample -DONT_BUILD_RELINKED=1 -BUILD_ARCHIVE=1 # # Include Makefile.common so we know what to do. Modified: llvm/trunk/tools/gold/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/Makefile?rev=74065&r1=74064&r2=74065&view=diff ============================================================================== --- llvm/trunk/tools/gold/Makefile (original) +++ llvm/trunk/tools/gold/Makefile Wed Jun 24 00:29:56 2009 @@ -18,7 +18,6 @@ LINK_LIBS_IN_SHARED=1 SHARED_LIBRARY = 1 BUILD_ARCHIVE = 0 -DONT_BUILD_RELINKED = 1 LINK_COMPONENTS := LIBS += -llto Modified: llvm/trunk/tools/lto/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/Makefile?rev=74065&r1=74064&r2=74065&view=diff ============================================================================== --- llvm/trunk/tools/lto/Makefile (original) +++ llvm/trunk/tools/lto/Makefile Wed Jun 24 00:29:56 2009 @@ -17,7 +17,6 @@ LINK_LIBS_IN_SHARED = 1 SHARED_LIBRARY = 1 -DONT_BUILD_RELINKED = 1 LINK_COMPONENTS := $(TARGETS_TO_BUILD) ipo scalaropts linker bitreader bitwriter From sabre at nondot.org Wed Jun 24 00:46:28 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 05:46:28 -0000 Subject: [llvm-commits] [llvm] r74066 - in /llvm/trunk/lib/Target/X86/AsmPrinter: X86ATTAsmPrinter.cpp X86ATTAsmPrinter.h Message-ID: <200906240546.n5O5kSfW020208@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 00:46:28 2009 New Revision: 74066 URL: http://llvm.org/viewvc/llvm-project?rev=74066&view=rev Log: wire up support for MCContext/MCStreamer in -experimental-asm-printer mode. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74066&r1=74065&r2=74066&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 00:46:28 2009 @@ -26,7 +26,9 @@ #include "llvm/Type.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/MC/MCContext.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCStreamer.h" #include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/Support/CommandLine.h" @@ -933,6 +935,14 @@ bool X86ATTAsmPrinter::doInitialization(Module &M) { if (TAI->doesSupportDebugInformation() || TAI->doesSupportExceptionHandling()) MMI = getAnalysisIfAvailable(); + + if (NewAsmPrinter) { + Context = new MCContext(); + // FIXME: Send this to "O" instead of outs(). For now, we force it to + // stdout to make it easy to compare. + Streamer = createAsmStreamer(*Context, outs()); + } + return AsmPrinter::doInitialization(M); } @@ -1214,6 +1224,15 @@ DW->EndModule(); } + if (NewAsmPrinter) { + Streamer->Finish(); + + delete Streamer; + delete Context; + Streamer = 0; + Context = 0; + } + return AsmPrinter::doFinalization(M); } Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=74066&r1=74065&r2=74066&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Wed Jun 24 00:46:28 2009 @@ -27,17 +27,24 @@ namespace llvm { class MachineJumpTableInfo; +class MCContext; class MCInst; +class MCStreamer; class VISIBILITY_HIDDEN X86ATTAsmPrinter : public AsmPrinter { MachineModuleInfo *MMI; const X86Subtarget *Subtarget; + + MCContext *Context; + MCStreamer *Streamer; public: explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM, const TargetAsmInfo *T, CodeGenOpt::Level OL, bool V) : AsmPrinter(O, TM, T, OL, V), MMI(0) { Subtarget = &TM.getSubtarget(); + Context = 0; + Streamer = 0; } virtual const char *getPassName() const { From sabre at nondot.org Wed Jun 24 00:48:00 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 05:48:00 -0000 Subject: [llvm-commits] [llvm] r74067 - /llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Message-ID: <200906240548.n5O5m0Be020267@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 00:47:59 2009 New Revision: 74067 URL: http://llvm.org/viewvc/llvm-project?rev=74067&view=rev Log: factor some code better. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74067&r1=74066&r2=74067&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 00:47:59 2009 @@ -1195,10 +1195,6 @@ printHiddenGVStub(i->getKeyData()); } - // Emit final debug information. - if (TAI->doesSupportDebugInformation() || TAI->doesSupportExceptionHandling()) - DW->EndModule(); - // Funny Darwin hack: This flag tells the linker that no global symbols // contain code that falls through to other global symbols (e.g. the obvious // implementation of multiple entry points). If this doesn't occur, the @@ -1214,16 +1210,13 @@ << ";\t.type\t" << (COFF::DT_FCN << COFF::N_BTSHFT) << ";\t.endef\n"; } - - // Emit final debug information. - if (TAI->doesSupportDebugInformation() || TAI->doesSupportExceptionHandling()) - DW->EndModule(); - } else if (Subtarget->isTargetELF()) { - // Emit final debug information. - if (TAI->doesSupportDebugInformation() || TAI->doesSupportExceptionHandling()) - DW->EndModule(); } - + + // Emit final debug information. + if (TAI->doesSupportDebugInformation() || TAI->doesSupportExceptionHandling()) + DW->EndModule(); + + if (NewAsmPrinter) { Streamer->Finish(); From clattner at apple.com Wed Jun 24 01:11:23 2009 From: clattner at apple.com (Chris Lattner) Date: Tue, 23 Jun 2009 23:11:23 -0700 Subject: [llvm-commits] Patch to allow the JITMemoryManager to allocate more blocks of memory In-Reply-To: <9a9942200906231705m4ec42d3drabd014f740867f28@mail.gmail.com> References: <9a9942200906231656r3fd098c6r9e3e53dffe7cf790@mail.gmail.com> <9a9942200906231659x2b73f65ap51207eb5eef56129@mail.gmail.com> <9a9942200906231705m4ec42d3drabd014f740867f28@mail.gmail.com> Message-ID: <718901DE-2AFB-4323-8204-4674B5F46B62@apple.com> On Jun 23, 2009, at 5:05 PM, Reid Kleckner wrote: > And of course I meant to attach the patch, goshdurnit. Have you run through the llvm testsuite with the initial threshold cranked way down? This would cause the test suite to check out whether the reallocation stuff is working. If that works, it looks good to me. -Chris > > Reid > > On Tue, Jun 23, 2009 at 4:59 PM, Reid Kleckner wrote: >> I meant to send this to llvm-commits at cs.uiuc.edu: >> >> On Tue, Jun 23, 2009 at 4:56 PM, Reid Kleckner wrote: >>> Hey all, >>> >>> I'm working on unladen-swallow, and our regression tests currently >>> fail halfway through because the DefaultJITMemoryManager doesn't >>> allocate more memory when it runs out of space. This patch fixes >>> that >>> by retrying and asking for twice as much space, which the memory >>> manager uses to allocate a new slab of memory. >>> >>> I ran it by Jeff Yasskin and Nick Lewycky here: >>> http://codereview.appspot.com/71042 >>> >>> The patch is attached. >>> >>> Reid >>> >> > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Wed Jun 24 01:36:08 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 24 Jun 2009 06:36:08 -0000 Subject: [llvm-commits] [llvm] r74068 - in /llvm/trunk/test/CodeGen: ARM/ Thumb/ Thumb2/ Message-ID: <200906240636.n5O6a96U022051@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 24 01:36:07 2009 New Revision: 74068 URL: http://llvm.org/viewvc/llvm-project?rev=74068&view=rev Log: Move thumb and thumb2 tests into separate directories. Added: llvm/trunk/test/CodeGen/Thumb/ llvm/trunk/test/CodeGen/Thumb/2007-01-31-RegInfoAssert.ll - copied unchanged from r74067, llvm/trunk/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll llvm/trunk/test/CodeGen/Thumb/2007-02-02-JoinIntervalsCrash.ll - copied unchanged from r74067, llvm/trunk/test/CodeGen/ARM/2007-02-02-JoinIntervalsCrash.ll llvm/trunk/test/CodeGen/Thumb/2007-03-06-AddR7.ll - copied unchanged from r74067, llvm/trunk/test/CodeGen/ARM/2007-03-06-AddR7.ll llvm/trunk/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll - copied unchanged from r74067, llvm/trunk/test/CodeGen/ARM/2007-05-05-InvalidPushPop.ll llvm/trunk/test/CodeGen/Thumb/2009-06-18-ThumbCommuteMul.ll - copied unchanged from r74067, llvm/trunk/test/CodeGen/ARM/2009-06-18-ThumbCommuteMul.ll llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll llvm/trunk/test/CodeGen/Thumb/fpconv.ll llvm/trunk/test/CodeGen/Thumb/fpow.ll llvm/trunk/test/CodeGen/Thumb/frame_thumb.ll - copied, changed from r74067, llvm/trunk/test/CodeGen/ARM/frame_thumb.ll llvm/trunk/test/CodeGen/Thumb/iabs.ll llvm/trunk/test/CodeGen/Thumb/inlineasm-imm-thumb.ll - copied unchanged from r74067, llvm/trunk/test/CodeGen/ARM/inlineasm-imm-thumb.ll llvm/trunk/test/CodeGen/Thumb/ispositive.ll llvm/trunk/test/CodeGen/Thumb/large-stack.ll llvm/trunk/test/CodeGen/Thumb/ldr_ext.ll llvm/trunk/test/CodeGen/Thumb/ldr_frame.ll llvm/trunk/test/CodeGen/Thumb/long-setcc.ll llvm/trunk/test/CodeGen/Thumb/long.ll llvm/trunk/test/CodeGen/Thumb/select.ll llvm/trunk/test/CodeGen/Thumb/stack-frame.ll llvm/trunk/test/CodeGen/Thumb/thumb-imm.ll - copied unchanged from r74067, llvm/trunk/test/CodeGen/ARM/thumb-imm.ll llvm/trunk/test/CodeGen/Thumb/tst_teq.ll llvm/trunk/test/CodeGen/Thumb/unord.ll llvm/trunk/test/CodeGen/Thumb/vargs.ll - copied, changed from r74067, llvm/trunk/test/CodeGen/ARM/vargs2.ll llvm/trunk/test/CodeGen/Thumb2/ llvm/trunk/test/CodeGen/Thumb2/thumb2-add.ll - copied unchanged from r74060, llvm/trunk/test/CodeGen/ARM/thumb2-add.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-mov.ll - copied unchanged from r74060, llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-mov2.ll - copied unchanged from r74060, llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-shifter.ll - copied unchanged from r74067, llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll Removed: llvm/trunk/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll llvm/trunk/test/CodeGen/ARM/2007-02-02-JoinIntervalsCrash.ll llvm/trunk/test/CodeGen/ARM/2007-03-06-AddR7.ll llvm/trunk/test/CodeGen/ARM/2007-05-05-InvalidPushPop.ll llvm/trunk/test/CodeGen/ARM/2009-06-18-ThumbCommuteMul.ll llvm/trunk/test/CodeGen/ARM/frame_thumb.ll llvm/trunk/test/CodeGen/ARM/inlineasm-imm-thumb.ll llvm/trunk/test/CodeGen/ARM/thumb-imm.ll llvm/trunk/test/CodeGen/ARM/thumb2-add.ll llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll llvm/trunk/test/CodeGen/ARM/vargs2.ll Modified: llvm/trunk/test/CodeGen/ARM/dyn-stackalloc.ll llvm/trunk/test/CodeGen/ARM/fpconv.ll llvm/trunk/test/CodeGen/ARM/fpow.ll llvm/trunk/test/CodeGen/ARM/iabs.ll llvm/trunk/test/CodeGen/ARM/ispositive.ll llvm/trunk/test/CodeGen/ARM/large-stack.ll llvm/trunk/test/CodeGen/ARM/ldr_ext.ll llvm/trunk/test/CodeGen/ARM/ldr_frame.ll llvm/trunk/test/CodeGen/ARM/long-setcc.ll llvm/trunk/test/CodeGen/ARM/long.ll llvm/trunk/test/CodeGen/ARM/long_shift.ll llvm/trunk/test/CodeGen/ARM/mul.ll llvm/trunk/test/CodeGen/ARM/select.ll llvm/trunk/test/CodeGen/ARM/stack-frame.ll llvm/trunk/test/CodeGen/ARM/tst_teq.ll llvm/trunk/test/CodeGen/ARM/unord.ll Removed: llvm/trunk/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll?rev=74067&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll (removed) @@ -1,16 +0,0 @@ -; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin - -%struct.rtx_def = type { i8 } - at str = external global [7 x i8] - -define void @f1() { - %D = alloca %struct.rtx_def, align 1 - %tmp1 = bitcast %struct.rtx_def* %D to i32* - %tmp7 = load i32* %tmp1 - %tmp14 = lshr i32 %tmp7, 1 - %tmp1415 = and i32 %tmp14, 1 - call void (i32, ...)* @printf( i32 undef, i32 0, i32 %tmp1415 ) - ret void -} - -declare void @printf(i32, ...) Removed: llvm/trunk/test/CodeGen/ARM/2007-02-02-JoinIntervalsCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-02-02-JoinIntervalsCrash.ll?rev=74067&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2007-02-02-JoinIntervalsCrash.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2007-02-02-JoinIntervalsCrash.ll (removed) @@ -1,27 +0,0 @@ -; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin - - %struct.color_sample = type { i32 } - %struct.ref = type { %struct.color_sample, i16, i16 } - -define void @zcvrs() { - br i1 false, label %bb22, label %UnifiedReturnBlock - -bb22: - br i1 false, label %bb64, label %UnifiedReturnBlock - -bb64: - %tmp67 = urem i32 0, 0 - %tmp69 = icmp slt i32 %tmp67, 10 - %iftmp.13.0 = select i1 %tmp69, i8 48, i8 55 - %tmp75 = add i8 %iftmp.13.0, 0 - store i8 %tmp75, i8* null - %tmp81 = udiv i32 0, 0 - %tmp83 = icmp eq i32 %tmp81, 0 - br i1 %tmp83, label %bb85, label %bb64 - -bb85: - ret void - -UnifiedReturnBlock: - ret void -} Removed: llvm/trunk/test/CodeGen/ARM/2007-03-06-AddR7.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-03-06-AddR7.ll?rev=74067&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2007-03-06-AddR7.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2007-03-06-AddR7.ll (removed) @@ -1,117 +0,0 @@ -; RUN: llvm-as < %s | llc -march=thumb -; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin -relocation-model=pic \ -; RUN: -mattr=+v6,+vfp2 | not grep {add r., r7, #2 \\* 4} - - %struct.__fooAllocator = type opaque - %struct.__fooY = type { %struct.fooXBase, %struct.__fooString*, %struct.__fooU*, %struct.__fooV*, i8** } - %struct.__fooZ = type opaque - %struct.__fooU = type opaque - %struct.__fooString = type opaque - %struct.__fooV = type opaque - %struct.fooXBase = type { i32, [4 x i8] } - %struct.fooXClass = type { i32, i8*, void (i8*)*, i8* (%struct.__fooAllocator*, i8*)*, void (i8*)*, i8 (i8*, i8*) zeroext *, i32 (i8*)*, %struct.__fooString* (i8*, %struct.__fooZ*)*, %struct.__fooString* (i8*)* } - %struct.aa_cache = type { i32, i32, [1 x %struct.aa_method*] } - %struct.aa_class = type { %struct.aa_class*, %struct.aa_class*, i8*, i32, i32, i32, %struct.aa_ivar_list*, %struct.aa_method_list**, %struct.aa_cache*, %struct.aa_protocol_list* } - %struct.aa_ivar = type { i8*, i8*, i32 } - %struct.aa_ivar_list = type { i32, [1 x %struct.aa_ivar] } - %struct.aa_method = type { %struct.aa_ss*, i8*, %struct.aa_object* (%struct.aa_object*, %struct.aa_ss*, ...)* } - %struct.aa_method_list = type { %struct.aa_method_list*, i32, [1 x %struct.aa_method] } - %struct.aa_object = type { %struct.aa_class* } - %struct.aa_protocol_list = type { %struct.aa_protocol_list*, i32, [1 x %struct.aa_object*] } - %struct.aa_ss = type opaque - at __kfooYTypeID = external global i32 ; [#uses=3] - at __fooYClass = external constant %struct.fooXClass ; <%struct.fooXClass*> [#uses=1] - at __fooXClassTableSize = external global i32 ; [#uses=1] - at __fooXAaClassTable = external global i32* ; [#uses=1] - at s.10319 = external global %struct.aa_ss* ; <%struct.aa_ss**> [#uses=2] - at str15 = external constant [24 x i8] ; <[24 x i8]*> [#uses=1] - - -define i8 @test(%struct.__fooY* %calendar, double* %atp, i8* %componentDesc, ...) zeroext { -entry: - %args = alloca i8*, align 4 ; [#uses=5] - %args4 = bitcast i8** %args to i8* ; [#uses=2] - call void @llvm.va_start( i8* %args4 ) - %tmp6 = load i32* @__kfooYTypeID ; [#uses=1] - icmp eq i32 %tmp6, 0 ; :0 [#uses=1] - br i1 %0, label %cond_true, label %cond_next - -cond_true: ; preds = %entry - %tmp7 = call i32 @_fooXRegisterClass( %struct.fooXClass* @__fooYClass ) ; [#uses=1] - store i32 %tmp7, i32* @__kfooYTypeID - br label %cond_next - -cond_next: ; preds = %cond_true, %entry - %tmp8 = load i32* @__kfooYTypeID ; [#uses=2] - %tmp15 = load i32* @__fooXClassTableSize ; [#uses=1] - icmp ugt i32 %tmp15, %tmp8 ; :1 [#uses=1] - br i1 %1, label %cond_next18, label %cond_true58 - -cond_next18: ; preds = %cond_next - %tmp21 = getelementptr %struct.__fooY* %calendar, i32 0, i32 0, i32 0 ; [#uses=1] - %tmp22 = load i32* %tmp21 ; [#uses=2] - %tmp29 = load i32** @__fooXAaClassTable ; [#uses=1] - %tmp31 = getelementptr i32* %tmp29, i32 %tmp8 ; [#uses=1] - %tmp32 = load i32* %tmp31 ; [#uses=1] - icmp eq i32 %tmp22, %tmp32 ; :2 [#uses=1] - %.not = xor i1 %2, true ; [#uses=1] - icmp ugt i32 %tmp22, 4095 ; :3 [#uses=1] - %bothcond = and i1 %.not, %3 ; [#uses=1] - br i1 %bothcond, label %cond_true58, label %bb48 - -bb48: ; preds = %cond_next18 - %tmp78 = call i32 @strlen( i8* %componentDesc ) ; [#uses=4] - %tmp92 = alloca i32, i32 %tmp78 ; [#uses=2] - icmp sgt i32 %tmp78, 0 ; :4 [#uses=1] - br i1 %4, label %cond_true111, label %bb114 - -cond_true58: ; preds = %cond_next18, %cond_next - %tmp59 = load %struct.aa_ss** @s.10319 ; <%struct.aa_ss*> [#uses=2] - icmp eq %struct.aa_ss* %tmp59, null ; :5 [#uses=1] - %tmp6869 = bitcast %struct.__fooY* %calendar to i8* ; [#uses=2] - br i1 %5, label %cond_true60, label %cond_next64 - -cond_true60: ; preds = %cond_true58 - %tmp63 = call %struct.aa_ss* @sel_registerName( i8* getelementptr ([24 x i8]* @str15, i32 0, i32 0) ) ; <%struct.aa_ss*> [#uses=2] - store %struct.aa_ss* %tmp63, %struct.aa_ss** @s.10319 - %tmp66137 = volatile load i8** %args ; [#uses=1] - %tmp73138 = call i8 (i8*, %struct.aa_ss*, ...) zeroext * bitcast (%struct.aa_object* (%struct.aa_object*, %struct.aa_ss*, ...)* @aa_mm to i8 (i8*, %struct.aa_ss*, ...) zeroext *)( i8* %tmp6869, %struct.aa_ss* %tmp63, double* %atp, i8* %componentDesc, i8* %tmp66137) zeroext ; [#uses=1] - ret i8 %tmp73138 - -cond_next64: ; preds = %cond_true58 - %tmp66 = volatile load i8** %args ; [#uses=1] - %tmp73 = call i8 (i8*, %struct.aa_ss*, ...) zeroext * bitcast (%struct.aa_object* (%struct.aa_object*, %struct.aa_ss*, ...)* @aa_mm to i8 (i8*, %struct.aa_ss*, ...) zeroext *)( i8* %tmp6869, %struct.aa_ss* %tmp59, double* %atp, i8* %componentDesc, i8* %tmp66 ) zeroext ; [#uses=1] - ret i8 %tmp73 - -cond_true111: ; preds = %cond_true111, %bb48 - %idx.2132.0 = phi i32 [ 0, %bb48 ], [ %indvar.next, %cond_true111 ] ; [#uses=2] - %tmp95 = volatile load i8** %args ; [#uses=2] - %tmp97 = getelementptr i8* %tmp95, i32 4 ; [#uses=1] - volatile store i8* %tmp97, i8** %args - %tmp9899 = bitcast i8* %tmp95 to i32* ; [#uses=1] - %tmp100 = load i32* %tmp9899 ; [#uses=1] - %tmp104 = getelementptr i32* %tmp92, i32 %idx.2132.0 ; [#uses=1] - store i32 %tmp100, i32* %tmp104 - %indvar.next = add i32 %idx.2132.0, 1 ; [#uses=2] - icmp eq i32 %indvar.next, %tmp78 ; :6 [#uses=1] - br i1 %6, label %bb114, label %cond_true111 - -bb114: ; preds = %cond_true111, %bb48 - call void @llvm.va_end( i8* %args4 ) - %tmp122 = call i8 @_fooYCCV( %struct.__fooY* %calendar, double* %atp, i8* %componentDesc, i32* %tmp92, i32 %tmp78 ) zeroext ; [#uses=1] - ret i8 %tmp122 -} - -declare i32 @_fooXRegisterClass(%struct.fooXClass*) - -declare i8 @_fooYCCV(%struct.__fooY*, double*, i8*, i32*, i32) zeroext - -declare %struct.aa_object* @aa_mm(%struct.aa_object*, %struct.aa_ss*, ...) - -declare %struct.aa_ss* @sel_registerName(i8*) - -declare void @llvm.va_start(i8*) - -declare i32 @strlen(i8*) - -declare void @llvm.va_end(i8*) Removed: llvm/trunk/test/CodeGen/ARM/2007-05-05-InvalidPushPop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-05-05-InvalidPushPop.ll?rev=74067&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2007-05-05-InvalidPushPop.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2007-05-05-InvalidPushPop.ll (removed) @@ -1,41 +0,0 @@ -; RUN: llvm-as < %s | llc | not grep r11 - -target triple = "thumb-linux-gnueabi" - %struct.__sched_param = type { i32 } - %struct.pthread_attr_t = type { i32, i32, %struct.__sched_param, i32, i32, i32, i32, i8*, i32 } - at i.1882 = internal global i32 1 ; [#uses=2] - at .str = internal constant [14 x i8] c"Thread 1: %d\0A\00" ; <[14 x i8]*> [#uses=1] - at .str1 = internal constant [14 x i8] c"Thread 2: %d\0A\00" ; <[14 x i8]*> [#uses=1] - -define i8* @f(i8* %a) { -entry: - %tmp1 = load i32* @i.1882 ; [#uses=1] - %tmp2 = add i32 %tmp1, 1 ; [#uses=2] - store i32 %tmp2, i32* @i.1882 - %tmp34 = inttoptr i32 %tmp2 to i8* ; [#uses=1] - ret i8* %tmp34 -} - -define i32 @main() { -entry: - %t = alloca i32, align 4 ; [#uses=4] - %ret = alloca i32, align 4 ; [#uses=3] - %tmp1 = call i32 @pthread_create( i32* %t, %struct.pthread_attr_t* null, i8* (i8*)* @f, i8* null ) ; [#uses=0] - %tmp2 = load i32* %t ; [#uses=1] - %ret3 = bitcast i32* %ret to i8** ; [#uses=2] - %tmp4 = call i32 @pthread_join( i32 %tmp2, i8** %ret3 ) ; [#uses=0] - %tmp5 = load i32* %ret ; [#uses=1] - %tmp7 = call i32 (i8*, ...)* @printf( i8* getelementptr ([14 x i8]* @.str, i32 0, i32 0), i32 %tmp5 ) ; [#uses=0] - %tmp8 = call i32 @pthread_create( i32* %t, %struct.pthread_attr_t* null, i8* (i8*)* @f, i8* null ) ; [#uses=0] - %tmp9 = load i32* %t ; [#uses=1] - %tmp11 = call i32 @pthread_join( i32 %tmp9, i8** %ret3 ) ; [#uses=0] - %tmp12 = load i32* %ret ; [#uses=1] - %tmp14 = call i32 (i8*, ...)* @printf( i8* getelementptr ([14 x i8]* @.str1, i32 0, i32 0), i32 %tmp12 ) ; [#uses=0] - ret i32 0 -} - -declare i32 @pthread_create(i32*, %struct.pthread_attr_t*, i8* (i8*)*, i8*) - -declare i32 @pthread_join(i32, i8**) - -declare i32 @printf(i8*, ...) Removed: llvm/trunk/test/CodeGen/ARM/2009-06-18-ThumbCommuteMul.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-06-18-ThumbCommuteMul.ll?rev=74067&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-06-18-ThumbCommuteMul.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-06-18-ThumbCommuteMul.ll (removed) @@ -1,8 +0,0 @@ -; RUN: llvm-as < %s | llc -march=thumb | grep r0 | count 1 - -define i32 @a(i32 %x, i32 %y) nounwind readnone { -entry: - %mul = mul i32 %y, %x ; [#uses=1] - ret i32 %mul -} - Modified: llvm/trunk/test/CodeGen/ARM/dyn-stackalloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/dyn-stackalloc.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/dyn-stackalloc.ll (original) +++ llvm/trunk/test/CodeGen/ARM/dyn-stackalloc.ll Wed Jun 24 01:36:07 2009 @@ -1,8 +1,4 @@ ; RUN: llvm-as < %s | llc -march=arm -; RUN: llvm-as < %s | llc -march=thumb | not grep {ldr sp} -; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin | \ -; RUN: not grep {sub.*r7} -; RUN: llvm-as < %s | llc -march=thumb | grep 4294967280 %struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* } %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* } Modified: llvm/trunk/test/CodeGen/ARM/fpconv.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpconv.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fpconv.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fpconv.ll Wed Jun 24 01:36:07 2009 @@ -20,7 +20,6 @@ ; RUN: grep floatsidf %t ; RUN: grep floatunsisf %t ; RUN: grep floatunsidf %t -; RUN: llvm-as < %s | llc -march=thumb define float @f1(double %x) { entry: Modified: llvm/trunk/test/CodeGen/ARM/fpow.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpow.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fpow.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fpow.ll Wed Jun 24 01:36:07 2009 @@ -1,5 +1,4 @@ ; RUN: llvm-as < %s | llc -march=arm -; RUN: llvm-as < %s | llc -march=thumb define double @t(double %x, double %y) nounwind optsize { entry: Removed: llvm/trunk/test/CodeGen/ARM/frame_thumb.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/frame_thumb.ll?rev=74067&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/frame_thumb.ll (original) +++ llvm/trunk/test/CodeGen/ARM/frame_thumb.ll (removed) @@ -1,9 +0,0 @@ -; RUN: llvm-as < %s | llc -march=thumb -mtriple=arm-apple-darwin \ -; RUN: -disable-fp-elim | not grep {r11} -; RUN: llvm-as < %s | llc -march=thumb -mtriple=arm-linux-gnueabi \ -; RUN: -disable-fp-elim | not grep {r11} - -define i32 @f() { -entry: - ret i32 10 -} Modified: llvm/trunk/test/CodeGen/ARM/iabs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/iabs.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/iabs.ll (original) +++ llvm/trunk/test/CodeGen/ARM/iabs.ll Wed Jun 24 01:36:07 2009 @@ -1,17 +1,10 @@ ; RUN: llvm-as < %s | llc -march=arm -stats |& \ ; RUN: grep {3 .*Number of machine instrs printed} -; RUN: llvm-as < %s | llc -march=thumb -stats |& \ -; RUN: grep {4 .*Number of machine instrs printed} ;; Integer absolute value, should produce something as good as: ARM: ;; add r3, r0, r0, asr #31 ;; eor r0, r3, r0, asr #31 ;; bx lr -;; Thumb: -;; asr r2, r0, #31 -;; add r0, r0, r2 -;; eor r0, r2 -;; bx lr define i32 @test(i32 %a) { %tmp1neg = sub i32 0, %a Removed: llvm/trunk/test/CodeGen/ARM/inlineasm-imm-thumb.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm-imm-thumb.ll?rev=74067&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/inlineasm-imm-thumb.ll (original) +++ llvm/trunk/test/CodeGen/ARM/inlineasm-imm-thumb.ll (removed) @@ -1,43 +0,0 @@ -; RUN: llvm-as < %s | llc -march=thumb - -; Test Thumb-mode "I" constraint, for ADD immediate. -define i32 @testI(i32 %x) { - %y = call i32 asm "add $0, $1, $2", "=r,r,I"( i32 %x, i32 255 ) nounwind - ret i32 %y -} - -; Test Thumb-mode "J" constraint, for negated ADD immediates. -define void @testJ() { - tail call void asm sideeffect ".word $0", "J"( i32 -255 ) nounwind - ret void -} - -; Test Thumb-mode "K" constraint, for compatibility with GCC's internal use. -define void @testK() { - tail call void asm sideeffect ".word $0", "K"( i32 65280 ) nounwind - ret void -} - -; Test Thumb-mode "L" constraint, for 3-operand ADD immediates. -define i32 @testL(i32 %x) { - %y = call i32 asm "add $0, $1, $2", "=r,r,L"( i32 %x, i32 -7 ) nounwind - ret i32 %y -} - -; Test Thumb-mode "M" constraint, for "ADD r = sp + imm". -define i32 @testM() { - %y = call i32 asm "add $0, sp, $1", "=r,M"( i32 1020 ) nounwind - ret i32 %y -} - -; Test Thumb-mode "N" constraint, for values between 0 and 31. -define i32 @testN(i32 %x) { - %y = call i32 asm "lsl $0, $1, $2", "=r,r,N"( i32 %x, i32 31 ) nounwind - ret i32 %y -} - -; Test Thumb-mode "O" constraint, for "ADD sp = sp + imm". -define void @testO() { - tail call void asm sideeffect "add sp, sp, $0; add sp, sp, $1", "O,O"( i32 -508, i32 508 ) nounwind - ret void -} Modified: llvm/trunk/test/CodeGen/ARM/ispositive.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ispositive.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ispositive.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ispositive.ll Wed Jun 24 01:36:07 2009 @@ -1,5 +1,4 @@ ; RUN: llvm-as < %s | llc -march=arm | grep {mov r0, r0, lsr #31} -; RUN: llvm-as < %s | llc -march=thumb | grep {lsr r0, r0, #31} define i32 @test1(i32 %X) { entry: Modified: llvm/trunk/test/CodeGen/ARM/large-stack.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/large-stack.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/large-stack.ll (original) +++ llvm/trunk/test/CodeGen/ARM/large-stack.ll Wed Jun 24 01:36:07 2009 @@ -1,5 +1,4 @@ ; RUN: llvm-as < %s | llc -march=arm -; RUN: llvm-as < %s | llc -march=thumb | grep {ldr.*LCP} | count 5 define void @test1() { %tmp = alloca [ 64 x i32 ] , align 4 Modified: llvm/trunk/test/CodeGen/ARM/ldr_ext.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ldr_ext.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ldr_ext.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ldr_ext.ll Wed Jun 24 01:36:07 2009 @@ -2,10 +2,6 @@ ; RUN: llvm-as < %s | llc -march=arm | grep ldrh | count 1 ; RUN: llvm-as < %s | llc -march=arm | grep ldrsb | count 1 ; RUN: llvm-as < %s | llc -march=arm | grep ldrsh | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep ldrb | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep ldrh | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep ldrsb | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep ldrsh | count 1 define i32 @test1(i8* %v.pntr.s0.u1) { %tmp.u = load i8* %v.pntr.s0.u1 Modified: llvm/trunk/test/CodeGen/ARM/ldr_frame.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ldr_frame.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ldr_frame.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ldr_frame.ll Wed Jun 24 01:36:07 2009 @@ -1,5 +1,4 @@ ; RUN: llvm-as < %s | llc -march=arm | not grep mov -; RUN: llvm-as < %s | llc -march=thumb | grep cpy | count 2 define i32 @f1() { %buf = alloca [32 x i32], align 4 Modified: llvm/trunk/test/CodeGen/ARM/long-setcc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/long-setcc.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/long-setcc.ll (original) +++ llvm/trunk/test/CodeGen/ARM/long-setcc.ll Wed Jun 24 01:36:07 2009 @@ -1,5 +1,4 @@ ; RUN: llvm-as < %s | llc -march=arm | grep cmp | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep cmp | count 1 define i1 @t1(i64 %x) { Modified: llvm/trunk/test/CodeGen/ARM/long.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/long.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/long.ll (original) +++ llvm/trunk/test/CodeGen/ARM/long.ll Wed Jun 24 01:36:07 2009 @@ -9,13 +9,6 @@ ; RUN: grep smull | count 1 ; RUN: llvm-as < %s | llc -march=arm | \ ; RUN: grep umull | count 1 -; RUN: llvm-as < %s | llc -march=thumb | \ -; RUN: grep mvn | count 1 -; RUN: llvm-as < %s | llc -march=thumb | \ -; RUN: grep adc | count 1 -; RUN: llvm-as < %s | llc -march=thumb | \ -; RUN: grep sbc | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep __muldi3 define i64 @f1() { entry: Modified: llvm/trunk/test/CodeGen/ARM/long_shift.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/long_shift.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/long_shift.ll (original) +++ llvm/trunk/test/CodeGen/ARM/long_shift.ll Wed Jun 24 01:36:07 2009 @@ -1,4 +1,3 @@ -; RUN: llvm-as < %s | llc -march=thumb ; RUN: llvm-as < %s | llc -march=arm > %t ; RUN: grep rrx %t | count 1 ; RUN: grep __ashldi3 %t Modified: llvm/trunk/test/CodeGen/ARM/mul.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/mul.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/mul.ll (original) +++ llvm/trunk/test/CodeGen/ARM/mul.ll Wed Jun 24 01:36:07 2009 @@ -1,7 +1,5 @@ ; RUN: llvm-as < %s | llc -march=arm | grep mul | count 2 ; RUN: llvm-as < %s | llc -march=arm | grep lsl | count 2 -; RUN: llvm-as < %s | llc -march=thumb | grep mul | count 3 -; RUN: llvm-as < %s | llc -march=thumb | grep lsl | count 1 define i32 @f1(i32 %u) { %tmp = mul i32 %u, %u Modified: llvm/trunk/test/CodeGen/ARM/select.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/select.ll (original) +++ llvm/trunk/test/CodeGen/ARM/select.ll Wed Jun 24 01:36:07 2009 @@ -6,13 +6,6 @@ ; RUN: llvm-as < %s | llc -march=arm | grep movhi | count 1 ; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \ ; RUN: grep fcpydmi | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep beq | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep bgt | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep blt | count 3 -; RUN: llvm-as < %s | llc -march=thumb | grep ble | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep bls | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep bhi | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep __ltdf2 define i32 @f1(i32 %a.s) { entry: Modified: llvm/trunk/test/CodeGen/ARM/stack-frame.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/stack-frame.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/stack-frame.ll (original) +++ llvm/trunk/test/CodeGen/ARM/stack-frame.ll Wed Jun 24 01:36:07 2009 @@ -1,7 +1,5 @@ ; RUN: llvm-as < %s | llc -march=arm ; RUN: llvm-as < %s | llc -march=arm | grep add | count 1 -; RUN: llvm-as < %s | llc -march=thumb -; RUN: llvm-as < %s | llc -march=thumb | grep add | count 1 define void @f1() { %c = alloca i8, align 1 Removed: llvm/trunk/test/CodeGen/ARM/thumb-imm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb-imm.ll?rev=74067&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/thumb-imm.ll (original) +++ llvm/trunk/test/CodeGen/ARM/thumb-imm.ll (removed) @@ -1,10 +0,0 @@ -; RUN: llvm-as < %s | llc -march=thumb | not grep CPI - - -define i32 @test1() { - ret i32 1000 -} - -define i32 @test2() { - ret i32 -256 -} Removed: llvm/trunk/test/CodeGen/ARM/thumb2-add.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-add.ll?rev=74067&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/thumb2-add.ll (original) +++ llvm/trunk/test/CodeGen/ARM/thumb2-add.ll (removed) @@ -1,50 +0,0 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #255 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #256 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #257 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #4094 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #4095 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #4096 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep lsl | grep #8 - -define i32 @t2ADDrc_255(i32 %lhs) { - %Rd = add i32 %lhs, 255; - ret i32 %Rd -} - -define i32 @t2ADDrc_256(i32 %lhs) { - %Rd = add i32 %lhs, 256; - ret i32 %Rd -} - -define i32 @t2ADDrc_257(i32 %lhs) { - %Rd = add i32 %lhs, 257; - ret i32 %Rd -} - -define i32 @t2ADDrc_4094(i32 %lhs) { - %Rd = add i32 %lhs, 4094; - ret i32 %Rd -} - -define i32 @t2ADDrc_4095(i32 %lhs) { - %Rd = add i32 %lhs, 4095; - ret i32 %Rd -} - -define i32 @t2ADDrc_4096(i32 %lhs) { - %Rd = add i32 %lhs, 4096; - ret i32 %Rd -} - -define i32 @t2ADDrr(i32 %lhs, i32 %rhs) { - %Rd = add i32 %lhs, %rhs; - ret i32 %Rd -} - -define i32 @t2ADDrs(i32 %lhs, i32 %rhs) { - %tmp = shl i32 %rhs, 8 - %Rd = add i32 %lhs, %tmp; - ret i32 %Rd -} - Removed: llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll?rev=74067&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll (original) +++ llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll (removed) @@ -1,127 +0,0 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #11206827 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #2868947712 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #2880154539 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #251658240 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #3948544 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #258 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #4026531840 - -; Test # - -; var 2.1 - 0x00ab00ab -define i32 @t2_const_var2_1_ok_1(i32 %lhs) { - %ret = add i32 %lhs, 11206827 ; 0x00ab00ab - ret i32 %ret -} - -define i32 @t2_const_var2_1_fail_1(i32 %lhs) { - %ret = add i32 %lhs, 11206843 ; 0x00ab00bb - ret i32 %ret -} - -define i32 @t2_const_var2_1_fail_2(i32 %lhs) { - %ret = add i32 %lhs, 27984043 ; 0x01ab00ab - ret i32 %ret -} - -define i32 @t2_const_var2_1_fail_3(i32 %lhs) { - %ret = add i32 %lhs, 27984299 ; 0x01ab01ab - ret i32 %ret -} - -define i32 @t2_const_var2_1_fail_4(i32 %lhs) { - %ret = add i32 %lhs, 28027649 ; 0x01abab01 - ret i32 %ret -} - -; var 2.2 - 0xab00ab00 -define i32 @t2_const_var2_2_ok_1(i32 %lhs) { - %ret = add i32 %lhs, 2868947712 ; 0xab00ab00 - ret i32 %ret -} - -define i32 @t2_const_var2_2_fail_1(i32 %lhs) { - %ret = add i32 %lhs, 2868951552 ; 0xab00ba00 - ret i32 %ret -} - -define i32 @t2_const_var2_2_fail_2(i32 %lhs) { - %ret = add i32 %lhs, 2868947728 ; 0xab00ab10 - ret i32 %ret -} - -define i32 @t2_const_var2_2_fail_3(i32 %lhs) { - %ret = add i32 %lhs, 2869996304 ; 0xab10ab10 - ret i32 %ret -} - -define i32 @t2_const_var2_2_fail_4(i32 %lhs) { - %ret = add i32 %lhs, 279685904 ; 0x10abab10 - ret i32 %ret -} - -; var 2.3 - 0xabababab -define i32 @t2_const_var2_3_ok_1(i32 %lhs) { - %ret = add i32 %lhs, 2880154539 ; 0xabababab - ret i32 %ret -} - -define i32 @t2_const_var2_3_fail_1(i32 %lhs) { - %ret = add i32 %lhs, 2880154554 ; 0xabababba - ret i32 %ret -} - -define i32 @t2_const_var2_3_fail_2(i32 %lhs) { - %ret = add i32 %lhs, 2880158379 ; 0xababbaab - ret i32 %ret -} - -define i32 @t2_const_var2_3_fail_3(i32 %lhs) { - %ret = add i32 %lhs, 2881137579 ; 0xabbaabab - ret i32 %ret -} - -define i32 @t2_const_var2_3_fail_4(i32 %lhs) { - %ret = add i32 %lhs, 3131812779 ; 0xbaababab - ret i32 %ret -} - -; var 3 - 0x0F000000 -define i32 @t2_const_var3_1_ok_1(i32 %lhs) { - %ret = add i32 %lhs, 251658240 ; 0x0F000000 - ret i32 %ret -} - -define i32 @t2_const_var3_2_ok_1(i32 %lhs) { - %ret = add i32 %lhs, 3948544 ; 0b00000000001111000100000000000000 - ret i32 %ret -} - -define i32 @t2_const_var3_2_fail_1(i32 %lhs) { - %ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000 - ret i32 %ret -} - -define i32 @t2_const_var3_3_ok_1(i32 %lhs) { - %ret = add i32 %lhs, 258 ; 0b00000000000000000000000100000010 - ret i32 %ret -} - -define i32 @t2_const_var3_4_ok_1(i32 %lhs) { - %ret = add i32 %lhs, 4026531840 ; 0xF0000000 - ret i32 %ret -} - Removed: llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll?rev=74067&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll (original) +++ llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll (removed) @@ -1,65 +0,0 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | grep #1234 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | grep #1234 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | grep #1234 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | grep #1234 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt - -define i32 @t2MOVTi16_ok_1(i32 %a) { - %1 = and i32 %a, 65535 - %2 = shl i32 1234, 16 - %3 = or i32 %1, %2 - - ret i32 %3 -} - -define i32 @t2MOVTi16_test_1(i32 %a) { - %1 = shl i32 255, 8 - %2 = shl i32 1234, 8 - %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 - %4 = shl i32 %2, 8 ; This gives us (1234 << 16) in %4 - %5 = and i32 %a, %3 - %6 = or i32 %4, %5 - - ret i32 %6 -} - -define i32 @t2MOVTi16_test_2(i32 %a) { - %1 = shl i32 255, 8 - %2 = shl i32 1234, 8 - %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 - %4 = shl i32 %2, 6 - %5 = and i32 %a, %3 - %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6 - %7 = or i32 %5, %6 - - ret i32 %7 -} - -define i32 @t2MOVTi16_test_3(i32 %a) { - %1 = shl i32 255, 8 - %2 = shl i32 1234, 8 - %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 - %4 = shl i32 %2, 6 - %5 = and i32 %a, %3 - %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6 - %7 = lshr i32 %6, 6 - %8 = shl i32 %7, 6 - %9 = or i32 %5, %8 - - ret i32 %9 -} - -define i32 @t2MOVTi16_test_nomatch_1(i32 %a) { - %1 = shl i32 255, 8 - %2 = shl i32 1234, 8 - %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 - %4 = shl i32 %2, 6 - %5 = and i32 %a, %3 - %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6 - %7 = lshr i32 %6, 3 - %8 = or i32 %5, %7 - - ret i32 %8 -} - - Removed: llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll?rev=74067&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll (original) +++ llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll (removed) @@ -1,40 +0,0 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsl -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsr -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep asr -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ror -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep mov - -define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) { - %A = shl i32 %Y, 16 - %B = add i32 %X, %A - ret i32 %B -} - -define i32 @t2ADDrs_lsr(i32 %X, i32 %Y) { - %A = lshr i32 %Y, 16 - %B = add i32 %X, %A - ret i32 %B -} - -define i32 @t2ADDrs_asr(i32 %X, i32 %Y) { - %A = ashr i32 %Y, 16 - %B = add i32 %X, %A - ret i32 %B -} - -; i32 ror(n) = (x >> n) | (x << (32 - n)) -define i32 @t2ADDrs_ror(i32 %X, i32 %Y) { - %A = lshr i32 %Y, 16 - %B = shl i32 %Y, 16 - %C = or i32 %B, %A - %R = add i32 %X, %C - ret i32 %R -} - -define i32 @t2ADDrs_noRegShift(i32 %X, i32 %Y, i8 %sh) { - %shift.upgrd.1 = zext i8 %sh to i32 - %A = shl i32 %Y, %shift.upgrd.1 - %B = add i32 %X, %A - ret i32 %B -} - Modified: llvm/trunk/test/CodeGen/ARM/tst_teq.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/tst_teq.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/tst_teq.ll (original) +++ llvm/trunk/test/CodeGen/ARM/tst_teq.ll Wed Jun 24 01:36:07 2009 @@ -1,6 +1,5 @@ ; RUN: llvm-as < %s | llc -march=arm | grep tst ; RUN: llvm-as < %s | llc -march=arm | grep teq -; RUN: llvm-as < %s | llc -march=thumb | grep tst define i32 @f(i32 %a) { entry: Modified: llvm/trunk/test/CodeGen/ARM/unord.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/unord.ll?rev=74068&r1=74067&r2=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/unord.ll (original) +++ llvm/trunk/test/CodeGen/ARM/unord.ll Wed Jun 24 01:36:07 2009 @@ -1,7 +1,5 @@ ; RUN: llvm-as < %s | llc -march=arm | grep movne | count 1 ; RUN: llvm-as < %s | llc -march=arm | grep moveq | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep bne | count 1 -; RUN: llvm-as < %s | llc -march=thumb | grep beq | count 1 define i32 @f1(float %X, float %Y) { %tmp = fcmp uno float %X, %Y Removed: llvm/trunk/test/CodeGen/ARM/vargs2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vargs2.ll?rev=74067&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vargs2.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vargs2.ll (removed) @@ -1,36 +0,0 @@ -; RUN: llvm-as < %s | llc -march=thumb -; RUN: llvm-as < %s | llc -mtriple=arm-linux -march=thumb | grep pop | count 1 -; RUN: llvm-as < %s | llc -mtriple=arm-darwin -march=thumb | grep pop | count 2 - - at str = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1] - -define void @f(i32 %a, ...) { -entry: - %va = alloca i8*, align 4 ; [#uses=4] - %va.upgrd.1 = bitcast i8** %va to i8* ; [#uses=1] - call void @llvm.va_start( i8* %va.upgrd.1 ) - br label %bb - -bb: ; preds = %bb, %entry - %a_addr.0 = phi i32 [ %a, %entry ], [ %tmp5, %bb ] ; [#uses=2] - %tmp = volatile load i8** %va ; [#uses=2] - %tmp2 = getelementptr i8* %tmp, i32 4 ; [#uses=1] - volatile store i8* %tmp2, i8** %va - %tmp5 = add i32 %a_addr.0, -1 ; [#uses=1] - %tmp.upgrd.2 = icmp eq i32 %a_addr.0, 1 ; [#uses=1] - br i1 %tmp.upgrd.2, label %bb7, label %bb - -bb7: ; preds = %bb - %tmp3 = bitcast i8* %tmp to i32* ; [#uses=1] - %tmp.upgrd.3 = load i32* %tmp3 ; [#uses=1] - %tmp10 = call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @str, i32 0, i64 0), i32 %tmp.upgrd.3 ) ; [#uses=0] - %va.upgrd.4 = bitcast i8** %va to i8* ; [#uses=1] - call void @llvm.va_end( i8* %va.upgrd.4 ) - ret void -} - -declare void @llvm.va_start(i8*) - -declare i32 @printf(i8*, ...) - -declare void @llvm.va_end(i8*) Added: llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,59 @@ +; RUN: llvm-as < %s | llc -march=thumb | not grep {ldr sp} +; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin | \ +; RUN: not grep {sub.*r7} +; RUN: llvm-as < %s | llc -march=thumb | grep 4294967280 + + %struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* } + %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* } + +define void @t1(%struct.state* %v) { + %tmp6 = load i32* null + %tmp8 = alloca float, i32 %tmp6 + store i32 1, i32* null + br i1 false, label %bb123.preheader, label %return + +bb123.preheader: + br i1 false, label %bb43, label %return + +bb43: + call fastcc void @f1( float* %tmp8, float* null, i32 0 ) + %tmp70 = load i32* null + %tmp85 = getelementptr float* %tmp8, i32 0 + call fastcc void @f2( float* null, float* null, float* %tmp85, i32 %tmp70 ) + ret void + +return: + ret void +} + +declare fastcc void @f1(float*, float*, i32) + +declare fastcc void @f2(float*, float*, float*, i32) + + %struct.comment = type { i8**, i32*, i32, i8* } + at str215 = external global [2 x i8] + +define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) { + %tmp1 = call i32 @strlen( i8* %tag ) + %tmp3 = call i32 @strlen( i8* %contents ) + %tmp4 = add i32 %tmp1, 2 + %tmp5 = add i32 %tmp4, %tmp3 + %tmp6 = alloca i8, i32 %tmp5 + %tmp9 = call i8* @strcpy( i8* %tmp6, i8* %tag ) + %tmp6.len = call i32 @strlen( i8* %tmp6 ) + %tmp6.indexed = getelementptr i8* %tmp6, i32 %tmp6.len + call void @llvm.memcpy.i32( i8* %tmp6.indexed, i8* getelementptr ([2 x i8]* @str215, i32 0, i32 0), i32 2, i32 1 ) + %tmp15 = call i8* @strcat( i8* %tmp6, i8* %contents ) + call fastcc void @comment_add( %struct.comment* %vc, i8* %tmp6 ) + ret void +} + +declare i32 @strlen(i8*) + +declare i8* @strcat(i8*, i8*) + +declare fastcc void @comment_add(%struct.comment*, i8*) + +declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) + +declare i8* @strcpy(i8*, i8*) Added: llvm/trunk/test/CodeGen/Thumb/fpconv.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/fpconv.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/fpconv.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/fpconv.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,61 @@ +; RUN: llvm-as < %s | llc -march=thumb + +define float @f1(double %x) { +entry: + %tmp1 = fptrunc double %x to float ; [#uses=1] + ret float %tmp1 +} + +define double @f2(float %x) { +entry: + %tmp1 = fpext float %x to double ; [#uses=1] + ret double %tmp1 +} + +define i32 @f3(float %x) { +entry: + %tmp = fptosi float %x to i32 ; [#uses=1] + ret i32 %tmp +} + +define i32 @f4(float %x) { +entry: + %tmp = fptoui float %x to i32 ; [#uses=1] + ret i32 %tmp +} + +define i32 @f5(double %x) { +entry: + %tmp = fptosi double %x to i32 ; [#uses=1] + ret i32 %tmp +} + +define i32 @f6(double %x) { +entry: + %tmp = fptoui double %x to i32 ; [#uses=1] + ret i32 %tmp +} + +define float @f7(i32 %a) { +entry: + %tmp = sitofp i32 %a to float ; [#uses=1] + ret float %tmp +} + +define double @f8(i32 %a) { +entry: + %tmp = sitofp i32 %a to double ; [#uses=1] + ret double %tmp +} + +define float @f9(i32 %a) { +entry: + %tmp = uitofp i32 %a to float ; [#uses=1] + ret float %tmp +} + +define double @f10(i32 %a) { +entry: + %tmp = uitofp i32 %a to double ; [#uses=1] + ret double %tmp +} Added: llvm/trunk/test/CodeGen/Thumb/fpow.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/fpow.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/fpow.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/fpow.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=thumb + +define double @t(double %x, double %y) nounwind optsize { +entry: + %0 = tail call double @llvm.pow.f64( double %x, double %y ) ; [#uses=1] + ret double %0 +} + +declare double @llvm.pow.f64(double, double) nounwind readonly Copied: llvm/trunk/test/CodeGen/Thumb/frame_thumb.ll (from r74067, llvm/trunk/test/CodeGen/ARM/frame_thumb.ll) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/frame_thumb.ll?p2=llvm/trunk/test/CodeGen/Thumb/frame_thumb.ll&p1=llvm/trunk/test/CodeGen/ARM/frame_thumb.ll&r1=74067&r2=74068&rev=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/frame_thumb.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/frame_thumb.ll Wed Jun 24 01:36:07 2009 @@ -1,6 +1,6 @@ -; RUN: llvm-as < %s | llc -march=thumb -mtriple=arm-apple-darwin \ +; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin \ ; RUN: -disable-fp-elim | not grep {r11} -; RUN: llvm-as < %s | llc -march=thumb -mtriple=arm-linux-gnueabi \ +; RUN: llvm-as < %s | llc -mtriple=thumb-linux-gnueabi \ ; RUN: -disable-fp-elim | not grep {r11} define i32 @f() { Added: llvm/trunk/test/CodeGen/Thumb/iabs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/iabs.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/iabs.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/iabs.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc -march=thumb -stats |& \ +; RUN: grep {4 .*Number of machine instrs printed} + +;; Integer absolute value, should produce something as good as: +;; Thumb: +;; asr r2, r0, #31 +;; add r0, r0, r2 +;; eor r0, r2 +;; bx lr + +define i32 @test(i32 %a) { + %tmp1neg = sub i32 0, %a + %b = icmp sgt i32 %a, -1 + %abs = select i1 %b, i32 %a, i32 %tmp1neg + ret i32 %abs +} + Added: llvm/trunk/test/CodeGen/Thumb/ispositive.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/ispositive.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/ispositive.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/ispositive.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=thumb | grep {lsr r0, r0, #31} + +define i32 @test1(i32 %X) { +entry: + icmp slt i32 %X, 0 ; :0 [#uses=1] + zext i1 %0 to i32 ; :1 [#uses=1] + ret i32 %1 +} + Added: llvm/trunk/test/CodeGen/Thumb/large-stack.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/large-stack.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/large-stack.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/large-stack.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=thumb | grep {ldr.*LCP} | count 5 + +define void @test1() { + %tmp = alloca [ 64 x i32 ] , align 4 + ret void +} + +define void @test2() { + %tmp = alloca [ 4168 x i8 ] , align 4 + ret void +} + +define i32 @test3() { + %retval = alloca i32, align 4 + %tmp = alloca i32, align 4 + %a = alloca [805306369 x i8], align 16 + store i32 0, i32* %tmp + %tmp1 = load i32* %tmp + ret i32 %tmp1 +} Added: llvm/trunk/test/CodeGen/Thumb/ldr_ext.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/ldr_ext.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/ldr_ext.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/ldr_ext.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,28 @@ +; RUN: llvm-as < %s | llc -march=thumb | grep ldrb | count 1 +; RUN: llvm-as < %s | llc -march=thumb | grep ldrh | count 1 +; RUN: llvm-as < %s | llc -march=thumb | grep ldrsb | count 1 +; RUN: llvm-as < %s | llc -march=thumb | grep ldrsh | count 1 + +define i32 @test1(i8* %v.pntr.s0.u1) { + %tmp.u = load i8* %v.pntr.s0.u1 + %tmp1.s = zext i8 %tmp.u to i32 + ret i32 %tmp1.s +} + +define i32 @test2(i16* %v.pntr.s0.u1) { + %tmp.u = load i16* %v.pntr.s0.u1 + %tmp1.s = zext i16 %tmp.u to i32 + ret i32 %tmp1.s +} + +define i32 @test3(i8* %v.pntr.s1.u0) { + %tmp.s = load i8* %v.pntr.s1.u0 + %tmp1.s = sext i8 %tmp.s to i32 + ret i32 %tmp1.s +} + +define i32 @test4() { + %tmp.s = load i16* null + %tmp1.s = sext i16 %tmp.s to i32 + ret i32 %tmp1.s +} Added: llvm/trunk/test/CodeGen/Thumb/ldr_frame.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/ldr_frame.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/ldr_frame.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/ldr_frame.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,31 @@ +; RUN: llvm-as < %s | llc -march=thumb | grep cpy | count 2 + +define i32 @f1() { + %buf = alloca [32 x i32], align 4 + %tmp = getelementptr [32 x i32]* %buf, i32 0, i32 0 + %tmp1 = load i32* %tmp + ret i32 %tmp1 +} + +define i32 @f2() { + %buf = alloca [32 x i8], align 4 + %tmp = getelementptr [32 x i8]* %buf, i32 0, i32 0 + %tmp1 = load i8* %tmp + %tmp2 = zext i8 %tmp1 to i32 + ret i32 %tmp2 +} + +define i32 @f3() { + %buf = alloca [32 x i32], align 4 + %tmp = getelementptr [32 x i32]* %buf, i32 0, i32 32 + %tmp1 = load i32* %tmp + ret i32 %tmp1 +} + +define i32 @f4() { + %buf = alloca [32 x i8], align 4 + %tmp = getelementptr [32 x i8]* %buf, i32 0, i32 2 + %tmp1 = load i8* %tmp + %tmp2 = zext i8 %tmp1 to i32 + ret i32 %tmp2 +} Added: llvm/trunk/test/CodeGen/Thumb/long-setcc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/long-setcc.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/long-setcc.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/long-setcc.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc -march=thumb | grep cmp | count 1 + + +define i1 @t1(i64 %x) { + %B = icmp slt i64 %x, 0 + ret i1 %B +} + +define i1 @t2(i64 %x) { + %tmp = icmp ult i64 %x, 4294967296 + ret i1 %tmp +} + +define i1 @t3(i32 %x) { + %tmp = icmp ugt i32 %x, -1 + ret i1 %tmp +} Added: llvm/trunk/test/CodeGen/Thumb/long.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/long.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/long.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/long.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,76 @@ +; RUN: llvm-as < %s | llc -march=thumb | \ +; RUN: grep mvn | count 1 +; RUN: llvm-as < %s | llc -march=thumb | \ +; RUN: grep adc | count 1 +; RUN: llvm-as < %s | llc -march=thumb | \ +; RUN: grep sbc | count 1 +; RUN: llvm-as < %s | llc -march=thumb | grep __muldi3 + +define i64 @f1() { +entry: + ret i64 0 +} + +define i64 @f2() { +entry: + ret i64 1 +} + +define i64 @f3() { +entry: + ret i64 2147483647 +} + +define i64 @f4() { +entry: + ret i64 2147483648 +} + +define i64 @f5() { +entry: + ret i64 9223372036854775807 +} + +define i64 @f6(i64 %x, i64 %y) { +entry: + %tmp1 = add i64 %y, 1 ; [#uses=1] + ret i64 %tmp1 +} + +define void @f7() { +entry: + %tmp = call i64 @f8( ) ; [#uses=0] + ret void +} + +declare i64 @f8() + +define i64 @f9(i64 %a, i64 %b) { +entry: + %tmp = sub i64 %a, %b ; [#uses=1] + ret i64 %tmp +} + +define i64 @f(i32 %a, i32 %b) { +entry: + %tmp = sext i32 %a to i64 ; [#uses=1] + %tmp1 = sext i32 %b to i64 ; [#uses=1] + %tmp2 = mul i64 %tmp1, %tmp ; [#uses=1] + ret i64 %tmp2 +} + +define i64 @g(i32 %a, i32 %b) { +entry: + %tmp = zext i32 %a to i64 ; [#uses=1] + %tmp1 = zext i32 %b to i64 ; [#uses=1] + %tmp2 = mul i64 %tmp1, %tmp ; [#uses=1] + ret i64 %tmp2 +} + +define i64 @f10() { +entry: + %a = alloca i64, align 8 ; [#uses=1] + %retval = load i64* %a ; [#uses=1] + ret i64 %retval +} + Added: llvm/trunk/test/CodeGen/Thumb/select.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/select.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/select.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/select.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,55 @@ +; RUN: llvm-as < %s | llc -march=thumb | grep beq | count 1 +; RUN: llvm-as < %s | llc -march=thumb | grep bgt | count 1 +; RUN: llvm-as < %s | llc -march=thumb | grep blt | count 3 +; RUN: llvm-as < %s | llc -march=thumb | grep ble | count 1 +; RUN: llvm-as < %s | llc -march=thumb | grep bls | count 1 +; RUN: llvm-as < %s | llc -march=thumb | grep bhi | count 1 +; RUN: llvm-as < %s | llc -march=thumb | grep __ltdf2 + +define i32 @f1(i32 %a.s) { +entry: + %tmp = icmp eq i32 %a.s, 4 + %tmp1.s = select i1 %tmp, i32 2, i32 3 + ret i32 %tmp1.s +} + +define i32 @f2(i32 %a.s) { +entry: + %tmp = icmp sgt i32 %a.s, 4 + %tmp1.s = select i1 %tmp, i32 2, i32 3 + ret i32 %tmp1.s +} + +define i32 @f3(i32 %a.s, i32 %b.s) { +entry: + %tmp = icmp slt i32 %a.s, %b.s + %tmp1.s = select i1 %tmp, i32 2, i32 3 + ret i32 %tmp1.s +} + +define i32 @f4(i32 %a.s, i32 %b.s) { +entry: + %tmp = icmp sle i32 %a.s, %b.s + %tmp1.s = select i1 %tmp, i32 2, i32 3 + ret i32 %tmp1.s +} + +define i32 @f5(i32 %a.u, i32 %b.u) { +entry: + %tmp = icmp ule i32 %a.u, %b.u + %tmp1.s = select i1 %tmp, i32 2, i32 3 + ret i32 %tmp1.s +} + +define i32 @f6(i32 %a.u, i32 %b.u) { +entry: + %tmp = icmp ugt i32 %a.u, %b.u + %tmp1.s = select i1 %tmp, i32 2, i32 3 + ret i32 %tmp1.s +} + +define double @f7(double %a, double %b) { + %tmp = fcmp olt double %a, 1.234e+00 + %tmp1 = select i1 %tmp, double -1.000e+00, double %b + ret double %tmp1 +} Added: llvm/trunk/test/CodeGen/Thumb/stack-frame.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/stack-frame.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/stack-frame.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/stack-frame.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,13 @@ +; RUN: llvm-as < %s | llc -march=thumb +; RUN: llvm-as < %s | llc -march=thumb | grep add | count 1 + +define void @f1() { + %c = alloca i8, align 1 + ret void +} + +define i32 @f2() { + ret i32 1 +} + + Added: llvm/trunk/test/CodeGen/Thumb/tst_teq.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/tst_teq.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/tst_teq.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/tst_teq.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc -march=thumb | grep tst + +define i32 @f(i32 %a) { +entry: + %tmp2 = and i32 %a, 255 ; [#uses=1] + icmp eq i32 %tmp2, 0 ; :0 [#uses=1] + %retval = select i1 %0, i32 20, i32 10 ; [#uses=1] + ret i32 %retval +} + +define i32 @g(i32 %a) { +entry: + %tmp2 = xor i32 %a, 255 + icmp eq i32 %tmp2, 0 ; :0 [#uses=1] + %retval = select i1 %0, i32 20, i32 10 ; [#uses=1] + ret i32 %retval +} Added: llvm/trunk/test/CodeGen/Thumb/unord.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/unord.ll?rev=74068&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/unord.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/unord.ll Wed Jun 24 01:36:07 2009 @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=thumb | grep bne | count 1 +; RUN: llvm-as < %s | llc -march=thumb | grep beq | count 1 + +define i32 @f1(float %X, float %Y) { + %tmp = fcmp uno float %X, %Y + %retval = select i1 %tmp, i32 1, i32 -1 + ret i32 %retval +} + +define i32 @f2(float %X, float %Y) { + %tmp = fcmp ord float %X, %Y + %retval = select i1 %tmp, i32 1, i32 -1 + ret i32 %retval +} Copied: llvm/trunk/test/CodeGen/Thumb/vargs.ll (from r74067, llvm/trunk/test/CodeGen/ARM/vargs2.ll) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/vargs.ll?p2=llvm/trunk/test/CodeGen/Thumb/vargs.ll&p1=llvm/trunk/test/CodeGen/ARM/vargs2.ll&r1=74067&r2=74068&rev=74068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vargs2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/vargs.ll Wed Jun 24 01:36:07 2009 @@ -1,6 +1,6 @@ ; RUN: llvm-as < %s | llc -march=thumb -; RUN: llvm-as < %s | llc -mtriple=arm-linux -march=thumb | grep pop | count 1 -; RUN: llvm-as < %s | llc -mtriple=arm-darwin -march=thumb | grep pop | count 2 +; RUN: llvm-as < %s | llc -mtriple=thumb-linux | grep pop | count 1 +; RUN: llvm-as < %s | llc -mtriple=thumb-darwin | grep pop | count 2 @str = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1] From baldrick at free.fr Wed Jun 24 03:17:35 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 24 Jun 2009 08:17:35 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r74069 - in /llvm-gcc-4.2/trunk/gcc: llvm-convert.cpp llvm-internal.h Message-ID: <200906240817.n5O8HZsl004728@zion.cs.uiuc.edu> Author: baldrick Date: Wed Jun 24 03:17:34 2009 New Revision: 74069 URL: http://llvm.org/viewvc/llvm-project?rev=74069&view=rev Log: Add some trivial lvalue emission helpers, and reorder the emission functions alphabetically. Strip some trailing whitespace. No functionality change. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/llvm-internal.h Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=74069&r1=74068&r2=74069&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Jun 24 03:17:34 2009 @@ -1026,15 +1026,10 @@ // Trivial Cases. case WITH_SIZE_EXPR: - // The address is the address of the operand. - LV = EmitLV(TREE_OPERAND(exp, 0)); + LV = EmitLV_WITH_SIZE_EXPR(exp); break; case INDIRECT_REF: - // The lvalue is just the address. - LV = LValue(Emit(TREE_OPERAND(exp, 0), 0), expr_align(exp) / 8); - // Correct for implicit type conversion: INDIRECT_REF can be applied to a - // void*, resulting in a non-void type. - LV.Ptr = BitCastToType(LV.Ptr, ConvertType(TREE_TYPE(exp))->getPointerTo()); + LV = EmitLV_INDIRECT_REF(exp); break; } @@ -5877,85 +5872,91 @@ // ... L-Value Expressions ... //===----------------------------------------------------------------------===// -LValue TreeToLLVM::EmitLV_DECL(tree exp) { - if (TREE_CODE(exp) == PARM_DECL || TREE_CODE(exp) == VAR_DECL || - TREE_CODE(exp) == CONST_DECL) { - // If a static var's type was incomplete when the decl was written, - // but the type is complete now, lay out the decl now. - if (DECL_SIZE(exp) == 0 && COMPLETE_OR_UNBOUND_ARRAY_TYPE_P(TREE_TYPE(exp)) - && (TREE_STATIC(exp) || DECL_EXTERNAL(exp))) { - layout_decl(exp, 0); - - // This mirrors code in layout_decl for munging the RTL. Here we actually - // emit a NEW declaration for the global variable, now that it has been - // laid out. We then tell the compiler to "forward" any uses of the old - // global to this new one. - if (Value *Val = DECL_LLVM_IF_SET(exp)) { - //fprintf(stderr, "***\n*** SHOULD HANDLE GLOBAL VARIABLES!\n***\n"); - //assert(0 && "Reimplement this with replace all uses!"); -#if 0 - SET_DECL_LLVM(exp, 0); - // Create a new global variable declaration - llvm_assemble_external(exp); - V2GV(Val)->ForwardedGlobal = V2GV(DECL_LLVM(exp)); -#endif - } - } - } +/// getFieldOffsetInBits - Return the offset (in bits) of a FIELD_DECL in a +/// structure. +static unsigned getFieldOffsetInBits(tree Field) { + assert(DECL_FIELD_BIT_OFFSET(Field) != 0 && DECL_FIELD_OFFSET(Field) != 0); + unsigned Result = TREE_INT_CST_LOW(DECL_FIELD_BIT_OFFSET(Field)); + if (TREE_CODE(DECL_FIELD_OFFSET(Field)) == INTEGER_CST) + Result += TREE_INT_CST_LOW(DECL_FIELD_OFFSET(Field))*8; + return Result; +} - assert(!isGimpleTemporary(exp) && - "Cannot use a gimple temporary as an l-value"); - - Value *Decl = DECL_LLVM(exp); - if (Decl == 0) { - if (errorcount || sorrycount) { - const Type *Ty = ConvertType(TREE_TYPE(exp)); - const PointerType *PTy = PointerType::getUnqual(Ty); - LValue LV(ConstantPointerNull::get(PTy), 1); - return LV; - } - assert(0 && "INTERNAL ERROR: Referencing decl that hasn't been laid out"); - abort(); - } - - // Ensure variable marked as used even if it doesn't go through a parser. If - // it hasn't been used yet, write out an external definition. - if (!TREE_USED(exp)) { - assemble_external(exp); - TREE_USED(exp) = 1; - Decl = DECL_LLVM(exp); - } - - if (GlobalValue *GV = dyn_cast(Decl)) { - // If this is an aggregate, emit it to LLVM now. GCC happens to - // get this case right by forcing the initializer into memory. - if (TREE_CODE(exp) == CONST_DECL || TREE_CODE(exp) == VAR_DECL) { - if ((DECL_INITIAL(exp) || !TREE_PUBLIC(exp)) && !DECL_EXTERNAL(exp) && - GV->isDeclaration() && - !BOGUS_CTOR(exp)) { - emit_global_to_llvm(exp); - Decl = DECL_LLVM(exp); // Decl could have change if it changed type. - } - } else { - // Otherwise, inform cgraph that we used the global. - mark_decl_referenced(exp); - if (tree ID = DECL_ASSEMBLER_NAME(exp)) - mark_referenced(ID); +/// getComponentRefOffsetInBits - Return the offset (in bits) of the field +/// referenced in a COMPONENT_REF exp. +static unsigned getComponentRefOffsetInBits(tree exp) { + assert(TREE_CODE(exp) == COMPONENT_REF && "not a COMPONENT_REF!"); + tree field = TREE_OPERAND(exp, 1); + assert(TREE_CODE(field) == FIELD_DECL && "not a FIELD_DECL!"); + tree field_offset = component_ref_field_offset (exp); + assert(DECL_FIELD_BIT_OFFSET(field) && field_offset); + unsigned Result = TREE_INT_CST_LOW(DECL_FIELD_BIT_OFFSET(field)); + if (TREE_CODE(field_offset) == INTEGER_CST) + Result += TREE_INT_CST_LOW(field_offset)*8; + return Result; +} + +Value *TreeToLLVM::EmitFieldAnnotation(Value *FieldPtr, tree FieldDecl) { + tree AnnotateAttr = lookup_attribute("annotate", DECL_ATTRIBUTES(FieldDecl)); + + const Type *OrigPtrTy = FieldPtr->getType(); + const Type *SBP = PointerType::getUnqual(Type::Int8Ty); + + Function *Fn = Intrinsic::getDeclaration(TheModule, + Intrinsic::ptr_annotation, + &SBP, 1); + + // Get file and line number. FIXME: Should this be for the decl or the + // use. Is there a location info for the use? + Constant *LineNo = ConstantInt::get(Type::Int32Ty, + DECL_SOURCE_LINE(FieldDecl)); + Constant *File = ConvertMetadataStringToGV(DECL_SOURCE_FILE(FieldDecl)); + + File = TheFolder->CreateBitCast(File, SBP); + + // There may be multiple annotate attributes. Pass return of lookup_attr + // to successive lookups. + while (AnnotateAttr) { + // Each annotate attribute is a tree list. + // Get value of list which is our linked list of args. + tree args = TREE_VALUE(AnnotateAttr); + + // Each annotate attribute may have multiple args. + // Treat each arg as if it were a separate annotate attribute. + for (tree a = args; a; a = TREE_CHAIN(a)) { + // Each element of the arg list is a tree list, so get value + tree val = TREE_VALUE(a); + + // Assert its a string, and then get that string. + assert(TREE_CODE(val) == STRING_CST && + "Annotate attribute arg should always be a string"); + + Constant *strGV = TreeConstantToLLVM::EmitLV_STRING_CST(val); + + // We can not use the IRBuilder because it will constant fold away + // the GEP that is critical to distinguish between an annotate + // attribute on a whole struct from one on the first element of the + // struct. + BitCastInst *CastFieldPtr = new BitCastInst(FieldPtr, SBP, + FieldPtr->getNameStart()); + Builder.Insert(CastFieldPtr); + + Value *Ops[4] = { + CastFieldPtr, BitCastToType(strGV, SBP), + File, LineNo + }; + + const Type* FieldPtrType = FieldPtr->getType(); + FieldPtr = Builder.CreateCall(Fn, Ops, Ops+4); + FieldPtr = BitCastToType(FieldPtr, FieldPtrType); } - } - const Type *Ty = ConvertType(TREE_TYPE(exp)); - // If we have "extern void foo", make the global have type {} instead of - // type void. - if (Ty == Type::VoidTy) Ty = StructType::get(NULL, NULL); - const PointerType *PTy = PointerType::getUnqual(Ty); - unsigned Alignment = Ty->isSized() ? TD.getABITypeAlignment(Ty) : 1; - if (DECL_ALIGN(exp)) { - if (DECL_USER_ALIGN(exp) || 8 * Alignment < (unsigned)DECL_ALIGN(exp)) - Alignment = DECL_ALIGN(exp) / 8; + // Get next annotate attribute. + AnnotateAttr = TREE_CHAIN(AnnotateAttr); + if (AnnotateAttr) + AnnotateAttr = lookup_attribute("annotate", AnnotateAttr); } - - return LValue(BitCastToType(Decl, PTy), Alignment); + return FieldPtr; } LValue TreeToLLVM::EmitLV_ARRAY_REF(tree exp) { @@ -6043,126 +6044,76 @@ Alignment); } -/// getFieldOffsetInBits - Return the offset (in bits) of a FIELD_DECL in a -/// structure. -static unsigned getFieldOffsetInBits(tree Field) { - assert(DECL_FIELD_BIT_OFFSET(Field) != 0 && DECL_FIELD_OFFSET(Field) != 0); - unsigned Result = TREE_INT_CST_LOW(DECL_FIELD_BIT_OFFSET(Field)); - if (TREE_CODE(DECL_FIELD_OFFSET(Field)) == INTEGER_CST) - Result += TREE_INT_CST_LOW(DECL_FIELD_OFFSET(Field))*8; - return Result; -} +LValue TreeToLLVM::EmitLV_BIT_FIELD_REF(tree exp) { + LValue Ptr = EmitLV(TREE_OPERAND(exp, 0)); + assert(!Ptr.isBitfield() && "BIT_FIELD_REF operands cannot be bitfields!"); -/// getComponentRefOffsetInBits - Return the offset (in bits) of the field -/// referenced in a COMPONENT_REF exp. -static unsigned getComponentRefOffsetInBits(tree exp) { - assert(TREE_CODE(exp) == COMPONENT_REF && "not a COMPONENT_REF!"); - tree field = TREE_OPERAND(exp, 1); - assert(TREE_CODE(field) == FIELD_DECL && "not a FIELD_DECL!"); - tree field_offset = component_ref_field_offset (exp); - assert(DECL_FIELD_BIT_OFFSET(field) && field_offset); - unsigned Result = TREE_INT_CST_LOW(DECL_FIELD_BIT_OFFSET(field)); - if (TREE_CODE(field_offset) == INTEGER_CST) - Result += TREE_INT_CST_LOW(field_offset)*8; - return Result; -} + unsigned BitStart = (unsigned)TREE_INT_CST_LOW(TREE_OPERAND(exp, 2)); + unsigned BitSize = (unsigned)TREE_INT_CST_LOW(TREE_OPERAND(exp, 1)); + const Type *ValTy = ConvertType(TREE_TYPE(exp)); -Value *TreeToLLVM::EmitFieldAnnotation(Value *FieldPtr, tree FieldDecl) { - tree AnnotateAttr = lookup_attribute("annotate", DECL_ATTRIBUTES(FieldDecl)); + unsigned ValueSizeInBits = TD.getTypeSizeInBits(ValTy); + assert(BitSize <= ValueSizeInBits && + "ValTy isn't large enough to hold the value loaded!"); - const Type *OrigPtrTy = FieldPtr->getType(); - const Type *SBP = PointerType::getUnqual(Type::Int8Ty); - - Function *Fn = Intrinsic::getDeclaration(TheModule, - Intrinsic::ptr_annotation, - &SBP, 1); - - // Get file and line number. FIXME: Should this be for the decl or the - // use. Is there a location info for the use? - Constant *LineNo = ConstantInt::get(Type::Int32Ty, - DECL_SOURCE_LINE(FieldDecl)); - Constant *File = ConvertMetadataStringToGV(DECL_SOURCE_FILE(FieldDecl)); - - File = TheFolder->CreateBitCast(File, SBP); - - // There may be multiple annotate attributes. Pass return of lookup_attr - // to successive lookups. - while (AnnotateAttr) { - // Each annotate attribute is a tree list. - // Get value of list which is our linked list of args. - tree args = TREE_VALUE(AnnotateAttr); - - // Each annotate attribute may have multiple args. - // Treat each arg as if it were a separate annotate attribute. - for (tree a = args; a; a = TREE_CHAIN(a)) { - // Each element of the arg list is a tree list, so get value - tree val = TREE_VALUE(a); - - // Assert its a string, and then get that string. - assert(TREE_CODE(val) == STRING_CST && - "Annotate attribute arg should always be a string"); - - Constant *strGV = TreeConstantToLLVM::EmitLV_STRING_CST(val); - - // We can not use the IRBuilder because it will constant fold away - // the GEP that is critical to distinguish between an annotate - // attribute on a whole struct from one on the first element of the - // struct. - BitCastInst *CastFieldPtr = new BitCastInst(FieldPtr, SBP, - FieldPtr->getNameStart()); - Builder.Insert(CastFieldPtr); - - Value *Ops[4] = { - CastFieldPtr, BitCastToType(strGV, SBP), - File, LineNo - }; - - const Type* FieldPtrType = FieldPtr->getType(); - FieldPtr = Builder.CreateCall(Fn, Ops, Ops+4); - FieldPtr = BitCastToType(FieldPtr, FieldPtrType); - } - - // Get next annotate attribute. - AnnotateAttr = TREE_CHAIN(AnnotateAttr); - if (AnnotateAttr) - AnnotateAttr = lookup_attribute("annotate", AnnotateAttr); + assert(ValueSizeInBits == TD.getTypeAllocSizeInBits(ValTy) && + "FIXME: BIT_FIELD_REF logic is broken for non-round types"); + + // BIT_FIELD_REF values can have BitStart values that are quite large. We + // know that the thing we are loading is ValueSizeInBits large. If BitStart + // is larger than ValueSizeInBits, bump the pointer over to where it should + // be. + if (unsigned UnitOffset = BitStart / ValueSizeInBits) { + // TODO: If Ptr.Ptr is a struct type or something, we can do much better + // than this. e.g. check out when compiling unwind-dw2-fde-darwin.c. + Ptr.Ptr = BitCastToType(Ptr.Ptr, PointerType::getUnqual(ValTy)); + Ptr.Ptr = Builder.CreateGEP(Ptr.Ptr, + ConstantInt::get(Type::Int32Ty, UnitOffset)); + BitStart -= UnitOffset*ValueSizeInBits; } - return FieldPtr; -} + // If this is referring to the whole field, return the whole thing. + if (BitStart == 0 && BitSize == ValueSizeInBits) { + return LValue(BitCastToType(Ptr.Ptr, PointerType::getUnqual(ValTy)), + Ptr.getAlignment()); + } + + return LValue(BitCastToType(Ptr.Ptr, PointerType::getUnqual(ValTy)), 1, + BitStart, BitSize); +} LValue TreeToLLVM::EmitLV_COMPONENT_REF(tree exp) { LValue StructAddrLV = EmitLV(TREE_OPERAND(exp, 0)); - tree FieldDecl = TREE_OPERAND(exp, 1); + tree FieldDecl = TREE_OPERAND(exp, 1); unsigned LVAlign = StructAddrLV.getAlignment(); - + assert((TREE_CODE(DECL_CONTEXT(FieldDecl)) == RECORD_TYPE || TREE_CODE(DECL_CONTEXT(FieldDecl)) == UNION_TYPE || TREE_CODE(DECL_CONTEXT(FieldDecl)) == QUAL_UNION_TYPE)); - + // Ensure that the struct type has been converted, so that the fielddecls // are laid out. Note that we convert to the context of the Field, not to the // type of Operand #0, because GCC doesn't always have the field match up with // operand #0's type. const Type *StructTy = ConvertType(DECL_CONTEXT(FieldDecl)); - - assert((!StructAddrLV.isBitfield() || + + assert((!StructAddrLV.isBitfield() || StructAddrLV.BitStart == 0) && "structs cannot be bitfields!"); - + StructAddrLV.Ptr = BitCastToType(StructAddrLV.Ptr, PointerType::getUnqual(StructTy)); const Type *FieldTy = ConvertType(getDeclaredType(FieldDecl)); - + // BitStart - This is the actual offset of the field from the start of the // struct, in bits. For bitfields this may be on a non-byte boundary. unsigned BitStart = getComponentRefOffsetInBits(exp); Value *FieldPtr; - + tree field_offset = component_ref_field_offset (exp); // If this is a normal field at a fixed offset from the start, handle it. if (TREE_CODE(field_offset) == INTEGER_CST) { unsigned int MemberIndex = GetFieldIndex(FieldDecl); - + // If the LLVM struct has zero field, don't try to index into it, just use // the current pointer. FieldPtr = StructAddrLV.Ptr; @@ -6171,14 +6122,14 @@ "Field Idx out of range!"); FieldPtr = Builder.CreateStructGEP(FieldPtr, MemberIndex); } - + // Now that we did an offset from the start of the struct, subtract off // the offset from BitStart. if (MemberIndex) { const StructLayout *SL = TD.getStructLayout(cast(StructTy)); unsigned Offset = SL->getElementOffset(MemberIndex); BitStart -= Offset * 8; - + // If the base is known to be 8-byte aligned, and we're adding a 4-byte // offset, the field is known to be 4-byte aligned. LVAlign = MinAlign(LVAlign, Offset); @@ -6195,7 +6146,7 @@ DECL_ALIGN(FieldDecl)) LVAlign = std::max(LVAlign, unsigned(DECL_ALIGN(FieldDecl)) / 8); #endif - + // If the FIELD_DECL has an annotate attribute on it, emit it. if (lookup_attribute("annotate", DECL_ATTRIBUTES(FieldDecl))) FieldPtr = EmitFieldAnnotation(FieldPtr, FieldDecl); @@ -6223,10 +6174,10 @@ LVAlign = MinAlign(LVAlign, ByteOffset); } - Value *Ptr = CastToType(Instruction::PtrToInt, StructAddrLV.Ptr, + Value *Ptr = CastToType(Instruction::PtrToInt, StructAddrLV.Ptr, Offset->getType()); Ptr = Builder.CreateAdd(Ptr, Offset); - FieldPtr = CastToType(Instruction::IntToPtr, Ptr, + FieldPtr = CastToType(Instruction::IntToPtr, Ptr, PointerType::getUnqual(FieldTy)); } @@ -6328,57 +6279,112 @@ return LValue(FieldPtr, LVAlign); } -LValue TreeToLLVM::EmitLV_BIT_FIELD_REF(tree exp) { - LValue Ptr = EmitLV(TREE_OPERAND(exp, 0)); - assert(!Ptr.isBitfield() && "BIT_FIELD_REF operands cannot be bitfields!"); - - unsigned BitStart = (unsigned)TREE_INT_CST_LOW(TREE_OPERAND(exp, 2)); - unsigned BitSize = (unsigned)TREE_INT_CST_LOW(TREE_OPERAND(exp, 1)); - const Type *ValTy = ConvertType(TREE_TYPE(exp)); - - unsigned ValueSizeInBits = TD.getTypeSizeInBits(ValTy); - assert(BitSize <= ValueSizeInBits && - "ValTy isn't large enough to hold the value loaded!"); +LValue TreeToLLVM::EmitLV_DECL(tree exp) { + if (TREE_CODE(exp) == PARM_DECL || TREE_CODE(exp) == VAR_DECL || + TREE_CODE(exp) == CONST_DECL) { + // If a static var's type was incomplete when the decl was written, + // but the type is complete now, lay out the decl now. + if (DECL_SIZE(exp) == 0 && COMPLETE_OR_UNBOUND_ARRAY_TYPE_P(TREE_TYPE(exp)) + && (TREE_STATIC(exp) || DECL_EXTERNAL(exp))) { + layout_decl(exp, 0); - assert(ValueSizeInBits == TD.getTypeAllocSizeInBits(ValTy) && - "FIXME: BIT_FIELD_REF logic is broken for non-round types"); + // This mirrors code in layout_decl for munging the RTL. Here we actually + // emit a NEW declaration for the global variable, now that it has been + // laid out. We then tell the compiler to "forward" any uses of the old + // global to this new one. + if (Value *Val = DECL_LLVM_IF_SET(exp)) { + //fprintf(stderr, "***\n*** SHOULD HANDLE GLOBAL VARIABLES!\n***\n"); + //assert(0 && "Reimplement this with replace all uses!"); +#if 0 + SET_DECL_LLVM(exp, 0); + // Create a new global variable declaration + llvm_assemble_external(exp); + V2GV(Val)->ForwardedGlobal = V2GV(DECL_LLVM(exp)); +#endif + } + } + } - // BIT_FIELD_REF values can have BitStart values that are quite large. We - // know that the thing we are loading is ValueSizeInBits large. If BitStart - // is larger than ValueSizeInBits, bump the pointer over to where it should - // be. - if (unsigned UnitOffset = BitStart / ValueSizeInBits) { - // TODO: If Ptr.Ptr is a struct type or something, we can do much better - // than this. e.g. check out when compiling unwind-dw2-fde-darwin.c. - Ptr.Ptr = BitCastToType(Ptr.Ptr, PointerType::getUnqual(ValTy)); - Ptr.Ptr = Builder.CreateGEP(Ptr.Ptr, - ConstantInt::get(Type::Int32Ty, UnitOffset)); - BitStart -= UnitOffset*ValueSizeInBits; + assert(!isGimpleTemporary(exp) && + "Cannot use a gimple temporary as an l-value"); + + Value *Decl = DECL_LLVM(exp); + if (Decl == 0) { + if (errorcount || sorrycount) { + const Type *Ty = ConvertType(TREE_TYPE(exp)); + const PointerType *PTy = PointerType::getUnqual(Ty); + LValue LV(ConstantPointerNull::get(PTy), 1); + return LV; + } + assert(0 && "INTERNAL ERROR: Referencing decl that hasn't been laid out"); + abort(); } - - // If this is referring to the whole field, return the whole thing. - if (BitStart == 0 && BitSize == ValueSizeInBits) { - return LValue(BitCastToType(Ptr.Ptr, PointerType::getUnqual(ValTy)), - Ptr.getAlignment()); + + // Ensure variable marked as used even if it doesn't go through a parser. If + // it hasn't been used yet, write out an external definition. + if (!TREE_USED(exp)) { + assemble_external(exp); + TREE_USED(exp) = 1; + Decl = DECL_LLVM(exp); } - - return LValue(BitCastToType(Ptr.Ptr, PointerType::getUnqual(ValTy)), 1, - BitStart, BitSize); + + if (GlobalValue *GV = dyn_cast(Decl)) { + // If this is an aggregate, emit it to LLVM now. GCC happens to + // get this case right by forcing the initializer into memory. + if (TREE_CODE(exp) == CONST_DECL || TREE_CODE(exp) == VAR_DECL) { + if ((DECL_INITIAL(exp) || !TREE_PUBLIC(exp)) && !DECL_EXTERNAL(exp) && + GV->isDeclaration() && + !BOGUS_CTOR(exp)) { + emit_global_to_llvm(exp); + Decl = DECL_LLVM(exp); // Decl could have change if it changed type. + } + } else { + // Otherwise, inform cgraph that we used the global. + mark_decl_referenced(exp); + if (tree ID = DECL_ASSEMBLER_NAME(exp)) + mark_referenced(ID); + } + } + + const Type *Ty = ConvertType(TREE_TYPE(exp)); + // If we have "extern void foo", make the global have type {} instead of + // type void. + if (Ty == Type::VoidTy) Ty = StructType::get(NULL, NULL); + const PointerType *PTy = PointerType::getUnqual(Ty); + unsigned Alignment = Ty->isSized() ? TD.getABITypeAlignment(Ty) : 1; + if (DECL_ALIGN(exp)) { + if (DECL_USER_ALIGN(exp) || 8 * Alignment < (unsigned)DECL_ALIGN(exp)) + Alignment = DECL_ALIGN(exp) / 8; + } + + return LValue(BitCastToType(Decl, PTy), Alignment); } -LValue TreeToLLVM::EmitLV_XXXXPART_EXPR(tree exp, unsigned Idx) { - LValue Ptr = EmitLV(TREE_OPERAND(exp, 0)); - assert(!Ptr.isBitfield() && - "REALPART_EXPR / IMAGPART_EXPR operands cannot be bitfields!"); - unsigned Alignment; - if (Idx == 0) - // REALPART alignment is same as the complex operand. - Alignment = Ptr.getAlignment(); - else - // IMAGPART alignment = MinAlign(Ptr.Alignment, sizeof field); - Alignment = MinAlign(Ptr.getAlignment(), - TD.getTypeAllocSize(Ptr.Ptr->getType())); - return LValue(Builder.CreateStructGEP(Ptr.Ptr, Idx), Alignment); +LValue TreeToLLVM::EmitLV_EXC_PTR_EXPR(tree exp) { + CreateExceptionValues(); + // Cast the address pointer to the expected type. + unsigned Alignment = TD.getABITypeAlignment(cast(ExceptionValue-> + getType())->getElementType()); + return LValue(BitCastToType(ExceptionValue, + PointerType::getUnqual(ConvertType(TREE_TYPE(exp)))), + Alignment); +} + +LValue TreeToLLVM::EmitLV_FILTER_EXPR(tree exp) { + CreateExceptionValues(); + unsigned Alignment = + TD.getABITypeAlignment(cast(ExceptionSelectorValue-> + getType())->getElementType()); + return LValue(ExceptionSelectorValue, Alignment); +} + +LValue TreeToLLVM::EmitLV_INDIRECT_REF(tree exp) { + // The lvalue is just the address. + LValue LV = LValue(Emit(TREE_OPERAND(exp, 0), 0), expr_align(exp) / 8); + // Correct for implicit type conversion: INDIRECT_REF can be applied to a + // void*, resulting in a non-void type. + LV.Ptr = BitCastToType(LV.Ptr, ConvertType(TREE_TYPE(exp))->getPointerTo()); + return LV; } LValue TreeToLLVM::EmitLV_VIEW_CONVERT_EXPR(tree exp) { @@ -6388,7 +6394,7 @@ // If the input is an aggregate, the address is the address of the operand. LValue LV = EmitLV(Op); // The type is the type of the expression. - LV.Ptr = BitCastToType(LV.Ptr, + LV.Ptr = BitCastToType(LV.Ptr, PointerType::getUnqual(ConvertType(TREE_TYPE(exp)))); return LV; } else { @@ -6396,30 +6402,33 @@ Value *Dest = CreateTemporary(ConvertType(TREE_TYPE(Op))); StoreInst *S = Builder.CreateStore(Emit(Op, 0), Dest); // The type is the type of the expression. - Dest = BitCastToType(Dest, + Dest = BitCastToType(Dest, PointerType::getUnqual(ConvertType(TREE_TYPE(exp)))); return LValue(Dest, 1); } } -LValue TreeToLLVM::EmitLV_EXC_PTR_EXPR(tree exp) { - CreateExceptionValues(); - // Cast the address pointer to the expected type. - unsigned Alignment = TD.getABITypeAlignment(cast(ExceptionValue-> - getType())->getElementType()); - return LValue(BitCastToType(ExceptionValue, - PointerType::getUnqual(ConvertType(TREE_TYPE(exp)))), - Alignment); +LValue TreeToLLVM::EmitLV_WITH_SIZE_EXPR(tree exp) { + // The address is the address of the operand. + return EmitLV(TREE_OPERAND(exp, 0)); } -LValue TreeToLLVM::EmitLV_FILTER_EXPR(tree exp) { - CreateExceptionValues(); - unsigned Alignment = - TD.getABITypeAlignment(cast(ExceptionSelectorValue-> - getType())->getElementType()); - return LValue(ExceptionSelectorValue, Alignment); +LValue TreeToLLVM::EmitLV_XXXXPART_EXPR(tree exp, unsigned Idx) { + LValue Ptr = EmitLV(TREE_OPERAND(exp, 0)); + assert(!Ptr.isBitfield() && + "REALPART_EXPR / IMAGPART_EXPR operands cannot be bitfields!"); + unsigned Alignment; + if (Idx == 0) + // REALPART alignment is same as the complex operand. + Alignment = Ptr.getAlignment(); + else + // IMAGPART alignment = MinAlign(Ptr.Alignment, sizeof field); + Alignment = MinAlign(Ptr.getAlignment(), + TD.getTypeAllocSize(Ptr.Ptr->getType())); + return LValue(Builder.CreateStructGEP(Ptr.Ptr, Idx), Alignment); } + //===----------------------------------------------------------------------===// // ... Constant Expressions ... //===----------------------------------------------------------------------===// Modified: llvm-gcc-4.2/trunk/gcc/llvm-internal.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-internal.h?rev=74069&r1=74068&r2=74069&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-internal.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-internal.h Wed Jun 24 03:17:34 2009 @@ -527,6 +527,7 @@ Value *EmitCEIL_DIV_EXPR(tree_node *exp); Value *EmitFLOOR_DIV_EXPR(tree_node *exp); Value *EmitROUND_DIV_EXPR(tree_node *exp); + Value *EmitFieldAnnotation(Value *FieldPtr, tree_node *FieldDecl); // Exception Handling. Value *EmitEXC_PTR_EXPR(tree_node *exp); @@ -589,15 +590,16 @@ Value *EmitComplexBinOp(tree_node *exp, const MemRef *DestLoc); // L-Value Expressions. - LValue EmitLV_DECL(tree_node *exp); LValue EmitLV_ARRAY_REF(tree_node *exp); - LValue EmitLV_COMPONENT_REF(tree_node *exp); - Value *EmitFieldAnnotation(Value *FieldPtr, tree_node *FieldDecl); LValue EmitLV_BIT_FIELD_REF(tree_node *exp); - LValue EmitLV_XXXXPART_EXPR(tree_node *exp, unsigned Idx); - LValue EmitLV_VIEW_CONVERT_EXPR(tree_node *exp); + LValue EmitLV_COMPONENT_REF(tree_node *exp); + LValue EmitLV_DECL(tree_node *exp); LValue EmitLV_EXC_PTR_EXPR(tree_node *exp); LValue EmitLV_FILTER_EXPR(tree_node *exp); + LValue EmitLV_INDIRECT_REF(tree_node *exp); + LValue EmitLV_VIEW_CONVERT_EXPR(tree_node *exp); + LValue EmitLV_WITH_SIZE_EXPR(tree_node *exp); + LValue EmitLV_XXXXPART_EXPR(tree_node *exp, unsigned Idx); // Constant Expressions. Value *EmitINTEGER_CST(tree_node *exp); From baldrick at free.fr Wed Jun 24 03:38:48 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 24 Jun 2009 08:38:48 -0000 Subject: [llvm-commits] [llvm] r74070 - /llvm/trunk/docs/ReleaseNotes-2.6.html Message-ID: <200906240838.n5O8cmYH005532@zion.cs.uiuc.edu> Author: baldrick Date: Wed Jun 24 03:38:48 2009 New Revision: 74070 URL: http://llvm.org/viewvc/llvm-project?rev=74070&view=rev Log: Start sketching 2.6 release notes. This provides a place to note major API changes (I've noted the getABITypeSize -> getAllocSize change). Added: llvm/trunk/docs/ReleaseNotes-2.6.html - copied, changed from r74068, llvm/trunk/docs/ReleaseNotes.html Copied: llvm/trunk/docs/ReleaseNotes-2.6.html (from r74068, llvm/trunk/docs/ReleaseNotes.html) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes-2.6.html?p2=llvm/trunk/docs/ReleaseNotes-2.6.html&p1=llvm/trunk/docs/ReleaseNotes.html&r1=74068&r2=74070&rev=74070&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes-2.6.html Wed Jun 24 03:38:48 2009 @@ -4,17 +4,17 @@ - LLVM 2.5 Release Notes + LLVM 2.6 Release Notes -
LLVM 2.5 Release Notes
+
LLVM 2.6 Release Notes
  1. Introduction
  2. Sub-project Status Update
    3. -
  3. External Projects Using LLVM 2.5
    4. -
  4. What's New in LLVM 2.5?
    5. +
  5. External Projects Using LLVM 2.6
    6. +
  6. What's New in LLVM 2.6?
  7. Installation Instructions
  8. Portability and Supported Platforms
  9. Known Problems
    10. @@ -34,7 +34,7 @@

    This document contains the release notes for the LLVM Compiler -Infrastructure, release 2.5. Here we describe the status of LLVM, including +Infrastructure, release 2.6. Here we describe the status of LLVM, including major improvements from the previous release and significant known problems. All LLVM releases may be downloaded from the LLVM releases web site.

    @@ -80,7 +80,7 @@

    -The LLVM 2.5 distribution currently consists of code from the core LLVM +The LLVM 2.6 distribution currently consists of code from the core LLVM repository —which roughly includes the LLVM optimizers, code generators and supporting tools — and the llvm-gcc repository. In addition to this code, the LLVM Project includes other sub-projects that are in development. The @@ -100,7 +100,7 @@

    The Clang project is an effort to build a set of new 'LLVM native' front-end technologies for the LLVM optimizer and -code generator. While Clang is not included in the LLVM 2.5 release, it is +code generator. While Clang is not included in the LLVM 2.6 release, it is continuing to make major strides forward in all areas. Its C and Objective-C parsing and code generation support is now very solid. For example, it is capable of successfully building many real-world applications for X86-32 @@ -115,20 +115,10 @@ href="http://lists.cs.uiuc.edu/mailman/listinfo/cfe-dev">Clang front-end mailing list.

    -

    In the LLVM 2.5 time-frame, the Clang team has made many improvements:

    +

    In the LLVM 2.6 time-frame, the Clang team has made many improvements:

      -
    • Clang now has a new driver, which is focused on providing a GCC-compatible - interface.
      • -
    • The X86-64 ABI is now supported, including support for the Apple - 64-bit Objective-C runtime and zero cost exception handling.
      • -
    • Precompiled header support is now implemented.
      • -
    • Objective-C support is significantly improved beyond LLVM 2.4, supporting - many features, such as Objective-C Garbage Collection.
      • -
    • Variable length arrays are now fully supported.
      • -
    • C99 designated initializers are now fully supported.
      • -
    • Clang now includes all major compiler headers, including a - redesigned tgmath.h and several more intrinsic headers.
      • +
    • Something wonderful!
    • Many many bugs are fixed and many features have been added.
    @@ -140,19 +130,14 @@
    -

    Previously announced in the last LLVM release, the Clang project also +

    Previously announced in the 2.4 LLVM release, the Clang project also includes an early stage static source code analysis tool for automatically finding bugs in C and Objective-C programs. The tool performs a growing set of checks to find bugs that occur on a specific path within a program.

    -

    In the LLVM 2.5 time-frame there have been many significant improvements to -the analyzer's core path simulation engine and machinery for generating -path-based bug reports to end-users. Particularly noteworthy improvements -include experimental support for full field-sensitivity and reasoning about heap -objects as well as an improved value-constraints subengine that does a much -better job of reasoning about inequality relationships (e.g., x > 2) -between variables and constants. +

    In the LLVM 2.6 time-frame there have been many significant improvements to +XYZ.

    The set of checks performed by the static analyzer continues to expand, and future plans for the tool include full source-level inter-procedural analysis @@ -173,38 +158,20 @@ a JVM and a CLI Virtual Machines (Microsoft .NET is an implementation of the CLI) using the Just-In-Time compiler of LLVM.

    -

    Following LLVM 2.5, VMKit has its second release that you can find on its +

    Following LLVM 2.6, VMKit has its XYZ release that you can find on its webpage. The release includes bug fixes, cleanup and new features. The major changes are:

      -
    • Ahead of Time compiler: compiles .class files to llvm .bc. VMKit uses this -functionality to native compile the standard classes (e.g. java.lang.String). -Users can compile AoT .class files into dynamic libraries and run them with the -help of VMKit.
      • - -
    • New exception model: the dwarf exception model is very slow for -exception-intensive applications, so the JVM has had a new implementation of -exceptions which check at each function call if an exception happened. There is -a low performance penalty on applications without exceptions, but it is a big -gain for exception-intensive applications. For example the jack benchmark in -Spec JVM98 is 6x faster (performance gain of 83%).
      • - -
    • User-level management of thread stacks, so that thread local data access -at runtime is fast and portable.
      • - -
    • Implementation of biased locking for faster object synchronizations at -runtime.
      • - -
    • New support for OSX/X64, Linux/X64 (with the Boehm GC) and Linux/ppc32.
      • +
    • Something wonderful!
    - External Projects Using LLVM 2.5 + External Projects Using LLVM 2.6
    @@ -243,7 +210,7 @@

    LDC is an implementation of the D Programming Language using the LLVM optimizer and code generator. -The LDC project works great with the LLVM 2.5 release. General improvements in +The LDC project works great with the LLVM 2.6 release. General improvements in this cycle have included new inline asm constraint handling, better debug info support, general bugfixes, and better x86-64 support. This has allowed @@ -267,7 +234,7 @@

    - What's New in LLVM 2.5? + What's New in LLVM 2.6?
    @@ -286,28 +253,10 @@
    -

    LLVM 2.5 includes several major new capabilities:

    +

    LLVM 2.6 includes several major new capabilities:

      -
    • LLVM 2.5 includes a brand new XCore backend.
      • - -
    • llvm-gcc now generally supports the GFortran front-end, and the precompiled -release binaries now support Fortran, even on Mac OS/X.
      • - -
    • CMake is now used by the LLVM build process -on Windows. It automatically generates Visual Studio project files (and -more) from a set of simple text files. This makes it much easier to -maintain. In time, we'd like to standardize on CMake for everything.
      • - -
    • LLVM 2.5 now uses (and includes) Google Test for unit testing.
      • - -
    • The LLVM native code generator now supports arbitrary precision integers. -Types like i33 have long been valid in the LLVM IR, but were previously -only supported by the interpreter. Note that the C backend still does not -support these.
      • - -
    • LLVM 2.5 no longer uses 'bison,' so it is easier to build on Windows.
      • +
    • Something wonderful!
    @@ -325,18 +274,7 @@ includes support for the C, C++, Objective-C, Ada, and Fortran front-ends.

      -
    • In this release, the GCC inliner is completely disabled. Previously the GCC -inliner was used to handle always-inline functions and other cases. This caused -problems with code size growth, and it is completely disabled in this -release.
      • - -
    • llvm-gcc (and LLVM in general) now support code generation for stack -canaries, which is an effective form of buffer overflow -protection. llvm-gcc supports this with the -fstack-protector -command line option (just like GCC). In LLVM IR, you can request code -generation for stack canaries with function attributes. -
      • +
    • Something wonderful!
    @@ -352,48 +290,7 @@ can be useful if you are writing a front-end for LLVM:

      -
    • The shufflevector instruction -has been generalized to allow different shuffle mask width than its input -vectors. This allows you to use shufflevector to combine two -"<4 x float>" vectors into a "<8 x float>" for example.
      • - -
    • LLVM IR now supports new intrinsics for computing and acting on overflow of integer operations. This allows -efficient code generation for languages that must trap or throw an exception on -overflow. While these intrinsics work on all targets, they only generate -efficient code on X86 so far.
      • - -
    • LLVM IR now supports a new private -linkage type to produce labels that are stripped by the assembler before it -produces a .o file (thus they are invisible to the linker).
      • - -
    • LLVM IR supports two new attributes for better alias analysis. The noalias attribute can now be used on the -return value of a function to indicate that it returns new memory (e.g. -'malloc', 'calloc', etc). -The new nocapture attribute can be used -on pointer arguments to indicate that the function does not return the pointer, -store it in an object that outlives the call, or let the value of the pointer -escape from the function in any other way. -Note that it is the pointer itself that must not escape, not the value it -points to: loading a value out of the pointer is perfectly fine. -Many standard library functions (e.g. 'strlen', 'memcpy') have this property. - -
      • - -
    • The parser for ".ll" files in lib/AsmParser is now completely rewritten as a -recursive descent parser. This parser produces better error messages (including -caret diagnostics), is less fragile (less likely to crash on strange things), -does not leak memory, is more efficient, and eliminates LLVM's last use of the -'bison' tool.
      • - -
    • Debug information representation and manipulation internals have been - consolidated to use a new set of classes in - llvm/Analysis/DebugInfo.h. These routines are more - efficient, robust, and extensible and replace the older mechanisms. - llvm-gcc, clang, and the code generator now use them to create and process - debug information.
      • - +
    • Something wonderful!
    @@ -410,21 +307,7 @@
      -
    • The loop optimizer now improves floating point induction variables in -several ways, including adding shadow induction variables to avoid -"integer <-> floating point" conversions in loops when safe.
      • - -
    • The "-mem2reg" pass is now much faster on code with large basic blocks.
      • - -
    • The "-jump-threading" pass is more powerful: it is iterative - and handles threading based on values with fully and partially redundant - loads.
      • - -
    • The "-memdep" memory dependence analysis pass (used by GVN and memcpyopt) is - both faster and more aggressive.
      • - -
    • The "-scalarrepl" scalar replacement of aggregates pass is more aggressive - about promoting unions to registers.
      • +
    • Something wonderful!
    @@ -442,33 +325,8 @@ it run faster:

      -
    • The Writing an LLVM Compiler -Backend document has been greatly expanded and is substantially more -complete.
      • - -
    • The SelectionDAG type legalization logic has been completely rewritten, is -now more powerful (it supports arbitrary precision integer types for example), -and is more correct in several corner cases. The type legalizer converts -operations on types that are not natively supported by the target machine into -equivalent code sequences that only use natively supported types. The old type -legalizer is still available (for now) and will be used if --disable-legalize-types is passed to the code generator. -
      • -
    • The code generator now supports widening illegal vectors to larger legal -ones (for example, converting operations on <3 x float> to work on -<4 x float>) which is very important for common graphics -applications.
      • - -
    • The assembly printers for each target are now split out into their own -libraries that are separate from the main code generation logic. This reduces -the code size of JIT compilers by not requiring them to be linked in.
      • - -
    • The 'fast' instruction selection path (used at -O0 and for fast JIT - compilers) now supports accelerating codegen for code that uses exception - handling constructs.
      • - -
    • The optional PBQP register allocator now supports register coalescing.
      • +
    • Something wonderful!
    @@ -482,37 +340,8 @@

      -
    • The llvm.returnaddress -intrinsic (which is used to implement __builtin_return_address) now -supports non-zero stack depths on X86.
      • - -
    • The X86 backend now supports code generation of vector shift operations -using SSE instructions.
      • - -
    • X86-64 code generation now takes advantage of red zone, unless the --mno-red-zone option is specified.
      • - -
    • The X86 backend now supports using address space #256 in LLVM IR as a way of -performing memory references off the GS segment register. This allows a -front-end to take advantage of very low-level programming techniques when -targeting X86 CPUs. See test/CodeGen/X86/movgs.ll for a simple -example.
      • - -
    • The X86 backend now supports a -disable-mmx command line option to - prevent use of MMX even on chips that support it. This is important for cases - where code does not contain the proper llvm.x86.mmx.emms - intrinsics.
      • - -
    • The X86 JIT now detects the new Intel Core i7 and Atom chips and - auto-configures itself appropriately for the features of these chips.
      • - -
    • The JIT now supports exception handling constructs on Linux/X86-64 and - Darwin/x86-64.
      • -
    • The JIT supports Thread Local Storage (TLS) on Linux/X86-32 but not yet on - X86-64.
      • +
    • Something wonderful!
    @@ -527,14 +356,7 @@

      -
    • Both direct and indirect load/stores work now.
      • -
    • Logical, bitwise and conditional operations now work for integer data -types.
      • -
    • Function calls involving basic types work now.
      • -
    • Support for integer arrays.
      • -
    • The compiler can now emit libcalls for operations not supported by m/c -instructions.
      • -
    • Support for both data and ROM address spaces.
      • +
    • Something wonderful!

    Things not yet supported:

    @@ -560,38 +382,7 @@

    New features include:

      -
    • Beginning with LLVM 2.5, llvmc2 is known as - just llvmc. The old llvmc driver was removed.
      • - -
    • The Clang plugin was substantially improved and is now enabled - by default. The command llvmc --clang can be now used as a - synonym to ccc.
      • - -
    • There is now a --check-graph option, which is supposed to catch - common errors like multiple default edges, mismatched output/input language - names and cycles. In general, these checks can't be done at compile-time - because of the need to support plugins.
      • - -
    • Plugins are now more flexible and can refer to compilation graph nodes and - options defined in other plugins. To manage dependencies, a priority-sorting - mechanism was introduced. This change affects the TableGen file syntax. See the - documentation for details.
      • - -
    • Hooks can now be provided with arguments. The syntax is "$CALL(MyHook, - 'Arg1', 'Arg2', 'Arg3')".
      • - -
    • A new option type: multi-valued option, for options that take more than one - argument (for example, "-foo a b c").
      • - -
    • New option properties: 'one_or_more', 'zero_or_more', -'hidden' and 'really_hidden'.
      • - -
    • The 'case' expression gained an 'error' action and - an 'empty' test (equivalent to "(not (not_empty ...))").
      • - -
    • Documentation now looks more consistent to the rest of the LLVM - docs. There is also a man page now.
      • - +
    • Something wonderful!
    @@ -610,7 +401,7 @@
      -
    • llvm-gcc defaults to -fno-math-errno on all X86 targets.
      • +
    • Something horrible!
    @@ -619,8 +410,7 @@ API changes are:

      -
    • Some deprecated interfaces to create Instruction subclasses, that - were spelled with lower case "create," have been removed.
      • +
    • The getABITypeSize methods are now called getAllocSize.
    From xerxes at zafena.se Wed Jun 24 04:49:58 2009 From: xerxes at zafena.se (=?ISO-8859-1?Q?Xerxes_R=E5nby?=) Date: Wed, 24 Jun 2009 11:49:58 +0200 Subject: [llvm-commits] [patch] fix linking of llvm-mc with cmake Message-ID: <4A41F6C6.9040609@zafena.se> The problem (building llvm r74068 with cmake): Scanning dependencies of target llvm-mc [ 96%] Building CXX object tools/llvm-mc/CMakeFiles/llvm-mc.dir/llvm-mc.cpp.o [ 96%] Building CXX object tools/llvm-mc/CMakeFiles/llvm-mc.dir/AsmLexer.cpp.o [ 97%] Building CXX object tools/llvm-mc/CMakeFiles/llvm-mc.dir/AsmParser.cpp.o [ 97%] Building CXX object tools/llvm-mc/CMakeFiles/llvm-mc.dir/MC-X86Specific.cpp.o Linking CXX executable ../../bin/llvm-mc CMakeFiles/llvm-mc.dir/llvm-mc.cpp.o: In function `AssembleInput(char const*)': llvm-mc.cpp:(.text+0x51c): undefined reference to `llvm::createAsmStreamer(llvm::MCContext&, llvm::raw_ostream&)' collect2: ld returnerade avslutningsstatus 1 make[2]: *** [bin/llvm-mc] Fel 1 make[1]: *** [tools/llvm-mc/CMakeFiles/llvm-mc.dir/all] Fel 2 make: *** [all] Fel 2 The solution: The attached patch makes sure that createAsmStreamer are compiled into libLLVMMC. Cheers Xerxes -------------- next part -------------- A non-text attachment was scrubbed... Name: LLVMMC_cmake.patch Type: text/x-patch Size: 343 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090624/8a9714bf/attachment.bin From baldrick at free.fr Wed Jun 24 05:04:15 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 24 Jun 2009 10:04:15 -0000 Subject: [llvm-commits] [llvm] r74071 - /llvm/trunk/lib/MC/CMakeLists.txt Message-ID: <200906241004.n5OA4LJx008872@zion.cs.uiuc.edu> Author: baldrick Date: Wed Jun 24 05:03:44 2009 New Revision: 74071 URL: http://llvm.org/viewvc/llvm-project?rev=74071&view=rev Log: Add new files to cmake list. Modified: llvm/trunk/lib/MC/CMakeLists.txt Modified: llvm/trunk/lib/MC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/CMakeLists.txt?rev=74071&r1=74070&r2=74071&view=diff ============================================================================== --- llvm/trunk/lib/MC/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/CMakeLists.txt Wed Jun 24 05:03:44 2009 @@ -1,3 +1,5 @@ add_llvm_library(LLVMMC + MCAsmStreamer.cpp MCContext.cpp + MCStreamer.cpp ) From baldrick at free.fr Wed Jun 24 05:08:18 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 24 Jun 2009 12:08:18 +0200 Subject: [llvm-commits] [patch] fix linking of llvm-mc with cmake In-Reply-To: <4A41F6C6.9040609@zafena.se> References: <4A41F6C6.9040609@zafena.se> Message-ID: <4A41FB12.5070506@free.fr> > The solution: > The attached patch makes sure that createAsmStreamer are compiled into > libLLVMMC. Applied, thanks. Duncan. From gohman at apple.com Wed Jun 24 09:31:09 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 14:31:09 -0000 Subject: [llvm-commits] [llvm] r74072 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarSimplify/loop_evaluate7.ll Message-ID: <200906241431.n5OEVBLH018224@zion.cs.uiuc.edu> Author: djg Date: Wed Jun 24 09:31:06 2009 New Revision: 74072 URL: http://llvm.org/viewvc/llvm-project?rev=74072&view=rev Log: When inserting code into a loop preheader, insert it before the terminator, instead of after the last phi. This fixes a bug exposed by ScalarEvolution analyzing more kinds of loops. This fixes PR4436. Added: llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=74072&r1=74071&r2=74072&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Wed Jun 24 09:31:06 2009 @@ -230,13 +230,16 @@ // We insert the code into the preheader of the loop if the loop contains // multiple exit blocks, or in the exit block if there is exactly one. BasicBlock *BlockToInsertInto; + BasicBlock::iterator InsertPt; SmallVector ExitBlocks; L->getUniqueExitBlocks(ExitBlocks); - if (ExitBlocks.size() == 1) + if (ExitBlocks.size() == 1) { BlockToInsertInto = ExitBlocks[0]; - else + InsertPt = BlockToInsertInto->getFirstNonPHI(); + } else { BlockToInsertInto = Preheader; - BasicBlock::iterator InsertPt = BlockToInsertInto->getFirstNonPHI(); + InsertPt = BlockToInsertInto->getTerminator(); + } std::map ExitValues; Added: llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll?rev=74072&view=auto ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll (added) +++ llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll Wed Jun 24 09:31:06 2009 @@ -0,0 +1,61 @@ +; RUN: llvm-as < %s | opt -indvars +; PR4436 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" +target triple = "i386-pc-linux-gnu" + +define i8* @string_expandtabs() nounwind { +entry: + br i1 undef, label %bb33, label %bb1 + +bb1: ; preds = %entry + br i1 undef, label %overflow1, label %bb15 + +bb15: ; preds = %bb1 + br i1 undef, label %bb33, label %bb17 + +bb17: ; preds = %bb15 + br label %bb30 + +bb19: ; preds = %bb30 + br i1 undef, label %bb20, label %bb29 + +bb20: ; preds = %bb19 + %0 = load i32* undef, align 4 ; [#uses=1] + %1 = sub i32 %0, undef ; [#uses=1] + br label %bb23 + +bb21: ; preds = %bb23 + %2 = icmp ult i8* %q.0, undef ; [#uses=1] + br i1 %2, label %bb22, label %overflow2 + +bb22: ; preds = %bb21 + %3 = getelementptr i8* %q.0, i32 1 ; [#uses=1] + br label %bb23 + +bb23: ; preds = %bb22, %bb20 + %i.2 = phi i32 [ %1, %bb20 ], [ %4, %bb22 ] ; [#uses=1] + %q.0 = phi i8* [ undef, %bb20 ], [ %3, %bb22 ] ; [#uses=3] + %4 = add i32 %i.2, -1 ; [#uses=2] + %5 = icmp eq i32 %4, -1 ; [#uses=1] + br i1 %5, label %bb29, label %bb21 + +bb29: ; preds = %bb23, %bb19 + %q.1 = phi i8* [ undef, %bb19 ], [ %q.0, %bb23 ] ; [#uses=0] + br label %bb30 + +bb30: ; preds = %bb29, %bb17 + br i1 undef, label %bb19, label %bb33 + +overflow2: ; preds = %bb21 + br i1 undef, label %bb32, label %overflow1 + +bb32: ; preds = %overflow2 + br label %overflow1 + +overflow1: ; preds = %bb32, %overflow2, %bb1 + ret i8* null + +bb33: ; preds = %bb30, %bb15, %entry + ret i8* undef +} From gohman at apple.com Wed Jun 24 09:46:36 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 14:46:36 -0000 Subject: [llvm-commits] [llvm] r74073 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Transforms/IndVarSimplify/loop_evaluate7.ll test/Transforms/IndVarSimplify/loop_evaluate8.ll Message-ID: <200906241446.n5OEkbfr019015@zion.cs.uiuc.edu> Author: djg Date: Wed Jun 24 09:46:22 2009 New Revision: 74073 URL: http://llvm.org/viewvc/llvm-project?rev=74073&view=rev Log: Simplify [su]max(MAX, n) to MAX. This comes up in loop tripcount computations in loops with multiple exits. Adjust the testcase for PR4436 so that the relevant portion isn't optimized away. Added: llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate8.ll (contents, props changed) - copied, changed from r74072, llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=74073&r1=74072&r2=74073&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Jun 24 09:46:22 2009 @@ -1690,10 +1690,14 @@ LHSC = cast(Ops[0]); } - // If we are left with a constant -inf, strip it off. + // If we are left with a constant minimum-int, strip it off. if (cast(Ops[0])->getValue()->isMinValue(true)) { Ops.erase(Ops.begin()); --Idx; + } else if (cast(Ops[0])->getValue()->isMaxValue(true)) { + // If we have an smax with a constant maximum-int, it will always be + // maximum-int. + return Ops[0]; } } @@ -1777,10 +1781,14 @@ LHSC = cast(Ops[0]); } - // If we are left with a constant zero, strip it off. + // If we are left with a constant minimum-int, strip it off. if (cast(Ops[0])->getValue()->isMinValue(false)) { Ops.erase(Ops.begin()); --Idx; + } else if (cast(Ops[0])->getValue()->isMaxValue(false)) { + // If we have an umax with a constant maximum-int, it will always be + // maximum-int. + return Ops[0]; } } Modified: llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll?rev=74073&r1=74072&r2=74073&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll Wed Jun 24 09:46:22 2009 @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target triple = "i386-pc-linux-gnu" -define i8* @string_expandtabs() nounwind { +define i8* @string_expandtabs(i32 %n, i8* %m) nounwind { entry: br i1 undef, label %bb33, label %bb1 @@ -22,11 +22,11 @@ bb20: ; preds = %bb19 %0 = load i32* undef, align 4 ; [#uses=1] - %1 = sub i32 %0, undef ; [#uses=1] + %1 = sub i32 %0, %n ; [#uses=1] br label %bb23 bb21: ; preds = %bb23 - %2 = icmp ult i8* %q.0, undef ; [#uses=1] + %2 = icmp ult i8* %q.0, %m ; [#uses=1] br i1 %2, label %bb22, label %overflow2 bb22: ; preds = %bb21 Copied: llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate8.ll (from r74072, llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate8.ll?p2=llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate8.ll&p1=llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll&r1=74072&r2=74073&rev=74073&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate7.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate8.ll Wed Jun 24 09:46:22 2009 @@ -1,5 +1,7 @@ -; RUN: llvm-as < %s | opt -indvars -; PR4436 +; RUN: llvm-as < %s | opt -indvars | llvm-dis | not grep select + +; This loop has backedge-taken-count zero. Indvars shouldn't expand any +; instructions to compute a trip count. target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target triple = "i386-pc-linux-gnu" Propchange: llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate8.ll ------------------------------------------------------------------------------ svn:mergeinfo = From gohman at apple.com Wed Jun 24 09:49:01 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 14:49:01 -0000 Subject: [llvm-commits] [llvm] r74074 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <200906241449.n5OEn1Ip019198@zion.cs.uiuc.edu> Author: djg Date: Wed Jun 24 09:49:00 2009 New Revision: 74074 URL: http://llvm.org/viewvc/llvm-project?rev=74074&view=rev Log: Minor whitespace cleanups. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=74074&r1=74073&r2=74074&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Jun 24 09:49:00 2009 @@ -1508,8 +1508,8 @@ /// getUDivExpr - Get a canonical multiply expression, or something simpler if /// possible. -const SCEV* ScalarEvolution::getUDivExpr(const SCEV* LHS, - const SCEV* RHS) { +const SCEV *ScalarEvolution::getUDivExpr(const SCEV *LHS, + const SCEV *RHS) { assert(getEffectiveSCEVType(LHS->getType()) == getEffectiveSCEVType(RHS->getType()) && "SCEVUDivExpr operand types don't match!"); @@ -1652,8 +1652,8 @@ return Result; } -const SCEV* ScalarEvolution::getSMaxExpr(const SCEV* LHS, - const SCEV* RHS) { +const SCEV *ScalarEvolution::getSMaxExpr(const SCEV *LHS, + const SCEV *RHS) { SmallVector Ops; Ops.push_back(LHS); Ops.push_back(RHS); @@ -1743,8 +1743,8 @@ return Result; } -const SCEV* ScalarEvolution::getUMaxExpr(const SCEV* LHS, - const SCEV* RHS) { +const SCEV *ScalarEvolution::getUMaxExpr(const SCEV *LHS, + const SCEV *RHS) { SmallVector Ops; Ops.push_back(LHS); Ops.push_back(RHS); @@ -1834,14 +1834,14 @@ return Result; } -const SCEV* ScalarEvolution::getSMinExpr(const SCEV* LHS, - const SCEV* RHS) { +const SCEV *ScalarEvolution::getSMinExpr(const SCEV *LHS, + const SCEV *RHS) { // ~smax(~x, ~y) == smin(x, y). return getNotSCEV(getSMaxExpr(getNotSCEV(LHS), getNotSCEV(RHS))); } -const SCEV* ScalarEvolution::getUMinExpr(const SCEV* LHS, - const SCEV* RHS) { +const SCEV *ScalarEvolution::getUMinExpr(const SCEV *LHS, + const SCEV *RHS) { // ~umax(~x, ~y) == umin(x, y) return getNotSCEV(getUMaxExpr(getNotSCEV(LHS), getNotSCEV(RHS))); } @@ -1960,8 +1960,8 @@ /// getMinusSCEV - Return a SCEV corresponding to LHS - RHS. /// -const SCEV* ScalarEvolution::getMinusSCEV(const SCEV* LHS, - const SCEV* RHS) { +const SCEV *ScalarEvolution::getMinusSCEV(const SCEV *LHS, + const SCEV *RHS) { // X - Y --> X + -Y return getAddExpr(LHS, getNegativeSCEV(RHS)); } @@ -2067,8 +2067,8 @@ /// getUMaxFromMismatchedTypes - Promote the operands to the wider of /// the types using zero-extension, and then perform a umax operation /// with them. -const SCEV* ScalarEvolution::getUMaxFromMismatchedTypes(const SCEV* LHS, - const SCEV* RHS) { +const SCEV *ScalarEvolution::getUMaxFromMismatchedTypes(const SCEV *LHS, + const SCEV *RHS) { const SCEV* PromotedLHS = LHS; const SCEV* PromotedRHS = RHS; @@ -2083,8 +2083,8 @@ /// getUMinFromMismatchedTypes - Promote the operands to the wider of /// the types using zero-extension, and then perform a umin operation /// with them. -const SCEV* ScalarEvolution::getUMinFromMismatchedTypes(const SCEV* LHS, - const SCEV* RHS) { +const SCEV *ScalarEvolution::getUMinFromMismatchedTypes(const SCEV *LHS, + const SCEV *RHS) { const SCEV* PromotedLHS = LHS; const SCEV* PromotedRHS = RHS; From daniel at zuster.org Wed Jun 24 11:05:41 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 24 Jun 2009 16:05:41 -0000 Subject: [llvm-commits] [llvm] r74076 - in /llvm/trunk: lib/MC/MCAsmStreamer.cpp unittests/MC/AsmStreamerTest.cpp Message-ID: <200906241605.n5OG5jmS022675@zion.cs.uiuc.edu> Author: ddunbar Date: Wed Jun 24 11:05:35 2009 New Revision: 74076 URL: http://llvm.org/viewvc/llvm-project?rev=74076&view=rev Log: MCStreamer: Test printing values. Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/unittests/MC/AsmStreamerTest.cpp Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=74076&r1=74075&r2=74076&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Jun 24 11:05:35 2009 @@ -121,7 +121,7 @@ default: assert(0 && "Invalid size for machine code value!"); case 1: OS << ".byte"; break; - case 2: OS << ".hword"; break; + case 2: OS << ".short"; break; case 4: OS << ".long"; break; case 8: OS << ".quad"; break; } Modified: llvm/trunk/unittests/MC/AsmStreamerTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/MC/AsmStreamerTest.cpp?rev=74076&r1=74075&r2=74076&view=diff ============================================================================== --- llvm/trunk/unittests/MC/AsmStreamerTest.cpp (original) +++ llvm/trunk/unittests/MC/AsmStreamerTest.cpp Wed Jun 24 11:05:35 2009 @@ -10,6 +10,7 @@ #include "gtest/gtest.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCValue.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -49,4 +50,28 @@ EXPECT_EQ(S.getString(), ".section foo\n"); } +TEST(AsmStreamer, Values) { + StringAsmStreamer S; + MCSection *Sec0 = S.getContext().GetSection("foo"); + MCSymbol *A = S.getContext().CreateSymbol(S.getContext().CreateAtom(Sec0), + "a"); + MCSymbol *B = S.getContext().CreateSymbol(S.getContext().CreateAtom(Sec0), + "b"); + S.getStreamer().SwitchSection(Sec0); + S.getStreamer().EmitLabel(A); + S.getStreamer().EmitLabel(B); + S.getStreamer().EmitValue(MCValue::get(A, B, 10), 1); + S.getStreamer().EmitValue(MCValue::get(A, B, 10), 2); + S.getStreamer().EmitValue(MCValue::get(A, B, 10), 4); + S.getStreamer().EmitValue(MCValue::get(A, B, 10), 8); + EXPECT_EQ(S.getString(), ".section foo\n\ +a:\n\ +b:\n\ +.byte a - b + 10\n\ +.short a - b + 10\n\ +.long a - b + 10\n\ +.quad a - b + 10\n\ +"); +} + } From daniel at zuster.org Wed Jun 24 11:36:58 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 24 Jun 2009 16:36:58 -0000 Subject: [llvm-commits] [llvm] r74077 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/MC/MCAsmStreamer.cpp Message-ID: <200906241636.n5OGaxVG023971@zion.cs.uiuc.edu> Author: ddunbar Date: Wed Jun 24 11:36:52 2009 New Revision: 74077 URL: http://llvm.org/viewvc/llvm-project?rev=74077&view=rev Log: MCStreamer: Add a few more "symbol attributes". Modified: llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/lib/MC/MCAsmStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=74077&r1=74076&r2=74077&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Wed Jun 24 11:36:52 2009 @@ -23,9 +23,21 @@ class MCStreamer { public: enum SymbolAttr { - Global, - Weak, - PrivateExtern + Global, /// .globl + Hidden, /// .hidden (ELF) + IndirectSymbol, /// .indirect_symbol (Apple) + Internal, /// .internal (ELF) + LazyReference, /// .lazy_reference (Apple) + NoDeadStrip, /// .no_dead_strip (Apple) + PrivateExtern, /// .private_extern (Apple) + Protected, /// .protected (ELF) + Reference, /// .reference (Apple) + Weak, /// .weak + WeakDefinition, /// .weak_definition (Apple) + WeakReference, /// .weak_reference (Apple) + + SymbolAttrFirst = Global, + SymbolAttrLast = WeakReference }; private: Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=74077&r1=74076&r2=74077&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Jun 24 11:36:52 2009 @@ -102,8 +102,17 @@ SymbolAttr Attribute) { switch (Attribute) { case Global: OS << ".globl"; break; - case Weak: OS << ".weak"; break; + case Hidden: OS << ".hidden"; break; + case IndirectSymbol: OS << ".indirect_symbol"; break; + case Internal: OS << ".internal"; break; + case LazyReference: OS << ".lazy_reference"; break; + case NoDeadStrip: OS << ".no_dead_strip"; break; case PrivateExtern: OS << ".private_extern"; break; + case Protected: OS << ".protected"; break; + case Reference: OS << ".reference"; break; + case Weak: OS << ".weak"; break; + case WeakDefinition: OS << ".weak_definition"; break; + case WeakReference: OS << ".weak_reference"; break; } OS << ' ' << Symbol->getName() << '\n'; From bob.wilson at apple.com Wed Jun 24 11:39:00 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 24 Jun 2009 16:39:00 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r74078 - /llvm-gcc-4.2/trunk/gcc/Makefile.in Message-ID: <200906241639.n5OGd1mq024039@zion.cs.uiuc.edu> Author: bwilson Date: Wed Jun 24 11:38:59 2009 New Revision: 74078 URL: http://llvm.org/viewvc/llvm-project?rev=74078&view=rev Log: Fix Apple-style build: Use renamed initialization functions with C linkage. Modified: llvm-gcc-4.2/trunk/gcc/Makefile.in Modified: llvm-gcc-4.2/trunk/gcc/Makefile.in URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/Makefile.in?rev=74078&r1=74077&r2=74078&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/Makefile.in (original) +++ llvm-gcc-4.2/trunk/gcc/Makefile.in Wed Jun 24 11:38:59 2009 @@ -1175,9 +1175,9 @@ ## Target symbols to force linking. This is to ensure that the code generators ## and asm printers actually get linked into libllvmgcc.dylib. LLVMTARGETSYMBOLS := \ - __ZN4llvm19InitializeARMTargetEv __ZN4llvm23InitializeARMAsmPrinterEv \ - __ZN4llvm23InitializePowerPCTargetEv __ZN4llvm27InitializePowerPCAsmPrinterEv\ - __ZN4llvm19InitializeX86TargetEv __ZN4llvm23InitializeX86AsmPrinterEv \ + _LLVMInitializeARMTarget _LLVMInitializeARMAsmPrinter \ + _LLVMInitializePowerPCTarget _LLVMInitializePowerPCAsmPrinter\ + _LLVMInitializeX86Target _LLVMInitializeX86AsmPrinter \ endif From daniel at zuster.org Wed Jun 24 12:00:43 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 24 Jun 2009 17:00:43 -0000 Subject: [llvm-commits] [llvm] r74081 - in /llvm/trunk: include/llvm/MC/MCAtom.h include/llvm/MC/MCContext.h include/llvm/MC/MCStreamer.h include/llvm/MC/MCSymbol.h lib/MC/MCAsmStreamer.cpp lib/MC/MCContext.cpp unittests/MC/AsmStreamerTest.cpp Message-ID: <200906241700.n5OH0hdf025297@zion.cs.uiuc.edu> Author: ddunbar Date: Wed Jun 24 12:00:42 2009 New Revision: 74081 URL: http://llvm.org/viewvc/llvm-project?rev=74081&view=rev Log: We decided to not worry about Atoms for now, it should be straightforward to reintroduce them later. Also, don't require MCSection* when creating a symbol. Removed: llvm/trunk/include/llvm/MC/MCAtom.h Modified: llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/include/llvm/MC/MCSymbol.h llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/unittests/MC/AsmStreamerTest.cpp Removed: llvm/trunk/include/llvm/MC/MCAtom.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAtom.h?rev=74080&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCAtom.h (original) +++ llvm/trunk/include/llvm/MC/MCAtom.h (removed) @@ -1,26 +0,0 @@ -//===- MCAtom.h - Machine Code Atoms ----------------------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_MC_MCATOM_H -#define LLVM_MC_MCATOM_H - -namespace llvm { - - class MCAtom { - MCSection *Section; - - public: - MCAtom(MCSection *_Section) : Section(_Section) {} - - MCSection *getSection() { return Section; } - }; - -} // end namespace llvm - -#endif Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=74081&r1=74080&r2=74081&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Wed Jun 24 12:00:42 2009 @@ -15,7 +15,6 @@ #include "llvm/Support/Allocator.h" namespace llvm { - class MCAtom; class MCValue; class MCSection; class MCSymbol; @@ -47,14 +46,10 @@ /// GetSection - Get or create a new section with the given @param Name. MCSection *GetSection(const char *Name); - /// CreateAtom - Create a new atom inside @param Section. - MCAtom *CreateAtom(MCSection *Section); - - /// CreateSymbol - Create a new symbol inside @param Atom with the specified - /// @param Name. + /// CreateSymbol - Create a new symbol with the specified @param Name. /// /// @param Name - The symbol name, which must be unique across all symbols. - MCSymbol *CreateSymbol(MCAtom *Atom, const char *Name); + MCSymbol *CreateSymbol(const char *Name); /// GetOrCreateSymbol - Lookup the symbol inside with the specified /// @param Name. If it exists, return it. If not, create a forward @@ -63,13 +58,13 @@ /// @param Name - The symbol name, which must be unique across all symbols. MCSymbol *GetOrCreateSymbol(const char *Name); - /// CreateTemporarySymbol - Create a new temporary symbol inside @param Atom - /// with the specified @param Name. + /// CreateTemporarySymbol - Create a new temporary symbol with the specified + /// @param Name. /// /// @param Name - The symbol name, for debugging purposes only, temporary /// symbols do not surive assembly. If non-empty the name must be unique /// across all symbols. - MCSymbol *CreateTemporarySymbol(MCAtom *Atom, const char *Name = ""); + MCSymbol *CreateTemporarySymbol(const char *Name = ""); /// LookupSymbol - Get the symbol for @param Name, or null. MCSymbol *LookupSymbol(const char *Name) const; Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=74081&r1=74080&r2=74081&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Wed Jun 24 12:00:42 2009 @@ -11,7 +11,6 @@ #define LLVM_MC_MCSTREAMER_H namespace llvm { - class MCAtom; class MCContext; class MCValue; class MCInst; Modified: llvm/trunk/include/llvm/MC/MCSymbol.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSymbol.h?rev=74081&r1=74080&r2=74081&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSymbol.h (original) +++ llvm/trunk/include/llvm/MC/MCSymbol.h Wed Jun 24 12:00:42 2009 @@ -13,20 +13,19 @@ #include namespace llvm { - class MCAtom; - class MCSymbol { - MCAtom *Atom; + MCSection *Section; std::string Name; unsigned IsTemporary : 1; public: - MCSymbol(MCAtom *_Atom, const char *_Name, bool _IsTemporary) - : Atom(_Atom), Name(_Name), IsTemporary(_IsTemporary) {} + MCSymbol(const char *_Name, bool _IsTemporary) + : Section(0), Name(_Name), IsTemporary(_IsTemporary) {} - MCAtom *getAtom() { return Atom; } + MCSection *getSection() const { return Section; } + void setSection(MCSection *Value) { Section = Value; } - const std::string &getName() { return Name; } + const std::string &getName() const { return Name; } }; } // end namespace llvm Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=74081&r1=74080&r2=74081&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Jun 24 12:00:42 2009 @@ -9,7 +9,6 @@ #include "llvm/MC/MCStreamer.h" -#include "llvm/MC/MCAtom.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCSection.h" #include "llvm/MC/MCSymbol.h" @@ -82,20 +81,26 @@ } void MCAsmStreamer::EmitLabel(MCSymbol *Symbol) { - // FIXME: We need to enforce that we aren't printing atoms which are more - // complicated than the assembler understands. - //assert(Symbol->getAtom()->getSection() == CurSection && - // "The label for a symbol must match its section!"); + assert(Symbol->getSection() == 0 && "Cannot emit a symbol twice!"); + assert(CurSection && "Cannot emit before setting section!"); + assert(!getContext().GetSymbolValue(Symbol) && + "Cannot emit symbol which was directly assigned to!"); + OS << Symbol->getName() << ":\n"; + Symbol->setSection(CurSection); } void MCAsmStreamer::EmitAssignment(MCSymbol *Symbol, const MCValue &Value, bool MakeAbsolute) { + assert(!Symbol->getSection() && "Cannot assign to a label!"); + if (MakeAbsolute) { OS << ".set " << Symbol->getName() << ", " << Value << '\n'; } else { OS << Symbol->getName() << " = " << Value << '\n'; } + + getContext().SetSymbolValue(Symbol, Value); } void MCAsmStreamer::EmitSymbolAttribute(MCSymbol *Symbol, @@ -119,12 +124,13 @@ } void MCAsmStreamer::EmitBytes(const char *Data, unsigned Length) { - for (unsigned i = 0; i != Length; ++i) { + assert(CurSection && "Cannot emit contents before setting section!"); + for (unsigned i = 0; i != Length; ++i) OS << ".byte " << (unsigned) Data[i] << '\n'; - } } void MCAsmStreamer::EmitValue(const MCValue &Value, unsigned Size) { + assert(CurSection && "Cannot emit contents before setting section!"); // Need target hooks to know how to print this. switch (Size) { default: @@ -139,6 +145,7 @@ } void MCAsmStreamer::EmitInstruction(const MCInst &Inst) { + assert(CurSection && "Cannot emit contents before setting section!"); // FIXME: Implement. OS << "# FIXME: Implement instruction printing!\n"; } Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=74081&r1=74080&r2=74081&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Wed Jun 24 12:00:42 2009 @@ -9,7 +9,6 @@ #include "llvm/MC/MCContext.h" -#include "llvm/MC/MCAtom.h" #include "llvm/MC/MCSection.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCValue.h" @@ -30,43 +29,33 @@ return Entry; } - -MCAtom *MCContext::CreateAtom(MCSection *Section) { - return new (*this) MCAtom(Section); -} -MCSymbol *MCContext::CreateSymbol(MCAtom *Atom, const char *Name) { +MCSymbol *MCContext::CreateSymbol(const char *Name) { assert(Name[0] != '\0' && "Normal symbols cannot be unnamed!"); // Create and bind the symbol, and ensure that names are unique. MCSymbol *&Entry = Symbols[Name]; assert(!Entry && "Duplicate symbol definition!"); - return Entry = new (*this) MCSymbol(Atom, Name, false); + return Entry = new (*this) MCSymbol(Name, false); } -/// GetOrCreateSymbol - Lookup the symbol inside with the specified -/// @param Name. If it exists, return it. If not, create a forward -/// reference and return it. -/// -/// @param Name - The symbol name, which must be unique across all symbols. MCSymbol *MCContext::GetOrCreateSymbol(const char *Name) { MCSymbol *&Entry = Symbols[Name]; if (Entry) return Entry; - // FIXME: is a null atom the right way to make a forward ref? - return Entry = new (*this) MCSymbol(0, Name, false); + return Entry = new (*this) MCSymbol(Name, false); } -MCSymbol *MCContext::CreateTemporarySymbol(MCAtom *Atom, const char *Name) { +MCSymbol *MCContext::CreateTemporarySymbol(const char *Name) { // If unnamed, just create a symbol. if (Name[0] == '\0') - new (*this) MCSymbol(Atom, "", true); + new (*this) MCSymbol("", true); // Otherwise create as usual. MCSymbol *&Entry = Symbols[Name]; assert(!Entry && "Duplicate symbol definition!"); - return Entry = new (*this) MCSymbol(Atom, Name, true); + return Entry = new (*this) MCSymbol(Name, true); } MCSymbol *MCContext::LookupSymbol(const char *Name) const { Modified: llvm/trunk/unittests/MC/AsmStreamerTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/MC/AsmStreamerTest.cpp?rev=74081&r1=74080&r2=74081&view=diff ============================================================================== --- llvm/trunk/unittests/MC/AsmStreamerTest.cpp (original) +++ llvm/trunk/unittests/MC/AsmStreamerTest.cpp Wed Jun 24 12:00:42 2009 @@ -53,10 +53,8 @@ TEST(AsmStreamer, Values) { StringAsmStreamer S; MCSection *Sec0 = S.getContext().GetSection("foo"); - MCSymbol *A = S.getContext().CreateSymbol(S.getContext().CreateAtom(Sec0), - "a"); - MCSymbol *B = S.getContext().CreateSymbol(S.getContext().CreateAtom(Sec0), - "b"); + MCSymbol *A = S.getContext().CreateSymbol("a"); + MCSymbol *B = S.getContext().CreateSymbol("b"); S.getStreamer().SwitchSection(Sec0); S.getStreamer().EmitLabel(A); S.getStreamer().EmitLabel(B); From dalej at apple.com Wed Jun 24 12:11:33 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 24 Jun 2009 17:11:33 -0000 Subject: [llvm-commits] [llvm] r74082 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200906241711.n5OHBYMl025909@zion.cs.uiuc.edu> Author: johannes Date: Wed Jun 24 12:11:31 2009 New Revision: 74082 URL: http://llvm.org/viewvc/llvm-project?rev=74082&view=rev Log: Rewrite 73900 per Duncan's suggestion. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=74082&r1=74081&r2=74082&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jun 24 12:11:31 2009 @@ -3181,27 +3181,17 @@ } else { // The type might not be legal for the target. This should only happen // if the type is smaller than a legal type, as on PPC, so the right - // thing to do is generate a LoadExt/StoreTrunc pair. + // thing to do is generate a LoadExt/StoreTrunc pair. These simplify + // to Load/Store if NVT==VT. // FIXME does the case above also need this? - if (TLI.isTypeLegal(VT)) { - Value = DAG.getLoad(VT, dl, Chain, - getMemBasePlusOffset(Src, SrcOff, DAG), - SrcSV, SrcSVOff + SrcOff, false, Align); - Store = DAG.getStore(Chain, dl, Value, + MVT NVT = TLI.getTypeToTransformTo(VT); + assert(NVT.bitsGE(VT)); + Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain, + getMemBasePlusOffset(Src, SrcOff, DAG), + SrcSV, SrcSVOff + SrcOff, VT, false, Align); + Store = DAG.getTruncStore(Chain, dl, Value, getMemBasePlusOffset(Dst, DstOff, DAG), - DstSV, DstSVOff + DstOff, false, DstAlign); - } else { - MVT NVT = VT; - while (!TLI.isTypeLegal(NVT)) { - NVT = (MVT::SimpleValueType(NVT.getSimpleVT() + 1)); - } - Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain, - getMemBasePlusOffset(Src, SrcOff, DAG), - SrcSV, SrcSVOff + SrcOff, VT, false, Align); - Store = DAG.getTruncStore(Chain, dl, Value, - getMemBasePlusOffset(Dst, DstOff, DAG), - DstSV, DstSVOff + DstOff, VT, false, DstAlign); - } + DstSV, DstSVOff + DstOff, VT, false, DstAlign); } OutChains.push_back(Store); SrcOff += VTSize; From gohman at apple.com Wed Jun 24 12:29:20 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 24 Jun 2009 10:29:20 -0700 Subject: [llvm-commits] [PATCH] Scaffolding for LDA pass. In-Reply-To: <1245796690-sup-9594@strider> References: <1245796690-sup-9594@strider> Message-ID: <1E8830D0-2237-4DBC-B56C-48FCB6EB3A7D@apple.com> Hi Andreas, This patch looks fine. If you have commit access, feel free to commit it. Otherwise I or someone else can commit it for you. Dan On Jun 23, 2009, at 3:51 PM, Andreas Bolka wrote: > I am working on auto-vectorization/loop dependence analysis as part of > Google's Summer of Code program. > > Here's a patch to add a minimal skeleton for a loop dependence > analysis > pass. > > While this pass currently does nothing, it allows future patches to be > constrained to only modify the .h and .cpp, which should make them > easier to review. > > Comments welcome! > > --- > include/llvm/Analysis/LoopDependenceAnalysis.h | 52 +++++++++++++++ > +++++++++ > include/llvm/Analysis/Passes.h | 8 ++++ > include/llvm/LinkAllPasses.h | 1 + > lib/Analysis/CMakeLists.txt | 1 + > lib/Analysis/LoopDependenceAnalysis.cpp | 47 +++++++++++++++ > ++++++ > 5 files changed, 109 insertions(+), 0 deletions(-) > create mode 100644 include/llvm/Analysis/LoopDependenceAnalysis.h > create mode 100644 lib/Analysis/LoopDependenceAnalysis.cpp > > -- > Andreas > > <01-lda-scaffolding.patch> > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From resistor at mac.com Wed Jun 24 12:37:11 2009 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Jun 2009 17:37:11 -0000 Subject: [llvm-commits] [llvm] r74084 - in /llvm/trunk: include/llvm/Support/DOTGraphTraits.h include/llvm/Support/GraphWriter.h lib/Analysis/CFGPrinter.cpp lib/CodeGen/MachineFunction.cpp lib/CodeGen/ScheduleDAGPrinter.cpp lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp lib/CompilerDriver/CompilationGraph.cpp tools/opt/GraphPrinters.cpp Message-ID: <200906241737.n5OHbClE026907@zion.cs.uiuc.edu> Author: resistor Date: Wed Jun 24 12:37:09 2009 New Revision: 74084 URL: http://llvm.org/viewvc/llvm-project?rev=74084&view=rev Log: Get rid of the global CFGOnly flag by threading a ShortNames parameters through the GraphViz rendering code. Update other uses in the codebase for this change. Modified: llvm/trunk/include/llvm/Support/DOTGraphTraits.h llvm/trunk/include/llvm/Support/GraphWriter.h llvm/trunk/lib/Analysis/CFGPrinter.cpp llvm/trunk/lib/CodeGen/MachineFunction.cpp llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp llvm/trunk/tools/opt/GraphPrinters.cpp Modified: llvm/trunk/include/llvm/Support/DOTGraphTraits.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/DOTGraphTraits.h?rev=74084&r1=74083&r2=74084&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/DOTGraphTraits.h (original) +++ llvm/trunk/include/llvm/Support/DOTGraphTraits.h Wed Jun 24 12:37:09 2009 @@ -51,7 +51,8 @@ /// getNodeLabel - Given a node and a pointer to the top level graph, return /// the label to print in the node. template - static std::string getNodeLabel(const void *Node, const GraphType& Graph) { + static std::string getNodeLabel(const void *Node, + const GraphType& Graph, bool ShortNames) { return ""; } Modified: llvm/trunk/include/llvm/Support/GraphWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/GraphWriter.h?rev=74084&r1=74083&r2=74084&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/GraphWriter.h (original) +++ llvm/trunk/include/llvm/Support/GraphWriter.h Wed Jun 24 12:37:09 2009 @@ -72,6 +72,7 @@ class GraphWriter { std::ostream &O; const GraphType &G; + bool ShortNames; typedef DOTGraphTraits DOTTraits; typedef GraphTraits GTraits; @@ -79,7 +80,8 @@ typedef typename GTraits::nodes_iterator node_iterator; typedef typename GTraits::ChildIteratorType child_iterator; public: - GraphWriter(std::ostream &o, const GraphType &g) : O(o), G(g) {} + GraphWriter(std::ostream &o, const GraphType &g, bool SN) : + O(o), G(g), ShortNames(SN) {} void writeHeader(const std::string &Name) { std::string GraphName = DOTTraits::getGraphName(G); @@ -130,7 +132,7 @@ O << "label=\"{"; if (!DOTTraits::renderGraphFromBottomUp()) { - O << DOT::EscapeString(DOTTraits::getNodeLabel(Node, G)); + O << DOT::EscapeString(DOTTraits::getNodeLabel(Node, G, ShortNames)); // If we should include the address of the node in the label, do so now. if (DOTTraits::hasNodeAddressLabel(Node, G)) @@ -156,7 +158,7 @@ } if (DOTTraits::renderGraphFromBottomUp()) { - O << DOT::EscapeString(DOTTraits::getNodeLabel(Node, G)); + O << DOT::EscapeString(DOTTraits::getNodeLabel(Node, G, ShortNames)); // If we should include the address of the node in the label, do so now. if (DOTTraits::hasNodeAddressLabel(Node, G)) @@ -250,10 +252,11 @@ template std::ostream &WriteGraph(std::ostream &O, const GraphType &G, + bool ShortNames = false, const std::string &Name = "", const std::string &Title = "") { // Start the graph emission process... - GraphWriter W(O, G); + GraphWriter W(O, G, ShortNames); // Output the header for the graph... W.writeHeader(Title); @@ -272,6 +275,7 @@ template sys::Path WriteGraph(const GraphType &G, const std::string& Name, + bool ShortNames = false, const std::string& Title = "") { std::string ErrMsg; sys::Path Filename = sys::Path::GetTemporaryDirectory(&ErrMsg); @@ -290,7 +294,7 @@ std::ofstream O(Filename.c_str()); if (O.good()) { - WriteGraph(O, G, Name, Title); + WriteGraph(O, G, ShortNames, Name, Title); cerr << " done. \n"; O.close(); @@ -308,8 +312,9 @@ template void ViewGraph(const GraphType& G, const std::string& Name, + bool ShortNames = false, const std::string& Title = "") { - sys::Path Filename = WriteGraph(G, Name, Title); + sys::Path Filename = WriteGraph(G, Name, ShortNames, Title); if (Filename.isEmpty()) { return; Modified: llvm/trunk/lib/Analysis/CFGPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CFGPrinter.cpp?rev=74084&r1=74083&r2=74084&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CFGPrinter.cpp (original) +++ llvm/trunk/lib/Analysis/CFGPrinter.cpp Wed Jun 24 12:37:09 2009 @@ -31,12 +31,6 @@ #include using namespace llvm; -/// CFGOnly flag - This is used to control whether or not the CFG graph printer -/// prints out the contents of basic blocks or not. This is acceptable because -/// this code is only really used for debugging purposes. -/// -static bool CFGOnly = false; - namespace llvm { template<> struct DOTGraphTraits : public DefaultDOTGraphTraits { @@ -45,12 +39,13 @@ } static std::string getNodeLabel(const BasicBlock *Node, - const Function *Graph) { - if (CFGOnly && !Node->getName().empty()) + const Function *Graph, + bool ShortNames) { + if (ShortNames && !Node->getName().empty()) return Node->getName() + ":"; std::ostringstream Out; - if (CFGOnly) { + if (ShortNames) { WriteAsOperand(Out, Node, false); return Out.str(); } @@ -117,9 +112,7 @@ CFGOnlyViewer() : FunctionPass(&ID) {} virtual bool runOnFunction(Function &F) { - CFGOnly = true; F.viewCFG(); - CFGOnly = false; return false; } @@ -168,14 +161,20 @@ P1("dot-cfg", "Print CFG of function to 'dot' file", false, true); namespace { - struct VISIBILITY_HIDDEN CFGOnlyPrinter : public CFGPrinter { + struct VISIBILITY_HIDDEN CFGOnlyPrinter : public FunctionPass { static char ID; // Pass identification, replacement for typeid - CFGOnlyPrinter() : CFGPrinter(&ID) {} + CFGOnlyPrinter() : FunctionPass(&ID) {} + explicit CFGOnlyPrinter(void *pid) : FunctionPass(pid) {} virtual bool runOnFunction(Function &F) { - bool OldCFGOnly = CFGOnly; - CFGOnly = true; - CFGPrinter::runOnFunction(F); - CFGOnly = OldCFGOnly; + std::string Filename = "cfg." + F.getName() + ".dot"; + cerr << "Writing '" << Filename << "'..."; + std::ofstream File(Filename.c_str()); + + if (File.good()) + WriteGraph(File, (const Function*)&F, true); + else + cerr << " error opening file for writing!"; + cerr << "\n"; return false; } void print(std::ostream &OS, const Module* = 0) const {} @@ -206,9 +205,7 @@ /// his can make the graph smaller. /// void Function::viewCFGOnly() const { - CFGOnly = true; - viewCFG(); - CFGOnly = false; + ViewGraph(this, "cfg" + getName(), true); } FunctionPass *llvm::createCFGPrinterPass () { Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=74084&r1=74083&r2=74084&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Wed Jun 24 12:37:09 2009 @@ -295,12 +295,6 @@ OS << "\n# End machine code for " << Fn->getName () << "().\n\n"; } -/// CFGOnly flag - This is used to control whether or not the CFG graph printer -/// prints out the contents of basic blocks or not. This is acceptable because -/// this code is only really used for debugging purposes. -/// -static bool CFGOnly = false; - namespace llvm { template<> struct DOTGraphTraits : public DefaultDOTGraphTraits { @@ -309,13 +303,14 @@ } static std::string getNodeLabel(const MachineBasicBlock *Node, - const MachineFunction *Graph) { - if (CFGOnly && Node->getBasicBlock() && + const MachineFunction *Graph, + bool ShortNames) { + if (ShortNames && Node->getBasicBlock() && !Node->getBasicBlock()->getName().empty()) return Node->getBasicBlock()->getName() + ":"; std::ostringstream Out; - if (CFGOnly) { + if (ShortNames) { Out << Node->getNumber() << ':'; return Out.str(); } @@ -348,9 +343,12 @@ void MachineFunction::viewCFGOnly() const { - CFGOnly = true; - viewCFG(); - CFGOnly = false; +#ifndef NDEBUG + ViewGraph(this, "mf" + getFunction()->getName(), true); +#else + cerr << "SelectionDAG::viewGraph is only available in debug builds on " + << "systems with Graphviz or gv!\n"; +#endif // NDEBUG } // The next two methods are used to construct and to retrieve Modified: llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp?rev=74084&r1=74083&r2=74084&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp Wed Jun 24 12:37:09 2009 @@ -59,7 +59,8 @@ static std::string getNodeLabel(const SUnit *Node, - const ScheduleDAG *Graph); + const ScheduleDAG *Graph, + bool ShortNames); static std::string getNodeAttributes(const SUnit *N, const ScheduleDAG *Graph) { return "shape=Mrecord"; @@ -73,7 +74,8 @@ } std::string DOTGraphTraits::getNodeLabel(const SUnit *SU, - const ScheduleDAG *G) { + const ScheduleDAG *G, + bool ShortNames) { return G->getGraphNodeLabel(SU); } @@ -84,11 +86,11 @@ // This code is only for debugging! #ifndef NDEBUG if (BB->getBasicBlock()) - ViewGraph(this, "dag." + MF.getFunction()->getName(), + ViewGraph(this, "dag." + MF.getFunction()->getName(), false, "Scheduling-Units Graph for " + MF.getFunction()->getName() + ':' + BB->getBasicBlock()->getName()); else - ViewGraph(this, "dag." + MF.getFunction()->getName(), + ViewGraph(this, "dag." + MF.getFunction()->getName(), false, "Scheduling-Units Graph for " + MF.getFunction()->getName()); #else cerr << "ScheduleDAG::viewGraph is only available in debug builds on " Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=74084&r1=74083&r2=74084&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Wed Jun 24 12:37:09 2009 @@ -94,7 +94,8 @@ static std::string getNodeLabel(const SDNode *Node, - const SelectionDAG *Graph); + const SelectionDAG *Graph, + bool ShortNames); static std::string getNodeAttributes(const SDNode *N, const SelectionDAG *Graph) { #ifndef NDEBUG @@ -120,7 +121,8 @@ } std::string DOTGraphTraits::getNodeLabel(const SDNode *Node, - const SelectionDAG *G) { + const SelectionDAG *G, + bool ShortNames) { std::string Op = Node->getOperationName(G); if (const ConstantSDNode *CSDN = dyn_cast(Node)) { @@ -262,7 +264,7 @@ void SelectionDAG::viewGraph(const std::string &Title) { // This code is only for debugging! #ifndef NDEBUG - ViewGraph(this, "dag." + getMachineFunction().getFunction()->getName(), + ViewGraph(this, "dag." + getMachineFunction().getFunction()->getName(), false, Title); #else cerr << "SelectionDAG::viewGraph is only available in debug builds on " @@ -393,7 +395,8 @@ for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) FlaggedNodes.push_back(N); while (!FlaggedNodes.empty()) { - O << DOTGraphTraits::getNodeLabel(FlaggedNodes.back(), DAG); + O << DOTGraphTraits::getNodeLabel(FlaggedNodes.back(), + DAG, false); FlaggedNodes.pop_back(); if (!FlaggedNodes.empty()) O << "\n "; Modified: llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp?rev=74084&r1=74083&r2=74084&view=diff ============================================================================== --- llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp (original) +++ llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp Wed Jun 24 12:37:09 2009 @@ -477,7 +477,8 @@ { template - static std::string getNodeLabel(const Node* N, const GraphType&) + static std::string getNodeLabel(const Node* N, const GraphType&, + bool ShortNames) { if (N->ToolPtr) if (N->ToolPtr->IsJoin()) Modified: llvm/trunk/tools/opt/GraphPrinters.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/GraphPrinters.cpp?rev=74084&r1=74083&r2=74084&view=diff ============================================================================== --- llvm/trunk/tools/opt/GraphPrinters.cpp (original) +++ llvm/trunk/tools/opt/GraphPrinters.cpp Wed Jun 24 12:37:09 2009 @@ -49,7 +49,8 @@ return "Call Graph"; } - static std::string getNodeLabel(CallGraphNode *Node, CallGraph *Graph) { + static std::string getNodeLabel(CallGraphNode *Node, CallGraph *Graph, + bool ShortNames) { if (Node->getFunction()) return ((Value*)Node->getFunction())->getName(); else From sabre at nondot.org Wed Jun 24 12:54:54 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 17:54:54 -0000 Subject: [llvm-commits] [llvm] r74087 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp Message-ID: <200906241754.n5OHsuxx027906@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 12:54:48 2009 New Revision: 74087 URL: http://llvm.org/viewvc/llvm-project?rev=74087&view=rev Log: Rearrange some stuff in MachineOperand and add a new TargetFlags field. Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h llvm/trunk/lib/CodeGen/MachineInstr.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=74087&r1=74086&r2=74087&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Wed Jun 24 12:54:48 2009 @@ -47,7 +47,14 @@ private: /// OpKind - Specify what kind of operand this is. This discriminates the /// union. - MachineOperandType OpKind : 8; + unsigned char OpKind; // MachineOperandType + + /// SubReg - Subregister number, only valid for MO_Register. A value of 0 + /// indicates the MO_Register has no subReg. + unsigned char SubReg; + + /// TargetFlags - This is a set of target-specific operand flags. + unsigned char TargetFlags; /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register /// operands. @@ -73,10 +80,6 @@ /// model the GCC inline asm '&' constraint modifier. bool IsEarlyClobber : 1; - /// SubReg - Subregister number, only valid for MO_Register. A value of 0 - /// indicates the MO_Register has no subReg. - unsigned char SubReg; - /// ParentMI - This is the instruction that this operand is embedded into. /// This is valid for all operand types, when the operand is in an instr. MachineInstr *ParentMI; @@ -105,7 +108,9 @@ } OffsetedInfo; } Contents; - explicit MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) {} + explicit MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) { + TargetFlags = 0; + } public: MachineOperand(const MachineOperand &M) { *this = M; @@ -115,7 +120,12 @@ /// getType - Returns the MachineOperandType for this operand. /// - MachineOperandType getType() const { return OpKind; } + MachineOperandType getType() const { return (MachineOperandType)OpKind; } + + unsigned char getTargetFlags() const { return TargetFlags; } + void setTargetFlags(unsigned char F) { TargetFlags = F; } + void addTargetFlag(unsigned char F) { TargetFlags |= F; } + /// getParent - Return the instruction that this operand belongs to. /// @@ -404,6 +414,7 @@ SubReg = MO.SubReg; ParentMI = MO.ParentMI; Contents = MO.Contents; + TargetFlags = MO.TargetFlags; return *this; } Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=74087&r1=74086&r2=74087&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Wed Jun 24 12:54:48 2009 @@ -150,7 +150,9 @@ /// isIdenticalTo - Return true if this operand is identical to the specified /// operand. bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { - if (getType() != Other.getType()) return false; + if (getType() != Other.getType() || + getTargetFlags() != Other.getTargetFlags()) + return false; switch (getType()) { default: assert(0 && "Unrecognized operand type"); @@ -205,70 +207,72 @@ } if (getSubReg() != 0) { - OS << ":" << getSubReg(); + OS << ':' << getSubReg(); } if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) { - OS << "<"; + OS << '<'; bool NeedComma = false; if (isImplicit()) { - if (NeedComma) OS << ","; + if (NeedComma) OS << ','; OS << (isDef() ? "imp-def" : "imp-use"); NeedComma = true; } else if (isDef()) { - if (NeedComma) OS << ","; + if (NeedComma) OS << ','; if (isEarlyClobber()) OS << "earlyclobber,"; OS << "def"; NeedComma = true; } if (isKill() || isDead()) { - if (NeedComma) OS << ","; + if (NeedComma) OS << ','; if (isKill()) OS << "kill"; if (isDead()) OS << "dead"; } - OS << ">"; + OS << '>'; } break; case MachineOperand::MO_Immediate: OS << getImm(); break; case MachineOperand::MO_FPImmediate: - if (getFPImm()->getType() == Type::FloatTy) { + if (getFPImm()->getType() == Type::FloatTy) OS << getFPImm()->getValueAPF().convertToFloat(); - } else { + else OS << getFPImm()->getValueAPF().convertToDouble(); - } break; case MachineOperand::MO_MachineBasicBlock: OS << "mbb<" << ((Value*)getMBB()->getBasicBlock())->getName() - << "," << (void*)getMBB() << ">"; + << "," << (void*)getMBB() << '>'; break; case MachineOperand::MO_FrameIndex: - OS << ""; + OS << "'; break; case MachineOperand::MO_ConstantPoolIndex: OS << ""; + OS << '>'; break; case MachineOperand::MO_JumpTableIndex: - OS << ""; + OS << "'; break; case MachineOperand::MO_GlobalAddress: OS << "getName(); if (getOffset()) OS << "+" << getOffset(); - OS << ">"; + OS << '>'; break; case MachineOperand::MO_ExternalSymbol: OS << ""; + OS << '>'; break; default: assert(0 && "Unrecognized operand type"); } + + if (unsigned TF = getTargetFlags()) + OS << "[TF=" << TF << ']'; } //===----------------------------------------------------------------------===// @@ -1104,13 +1108,13 @@ // If not found, this means an alias of one of the operands is dead. Add a // new implicit operand if required. - if (!Found && AddIfNotFound) { - addOperand(MachineOperand::CreateReg(IncomingReg, - true /*IsDef*/, - true /*IsImp*/, - false /*IsKill*/, - true /*IsDead*/)); - return true; - } - return Found; + if (Found || !AddIfNotFound) + return Found; + + addOperand(MachineOperand::CreateReg(IncomingReg, + true /*IsDef*/, + true /*IsImp*/, + false /*IsKill*/, + true /*IsDead*/)); + return true; } From dalej at apple.com Wed Jun 24 12:58:28 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 24 Jun 2009 17:58:28 -0000 Subject: [llvm-commits] [test-suite] r74088 - /test-suite/trunk/MultiSource/Benchmarks/VersaBench/Makefile Message-ID: <200906241758.n5OHwS5l028076@zion.cs.uiuc.edu> Author: johannes Date: Wed Jun 24 12:58:27 2009 New Revision: 74088 URL: http://llvm.org/viewvc/llvm-project?rev=74088&view=rev Log: Disable a little-endian specific benchmark on big-endian targets. Modified: test-suite/trunk/MultiSource/Benchmarks/VersaBench/Makefile Modified: test-suite/trunk/MultiSource/Benchmarks/VersaBench/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/VersaBench/Makefile?rev=74088&r1=74087&r2=74088&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/VersaBench/Makefile (original) +++ test-suite/trunk/MultiSource/Benchmarks/VersaBench/Makefile Wed Jun 24 12:58:27 2009 @@ -1,6 +1,14 @@ # MultiSource/VersaBench Makefile: Build all subdirectories automatically LEVEL = ../../.. +# Get the $(ENDIAN) setting +include $(LEVEL)/Makefile.config + +# 8b10b is inherently little-endian, don't bother on big-endian. +ifeq ($(ENDIAN),big) +PARALLEL_DIRS = beamformer bmm dbms ecbdes +else PARALLEL_DIRS = 8b10b beamformer bmm dbms ecbdes +endif include $(LEVEL)/Makefile.programs From sabre at nondot.org Wed Jun 24 13:00:11 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 18:00:11 -0000 Subject: [llvm-commits] [llvm] r74089 - in /llvm/trunk/lib/Target/X86/AsmPrinter: X86ATTAsmPrinter.cpp X86ATTAsmPrinter.h Message-ID: <200906241800.n5OI0DR8028231@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 13:00:11 2009 New Revision: 74089 URL: http://llvm.org/viewvc/llvm-project?rev=74089&view=rev Log: remove dead argument Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74089&r1=74088&r2=74089&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 13:00:11 2009 @@ -1089,10 +1089,9 @@ /// printHiddenGVStub - Print stub for a hidden global value. /// -void X86ATTAsmPrinter::printHiddenGVStub(const char *GV, const char *Prefix) { +void X86ATTAsmPrinter::printHiddenGVStub(const char *GV) { EmitAlignment(2); - printSuffixedName(GV, "$non_lazy_ptr", Prefix); - if (Prefix) O << Prefix; + printSuffixedName(GV, "$non_lazy_ptr"); O << ":\n" << TAI->getData32bitsDirective() << GV << '\n'; } Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=74089&r1=74088&r2=74089&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Wed Jun 24 13:00:11 2009 @@ -189,7 +189,7 @@ void printModuleLevelGV(const GlobalVariable* GVar); void printGVStub(const char *GV, const char *Prefix = NULL); - void printHiddenGVStub(const char *GV, const char *Prefix = NULL); + void printHiddenGVStub(const char *GV); bool runOnMachineFunction(MachineFunction &F); From sabre at nondot.org Wed Jun 24 13:17:12 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 18:17:12 -0000 Subject: [llvm-commits] [llvm] r74090 - /llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Message-ID: <200906241817.n5OIHFpG028818@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 13:17:00 2009 New Revision: 74090 URL: http://llvm.org/viewvc/llvm-project?rev=74090&view=rev Log: simplify personality function stub printing to use the mangler and decorateName like other stuff instead of special casing _. Also, stick it into GVStubs and let the normal stub printer print the stub instead of doing it manually. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74090&r1=74089&r2=74090&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 13:17:00 2009 @@ -1134,9 +1134,8 @@ i != e; ++i) O << "\t.ascii \" -export:" << i->getKeyData() << ",data\"\n"; - if (!DLLExportedFns.empty()) { + if (!DLLExportedFns.empty()) SwitchToDataSection(".section .drectve"); - } for (StringSet<>::iterator i = DLLExportedFns.begin(), e = DLLExportedFns.end(); @@ -1162,20 +1161,21 @@ // Print global value stubs. bool InStubSection = false; + // Add the (possibly multiple) personalities to the set of global value + // stubs. Only referenced functions get into the Personalities list. if (TAI->doesSupportExceptionHandling() && MMI && !Subtarget->is64Bit()) { - // Add the (possibly multiple) personalities to the set of global values. - // Only referenced functions get into the Personalities list. - const std::vector& Personalities = MMI->getPersonalities(); - for (std::vector::const_iterator I = Personalities.begin(), - E = Personalities.end(); I != E; ++I) { - if (!*I) + const std::vector &Personalities = MMI->getPersonalities(); + for (unsigned i = 0, e = Personalities.size(); i != e; ++i) { + if (Personalities[i] == 0) continue; if (!InStubSection) { SwitchToDataSection( "\t.section __IMPORT,__pointers,non_lazy_symbol_pointers"); InStubSection = true; } - printGVStub((*I)->getNameStart(), "_"); + std::string Name = Mang->getValueName(Personalities[i]); + decorateName(Name, Personalities[i]); + GVStubs.insert(Name); } } From sabre at nondot.org Wed Jun 24 13:17:57 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 18:17:57 -0000 Subject: [llvm-commits] [llvm] r74091 - in /llvm/trunk/lib/Target/X86/AsmPrinter: X86ATTAsmPrinter.cpp X86ATTAsmPrinter.h Message-ID: <200906241817.n5OIHvUr028853@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 13:17:56 2009 New Revision: 74091 URL: http://llvm.org/viewvc/llvm-project?rev=74091&view=rev Log: remove now-dead argument. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74091&r1=74090&r2=74091&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 13:17:56 2009 @@ -1080,11 +1080,9 @@ /// printGVStub - Print stub for a global value. /// -void X86ATTAsmPrinter::printGVStub(const char *GV, const char *Prefix) { - printSuffixedName(GV, "$non_lazy_ptr", Prefix); - O << ":\n\t.indirect_symbol "; - if (Prefix) O << Prefix; - O << GV << "\n\t.long\t0\n"; +void X86ATTAsmPrinter::printGVStub(const char *GV) { + printSuffixedName(GV, "$non_lazy_ptr"); + O << ":\n\t.indirect_symbol " << GV << "\n\t.long\t0\n"; } /// printHiddenGVStub - Print stub for a hidden global value. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=74091&r1=74090&r2=74091&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Wed Jun 24 13:17:56 2009 @@ -188,7 +188,7 @@ void printPICLabel(const MachineInstr *MI, unsigned Op); void printModuleLevelGV(const GlobalVariable* GVar); - void printGVStub(const char *GV, const char *Prefix = NULL); + void printGVStub(const char *GV); void printHiddenGVStub(const char *GV); bool runOnMachineFunction(MachineFunction &F); From sabre at nondot.org Wed Jun 24 13:19:01 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 18:19:01 -0000 Subject: [llvm-commits] [llvm] r74092 - /llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Message-ID: <200906241819.n5OIJ10c028905@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 13:19:01 2009 New Revision: 74092 URL: http://llvm.org/viewvc/llvm-project?rev=74092&view=rev Log: remove dead code now that personality functions don't print stubs directly. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74092&r1=74091&r2=74092&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 13:19:01 2009 @@ -1157,8 +1157,6 @@ O << '\n'; - // Print global value stubs. - bool InStubSection = false; // Add the (possibly multiple) personalities to the set of global value // stubs. Only referenced functions get into the Personalities list. if (TAI->doesSupportExceptionHandling() && MMI && !Subtarget->is64Bit()) { @@ -1166,11 +1164,6 @@ for (unsigned i = 0, e = Personalities.size(); i != e; ++i) { if (Personalities[i] == 0) continue; - if (!InStubSection) { - SwitchToDataSection( - "\t.section __IMPORT,__pointers,non_lazy_symbol_pointers"); - InStubSection = true; - } std::string Name = Mang->getValueName(Personalities[i]); decorateName(Name, Personalities[i]); GVStubs.insert(Name); @@ -1178,7 +1171,7 @@ } // Output stubs for external and common global variables. - if (!InStubSection && !GVStubs.empty()) + if (!GVStubs.empty()) SwitchToDataSection( "\t.section __IMPORT,__pointers,non_lazy_symbol_pointers"); for (StringSet<>::iterator i = GVStubs.begin(), e = GVStubs.end(); From sabre at nondot.org Wed Jun 24 13:24:16 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 18:24:16 -0000 Subject: [llvm-commits] [llvm] r74093 - in /llvm/trunk/lib/Target/X86/AsmPrinter: X86ATTAsmPrinter.cpp X86ATTAsmPrinter.h Message-ID: <200906241824.n5OIOI9i029100@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 13:24:09 2009 New Revision: 74093 URL: http://llvm.org/viewvc/llvm-project?rev=74093&view=rev Log: inline print*Stub and rearrange function stub printing to more closely match gv and hiddengv stub printing. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74093&r1=74092&r2=74093&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 13:24:09 2009 @@ -1078,22 +1078,6 @@ EmitGlobalConstant(C); } -/// printGVStub - Print stub for a global value. -/// -void X86ATTAsmPrinter::printGVStub(const char *GV) { - printSuffixedName(GV, "$non_lazy_ptr"); - O << ":\n\t.indirect_symbol " << GV << "\n\t.long\t0\n"; -} - -/// printHiddenGVStub - Print stub for a hidden global value. -/// -void X86ATTAsmPrinter::printHiddenGVStub(const char *GV) { - EmitAlignment(2); - printSuffixedName(GV, "$non_lazy_ptr"); - O << ":\n" << TAI->getData32bitsDirective() << GV << '\n'; -} - - bool X86ATTAsmPrinter::doFinalization(Module &M) { // Print out module-level global variables here. for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); @@ -1142,21 +1126,7 @@ if (Subtarget->isTargetDarwin()) { SwitchToDataSection(""); - - // Output stubs for dynamically-linked functions - for (StringSet<>::iterator i = FnStubs.begin(), e = FnStubs.end(); - i != e; ++i) { - SwitchToDataSection("\t.section __IMPORT,__jump_table,symbol_stubs," - "self_modifying_code+pure_instructions,5", 0); - const char *p = i->getKeyData(); - printSuffixedName(p, "$stub"); - O << ":\n" - "\t.indirect_symbol " << p << "\n" - "\thlt ; hlt ; hlt ; hlt ; hlt\n"; - } - - O << '\n'; - + // Add the (possibly multiple) personalities to the set of global value // stubs. Only referenced functions get into the Personalities list. if (TAI->doesSupportExceptionHandling() && MMI && !Subtarget->is64Bit()) { @@ -1170,19 +1140,42 @@ } } + // Output stubs for dynamically-linked functions + if (!FnStubs.empty()) { + for (StringSet<>::iterator I = FnStubs.begin(), E = FnStubs.end(); + I != E; ++I) { + SwitchToDataSection("\t.section __IMPORT,__jump_table,symbol_stubs," + "self_modifying_code+pure_instructions,5", 0); + const char *Name = I->getKeyData(); + printSuffixedName(Name, "$stub"); + O << ":\n" + "\t.indirect_symbol " << Name << "\n" + "\thlt ; hlt ; hlt ; hlt ; hlt\n"; + } + O << '\n'; + } + // Output stubs for external and common global variables. - if (!GVStubs.empty()) + if (!GVStubs.empty()) { SwitchToDataSection( "\t.section __IMPORT,__pointers,non_lazy_symbol_pointers"); - for (StringSet<>::iterator i = GVStubs.begin(), e = GVStubs.end(); - i != e; ++i) - printGVStub(i->getKeyData()); + for (StringSet<>::iterator I = GVStubs.begin(), E = GVStubs.end(); + I != E; ++I) { + const char *Name = I->getKeyData(); + printSuffixedName(Name, "$non_lazy_ptr"); + O << ":\n\t.indirect_symbol " << Name << "\n\t.long\t0\n"; + } + } if (!HiddenGVStubs.empty()) { SwitchToSection(TAI->getDataSection()); - for (StringSet<>::iterator i = HiddenGVStubs.begin(), e = HiddenGVStubs.end(); - i != e; ++i) - printHiddenGVStub(i->getKeyData()); + for (StringSet<>::iterator I = HiddenGVStubs.begin(), + E = HiddenGVStubs.end(); I != E; ++I) { + EmitAlignment(2); + const char *Name = I->getKeyData(); + printSuffixedName(Name, "$non_lazy_ptr"); + O << ":\n" << TAI->getData32bitsDirective() << Name << '\n'; + } } // Funny Darwin hack: This flag tells the linker that no global symbols Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=74093&r1=74092&r2=74093&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Wed Jun 24 13:24:09 2009 @@ -188,9 +188,6 @@ void printPICLabel(const MachineInstr *MI, unsigned Op); void printModuleLevelGV(const GlobalVariable* GVar); - void printGVStub(const char *GV); - void printHiddenGVStub(const char *GV); - bool runOnMachineFunction(MachineFunction &F); void emitFunctionHeader(const MachineFunction &MF); From sabre at nondot.org Wed Jun 24 13:24:43 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 18:24:43 -0000 Subject: [llvm-commits] [llvm] r74094 - /llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Message-ID: <200906241824.n5OIOhjS029125@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 13:24:42 2009 New Revision: 74094 URL: http://llvm.org/viewvc/llvm-project?rev=74094&view=rev Log: only emit one .align for all the hidden gv stubs instead of one for each. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74094&r1=74093&r2=74094&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 13:24:42 2009 @@ -1169,9 +1169,9 @@ if (!HiddenGVStubs.empty()) { SwitchToSection(TAI->getDataSection()); + EmitAlignment(2); for (StringSet<>::iterator I = HiddenGVStubs.begin(), E = HiddenGVStubs.end(); I != E; ++I) { - EmitAlignment(2); const char *Name = I->getKeyData(); printSuffixedName(Name, "$non_lazy_ptr"); O << ":\n" << TAI->getData32bitsDirective() << Name << '\n'; From sabre at nondot.org Wed Jun 24 13:52:02 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 18:52:02 -0000 Subject: [llvm-commits] [llvm] r74096 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp Message-ID: <200906241852.n5OIq4wV030036@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 13:52:01 2009 New Revision: 74096 URL: http://llvm.org/viewvc/llvm-project?rev=74096&view=rev Log: eliminate the ExtWeakSymbols set from AsmPrinter. This eliminates a bunch of code from all the targets, and eliminates nondeterministic ordering of directives being emitted in the output. Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=74096&r1=74095&r2=74096&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Wed Jun 24 13:52:01 2009 @@ -63,9 +63,6 @@ /// that ought be fixed soon. DwarfWriter *DW; - // Necessary for external weak linkage support - std::set ExtWeakSymbols; - /// OptLevel - Generating code at a specific optimization level. CodeGenOpt::Level OptLevel; public: Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=74096&r1=74095&r2=74096&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Jun 24 13:52:01 2009 @@ -192,13 +192,26 @@ } bool AsmPrinter::doFinalization(Module &M) { + // If the target wants to know about weak references, print them all. if (TAI->getWeakRefDirective()) { - if (!ExtWeakSymbols.empty()) - SwitchToDataSection(""); - - for (std::set::iterator i = ExtWeakSymbols.begin(), - e = ExtWeakSymbols.end(); i != e; ++i) - O << TAI->getWeakRefDirective() << Mang->getValueName(*i) << '\n'; + // FIXME: This is not lazy, it would be nice to only print weak references + // to stuff that is actually used. Note that doing so would require targets + // to notice uses in operands (due to constant exprs etc). This should + // happen with the MC stuff eventually. + SwitchToDataSection(""); + + // Print out module-level global variables here. + for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); + I != E; ++I) { + if (I->hasExternalWeakLinkage()) + O << TAI->getWeakRefDirective() << Mang->getValueName(I) << '\n'; + } + + for (Module::const_iterator I = M.begin(), E = M.end(); + I != E; ++I) { + if (I->hasExternalWeakLinkage()) + O << TAI->getWeakRefDirective() << Mang->getValueName(I) << '\n'; + } } if (TAI->getSetDirective()) { @@ -207,7 +220,7 @@ O << '\n'; for (Module::const_alias_iterator I = M.alias_begin(), E = M.alias_end(); - I!=E; ++I) { + I != E; ++I) { std::string Name = Mang->getValueName(I); std::string Target; @@ -235,7 +248,7 @@ // If we don't have any trampolines, then we don't require stack memory // to be executable. Some targets have a directive to declare this. - Function* InitTrampolineIntrinsic = M.getFunction("llvm.init.trampoline"); + Function *InitTrampolineIntrinsic = M.getFunction("llvm.init.trampoline"); if (!InitTrampolineIntrinsic || InitTrampolineIntrinsic->use_empty()) if (TAI->getNonexecutableStackDirective()) O << TAI->getNonexecutableStackDirective() << '\n'; Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=74096&r1=74095&r2=74096&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Wed Jun 24 13:52:01 2009 @@ -169,11 +169,6 @@ O << ")"; } O << "\n"; - - // If the constant pool value is a extern weak symbol, remember to emit - // the weak reference. - if (GV && GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); } void getAnalysisUsage(AnalysisUsage &AU) const { @@ -331,8 +326,6 @@ if (isCallOp && Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_) O << "(PLT)"; - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); break; } case MachineOperand::MO_ExternalSymbol: { @@ -749,10 +742,6 @@ EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal); } else { EmitGlobalConstant(MCPE.Val.ConstVal); - // remember to emit the weak reference - if (const GlobalValue *GV = dyn_cast(MCPE.Val.ConstVal)) - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); } } } @@ -1046,12 +1035,6 @@ if (TAI->hasDotTypeDotSizeDirective()) O << "\t.size " << name << ", " << Size << "\n"; - // If the initializer is a extern weak symbol, remember to emit the weak - // reference! - if (const GlobalValue *GV = dyn_cast(C)) - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); - EmitGlobalConstant(C); O << '\n'; } Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=74096&r1=74095&r2=74096&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Wed Jun 24 13:52:01 2009 @@ -121,8 +121,6 @@ case MachineOperand::MO_GlobalAddress: { GlobalValue *GV = MO.getGlobal(); O << Mang->getValueName(GV); - if (GV->isDeclaration() && GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); return; } @@ -265,12 +263,6 @@ O << name << ":\n"; - // If the initializer is a extern weak symbol, remember to emit the weak - // reference! - if (const GlobalValue *GV = dyn_cast(C)) - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); - EmitGlobalConstant(C); O << '\n'; } Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=74096&r1=74095&r2=74096&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Wed Jun 24 13:52:01 2009 @@ -361,9 +361,6 @@ } } O << Name; - - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); return; } @@ -584,12 +581,6 @@ PrintUnmangledNameSafely(GVar, O); O << "'\n"; - // If the initializer is a extern weak symbol, remember to emit the weak - // reference! - if (const GlobalValue *GV = dyn_cast(C)) - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); - EmitGlobalConstant(C); O << '\n'; } Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=74096&r1=74095&r2=74096&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Wed Jun 24 13:52:01 2009 @@ -194,8 +194,6 @@ std::string Name = Mang->getValueName(GV); FnStubs.insert(Name); printSuffixedName(Name, "$stub"); - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); return; } } @@ -403,17 +401,12 @@ GVStubs.insert(Name); printSuffixedName(Name, "$non_lazy_ptr"); } - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); return; } } O << Name; printOffset(MO.getOffset()); - - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); return; } @@ -743,12 +736,6 @@ } O << '\n'; - // If the initializer is a extern weak symbol, remember to emit the weak - // reference! - if (const GlobalValue *GV = dyn_cast(C)) - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); - EmitGlobalConstant(C); O << '\n'; } @@ -987,12 +974,6 @@ } O << '\n'; - // If the initializer is a extern weak symbol, remember to emit the weak - // reference! - if (const GlobalValue *GV = dyn_cast(C)) - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); - EmitGlobalConstant(C); O << '\n'; } Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74096&r1=74095&r2=74096&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 13:52:01 2009 @@ -372,9 +372,6 @@ FnStubs.insert(Name); } - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); - printOffset(MO.getOffset()); if (needCloseParen) @@ -549,9 +546,6 @@ O << Name; } - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); - printOffset(MO.getOffset()); if (needCloseParen) @@ -1086,44 +1080,8 @@ if (I->hasDLLExportLinkage()) DLLExportedGVs.insert(Mang->makeNameProper(I->getName(),"")); - - // If the global is a extern weak symbol, remember to emit the weak - // reference! - // FIXME: This is rather hacky, since we'll emit references to ALL weak - // stuff, not used. But currently it's the only way to deal with extern weak - // initializers hidden deep inside constant expressions. - if (I->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(I); } - for (Module::const_iterator I = M.begin(), E = M.end(); - I != E; ++I) { - // If the global is a extern weak symbol, remember to emit the weak - // reference! - // FIXME: This is rather hacky, since we'll emit references to ALL weak - // stuff, not used. But currently it's the only way to deal with extern weak - // initializers hidden deep inside constant expressions. - if (I->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(I); - } - - // Output linker support code for dllexported globals - if (!DLLExportedGVs.empty()) - SwitchToDataSection(".section .drectve"); - - for (StringSet<>::iterator i = DLLExportedGVs.begin(), - e = DLLExportedGVs.end(); - i != e; ++i) - O << "\t.ascii \" -export:" << i->getKeyData() << ",data\"\n"; - - if (!DLLExportedFns.empty()) - SwitchToDataSection(".section .drectve"); - - for (StringSet<>::iterator i = DLLExportedFns.begin(), - e = DLLExportedFns.end(); - i != e; ++i) - O << "\t.ascii \" -export:" << i->getKeyData() << "\"\n"; - if (Subtarget->isTargetDarwin()) { SwitchToDataSection(""); @@ -1195,10 +1153,32 @@ } } + + // Output linker support code for dllexported globals on windows. + if (!DLLExportedGVs.empty()) { + SwitchToDataSection(".section .drectve"); + + for (StringSet<>::iterator i = DLLExportedGVs.begin(), + e = DLLExportedGVs.end(); i != e; ++i) + O << "\t.ascii \" -export:" << i->getKeyData() << ",data\"\n"; + } + + if (!DLLExportedFns.empty()) { + SwitchToDataSection(".section .drectve"); + + for (StringSet<>::iterator i = DLLExportedFns.begin(), + e = DLLExportedFns.end(); + i != e; ++i) + O << "\t.ascii \" -export:" << i->getKeyData() << "\"\n"; + } + // Emit final debug information. + // FIXME: Sink into DoFinalization. if (TAI->doesSupportDebugInformation() || TAI->doesSupportExceptionHandling()) DW->EndModule(); - + + // Do common shutdown. + bool Changed = AsmPrinter::doFinalization(M); if (NewAsmPrinter) { Streamer->Finish(); @@ -1209,7 +1189,7 @@ Context = 0; } - return AsmPrinter::doFinalization(M); + return Changed; } // Include the auto-generated portion of the assembly writer. Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=74096&r1=74095&r2=74096&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Wed Jun 24 13:52:01 2009 @@ -244,9 +244,6 @@ // Mark the end of the global O << "\t.cc_bottom " << name << ".data\n"; - } else { - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); } } @@ -375,12 +372,7 @@ printBasicBlockLabel(MO.getMBB()); break; case MachineOperand::MO_GlobalAddress: - { - const GlobalValue *GV = MO.getGlobal(); - O << Mang->getValueName(GV); - if (GV->hasExternalWeakLinkage()) - ExtWeakSymbols.insert(GV); - } + O << Mang->getValueName(MO.getGlobal()); break; case MachineOperand::MO_ExternalSymbol: O << MO.getSymbolName(); @@ -430,25 +422,8 @@ bool Result = AsmPrinter::doInitialization(M); DW = getAnalysisIfAvailable(); - if (!FileDirective.empty()) { + if (!FileDirective.empty()) emitFileDirective(FileDirective); - } - - // Print out type strings for external functions here - for (Module::const_iterator I = M.begin(), E = M.end(); - I != E; ++I) { - if (I->isDeclaration() && !I->isIntrinsic()) { - switch (I->getLinkage()) { - default: - assert(0 && "Unexpected linkage"); - case Function::ExternalWeakLinkage: - ExtWeakSymbols.insert(I); - // fallthrough - case Function::ExternalLinkage: - break; - } - } - } return Result; } From sabre at nondot.org Wed Jun 24 13:54:41 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 18:54:41 -0000 Subject: [llvm-commits] [llvm] r74097 - in /llvm/trunk/lib: CodeGen/AsmPrinter/AsmPrinter.cpp Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Target/XCore/XCoreAsmPrinter.cpp Message-ID: <200906241854.n5OIsjqa030136@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 13:54:37 2009 New Revision: 74097 URL: http://llvm.org/viewvc/llvm-project?rev=74097&view=rev Log: sink dwarf finalization out of each target into AsmPrinter::doFinalization Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=74097&r1=74096&r2=74097&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Jun 24 13:54:37 2009 @@ -192,6 +192,10 @@ } bool AsmPrinter::doFinalization(Module &M) { + // Emit final debug information. + if (TAI->doesSupportDebugInformation() || TAI->doesSupportExceptionHandling()) + DW->EndModule(); + // If the target wants to know about weak references, print them all. if (TAI->getWeakRefDirective()) { // FIXME: This is not lazy, it would be nice to only print weak references Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=74097&r1=74096&r2=74097&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Wed Jun 24 13:54:37 2009 @@ -1118,18 +1118,12 @@ } - // Emit initial debug information. - DW->EndModule(); - // Funny Darwin hack: This flag tells the linker that no global symbols // contain code that falls through to other global symbols (e.g. the obvious // implementation of multiple entry points). If this doesn't occur, the // linker can safely perform dead code stripping. Since LLVM never // generates code that does this, it is always safe to set. O << "\t.subsections_via_symbols\n"; - } else { - // Emit final debug information for ELF. - DW->EndModule(); } return AsmPrinter::doFinalization(M); Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=74097&r1=74096&r2=74097&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Wed Jun 24 13:54:37 2009 @@ -591,9 +591,6 @@ I != E; ++I) printModuleLevelGV(I); - // Emit initial debug information. - DW->EndModule(); - return AsmPrinter::doFinalization(M); } Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=74097&r1=74096&r2=74097&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Wed Jun 24 13:54:37 2009 @@ -746,11 +746,6 @@ I != E; ++I) printModuleLevelGV(I); - // TODO - - // Emit initial debug information. - DW->EndModule(); - return AsmPrinter::doFinalization(M); } @@ -1120,10 +1115,6 @@ } } - - // Emit initial debug information. - DW->EndModule(); - // Funny Darwin hack: This flag tells the linker that no global symbols // contain code that falls through to other global symbols (e.g. the obvious // implementation of multiple entry points). If this doesn't occur, the Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74097&r1=74096&r2=74097&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 13:54:37 2009 @@ -1172,11 +1172,6 @@ O << "\t.ascii \" -export:" << i->getKeyData() << "\"\n"; } - // Emit final debug information. - // FIXME: Sink into DoFinalization. - if (TAI->doesSupportDebugInformation() || TAI->doesSupportExceptionHandling()) - DW->EndModule(); - // Do common shutdown. bool Changed = AsmPrinter::doFinalization(M); Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=74097&r1=74096&r2=74097&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Wed Jun 24 13:54:37 2009 @@ -436,8 +436,5 @@ emitGlobal(I); } - // Emit final debug information. - DW->EndModule(); - return AsmPrinter::doFinalization(M); } From sabre at nondot.org Wed Jun 24 14:10:01 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 19:10:01 -0000 Subject: [llvm-commits] [llvm] r74101 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Message-ID: <200906241910.n5OJA42b030688@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 14:09:55 2009 New Revision: 74101 URL: http://llvm.org/viewvc/llvm-project?rev=74101&view=rev Log: sink management of DwarfWriter & MachineModuleInfo into the AsmPrinter base class. Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=74101&r1=74100&r2=74101&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Wed Jun 24 14:09:55 2009 @@ -33,6 +33,7 @@ class GlobalVariable; class MachineConstantPoolEntry; class MachineConstantPoolValue; + class MachineModuleInfo; class DwarfWriter; class Mangler; class Section; @@ -58,9 +59,10 @@ gcp_map_type GCMetadataPrinters; protected: - /// DW -This is needed because printDeclare() has to insert - /// DbgVariable entries into the dwarf table. This is a short term hack - /// that ought be fixed soon. + /// MMI - If available, this is a pointer to the current MachineModuleInfo. + MachineModuleInfo *MMI; + + /// DW - If available, this is a pointer to the current dwarf writer. DwarfWriter *DW; /// OptLevel - Generating code at a specific optimization level. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=74101&r1=74100&r2=74101&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Jun 24 14:09:55 2009 @@ -45,8 +45,8 @@ const TargetAsmInfo *T, CodeGenOpt::Level OL, bool VDef) : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o), TM(tm), TAI(T), TRI(tm.getRegisterInfo()), - IsInTextSection(false) -{ + IsInTextSection(false) { + DW = 0; MMI = 0; switch (AsmVerbose) { case cl::BOU_UNSET: VerboseAsm = VDef; break; case cl::BOU_TRUE: VerboseAsm = true; break; @@ -177,15 +177,14 @@ SwitchToDataSection(""); // Reset back to no section. - if (TAI->doesSupportDebugInformation() - || TAI->doesSupportExceptionHandling()) { - MachineModuleInfo *MMI = getAnalysisIfAvailable(); - if (MMI) { + if (TAI->doesSupportDebugInformation() || + TAI->doesSupportExceptionHandling()) { + MMI = getAnalysisIfAvailable(); + if (MMI) MMI->AnalyzeModule(M); - DW = getAnalysisIfAvailable(); - if (DW) - DW->BeginModule(&M, MMI, O, this, TAI); - } + DW = getAnalysisIfAvailable(); + if (DW) + DW->BeginModule(&M, MMI, O, this, TAI); } return false; @@ -258,6 +257,7 @@ O << TAI->getNonexecutableStackDirective() << '\n'; delete Mang; Mang = 0; + DW = 0; MMI = 0; return false; } Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=74101&r1=74100&r2=74101&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Wed Jun 24 14:09:55 2009 @@ -293,20 +293,17 @@ /// PPCLinuxAsmPrinter - PowerPC assembly printer, customized for Linux class VISIBILITY_HIDDEN PPCLinuxAsmPrinter : public PPCAsmPrinter { - DwarfWriter *DW; - MachineModuleInfo *MMI; public: explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM, const TargetAsmInfo *T, CodeGenOpt::Level OL, bool V) - : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {} + : PPCAsmPrinter(O, TM, T, OL, V){} virtual const char *getPassName() const { return "Linux PPC Assembly Printer"; } bool runOnMachineFunction(MachineFunction &F); - bool doInitialization(Module &M); bool doFinalization(Module &M); void getAnalysisUsage(AnalysisUsage &AU) const { @@ -322,14 +319,12 @@ /// PPCDarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac /// OS X class VISIBILITY_HIDDEN PPCDarwinAsmPrinter : public PPCAsmPrinter { - DwarfWriter *DW; - MachineModuleInfo *MMI; raw_ostream &OS; public: explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM, const TargetAsmInfo *T, CodeGenOpt::Level OL, bool V) - : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {} + : PPCAsmPrinter(O, TM, T, OL, V), OS(O) {} virtual const char *getPassName() const { return "Darwin PPC Assembly Printer"; @@ -637,15 +632,6 @@ return false; } -bool PPCLinuxAsmPrinter::doInitialization(Module &M) { - bool Result = AsmPrinter::doInitialization(M); - DW = getAnalysisIfAvailable(); - MMI = getAnalysisIfAvailable(); - assert(MMI); - SwitchToSection(TAI->getTextSection()); - return Result; -} - /// PrintUnmangledNameSafely - Print out the printable characters in the name. /// Don't print things like \\n or \\0. static void PrintUnmangledNameSafely(const Value *V, raw_ostream &OS) { @@ -848,8 +834,6 @@ O << "\t.machine " << CPUDirectives[Directive] << '\n'; bool Result = AsmPrinter::doInitialization(M); - DW = getAnalysisIfAvailable(); - MMI = getAnalysisIfAvailable(); assert(MMI); // Prime text sections so they are adjacent. This reduces the likelihood a @@ -1076,8 +1060,7 @@ if (TAI->doesSupportExceptionHandling() && MMI) { // Add the (possibly multiple) personalities to the set of global values. // Only referenced functions get into the Personalities list. - const std::vector& Personalities = MMI->getPersonalities(); - + const std::vector &Personalities = MMI->getPersonalities(); for (std::vector::const_iterator I = Personalities.begin(), E = Personalities.end(); I != E; ++I) if (*I) GVStubs.insert("_" + (*I)->getName()); Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74101&r1=74100&r2=74101&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 14:09:55 2009 @@ -927,9 +927,6 @@ /// doInitialization bool X86ATTAsmPrinter::doInitialization(Module &M) { - if (TAI->doesSupportDebugInformation() || TAI->doesSupportExceptionHandling()) - MMI = getAnalysisIfAvailable(); - if (NewAsmPrinter) { Context = new MCContext(); // FIXME: Send this to "O" instead of outs(). For now, we force it to Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=74101&r1=74100&r2=74101&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Wed Jun 24 14:09:55 2009 @@ -32,7 +32,6 @@ class MCStreamer; class VISIBILITY_HIDDEN X86ATTAsmPrinter : public AsmPrinter { - MachineModuleInfo *MMI; const X86Subtarget *Subtarget; MCContext *Context; @@ -41,7 +40,7 @@ explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM, const TargetAsmInfo *T, CodeGenOpt::Level OL, bool V) - : AsmPrinter(O, TM, T, OL, V), MMI(0) { + : AsmPrinter(O, TM, T, OL, V) { Subtarget = &TM.getSubtarget(); Context = 0; Streamer = 0; From sabre at nondot.org Wed Jun 24 14:19:17 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 19:19:17 -0000 Subject: [llvm-commits] [llvm] r74105 - in /llvm/trunk/lib/Target/X86/AsmPrinter: X86ATTAsmPrinter.cpp X86ATTAsmPrinter.h Message-ID: <200906241919.n5OJJH39031004@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 14:19:16 2009 New Revision: 74105 URL: http://llvm.org/viewvc/llvm-project?rev=74105&view=rev Log: reimplement getPICLabelString as PrintPICBaseSymbol to eliminate std::string heap thrashing. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74105&r1=74104&r2=74105&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 14:19:16 2009 @@ -43,20 +43,17 @@ static cl::opt NewAsmPrinter("experimental-asm-printer", cl::Hidden); -static std::string getPICLabelString(unsigned FnNum, - const TargetAsmInfo *TAI, - const X86Subtarget* Subtarget) { - std::string label; + +void X86ATTAsmPrinter::PrintPICBaseSymbol() const { if (Subtarget->isTargetDarwin()) - label = "\"L" + utostr_32(FnNum) + "$pb\""; + O << "\"L" << getFunctionNumber() << "$pb\""; else if (Subtarget->isTargetELF()) - label = ".Lllvm$" + utostr_32(FnNum) + "." "$piclabel"; + O << ".Lllvm$" << getFunctionNumber() << "." "$piclabel"; else assert(0 && "Don't know how to print PIC label!\n"); - - return label; } + static X86MachineFunctionInfo calculateFunctionInfo(const Function *F, const TargetData *TD) { X86MachineFunctionInfo Info; @@ -403,7 +400,7 @@ if (shouldPrintPLT(TM, Subtarget)) { std::string GOTName(TAI->getGlobalPrefix()); GOTName+="_GLOBAL_OFFSET_TABLE_"; - if (Name == GOTName) + if (Name == GOTName) { // HACK! Emit extra offset to PC during printing GOT offset to // compensate for the size of popl instruction. The resulting code // should look like: @@ -411,8 +408,10 @@ // piclabel: // popl %some_register // addl $_GLOBAL_ADDRESS_TABLE_ + [.-piclabel], %some_register - O << " + [.-" - << getPICLabelString(getFunctionNumber(), TAI, Subtarget) << ']'; + O << " + [.-"; + PrintPICBaseSymbol(); + O << ']'; + } O << "@PLT"; } @@ -538,8 +537,10 @@ O << Name; } - if (TM.getRelocationModel() == Reloc::PIC_) - O << '-' << getPICLabelString(getFunctionNumber(), TAI, Subtarget); + if (TM.getRelocationModel() == Reloc::PIC_) { + O << '-'; + PrintPICBaseSymbol(); + } } else { if (GV->hasDLLImportLinkage()) O << "__imp_"; @@ -626,7 +627,7 @@ if (shouldPrintPLT(TM, Subtarget)) { std::string GOTName(TAI->getGlobalPrefix()); GOTName+="_GLOBAL_OFFSET_TABLE_"; - if (Name == GOTName) + if (Name == GOTName) { // HACK! Emit extra offset to PC during printing GOT offset to // compensate for the size of popl instruction. The resulting code // should look like: @@ -634,8 +635,10 @@ // piclabel: // popl %some_register // addl $_GLOBAL_ADDRESS_TABLE_ + [.-piclabel], %some_register - O << " + [.-" - << getPICLabelString(getFunctionNumber(), TAI, Subtarget) << ']'; + O << " + [.-"; + PrintPICBaseSymbol(); + O << ']'; + } } if (needCloseParen) @@ -737,13 +740,19 @@ if (Subtarget->isPICStyleRIPRel()) O << '-' << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_' << uid << '\n'; - else - O << '-' << getPICLabelString(getFunctionNumber(), TAI, Subtarget) << '\n'; + else { + O << '-'; + PrintPICBaseSymbol(); + O << '\n'; + } } + void X86ATTAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) { - std::string label = getPICLabelString(getFunctionNumber(), TAI, Subtarget); - O << label << '\n' << label << ':'; + PrintPICBaseSymbol(); + O << '\n'; + PrintPICBaseSymbol(); + O << ':'; } Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=74105&r1=74104&r2=74105&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Wed Jun 24 14:19:16 2009 @@ -187,6 +187,8 @@ void printPICLabel(const MachineInstr *MI, unsigned Op); void printModuleLevelGV(const GlobalVariable* GVar); + void PrintPICBaseSymbol() const; + bool runOnMachineFunction(MachineFunction &F); void emitFunctionHeader(const MachineFunction &MF); From andreas.bolka at gmx.net Wed Jun 24 14:24:10 2009 From: andreas.bolka at gmx.net (Andreas Bolka) Date: Wed, 24 Jun 2009 21:24:10 +0200 Subject: [llvm-commits] [PATCH] Scaffolding for LDA pass. In-Reply-To: <1E8830D0-2237-4DBC-B56C-48FCB6EB3A7D@apple.com> References: <1245796690-sup-9594@strider> <1E8830D0-2237-4DBC-B56C-48FCB6EB3A7D@apple.com> Message-ID: <1245871378-sup-5059@strider> On Wed Jun 24 19:29:20 +0200 2009, Dan Gohman wrote: > This patch looks fine. If you have commit access, feel free to commit > it. Otherwise I or someone else can commit it for you. Thanks Dan! I'll commit it myself. -- Andreas From daniel at zuster.org Wed Jun 24 14:25:36 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 24 Jun 2009 19:25:36 -0000 Subject: [llvm-commits] [llvm] r74109 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/MC/MCAsmStreamer.cpp unittests/MC/AsmStreamerTest.cpp Message-ID: <200906241925.n5OJPaOV031233@zion.cs.uiuc.edu> Author: ddunbar Date: Wed Jun 24 14:25:34 2009 New Revision: 74109 URL: http://llvm.org/viewvc/llvm-project?rev=74109&view=rev Log: Sketch streamer support for .align, .org functionality. Modified: llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/unittests/MC/AsmStreamerTest.cpp Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=74109&r1=74108&r2=74109&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Wed Jun 24 14:25:34 2009 @@ -10,6 +10,8 @@ #ifndef LLVM_MC_MCSTREAMER_H #define LLVM_MC_MCSTREAMER_H +#include "llvm/Support/DataTypes.h" + namespace llvm { class MCContext; class MCValue; @@ -53,6 +55,9 @@ MCContext &getContext() const { return Context; } + /// @name Symbol & Section Management + /// @{ + /// SwitchSection - Set the current section where code is being emitted to /// @param Section. /// @@ -98,6 +103,10 @@ virtual void EmitSymbolAttribute(MCSymbol *Symbol, SymbolAttr Attribute) = 0; + /// @} + /// @name Generating Data + /// @{ + /// EmitBytes - Emit @param Length bytes starting at @param Data into the /// output. /// @@ -116,6 +125,42 @@ /// match a native machine width. virtual void EmitValue(const MCValue &Value, unsigned Size) = 0; + /// EmitValueToAlignment - Emit some number of copies of @param Value until + /// the byte alignment @param ByteAlignment is reached. + /// + /// If the number of bytes need to emit for the alignment is not a multiple + /// of @param ValueSize, then the contents of the emitted fill bytes is + /// undefined. + /// + /// This used to implement the .align assembler directive. + /// + /// @param ByteAlignment - The alignment to reach. This must be a power of + /// two. + /// @param Value - The value to use when filling bytes. + /// @param Size - The size of the integer (in bytes) to emit for @param + /// Value. This must match a native machine width. + /// @param MaxBytesToEmit - The maximum numbers of bytes to emit, or 0. If + /// the alignment cannot be reached in this many bytes, no bytes are + /// emitted. + virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value = 0, + unsigned ValueSize = 1, + unsigned MaxBytesToEmit = 0) = 0; + + /// EmitValueToOffset - Emit some number of copies of @param Value until the + /// byte offset @param Offset is reached. + /// + /// This is used to implement assembler directives such as .org. + /// + /// @param Offset - The offset to reach.This may be an expression, but the + /// expression must be associated with the current section. + /// @param Value - The value to use when filling bytes. + // + // FIXME: How are we going to signal failures out of this? + virtual void EmitValueToOffset(const MCValue &Offset, + unsigned char Value = 0) = 0; + + /// @} + /// EmitInstruction - Emit the given @param Instruction into the current /// section. virtual void EmitInstruction(const MCInst &Inst) = 0; Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=74109&r1=74108&r2=74109&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Jun 24 14:25:34 2009 @@ -44,6 +44,13 @@ virtual void EmitValue(const MCValue &Value, unsigned Size); + virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value = 0, + unsigned ValueSize = 1, + unsigned MaxBytesToEmit = 0); + + virtual void EmitValueToOffset(const MCValue &Offset, + unsigned char Value = 0); + virtual void EmitInstruction(const MCInst &Inst); virtual void Finish(); @@ -144,6 +151,36 @@ OS << ' ' << Value << '\n'; } +void MCAsmStreamer::EmitValueToAlignment(unsigned ByteAlignment, int64_t Value, + unsigned ValueSize, + unsigned MaxBytesToEmit) { + unsigned Pow2 = Log2_32(ByteAlignment); + assert((1U << Pow2) == ByteAlignment && "Invalid alignment!"); + + switch (ValueSize) { + default: + assert(0 && "Invalid size for machine code value!"); + case 8: + assert(0 && "Unsupported alignment size!"); + case 1: OS << ".p2align"; break; + case 2: OS << ".p2alignw"; break; + case 4: OS << ".p2alignl"; break; + } + + OS << ' ' << Pow2; + + OS << ", " << Value; + if (MaxBytesToEmit) + OS << ", " << MaxBytesToEmit; + OS << '\n'; +} + +void MCAsmStreamer::EmitValueToOffset(const MCValue &Offset, + unsigned char Value) { + // FIXME: Verify that Offset is associated with the current section. + OS << ".org " << Offset << ", " << (unsigned) Value << '\n'; +} + void MCAsmStreamer::EmitInstruction(const MCInst &Inst) { assert(CurSection && "Cannot emit contents before setting section!"); // FIXME: Implement. Modified: llvm/trunk/unittests/MC/AsmStreamerTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/MC/AsmStreamerTest.cpp?rev=74109&r1=74108&r2=74109&view=diff ============================================================================== --- llvm/trunk/unittests/MC/AsmStreamerTest.cpp (original) +++ llvm/trunk/unittests/MC/AsmStreamerTest.cpp Wed Jun 24 14:25:34 2009 @@ -72,4 +72,32 @@ "); } +TEST(AsmStreamer, Align) { + StringAsmStreamer S; + MCSection *Sec0 = S.getContext().GetSection("foo"); + S.getStreamer().SwitchSection(Sec0); + S.getStreamer().EmitValueToAlignment(4); + S.getStreamer().EmitValueToAlignment(4, /*Value=*/12, /*ValueSize=*/2); + S.getStreamer().EmitValueToAlignment(8, /*Value=*/12, /*ValueSize=*/4, + /*MaxBytesToEmit=*/24); + EXPECT_EQ(S.getString(), ".section foo\n\ +.p2align 2, 0\n\ +.p2alignw 2, 12\n\ +.p2alignl 3, 12, 24\n\ +"); +} + +TEST(AsmStreamer, Org) { + StringAsmStreamer S; + MCSection *Sec0 = S.getContext().GetSection("foo"); + S.getStreamer().SwitchSection(Sec0); + MCSymbol *A = S.getContext().CreateSymbol("a"); + S.getStreamer().EmitLabel(A); + S.getStreamer().EmitValueToOffset(MCValue::get(A, 0, 4), 32); + EXPECT_EQ(S.getString(), ".section foo\n\ +a:\n\ +.org a + 4, 32\n\ +"); +} + } From greened at obbligato.org Wed Jun 24 14:42:14 2009 From: greened at obbligato.org (David Greene) Date: Wed, 24 Jun 2009 19:42:14 -0000 Subject: [llvm-commits] [llvm] r74110 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <200906241942.n5OJgM59031890@zion.cs.uiuc.edu> Author: greened Date: Wed Jun 24 14:41:55 2009 New Revision: 74110 URL: http://llvm.org/viewvc/llvm-project?rev=74110&view=rev Log: This increases the maximum for MVT::LAST_VALUETYPE This change doubles the allowable value for MVT::LAST_VALUETYPE. It does this by doing several things. 1. Introduces MVT::MAX_ALLOWED_LAST_VALUETYPE which in this change has a value of 64. This value contains the current maximum for the MVT::LAST_VALUETYPE. 2. Instead of checking "MVT::LAST_VALUETYPE <= 32", all of those uses now become "MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_LAST_VALUETYPE" 3. Changes the dimension of the ValueTypeActions from 2 elements to four elements and adds comments ahead of the declaration indicating the it is "(MVT::MAX_ALLOWED_LAST_VALUETYPE/32) * 2". This at least lets us find what is affected if and when MVT::MAX_ALLOWED_LAST_VALUETYPE gets changed. 4. Adds initializers for the new elements of ValueTypeActions. This does NOT add any types in MVT. That would be done separately. This doubles the size of ValueTypeActions from 64 bits to 128 bits and gives us the freedom to add more types for AVX. Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=74110&r1=74109&r2=74110&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Wed Jun 24 14:41:55 2009 @@ -1,3 +1,4 @@ + //===- CodeGen/ValueTypes.h - Low-Level Target independ. types --*- C++ -*-===// // // The LLVM Compiler Infrastructure @@ -72,6 +73,11 @@ LAST_VALUETYPE = 30, // This always remains at the end of the list. + // This is the current maximum for LAST_VALUETYPE. + // Affects ValueTypeActions in TargetLowering.h. + // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors + MAX_ALLOWED_VALUETYPE = 64, + // iPTRAny - An int value the size of the pointer of the current // target to any address space. This must only be used internal to // tblgen. Other than for overloading, we treat iPTRAny the same as iPTR. Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=74110&r1=74109&r2=74110&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Jun 24 14:41:55 2009 @@ -173,14 +173,18 @@ /// ValueTypeActions - This is a bitvector that contains two bits for each /// value type, where the two bits correspond to the LegalizeAction enum. /// This can be queried with "getTypeAction(VT)". - uint32_t ValueTypeActions[2]; + /// dimension by (MVT::MAX_ALLOWED_LAST_VALUETYPE/32) * 2 + uint32_t ValueTypeActions[4]; public: ValueTypeActionImpl() { ValueTypeActions[0] = ValueTypeActions[1] = 0; + ValueTypeActions[2] = ValueTypeActions[3] = 0; } ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { ValueTypeActions[0] = RHS.ValueTypeActions[0]; ValueTypeActions[1] = RHS.ValueTypeActions[1]; + ValueTypeActions[2] = RHS.ValueTypeActions[2]; + ValueTypeActions[3] = RHS.ValueTypeActions[3]; } LegalizeAction getTypeAction(MVT VT) const { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=74110&r1=74109&r2=74110&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jun 24 14:41:55 2009 @@ -211,7 +211,7 @@ CodeGenOpt::Level ol) : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), ValueTypeActions(TLI.getValueTypeActions()) { - assert(MVT::LAST_VALUETYPE <= 32 && + assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && "Too many value types for ValueTypeActions to hold!"); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=74110&r1=74109&r2=74110&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed Jun 24 14:41:55 2009 @@ -159,7 +159,7 @@ explicit DAGTypeLegalizer(SelectionDAG &dag) : TLI(dag.getTargetLoweringInfo()), DAG(dag), ValueTypeActions(TLI.getValueTypeActions()) { - assert(MVT::LAST_VALUETYPE <= 32 && + assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && "Too many value types for ValueTypeActions to hold!"); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=74110&r1=74109&r2=74110&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun 24 14:41:55 2009 @@ -527,7 +527,7 @@ /// computeRegisterProperties - Once all of the register classes are added, /// this allows us to compute derived properties we expose. void TargetLowering::computeRegisterProperties() { - assert(MVT::LAST_VALUETYPE <= 32 && + assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && "Too many value types for ValueTypeActions to hold!"); // Everything defaults to needing one register. From sabre at nondot.org Wed Jun 24 14:44:38 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 19:44:38 -0000 Subject: [llvm-commits] [llvm] r74111 - /llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Message-ID: <200906241944.n5OJid0a031960@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 14:44:36 2009 New Revision: 74111 URL: http://llvm.org/viewvc/llvm-project?rev=74111&view=rev Log: move some functions, add a FIXME, use PrintPICBaseSymbol to print the picbase instead of inlining it. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74111&r1=74110&r2=74111&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 14:44:36 2009 @@ -43,6 +43,9 @@ static cl::opt NewAsmPrinter("experimental-asm-printer", cl::Hidden); +//===----------------------------------------------------------------------===// +// Primitive Helper Functions. +//===----------------------------------------------------------------------===// void X86ATTAsmPrinter::PrintPICBaseSymbol() const { if (Subtarget->isTargetDarwin()) @@ -53,6 +56,14 @@ assert(0 && "Don't know how to print PIC label!\n"); } +/// PrintUnmangledNameSafely - Print out the printable characters in the name. +/// Don't print things like \\n or \\0. +static void PrintUnmangledNameSafely(const Value *V, raw_ostream &OS) { + for (const char *Name = V->getNameStart(), *E = Name+V->getNameLen(); + Name != E; ++Name) + if (isprint(*Name)) + OS << *Name; +} static X86MachineFunctionInfo calculateFunctionInfo(const Function *F, const TargetData *TD) { @@ -88,15 +99,6 @@ return Info; } -/// PrintUnmangledNameSafely - Print out the printable characters in the name. -/// Don't print things like \\n or \\0. -static void PrintUnmangledNameSafely(const Value *V, raw_ostream &OS) { - for (const char *Name = V->getNameStart(), *E = Name+V->getNameLen(); - Name != E; ++Name) - if (isprint(*Name)) - OS << *Name; -} - /// decorateName - Query FunctionInfoMap and use this information for various /// name decoration. void X86ATTAsmPrinter::decorateName(std::string &Name, @@ -151,6 +153,8 @@ } } + + void X86ATTAsmPrinter::emitFunctionHeader(const MachineFunction &MF) { const Function *F = MF.getFunction(); @@ -158,9 +162,12 @@ SwitchToSection(TAI->SectionForGlobal(F)); + // FIXME: A function's alignment should be part of MachineFunction. There + // shouldn't be a policy decision here. unsigned FnAlign = 4; if (F->hasFnAttr(Attribute::OptimizeForSize)) FnAlign = 1; + switch (F->getLinkage()) { default: assert(0 && "Unknown linkage type!"); case Function::InternalLinkage: // Symbols default to internal. @@ -456,11 +463,12 @@ << MO.getIndex(); if (TM.getRelocationModel() == Reloc::PIC_) { - if (Subtarget->isPICStyleStub()) - O << "-\"" << TAI->getPrivateGlobalPrefix() << getFunctionNumber() - << "$pb\""; - else if (Subtarget->isPICStyleGOT()) + if (Subtarget->isPICStyleStub()) { + O << '-'; + PrintPICBaseSymbol(); + } else if (Subtarget->isPICStyleGOT()) { O << "@GOTOFF"; + } } if (isMemOp && Subtarget->isPICStyleRIPRel() && !NotRIPRel) @@ -474,10 +482,10 @@ << MO.getIndex(); if (TM.getRelocationModel() == Reloc::PIC_) { - if (Subtarget->isPICStyleStub()) - O << "-\"" << TAI->getPrivateGlobalPrefix() << getFunctionNumber() - << "$pb\""; - else if (Subtarget->isPICStyleGOT()) + if (Subtarget->isPICStyleStub()) { + O << '-'; + PrintPICBaseSymbol(); + } else if (Subtarget->isPICStyleGOT()) O << "@GOTOFF"; } From sabre at nondot.org Wed Jun 24 14:48:31 2009 From: sabre at nondot.org (Chris Lattner) Date: Wed, 24 Jun 2009 19:48:31 -0000 Subject: [llvm-commits] [llvm] r74112 - /llvm/trunk/test/CodeGen/X86/pic-1.ll Message-ID: <200906241948.n5OJmciY032091@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 14:48:04 2009 New Revision: 74112 URL: http://llvm.org/viewvc/llvm-project?rev=74112&view=rev Log: unwind info not needed. Modified: llvm/trunk/test/CodeGen/X86/pic-1.ll Modified: llvm/trunk/test/CodeGen/X86/pic-1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pic-1.ll?rev=74112&r1=74111&r2=74112&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pic-1.ll (original) +++ llvm/trunk/test/CodeGen/X86/pic-1.ll Wed Jun 24 14:48:04 2009 @@ -9,7 +9,7 @@ @dst = external global i32 @src = external global i32 -define void @foo() { +define void @foo() nounwind { entry: store i32* @dst, i32** @ptr %tmp.s = load i32* @src From baldrick at free.fr Wed Jun 24 15:14:43 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 24 Jun 2009 22:14:43 +0200 Subject: [llvm-commits] [llvm] r74110 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/TargetLowering.cpp In-Reply-To: <200906241942.n5OJgM59031890@zion.cs.uiuc.edu> References: <200906241942.n5OJgM59031890@zion.cs.uiuc.edu> Message-ID: <4A428933.3050005@free.fr> Hi David, > --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original) > +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Wed Jun 24 14:41:55 2009 > @@ -1,3 +1,4 @@ > + pointless newline! > //===- CodeGen/ValueTypes.h - Low-Level Target independ. types --*- C++ -*-===// > // > // The LLVM Compiler Infrastructure > @@ -72,6 +73,11 @@ > > LAST_VALUETYPE = 30, // This always remains at the end of the list. > > + // This is the current maximum for LAST_VALUETYPE. > + // Affects ValueTypeActions in TargetLowering.h. > + // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors > + MAX_ALLOWED_VALUETYPE = 64, > + Is it checked anywhere that LAST_VALUETYPE <= MAX_ALLOWED_VALUETYPE? Ciao, Duncan. From jyasskin at google.com Wed Jun 24 15:26:12 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Wed, 24 Jun 2009 13:26:12 -0700 Subject: [llvm-commits] JITEventListener for eventual profiling and maybe gdb support In-Reply-To: References: Message-ID: Ack, sorry. I should have sent this to llvm-commits instead. :-P Followups there please. On Wed, Jun 24, 2009 at 12:02 PM, Jeffrey Yasskin wrote: > I intend to use this to support oprofile's ability to symbolize JITted > code through the interface described at > http://oprofile.sourceforge.net/doc/devel/jit-interface.html. I > believe the interface will also be useful for gdb support. I'm > considering adding some flags to the JITEventListener to let the JIT > avoid collecting information no listener is going to use, but I won't > do that until there's a need. > > I've added EmittedFunctionDetails in this patch so that I don't have > to change the NotifyFunctionEmitted() interface in a future patch. To > record line number information, oprofile wants an array of structs of > the form: > > ?struct debug_line_info { > ? ? ? unsigned long vma; > ? ? ? unsigned int lineno; > ? ? ? /* The filename format is unspecified, absolute path, relative etc. */ > ? ? ? char const * filename; > ?}; > > so I'll add enough information to produce that to the > EmittedFunctionDetails in a later patch. > > Chris mentioned that someone may want to extend this to fire events on > stub emission too. > > Let me know what you think. > Jeffrey > -------------- next part -------------- A non-text attachment was scrubbed... Name: event-listener.patch Type: application/octet-stream Size: 34353 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090624/49203279/attachment.obj From resistor at mac.com Wed Jun 24 15:41:32 2009 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Jun 2009 20:41:32 -0000 Subject: [llvm-commits] [llvm] r74113 - /llvm/trunk/include/llvm/ADT/Trie.h Message-ID: <200906242041.n5OKfbpv001283@zion.cs.uiuc.edu> Author: resistor Date: Wed Jun 24 15:41:17 2009 New Revision: 74113 URL: http://llvm.org/viewvc/llvm-project?rev=74113&view=rev Log: Update for DOTGraphTraits changes. Modified: llvm/trunk/include/llvm/ADT/Trie.h Modified: llvm/trunk/include/llvm/ADT/Trie.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Trie.h?rev=74113&r1=74112&r2=74113&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/Trie.h (original) +++ llvm/trunk/include/llvm/ADT/Trie.h Wed Jun 24 15:41:17 2009 @@ -308,7 +308,8 @@ return "Trie"; } - static std::string getNodeLabel(NodeType* Node, const Trie& T) { + static std::string getNodeLabel(NodeType* Node, const Trie& T, + bool ShortNames) { if (T.getRoot() == Node) return ""; else From lhames at gmail.com Wed Jun 24 15:46:34 2009 From: lhames at gmail.com (Lang Hames) Date: Wed, 24 Jun 2009 20:46:34 -0000 Subject: [llvm-commits] [llvm] r74114 - /llvm/trunk/lib/CodeGen/Spiller.cpp Message-ID: <200906242046.n5OKkYIp001446@zion.cs.uiuc.edu> Author: lhames Date: Wed Jun 24 15:46:24 2009 New Revision: 74114 URL: http://llvm.org/viewvc/llvm-project?rev=74114&view=rev Log: Completed basic intra block split implementation. Modified: llvm/trunk/lib/CodeGen/Spiller.cpp Modified: llvm/trunk/lib/CodeGen/Spiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=74114&r1=74113&r2=74114&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Spiller.cpp (original) +++ llvm/trunk/lib/CodeGen/Spiller.cpp Wed Jun 24 15:46:24 2009 @@ -78,24 +78,21 @@ return miIdx; } - /// Insert a store of the given vreg to the given stack slot immediately /// after the given instruction. Returns the base index of the inserted /// instruction. The caller is responsible for adding an appropriate /// LiveInterval to the LiveIntervals analysis. - unsigned insertStoreFor(MachineInstr *mi, unsigned ss, + unsigned insertStoreAfter(MachineInstr *mi, unsigned ss, unsigned vreg, const TargetRegisterClass *trc) { - MachineBasicBlock::iterator nextInstItr(mi); - ++nextInstItr; + MachineBasicBlock::iterator nextInstItr(next(mi)); unsigned miIdx = makeSpaceAfter(mi); tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, vreg, true, ss, trc); - MachineBasicBlock::iterator storeInstItr(mi); - ++storeInstItr; + MachineBasicBlock::iterator storeInstItr(next(mi)); MachineInstr *storeInst = &*storeInstItr; unsigned storeInstIdx = miIdx + LiveInterval::InstrSlots::NUM; @@ -107,37 +104,81 @@ return storeInstIdx; } - void insertStoreOnInterval(LiveInterval *li, - MachineInstr *mi, unsigned ss, - unsigned vreg, - const TargetRegisterClass *trc) { + /// Insert a store of the given vreg to the given stack slot immediately + /// before the given instructnion. Returns the base index of the inserted + /// Instruction. + unsigned insertStoreBefore(MachineInstr *mi, unsigned ss, + unsigned vreg, + const TargetRegisterClass *trc) { + unsigned miIdx = makeSpaceBefore(mi); + + tii->storeRegToStackSlot(*mi->getParent(), mi, vreg, true, ss, trc); + MachineBasicBlock::iterator storeInstItr(prior(mi)); + MachineInstr *storeInst = &*storeInstItr; + unsigned storeInstIdx = miIdx - LiveInterval::InstrSlots::NUM; - unsigned storeInstIdx = insertStoreFor(mi, ss, vreg, trc); + assert(lis->getInstructionFromIndex(storeInstIdx) == 0 && + "Store inst index already in use."); + + lis->InsertMachineInstrInMaps(storeInst, storeInstIdx); + + return storeInstIdx; + } + + void insertStoreAfterInstOnInterval(LiveInterval *li, + MachineInstr *mi, unsigned ss, + unsigned vreg, + const TargetRegisterClass *trc) { + + unsigned storeInstIdx = insertStoreAfter(mi, ss, vreg, trc); unsigned start = lis->getDefIndex(lis->getInstructionIndex(mi)), end = lis->getUseIndex(storeInstIdx); VNInfo *vni = li->getNextValue(storeInstIdx, 0, true, lis->getVNInfoAllocator()); vni->kills.push_back(storeInstIdx); + DOUT << " Inserting store range: [" << start << ", " << end << ")\n"; LiveRange lr(start, end, vni); li->addRange(lr); } - /// Insert a load of the given veg from the given stack slot immediately + /// Insert a load of the given vreg from the given stack slot immediately + /// after the given instruction. Returns the base index of the inserted + /// instruction. The caller is responsibel for adding/removing an appropriate + /// range vreg's LiveInterval. + unsigned insertLoadAfter(MachineInstr *mi, unsigned ss, + unsigned vreg, + const TargetRegisterClass *trc) { + + MachineBasicBlock::iterator nextInstItr(next(mi)); + + unsigned miIdx = makeSpaceAfter(mi); + + tii->loadRegFromStackSlot(*mi->getParent(), nextInstItr, vreg, ss, trc); + MachineBasicBlock::iterator loadInstItr(next(mi)); + MachineInstr *loadInst = &*loadInstItr; + unsigned loadInstIdx = miIdx + LiveInterval::InstrSlots::NUM; + + assert(lis->getInstructionFromIndex(loadInstIdx) == 0 && + "Store inst index already in use."); + + lis->InsertMachineInstrInMaps(loadInst, loadInstIdx); + + return loadInstIdx; + } + + /// Insert a load of the given vreg from the given stack slot immediately /// before the given instruction. Returns the base index of the inserted /// instruction. The caller is responsible for adding an appropriate /// LiveInterval to the LiveIntervals analysis. - unsigned insertLoadFor(MachineInstr *mi, unsigned ss, - unsigned vreg, - const TargetRegisterClass *trc) { - MachineBasicBlock::iterator useInstItr(mi); - + unsigned insertLoadBefore(MachineInstr *mi, unsigned ss, + unsigned vreg, + const TargetRegisterClass *trc) { unsigned miIdx = makeSpaceBefore(mi); - tii->loadRegFromStackSlot(*mi->getParent(), useInstItr, vreg, ss, trc); - MachineBasicBlock::iterator loadInstItr(mi); - --loadInstItr; + tii->loadRegFromStackSlot(*mi->getParent(), mi, vreg, ss, trc); + MachineBasicBlock::iterator loadInstItr(prior(mi)); MachineInstr *loadInst = &*loadInstItr; unsigned loadInstIdx = miIdx - LiveInterval::InstrSlots::NUM; @@ -149,18 +190,19 @@ return loadInstIdx; } - void insertLoadOnInterval(LiveInterval *li, - MachineInstr *mi, unsigned ss, - unsigned vreg, - const TargetRegisterClass *trc) { + void insertLoadBeforeInstOnInterval(LiveInterval *li, + MachineInstr *mi, unsigned ss, + unsigned vreg, + const TargetRegisterClass *trc) { - unsigned loadInstIdx = insertLoadFor(mi, ss, vreg, trc); + unsigned loadInstIdx = insertLoadBefore(mi, ss, vreg, trc); unsigned start = lis->getDefIndex(loadInstIdx), end = lis->getUseIndex(lis->getInstructionIndex(mi)); VNInfo *vni = li->getNextValue(loadInstIdx, 0, true, lis->getVNInfoAllocator()); vni->kills.push_back(lis->getInstructionIndex(mi)); + DOUT << " Intserting load range: [" << start << ", " << end << ")\n"; LiveRange lr(start, end, vni); li->addRange(lr); @@ -180,6 +222,8 @@ assert(!li->isStackSlot() && "Trying to spill a stack slot."); + DOUT << "Trivial spill everywhere of reg" << li->reg << "\n"; + std::vector added; const TargetRegisterClass *trc = mri->getRegClass(li->reg); @@ -189,6 +233,9 @@ regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) { MachineInstr *mi = &*regItr; + + DOUT << " Processing " << *mi; + do { ++regItr; } while (regItr != mri->reg_end() && (&*regItr == mi)); @@ -227,11 +274,11 @@ assert(hasUse || hasDef); if (hasUse) { - insertLoadOnInterval(newLI, mi, ss, newVReg, trc); + insertLoadBeforeInstOnInterval(newLI, mi, ss, newVReg, trc); } if (hasDef) { - insertStoreOnInterval(newLI, mi, ss, newVReg, trc); + insertStoreAfterInstOnInterval(newLI, mi, ss, newVReg, trc); } added.push_back(newLI); @@ -258,29 +305,53 @@ std::vector intraBlockSplit(LiveInterval *li, VNInfo *valno) { std::vector spillIntervals; - MachineBasicBlock::iterator storeInsertPoint; + + if (!valno->isDefAccurate() && !valno->isPHIDef()) { + // Early out for values which have no well defined def point. + return spillIntervals; + } + + // Ok.. we should be able to proceed... + const TargetRegisterClass *trc = mri->getRegClass(li->reg); + unsigned ss = vrm->assignVirt2StackSlot(li->reg); + vrm->grow(); + vrm->assignVirt2StackSlot(li->reg, ss); + + MachineInstr *mi = 0; + unsigned storeIdx = 0; if (valno->isDefAccurate()) { // If we have an accurate def we can just grab an iterator to the instr // after the def. - storeInsertPoint = - next(MachineBasicBlock::iterator(lis->getInstructionFromIndex(valno->def))); + mi = lis->getInstructionFromIndex(valno->def); + storeIdx = insertStoreAfter(mi, ss, li->reg, trc) + + LiveInterval::InstrSlots::DEF; } else { - // If the def info isn't accurate we check if this is a PHI def. - // If it is then def holds the index of the defining Basic Block, and we - // can use that to get an insertion point. - if (valno->isPHIDef()) { - - } else { - // We have no usable def info. We can't split this value sensibly. - // FIXME: Need sensible feedback for "failure to split", an empty - // set of spill intervals could be reasonably returned from a - // split where both the store and load are folded. - return spillIntervals; - } + // if we get here we have a PHI def. + mi = &lis->getMBBFromIndex(valno->def)->front(); + storeIdx = insertStoreBefore(mi, ss, li->reg, trc) + + LiveInterval::InstrSlots::DEF; + } + + MachineBasicBlock *defBlock = mi->getParent(); + unsigned loadIdx = 0; + + // Now we need to find the load... + MachineBasicBlock::iterator useItr(mi); + for (; !useItr->readsRegister(li->reg); ++useItr) {} + + if (useItr != defBlock->end()) { + MachineInstr *loadInst = useItr; + loadIdx = insertLoadBefore(loadInst, ss, li->reg, trc) + + LiveInterval::InstrSlots::USE; + } + else { + MachineInstr *loadInst = &defBlock->back(); + loadIdx = insertLoadAfter(loadInst, ss, li->reg, trc) + + LiveInterval::InstrSlots::USE; } - + li->removeRange(storeIdx, loadIdx, true); return spillIntervals; } From dag at cray.com Wed Jun 24 16:05:08 2009 From: dag at cray.com (David Greene) Date: Wed, 24 Jun 2009 16:05:08 -0500 Subject: [llvm-commits] [llvm] r74110 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/TargetLowering.cpp In-Reply-To: <4A428933.3050005@free.fr> References: <200906241942.n5OJgM59031890@zion.cs.uiuc.edu> <4A428933.3050005@free.fr> Message-ID: <200906241605.08880.dag@cray.com> On Wednesday 24 June 2009 15:14, Duncan Sands wrote: > > //===- CodeGen/ValueTypes.h - Low-Level Target independ. types --*- C++ > > -*-===// // > > // The LLVM Compiler Infrastructure > > @@ -72,6 +73,11 @@ > > > > LAST_VALUETYPE = 30, // This always remains at the end of the > > list. > > > > + // This is the current maximum for LAST_VALUETYPE. > > + // Affects ValueTypeActions in TargetLowering.h. > > + // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit > > vectors + MAX_ALLOWED_VALUETYPE = 64, > > + > > Is it checked anywhere that LAST_VALUETYPE <= MAX_ALLOWED_VALUETYPE? >From the log: 2. Instead of checking "MVT::LAST_VALUETYPE <= 32", all of those uses now become "MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_LAST_VALUETYPE" -Dave From bob.wilson at apple.com Wed Jun 24 16:09:26 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 24 Jun 2009 21:09:26 -0000 Subject: [llvm-commits] [llvm] r74117 - in /llvm/trunk: bindings/ocaml/executionengine/executionengine_ocaml.c include/llvm-c/ExecutionEngine.h include/llvm/ExecutionEngine/Interpreter.h include/llvm/ExecutionEngine/JIT.h lib/ExecutionEngine/Interpreter/Interpreter.cpp lib/ExecutionEngine/JIT/JIT.cpp Message-ID: <200906242109.n5OL9V8X002223@zion.cs.uiuc.edu> Author: bwilson Date: Wed Jun 24 16:09:18 2009 New Revision: 74117 URL: http://llvm.org/viewvc/llvm-project?rev=74117&view=rev Log: Fix the Ocaml bindings for the ExecutionEngine: with the change to build libraries instead of relinked objects, the interpreter, JIT, and native target libraries were not being linked in to an ocaml program using the ExecutionEngine. Modified: llvm/trunk/bindings/ocaml/executionengine/executionengine_ocaml.c llvm/trunk/include/llvm-c/ExecutionEngine.h llvm/trunk/include/llvm/ExecutionEngine/Interpreter.h llvm/trunk/include/llvm/ExecutionEngine/JIT.h llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp Modified: llvm/trunk/bindings/ocaml/executionengine/executionengine_ocaml.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/executionengine/executionengine_ocaml.c?rev=74117&r1=74116&r2=74117&view=diff ============================================================================== --- llvm/trunk/bindings/ocaml/executionengine/executionengine_ocaml.c (original) +++ llvm/trunk/bindings/ocaml/executionengine/executionengine_ocaml.c Wed Jun 24 16:09:18 2009 @@ -16,6 +16,7 @@ \*===----------------------------------------------------------------------===*/ #include "llvm-c/ExecutionEngine.h" +#include "llvm-c/Target.h" #include "caml/alloc.h" #include "caml/custom.h" #include "caml/fail.h" @@ -23,6 +24,12 @@ #include #include +/* Force the LLVM interpreter, JIT, and native target to be linked in. */ +void llvm_initialize(void) { + LLVMLinkInInterpreter(); + LLVMLinkInJIT(); + LLVMInitializeNativeTarget(); +} /* Can't use the recommended caml_named_value mechanism for backwards compatibility reasons. This is largely equivalent. */ Modified: llvm/trunk/include/llvm-c/ExecutionEngine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/ExecutionEngine.h?rev=74117&r1=74116&r2=74117&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/ExecutionEngine.h (original) +++ llvm/trunk/include/llvm-c/ExecutionEngine.h Wed Jun 24 16:09:18 2009 @@ -26,6 +26,9 @@ extern "C" { #endif +void LLVMLinkInJIT(void); +void LLVMLinkInInterpreter(void); + typedef struct LLVMOpaqueGenericValue *LLVMGenericValueRef; typedef struct LLVMOpaqueExecutionEngine *LLVMExecutionEngineRef; Modified: llvm/trunk/include/llvm/ExecutionEngine/Interpreter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/Interpreter.h?rev=74117&r1=74116&r2=74117&view=diff ============================================================================== --- llvm/trunk/include/llvm/ExecutionEngine/Interpreter.h (original) +++ llvm/trunk/include/llvm/ExecutionEngine/Interpreter.h Wed Jun 24 16:09:18 2009 @@ -18,9 +18,7 @@ #include "llvm/ExecutionEngine/ExecutionEngine.h" #include -namespace llvm { - extern void LinkInInterpreter(); -} +extern "C" void LLVMLinkInInterpreter(); namespace { struct ForceInterpreterLinking { @@ -32,7 +30,7 @@ if (std::getenv("bar") != (char*) -1) return; - llvm::LinkInInterpreter(); + LLVMLinkInInterpreter(); } } ForceInterpreterLinking; } Modified: llvm/trunk/include/llvm/ExecutionEngine/JIT.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/JIT.h?rev=74117&r1=74116&r2=74117&view=diff ============================================================================== --- llvm/trunk/include/llvm/ExecutionEngine/JIT.h (original) +++ llvm/trunk/include/llvm/ExecutionEngine/JIT.h Wed Jun 24 16:09:18 2009 @@ -18,9 +18,7 @@ #include "llvm/ExecutionEngine/ExecutionEngine.h" #include -namespace llvm { - extern void LinkInJIT(); -} +extern "C" void LLVMLinkInJIT(); namespace { struct ForceJITLinking { @@ -32,7 +30,7 @@ if (std::getenv("bar") != (char*) -1) return; - llvm::LinkInJIT(); + LLVMLinkInJIT(); } } ForceJITLinking; } Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp?rev=74117&r1=74116&r2=74117&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.cpp Wed Jun 24 16:09:18 2009 @@ -29,10 +29,7 @@ } -namespace llvm { - void LinkInInterpreter() { - } -} +extern "C" void LLVMLinkInInterpreter() { } /// create - Create a new interpreter object. This can never fail. /// Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp?rev=74117&r1=74116&r2=74117&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp Wed Jun 24 16:09:18 2009 @@ -60,9 +60,7 @@ } -namespace llvm { - void LinkInJIT() { - } +extern "C" void LLVMLinkInJIT() { } From jyasskin at google.com Wed Jun 24 16:09:26 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Wed, 24 Jun 2009 21:09:26 -0000 Subject: [llvm-commits] [llvm] r74116 - /llvm/trunk/docs/ReleaseNotes-2.6.html Message-ID: <200906242109.n5OL9VQ3002215@zion.cs.uiuc.edu> Author: jyasskin Date: Wed Jun 24 16:09:13 2009 New Revision: 74116 URL: http://llvm.org/viewvc/llvm-project?rev=74116&view=rev Log: ReleaseNotes.External Projects += Unladen Swallow Modified: llvm/trunk/docs/ReleaseNotes-2.6.html Modified: llvm/trunk/docs/ReleaseNotes-2.6.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes-2.6.html?rev=74116&r1=74115&r2=74116&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes-2.6.html (original) +++ llvm/trunk/docs/ReleaseNotes-2.6.html Wed Jun 24 16:09:13 2009 @@ -231,6 +231,18 @@ reimplementation of an earlier project that is now based on LLVM.

    + +
    +Unladen Swallow +
    + +
    +

    Unladen Swallow is a +branch of Python intended to be fully +compatible and significantly faster. It uses LLVM's optimization passes and JIT +compiler.

    +
    +
    From jyasskin at google.com Wed Jun 24 16:26:43 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Wed, 24 Jun 2009 21:26:43 -0000 Subject: [llvm-commits] [llvm] r74119 - /llvm/trunk/docs/ReleaseNotes-2.6.html Message-ID: <200906242126.n5OLQiJ1002735@zion.cs.uiuc.edu> Author: jyasskin Date: Wed Jun 24 16:26:42 2009 New Revision: 74119 URL: http://llvm.org/viewvc/llvm-project?rev=74119&view=rev Log: ReleaseNotes.External Projects += Rubinius Modified: llvm/trunk/docs/ReleaseNotes-2.6.html Modified: llvm/trunk/docs/ReleaseNotes-2.6.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes-2.6.html?rev=74119&r1=74118&r2=74119&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes-2.6.html (original) +++ llvm/trunk/docs/ReleaseNotes-2.6.html Wed Jun 24 16:26:42 2009 @@ -243,6 +243,17 @@ compiler.

    + +
    +Rubinius +
    + +
    +

    Rubinius is a new virtual +machine for Ruby. It leverages LLVM to dynamically compile Ruby code down to +machine code using LLVM's JIT.

    +
    +
    From evan.cheng at apple.com Wed Jun 24 16:36:52 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 24 Jun 2009 21:36:52 -0000 Subject: [llvm-commits] [llvm] r74121 - in /llvm/trunk/test/CodeGen: Thumb/dg.exp Thumb2/dg.exp Message-ID: <200906242136.n5OLas6X003162@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 24 16:36:26 2009 New Revision: 74121 URL: http://llvm.org/viewvc/llvm-project?rev=74121&view=rev Log: We should run these tests as well. Added: llvm/trunk/test/CodeGen/Thumb/dg.exp llvm/trunk/test/CodeGen/Thumb2/dg.exp Added: llvm/trunk/test/CodeGen/Thumb/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/dg.exp?rev=74121&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/dg.exp (added) +++ llvm/trunk/test/CodeGen/Thumb/dg.exp Wed Jun 24 16:36:26 2009 @@ -0,0 +1,5 @@ +load_lib llvm.exp + +if { [llvm_supports_target ARM] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] +} Added: llvm/trunk/test/CodeGen/Thumb2/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/dg.exp?rev=74121&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/dg.exp (added) +++ llvm/trunk/test/CodeGen/Thumb2/dg.exp Wed Jun 24 16:36:26 2009 @@ -0,0 +1,5 @@ +load_lib llvm.exp + +if { [llvm_supports_target ARM] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] +} From evan.cheng at apple.com Wed Jun 24 16:43:50 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 24 Jun 2009 14:43:50 -0700 Subject: [llvm-commits] JITEventListener for eventual profiling and maybe gdb support In-Reply-To: References: Message-ID: <62DFCB0E-A015-41DF-8D69-BEBFB77D9661@apple.com> Hi Jeffrey, This looks very good. Thanks. Some comments: +/// JitSymbolEntry - Each function that is JIT compiled results in one of these +/// being added to an array of symbols. This indicates the name of the function +/// as well as the address range it occupies. This allows the client to map +/// from a PC value to the name of the function. +struct JitSymbolEntry { A nitpick. Please rename it to "JITSymbolEntry" for naming consistency. + +// This is a public symbol so the performance tools can find it. +JitSymbolTable *__jitSymbolTable; + Hmm. Is there a better solution? From what I can tell, the event listener is responsible for allocating symbol table memory so it effectively owns it. Can we register the address with the performance tools? We're pushing to be more thread safe. +struct FunctionEmittedEvent { + // Indices are local to the RecordingJITEventListener, since the + // JITEventListener interface makes no guarantees about the order of + // calls between Listeners. + int Index; Use "unsigned" instead of "int"? Can index ever be negative? Evan On Jun 24, 2009, at 1:26 PM, Jeffrey Yasskin wrote: > Ack, sorry. I should have sent this to llvm-commits instead. :-P > Followups there please. > > On Wed, Jun 24, 2009 at 12:02 PM, Jeffrey > Yasskin wrote: >> I intend to use this to support oprofile's ability to symbolize >> JITted >> code through the interface described at >> http://oprofile.sourceforge.net/doc/devel/jit-interface.html. I >> believe the interface will also be useful for gdb support. I'm >> considering adding some flags to the JITEventListener to let the JIT >> avoid collecting information no listener is going to use, but I won't >> do that until there's a need. >> >> I've added EmittedFunctionDetails in this patch so that I don't have >> to change the NotifyFunctionEmitted() interface in a future patch. To >> record line number information, oprofile wants an array of structs of >> the form: >> >> struct debug_line_info { >> unsigned long vma; >> unsigned int lineno; >> /* The filename format is unspecified, absolute path, >> relative etc. */ >> char const * filename; >> }; >> >> so I'll add enough information to produce that to the >> EmittedFunctionDetails in a later patch. >> >> Chris mentioned that someone may want to extend this to fire events >> on >> stub emission too. >> >> Let me know what you think. >> Jeffrey >> > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Wed Jun 24 16:46:58 2009 From: echristo at apple.com (Eric Christopher) Date: Wed, 24 Jun 2009 14:46:58 -0700 Subject: [llvm-commits] JITEventListener for eventual profiling and maybe gdb support In-Reply-To: <62DFCB0E-A015-41DF-8D69-BEBFB77D9661@apple.com> References: <62DFCB0E-A015-41DF-8D69-BEBFB77D9661@apple.com> Message-ID: <10F2DC61-03F0-4548-91B1-A1C0DD0FBB10@apple.com> On Jun 24, 2009, at 2:43 PM, Evan Cheng wrote: > +// This is a public symbol so the performance tools can find it. > +JitSymbolTable *__jitSymbolTable; > + > > Hmm. Is there a better solution? From what I can tell, the event > listener is responsible for allocating symbol table memory so it > effectively owns it. Can we register the address with the performance > tools? We're pushing to be more thread safe. This code is just a move of something already in llvm. I'm currently bugging the performance tools guys here for a better way to do this, and have hopes of something reasonably soon I can add into llvm. That said, as far as I can tell from asking this code doesn't work with any performance tools at apple and is off by default :) -eric From dalej at apple.com Wed Jun 24 16:53:46 2009 From: dalej at apple.com (Dale Johannesen) Date: Wed, 24 Jun 2009 21:53:46 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r74123 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200906242154.n5OLs3vx003857@zion.cs.uiuc.edu> Author: johannes Date: Wed Jun 24 16:53:10 2009 New Revision: 74123 URL: http://llvm.org/viewvc/llvm-project?rev=74123&view=rev Log: More resurrection of int complex. gcc.c-torture/execute/complex-6.c Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=74123&r1=74122&r2=74123&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Jun 24 16:53:10 2009 @@ -3120,8 +3120,13 @@ // Handle complex numbers: -(a+ib) = -a + i*-b Value *R, *I; EmitLoadFromComplex(R, I, Tmp); - R = Builder.CreateFNeg(R); - I = Builder.CreateFNeg(I); + if (R->getType()->isFloatingPoint()) { + R = Builder.CreateFNeg(R); + I = Builder.CreateFNeg(I); + } else { + R = Builder.CreateNeg(R); + I = Builder.CreateNeg(I); + } EmitStoreToComplex(*DestLoc, R, I); return 0; } @@ -3137,7 +3142,10 @@ // Handle complex numbers: ~(a+ib) = a + i*-b Value *R, *I; EmitLoadFromComplex(R, I, Tmp); - I = Builder.CreateFNeg(I); + if (I->getType()->isFloatingPoint()) + I = Builder.CreateFNeg(I); + else + I = Builder.CreateNeg(I); EmitStoreToComplex(*DestLoc, R, I); return 0; } @@ -4550,6 +4558,8 @@ return false; } + // This treats everything as unknown, and is minimally defensible as + // correct, although completely useless. if (tree_low_cst (ObjSizeTree, 0) < 2) Result = ConstantInt::getAllOnesValue(TD.getIntPtrType()); else From isanbard at gmail.com Wed Jun 24 16:53:46 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 24 Jun 2009 21:53:46 -0000 Subject: [llvm-commits] [llvm] r74122 - /llvm/tags/Apple/llvmCore-2115/ Message-ID: <200906242154.n5OLs3qm003848@zion.cs.uiuc.edu> Author: void Date: Wed Jun 24 16:52:48 2009 New Revision: 74122 URL: http://llvm.org/viewvc/llvm-project?rev=74122&view=rev Log: Creating llvmCore-2115 branch Added: llvm/tags/Apple/llvmCore-2115/ - copied from r74121, llvm/branches/Apple/Bender/ From isanbard at gmail.com Wed Jun 24 16:54:52 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 24 Jun 2009 21:54:52 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r74124 - /llvm-gcc-4.2/tags/Apple/llvmgcc42-2115/ Message-ID: <200906242154.n5OLsrbu003948@zion.cs.uiuc.edu> Author: void Date: Wed Jun 24 16:54:40 2009 New Revision: 74124 URL: http://llvm.org/viewvc/llvm-project?rev=74124&view=rev Log: Creating llvmgcc42-2115 branch Added: llvm-gcc-4.2/tags/Apple/llvmgcc42-2115/ - copied from r74123, llvm-gcc-4.2/branches/Apple/Bender/ From resistor at mac.com Wed Jun 24 17:09:11 2009 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Jun 2009 22:09:11 -0000 Subject: [llvm-commits] [llvm] r74125 - in /llvm/trunk: include/llvm/Analysis/ProfileInfoLoader.h lib/Analysis/ProfileInfoLoader.cpp Message-ID: <200906242209.n5OM9N7t004378@zion.cs.uiuc.edu> Author: resistor Date: Wed Jun 24 17:08:59 2009 New Revision: 74125 URL: http://llvm.org/viewvc/llvm-project?rev=74125&view=rev Log: Get rid of a static boolean. Modified: llvm/trunk/include/llvm/Analysis/ProfileInfoLoader.h llvm/trunk/lib/Analysis/ProfileInfoLoader.cpp Modified: llvm/trunk/include/llvm/Analysis/ProfileInfoLoader.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ProfileInfoLoader.h?rev=74125&r1=74124&r2=74125&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ProfileInfoLoader.h (original) +++ llvm/trunk/include/llvm/Analysis/ProfileInfoLoader.h Wed Jun 24 17:08:59 2009 @@ -33,6 +33,7 @@ std::vector BlockCounts; std::vector EdgeCounts; std::vector BBTrace; + bool Warned; public: // ProfileInfoLoader ctor - Read the specified profiling data file, exiting // the program if the file is invalid or broken. Modified: llvm/trunk/lib/Analysis/ProfileInfoLoader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ProfileInfoLoader.cpp?rev=74125&r1=74124&r2=74125&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ProfileInfoLoader.cpp (original) +++ llvm/trunk/lib/Analysis/ProfileInfoLoader.cpp Wed Jun 24 17:08:59 2009 @@ -73,7 +73,8 @@ // ProfileInfoLoader::ProfileInfoLoader(const char *ToolName, const std::string &Filename, - Module &TheModule) : M(TheModule) { + Module &TheModule) : + M(TheModule), Warned(false) { FILE *F = fopen(Filename.c_str(), "r"); if (F == 0) { cerr << ToolName << ": Error opening '" << Filename << "': "; @@ -200,7 +201,6 @@ Counts.back().second += EdgeCounts[i].second; unsigned SuccNum = EdgeCounts[i].first.second; if (SuccNum >= TI->getNumSuccessors()) { - static bool Warned = false; if (!Warned) { cerr << "WARNING: profile info doesn't seem to match" << " the program!\n"; From resistor at mac.com Wed Jun 24 17:16:53 2009 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Jun 2009 22:16:53 -0000 Subject: [llvm-commits] [llvm] r74129 - /llvm/trunk/lib/Analysis/IPA/Andersens.cpp Message-ID: <200906242216.n5OMGrdb004695@zion.cs.uiuc.edu> Author: resistor Date: Wed Jun 24 17:16:52 2009 New Revision: 74129 URL: http://llvm.org/viewvc/llvm-project?rev=74129&view=rev Log: Make this thread-safe. Modified: llvm/trunk/lib/Analysis/IPA/Andersens.cpp Modified: llvm/trunk/lib/Analysis/IPA/Andersens.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/Andersens.cpp?rev=74129&r1=74128&r2=74129&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/Andersens.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/Andersens.cpp Wed Jun 24 17:16:52 2009 @@ -65,6 +65,7 @@ #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/Passes.h" #include "llvm/Support/Debug.h" +#include "llvm/System/Atomic.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/SparseBitVector.h" #include "llvm/ADT/DenseSet.h" @@ -284,7 +285,8 @@ // Timestamp a node (used for work list prioritization) void Stamp() { - Timestamp = Counter++; + Timestamp = Counter; + sys::AtomicIncrement(&Counter); } bool isRep() const { From greened at obbligato.org Wed Jun 24 17:22:03 2009 From: greened at obbligato.org (David Greene) Date: Wed, 24 Jun 2009 22:22:03 -0000 Subject: [llvm-commits] [llvm] r74130 - in /llvm/trunk/include/llvm: CodeGen/ValueTypes.h Target/TargetLowering.h Message-ID: <200906242222.n5OMM4MJ004873@zion.cs.uiuc.edu> Author: greened Date: Wed Jun 24 17:22:02 2009 New Revision: 74130 URL: http://llvm.org/viewvc/llvm-project?rev=74130&view=rev Log: Increase limit for OpActions array The OpActions array had a limit of 32 value types, so change it to use MVT::MAX_ALLOWED_VALUETYPE in its declaration and change the accesses to this array to work with a VT.getSimpleVT() that is larger than 32. Also, add a comment to the place where MVT::MAX_ALLOWED_VALUETYPE is defined indicating that it must be a multiple of 32. This is part of the work allow MVT::LAST_VALUETYPE be greater than 32. Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h llvm/trunk/include/llvm/Target/TargetLowering.h Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=74130&r1=74129&r2=74130&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Wed Jun 24 17:22:02 2009 @@ -76,6 +76,7 @@ // This is the current maximum for LAST_VALUETYPE. // Affects ValueTypeActions in TargetLowering.h. // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors + // This value must be a multiple of 32. MAX_ALLOWED_VALUETYPE = 64, // iPTRAny - An int value the size of the pointer of the current Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=74130&r1=74129&r2=74130&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Jun 24 17:22:02 2009 @@ -173,8 +173,8 @@ /// ValueTypeActions - This is a bitvector that contains two bits for each /// value type, where the two bits correspond to the LegalizeAction enum. /// This can be queried with "getTypeAction(VT)". - /// dimension by (MVT::MAX_ALLOWED_LAST_VALUETYPE/32) * 2 - uint32_t ValueTypeActions[4]; + /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2 + uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2]; public: ValueTypeActionImpl() { ValueTypeActions[0] = ValueTypeActions[1] = 0; @@ -353,10 +353,13 @@ /// for it. LegalizeAction getOperationAction(unsigned Op, MVT VT) const { if (VT.isExtended()) return Expand; - assert(Op < array_lengthof(OpActions) && - (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*8 && + assert(Op < array_lengthof(OpActions[0]) && + (unsigned)VT.getSimpleVT() < sizeof(OpActions[0][0])*8 && "Table isn't big enough!"); - return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3); + unsigned I = (unsigned) VT.getSimpleVT(); + unsigned J = I & 31; + I = I >> 5; + return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3); } /// isOperationLegalOrCustom - Return true if the specified operation is @@ -944,10 +947,13 @@ /// with the specified type and indicate what to do about it. void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) { - assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*8 && - Op < array_lengthof(OpActions) && "Table isn't big enough!"); - OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); - OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2; + assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0][0])*8 && + Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); + unsigned I = (unsigned) VT.getSimpleVT(); + unsigned J = I & 31; + I = I >> 5; + OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2)); + OpActions[I][Op] |= (uint64_t)Action << (J*2); } /// setLoadExtAction - Indicate that the specified load with extension does @@ -1570,7 +1576,9 @@ /// Most operations are Legal (aka, supported natively by the target), but /// operations that are not should be described. Note that operations on /// non-legal value types are not described here. - uint64_t OpActions[ISD::BUILTIN_OP_END]; + /// This array is accessed using VT.getSimpleVT(), so it is subject to + /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits. + uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END]; /// LoadExtActions - For each load of load extension type and each value type, /// keep a LegalizeAction that indicates how instruction selection should deal From resistor at mac.com Wed Jun 24 17:28:13 2009 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Jun 2009 22:28:13 -0000 Subject: [llvm-commits] [llvm] r74132 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp Message-ID: <200906242228.n5OMSEQj005083@zion.cs.uiuc.edu> Author: resistor Date: Wed Jun 24 17:28:12 2009 New Revision: 74132 URL: http://llvm.org/viewvc/llvm-project?rev=74132&view=rev Log: Move local statics to per-instance variables. Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=74132&r1=74131&r2=74132&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Wed Jun 24 17:28:12 2009 @@ -109,6 +109,12 @@ /// bool VerboseAsm; + /// Private state for PrintSpecial() + // Assign a unique ID to this machine instruction. + mutable const MachineInstr *LastMI; + mutable const Function *LastFn; + mutable unsigned Counter; + protected: explicit AsmPrinter(raw_ostream &o, TargetMachine &TM, const TargetAsmInfo *T, CodeGenOpt::Level OL, bool V); Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=74132&r1=74131&r2=74132&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Jun 24 17:28:12 2009 @@ -45,7 +45,7 @@ const TargetAsmInfo *T, CodeGenOpt::Level OL, bool VDef) : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o), TM(tm), TAI(T), TRI(tm.getRegisterInfo()), - IsInTextSection(false) { + IsInTextSection(false), LastMI(0), LastFn(0), Counter(~0U) { DW = 0; MMI = 0; switch (AsmVerbose) { case cl::BOU_UNSET: VerboseAsm = VDef; break; @@ -1315,20 +1315,15 @@ if (VerboseAsm) O << TAI->getCommentString(); } else if (!strcmp(Code, "uid")) { - // Assign a unique ID to this machine instruction. - static const MachineInstr *LastMI = 0; - static const Function *F = 0; - static unsigned Counter = 0U-1; - // Comparing the address of MI isn't sufficient, because machineinstrs may // be allocated to the same address across functions. const Function *ThisF = MI->getParent()->getParent()->getFunction(); - // If this is a new machine instruction, bump the counter. - if (LastMI != MI || F != ThisF) { + // If this is a new LastFn instruction, bump the counter. + if (LastMI != MI || LastFn != ThisF) { ++Counter; LastMI = MI; - F = ThisF; + LastFn = ThisF; } O << Counter; } else { From dpatel at apple.com Wed Jun 24 17:43:05 2009 From: dpatel at apple.com (Devang Patel) Date: Wed, 24 Jun 2009 22:43:05 -0000 Subject: [llvm-commits] [llvm] r74133 - in /llvm/trunk: include/llvm/Constants.h lib/VMCore/Constants.cpp Message-ID: <200906242243.n5OMhGOe005520@zion.cs.uiuc.edu> Author: dpatel Date: Wed Jun 24 17:42:39 2009 New Revision: 74133 URL: http://llvm.org/viewvc/llvm-project?rev=74133&view=rev Log: Add constructor to create MDString using std::string Modified: llvm/trunk/include/llvm/Constants.h llvm/trunk/lib/VMCore/Constants.cpp Modified: llvm/trunk/include/llvm/Constants.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=74133&r1=74132&r2=74133&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constants.h (original) +++ llvm/trunk/include/llvm/Constants.h Wed Jun 24 17:42:39 2009 @@ -865,6 +865,7 @@ /// get() - Static factory methods - Return objects of the specified value. /// static MDString *get(const char *StrBegin, const char *StrEnd); + static MDString *get(const std::string &Str); /// size() - The length of this string. /// Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=74133&r1=74132&r2=74133&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Wed Jun 24 17:42:39 2009 @@ -1803,6 +1803,17 @@ return S; } +MDString *MDString::get(const std::string &Str) { + sys::SmartScopedWriter Writer(&*ConstantsLock); + StringMapEntry &Entry = MDStringCache->GetOrCreateValue( + Str.data(), Str.data() + Str.size()); + MDString *&S = Entry.getValue(); + if (!S) S = new MDString(Entry.getKeyData(), + Entry.getKeyData() + Entry.getKeyLength()); + + return S; +} + void MDString::destroyConstant() { sys::SmartScopedWriter Writer(&*ConstantsLock); MDStringCache->erase(MDStringCache->find(StrBegin, StrEnd)); From resistor at mac.com Wed Jun 24 17:53:43 2009 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Jun 2009 22:53:43 -0000 Subject: [llvm-commits] [llvm] r74134 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <200906242253.n5OMrmA7005859@zion.cs.uiuc.edu> Author: resistor Date: Wed Jun 24 17:53:20 2009 New Revision: 74134 URL: http://llvm.org/viewvc/llvm-project?rev=74134&view=rev Log: Down with statics! Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=74134&r1=74133&r2=74134&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Wed Jun 24 17:53:20 2009 @@ -114,6 +114,9 @@ mutable const MachineInstr *LastMI; mutable const Function *LastFn; mutable unsigned Counter; + + // Private state for dump() + static unsigned IndentLevel; protected: explicit AsmPrinter(raw_ostream &o, TargetMachine &TM, Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=74134&r1=74133&r2=74134&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Jun 24 17:53:20 2009 @@ -141,9 +141,12 @@ SmallVector Scopes; // Scopes defined in scope. SmallVector Variables;// Variables declared in scope. SmallVector ConcreteInsts;// Concrete insts of funcs. + + // Private state for dump() + mutable unsigned IndentLevel; public: DbgScope(DbgScope *P, DIDescriptor D) - : Parent(P), Desc(D), StartLabelID(0), EndLabelID(0) {} + : Parent(P), Desc(D), StartLabelID(0), EndLabelID(0), IndentLevel(0) {} virtual ~DbgScope(); // Accessors. @@ -176,7 +179,6 @@ #ifndef NDEBUG void DbgScope::dump() const { - static unsigned IndentLevel = 0; std::string Indent(IndentLevel, ' '); cerr << Indent; Desc.dump(); From resistor at mac.com Wed Jun 24 17:59:05 2009 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Jun 2009 22:59:05 -0000 Subject: [llvm-commits] [llvm] r74135 - /llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200906242259.n5OMx8CM006005@zion.cs.uiuc.edu> Author: resistor Date: Wed Jun 24 17:58:48 2009 New Revision: 74135 URL: http://llvm.org/viewvc/llvm-project?rev=74135&view=rev Log: Didn't mean to commit this part. Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=74135&r1=74134&r2=74135&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Wed Jun 24 17:58:48 2009 @@ -114,9 +114,6 @@ mutable const MachineInstr *LastMI; mutable const Function *LastFn; mutable unsigned Counter; - - // Private state for dump() - static unsigned IndentLevel; protected: explicit AsmPrinter(raw_ostream &o, TargetMachine &TM, From resistor at mac.com Wed Jun 24 18:14:15 2009 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Jun 2009 23:14:15 -0000 Subject: [llvm-commits] [llvm] r74137 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DIE.cpp DIE.h Message-ID: <200906242314.n5ONEIci006627@zion.cs.uiuc.edu> Author: resistor Date: Wed Jun 24 18:13:56 2009 New Revision: 74137 URL: http://llvm.org/viewvc/llvm-project?rev=74137&view=rev Log: Down with _even more_ statics! Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp?rev=74137&r1=74136&r2=74137&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp Wed Jun 24 18:13:56 2009 @@ -126,7 +126,6 @@ #ifndef NDEBUG void DIE::print(std::ostream &O, unsigned IncIndent) { - static unsigned IndentCount = 0; IndentCount += IncIndent; const std::string Indent(IndentCount, ' '); bool isBlock = Abbrev.getTag() == 0; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h?rev=74137&r1=74136&r2=74137&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h Wed Jun 24 18:13:56 2009 @@ -141,9 +141,13 @@ /// Abstract compile unit. CompileUnit *AbstractCU; + + // Private data for print() + mutable unsigned IndentCount; public: explicit DIE(unsigned Tag) - : Abbrev(Tag, dwarf::DW_CHILDREN_no), Offset(0), Size(0) {} + : Abbrev(Tag, dwarf::DW_CHILDREN_no), Offset(0), + Size(0), IndentCount(0) {} virtual ~DIE(); // Accessors. From evan.cheng at apple.com Wed Jun 24 18:14:47 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 24 Jun 2009 23:14:47 -0000 Subject: [llvm-commits] [llvm] r74138 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <200906242314.n5ONEl3p006651@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 24 18:14:45 2009 New Revision: 74138 URL: http://llvm.org/viewvc/llvm-project?rev=74138&view=rev Log: 80 col violation. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=74138&r1=74137&r2=74138&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jun 24 18:14:45 2009 @@ -535,7 +535,8 @@ "add$p $dst, pc, #PCRELV${:uid}")), []>; -def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p), +def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), + (ins i32imm:$label, i32imm:$id, pred:$p), Pseudo, !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", "${:private}PCRELL${:uid}+8))\n"), From daniel at zuster.org Wed Jun 24 18:30:18 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 24 Jun 2009 23:30:18 -0000 Subject: [llvm-commits] [llvm] r74139 - in /llvm/trunk: test/MC/ test/MC/AsmParser/ test/MC/AsmParser/dg.exp test/MC/AsmParser/directive_ascii.s test/MC/AsmParser/directive_fill.s test/MC/AsmParser/directive_space.s test/MC/AsmParser/directive_values.s tools/llvm-mc/AsmParser.cpp tools/llvm-mc/AsmParser.h tools/llvm-mc/llvm-mc.cpp Message-ID: <200906242330.n5ONUVE6007123@zion.cs.uiuc.edu> Author: ddunbar Date: Wed Jun 24 18:30:00 2009 New Revision: 74139 URL: http://llvm.org/viewvc/llvm-project?rev=74139&view=rev Log: Basic .s parsing for .asci[iz], .fill, .space, {.byte, .short, ... } - Includes some DG tests in test/MC/AsmParser, which are rather primitive since we don't have a -verify mode yet. Added: llvm/trunk/test/MC/ llvm/trunk/test/MC/AsmParser/ (with props) llvm/trunk/test/MC/AsmParser/dg.exp llvm/trunk/test/MC/AsmParser/directive_ascii.s llvm/trunk/test/MC/AsmParser/directive_fill.s llvm/trunk/test/MC/AsmParser/directive_space.s llvm/trunk/test/MC/AsmParser/directive_values.s Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp llvm/trunk/tools/llvm-mc/AsmParser.h llvm/trunk/tools/llvm-mc/llvm-mc.cpp Propchange: llvm/trunk/test/MC/AsmParser/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Wed Jun 24 18:30:00 2009 @@ -0,0 +1 @@ +Output Added: llvm/trunk/test/MC/AsmParser/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/dg.exp?rev=74139&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/dg.exp (added) +++ llvm/trunk/test/MC/AsmParser/dg.exp Wed Jun 24 18:30:00 2009 @@ -0,0 +1,3 @@ +load_lib llvm.exp + +RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{s}]] Added: llvm/trunk/test/MC/AsmParser/directive_ascii.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_ascii.s?rev=74139&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_ascii.s (added) +++ llvm/trunk/test/MC/AsmParser/directive_ascii.s Wed Jun 24 18:30:00 2009 @@ -0,0 +1,25 @@ +# RUN: llvm-mc %s > %t + +# RUN: grep -A 1 TEST0 %t > %t2 +# RUN: not grep ".byte" %t2 +TEST0: + .ascii + +# RUN: grep -A 1 TEST1 %t > %t2 +# RUN: not grep "byte" %t2 +TEST1: + .asciz + +# RUN: grep -A 2 TEST2 %t > %t2 +# RUN: grep ".byte 65" %t2 | count 1 +TEST2: + .ascii "A" + +# RUN: grep -A 5 TEST3 %t > %t2 +# RUN: grep ".byte 66" %t2 | count 1 +# RUN: grep ".byte 67" %t2 | count 1 +# RUN: grep ".byte 0" %t2 | count 2 +TEST3: + .asciz "B", "C" + + \ No newline at end of file Added: llvm/trunk/test/MC/AsmParser/directive_fill.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_fill.s?rev=74139&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_fill.s (added) +++ llvm/trunk/test/MC/AsmParser/directive_fill.s Wed Jun 24 18:30:00 2009 @@ -0,0 +1,11 @@ +# RUN: llvm-mc %s > %t + +# RUN: grep -A 2 TEST0 %t > %t2 +# RUN: grep ".byte 10" %t2 | count 1 +TEST0: + .fill 1, 1, 10 + +# RUN: grep -A 3 TEST1 %t > %t2 +# RUN: grep ".short 3" %t2 | count 2 +TEST1: + .fill 2, 2, 3 Added: llvm/trunk/test/MC/AsmParser/directive_space.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_space.s?rev=74139&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_space.s (added) +++ llvm/trunk/test/MC/AsmParser/directive_space.s Wed Jun 24 18:30:00 2009 @@ -0,0 +1,11 @@ +# RUN: llvm-mc %s > %t + +# RUN: grep -A 2 TEST0 %t > %t2 +# RUN: grep ".byte 0" %t2 | count 1 +TEST0: + .space 1 + +# RUN: grep -A 3 TEST1 %t > %t2 +# RUN: grep ".byte 3" %t2 | count 2 +TEST1: + .space 2, 3 Added: llvm/trunk/test/MC/AsmParser/directive_values.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_values.s?rev=74139&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_values.s (added) +++ llvm/trunk/test/MC/AsmParser/directive_values.s Wed Jun 24 18:30:00 2009 @@ -0,0 +1,21 @@ +# RUN: llvm-mc %s > %t + +# RUN: grep -A 2 TEST0 %t > %t2 +# RUN: grep ".byte 0" %t2 | count 1 +TEST0: + .byte 0 + +# RUN: grep -A 2 TEST1 %t > %t2 +# RUN: grep ".short 3" %t2 | count 1 +TEST1: + .short 3 + +# RUN: grep -A 2 TEST2 %t > %t2 +# RUN: grep ".long 8" %t2 | count 1 +TEST2: + .long 8 + +# RUN: grep -A 2 TEST3 %t > %t2 +# RUN: grep ".quad 9" %t2 | count 1 +TEST3: + .quad 9 Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=74139&r1=74138&r2=74139&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Wed Jun 24 18:30:00 2009 @@ -291,7 +291,27 @@ if (!strcmp(IDVal, ".objc_selector_strs")) return ParseDirectiveSectionSwitch("__OBJC,__selector_strs"); - + // Data directives + + if (!strcmp(IDVal, ".ascii")) + return ParseDirectiveAscii(false); + if (!strcmp(IDVal, ".asciz")) + return ParseDirectiveAscii(true); + + // FIXME: Target hooks for size? Also for "word", "hword". + if (!strcmp(IDVal, ".byte")) + return ParseDirectiveValue(1); + if (!strcmp(IDVal, ".short")) + return ParseDirectiveValue(2); + if (!strcmp(IDVal, ".long")) + return ParseDirectiveValue(4); + if (!strcmp(IDVal, ".quad")) + return ParseDirectiveValue(8); + if (!strcmp(IDVal, ".fill")) + return ParseDirectiveFill(); + if (!strcmp(IDVal, ".space")) + return ParseDirectiveSpace(); + Lexer.PrintMessage(IDLoc, "warning: ignoring directive for now"); EatToEndOfStatement(); return false; @@ -361,3 +381,131 @@ Out.SwitchSection(Ctx.GetSection(Section)); return false; } + +/// ParseDirectiveAscii: +/// ::= ( .ascii | .asciiz ) [ "string" ( , "string" )* ] +bool AsmParser::ParseDirectiveAscii(bool ZeroTerminated) { + if (Lexer.isNot(asmtok::EndOfStatement)) { + for (;;) { + if (Lexer.isNot(asmtok::String)) + return TokError("expected string in '.ascii' or '.asciz' directive"); + + // FIXME: This shouldn't use a const char* + strlen, the string could have + // embedded nulls. + // FIXME: Should have accessor for getting string contents. + const char *Str = Lexer.getCurStrVal(); + Out.EmitBytes(Str + 1, strlen(Str) - 2); + if (ZeroTerminated) + Out.EmitBytes("\0", 1); + + Lexer.Lex(); + + if (Lexer.is(asmtok::EndOfStatement)) + break; + + if (Lexer.isNot(asmtok::Comma)) + return TokError("unexpected token in '.ascii' or '.asciz' directive"); + Lexer.Lex(); + } + } + + Lexer.Lex(); + return false; +} + +/// ParseDirectiveValue +/// ::= (.byte | .short | ... ) [ expression (, expression)* ] +bool AsmParser::ParseDirectiveValue(unsigned Size) { + if (Lexer.isNot(asmtok::EndOfStatement)) { + for (;;) { + int64_t Expr; + if (ParseExpression(Expr)) + return true; + + Out.EmitValue(MCValue::get(Expr), Size); + + if (Lexer.is(asmtok::EndOfStatement)) + break; + + // FIXME: Improve diagnostic. + if (Lexer.isNot(asmtok::Comma)) + return TokError("unexpected token in directive"); + Lexer.Lex(); + } + } + + Lexer.Lex(); + return false; +} + +/// ParseDirectiveSpace +/// ::= .space expression [ , expression ] +bool AsmParser::ParseDirectiveSpace() { + int64_t NumBytes; + if (ParseExpression(NumBytes)) + return true; + + int64_t FillExpr = 0; + bool HasFillExpr = false; + if (Lexer.isNot(asmtok::EndOfStatement)) { + if (Lexer.isNot(asmtok::Comma)) + return TokError("unexpected token in '.space' directive"); + Lexer.Lex(); + + if (ParseExpression(FillExpr)) + return true; + + HasFillExpr = true; + + if (Lexer.isNot(asmtok::EndOfStatement)) + return TokError("unexpected token in '.space' directive"); + } + + Lexer.Lex(); + + if (NumBytes <= 0) + return TokError("invalid number of bytes in '.space' directive"); + + // FIXME: Sometimes the fill expr is 'nop' if it isn't supplied, instead of 0. + for (uint64_t i = 0, e = NumBytes; i != e; ++i) + Out.EmitValue(MCValue::get(FillExpr), 1); + + return false; +} + +/// ParseDirectiveFill +/// ::= .fill expression , expression , expression +bool AsmParser::ParseDirectiveFill() { + int64_t NumValues; + if (ParseExpression(NumValues)) + return true; + + if (Lexer.isNot(asmtok::Comma)) + return TokError("unexpected token in '.fill' directive"); + Lexer.Lex(); + + int64_t FillSize; + if (ParseExpression(FillSize)) + return true; + + if (Lexer.isNot(asmtok::Comma)) + return TokError("unexpected token in '.fill' directive"); + Lexer.Lex(); + + int64_t FillExpr; + if (ParseExpression(FillExpr)) + return true; + + if (Lexer.isNot(asmtok::EndOfStatement)) + return TokError("unexpected token in '.fill' directive"); + + Lexer.Lex(); + + if (FillSize != 1 && FillSize != 2 && FillSize != 4) + return TokError("invalid '.fill' size, expected 1, 2, or 4"); + + for (uint64_t i = 0, e = NumValues; i != e; ++i) + Out.EmitValue(MCValue::get(FillExpr), FillSize); + + return false; +} Modified: llvm/trunk/tools/llvm-mc/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.h?rev=74139&r1=74138&r2=74139&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.h (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.h Wed Jun 24 18:30:00 2009 @@ -57,6 +57,10 @@ bool ParseDirectiveDarwinSection(); // Darwin specific ".section". bool ParseDirectiveSectionSwitch(const char *Section, const char *Directives = 0); + bool ParseDirectiveAscii(bool ZeroTerminated); // ".ascii", ".asciiz" + bool ParseDirectiveValue(unsigned Size); // ".byte", ".long", ... + bool ParseDirectiveFill(); // ".fill" + bool ParseDirectiveSpace(); // ".space" }; Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=74139&r1=74138&r2=74139&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Jun 24 18:30:00 2009 @@ -141,6 +141,10 @@ MCContext Ctx; OwningPtr Str(createAsmStreamer(Ctx, outs())); + + // FIXME: Target hook & command line option for initial section. + Str.get()->SwitchSection(Ctx.GetSection("__TEXT,__text,regular,pure_instructions")); + AsmParser Parser(SrcMgr, Ctx, *Str.get()); return Parser.Run(); } From resistor at mac.com Wed Jun 24 18:42:17 2009 From: resistor at mac.com (Owen Anderson) Date: Wed, 24 Jun 2009 23:42:17 -0000 Subject: [llvm-commits] [llvm] r74140 - /llvm/trunk/lib/CodeGen/IfConversion.cpp Message-ID: <200906242342.n5ONgLXx007483@zion.cs.uiuc.edu> Author: resistor Date: Wed Jun 24 18:41:44 2009 New Revision: 74140 URL: http://llvm.org/viewvc/llvm-project?rev=74140&view=rev Log: Fewer static variables, part 3 of many. Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=74140&r1=74139&r2=74140&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Wed Jun 24 18:41:44 2009 @@ -144,9 +144,10 @@ const TargetLowering *TLI; const TargetInstrInfo *TII; bool MadeChange; + int FnNum; public: static char ID; - IfConverter() : MachineFunctionPass(&ID) {} + IfConverter() : MachineFunctionPass(&ID), FnNum(-1) {} virtual bool runOnMachineFunction(MachineFunction &MF); virtual const char *getPassName() const { return "If Converter"; } @@ -225,7 +226,6 @@ TII = MF.getTarget().getInstrInfo(); if (!TII) return false; - static int FnNum = -1; DOUT << "\nIfcvt: function (" << ++FnNum << ") \'" << MF.getFunction()->getName() << "\'"; From evan.cheng at apple.com Wed Jun 24 18:48:02 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 24 Jun 2009 23:48:02 -0000 Subject: [llvm-commits] [llvm] r74141 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/Thumb2/load-global.ll test/CodeGen/Thumb2/pic-jtbl.ll Message-ID: <200906242348.n5ONm5i8007653@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 24 18:47:58 2009 New Revision: 74141 URL: http://llvm.org/viewvc/llvm-project?rev=74141&view=rev Log: Add Thumb2 pc relative add. Added: llvm/trunk/test/CodeGen/Thumb2/load-global.ll llvm/trunk/test/CodeGen/Thumb2/pic-jtbl.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=74141&r1=74140&r2=74141&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Jun 24 18:47:58 2009 @@ -128,7 +128,7 @@ } let isNotDuplicable = 1 in -def tPICADD : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp), +def tPICADD : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp), "$cp:\n\tadd $dst, pc", [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=74141&r1=74140&r2=74141&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jun 24 18:47:58 2009 @@ -315,6 +315,33 @@ } //===----------------------------------------------------------------------===// +// Miscellaneous Instructions. +// + +let isNotDuplicable = 1 in +def t2PICADD : T2I<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp), + "$cp:\n\tadd $dst, pc", + [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>; + + +// LEApcrel - Load a pc-relative address into a register without offending the +// assembler. +def t2LEApcrel : T2I<(outs GPR:$dst), (ins i32imm:$label, pred:$p), + !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", + "${:private}PCRELL${:uid}+8))\n"), + !strconcat("${:private}PCRELL${:uid}:\n\t", + "add$p $dst, pc, #PCRELV${:uid}")), + []>; + +def t2LEApcrelJT : T2I<(outs GPR:$dst), + (ins i32imm:$label, i32imm:$id, pred:$p), + !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", + "${:private}PCRELL${:uid}+8))\n"), + !strconcat("${:private}PCRELL${:uid}:\n\t", + "add$p $dst, pc, #PCRELV${:uid}")), + []>; + +//===----------------------------------------------------------------------===// // Arithmetic Instructions. // @@ -493,6 +520,12 @@ // Non-Instruction Patterns // +// ConstantPool, GlobalAddress, and JumpTable +def : Thumb2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>; +def : Thumb2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; +def : Thumb2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), + (t2LEApcrelJT tjumptable:$dst, imm:$id)>; + // Large immediate handling. def : Thumb2Pat<(i32 imm:$src), Added: llvm/trunk/test/CodeGen/Thumb2/load-global.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/load-global.ll?rev=74141&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/load-global.ll (added) +++ llvm/trunk/test/CodeGen/Thumb2/load-global.ll Wed Jun 24 18:47:58 2009 @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin +; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -relocation-model=pic | grep add | grep pc + + at G = external global i32 + +define i32 @test1() { + %tmp = load i32* @G + ret i32 %tmp +} Added: llvm/trunk/test/CodeGen/Thumb2/pic-jtbl.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/pic-jtbl.ll?rev=74141&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/pic-jtbl.ll (added) +++ llvm/trunk/test/CodeGen/Thumb2/pic-jtbl.ll Wed Jun 24 18:47:58 2009 @@ -0,0 +1,55 @@ +; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -relocation-model=pic \ +; RUN: -o %t -f +; RUN: grep add %t | grep pc +;; NOT YET: grep "add pc" + +define void @bar(i32 %n.u) { +entry: + switch i32 %n.u, label %bb12 [i32 1, label %bb i32 2, label %bb6 i32 4, label %bb7 i32 5, label %bb8 i32 6, label %bb10 i32 7, label %bb1 i32 8, label %bb3 i32 9, label %bb4 i32 10, label %bb9 i32 11, label %bb2 i32 12, label %bb5 i32 13, label %bb11 ] +bb: + tail call void(...)* @foo1() + ret void +bb1: + tail call void(...)* @foo2() + ret void +bb2: + tail call void(...)* @foo6() + ret void +bb3: + tail call void(...)* @foo3() + ret void +bb4: + tail call void(...)* @foo4() + ret void +bb5: + tail call void(...)* @foo5() + ret void +bb6: + tail call void(...)* @foo1() + ret void +bb7: + tail call void(...)* @foo2() + ret void +bb8: + tail call void(...)* @foo6() + ret void +bb9: + tail call void(...)* @foo3() + ret void +bb10: + tail call void(...)* @foo4() + ret void +bb11: + tail call void(...)* @foo5() + ret void +bb12: + tail call void(...)* @foo6() + ret void +} + +declare void @foo1(...) +declare void @foo2(...) +declare void @foo6(...) +declare void @foo3(...) +declare void @foo4(...) +declare void @foo5(...) From resistor at mac.com Wed Jun 24 19:04:23 2009 From: resistor at mac.com (Owen Anderson) Date: Thu, 25 Jun 2009 00:04:23 -0000 Subject: [llvm-commits] [llvm] r74143 - in /llvm/trunk: include/llvm/CodeGen/IntrinsicLowering.h lib/CodeGen/IntrinsicLowering.cpp Message-ID: <200906250004.n5P04PtK008245@zion.cs.uiuc.edu> Author: resistor Date: Wed Jun 24 19:04:15 2009 New Revision: 74143 URL: http://llvm.org/viewvc/llvm-project?rev=74143&view=rev Log: Now with EVEN FEWER statics! Modified: llvm/trunk/include/llvm/CodeGen/IntrinsicLowering.h llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/IntrinsicLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/IntrinsicLowering.h?rev=74143&r1=74142&r2=74143&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/IntrinsicLowering.h (original) +++ llvm/trunk/include/llvm/CodeGen/IntrinsicLowering.h Wed Jun 24 19:04:15 2009 @@ -25,8 +25,45 @@ class IntrinsicLowering { const TargetData& TD; + + Constant *SetjmpFCache; + Constant *LongjmpFCache; + Constant *AbortFCache; + Constant *MemcpyFCache; + Constant *MemmoveFCache; + Constant *MemsetFCache; + Constant *sqrtFCache; + Constant *sqrtDCache; + Constant *sqrtLDCache; + Constant *logFCache; + Constant *logDCache; + Constant *logLDCache; + Constant *log2FCache; + Constant *log2DCache; + Constant *log2LDCache; + Constant *log10FCache; + Constant *log10DCache; + Constant *log10LDCache; + Constant *expFCache; + Constant *expDCache; + Constant *expLDCache; + Constant *exp2FCache; + Constant *exp2DCache; + Constant *exp2LDCache; + Constant *powFCache; + Constant *powDCache; + Constant *powLDCache; + + bool Warned; public: - explicit IntrinsicLowering(const TargetData &td) : TD(td) {} + explicit IntrinsicLowering(const TargetData &td) : + TD(td), SetjmpFCache(0), LongjmpFCache(0), AbortFCache(0), + MemcpyFCache(0), MemmoveFCache(0), MemsetFCache(0), sqrtFCache(0), + sqrtDCache(0), sqrtLDCache(0), logFCache(0), logDCache(0), logLDCache(0), + log2FCache(0), log2DCache(0), log2LDCache(0), log10FCache(0), + log10DCache(0), log10LDCache(0), expFCache(0), expDCache(0), + expLDCache(0), exp2FCache(0), exp2DCache(0), exp2LDCache(0), powFCache(0), + powDCache(0), powLDCache(0), Warned(false) {} /// AddPrototypes - This method, if called, causes all of the prototypes /// that might be needed by an intrinsic lowering implementation to be Modified: llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp?rev=74143&r1=74142&r2=74143&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp Wed Jun 24 19:04:15 2009 @@ -668,7 +668,6 @@ // by the lowerinvoke pass. In both cases, the right thing to do is to // convert the call to an explicit setjmp or longjmp call. case Intrinsic::setjmp: { - static Constant *SetjmpFCache = 0; Value *V = ReplaceCallWith("setjmp", CI, CI->op_begin() + 1, CI->op_end(), Type::Int32Ty, SetjmpFCache); if (CI->getType() != Type::VoidTy) @@ -681,7 +680,6 @@ break; case Intrinsic::longjmp: { - static Constant *LongjmpFCache = 0; ReplaceCallWith("longjmp", CI, CI->op_begin() + 1, CI->op_end(), Type::VoidTy, LongjmpFCache); break; @@ -689,7 +687,6 @@ case Intrinsic::siglongjmp: { // Insert the call to abort - static Constant *AbortFCache = 0; ReplaceCallWith("abort", CI, CI->op_end(), CI->op_end(), Type::VoidTy, AbortFCache); break; @@ -728,7 +725,6 @@ case Intrinsic::stacksave: case Intrinsic::stackrestore: { - static bool Warned = false; if (!Warned) cerr << "WARNING: this target does not support the llvm.stack" << (Callee->getIntrinsicID() == Intrinsic::stacksave ? @@ -783,7 +779,6 @@ break; // Strip out annotate intrinsic case Intrinsic::memcpy: { - static Constant *MemcpyFCache = 0; const IntegerType *IntPtr = TD.getIntPtrType(); Value *Size = Builder.CreateIntCast(CI->getOperand(3), IntPtr, /* isSigned */ false); @@ -796,7 +791,6 @@ break; } case Intrinsic::memmove: { - static Constant *MemmoveFCache = 0; const IntegerType *IntPtr = TD.getIntPtrType(); Value *Size = Builder.CreateIntCast(CI->getOperand(3), IntPtr, /* isSigned */ false); @@ -809,7 +803,6 @@ break; } case Intrinsic::memset: { - static Constant *MemsetFCache = 0; const IntegerType *IntPtr = TD.getIntPtrType(); Value *Size = Builder.CreateIntCast(CI->getOperand(3), IntPtr, /* isSigned */ false); @@ -824,57 +817,36 @@ break; } case Intrinsic::sqrt: { - static Constant *sqrtFCache = 0; - static Constant *sqrtDCache = 0; - static Constant *sqrtLDCache = 0; ReplaceFPIntrinsicWithCall(CI, sqrtFCache, sqrtDCache, sqrtLDCache, "sqrtf", "sqrt", "sqrtl"); break; } case Intrinsic::log: { - static Constant *logFCache = 0; - static Constant *logDCache = 0; - static Constant *logLDCache = 0; ReplaceFPIntrinsicWithCall(CI, logFCache, logDCache, logLDCache, "logf", "log", "logl"); break; } case Intrinsic::log2: { - static Constant *log2FCache = 0; - static Constant *log2DCache = 0; - static Constant *log2LDCache = 0; ReplaceFPIntrinsicWithCall(CI, log2FCache, log2DCache, log2LDCache, "log2f", "log2", "log2l"); break; } case Intrinsic::log10: { - static Constant *log10FCache = 0; - static Constant *log10DCache = 0; - static Constant *log10LDCache = 0; ReplaceFPIntrinsicWithCall(CI, log10FCache, log10DCache, log10LDCache, "log10f", "log10", "log10l"); break; } case Intrinsic::exp: { - static Constant *expFCache = 0; - static Constant *expDCache = 0; - static Constant *expLDCache = 0; ReplaceFPIntrinsicWithCall(CI, expFCache, expDCache, expLDCache, "expf", "exp", "expl"); break; } case Intrinsic::exp2: { - static Constant *exp2FCache = 0; - static Constant *exp2DCache = 0; - static Constant *exp2LDCache = 0; ReplaceFPIntrinsicWithCall(CI, exp2FCache, exp2DCache, exp2LDCache, "exp2f", "exp2", "exp2l"); break; } case Intrinsic::pow: { - static Constant *powFCache = 0; - static Constant *powDCache = 0; - static Constant *powLDCache = 0; ReplaceFPIntrinsicWithCall(CI, powFCache, powDCache, powLDCache, "powf", "pow", "powl"); break; From gohman at apple.com Wed Jun 24 19:09:57 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 25 Jun 2009 00:09:57 -0000 Subject: [llvm-commits] [llvm] r74145 - /llvm/trunk/include/llvm/Analysis/LoopInfo.h Message-ID: <200906250009.n5P09ws1008470@zion.cs.uiuc.edu> Author: djg Date: Wed Jun 24 19:09:57 2009 New Revision: 74145 URL: http://llvm.org/viewvc/llvm-project?rev=74145&view=rev Log: Add a getUniqueExitBlock utility function, similar to getExitBlock, but for getUniqueExitBlocks. Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=74145&r1=74144&r2=74145&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Wed Jun 24 19:09:57 2009 @@ -281,6 +281,16 @@ } } + /// getUniqueExitBlock - If getUniqueExitBlocks would return exactly one + /// block, return that block. Otherwise return null. + BlockT *getUniqueExitBlock() const { + SmallVector UniqueExitBlocks; + getUniqueExitBlocks(UniqueExitBlocks); + if (UniqueExitBlocks.size() == 1) + return UniqueExitBlocks[0]; + return 0; + } + /// getLoopPreheader - If there is a preheader for this loop, return it. A /// loop has a preheader if there is only one edge to the header of the loop /// from outside of the loop. If this is the case, the block branching to the From gohman at apple.com Wed Jun 24 19:22:45 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 25 Jun 2009 00:22:45 -0000 Subject: [llvm-commits] [llvm] r74146 - /llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Message-ID: <200906250022.n5P0MjbA008875@zion.cs.uiuc.edu> Author: djg Date: Wed Jun 24 19:22:44 2009 New Revision: 74146 URL: http://llvm.org/viewvc/llvm-project?rev=74146&view=rev Log: Reword a few comments. Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp?rev=74146&r1=74145&r2=74146&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Wed Jun 24 19:22:44 2009 @@ -108,7 +108,7 @@ Pass *llvm::createLoopRotatePass() { return new LoopRotate(); } /// Rotate Loop L as many times as possible. Return true if -/// loop is rotated at least once. +/// the loop is rotated at least once. bool LoopRotate::runOnLoop(Loop *Lp, LPPassManager &LPM) { bool RotatedOneLoop = false; @@ -132,15 +132,15 @@ OrigPreHeader = L->getLoopPreheader(); OrigLatch = L->getLoopLatch(); - // If loop has only one block then there is not much to rotate. + // If the loop has only one block then there is not much to rotate. if (L->getBlocks().size() == 1) return false; assert(OrigHeader && OrigLatch && OrigPreHeader && "Loop is not in canonical form"); - // If loop header is not one of the loop exit block then - // either this loop is already rotated or it is not + // If the loop header is not one of the loop exiting blocks then + // either this loop is already rotated or it is not // suitable for loop rotation transformations. if (!L->isLoopExit(OrigHeader)) return false; @@ -189,19 +189,19 @@ assert(L->contains(NewHeader) && !L->contains(Exit) && "Unable to determine loop header and exit blocks"); - // This code assumes that new header has exactly one predecessor. Remove any - // single entry PHI nodes in it. + // This code assumes that the new header has exactly one predecessor. + // Remove any single-entry PHI nodes in it. assert(NewHeader->getSinglePredecessor() && "New header doesn't have one pred!"); FoldSingleEntryPHINodes(NewHeader); - // Copy PHI nodes and other instructions from original header - // into original pre-header. Unlike original header, original pre-header is - // not a member of loop. + // Copy PHI nodes and other instructions from the original header + // into the original pre-header. Unlike the original header, the original + // pre-header is not a member of the loop. // - // New loop header is one and only successor of original header that + // The new loop header is the one and only successor of original header that // is inside the loop. All other original header successors are outside - // the loop. Copy PHI Nodes from original header into new loop header. + // the loop. Copy PHI Nodes from the original header into the new loop header. // Add second incoming value, from original loop pre-header into these phi // nodes. If a value defined in original header is used outside original // header then new loop header will need new phi nodes with two incoming @@ -218,8 +218,8 @@ // are directly propagated. Value *NPV = PN->getIncomingValueForBlock(OrigPreHeader); - // Create new PHI node with two incoming values for NewHeader. - // One incoming value is from OrigLatch (through OrigHeader) and + // Create a new PHI node with two incoming values for NewHeader. + // One incoming value is from OrigLatch (through OrigHeader) and the // second incoming value is from original pre-header. PHINode *NH = PHINode::Create(PN->getType(), PN->getName(), NewHeader->begin()); @@ -334,8 +334,8 @@ // Add second incoming argument from new Pre header. UPhi->addIncoming(ILoopHeaderInfo.PreHeader, OrigPreHeader); } else { - // Used outside Exit block. Create a new PHI node from exit block - // to receive value from ne new header ane pre header. + // Used outside Exit block. Create a new PHI node in the exit block + // to receive the value from the new header and pre-header. PHINode *PN = PHINode::Create(U->getType(), U->getName(), Exit->begin()); PN->addIncoming(ILoopHeaderInfo.PreHeader, OrigPreHeader); @@ -367,8 +367,8 @@ } /// Make sure all Exit block PHINodes have required incoming values. -/// If incoming value is constant or defined outside the loop then -/// PHINode may not have an entry for original pre-header. +/// If an incoming value is constant or defined outside the loop then +/// PHINode may not have an entry for the original pre-header. void LoopRotate::updateExitBlock() { for (BasicBlock::iterator I = Exit->begin(), E = Exit->end(); From isanbard at gmail.com Wed Jun 24 19:32:48 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 25 Jun 2009 00:32:48 -0000 Subject: [llvm-commits] [llvm] r74147 - /llvm/trunk/lib/CodeGen/MachineFunction.cpp Message-ID: <200906250032.n5P0WmTu009237@zion.cs.uiuc.edu> Author: void Date: Wed Jun 24 19:32:48 2009 New Revision: 74147 URL: http://llvm.org/viewvc/llvm-project?rev=74147&view=rev Log: My guess is that RegInfo should only call the Allocator.Deallocator if it's not null. Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=74147&r1=74146&r2=74147&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Wed Jun 24 19:32:48 2009 @@ -124,25 +124,28 @@ MachineFrameInfo(*TM.getFrameInfo()); ConstantPool = new (Allocator.Allocate()) MachineConstantPool(TM.getTargetData()); - + // Set up jump table. const TargetData &TD = *TM.getTargetData(); bool IsPic = TM.getRelocationModel() == Reloc::PIC_; unsigned EntrySize = IsPic ? 4 : TD.getPointerSize(); - unsigned Alignment = IsPic ? TD.getABITypeAlignment(Type::Int32Ty) - : TD.getPointerABIAlignment(); + unsigned TyAlignment = IsPic ? TD.getABITypeAlignment(Type::Int32Ty) + : TD.getPointerABIAlignment(); JumpTableInfo = new (Allocator.Allocate()) - MachineJumpTableInfo(EntrySize, Alignment); + MachineJumpTableInfo(EntrySize, TyAlignment); } MachineFunction::~MachineFunction() { BasicBlocks.clear(); InstructionRecycler.clear(Allocator); BasicBlockRecycler.clear(Allocator); - if (RegInfo) - RegInfo->~MachineRegisterInfo(); Allocator.Deallocate(RegInfo); + if (RegInfo) { + RegInfo->~MachineRegisterInfo(); + Allocator.Deallocate(RegInfo); + } if (MFInfo) { - MFInfo->~MachineFunctionInfo(); Allocator.Deallocate(MFInfo); + MFInfo->~MachineFunctionInfo(); + Allocator.Deallocate(MFInfo); } FrameInfo->~MachineFrameInfo(); Allocator.Deallocate(FrameInfo); ConstantPool->~MachineConstantPool(); Allocator.Deallocate(ConstantPool); From jyasskin at google.com Wed Jun 24 19:43:36 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Wed, 24 Jun 2009 17:43:36 -0700 Subject: [llvm-commits] JITEventListener for eventual profiling and maybe gdb support In-Reply-To: <62DFCB0E-A015-41DF-8D69-BEBFB77D9661@apple.com> References: <62DFCB0E-A015-41DF-8D69-BEBFB77D9661@apple.com> Message-ID: On Wed, Jun 24, 2009 at 2:43 PM, Evan Cheng wrote: > Hi Jeffrey, > > This looks very good. Thanks. Some comments: > > +/// JitSymbolEntry - Each function that is JIT compiled results in > one of these > +/// being added to an array of symbols. ?This indicates the name of > the function > +/// as well as the address range it occupies. ?This allows the client > to map > +/// from a PC value to the name of the function. > +struct JitSymbolEntry { > > A nitpick. Please rename it to "JITSymbolEntry" for naming consistency. Done, although this is just a move. > + > +// This is a public symbol so the performance tools can find it. > +JitSymbolTable *__jitSymbolTable; > + > > Hmm. Is there a better solution? From what I can tell, the event > listener is responsible for allocating symbol table memory so it > effectively owns it. Can we register the address with the performance > tools? We're pushing to be more thread safe. As Eric said, this is just moving existing code, and it's #ifdef'ed out. I'll let the Shark folks invent a better solution. :) > +struct FunctionEmittedEvent { > + ?// Indices are local to the RecordingJITEventListener, since the > + ?// JITEventListener interface makes no guarantees about the order of > + ?// calls between Listeners. > + ?int Index; > > Use "unsigned" instead of "int"? Can index ever be negative? Sure, it's unsigned now. > On Jun 24, 2009, at 1:26 PM, Jeffrey Yasskin wrote: > >> Ack, sorry. I should have sent this to llvm-commits instead. :-P >> Followups there please. >> >> On Wed, Jun 24, 2009 at 12:02 PM, Jeffrey >> Yasskin wrote: >>> I intend to use this to support oprofile's ability to symbolize >>> JITted >>> code through the interface described at >>> http://oprofile.sourceforge.net/doc/devel/jit-interface.html. I >>> believe the interface will also be useful for gdb support. I'm >>> considering adding some flags to the JITEventListener to let the JIT >>> avoid collecting information no listener is going to use, but I won't >>> do that until there's a need. >>> >>> I've added EmittedFunctionDetails in this patch so that I don't have >>> to change the NotifyFunctionEmitted() interface in a future patch. To >>> record line number information, oprofile wants an array of structs of >>> the form: >>> >>> ?struct debug_line_info { >>> ? ? ? unsigned long vma; >>> ? ? ? unsigned int lineno; >>> ? ? ? /* The filename format is unspecified, absolute path, >>> relative etc. */ >>> ? ? ? char const * filename; >>> ?}; >>> >>> so I'll add enough information to produce that to the >>> EmittedFunctionDetails in a later patch. >>> >>> Chris mentioned that someone may want to extend this to fire events >>> on >>> stub emission too. >>> >>> Let me know what you think. >>> Jeffrey >>> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- A non-text attachment was scrubbed... Name: event-listener.patch Type: text/x-diff Size: 34383 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090624/18380581/attachment.bin From dpatel at apple.com Wed Jun 24 19:47:43 2009 From: dpatel at apple.com (Devang Patel) Date: Thu, 25 Jun 2009 00:47:43 -0000 Subject: [llvm-commits] [llvm] r74150 - in /llvm/trunk: lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp test/Feature/mdnode.ll Message-ID: <200906250047.n5P0lhxF009777@zion.cs.uiuc.edu> Author: dpatel Date: Wed Jun 24 19:47:42 2009 New Revision: 74150 URL: http://llvm.org/viewvc/llvm-project?rev=74150&view=rev Log: No need to code gen MDNodes Added: llvm/trunk/test/Feature/mdnode.ll Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Wed Jun 24 19:47:42 2009 @@ -21,6 +21,7 @@ #include "ARMMachineFunctionInfo.h" #include "llvm/Constants.h" #include "llvm/Module.h" +#include "llvm/MDNode.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineModuleInfo.h" @@ -923,6 +924,8 @@ std::string name = Mang->getValueName(GVar); Constant *C = GVar->getInitializer(); + if (isa(C)) + return; const Type *Type = C->getType(); unsigned Size = TD->getTypeAllocSize(Type); unsigned Align = TD->getPreferredAlignmentLog(GVar); Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Wed Jun 24 19:47:42 2009 @@ -17,6 +17,7 @@ #include "AlphaInstrInfo.h" #include "AlphaTargetMachine.h" #include "llvm/Module.h" +#include "llvm/MDNode.h" #include "llvm/Type.h" #include "llvm/Assembly/Writer.h" #include "llvm/CodeGen/AsmPrinter.h" @@ -222,6 +223,8 @@ std::string name = Mang->getValueName(GVar); Constant *C = GVar->getInitializer(); + if (isa(C)) + return; unsigned Size = TD->getTypeAllocSize(C->getType()); unsigned Align = TD->getPreferredAlignmentLog(GVar); Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Wed Jun 24 19:47:42 2009 @@ -19,6 +19,7 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" +#include "llvm/MDNode.h" #include "llvm/Assembly/Writer.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/DwarfWriter.h" @@ -521,6 +522,8 @@ printVisibility(name, GVar->getVisibility()); Constant *C = GVar->getInitializer(); + if (isa(C)) + return; const Type *Type = C->getType(); unsigned Size = TD->getTypeAllocSize(Type); unsigned Align = TD->getPreferredAlignmentLog(GVar); Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Wed Jun 24 19:47:42 2009 @@ -20,6 +20,7 @@ #include "IA64.h" #include "IA64TargetMachine.h" #include "llvm/Module.h" +#include "llvm/MDNode.h" #include "llvm/Type.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/DwarfWriter.h" @@ -269,6 +270,8 @@ O << "\n\n"; std::string name = Mang->getValueName(GVar); Constant *C = GVar->getInitializer(); + if (isa(C)) + return; unsigned Size = TD->getTypeAllocSize(C->getType()); unsigned Align = TD->getPreferredAlignmentLog(GVar); Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Wed Jun 24 19:47:42 2009 @@ -22,6 +22,7 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" +#include "llvm/MDNode.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineFunctionPass.h" @@ -483,6 +484,8 @@ O << "\n\n"; std::string name = Mang->getValueName(GVar); Constant *C = GVar->getInitializer(); + if (isa(C)) + return; const Type *CTy = C->getType(); unsigned Size = TD->getTypeAllocSize(CTy); const ConstantArray *CVA = dyn_cast(C); Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Wed Jun 24 19:47:42 2009 @@ -24,6 +24,7 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" +#include "llvm/MDNode.h" #include "llvm/Assembly/Writer.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/DwarfWriter.h" @@ -656,6 +657,8 @@ printVisibility(name, GVar->getVisibility()); Constant *C = GVar->getInitializer(); + if (isa(C)) + return; const Type *Type = C->getType(); unsigned Size = TD->getTypeAllocSize(Type); unsigned Align = TD->getPreferredAlignmentLog(GVar); Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp Wed Jun 24 19:47:42 2009 @@ -19,6 +19,7 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" +#include "llvm/MDNode.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineFunctionPass.h" @@ -253,6 +254,8 @@ O << "\n\n"; std::string name = Mang->getValueName(GVar); Constant *C = GVar->getInitializer(); + if (isa(C)) + return; unsigned Size = TD->getTypeAllocSize(C->getType()); unsigned Align = TD->getPreferredAlignment(GVar); Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 19:47:42 2009 @@ -23,6 +23,7 @@ #include "llvm/CallingConv.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" +#include "llvm/MDNode.h" #include "llvm/Type.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/StringExtras.h" @@ -974,6 +975,8 @@ std::string name = Mang->getValueName(GVar); Constant *C = GVar->getInitializer(); + if (isa(C)) + return; const Type *Type = C->getType(); unsigned Size = TD->getTypeAllocSize(Type); unsigned Align = TD->getPreferredAlignmentLog(GVar); Added: llvm/trunk/test/Feature/mdnode.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/mdnode.ll?rev=74150&view=auto ============================================================================== --- llvm/trunk/test/Feature/mdnode.ll (added) +++ llvm/trunk/test/Feature/mdnode.ll Wed Jun 24 19:47:42 2009 @@ -0,0 +1,2 @@ +; RUN: llvm-as < %s | llc -f -o /dev/null + at llvm.foo = constant metadata !{i17 123, null, metadata !"foobar"} \ No newline at end of file From evan.cheng at apple.com Wed Jun 24 19:48:01 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 24 Jun 2009 17:48:01 -0700 Subject: [llvm-commits] [LLVMdev] JITEventListener for eventual profiling and maybe gdb support In-Reply-To: References: <62DFCB0E-A015-41DF-8D69-BEBFB77D9661@apple.com> Message-ID: <0AF2D968-A659-4C21-AF19-CECD07F24D59@apple.com> Thanks. Please commit. Owen, just a FYI about __jitSymbolTable. I thought you should care because of your thread safe work. Evan On Jun 24, 2009, at 5:43 PM, Jeffrey Yasskin wrote: > On Wed, Jun 24, 2009 at 2:43 PM, Evan Cheng > wrote: >> Hi Jeffrey, >> >> This looks very good. Thanks. Some comments: >> >> +/// JitSymbolEntry - Each function that is JIT compiled results in >> one of these >> +/// being added to an array of symbols. This indicates the name of >> the function >> +/// as well as the address range it occupies. This allows the >> client >> to map >> +/// from a PC value to the name of the function. >> +struct JitSymbolEntry { >> >> A nitpick. Please rename it to "JITSymbolEntry" for naming >> consistency. > > Done, although this is just a move. > >> + >> +// This is a public symbol so the performance tools can find it. >> +JitSymbolTable *__jitSymbolTable; >> + >> >> Hmm. Is there a better solution? From what I can tell, the event >> listener is responsible for allocating symbol table memory so it >> effectively owns it. Can we register the address with the performance >> tools? We're pushing to be more thread safe. > > As Eric said, this is just moving existing code, and it's #ifdef'ed > out. I'll let the Shark folks invent a better solution. :) > >> +struct FunctionEmittedEvent { >> + // Indices are local to the RecordingJITEventListener, since the >> + // JITEventListener interface makes no guarantees about the >> order of >> + // calls between Listeners. >> + int Index; >> >> Use "unsigned" instead of "int"? Can index ever be negative? > > Sure, it's unsigned now. > >> On Jun 24, 2009, at 1:26 PM, Jeffrey Yasskin wrote: >> >>> Ack, sorry. I should have sent this to llvm-commits instead. :-P >>> Followups there please. >>> >>> On Wed, Jun 24, 2009 at 12:02 PM, Jeffrey >>> Yasskin wrote: >>>> I intend to use this to support oprofile's ability to symbolize >>>> JITted >>>> code through the interface described at >>>> http://oprofile.sourceforge.net/doc/devel/jit-interface.html. I >>>> believe the interface will also be useful for gdb support. I'm >>>> considering adding some flags to the JITEventListener to let the >>>> JIT >>>> avoid collecting information no listener is going to use, but I >>>> won't >>>> do that until there's a need. >>>> >>>> I've added EmittedFunctionDetails in this patch so that I don't >>>> have >>>> to change the NotifyFunctionEmitted() interface in a future >>>> patch. To >>>> record line number information, oprofile wants an array of >>>> structs of >>>> the form: >>>> >>>> struct debug_line_info { >>>> unsigned long vma; >>>> unsigned int lineno; >>>> /* The filename format is unspecified, absolute path, >>>> relative etc. */ >>>> char const * filename; >>>> }; >>>> >>>> so I'll add enough information to produce that to the >>>> EmittedFunctionDetails in a later patch. >>>> >>>> Chris mentioned that someone may want to extend this to fire events >>>> on >>>> stub emission too. >>>> >>>> Let me know what you think. >>>> Jeffrey >>>> >>> >> listener.patch>_______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev From clattner at apple.com Wed Jun 24 19:56:57 2009 From: clattner at apple.com (Chris Lattner) Date: Wed, 24 Jun 2009 17:56:57 -0700 Subject: [llvm-commits] [llvm] r74143 - in /llvm/trunk: include/llvm/CodeGen/IntrinsicLowering.h lib/CodeGen/IntrinsicLowering.cpp In-Reply-To: <200906250004.n5P04PtK008245@zion.cs.uiuc.edu> References: <200906250004.n5P04PtK008245@zion.cs.uiuc.edu> Message-ID: On Jun 24, 2009, at 5:04 PM, Owen Anderson wrote: > Author: resistor > Date: Wed Jun 24 19:04:15 2009 > New Revision: 74143 > > URL: http://llvm.org/viewvc/llvm-project?rev=74143&view=rev > Log: > Now with EVEN FEWER statics! How about just not caching them? This was important when we had "type planes", but now a lookup in the module symbol table is "fast enough" that we don't need a cache. -Chris > > > Modified: > llvm/trunk/include/llvm/CodeGen/IntrinsicLowering.h > llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp > > Modified: llvm/trunk/include/llvm/CodeGen/IntrinsicLowering.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/IntrinsicLowering.h?rev=74143&r1=74142&r2=74143&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/IntrinsicLowering.h (original) > +++ llvm/trunk/include/llvm/CodeGen/IntrinsicLowering.h Wed Jun 24 > 19:04:15 2009 > @@ -25,8 +25,45 @@ > > class IntrinsicLowering { > const TargetData& TD; > + > + Constant *SetjmpFCache; > + Constant *LongjmpFCache; > + Constant *AbortFCache; > + Constant *MemcpyFCache; > + Constant *MemmoveFCache; > + Constant *MemsetFCache; > + Constant *sqrtFCache; > + Constant *sqrtDCache; > + Constant *sqrtLDCache; > + Constant *logFCache; > + Constant *logDCache; > + Constant *logLDCache; > + Constant *log2FCache; > + Constant *log2DCache; > + Constant *log2LDCache; > + Constant *log10FCache; > + Constant *log10DCache; > + Constant *log10LDCache; > + Constant *expFCache; > + Constant *expDCache; > + Constant *expLDCache; > + Constant *exp2FCache; > + Constant *exp2DCache; > + Constant *exp2LDCache; > + Constant *powFCache; > + Constant *powDCache; > + Constant *powLDCache; > + > + bool Warned; > public: > - explicit IntrinsicLowering(const TargetData &td) : TD(td) {} > + explicit IntrinsicLowering(const TargetData &td) : > + TD(td), SetjmpFCache(0), LongjmpFCache(0), AbortFCache(0), > + MemcpyFCache(0), MemmoveFCache(0), MemsetFCache(0), > sqrtFCache(0), > + sqrtDCache(0), sqrtLDCache(0), logFCache(0), logDCache(0), > logLDCache(0), > + log2FCache(0), log2DCache(0), log2LDCache(0), log10FCache(0), > + log10DCache(0), log10LDCache(0), expFCache(0), expDCache(0), > + expLDCache(0), exp2FCache(0), exp2DCache(0), exp2LDCache(0), > powFCache(0), > + powDCache(0), powLDCache(0), Warned(false) {} > > /// AddPrototypes - This method, if called, causes all of the > prototypes > /// that might be needed by an intrinsic lowering implementation > to be > > Modified: llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp?rev=74143&r1=74142&r2=74143&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp (original) > +++ llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp Wed Jun 24 19:04:15 > 2009 > @@ -668,7 +668,6 @@ > // by the lowerinvoke pass. In both cases, the right thing to > do is to > // convert the call to an explicit setjmp or longjmp call. > case Intrinsic::setjmp: { > - static Constant *SetjmpFCache = 0; > Value *V = ReplaceCallWith("setjmp", CI, CI->op_begin() + 1, CI- > >op_end(), > Type::Int32Ty, SetjmpFCache); > if (CI->getType() != Type::VoidTy) > @@ -681,7 +680,6 @@ > break; > > case Intrinsic::longjmp: { > - static Constant *LongjmpFCache = 0; > ReplaceCallWith("longjmp", CI, CI->op_begin() + 1, CI->op_end(), > Type::VoidTy, LongjmpFCache); > break; > @@ -689,7 +687,6 @@ > > case Intrinsic::siglongjmp: { > // Insert the call to abort > - static Constant *AbortFCache = 0; > ReplaceCallWith("abort", CI, CI->op_end(), CI->op_end(), > Type::VoidTy, AbortFCache); > break; > @@ -728,7 +725,6 @@ > > case Intrinsic::stacksave: > case Intrinsic::stackrestore: { > - static bool Warned = false; > if (!Warned) > cerr << "WARNING: this target does not support the llvm.stack" > << (Callee->getIntrinsicID() == Intrinsic::stacksave ? > @@ -783,7 +779,6 @@ > break; // Strip out annotate intrinsic > > case Intrinsic::memcpy: { > - static Constant *MemcpyFCache = 0; > const IntegerType *IntPtr = TD.getIntPtrType(); > Value *Size = Builder.CreateIntCast(CI->getOperand(3), IntPtr, > /* isSigned */ false); > @@ -796,7 +791,6 @@ > break; > } > case Intrinsic::memmove: { > - static Constant *MemmoveFCache = 0; > const IntegerType *IntPtr = TD.getIntPtrType(); > Value *Size = Builder.CreateIntCast(CI->getOperand(3), IntPtr, > /* isSigned */ false); > @@ -809,7 +803,6 @@ > break; > } > case Intrinsic::memset: { > - static Constant *MemsetFCache = 0; > const IntegerType *IntPtr = TD.getIntPtrType(); > Value *Size = Builder.CreateIntCast(CI->getOperand(3), IntPtr, > /* isSigned */ false); > @@ -824,57 +817,36 @@ > break; > } > case Intrinsic::sqrt: { > - static Constant *sqrtFCache = 0; > - static Constant *sqrtDCache = 0; > - static Constant *sqrtLDCache = 0; > ReplaceFPIntrinsicWithCall(CI, sqrtFCache, sqrtDCache, > sqrtLDCache, > "sqrtf", "sqrt", "sqrtl"); > break; > } > case Intrinsic::log: { > - static Constant *logFCache = 0; > - static Constant *logDCache = 0; > - static Constant *logLDCache = 0; > ReplaceFPIntrinsicWithCall(CI, logFCache, logDCache, logLDCache, > "logf", "log", "logl"); > break; > } > case Intrinsic::log2: { > - static Constant *log2FCache = 0; > - static Constant *log2DCache = 0; > - static Constant *log2LDCache = 0; > ReplaceFPIntrinsicWithCall(CI, log2FCache, log2DCache, > log2LDCache, > "log2f", "log2", "log2l"); > break; > } > case Intrinsic::log10: { > - static Constant *log10FCache = 0; > - static Constant *log10DCache = 0; > - static Constant *log10LDCache = 0; > ReplaceFPIntrinsicWithCall(CI, log10FCache, log10DCache, > log10LDCache, > "log10f", "log10", "log10l"); > break; > } > case Intrinsic::exp: { > - static Constant *expFCache = 0; > - static Constant *expDCache = 0; > - static Constant *expLDCache = 0; > ReplaceFPIntrinsicWithCall(CI, expFCache, expDCache, expLDCache, > "expf", "exp", "expl"); > break; > } > case Intrinsic::exp2: { > - static Constant *exp2FCache = 0; > - static Constant *exp2DCache = 0; > - static Constant *exp2LDCache = 0; > ReplaceFPIntrinsicWithCall(CI, exp2FCache, exp2DCache, > exp2LDCache, > "exp2f", "exp2", "exp2l"); > break; > } > case Intrinsic::pow: { > - static Constant *powFCache = 0; > - static Constant *powDCache = 0; > - static Constant *powLDCache = 0; > ReplaceFPIntrinsicWithCall(CI, powFCache, powDCache, powLDCache, > "powf", "pow", "powl"); > break; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Wed Jun 24 20:05:07 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 25 Jun 2009 01:05:07 -0000 Subject: [llvm-commits] [llvm] r74152 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <200906250105.n5P157kv010425@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 24 20:05:06 2009 New Revision: 74152 URL: http://llvm.org/viewvc/llvm-project?rev=74152&view=rev Log: Some reorg and additional comments. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=74152&r1=74151&r2=74152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Jun 24 20:05:06 2009 @@ -132,6 +132,24 @@ "$cp:\n\tadd $dst, pc", [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>; +// PC relative add. +def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), + "add $dst, pc, $rhs * 4", []>; + +// ADD rd, sp, #imm8 +// FIXME: hard code sp? +def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), + "add $dst, $sp, $rhs * 4 @ addrspi", []>; + +// ADD sp, sp, #imm7 +// FIXME: hard code sp? +def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), + "add $dst, $rhs * 4", []>; + +// FIXME: Make use of the following? +// ADD rm, sp, rm +// ADD sp, rm + //===----------------------------------------------------------------------===// // Control Flow Instructions. // @@ -303,15 +321,6 @@ def tADDhirr : T1It<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs), "add $dst, $rhs @ addhirr", []>; -def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), - "add $dst, pc, $rhs * 4", []>; - -def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), - "add $dst, $sp, $rhs * 4 @ addrspi", []>; - -def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), - "add $dst, $rhs * 4", []>; - let isCommutable = 1 in def tAND : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "and $dst, $rhs", From foldr at codedgers.com Wed Jun 24 20:07:00 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Thu, 25 Jun 2009 01:07:00 -0000 Subject: [llvm-commits] [llvm] r74153 - in /llvm/trunk: Makefile.rules tools/llvmc/driver/Makefile tools/llvmc/example/Skeleton/Makefile tools/llvmc/example/Skeleton/driver/Makefile tools/llvmc/example/mcc16/Makefile tools/llvmc/example/mcc16/driver/Makefile Message-ID: <200906250107.n5P171XZ010546@zion.cs.uiuc.edu> Author: foldr Date: Wed Jun 24 20:07:00 2009 New Revision: 74153 URL: http://llvm.org/viewvc/llvm-project?rev=74153&view=rev Log: Remove duplication. Factor out common preprocessor-related bits to Makefile.rules. Modified: llvm/trunk/Makefile.rules llvm/trunk/tools/llvmc/driver/Makefile llvm/trunk/tools/llvmc/example/Skeleton/Makefile llvm/trunk/tools/llvmc/example/Skeleton/driver/Makefile llvm/trunk/tools/llvmc/example/mcc16/Makefile llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=74153&r1=74152&r2=74153&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Wed Jun 24 20:07:00 2009 @@ -214,6 +214,49 @@ endif # LLVMC_PLUGIN +ifdef LLVMC_BASED_DRIVER + +TOOLNAME = $(LLVMC_BASED_DRIVER) +LLVMLIBS = CompilerDriver.a +LINK_COMPONENTS = support system +REQUIRES_EH := 1 + +# Preprocessor magic that generates references to static variables in built-in +# plugins. +ifneq ($(LLVMC_BUILTIN_PLUGINS),) + +USEDLIBS += $(patsubst %,plugin_llvmc_%.a,$(LLVMC_BUILTIN_PLUGINS)) + +LLVMC_BUILTIN_PLUGIN_1 = $(word 1, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_2 = $(word 2, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_3 = $(word 3, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_4 = $(word 4, $(LLVMC_BUILTIN_PLUGINS)) +LLVMC_BUILTIN_PLUGIN_5 = $(word 5, $(LLVMC_BUILTIN_PLUGINS)) + +ifneq ($(LLVMC_BUILTIN_PLUGIN_1),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_1=$(LLVMC_BUILTIN_PLUGIN_1) +endif + +ifneq ($(LLVMC_BUILTIN_PLUGIN_2),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_2=$(LLVMC_BUILTIN_PLUGIN_2) +endif + +ifneq ($(LLVMC_BUILTIN_PLUGIN_3),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_3=$(LLVMC_BUILTIN_PLUGIN_3) +endif + +ifneq ($(LLVMC_BUILTIN_PLUGIN_4),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_4=$(LLVMC_BUILTIN_PLUGIN_4) +endif + +ifneq ($(LLVMC_BUILTIN_PLUGIN_5),) +CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_5=$(LLVMC_BUILTIN_PLUGIN_5) +endif + +endif + +endif # LLVMC_BASED_DRIVER + ############################################################################### # VARIABLES: Set up various variables based on configuration data ############################################################################### Modified: llvm/trunk/tools/llvmc/driver/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/driver/Makefile?rev=74153&r1=74152&r2=74153&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/driver/Makefile (original) +++ llvm/trunk/tools/llvmc/driver/Makefile Wed Jun 24 20:07:00 2009 @@ -8,46 +8,6 @@ ##===----------------------------------------------------------------------===## LEVEL = ../../.. -include $(LEVEL)/Makefile.config - -TOOLNAME = $(LLVMC_BASED_DRIVER_NAME) -LLVMLIBS = CompilerDriver.a -LINK_COMPONENTS = support system -REQUIRES_EH := 1 - -# Preprocessor magic that generates references to static variables in built-in -# plugins. -# TODO: Move this to Makefile.rules? (also used by examples/{Skeleton, mcc16}) -ifneq ($(LLVMC_BUILTIN_PLUGINS),) - -USEDLIBS += $(patsubst %,plugin_llvmc_%.a,$(LLVMC_BUILTIN_PLUGINS)) - -LLVMC_BUILTIN_PLUGIN_1 = $(word 1, $(LLVMC_BUILTIN_PLUGINS)) -LLVMC_BUILTIN_PLUGIN_2 = $(word 2, $(LLVMC_BUILTIN_PLUGINS)) -LLVMC_BUILTIN_PLUGIN_3 = $(word 3, $(LLVMC_BUILTIN_PLUGINS)) -LLVMC_BUILTIN_PLUGIN_4 = $(word 4, $(LLVMC_BUILTIN_PLUGINS)) -LLVMC_BUILTIN_PLUGIN_5 = $(word 5, $(LLVMC_BUILTIN_PLUGINS)) - -ifneq ($(LLVMC_BUILTIN_PLUGIN_1),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_1=$(LLVMC_BUILTIN_PLUGIN_1) -endif - -ifneq ($(LLVMC_BUILTIN_PLUGIN_2),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_2=$(LLVMC_BUILTIN_PLUGIN_2) -endif - -ifneq ($(LLVMC_BUILTIN_PLUGIN_3),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_3=$(LLVMC_BUILTIN_PLUGIN_3) -endif - -ifneq ($(LLVMC_BUILTIN_PLUGIN_4),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_4=$(LLVMC_BUILTIN_PLUGIN_4) -endif - -ifneq ($(LLVMC_BUILTIN_PLUGIN_5),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_5=$(LLVMC_BUILTIN_PLUGIN_5) -endif - -endif +LLVMC_BASED_DRIVER = $(LLVMC_BASED_DRIVER_NAME) include $(LEVEL)/Makefile.common Modified: llvm/trunk/tools/llvmc/example/Skeleton/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/Skeleton/Makefile?rev=74153&r1=74152&r2=74153&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/example/Skeleton/Makefile (original) +++ llvm/trunk/tools/llvmc/example/Skeleton/Makefile Wed Jun 24 20:07:00 2009 @@ -8,7 +8,7 @@ ##===----------------------------------------------------------------------===## # Change this so that $(BASE_LEVEL)/Makefile.common refers to -# $LLVM_DIR/Makefile.common. +# $LLVM_DIR/Makefile.common or $YOUR_LLVM_BASED_PROJECT/Makefile.common. export LLVMC_BASE_LEVEL = ../../../.. # Change this to the name of your LLVMC-based driver. Modified: llvm/trunk/tools/llvmc/example/Skeleton/driver/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/Skeleton/driver/Makefile?rev=74153&r1=74152&r2=74153&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/example/Skeleton/driver/Makefile (original) +++ llvm/trunk/tools/llvmc/example/Skeleton/driver/Makefile Wed Jun 24 20:07:00 2009 @@ -8,46 +8,6 @@ ##===----------------------------------------------------------------------===## LEVEL = $(LLVMC_BASE_LEVEL)/.. -include $(LEVEL)/Makefile.config - -TOOLNAME = $(LLVMC_BASED_DRIVER_NAME) -LLVMLIBS = CompilerDriver.a -LINK_COMPONENTS = support system -REQUIRES_EH := 1 - -# Preprocessor magic that generates references to static variables in built-in -# plugins. -# TODO: Move this to Makefile.rules? (also used by examples/{Skeleton, mcc16}) -ifneq ($(LLVMC_BUILTIN_PLUGINS),) - -USEDLIBS += $(patsubst %,plugin_llvmc_%.a,$(LLVMC_BUILTIN_PLUGINS)) - -LLVMC_BUILTIN_PLUGIN_1 = $(word 1, $(LLVMC_BUILTIN_PLUGINS)) -LLVMC_BUILTIN_PLUGIN_2 = $(word 2, $(LLVMC_BUILTIN_PLUGINS)) -LLVMC_BUILTIN_PLUGIN_3 = $(word 3, $(LLVMC_BUILTIN_PLUGINS)) -LLVMC_BUILTIN_PLUGIN_4 = $(word 4, $(LLVMC_BUILTIN_PLUGINS)) -LLVMC_BUILTIN_PLUGIN_5 = $(word 5, $(LLVMC_BUILTIN_PLUGINS)) - -ifneq ($(LLVMC_BUILTIN_PLUGIN_1),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_1=$(LLVMC_BUILTIN_PLUGIN_1) -endif - -ifneq ($(LLVMC_BUILTIN_PLUGIN_2),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_2=$(LLVMC_BUILTIN_PLUGIN_2) -endif - -ifneq ($(LLVMC_BUILTIN_PLUGIN_3),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_3=$(LLVMC_BUILTIN_PLUGIN_3) -endif - -ifneq ($(LLVMC_BUILTIN_PLUGIN_4),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_4=$(LLVMC_BUILTIN_PLUGIN_4) -endif - -ifneq ($(LLVMC_BUILTIN_PLUGIN_5),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_5=$(LLVMC_BUILTIN_PLUGIN_5) -endif - -endif +LLVMC_BASED_DRIVER = $(LLVMC_BASED_DRIVER_NAME) include $(LEVEL)/Makefile.common Modified: llvm/trunk/tools/llvmc/example/mcc16/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/mcc16/Makefile?rev=74153&r1=74152&r2=74153&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/example/mcc16/Makefile (original) +++ llvm/trunk/tools/llvmc/example/mcc16/Makefile Wed Jun 24 20:07:00 2009 @@ -7,14 +7,8 @@ # ##===----------------------------------------------------------------------===## -# Change this so that $(BASE_LEVEL)/Makefile.common refers to -# $LLVM_DIR/Makefile.common. export LLVMC_BASE_LEVEL = ../../../.. - -# Change this to the name of your LLVMC-based driver. export LLVMC_BASED_DRIVER_NAME = mcc16 - -# List your plugin names here export LLVMC_BUILTIN_PLUGINS = PIC16Base LEVEL = $(LLVMC_BASE_LEVEL) Modified: llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile?rev=74153&r1=74152&r2=74153&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile (original) +++ llvm/trunk/tools/llvmc/example/mcc16/driver/Makefile Wed Jun 24 20:07:00 2009 @@ -8,46 +8,6 @@ ##===----------------------------------------------------------------------===## LEVEL = $(LLVMC_BASE_LEVEL)/.. -include $(LEVEL)/Makefile.config - -TOOLNAME = $(LLVMC_BASED_DRIVER_NAME) -LLVMLIBS = CompilerDriver.a -LINK_COMPONENTS = support system -REQUIRES_EH := 1 - -# Preprocessor magic that generates references to static variables in built-in -# plugins. -# TODO: Move this to Makefile.rules? (also used by examples/{Skeleton, mcc16}) -ifneq ($(LLVMC_BUILTIN_PLUGINS),) - -USEDLIBS += $(patsubst %,plugin_llvmc_%.a,$(LLVMC_BUILTIN_PLUGINS)) - -LLVMC_BUILTIN_PLUGIN_1 = $(word 1, $(LLVMC_BUILTIN_PLUGINS)) -LLVMC_BUILTIN_PLUGIN_2 = $(word 2, $(LLVMC_BUILTIN_PLUGINS)) -LLVMC_BUILTIN_PLUGIN_3 = $(word 3, $(LLVMC_BUILTIN_PLUGINS)) -LLVMC_BUILTIN_PLUGIN_4 = $(word 4, $(LLVMC_BUILTIN_PLUGINS)) -LLVMC_BUILTIN_PLUGIN_5 = $(word 5, $(LLVMC_BUILTIN_PLUGINS)) - -ifneq ($(LLVMC_BUILTIN_PLUGIN_1),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_1=$(LLVMC_BUILTIN_PLUGIN_1) -endif - -ifneq ($(LLVMC_BUILTIN_PLUGIN_2),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_2=$(LLVMC_BUILTIN_PLUGIN_2) -endif - -ifneq ($(LLVMC_BUILTIN_PLUGIN_3),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_3=$(LLVMC_BUILTIN_PLUGIN_3) -endif - -ifneq ($(LLVMC_BUILTIN_PLUGIN_4),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_4=$(LLVMC_BUILTIN_PLUGIN_4) -endif - -ifneq ($(LLVMC_BUILTIN_PLUGIN_5),) -CPP.Flags += -DLLVMC_BUILTIN_PLUGIN_5=$(LLVMC_BUILTIN_PLUGIN_5) -endif - -endif +LLVMC_BASED_DRIVER = $(LLVMC_BASED_DRIVER_NAME) include $(LEVEL)/Makefile.common From nlewycky at google.com Wed Jun 24 20:14:36 2009 From: nlewycky at google.com (Nick Lewycky) Date: Wed, 24 Jun 2009 18:14:36 -0700 Subject: [llvm-commits] [llvm] r74150 - in /llvm/trunk: lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp lib/Target/Mi Message-ID: 2009/6/24 Devang Patel > Author: dpatel > Date: Wed Jun 24 19:47:42 2009 > New Revision: 74150 > > URL: http://llvm.org/viewvc/llvm-project?rev=74150&view=rev > Log: > > No need to code gen MDNodes Hi Devang, thanks for working on this! We probably also don't want to codegen MDStrings either. Nick Added: > llvm/trunk/test/Feature/mdnode.ll > Modified: > llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp > llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp > llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp > llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp > llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp > llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp > llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp > llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp > > Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff > > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Wed Jun 24 > 19:47:42 2009 > @@ -21,6 +21,7 @@ > #include "ARMMachineFunctionInfo.h" > #include "llvm/Constants.h" > #include "llvm/Module.h" > +#include "llvm/MDNode.h" > #include "llvm/CodeGen/AsmPrinter.h" > #include "llvm/CodeGen/DwarfWriter.h" > #include "llvm/CodeGen/MachineModuleInfo.h" > @@ -923,6 +924,8 @@ > > std::string name = Mang->getValueName(GVar); > Constant *C = GVar->getInitializer(); > + if (isa(C)) > + return; > const Type *Type = C->getType(); > unsigned Size = TD->getTypeAllocSize(Type); > unsigned Align = TD->getPreferredAlignmentLog(GVar); > > Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff > > > ============================================================================== > --- llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp Wed Jun 24 > 19:47:42 2009 > @@ -17,6 +17,7 @@ > #include "AlphaInstrInfo.h" > #include "AlphaTargetMachine.h" > #include "llvm/Module.h" > +#include "llvm/MDNode.h" > #include "llvm/Type.h" > #include "llvm/Assembly/Writer.h" > #include "llvm/CodeGen/AsmPrinter.h" > @@ -222,6 +223,8 @@ > > std::string name = Mang->getValueName(GVar); > Constant *C = GVar->getInitializer(); > + if (isa(C)) > + return; > unsigned Size = TD->getTypeAllocSize(C->getType()); > unsigned Align = TD->getPreferredAlignmentLog(GVar); > > > Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff > > > ============================================================================== > --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Wed Jun 24 > 19:47:42 2009 > @@ -19,6 +19,7 @@ > #include "llvm/Constants.h" > #include "llvm/DerivedTypes.h" > #include "llvm/Module.h" > +#include "llvm/MDNode.h" > #include "llvm/Assembly/Writer.h" > #include "llvm/CodeGen/AsmPrinter.h" > #include "llvm/CodeGen/DwarfWriter.h" > @@ -521,6 +522,8 @@ > printVisibility(name, GVar->getVisibility()); > > Constant *C = GVar->getInitializer(); > + if (isa(C)) > + return; > const Type *Type = C->getType(); > unsigned Size = TD->getTypeAllocSize(Type); > unsigned Align = TD->getPreferredAlignmentLog(GVar); > > Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff > > > ============================================================================== > --- llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp Wed Jun 24 > 19:47:42 2009 > @@ -20,6 +20,7 @@ > #include "IA64.h" > #include "IA64TargetMachine.h" > #include "llvm/Module.h" > +#include "llvm/MDNode.h" > #include "llvm/Type.h" > #include "llvm/CodeGen/AsmPrinter.h" > #include "llvm/CodeGen/DwarfWriter.h" > @@ -269,6 +270,8 @@ > O << "\n\n"; > std::string name = Mang->getValueName(GVar); > Constant *C = GVar->getInitializer(); > + if (isa(C)) > + return; > unsigned Size = TD->getTypeAllocSize(C->getType()); > unsigned Align = TD->getPreferredAlignmentLog(GVar); > > > Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff > > > ============================================================================== > --- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Wed Jun 24 > 19:47:42 2009 > @@ -22,6 +22,7 @@ > #include "llvm/Constants.h" > #include "llvm/DerivedTypes.h" > #include "llvm/Module.h" > +#include "llvm/MDNode.h" > #include "llvm/CodeGen/AsmPrinter.h" > #include "llvm/CodeGen/DwarfWriter.h" > #include "llvm/CodeGen/MachineFunctionPass.h" > @@ -483,6 +484,8 @@ > O << "\n\n"; > std::string name = Mang->getValueName(GVar); > Constant *C = GVar->getInitializer(); > + if (isa(C)) > + return; > const Type *CTy = C->getType(); > unsigned Size = TD->getTypeAllocSize(CTy); > const ConstantArray *CVA = dyn_cast(C); > > Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff > > > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Wed Jun 24 > 19:47:42 2009 > @@ -24,6 +24,7 @@ > #include "llvm/Constants.h" > #include "llvm/DerivedTypes.h" > #include "llvm/Module.h" > +#include "llvm/MDNode.h" > #include "llvm/Assembly/Writer.h" > #include "llvm/CodeGen/AsmPrinter.h" > #include "llvm/CodeGen/DwarfWriter.h" > @@ -656,6 +657,8 @@ > printVisibility(name, GVar->getVisibility()); > > Constant *C = GVar->getInitializer(); > + if (isa(C)) > + return; > const Type *Type = C->getType(); > unsigned Size = TD->getTypeAllocSize(Type); > unsigned Align = TD->getPreferredAlignmentLog(GVar); > > Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff > > > ============================================================================== > --- llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp Wed Jun 24 > 19:47:42 2009 > @@ -19,6 +19,7 @@ > #include "llvm/Constants.h" > #include "llvm/DerivedTypes.h" > #include "llvm/Module.h" > +#include "llvm/MDNode.h" > #include "llvm/CodeGen/AsmPrinter.h" > #include "llvm/CodeGen/DwarfWriter.h" > #include "llvm/CodeGen/MachineFunctionPass.h" > @@ -253,6 +254,8 @@ > O << "\n\n"; > std::string name = Mang->getValueName(GVar); > Constant *C = GVar->getInitializer(); > + if (isa(C)) > + return; > unsigned Size = TD->getTypeAllocSize(C->getType()); > unsigned Align = TD->getPreferredAlignment(GVar); > > > Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74150&r1=74149&r2=74150&view=diff > > > ============================================================================== > --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 > 19:47:42 2009 > @@ -23,6 +23,7 @@ > #include "llvm/CallingConv.h" > #include "llvm/DerivedTypes.h" > #include "llvm/Module.h" > +#include "llvm/MDNode.h" > #include "llvm/Type.h" > #include "llvm/ADT/Statistic.h" > #include "llvm/ADT/StringExtras.h" > @@ -974,6 +975,8 @@ > > std::string name = Mang->getValueName(GVar); > Constant *C = GVar->getInitializer(); > + if (isa(C)) > + return; > const Type *Type = C->getType(); > unsigned Size = TD->getTypeAllocSize(Type); > unsigned Align = TD->getPreferredAlignmentLog(GVar); > > Added: llvm/trunk/test/Feature/mdnode.ll > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/mdnode.ll?rev=74150&view=auto > > > ============================================================================== > --- llvm/trunk/test/Feature/mdnode.ll (added) > +++ llvm/trunk/test/Feature/mdnode.ll Wed Jun 24 19:47:42 2009 > @@ -0,0 +1,2 @@ > +; RUN: llvm-as < %s | llc -f -o /dev/null > + at llvm.foo = constant metadata !{i17 123, null, metadata !"foobar"} > \ No newline at end of file > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090624/bad50463/attachment.html From sabre at nondot.org Wed Jun 24 20:15:49 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 25 Jun 2009 01:15:49 -0000 Subject: [llvm-commits] [llvm] r74154 - /llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Message-ID: <200906250115.n5P1Fn4M010838@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 20:15:47 2009 New Revision: 74154 URL: http://llvm.org/viewvc/llvm-project?rev=74154&view=rev Log: fix comments to be correct. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74154&r1=74153&r2=74154&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Wed Jun 24 20:15:47 2009 @@ -415,7 +415,7 @@ // call .piclabel // piclabel: // popl %some_register - // addl $_GLOBAL_ADDRESS_TABLE_ + [.-piclabel], %some_register + // addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register O << " + [.-"; PrintPICBaseSymbol(); O << ']'; @@ -643,7 +643,7 @@ // call .piclabel // piclabel: // popl %some_register - // addl $_GLOBAL_ADDRESS_TABLE_ + [.-piclabel], %some_register + // addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register O << " + [.-"; PrintPICBaseSymbol(); O << ']'; From sabre at nondot.org Wed Jun 24 20:16:23 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 25 Jun 2009 01:16:23 -0000 Subject: [llvm-commits] [llvm] r74155 - in /llvm/trunk/include/llvm/CodeGen: MachineInstrBuilder.h MachineOperand.h Message-ID: <200906250116.n5P1GNvZ010870@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 20:16:22 2009 New Revision: 74155 URL: http://llvm.org/viewvc/llvm-project?rev=74155&view=rev Log: ad MachineInstrBuilder support for target flags on operands. Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h llvm/trunk/include/llvm/CodeGen/MachineOperand.h Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=74155&r1=74154&r2=74155&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Wed Jun 24 20:16:22 2009 @@ -74,8 +74,9 @@ return *this; } - const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB) const { - MI->addOperand(MachineOperand::CreateMBB(MBB)); + const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB, + unsigned char TargetFlags = 0) const { + MI->addOperand(MachineOperand::CreateMBB(MBB, TargetFlags)); return *this; } @@ -85,25 +86,29 @@ } const MachineInstrBuilder &addConstantPoolIndex(unsigned Idx, - int Offset = 0) const { - MI->addOperand(MachineOperand::CreateCPI(Idx, Offset)); + int Offset = 0, + unsigned char TargetFlags = 0) const { + MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, TargetFlags)); return *this; } - const MachineInstrBuilder &addJumpTableIndex(unsigned Idx) const { - MI->addOperand(MachineOperand::CreateJTI(Idx)); + const MachineInstrBuilder &addJumpTableIndex(unsigned Idx, + unsigned char TargetFlags = 0) const { + MI->addOperand(MachineOperand::CreateJTI(Idx, TargetFlags)); return *this; } const MachineInstrBuilder &addGlobalAddress(GlobalValue *GV, - int64_t Offset = 0) const { - MI->addOperand(MachineOperand::CreateGA(GV, Offset)); + int64_t Offset = 0, + unsigned char TargetFlags = 0) const { + MI->addOperand(MachineOperand::CreateGA(GV, Offset, TargetFlags)); return *this; } const MachineInstrBuilder &addExternalSymbol(const char *FnName, - int64_t Offset = 0) const { - MI->addOperand(MachineOperand::CreateES(FnName, Offset)); + int64_t Offset = 0, + unsigned char TargetFlags = 0) const { + MI->addOperand(MachineOperand::CreateES(FnName, Offset, TargetFlags)); return *this; } @@ -126,13 +131,17 @@ if (MO.isFI()) return addFrameIndex(MO.getIndex()); if (MO.isGlobal()) - return addGlobalAddress(MO.getGlobal(), MO.getOffset()); + return addGlobalAddress(MO.getGlobal(), MO.getOffset(), + MO.getTargetFlags()); if (MO.isCPI()) - return addConstantPoolIndex(MO.getIndex(), MO.getOffset()); + return addConstantPoolIndex(MO.getIndex(), MO.getOffset(), + MO.getTargetFlags()); if (MO.isSymbol()) - return addExternalSymbol(MO.getSymbolName()); + return addExternalSymbol(MO.getSymbolName(), MO.getOffset(), + MO.getTargetFlags()); if (MO.isJTI()) - return addJumpTableIndex(MO.getIndex()); + return addJumpTableIndex(MO.getIndex(), + MO.getTargetFlags()); assert(0 && "Unknown operand for MachineInstrBuilder::AddOperand!"); return *this; Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=74155&r1=74154&r2=74155&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Wed Jun 24 20:16:22 2009 @@ -371,9 +371,11 @@ Op.SubReg = SubReg; return Op; } - static MachineOperand CreateMBB(MachineBasicBlock *MBB) { + static MachineOperand CreateMBB(MachineBasicBlock *MBB, + unsigned char TargetFlags = 0) { MachineOperand Op(MachineOperand::MO_MachineBasicBlock); Op.setMBB(MBB); + Op.setTargetFlags(TargetFlags); return Op; } static MachineOperand CreateFI(unsigned Idx) { @@ -381,27 +383,35 @@ Op.setIndex(Idx); return Op; } - static MachineOperand CreateCPI(unsigned Idx, int Offset) { + static MachineOperand CreateCPI(unsigned Idx, int Offset, + unsigned char TargetFlags = 0) { MachineOperand Op(MachineOperand::MO_ConstantPoolIndex); Op.setIndex(Idx); Op.setOffset(Offset); + Op.setTargetFlags(TargetFlags); return Op; } - static MachineOperand CreateJTI(unsigned Idx) { + static MachineOperand CreateJTI(unsigned Idx, + unsigned char TargetFlags = 0) { MachineOperand Op(MachineOperand::MO_JumpTableIndex); Op.setIndex(Idx); + Op.setTargetFlags(TargetFlags); return Op; } - static MachineOperand CreateGA(GlobalValue *GV, int64_t Offset) { + static MachineOperand CreateGA(GlobalValue *GV, int64_t Offset, + unsigned char TargetFlags = 0) { MachineOperand Op(MachineOperand::MO_GlobalAddress); Op.Contents.OffsetedInfo.Val.GV = GV; Op.setOffset(Offset); + Op.setTargetFlags(TargetFlags); return Op; } - static MachineOperand CreateES(const char *SymName, int64_t Offset = 0) { + static MachineOperand CreateES(const char *SymName, int64_t Offset = 0, + unsigned char TargetFlags = 0) { MachineOperand Op(MachineOperand::MO_ExternalSymbol); Op.Contents.OffsetedInfo.Val.SymbolName = SymName; Op.setOffset(Offset); + Op.setTargetFlags(TargetFlags); return Op; } const MachineOperand &operator=(const MachineOperand &MO) { From evan.cheng at apple.com Wed Jun 24 20:21:30 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 25 Jun 2009 01:21:30 -0000 Subject: [llvm-commits] [llvm] r74156 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <200906250121.n5P1LV7m011024@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 24 20:21:30 2009 New Revision: 74156 URL: http://llvm.org/viewvc/llvm-project?rev=74156&view=rev Log: Add thumb2 add sp. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=74156&r1=74155&r2=74156&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jun 24 20:21:30 2009 @@ -341,6 +341,21 @@ "add$p $dst, pc, #PCRELV${:uid}")), []>; +// ADD rd, sp, #so_imm +def t2ADDrSPi : T2I<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), + "add $dst, $sp, $imm", + []>; + +// ADD rd, sp, #imm12 +def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm), + "addw $dst, $sp, $imm", + []>; + +def t2ADDrSPs : T2I<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), + "addw $dst, $sp, $rhs", + []>; + + //===----------------------------------------------------------------------===// // Arithmetic Instructions. // From jyasskin at google.com Wed Jun 24 21:04:05 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Thu, 25 Jun 2009 02:04:05 -0000 Subject: [llvm-commits] [llvm] r74157 - in /llvm/trunk: include/llvm/ExecutionEngine/ExecutionEngine.h include/llvm/ExecutionEngine/JITEventListener.h lib/ExecutionEngine/JIT/JIT.cpp lib/ExecutionEngine/JIT/JIT.h lib/ExecutionEngine/JIT/JITEmitter.cpp lib/ExecutionEngine/JIT/MacOSJITEventListener.cpp tools/lli/lli.cpp unittests/ExecutionEngine/ unittests/ExecutionEngine/JIT/ unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp unittests/ExecutionEngine/JIT/Makefile unittests/ExecutionEngine/Makefile unittests/Makefile Message-ID: <200906250204.n5P245aI012330@zion.cs.uiuc.edu> Author: jyasskin Date: Wed Jun 24 21:04:04 2009 New Revision: 74157 URL: http://llvm.org/viewvc/llvm-project?rev=74157&view=rev Log: Add a JITEventListener interface that gets called back when a new function is emitted or the machine code for a function is freed. Chris mentioned that we may also want a notification when a stub is emitted, but that'll be a future change. I intend to use this to tell oprofile where functions are emitted and what lines correspond to what addresses. Added: llvm/trunk/include/llvm/ExecutionEngine/JITEventListener.h llvm/trunk/lib/ExecutionEngine/JIT/MacOSJITEventListener.cpp llvm/trunk/unittests/ExecutionEngine/ llvm/trunk/unittests/ExecutionEngine/JIT/ llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp llvm/trunk/unittests/ExecutionEngine/JIT/Makefile llvm/trunk/unittests/ExecutionEngine/Makefile Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp llvm/trunk/lib/ExecutionEngine/JIT/JIT.h llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp llvm/trunk/tools/lli/lli.cpp llvm/trunk/unittests/Makefile Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h?rev=74157&r1=74156&r2=74157&view=diff ============================================================================== --- llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h (original) +++ llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Wed Jun 24 21:04:04 2009 @@ -29,13 +29,14 @@ class Function; class GlobalVariable; class GlobalValue; +class JITEventListener; +class JITMemoryManager; +class MachineCodeInfo; class Module; class ModuleProvider; +class MutexGuard; class TargetData; class Type; -class MutexGuard; -class JITMemoryManager; -class MachineCodeInfo; class ExecutionEngineState { private: @@ -276,7 +277,14 @@ virtual void *getOrEmitGlobalVariable(const GlobalVariable *GV) { return getPointerToGlobal((GlobalValue*)GV); } - + + /// Registers a listener to be called back on various events within + /// the JIT. See JITEventListener.h for more details. Does not + /// take ownership of the argument. The argument may be NULL, in + /// which case these functions do nothing. + virtual void RegisterJITEventListener(JITEventListener *L) {} + virtual void UnregisterJITEventListener(JITEventListener *L) {} + /// DisableLazyCompilation - If called, the JIT will abort if lazy compilation /// is ever attempted. void DisableLazyCompilation(bool Disabled = true) { Added: llvm/trunk/include/llvm/ExecutionEngine/JITEventListener.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/JITEventListener.h?rev=74157&view=auto ============================================================================== --- llvm/trunk/include/llvm/ExecutionEngine/JITEventListener.h (added) +++ llvm/trunk/include/llvm/ExecutionEngine/JITEventListener.h Wed Jun 24 21:04:04 2009 @@ -0,0 +1,59 @@ +//===- JITEventListener.h - Exposes events from JIT compilation -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the JITEventListener interface, which lets users get +// callbacks when significant events happen during the JIT compilation process. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_EXECUTION_ENGINE_JIT_EVENTLISTENER_H +#define LLVM_EXECUTION_ENGINE_JIT_EVENTLISTENER_H + +#include "llvm/Support/DataTypes.h" + +namespace llvm { +class Function; + +/// Empty for now, but this object will contain all details about the +/// generated machine code that a Listener might care about. +struct JITEvent_EmittedFunctionDetails { +}; + +/// JITEventListener - This interface is used by the JIT to notify clients about +/// significant events during compilation. For example, we could have +/// implementations for profilers and debuggers that need to know where +/// functions have been emitted. +/// +/// Each method defaults to doing nothing, so you only need to override the ones +/// you care about. +class JITEventListener { +public: + JITEventListener() {} + virtual ~JITEventListener(); // Defined in JIT.cpp. + + typedef JITEvent_EmittedFunctionDetails EmittedFunctionDetails; + /// NotifyFunctionEmitted - Called after a function has been successfully + /// emitted to memory. The function still has its MachineFunction attached, + /// if you should happen to need that. + virtual void NotifyFunctionEmitted(const Function &F, + void *Code, size_t Size, + const EmittedFunctionDetails &Details) {} + + /// NotifyFreeingMachineCode - This is called inside of + /// freeMachineCodeForFunction(), after the global mapping is removed, but + /// before the machine code is returned to the allocator. OldPtr is the + /// address of the machine code. + virtual void NotifyFreeingMachineCode(const Function &F, void *OldPtr) {} +}; + +JITEventListener *createMacOSJITEventListener(); + +} // end namespace llvm. + +#endif Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp?rev=74157&r1=74156&r2=74157&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp Wed Jun 24 21:04:04 2009 @@ -20,8 +20,9 @@ #include "llvm/Instructions.h" #include "llvm/ModuleProvider.h" #include "llvm/CodeGen/JITCodeEmitter.h" -#include "llvm/ExecutionEngine/GenericValue.h" #include "llvm/CodeGen/MachineCodeInfo.h" +#include "llvm/ExecutionEngine/GenericValue.h" +#include "llvm/ExecutionEngine/JITEventListener.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetJITInfo.h" @@ -507,6 +508,40 @@ return runFunction(Stub, std::vector()); } +void JIT::RegisterJITEventListener(JITEventListener *L) { + if (L == NULL) + return; + MutexGuard locked(lock); + EventListeners.push_back(L); +} +void JIT::UnregisterJITEventListener(JITEventListener *L) { + if (L == NULL) + return; + MutexGuard locked(lock); + std::vector::reverse_iterator I= + std::find(EventListeners.rbegin(), EventListeners.rend(), L); + if (I != EventListeners.rend()) { + std::swap(*I, EventListeners.back()); + EventListeners.pop_back(); + } +} +void JIT::NotifyFunctionEmitted( + const Function &F, + void *Code, size_t Size, + const JITEvent_EmittedFunctionDetails &Details) { + MutexGuard locked(lock); + for (unsigned I = 0, S = EventListeners.size(); I < S; ++I) { + EventListeners[I]->NotifyFunctionEmitted(F, Code, Size, Details); + } +} + +void JIT::NotifyFreeingMachineCode(const Function &F, void *OldPtr) { + MutexGuard locked(lock); + for (unsigned I = 0, S = EventListeners.size(); I < S; ++I) { + EventListeners[I]->NotifyFreeingMachineCode(F, OldPtr); + } +} + /// runJITOnFunction - Run the FunctionPassManager full of /// just-in-time compilation passes on F, hopefully filling in /// GlobalAddress[F] with the address of F's machine code. @@ -514,11 +549,23 @@ void JIT::runJITOnFunction(Function *F, MachineCodeInfo *MCI) { MutexGuard locked(lock); - registerMachineCodeInfo(MCI); + class MCIListener : public JITEventListener { + MachineCodeInfo *const MCI; + public: + MCIListener(MachineCodeInfo *mci) : MCI(mci) {} + virtual void NotifyFunctionEmitted(const Function &, + void *Code, size_t Size, + const EmittedFunctionDetails &) { + MCI->setAddress(Code); + MCI->setSize(Size); + } + }; + MCIListener MCIL(MCI); + RegisterJITEventListener(&MCIL); runJITOnFunctionUnlocked(F, locked); - registerMachineCodeInfo(0); + UnregisterJITEventListener(&MCIL); } void JIT::runJITOnFunctionUnlocked(Function *F, const MutexGuard &locked) { @@ -709,3 +756,6 @@ MutexGuard locked(lock); jitstate->getPendingFunctions(locked).push_back(F); } + + +JITEventListener::~JITEventListener() {} Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.h?rev=74157&r1=74156&r2=74157&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.h (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.h Wed Jun 24 21:04:04 2009 @@ -20,10 +20,11 @@ namespace llvm { class Function; -class TargetMachine; -class TargetJITInfo; +class JITEvent_EmittedFunctionDetails; class MachineCodeEmitter; class MachineCodeInfo; +class TargetJITInfo; +class TargetMachine; class JITState { private: @@ -52,6 +53,7 @@ TargetMachine &TM; // The current target we are compiling to TargetJITInfo &TJI; // The JITInfo for the target we are compiling to JITCodeEmitter *JCE; // JCE object + std::vector EventListeners; JITState *jitstate; @@ -157,9 +159,18 @@ // Run the JIT on F and return information about the generated code void runJITOnFunction(Function *F, MachineCodeInfo *MCI = 0); + virtual void RegisterJITEventListener(JITEventListener *L); + virtual void UnregisterJITEventListener(JITEventListener *L); + /// These functions correspond to the methods on JITEventListener. They + /// iterate over the registered listeners and call the corresponding method on + /// each. + void NotifyFunctionEmitted( + const Function &F, void *Code, size_t Size, + const JITEvent_EmittedFunctionDetails &Details); + void NotifyFreeingMachineCode(const Function &F, void *OldPtr); + private: static JITCodeEmitter *createEmitter(JIT &J, JITMemoryManager *JMM); - void registerMachineCodeInfo(MachineCodeInfo *MCI); void runJITOnFunctionUnlocked(Function *F, const MutexGuard &locked); void updateFunctionStub(Function *F); void updateDlsymStubTable(); Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp?rev=74157&r1=74156&r2=74157&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Wed Jun 24 21:04:04 2009 @@ -24,8 +24,9 @@ #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRelocation.h" -#include "llvm/ExecutionEngine/JITMemoryManager.h" #include "llvm/ExecutionEngine/GenericValue.h" +#include "llvm/ExecutionEngine/JITEventListener.h" +#include "llvm/ExecutionEngine/JITMemoryManager.h" #include "llvm/CodeGen/MachineCodeInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetJITInfo.h" @@ -411,136 +412,6 @@ } //===----------------------------------------------------------------------===// -// Function Index Support - -// On MacOS we generate an index of currently JIT'd functions so that -// performance tools can determine a symbol name and accurate code range for a -// PC value. Because performance tools are generally asynchronous, the code -// below is written with the hope that it could be interrupted at any time and -// have useful answers. However, we don't go crazy with atomic operations, we -// just do a "reasonable effort". -#ifdef __APPLE__ -#define ENABLE_JIT_SYMBOL_TABLE 0 -#endif - -/// JitSymbolEntry - Each function that is JIT compiled results in one of these -/// being added to an array of symbols. This indicates the name of the function -/// as well as the address range it occupies. This allows the client to map -/// from a PC value to the name of the function. -struct JitSymbolEntry { - const char *FnName; // FnName - a strdup'd string. - void *FnStart; - intptr_t FnSize; -}; - - -struct JitSymbolTable { - /// NextPtr - This forms a linked list of JitSymbolTable entries. This - /// pointer is not used right now, but might be used in the future. Consider - /// it reserved for future use. - JitSymbolTable *NextPtr; - - /// Symbols - This is an array of JitSymbolEntry entries. Only the first - /// 'NumSymbols' symbols are valid. - JitSymbolEntry *Symbols; - - /// NumSymbols - This indicates the number entries in the Symbols array that - /// are valid. - unsigned NumSymbols; - - /// NumAllocated - This indicates the amount of space we have in the Symbols - /// array. This is a private field that should not be read by external tools. - unsigned NumAllocated; -}; - -#if ENABLE_JIT_SYMBOL_TABLE -JitSymbolTable *__jitSymbolTable; -#endif - -static void AddFunctionToSymbolTable(const char *FnName, - void *FnStart, intptr_t FnSize) { - assert(FnName != 0 && FnStart != 0 && "Bad symbol to add"); - JitSymbolTable **SymTabPtrPtr = 0; -#if !ENABLE_JIT_SYMBOL_TABLE - return; -#else - SymTabPtrPtr = &__jitSymbolTable; -#endif - - // If this is the first entry in the symbol table, add the JitSymbolTable - // index. - if (*SymTabPtrPtr == 0) { - JitSymbolTable *New = new JitSymbolTable(); - New->NextPtr = 0; - New->Symbols = 0; - New->NumSymbols = 0; - New->NumAllocated = 0; - *SymTabPtrPtr = New; - } - - JitSymbolTable *SymTabPtr = *SymTabPtrPtr; - - // If we have space in the table, reallocate the table. - if (SymTabPtr->NumSymbols >= SymTabPtr->NumAllocated) { - // If we don't have space, reallocate the table. - unsigned NewSize = std::max(64U, SymTabPtr->NumAllocated*2); - JitSymbolEntry *NewSymbols = new JitSymbolEntry[NewSize]; - JitSymbolEntry *OldSymbols = SymTabPtr->Symbols; - - // Copy the old entries over. - memcpy(NewSymbols, OldSymbols, SymTabPtr->NumSymbols*sizeof(OldSymbols[0])); - - // Swap the new symbols in, delete the old ones. - SymTabPtr->Symbols = NewSymbols; - SymTabPtr->NumAllocated = NewSize; - delete [] OldSymbols; - } - - // Otherwise, we have enough space, just tack it onto the end of the array. - JitSymbolEntry &Entry = SymTabPtr->Symbols[SymTabPtr->NumSymbols]; - Entry.FnName = strdup(FnName); - Entry.FnStart = FnStart; - Entry.FnSize = FnSize; - ++SymTabPtr->NumSymbols; -} - -static void RemoveFunctionFromSymbolTable(void *FnStart) { - assert(FnStart && "Invalid function pointer"); - JitSymbolTable **SymTabPtrPtr = 0; -#if !ENABLE_JIT_SYMBOL_TABLE - return; -#else - SymTabPtrPtr = &__jitSymbolTable; -#endif - - JitSymbolTable *SymTabPtr = *SymTabPtrPtr; - JitSymbolEntry *Symbols = SymTabPtr->Symbols; - - // Scan the table to find its index. The table is not sorted, so do a linear - // scan. - unsigned Index; - for (Index = 0; Symbols[Index].FnStart != FnStart; ++Index) - assert(Index != SymTabPtr->NumSymbols && "Didn't find function!"); - - // Once we have an index, we know to nuke this entry, overwrite it with the - // entry at the end of the array, making the last entry redundant. - const char *OldName = Symbols[Index].FnName; - Symbols[Index] = Symbols[SymTabPtr->NumSymbols-1]; - free((void*)OldName); - - // Drop the number of symbols in the table. - --SymTabPtr->NumSymbols; - - // Finally, if we deleted the final symbol, deallocate the table itself. - if (SymTabPtr->NumSymbols != 0) - return; - - *SymTabPtrPtr = 0; - delete [] Symbols; - delete SymTabPtr; -} - -//===----------------------------------------------------------------------===// // JITEmitter code. // namespace { @@ -616,11 +487,8 @@ // in the JITResolver's ExternalFnToStubMap. StringMap ExtFnStubs; - // MCI - A pointer to a MachineCodeInfo object to update with information. - MachineCodeInfo *MCI; - public: - JITEmitter(JIT &jit, JITMemoryManager *JMM) : Resolver(jit), CurFn(0), MCI(0) { + JITEmitter(JIT &jit, JITMemoryManager *JMM) : Resolver(jit), CurFn(0) { MemMgr = JMM ? JMM : JITMemoryManager::CreateDefaultMemManager(); if (jit.getJITInfo().needsGOT()) { MemMgr->AllocateGOT(); @@ -716,10 +584,6 @@ JITMemoryManager *getMemMgr(void) const { return MemMgr; } - void setMachineCodeInfo(MachineCodeInfo *mci) { - MCI = mci; - } - private: void *getPointerToGlobal(GlobalValue *GV, void *Reference, bool NoNeedStub); void *getPointerToGVIndirectSym(GlobalValue *V, void *Reference, @@ -1157,21 +1021,16 @@ // Invalidate the icache if necessary. sys::Memory::InvalidateInstructionCache(FnStart, FnEnd-FnStart); - - // Add it to the JIT symbol table if the host wants it. - AddFunctionToSymbolTable(F.getFunction()->getNameStart(), - FnStart, FnEnd-FnStart); + + JITEvent_EmittedFunctionDetails Details; + TheJIT->NotifyFunctionEmitted(*F.getFunction(), FnStart, FnEnd-FnStart, + Details); DOUT << "JIT: Finished CodeGen of [" << (void*)FnStart << "] Function: " << F.getFunction()->getName() << ": " << (FnEnd-FnStart) << " bytes of text, " << Relocations.size() << " relocations\n"; - if (MCI) { - MCI->setAddress(FnStart); - MCI->setSize(FnEnd-FnStart); - } - Relocations.clear(); ConstPoolAddresses.clear(); @@ -1495,13 +1354,6 @@ return JE->getJITResolver().getFunctionStub(F); } -void JIT::registerMachineCodeInfo(MachineCodeInfo *mc) { - assert(isa(JCE) && "Unexpected MCE?"); - JITEmitter *JE = cast(getCodeEmitter()); - - JE->setMachineCodeInfo(mc); -} - void JIT::updateFunctionStub(Function *F) { // Get the empty stub we generated earlier. assert(isa(JCE) && "Unexpected MCE?"); @@ -1609,10 +1461,9 @@ void *OldPtr = updateGlobalMapping(F, 0); if (OldPtr) - RemoveFunctionFromSymbolTable(OldPtr); + TheJIT->NotifyFreeingMachineCode(*F, OldPtr); // Free the actual memory for the function body and related stuff. assert(isa(JCE) && "Unexpected MCE?"); cast(JCE)->deallocateMemForFunction(F); } - Added: llvm/trunk/lib/ExecutionEngine/JIT/MacOSJITEventListener.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/MacOSJITEventListener.cpp?rev=74157&view=auto ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/MacOSJITEventListener.cpp (added) +++ llvm/trunk/lib/ExecutionEngine/JIT/MacOSJITEventListener.cpp Wed Jun 24 21:04:04 2009 @@ -0,0 +1,173 @@ +//===-- MacOSJITEventListener.cpp - Save symbol table for OSX perf tools --===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines a JITEventListener object that records JITted functions to +// a global __jitSymbolTable linked list. Apple's performance tools use this to +// determine a symbol name and accurate code range for a PC value. Because +// performance tools are generally asynchronous, the code below is written with +// the hope that it could be interrupted at any time and have useful answers. +// However, we don't go crazy with atomic operations, we just do a "reasonable +// effort". +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "macos-jit-event-listener" +#include "llvm/Function.h" +#include "llvm/ExecutionEngine/JITEventListener.h" +#include +using namespace llvm; + +#ifdef __APPLE__ +#define ENABLE_JIT_SYMBOL_TABLE 0 +#endif + +#if ENABLE_JIT_SYMBOL_TABLE + +namespace { + +/// JITSymbolEntry - Each function that is JIT compiled results in one of these +/// being added to an array of symbols. This indicates the name of the function +/// as well as the address range it occupies. This allows the client to map +/// from a PC value to the name of the function. +struct JITSymbolEntry { + const char *FnName; // FnName - a strdup'd string. + void *FnStart; + intptr_t FnSize; +}; + + +struct JITSymbolTable { + /// NextPtr - This forms a linked list of JitSymbolTable entries. This + /// pointer is not used right now, but might be used in the future. Consider + /// it reserved for future use. + JITSymbolTable *NextPtr; + + /// Symbols - This is an array of JitSymbolEntry entries. Only the first + /// 'NumSymbols' symbols are valid. + JITSymbolEntry *Symbols; + + /// NumSymbols - This indicates the number entries in the Symbols array that + /// are valid. + unsigned NumSymbols; + + /// NumAllocated - This indicates the amount of space we have in the Symbols + /// array. This is a private field that should not be read by external tools. + unsigned NumAllocated; +}; + +class MacOSJITEventListener : public JITEventListener { +public: + virtual void NotifyFunctionEmitted(const Function &F, + void *FnStart, size_t FnSize, + const EmittedFunctionDetails &Details); + virtual void NotifyFreeingMachineCode(const Function &F, void *OldPtr); +}; + +} // anonymous namespace. + +// This is a public symbol so the performance tools can find it. +JITSymbolTable *__jitSymbolTable; + +namespace llvm { +JITEventListener *createMacOSJITEventListener() { + return new MacOSJITEventListener; +} +} + +// Adds the just-emitted function to the symbol table. +void MacOSJITEventListener::NotifyFunctionEmitted( + const Function &F, void *FnStart, size_t FnSize, + const EmittedFunctionDetails &) { + const char *const FnName = F.getNameStart(); + assert(FnName != 0 && FnStart != 0 && "Bad symbol to add"); + JITSymbolTable **SymTabPtrPtr = 0; + SymTabPtrPtr = &__jitSymbolTable; + + // If this is the first entry in the symbol table, add the JITSymbolTable + // index. + if (*SymTabPtrPtr == 0) { + JITSymbolTable *New = new JITSymbolTable(); + New->NextPtr = 0; + New->Symbols = 0; + New->NumSymbols = 0; + New->NumAllocated = 0; + *SymTabPtrPtr = New; + } + + JITSymbolTable *SymTabPtr = *SymTabPtrPtr; + + // If we have space in the table, reallocate the table. + if (SymTabPtr->NumSymbols >= SymTabPtr->NumAllocated) { + // If we don't have space, reallocate the table. + unsigned NewSize = std::max(64U, SymTabPtr->NumAllocated*2); + JITSymbolEntry *NewSymbols = new JITSymbolEntry[NewSize]; + JITSymbolEntry *OldSymbols = SymTabPtr->Symbols; + + // Copy the old entries over. + memcpy(NewSymbols, OldSymbols, SymTabPtr->NumSymbols*sizeof(OldSymbols[0])); + + // Swap the new symbols in, delete the old ones. + SymTabPtr->Symbols = NewSymbols; + SymTabPtr->NumAllocated = NewSize; + delete [] OldSymbols; + } + + // Otherwise, we have enough space, just tack it onto the end of the array. + JITSymbolEntry &Entry = SymTabPtr->Symbols[SymTabPtr->NumSymbols]; + Entry.FnName = strdup(FnName); + Entry.FnStart = FnStart; + Entry.FnSize = FnSize; + ++SymTabPtr->NumSymbols; +} + +// Removes the to-be-deleted function from the symbol table. +void MacOSJITEventListener::NotifyFreeingMachineCode( + const Function &, void *FnStart) { + assert(FnStart && "Invalid function pointer"); + JITSymbolTable **SymTabPtrPtr = 0; + SymTabPtrPtr = &__jitSymbolTable; + + JITSymbolTable *SymTabPtr = *SymTabPtrPtr; + JITSymbolEntry *Symbols = SymTabPtr->Symbols; + + // Scan the table to find its index. The table is not sorted, so do a linear + // scan. + unsigned Index; + for (Index = 0; Symbols[Index].FnStart != FnStart; ++Index) + assert(Index != SymTabPtr->NumSymbols && "Didn't find function!"); + + // Once we have an index, we know to nuke this entry, overwrite it with the + // entry at the end of the array, making the last entry redundant. + const char *OldName = Symbols[Index].FnName; + Symbols[Index] = Symbols[SymTabPtr->NumSymbols-1]; + free((void*)OldName); + + // Drop the number of symbols in the table. + --SymTabPtr->NumSymbols; + + // Finally, if we deleted the final symbol, deallocate the table itself. + if (SymTabPtr->NumSymbols != 0) + return; + + *SymTabPtrPtr = 0; + delete [] Symbols; + delete SymTabPtr; +} + +#else // !ENABLE_JIT_SYMBOL_TABLE + +namespace llvm { +// By defining this to return NULL, we can let clients call it unconditionally, +// even if they aren't on an Apple system. +JITEventListener *createMacOSJITEventListener() { + return NULL; +} +} // namespace llvm + +#endif // ENABLE_JIT_SYMBOL_TABLE Modified: llvm/trunk/tools/lli/lli.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lli/lli.cpp?rev=74157&r1=74156&r2=74157&view=diff ============================================================================== --- llvm/trunk/tools/lli/lli.cpp (original) +++ llvm/trunk/tools/lli/lli.cpp Wed Jun 24 21:04:04 2009 @@ -18,9 +18,10 @@ #include "llvm/Type.h" #include "llvm/Bitcode/ReaderWriter.h" #include "llvm/CodeGen/LinkAllCodegenComponents.h" -#include "llvm/ExecutionEngine/JIT.h" -#include "llvm/ExecutionEngine/Interpreter.h" #include "llvm/ExecutionEngine/GenericValue.h" +#include "llvm/ExecutionEngine/Interpreter.h" +#include "llvm/ExecutionEngine/JIT.h" +#include "llvm/ExecutionEngine/JITEventListener.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/MemoryBuffer.h" @@ -149,6 +150,8 @@ exit(1); } + EE->RegisterJITEventListener(createMacOSJITEventListener()); + if (NoLazyCompilation) EE->DisableLazyCompilation(); Added: llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp?rev=74157&view=auto ============================================================================== --- llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp (added) +++ llvm/trunk/unittests/ExecutionEngine/JIT/JITEventListenerTest.cpp Wed Jun 24 21:04:04 2009 @@ -0,0 +1,241 @@ +//===- JITEventListenerTest.cpp - Unit tests for JITEventListeners --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/ExecutionEngine/JITEventListener.h" + +#include "llvm/Instructions.h" +#include "llvm/Module.h" +#include "llvm/ModuleProvider.h" +#include "llvm/ADT/OwningPtr.h" +#include "llvm/CodeGen/MachineCodeInfo.h" +#include "llvm/ExecutionEngine/JIT.h" +#include "llvm/Support/TypeBuilder.h" +#include "llvm/Target/TargetSelect.h" +#include "gtest/gtest.h" +#include + +using namespace llvm; + +namespace { + +struct FunctionEmittedEvent { + // Indices are local to the RecordingJITEventListener, since the + // JITEventListener interface makes no guarantees about the order of + // calls between Listeners. + unsigned Index; + const Function *F; + void *Code; + size_t Size; + JITEvent_EmittedFunctionDetails Details; +}; +struct FunctionFreedEvent { + unsigned Index; + const Function *F; + void *Code; +}; + +struct RecordingJITEventListener : public JITEventListener { + std::vector EmittedEvents; + std::vector FreedEvents; + + int NextIndex; + + RecordingJITEventListener() : NextIndex(0) {} + + virtual void NotifyFunctionEmitted(const Function &F, + void *Code, size_t Size, + const EmittedFunctionDetails &Details) { + FunctionEmittedEvent Event = {NextIndex++, &F, Code, Size, Details}; + EmittedEvents.push_back(Event); + } + + virtual void NotifyFreeingMachineCode(const Function &F, void *OldPtr) { + FunctionFreedEvent Event = {NextIndex++, &F, OldPtr}; + FreedEvents.push_back(Event); + } +}; + +class JITEventListenerTest : public testing::Test { + protected: + JITEventListenerTest() + : M(new Module("module")), + EE(ExecutionEngine::createJIT(new ExistingModuleProvider(M))) { + } + + Module *M; + const OwningPtr EE; +}; + +Function *buildFunction(Module *M) { + Function *Result = Function::Create( + TypeBuilder::get(), + GlobalValue::ExternalLinkage, "id", M); + Value *Arg = Result->arg_begin(); + BasicBlock *BB = BasicBlock::Create("entry", Result); + ReturnInst::Create(Arg, BB); + return Result; +} + +// Tests that a single JITEventListener follows JIT events accurately. +TEST_F(JITEventListenerTest, Simple) { + RecordingJITEventListener Listener; + EE->RegisterJITEventListener(&Listener); + Function *F1 = buildFunction(M); + Function *F2 = buildFunction(M); + + void *F1_addr = EE->getPointerToFunction(F1); + void *F2_addr = EE->getPointerToFunction(F2); + EE->getPointerToFunction(F1); // Should do nothing. + EE->freeMachineCodeForFunction(F1); + EE->freeMachineCodeForFunction(F2); + + ASSERT_EQ(2U, Listener.EmittedEvents.size()); + ASSERT_EQ(2U, Listener.FreedEvents.size()); + + EXPECT_EQ(0U, Listener.EmittedEvents[0].Index); + EXPECT_EQ(F1, Listener.EmittedEvents[0].F); + EXPECT_EQ(F1_addr, Listener.EmittedEvents[0].Code); + EXPECT_LT(0U, Listener.EmittedEvents[0].Size) + << "We don't know how big the function will be, but it had better" + << " contain some bytes."; + + EXPECT_EQ(1U, Listener.EmittedEvents[1].Index); + EXPECT_EQ(F2, Listener.EmittedEvents[1].F); + EXPECT_EQ(F2_addr, Listener.EmittedEvents[1].Code); + EXPECT_LT(0U, Listener.EmittedEvents[1].Size) + << "We don't know how big the function will be, but it had better" + << " contain some bytes."; + + EXPECT_EQ(2U, Listener.FreedEvents[0].Index); + EXPECT_EQ(F1, Listener.FreedEvents[0].F); + EXPECT_EQ(F1_addr, Listener.FreedEvents[0].Code); + + EXPECT_EQ(3U, Listener.FreedEvents[1].Index); + EXPECT_EQ(F2, Listener.FreedEvents[1].F); + EXPECT_EQ(F2_addr, Listener.FreedEvents[1].Code); + + F1->eraseFromParent(); + F2->eraseFromParent(); +} + +// Tests that a single JITEventListener follows JIT events accurately. +TEST_F(JITEventListenerTest, MultipleListenersDontInterfere) { + RecordingJITEventListener Listener1; + RecordingJITEventListener Listener2; + RecordingJITEventListener Listener3; + Function *F1 = buildFunction(M); + Function *F2 = buildFunction(M); + + EE->RegisterJITEventListener(&Listener1); + EE->RegisterJITEventListener(&Listener2); + void *F1_addr = EE->getPointerToFunction(F1); + EE->RegisterJITEventListener(&Listener3); + EE->UnregisterJITEventListener(&Listener1); + void *F2_addr = EE->getPointerToFunction(F2); + EE->UnregisterJITEventListener(&Listener2); + EE->UnregisterJITEventListener(&Listener3); + EE->freeMachineCodeForFunction(F1); + EE->RegisterJITEventListener(&Listener2); + EE->RegisterJITEventListener(&Listener3); + EE->RegisterJITEventListener(&Listener1); + EE->freeMachineCodeForFunction(F2); + EE->UnregisterJITEventListener(&Listener1); + EE->UnregisterJITEventListener(&Listener2); + EE->UnregisterJITEventListener(&Listener3); + + // Listener 1. + ASSERT_EQ(1U, Listener1.EmittedEvents.size()); + ASSERT_EQ(1U, Listener1.FreedEvents.size()); + + EXPECT_EQ(0U, Listener1.EmittedEvents[0].Index); + EXPECT_EQ(F1, Listener1.EmittedEvents[0].F); + EXPECT_EQ(F1_addr, Listener1.EmittedEvents[0].Code); + EXPECT_LT(0U, Listener1.EmittedEvents[0].Size) + << "We don't know how big the function will be, but it had better" + << " contain some bytes."; + + EXPECT_EQ(1U, Listener1.FreedEvents[0].Index); + EXPECT_EQ(F2, Listener1.FreedEvents[0].F); + EXPECT_EQ(F2_addr, Listener1.FreedEvents[0].Code); + + // Listener 2. + ASSERT_EQ(2U, Listener2.EmittedEvents.size()); + ASSERT_EQ(1U, Listener2.FreedEvents.size()); + + EXPECT_EQ(0U, Listener2.EmittedEvents[0].Index); + EXPECT_EQ(F1, Listener2.EmittedEvents[0].F); + EXPECT_EQ(F1_addr, Listener2.EmittedEvents[0].Code); + EXPECT_LT(0U, Listener2.EmittedEvents[0].Size) + << "We don't know how big the function will be, but it had better" + << " contain some bytes."; + + EXPECT_EQ(1U, Listener2.EmittedEvents[1].Index); + EXPECT_EQ(F2, Listener2.EmittedEvents[1].F); + EXPECT_EQ(F2_addr, Listener2.EmittedEvents[1].Code); + EXPECT_LT(0U, Listener2.EmittedEvents[1].Size) + << "We don't know how big the function will be, but it had better" + << " contain some bytes."; + + EXPECT_EQ(2U, Listener2.FreedEvents[0].Index); + EXPECT_EQ(F2, Listener2.FreedEvents[0].F); + EXPECT_EQ(F2_addr, Listener2.FreedEvents[0].Code); + + // Listener 3. + ASSERT_EQ(1U, Listener3.EmittedEvents.size()); + ASSERT_EQ(1U, Listener3.FreedEvents.size()); + + EXPECT_EQ(0U, Listener3.EmittedEvents[0].Index); + EXPECT_EQ(F2, Listener3.EmittedEvents[0].F); + EXPECT_EQ(F2_addr, Listener3.EmittedEvents[0].Code); + EXPECT_LT(0U, Listener3.EmittedEvents[0].Size) + << "We don't know how big the function will be, but it had better" + << " contain some bytes."; + + EXPECT_EQ(1U, Listener3.FreedEvents[0].Index); + EXPECT_EQ(F2, Listener3.FreedEvents[0].F); + EXPECT_EQ(F2_addr, Listener3.FreedEvents[0].Code); + + F1->eraseFromParent(); + F2->eraseFromParent(); +} + +TEST_F(JITEventListenerTest, MatchesMachineCodeInfo) { + RecordingJITEventListener Listener; + MachineCodeInfo MCI; + Function *F = buildFunction(M); + + EE->RegisterJITEventListener(&Listener); + EE->runJITOnFunction(F, &MCI); + void *F_addr = EE->getPointerToFunction(F); + EE->freeMachineCodeForFunction(F); + + ASSERT_EQ(1U, Listener.EmittedEvents.size()); + ASSERT_EQ(1U, Listener.FreedEvents.size()); + + EXPECT_EQ(0U, Listener.EmittedEvents[0].Index); + EXPECT_EQ(F, Listener.EmittedEvents[0].F); + EXPECT_EQ(F_addr, Listener.EmittedEvents[0].Code); + EXPECT_EQ(MCI.address(), Listener.EmittedEvents[0].Code); + EXPECT_EQ(MCI.size(), Listener.EmittedEvents[0].Size); + + EXPECT_EQ(1U, Listener.FreedEvents[0].Index); + EXPECT_EQ(F, Listener.FreedEvents[0].F); + EXPECT_EQ(F_addr, Listener.FreedEvents[0].Code); +} + +class JITEnvironment : public testing::Environment { + virtual void SetUp() { + // Required for ExecutionEngine::createJIT to create a JIT. + InitializeNativeTarget(); + } +}; +testing::Environment* const jit_env = + testing::AddGlobalTestEnvironment(new JITEnvironment); + +} // anonymous namespace Added: llvm/trunk/unittests/ExecutionEngine/JIT/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ExecutionEngine/JIT/Makefile?rev=74157&view=auto ============================================================================== --- llvm/trunk/unittests/ExecutionEngine/JIT/Makefile (added) +++ llvm/trunk/unittests/ExecutionEngine/JIT/Makefile Wed Jun 24 21:04:04 2009 @@ -0,0 +1,15 @@ +##===- unittests/ExecutionEngine/JIT/Makefile --------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../.. +TESTNAME = JIT +LINK_COMPONENTS := core support jit native + +include $(LEVEL)/Makefile.config +include $(LLVM_SRC_ROOT)/unittests/Makefile.unittest Added: llvm/trunk/unittests/ExecutionEngine/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ExecutionEngine/Makefile?rev=74157&view=auto ============================================================================== --- llvm/trunk/unittests/ExecutionEngine/Makefile (added) +++ llvm/trunk/unittests/ExecutionEngine/Makefile Wed Jun 24 21:04:04 2009 @@ -0,0 +1,19 @@ +##===- unittests/ExecutionEngine/Makefile ------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../.. + +include $(LEVEL)/Makefile.config + +PARALLEL_DIRS = JIT + +include $(LEVEL)/Makefile.common + +clean:: + $(Verb) $(RM) -f *Tests Modified: llvm/trunk/unittests/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Makefile?rev=74157&r1=74156&r2=74157&view=diff ============================================================================== --- llvm/trunk/unittests/Makefile (original) +++ llvm/trunk/unittests/Makefile Wed Jun 24 21:04:04 2009 @@ -16,7 +16,7 @@ CPP.Flags += -I$(LLVM_SRC_ROOT)/utils/unittest/googletest/include/ CPP.Flags += -Wno-variadic-macros -PARALLEL_DIRS = ADT Support VMCore MC +PARALLEL_DIRS = ADT ExecutionEngine Support VMCore MC include $(LEVEL)/Makefile.common From evan.cheng at apple.com Wed Jun 24 21:08:06 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 25 Jun 2009 02:08:06 -0000 Subject: [llvm-commits] [llvm] r74158 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrThumb2.td Message-ID: <200906250208.n5P286TU012448@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 24 21:08:06 2009 New Revision: 74158 URL: http://llvm.org/viewvc/llvm-project?rev=74158&view=rev Log: Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=74158&r1=74157&r2=74158&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Jun 24 21:08:06 2009 @@ -773,20 +773,51 @@ list Predicates = [IsThumb1Only]; } -// T2I - Thumb2 instruction. +// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. +class Thumb2I pattern> + : InstARM { + let OutOperandList = oops; + let InOperandList = !con(iops, (ops pred:$p)); + let AsmString = !strconcat(opc, !strconcat("${p}", asm)); + let Pattern = pattern; + list Predicates = [IsThumb, HasThumb2]; +} -class Thumb2I pattern> +// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as +// an input operand since by default it's a zero register. It will +// become an implicit def once it's "flipped". +// FIXME: This uses unified syntax so {s} comes before {p}. We should make it +// more consistent. +class Thumb2sI pattern> : InstARM { - let OutOperandList = outs; - let InOperandList = ins; + let OutOperandList = oops; + let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); + let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); + let Pattern = pattern; + list Predicates = [IsThumb, HasThumb2]; +} + +// Special cases +class Thumb2XI pattern> + : InstARM { + let OutOperandList = oops; + let InOperandList = iops; let AsmString = asm; let Pattern = pattern; list Predicates = [IsThumb, HasThumb2]; } -class T2I pattern> - : Thumb2I; +class T2I pattern> + : Thumb2I; + +class T2sI pattern> + : Thumb2sI; + +class T2XI pattern> + : Thumb2XI; // Thumb2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. class Thumb2Pat : Pat { Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=74158&r1=74157&r2=74158&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jun 24 21:08:06 2009 @@ -131,55 +131,57 @@ // /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a -// unary operation that produces a value. +/// unary operation that produces a value. These are predicable and can be +/// changed to modify CPSR. multiclass T2I_un_irs{ // shifted imm - def i : T2I<(outs GPR:$dst), (ins t2_so_imm:$src), - !strconcat(opc, " $dst, $src"), + def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), + opc, " $dst, $src", [(set GPR:$dst, (opnode t2_so_imm:$src))]> { let isAsCheapAsAMove = Cheap; let isReMaterializable = ReMat; } // register def r : T2I<(outs GPR:$dst), (ins GPR:$src), - !strconcat(opc, " $dst, $src"), + opc, " $dst, $src", [(set GPR:$dst, (opnode GPR:$src))]>; // shifted register def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), - !strconcat(opc, " $dst, $src"), - [(set GPR:$dst, (opnode t2_so_reg:$src))]>; + opc, " $dst, $src", + [(set GPR:$dst, (opnode t2_so_reg:$src))]>; } /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a -// binary operation that produces a value. +// binary operation that produces a value. These are predicable and can be +/// changed to modify CPSR. multiclass T2I_bin_irs { // shifted imm - def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), - !strconcat(opc, " $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; + def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), + opc, " $dst, $lhs, $rhs", + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; // register - def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), - !strconcat(opc, " $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; + def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), + opc, " $dst, $lhs, $rhs", + [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register - def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), - !strconcat(opc, " $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; + def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), + opc, " $dst, $lhs, $rhs", + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; } -/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are reversed. +/// T2I_rbin_irs - Same as T2I_bin_irs except the order of operands are reversed. multiclass T2I_rbin_irs { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), - !strconcat(opc, " $dst, $rhs, $lhs"), + opc, " $dst, $rhs, $lhs", [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; // register def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs), - !strconcat(opc, " $dst, $rhs, $lhs"), + opc, " $dst, $rhs, $lhs", [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), - !strconcat(opc, " $dst, $rhs, $lhs"), + opc, " $dst, $rhs, $lhs", [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; } @@ -189,15 +191,15 @@ multiclass T2I_bin_s_irs { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), - !strconcat(opc, "s $dst, $lhs, $rhs"), + !strconcat(opc, "s"), " $dst, $lhs, $rhs", [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; // register def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), - !strconcat(opc, " $dst, $lhs, $rhs"), + !strconcat(opc, "s"), " $dst, $lhs, $rhs", [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), - !strconcat(opc, "s $dst, $lhs, $rhs"), + !strconcat(opc, "s"), " $dst, $lhs, $rhs", [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; } } @@ -208,15 +210,15 @@ multiclass T2I_rbin_s_irs { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), - !strconcat(opc, "s $dst, $rhs, $lhs"), + !strconcat(opc, "s"), " $dst, $rhs, $lhs", [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; // register def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs), - !strconcat(opc, " $dst, $rhs, $lhs"), + !strconcat(opc, "s"), " $dst, $rhs, $lhs", [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), - !strconcat(opc, "s $dst, $rhs, $lhs"), + !strconcat(opc, "s"), " $dst, $rhs, $lhs", [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; } } @@ -225,21 +227,21 @@ /// patterns for a binary operation that produces a value. multiclass T2I_bin_ii12rs { // shifted imm - def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), - !strconcat(opc, " $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; + def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), + opc, " $dst, $lhs, $rhs", + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; // 12-bit imm - def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), - !strconcat(opc, "w $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>; + def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), + !strconcat(opc, "w"), " $dst, $lhs, $rhs", + [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>; // register - def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), - !strconcat(opc, " $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; + def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), + opc, " $dst, $lhs, $rhs", + [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register - def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), - !strconcat(opc, " $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; + def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), + opc, " $dst, $lhs, $rhs", + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; } /// T2I_bin_c_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a @@ -248,17 +250,17 @@ let Uses = [CPSR] in { multiclass T2I_bin_c_irs { // shifted imm - def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; + def ri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs, cc_out:$s), + !strconcat(opc, "${s} $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; // register - def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; + def rr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s), + !strconcat(opc, "${s} $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register - def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; + def rs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s), + !strconcat(opc, "${s} $dst, $lhs, $rhs"), + [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; } } @@ -267,17 +269,17 @@ let Uses = [CPSR] in { multiclass T2I_rbin_c_irs { // shifted imm - def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $rhs, $lhs"), - [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; + def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), + !strconcat(opc, "${s} $dst, $rhs, $lhs"), + [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; // register - def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $rhs, $lhs"), - [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; + def rr : T2XI<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs, cc_out:$s), + !strconcat(opc, "${s} $dst, $rhs, $lhs"), + [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register - def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $rhs, $lhs"), - [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; + def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), + !strconcat(opc, "${s} $dst, $rhs, $lhs"), + [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; } } @@ -285,13 +287,13 @@ // rotate operation that produces a value. multiclass T2I_sh_ir { // 5-bit imm - def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), - !strconcat(opc, " $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>; + def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), + opc, " $dst, $lhs, $rhs", + [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>; // register - def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), - !strconcat(opc, " $dst, $lhs, $rhs"), - [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; + def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), + opc, " $dst, $lhs, $rhs", + [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; } /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test @@ -301,15 +303,15 @@ multiclass T2I_cmp_is { // shifted imm def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), - !strconcat(opc, " $lhs, $rhs"), + opc, " $lhs, $rhs", [(opnode GPR:$lhs, t2_so_imm:$rhs)]>; // register def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), - !strconcat(opc, " $lhs, $rhs"), + opc, " $lhs, $rhs", [(opnode GPR:$lhs, GPR:$rhs)]>; // shifted register def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), - !strconcat(opc, " $lhs, $rhs"), + opc, " $lhs, $rhs", [(opnode GPR:$lhs, t2_so_reg:$rhs)]>; } } @@ -319,21 +321,21 @@ // let isNotDuplicable = 1 in -def t2PICADD : T2I<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp), - "$cp:\n\tadd $dst, pc", - [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>; +def t2PICADD : T2XI<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp), + "$cp:\n\tadd $dst, pc", + [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>; // LEApcrel - Load a pc-relative address into a register without offending the // assembler. -def t2LEApcrel : T2I<(outs GPR:$dst), (ins i32imm:$label, pred:$p), +def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", "${:private}PCRELL${:uid}+8))\n"), !strconcat("${:private}PCRELL${:uid}:\n\t", "add$p $dst, pc, #PCRELV${:uid}")), []>; -def t2LEApcrelJT : T2I<(outs GPR:$dst), +def t2LEApcrelJT : T2XI<(outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p), !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", "${:private}PCRELL${:uid}+8))\n"), @@ -342,43 +344,39 @@ []>; // ADD rd, sp, #so_imm -def t2ADDrSPi : T2I<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), - "add $dst, $sp, $imm", - []>; +def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), + "add $dst, $sp, $imm", + []>; // ADD rd, sp, #imm12 -def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm), - "addw $dst, $sp, $imm", - []>; - -def t2ADDrSPs : T2I<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), - "addw $dst, $sp, $rhs", - []>; - +def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm), + "addw $dst, $sp, $imm", + []>; + +def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), + "addw $dst, $sp, $rhs", + []>; -//===----------------------------------------------------------------------===// -// Arithmetic Instructions. -// //===----------------------------------------------------------------------===// // Move Instructions. // let neverHasSideEffects = 1 in -def t2MOVr : T2I<(outs GPR:$dst), (ins GPR:$src), - "mov $dst, $src", []>; +def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), + "mov", " $dst, $src", []>; let isReMaterializable = 1, isAsCheapAsAMove = 1 in -def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), - "movw $dst, $src", - [(set GPR:$dst, imm0_65535:$src)]>; +def t2MOVi16 : T2sI<(outs GPR:$dst), (ins i32imm:$src), + "movw", " $dst, $src", + [(set GPR:$dst, imm0_65535:$src)]>; // FIXME: Also available in ARM mode. let Constraints = "$src = $dst" in -def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), - "movt $dst, $imm", - [(set GPR:$dst, - (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>; +def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), + "movt", " $dst, $imm", + [(set GPR:$dst, + (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>; //===----------------------------------------------------------------------===// // Arithmetic Instructions. @@ -416,9 +414,9 @@ defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; -def t2MOVrx : T2I<(outs GPR:$dst), (ins GPR:$src), - "mov $dst, $src, rrx", - [(set GPR:$dst, (ARMrrx GPR:$src))]>; +def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), + "mov", " $dst, $src, rrx", + [(set GPR:$dst, (ARMrrx GPR:$src))]>; //===----------------------------------------------------------------------===// // Bitwise Instructions. @@ -444,7 +442,7 @@ // FIXME: Also available in ARM mode. let Constraints = "$src = $dst" in def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), - "bfc $dst, $imm", + "bfc", " $dst, $imm", [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>; // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1) @@ -453,15 +451,15 @@ // Multiply Instructions. // def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), - "mul $dst, $a, $b", + "mul", " $dst, $a, $b", [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), - "mla $dst, $a, $b, $c", + "mla", " $dst, $a, $b, $c", [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), - "mls $dst, $a, $b, $c", + "mls", " $dst, $a, $b, $c", [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>; // FIXME: SMULL, etc. @@ -475,15 +473,15 @@ ///// // FIXME not firing? but ARM version does... def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), - "clz $dst, $src", + "clz", " $dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>; def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), - "rev $dst, $src", + "rev", " $dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>; def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), - "rev16 $dst, $src", + "rev16", " $dst, $src", [(set GPR:$dst, (or (and (srl GPR:$src, (i32 8)), 0xFF), (or (and (shl GPR:$src, (i32 8)), 0xFF00), @@ -494,7 +492,7 @@ /// A8.6.137 REVSH ///// def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), - "revsh $dst, $src", + "revsh", " $dst, $src", [(set GPR:$dst, (sext_inreg (or (srl (and GPR:$src, 0xFFFF), (i32 8)), From a at bolka.at Wed Jun 24 16:29:15 2009 From: a at bolka.at (Andreas Bolka) Date: Wed, 24 Jun 2009 21:29:15 -0000 Subject: [llvm-commits] [llvm] r74120 - in /llvm/trunk: include/llvm/Analysis/LoopDependenceAnalysis.h include/llvm/Analysis/Passes.h include/llvm/LinkAllPasses.h lib/Analysis/CMakeLists.txt lib/Analysis/LoopDependenceAnalysis.cpp Message-ID: <200906242129.n5OLTHcu002868@zion.cs.uiuc.edu> Author: abolka Date: Wed Jun 24 16:29:13 2009 New Revision: 74120 URL: http://llvm.org/viewvc/llvm-project?rev=74120&view=rev Log: Scaffolding for LDA pass. Added: llvm/trunk/include/llvm/Analysis/LoopDependenceAnalysis.h llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp Modified: llvm/trunk/include/llvm/Analysis/Passes.h llvm/trunk/include/llvm/LinkAllPasses.h llvm/trunk/lib/Analysis/CMakeLists.txt Added: llvm/trunk/include/llvm/Analysis/LoopDependenceAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopDependenceAnalysis.h?rev=74120&view=auto ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopDependenceAnalysis.h (added) +++ llvm/trunk/include/llvm/Analysis/LoopDependenceAnalysis.h Wed Jun 24 16:29:13 2009 @@ -0,0 +1,52 @@ +//===- llvm/Analysis/LoopDependenceAnalysis.h --------------- -*- C++ -*---===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// LoopDependenceAnalysis is an LLVM pass that analyses dependences in memory +// accesses in loops. +// +// Please note that this is work in progress and the interface is subject to +// change. +// +// TODO: adapt as interface progresses +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ANALYSIS_LOOP_DEPENDENCE_ANALYSIS_H +#define LLVM_ANALYSIS_LOOP_DEPENDENCE_ANALYSIS_H + +#include "llvm/Analysis/LoopPass.h" + +namespace llvm { + + class AnalysisUsage; + class LoopPass; + class ScalarEvolution; + + class LoopDependenceAnalysis : public LoopPass { + Loop *L; + ScalarEvolution *SE; + + public: + static char ID; // Class identification, replacement for typeinfo + LoopDependenceAnalysis() : LoopPass(&ID) {} + + bool runOnLoop(Loop*, LPPassManager&); + + virtual void getAnalysisUsage(AnalysisUsage&) const; + }; // class LoopDependenceAnalysis + + + // createLoopDependenceAnalysisPass - This creates an instance of the + // LoopDependenceAnalysis pass. + // + LoopPass *createLoopDependenceAnalysisPass(); + +} // namespace llvm + +#endif /* LLVM_ANALYSIS_LOOP_DEPENDENCE_ANALYSIS_H */ Modified: llvm/trunk/include/llvm/Analysis/Passes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Passes.h?rev=74120&r1=74119&r2=74120&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/Passes.h (original) +++ llvm/trunk/include/llvm/Analysis/Passes.h Wed Jun 24 16:29:13 2009 @@ -18,6 +18,7 @@ namespace llvm { class FunctionPass; class ImmutablePass; + class LoopPass; class ModulePass; class Pass; class LibCallInfo; @@ -116,6 +117,13 @@ // createLiveValuesPass - This creates an instance of the LiveValues pass. // FunctionPass *createLiveValuesPass(); + + //===--------------------------------------------------------------------===// + // + // createLoopDependenceAnalysisPass - This creates an instance of the + // LoopDependenceAnalysis pass. + // + LoopPass *createLoopDependenceAnalysisPass(); // Minor pass prototypes, allowing us to expose them through bugpoint and // analyze. Modified: llvm/trunk/include/llvm/LinkAllPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=74120&r1=74119&r2=74120&view=diff ============================================================================== --- llvm/trunk/include/llvm/LinkAllPasses.h (original) +++ llvm/trunk/include/llvm/LinkAllPasses.h Wed Jun 24 16:29:13 2009 @@ -77,6 +77,7 @@ (void) llvm::createLCSSAPass(); (void) llvm::createLICMPass(); (void) llvm::createLiveValuesPass(); + (void) llvm::createLoopDependenceAnalysisPass(); (void) llvm::createLoopExtractorPass(); (void) llvm::createLoopSimplifyPass(); (void) llvm::createLoopStrengthReducePass(); Modified: llvm/trunk/lib/Analysis/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CMakeLists.txt?rev=74120&r1=74119&r2=74120&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CMakeLists.txt (original) +++ llvm/trunk/lib/Analysis/CMakeLists.txt Wed Jun 24 16:29:13 2009 @@ -18,6 +18,7 @@ LibCallAliasAnalysis.cpp LibCallSemantics.cpp LiveValues.cpp + LoopDependenceAnalysis.cpp LoopInfo.cpp LoopPass.cpp LoopVR.cpp Added: llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp?rev=74120&view=auto ============================================================================== --- llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp (added) +++ llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp Wed Jun 24 16:29:13 2009 @@ -0,0 +1,47 @@ +//===- LoopDependenceAnalysis.cpp - LDA Implementation ----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This is the (beginning) of an implementation of a loop dependence analysis +// framework, which is used to detect dependences in memory accesses in loops. +// +// Please note that this is work in progress and the interface is subject to +// change. +// +// TODO: adapt as implementation progresses. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "lda" +#include "llvm/Analysis/LoopDependenceAnalysis.h" +#include "llvm/Analysis/LoopPass.h" +#include "llvm/Analysis/ScalarEvolution.h" +using namespace llvm; + +LoopPass *llvm::createLoopDependenceAnalysisPass() { + return new LoopDependenceAnalysis(); +} + +static RegisterPass +R("lda", "Loop Dependence Analysis", false, true); +char LoopDependenceAnalysis::ID = 0; + +//===----------------------------------------------------------------------===// +// LoopDependenceAnalysis Implementation +//===----------------------------------------------------------------------===// + +bool LoopDependenceAnalysis::runOnLoop(Loop *L, LPPassManager &) { + this->L = L; + SE = &getAnalysis(); + return false; +} + +void LoopDependenceAnalysis::getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesAll(); + AU.addRequired(); +} From sabre at nondot.org Wed Jun 24 23:29:09 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 25 Jun 2009 04:29:09 -0000 Subject: [llvm-commits] [llvm] r74159 - /llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt Message-ID: <200906250429.n5P4T9mP016830@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 24 23:29:08 2009 New Revision: 74159 URL: http://llvm.org/viewvc/llvm-project?rev=74159&view=rev Log: add file to cmake Modified: llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt Modified: llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt?rev=74159&r1=74158&r2=74159&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt Wed Jun 24 23:29:08 2009 @@ -7,5 +7,6 @@ JITDwarfEmitter.cpp JITEmitter.cpp JITMemoryManager.cpp + MacOSJITEventListener.cpp TargetSelect.cpp ) From dgregor at apple.com Thu Jun 25 00:03:06 2009 From: dgregor at apple.com (Douglas Gregor) Date: Thu, 25 Jun 2009 05:03:06 -0000 Subject: [llvm-commits] [llvm] r74161 - in /llvm/trunk: cmake/modules/TableGen.cmake lib/Target/ARM/AsmPrinter/CMakeLists.txt lib/Target/Alpha/AsmPrinter/CMakeLists.txt lib/Target/CellSPU/AsmPrinter/CMakeLists.txt lib/Target/IA64/AsmPrinter/CMakeLists.txt lib/Target/Mips/AsmPrinter/CMakeLists.txt lib/Target/PowerPC/AsmPrinter/CMakeLists.txt lib/Target/Sparc/AsmPrinter/CMakeLists.txt lib/Target/X86/AsmPrinter/CMakeLists.txt Message-ID: <200906250503.n5P536Pq017977@zion.cs.uiuc.edu> Author: dgregor Date: Thu Jun 25 00:03:06 2009 New Revision: 74161 URL: http://llvm.org/viewvc/llvm-project?rev=74161&view=rev Log: Add missing dependencies to the CMake build system. Modified: llvm/trunk/cmake/modules/TableGen.cmake llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/Alpha/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/CellSPU/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/IA64/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/Mips/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/Sparc/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt Modified: llvm/trunk/cmake/modules/TableGen.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/TableGen.cmake?rev=74161&r1=74160&r2=74161&view=diff ============================================================================== --- llvm/trunk/cmake/modules/TableGen.cmake (original) +++ llvm/trunk/cmake/modules/TableGen.cmake Thu Jun 25 00:03:06 2009 @@ -20,4 +20,6 @@ COMMENT "Building ${ofn}..." ) set(TABLEGEN_OUTPUT ${TABLEGEN_OUTPUT} ${CMAKE_CURRENT_BINARY_DIR}/${ofn}) + set_source_files_properties(${CMAKE_CURRENT_BINARY_DIR}/${ofn} + PROPERTIES GENERATED 1) endmacro(tablegen) Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt?rev=74161&r1=74160&r2=74161&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt Thu Jun 25 00:03:06 2009 @@ -3,3 +3,4 @@ add_llvm_library(LLVMARMAsmPrinter ARMAsmPrinter.cpp ) +add_dependencies(LLVMARMAsmPrinter ARMCodeGenTable_gen) \ No newline at end of file Modified: llvm/trunk/lib/Target/Alpha/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AsmPrinter/CMakeLists.txt?rev=74161&r1=74160&r2=74161&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Alpha/AsmPrinter/CMakeLists.txt Thu Jun 25 00:03:06 2009 @@ -3,3 +3,4 @@ add_llvm_library(LLVMAlphaAsmPrinter AlphaAsmPrinter.cpp ) +add_dependencies(LLVMAlphaAsmPrinter AlphaCodeGenTable_gen) Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/CMakeLists.txt?rev=74161&r1=74160&r2=74161&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/CMakeLists.txt Thu Jun 25 00:03:06 2009 @@ -6,3 +6,4 @@ add_llvm_library(LLVMCellSPUAsmPrinter SPUAsmPrinter.cpp ) +add_dependencies(LLVMCellSPUAsmPrinter CellSPUCodeGenTable_gen) \ No newline at end of file Modified: llvm/trunk/lib/Target/IA64/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/AsmPrinter/CMakeLists.txt?rev=74161&r1=74160&r2=74161&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/IA64/AsmPrinter/CMakeLists.txt Thu Jun 25 00:03:06 2009 @@ -6,3 +6,4 @@ add_llvm_library(LLVMIA64AsmPrinter IA64AsmPrinter.cpp ) +add_dependencies(LLVMIA64AsmPrinter IA64CodeGenTable_gen) \ No newline at end of file Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/CMakeLists.txt?rev=74161&r1=74160&r2=74161&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/AsmPrinter/CMakeLists.txt Thu Jun 25 00:03:06 2009 @@ -6,3 +6,4 @@ add_llvm_library(LLVMMipsAsmPrinter MipsAsmPrinter.cpp ) +add_dependencies(LLVMMipsAsmPrinter MipsCodeGenTable_gen) \ No newline at end of file Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/CMakeLists.txt?rev=74161&r1=74160&r2=74161&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/CMakeLists.txt Thu Jun 25 00:03:06 2009 @@ -3,3 +3,4 @@ add_llvm_library(LLVMPowerPCAsmPrinter PPCAsmPrinter.cpp ) +add_dependencies(LLVMPowerPCAsmPrinter PowerPCCodeGenTable_gen) \ No newline at end of file Modified: llvm/trunk/lib/Target/Sparc/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmPrinter/CMakeLists.txt?rev=74161&r1=74160&r2=74161&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Sparc/AsmPrinter/CMakeLists.txt Thu Jun 25 00:03:06 2009 @@ -3,3 +3,4 @@ add_llvm_library(LLVMSparcAsmPrinter SparcAsmPrinter.cpp ) +add_dependencies(LLVMSparcAsmPrinter SparcCodeGenTable_gen) \ No newline at end of file Modified: llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt?rev=74161&r1=74160&r2=74161&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt Thu Jun 25 00:03:06 2009 @@ -6,3 +6,4 @@ X86AsmPrinter.cpp X86IntelAsmPrinter.cpp ) +add_dependencies(LLVMX86AsmPrinter X86CodeGenTable_gen) \ No newline at end of file From bob.wilson at apple.com Thu Jun 25 00:20:33 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 25 Jun 2009 05:20:33 -0000 Subject: [llvm-commits] [llvm] r74164 - /llvm/trunk/lib/Target/ARM/ARMSubtarget.h Message-ID: <200906250520.n5P5KXqF018529@zion.cs.uiuc.edu> Author: bwilson Date: Thu Jun 25 00:20:31 2009 New Revision: 74164 URL: http://llvm.org/viewvc/llvm-project?rev=74164&view=rev Log: Remove unused hasV6T2Ops method. We already have a separate feature to identify Thumb2. Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=74164&r1=74163&r2=74164&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Jun 25 00:20:31 2009 @@ -93,7 +93,6 @@ bool hasV5TOps() const { return ARMArchVersion >= V5T; } bool hasV5TEOps() const { return ARMArchVersion >= V5TE; } bool hasV6Ops() const { return ARMArchVersion >= V6; } - bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } bool hasV7Ops() const { return ARMArchVersion >= V7A; } bool hasVFP2() const { return ARMFPUType >= VFPv2; } From evan.cheng at apple.com Thu Jun 25 01:30:26 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 24 Jun 2009 23:30:26 -0700 Subject: [llvm-commits] [llvm] r74164 - /llvm/trunk/lib/Target/ARM/ARMSubtarget.h In-Reply-To: <200906250520.n5P5KXqF018529@zion.cs.uiuc.edu> References: <200906250520.n5P5KXqF018529@zion.cs.uiuc.edu> Message-ID: I am not sure about this. Some ARM instructions are only available when Thumb2 is available. But using hasThumb2() predicate in ARM mode just seem strange. How about leaving the predicate in but change it to "return ARMArchVersion >= V6 && ThumbMode >= Thumb2"? Evan On Jun 24, 2009, at 10:20 PM, Bob Wilson wrote: > Author: bwilson > Date: Thu Jun 25 00:20:31 2009 > New Revision: 74164 > > URL: http://llvm.org/viewvc/llvm-project?rev=74164&view=rev > Log: > Remove unused hasV6T2Ops method. We already have a separate feature > to > identify Thumb2. > > Modified: > llvm/trunk/lib/Target/ARM/ARMSubtarget.h > > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=74164&r1=74163&r2=74164&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Jun 25 00:20:31 2009 > @@ -93,7 +93,6 @@ > bool hasV5TOps() const { return ARMArchVersion >= V5T; } > bool hasV5TEOps() const { return ARMArchVersion >= V5TE; } > bool hasV6Ops() const { return ARMArchVersion >= V6; } > - bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } > bool hasV7Ops() const { return ARMArchVersion >= V7A; } > > bool hasVFP2() const { return ARMFPUType >= VFPv2; } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bruno.cardoso at gmail.com Thu Jun 25 02:36:25 2009 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 25 Jun 2009 07:36:25 -0000 Subject: [llvm-commits] [llvm] r74170 - in /llvm/trunk/lib/CodeGen: ELF.h ELFCodeEmitter.cpp ELFCodeEmitter.h ELFWriter.cpp ELFWriter.h Message-ID: <200906250736.n5P7aQMG024390@zion.cs.uiuc.edu> Author: bruno Date: Thu Jun 25 02:36:24 2009 New Revision: 74170 URL: http://llvm.org/viewvc/llvm-project?rev=74170&view=rev Log: Support Constant Pool Sections Add section symbols to the symbol table Modified: llvm/trunk/lib/CodeGen/ELF.h llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp llvm/trunk/lib/CodeGen/ELFCodeEmitter.h llvm/trunk/lib/CodeGen/ELFWriter.cpp llvm/trunk/lib/CodeGen/ELFWriter.h Modified: llvm/trunk/lib/CodeGen/ELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELF.h?rev=74170&r1=74169&r2=74170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELF.h (original) +++ llvm/trunk/lib/CodeGen/ELF.h Thu Jun 25 02:36:24 2009 @@ -144,6 +144,9 @@ uint8_t Other; unsigned short SectionIdx; + // Symbol index into the Symbol table + unsigned SymTabIdx; + enum { STB_LOCAL = 0, STB_GLOBAL = 1, @@ -168,7 +171,8 @@ ELFSym(const GlobalValue *gv) : GV(gv), IsCommon(false), IsBss(false), IsConstant(false), NameIdx(0), Value(0), Size(0), Info(0), Other(STV_DEFAULT), - SectionIdx(ELFSection::SHN_UNDEF) { + SectionIdx(ELFSection::SHN_UNDEF), + SymTabIdx(0) { if (!GV) return; @@ -191,6 +195,10 @@ return (Info >> 4) & 0xf; } + unsigned getType() { + return Info & 0xf; + } + void setBind(unsigned X) { assert(X == (X & 0xF) && "Bind value out of range!"); Info = (Info & 0x0F) | (X << 4); Modified: llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp?rev=74170&r1=74169&r2=74170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp (original) +++ llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp Thu Jun 25 02:36:24 2009 @@ -16,6 +16,7 @@ #include "llvm/CodeGen/BinaryObject.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" +#include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/Debug.h" @@ -103,21 +104,28 @@ break; } + // Emit constant pool to appropriate section(s) + emitConstantPool(MF.getConstantPool()); + // Relocations // ----------- - // If we have emitted any relocations to function-specific objects such as + // If we have emitted any relocations to function-specific objects such as // basic blocks, constant pools entries, or jump tables, record their // addresses now so that we can rewrite them with the correct addresses // later. for (unsigned i = 0, e = Relocations.size(); i != e; ++i) { MachineRelocation &MR = Relocations[i]; intptr_t Addr; - if (MR.isBasicBlock()) { + if (MR.isGlobalValue()) { + EW.PendingGlobals.insert(MR.getGlobalValue()); + } else if (MR.isBasicBlock()) { Addr = getMachineBasicBlockAddress(MR.getBasicBlock()); MR.setConstantVal(ES->SectionIdx); MR.setResultPointer((void*)Addr); - } else if (MR.isGlobalValue()) { - EW.PendingGlobals.insert(MR.getGlobalValue()); + } else if (MR.isConstantPoolIndex()) { + Addr = getConstantPoolEntryAddress(MR.getConstantPoolIndex()); + MR.setConstantVal(CPSections[MR.getConstantPoolIndex()]); + MR.setResultPointer((void*)Addr); } else { assert(0 && "Unhandled relocation type"); } @@ -128,4 +136,36 @@ return false; } +/// emitConstantPool - For each constant pool entry, figure out which section +/// the constant should live in and emit the constant +void ELFCodeEmitter::emitConstantPool(MachineConstantPool *MCP) { + const std::vector &CP = MCP->getConstants(); + if (CP.empty()) return; + + // TODO: handle PIC codegen + assert(TM.getRelocationModel() != Reloc::PIC_ && + "PIC codegen not yet handled for elf constant pools!"); + + const TargetAsmInfo *TAI = TM.getTargetAsmInfo(); + for (unsigned i = 0, e = CP.size(); i != e; ++i) { + MachineConstantPoolEntry CPE = CP[i]; + + // Get the right ELF Section for this constant pool entry + std::string CstPoolName = + TAI->SelectSectionForMachineConst(CPE.getType())->getName(); + ELFSection &CstPoolSection = + EW.getConstantPoolSection(CstPoolName, CPE.getAlignment()); + + // Record the constant pool location and the section index + CPLocations.push_back(CstPoolSection.size()); + CPSections.push_back(CstPoolSection.SectionIdx); + + if (CPE.isMachineConstantPoolEntry()) + assert("CPE.isMachineConstantPoolEntry not supported yet"); + + // Emit the constant to constant pool section + EW.EmitGlobalConstant(CPE.Val.ConstVal, CstPoolSection); + } +} + } // end namespace llvm Modified: llvm/trunk/lib/CodeGen/ELFCodeEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFCodeEmitter.h?rev=74170&r1=74169&r2=74170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFCodeEmitter.h (original) +++ llvm/trunk/lib/CodeGen/ELFCodeEmitter.h Thu Jun 25 02:36:24 2009 @@ -31,6 +31,14 @@ /// emitted. std::vector Relocations; + /// CPLocations - This is a map of constant pool indices to offsets from the + /// start of the section for that constant pool index. + std::vector CPLocations; + + /// CPSections - This is a map of constant pool indices to the MachOSection + /// containing the constant pool entry for that index. + std::vector CPSections; + /// MBBLocations - This vector is a mapping from MBB ID's to their address. /// It is filled in by the StartMachineBasicBlock callback and queried by /// the getMachineBasicBlockAddress callback. @@ -62,9 +70,10 @@ } virtual uintptr_t getConstantPoolEntryAddress(unsigned Index) const { - assert(0 && "CP not implementated yet!"); - return 0; + assert(CPLocations.size() > Index && "CP not emitted!"); + return CPLocations[Index]; } + virtual uintptr_t getJumpTableEntryAddress(unsigned Index) const { assert(0 && "JT not implementated yet!"); return 0; @@ -86,6 +95,10 @@ abort(); } + /// emitConstantPool - For each constant pool entry, figure out which section + /// the constant should live in and emit the constant. + void emitConstantPool(MachineConstantPool *MCP); + virtual void setModuleInfo(llvm::MachineModuleInfo* MMI) { } /// JIT SPECIFIC FUNCTIONS - DO NOT IMPLEMENT THESE HERE! Modified: llvm/trunk/lib/CodeGen/ELFWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.cpp?rev=74170&r1=74169&r2=74170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.cpp Thu Jun 25 02:36:24 2009 @@ -389,6 +389,24 @@ if (TAI->getNonexecutableStackDirective()) getNonExecStackSection(); + // Emit a symbol for each section created until now + for (std::map::iterator I = SectionLookup.begin(), + E = SectionLookup.end(); I != E; ++I) { + ELFSection *ES = I->second; + + // Skip null section + if (ES->SectionIdx == 0) continue; + + ELFSym SectionSym(0); + SectionSym.SectionIdx = ES->SectionIdx; + SectionSym.Size = 0; + SectionSym.setBind(ELFSym::STB_LOCAL); + SectionSym.setType(ELFSym::STT_SECTION); + + // Local symbols go in the list front + SymbolList.push_front(SectionSym); + } + // Emit string table EmitStringTable(); @@ -451,15 +469,25 @@ // Constant addend used to compute the value to be stored // into the relocatable field - int64_t Addend = TEW->getAddendForRelTy(RelType); + int64_t Addend = 0; // There are several machine relocations types, and each one of // them needs a different approach to retrieve the symbol table index. if (MR.isGlobalValue()) { const GlobalValue *G = MR.getGlobalValue(); SymIdx = GblSymLookup[G]; + Addend = TEW->getAddendForRelTy(RelType); } else { - assert(0 && "dunno how to handle other relocation types"); + unsigned SectionIdx = MR.getConstantVal(); + // TODO: use a map for this. + for (std::list::iterator I = SymbolList.begin(), + E = SymbolList.end(); I != E; ++I) + if ((SectionIdx == I->SectionIdx) && + (I->getType() == ELFSym::STT_SECTION)) { + SymIdx = I->SymTabIdx; + break; + } + Addend = (uint64_t)MR.getResultPointer(); } // Get the relocation entry and emit to the relocation section @@ -540,7 +568,8 @@ E = SymbolList.end(); I != E; ++I) { // Use the name mangler to uniquify the LLVM symbol. - std::string Name = Mang->getValueName(I->GV); + std::string Name; + if (I->GV) Name.append(Mang->getValueName(I->GV)); if (Name.empty()) { I->NameIdx = 0; @@ -589,7 +618,11 @@ EmitSymbol(SymTab, *I); // Record the symbol table index for each global value - GblSymLookup[I->GV] = Index; + if (I->GV) + GblSymLookup[I->GV] = Index; + + // Keep track on the symbol index into the symbol table + I->SymTabIdx = Index; } SymTab.Info = FirstNonLocalSymbol; Modified: llvm/trunk/lib/CodeGen/ELFWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.h?rev=74170&r1=74169&r2=74170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.h (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.h Thu Jun 25 02:36:24 2009 @@ -147,6 +147,12 @@ ELFSection::SHF_EXECINSTR | ELFSection::SHF_ALLOC); } + /// Get a constant pool section based on the section name returned by TAI + ELFSection &getConstantPoolSection(std::string SName, unsigned Align) { + return getSection(SName, ELFSection::SHT_PROGBITS, + ELFSection::SHF_MERGE | ELFSection::SHF_ALLOC, Align); + } + /// Return the relocation section of section 'S'. 'RelA' is true /// if the relocation section contains entries with addends. ELFSection &getRelocSection(std::string SName, bool RelA) { From baldrick at free.fr Thu Jun 25 03:19:08 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 25 Jun 2009 10:19:08 +0200 Subject: [llvm-commits] [llvm-gcc-4.2] r74123 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <200906242154.n5OLs3vx003857@zion.cs.uiuc.edu> References: <200906242154.n5OLs3vx003857@zion.cs.uiuc.edu> Message-ID: <4A4332FC.4020004@free.fr> Hi Dale, > More resurrection of int complex. > gcc.c-torture/execute/complex-6.c how about adding a builder method CreateAnyNeg which creates an integer or float negation as appropriate? Ciao, Duncan. > Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=74123&r1=74122&r2=74123&view=diff > > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Jun 24 16:53:10 2009 > @@ -3120,8 +3120,13 @@ > // Handle complex numbers: -(a+ib) = -a + i*-b > Value *R, *I; > EmitLoadFromComplex(R, I, Tmp); > - R = Builder.CreateFNeg(R); > - I = Builder.CreateFNeg(I); > + if (R->getType()->isFloatingPoint()) { > + R = Builder.CreateFNeg(R); > + I = Builder.CreateFNeg(I); > + } else { > + R = Builder.CreateNeg(R); > + I = Builder.CreateNeg(I); > + } > EmitStoreToComplex(*DestLoc, R, I); > return 0; > } > @@ -3137,7 +3142,10 @@ > // Handle complex numbers: ~(a+ib) = a + i*-b > Value *R, *I; > EmitLoadFromComplex(R, I, Tmp); > - I = Builder.CreateFNeg(I); > + if (I->getType()->isFloatingPoint()) > + I = Builder.CreateFNeg(I); > + else > + I = Builder.CreateNeg(I); > EmitStoreToComplex(*DestLoc, R, I); > return 0; > } > @@ -4550,6 +4558,8 @@ > return false; > } > > + // This treats everything as unknown, and is minimally defensible as > + // correct, although completely useless. > if (tree_low_cst (ObjSizeTree, 0) < 2) > Result = ConstantInt::getAllOnesValue(TD.getIntPtrType()); > else > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Thu Jun 25 03:20:37 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 25 Jun 2009 10:20:37 +0200 Subject: [llvm-commits] [llvm] r74129 - /llvm/trunk/lib/Analysis/IPA/Andersens.cpp In-Reply-To: <200906242216.n5OMGrdb004695@zion.cs.uiuc.edu> References: <200906242216.n5OMGrdb004695@zion.cs.uiuc.edu> Message-ID: <4A433355.90405@free.fr> Hi Owen, > // Timestamp a node (used for work list prioritization) > void Stamp() { > - Timestamp = Counter++; > + Timestamp = Counter; > + sys::AtomicIncrement(&Counter); does it matter if different threads have the same value for Timestamp? Ciao, Duncan. From baldrick at free.fr Thu Jun 25 03:25:01 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 25 Jun 2009 10:25:01 +0200 Subject: [llvm-commits] [llvm] r74130 - in /llvm/trunk/include/llvm: CodeGen/ValueTypes.h Target/TargetLowering.h In-Reply-To: <200906242222.n5OMM4MJ004873@zion.cs.uiuc.edu> References: <200906242222.n5OMM4MJ004873@zion.cs.uiuc.edu> Message-ID: <4A43345D.90801@free.fr> Hi David, > // This is the current maximum for LAST_VALUETYPE. > // Affects ValueTypeActions in TargetLowering.h. I don't think this "Affects ValueTypeActions..." comment should be here. Better to have places that use MAX_ALLOWED_VALUETYPE use it in a clear way that can be found by searching. In fact if you search you will find ValueTypeActions already... Also, the comment is already out of date (OpActions is also affected). Ciao, Duncan. From baldrick at free.fr Thu Jun 25 03:26:52 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 25 Jun 2009 10:26:52 +0200 Subject: [llvm-commits] [llvm] r74134 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter/DwarfDebug.cpp In-Reply-To: <200906242253.n5OMrmA7005859@zion.cs.uiuc.edu> References: <200906242253.n5OMrmA7005859@zion.cs.uiuc.edu> Message-ID: <4A4334CC.8080708@free.fr> Hi Owen, for someone who doesn't like statics... > Down with statics! ... > + > + // Private state for dump() > + static unsigned IndentLevel; ... you just introduced one! Ciao, Duncan. From resistor at mac.com Thu Jun 25 03:33:45 2009 From: resistor at mac.com (Owen Anderson) Date: Thu, 25 Jun 2009 01:33:45 -0700 Subject: [llvm-commits] [llvm] r74129 - /llvm/trunk/lib/Analysis/IPA/Andersens.cpp In-Reply-To: <4A433355.90405@free.fr> References: <200906242216.n5OMGrdb004695@zion.cs.uiuc.edu> <4A433355.90405@free.fr> Message-ID: <98E33B2F-8BF6-4F81-924C-8DED1089E895@mac.com> On Jun 25, 2009, at 1:20 AM, Duncan Sands wrote: > Hi Owen, > >> // Timestamp a node (used for work list prioritization) >> void Stamp() { >> - Timestamp = Counter++; >> + Timestamp = Counter; >> + sys::AtomicIncrement(&Counter); > > does it matter if different threads have the same value for Timestamp? No. Really, the counter could be per-thread, but this solution was simpler to implement. --Owen -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 2620 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090625/029c3937/attachment.bin From sanjiv.gupta at microchip.com Thu Jun 25 06:03:26 2009 From: sanjiv.gupta at microchip.com (Sanjiv Gupta) Date: Thu, 25 Jun 2009 11:03:26 -0000 Subject: [llvm-commits] [llvm] r74172 - in /llvm/trunk: include/llvm/CodeGen/MachineInstrBuilder.h lib/Target/PIC16/PIC16MemSelOpt.cpp Message-ID: <200906251103.n5PB3ScC008835@zion.cs.uiuc.edu> Author: sgupta Date: Thu Jun 25 06:03:14 2009 New Revision: 74172 URL: http://llvm.org/viewvc/llvm-project?rev=74172&view=rev Log: Identify unconditional gotos and generate a page sel instructions before them. Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h llvm/trunk/lib/Target/PIC16/PIC16MemSelOpt.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=74172&r1=74171&r2=74172&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Thu Jun 25 06:03:14 2009 @@ -133,6 +133,8 @@ if (MO.isGlobal()) return addGlobalAddress(MO.getGlobal(), MO.getOffset(), MO.getTargetFlags()); + if (MO.isMBB()) + return addMBB(MO.getMBB()); if (MO.isCPI()) return addConstantPoolIndex(MO.getIndex(), MO.getOffset(), MO.getTargetFlags()); Modified: llvm/trunk/lib/Target/PIC16/PIC16MemSelOpt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16MemSelOpt.cpp?rev=74172&r1=74171&r2=74172&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16MemSelOpt.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16MemSelOpt.cpp Thu Jun 25 06:03:14 2009 @@ -109,7 +109,7 @@ // If this insn is not going to access any memory, return. const TargetInstrDesc &TID = TII->get(MI->getOpcode()); - if (! (TID.isCall() || TID.mayLoad() || TID.mayStore())) + if (!(TID.isBranch() || TID.isCall() || TID.mayLoad() || TID.mayStore())) return false; // Scan for the memory address operand. @@ -119,8 +119,9 @@ for (unsigned i = 0; i < NumOperands; i++) { MachineOperand Op = MI->getOperand(i); if (Op.getType() == MachineOperand::MO_GlobalAddress || - Op.getType() == MachineOperand::MO_ExternalSymbol) { - // We found one mem operand. Next one should be BS. + Op.getType() == MachineOperand::MO_ExternalSymbol || + Op.getType() == MachineOperand::MO_MachineBasicBlock) { + // We found one mem operand. Next one may be BS. MemOpPos = i; break; } @@ -133,7 +134,8 @@ MachineOperand &Op = MI->getOperand(MemOpPos); // If this is a pagesel material, handle it first. - if (MI->getOpcode() == PIC16::CALL) { + if (MI->getOpcode() == PIC16::CALL || + MI->getOpcode() == PIC16::br_uncond) { DebugLoc dl = MI->getDebugLoc(); BuildMI(*MBB, MI, dl, TII->get(PIC16::pagesel)). addOperand(Op); From xerxes at zafena.se Thu Jun 25 06:12:57 2009 From: xerxes at zafena.se (=?ISO-8859-1?Q?Xerxes_R=E5nby?=) Date: Thu, 25 Jun 2009 13:12:57 +0200 Subject: [llvm-commits] [patch] fix linking of llvm-ld and lli with cmake Message-ID: <4A435BB9.5050307@zafena.se> The problem: Linking CXX executable ../../bin/llvm-ld ../../lib/libLLVMTransformUtils.a(LCSSA.cpp.o): In function `llvm::PredIteratorCache::~PredIteratorCache()': LCSSA.cpp:(.text._ZN4llvm17PredIteratorCacheD1Ev[llvm::PredIteratorCache::~PredIteratorCache()]+0x11): undefined reference to `llvm::BumpPtrAllocator::~BumpPtrAllocator()' ... ../../lib/libLLVMAnalysis.a(DebugInfo.cpp.o): In function `llvm::DIDescriptor::dump() const': DebugInfo.cpp:(.text+0x1e7e): undefined reference to `llvm::dwarf::TagString(unsigned int)' ... Linking CXX executable ../../bin/lli ../../lib/libLLVMCodeGen.a(LLVMTargetMachine.cpp.o): In function `llvm::LLVMTargetMachine::addCommonCodeGenPasses(llvm::PassManagerBase&, llvm::CodeGenOpt::Level)': LLVMTargetMachine.cpp:(.text+0x914): undefined reference to `llvm::createPrintFunctionPass(std::basic_string, std::allocator > const&, llvm::raw_ostream*, bool)' ... ../../lib/libLLVMScalarOpts.a(CodeGenPrepare.cpp.o): In function `llvm::operator<<(llvm::BaseStream > >&, llvm::ExtAddrMode const&)': CodeGenPrepare.cpp:(.text+0x8a4): undefined reference to `llvm::ExtAddrMode::print(llvm::BaseStream > >&) const' This was quite odd since both libLLVMSupport.a and libLLVMTransformUtils.a got passed to the linker: nm -A lib/*.a | c++filt | grep llvm::BumpPtrAllocator::~BumpPtrAllocator .. lib/libLLVMSupport.a:Allocator.cpp.o:000004f6 T llvm::BumpPtrAllocator::~BumpPtrAllocator() lib/libLLVMSupport.a:Allocator.cpp.o:00000508 T llvm::BumpPtrAllocator::~BumpPtrAllocator() lib/libLLVMTransformUtils.a:LCSSA.cpp.o: U llvm::BumpPtrAllocator::~BumpPtrAllocator() by analysing the generated library .a archives it was clear the methods existed yet the linker tried to combine the librarys in the wrong order. remember that linkers never look back to see if a new undefined symbol existed in a file it had allready processed. thus if libLLVMSupport.a are passed to the linker before libLLVMTransformUtils.a then the linker will fail saying libLLVMTransformUtils.a have missing symbols. The solution: add target_link_libraries dependencies to the libraries so that cmake can figure out in what order the librarys should be passed to the linker. This patch includes only whats needed to compleatly build llvm using cmake. Cheers Xerxes -------------- next part -------------- A non-text attachment was scrubbed... Name: cmake_dependencies.patch Type: text/x-patch Size: 1930 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090625/477a0da1/attachment.bin From xerxes at zafena.se Thu Jun 25 07:48:03 2009 From: xerxes at zafena.se (=?ISO-8859-1?Q?Xerxes_R=E5nby?=) Date: Thu, 25 Jun 2009 14:48:03 +0200 Subject: [llvm-commits] [patch] reenable llvm-config for cmake builds Message-ID: <4A437203.1020005@zafena.se> Hi llvm-config are used by various projects like OpenJDK and OpenEmbedded when using llvm built using cmake. Since llvm-config builds fine (works for me) would it be ok to reenable it for cmake builds? Tested on llvm r74172 with http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090622/079429.html patch applied. Cheers Xerxes -------------- next part -------------- A non-text attachment was scrubbed... Name: enable_llvm_config.cmake.patch Type: text/x-patch Size: 628 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090625/5204c082/attachment.bin From criswell at uiuc.edu Thu Jun 25 09:32:29 2009 From: criswell at uiuc.edu (John Criswell) Date: Thu, 25 Jun 2009 14:32:29 -0000 Subject: [llvm-commits] [poolalloc] r74174 - in /poolalloc/trunk: include/poolalloc_runtime/Support/SplayTree.h lib/DSA/Printer.cpp Message-ID: <200906251432.n5PEWWo5016003@zion.cs.uiuc.edu> Author: criswell Date: Thu Jun 25 09:32:15 2009 New Revision: 74174 URL: http://llvm.org/viewvc/llvm-project?rev=74174&view=rev Log: Updated to the new LLVM API for the GraphWriter class. Added comments to a splay tree method. Modified: poolalloc/trunk/include/poolalloc_runtime/Support/SplayTree.h poolalloc/trunk/lib/DSA/Printer.cpp Modified: poolalloc/trunk/include/poolalloc_runtime/Support/SplayTree.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/poolalloc_runtime/Support/SplayTree.h?rev=74174&r1=74173&r2=74174&view=diff ============================================================================== --- poolalloc/trunk/include/poolalloc_runtime/Support/SplayTree.h (original) +++ poolalloc/trunk/include/poolalloc_runtime/Support/SplayTree.h Thu Jun 25 09:32:15 2009 @@ -254,6 +254,10 @@ // start - The first valid address of the object. // end - The last valid address of the object. // + // Return value: + // true - The insert succeeded. + // false - The insert failed. + // bool insert(void* start, void* end) { return 0 != Tree.__insert(start,end); } Modified: poolalloc/trunk/lib/DSA/Printer.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Printer.cpp?rev=74174&r1=74173&r2=74174&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/Printer.cpp (original) +++ poolalloc/trunk/lib/DSA/Printer.cpp Thu Jun 25 09:32:15 2009 @@ -120,7 +120,8 @@ } } - static std::string getNodeLabel(const DSNode *Node, const DSGraph *Graph) { + static std::string + getNodeLabel(const DSNode *Node, const DSGraph *Graph, bool ShortNames) { return getCaption(Node, Graph); } @@ -243,7 +244,7 @@ } // end namespace llvm void DSNode::print(std::ostream &O, const DSGraph *G) const { - GraphWriter W(O, G); + GraphWriter W(O, G, false); W.writeNode(this); } From andrelct at dcc.ufmg.br Thu Jun 25 07:59:49 2009 From: andrelct at dcc.ufmg.br (Andre Tavares) Date: Thu, 25 Jun 2009 09:59:49 -0300 Subject: [llvm-commits] SSI patch Message-ID: <4A4374C5.7090508@dcc.ufmg.br> Hello, I'm submiting a patch that will be responsible to create SSI representation on demand. This representation conforms with the current SSA, and will not break other optimizations. It only inserts some phi functions on the code. A brief description is below, and the code is attached. // This pass converts a list of variables to the Static Single Information // form. This is a program representation described by Scott Ananian in his // Master Thesis: "The Static Single Information Form (1999)". // We are building an on-demand representation, that is, we do not convert // every single variable in the target function to SSI form. Rather, we receive // a list of target variables that must be converted. We also do not // completely convert a target variable to the SSI format. Instead, we only // change the variable in the points where new information can be attached // to its live range, that is, at branch points. -- Andre Tavares Master Student in Computer Science - UFMG - Brasil http://dcc.ufmg.br/~andrelct -------------- next part -------------- A non-text attachment was scrubbed... Name: SSI_And.cpp Type: text/x-c++src Size: 12790 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090625/01cd26c4/attachment.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: SSI_And.h Type: text/x-chdr Size: 3602 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090625/01cd26c4/attachment-0001.bin From bob.wilson at apple.com Thu Jun 25 11:03:10 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 25 Jun 2009 16:03:10 -0000 Subject: [llvm-commits] [llvm] r74176 - /llvm/trunk/lib/Target/ARM/ARMSubtarget.h Message-ID: <200906251603.n5PG3BhW019031@zion.cs.uiuc.edu> Author: bwilson Date: Thu Jun 25 11:03:07 2009 New Revision: 74176 URL: http://llvm.org/viewvc/llvm-project?rev=74176&view=rev Log: Revert 74164. We'll want to use this method later. Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=74176&r1=74175&r2=74176&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Jun 25 11:03:07 2009 @@ -93,6 +93,7 @@ bool hasV5TOps() const { return ARMArchVersion >= V5T; } bool hasV5TEOps() const { return ARMArchVersion >= V5TE; } bool hasV6Ops() const { return ARMArchVersion >= V6; } + bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } bool hasV7Ops() const { return ARMArchVersion >= V7A; } bool hasVFP2() const { return ARMFPUType >= VFPv2; } From bob.wilson at apple.com Thu Jun 25 11:03:46 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 25 Jun 2009 09:03:46 -0700 Subject: [llvm-commits] [llvm] r74164 - /llvm/trunk/lib/Target/ARM/ARMSubtarget.h In-Reply-To: References: <200906250520.n5P5KXqF018529@zion.cs.uiuc.edu> Message-ID: That's a good point. I wasn't aware of those instructions, but I see them now. I'll revert the change. The one place I had seen this method used was in the change that I backed out earlier to avoid relying on MOVT in ARM mode. Since MOVT is only available in V6T2 and later, I see now that this is exactly the right thing to check, and we'll want it back when we add the MOVT support in ARM mode. On Jun 24, 2009, at 11:30 PM, Evan Cheng wrote: > I am not sure about this. Some ARM instructions are only available > when Thumb2 is available. But using hasThumb2() predicate in ARM mode > just seem strange. > > How about leaving the predicate in but change it to "return > ARMArchVersion >= V6 && ThumbMode >= Thumb2"? > > Evan > > On Jun 24, 2009, at 10:20 PM, Bob Wilson wrote: > >> Author: bwilson >> Date: Thu Jun 25 00:20:31 2009 >> New Revision: 74164 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=74164&view=rev >> Log: >> Remove unused hasV6T2Ops method. We already have a separate feature >> to >> identify Thumb2. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMSubtarget.h >> >> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=74164&r1=74163&r2=74164&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) >> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Jun 25 00:20:31 2009 >> @@ -93,7 +93,6 @@ >> bool hasV5TOps() const { return ARMArchVersion >= V5T; } >> bool hasV5TEOps() const { return ARMArchVersion >= V5TE; } >> bool hasV6Ops() const { return ARMArchVersion >= V6; } >> - bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } >> bool hasV7Ops() const { return ARMArchVersion >= V7A; } >> >> bool hasVFP2() const { return ARMFPUType >= VFPv2; } >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bruno.cardoso at gmail.com Thu Jun 25 11:29:41 2009 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 25 Jun 2009 13:29:41 -0300 Subject: [llvm-commits] SSI patch In-Reply-To: <4A4374C5.7090508@dcc.ufmg.br> References: <4A4374C5.7090508@dcc.ufmg.br> Message-ID: <275e64e40906250929y12d1341t33a6e53174df9ebb@mail.gmail.com> Hi Andre, On Thu, Jun 25, 2009 at 9:59 AM, Andre Tavares wrote: > Hello, > > I'm submiting a patch that will be responsible to create SSI representation > on demand. This representation conforms with the current SSA, and will not > break other optimizations. It only inserts some phi functions on the code. A > brief description is below, and the code is attached. > > // This pass converts a list of variables to the Static Single Information > // form. This is a program representation described by Scott Ananian in his > // Master Thesis: "The Static Single Information Form (1999)". > // We are building an on-demand representation, that is, we do not convert > // every single variable in the target function to SSI form. Rather, we > receive > // a list of target variables that must be converted. We also do not > // completely convert a target variable to the SSI format. Instead, we only > // change the variable in the points where new information can be attached > // to its live range, that is, at branch points. Just some coding style comments, lines not within 80 columns: SSI_And.cpp 78: /// Insert sigma functions (a sigma function is a phi function with one operator) 236: for (DomTreeNode::iterator begin = DTN->begin(); begin != DTN->end(); ++begin) { 253: /// Substitute any use in this instruction for the last definition of the variable SSI_And.h 23: // (either it has virtual methods or it derives from classes with virtual methods), -- Bruno Cardoso Lopes http://www.brunocardoso.cc From resistor at mac.com Thu Jun 25 11:32:52 2009 From: resistor at mac.com (Owen Anderson) Date: Thu, 25 Jun 2009 16:32:52 -0000 Subject: [llvm-commits] [llvm] r74178 - /llvm/trunk/lib/Analysis/IPA/Andersens.cpp Message-ID: <200906251632.n5PGWqRS020056@zion.cs.uiuc.edu> Author: resistor Date: Thu Jun 25 11:32:45 2009 New Revision: 74178 URL: http://llvm.org/viewvc/llvm-project?rev=74178&view=rev Log: Use a more correct atomic increment style. This isn't really necessary in this case, but it should help avoid issues in the future. Modified: llvm/trunk/lib/Analysis/IPA/Andersens.cpp Modified: llvm/trunk/lib/Analysis/IPA/Andersens.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/Andersens.cpp?rev=74178&r1=74177&r2=74178&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/Andersens.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/Andersens.cpp Thu Jun 25 11:32:45 2009 @@ -285,8 +285,8 @@ // Timestamp a node (used for work list prioritization) void Stamp() { - Timestamp = Counter; - sys::AtomicIncrement(&Counter); + Timestamp = sys::AtomicIncrement(&Counter); + --Timestamp; } bool isRep() const { From resistor at mac.com Thu Jun 25 11:55:48 2009 From: resistor at mac.com (Owen Anderson) Date: Thu, 25 Jun 2009 16:55:48 -0000 Subject: [llvm-commits] [llvm] r74179 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp Message-ID: <200906251655.n5PGtnQP021050@zion.cs.uiuc.edu> Author: resistor Date: Thu Jun 25 11:55:32 2009 New Revision: 74179 URL: http://llvm.org/viewvc/llvm-project?rev=74179&view=rev Log: Privatize some more debug-related static data. Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=74179&r1=74178&r2=74179&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Thu Jun 25 11:55:32 2009 @@ -114,6 +114,9 @@ mutable const MachineInstr *LastMI; mutable const Function *LastFn; mutable unsigned Counter; + + // Private state for processDebugLock() + mutable DebugLocTuple PrevDLT; protected: explicit AsmPrinter(raw_ostream &o, TargetMachine &TM, Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=74179&r1=74178&r2=74179&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Jun 25 11:55:32 2009 @@ -45,7 +45,8 @@ const TargetAsmInfo *T, CodeGenOpt::Level OL, bool VDef) : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o), TM(tm), TAI(T), TRI(tm.getRegisterInfo()), - IsInTextSection(false), LastMI(0), LastFn(0), Counter(~0U) { + IsInTextSection(false), LastMI(0), LastFn(0), Counter(~0U), + PrevDLT(0, ~0U, ~0U) { DW = 0; MMI = 0; switch (AsmVerbose) { case cl::BOU_UNSET: VerboseAsm = VDef; break; @@ -1338,7 +1339,6 @@ void AsmPrinter::processDebugLoc(DebugLoc DL) { if (TAI->doesSupportDebugInformation() && DW->ShouldEmitDwarfDebug()) { if (!DL.isUnknown()) { - static DebugLocTuple PrevDLT(0, ~0U, ~0U); DebugLocTuple CurDLT = MF->getDebugLocTuple(DL); if (CurDLT.CompileUnit != 0 && PrevDLT != CurDLT) From dalej at apple.com Thu Jun 25 11:58:23 2009 From: dalej at apple.com (Dale Johannesen) Date: Thu, 25 Jun 2009 09:58:23 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r74123 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <4A4332FC.4020004@free.fr> References: <200906242154.n5OLs3vx003857@zion.cs.uiuc.edu> <4A4332FC.4020004@free.fr> Message-ID: On Jun 25, 2009, at 1:19 AMPDT, Duncan Sands wrote: > Hi Dale, > >> More resurrection of int complex. >> gcc.c-torture/execute/complex-6.c > > how about adding a builder method CreateAnyNeg which > creates an integer or float negation as appropriate? We had that when Neg could be either int or float. I think I'll leave this for the guy who decided splitting off FNeg was a good idea, if he wants to. > Ciao, > > Duncan. > >> Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=74123&r1=74122&r2=74123&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) >> +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Jun 24 16:53:10 2009 >> @@ -3120,8 +3120,13 @@ >> // Handle complex numbers: -(a+ib) = -a + i*-b >> Value *R, *I; >> EmitLoadFromComplex(R, I, Tmp); >> - R = Builder.CreateFNeg(R); >> - I = Builder.CreateFNeg(I); >> + if (R->getType()->isFloatingPoint()) { >> + R = Builder.CreateFNeg(R); >> + I = Builder.CreateFNeg(I); >> + } else { >> + R = Builder.CreateNeg(R); >> + I = Builder.CreateNeg(I); >> + } >> EmitStoreToComplex(*DestLoc, R, I); >> return 0; >> } >> @@ -3137,7 +3142,10 @@ >> // Handle complex numbers: ~(a+ib) = a + i*-b >> Value *R, *I; >> EmitLoadFromComplex(R, I, Tmp); >> - I = Builder.CreateFNeg(I); >> + if (I->getType()->isFloatingPoint()) >> + I = Builder.CreateFNeg(I); >> + else >> + I = Builder.CreateNeg(I); >> EmitStoreToComplex(*DestLoc, R, I); >> return 0; >> } >> @@ -4550,6 +4558,8 @@ >> return false; >> } >> >> + // This treats everything as unknown, and is minimally >> defensible as >> + // correct, although completely useless. >> if (tree_low_cst (ObjSizeTree, 0) < 2) >> Result = ConstantInt::getAllOnesValue(TD.getIntPtrType()); >> else >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Thu Jun 25 12:01:08 2009 From: resistor at mac.com (Owen Anderson) Date: Thu, 25 Jun 2009 10:01:08 -0700 Subject: [llvm-commits] SSI patch In-Reply-To: <4A4374C5.7090508@dcc.ufmg.br> References: <4A4374C5.7090508@dcc.ufmg.br> Message-ID: <9B69C6B6-6AB1-406D-B02F-63981BE4725D@mac.com> Andre, A general comment: please, PLEASE avoid using (mutable) global data. All data used by your pass should be instance data of the pass object. You can use the releaseMemory() method to clean up after yourself, if need be. Thanks, --Owen On Jun 25, 2009, at 5:59 AM, Andre Tavares wrote: > Hello, > > I'm submiting a patch that will be responsible to create SSI > representation on demand. This representation conforms with the > current SSA, and will not break other optimizations. It only inserts > some phi functions on the code. A brief description is below, and > the code is attached. > > // This pass converts a list of variables to the Static Single > Information > // form. This is a program representation described by Scott Ananian > in his > // Master Thesis: "The Static Single Information Form (1999)". > // We are building an on-demand representation, that is, we do not > convert > // every single variable in the target function to SSI form. Rather, > we receive > // a list of target variables that must be converted. We also do not > // completely convert a target variable to the SSI format. Instead, > we only > // change the variable in the points where new information can be > attached > // to its live range, that is, at branch points. > > -- > Andre Tavares > Master Student in Computer Science - UFMG - Brasil > http://dcc.ufmg.br/~andrelct > > < > SSI_And.cpp>_______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Thu Jun 25 12:09:04 2009 From: resistor at mac.com (Owen Anderson) Date: Thu, 25 Jun 2009 17:09:04 -0000 Subject: [llvm-commits] [llvm] r74180 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200906251709.n5PH95II021631@zion.cs.uiuc.edu> Author: resistor Date: Thu Jun 25 12:09:00 2009 New Revision: 74180 URL: http://llvm.org/viewvc/llvm-project?rev=74180&view=rev Log: Provide guards for this shared structure. I'm not sure this actually needs to be shared, but how/where to privatize it is not immediately clear to me. If any SelectionDAG experts see a better solution, please share! Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=74180&r1=74179&r2=74180&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jun 25 12:09:00 2009 @@ -31,8 +31,10 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/ManagedStatic.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/System/Mutex.h" #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallSet.h" @@ -4977,14 +4979,17 @@ AddNodeIDNode(ID, this); } +static ManagedStatic > EVTs; +static MVT VTs[MVT::LAST_VALUETYPE]; +static ManagedStatic > VTMutex; + /// getValueTypeList - Return a pointer to the specified value type. /// const MVT *SDNode::getValueTypeList(MVT VT) { + sys::SmartScopedLock Lock(&*VTMutex); if (VT.isExtended()) { - static std::set EVTs; - return &(*EVTs.insert(VT).first); + return &(*EVTs->insert(VT).first); } else { - static MVT VTs[MVT::LAST_VALUETYPE]; VTs[VT.getSimpleVT()] = VT; return &VTs[VT.getSimpleVT()]; } From sabre at nondot.org Thu Jun 25 12:21:45 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 25 Jun 2009 17:21:45 -0000 Subject: [llvm-commits] [llvm] r74181 - /llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Message-ID: <200906251721.n5PHLkVQ022134@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 25 12:21:32 2009 New Revision: 74181 URL: http://llvm.org/viewvc/llvm-project?rev=74181&view=rev Log: Clone target flags when copying mbb operands. Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=74181&r1=74180&r2=74181&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Thu Jun 25 12:21:32 2009 @@ -134,7 +134,7 @@ return addGlobalAddress(MO.getGlobal(), MO.getOffset(), MO.getTargetFlags()); if (MO.isMBB()) - return addMBB(MO.getMBB()); + return addMBB(MO.getMBB(), MO.getTargetFlags()); if (MO.isCPI()) return addConstantPoolIndex(MO.getIndex(), MO.getOffset(), MO.getTargetFlags()); From sabre at nondot.org Thu Jun 25 12:28:08 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 25 Jun 2009 17:28:08 -0000 Subject: [llvm-commits] [llvm] r74183 - in /llvm/trunk: include/llvm/CodeGen/MachineInstrBuilder.h lib/Target/X86/X86InstrInfo.cpp Message-ID: <200906251728.n5PHS97f022455@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 25 12:28:07 2009 New Revision: 74183 URL: http://llvm.org/viewvc/llvm-project?rev=74183&view=rev Log: just eliminate the code entirely! Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=74183&r1=74182&r2=74183&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Thu Jun 25 12:28:07 2009 @@ -118,34 +118,7 @@ } const MachineInstrBuilder &addOperand(const MachineOperand &MO) const { - if (MO.isReg()) - return addReg(MO.getReg(), - (MO.isDef() ? RegState::Define : 0) | - (MO.isImplicit() ? RegState::Implicit : 0) | - (MO.isKill() ? RegState::Kill : 0) | - (MO.isDead() ? RegState::Dead : 0) | - (MO.isEarlyClobber() ? RegState::EarlyClobber : 0), - MO.getSubReg()); - if (MO.isImm()) - return addImm(MO.getImm()); - if (MO.isFI()) - return addFrameIndex(MO.getIndex()); - if (MO.isGlobal()) - return addGlobalAddress(MO.getGlobal(), MO.getOffset(), - MO.getTargetFlags()); - if (MO.isMBB()) - return addMBB(MO.getMBB(), MO.getTargetFlags()); - if (MO.isCPI()) - return addConstantPoolIndex(MO.getIndex(), MO.getOffset(), - MO.getTargetFlags()); - if (MO.isSymbol()) - return addExternalSymbol(MO.getSymbolName(), MO.getOffset(), - MO.getTargetFlags()); - if (MO.isJTI()) - return addJumpTableIndex(MO.getIndex(), - MO.getTargetFlags()); - - assert(0 && "Unknown operand for MachineInstrBuilder::AddOperand!"); + MI->addOperand(MO); return *this; } }; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=74183&r1=74182&r2=74183&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Jun 25 12:28:07 2009 @@ -3190,9 +3190,8 @@ bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_); bool Is64BitMode = TM.getSubtargetImpl()->is64Bit(); unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode); - if (Desc.getOpcode() == X86::MOVPC32r) { + if (Desc.getOpcode() == X86::MOVPC32r) Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode); - } return Size; } From sabre at nondot.org Thu Jun 25 12:38:37 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 25 Jun 2009 17:38:37 -0000 Subject: [llvm-commits] [llvm] r74184 - in /llvm/trunk/lib/Target/X86: AsmPrinter/X86ATTAsmPrinter.cpp X86InstrInfo.cpp X86InstrInfo.h Message-ID: <200906251738.n5PHcdwh022788@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 25 12:38:33 2009 New Revision: 74184 URL: http://llvm.org/viewvc/llvm-project?rev=74184&view=rev Log: Use target-specific machine operand flags to eliminate a gross hack from the asmprinter. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.h Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74184&r1=74183&r2=74184&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Thu Jun 25 12:38:33 2009 @@ -405,25 +405,15 @@ O << Name; - if (shouldPrintPLT(TM, Subtarget)) { - std::string GOTName(TAI->getGlobalPrefix()); - GOTName+="_GLOBAL_OFFSET_TABLE_"; - if (Name == GOTName) { - // HACK! Emit extra offset to PC during printing GOT offset to - // compensate for the size of popl instruction. The resulting code - // should look like: - // call .piclabel - // piclabel: - // popl %some_register - // addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register - O << " + [.-"; - PrintPICBaseSymbol(); - O << ']'; - } - - O << "@PLT"; + if (MO.getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) { + O << " + [.-"; + PrintPICBaseSymbol(); + O << ']'; } + if (shouldPrintPLT(TM, Subtarget)) + O << "@PLT"; + if (needCloseParen) O << ')'; @@ -633,21 +623,10 @@ O << Name; - if (shouldPrintPLT(TM, Subtarget)) { - std::string GOTName(TAI->getGlobalPrefix()); - GOTName+="_GLOBAL_OFFSET_TABLE_"; - if (Name == GOTName) { - // HACK! Emit extra offset to PC during printing GOT offset to - // compensate for the size of popl instruction. The resulting code - // should look like: - // call .piclabel - // piclabel: - // popl %some_register - // addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register - O << " + [.-"; - PrintPICBaseSymbol(); - O << ']'; - } + if (MO.getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) { + O << " + [.-"; + PrintPICBaseSymbol(); + O << ']'; } if (needCloseParen) Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=74184&r1=74183&r2=74184&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Jun 25 12:38:33 2009 @@ -3219,17 +3219,17 @@ const TargetInstrInfo *TII = TM.getInstrInfo(); // Operand of MovePCtoStack is completely ignored by asm printer. It's // only used in JIT code emission as displacement to pc. - BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC) - .addImm(0); + BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); // If we're using vanilla 'GOT' PIC style, we should use relative addressing - // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external + // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. if (TM.getRelocationModel() == Reloc::PIC_ && TM.getSubtarget().isPICStyleGOT()) { - GlobalBaseReg = - RegInfo.createVirtualRegister(X86::GR32RegisterClass); + GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass); + // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) - .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_"); + .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 0, + X86II::MO_GOT_ABSOLUTE_ADDRESS); } else { GlobalBaseReg = PC; } Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=74184&r1=74183&r2=74184&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Thu Jun 25 12:38:33 2009 @@ -71,7 +71,18 @@ namespace X86II { enum { //===------------------------------------------------------------------===// - // Instruction types. These are the standard/most common forms for X86 + // X86 Specific MachineOperand flags. + + MO_NO_FLAG = 0, + + /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a + /// relocation of: + /// $SYMBOL_LABEL + [. - PICBASELABEL] + MO_GOT_ABSOLUTE_ADDRESS = 1, + + + //===------------------------------------------------------------------===// + // Instruction encodings. These are the standard/most common forms for X86 // instructions. // From david_goodwin at apple.com Thu Jun 25 12:52:46 2009 From: david_goodwin at apple.com (David Goodwin) Date: Thu, 25 Jun 2009 17:52:46 -0000 Subject: [llvm-commits] [llvm] r74185 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <200906251752.n5PHqpEC023190@zion.cs.uiuc.edu> Author: david_goodwin Date: Thu Jun 25 12:52:32 2009 New Revision: 74185 URL: http://llvm.org/viewvc/llvm-project?rev=74185&view=rev Log: Test commit Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=74185&r1=74184&r2=74185&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Jun 25 12:52:32 2009 @@ -294,7 +294,7 @@ // Arithmetic Instructions. // -// Add with carry +// Add with carry let isCommutable = 1 in def tADC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "adc $dst, $rhs", From sabre at nondot.org Thu Jun 25 12:58:52 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 25 Jun 2009 17:58:52 -0000 Subject: [llvm-commits] [llvm] r74186 - /llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Message-ID: <200906251758.n5PHwrC0023416@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 25 12:58:52 2009 New Revision: 74186 URL: http://llvm.org/viewvc/llvm-project?rev=74186&view=rev Log: simplify shouldPrintPLT Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=74186&r1=74185&r2=74186&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Thu Jun 25 12:58:52 2009 @@ -295,8 +295,7 @@ } static inline bool shouldPrintPLT(TargetMachine &TM, const X86Subtarget* ST) { - return ST->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_ && - (ST->isPICStyleRIPRel() || ST->isPICStyleGOT()); + return ST->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_; } static inline bool shouldPrintStub(TargetMachine &TM, const X86Subtarget* ST) { @@ -331,6 +330,8 @@ } if (shouldPrintStub(TM, Subtarget)) { + // DARWIN/X86-32 in != static mode. + // Link-once, declaration, or Weakly-linked global variables need // non-lazily-resolved stubs if (GV->isDeclaration() || GV->isWeakForLinker()) { @@ -361,9 +362,8 @@ O << Name; } } else { - if (GV->hasDLLImportLinkage()) { + if (GV->hasDLLImportLinkage()) O << "__imp_"; - } O << Name; if (shouldPrintPLT(TM, Subtarget)) { @@ -390,7 +390,9 @@ Name += MO.getSymbolName(); // Print function stub suffix unless it's Mac OS X 10.5 and up. if (shouldPrintStub(TM, Subtarget) && + // DARWIN/X86-32 in != static mode. !(Subtarget->isTargetDarwin() && Subtarget->getDarwinVers() >= 9)) { + FnStubs.insert(Name); printSuffixedName(Name, "$stub"); return; @@ -514,6 +516,8 @@ } if (shouldPrintStub(TM, Subtarget)) { + // DARWIN/X86-32 in != static mode. + // Link-once, declaration, or Weakly-linked global variables need // non-lazily-resolved stubs if (GV->isDeclaration() || GV->isWeakForLinker()) { From nlewycky at google.com Thu Jun 25 13:01:22 2009 From: nlewycky at google.com (Nick Lewycky) Date: Thu, 25 Jun 2009 11:01:22 -0700 Subject: [llvm-commits] SSI patch In-Reply-To: <4A4374C5.7090508@dcc.ufmg.br> References: <4A4374C5.7090508@dcc.ufmg.br> Message-ID: I haven't looked closely at the algorithm yet. What jumped out were a number of stylistic concerns, first of all. We have a number of ADTs in LLVM that we like more than C++ STL ones (see http://llvm.org/docs/ProgrammersManual.html for why). You should use SmallVector instead of std::vector&. For example, "SSI::createSSI(SmallVectorImpl value) {", or possibly make it take an Instruction** and a size. Similarly, std::set is horrible in general, you should make SSI::created be a SmallPtrSet. (Or remove SSI::created entirely in favour of making createSSI take a set and tell the caller they're not allowed to call createSSI on the same value twice.) You declare some global constants which should at least also be static. You shouldn't evaluate X->size() on every iteration of a loop; for example the "for" statement in isUsedInTerminator should be written like "for (unsigned i = 0, e = TI->getNumOperands(); i != e; ++i) {". This is done in a few other places as well. Some of your comments (SSI::insertPhiFunctions) are missing a space after // and before the text. Please add it where missing. // TODO: We do modify the programs code, but we do not know which // Passes we break. void SSI::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired (); AU.addRequired (); AU.setPreservesAll(); } If you don't know what you preserve, don't preserve anything. I think your pass preserves the CFG (you don't modify any TerminatorInsts) so you can mark it AU.setPreservesCFG(). bool SSI::runOnFunction(Function &F) { DT_ = &getAnalysis (); return false; } This runOnFunction doesn't transform anything. That means that if I run "opt -ssi_and_pass" over a .bc then no transform or analysis will happen. That's okay -- opt -scalar-evolution does the same thing -- but if you do this you should also supply a print() method where the pass dumps out what it would have done (the results of its analysis on every variable, in scalar-evolutions case). You can then read it with "opt -analyze -ssi_and_pass". /// Test if the BasicBlock BB dominates any use or definition of value. /// bool SSI::dominateAny(BasicBlock * BB, Instruction * value) { Value::use_iterator begin = value->use_begin(); Value::use_iterator end = value->use_end(); for (; begin != end; ++begin) { Instruction * I = dyn_cast (*begin); Use cast instead of dyn_cast since we know in advance that it must be an Instruction. BasicBlock * BB_father = I->getParent(); if (DT_->dominates(BB, BB_father)) { return true; } } return false; } So overall this looks like a good start. I think we may want to move createSSI out of the pass and into its own lib/Transforms/Utils/SSI.cpp which takes the DominatorTree* and DominatorFrontier*. This method could then be called from any pass without having to declare it in advance in its own analysis usage. Then the SSI pass would then exist for testing purposes; it could do something like either collect the sensible instructions or maybe just all non-void instructions and run createSSI over them. I'll try to do a more thorough review soon. Nick 2009/6/25 Andre Tavares > Hello, > > I'm submiting a patch that will be responsible to create SSI representation > on demand. This representation conforms with the current SSA, and will not > break other optimizations. It only inserts some phi functions on the code. A > brief description is below, and the code is attached. > > // This pass converts a list of variables to the Static Single Information > // form. This is a program representation described by Scott Ananian in his > // Master Thesis: "The Static Single Information Form (1999)". > // We are building an on-demand representation, that is, we do not convert > // every single variable in the target function to SSI form. Rather, we > receive > // a list of target variables that must be converted. We also do not > // completely convert a target variable to the SSI format. Instead, we only > // change the variable in the points where new information can be attached > // to its live range, that is, at branch points. > > -- > Andre Tavares > Master Student in Computer Science - UFMG - Brasil > http://dcc.ufmg.br/~andrelct > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090625/105698a9/attachment.html From sanjiv.gupta at microchip.com Thu Jun 25 13:12:17 2009 From: sanjiv.gupta at microchip.com (Sanjiv Gupta) Date: Thu, 25 Jun 2009 18:12:17 -0000 Subject: [llvm-commits] [llvm] r74187 - /llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Message-ID: <200906251812.n5PICMeS023811@zion.cs.uiuc.edu> Author: sgupta Date: Thu Jun 25 13:12:06 2009 New Revision: 74187 URL: http://llvm.org/viewvc/llvm-project?rev=74187&view=rev Log: Added floating point conditional operations support via libcalls. Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=74187&r1=74186&r2=74187&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Thu Jun 25 13:12:06 2009 @@ -97,6 +97,16 @@ case RTLIB::SUB_F32: Basename = "sub.f32"; break; case RTLIB::MUL_F32: Basename = "mul.f32"; break; case RTLIB::DIV_F32: Basename = "div.f32"; break; + + // Floating point comparison + case RTLIB::O_F32: Basename = "unordered.f32"; break; + case RTLIB::UO_F32: Basename = "unordered.f32"; break; + case RTLIB::OLE_F32: Basename = "le.f32"; break; + case RTLIB::OGE_F32: Basename = "ge.f32"; break; + case RTLIB::OLT_F32: Basename = "lt.f32"; break; + case RTLIB::OGT_F32: Basename = "gt.f32"; break; + case RTLIB::OEQ_F32: Basename = "eq.f32"; break; + case RTLIB::UNE_F32: Basename = "neq.f32"; break; } std::string prefix = PAN::getTagName(PAN::PREFIX_SYMBOL); @@ -187,6 +197,25 @@ setLibcallName(RTLIB::MUL_F32, getIntrinsicName(RTLIB::MUL_F32)); setLibcallName(RTLIB::DIV_F32, getIntrinsicName(RTLIB::DIV_F32)); + // Floationg point comparison + setLibcallName(RTLIB::UO_F32, getIntrinsicName(RTLIB::UO_F32)); + setLibcallName(RTLIB::OLE_F32, getIntrinsicName(RTLIB::OLE_F32)); + setLibcallName(RTLIB::OGE_F32, getIntrinsicName(RTLIB::OGE_F32)); + setLibcallName(RTLIB::OLT_F32, getIntrinsicName(RTLIB::OLT_F32)); + setLibcallName(RTLIB::OGT_F32, getIntrinsicName(RTLIB::OGT_F32)); + setLibcallName(RTLIB::OEQ_F32, getIntrinsicName(RTLIB::OEQ_F32)); + setLibcallName(RTLIB::UNE_F32, getIntrinsicName(RTLIB::UNE_F32)); + + // Return value comparisons of floating point calls. + setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); + setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); + setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); + setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); + setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); + setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); + setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); + setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); + setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom); From resistor at mac.com Thu Jun 25 13:12:45 2009 From: resistor at mac.com (Owen Anderson) Date: Thu, 25 Jun 2009 18:12:45 -0000 Subject: [llvm-commits] [llvm] r74188 - in /llvm/trunk/lib/System: DynamicLibrary.cpp Win32/DynamicLibrary.inc Message-ID: <200906251812.n5PICjLr023833@zion.cs.uiuc.edu> Author: resistor Date: Thu Jun 25 13:12:44 2009 New Revision: 74188 URL: http://llvm.org/viewvc/llvm-project?rev=74188&view=rev Log: Guard dynamic library loading. I did my best at implementing this for Win32, but I don't have a way to test it. Can someone with access to a Win32 machine test/fix this? Modified: llvm/trunk/lib/System/DynamicLibrary.cpp llvm/trunk/lib/System/Win32/DynamicLibrary.inc Modified: llvm/trunk/lib/System/DynamicLibrary.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/DynamicLibrary.cpp?rev=74188&r1=74187&r2=74188&view=diff ============================================================================== --- llvm/trunk/lib/System/DynamicLibrary.cpp (original) +++ llvm/trunk/lib/System/DynamicLibrary.cpp Thu Jun 25 13:12:44 2009 @@ -12,20 +12,22 @@ //===----------------------------------------------------------------------===// #include "llvm/System/DynamicLibrary.h" +#include "llvm/Support/ManagedStatic.h" +#include "llvm/System/RWMutex.h" #include "llvm/Config/config.h" #include #include #include // Collection of symbol name/value pairs to be searched prior to any libraries. -std::map &g_symbols() { - static std::map symbols; - return symbols; -} +static std::map symbols; +static llvm::sys::SmartRWMutex SymbolsLock; + void llvm::sys::DynamicLibrary::AddSymbol(const char* symbolName, void *symbolValue) { - g_symbols()[symbolName] = symbolValue; + llvm::sys::SmartScopedWriter Writer(&SymbolsLock); + symbols[symbolName] = symbolValue; } // It is not possible to use ltdl.c on VC++ builds as the terms of its LGPL @@ -57,6 +59,7 @@ DynamicLibrary::DynamicLibrary() {} DynamicLibrary::~DynamicLibrary() { + SmartScopedWriter Writer(&SymbolsLock); while(!OpenedHandles.empty()) { void *H = OpenedHandles.back(); OpenedHandles.pop_back(); dlclose(H); @@ -65,6 +68,7 @@ bool DynamicLibrary::LoadLibraryPermanently(const char *Filename, std::string *ErrMsg) { + SmartScopedWriter Writer(&SymbolsLock); void *H = dlopen(Filename, RTLD_LAZY|RTLD_GLOBAL); if (H == 0) { if (ErrMsg) @@ -77,20 +81,28 @@ void* DynamicLibrary::SearchForAddressOfSymbol(const char* symbolName) { // check_ltdl_initialization(); - + // First check symbols added via AddSymbol(). - std::map::iterator I = g_symbols().find(symbolName); - if (I != g_symbols().end()) + SymbolsLock.reader_acquire(); + std::map::iterator I = symbols.find(symbolName); + std::map::iterator E = symbols.end(); + SymbolsLock.reader_release(); + + if (I != E) return I->second; + SymbolsLock.writer_acquire(); // Now search the libraries. for (std::vector::iterator I = OpenedHandles.begin(), E = OpenedHandles.end(); I != E; ++I) { //lt_ptr ptr = lt_dlsym(*I, symbolName); void *ptr = dlsym(*I, symbolName); - if (ptr) + if (ptr) { + SymbolsLock.writer_release(); return ptr; + } } + SymbolsLock.writer_release(); #define EXPLICIT_SYMBOL(SYM) \ extern void *SYM; if (!strcmp(symbolName, #SYM)) return &SYM Modified: llvm/trunk/lib/System/Win32/DynamicLibrary.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/DynamicLibrary.inc?rev=74188&r1=74187&r2=74188&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/DynamicLibrary.inc (original) +++ llvm/trunk/lib/System/Win32/DynamicLibrary.inc Thu Jun 25 13:12:44 2009 @@ -67,6 +67,7 @@ PVOID UserContext) #endif { + llvm::sys::SmartScopedWriter Writer(&SymbolsLock); // Ignore VC++ runtimes prior to 7.1. Somehow some of them get loaded // into the process. if (stricmp(ModuleName, "msvci70") != 0 && @@ -89,11 +90,13 @@ } DynamicLibrary::DynamicLibrary() : handle(0) { + SmartScopedWriter Writer(&SymbolsLock); handle = GetModuleHandle(NULL); OpenedHandles.push_back((HMODULE)handle); } DynamicLibrary::~DynamicLibrary() { + llvm::sys::SmartScopedWriter Writer(&SymbolsLock); if (handle == 0) return; @@ -113,8 +116,9 @@ } bool DynamicLibrary::LoadLibraryPermanently(const char *filename, - std::string *ErrMsg) { + std::string *ErrMsg) { if (filename) { + llvm::sys::SmartScopedWriter Writer(&SymbolsLock); HMODULE a_handle = LoadLibrary(filename); if (a_handle == 0) @@ -166,17 +170,24 @@ void* DynamicLibrary::SearchForAddressOfSymbol(const char* symbolName) { // First check symbols added via AddSymbol(). - std::map::iterator I = g_symbols().find(symbolName); - if (I != g_symbols().end()) + SymbolsLock.reader_acquire(); + std::map::iterator I = symbols.find(symbolName); + std::map::iterator E = symbols.end(); + SymbolsLock.reader_release(); + if (I != E) return I->second; // Now search the libraries. + SymbolsLock.writer_acquire(); for (std::vector::iterator I = OpenedHandles.begin(), E = OpenedHandles.end(); I != E; ++I) { FARPROC ptr = GetProcAddress((HMODULE)*I, symbolName); - if (ptr) + if (ptr) { + SymbolsLock.writer_release(); return (void *) ptr; + } } + SymbolsLock.writer_release(); #if defined(__MINGW32__) { From resistor at mac.com Thu Jun 25 13:13:05 2009 From: resistor at mac.com (Owen Anderson) Date: Thu, 25 Jun 2009 18:13:05 -0000 Subject: [llvm-commits] [llvm] r74189 - in /llvm/trunk/lib/Target/Alpha: AlphaJITInfo.cpp AlphaJITInfo.h Message-ID: <200906251813.n5PID6iB023861@zion.cs.uiuc.edu> Author: resistor Date: Thu Jun 25 13:13:04 2009 New Revision: 74189 URL: http://llvm.org/viewvc/llvm-project?rev=74189&view=rev Log: Privatize this map. Modified: llvm/trunk/lib/Target/Alpha/AlphaJITInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaJITInfo.h Modified: llvm/trunk/lib/Target/Alpha/AlphaJITInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaJITInfo.cpp?rev=74189&r1=74188&r2=74189&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaJITInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaJITInfo.cpp Thu Jun 25 13:13:04 2009 @@ -19,7 +19,6 @@ #include "llvm/Config/alloca.h" #include "llvm/Support/Debug.h" #include -#include using namespace llvm; #define BUILD_OFormatI(Op, RA, LIT, FUN, RC) \ @@ -237,11 +236,6 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR, unsigned NumRelocs, unsigned char* GOTBase) { - //because gpdist are paired and relative to the pc of the first inst, - //we need to have some state - - static std::map, void*> gpdistmap; - for (unsigned i = 0; i != NumRelocs; ++i, ++MR) { unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4; long idx = 0; Modified: llvm/trunk/lib/Target/Alpha/AlphaJITInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaJITInfo.h?rev=74189&r1=74188&r2=74189&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaJITInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaJITInfo.h Thu Jun 25 13:13:04 2009 @@ -15,6 +15,7 @@ #define ALPHA_JITINFO_H #include "llvm/Target/TargetJITInfo.h" +#include namespace llvm { class TargetMachine; @@ -22,6 +23,10 @@ class AlphaJITInfo : public TargetJITInfo { protected: TargetMachine &TM; + + //because gpdist are paired and relative to the pc of the first inst, + //we need to have some state + std::map, void*> gpdistmap; public: explicit AlphaJITInfo(TargetMachine &tm) : TM(tm) { useGOT = true; } From resistor at mac.com Thu Jun 25 13:17:57 2009 From: resistor at mac.com (Owen Anderson) Date: Thu, 25 Jun 2009 11:17:57 -0700 Subject: [llvm-commits] SSI patch In-Reply-To: References: <4A4374C5.7090508@dcc.ufmg.br> Message-ID: On Jun 25, 2009, at 11:01 AM, Nick Lewycky wrote: > // TODO: We do modify the programs code, but we do not know which > // Passes we break. > void SSI::getAnalysisUsage(AnalysisUsage &AU) const { > AU.addRequired (); > AU.addRequired (); > AU.setPreservesAll(); > } Actually, since he doesn't do anything in his runOnFunction(), he does, in fact, preserves all passes. It's the client transformation's responsibility to maintain other analyses. This might also be an argument in favor of making this a utility function under lib/ Transforms/Utils rather than a separate pass. Also, he needs to addRequiredTransitively() his dependencies, rather than addRequired(). The former guarantees that they will be around until his pass is destructed, while the latter only guarantees their existence until the end of runOnFunction(). > /// Test if the BasicBlock BB dominates any use or definition of > value. > /// > bool SSI::dominateAny(BasicBlock * BB, Instruction * value) { > Value::use_iterator begin = value->use_begin(); > Value::use_iterator end = value->use_end(); > for (; begin != end; ++begin) { > Instruction * I = dyn_cast (*begin); This function can be much simpler. The only use of an instruction that isn't dominated by the def is a phi-use. So you really only need to check the def itself, and any uses that are also phis. --Owen From ssen at apple.com Thu Jun 25 13:19:04 2009 From: ssen at apple.com (Shantonu Sen) Date: Thu, 25 Jun 2009 11:19:04 -0700 Subject: [llvm-commits] [patch] test suite documentation updates, new "XFAIL: disable_assertions" Message-ID: <0B7C2DE8-1572-42EF-9C4F-0C64FA399EA2@apple.com> I was getting a test suite failure with a Release-Asserts build on test/CodeGen/PowerPC/int-fp-conv-0.ll because it does: > ; RUN: llvm-as < %s | llc -march=ppc64 -debug |& not grep {= store} "llc -debug" is only available when assertions are enabled, so there should be a way to XFAIL this when assertions are disabled. I added this ability to the llvm dejagnu tests, and now the test PASSes for a Debug build, and XFAILs for Release-Asserts. I noticed a bunch of other documentation issues that I ran into, which I expanded on. Chris L. says that --with-f2c hasn't been supported in a while, and should probably be removed, so I did (it also breaks W3C validation of the HTML) Mac OS X has shipped Tcl and expect since 10.4 at least, I don't think it's relevant to recommend ways to install them. Diff attached -------------- next part -------------- A non-text attachment was scrubbed... Name: test-disable-assertions.patch Type: application/octet-stream Size: 8141 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090625/14d60d12/attachment.obj -------------- next part -------------- Shantonu Sen ssen at apple.com Sent from my Mac Pro From foldr at codedgers.com Thu Jun 25 13:20:11 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Thu, 25 Jun 2009 18:20:11 -0000 Subject: [llvm-commits] [llvm] r74190 - in /llvm/trunk: include/llvm/CompilerDriver/BuiltinOptions.h include/llvm/CompilerDriver/Main.inc lib/CompilerDriver/Action.cpp lib/CompilerDriver/CompilationGraph.cpp lib/CompilerDriver/Tool.cpp Message-ID: <200906251820.n5PIKBfK024084@zion.cs.uiuc.edu> Author: foldr Date: Thu Jun 25 13:20:10 2009 New Revision: 74190 URL: http://llvm.org/viewvc/llvm-project?rev=74190&view=rev Log: Make -save-temps behave like in GCC 4.5. The -save-temps option now behaves like described in GCC 4.5 release notes (you can specify output directory for temporary files with -save-temps=obj -o $DIRNAME). I do not have GCC 4.5 installed, so if there are any inconsistencies between llvmc and GCC in the implementation of this feature, please let me know. Added: llvm/trunk/include/llvm/CompilerDriver/BuiltinOptions.h Modified: llvm/trunk/include/llvm/CompilerDriver/Main.inc llvm/trunk/lib/CompilerDriver/Action.cpp llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp llvm/trunk/lib/CompilerDriver/Tool.cpp Added: llvm/trunk/include/llvm/CompilerDriver/BuiltinOptions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CompilerDriver/BuiltinOptions.h?rev=74190&view=auto ============================================================================== --- llvm/trunk/include/llvm/CompilerDriver/BuiltinOptions.h (added) +++ llvm/trunk/include/llvm/CompilerDriver/BuiltinOptions.h Thu Jun 25 13:20:10 2009 @@ -0,0 +1,33 @@ +//===--- BuiltinOptions.h - The LLVM Compiler Driver ------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open +// Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Declarations of all global command-line option variables. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_INCLUDE_COMPILER_DRIVER_BUILTIN_OPTIONS_H +#define LLVM_INCLUDE_COMPILER_DRIVER_BUILTIN_OPTIONS_H + +#include "llvm/Support/CommandLine.h" + +#include + +namespace SaveTempsEnum { enum Values { Cwd, Obj, Unset }; } + +extern llvm::cl::list InputFilenames; +extern llvm::cl::opt OutputFilename; +extern llvm::cl::list Languages; +extern llvm::cl::opt DryRun; +extern llvm::cl::opt VerboseMode; +extern llvm::cl::opt CheckGraph; +extern llvm::cl::opt WriteGraph; +extern llvm::cl::opt ViewGraph; +extern llvm::cl::opt SaveTemps; + +#endif // LLVM_INCLUDE_COMPILER_DRIVER_BUILTIN_OPTIONS_H Modified: llvm/trunk/include/llvm/CompilerDriver/Main.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CompilerDriver/Main.inc?rev=74190&r1=74189&r2=74190&view=diff ============================================================================== --- llvm/trunk/include/llvm/CompilerDriver/Main.inc (original) +++ llvm/trunk/include/llvm/CompilerDriver/Main.inc Thu Jun 25 13:20:10 2009 @@ -17,6 +17,7 @@ #ifndef LLVM_INCLUDE_COMPILER_DRIVER_MAIN_INC #define LLVM_INCLUDE_COMPILER_DRIVER_MAIN_INC +#include "llvm/CompilerDriver/BuiltinOptions.h" #include "llvm/CompilerDriver/CompilationGraph.h" #include "llvm/CompilerDriver/Error.h" #include "llvm/CompilerDriver/ForceLinkage.h" @@ -58,27 +59,56 @@ cl::opt ViewGraph("view-graph", cl::desc("Show compilation graph in GhostView"), cl::Hidden); -cl::opt SaveTemps("save-temps", - cl::desc("Keep temporary files"), - cl::Hidden); + +cl::opt SaveTemps +("save-temps", cl::desc("Keep temporary files"), + cl::init(SaveTempsEnum::Unset), + cl::values(clEnumValN(SaveTempsEnum::Obj, "obj", + "Save files in the directory specified with -o"), + clEnumValN(SaveTempsEnum::Cwd, "cwd", + "Use current working directory"), + clEnumValN(SaveTempsEnum::Obj, "", "Same as 'cwd'"), + clEnumValEnd), + cl::ValueOptional); namespace { + + sys::Path getTempDir() { + sys::Path tempDir; + + // GCC 4.5-style -save-temps handling. + if (SaveTemps == SaveTempsEnum::Unset) { + tempDir = sys::Path::GetTemporaryDirectory(); + } + else if (SaveTemps == SaveTempsEnum::Obj && !OutputFilename.empty()) { + tempDir = OutputFilename; + + if (!tempDir.exists()) { + std::string ErrMsg; + if (tempDir.createDirectoryOnDisk(true, &ErrMsg)) + throw std::runtime_error(ErrMsg); + } + } + // else if (SaveTemps == Cwd) -> use current dir (leave tempDir empty) + + return tempDir; + } + /// BuildTargets - A small wrapper for CompilationGraph::Build. int BuildTargets(CompilationGraph& graph, const LanguageMap& langMap) { int ret; - const sys::Path& tempDir = SaveTemps - ? sys::Path("") - : sys::Path(sys::Path::GetTemporaryDirectory()); + const sys::Path& tempDir = getTempDir(); try { ret = graph.Build(tempDir, langMap); } catch(...) { - tempDir.eraseFromDisk(true); + if (SaveTemps == SaveTempsEnum::Unset) + tempDir.eraseFromDisk(true); throw; } - if (!SaveTemps) + if (SaveTemps == SaveTempsEnum::Unset) tempDir.eraseFromDisk(true); return ret; } Modified: llvm/trunk/lib/CompilerDriver/Action.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CompilerDriver/Action.cpp?rev=74190&r1=74189&r2=74190&view=diff ============================================================================== --- llvm/trunk/lib/CompilerDriver/Action.cpp (original) +++ llvm/trunk/lib/CompilerDriver/Action.cpp Thu Jun 25 13:20:10 2009 @@ -12,8 +12,8 @@ //===----------------------------------------------------------------------===// #include "llvm/CompilerDriver/Action.h" +#include "llvm/CompilerDriver/BuiltinOptions.h" -#include "llvm/Support/CommandLine.h" #include "llvm/System/Program.h" #include @@ -22,9 +22,6 @@ using namespace llvm; using namespace llvmc; -extern cl::opt DryRun; -extern cl::opt VerboseMode; - namespace { int ExecuteProgram(const std::string& name, const StrVector& args) { Modified: llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp?rev=74190&r1=74189&r2=74190&view=diff ============================================================================== --- llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp (original) +++ llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp Thu Jun 25 13:20:10 2009 @@ -11,11 +11,11 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CompilerDriver/BuiltinOptions.h" #include "llvm/CompilerDriver/CompilationGraph.h" #include "llvm/CompilerDriver/Error.h" #include "llvm/ADT/STLExtras.h" -#include "llvm/Support/CommandLine.h" #include "llvm/Support/DOTGraphTraits.h" #include "llvm/Support/GraphWriter.h" @@ -30,9 +30,6 @@ using namespace llvm; using namespace llvmc; -extern cl::list InputFilenames; -extern cl::list Languages; - namespace llvmc { const std::string& LanguageMap::GetLanguage(const sys::Path& File) const { @@ -477,7 +474,7 @@ { template - static std::string getNodeLabel(const Node* N, const GraphType&, + static std::string getNodeLabel(const Node* N, const GraphType&, bool ShortNames) { if (N->ToolPtr) Modified: llvm/trunk/lib/CompilerDriver/Tool.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CompilerDriver/Tool.cpp?rev=74190&r1=74189&r2=74190&view=diff ============================================================================== --- llvm/trunk/lib/CompilerDriver/Tool.cpp (original) +++ llvm/trunk/lib/CompilerDriver/Tool.cpp Thu Jun 25 13:20:10 2009 @@ -11,16 +11,14 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CompilerDriver/BuiltinOptions.h" #include "llvm/CompilerDriver/Tool.h" #include "llvm/System/Path.h" -#include "llvm/Support/CommandLine.h" using namespace llvm; using namespace llvmc; -extern cl::opt OutputFilename; - namespace { sys::Path MakeTempFile(const sys::Path& TempDir, const std::string& BaseName, const std::string& Suffix) { @@ -39,7 +37,7 @@ // NOTE: makeUnique always *creates* a unique temporary file, // which is good, since there will be no races. However, some // tools do not like it when the output file already exists, so - // they have to be placated with -f or something like that. + // they need to be placated with -f or something like that. Out.makeUnique(true, NULL); return Out; } @@ -52,7 +50,7 @@ sys::Path Out; if (StopCompilation) { - if (!OutputFilename.empty()) { + if (!OutputFilename.empty() && SaveTemps != SaveTempsEnum::Obj ) { Out.set(OutputFilename); } else if (IsJoin()) { From foldr at codedgers.com Thu Jun 25 13:20:44 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Thu, 25 Jun 2009 18:20:44 -0000 Subject: [llvm-commits] [llvm] r74191 - in /llvm/trunk: docs/CommandGuide/llvmc.pod tools/llvmc/doc/LLVMC-Reference.rst Message-ID: <200906251820.n5PIKiS6024113@zion.cs.uiuc.edu> Author: foldr Date: Thu Jun 25 13:20:44 2009 New Revision: 74191 URL: http://llvm.org/viewvc/llvm-project?rev=74191&view=rev Log: Update documentation. Modified: llvm/trunk/docs/CommandGuide/llvmc.pod llvm/trunk/tools/llvmc/doc/LLVMC-Reference.rst Modified: llvm/trunk/docs/CommandGuide/llvmc.pod URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CommandGuide/llvmc.pod?rev=74191&r1=74190&r2=74191&view=diff ============================================================================== --- llvm/trunk/docs/CommandGuide/llvmc.pod (original) +++ llvm/trunk/docs/CommandGuide/llvmc.pod Thu Jun 25 13:20:44 2009 @@ -65,8 +65,11 @@ =item B<--save-temps> -Write temporary files to the current directory and do not delete them -on exit. Hidden option, useful for debugging. +Write temporary files to the current directory and do not delete them on +exit. This option can also take an argument: the I<--save-temps=obj> switch will +write files into the directory specified with the I<-o> option. The +I<--save-temps=cwd> and I<--save-temps> switches are both synonyms for the +default behaviour. =item B<--help> Modified: llvm/trunk/tools/llvmc/doc/LLVMC-Reference.rst URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/doc/LLVMC-Reference.rst?rev=74191&r1=74190&r2=74191&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/doc/LLVMC-Reference.rst (original) +++ llvm/trunk/tools/llvmc/doc/LLVMC-Reference.rst Thu Jun 25 13:20:44 2009 @@ -92,6 +92,12 @@ * ``-v`` - Enable verbose mode, i.e. print out all executed commands. +* ``--save-temps`` - Write temporary files to the current directory and do not + delete them on exit. This option can also take an argument: the + ``--save-temps=obj`` switch will write files into the directory specified with + the ``-o`` option. The ``--save-temps=cwd`` and ``--save-temps`` switches are + both synonyms for the default behaviour. + * ``--check-graph`` - Check the compilation for common errors like mismatched output/input language names, multiple default edges and cycles. Because of plugins, these checks can't be performed at compile-time. Exit with code zero @@ -108,9 +114,6 @@ used to set the output file name. Hidden option, useful for debugging LLVMC plugins. -* ``--save-temps`` - Write temporary files to the current directory - and do not delete them on exit. Hidden option, useful for debugging. - * ``--help``, ``--help-hidden``, ``--version`` - These options have their standard meaning. From foldr at codedgers.com Thu Jun 25 13:21:10 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Thu, 25 Jun 2009 18:21:10 -0000 Subject: [llvm-commits] [llvm] r74192 - /llvm/trunk/docs/CompilerDriver.html Message-ID: <200906251821.n5PILA68024169@zion.cs.uiuc.edu> Author: foldr Date: Thu Jun 25 13:21:10 2009 New Revision: 74192 URL: http://llvm.org/viewvc/llvm-project?rev=74192&view=rev Log: Regenerate. Modified: llvm/trunk/docs/CompilerDriver.html Modified: llvm/trunk/docs/CompilerDriver.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CompilerDriver.html?rev=74192&r1=74191&r2=74192&view=diff ============================================================================== --- llvm/trunk/docs/CompilerDriver.html (original) +++ llvm/trunk/docs/CompilerDriver.html Thu Jun 25 13:21:10 2009 @@ -109,6 +109,11 @@
  10. -load PLUGIN_NAME - Load the specified plugin DLL. Example: -load $LLVM_DIR/Release/lib/LLVMCSimple.so.
  11. -v - Enable verbose mode, i.e. print out all executed commands.
    12. +
  12. --save-temps - Write temporary files to the current directory and do not +delete them on exit. This option can also take an argument: the +--save-temps=obj switch will write files into the directory specified with +the -o option. The --save-temps=cwd and --save-temps switches are +both synonyms for the default behaviour.
  13. --check-graph - Check the compilation for common errors like mismatched output/input language names, multiple default edges and cycles. Because of plugins, these checks can't be performed at compile-time. Exit with code zero @@ -122,8 +127,6 @@ to the file used by the --view-graph option). The -o option can be used to set the output file name. Hidden option, useful for debugging LLVMC plugins.
    14. -
  14. --save-temps - Write temporary files to the current directory -and do not delete them on exit. Hidden option, useful for debugging.
  15. --help, --help-hidden, --version - These options have their standard meaning.
    16. From foldr at codedgers.com Thu Jun 25 13:21:34 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Thu, 25 Jun 2009 18:21:34 -0000 Subject: [llvm-commits] [llvm] r74193 - /llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Message-ID: <200906251821.n5PILYNn024195@zion.cs.uiuc.edu> Author: foldr Date: Thu Jun 25 13:21:34 2009 New Revision: 74193 URL: http://llvm.org/viewvc/llvm-project?rev=74193&view=rev Log: Better error message. Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp?rev=74193&r1=74192&r2=74193&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Thu Jun 25 13:21:34 2009 @@ -1132,12 +1132,14 @@ enum TokenizerState { Normal, SpecialCommand, InsideSpecialCommand, InsideQuotationMarks } cur_st = Normal; + + if (CmdLine.empty()) + return; Out.push_back(""); std::string::size_type B = CmdLine.find_first_not_of(Delimiters), E = CmdLine.size(); - if (B == std::string::npos) - throw "Empty command-line string!"; + for (; B != E; ++B) { char cur_ch = CmdLine[B]; @@ -1278,7 +1280,7 @@ TokenizeCmdline(InitPtrToString(CmdLine), StrVec); if (StrVec.empty()) - throw "Tool " + ToolName + " has empty command line!"; + throw "Tool '" + ToolName + "' has empty command line!"; StrVector::const_iterator I = StrVec.begin(), E = StrVec.end(); From sabre at nondot.org Thu Jun 25 13:45:54 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 25 Jun 2009 18:45:54 -0000 Subject: [llvm-commits] [llvm] r74199 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200906251845.n5PIjtKj025194@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 25 13:45:50 2009 New Revision: 74199 URL: http://llvm.org/viewvc/llvm-project?rev=74199&view=rev Log: start bringing targetoperand flags into isel, first up, ExternalSymbol. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=74199&r1=74198&r2=74199&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Jun 25 13:45:50 2009 @@ -310,8 +310,8 @@ SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl); SDValue getExternalSymbol(const char *Sym, MVT VT); SDValue getExternalSymbol(const char *Sym, DebugLoc dl, MVT VT); - SDValue getTargetExternalSymbol(const char *Sym, MVT VT); - SDValue getTargetExternalSymbol(const char *Sym, DebugLoc dl, MVT VT); + SDValue getTargetExternalSymbol(const char *Sym, MVT VT, + unsigned char TargetFlags = 0); SDValue getArgFlags(ISD::ArgFlagsTy Flags); SDValue getValueType(MVT); SDValue getRegister(unsigned Reg, MVT VT); @@ -862,7 +862,8 @@ std::vector ValueTypeNodes; std::map ExtendedValueTypeNodes; StringMap ExternalSymbols; - StringMap TargetExternalSymbols; + + std::map,SDNode*> TargetExternalSymbols; }; template <> struct GraphTraits : public GraphTraits { Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=74199&r1=74198&r2=74199&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Jun 25 13:45:50 2009 @@ -2101,15 +2101,18 @@ class ExternalSymbolSDNode : public SDNode { const char *Symbol; + unsigned char TargetFlags; + friend class SelectionDAG; - ExternalSymbolSDNode(bool isTarget, const char *Sym, MVT VT) + ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned char TF, MVT VT) : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, DebugLoc::getUnknownLoc(), - getSDVTList(VT)), Symbol(Sym) { + getSDVTList(VT)), Symbol(Sym), TargetFlags(TF) { } public: const char *getSymbol() const { return Symbol; } + unsigned char getTargetFlags() const { return TargetFlags; } static bool classof(const ExternalSymbolSDNode *) { return true; } static bool classof(const SDNode *N) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=74199&r1=74198&r2=74199&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jun 25 13:45:50 2009 @@ -632,10 +632,13 @@ case ISD::ExternalSymbol: Erased = ExternalSymbols.erase(cast(N)->getSymbol()); break; - case ISD::TargetExternalSymbol: - Erased = - TargetExternalSymbols.erase(cast(N)->getSymbol()); + case ISD::TargetExternalSymbol: { + ExternalSymbolSDNode *ESN = cast(N); + Erased = TargetExternalSymbols.erase( + std::pair(ESN->getSymbol(), + ESN->getTargetFlags())); break; + } case ISD::VALUETYPE: { MVT VT = cast(N)->getVT(); if (VT.isExtended()) { @@ -1108,16 +1111,19 @@ SDNode *&N = ExternalSymbols[Sym]; if (N) return SDValue(N, 0); N = NodeAllocator.Allocate(); - new (N) ExternalSymbolSDNode(false, Sym, VT); + new (N) ExternalSymbolSDNode(false, Sym, 0, VT); AllNodes.push_back(N); return SDValue(N, 0); } -SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { - SDNode *&N = TargetExternalSymbols[Sym]; +SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT, + unsigned char TargetFlags) { + SDNode *&N = + TargetExternalSymbols[std::pair(Sym, + TargetFlags)]; if (N) return SDValue(N, 0); N = NodeAllocator.Allocate(); - new (N) ExternalSymbolSDNode(true, Sym, VT); + new (N) ExternalSymbolSDNode(true, Sym, TargetFlags, VT); AllNodes.push_back(N); return SDValue(N, 0); } From isanbard at gmail.com Thu Jun 25 15:25:41 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 25 Jun 2009 13:25:41 -0700 Subject: [llvm-commits] [patch] test suite documentation updates, new "XFAIL: disable_assertions" In-Reply-To: <0B7C2DE8-1572-42EF-9C4F-0C64FA399EA2@apple.com> References: <0B7C2DE8-1572-42EF-9C4F-0C64FA399EA2@apple.com> Message-ID: <16e5fdf90906251325u6371e07fm756b59729a101952@mail.gmail.com> On Thu, Jun 25, 2009 at 11:19 AM, Shantonu Sen wrote: > I was getting a test suite failure with a Release-Asserts build on > test/CodeGen/PowerPC/int-fp-conv-0.ll because it does: > >> ?; RUN: llvm-as < %s | llc -march=ppc64 -debug |& not grep {= store} > > "llc -debug" is only available when assertions are enabled, so there should > be a way to XFAIL this when assertions are disabled. I added this ability to > the llvm dejagnu tests, and now the test PASSes for a Debug build, and > XFAILs for Release-Asserts. > Relying upon grepping the output of the '-debug' flag is a Bad Thing(tm). Someone should just make this test work the standard way (grepping .ll files) or remove it. -bw > I noticed a bunch of other documentation issues that I ran into, which I > expanded on. > > Chris L. says that --with-f2c hasn't been supported in a while, and should > probably be removed, so I did (it also breaks W3C validation of the HTML) > > Mac OS X has shipped Tcl and expect since 10.4 at least, I don't think it's > relevant to recommend ways to install them. > > Diff attached > > > > Shantonu Sen > ssen at apple.com > > Sent from my Mac Pro > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From vkutuzov at accesssoftek.com Thu Jun 25 14:16:17 2009 From: vkutuzov at accesssoftek.com (Viktor Kutuzov) Date: Thu, 25 Jun 2009 12:16:17 -0700 Subject: [llvm-commits] [PATCH] Fix for broken llvm build for Windows References: <200906250736.n5P7aQMG024390@zion.cs.uiuc.edu> Message-ID: Hello everyone, The llvm build with MinGW fails with the following error: llvm[4]: Compiling ARMAsmPrinter.cpp for Release build C:/msys/1.0/home/src/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp: In member function `void ::ARMAsmPrinter::printBitfieldInvMaskImmOperand(const llvm::MachineInstr*, int)': C:/msys/1.0/home/src/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp:640: error: `ffs' was not declared in this scope C:/msys/1.0/home/src/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp:640: warning: unused variable 'ffs' make[4]: *** [/home/build-arm-elf/llvm/lib/Target/ARM/AsmPrinter/Release/ARMAsmPrinter.o] Error 1 It's better to use llvm CountTrailingZeros_32 instead. Please find the patch attached. Best regards, Viktor -------------- next part -------------- A non-text attachment was scrubbed... Name: ARMASMPrinter.diff Type: application/octet-stream Size: 660 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090625/ac7f51b6/attachment.obj From evan.cheng at apple.com Thu Jun 25 15:59:24 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 25 Jun 2009 20:59:24 -0000 Subject: [llvm-commits] [llvm] r74200 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/carry.ll test/CodeGen/Thumb2/carry.ll Message-ID: <200906252059.n5PKxOiF029956@zion.cs.uiuc.edu> Author: evancheng Date: Thu Jun 25 15:59:23 2009 New Revision: 74200 URL: http://llvm.org/viewvc/llvm-project?rev=74200&view=rev Log: ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. Added: llvm/trunk/test/CodeGen/ARM/carry.ll llvm/trunk/test/CodeGen/Thumb2/carry.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=74200&r1=74199&r2=74200&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jun 25 15:59:23 2009 @@ -365,10 +365,10 @@ [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; } -/// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the +/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the /// instruction modifies the CSPR register. let Defs = [CPSR] in { -multiclass ASI1_bin_s_irs opcod, string opc, PatFrag opnode> { +multiclass AI1_bin_s_irs opcod, string opc, PatFrag opnode> { def ri : AI1; @@ -430,18 +430,18 @@ Requires<[IsARM, HasV6]>; } -/// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and -/// setting carry bit. But it can optionally set CPSR. -let Uses = [CPSR] in { -multiclass AsXI1_bin_c_irs opcod, string opc, PatFrag opnode> { - def ri : AXI1 opcod, string opc, PatFrag opnode> { + def ri : AXI1; - def rr : AXI1; - def rs : AXI1; } } @@ -905,16 +905,16 @@ BinOpFrag<(sub node:$LHS, node:$RHS)>>; // ADD and SUB with 's' bit set. -defm ADDS : ASI1_bin_s_irs<0b0100, "add", - BinOpFrag<(addc node:$LHS, node:$RHS)>>; -defm SUBS : ASI1_bin_s_irs<0b0010, "sub", - BinOpFrag<(subc node:$LHS, node:$RHS)>>; - -// FIXME: Do not allow ADC / SBC to be predicated for now. -defm ADC : AsXI1_bin_c_irs<0b0101, "adc", - BinOpFrag<(adde node:$LHS, node:$RHS)>>; -defm SBC : AsXI1_bin_c_irs<0b0110, "sbc", - BinOpFrag<(sube node:$LHS, node:$RHS)>>; +defm ADDS : AI1_bin_s_irs<0b0100, "add", + BinOpFrag<(addc node:$LHS, node:$RHS)>>; +defm SUBS : AI1_bin_s_irs<0b0010, "sub", + BinOpFrag<(subc node:$LHS, node:$RHS)>>; + +// FIXME: Do not allow ADCS / SBCS to be predicated for now. +defm ADCS : AI1_bin_cs_irs<0b0101, "adc", + BinOpFrag<(adde node:$LHS, node:$RHS)>>; +defm SBCS : AI1_bin_cs_irs<0b0110, "sbc", + BinOpFrag<(sube node:$LHS, node:$RHS)>>; // These don't define reg/reg forms, because they are handled above. def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, @@ -935,14 +935,14 @@ [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>; } -// FIXME: Do not allow RSC to be predicated for now. But they can set CPSR. -let Uses = [CPSR] in { -def RSCri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s), - DPFrm, "rsc${s} $dst, $a, $b", - [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>; -def RSCrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s), - DPSoRegFrm, "rsc${s} $dst, $a, $b", - [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>; +// FIXME: Do not allow RSC to be predicated for now. +let Defs = [CPSR], Uses = [CPSR] in { +def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), + DPFrm, "rscs $dst, $a, $b", + [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>; +def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), + DPSoRegFrm, "rscs $dst, $a, $b", + [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>; } // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=74200&r1=74199&r2=74200&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Jun 25 15:59:23 2009 @@ -169,16 +169,14 @@ [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; } -/// T2I_rbin_irs - Same as T2I_bin_irs except the order of operands are reversed. -multiclass T2I_rbin_irs { +/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are +/// reversed. It doesn't define the 'rr' form since it's handled by its +/// T2I_bin_irs counterpart. +multiclass T2I_rbin_is { // shifted imm def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), opc, " $dst, $rhs, $lhs", [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; - // register - def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs), - opc, " $dst, $rhs, $lhs", - [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), opc, " $dst, $rhs, $lhs", @@ -204,25 +202,6 @@ } } -/// T2I_rbin_s_irs - Same as T2I_bin_s_irs except the order of operands are -/// reversed. -let Defs = [CPSR] in { -multiclass T2I_rbin_s_irs { - // shifted imm - def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), - !strconcat(opc, "s"), " $dst, $rhs, $lhs", - [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; - // register - def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs), - !strconcat(opc, "s"), " $dst, $rhs, $lhs", - [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; - // shifted register - def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), - !strconcat(opc, "s"), " $dst, $rhs, $lhs", - [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; -} -} - /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) /// patterns for a binary operation that produces a value. multiclass T2I_bin_ii12rs { @@ -244,39 +223,56 @@ [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; } -/// T2I_bin_c_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a -// binary operation that produces a value and set the carry bit. It can also -/// optionally set CPSR. -let Uses = [CPSR] in { -multiclass T2I_bin_c_irs { +/// T2I_bin_cs_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a +/// binary operation that produces a value and use and define the carry bit. +/// It's not predicable. +let Defs = [CPSR], Uses = [CPSR] in { +multiclass T2I_bin_cs_irs { // shifted imm - def ri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $lhs, $rhs"), + def ri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), + !strconcat(opc, "s $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; // register - def rr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $lhs, $rhs"), + def rr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), + !strconcat(opc, "s $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register - def rs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $lhs, $rhs"), + def rs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), + !strconcat(opc, "s $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; } } -/// T2I_rbin_c_irs - Same as T2I_bin_c_irs except the order of operands are -/// reversed. -let Uses = [CPSR] in { -multiclass T2I_rbin_c_irs { +/// T2I_rbin_cs_is - Same as T2I_bin_cs_irs except the order of operands are +/// reversed. It doesn't define the 'rr' form since it's handled by its +/// T2I_bin_cs_irs counterpart. +let Defs = [CPSR], Uses = [CPSR] in { +multiclass T2I_rbin_cs_is { // shifted imm - def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $rhs, $lhs"), + def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), + !strconcat(opc, "s $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; // register - def rr : T2XI<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs, cc_out:$s), - !strconcat(opc, "${s} $dst, $rhs, $lhs"), + def rr : T2XI<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs), + !strconcat(opc, "s $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; // shifted register + def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), + !strconcat(opc, "s $dst, $rhs, $lhs"), + [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; +} +} + +/// T2I_rbin_s_is - Same as T2I_bin_s_irs except the order of operands are +/// reversed. It doesn't define the 'rr' form since it's handled by its +/// T2I_bin_s_irs counterpart. +let Defs = [CPSR] in { +multiclass T2I_rbin_s_is { + // shifted imm + def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), + !strconcat(opc, "${s} $dst, $rhs, $lhs"), + [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; + // shifted register def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), !strconcat(opc, "${s} $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; @@ -386,17 +382,17 @@ defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. -defm t2ADDS : T2I_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>; -defm t2SUBS : T2I_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; +defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>; +defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; // FIXME: predication support -defm t2ADC : T2I_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>; -defm t2SBC : T2I_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; +defm t2ADC : T2I_bin_cs_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>; +defm t2SBC : T2I_bin_cs_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; // RSB, RSC -defm t2RSB : T2I_rbin_irs <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>; -defm t2RSBS : T2I_rbin_c_irs<"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>; -defm t2RSC : T2I_rbin_s_irs<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; +defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>; +defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>; +defm t2RSC : T2I_rbin_cs_is<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. def : Thumb2Pat<(add GPR:$src, t2_so_imm_neg:$imm), Added: llvm/trunk/test/CodeGen/ARM/carry.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/carry.ll?rev=74200&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/carry.ll (added) +++ llvm/trunk/test/CodeGen/ARM/carry.ll Thu Jun 25 15:59:23 2009 @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=arm | grep "subs r" | count 2 +; RUN: llvm-as < %s | llc -march=arm | grep adc +; RUN: llvm-as < %s | llc -march=arm | grep sbc + +define i64 @f1(i64 %a, i64 %b) { +entry: + %tmp = sub i64 %a, %b + ret i64 %tmp +} + +define i64 @f2(i64 %a, i64 %b) { +entry: + %tmp1 = shl i64 %a, 1 + %tmp2 = sub i64 %tmp1, %b + ret i64 %tmp2 +} Added: llvm/trunk/test/CodeGen/Thumb2/carry.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/carry.ll?rev=74200&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/carry.ll (added) +++ llvm/trunk/test/CodeGen/Thumb2/carry.ll Thu Jun 25 15:59:23 2009 @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "subs r" | count 2 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep adc +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep sbc + +define i64 @f1(i64 %a, i64 %b) { +entry: + %tmp = sub i64 %a, %b + ret i64 %tmp +} + +define i64 @f2(i64 %a, i64 %b) { +entry: + %tmp1 = shl i64 %a, 1 + %tmp2 = sub i64 %tmp1, %b + ret i64 %tmp2 +} From daniel at zuster.org Thu Jun 25 16:03:18 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 25 Jun 2009 21:03:18 -0000 Subject: [llvm-commits] [llvm] r74201 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp Message-ID: <200906252103.n5PL3IsE030092@zion.cs.uiuc.edu> Author: ddunbar Date: Thu Jun 25 16:03:18 2009 New Revision: 74201 URL: http://llvm.org/viewvc/llvm-project?rev=74201&view=rev Log: MC: Truncate values when printing, to keep 'as' happy. Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=74201&r1=74200&r2=74201&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Thu Jun 25 16:03:18 2009 @@ -61,7 +61,7 @@ } /// Allow printing values directly to a raw_ostream. -inline raw_ostream &operator<<(raw_ostream &os, const MCValue &Value) { +static inline raw_ostream &operator<<(raw_ostream &os, const MCValue &Value) { if (Value.getSymA()) { os << Value.getSymA()->getName(); if (Value.getSymB()) @@ -76,6 +76,16 @@ return os; } +static inline int64_t truncateToSize(int64_t Value, unsigned Bytes) { + assert(Bytes && "Invalid size!"); + return Value & ((uint64_t) (int64_t) -1 >> (64 - Bytes * 8)); +} + +static inline MCValue truncateToSize(const MCValue &Value, unsigned Bytes) { + return MCValue::get(Value.getSymA(), Value.getSymB(), + truncateToSize(Value.getCst(), Bytes)); +} + void MCAsmStreamer::SwitchSection(MCSection *Section) { if (Section != CurSection) { CurSection = Section; @@ -148,7 +158,7 @@ case 8: OS << ".quad"; break; } - OS << ' ' << Value << '\n'; + OS << ' ' << truncateToSize(Value, Size) << '\n'; } void MCAsmStreamer::EmitValueToAlignment(unsigned ByteAlignment, int64_t Value, @@ -169,7 +179,7 @@ OS << ' ' << Pow2; - OS << ", " << Value; + OS << ", " << truncateToSize(Value, ValueSize); if (MaxBytesToEmit) OS << ", " << MaxBytesToEmit; OS << '\n'; From sabre at nondot.org Thu Jun 25 16:21:14 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 25 Jun 2009 21:21:14 -0000 Subject: [llvm-commits] [llvm] r74203 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200906252121.n5PLLED5030787@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 25 16:21:14 2009 New Revision: 74203 URL: http://llvm.org/viewvc/llvm-project?rev=74203&view=rev Log: allow setting target operand flags on TargetGlobalAddress nodes. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=74203&r1=74202&r2=74203&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Jun 25 16:21:14 2009 @@ -278,10 +278,12 @@ return getConstantFP(Val, VT, true); } SDValue getGlobalAddress(const GlobalValue *GV, MVT VT, - int64_t offset = 0, bool isTargetGA = false); + int64_t offset = 0, bool isTargetGA = false, + unsigned char TargetFlags = 0); SDValue getTargetGlobalAddress(const GlobalValue *GV, MVT VT, - int64_t offset = 0) { - return getGlobalAddress(GV, VT, offset, true); + int64_t offset = 0, + unsigned char TargetFlags = 0) { + return getGlobalAddress(GV, VT, offset, true, TargetFlags); } SDValue getFrameIndex(int FI, MVT VT, bool isTarget = false); SDValue getTargetFrameIndex(int FI, MVT VT) { Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=74203&r1=74202&r2=74203&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Jun 25 16:21:14 2009 @@ -1819,13 +1819,15 @@ class GlobalAddressSDNode : public SDNode { GlobalValue *TheGlobal; int64_t Offset; + unsigned char TargetFlags; friend class SelectionDAG; GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, MVT VT, - int64_t o = 0); + int64_t o, unsigned char TargetFlags); public: GlobalValue *getGlobal() const { return TheGlobal; } int64_t getOffset() const { return Offset; } + unsigned char getTargetFlags() const { return TargetFlags; } // Return the address space this GlobalAddress belongs to. unsigned getAddressSpace() const; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=74203&r1=74202&r2=74203&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jun 25 16:21:14 2009 @@ -361,6 +361,9 @@ /// the NodeID data. static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { switch (N->getOpcode()) { + case ISD::TargetExternalSymbol: + case ISD::ExternalSymbol: + assert(0 && "Should only be used on nodes with operands"); default: break; // Normal nodes don't need extra info. case ISD::ARG_FLAGS: ID.AddInteger(cast(N)->getArgFlags().getRawBits()); @@ -381,6 +384,7 @@ const GlobalAddressSDNode *GA = cast(N); ID.AddPointer(GA->getGlobal()); ID.AddInteger(GA->getOffset()); + ID.AddInteger(GA->getTargetFlags()); break; } case ISD::BasicBlock: @@ -958,9 +962,11 @@ SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, MVT VT, int64_t Offset, - bool isTargetGA) { - unsigned Opc; - + bool isTargetGA, + unsigned char TargetFlags) { + assert((TargetFlags == 0 || isTargetGA) && + "Cannot set target flags on target-independent globals"); + // Truncate (with sign-extension) the offset value to the pointer size. unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); if (BitWidth < 64) @@ -973,6 +979,7 @@ GVar = dyn_cast_or_null(GA->resolveAliasedGlobal(false)); } + unsigned Opc; if (GVar && GVar->isThreadLocal()) Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; else @@ -982,11 +989,12 @@ AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); ID.AddPointer(GV); ID.AddInteger(Offset); + ID.AddInteger(TargetFlags); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); SDNode *N = NodeAllocator.Allocate(); - new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); + new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset, TargetFlags); CSEMap.InsertNode(N, IP); AllNodes.push_back(N); return SDValue(N, 0); @@ -4914,14 +4922,15 @@ } GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, - MVT VT, int64_t o) + MVT VT, int64_t o, unsigned char TF) : SDNode(isa(GA) && cast(GA)->isThreadLocal() ? // Thread Local (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : // Non Thread Local (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), - DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o) { + DebugLoc::getUnknownLoc(), getSDVTList(VT)), + Offset(o), TargetFlags(TF) { TheGlobal = const_cast(GA); } @@ -5487,6 +5496,8 @@ OS << " + " << offset; else OS << " " << offset; + if (unsigned char TF = GADN->getTargetFlags()) + OS << " [TF=" << TF << ']'; } else if (const FrameIndexSDNode *FIDN = dyn_cast(this)) { OS << "<" << FIDN->getIndex() << ">"; } else if (const JumpTableSDNode *JTDN = dyn_cast(this)) { @@ -5517,6 +5528,8 @@ } else if (const ExternalSymbolSDNode *ES = dyn_cast(this)) { OS << "'" << ES->getSymbol() << "'"; + if (unsigned char TF = GADN->getTargetFlags()) + OS << " [TF=" << TF << ']'; } else if (const SrcValueSDNode *M = dyn_cast(this)) { if (M->getValue()) OS << "<" << M->getValue() << ">"; From sabre at nondot.org Thu Jun 25 16:35:31 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 25 Jun 2009 21:35:31 -0000 Subject: [llvm-commits] [llvm] r74204 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200906252135.n5PLZV4u031189@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 25 16:35:31 2009 New Revision: 74204 URL: http://llvm.org/viewvc/llvm-project?rev=74204&view=rev Log: add targetflags to jump tables and constant pool entries. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=74204&r1=74203&r2=74204&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Jun 25 16:35:31 2009 @@ -289,22 +289,26 @@ SDValue getTargetFrameIndex(int FI, MVT VT) { return getFrameIndex(FI, VT, true); } - SDValue getJumpTable(int JTI, MVT VT, bool isTarget = false); - SDValue getTargetJumpTable(int JTI, MVT VT) { - return getJumpTable(JTI, VT, true); + SDValue getJumpTable(int JTI, MVT VT, bool isTarget = false, + unsigned char TargetFlags = 0); + SDValue getTargetJumpTable(int JTI, MVT VT, unsigned char TargetFlags = 0) { + return getJumpTable(JTI, VT, true, TargetFlags); } SDValue getConstantPool(Constant *C, MVT VT, - unsigned Align = 0, int Offs = 0, bool isT=false); + unsigned Align = 0, int Offs = 0, bool isT=false, + unsigned char TargetFlags = 0); SDValue getTargetConstantPool(Constant *C, MVT VT, - unsigned Align = 0, int Offset = 0) { - return getConstantPool(C, VT, Align, Offset, true); + unsigned Align = 0, int Offset = 0, + unsigned char TargetFlags = 0) { + return getConstantPool(C, VT, Align, Offset, true, TargetFlags); } SDValue getConstantPool(MachineConstantPoolValue *C, MVT VT, - unsigned Align = 0, int Offs = 0, bool isT=false); + unsigned Align = 0, int Offs = 0, bool isT=false, + unsigned char TargetFlags = 0); SDValue getTargetConstantPool(MachineConstantPoolValue *C, MVT VT, unsigned Align = 0, - int Offset = 0) { - return getConstantPool(C, VT, Align, Offset, true); + int Offset = 0, unsigned char TargetFlags=0) { + return getConstantPool(C, VT, Align, Offset, true, TargetFlags); } // When generating a branch to a BB, we don't in general know enough // to provide debug info for the BB at that time, so keep this one around. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=74204&r1=74203&r2=74204&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Jun 25 16:35:31 2009 @@ -1860,14 +1860,16 @@ class JumpTableSDNode : public SDNode { int JTI; + unsigned char TargetFlags; friend class SelectionDAG; - JumpTableSDNode(int jti, MVT VT, bool isTarg) + JumpTableSDNode(int jti, MVT VT, bool isTarg, unsigned char TF) : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable, - DebugLoc::getUnknownLoc(), getSDVTList(VT)), JTI(jti) { + DebugLoc::getUnknownLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) { } public: int getIndex() const { return JTI; } + unsigned char getTargetFlags() const { return TargetFlags; } static bool classof(const JumpTableSDNode *) { return true; } static bool classof(const SDNode *N) { @@ -1883,40 +1885,27 @@ } Val; int Offset; // It's a MachineConstantPoolValue if top bit is set. unsigned Alignment; // Minimum alignment requirement of CP (not log2 value). + unsigned char TargetFlags; friend class SelectionDAG; - ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o=0) + ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o, unsigned Align, + unsigned char TF) : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, DebugLoc::getUnknownLoc(), - getSDVTList(VT)), Offset(o), Alignment(0) { - assert((int)Offset >= 0 && "Offset is too large"); - Val.ConstVal = c; - } - ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o, unsigned Align) - : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, - DebugLoc::getUnknownLoc(), - getSDVTList(VT)), Offset(o), Alignment(Align) { + getSDVTList(VT)), Offset(o), Alignment(Align), TargetFlags(TF) { assert((int)Offset >= 0 && "Offset is too large"); Val.ConstVal = c; } ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, - MVT VT, int o=0) + MVT VT, int o, unsigned Align, unsigned char TF) : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, DebugLoc::getUnknownLoc(), - getSDVTList(VT)), Offset(o), Alignment(0) { - assert((int)Offset >= 0 && "Offset is too large"); - Val.MachineCPVal = v; - Offset |= 1 << (sizeof(unsigned)*CHAR_BIT-1); - } - ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, - MVT VT, int o, unsigned Align) - : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, - DebugLoc::getUnknownLoc(), - getSDVTList(VT)), Offset(o), Alignment(Align) { + getSDVTList(VT)), Offset(o), Alignment(Align), TargetFlags(TF) { assert((int)Offset >= 0 && "Offset is too large"); Val.MachineCPVal = v; Offset |= 1 << (sizeof(unsigned)*CHAR_BIT-1); } public: + bool isMachineConstantPoolEntry() const { return (int)Offset < 0; @@ -1939,6 +1928,7 @@ // Return the alignment of this constant pool object, which is either 0 (for // default alignment) or the desired value. unsigned getAlignment() const { return Alignment; } + unsigned char getTargetFlags() const { return TargetFlags; } const Type *getType() const; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=74204&r1=74203&r2=74204&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jun 25 16:35:31 2009 @@ -415,6 +415,7 @@ case ISD::JumpTable: case ISD::TargetJumpTable: ID.AddInteger(cast(N)->getIndex()); + ID.AddInteger(cast(N)->getTargetFlags()); break; case ISD::ConstantPool: case ISD::TargetConstantPool: { @@ -425,6 +426,7 @@ CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); else ID.AddPointer(CP->getConstVal()); + ID.AddInteger(CP->getTargetFlags()); break; } case ISD::CALL: { @@ -1015,16 +1017,20 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ +SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget, + unsigned char TargetFlags) { + assert((TargetFlags == 0 || isTarget) && + "Cannot set target flags on target-independent jump tables"); unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; FoldingSetNodeID ID; AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); ID.AddInteger(JTI); + ID.AddInteger(TargetFlags); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); SDNode *N = NodeAllocator.Allocate(); - new (N) JumpTableSDNode(JTI, VT, isTarget); + new (N) JumpTableSDNode(JTI, VT, isTarget, TargetFlags); CSEMap.InsertNode(N, IP); AllNodes.push_back(N); return SDValue(N, 0); @@ -1032,7 +1038,10 @@ SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, unsigned Alignment, int Offset, - bool isTarget) { + bool isTarget, + unsigned char TargetFlags) { + assert((TargetFlags == 0 || isTarget) && + "Cannot set target flags on target-independent globals"); if (Alignment == 0) Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; @@ -1041,11 +1050,12 @@ ID.AddInteger(Alignment); ID.AddInteger(Offset); ID.AddPointer(C); + ID.AddInteger(TargetFlags); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); SDNode *N = NodeAllocator.Allocate(); - new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); + new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment, TargetFlags); CSEMap.InsertNode(N, IP); AllNodes.push_back(N); return SDValue(N, 0); @@ -1054,7 +1064,10 @@ SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, unsigned Alignment, int Offset, - bool isTarget) { + bool isTarget, + unsigned char TargetFlags) { + assert((TargetFlags == 0 || isTarget) && + "Cannot set target flags on target-independent globals"); if (Alignment == 0) Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; @@ -1063,11 +1076,12 @@ ID.AddInteger(Alignment); ID.AddInteger(Offset); C->AddSelectionDAGCSEId(ID); + ID.AddInteger(TargetFlags); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); SDNode *N = NodeAllocator.Allocate(); - new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); + new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment, TargetFlags); CSEMap.InsertNode(N, IP); AllNodes.push_back(N); return SDValue(N, 0); @@ -5502,6 +5516,8 @@ OS << "<" << FIDN->getIndex() << ">"; } else if (const JumpTableSDNode *JTDN = dyn_cast(this)) { OS << "<" << JTDN->getIndex() << ">"; + if (unsigned char TF = JTDN->getTargetFlags()) + OS << " [TF=" << TF << ']'; } else if (const ConstantPoolSDNode *CP = dyn_cast(this)){ int offset = CP->getOffset(); if (CP->isMachineConstantPoolEntry()) @@ -5512,6 +5528,8 @@ OS << " + " << offset; else OS << " " << offset; + if (unsigned char TF = CP->getTargetFlags()) + OS << " [TF=" << TF << ']'; } else if (const BasicBlockSDNode *BBDN = dyn_cast(this)) { OS << "<"; const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); From david_goodwin at apple.com Thu Jun 25 16:40:00 2009 From: david_goodwin at apple.com (David Goodwin) Date: Thu, 25 Jun 2009 14:40:00 -0700 Subject: [llvm-commits] [patch] update thumb-1 description to correctly def/use CC registers Message-ID: <81E22538-3B6E-4475-8258-BF658BAA0ECB@apple.com> For many instructions, the thumb-1 description is missing indication that CPSR is defined or used. David -------------- next part -------------- A non-text attachment was scrubbed... Name: thumb1.patch Type: application/octet-stream Size: 10375 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090625/97b2d9f7/attachment.obj From sabre at nondot.org Thu Jun 25 16:48:17 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 25 Jun 2009 21:48:17 -0000 Subject: [llvm-commits] [llvm] r74206 - /llvm/trunk/test/CodeGen/X86/pic_jumptable.ll Message-ID: <200906252148.n5PLmH6T031687@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 25 16:48:17 2009 New Revision: 74206 URL: http://llvm.org/viewvc/llvm-project?rev=74206&view=rev Log: down with unwind info :) Modified: llvm/trunk/test/CodeGen/X86/pic_jumptable.ll Modified: llvm/trunk/test/CodeGen/X86/pic_jumptable.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pic_jumptable.ll?rev=74206&r1=74205&r2=74206&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pic_jumptable.ll (original) +++ llvm/trunk/test/CodeGen/X86/pic_jumptable.ll Thu Jun 25 16:48:17 2009 @@ -6,7 +6,7 @@ declare void @_Z3bari(i32) -define linkonce void @_Z3fooILi1EEvi(i32 %Y) { +define linkonce void @_Z3fooILi1EEvi(i32 %Y) nounwind { entry: %Y_addr = alloca i32 ; [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] From daniel at zuster.org Thu Jun 25 16:56:12 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 25 Jun 2009 21:56:12 -0000 Subject: [llvm-commits] [llvm] r74208 - in /llvm/trunk: test/MC/AsmParser/assignment.s test/MC/AsmParser/directive_set.s tools/llvm-mc/AsmLexer.cpp tools/llvm-mc/AsmLexer.h tools/llvm-mc/AsmParser.cpp tools/llvm-mc/AsmParser.h Message-ID: <200906252156.n5PLuClt031937@zion.cs.uiuc.edu> Author: ddunbar Date: Thu Jun 25 16:56:11 2009 New Revision: 74208 URL: http://llvm.org/viewvc/llvm-project?rev=74208&view=rev Log: MC: Parse .set and assignments. Added: llvm/trunk/test/MC/AsmParser/assignment.s llvm/trunk/test/MC/AsmParser/directive_set.s Modified: llvm/trunk/tools/llvm-mc/AsmLexer.cpp llvm/trunk/tools/llvm-mc/AsmLexer.h llvm/trunk/tools/llvm-mc/AsmParser.cpp llvm/trunk/tools/llvm-mc/AsmParser.h Added: llvm/trunk/test/MC/AsmParser/assignment.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/assignment.s?rev=74208&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/assignment.s (added) +++ llvm/trunk/test/MC/AsmParser/assignment.s Thu Jun 25 16:56:11 2009 @@ -0,0 +1,7 @@ +# RUN: llvm-mc %s > %t + +# RUN: grep -A 2 TEST0 %t > %t2 +# RUN: grep "a = 0" %t2 +TEST0: + a = 0 + \ No newline at end of file Added: llvm/trunk/test/MC/AsmParser/directive_set.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_set.s?rev=74208&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_set.s (added) +++ llvm/trunk/test/MC/AsmParser/directive_set.s Thu Jun 25 16:56:11 2009 @@ -0,0 +1,7 @@ +# RUN: llvm-mc %s > %t + +# RUN: grep -A 2 TEST0 %t > %t2 +# RUN: grep ".set a, 0" %t2 +TEST0: + .set a, 0 + \ No newline at end of file Modified: llvm/trunk/tools/llvm-mc/AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmLexer.cpp?rev=74208&r1=74207&r2=74208&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmLexer.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmLexer.cpp Thu Jun 25 16:56:11 2009 @@ -262,6 +262,7 @@ case '*': return asmtok::Star; case ',': return asmtok::Comma; case '$': return asmtok::Dollar; + case '=': return asmtok::Equal; case '|': return asmtok::Pipe; case '^': return asmtok::Caret; case '&': return asmtok::Amp; Modified: llvm/trunk/tools/llvm-mc/AsmLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmLexer.h?rev=74208&r1=74207&r2=74208&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmLexer.h (original) +++ llvm/trunk/tools/llvm-mc/AsmLexer.h Thu Jun 25 16:56:11 2009 @@ -42,7 +42,7 @@ Plus, Minus, Tilde, Slash, // '/' LParen, RParen, - Star, Comma, Dollar, + Star, Comma, Dollar, Equal, Pipe, Caret, Amp, Exclaim, Percent, LessLess, GreaterGreater Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=74208&r1=74207&r2=74208&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Thu Jun 25 16:56:11 2009 @@ -182,7 +182,8 @@ const char *IDVal = Lexer.getCurStrVal(); // Consume the identifier, see what is after it. - if (Lexer.Lex() == asmtok::Colon) { + switch (Lexer.Lex()) { + case asmtok::Colon: // identifier ':' -> Label. Lexer.Lex(); @@ -192,6 +193,15 @@ Out.EmitLabel(Ctx.GetOrCreateSymbol(IDVal)); return ParseStatement(); + + case asmtok::Equal: + // identifier '=' ... -> assignment statement + Lexer.Lex(); + + return ParseAssignment(IDVal, false); + + default: // Normal instruction or directive. + break; } // Otherwise, we have a normal instruction or directive. @@ -209,7 +219,8 @@ if (!strcmp(IDVal, ".static_const")) return ParseDirectiveSectionSwitch("__TEXT,__static_const"); if (!strcmp(IDVal, ".cstring")) - return ParseDirectiveSectionSwitch("__TEXT,__cstring","cstring_literals"); + return ParseDirectiveSectionSwitch("__TEXT,__cstring", + "cstring_literals"); if (!strcmp(IDVal, ".literal4")) return ParseDirectiveSectionSwitch("__TEXT,__literal4", "4byte_literals"); if (!strcmp(IDVal, ".literal8")) @@ -291,6 +302,10 @@ if (!strcmp(IDVal, ".objc_selector_strs")) return ParseDirectiveSectionSwitch("__OBJC,__selector_strs"); + // Assembler features + if (!strcmp(IDVal, ".set")) + return ParseDirectiveSet(); + // Data directives if (!strcmp(IDVal, ".ascii")) @@ -336,6 +351,40 @@ return false; } +bool AsmParser::ParseAssignment(const char *Name, bool IsDotSet) { + int64_t Value; + if (ParseExpression(Value)) + return true; + + if (Lexer.isNot(asmtok::EndOfStatement)) + return TokError("unexpected token in assignment"); + + // Eat the end of statement marker. + Lexer.Lex(); + + // Get the symbol for this name. + // FIXME: Handle '.'. + MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name); + Out.EmitAssignment(Sym, MCValue::get(Value), IsDotSet); + + return false; +} + +/// ParseDirectiveSet: +/// ::= .set identifier ',' expression +bool AsmParser::ParseDirectiveSet() { + if (Lexer.isNot(asmtok::Identifier)) + return TokError("expected identifier after '.set' directive"); + + const char *Name = Lexer.getCurStrVal(); + + if (Lexer.Lex() != asmtok::Comma) + return TokError("unexpected token in '.set'"); + Lexer.Lex(); + + return ParseAssignment(Name, true); +} + /// ParseDirectiveSection: /// ::= .section identifier (',' identifier)* /// FIXME: This should actually parse out the segment, section, attributes and Modified: llvm/trunk/tools/llvm-mc/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.h?rev=74208&r1=74207&r2=74208&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.h (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.h Thu Jun 25 16:56:11 2009 @@ -43,6 +43,7 @@ void EatToEndOfStatement(); + bool ParseAssignment(const char *Name, bool IsDotSet); bool ParseExpression(int64_t &Res); bool ParsePrimaryExpr(int64_t &Res); bool ParseBinOpRHS(unsigned Precedence, int64_t &Res); @@ -61,6 +62,7 @@ bool ParseDirectiveValue(unsigned Size); // ".byte", ".long", ... bool ParseDirectiveFill(); // ".fill" bool ParseDirectiveSpace(); // ".space" + bool ParseDirectiveSet(); // ".set" }; From resistor at mac.com Thu Jun 25 16:58:02 2009 From: resistor at mac.com (Owen Anderson) Date: Thu, 25 Jun 2009 21:58:02 -0000 Subject: [llvm-commits] [llvm] r74209 - in /llvm/trunk: include/llvm/System/ThreadLocal.h lib/System/ThreadLocal.cpp lib/System/Unix/ThreadLocal.inc lib/System/Win32/ThreadLocal.inc Message-ID: <200906252158.n5PLw2Ub032002@zion.cs.uiuc.edu> Author: resistor Date: Thu Jun 25 16:58:01 2009 New Revision: 74209 URL: http://llvm.org/viewvc/llvm-project?rev=74209&view=rev Log: Add a class for supporting platform independent thread-local storage. Windows people, please double-check/patch this. Added: llvm/trunk/include/llvm/System/ThreadLocal.h llvm/trunk/lib/System/ThreadLocal.cpp llvm/trunk/lib/System/Unix/ThreadLocal.inc llvm/trunk/lib/System/Win32/ThreadLocal.inc Added: llvm/trunk/include/llvm/System/ThreadLocal.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/ThreadLocal.h?rev=74209&view=auto ============================================================================== --- llvm/trunk/include/llvm/System/ThreadLocal.h (added) +++ llvm/trunk/include/llvm/System/ThreadLocal.h Thu Jun 25 16:58:01 2009 @@ -0,0 +1,41 @@ +//===- llvm/System/ThreadLocal.h - Thread Local Data ------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the llvm::sys::ThreadLocal class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_SYSTEM_THREAD_LOCAL_H +#define LLVM_SYSTEM_THREAD_LOCAL_H + +#include "llvm/System/Threading.h" +#include + +namespace llvm { + namespace sys { + class ThreadLocalImpl { + void* data; + public: + ThreadLocalImpl(); + virtual ~ThreadLocalImpl(); + void setInstance(void* d); + void* getInstance(); + }; + + template + class ThreadLocal : public ThreadLocalImpl { + public: + ThreadLocal() : ThreadLocalImpl() { } + T* get() { return static_cast(getInstance()); } + void set(T* d) { setInstance(d); } + }; + } +} + +#endif Added: llvm/trunk/lib/System/ThreadLocal.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/ThreadLocal.cpp?rev=74209&view=auto ============================================================================== --- llvm/trunk/lib/System/ThreadLocal.cpp (added) +++ llvm/trunk/lib/System/ThreadLocal.cpp Thu Jun 25 16:58:01 2009 @@ -0,0 +1,77 @@ +//===- ThreadLocal.cpp - Thread Local Data ----------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the llvm::sys::ThreadLocal class. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Config/config.h" +#include "llvm/System/ThreadLocal.h" + +//===----------------------------------------------------------------------===// +//=== WARNING: Implementation here must contain only TRULY operating system +//=== independent code. +//===----------------------------------------------------------------------===// + +#if !defined(ENABLE_THREADS) || ENABLE_THREADS == 0 +// Define all methods as no-ops if threading is explicitly disabled +namespace llvm { +using namespace sys; +ThreadLocalImpl::ThreadLocalImpl() { } +ThreadLocalImpl::~ThreadLocalImpl() { } +void ThreadLocalImpl::setInstance(void* d) { data = d; } +void* ThreadLocalImpl::getInstance() { return data; } +} +#else + +#if defined(HAVE_PTHREAD_H) && defined(HAVE_PTHREAD_MUTEX_LOCK) + +#include +#include +#include + +namespace llvm { +using namespace sys; + +ThreadLocalImpl::ThreadLocalImpl() : data(0) { + pthread_key_t* key = new pthread_key_t; + int errorcode = pthread_key_create(key, NULL); + assert(errorcode == 0); + data = key; +} + +ThreadLocalImpl::~ThreadLocalImpl() { + pthread_key_t* key = static_cast(data); + int errorcode = pthread_key_delete(*key); + assert(errorcode = 0); + delete key; +} + +void ThreadLocalImpl::setInstance(void* d) { + pthread_key_t* key = static_cast(data); + int errorcode = pthread_setspecific(*key, d); + assert(errorcode == 0); +} + +void* ThreadLocalImpl::getInstance() { + pthread_key_t* key = static_cast(data); + return pthread_getspecific(*key); +} + +} + +#elif defined(LLVM_ON_UNIX) +#include "Unix/ThreadLocal.inc" +#elif defined( LLVM_ON_WIN32) +#include "Win32/ThreadLocal.inc" +#else +#warning Neither LLVM_ON_UNIX nor LLVM_ON_WIN32 was set in System/ThreadLocal.cpp +#endif +#endif + Added: llvm/trunk/lib/System/Unix/ThreadLocal.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/ThreadLocal.inc?rev=74209&view=auto ============================================================================== --- llvm/trunk/lib/System/Unix/ThreadLocal.inc (added) +++ llvm/trunk/lib/System/Unix/ThreadLocal.inc Thu Jun 25 16:58:01 2009 @@ -0,0 +1,25 @@ +//=== llvm/System/Unix/ThreadLocal.inc - Unix Thread Local Data -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the Unix specific (non-pthread) ThreadLocal class. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +//=== WARNING: Implementation here must contain only generic UNIX code that +//=== is guaranteed to work on *all* UNIX variants. +//===----------------------------------------------------------------------===// + +namespace llvm { +using namespace sys; +ThreadLocalImpl::ThreadLocalImpl() { } +ThreadLocalImpl::~ThreadLocalImpl() { } +void ThreadLocalImpl::setInstance(void* d) { data = d; } +void* ThreadLocalImpl::getInstance() { return data; } +} \ No newline at end of file Added: llvm/trunk/lib/System/Win32/ThreadLocal.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/ThreadLocal.inc?rev=74209&view=auto ============================================================================== --- llvm/trunk/lib/System/Win32/ThreadLocal.inc (added) +++ llvm/trunk/lib/System/Win32/ThreadLocal.inc Thu Jun 25 16:58:01 2009 @@ -0,0 +1,49 @@ +//= llvm/System/Win32/ThreadLocal.inc - Win32 Thread Local Data -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the Win32 specific (non-pthread) ThreadLocal class. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +//=== WARNING: Implementation here must contain only generic Win32 code that +//=== is guaranteed to work on *all* Win32 variants. +//===----------------------------------------------------------------------===// + +#include "Win32.h" +#include "llvm/System/ThreadLocal.h" + +namespace llvm { +using namespace sys; + +ThreadLocalImpl::ThreadLocalImpl() { + DWORD* tls = new DWORD; + *tls = TlsAlloc(); + assert(*tls != TLS_OUT_OF_INDEXES); + data = tls; +} + +ThreadLocalImpl::~ThreadLocalImpl() { + DWORD* tls = static_cast(data); + TlsFree(*tls); + delete tls; +} + +void* ThreadLocalImpl::getInstance() { + DWORD* tls = static_cast(data); + return TlsGetValue(*tls); +} + +void ThreadLocalImpl::setInstance(void* d){ + DWORD* tls = static_cast(data); + int errorcode = TlsSetValue(*tls, d); + assert(errorcode == 0); +} + +} From resistor at mac.com Thu Jun 25 16:58:34 2009 From: resistor at mac.com (Owen Anderson) Date: Thu, 25 Jun 2009 21:58:34 -0000 Subject: [llvm-commits] [llvm] r74210 - /llvm/trunk/lib/System/CMakeLists.txt Message-ID: <200906252158.n5PLwYal032077@zion.cs.uiuc.edu> Author: resistor Date: Thu Jun 25 16:58:34 2009 New Revision: 74210 URL: http://llvm.org/viewvc/llvm-project?rev=74210&view=rev Log: Update cmake build files. Modified: llvm/trunk/lib/System/CMakeLists.txt Modified: llvm/trunk/lib/System/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/CMakeLists.txt?rev=74210&r1=74209&r2=74210&view=diff ============================================================================== --- llvm/trunk/lib/System/CMakeLists.txt (original) +++ llvm/trunk/lib/System/CMakeLists.txt Thu Jun 25 16:58:34 2009 @@ -14,6 +14,7 @@ Signals.cpp Threading.cpp TimeValue.cpp + ThreadLocal.cpp ) if( BUILD_SHARED_LIBS AND NOT WIN32 ) From isanbard at gmail.com Thu Jun 25 16:59:32 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 25 Jun 2009 21:59:32 -0000 Subject: [llvm-commits] [llvm] r74211 - /llvm/trunk/test/CodeGen/PowerPC/int-fp-conv-0.ll Message-ID: <200906252159.n5PLxW4s032124@zion.cs.uiuc.edu> Author: void Date: Thu Jun 25 16:59:32 2009 New Revision: 74211 URL: http://llvm.org/viewvc/llvm-project?rev=74211&view=rev Log: Don't grep the -debug output. This isn't the way to test changes. Modified: llvm/trunk/test/CodeGen/PowerPC/int-fp-conv-0.ll Modified: llvm/trunk/test/CodeGen/PowerPC/int-fp-conv-0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/int-fp-conv-0.ll?rev=74211&r1=74210&r2=74211&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/int-fp-conv-0.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/int-fp-conv-0.ll Thu Jun 25 16:59:32 2009 @@ -1,4 +1,3 @@ -; RUN: llvm-as < %s | llc -march=ppc64 -debug |& not grep {= store} ; RUN: llvm-as < %s | llc -march=ppc64 > %t ; RUN: grep __floattitf %t ; RUN: grep __fixunstfti %t From evan.cheng at apple.com Thu Jun 25 17:04:44 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 25 Jun 2009 22:04:44 -0000 Subject: [llvm-commits] [llvm] r74212 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Message-ID: <200906252204.n5PM4iXd032310@zion.cs.uiuc.edu> Author: evancheng Date: Thu Jun 25 17:04:44 2009 New Revision: 74212 URL: http://llvm.org/viewvc/llvm-project?rev=74212&view=rev Log: Unbreak mingw build. Patch by Viktor Kutuzov. Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=74212&r1=74211&r2=74212&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Thu Jun 25 17:04:44 2009 @@ -637,7 +637,7 @@ ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) { const MachineOperand &MO = MI->getOperand(Op); uint32_t v = ~MO.getImm(); - int32_t lsb = ffs (v) - 1; + int32_t lsb = CountTrailingZeros_32(v); int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb; assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); O << "#" << lsb << ", #" << width; From dpatel at apple.com Thu Jun 25 17:36:02 2009 From: dpatel at apple.com (Devang Patel) Date: Thu, 25 Jun 2009 22:36:02 -0000 Subject: [llvm-commits] [llvm] r74215 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h DwarfException.h DwarfWriter.cpp Message-ID: <200906252236.n5PMa23t000940@zion.cs.uiuc.edu> Author: dpatel Date: Thu Jun 25 17:36:02 2009 New Revision: 74215 URL: http://llvm.org/viewvc/llvm-project?rev=74215&view=rev Log: Simplify. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=74215&r1=74214&r2=74215&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Jun 25 17:36:02 2009 @@ -1371,9 +1371,12 @@ return Result; } -/// SetDebugInfo - Create global DIEs and emit initial debug info sections. -/// This is inovked by the target AsmPrinter. -void DwarfDebug::SetDebugInfo(MachineModuleInfo *mmi) { + /// BeginModule - Emit all Dwarf sections that should come prior to the + /// content. Create global DIEs and emit initial debug info sections. + /// This is inovked by the target AsmPrinter. +void DwarfDebug::BeginModule(Module *M, MachineModuleInfo *mmi) { + this->M = M; + if (TimePassesIsEnabled) DebugTimer->startTimer(); Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=74215&r1=74214&r2=74215&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Thu Jun 25 17:36:02 2009 @@ -486,15 +486,9 @@ /// be emitted. bool ShouldEmitDwarfDebug() const { return shouldEmit; } - /// SetDebugInfo - Create global DIEs and emit initial debug info sections. - /// This is inovked by the target AsmPrinter. - void SetDebugInfo(MachineModuleInfo *mmi); - /// BeginModule - Emit all Dwarf sections that should come prior to the /// content. - void BeginModule(Module *M) { - this->M = M; - } + void BeginModule(Module *M, MachineModuleInfo *MMI); /// EndModule - Emit all Dwarf sections that should come after the content. /// Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h?rev=74215&r1=74214&r2=74215&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h Thu Jun 25 17:36:02 2009 @@ -149,16 +149,11 @@ DwarfException(raw_ostream &OS, AsmPrinter *A, const TargetAsmInfo *T); virtual ~DwarfException(); - /// SetModuleInfo - Set machine module information when it's known that pass - /// manager has created it. Set by the target AsmPrinter. - void SetModuleInfo(MachineModuleInfo *mmi) { - MMI = mmi; - } - /// BeginModule - Emit all exception information that should come prior to the /// content. - void BeginModule(Module *M) { - this->M = M; + void BeginModule(Module *m, MachineModuleInfo *mmi) { + this->M = m; + this->MMI = mmi; } /// EndModule - Emit all exception information that should come after the Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=74215&r1=74214&r2=74215&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Thu Jun 25 17:36:02 2009 @@ -42,10 +42,8 @@ const TargetAsmInfo *T) { DE = new DwarfException(OS, A, T); DD = new DwarfDebug(OS, A, T); - DE->BeginModule(M); - DD->BeginModule(M); - DD->SetDebugInfo(MMI); - DE->SetModuleInfo(MMI); + DE->BeginModule(M, MMI); + DD->BeginModule(M, MMI); } /// EndModule - Emit all Dwarf sections that should come after the content. From david_goodwin at apple.com Thu Jun 25 17:37:12 2009 From: david_goodwin at apple.com (David Goodwin) Date: Thu, 25 Jun 2009 15:37:12 -0700 Subject: [llvm-commits] [patch] MVN pattern for Thumb-2 to load t2_so_imm_not immediates Message-ID: <2A8C9B22-9E1C-419A-95F2-E7019AB27F4F@apple.com> Currently immediates that are ~t2_so_imm are loaded with movw/movt. But we should use mvn for these. Patch and a test attached. -------------- next part -------------- A non-text attachment was scrubbed... Name: mvn.patch Type: application/octet-stream Size: 1354 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20090625/16c02f46/attachment.obj -------------- next part -------------- From evan.cheng at apple.com Thu Jun 25 17:44:45 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 25 Jun 2009 15:44:45 -0700 Subject: [llvm-commits] [patch] update thumb-1 description to correctly def/use CC registers In-Reply-To: <81E22538-3B6E-4475-8258-BF658BAA0ECB@apple.com> References: <81E22538-3B6E-4475-8258-BF658BAA0ECB@apple.com> Message-ID: <6F630D22-0BCA-44F3-ABD1-D53D8F93B61D@apple.com> Looks great. Please commit. Thanks, Evan On Jun 25, 2009, at 2:40 PM, David Goodwin wrote: > For many instructions, the thumb-1 description is missing indication > that CPSR is defined or used. > > David > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From daniel at zuster.org Thu Jun 25 17:44:52 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 25 Jun 2009 22:44:52 -0000 Subject: [llvm-commits] [llvm] r74218 - in /llvm/trunk: test/MC/AsmParser/directive_org.s tools/llvm-mc/AsmParser.cpp tools/llvm-mc/AsmParser.h Message-ID: <200906252244.n5PMiqsr001223@zion.cs.uiuc.edu> Author: ddunbar Date: Thu Jun 25 17:44:51 2009 New Revision: 74218 URL: http://llvm.org/viewvc/llvm-project?rev=74218&view=rev Log: MC: Parse .org directives. Added: llvm/trunk/test/MC/AsmParser/directive_org.s Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp llvm/trunk/tools/llvm-mc/AsmParser.h Added: llvm/trunk/test/MC/AsmParser/directive_org.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_org.s?rev=74218&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_org.s (added) +++ llvm/trunk/test/MC/AsmParser/directive_org.s Thu Jun 25 17:44:51 2009 @@ -0,0 +1,11 @@ +# RUN: llvm-mc %s > %t + +# RUN: grep -A 2 TEST0 %t > %t2 +# RUN: grep ".org 1, 0" %t2 | count 1 +TEST0: + .org 1 + +# RUN: grep -A 2 TEST1 %t > %t2 +# RUN: grep ".org 1, 3" %t2 | count 1 +TEST1: + .org 1, 3 Modified: llvm/trunk/tools/llvm-mc/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.cpp?rev=74218&r1=74217&r2=74218&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.cpp (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.cpp Thu Jun 25 17:44:51 2009 @@ -324,6 +324,8 @@ return ParseDirectiveValue(8); if (!strcmp(IDVal, ".fill")) return ParseDirectiveFill(); + if (!strcmp(IDVal, ".org")) + return ParseDirectiveOrg(); if (!strcmp(IDVal, ".space")) return ParseDirectiveSpace(); @@ -332,7 +334,6 @@ return false; } - MCInst Inst; if (ParseX86InstOperands(Inst)) return true; @@ -558,3 +559,31 @@ return false; } + +/// ParseDirectiveOrg +/// ::= .org expression [ , expression ] +bool AsmParser::ParseDirectiveOrg() { + int64_t Offset; + if (ParseExpression(Offset)) + return true; + + // Parse optional fill expression. + int64_t FillExpr = 0; + if (Lexer.isNot(asmtok::EndOfStatement)) { + if (Lexer.isNot(asmtok::Comma)) + return TokError("unexpected token in '.org' directive"); + Lexer.Lex(); + + if (ParseExpression(FillExpr)) + return true; + + if (Lexer.isNot(asmtok::EndOfStatement)) + return TokError("unexpected token in '.org' directive"); + } + + Lexer.Lex(); + + Out.EmitValueToOffset(MCValue::get(Offset), FillExpr); + + return false; +} Modified: llvm/trunk/tools/llvm-mc/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/AsmParser.h?rev=74218&r1=74217&r2=74218&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/AsmParser.h (original) +++ llvm/trunk/tools/llvm-mc/AsmParser.h Thu Jun 25 17:44:51 2009 @@ -63,6 +63,7 @@ bool ParseDirectiveFill(); // ".fill" bool ParseDirectiveSpace(); // ".space" bool ParseDirectiveSet(); // ".set" + bool ParseDirectiveOrg(); // ".org" }; From david_goodwin at apple.com Thu Jun 25 17:49:55 2009 From: david_goodwin at apple.com (David Goodwin) Date: Thu, 25 Jun 2009 22:49:55 -0000 Subject: [llvm-commits] [llvm] r74219 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <200906252249.n5PMntWD001370@zion.cs.uiuc.edu> Author: david_goodwin Date: Thu Jun 25 17:49:55 2009 New Revision: 74219 URL: http://llvm.org/viewvc/llvm-project?rev=74219&view=rev Log: Add Def/Use of CPSR for Thumb-1 instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=74219&r1=74218&r2=74219&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Jun 25 17:49:55 2009 @@ -294,103 +294,134 @@ // Arithmetic Instructions. // -// Add with carry -let isCommutable = 1 in -def tADC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), - "adc $dst, $rhs", - [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>; - -def tADDS : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), - "add $dst, $lhs, $rhs", - [(set tGPR:$dst, (addc tGPR:$lhs, tGPR:$rhs))]>; - +// Add with carry register +let isCommutable = 1, Defs = [CPSR], Uses = [CPSR] in +def tADCS : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), + "adc $dst, $rhs", + [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>; +// Add immediate +let Defs = [CPSR] in { def tADDi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "add $dst, $lhs, $rhs", [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>; +def tADDSi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), + "add $dst, $lhs, $rhs", + [(set tGPR:$dst, (addc tGPR:$lhs, imm0_7:$rhs))]>; +} +let Defs = [CPSR] in { def tADDi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "add $dst, $rhs", [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>; +def tADDSi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), + "add $dst, $rhs", + [(set tGPR:$dst, (addc tGPR:$lhs, imm8_255:$rhs))]>; +} +// Add register +let isCommutable = 1, Defs = [CPSR] in { def tADDrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "add $dst, $lhs, $rhs", [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>; +def tADDSrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), + "add $dst, $lhs, $rhs", + [(set tGPR:$dst, (addc tGPR:$lhs, tGPR:$rhs))]>; +} let neverHasSideEffects = 1 in def tADDhirr : T1It<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs), "add $dst, $rhs @ addhirr", []>; -let isCommutable = 1 in +// And register +let isCommutable = 1, Defs = [CPSR] in def tAND : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "and $dst, $rhs", [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>; +// ASR immediate +let Defs = [CPSR] in def tASRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "asr $dst, $lhs, $rhs", [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>; +// ASR register +let Defs = [CPSR] in def tASRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "asr $dst, $rhs", [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>; +// BIC register +let Defs = [CPSR] in def tBIC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "bic $dst, $rhs", [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>; - +// CMN register +let Defs = [CPSR] in { def tCMN : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs), "cmn $lhs, $rhs", [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; - -def tCMPi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs), - "cmp $lhs, $rhs", - [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>; - -def tCMPr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs), - "cmp $lhs, $rhs", - [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>; - -def tTST : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs), - "tst $lhs, $rhs", - [(ARMcmpNZ (and tGPR:$lhs, tGPR:$rhs), 0)]>; - def tCMNNZ : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs), "cmn $lhs, $rhs", [(ARMcmpNZ tGPR:$lhs, (ineg tGPR:$rhs))]>; +} +// CMP immediate +let Defs = [CPSR] in { +def tCMPi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs), + "cmp $lhs, $rhs", + [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>; def tCMPNZi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs), "cmp $lhs, $rhs", [(ARMcmpNZ tGPR:$lhs, imm0_255:$rhs)]>; +} + +// CMP register +let Defs = [CPSR] in { +def tCMPr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs), + "cmp $lhs, $rhs", + [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>; def tCMPNZr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs), "cmp $lhs, $rhs", [(ARMcmpNZ tGPR:$lhs, tGPR:$rhs)]>; +} // TODO: A7-37: CMP(3) - cmp hi regs -let isCommutable = 1 in +// XOR register +let isCommutable = 1, Defs = [CPSR] in def tEOR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "eor $dst, $rhs", [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>; +// LSL immediate +let Defs = [CPSR] in def tLSLri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "lsl $dst, $lhs, $rhs", [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>; +// LSL register +let Defs = [CPSR] in def tLSLrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "lsl $dst, $rhs", [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>; +// LSR immediate +let Defs = [CPSR] in def tLSRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "lsr $dst, $lhs, $rhs", [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>; +// LSR register +let Defs = [CPSR] in def tLSRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "lsr $dst, $rhs", [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>; -// FIXME: This is not rematerializable because mov changes the condition code. +// move register +let Defs = [CPSR] in def tMOVi8 : T1I<(outs tGPR:$dst), (ins i32imm:$src), "mov $dst, $src", [(set tGPR:$dst, imm0_255:$src)]>; @@ -411,25 +442,31 @@ "cpy $dst, $src\t@ hir2hir", []>; } // neverHasSideEffects -let isCommutable = 1 in +// multiply register +let isCommutable = 1, Defs = [CPSR] in def tMUL : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "mul $dst, $rhs", [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>; +// move inverse register +let Defs = [CPSR] in def tMVN : T1I<(outs tGPR:$dst), (ins tGPR:$src), "mvn $dst, $src", [(set tGPR:$dst, (not tGPR:$src))]>; +// negate register +let Defs = [CPSR] in def tNEG : T1I<(outs tGPR:$dst), (ins tGPR:$src), "neg $dst, $src", [(set tGPR:$dst, (ineg tGPR:$src))]>; -let isCommutable = 1 in +// bitwise or register +let isCommutable = 1, Defs = [CPSR] in def tORR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "orr $dst, $rhs", [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>; - +// swaps def tREV : T1I<(outs tGPR:$dst), (ins tGPR:$src), "rev $dst, $src", [(set tGPR:$dst, (bswap tGPR:$src))]>, @@ -452,52 +489,77 @@ (shl tGPR:$src, (i32 8))), i16))]>, Requires<[IsThumb, HasV6]>; +// rotate right register +let Defs = [CPSR] in def tROR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "ror $dst, $rhs", [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>; - -// Subtract with carry -def tSBC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), +// Subtract with carry register +let Defs = [CPSR], Uses = [CPSR] in +def tSBCS : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "sbc $dst, $rhs", [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>; -def tSUBS : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), - "sub $dst, $lhs, $rhs", - [(set tGPR:$dst, (subc tGPR:$lhs, tGPR:$rhs))]>; - - -// TODO: A7-96: STMIA - store multiple. - +// Subtract immediate +let Defs = [CPSR] in { def tSUBi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "sub $dst, $lhs, $rhs", [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>; +def tSUBSi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), + "sub $dst, $lhs, $rhs", + [(set tGPR:$dst, (addc tGPR:$lhs, imm0_7_neg:$rhs))]>; +} +let Defs = [CPSR] in { def tSUBi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "sub $dst, $rhs", [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>; +def tSUBSi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), + "sub $dst, $rhs", + [(set tGPR:$dst, (addc tGPR:$lhs, imm8_255_neg:$rhs))]>; +} +// subtract register +let Defs = [CPSR] in { def tSUBrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "sub $dst, $lhs, $rhs", [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>; +def tSUBSrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), + "sub $dst, $lhs, $rhs", + [(set tGPR:$dst, (subc tGPR:$lhs, tGPR:$rhs))]>; +} + +// TODO: A7-96: STMIA - store multiple. def tSUBspi : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "sub $dst, $rhs * 4", []>; +// sign-extend byte def tSXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src), "sxtb $dst, $src", [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>, Requires<[IsThumb, HasV6]>; + +// sign-extend short def tSXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src), "sxth $dst, $src", [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>, Requires<[IsThumb, HasV6]>; +// test +let Defs = [CPSR] in +def tTST : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs), + "tst $lhs, $rhs", + [(ARMcmpNZ (and tGPR:$lhs, tGPR:$rhs), 0)]>; +// zero-extend byte def tUXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src), "uxtb $dst, $src", [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>, Requires<[IsThumb, HasV6]>; + +// zero-extend short def tUXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src), "uxth $dst, $src", [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>, From evan.cheng at apple.com Thu Jun 25 17:51:11 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 25 Jun 2009 15:51:11 -0700 Subject: [llvm-commits] [patch] MVN pattern for Thumb-2 to load t2_so_imm_not immediat