From evan.cheng at apple.com Mon Sep 28 00:28:43 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 28 Sep 2009 05:28:43 -0000 Subject: [llvm-commits] [llvm] r82968 - in /llvm/trunk: lib/CodeGen/SimpleRegisterCoalescing.cpp test/CodeGen/ARM/2009-09-27-CoalescerBug.ll test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll test/CodeGen/X86/sink-hoist.ll Message-ID: <200909280528.n8S5Shgv030202@zion.cs.uiuc.edu> Author: evancheng Date: Mon Sep 28 00:28:43 2009 New Revision: 82968 URL: http://llvm.org/viewvc/llvm-project?rev=82968&view=rev Log: Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of physical registers. This is especially critical for the later two since they start the live interval of a super-register. e.g. %DO = INSERT_SUBREG %D0, %S0, 1 If this instruction is eliminated, the register scavenger will not be happy as D0 is not defined previously. This fixes PR5055. Added: llvm/trunk/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp llvm/trunk/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll llvm/trunk/test/CodeGen/X86/sink-hoist.ll Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=82968&r1=82967&r2=82968&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon Sep 28 00:28:43 2009 @@ -2692,21 +2692,34 @@ unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; if (JoinedCopies.count(MI)) { // Delete all coalesced copies. + bool DoDelete = true; if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) { assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG || MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG || MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) && "Unrecognized copy instruction"); DstReg = MI->getOperand(0).getReg(); + if (TargetRegisterInfo::isPhysicalRegister(DstReg)) + // Do not delete extract_subreg, insert_subreg of physical + // registers unless the definition is dead. e.g. + // %DO = INSERT_SUBREG %D0, %S0, 1 + // or else the scavenger may complain. LowerSubregs will + // change this to an IMPLICIT_DEF later. + DoDelete = false; } if (MI->registerDefIsDead(DstReg)) { LiveInterval &li = li_->getInterval(DstReg); if (!ShortenDeadCopySrcLiveRange(li, MI)) ShortenDeadCopyLiveRange(li, MI); + DoDelete = true; + } + if (!DoDelete) + mii = next(mii); + else { + li_->RemoveMachineInstrFromMaps(MI); + mii = mbbi->erase(mii); + ++numPeep; } - li_->RemoveMachineInstrFromMaps(MI); - mii = mbbi->erase(mii); - ++numPeep; continue; } Added: llvm/trunk/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll?rev=82968&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll Mon Sep 28 00:28:43 2009 @@ -0,0 +1,24 @@ +; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 +; PR5055 + +module asm ".globl\09__aeabi_f2lz" +module asm ".set\09__aeabi_f2lz, __fixsfdi" +module asm "" + +define arm_aapcs_vfpcc i64 @__fixsfdi(float %a) nounwind { +entry: + %0 = fcmp olt float %a, 0.000000e+00 ; [#uses=1] + br i1 %0, label %bb, label %bb1 + +bb: ; preds = %entry + %1 = fsub float -0.000000e+00, %a ; [#uses=1] + %2 = tail call arm_aapcs_vfpcc i64 @__fixunssfdi(float %1) nounwind ; [#uses=1] + %3 = sub i64 0, %2 ; [#uses=1] + ret i64 %3 + +bb1: ; preds = %entry + %4 = tail call arm_aapcs_vfpcc i64 @__fixunssfdi(float %a) nounwind ; [#uses=1] + ret i64 %4 +} + +declare arm_aapcs_vfpcc i64 @__fixunssfdi(float) Modified: llvm/trunk/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll?rev=82968&r1=82967&r2=82968&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll (original) +++ llvm/trunk/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll Mon Sep 28 00:28:43 2009 @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=bfin -verify-machineinstrs -; XFAIL: * ; When joining live intervals of sub-registers, an MBB live-in list is not ; updated properly. The register scavenger asserts on an undefined register. Modified: llvm/trunk/test/CodeGen/X86/sink-hoist.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sink-hoist.ll?rev=82968&r1=82967&r2=82968&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sink-hoist.ll (original) +++ llvm/trunk/test/CodeGen/X86/sink-hoist.ll Mon Sep 28 00:28:43 2009 @@ -7,7 +7,7 @@ ; CHECK: foo: ; CHECK-NEXT: divsd -; CHECK-NEXT: testb $1, %dil +; CHECK: testb $1, %dil ; CHECK-NEXT: jne define double @foo(double %x, double %y, i1 %c) nounwind { From evan.cheng at apple.com Mon Sep 28 00:46:20 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 27 Sep 2009 22:46:20 -0700 Subject: [llvm-commits] [llvm] r82948 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/t2-imm.ll In-Reply-To: <200909272352.n8RNqx0j021061@zion.cs.uiuc.edu> References: <200909272352.n8RNqx0j021061@zion.cs.uiuc.edu> Message-ID: On Sep 27, 2009, at 4:52 PM, Anton Korobeynikov wrote: > > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=82948&r1=82947&r2=82948&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Sun Sep 27 18:52:58 > 2009 > @@ -96,6 +96,9 @@ > > MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); > MI->getOperand(0).setReg(DestReg); > + if (Orig->getOpcode() == ARM::MOVTi16) > + MI->getOperand(1).setReg(DestReg); > + > MBB.insert(I, MI); > } Hmm. This is interesting. Since MOVTi16 has a register source operand, it's not safe for it to be rematerialized. This change is wrong, but it's not going to be exercised. That said, I think it's good idea to re-materialize these instructions. So I believe the correct solution is to add a pseudo instruction that's printed as a pair of movw + movt instructions. That allows it to be re-materializable. Evan > > > > +let isReMaterializable = 1, isAsCheapAsAMove = 1, > + Constraints = "$src = $dst" in > +def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm: > $imm), > + DPFrm, IIC_iMOVi, > + "movt", " $dst, $imm", > + [(set GPR:$dst, > + (or (and GPR:$src, 0xffff), > + lo16AllZero:$imm))]>, UnaryDP, > + Requires<[IsARM, HasV6T2]> { > + let Inst{25} = 1; > } From stoklund at 2pi.dk Mon Sep 28 00:52:47 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 28 Sep 2009 07:52:47 +0200 Subject: [llvm-commits] [llvm] r82968 - in /llvm/trunk: lib/CodeGen/SimpleRegisterCoalescing.cpp test/CodeGen/ARM/2009-09-27-CoalescerBug.ll test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll test/CodeGen/X86/sink-hoist.ll In-Reply-To: <200909280528.n8S5Shgv030202@zion.cs.uiuc.edu> References: <200909280528.n8S5Shgv030202@zion.cs.uiuc.edu> Message-ID: <898940BA-112A-423D-B4B7-69F5D10637CF@2pi.dk> On 28/09/2009, at 07.28, Evan Cheng wrote: > > Coalescer should not delete extract_subreg, insert_subreg, and > subreg_to_reg of > physical registers. This is especially critical for the later two > since they > start the live interval of a super-register. e.g. > %DO = INSERT_SUBREG %D0, %S0, 1 > If this instruction is eliminated, the register scavenger will not > be happy as > D0 is not defined previously. > This fixes PR5055. Right. It should be harmless to leave them for LowerSubreg. Are we aiming to introduce the KILL instruction in a 2.7 time frame? It seems like a simple operation to me. > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll > (original) > +++ llvm/trunk/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll Mon > Sep 28 00:28:43 2009 > @@ -1,5 +1,4 @@ > ; RUN: llc < %s -march=bfin -verify-machineinstrs > -; XFAIL: * Awesome! From evan.cheng at apple.com Mon Sep 28 01:02:46 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 27 Sep 2009 23:02:46 -0700 Subject: [llvm-commits] [llvm] r82968 - in /llvm/trunk: lib/CodeGen/SimpleRegisterCoalescing.cpp test/CodeGen/ARM/2009-09-27-CoalescerBug.ll test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll test/CodeGen/X86/sink-hoist.ll In-Reply-To: <898940BA-112A-423D-B4B7-69F5D10637CF@2pi.dk> References: <200909280528.n8S5Shgv030202@zion.cs.uiuc.edu> <898940BA-112A-423D-B4B7-69F5D10637CF@2pi.dk> Message-ID: <3362F350-DC41-421F-91A6-35E2779F19FE@apple.com> On Sep 27, 2009, at 10:52 PM, Jakob Stoklund Olesen wrote: > > On 28/09/2009, at 07.28, Evan Cheng wrote: >> >> Coalescer should not delete extract_subreg, insert_subreg, and >> subreg_to_reg of >> physical registers. This is especially critical for the later two >> since they >> start the live interval of a super-register. e.g. >> %DO = INSERT_SUBREG %D0, %S0, 1 >> If this instruction is eliminated, the register scavenger will not >> be happy as >> D0 is not defined previously. >> This fixes PR5055. > > Right. It should be harmless to leave them for LowerSubreg. > > Are we aiming to introduce the KILL instruction in a 2.7 time frame? > It seems like a simple operation to me. It would be a nice clean up. If I (or someone else) have the time, I would like to get it in sooner rather than later. Evan > >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll >> (original) >> +++ llvm/trunk/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll >> Mon Sep 28 00:28:43 2009 >> @@ -1,5 +1,4 @@ >> ; RUN: llc < %s -march=bfin -verify-machineinstrs >> -; XFAIL: * > > Awesome! > From evan.cheng at apple.com Mon Sep 28 01:07:39 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 27 Sep 2009 23:07:39 -0700 Subject: [llvm-commits] [PATCH] Avoid overflow in scheduling In-Reply-To: <9a9942200909272117y4747ab92t918a1ab4313bc793@mail.gmail.com> References: <9a9942200909261319r2aea8972m778cf6283406bd6e@mail.gmail.com> <37B7525D-CB71-42FC-9B57-5E2EF0F8C7BC@apple.com> <4086D5F5-96A6-42F9-A549-6DB17570BE77@apple.com> <9a9942200909272117y4747ab92t918a1ab4313bc793@mail.gmail.com> Message-ID: On Sep 27, 2009, at 9:17 PM, Reid Kleckner wrote: > I added assertions to catch overflow, and they fired when I ran it on > the input. Should I really keep these in? I feel like it's always > assumed that there is no integer overflow in a program, and that any > overflow is an error. These assertions just clutter the code if we > move from shorts to ints. If you want to stick with shorts, then I > agree, because there is actually a risk of the overflow, they should > probably stay in. I think the assertion should stay because the bug is very hard to track down. If the field is changed to ints it should be adjusted accordingly. > > I think the characteristic of this input is that we have 35K BB's in > the function, and each line has a guard that creates a basic block > edge to a single bailing block. When it's time to do scheduling, that > manifests as more than SHRT_MAX predecessors, causing the overflow in > NumSuccs. > > Talking with jyasskin and nlewycky, we think that if LLVM wants the > language restriction that there be no more than SHRT_MAX incoming > edges to a basic block, that's fine, but the verifier should catch it, > because we run the verifier on our code. Otherwise, scheduling > probably needs to support more predecessors. > > One other option is to change the relevant shorts from signed to > unsigned, which I think would solve our problems. However, if we > simply doubled the input size, it would break again. Using ints > should only add 8 bytes to the entire class, which has plenty of > pointer fields and two SmallVectors. The size increase should only be > a small percentage. Even if the cost is small, I am still hesitant to grow it for the sake of the some extreme test. It almost feel like the type should be configurable for different uses. Evan > > For the curious, this is the bad .ll file linked to in the bug: > http://web.mit.edu/rnk/www/bad_ir_small.ll.bz2 (2.5 MB) > > Reid > > On Sun, Sep 27, 2009 at 1:19 AM, Evan Cheng > wrote: >> Also, could you first add assertions to catch the overflow? Thanks. >> >> Evan >> >> On Sep 26, 2009, at 3:36 PM, Evan Cheng wrote: >> >>> I am concerned this can increase memory usage though for all >>> "normal" >>> usage cases though. It can a real issue for embedded hosts. >>> >>> Evan >>> >>> On Sep 26, 2009, at 1:19 PM, Reid Kleckner wrote: >>> >>>> Hey all, >>>> >>>> One of our nasty regression test cases generates a ginormous (4 >>>> MB of >>>> bitcode) function that overflows a short integer in some >>>> instruction >>>> scheduling code. Is the attached fix OK? If so, I'll commit it. >>>> >>>> This fixes PR4401. >>>> >>>> Thanks, >>>> Reid >>>> >>> overflow.diff>_______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> From sabre at nondot.org Mon Sep 28 01:49:44 2009 From: sabre at nondot.org (Chris Lattner) Date: Mon, 28 Sep 2009 06:49:44 -0000 Subject: [llvm-commits] [llvm] r82970 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/select.ll Message-ID: <200909280649.n8S6njv9007835@zion.cs.uiuc.edu> Author: lattner Date: Mon Sep 28 01:49:44 2009 New Revision: 82970 URL: http://llvm.org/viewvc/llvm-project?rev=82970&view=rev Log: The select instruction is not neccesarily in the same block as the phi nodes. Make sure to phi translate from the right block. This fixes a llvm-building-llvm failure on GVN-PRE.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp llvm/trunk/test/Transforms/InstCombine/select.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=82970&r1=82969&r2=82970&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Mon Sep 28 01:49:44 2009 @@ -2002,10 +2002,11 @@ // not the true/false values. Value *TrueV = SI->getTrueValue(); Value *FalseV = SI->getFalseValue(); + BasicBlock *PhiTransBB = PN->getParent(); for (unsigned i = 0; i != NumPHIValues; ++i) { BasicBlock *ThisBB = PN->getIncomingBlock(i); - Value *TrueVInPred = TrueV->DoPHITranslation(I.getParent(), ThisBB); - Value *FalseVInPred = FalseV->DoPHITranslation(I.getParent(), ThisBB); + Value *TrueVInPred = TrueV->DoPHITranslation(PhiTransBB, ThisBB); + Value *FalseVInPred = FalseV->DoPHITranslation(PhiTransBB, ThisBB); Value *InV = 0; if (Constant *InC = dyn_cast(PN->getIncomingValue(i))) { InV = InC->isNullValue() ? FalseVInPred : TrueVInPred; Modified: llvm/trunk/test/Transforms/InstCombine/select.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select.ll?rev=82970&r1=82969&r2=82970&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/select.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/select.ll Mon Sep 28 01:49:44 2009 @@ -247,3 +247,19 @@ %b = select i1 %a, i32 %A, i32 %c ret i32 %b } + +define i32 @test29(i1 %cond, i32 %A, i32 %B) { +entry: + br i1 %cond, label %jump, label %ret +jump: + br label %ret +ret: + %c = phi i32 [%A, %jump], [%B, %entry] + %a = phi i1 [true, %jump], [false, %entry] + br label %next + +next: + %b = select i1 %a, i32 %A, i32 %c + ret i32 %b +} + From asl at math.spbu.ru Mon Sep 28 02:26:46 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 28 Sep 2009 07:26:46 -0000 Subject: [llvm-commits] [llvm] r82975 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.cpp ARMInstrInfo.td Message-ID: <200909280726.n8S7Qk1o012519@zion.cs.uiuc.edu> Author: asl Date: Mon Sep 28 02:26:46 2009 New Revision: 82975 URL: http://llvm.org/viewvc/llvm-project?rev=82975&view=rev Log: Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument. Disable rematting of it for now. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=82975&r1=82974&r2=82975&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Mon Sep 28 02:26:46 2009 @@ -96,8 +96,6 @@ MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); MI->getOperand(0).setReg(DestReg); - if (Orig->getOpcode() == ARM::MOVTi16) - MI->getOperand(1).setReg(DestReg); MBB.insert(I, MI); } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=82975&r1=82974&r2=82975&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Sep 28 02:26:46 2009 @@ -938,8 +938,7 @@ let Inst{25} = 1; } -let isReMaterializable = 1, isAsCheapAsAMove = 1, - Constraints = "$src = $dst" in +let isAsCheapAsAMove = 1, Constraints = "$src = $dst" in def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm), DPFrm, IIC_iMOVi, "movt", " $dst, $imm", From asl at math.spbu.ru Mon Sep 28 02:27:25 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 28 Sep 2009 11:27:25 +0400 Subject: [llvm-commits] [llvm] r82948 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/t2-imm.ll In-Reply-To: References: <200909272352.n8RNqx0j021061@zion.cs.uiuc.edu> Message-ID: Hello, Evan > Hmm. This is interesting. Since MOVTi16 has a register source operand, > it's not safe for it to be rematerialized. This change is wrong, but > it's not going to be exercised. Oh, right. I've disabled remtting in r82975 for now > That said, I think it's good idea to re-materialize these > instructions. So I believe the correct solution is to add a pseudo > instruction that's printed as a pair of movw + movt instructions. That > allows it to be re-materializable. Sounds good. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From baldrick at free.fr Mon Sep 28 02:28:19 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 28 Sep 2009 07:28:19 -0000 Subject: [llvm-commits] [gcc-plugin] r82976 - /gcc-plugin/trunk/x86/llvm-target.h Message-ID: <200909280728.n8S7SJkr012731@zion.cs.uiuc.edu> Author: baldrick Date: Mon Sep 28 02:28:18 2009 New Revision: 82976 URL: http://llvm.org/viewvc/llvm-project?rev=82976&view=rev Log: Treat all subfeatures uniformly, and wire up a few more. I mapped FMA to fma3 rather than fma4 because the GCC support was done by intel people, so presumably is for intel's fma3 rather than amd's fma4. Modified: gcc-plugin/trunk/x86/llvm-target.h Modified: gcc-plugin/trunk/x86/llvm-target.h URL: http://llvm.org/viewvc/llvm-project/gcc-plugin/trunk/x86/llvm-target.h?rev=82976&r1=82975&r2=82976&view=diff ============================================================================== --- gcc-plugin/trunk/x86/llvm-target.h (original) +++ gcc-plugin/trunk/x86/llvm-target.h Mon Sep 28 02:28:18 2009 @@ -850,24 +850,71 @@ F.setCPU(TARGET_64BIT ? "core2" : "yonah"); \ else \ F.setCPU(ix86_arch_string); \ - if (TARGET_64BIT) F.AddFeature("64bit"); \ - if (TARGET_MMX) F.AddFeature("mmx"); \ + \ + if (TARGET_64BIT) \ + F.AddFeature("64bit"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_64BIT) \ + F.AddFeature("64bit", false); \ + \ + if (TARGET_MMX) \ + F.AddFeature("mmx"); \ else if (target_flags_explicit & OPTION_MASK_ISA_MMX) \ F.AddFeature("mmx", false); \ - if (TARGET_SSE) F.AddFeature("sse"); \ + \ + if (TARGET_3DNOW) \ + F.AddFeature("3dnow"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_3DNOW) \ + F.AddFeature("3dnow", false); \ + \ + if (TARGET_3DNOW_A) \ + F.AddFeature("3dnowa"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_3DNOW_A) \ + F.AddFeature("3dnowa", false); \ + \ + if (TARGET_SSE) \ + F.AddFeature("sse"); \ else if (target_flags_explicit & OPTION_MASK_ISA_SSE) \ F.AddFeature("sse", false); \ - if (TARGET_SSE2) F.AddFeature("sse2"); \ + \ + if (TARGET_SSE2) \ + F.AddFeature("sse2"); \ else if (target_flags_explicit & OPTION_MASK_ISA_SSE2) \ F.AddFeature("sse2", false); \ - if (TARGET_SSE3) F.AddFeature("sse3"); \ + \ + if (TARGET_SSE3) \ + F.AddFeature("sse3"); \ else if (target_flags_explicit & OPTION_MASK_ISA_SSE3) \ F.AddFeature("sse3", false); \ - if (TARGET_SSSE3) F.AddFeature("ssse3"); \ - if (TARGET_SSE4_1) F.AddFeature("sse41"); \ - if (TARGET_SSE4_2) F.AddFeature("sse42"); \ - if (TARGET_3DNOW) F.AddFeature("3dnow"); \ - if (TARGET_3DNOW_A) F.AddFeature("3dnowa"); \ + \ + if (TARGET_SSSE3) \ + F.AddFeature("ssse3"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_SSSE3) \ + F.AddFeature("ssse3", false); \ + \ + if (TARGET_SSE4_1) \ + F.AddFeature("sse41"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_SSE4_1) \ + F.AddFeature("sse41", false); \ + \ + if (TARGET_SSE4_2) \ + F.AddFeature("sse42"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_SSE4_2) \ + F.AddFeature("sse42", false); \ + \ + if (TARGET_AVX) \ + F.AddFeature("avx"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_AVX) \ + F.AddFeature("avx", false); \ + \ + if (TARGET_FMA) \ + F.AddFeature("fma3"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_FMA) \ + F.AddFeature("fma3", false); \ + \ + if (TARGET_SSE4A) \ + F.AddFeature("sse4a"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_SSE4A) \ + F.AddFeature("sse4a", false); \ } #define LLVM_SET_IMPLICIT_FLOAT(flag_no_implicit_float) \ From gohman at apple.com Mon Sep 28 10:20:29 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 28 Sep 2009 08:20:29 -0700 Subject: [llvm-commits] [llvm] r82834 - in /llvm/trunk/lib/CodeGen: MachineLICM.cpp MachineSink.cpp In-Reply-To: <3CA33E5B-141F-48A1-BF09-550CE4930913@apple.com> References: <200909260234.n8Q2Y0Sd016383@zion.cs.uiuc.edu> <3CA33E5B-141F-48A1-BF09-550CE4930913@apple.com> Message-ID: I don't understand what you're asking here. What do you mean, and what problem would it fix? Dan On Sep 26, 2009, at 10:17 PM, Evan Cheng wrote: > Why not just add the phys register uses to the destination's livein > set? > > Evan > > On Sep 25, 2009, at 7:34 PM, Dan Gohman wrote: > >> Author: djg >> Date: Fri Sep 25 21:34:00 2009 >> New Revision: 82834 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=82834&view=rev >> Log: >> Don't hoist or sink instructions with physreg uses if the physreg is >> allocatable. Even if it doesn't appear to have any defs, it may >> latter >> on after register allocation. >> >> Modified: >> llvm/trunk/lib/CodeGen/MachineLICM.cpp >> llvm/trunk/lib/CodeGen/MachineSink.cpp >> >> Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=82834&r1=82833&r2=82834&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) >> +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Fri Sep 25 21:34:00 2009 >> @@ -44,6 +44,7 @@ >> const TargetMachine *TM; >> const TargetInstrInfo *TII; >> const TargetRegisterInfo *TRI; >> + BitVector AllocatableSet; >> >> // Various analyses that we use... >> MachineLoopInfo *LI; // Current MachineLoopInfo >> @@ -138,6 +139,7 @@ >> TII = TM->getInstrInfo(); >> TRI = TM->getRegisterInfo(); >> RegInfo = &MF.getRegInfo(); >> + AllocatableSet = TRI->getAllocatableSet(MF); >> >> // Get our Loop information... >> LI = &getAnalysis(); >> @@ -261,13 +263,20 @@ >> // we can move it, but only if the def is dead. >> if (MO.isUse()) { >> // If the physreg has no defs anywhere, it's just an ambient >> register >> - // and we can freely move its uses. >> + // and we can freely move its uses. Alternatively, if it's >> allocatable, >> + // it could get allocated to something with a def during >> allocation. >> if (!RegInfo->def_empty(Reg)) >> return false; >> + if (AllocatableSet.test(Reg)) >> + return false; >> // Check for a def among the register's aliases too. >> - for (const unsigned *Alias = TRI->getAliasSet(Reg); >> *Alias; ++Alias) >> - if (!RegInfo->def_empty(*Alias)) >> + for (const unsigned *Alias = TRI->getAliasSet(Reg); >> *Alias; ++Alias) { >> + unsigned AliasReg = *Alias; >> + if (!RegInfo->def_empty(AliasReg)) >> + return false; >> + if (AllocatableSet.test(AliasReg)) >> return false; >> + } >> // Otherwise it's safe to move. >> continue; >> } else if (!MO.isDead()) { >> >> Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=82834&r1=82833&r2=82834&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/MachineSink.cpp (original) >> +++ llvm/trunk/lib/CodeGen/MachineSink.cpp Fri Sep 25 21:34:00 2009 >> @@ -39,6 +39,7 @@ >> MachineFunction *CurMF; // Current MachineFunction >> MachineRegisterInfo *RegInfo; // Machine register information >> MachineDominatorTree *DT; // Machine dominator tree >> + BitVector AllocatableSet; // Which physregs are allocatable? >> >> public: >> static char ID; // Pass identification >> @@ -99,6 +100,7 @@ >> TRI = TM->getRegisterInfo(); >> RegInfo = &CurMF->getRegInfo(); >> DT = &getAnalysis(); >> + AllocatableSet = TRI->getAllocatableSet(*CurMF); >> >> bool EverMadeChange = false; >> >> @@ -180,13 +182,20 @@ >> // we can move it, but only if the def is dead. >> if (MO.isUse()) { >> // If the physreg has no defs anywhere, it's just an ambient >> register >> - // and we can freely move its uses. >> + // and we can freely move its uses. Alternatively, if it's >> allocatable, >> + // it could get allocated to something with a def during >> allocation. >> if (!RegInfo->def_empty(Reg)) >> return false; >> + if (AllocatableSet.test(Reg)) >> + return false; >> // Check for a def among the register's aliases too. >> - for (const unsigned *Alias = TRI->getAliasSet(Reg); >> *Alias; ++Alias) >> - if (!RegInfo->def_empty(*Alias)) >> + for (const unsigned *Alias = TRI->getAliasSet(Reg); >> *Alias; ++Alias) { >> + unsigned AliasReg = *Alias; >> + if (!RegInfo->def_empty(AliasReg)) >> + return false; >> + if (AllocatableSet.test(AliasReg)) >> return false; >> + } >> } else if (!MO.isDead()) { >> // A def that isn't dead. We can't move it. >> return false; >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From grosbach at apple.com Mon Sep 28 11:25:17 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 28 Sep 2009 09:25:17 -0700 Subject: [llvm-commits] [llvm] r82734 - in /llvm/trunk/lib: CodeGen/PrologEpilogInserter.cpp CodeGen/PrologEpilogInserter.h Target/ARM/ARMBaseRegisterInfo.cpp Target/ARM/Thumb1RegisterInfo.cpp In-Reply-To: <975E430D-FB46-4A03-A722-10537A055CC5@2pi.dk> References: <200909242352.n8ONqJGh025506@zion.cs.uiuc.edu> <975E430D-FB46-4A03-A722-10537A055CC5@2pi.dk> Message-ID: <34E61E7B-F61C-462C-BD5D-4A0FEE0B3580@apple.com> Hi Jakob, Thanks for the great feedback. I'll incorporate some changes today now that I'm back in the office (was sick over the weekend). Comments below. On Sep 25, 2009, at 12:47 AM, Jakob Stoklund Olesen wrote: > > On 25/09/2009, at 01.52, Jim Grosbach wrote: >> Start of revamping the register scavenging in PEI. ARM Thumb1 is >> the driving >> interest for this, as it currently reserves a register rather than >> using >> the scavenger for matierializing constants as needed. > > Great! Please see comments below. > >> +void PEI::scavengeFrameVirtualRegs(MachineFunction &Fn) { > ... >> + // Keep a map of which scratch reg we use for each virtual reg. >> + // FIXME: Is a map like this the best solution? Seems like >> overkill, >> + // but to get rid of it would need some fairly strong >> assumptions >> + // that may not be valid as this gets smarter about reuse and >> such. >> + IndexedMap ScratchRegForVirtReg; > > It seems that for now, we must require that live ranges of virtual > registers are disjoint. Otherwise we would need more than one > emergency spill slot in the worst case. > > With only one virtual register live at a time, the map is indeed > overkill. > > It would also be a good idea to enforce the one-virtual-register-at- > a-time rule with asserts here. > Agreed to both. As indicated by the comment, I was thinking towards doing something fancier when we start to re-use these. Allowing more than one to be live so long as the emergency spill slot is unused, or something like that. Thus, I didn't want to encode too many strong assumption in place that would make that harder. Upon reflection, however, I don't think that's a direction we should go. If we want the compiler to be that much smarter about reusing the constants, we should work towards letting the real register allocator do the work. This pass should be a quick and simple one to handle obvious cases and shouldn't try to get too smart. >> + ScratchRegForVirtReg.grow(Fn.getRegInfo().getLastVirtReg()); >> + >> + for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end >> (); ++I) { >> + MachineInstr *MI = I; >> + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) >> + if (MI->getOperand(i).isReg()) { >> + unsigned Reg = MI->getOperand(i).getReg(); >> + if (Reg && TRI->isVirtualRegister(Reg)) { > > Would it perhaps be possible to reduce nesting with 'continue' here? Can't see why not. > >> + // If we already have a scratch for this virtual >> register, use it >> + unsigned NewReg = ScratchRegForVirtReg[Reg]; >> + if (!NewReg) { >> + const TargetRegisterClass *RC = Fn.getRegInfo >> ().getRegClass(Reg); >> + NewReg = RS->FindUnusedReg(RC); >> + if (NewReg == 0) >> + // No register is "free". Scavenge a register. >> + // FIXME: Track SPAdj. Zero won't always be right >> + NewReg = RS->scavengeRegister(RC, I, 0); > > Ideally, I would like to get rid of FindUnusedReg(), so you could > just say scavengeRegister() here. The ARMLoadStoreOptimizer is the > only one to use FindUnusedReg() without immediately calling > scavengerRegister() when it fails. I am no sure if that is > intentional. I've been thinking about that, too. I can see the benefit in asking it for a register, but only if a spill isn't necessary. For example, when loading a constant, materializing the constant directly may be more expensive than a load, but still cheaper if spills are necessary. Nothing is being that smart currently, though. In practice, it looks like one could call scavengeRegister() directly without first calling FindUnusedReg() and get the single-call interface you're looking for. > > There is another issue here. FindUnusedReg() will give you a > register that is unused /at the current position/. You really need a > register that is unused in the whole live range of the virtual > register you are replacing. scavengeRegister() won't return a > register that is used by the instruction at I, but it looks like we > need a variant that can exclude from whole range of instructions. > > The rule should be: "NewReg must not be defined by any instruction > in the range, except for the last. NewReg must not be an > EarlyClobber operand on the last instruction." In the general case, yes, that's true. In the cases we're dealing with, however, we don't need to be that careful. The register is defined, then used in the next instruction or two. We're splitting out a single instruction referencing the frame when the constant offset is too large. Either we're adjusting the stack point by a constant value and need a register to hold the constant, or we're accessing a stack slot and need a register to hold the offset to the slot. Either way, if the register live range is such that it's insufficient to check if the register is available at the current location, then it's a flaw in the way the back end is using this pass. That said, that's an assumption worth enforcing. Perhaps in the loop, if we have an active scavenged register, we should add an assert() that the current instruction does not reference it. The reference we're looking for will still be a virtual register, so it won't fire on that. Hmmm. >> + assert (NewReg && "unable to scavenge register!"); >> + ScratchRegForVirtReg[Reg] = NewReg; >> + } >> + MI->getOperand(i).setReg(NewReg); > > For full generality, you need to watch out for subreg operands when > replacing a virtreg with a physreg. At least you should assert > (getSubReg()==0). Yeah, adding an assert is a good idea. We shouldn't be seeing any of that sort of thing, and it's best to verify that when possible. >> + } >> + } >> + RS->forward(MI); > > Yeah, I also want to get rid of forward() as a public method. Since > scavengeRegister takes an iterator argument that /must/ be next(MI) > anyway, there is really no point to having it. I'm a bit leery of merging it with scavengeRegister(). It feels more appropriate to keep those bits of functionality separate since they're logically distinct. I can envision wanting to do things like tracking to a point in the block and only conditionally scavenging a register before proceeding. > > Batch forwarding over a range of instructions is going to be faster > as well. forward(MachineBasicBlock::iterator I) just loops over calls to forward () currently. Any performance improvements available from merging the forwarding into scavengeRegister() should be equally applicable as improvements to the current implementation, I would think. Can you elaborate a bit on why you want to remove forward()? I like the idea of removing methods that aren't really necessary, but I'm not sure that's the case here. Are there other motivations? Regards, -Jim From gohman at apple.com Mon Sep 28 11:45:05 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 28 Sep 2009 09:45:05 -0700 Subject: [llvm-commits] [PATCH] Avoid overflow in scheduling In-Reply-To: <9a9942200909272117y4747ab92t918a1ab4313bc793@mail.gmail.com> References: <9a9942200909261319r2aea8972m778cf6283406bd6e@mail.gmail.com> <37B7525D-CB71-42FC-9B57-5E2EF0F8C7BC@apple.com> <4086D5F5-96A6-42F9-A549-6DB17570BE77@apple.com> <9a9942200909272117y4747ab92t918a1ab4313bc793@mail.gmail.com> Message-ID: <1F32C719-9D60-4037-9139-C7367627C2C1@apple.com> On Sep 27, 2009, at 9:17 PM, Reid Kleckner wrote: > > I think the characteristic of this input is that we have 35K BB's in > the function, and each line has a guard that creates a basic block > edge to a single bailing block. When it's time to do scheduling, that > manifests as more than SHRT_MAX predecessors, causing the overflow in > NumSuccs. The NumPreds and NumSuccs values are talking about scheduling units within a basic block, not basic blocks themselves. So it sounds like you not only have large numbers of BBs, but you also have some large individual BBs :-). > > Talking with jyasskin and nlewycky, we think that if LLVM wants the > language restriction that there be no more than SHRT_MAX incoming > edges to a basic block, that's fine, but the verifier should catch it, > because we run the verifier on our code. Otherwise, scheduling > probably needs to support more predecessors. I don't think we want a language restriction like this. I favor changing the fields to ints for now. I think there are some opportunities to make the scheduler use less memory that we can pursue instead of trying to get by with short fields. Dan From evan.cheng at apple.com Mon Sep 28 12:29:41 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 28 Sep 2009 10:29:41 -0700 Subject: [llvm-commits] [llvm] r82834 - in /llvm/trunk/lib/CodeGen: MachineLICM.cpp MachineSink.cpp In-Reply-To: References: <200909260234.n8Q2Y0Sd016383@zion.cs.uiuc.edu> <3CA33E5B-141F-48A1-BF09-550CE4930913@apple.com> Message-ID: On Sep 28, 2009, at 8:20 AM, Dan Gohman wrote: > I don't understand what you're asking here. What do you mean, and > what problem would it fix? I see cases where instructions are using physical registers that were not defined at machinesink time. These are function arguments, etc. We should be able to sink them assuming the bb livein set is updated accordingly. Evan > > Dan > > On Sep 26, 2009, at 10:17 PM, Evan Cheng wrote: > >> Why not just add the phys register uses to the destination's livein >> set? >> >> Evan >> >> On Sep 25, 2009, at 7:34 PM, Dan Gohman wrote: >> >>> Author: djg >>> Date: Fri Sep 25 21:34:00 2009 >>> New Revision: 82834 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=82834&view=rev >>> Log: >>> Don't hoist or sink instructions with physreg uses if the physreg is >>> allocatable. Even if it doesn't appear to have any defs, it may >>> latter >>> on after register allocation. >>> >>> Modified: >>> llvm/trunk/lib/CodeGen/MachineLICM.cpp >>> llvm/trunk/lib/CodeGen/MachineSink.cpp >>> >>> Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=82834&r1=82833&r2=82834&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) >>> +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Fri Sep 25 21:34:00 2009 >>> @@ -44,6 +44,7 @@ >>> const TargetMachine *TM; >>> const TargetInstrInfo *TII; >>> const TargetRegisterInfo *TRI; >>> + BitVector AllocatableSet; >>> >>> // Various analyses that we use... >>> MachineLoopInfo *LI; // Current MachineLoopInfo >>> @@ -138,6 +139,7 @@ >>> TII = TM->getInstrInfo(); >>> TRI = TM->getRegisterInfo(); >>> RegInfo = &MF.getRegInfo(); >>> + AllocatableSet = TRI->getAllocatableSet(MF); >>> >>> // Get our Loop information... >>> LI = &getAnalysis(); >>> @@ -261,13 +263,20 @@ >>> // we can move it, but only if the def is dead. >>> if (MO.isUse()) { >>> // If the physreg has no defs anywhere, it's just an ambient >>> register >>> - // and we can freely move its uses. >>> + // and we can freely move its uses. Alternatively, if >>> it's allocatable, >>> + // it could get allocated to something with a def during >>> allocation. >>> if (!RegInfo->def_empty(Reg)) >>> return false; >>> + if (AllocatableSet.test(Reg)) >>> + return false; >>> // Check for a def among the register's aliases too. >>> - for (const unsigned *Alias = TRI->getAliasSet(Reg); >>> *Alias; ++Alias) >>> - if (!RegInfo->def_empty(*Alias)) >>> + for (const unsigned *Alias = TRI->getAliasSet(Reg); >>> *Alias; ++Alias) { >>> + unsigned AliasReg = *Alias; >>> + if (!RegInfo->def_empty(AliasReg)) >>> + return false; >>> + if (AllocatableSet.test(AliasReg)) >>> return false; >>> + } >>> // Otherwise it's safe to move. >>> continue; >>> } else if (!MO.isDead()) { >>> >>> Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=82834&r1=82833&r2=82834&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/lib/CodeGen/MachineSink.cpp (original) >>> +++ llvm/trunk/lib/CodeGen/MachineSink.cpp Fri Sep 25 21:34:00 2009 >>> @@ -39,6 +39,7 @@ >>> MachineFunction *CurMF; // Current MachineFunction >>> MachineRegisterInfo *RegInfo; // Machine register information >>> MachineDominatorTree *DT; // Machine dominator tree >>> + BitVector AllocatableSet; // Which physregs are allocatable? >>> >>> public: >>> static char ID; // Pass identification >>> @@ -99,6 +100,7 @@ >>> TRI = TM->getRegisterInfo(); >>> RegInfo = &CurMF->getRegInfo(); >>> DT = &getAnalysis(); >>> + AllocatableSet = TRI->getAllocatableSet(*CurMF); >>> >>> bool EverMadeChange = false; >>> >>> @@ -180,13 +182,20 @@ >>> // we can move it, but only if the def is dead. >>> if (MO.isUse()) { >>> // If the physreg has no defs anywhere, it's just an ambient >>> register >>> - // and we can freely move its uses. >>> + // and we can freely move its uses. Alternatively, if >>> it's allocatable, >>> + // it could get allocated to something with a def during >>> allocation. >>> if (!RegInfo->def_empty(Reg)) >>> return false; >>> + if (AllocatableSet.test(Reg)) >>> + return false; >>> // Check for a def among the register's aliases too. >>> - for (const unsigned *Alias = TRI->getAliasSet(Reg); >>> *Alias; ++Alias) >>> - if (!RegInfo->def_empty(*Alias)) >>> + for (const unsigned *Alias = TRI->getAliasSet(Reg); >>> *Alias; ++Alias) { >>> + unsigned AliasReg = *Alias; >>> + if (!RegInfo->def_empty(AliasReg)) >>> + return false; >>> + if (AllocatableSet.test(AliasReg)) >>> return false; >>> + } >>> } else if (!MO.isDead()) { >>> // A def that isn't dead. We can't move it. >>> return false; >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > From devang.patel at gmail.com Mon Sep 28 12:31:25 2009 From: devang.patel at gmail.com (Devang Patel) Date: Mon, 28 Sep 2009 10:31:25 -0700 Subject: [llvm-commits] [llvm] r82060 - in /llvm/trunk: include/llvm/LLVMContext.h include/llvm/Metadata.h include/llvm/Value.h lib/VMCore/LLVMContext.cpp lib/VMCore/LLVMContextImpl.h lib/VMCore/Metadata.cpp lib/VMCore/Value.cpp In-Reply-To: <69CA0E3C-E4DE-4074-8D4C-399AC5405C78@apple.com> References: <200909161809.n8GI914r021614@zion.cs.uiuc.edu> <69CA0E3C-E4DE-4074-8D4C-399AC5405C78@apple.com> Message-ID: <352a1fb20909281031n2f06473fj38e47e979ef72ea@mail.gmail.com> Hi Chris On Sun, Sep 27, 2009 at 3:27 PM, Chris Lattner wrote: > On Sep 16, 2009, at 11:09 AM, Devang Patel wrote: >> URL: http://llvm.org/viewvc/llvm-project?rev=82060&view=rev >> Log: >> Add llvm::Metadata to manage metadata used in a context. >> This interface will be used to attach metadata with an instruction. > > Hi Devang, > > Just getting caught up on commits... Thanks! I have not checked in doc updates yet. >> +++ llvm/trunk/include/llvm/Metadata.h Wed Sep 16 13:09:00 2009 > > +#include "llvm/ADT/SmallSet.h" > > This isn't needed, please remove. ok >> +// >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> +/// Metadata - >> +/// Metadata manages metadata used in a context. >> + >> +/// MDKindID - This id identifies metadata kind the metadata store. >> Valid >> +/// ID values are 1 or higher. This ID is set by RegisterMDKind. >> +typedef unsigned MDKindID; >> +class Metadata { > > Please rename this MetadataContext or something like that. ?This class > *isn't* metadata, it is meta-metadata :). ok. How about ContextMetadata? It manages metadata for one llvm context. > Also, please don't use global typedefs like MDKindID. ?If it is > important enough to give the type a name (other than 'unsigned'), > please use a wrapper struct so that it is "a type safe typedef". ok >> +private: >> + ?typedef std::pair MDPairTy; >> + ?typedef SmallVector MDMapTy; >> + ?typedef DenseMap MDStoreTy; >> + >> + ?/// MetadataStore - Collection of metadata used in this context. >> + ?MDStoreTy MetadataStore; >> + >> + ?/// MDHandlerNames - Map to hold metadata handler names. >> + ?StringMap MDHandlerNames; > > It is unfortunate that implementation details of this class require > pulling in #includes. ?Please change these to be void*'s in the header > and cast to the right type in the .cpp file. ?An example of this is > llvm/Target/TargetLoweringObjectFile.h with "UniquingMap". > Alternatively, put all of this stuff into a "MetadataContextImpl" > class, and make this class have a pointer to that. ok > >> +public: >> + >> + ?/// RegisterMDKind - Register a new metadata kind and return its >> ID. >> + ?/// A metadata kind can be registered only once. >> + ?MDKindID RegisterMDKind(const char *Name); >> + >> + ?/// getMDKind - Return metadata kind. If the requested metadata >> kind >> + ?/// is not registered then return 0. >> + ?MDKindID getMDKind(const char *Name); > > The doxygen comment for this class should explain that this class is > the thing that handles uniquing and assignment of IDs for custom > metadata types, and should explain the restrictions on the names. ok > >> + ?/// getMD - Get the metadata of given kind attached with an >> Instruction. >> + ?/// If the metadata is not found then return 0. >> + ?MDNode *getMD(MDKindID Kind, const Instruction *Inst); >> + >> + ?/// setMD - Attach the metadata of given kind with an Instruction. >> + ?void setMD(MDKindID Kind, MDNode *Node, Instruction *Inst); > > This should probably be named "AddMD" not "setMD". ?"set" implies that > there can only be one. ok > > There should also be a "remove" method. And ReplaceMD. But I see below that you're suggesting to use AddMD to replace existing entry, if any. > >> + >> + ?/// ValueIsDeleted - This handler is used to update metadata store >> + ?/// when a value is deleted. >> + ?void ValueIsDeleted(Value *V) {} >> + ?void ValueIsDeleted(const Instruction *Inst); > > Is there any reason that Value needs to explicitly know about this? > Why not use the existing CallbackVH interfaces? ?If it would be much > more inefficient or something, then I can see having a custom > extension like this, but it would be nice to minimize this if possible. Right now it uses WeakVH. The goal is to either extend CallBackVH or write a new VH to handle "clone", "merge" etc.. >> +++ llvm/trunk/lib/VMCore/Metadata.cpp Wed Sep 16 13:09:00 2009 >> @@ -15,6 +15,7 @@ >> #include "llvm/Metadata.h" >> #include "llvm/LLVMContext.h" >> #include "llvm/Module.h" >> +#include "llvm/Instruction.h" >> #include "SymbolTableListTraitsImpl.h" >> using namespace llvm; >> >> @@ -251,3 +252,74 @@ >> NamedMDNode::~NamedMDNode() { >> ? dropAllReferences(); >> } >> + >> +// >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> +//Metadata implementation >> +// >> + >> +/// RegisterMDKind - Register a new metadata kind and return its ID. >> +/// A metadata kind can be registered only once. >> +MDKindID Metadata::RegisterMDKind(const char *Name) { > > This needs to enforce various constraints on the name. ?For example, > you can't have a space in the name etc. ?Whatever requirements the .ll > lexer have should be enforced here with an assert. Right now lexer hardcodes string names, but I'm going to update lexer. I didn't plan, but l'll add check here also. > >> + ?MDKindID Count = MDHandlerNames.size(); >> + ?StringMap::iterator I = MDHandlerNames.find(Name); >> + ?assert(I == MDHandlerNames.end() && "Already registered MDKind!"); > > Please only do the lookup in MDHandlerNames.find when assertions are > enabled. ok > >> + ?MDHandlerNames[Name] = Count + 1; >> + ?return Count + 1; >> +} >> + >> +/// getMDKind - Return metadata kind. If the requested metadata kind >> +/// is not registered then return 0. >> +MDKindID Metadata::getMDKind(const char *Name) { >> + ?StringMap::iterator I = MDHandlerNames.find(Name); >> + ?if (I == MDHandlerNames.end()) >> + ? ?return 0; >> + >> + ?return I->getValue(); >> +} >> + >> +/// setMD - Attach the metadata of given kind with an Instruction. >> +void Metadata::setMD(MDKindID MDKind, MDNode *Node, Instruction >> *Inst) { >> + ?MDStoreTy::iterator I = MetadataStore.find(Inst); >> + ?Inst->HasMetadata = true; >> + ?if (I == MetadataStore.end()) { >> + ? ?MDMapTy Info; >> + ? ?Info.push_back(std::make_pair(MDKind, Node)); >> + ? ?MetadataStore.insert(std::make_pair(Inst, Info)); >> + ? ?return; >> + ?} >> + >> + ?MDMapTy &Info = I->second; >> + ?Info.push_back(std::make_pair(MDKind, Node)); >> + ?return; > > It is simpler to write this as: > > void Metadata::setMD(MDKindID MDKind, MDNode *Node, Instruction *Inst) { > ? asert(Node == 0 && "Use removeMD to remove metadata"); > > ? Inst->HasMetadata = true; > ? MDMapTy &Entry = MetadataStore[I]; > ? if (Entry doesn't already have a "MDKind" entry) > ? ? Entry.push_back(std::make_pair(MDKind, Node)); > ? else // Otherwise replace it. > ? ? Entry[j] = Node; > } > > We don't want to allow multiple entries for one MDKind. ok > >> +/// getMD - Get the metadata of given kind attached with an >> Instruction. >> +/// If the metadata is not found then return 0. >> +MDNode *Metadata::getMD(MDKindID MDKind, const Instruction *Inst) { >> + ?MDNode *Node = NULL; >> + ?MDStoreTy::iterator I = MetadataStore.find(Inst); >> + ?if (I == MetadataStore.end()) >> + ? ?return Node; >> + >> + ?MDMapTy &Info = I->second; >> + ?for (MDMapTy::iterator I = Info.begin(), E = Info.end(); I != E; + >> +I) >> + ? ?if (I->first == MDKind) >> + ? ? ?Node = dyn_cast_or_null(I->second); > > We shouldn't allow duplicates, so this can be simplified to early > return when MDKind is found. ?You can eliminate the Node variable. ok >> +/// ValueIsDeleted - This handler is used to update metadata store >> +/// when a value is deleted. >> +void Metadata::ValueIsDeleted(const Instruction *Inst) { >> + ?// Find Metadata handles for this instruction. >> + ?MDStoreTy::iterator I = MetadataStore.find(Inst); >> + ?if (I == MetadataStore.end()) >> + ? ?return; > > This is a serious logic error if HasMetadata is set on an instruction > but it doesn't have an entry in MetadataStore. ok, I'll put an assert here instead of early return. >> + ?MDMapTy &Info = I->second; >> + >> + ?// FIXME : Give all metadata handlers a chance to adjust. >> + >> + ?// Remove the entries for this instruction. >> + ?Info.clear(); >> + ?MetadataStore.erase(Inst); > > This should erase(I) to avoid having to do another lookup. ok Thanks! - Devang From devang.patel at gmail.com Mon Sep 28 12:37:32 2009 From: devang.patel at gmail.com (Devang Patel) Date: Mon, 28 Sep 2009 10:37:32 -0700 Subject: [llvm-commits] [llvm] r82062 - /llvm/trunk/include/llvm/Support/IRBuilder.h In-Reply-To: <6AE32737-ECFD-4D54-9F1C-ABE2629C01CF@apple.com> References: <200909161816.n8GIGCZa022582@zion.cs.uiuc.edu> <6AE32737-ECFD-4D54-9F1C-ABE2629C01CF@apple.com> Message-ID: <352a1fb20909281037x3713fbd0w8e117b462327e935@mail.gmail.com> Chris, On Sun, Sep 27, 2009 at 3:35 PM, Chris Lattner wrote: > On Sep 16, 2009, at 11:16 AM, Devang Patel wrote: >> URL: http://llvm.org/viewvc/llvm-project?rev=82062&view=rev >> Log: >> Add an interface to attach debugging information with an instruction. > > Ok, a couple of quibbles: > >> +++ llvm/trunk/include/llvm/Support/IRBuilder.h Wed Sep 16 13:16:11 >> 2009 >> @@ -20,6 +20,7 @@ >> #include "llvm/GlobalAlias.h" >> #include "llvm/GlobalVariable.h" >> #include "llvm/Function.h" >> +#include "llvm/Metadata.h" > > This shouldn't be needed with changes below: > >> #include "llvm/LLVMContext.h" >> #include "llvm/ADT/Twine.h" >> #include "llvm/Support/ConstantFolder.h" >> @@ -60,35 +61,38 @@ >> class IRBuilder : public Inserter { >> ? BasicBlock *BB; >> ? BasicBlock::iterator InsertPt; >> + ?MDKindID MDKind; >> + ?MDNode *CurLocation; >> ? LLVMContext &Context; >> ? T Folder; > > ... > >> >> + ?/// SetCurrentLocation - This specifies the location information >> used >> + ?/// by debugging information. >> + ?void SetCurrentLocation(MDNode *L) { >> + ? ?if (MDKind == 0) { > > MDKind should be an argument to SetCurrentLocation. ?IRBuilder should > not implicitly look it up. IMO IRBuilder clients do not need to know about MDKind that is used for debug info. In fact they don't know how debug location info is encoded. The IRBuilder handles this transparently. The FE keeps track of current source location for many reasons anyway. Whenever the location is changed, the IRBuilder is notified (through SetCurrentDebugLocation) if -g is specified on the command line. And IRBuilder is responsible to encode this appropriately in IR. This is why I renamed it as "SetCurrentDebugLocation(). > > Also, you renamed SetCurrentLocation -> SetCurrentDebugLocation. ?Why > not rename it to "SetDebugLocation"? - Devang > >> ? /// Insert - Insert and return the specified instruction. >> ? template >> ? InstTy *Insert(InstTy *I, const Twine &Name = "") const { >> ? ? this->InsertHelper(I, Name, BB, InsertPt); >> + ? ?if (CurLocation) >> + ? ? ?Context.getMetadata().setMD(MDKind, CurLocation, I); > > We should have an API on instruction that forwards to the MD api: > ? ?Something like: I->AddMD(MDKind, CurLocation); > > Most clients should only poke the "Metadata" class when they register > their MDKind, and they should pass them around as opaque unsigned's. > > -Chris > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From devang.patel at gmail.com Mon Sep 28 12:40:09 2009 From: devang.patel at gmail.com (Devang Patel) Date: Mon, 28 Sep 2009 10:40:09 -0700 Subject: [llvm-commits] [llvm] r82063 - in /llvm/trunk/lib/AsmParser: LLLexer.cpp LLParser.cpp LLToken.h In-Reply-To: <24922F00-A607-4B88-AE4C-1AA5730B5E3F@apple.com> References: <200909161818.n8GII6tD022837@zion.cs.uiuc.edu> <24922F00-A607-4B88-AE4C-1AA5730B5E3F@apple.com> Message-ID: <352a1fb20909281040g30177202r3d85c3a99f954ef0@mail.gmail.com> Chris, On Sun, Sep 27, 2009 at 3:36 PM, Chris Lattner wrote: > On Sep 16, 2009, at 11:18 AM, Devang Patel wrote: >> URL: http://llvm.org/viewvc/llvm-project?rev=82063&view=rev >> Log: >> Parse debug info attached with an instruction. > > Why is debug info a special case here? ?Arbitrarily extensible > metadata can't be extensible if you have to hack the parser :) > Yes! I am going to fix this. - Devang From devang.patel at gmail.com Mon Sep 28 12:44:44 2009 From: devang.patel at gmail.com (Devang Patel) Date: Mon, 28 Sep 2009 10:44:44 -0700 Subject: [llvm-commits] [llvm] r82077 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp In-Reply-To: <900D02FA-9206-479C-ABE7-6BDCAEAE039A@apple.com> References: <200909162039.n8GKdBvu008848@zion.cs.uiuc.edu> <900D02FA-9206-479C-ABE7-6BDCAEAE039A@apple.com> Message-ID: <352a1fb20909281044v562db286j30ea9cb3e85b168d@mail.gmail.com> Chris, On Sun, Sep 27, 2009 at 3:40 PM, Chris Lattner wrote: > On Sep 16, 2009, at 1:39 PM, Devang Patel wrote: > Author: dpatel >> Date: Wed Sep 16 15:39:11 2009 >> New Revision: 82077 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=82077&view=rev >> Log: >> At iSel time, update DebugLoc based on debug info attached with an >> instruction. > > Ok, > >> ? // Lower all of the non-terminator instructions. If a call is >> emitted >> ? // as a tail call, cease emitting nodes for this block. >> - ?for (BasicBlock::iterator I = Begin; I != End && !SDL- >> >HasTailCall; ++I) >> + ?for (BasicBlock::iterator I = Begin; I != End && !SDL- >> >HasTailCall; ++I) { >> + ? ?if (MDDbgKind) { >> + ? ? ?// Update DebugLoc if debug information is attached with this >> + ? ? ?// instruction. >> + ? ? ?if (MDNode *Dbg = >> + ? ? ? dyn_cast_or_null(TheMetadata.getMD(MDDbgKind, I))) { > > This cast should not be needed, getMD returns an MDNode*. ok > >> + ?Metadata &TheMetadata = Fn.getContext().getMetadata(); >> + ?MDKindID MDDbgKind = TheMetadata.getMDKind("dbg"); >> + >> ? // Iterate over all basic blocks in the function. >> ? for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { >> ? ? BasicBlock *LLVMBB = &*I; >> @@ -722,6 +739,18 @@ >> ? ? ? FastIS->startNewBlock(BB); >> ? ? ? // Do FastISel on as many instructions as possible. >> ? ? ? for (; BI != End; ++BI) { >> + ? ? if (MDDbgKind) { >> + ? ? ? // Update DebugLoc if debug information is attached with this >> + ? ? ? // instruction. >> + ? ? ? if (MDNode *Dbg = >> + ? ? ? ? ? dyn_cast_or_null(TheMetadata.getMD(MDDbgKind, BI))) { > > Likewise, also, why is this code duplicated in two places? Once for FastISel and once for SelectBasicBlock() when FastISel is not used. - Devang From stoklund at 2pi.dk Mon Sep 28 13:23:47 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 28 Sep 2009 20:23:47 +0200 Subject: [llvm-commits] [llvm] r82734 - in /llvm/trunk/lib: CodeGen/PrologEpilogInserter.cpp CodeGen/PrologEpilogInserter.h Target/ARM/ARMBaseRegisterInfo.cpp Target/ARM/Thumb1RegisterInfo.cpp In-Reply-To: <34E61E7B-F61C-462C-BD5D-4A0FEE0B3580@apple.com> References: <200909242352.n8ONqJGh025506@zion.cs.uiuc.edu> <975E430D-FB46-4A03-A722-10537A055CC5@2pi.dk> <34E61E7B-F61C-462C-BD5D-4A0FEE0B3580@apple.com> Message-ID: On 28/09/2009, at 18.25, Jim Grosbach wrote: > On Sep 25, 2009, at 12:47 AM, Jakob Stoklund Olesen wrote: >> It seems that for now, we must require that live ranges of virtual >> registers are disjoint. Otherwise we would need more than one >> emergency spill slot in the worst case. >> >> With only one virtual register live at a time, the map is indeed >> overkill. >> >> It would also be a good idea to enforce the one-virtual-register-at- >> a-time rule with asserts here. > > Agreed to both. As indicated by the comment, I was thinking towards > doing something fancier when we start to re-use these. Allowing more > than one to be live so long as the emergency spill slot is unused, > or something like that. Thus, I didn't want to encode too many > strong assumption in place that would make that harder. It is definitely possible to do something fancier here. The thing to remember, though, is that this pass must work /every/ time. A clever trick that relies on a register or the emergency spill slot being available will maybe work 99% of the time, but we must have a fallback solution for the last 1%. Therefore, if virtual registers overlap, we must have two (or more) emergency spill slots. In a situation like this, I think we need to make clear rules for the scavenger clients: If your virtual registers don't overlap, the scavenger will work every time. Clients must follow the rules, otherwise there will be weird functions that don't compile. If a client needs more flexibility, we can change the rules. For instance: "You must give the scavenger as many emergency spill slots as the maximum possible number of simultaneous virtual registers". I don't think that is needed for now. Fancy code can give us better performance, for instance by reducing the number of emergency spills, but we must have a worst-case fallback always. > Upon reflection, however, I don't think that's a direction we should > go. If we want the compiler to be that much smarter about reusing > the constants, we should work towards letting the real register > allocator do the work. This pass should be a quick and simple one to > handle obvious cases and shouldn't try to get too smart. That is probably true. We can improve performance by using available callee-saved registers, and optimizing emergency spill locations. If things get more complicated, it is probably a good idea to involve the register allocator somehow. [...] >> Ideally, I would like to get rid of FindUnusedReg(), so you could >> just say scavengeRegister() here. The ARMLoadStoreOptimizer is the >> only one to use FindUnusedReg() without immediately calling >> scavengerRegister() when it fails. I am no sure if that is >> intentional. > > I've been thinking about that, too. I can see the benefit in asking > it for a register, but only if a spill isn't necessary. For example, > when loading a constant, materializing the constant directly may be > more expensive than a load, but still cheaper if spills are > necessary. Nothing is being that smart currently, though. In > practice, it looks like one could call scavengeRegister() directly > without first calling FindUnusedReg() and get the single-call > interface you're looking for. I think that scavengerRegister should implicitly call FindUnusedReg so that clients don't have to worry about it. I can see a case for still needing a raw FindUnusedReg, yes. But the needed function is probably really FindUnusedRegThatIsAlsoNotUsedByThisInstructionRange(). Such clever clients must always be able to handle FindUnusedReg returning 0. It looks like the ARMLoadStoreOptimizer handles that correctly. >> There is another issue here. FindUnusedReg() will give you a >> register that is unused /at the current position/. You really need >> a register that is unused in the whole live range of the virtual >> register you are replacing. scavengeRegister() won't return a >> register that is used by the instruction at I, but it looks like we >> need a variant that can exclude from whole range of instructions. >> >> The rule should be: "NewReg must not be defined by any instruction >> in the range, except for the last. NewReg must not be an >> EarlyClobber operand on the last instruction." > > In the general case, yes, that's true. In the cases we're dealing > with, however, we don't need to be that careful. The register is > defined, then used in the next instruction or two. We're splitting > out a single instruction referencing the frame when the constant > offset is too large. Either we're adjusting the stack point by a > constant value and need a register to hold the constant, or we're > accessing a stack slot and need a register to hold the offset to the > slot. Either way, if the register live range is such that it's > insufficient to check if the register is available at the current > location, then it's a flaw in the way the back end is using this pass. An example from the Blackfin backend. Storing a 16-bit subregister to a stack slot: STORE16fi P0.L, , 0 With the new vreg code, eliminateFrameIndex will produce: %reg2000 = LOADuimm16 100 %reg2000 = ADDpp %reg2000, %FP STORE16pi %reg2000, %P0.L Now we need to replace the vreg with a scavenged register. Assume all P-class registers are used, so we must scavenge one. If scavengeRegister() chooses to scavenge P0, we are dead - the code would become STORE32pi %FP, emergengy-slot, P0 %P0 = LOADuimm16 100 %P0 = ADDpp %P0, %FP STORE16pi %P0, %P0.L LOAD32pi %P0, %FP, emergency-slot This disaster won't actually happen because the heuristics in RegScavenger::findSurvivorReg() choose the candidate that is untouched for the longest time. But that is just a heuristic, we shouldn't rely on that. I think scavengeRegister needs to examine all three instructions (the live range of %reg2000) to avoid such disasters. > That said, that's an assumption worth enforcing. Perhaps in the > loop, if we have an active scavenged register, we should add an > assert() that the current instruction does not reference it. The > reference we're looking for will still be a virtual register, so it > won't fire on that. Hmmm. That is a very good idea. It is simple to do, and you are scanning operands anyway. [...] >> Yeah, I also want to get rid of forward() as a public method. Since >> scavengeRegister takes an iterator argument that /must/ be next(MI) >> anyway, there is really no point to having it. > > I'm a bit leery of merging it with scavengeRegister(). It feels more > appropriate to keep those bits of functionality separate since > they're logically distinct. I can envision wanting to do things like > tracking to a point in the block and only conditionally scavenging a > register before proceeding. >> >> Batch forwarding over a range of instructions is going to be faster >> as well. > > forward(MachineBasicBlock::iterator I) just loops over calls to > forward() currently. Any performance improvements available from > merging the forwarding into scavengeRegister() should be equally > applicable as improvements to the current implementation, I would > think. Yes. The performance improvement I am after mostly involves the four BitVectors in RegScavenger::forward(). They currently cost four mallocs and frees per instruction. By swapping forward() and forward (MI), we could make a tighter loop around the core logic, and only allocate BitVectors once per bulk skip. > Can you elaborate a bit on why you want to remove forward()? I like > the idea of removing methods that aren't really necessary, but I'm > not sure that's the case here. Are there other motivations? Forget about performance. The impact of those four BitVectors probably can't be measured. I want to eliminate redundancy from the API. Right now, you have to call forward(MI) to advance the scavenger to your position. Then you call scavengeRegister(RC, I, 0) where I /must/ be equal to next(MI). It is an error to pass any other iterator, so what is the point of having the argument? So you can choose to remove the iterator argument from scavengeRegister (), or you can get rid of forward() (as a public method, anyway). I am shooting for forward() because the semantics are already a bit weird. Calling forward(MI) places the scavenger /after/ MI while BuildMI() inserts instructions /before/ the iterator. That is why you are calling forward() at the bottom of you loop, rather than at the top. There are good reasons for this, but it is still weird. By removing forward(), we push the weirdness into the RegScavenger. If the choose to retain FindUnusedReg, it would need to take an iterator argument as well. But given the discussion above, I think that both methods should take two iterator arguments specifying a range of instructions that must not be using the returned register. From dpatel at apple.com Mon Sep 28 13:31:58 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 28 Sep 2009 18:31:58 -0000 Subject: [llvm-commits] [llvm] r82999 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <200909281831.n8SIVx09021679@zion.cs.uiuc.edu> Author: dpatel Date: Mon Sep 28 13:31:56 2009 New Revision: 82999 URL: http://llvm.org/viewvc/llvm-project?rev=82999&view=rev Log: Remove dead code. Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=82999&r1=82998&r2=82999&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Sep 28 13:31:56 2009 @@ -1267,15 +1267,11 @@ AssemblyAnnotationWriter *AnnotationWriter; std::vector NumberedTypes; - // Each MDNode is assigned unique MetadataIDNo. - std::map MDNodes; - unsigned MetadataIDNo; - public: inline AssemblyWriter(formatted_raw_ostream &o, SlotTracker &Mac, const Module *M, AssemblyAnnotationWriter *AAW) - : Out(o), Machine(Mac), TheModule(M), AnnotationWriter(AAW), MetadataIDNo(0) { + : Out(o), Machine(Mac), TheModule(M), AnnotationWriter(AAW) { AddModuleTypesToPrinter(TypePrinter, NumberedTypes, M); } From gohman at apple.com Mon Sep 28 13:38:53 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 28 Sep 2009 18:38:53 -0000 Subject: [llvm-commits] [llvm] r83001 - /llvm/trunk/lib/Analysis/README.txt Message-ID: <200909281838.n8SIcrEO024081@zion.cs.uiuc.edu> Author: djg Date: Mon Sep 28 13:38:53 2009 New Revision: 83001 URL: http://llvm.org/viewvc/llvm-project?rev=83001&view=rev Log: Create a README.txt for lib/Analysis, and add an entry. Added: llvm/trunk/lib/Analysis/README.txt Added: llvm/trunk/lib/Analysis/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/README.txt?rev=83001&view=auto ============================================================================== --- llvm/trunk/lib/Analysis/README.txt (added) +++ llvm/trunk/lib/Analysis/README.txt Mon Sep 28 13:38:53 2009 @@ -0,0 +1,18 @@ +Analysis Opportunities: + +//===---------------------------------------------------------------------===// + +In test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll, the +ScalarEvolution expression for %r is this: + + {1,+,3,+,2} + +Outside the loop, this could be evaluated simply as (%n * %n), however +ScalarEvolution currently evaluates it as + + (-2 + (2 * (trunc i65 (((zext i64 (-2 + %n) to i65) * (zext i64 (-1 + %n) to i65)) /u 2) to i64)) + (3 * %n)) + +In addition to being much more complicated, it involves i65 arithmetic, +which is very inefficient when expanded into code. + +//===---------------------------------------------------------------------===// From gohman at apple.com Mon Sep 28 13:40:28 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 28 Sep 2009 18:40:28 -0000 Subject: [llvm-commits] [llvm] r83002 - /llvm/trunk/test/Transforms/LoopRotate/preserve-scev.ll Message-ID: <200909281840.n8SIeSpe024508@zion.cs.uiuc.edu> Author: djg Date: Mon Sep 28 13:40:27 2009 New Revision: 83002 URL: http://llvm.org/viewvc/llvm-project?rev=83002&view=rev Log: Add a testcase to help test analysis preservation. Added: llvm/trunk/test/Transforms/LoopRotate/preserve-scev.ll Added: llvm/trunk/test/Transforms/LoopRotate/preserve-scev.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopRotate/preserve-scev.ll?rev=83002&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopRotate/preserve-scev.ll (added) +++ llvm/trunk/test/Transforms/LoopRotate/preserve-scev.ll Mon Sep 28 13:40:27 2009 @@ -0,0 +1,47 @@ +; RUN: opt < %s -loop-rotate -loop-reduce -disable-output + +define fastcc void @foo() nounwind { +BB: + br label %BB1 + +BB1: ; preds = %BB19, %BB + br label %BB4 + +BB2: ; preds = %BB4 + %tmp = bitcast i32 undef to i32 ; [#uses=1] + br label %BB4 + +BB4: ; preds = %BB3, %BB1 + %tmp5 = phi i32 [ undef, %BB1 ], [ %tmp, %BB2 ] ; [#uses=1] + br i1 false, label %BB8, label %BB2 + +BB8: ; preds = %BB6 + %tmp7 = bitcast i32 %tmp5 to i32 ; [#uses=2] + br i1 false, label %BB9, label %BB13 + +BB9: ; preds = %BB12, %BB8 + %tmp10 = phi i32 [ %tmp11, %BB12 ], [ %tmp7, %BB8 ] ; [#uses=2] + %tmp11 = add i32 %tmp10, 1 ; [#uses=1] + br label %BB12 + +BB12: ; preds = %BB9 + br i1 false, label %BB9, label %BB17 + +BB13: ; preds = %BB15, %BB8 + %tmp14 = phi i32 [ %tmp16, %BB15 ], [ %tmp7, %BB8 ] ; [#uses=1] + br label %BB15 + +BB15: ; preds = %BB13 + %tmp16 = add i32 %tmp14, -1 ; [#uses=1] + br i1 false, label %BB13, label %BB18 + +BB17: ; preds = %BB12 + br label %BB19 + +BB18: ; preds = %BB15 + br label %BB19 + +BB19: ; preds = %BB18, %BB17 + %tmp20 = phi i32 [ %tmp10, %BB17 ], [ undef, %BB18 ] ; [#uses=0] + br label %BB1 +} From evan.cheng at apple.com Mon Sep 28 15:26:50 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 28 Sep 2009 13:26:50 -0700 Subject: [llvm-commits] [PATCH] Avoid overflow in scheduling In-Reply-To: <1F32C719-9D60-4037-9139-C7367627C2C1@apple.com> References: <9a9942200909261319r2aea8972m778cf6283406bd6e@mail.gmail.com> <37B7525D-CB71-42FC-9B57-5E2EF0F8C7BC@apple.com> <4086D5F5-96A6-42F9-A549-6DB17570BE77@apple.com> <9a9942200909272117y4747ab92t918a1ab4313bc793@mail.gmail.com> <1F32C719-9D60-4037-9139-C7367627C2C1@apple.com> Message-ID: <72390274-404F-4A0F-B439-3027F7D6E03E@apple.com> On Sep 28, 2009, at 9:45 AM, Dan Gohman wrote: > > On Sep 27, 2009, at 9:17 PM, Reid Kleckner wrote: >> >> I think the characteristic of this input is that we have 35K BB's in >> the function, and each line has a guard that creates a basic block >> edge to a single bailing block. When it's time to do scheduling, >> that >> manifests as more than SHRT_MAX predecessors, causing the overflow in >> NumSuccs. > > The NumPreds and NumSuccs values are talking about scheduling > units within a basic block, not basic blocks themselves. So it sounds > like you not only have large numbers of BBs, but you also have > some large individual BBs :-). > >> >> Talking with jyasskin and nlewycky, we think that if LLVM wants the >> language restriction that there be no more than SHRT_MAX incoming >> edges to a basic block, that's fine, but the verifier should catch >> it, >> because we run the verifier on our code. Otherwise, scheduling >> probably needs to support more predecessors. > > I don't think we want a language restriction like this. I favor > changing the > fields to ints for now. > > I think there are some opportunities to make the scheduler use less > memory that we can pursue instead of trying to get by with short > fields. Alright. Evan > > Dan > From stoklund at 2pi.dk Mon Sep 28 15:32:27 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 28 Sep 2009 20:32:27 -0000 Subject: [llvm-commits] [llvm] r83006 - in /llvm/trunk: include/llvm/Target/Target.td include/llvm/Target/TargetInstrInfo.h lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/Alpha/AlphaCodeEmitter.cpp lib/Target/PowerPC/PPCCodeEmitter.cpp lib/Target/X86/AsmPrinter/X86MCInstLower.cpp lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86InstrInfo.cpp utils/TableGen/AsmWriterEmitter.cpp utils/TableGen/CodeEmitterGen.cpp utils/TableGen/CodeGenTarget.cpp utils/TableGen/InstrInfoEmitter.cpp Message-ID: <200909282032.n8SKWSQ8009231@zion.cs.uiuc.edu> Author: stoklund Date: Mon Sep 28 15:32:26 2009 New Revision: 83006 URL: http://llvm.org/viewvc/llvm-project?rev=83006&view=rev Log: Introduce the TargetInstrInfo::KILL machine instruction and get rid of the unused DECLARE instruction. KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF in the places where IMPLICIT_DEF is just used to alter liveness of physical registers. Modified: llvm/trunk/include/llvm/Target/Target.td llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp llvm/trunk/utils/TableGen/CodeEmitterGen.cpp llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=83006&r1=83005&r2=83006&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Mon Sep 28 15:32:26 2009 @@ -426,12 +426,12 @@ let Namespace = "TargetInstrInfo"; let hasCtrlDep = 1; } -def DECLARE : Instruction { +def KILL : Instruction { let OutOperandList = (ops); let InOperandList = (ops variable_ops); let AsmString = ""; let Namespace = "TargetInstrInfo"; - let hasCtrlDep = 1; + let neverHasSideEffects = 1; } def EXTRACT_SUBREG : Instruction { let OutOperandList = (ops unknown:$dst); Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=83006&r1=83005&r2=83006&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Sep 28 15:32:26 2009 @@ -51,7 +51,10 @@ DBG_LABEL = 2, EH_LABEL = 3, GC_LABEL = 4, - // FIXME: DECLARE is removed. Readjust enum values ? + + /// KILL - This instruction is a noop that is used only to adjust the liveness + /// of registers. This can be useful when dealing with sub-registers. + KILL = 5, /// EXTRACT_SUBREG - This instruction takes two operands: a register /// that has subregisters, and a subregister index. It returns the Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=83006&r1=83005&r2=83006&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Sep 28 15:32:26 2009 @@ -423,6 +423,7 @@ default: llvm_unreachable("Unknown or unset size field for instr!"); case TargetInstrInfo::IMPLICIT_DEF: + case TargetInstrInfo::KILL: case TargetInstrInfo::DBG_LABEL: case TargetInstrInfo::EH_LABEL: return 0; Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=83006&r1=83005&r2=83006&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Sep 28 15:32:26 2009 @@ -611,6 +611,7 @@ MCE.emitLabel(MI.getOperand(0).getImm()); break; case TargetInstrInfo::IMPLICIT_DEF: + case TargetInstrInfo::KILL: case ARM::DWARF_LOC: // Do nothing. break; Modified: llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp?rev=83006&r1=83005&r2=83006&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp Mon Sep 28 15:32:26 2009 @@ -125,6 +125,7 @@ case Alpha::PCLABEL: case Alpha::MEMLABEL: case TargetInstrInfo::IMPLICIT_DEF: + case TargetInstrInfo::KILL: break; //skip these } } Modified: llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=83006&r1=83005&r2=83006&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp Mon Sep 28 15:32:26 2009 @@ -142,6 +142,7 @@ MCE.emitLabel(MI.getOperand(0).getImm()); break; case TargetInstrInfo::IMPLICIT_DEF: + case TargetInstrInfo::KILL: break; // pseudo opcode, no side effects case PPC::MovePCtoLR: case PPC::MovePCtoLR8: Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp?rev=83006&r1=83005&r2=83006&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Mon Sep 28 15:32:26 2009 @@ -407,6 +407,8 @@ case TargetInstrInfo::IMPLICIT_DEF: printImplicitDef(MI); return; + case TargetInstrInfo::KILL: + return; case X86::MOVPC32r: { MCInst TmpInst; // This is a pseudo op for a two instruction sequence with a label, which Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=83006&r1=83005&r2=83006&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Mon Sep 28 15:32:26 2009 @@ -596,6 +596,7 @@ MCE.emitLabel(MI.getOperand(0).getImm()); break; case TargetInstrInfo::IMPLICIT_DEF: + case TargetInstrInfo::KILL: case X86::DWARF_LOC: case X86::FP_REG_KILL: break; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=83006&r1=83005&r2=83006&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Sep 28 15:32:26 2009 @@ -3061,6 +3061,7 @@ case TargetInstrInfo::EH_LABEL: break; case TargetInstrInfo::IMPLICIT_DEF: + case TargetInstrInfo::KILL: case X86::DWARF_LOC: case X86::FP_REG_KILL: break; Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=83006&r1=83005&r2=83006&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Mon Sep 28 15:32:26 2009 @@ -681,6 +681,8 @@ << " } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {\n" << " printImplicitDef(MI);\n" << " return;\n" + << " } else if (MI->getOpcode() == TargetInstrInfo::KILL) {\n" + << " return;\n" << " }\n\n"; O << "\n#endif\n"; Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=83006&r1=83005&r2=83006&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original) +++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Mon Sep 28 15:32:26 2009 @@ -29,7 +29,7 @@ R->getName() == "DBG_LABEL" || R->getName() == "EH_LABEL" || R->getName() == "GC_LABEL" || - R->getName() == "DECLARE" || + R->getName() == "KILL" || R->getName() == "EXTRACT_SUBREG" || R->getName() == "INSERT_SUBREG" || R->getName() == "IMPLICIT_DEF" || @@ -106,7 +106,7 @@ R->getName() == "DBG_LABEL" || R->getName() == "EH_LABEL" || R->getName() == "GC_LABEL" || - R->getName() == "DECLARE" || + R->getName() == "KILL" || R->getName() == "EXTRACT_SUBREG" || R->getName() == "INSERT_SUBREG" || R->getName() == "IMPLICIT_DEF" || @@ -144,7 +144,7 @@ InstName == "DBG_LABEL"|| InstName == "EH_LABEL"|| InstName == "GC_LABEL"|| - InstName == "DECLARE"|| + InstName == "KILL"|| InstName == "EXTRACT_SUBREG" || InstName == "INSERT_SUBREG" || InstName == "IMPLICIT_DEF" || Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=83006&r1=83005&r2=83006&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Sep 28 15:32:26 2009 @@ -308,9 +308,9 @@ if (I == Instructions.end()) throw "Could not find 'GC_LABEL' instruction!"; const CodeGenInstruction *GC_LABEL = &I->second; - I = getInstructions().find("DECLARE"); - if (I == Instructions.end()) throw "Could not find 'DECLARE' instruction!"; - const CodeGenInstruction *DECLARE = &I->second; + I = getInstructions().find("KILL"); + if (I == Instructions.end()) throw "Could not find 'KILL' instruction!"; + const CodeGenInstruction *KILL = &I->second; I = getInstructions().find("EXTRACT_SUBREG"); if (I == Instructions.end()) @@ -343,7 +343,7 @@ NumberedInstructions.push_back(DBG_LABEL); NumberedInstructions.push_back(EH_LABEL); NumberedInstructions.push_back(GC_LABEL); - NumberedInstructions.push_back(DECLARE); + NumberedInstructions.push_back(KILL); NumberedInstructions.push_back(EXTRACT_SUBREG); NumberedInstructions.push_back(INSERT_SUBREG); NumberedInstructions.push_back(IMPLICIT_DEF); @@ -355,7 +355,7 @@ &II->second != DBG_LABEL && &II->second != EH_LABEL && &II->second != GC_LABEL && - &II->second != DECLARE && + &II->second != KILL && &II->second != EXTRACT_SUBREG && &II->second != INSERT_SUBREG && &II->second != IMPLICIT_DEF && Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=83006&r1=83005&r2=83006&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Mon Sep 28 15:32:26 2009 @@ -339,7 +339,7 @@ R->getName() != "DBG_LABEL" && R->getName() != "EH_LABEL" && R->getName() != "GC_LABEL" && - R->getName() != "DECLARE" && + R->getName() != "KILL" && R->getName() != "EXTRACT_SUBREG" && R->getName() != "INSERT_SUBREG" && R->getName() != "IMPLICIT_DEF" && From stoklund at 2pi.dk Mon Sep 28 15:32:46 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 28 Sep 2009 20:32:46 -0000 Subject: [llvm-commits] [llvm] r83007 - in /llvm/trunk/lib/CodeGen: LowerSubregs.cpp PostRASchedulerList.cpp Message-ID: <200909282032.n8SKWk3Y009288@zion.cs.uiuc.edu> Author: stoklund Date: Mon Sep 28 15:32:46 2009 New Revision: 83007 URL: http://llvm.org/viewvc/llvm-project?rev=83007&view=rev Log: Use KILL instead of IMPLICIT_DEF in LowerSubregs pass. Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=83007&r1=83006&r2=83007&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original) +++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Mon Sep 28 15:32:46 2009 @@ -126,11 +126,10 @@ if (SrcReg == DstReg) { // No need to insert an identity copy instruction. if (MI->getOperand(1).isKill()) { - // We must make sure the super-register gets killed.Replace the - // instruction with IMPLICIT_DEF. - MI->setDesc(TII.get(TargetInstrInfo::IMPLICIT_DEF)); + // We must make sure the super-register gets killed. Replace the + // instruction with KILL. + MI->setDesc(TII.get(TargetInstrInfo::KILL)); MI->RemoveOperand(2); // SubIdx - MI->getOperand(1).setImplicit(true); DEBUG(errs() << "subreg: replace by: " << *MI); return true; } @@ -243,14 +242,14 @@ if (DstSubReg == InsReg) { // No need to insert an identity copy instruction. If the SrcReg was - // , we need to make sure it is alive by inserting an IMPLICIT_DEF + // , we need to make sure it is alive by inserting a KILL if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) { MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), - TII.get(TargetInstrInfo::IMPLICIT_DEF), DstReg); + TII.get(TargetInstrInfo::KILL), DstReg); if (MI->getOperand(2).isUndef()) - MIB.addReg(InsReg, RegState::Implicit | RegState::Undef); + MIB.addReg(InsReg, RegState::Undef); else - MIB.addReg(InsReg, RegState::ImplicitKill); + MIB.addReg(InsReg, RegState::Kill); } else { DEBUG(errs() << "subreg: eliminated!\n"); MBB->erase(MI); @@ -261,10 +260,10 @@ const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg); if (MI->getOperand(2).isUndef()) - // If the source register being inserted is undef, then this becomes an - // implicit_def. + // If the source register being inserted is undef, then this becomes a + // KILL. BuildMI(*MBB, MI, MI->getDebugLoc(), - TII.get(TargetInstrInfo::IMPLICIT_DEF), DstSubReg); + TII.get(TargetInstrInfo::KILL), DstSubReg); else TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); MachineBasicBlock::iterator CopyMI = MI; Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=83007&r1=83006&r2=83007&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Mon Sep 28 15:32:46 2009 @@ -655,11 +655,11 @@ I != E; --Count) { MachineInstr *MI = --I; - // After regalloc, IMPLICIT_DEF instructions aren't safe to treat as - // dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF + // After regalloc, KILL instructions aren't safe to treat as + // dependence-breaking. In the case of an INSERT_SUBREG, the KILL // is left behind appearing to clobber the super-register, while the // subregister needs to remain live. So we just ignore them. - if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) + if (MI->getOpcode() == TargetInstrInfo::KILL) continue; // Check if this instruction has a dependence on the critical path that From evan.cheng at apple.com Mon Sep 28 15:47:15 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 28 Sep 2009 20:47:15 -0000 Subject: [llvm-commits] [llvm] r83008 - /llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Message-ID: <200909282047.n8SKlGl6011270@zion.cs.uiuc.edu> Author: evancheng Date: Mon Sep 28 15:47:15 2009 New Revision: 83008 URL: http://llvm.org/viewvc/llvm-project?rev=83008&view=rev Log: Fix Thumb2 IT block pass bug. t2MOVi32imm may not be the start of a IT block. Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=83008&r1=83007&r2=83008&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Mon Sep 28 15:47:15 2009 @@ -35,6 +35,10 @@ } private: + MachineBasicBlock::iterator + SplitT2MOV32imm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + MachineInstr *MI, DebugLoc dl, + unsigned PredReg, ARMCC::CondCodes CC); bool InsertITBlocks(MachineBasicBlock &MBB); }; char Thumb2ITBlockPass::ID = 0; @@ -47,6 +51,34 @@ return llvm::getInstrPredicate(MI, PredReg); } +MachineBasicBlock::iterator +Thumb2ITBlockPass::SplitT2MOV32imm(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + MachineInstr *MI, + DebugLoc dl, unsigned PredReg, + ARMCC::CondCodes CC) { + // Splitting t2MOVi32imm into a pair of t2MOVi16 + t2MOVTi16 here. + // The only reason it was a single instruction was so it could be + // re-materialized. We want to split it before this and the thumb2 + // size reduction pass to make sure the IT mask is correct and expose + // width reduction opportunities. It doesn't make sense to do this in a + // separate pass so here it is. + unsigned DstReg = MI->getOperand(0).getReg(); + bool DstDead = MI->getOperand(0).isDead(); // Is this possible? + unsigned Imm = MI->getOperand(1).getImm(); + unsigned Lo16 = Imm & 0xffff; + unsigned Hi16 = (Imm >> 16) & 0xffff; + BuildMI(MBB, MBBI, dl, TII->get(ARM::t2MOVi16), DstReg) + .addImm(Lo16).addImm(CC).addReg(PredReg); + BuildMI(MBB, MBBI, dl, TII->get(ARM::t2MOVTi16)) + .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)) + .addReg(DstReg).addImm(Hi16).addImm(CC).addReg(PredReg); + --MBBI; + --MBBI; + MI->eraseFromParent(); + return MBBI; +} + bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) { bool Modified = false; @@ -57,26 +89,8 @@ unsigned PredReg = 0; ARMCC::CondCodes CC = getPredicate(MI, PredReg); - // Splitting t2MOVi32imm into a pair of t2MOVi16 + t2MOVTi16 here. - // The only reason it was a single instruction was so it could be - // re-materialized. We want to split it before this and the thumb2 - // size reduction pass to make sure the IT mask is correct and expose - // width reduction opportunities. It doesn't make sense to do this in a - // separate pass so here it is. if (MI->getOpcode() == ARM::t2MOVi32imm) { - unsigned DstReg = MI->getOperand(0).getReg(); - bool DstDead = MI->getOperand(0).isDead(); // Is this possible? - unsigned Imm = MI->getOperand(1).getImm(); - unsigned Lo16 = Imm & 0xffff; - unsigned Hi16 = (Imm >> 16) & 0xffff; - BuildMI(MBB, MBBI, dl, TII->get(ARM::t2MOVi16), DstReg) - .addImm(Lo16).addImm(CC).addReg(PredReg); - BuildMI(MBB, MBBI, dl, TII->get(ARM::t2MOVTi16)) - .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)) - .addReg(DstReg).addImm(Hi16).addImm(CC).addReg(PredReg); - --MBBI; - --MBBI; - MI->eraseFromParent(); + MBBI = SplitT2MOV32imm(MBB, MBBI, MI, dl, PredReg, CC); continue; } @@ -94,8 +108,15 @@ ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); unsigned Mask = 0, Pos = 3; while (MBBI != E && Pos) { - unsigned Dummy = 0; - ARMCC::CondCodes NCC = getPredicate(&*MBBI, Dummy); + MachineInstr *NMI = &*MBBI; + DebugLoc ndl = NMI->getDebugLoc(); + unsigned NPredReg = 0; + ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg); + if (NMI->getOpcode() == ARM::t2MOVi32imm) { + MBBI = SplitT2MOV32imm(MBB, MBBI, NMI, ndl, NPredReg, NCC); + continue; + } + if (NCC == OCC) { Mask |= (1 << Pos); } else if (NCC != CC) From gohman at apple.com Mon Sep 28 15:48:39 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 28 Sep 2009 20:48:39 -0000 Subject: [llvm-commits] [llvm] r83009 - /llvm/trunk/test/CodeGen/X86/sink-hoist.ll Message-ID: <200909282048.n8SKmd3n011441@zion.cs.uiuc.edu> Author: djg Date: Mon Sep 28 15:48:39 2009 New Revision: 83009 URL: http://llvm.org/viewvc/llvm-project?rev=83009&view=rev Log: Add a CHECK line to check the position of the second divsd. Modified: llvm/trunk/test/CodeGen/X86/sink-hoist.ll Modified: llvm/trunk/test/CodeGen/X86/sink-hoist.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sink-hoist.ll?rev=83009&r1=83008&r2=83009&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sink-hoist.ll (original) +++ llvm/trunk/test/CodeGen/X86/sink-hoist.ll Mon Sep 28 15:48:39 2009 @@ -9,6 +9,7 @@ ; CHECK-NEXT: divsd ; CHECK: testb $1, %dil ; CHECK-NEXT: jne +; CHECK: divsd define double @foo(double %x, double %y, i1 %c) nounwind { %a = fdiv double %x, 3.2 From dpatel at apple.com Mon Sep 28 15:56:00 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 28 Sep 2009 20:56:00 -0000 Subject: [llvm-commits] [llvm] r83010 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <200909282056.n8SKu0ca012458@zion.cs.uiuc.edu> Author: dpatel Date: Mon Sep 28 15:56:00 2009 New Revision: 83010 URL: http://llvm.org/viewvc/llvm-project?rev=83010&view=rev Log: Do not hardcode metadata names. Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=83010&r1=83009&r2=83010&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Sep 28 15:56:00 2009 @@ -1266,6 +1266,7 @@ TypePrinting TypePrinter; AssemblyAnnotationWriter *AnnotationWriter; std::vector NumberedTypes; + DenseMap MDNames; public: inline AssemblyWriter(formatted_raw_ostream &o, SlotTracker &Mac, @@ -1273,6 +1274,14 @@ AssemblyAnnotationWriter *AAW) : Out(o), Machine(Mac), TheModule(M), AnnotationWriter(AAW) { AddModuleTypesToPrinter(TypePrinter, NumberedTypes, M); + // FIXME: Provide MDPrinter + Metadata &TheMetadata = M->getContext().getMetadata(); + const StringMap *Names = TheMetadata.getHandlerNames(); + for (StringMapConstIterator I = Names->begin(), + E = Names->end(); I != E; ++I) { + const StringMapEntry &Entry = *I; + MDNames[I->second] = Entry.getKeyData(); + } } void write(const Module *M) { printModule(M); } @@ -1991,11 +2000,16 @@ Out << ", align " << cast(I).getAlignment(); } - // Print DebugInfo + // Print Metadata info Metadata &TheMetadata = I.getContext().getMetadata(); - unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); - if (const MDNode *Dbg = TheMetadata.getMD(MDDbgKind, &I)) - Out << ", dbg !" << Machine.getMetadataSlot(Dbg); + const Metadata::MDMapTy *MDMap = TheMetadata.getMDs(&I); + if (MDMap) + for (Metadata::MDMapTy::const_iterator MI = MDMap->begin(), + ME = MDMap->end(); MI != ME; ++MI) + if (const MDNode *MD = dyn_cast_or_null(MI->second)) + Out << ", " << MDNames[MI->first] + << " !" << Machine.getMetadataSlot(MD); + printInfoComment(I); } From devang.patel at gmail.com Mon Sep 28 15:56:36 2009 From: devang.patel at gmail.com (Devang Patel) Date: Mon, 28 Sep 2009 13:56:36 -0700 Subject: [llvm-commits] [llvm] r82075 - in /llvm/trunk: include/llvm/Metadata.h lib/VMCore/AsmWriter.cpp lib/VMCore/Metadata.cpp In-Reply-To: References: <200909162021.n8GKLHLD006575@zion.cs.uiuc.edu> Message-ID: <352a1fb20909281356j62981cfbobfd8b6e7e0c3ed16@mail.gmail.com> On Sun, Sep 27, 2009 at 3:38 PM, Chris Lattner wrote: > > On Sep 16, 2009, at 1:21 PM, Devang Patel wrote: > >> Author: dpatel >> Date: Wed Sep 16 15:21:17 2009 >> New Revision: 82075 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=82075&view=rev >> Log: >> Print debug info attached with an instruction. > > Again, debug info should not be special here. ?Instead of the name > 'dbg' being hard coded, this should just iterate over all metadata > attached to an instruction, and ask the "Metadata" class (which still > really needs to be renamed) what the spelling of the MDKind is. Done. - Devang From gohman at apple.com Mon Sep 28 16:01:48 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 28 Sep 2009 21:01:48 -0000 Subject: [llvm-commits] [llvm] r83011 - /llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Message-ID: <200909282101.n8SL1mxx013192@zion.cs.uiuc.edu> Author: djg Date: Mon Sep 28 16:01:47 2009 New Revision: 83011 URL: http://llvm.org/viewvc/llvm-project?rev=83011&view=rev Log: When extending the operands of an addrec, iterate through all the operands, rather than trying to partition them into a start and a step. This handles non-affine add recurrences correctly. Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=83011&r1=83010&r2=83011&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Mon Sep 28 16:01:47 2009 @@ -620,11 +620,11 @@ if (CanonicalIV && SE.getTypeSizeInBits(CanonicalIV->getType()) > SE.getTypeSizeInBits(Ty)) { - const SCEV *Start = SE.getAnyExtendExpr(S->getStart(), - CanonicalIV->getType()); - const SCEV *Step = SE.getAnyExtendExpr(S->getStepRecurrence(SE), - CanonicalIV->getType()); - Value *V = expand(SE.getAddRecExpr(Start, Step, S->getLoop())); + const SmallVectorImpl &Ops = S->getOperands(); + SmallVector NewOps(Ops.size()); + for (unsigned i = 0, e = Ops.size(); i != e; ++i) + NewOps[i] = SE.getAnyExtendExpr(Ops[i], CanonicalIV->getType()); + Value *V = expand(SE.getAddRecExpr(NewOps, S->getLoop())); BasicBlock *SaveInsertBB = Builder.GetInsertBlock(); BasicBlock::iterator SaveInsertPt = Builder.GetInsertPoint(); BasicBlock::iterator NewInsertPt = From gohman at apple.com Mon Sep 28 16:03:02 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 28 Sep 2009 21:03:02 -0000 Subject: [llvm-commits] [llvm] r83012 - /llvm/trunk/test/Transforms/IndVarSimplify/polynomial-expand.ll Message-ID: <200909282103.n8SL32Pi013361@zion.cs.uiuc.edu> Author: djg Date: Mon Sep 28 16:03:02 2009 New Revision: 83012 URL: http://llvm.org/viewvc/llvm-project?rev=83012&view=rev Log: Add a testcase for r83011. Added: llvm/trunk/test/Transforms/IndVarSimplify/polynomial-expand.ll Added: llvm/trunk/test/Transforms/IndVarSimplify/polynomial-expand.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/polynomial-expand.ll?rev=83012&view=auto ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/polynomial-expand.ll (added) +++ llvm/trunk/test/Transforms/IndVarSimplify/polynomial-expand.ll Mon Sep 28 16:03:02 2009 @@ -0,0 +1,38 @@ +; RUN: opt < %s -indvars -disable-output +; PR5073 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + +define void @ctpmv_(float* noalias nocapture %tmp4, i32 %tmp21) nounwind { +bb20: ; preds = %bb19 + br label %bb24 + +bb24: ; preds = %bb40, %bb23 + %tmp25 = phi i32 [ %tmp43, %bb40 ], [ %tmp21, %bb20 ] ; [#uses=4] + %tmp26 = phi i32 [ %tmp41, %bb40 ], [ undef, %bb20 ] ; [#uses=2] + %tmp27 = add nsw i32 %tmp26, -1 ; [#uses=1] + %tmp28 = add nsw i32 %tmp25, -1 ; [#uses=2] + %tmp29 = icmp sgt i32 %tmp28, 0 ; [#uses=1] + br i1 %tmp29, label %bb30, label %bb40 + +bb30: ; preds = %bb30, %bb24 + %tmp31 = phi i32 [ %tmp39, %bb30 ], [ %tmp28, %bb24 ] ; [#uses=2] + %tmp32 = phi i32 [ %tmp37, %bb30 ], [ %tmp27, %bb24 ] ; [#uses=2] + %tmp33 = sext i32 %tmp32 to i64 ; [#uses=1] + %tmp35 = getelementptr float* %tmp4, i64 %tmp33 ; <%0*> [#uses=1] + %tmp36 = load float* %tmp35, align 4 ; <%0> [#uses=0] + %tmp37 = add nsw i32 %tmp32, -1 ; [#uses=1] + %tmp39 = add nsw i32 %tmp31, -1 ; [#uses=1] + %tmp38 = icmp eq i32 %tmp31, 1 ; [#uses=1] + br i1 %tmp38, label %bb40, label %bb30 + +bb40: ; preds = %bb30, %bb24 + %tmp41 = sub i32 %tmp26, %tmp25 ; [#uses=1] + %tmp43 = add nsw i32 %tmp25, -1 ; [#uses=1] + %tmp42 = icmp eq i32 %tmp25, 1 ; [#uses=1] + br i1 %tmp42, label %bb46, label %bb24 + +bb46: ; preds = %bb40, %bb23, %bb19 + ret void +} From dpatel at apple.com Mon Sep 28 16:06:38 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 28 Sep 2009 21:06:38 -0000 Subject: [llvm-commits] [llvm] r83013 - /llvm/trunk/include/llvm/Metadata.h Message-ID: <200909282106.n8SL6cYd013842@zion.cs.uiuc.edu> Author: dpatel Date: Mon Sep 28 16:06:38 2009 New Revision: 83013 URL: http://llvm.org/viewvc/llvm-project?rev=83013&view=rev Log: Remove unnecessary include. Modified: llvm/trunk/include/llvm/Metadata.h Modified: llvm/trunk/include/llvm/Metadata.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Metadata.h?rev=83013&r1=83012&r2=83013&view=diff ============================================================================== --- llvm/trunk/include/llvm/Metadata.h (original) +++ llvm/trunk/include/llvm/Metadata.h Mon Sep 28 16:06:38 2009 @@ -23,7 +23,6 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/ilist_node.h" #include "llvm/Support/ErrorHandling.h" From jyasskin at google.com Mon Sep 28 16:14:40 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Mon, 28 Sep 2009 21:14:40 -0000 Subject: [llvm-commits] [llvm] r83015 - /llvm/trunk/docs/MakefileGuide.html Message-ID: <200909282114.n8SLEepP015075@zion.cs.uiuc.edu> Author: jyasskin Date: Mon Sep 28 16:14:38 2009 New Revision: 83015 URL: http://llvm.org/viewvc/llvm-project?rev=83015&view=rev Log: Forgot to update the documentation in r82906. s/DEBUG_RUNTIME/DEBUG_SYMBOLS/. Modified: llvm/trunk/docs/MakefileGuide.html Modified: llvm/trunk/docs/MakefileGuide.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/MakefileGuide.html?rev=83015&r1=83014&r2=83015&view=diff ============================================================================== --- llvm/trunk/docs/MakefileGuide.html (original) +++ llvm/trunk/docs/MakefileGuide.html Mon Sep 28 16:14:38 2009 @@ -626,7 +626,7 @@
If set to any value, causes a bitcode library (.bc) to be built.
CONFIG_FILES
Specifies a set of configuration files to be installed.
-
DEBUG_RUNTIME
+
DEBUG_SYMBOLS
If set to any value, causes the build to include debugging symbols even in optimized objects, libraries and executables. This alters the flags specified to the compilers and linkers. Debugging From dpatel at apple.com Mon Sep 28 16:14:56 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 28 Sep 2009 21:14:56 -0000 Subject: [llvm-commits] [llvm] r83016 - in /llvm/trunk: include/llvm/Metadata.h include/llvm/Support/IRBuilder.h lib/AsmParser/LLParser.cpp lib/AsmParser/LLParser.h lib/Bitcode/Reader/BitcodeReader.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/VMCore/Metadata.cpp Message-ID: <200909282114.n8SLEuc4015206@zion.cs.uiuc.edu> Author: dpatel Date: Mon Sep 28 16:14:55 2009 New Revision: 83016 URL: http://llvm.org/viewvc/llvm-project?rev=83016&view=rev Log: Do not use global typedef for MDKindID. Modified: llvm/trunk/include/llvm/Metadata.h llvm/trunk/include/llvm/Support/IRBuilder.h llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/AsmParser/LLParser.h llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/VMCore/Metadata.cpp Modified: llvm/trunk/include/llvm/Metadata.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Metadata.h?rev=83016&r1=83015&r2=83016&view=diff ============================================================================== --- llvm/trunk/include/llvm/Metadata.h (original) +++ llvm/trunk/include/llvm/Metadata.h Mon Sep 28 16:14:55 2009 @@ -307,13 +307,9 @@ /// Metadata - /// Metadata manages metadata used in a context. -/// MDKindID - This id identifies metadata kind the metadata store. Valid -/// ID values are 1 or higher. This ID is set by RegisterMDKind. -typedef unsigned MDKindID; - class Metadata { public: - typedef std::pair MDPairTy; + typedef std::pair MDPairTy; typedef SmallVector MDMapTy; typedef DenseMap MDStoreTy; friend class BitcodeReader; @@ -328,21 +324,21 @@ public: /// RegisterMDKind - Register a new metadata kind and return its ID. /// A metadata kind can be registered only once. - MDKindID RegisterMDKind(const char *Name); + unsigned RegisterMDKind(const char *Name); /// getMDKind - Return metadata kind. If the requested metadata kind /// is not registered then return 0. - MDKindID getMDKind(const char *Name); + unsigned getMDKind(const char *Name); /// getMD - Get the metadata of given kind attached with an Instruction. /// If the metadata is not found then return 0. - MDNode *getMD(MDKindID Kind, const Instruction *Inst); + MDNode *getMD(unsigned Kind, const Instruction *Inst); /// getMDs - Get the metadata attached with an Instruction. const MDMapTy *getMDs(const Instruction *Inst); /// setMD - Attach the metadata of given kind with an Instruction. - void setMD(MDKindID Kind, MDNode *Node, Instruction *Inst); + void setMD(unsigned Kind, MDNode *Node, Instruction *Inst); /// getHandlerNames - Get handler names. This is used by bitcode /// writer. Modified: llvm/trunk/include/llvm/Support/IRBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=83016&r1=83015&r2=83016&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) +++ llvm/trunk/include/llvm/Support/IRBuilder.h Mon Sep 28 16:14:55 2009 @@ -61,7 +61,7 @@ class IRBuilder : public Inserter { BasicBlock *BB; BasicBlock::iterator InsertPt; - MDKindID MDKind; + unsigned MDKind; MDNode *CurDbgLocation; LLVMContext &Context; T Folder; Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=83016&r1=83015&r2=83016&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Sep 28 16:14:55 2009 @@ -2657,7 +2657,7 @@ // Set metadata attached with this instruction. Metadata &TheMetadata = M->getContext().getMetadata(); - for (SmallVector, 2>::iterator + for (SmallVector, 2>::iterator MDI = MDsOnInst.begin(), MDE = MDsOnInst.end(); MDI != MDE; ++MDI) TheMetadata.setMD(MDI->first, MDI->second, Inst); MDsOnInst.clear(); Modified: llvm/trunk/lib/AsmParser/LLParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.h?rev=83016&r1=83015&r2=83016&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.h (original) +++ llvm/trunk/lib/AsmParser/LLParser.h Mon Sep 28 16:14:55 2009 @@ -48,7 +48,7 @@ /// MetadataCache - This map keeps track of parsed metadata constants. std::map MetadataCache; std::map > ForwardRefMDNodes; - SmallVector, 2> MDsOnInst; + SmallVector, 2> MDsOnInst; struct UpRefRecord { /// Loc - This is the location of the upref. LocTy Loc; Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=83016&r1=83015&r2=83016&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Mon Sep 28 16:14:55 2009 @@ -836,7 +836,7 @@ return Error("Invalid METADATA_KIND record"); SmallString<8> Name; Name.resize(RecordLength-1); - MDKindID Kind = Record[0]; + unsigned Kind = Record[0]; for (unsigned i = 1; i != RecordLength; ++i) Name[i-1] = Record[i]; Metadata &TheMetadata = Context.getMetadata(); @@ -1580,7 +1580,7 @@ return Error ("Invalid METADATA_ATTACHMENT reader!"); Instruction *Inst = InstructionList[Record[0]]; for (unsigned i = 1; i != RecordLength; i = i+2) { - MDKindID Kind = Record[i]; + unsigned Kind = Record[i]; Value *Node = MDValueList.getValueFwdRef(Record[i+1]); TheMetadata.setMD(Kind, cast(Node), Inst); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=83016&r1=83015&r2=83016&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Sep 28 16:14:55 2009 @@ -373,7 +373,7 @@ BasicBlock::iterator End) { SDL->setCurrentBasicBlock(BB); Metadata &TheMetadata = LLVMBB->getParent()->getContext().getMetadata(); - MDKindID MDDbgKind = TheMetadata.getMDKind("dbg"); + unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); // Lower all of the non-terminator instructions. If a call is emitted // as a tail call, cease emitting nodes for this block. @@ -656,7 +656,7 @@ ); Metadata &TheMetadata = Fn.getContext().getMetadata(); - MDKindID MDDbgKind = TheMetadata.getMDKind("dbg"); + unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); // Iterate over all basic blocks in the function. for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { Modified: llvm/trunk/lib/VMCore/Metadata.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=83016&r1=83015&r2=83016&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Metadata.cpp (original) +++ llvm/trunk/lib/VMCore/Metadata.cpp Mon Sep 28 16:14:55 2009 @@ -259,8 +259,8 @@ /// RegisterMDKind - Register a new metadata kind and return its ID. /// A metadata kind can be registered only once. -MDKindID Metadata::RegisterMDKind(const char *Name) { - MDKindID Count = MDHandlerNames.size(); +unsigned Metadata::RegisterMDKind(const char *Name) { + unsigned Count = MDHandlerNames.size(); StringMap::iterator I = MDHandlerNames.find(Name); assert(I == MDHandlerNames.end() && "Already registered MDKind!"); MDHandlerNames[Name] = Count + 1; @@ -269,7 +269,7 @@ /// getMDKind - Return metadata kind. If the requested metadata kind /// is not registered then return 0. -MDKindID Metadata::getMDKind(const char *Name) { +unsigned Metadata::getMDKind(const char *Name) { StringMap::iterator I = MDHandlerNames.find(Name); if (I == MDHandlerNames.end()) return 0; @@ -278,7 +278,7 @@ } /// setMD - Attach the metadata of given kind with an Instruction. -void Metadata::setMD(MDKindID MDKind, MDNode *Node, Instruction *Inst) { +void Metadata::setMD(unsigned MDKind, MDNode *Node, Instruction *Inst) { MDStoreTy::iterator I = MetadataStore.find(Inst); Inst->HasMetadata = true; if (I == MetadataStore.end()) { @@ -295,7 +295,7 @@ /// getMD - Get the metadata of given kind attached with an Instruction. /// If the metadata is not found then return 0. -MDNode *Metadata::getMD(MDKindID MDKind, const Instruction *Inst) { +MDNode *Metadata::getMD(unsigned MDKind, const Instruction *Inst) { MDNode *Node = NULL; MDStoreTy::iterator I = MetadataStore.find(Inst); if (I == MetadataStore.end()) From dpatel at apple.com Mon Sep 28 16:41:20 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 28 Sep 2009 21:41:20 -0000 Subject: [llvm-commits] [llvm] r83019 - in /llvm/trunk: include/llvm/LLVMContext.h include/llvm/Metadata.h include/llvm/Value.h lib/AsmParser/LLParser.cpp lib/Bitcode/Reader/BitcodeReader.cpp lib/Bitcode/Writer/BitcodeWriter.cpp lib/Bitcode/Writer/ValueEnumerator.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/VMCore/AsmWriter.cpp lib/VMCore/LLVMContext.cpp lib/VMCore/LLVMContextImpl.h lib/VMCore/Metadata.cpp Message-ID: <200909282141.n8SLfL3F018673@zion.cs.uiuc.edu> Author: dpatel Date: Mon Sep 28 16:41:20 2009 New Revision: 83019 URL: http://llvm.org/viewvc/llvm-project?rev=83019&view=rev Log: s/class Metadata/class MetadataContext/g Modified: llvm/trunk/include/llvm/LLVMContext.h llvm/trunk/include/llvm/Metadata.h llvm/trunk/include/llvm/Value.h llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/VMCore/AsmWriter.cpp llvm/trunk/lib/VMCore/LLVMContext.cpp llvm/trunk/lib/VMCore/LLVMContextImpl.h llvm/trunk/lib/VMCore/Metadata.cpp Modified: llvm/trunk/include/llvm/LLVMContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LLVMContext.h?rev=83019&r1=83018&r2=83019&view=diff ============================================================================== --- llvm/trunk/include/llvm/LLVMContext.h (original) +++ llvm/trunk/include/llvm/LLVMContext.h Mon Sep 28 16:41:20 2009 @@ -18,7 +18,7 @@ namespace llvm { class LLVMContextImpl; -class Metadata; +class MetadataContext; /// This is an important class for using LLVM in a threaded context. It /// (opaquely) owns and manages the core "global" data of LLVM's core /// infrastructure, including the type and constant uniquing tables. @@ -30,7 +30,7 @@ void operator=(LLVMContext&); public: LLVMContextImpl* pImpl; - Metadata &getMetadata(); + MetadataContext &getMetadata(); bool RemoveDeadMetadata(); LLVMContext(); ~LLVMContext(); Modified: llvm/trunk/include/llvm/Metadata.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Metadata.h?rev=83019&r1=83018&r2=83019&view=diff ============================================================================== --- llvm/trunk/include/llvm/Metadata.h (original) +++ llvm/trunk/include/llvm/Metadata.h Mon Sep 28 16:41:20 2009 @@ -304,10 +304,10 @@ }; //===----------------------------------------------------------------------===// -/// Metadata - -/// Metadata manages metadata used in a context. +/// MetadataContext - +/// MetadataContext manages metadata used in a context. -class Metadata { +class MetadataContext { public: typedef std::pair MDPairTy; typedef SmallVector MDMapTy; Modified: llvm/trunk/include/llvm/Value.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Value.h?rev=83019&r1=83018&r2=83019&view=diff ============================================================================== --- llvm/trunk/include/llvm/Value.h (original) +++ llvm/trunk/include/llvm/Value.h Mon Sep 28 16:41:20 2009 @@ -42,7 +42,7 @@ class AssemblyAnnotationWriter; class ValueHandleBase; class LLVMContext; -class Metadata; +class MetadataContext; //===----------------------------------------------------------------------===// // Value Class @@ -83,7 +83,7 @@ friend class ValueSymbolTable; // Allow ValueSymbolTable to directly mod Name. friend class SymbolTable; // Allow SymbolTable to directly poke Name. friend class ValueHandleBase; - friend class Metadata; + friend class MetadataContext; friend class AbstractTypeUser; ValueName *Name; Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=83019&r1=83018&r2=83019&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Sep 28 16:41:20 2009 @@ -1038,7 +1038,7 @@ MetadataBase *Node; if (ParseMDNode(Node)) return true; - Metadata &TheMetadata = M->getContext().getMetadata(); + MetadataContext &TheMetadata = M->getContext().getMetadata(); unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); if (!MDDbgKind) MDDbgKind = TheMetadata.RegisterMDKind("dbg"); @@ -2656,7 +2656,7 @@ ParseOptionalDbgInfo(); // Set metadata attached with this instruction. - Metadata &TheMetadata = M->getContext().getMetadata(); + MetadataContext &TheMetadata = M->getContext().getMetadata(); for (SmallVector, 2>::iterator MDI = MDsOnInst.begin(), MDE = MDsOnInst.end(); MDI != MDE; ++MDI) TheMetadata.setMD(MDI->first, MDI->second, Inst); Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=83019&r1=83018&r2=83019&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Mon Sep 28 16:41:20 2009 @@ -839,7 +839,7 @@ unsigned Kind = Record[0]; for (unsigned i = 1; i != RecordLength; ++i) Name[i-1] = Record[i]; - Metadata &TheMetadata = Context.getMetadata(); + MetadataContext &TheMetadata = Context.getMetadata(); assert(TheMetadata.MDHandlerNames.find(Name.str()) == TheMetadata.MDHandlerNames.end() && "Already registered MDKind!"); @@ -1556,7 +1556,7 @@ if (Stream.EnterSubBlock(bitc::METADATA_ATTACHMENT_ID)) return Error("Malformed block record"); - Metadata &TheMetadata = Context.getMetadata(); + MetadataContext &TheMetadata = Context.getMetadata(); SmallVector Record; while(1) { unsigned Code = Stream.ReadCode(); Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=83019&r1=83018&r2=83019&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Mon Sep 28 16:41:20 2009 @@ -562,15 +562,15 @@ // Write metadata attachments // METADATA_ATTACHMENT - [m x [value, [n x [id, mdnode]]] - Metadata &TheMetadata = F.getContext().getMetadata(); + MetadataContext &TheMetadata = F.getContext().getMetadata(); for (Function::const_iterator BB = F.begin(), E = F.end(); BB != E; ++BB) for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I) { - const Metadata::MDMapTy *P = TheMetadata.getMDs(I); + const MetadataContext::MDMapTy *P = TheMetadata.getMDs(I); if (!P) continue; bool RecordedInstruction = false; - for (Metadata::MDMapTy::const_iterator PI = P->begin(), PE = P->end(); - PI != PE; ++PI) { + for (MetadataContext::MDMapTy::const_iterator PI = P->begin(), + PE = P->end(); PI != PE; ++PI) { if (MDNode *ND = dyn_cast_or_null(PI->second)) { if (RecordedInstruction == false) { Record.push_back(VE.getInstructionID(I)); @@ -601,7 +601,7 @@ // Write metadata kinds // METADATA_KIND - [n x [id, name]] - Metadata &TheMetadata = M->getContext().getMetadata(); + MetadataContext &TheMetadata = M->getContext().getMetadata(); const StringMap *Kinds = TheMetadata.getHandlerNames(); for (StringMap::const_iterator I = Kinds->begin(), E = Kinds->end(); I != E; ++I) { Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp?rev=83019&r1=83018&r2=83019&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp Mon Sep 28 16:41:20 2009 @@ -86,7 +86,7 @@ I != E; ++I) EnumerateType(I->getType()); - Metadata &TheMetadata = F->getContext().getMetadata(); + MetadataContext &TheMetadata = F->getContext().getMetadata(); for (Function::const_iterator BB = F->begin(), E = F->end(); BB != E; ++BB) for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I!=E;++I){ for (User::const_op_iterator OI = I->op_begin(), E = I->op_end(); @@ -99,9 +99,9 @@ EnumerateAttributes(II->getAttributes()); // Enumerate metadata attached with this instruction. - const Metadata::MDMapTy *MDs = TheMetadata.getMDs(I); + const MetadataContext::MDMapTy *MDs = TheMetadata.getMDs(I); if (MDs) - for (Metadata::MDMapTy::const_iterator MI = MDs->begin(), + for (MetadataContext::MDMapTy::const_iterator MI = MDs->begin(), ME = MDs->end(); MI != ME; ++MI) if (MDNode *MDN = dyn_cast_or_null(MI->second)) EnumerateMetadata(MDN); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=83019&r1=83018&r2=83019&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Sep 28 16:41:20 2009 @@ -372,7 +372,7 @@ BasicBlock::iterator Begin, BasicBlock::iterator End) { SDL->setCurrentBasicBlock(BB); - Metadata &TheMetadata = LLVMBB->getParent()->getContext().getMetadata(); + MetadataContext &TheMetadata = LLVMBB->getParent()->getContext().getMetadata(); unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); // Lower all of the non-terminator instructions. If a call is emitted @@ -655,7 +655,7 @@ #endif ); - Metadata &TheMetadata = Fn.getContext().getMetadata(); + MetadataContext &TheMetadata = Fn.getContext().getMetadata(); unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); // Iterate over all basic blocks in the function. Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=83019&r1=83018&r2=83019&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Sep 28 16:41:20 2009 @@ -678,7 +678,7 @@ ST_DEBUG("Inserting Instructions:\n"); - Metadata &TheMetadata = TheFunction->getContext().getMetadata(); + MetadataContext &TheMetadata = TheFunction->getContext().getMetadata(); // Add all of the basic blocks and instructions with no names. for (Function::const_iterator BB = TheFunction->begin(), @@ -695,9 +695,9 @@ CreateMetadataSlot(N); // Process metadata attached with this instruction. - const Metadata::MDMapTy *MDs = TheMetadata.getMDs(I); + const MetadataContext::MDMapTy *MDs = TheMetadata.getMDs(I); if (MDs) - for (Metadata::MDMapTy::const_iterator MI = MDs->begin(), + for (MetadataContext::MDMapTy::const_iterator MI = MDs->begin(), ME = MDs->end(); MI != ME; ++MI) if (MDNode *MDN = dyn_cast_or_null(MI->second)) CreateMetadataSlot(MDN); @@ -1275,7 +1275,7 @@ : Out(o), Machine(Mac), TheModule(M), AnnotationWriter(AAW) { AddModuleTypesToPrinter(TypePrinter, NumberedTypes, M); // FIXME: Provide MDPrinter - Metadata &TheMetadata = M->getContext().getMetadata(); + MetadataContext &TheMetadata = M->getContext().getMetadata(); const StringMap *Names = TheMetadata.getHandlerNames(); for (StringMapConstIterator I = Names->begin(), E = Names->end(); I != E; ++I) { @@ -2001,10 +2001,10 @@ } // Print Metadata info - Metadata &TheMetadata = I.getContext().getMetadata(); - const Metadata::MDMapTy *MDMap = TheMetadata.getMDs(&I); + MetadataContext &TheMetadata = I.getContext().getMetadata(); + const MetadataContext::MDMapTy *MDMap = TheMetadata.getMDs(&I); if (MDMap) - for (Metadata::MDMapTy::const_iterator MI = MDMap->begin(), + for (MetadataContext::MDMapTy::const_iterator MI = MDMap->begin(), ME = MDMap->end(); MI != ME; ++MI) if (const MDNode *MD = dyn_cast_or_null(MI->second)) Out << ", " << MDNames[MI->first] Modified: llvm/trunk/lib/VMCore/LLVMContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContext.cpp?rev=83019&r1=83018&r2=83019&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/LLVMContext.cpp (original) +++ llvm/trunk/lib/VMCore/LLVMContext.cpp Mon Sep 28 16:41:20 2009 @@ -71,6 +71,6 @@ return Changed; } -Metadata &LLVMContext::getMetadata() { +MetadataContext &LLVMContext::getMetadata() { return pImpl->TheMetadata; } Modified: llvm/trunk/lib/VMCore/LLVMContextImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContextImpl.h?rev=83019&r1=83018&r2=83019&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/LLVMContextImpl.h (original) +++ llvm/trunk/lib/VMCore/LLVMContextImpl.h Mon Sep 28 16:41:20 2009 @@ -179,7 +179,7 @@ typedef DenseMap ValueHandlesTy; ValueHandlesTy ValueHandles; - Metadata TheMetadata; + MetadataContext TheMetadata; LLVMContextImpl(LLVMContext &C) : TheTrueVal(0), TheFalseVal(0), VoidTy(C, Type::VoidTyID), LabelTy(C, Type::LabelTyID), Modified: llvm/trunk/lib/VMCore/Metadata.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=83019&r1=83018&r2=83019&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Metadata.cpp (original) +++ llvm/trunk/lib/VMCore/Metadata.cpp Mon Sep 28 16:41:20 2009 @@ -259,7 +259,7 @@ /// RegisterMDKind - Register a new metadata kind and return its ID. /// A metadata kind can be registered only once. -unsigned Metadata::RegisterMDKind(const char *Name) { +unsigned MetadataContext::RegisterMDKind(const char *Name) { unsigned Count = MDHandlerNames.size(); StringMap::iterator I = MDHandlerNames.find(Name); assert(I == MDHandlerNames.end() && "Already registered MDKind!"); @@ -269,7 +269,7 @@ /// getMDKind - Return metadata kind. If the requested metadata kind /// is not registered then return 0. -unsigned Metadata::getMDKind(const char *Name) { +unsigned MetadataContext::getMDKind(const char *Name) { StringMap::iterator I = MDHandlerNames.find(Name); if (I == MDHandlerNames.end()) return 0; @@ -278,7 +278,7 @@ } /// setMD - Attach the metadata of given kind with an Instruction. -void Metadata::setMD(unsigned MDKind, MDNode *Node, Instruction *Inst) { +void MetadataContext::setMD(unsigned MDKind, MDNode *Node, Instruction *Inst) { MDStoreTy::iterator I = MetadataStore.find(Inst); Inst->HasMetadata = true; if (I == MetadataStore.end()) { @@ -295,7 +295,7 @@ /// getMD - Get the metadata of given kind attached with an Instruction. /// If the metadata is not found then return 0. -MDNode *Metadata::getMD(unsigned MDKind, const Instruction *Inst) { +MDNode *MetadataContext::getMD(unsigned MDKind, const Instruction *Inst) { MDNode *Node = NULL; MDStoreTy::iterator I = MetadataStore.find(Inst); if (I == MetadataStore.end()) @@ -309,7 +309,7 @@ } /// getMDs - Get the metadata attached with an Instruction. -const Metadata::MDMapTy *Metadata::getMDs(const Instruction *Inst) { +const MetadataContext::MDMapTy *MetadataContext::getMDs(const Instruction *Inst) { MDStoreTy::iterator I = MetadataStore.find(Inst); if (I == MetadataStore.end()) return NULL; @@ -319,13 +319,13 @@ /// getHandlerNames - Get handler names. This is used by bitcode /// writer. -const StringMap *Metadata::getHandlerNames() { +const StringMap *MetadataContext::getHandlerNames() { return &MDHandlerNames; } /// ValueIsDeleted - This handler is used to update metadata store /// when a value is deleted. -void Metadata::ValueIsDeleted(const Instruction *Inst) { +void MetadataContext::ValueIsDeleted(const Instruction *Inst) { // Find Metadata handles for this instruction. MDStoreTy::iterator I = MetadataStore.find(Inst); if (I == MetadataStore.end()) @@ -341,7 +341,7 @@ /// ValueIsCloned - This handler is used to update metadata store /// when In1 is cloned to create In2. -void Metadata::ValueIsCloned(const Instruction *In1, Instruction *In2) { +void MetadataContext::ValueIsCloned(const Instruction *In1, Instruction *In2) { // Find Metadata handles for In1. MDStoreTy::iterator I = MetadataStore.find(In1); if (I == MetadataStore.end()) From evan.cheng at apple.com Mon Sep 28 16:45:31 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 28 Sep 2009 14:45:31 -0700 Subject: [llvm-commits] [llvm] r83006 - in /llvm/trunk: include/llvm/Target/Target.td include/llvm/Target/TargetInstrInfo.h lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/Alpha/AlphaCodeEmitter.cpp lib/Target/PowerPC/PPCCodeEmitter.cpp lib/Target/X86/AsmPrinter/X86MCInstLower.cpp lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86InstrInfo.cpp utils/TableGen/AsmWriterEmitter.cpp utils/TableGen/CodeEmitterGen.cpp utils/TableGen/CodeGenTarget.cpp utils/TableGen/InstrInfoEmitter.cpp In-Reply-To: <200909282032.n8SKWSQ8009231@zion.cs.uiuc.edu> References: <200909282032.n8SKWSQ8009231@zion.cs.uiuc.edu> Message-ID: <9343E384-9C38-4A28-8FDD-D016182FD43F@apple.com> Thanks! Evan On Sep 28, 2009, at 1:32 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Mon Sep 28 15:32:26 2009 > New Revision: 83006 > > URL: http://llvm.org/viewvc/llvm-project?rev=83006&view=rev > Log: > Introduce the TargetInstrInfo::KILL machine instruction and get rid > of the > unused DECLARE instruction. > > KILL is not yet used anywhere, it will replace > TargetInstrInfo::IMPLICIT_DEF > in the places where IMPLICIT_DEF is just used to alter liveness of > physical > registers. > > Modified: > llvm/trunk/include/llvm/Target/Target.td > llvm/trunk/include/llvm/Target/TargetInstrInfo.h > llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp > llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp > llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp > llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp > llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp > llvm/trunk/lib/Target/X86/X86InstrInfo.cpp > llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp > llvm/trunk/utils/TableGen/CodeEmitterGen.cpp > llvm/trunk/utils/TableGen/CodeGenTarget.cpp > llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp > > Modified: llvm/trunk/include/llvm/Target/Target.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=83006&r1=83005&r2=83006&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Target/Target.td (original) > +++ llvm/trunk/include/llvm/Target/Target.td Mon Sep 28 15:32:26 2009 > @@ -426,12 +426,12 @@ > let Namespace = "TargetInstrInfo"; > let hasCtrlDep = 1; > } > -def DECLARE : Instruction { > +def KILL : Instruction { > let OutOperandList = (ops); > let InOperandList = (ops variable_ops); > let AsmString = ""; > let Namespace = "TargetInstrInfo"; > - let hasCtrlDep = 1; > + let neverHasSideEffects = 1; > } > def EXTRACT_SUBREG : Instruction { > let OutOperandList = (ops unknown:$dst); > > Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=83006&r1=83005&r2=83006&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) > +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Sep 28 > 15:32:26 2009 > @@ -51,7 +51,10 @@ > DBG_LABEL = 2, > EH_LABEL = 3, > GC_LABEL = 4, > - // FIXME: DECLARE is removed. Readjust enum values ? > + > + /// KILL - This instruction is a noop that is used only to > adjust the liveness > + /// of registers. This can be useful when dealing with sub- > registers. > + KILL = 5, > > /// EXTRACT_SUBREG - This instruction takes two operands: a > register > /// that has subregisters, and a subregister index. It returns the > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=83006&r1=83005&r2=83006&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Sep 28 > 15:32:26 2009 > @@ -423,6 +423,7 @@ > default: > llvm_unreachable("Unknown or unset size field for instr!"); > case TargetInstrInfo::IMPLICIT_DEF: > + case TargetInstrInfo::KILL: > case TargetInstrInfo::DBG_LABEL: > case TargetInstrInfo::EH_LABEL: > return 0; > > Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=83006&r1=83005&r2=83006&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Sep 28 15:32:26 > 2009 > @@ -611,6 +611,7 @@ > MCE.emitLabel(MI.getOperand(0).getImm()); > break; > case TargetInstrInfo::IMPLICIT_DEF: > + case TargetInstrInfo::KILL: > case ARM::DWARF_LOC: > // Do nothing. > break; > > Modified: llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp?rev=83006&r1=83005&r2=83006&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp Mon Sep 28 > 15:32:26 2009 > @@ -125,6 +125,7 @@ > case Alpha::PCLABEL: > case Alpha::MEMLABEL: > case TargetInstrInfo::IMPLICIT_DEF: > + case TargetInstrInfo::KILL: > break; //skip these > } > } > > Modified: llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=83006&r1=83005&r2=83006&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp Mon Sep 28 > 15:32:26 2009 > @@ -142,6 +142,7 @@ > MCE.emitLabel(MI.getOperand(0).getImm()); > break; > case TargetInstrInfo::IMPLICIT_DEF: > + case TargetInstrInfo::KILL: > break; // pseudo opcode, no side effects > case PPC::MovePCtoLR: > case PPC::MovePCtoLR8: > > Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp?rev=83006&r1=83005&r2=83006&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp (original) > +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Mon Sep > 28 15:32:26 2009 > @@ -407,6 +407,8 @@ > case TargetInstrInfo::IMPLICIT_DEF: > printImplicitDef(MI); > return; > + case TargetInstrInfo::KILL: > + return; > case X86::MOVPC32r: { > MCInst TmpInst; > // This is a pseudo op for a two instruction sequence with a > label, which > > Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=83006&r1=83005&r2=83006&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Mon Sep 28 15:32:26 > 2009 > @@ -596,6 +596,7 @@ > MCE.emitLabel(MI.getOperand(0).getImm()); > break; > case TargetInstrInfo::IMPLICIT_DEF: > + case TargetInstrInfo::KILL: > case X86::DWARF_LOC: > case X86::FP_REG_KILL: > break; > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=83006&r1=83005&r2=83006&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Sep 28 15:32:26 > 2009 > @@ -3061,6 +3061,7 @@ > case TargetInstrInfo::EH_LABEL: > break; > case TargetInstrInfo::IMPLICIT_DEF: > + case TargetInstrInfo::KILL: > case X86::DWARF_LOC: > case X86::FP_REG_KILL: > break; > > Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=83006&r1=83005&r2=83006&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Mon Sep 28 > 15:32:26 2009 > @@ -681,6 +681,8 @@ > << " } else if (MI->getOpcode() == > TargetInstrInfo::IMPLICIT_DEF) {\n" > << " printImplicitDef(MI);\n" > << " return;\n" > + << " } else if (MI->getOpcode() == TargetInstrInfo::KILL) {\n" > + << " return;\n" > << " }\n\n"; > > O << "\n#endif\n"; > > Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=83006&r1=83005&r2=83006&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original) > +++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Mon Sep 28 15:32:26 > 2009 > @@ -29,7 +29,7 @@ > R->getName() == "DBG_LABEL" || > R->getName() == "EH_LABEL" || > R->getName() == "GC_LABEL" || > - R->getName() == "DECLARE" || > + R->getName() == "KILL" || > R->getName() == "EXTRACT_SUBREG" || > R->getName() == "INSERT_SUBREG" || > R->getName() == "IMPLICIT_DEF" || > @@ -106,7 +106,7 @@ > R->getName() == "DBG_LABEL" || > R->getName() == "EH_LABEL" || > R->getName() == "GC_LABEL" || > - R->getName() == "DECLARE" || > + R->getName() == "KILL" || > R->getName() == "EXTRACT_SUBREG" || > R->getName() == "INSERT_SUBREG" || > R->getName() == "IMPLICIT_DEF" || > @@ -144,7 +144,7 @@ > InstName == "DBG_LABEL"|| > InstName == "EH_LABEL"|| > InstName == "GC_LABEL"|| > - InstName == "DECLARE"|| > + InstName == "KILL"|| > InstName == "EXTRACT_SUBREG" || > InstName == "INSERT_SUBREG" || > InstName == "IMPLICIT_DEF" || > > Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=83006&r1=83005&r2=83006&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) > +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Sep 28 15:32:26 > 2009 > @@ -308,9 +308,9 @@ > if (I == Instructions.end()) throw "Could not find 'GC_LABEL' > instruction!"; > const CodeGenInstruction *GC_LABEL = &I->second; > > - I = getInstructions().find("DECLARE"); > - if (I == Instructions.end()) throw "Could not find 'DECLARE' > instruction!"; > - const CodeGenInstruction *DECLARE = &I->second; > + I = getInstructions().find("KILL"); > + if (I == Instructions.end()) throw "Could not find 'KILL' > instruction!"; > + const CodeGenInstruction *KILL = &I->second; > > I = getInstructions().find("EXTRACT_SUBREG"); > if (I == Instructions.end()) > @@ -343,7 +343,7 @@ > NumberedInstructions.push_back(DBG_LABEL); > NumberedInstructions.push_back(EH_LABEL); > NumberedInstructions.push_back(GC_LABEL); > - NumberedInstructions.push_back(DECLARE); > + NumberedInstructions.push_back(KILL); > NumberedInstructions.push_back(EXTRACT_SUBREG); > NumberedInstructions.push_back(INSERT_SUBREG); > NumberedInstructions.push_back(IMPLICIT_DEF); > @@ -355,7 +355,7 @@ > &II->second != DBG_LABEL && > &II->second != EH_LABEL && > &II->second != GC_LABEL && > - &II->second != DECLARE && > + &II->second != KILL && > &II->second != EXTRACT_SUBREG && > &II->second != INSERT_SUBREG && > &II->second != IMPLICIT_DEF && > > Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=83006&r1=83005&r2=83006&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Mon Sep 28 > 15:32:26 2009 > @@ -339,7 +339,7 @@ > R->getName() != "DBG_LABEL" && > R->getName() != "EH_LABEL" && > R->getName() != "GC_LABEL" && > - R->getName() != "DECLARE" && > + R->getName() != "KILL" && > R->getName() != "EXTRACT_SUBREG" && > R->getName() != "INSERT_SUBREG" && > R->getName() != "IMPLICIT_DEF" && > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Mon Sep 28 16:51:41 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 28 Sep 2009 21:51:41 -0000 Subject: [llvm-commits] [llvm] r83021 - in /llvm/trunk: include/llvm-c/Core.h lib/VMCore/Core.cpp Message-ID: <200909282151.n8SLpfc3019960@zion.cs.uiuc.edu> Author: djg Date: Mon Sep 28 16:51:41 2009 New Revision: 83021 URL: http://llvm.org/viewvc/llvm-project?rev=83021&view=rev Log: Add C API calls for building FNeg operations. Patch by KS Sreeram! Modified: llvm/trunk/include/llvm-c/Core.h llvm/trunk/lib/VMCore/Core.cpp Modified: llvm/trunk/include/llvm-c/Core.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=83021&r1=83020&r2=83021&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Core.h (original) +++ llvm/trunk/include/llvm-c/Core.h Mon Sep 28 16:51:41 2009 @@ -736,6 +736,7 @@ LLVMValueRef LLVMBuildXor(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name); LLVMValueRef LLVMBuildNeg(LLVMBuilderRef, LLVMValueRef V, const char *Name); +LLVMValueRef LLVMBuildFNeg(LLVMBuilderRef, LLVMValueRef V, const char *Name); LLVMValueRef LLVMBuildNot(LLVMBuilderRef, LLVMValueRef V, const char *Name); /* Memory */ Modified: llvm/trunk/lib/VMCore/Core.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=83021&r1=83020&r2=83021&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Core.cpp (original) +++ llvm/trunk/lib/VMCore/Core.cpp Mon Sep 28 16:51:41 2009 @@ -1628,6 +1628,10 @@ return wrap(unwrap(B)->CreateNeg(unwrap(V), Name)); } +LLVMValueRef LLVMBuildFNeg(LLVMBuilderRef B, LLVMValueRef V, const char *Name) { + return wrap(unwrap(B)->CreateFNeg(unwrap(V), Name)); +} + LLVMValueRef LLVMBuildNot(LLVMBuilderRef B, LLVMValueRef V, const char *Name) { return wrap(unwrap(B)->CreateNot(unwrap(V), Name)); } From grosbach at apple.com Mon Sep 28 17:08:06 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 28 Sep 2009 22:08:06 -0000 Subject: [llvm-commits] [llvm] r83023 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <200909282208.n8SM87uk022072@zion.cs.uiuc.edu> Author: grosbach Date: Mon Sep 28 17:08:06 2009 New Revision: 83023 URL: http://llvm.org/viewvc/llvm-project?rev=83023&view=rev Log: Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack slot for the register scavenger when compiling Thumb1 functions. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=83023&r1=83022&r2=83023&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Sep 28 17:08:06 2009 @@ -536,7 +536,8 @@ } } - if (CSRegClasses[i] == ARM::GPRRegisterClass) { + if (CSRegClasses[i] == ARM::GPRRegisterClass || + CSRegClasses[i] == ARM::tGPRRegisterClass) { if (Spilled) { NumGPRSpills++; @@ -667,7 +668,8 @@ NumExtras--; } } - while (NumExtras && !UnspilledCS2GPRs.empty()) { + while (NumExtras && !UnspilledCS2GPRs.empty() && + !AFI->isThumb1OnlyFunction()) { unsigned Reg = UnspilledCS2GPRs.back(); UnspilledCS2GPRs.pop_back(); if (!isReservedReg(MF, Reg)) { From stuart at apple.com Mon Sep 28 17:17:54 2009 From: stuart at apple.com (Stuart Hastings) Date: Mon, 28 Sep 2009 22:17:54 -0000 Subject: [llvm-commits] [llvm] r83024 - /llvm/trunk/utils/buildit/build_llvm Message-ID: <200909282217.n8SMHs4p023277@zion.cs.uiuc.edu> Author: stuart Date: Mon Sep 28 17:17:53 2009 New Revision: 83024 URL: http://llvm.org/viewvc/llvm-project?rev=83024&view=rev Log: For B&I-style builds, tweak build_llvm script to prefer LLVM-G++ if available. Override by setting CC and CXX in the environment. Modified: llvm/trunk/utils/buildit/build_llvm Modified: llvm/trunk/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=83024&r1=83023&r2=83024&view=diff ============================================================================== --- llvm/trunk/utils/buildit/build_llvm (original) +++ llvm/trunk/utils/buildit/build_llvm Mon Sep 28 17:17:53 2009 @@ -56,9 +56,6 @@ DARWIN_VERS=`uname -r | sed 's/\..*//'` echo DARWIN_VERS = $DARWIN_VERS -# If the user has CC set in their environment unset it now -unset CC - if [ "x$RC_ProjectName" = "xllvmCore_Embedded" ]; then DT_HOME=$DEST_DIR/Developer/Platforms/iPhoneOS.platform/Developer/usr DEST_ROOT="/Developer/Platforms/iPhoneOS.platform/Developer$DEST_ROOT" @@ -90,6 +87,15 @@ mkdir -p $DIR/obj-llvm || exit 1 cd $DIR/obj-llvm || exit 1 +# If the user has set CC or CXX, respect their wishes. If not, +# compile with LLVM-GCC/LLVM-G++ if available; if LLVM is not +# available, fall back to usual GCC/G++ default. +XTMPCC=$(which llvm-gcc) +if [ x$CC = x -a x$XTMPCC != x ] ; then export CC=$XTMPCC ; fi +XTMPCC=$(which llvm-g++) +if [ x$CXX = x -a x$XTMPCC != x ] ; then export CXX=$XTMPCC ; fi +unset XTMPCC + if [ \! -f Makefile.config ]; then $SRC_DIR/configure --prefix=$DT_HOME/local \ --enable-targets=arm,x86,powerpc,cbe \ @@ -152,7 +158,7 @@ CXXFLAGS="-DLLVM_VERSION_INFO='\" Apple Build #$LLVM_VERSION\"'" \ VERBOSE=1 -if ! test $? == 0 ; then +if [ $? != 0 ] ; then echo "error: LLVM 'make' failed!" exit 1 fi From stuart at apple.com Mon Sep 28 18:42:39 2009 From: stuart at apple.com (Stuart Hastings) Date: Mon, 28 Sep 2009 23:42:39 -0000 Subject: [llvm-commits] [llvm] r83028 - /llvm/trunk/utils/buildit/build_llvm Message-ID: <200909282342.n8SNgdgi010636@zion.cs.uiuc.edu> Author: stuart Date: Mon Sep 28 18:42:38 2009 New Revision: 83028 URL: http://llvm.org/viewvc/llvm-project?rev=83028&view=rev Log: B&I's buildit forces a PATH that omits /Developer. Temporarily add /Developer/usr/bin to the PATH when looking for llvm-gcc. Modified: llvm/trunk/utils/buildit/build_llvm Modified: llvm/trunk/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=83028&r1=83027&r2=83028&view=diff ============================================================================== --- llvm/trunk/utils/buildit/build_llvm (original) +++ llvm/trunk/utils/buildit/build_llvm Mon Sep 28 18:42:38 2009 @@ -90,11 +90,13 @@ # If the user has set CC or CXX, respect their wishes. If not, # compile with LLVM-GCC/LLVM-G++ if available; if LLVM is not # available, fall back to usual GCC/G++ default. +savedPATH=$PATH ; PATH="$PATH:/Developer/usr/bin" XTMPCC=$(which llvm-gcc) if [ x$CC = x -a x$XTMPCC != x ] ; then export CC=$XTMPCC ; fi XTMPCC=$(which llvm-g++) if [ x$CXX = x -a x$XTMPCC != x ] ; then export CXX=$XTMPCC ; fi -unset XTMPCC +PATH=$savedPATH +unset XTMPCC savedPATH if [ \! -f Makefile.config ]; then $SRC_DIR/configure --prefix=$DT_HOME/local \ From stuart at apple.com Mon Sep 28 18:45:35 2009 From: stuart at apple.com (Stuart Hastings) Date: Mon, 28 Sep 2009 23:45:35 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r83029 - /llvm-gcc-4.2/trunk/build_gcc Message-ID: <200909282345.n8SNjZhn011958@zion.cs.uiuc.edu> Author: stuart Date: Mon Sep 28 18:45:35 2009 New Revision: 83029 URL: http://llvm.org/viewvc/llvm-project?rev=83029&view=rev Log: For Apple-style (B&I) builds, prefer LLVM-GCC if available, fall back to GCC if not. Respect CC and CXX if set in the environment. Temporarily adds /Developer/usr/bin to the PATH for checking. Modified: llvm-gcc-4.2/trunk/build_gcc Modified: llvm-gcc-4.2/trunk/build_gcc URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/build_gcc?rev=83029&r1=83028&r2=83029&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/build_gcc (original) +++ llvm-gcc-4.2/trunk/build_gcc Mon Sep 28 18:45:35 2009 @@ -263,6 +263,17 @@ fi # LLVM LOCAL end +# If the user has set CC or CXX, respect their wishes. If not, +# compile with LLVM-GCC/LLVM-G++ if available; if LLVM is not +# available, fall back to usual GCC/G++ default. +savedPATH=$PATH ; PATH="$PATH:/Developer/usr/bin" +XTMPCC=$(which llvm-gcc) +if [ x$CC = x -a x$XTMPCC != x ] ; then export CC=$XTMPCC forcedCC=1 ; fi +XTMPCC=$(which llvm-g++) +if [ x$CXX = x -a x$XTMPCC != x ] ; then export CXX=$XTMPCC forcedCXX=1 ; fi +PATH=$savedPATH +unset XTMPCC savedPATH + # Build the native GCC. Do this even if the user didn't ask for it # because it'll be needed for the bootstrap. mkdir -p $DIR/obj-$BUILD-$BUILD $DIR/dst-$BUILD-$BUILD || exit 1 @@ -272,6 +283,7 @@ --host=$BUILD-apple-darwin$DARWIN_VERS \ --target=$BUILD-apple-darwin$DARWIN_VERS || exit 1 fi + # Unset RC_DEBUG_OPTIONS because it causes the bootstrap to fail. # Also keep unset for cross compilers so that the cross built libraries are # comparable to the native built libraries. @@ -281,6 +293,11 @@ make $MAKEFLAGS DESTDIR=$DIR/dst-$BUILD-$BUILD install-gcc install-target \ CFLAGS="$CFLAGS" CXXFLAGS="$CFLAGS" || exit 1 +# Now that we've built a native compiler, un-kludge these so that +# subsequent cross-hosted compilers can be found normally. +if [ x$forcedCC != x ] ; then unset CC forcedCC ; fi +if [ x$forcedCXX != x ] ; then unset CXX forcedCXX ; fi + # Add the compiler we just built to the path, giving it appropriate names. # LLVM LOCAL begin Support for non /usr $DEST_ROOT D=$DIR/dst-$BUILD-$BUILD$DEST_ROOT/bin From dpatel at apple.com Mon Sep 28 19:01:15 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 29 Sep 2009 00:01:15 -0000 Subject: [llvm-commits] [llvm] r83033 - in /llvm/trunk: include/llvm/Metadata.h lib/AsmParser/LLLexer.cpp lib/AsmParser/LLParser.cpp lib/AsmParser/LLParser.h lib/AsmParser/LLToken.h lib/VMCore/AsmWriter.cpp lib/VMCore/Metadata.cpp test/Feature/md_on_instruction.ll test/Feature/md_on_instruction2.ll Message-ID: <200909290001.n8T01Fv3016515@zion.cs.uiuc.edu> Author: dpatel Date: Mon Sep 28 19:01:14 2009 New Revision: 83033 URL: http://llvm.org/viewvc/llvm-project?rev=83033&view=rev Log: Parse custom metadata attached with an instruction. Modified: llvm/trunk/include/llvm/Metadata.h llvm/trunk/lib/AsmParser/LLLexer.cpp llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/AsmParser/LLParser.h llvm/trunk/lib/AsmParser/LLToken.h llvm/trunk/lib/VMCore/AsmWriter.cpp llvm/trunk/lib/VMCore/Metadata.cpp llvm/trunk/test/Feature/md_on_instruction.ll llvm/trunk/test/Feature/md_on_instruction2.ll Modified: llvm/trunk/include/llvm/Metadata.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Metadata.h?rev=83033&r1=83032&r2=83033&view=diff ============================================================================== --- llvm/trunk/include/llvm/Metadata.h (original) +++ llvm/trunk/include/llvm/Metadata.h Mon Sep 28 19:01:14 2009 @@ -305,8 +305,10 @@ //===----------------------------------------------------------------------===// /// MetadataContext - -/// MetadataContext manages metadata used in a context. - +/// MetadataContext handles uniquing and assignment of IDs for custom metadata +/// types. Custom metadata handler names do not contain spaces. And the name +/// must start with an alphabet. The regular expression used to check name +/// is [a-zA-Z$._][a-zA-Z$._0-9]* class MetadataContext { public: typedef std::pair MDPairTy; @@ -330,6 +332,9 @@ /// is not registered then return 0. unsigned getMDKind(const char *Name); + /// validName - Return true if Name is a valid custom metadata handler name. + bool validName(const char *Name); + /// getMD - Get the metadata of given kind attached with an Instruction. /// If the metadata is not found then return 0. MDNode *getMD(unsigned Kind, const Instruction *Inst); Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=83033&r1=83032&r2=83033&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLLexer.cpp (original) +++ llvm/trunk/lib/AsmParser/LLLexer.cpp Mon Sep 28 19:01:14 2009 @@ -434,7 +434,7 @@ ++CurPtr; StrVal.assign(TokStart+1, CurPtr); // Skip ! - return lltok::NamedMD; + return lltok::NamedOrCustomMD; } return lltok::Metadata; } @@ -530,7 +530,6 @@ KEYWORD(asm); KEYWORD(sideeffect); KEYWORD(gc); - KEYWORD(dbg); KEYWORD(ccc); KEYWORD(fastcc); Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=83033&r1=83032&r2=83033&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Sep 28 19:01:14 2009 @@ -125,7 +125,7 @@ case lltok::GlobalID: if (ParseUnnamedGlobal()) return true; break; case lltok::GlobalVar: if (ParseNamedGlobal()) return true; break; case lltok::Metadata: if (ParseStandaloneMetadata()) return true; break; - case lltok::NamedMD: if (ParseNamedMetadata()) return true; break; + case lltok::NamedOrCustomMD: if (ParseNamedMetadata()) return true; break; // The Global variable production with no name can have many different // optional leading prefixes, the production is: @@ -461,7 +461,7 @@ ///ParseNamedMetadata: /// !foo = !{ !1, !2 } bool LLParser::ParseNamedMetadata() { - assert(Lex.getKind() == lltok::NamedMD); + assert(Lex.getKind() == lltok::NamedOrCustomMD); Lex.Lex(); std::string Name = Lex.getStrVal(); @@ -1025,24 +1025,30 @@ return false; } -/// ParseOptionalDbgInfo +/// ParseOptionalCustomMetadata /// ::= /* empty */ -/// ::= 'dbg' !42 -bool LLParser::ParseOptionalDbgInfo() { +/// ::= !dbg !42 +bool LLParser::ParseOptionalCustomMetadata() { - if (!EatIfPresent(lltok::kw_dbg)) + std::string Name; + if (Lex.getKind() == lltok::NamedOrCustomMD) { + Name = Lex.getStrVal(); + Lex.Lex(); + } else return false; + if (Lex.getKind() != lltok::Metadata) return TokError("Expected '!' here"); Lex.Lex(); + MetadataBase *Node; if (ParseMDNode(Node)) return true; MetadataContext &TheMetadata = M->getContext().getMetadata(); - unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); - if (!MDDbgKind) - MDDbgKind = TheMetadata.RegisterMDKind("dbg"); - MDsOnInst.push_back(std::make_pair(MDDbgKind, cast(Node))); + unsigned MDK = TheMetadata.getMDKind(Name.c_str()); + if (!MDK) + MDK = TheMetadata.RegisterMDKind(Name.c_str()); + MDsOnInst.push_back(std::make_pair(MDK, cast(Node))); return false; } @@ -1067,8 +1073,8 @@ // FIXME: Handle customized metadata info attached with an instruction. do { - if (Lex.getKind() == lltok::kw_dbg) { - if (ParseOptionalDbgInfo()) return true; + if (Lex.getKind() == lltok::NamedOrCustomMD) { + if (ParseOptionalCustomMetadata()) return true; } else if (Lex.getKind() == lltok::kw_align) { if (ParseOptionalAlignment(Alignment)) return true; } else @@ -2653,7 +2659,7 @@ if (ParseInstruction(Inst, BB, PFS)) return true; if (EatIfPresent(lltok::comma)) - ParseOptionalDbgInfo(); + ParseOptionalCustomMetadata(); // Set metadata attached with this instruction. MetadataContext &TheMetadata = M->getContext().getMetadata(); @@ -2841,9 +2847,9 @@ //===----------------------------------------------------------------------===// /// ParseRet - Parse a return instruction. -/// ::= 'ret' void (',' 'dbg' !1) -/// ::= 'ret' TypeAndValue (',' 'dbg' !1) -/// ::= 'ret' TypeAndValue (',' TypeAndValue)+ (',' 'dbg' !1) +/// ::= 'ret' void (',' !dbg, !1) +/// ::= 'ret' TypeAndValue (',' !dbg, !1) +/// ::= 'ret' TypeAndValue (',' TypeAndValue)+ (',' !dbg, !1) /// [[obsolete: LLVM 3.0]] bool LLParser::ParseRet(Instruction *&Inst, BasicBlock *BB, PerFunctionState &PFS) { @@ -2852,7 +2858,7 @@ if (Ty == Type::getVoidTy(Context)) { if (EatIfPresent(lltok::comma)) - if (ParseOptionalDbgInfo()) return true; + if (ParseOptionalCustomMetadata()) return true; Inst = ReturnInst::Create(Context); return false; } @@ -2861,9 +2867,9 @@ if (ParseValue(Ty, RV, PFS)) return true; if (EatIfPresent(lltok::comma)) { - // Parse optional 'dbg' - if (Lex.getKind() == lltok::kw_dbg) { - if (ParseOptionalDbgInfo()) return true; + // Parse optional custom metadata, e.g. !dbg + if (Lex.getKind() == lltok::NamedOrCustomMD) { + if (ParseOptionalCustomMetadata()) return true; } else { // The normal case is one return value. // FIXME: LLVM 3.0 remove MRV support for 'ret i32 1, i32 2', requiring use @@ -2872,8 +2878,9 @@ RVs.push_back(RV); do { - // If optional 'dbg' is seen then this is the end of MRV. - if (Lex.getKind() == lltok::kw_dbg) + // If optional custom metadata, e.g. !dbg is seen then this is the + // end of MRV. + if (Lex.getKind() == lltok::NamedOrCustomMD) break; if (ParseTypeAndValue(RV, PFS)) return true; RVs.push_back(RV); @@ -2888,7 +2895,7 @@ } } if (EatIfPresent(lltok::comma)) - if (ParseOptionalDbgInfo()) return true; + if (ParseOptionalCustomMetadata()) return true; Inst = ReturnInst::Create(Context, RV); return false; @@ -3439,7 +3446,8 @@ if (ParseType(Ty)) return true; if (EatIfPresent(lltok::comma)) { - if (Lex.getKind() == lltok::kw_align || Lex.getKind() == lltok::kw_dbg) { + if (Lex.getKind() == lltok::kw_align + || Lex.getKind() == lltok::NamedOrCustomMD) { if (ParseOptionalInfo(Alignment)) return true; } else { if (ParseTypeAndValue(Size, SizeLoc, PFS)) return true; Modified: llvm/trunk/lib/AsmParser/LLParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.h?rev=83033&r1=83032&r2=83033&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.h (original) +++ llvm/trunk/lib/AsmParser/LLParser.h Mon Sep 28 19:01:14 2009 @@ -128,7 +128,7 @@ bool ParseOptionalVisibility(unsigned &Visibility); bool ParseOptionalCallingConv(CallingConv::ID &CC); bool ParseOptionalAlignment(unsigned &Alignment); - bool ParseOptionalDbgInfo(); + bool ParseOptionalCustomMetadata(); bool ParseOptionalInfo(unsigned &Alignment); bool ParseIndexList(SmallVectorImpl &Indices); Modified: llvm/trunk/lib/AsmParser/LLToken.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=83033&r1=83032&r2=83033&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLToken.h (original) +++ llvm/trunk/lib/AsmParser/LLToken.h Mon Sep 28 19:01:14 2009 @@ -127,7 +127,7 @@ GlobalVar, // @foo @"foo" LocalVar, // %foo %"foo" StringConstant, // "foo" - NamedMD, // !foo + NamedOrCustomMD, // !foo // Metadata valued tokens. Metadata, // !"foo" !{i8 42} Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=83033&r1=83032&r2=83033&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Sep 28 19:01:14 2009 @@ -2007,7 +2007,7 @@ for (MetadataContext::MDMapTy::const_iterator MI = MDMap->begin(), ME = MDMap->end(); MI != ME; ++MI) if (const MDNode *MD = dyn_cast_or_null(MI->second)) - Out << ", " << MDNames[MI->first] + Out << ", !" << MDNames[MI->first] << " !" << Machine.getMetadataSlot(MD); printInfoComment(I); Modified: llvm/trunk/lib/VMCore/Metadata.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=83033&r1=83032&r2=83033&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Metadata.cpp (original) +++ llvm/trunk/lib/VMCore/Metadata.cpp Mon Sep 28 19:01:14 2009 @@ -260,6 +260,7 @@ /// RegisterMDKind - Register a new metadata kind and return its ID. /// A metadata kind can be registered only once. unsigned MetadataContext::RegisterMDKind(const char *Name) { + assert (validName(Name) && "Invalid custome metadata name!"); unsigned Count = MDHandlerNames.size(); StringMap::iterator I = MDHandlerNames.find(Name); assert(I == MDHandlerNames.end() && "Already registered MDKind!"); @@ -267,9 +268,31 @@ return Count + 1; } +/// validName - Return true if Name is a valid custom metadata handler name. +bool MetadataContext::validName(const char *Name) { + if (!Name) + return false; + + if (!isalpha(*Name)) + return false; + + unsigned Length = strlen(Name); + unsigned Count = 1; + ++Name; + while (Name && + (isalnum(*Name) || *Name == '_' || *Name == '-' || *Name == '.')) { + ++Name; + ++Count; + } + if (Length != Count) + return false; + return true; +} + /// getMDKind - Return metadata kind. If the requested metadata kind /// is not registered then return 0. unsigned MetadataContext::getMDKind(const char *Name) { + assert (validName(Name) && "Invalid custome metadata name!"); StringMap::iterator I = MDHandlerNames.find(Name); if (I == MDHandlerNames.end()) return 0; Modified: llvm/trunk/test/Feature/md_on_instruction.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/md_on_instruction.ll?rev=83033&r1=83032&r2=83033&view=diff ============================================================================== --- llvm/trunk/test/Feature/md_on_instruction.ll (original) +++ llvm/trunk/test/Feature/md_on_instruction.ll Mon Sep 28 19:01:14 2009 @@ -4,13 +4,13 @@ entry: %retval = alloca i32 ; [#uses=2] call void @llvm.dbg.func.start(metadata !0) - store i32 42, i32* %retval, dbg !3 - br label %0, dbg !3 + store i32 42, i32* %retval, !dbg !3 + br label %0, !dbg !3 ;
a dag value. The first element is required to be a record definition, the remaining elements in the list may be arbitrary other values, including nested `dag' values.
-
(implicit a)
-
an implicitly defined physical register. This tells the dag instruction - selection emitter the input pattern's extra definitions matches implicit - physical register definitions.
-
(parallel (a), (b))
-
a list of dags specifying parallel operations which map to the same - instruction.
!strconcat(a, b)
A string value that is the result of concatenating the 'a' and 'b' strings.
@@ -760,6 +753,25 @@ +
Code Generator backend info
+ + +

Expressions used by code generator to describe instructions and isel +patterns:

+ +
+ +
(implicit a)
+
an implicitly defined physical register. This tells the dag instruction + selection emitter the input pattern's extra definitions matches implicit + physical register definitions.
+
(parallel (a), (b))
+
a list of dags specifying parallel operations which map to the same + instruction.
+ +
+ +
TableGen backends