From evan.cheng at apple.com Mon Nov 16 00:31:50 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 16 Nov 2009 06:31:50 -0000 Subject: [llvm-commits] [llvm] r88899 - in /llvm/trunk: lib/CodeGen/TargetInstrInfoImpl.cpp test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll Message-ID: <200911160631.nAG6VosF021741@zion.cs.uiuc.edu> Author: evancheng Date: Mon Nov 16 00:31:49 2009 New Revision: 88899 URL: http://llvm.org/viewvc/llvm-project?rev=88899&view=rev Log: Check if subreg index is zero. Added: llvm/trunk/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=88899&r1=88898&r2=88899&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Mon Nov 16 00:31:49 2009 @@ -142,8 +142,10 @@ if (TargetRegisterInfo::isVirtualRegister(DestReg)) { MO.setReg(DestReg); MO.setSubReg(SubIdx); - } else { + } else if (SubIdx) { MO.setReg(TRI->getSubReg(DestReg, SubIdx)); + } else { + MO.setReg(DestReg); } MBB.insert(I, MI); } Added: llvm/trunk/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll?rev=88899&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll (added) +++ llvm/trunk/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll Mon Nov 16 00:31:49 2009 @@ -0,0 +1,155 @@ +; RUN: llc < %s -mtriple=powerpc-apple-darwin8 + +%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } +%struct.__gcov_var = type { %struct.FILE*, i32, i32, i32, i32, i32, i32, [1025 x i32] } +%struct.__sFILEX = type opaque +%struct.__sbuf = type { i8*, i32 } +%struct.gcov_ctr_info = type { i32, i64*, void (i64*, i32)* } +%struct.gcov_ctr_summary = type { i32, i32, i64, i64, i64 } +%struct.gcov_fn_info = type { i32, i32, [0 x i32] } +%struct.gcov_info = type { i32, %struct.gcov_info*, i32, i8*, i32, %struct.gcov_fn_info*, i32, [0 x %struct.gcov_ctr_info] } +%struct.gcov_summary = type { i32, [1 x %struct.gcov_ctr_summary] } + + at __gcov_var = external global %struct.__gcov_var ; <%struct.__gcov_var*> [#uses=1] + at __sF = external global [0 x %struct.FILE] ; <[0 x %struct.FILE]*> [#uses=1] + at .str = external constant [56 x i8], align 4 ; <[56 x i8]*> [#uses=1] + at gcov_list = external global %struct.gcov_info* ; <%struct.gcov_info**> [#uses=1] + at .str7 = external constant [35 x i8], align 4 ; <[35 x i8]*> [#uses=1] + at .str8 = external constant [9 x i8], align 4 ; <[9 x i8]*> [#uses=1] + at .str9 = external constant [10 x i8], align 4 ; <[10 x i8]*> [#uses=1] + at .str10 = external constant [36 x i8], align 4 ; <[36 x i8]*> [#uses=1] + +declare i32 @"\01_fprintf$LDBL128"(%struct.FILE*, i8*, ...) nounwind + +define void @gcov_exit() nounwind { +entry: + %gi_ptr.0357 = load %struct.gcov_info** @gcov_list, align 4 ; <%struct.gcov_info*> [#uses=1] + %0 = alloca i8, i32 undef, align 1 ; [#uses=3] + br i1 undef, label %return, label %bb.nph341 + +bb.nph341: ; preds = %entry + %object27 = bitcast %struct.gcov_summary* undef to i8* ; [#uses=1] + br label %bb25 + +bb25: ; preds = %read_fatal, %bb.nph341 + %gi_ptr.1329 = phi %struct.gcov_info* [ %gi_ptr.0357, %bb.nph341 ], [ undef, %read_fatal ] ; <%struct.gcov_info*> [#uses=1] + call void @llvm.memset.i32(i8* %object27, i8 0, i32 36, i32 8) + br i1 undef, label %bb49.1, label %bb48 + +bb48: ; preds = %bb25 + br label %bb49.1 + +bb51: ; preds = %bb48.4, %bb49.3 + switch i32 undef, label %bb58 [ + i32 0, label %rewrite + i32 1734567009, label %bb59 + ] + +bb58: ; preds = %bb51 + %1 = call i32 (%struct.FILE*, i8*, ...)* @"\01_fprintf$LDBL128"(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2), i8* getelementptr inbounds ([35 x i8]* @.str7, i32 0, i32 0), i8* %0) nounwind ; [#uses=0] + br label %read_fatal + +bb59: ; preds = %bb51 + br i1 undef, label %bb60, label %bb3.i156 + +bb3.i156: ; preds = %bb59 + store i8 52, i8* undef, align 1 + store i8 42, i8* undef, align 1 + %2 = call i32 (%struct.FILE*, i8*, ...)* @"\01_fprintf$LDBL128"(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2), i8* getelementptr inbounds ([56 x i8]* @.str, i32 0, i32 0), i8* %0, i8* undef, i8* undef) nounwind ; [#uses=0] + br label %read_fatal + +bb60: ; preds = %bb59 + br i1 undef, label %bb78.preheader, label %rewrite + +bb78.preheader: ; preds = %bb60 + br i1 undef, label %bb62, label %bb80 + +bb62: ; preds = %bb78.preheader + br i1 undef, label %bb64, label %read_mismatch + +bb64: ; preds = %bb62 + br i1 undef, label %bb65, label %read_mismatch + +bb65: ; preds = %bb64 + br i1 undef, label %bb75, label %read_mismatch + +read_mismatch: ; preds = %bb98, %bb119.preheader, %bb72, %bb71, %bb65, %bb64, %bb62 + %3 = icmp eq i32 undef, -1 ; [#uses=1] + %iftmp.11.0 = select i1 %3, i8* getelementptr inbounds ([10 x i8]* @.str9, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str8, i32 0, i32 0) ; [#uses=1] + %4 = call i32 (%struct.FILE*, i8*, ...)* @"\01_fprintf$LDBL128"(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2), i8* getelementptr inbounds ([36 x i8]* @.str10, i32 0, i32 0), i8* %0, i8* %iftmp.11.0) nounwind ; [#uses=0] + br label %read_fatal + +bb71: ; preds = %bb75 + %5 = load i32* undef, align 4 ; [#uses=1] + %6 = getelementptr inbounds %struct.gcov_info* %gi_ptr.1329, i32 0, i32 7, i32 undef, i32 2 ; [#uses=1] + %7 = load void (i64*, i32)** %6, align 4 ; [#uses=1] + %8 = call i32 @__gcov_read_unsigned() nounwind ; [#uses=1] + %9 = call i32 @__gcov_read_unsigned() nounwind ; [#uses=1] + %10 = icmp eq i32 %tmp386, %8 ; [#uses=1] + br i1 %10, label %bb72, label %read_mismatch + +bb72: ; preds = %bb71 + %11 = icmp eq i32 undef, %9 ; [#uses=1] + br i1 %11, label %bb73, label %read_mismatch + +bb73: ; preds = %bb72 + call void %7(i64* null, i32 %5) nounwind + unreachable + +bb74: ; preds = %bb75 + %12 = add i32 %13, 1 ; [#uses=1] + br label %bb75 + +bb75: ; preds = %bb74, %bb65 + %13 = phi i32 [ %12, %bb74 ], [ 0, %bb65 ] ; [#uses=2] + %tmp386 = add i32 0, 27328512 ; [#uses=1] + %14 = shl i32 1, %13 ; [#uses=1] + %15 = load i32* undef, align 4 ; [#uses=1] + %16 = and i32 %15, %14 ; [#uses=1] + %17 = icmp eq i32 %16, 0 ; [#uses=1] + br i1 %17, label %bb74, label %bb71 + +bb80: ; preds = %bb78.preheader + unreachable + +read_fatal: ; preds = %read_mismatch, %bb3.i156, %bb58 + br i1 undef, label %return, label %bb25 + +rewrite: ; preds = %bb60, %bb51 + store i32 -1, i32* getelementptr inbounds (%struct.__gcov_var* @__gcov_var, i32 0, i32 6), align 4 + br i1 undef, label %bb94, label %bb119.preheader + +bb94: ; preds = %rewrite + unreachable + +bb119.preheader: ; preds = %rewrite + br i1 undef, label %read_mismatch, label %bb98 + +bb98: ; preds = %bb119.preheader + br label %read_mismatch + +return: ; preds = %read_fatal, %entry + ret void + +bb49.1: ; preds = %bb48, %bb25 + br i1 undef, label %bb49.2, label %bb48.2 + +bb49.2: ; preds = %bb48.2, %bb49.1 + br i1 undef, label %bb49.3, label %bb48.3 + +bb48.2: ; preds = %bb49.1 + br label %bb49.2 + +bb49.3: ; preds = %bb48.3, %bb49.2 + br i1 undef, label %bb51, label %bb48.4 + +bb48.3: ; preds = %bb49.2 + br label %bb49.3 + +bb48.4: ; preds = %bb49.3 + br label %bb51 +} + +declare i32 @__gcov_read_unsigned() nounwind + +declare void @llvm.memset.i32(i8* nocapture, i8, i32, i32) nounwind From evan.cheng at apple.com Mon Nov 16 00:44:40 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 15 Nov 2009 22:44:40 -0800 Subject: [llvm-commits] [llvm] r88805 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp In-Reply-To: <200911142010.nAEKAIMp014778@zion.cs.uiuc.edu> References: <200911142010.nAEKAIMp014778@zion.cs.uiuc.edu> Message-ID: Hi Jim, Some comments for 86999 and friends: /// ReorderThumb2JumpTables - Use tbb / tbh instructions to generate smaller /// jumptables when it's possible. bool ARMConstantIslands::ReorderThumb2JumpTables(MachineFunction &MF) { This comment is misleading. tbb / tbh are formed later, right? + // FIXME: If it's a small block terminated by an unconditional branch, + // try to move it; otherwise, create a new block following the jump + // table that branches back to the actual target. This is an overly + // simplistic heuristic here for proof-of-concept. What do you plan as a replacement? Jump + jump seems bad for performance? Why not just add a unconditional branch to replace the fall through? + // If the block is small and ends in an unconditional branch, move it. + if (Size < 50 && Cond.empty()) Where is 50 coming from? Evan On Nov 14, 2009, at 12:10 PM, Jim Grosbach wrote: > Author: grosbach > Date: Sat Nov 14 14:10:18 2009 > New Revision: 88805 > > URL: http://llvm.org/viewvc/llvm-project?rev=88805&view=rev > Log: > Cleanup flow, and only update the jump table we're analyzing when replacing a destination MBB. > > Modified: > llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=88805&r1=88804&r2=88805&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Sat Nov 14 14:10:18 2009 > @@ -1749,7 +1749,7 @@ > MachineBasicBlock *NewBB = > AdjustJTTargetBlockForward(MBB, MI->getParent()); > if (NewBB) > - MJTI->ReplaceMBBInJumpTables(JTBBs[j], NewBB); > + MJTI->ReplaceMBBInJumpTable(JTI, JTBBs[j], NewBB); > MadeChange = true; > } > } > @@ -1772,16 +1772,16 @@ > int Size = BBSizes[BBI]; > MachineBasicBlock *TBB = 0, *FBB = 0; > SmallVector Cond; > - // If the block terminator isn't analyzable, don't try to move the block > - if (TII->AnalyzeBranch(*BB, TBB, FBB, Cond)) > - return NULL; > - > // If the block is small and ends in an unconditional branch, move it. > if (Size < 50 && Cond.empty()) { > + // If the block terminator isn't analyzable, don't try to move the block > + if (TII->AnalyzeBranch(*BB, TBB, FBB, Cond)) > + return NULL; > + > MachineFunction::iterator OldPrior = prior(BB); > BB->moveAfter(JTBB); > OldPrior->updateTerminator(); > - //BB->updateTerminator(); > + BB->updateTerminator(); > ++NumJTMoved; > return NULL; > } > @@ -1792,20 +1792,22 @@ > MachineFunction::iterator MBBI = JTBB; ++MBBI; > MF.insert(MBBI, NewBB); > > + //MF.splice(MBBI, NewBB, NewBB); > + > // Add an unconditional branch from NewBB to BB. > // There doesn't seem to be meaningful DebugInfo available; this doesn't > // correspond directly to anything in the source. > assert (isThumb2 && "Adjusting for TB[BH] but not in Thumb2?"); > BuildMI(NewBB, DebugLoc::getUnknownLoc(), TII->get(ARM::t2B)).addMBB(BB); > > + // Update internal data structures to account for the newly inserted MBB. > + MF.RenumberBlocks(NewBB); > + > // Update the CFG. > NewBB->addSuccessor(BB); > JTBB->removeSuccessor(BB); > JTBB->addSuccessor(NewBB); > > - // Update internal data structures to account for the newly inserted MBB. > - MF.RenumberBlocks(); > - > // Insert a size into BBSizes to align it properly with the (newly > // renumbered) block numbers. > BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Nov 16 01:10:36 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 16 Nov 2009 07:10:36 -0000 Subject: [llvm-commits] [llvm] r88902 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <200911160710.nAG7Aa2W023263@zion.cs.uiuc.edu> Author: evancheng Date: Mon Nov 16 01:10:36 2009 New Revision: 88902 URL: http://llvm.org/viewvc/llvm-project?rev=88902&view=rev Log: Special case FixedStackPseudoSourceValueVal as well. Do we really need to differentiate PseudoSourceValueVal from FixedStackPseudoSourceValueVal at this level? Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=88902&r1=88901&r2=88902&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Nov 16 01:10:36 2009 @@ -1238,7 +1238,8 @@ return; } - if (V->getValueID() == Value::PseudoSourceValueVal) { + if (V->getValueID() == Value::PseudoSourceValueVal || + V->getValueID() == Value::FixedStackPseudoSourceValueVal) { V->print(Out); return; } From evan.cheng at apple.com Mon Nov 16 01:12:29 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 15 Nov 2009 23:12:29 -0800 Subject: [llvm-commits] [llvm] r87028 - /llvm/trunk/include/llvm/Value.h In-Reply-To: <200911122104.nACL4KeC009301@zion.cs.uiuc.edu> References: <200911122104.nACL4KeC009301@zion.cs.uiuc.edu> Message-ID: <2E007F8C-185A-4FF7-93B6-580DD29F92C7@apple.com> Do we really want to differentiate FixedStackPseudoSourceValueVal as a distinct subclass at the IR level? This seems wrong to me. Evan On Nov 12, 2009, at 1:04 PM, David Greene wrote: > Author: greened > Date: Thu Nov 12 15:04:19 2009 > New Revision: 87028 > > URL: http://llvm.org/viewvc/llvm-project?rev=87028&view=rev > Log: > > Fix a build error by providing a missing enum value. > > Modified: > llvm/trunk/include/llvm/Value.h > > Modified: llvm/trunk/include/llvm/Value.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Value.h?rev=87028&r1=87027&r2=87028&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Value.h (original) > +++ llvm/trunk/include/llvm/Value.h Thu Nov 12 15:04:19 2009 > @@ -226,7 +226,9 @@ > PseudoSourceValueVal, // This is an instance of PseudoSourceValue > FixedStackPseudoSourceValueVal, // This is an instance of PseudoSourceValue > InstructionVal, // This is an instance of Instruction > - > + FixedStackPseudoSourceValueVal, // This is an instance of > + // FixedStackPseudoSourceValue > + > // Markers: > ConstantFirstVal = FunctionVal, > ConstantLastVal = ConstantPointerNullVal > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Nov 16 01:39:35 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 15 Nov 2009 23:39:35 -0800 Subject: [llvm-commits] [PATCH] Make X86-64 in the Large model always emit 64-bit calls In-Reply-To: References: <001636ed6e725660440478316be4@google.com> <0C21B7A2-76D2-48D4-8FE6-434AFC6FC5E1@apple.com> <072EB1A4-3A94-46BF-86CC-827F3F0E63E3@apple.com> Message-ID: On Nov 15, 2009, at 8:28 PM, Eric Christopher wrote: >> >> I'm trying for no far-stubs at all. :) With a unique stub for each >> GlobalValue, the _stub_ can be more than 2GB away from the code using >> it. And without either a unique stub or a bunch of work distinguishing >> uses from address-of operations, &GV == address_of_GV() can be false. > > After we took this offline I think I figured out what the problem is. We still had a point where we were trying to tell llvm that we wanted a small code model instead of large. > > That said, there's still a problem: what if someone really does want small code model? Do we want to support that? If so, then we need to have some way of making small code model continue to work on x86-64. I do have an internal customer that we believe needs small code model. Unless the new way has no disadvantages over small? We can support small code model. So we should force large code model unless explicitly specified otherwise. If the client wants small code model, the memory manager must be able to ensure that. Evan > > -eric > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Mon Nov 16 03:18:56 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 16 Nov 2009 09:18:56 -0000 Subject: [llvm-commits] [dragonegg] r88903 - in /dragonegg/trunk: llvm-convert.cpp x86/llvm-target.cpp Message-ID: <200911160918.nAG9Iu17009484@zion.cs.uiuc.edu> Author: baldrick Date: Mon Nov 16 03:18:55 2009 New Revision: 88903 URL: http://llvm.org/viewvc/llvm-project?rev=88903&view=rev Log: Get rid of CastToUIntType and CastToSIntType: use Builder.CreateIntCast instead. While there, I noticed that many calls to CreateIntCast were not passing a value for the isSigned boolean: the name (eg: "cast") was being used for isSigned! The definition of CreateIntCast should be tweaked so that this mistake is not possible... Modified: dragonegg/trunk/llvm-convert.cpp dragonegg/trunk/x86/llvm-target.cpp Modified: dragonegg/trunk/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-convert.cpp?rev=88903&r1=88902&r2=88903&view=diff ============================================================================== --- dragonegg/trunk/llvm-convert.cpp (original) +++ dragonegg/trunk/llvm-convert.cpp Mon Nov 16 03:18:55 2009 @@ -1345,38 +1345,6 @@ return Builder.CreateCast(opc, V, Ty); } -/// CastToUIntType - Cast the specified value to the specified type assuming -/// that the value and type are unsigned integer types. -Value *TreeToLLVM::CastToUIntType(Value *V, const Type* Ty) { - // Eliminate useless casts of a type to itself. - if (V->getType() == Ty) - return V; - - unsigned SrcBits = V->getType()->getPrimitiveSizeInBits(); - unsigned DstBits = Ty->getPrimitiveSizeInBits(); - assert(SrcBits != DstBits && "Types are different but have same #bits?"); - - Instruction::CastOps opcode = - (SrcBits > DstBits ? Instruction::Trunc : Instruction::ZExt); - return Builder.CreateCast(opcode, V, Ty); -} - -/// CastToSIntType - Cast the specified value to the specified type assuming -/// that the value and type are signed integer types. -Value *TreeToLLVM::CastToSIntType(Value *V, const Type* Ty) { - // Eliminate useless casts of a type to itself. - if (V->getType() == Ty) - return V; - - unsigned SrcBits = V->getType()->getPrimitiveSizeInBits(); - unsigned DstBits = Ty->getPrimitiveSizeInBits(); - assert(SrcBits != DstBits && "Types are different but have same #bits?"); - - Instruction::CastOps opcode = - (SrcBits > DstBits ? Instruction::Trunc : Instruction::SExt); - return Builder.CreateCast(opcode, V, Ty); -} - /// CastToFPType - Cast the specified value to the specified type assuming /// that the value and type are floating point. Value *TreeToLLVM::CastToFPType(Value *V, const Type* Ty) { @@ -1620,7 +1588,7 @@ Value *Ops[4] = { Builder.CreateBitCast(DestPtr, SBP), Builder.CreateBitCast(SrcPtr, SBP), - CastToSIntType(Size, IntPtr), + Builder.CreateIntCast(Size, IntPtr, /*isSigned*/true), ConstantInt::get(Type::getInt32Ty(Context), Align) }; @@ -1636,7 +1604,7 @@ Value *Ops[4] = { Builder.CreateBitCast(DestPtr, SBP), Builder.CreateBitCast(SrcPtr, SBP), - CastToSIntType(Size, IntPtr), + Builder.CreateIntCast(Size, IntPtr, /*isSigned*/true), ConstantInt::get(Type::getInt32Ty(Context), Align) }; @@ -1651,8 +1619,8 @@ const Type *IntPtr = TD.getIntPtrType(Context); Value *Ops[4] = { Builder.CreateBitCast(DestPtr, SBP), - CastToSIntType(SrcVal, Type::getInt8Ty(Context)), - CastToSIntType(Size, IntPtr), + Builder.CreateIntCast(SrcVal, Type::getInt8Ty(Context), /*isSigned*/true), + Builder.CreateIntCast(Size, IntPtr, /*isSigned*/true), ConstantInt::get(Type::getInt32Ty(Context), Align) }; @@ -1782,7 +1750,8 @@ Size = Emit(DECL_SIZE_UNIT(decl), 0); Ty = Type::getInt8Ty(Context); } - Size = CastToUIntType(Size, Type::getInt32Ty(Context)); + Size = Builder.CreateIntCast(Size, Type::getInt32Ty(Context), + /*isSigned*/false); } unsigned Alignment = 0; // Alignment in bytes. @@ -2502,10 +2471,8 @@ } } - if (TYPE_UNSIGNED(TREE_TYPE(exp))) - return CastToUIntType(Result, Ty); - else - return CastToSIntType(Result, Ty); + return Builder.CreateIntCast(Result, Ty, + /*isSigned*/!TYPE_UNSIGNED(TREE_TYPE(exp))); } } @@ -3233,7 +3200,7 @@ V = Builder.CreateICmpNE(V, Constant::getNullValue(V->getType()), "toBool"); V = Builder.CreateNot(V, (V->getNameStr()+"not").c_str()); - return CastToUIntType(V, ConvertType(type)); + return Builder.CreateIntCast(V, ConvertType(type), /*isSigned*/false); } /// EmitCompare - Compare LHS with RHS using the appropriate comparison code. @@ -3392,7 +3359,7 @@ Value *LHS = EmitGimpleReg(op0); Value *RHS = EmitGimpleReg(op1); if (RHS->getType() != LHS->getType()) - RHS = Builder.CreateIntCast(RHS, LHS->getType(), false, + RHS = Builder.CreateIntCast(RHS, LHS->getType(), /*isSigned*/false, (RHS->getNameStr()+".cast").c_str()); return Builder.CreateBinOp((Instruction::BinaryOps)Opc, LHS, RHS); @@ -3404,7 +3371,7 @@ Value *Amt = EmitGimpleReg(op1); if (Amt->getType() != In->getType()) - Amt = Builder.CreateIntCast(Amt, In->getType(), false, + Amt = Builder.CreateIntCast(Amt, In->getType(), /*isSigned*/false, (Amt->getNameStr()+".cast").c_str()); Value *TypeSize = @@ -3418,7 +3385,7 @@ // Or the two together to return them. Value *Merge = Builder.CreateOr(V1, V2); - return CastToUIntType(Merge, ConvertType(type)); + return Builder.CreateIntCast(Merge, ConvertType(type), /*isSigned*/false); } Value *TreeToLLVM::EmitMinMaxExpr(tree type, tree op0, tree op1, @@ -3679,7 +3646,9 @@ Value *Quotient = Builder.CreateUDiv(Numerator, RHS); // Return Quotient unless we overflowed, in which case return Quotient + 1. - return Builder.CreateAdd(Quotient, CastToUIntType(Overflowed, Ty), "rdiv"); + return Builder.CreateAdd(Quotient, Builder.CreateIntCast(Overflowed, Ty, + /*isSigned*/false), + "rdiv"); } Value *TreeToLLVM::EmitPOINTER_PLUS_EXPR(tree type, tree op0, tree op1) { @@ -4293,7 +4262,8 @@ Value * TreeToLLVM::BuildBinaryAtomicBuiltin(gimple stmt, Intrinsic::ID id) { - const Type *ResultTy = ConvertType(gimple_call_return_type(stmt)); + tree return_type = gimple_call_return_type(stmt); + const Type *ResultTy = ConvertType(return_type); Value* C[2] = { Emit(gimple_call_arg(stmt, 0), 0), Emit(gimple_call_arg(stmt, 1), 0) @@ -4302,7 +4272,9 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], + /*isSigned*/!TYPE_UNSIGNED(return_type), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. EmitMemoryBarrier(true, true, true, true); @@ -4326,8 +4298,10 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); - C[2] = Builder.CreateIntCast(C[2], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], /*isSigned*/!TYPE_UNSIGNED(type), + "cast"); + C[2] = Builder.CreateIntCast(C[2], Ty[0], /*isSigned*/!TYPE_UNSIGNED(type), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -4344,8 +4318,9 @@ EmitMemoryBarrier(true, true, true, true); if (isBool) - Result = CastToUIntType(Builder.CreateICmpEQ(Result, C[1]), - ConvertType(boolean_type_node)); + Result = Builder.CreateIntCast(Builder.CreateICmpEQ(Result, C[1]), + ConvertType(boolean_type_node), + /*isSigned*/false); else Result = Builder.CreateIntToPtr(Result, ResultTy); return Result; @@ -4473,7 +4448,8 @@ // Manually coerce the arg to the correct pointer type. Args[0] = Builder.CreateBitCast(Args[0], Type::getInt8PtrTy(Context)); - Args[1] = Builder.CreateIntCast(Args[1], Type::getInt32Ty(Context), false); + Args[1] = Builder.CreateIntCast(Args[1], Type::getInt32Ty(Context), + /*isSigned*/false); Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::objectsize, @@ -4490,8 +4466,11 @@ case BUILT_IN_CLZLL: { Value *Amt = Emit(gimple_call_arg(stmt, 0), 0); EmitBuiltinUnaryOp(Amt, Result, Intrinsic::ctlz); - const Type *DestTy = ConvertType(gimple_call_return_type(stmt)); - Result = Builder.CreateIntCast(Result, DestTy, "cast"); + tree return_type = gimple_call_return_type(stmt); + const Type *DestTy = ConvertType(return_type); + Result = Builder.CreateIntCast(Result, DestTy, + /*isSigned*/!TYPE_UNSIGNED(return_type), + "cast"); return true; } case BUILT_IN_CTZ: // These GCC builtins always return int. @@ -4499,8 +4478,11 @@ case BUILT_IN_CTZLL: { Value *Amt = Emit(gimple_call_arg(stmt, 0), 0); EmitBuiltinUnaryOp(Amt, Result, Intrinsic::cttz); - const Type *DestTy = ConvertType(gimple_call_return_type(stmt)); - Result = Builder.CreateIntCast(Result, DestTy, "cast"); + tree return_type = gimple_call_return_type(stmt); + const Type *DestTy = ConvertType(return_type); + Result = Builder.CreateIntCast(Result, DestTy, + /*isSigned*/!TYPE_UNSIGNED(return_type), + "cast"); return true; } case BUILT_IN_PARITYLL: @@ -4517,16 +4499,22 @@ case BUILT_IN_POPCOUNTLL: { Value *Amt = Emit(gimple_call_arg(stmt, 0), 0); EmitBuiltinUnaryOp(Amt, Result, Intrinsic::ctpop); - const Type *DestTy = ConvertType(gimple_call_return_type(stmt)); - Result = Builder.CreateIntCast(Result, DestTy, "cast"); + tree return_type = gimple_call_return_type(stmt); + const Type *DestTy = ConvertType(return_type); + Result = Builder.CreateIntCast(Result, DestTy, + /*isSigned*/!TYPE_UNSIGNED(return_type), + "cast"); return true; } case BUILT_IN_BSWAP32: case BUILT_IN_BSWAP64: { Value *Amt = Emit(gimple_call_arg(stmt, 0), 0); EmitBuiltinUnaryOp(Amt, Result, Intrinsic::bswap); - const Type *DestTy = ConvertType(gimple_call_return_type(stmt)); - Result = Builder.CreateIntCast(Result, DestTy, "cast"); + tree return_type = gimple_call_return_type(stmt); + const Type *DestTy = ConvertType(return_type); + Result = Builder.CreateIntCast(Result, DestTy, + /*isSigned*/!TYPE_UNSIGNED(return_type), + "cast"); return true; } @@ -4615,7 +4603,9 @@ EmitBuiltinUnaryOp(Amt, Result, Intrinsic::cttz); Result = Builder.CreateAdd(Result, ConstantInt::get(Result->getType(), 1)); - Result = CastToUIntType(Result, ConvertType(gimple_call_return_type(stmt))); + Result = Builder.CreateIntCast(Result, + ConvertType(gimple_call_return_type(stmt)), + /*isSigned*/false); Value *Cond = Builder.CreateICmpEQ(Amt, Constant::getNullValue(Amt->getType())); @@ -4810,7 +4800,8 @@ case BUILT_IN_ADD_AND_FETCH_1: case BUILT_IN_ADD_AND_FETCH_2: case BUILT_IN_ADD_AND_FETCH_4: { - const Type *ResultTy = ConvertType(gimple_call_return_type(stmt)); + tree return_type = gimple_call_return_type(stmt); + const Type *ResultTy = ConvertType(return_type); Value* C[2] = { Emit(gimple_call_arg(stmt, 0), 0), Emit(gimple_call_arg(stmt, 1), 0) @@ -4819,7 +4810,9 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], + /*isSigned*/!TYPE_UNSIGNED(return_type), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -4847,7 +4840,8 @@ case BUILT_IN_SUB_AND_FETCH_1: case BUILT_IN_SUB_AND_FETCH_2: case BUILT_IN_SUB_AND_FETCH_4: { - const Type *ResultTy = ConvertType(gimple_call_return_type(stmt)); + tree return_type = gimple_call_return_type(stmt); + const Type *ResultTy = ConvertType(return_type); Value* C[2] = { Emit(gimple_call_arg(stmt, 0), 0), Emit(gimple_call_arg(stmt, 1), 0) @@ -4856,7 +4850,9 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], + /*isSigned*/!TYPE_UNSIGNED(return_type), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -4884,7 +4880,8 @@ case BUILT_IN_OR_AND_FETCH_1: case BUILT_IN_OR_AND_FETCH_2: case BUILT_IN_OR_AND_FETCH_4: { - const Type *ResultTy = ConvertType(gimple_call_return_type(stmt)); + tree return_type = gimple_call_return_type(stmt); + const Type *ResultTy = ConvertType(return_type); Value* C[2] = { Emit(gimple_call_arg(stmt, 0), 0), Emit(gimple_call_arg(stmt, 1), 0) @@ -4893,7 +4890,9 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], + /*isSigned*/!TYPE_UNSIGNED(return_type), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -4921,7 +4920,8 @@ case BUILT_IN_AND_AND_FETCH_1: case BUILT_IN_AND_AND_FETCH_2: case BUILT_IN_AND_AND_FETCH_4: { - const Type *ResultTy = ConvertType(gimple_call_return_type(stmt)); + tree return_type = gimple_call_return_type(stmt); + const Type *ResultTy = ConvertType(return_type); Value* C[2] = { Emit(gimple_call_arg(stmt, 0), 0), Emit(gimple_call_arg(stmt, 1), 0) @@ -4930,7 +4930,9 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], + /*isSigned*/!TYPE_UNSIGNED(return_type), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -4958,7 +4960,8 @@ case BUILT_IN_XOR_AND_FETCH_1: case BUILT_IN_XOR_AND_FETCH_2: case BUILT_IN_XOR_AND_FETCH_4: { - const Type *ResultTy = ConvertType(gimple_call_return_type(stmt)); + tree return_type = gimple_call_return_type(stmt); + const Type *ResultTy = ConvertType(return_type); Value* C[2] = { Emit(gimple_call_arg(stmt, 0), 0), Emit(gimple_call_arg(stmt, 1), 0) @@ -4967,7 +4970,9 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], + /*isSigned*/!TYPE_UNSIGNED(return_type), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -4995,7 +5000,8 @@ case BUILT_IN_NAND_AND_FETCH_1: case BUILT_IN_NAND_AND_FETCH_2: case BUILT_IN_NAND_AND_FETCH_4: { - const Type *ResultTy = ConvertType(gimple_call_return_type(stmt)); + tree return_type = gimple_call_return_type(stmt); + const Type *ResultTy = ConvertType(return_type); Value* C[2] = { Emit(gimple_call_arg(stmt, 0), 0), Emit(gimple_call_arg(stmt, 1), 0) @@ -5004,7 +5010,9 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], + /*isSigned*/!TYPE_UNSIGNED(return_type), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -5123,7 +5131,7 @@ Value *Val = Emit(gimple_call_arg(stmt, 0), 0); Value *Pow = Emit(gimple_call_arg(stmt, 1), 0); const Type *Ty = Val->getType(); - Pow = CastToSIntType(Pow, Type::getInt32Ty(Context)); + Pow = Builder.CreateIntCast(Pow, Type::getInt32Ty(Context), /*isSigned*/true); SmallVector Args; Args.push_back(Val); @@ -5288,7 +5296,8 @@ ReadWrite = 0; } else { ReadWrite = Builder.getFolder().CreateIntCast(cast(ReadWrite), - Type::getInt32Ty(Context), false); + Type::getInt32Ty(Context), + /*isSigned*/false); } if (gimple_call_num_args(stmt) > 2) { @@ -5301,7 +5310,8 @@ Locality = 0; } else { Locality = Builder.getFolder().CreateIntCast(cast(Locality), - Type::getInt32Ty(Context), false); + Type::getInt32Ty(Context), + /*isSigned*/false); } } } @@ -5472,7 +5482,7 @@ Intrinsic::ID IID = (IntPtr == Type::getInt32Ty(Context) ? Intrinsic::eh_return_i32 : Intrinsic::eh_return_i64); - Offset = Builder.CreateIntCast(Offset, IntPtr, true); + Offset = Builder.CreateIntCast(Offset, IntPtr, /*isSigned*/true); Handler = Builder.CreateBitCast(Handler, Type::getInt8PtrTy(Context)); SmallVector Args; @@ -5579,7 +5589,7 @@ if (!validate_gimple_arglist(stmt, INTEGER_TYPE, VOID_TYPE)) return false; Value *Amt = Emit(gimple_call_arg(stmt, 0), 0); - Amt = CastToSIntType(Amt, Type::getInt32Ty(Context)); + Amt = Builder.CreateIntCast(Amt, Type::getInt32Ty(Context), /*isSigned*/true); Result = Builder.CreateAlloca(Type::getInt8Ty(Context), Amt); return true; } @@ -5925,12 +5935,8 @@ ArrayAlign = ArrayAddrLV.getAlignment(); const Type *IntPtrTy = getTargetData().getIntPtrType(Context); - if (TYPE_UNSIGNED(IndexType)) // if the index is unsigned - // ZExt it to retain its value in the larger type - IndexVal = CastToUIntType(IndexVal, IntPtrTy); - else - // SExt it to retain its value in the larger type - IndexVal = CastToSIntType(IndexVal, IntPtrTy); + IndexVal = Builder.CreateIntCast(IndexVal, IntPtrTy, + /*isSigned*/!TYPE_UNSIGNED(IndexType)); // If we are indexing over a fixed-size type, just use a GEP. if (isSequentialCompatible(ArrayTreeType)) { @@ -5965,7 +5971,8 @@ assert(TREE_OPERAND(exp, 3) && "Size missing for variable sized element!"); // ScaleFactor is the size of the element type in units divided by (exactly) // TYPE_ALIGN_UNIT(ElementType). - Value *ScaleFactor = CastToUIntType(Emit(TREE_OPERAND(exp, 3), 0), IntPtrTy); + Value *ScaleFactor = Builder.CreateIntCast(Emit(TREE_OPERAND(exp, 3), 0), + IntPtrTy, /*isSigned*/false); assert(isPowerOf2_32(TYPE_ALIGN(ElementType)) && "Alignment not a power of two!"); assert(TYPE_ALIGN(ElementType) >= 8 && "Unit size not a multiple of 8 bits!"); @@ -8169,9 +8176,8 @@ ArrayAddr = EmitLV(Array); const Type *IntPtrTy = getTargetData().getIntPtrType(Context); - if (IndexVal->getType() != IntPtrTy) - IndexVal = TheFolder->CreateIntCast(IndexVal, IntPtrTy, - !TYPE_UNSIGNED(IndexType)); + IndexVal = TheFolder->CreateIntCast(IndexVal, IntPtrTy, + /*isSigned*/!TYPE_UNSIGNED(IndexType)); Value *Idx[2]; Idx[0] = ConstantInt::get(IntPtrTy, 0); Modified: dragonegg/trunk/x86/llvm-target.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/x86/llvm-target.cpp?rev=88903&r1=88902&r2=88903&view=diff ============================================================================== --- dragonegg/trunk/x86/llvm-target.cpp (original) +++ dragonegg/trunk/x86/llvm-target.cpp Mon Nov 16 03:18:55 2009 @@ -1104,13 +1104,15 @@ IX86_BUILTIN_VEC_INIT_V4HI: // Sometimes G++ promotes arguments to int. for (unsigned i = 0; i != 4; ++i) - Ops[i] = Builder.CreateIntCast(Ops[i], Type::getInt16Ty(Context), false); + Ops[i] = Builder.CreateIntCast(Ops[i], Type::getInt16Ty(Context), + /*isSigned*/false); Result = BuildVector(Ops[0], Ops[1], Ops[2], Ops[3], NULL); return true; IX86_BUILTIN_VEC_INIT_V8QI: // Sometimes G++ promotes arguments to int. for (unsigned i = 0; i != 8; ++i) - Ops[i] = Builder.CreateIntCast(Ops[i], Type::getInt8Ty(Context), false); + Ops[i] = Builder.CreateIntCast(Ops[i], Type::getInt8Ty(Context), + /*isSigned*/false); Result = BuildVector(Ops[0], Ops[1], Ops[2], Ops[3], Ops[4], Ops[5], Ops[6], Ops[7], NULL); return true; @@ -1126,13 +1128,15 @@ return true; IX86_BUILTIN_VEC_SET_V16QI: // Sometimes G++ promotes arguments to int. - Ops[1] = Builder.CreateIntCast(Ops[1], Type::getInt8Ty(Context), false); + Ops[1] = Builder.CreateIntCast(Ops[1], Type::getInt8Ty(Context), + /*isSigned*/false); Result = Builder.CreateInsertElement(Ops[0], Ops[1], Ops[2]); return true; IX86_BUILTIN_VEC_SET_V4HI: IX86_BUILTIN_VEC_SET_V8HI: // GCC sometimes doesn't produce the right element type. - Ops[1] = Builder.CreateIntCast(Ops[1], Type::getInt16Ty(Context), false); + Ops[1] = Builder.CreateIntCast(Ops[1], Type::getInt16Ty(Context), + /*isSigned*/false); Result = Builder.CreateInsertElement(Ops[0], Ops[1], Ops[2]); return true; IX86_BUILTIN_VEC_SET_V4SI: From echristo at apple.com Mon Nov 16 04:00:29 2009 From: echristo at apple.com (Eric Christopher) Date: Mon, 16 Nov 2009 02:00:29 -0800 Subject: [llvm-commits] [PATCH] Make X86-64 in the Large model always emit 64-bit calls In-Reply-To: References: <001636ed6e725660440478316be4@google.com> <0C21B7A2-76D2-48D4-8FE6-434AFC6FC5E1@apple.com> <072EB1A4-3A94-46BF-86CC-827F3F0E63E3@apple.com> Message-ID: On Nov 15, 2009, at 11:39 PM, Evan Cheng wrote: > > On Nov 15, 2009, at 8:28 PM, Eric Christopher wrote: > >>> >>> I'm trying for no far-stubs at all. :) With a unique stub for each >>> GlobalValue, the _stub_ can be more than 2GB away from the code using >>> it. And without either a unique stub or a bunch of work distinguishing >>> uses from address-of operations, &GV == address_of_GV() can be false. >> >> After we took this offline I think I figured out what the problem is. We still had a point where we were trying to tell llvm that we wanted a small code model instead of large. >> >> That said, there's still a problem: what if someone really does want small code model? Do we want to support that? If so, then we need to have some way of making small code model continue to work on x86-64. I do have an internal customer that we believe needs small code model. Unless the new way has no disadvantages over small? > > We can support small code model. So we should force large code model unless explicitly specified otherwise. > Yep. That's what we're doing now after Jeffrey's patch. > If the client wants small code model, the memory manager must be able to ensure that. OK. I'll see what I can do to make sure this is actually working. -eric From baldrick at free.fr Mon Nov 16 06:32:28 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 16 Nov 2009 12:32:28 -0000 Subject: [llvm-commits] [llvm] r88908 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Message-ID: <200911161232.nAGCWSeq016169@zion.cs.uiuc.edu> Author: baldrick Date: Mon Nov 16 06:32:28 2009 New Revision: 88908 URL: http://llvm.org/viewvc/llvm-project?rev=88908&view=rev Log: CreateIntCast takes an "isSigned" parameter. Pass "true" for it, rather than a name. Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=88908&r1=88907&r2=88908&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Mon Nov 16 06:32:28 2009 @@ -259,6 +259,7 @@ CallInst *CI = B.CreateCall(PutChar, B.CreateIntCast(Char, Type::getInt32Ty(*Context), + /*isSigned*/true, "chari"), "putchar"); @@ -303,7 +304,8 @@ Type::getInt32Ty(*Context), Type::getInt32Ty(*Context), File->getType(), NULL); - Char = B.CreateIntCast(Char, Type::getInt32Ty(*Context), "chari"); + Char = B.CreateIntCast(Char, Type::getInt32Ty(*Context), /*isSigned*/true, + "chari"); CallInst *CI = B.CreateCall2(F, Char, File, "fputc"); if (const Function *Fn = dyn_cast(F->stripPointerCasts())) From baldrick at free.fr Mon Nov 16 07:15:29 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 16 Nov 2009 13:15:29 -0000 Subject: [llvm-commits] [llvm] r88910 - /llvm/trunk/lib/VMCore/Core.cpp Message-ID: <200911161315.nAGDFTMi017583@zion.cs.uiuc.edu> Author: baldrick Date: Mon Nov 16 07:15:28 2009 New Revision: 88910 URL: http://llvm.org/viewvc/llvm-project?rev=88910&view=rev Log: BuildIntCast takes an additional parameter, isSigned. Modified: llvm/trunk/lib/VMCore/Core.cpp Modified: llvm/trunk/lib/VMCore/Core.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=88910&r1=88909&r2=88910&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Core.cpp (original) +++ llvm/trunk/lib/VMCore/Core.cpp Mon Nov 16 07:15:28 2009 @@ -1860,8 +1860,9 @@ } LLVMValueRef LLVMBuildIntCast(LLVMBuilderRef B, LLVMValueRef Val, - LLVMTypeRef DestTy, const char *Name) { - return wrap(unwrap(B)->CreateIntCast(unwrap(Val), unwrap(DestTy), Name)); + LLVMTypeRef DestTy, int isSigned, + const char *Name) { + return wrap(unwrap(B)->CreateIntCast(unwrap(Val), unwrap(DestTy), isSigned, Name)); } LLVMValueRef LLVMBuildFPCast(LLVMBuilderRef B, LLVMValueRef Val, From greened at obbligato.org Mon Nov 16 09:12:23 2009 From: greened at obbligato.org (David Greene) Date: Mon, 16 Nov 2009 15:12:23 -0000 Subject: [llvm-commits] [llvm] r88911 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/2009-09-10-SpillComments.ll Message-ID: <200911161512.nAGFCNWI021792@zion.cs.uiuc.edu> Author: greened Date: Mon Nov 16 09:12:23 2009 New Revision: 88911 URL: http://llvm.org/viewvc/llvm-project?rev=88911&view=rev Log: Support spill comments. Have the asm printer emit a comment if an instruction is a spill or reload and have the spiller mark copies it introdues so the asm printer can also annotate those. Added: llvm/trunk/test/CodeGen/X86/2009-09-10-SpillComments.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=88911&r1=88910&r2=88911&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon Nov 16 09:12:23 2009 @@ -1846,6 +1846,58 @@ Newline = true; } + // Check for spills and reloads + int FI; + + const MachineFrameInfo *FrameInfo = + MI.getParent()->getParent()->getFrameInfo(); + + // We assume a single instruction only has a spill or reload, not + // both. + if (TM.getInstrInfo()->isLoadFromStackSlotPostFE(&MI, FI)) { + if (FrameInfo->isSpillSlotObjectIndex(FI)) { + if (Newline) O << '\n'; + O.PadToColumn(MAI->getCommentColumn()); + O << MAI->getCommentString() << " Reload"; + Newline = true; + } + } + else if (TM.getInstrInfo()->hasLoadFromStackSlot(&MI, FI)) { + if (FrameInfo->isSpillSlotObjectIndex(FI)) { + if (Newline) O << '\n'; + O.PadToColumn(MAI->getCommentColumn()); + O << MAI->getCommentString() << " Folded Reload"; + Newline = true; + } + } + else if (TM.getInstrInfo()->isStoreToStackSlotPostFE(&MI, FI)) { + if (FrameInfo->isSpillSlotObjectIndex(FI)) { + if (Newline) O << '\n'; + O.PadToColumn(MAI->getCommentColumn()); + O << MAI->getCommentString() << " Spill"; + Newline = true; + } + } + else if (TM.getInstrInfo()->hasStoreToStackSlot(&MI, FI)) { + if (FrameInfo->isSpillSlotObjectIndex(FI)) { + if (Newline) O << '\n'; + O.PadToColumn(MAI->getCommentColumn()); + O << MAI->getCommentString() << " Folded Spill"; + Newline = true; + } + } + + // Check for spill-induced copies + unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; + if (TM.getInstrInfo()->isMoveInstr(MI, SrcReg, DstReg, + SrcSubIdx, DstSubIdx)) { + if (MI.getAsmPrinterFlag(ReloadReuse)) { + if (Newline) O << '\n'; + O.PadToColumn(MAI->getCommentColumn()); + O << MAI->getCommentString() << " Reload Reuse"; + Newline = true; + } + } } /// PrintChildLoopComment - Print comments about child loops within Added: llvm/trunk/test/CodeGen/X86/2009-09-10-SpillComments.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-09-10-SpillComments.ll?rev=88911&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-09-10-SpillComments.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-09-10-SpillComments.ll Mon Nov 16 09:12:23 2009 @@ -0,0 +1,105 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Spill" +; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Folded Spill" +; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Reload" +; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Reload Reuse" + + %struct..0anon = type { i32 } + %struct.rtvec_def = type { i32, [1 x %struct..0anon] } + %struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] } + at rtx_format = external global [116 x i8*] ; <[116 x i8*]*> [#uses=1] + at rtx_length = external global [117 x i32] ; <[117 x i32]*> [#uses=1] + +declare %struct.rtx_def* @fixup_memory_subreg(%struct.rtx_def*, %struct.rtx_def*, i32) + +define %struct.rtx_def* @walk_fixup_memory_subreg(%struct.rtx_def* %x, %struct.rtx_def* %insn) { +entry: + %tmp2 = icmp eq %struct.rtx_def* %x, null ; [#uses=1] + br i1 %tmp2, label %UnifiedReturnBlock, label %cond_next + +cond_next: ; preds = %entry + %tmp6 = getelementptr %struct.rtx_def* %x, i32 0, i32 0 ; [#uses=1] + %tmp7 = load i16* %tmp6 ; [#uses=2] + %tmp78 = zext i16 %tmp7 to i32 ; [#uses=2] + %tmp10 = icmp eq i16 %tmp7, 54 ; [#uses=1] + br i1 %tmp10, label %cond_true13, label %cond_next32 + +cond_true13: ; preds = %cond_next + %tmp15 = getelementptr %struct.rtx_def* %x, i32 0, i32 3 ; <[1 x %struct..0anon]*> [#uses=1] + %tmp1718 = bitcast [1 x %struct..0anon]* %tmp15 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=1] + %tmp19 = load %struct.rtx_def** %tmp1718 ; <%struct.rtx_def*> [#uses=1] + %tmp20 = getelementptr %struct.rtx_def* %tmp19, i32 0, i32 0 ; [#uses=1] + %tmp21 = load i16* %tmp20 ; [#uses=1] + %tmp22 = icmp eq i16 %tmp21, 57 ; [#uses=1] + br i1 %tmp22, label %cond_true25, label %cond_next32 + +cond_true25: ; preds = %cond_true13 + %tmp29 = tail call %struct.rtx_def* @fixup_memory_subreg( %struct.rtx_def* %x, %struct.rtx_def* %insn, i32 1 ) ; <%struct.rtx_def*> [#uses=1] + ret %struct.rtx_def* %tmp29 + +cond_next32: ; preds = %cond_true13, %cond_next + %tmp34 = getelementptr [116 x i8*]* @rtx_format, i32 0, i32 %tmp78 ; [#uses=1] + %tmp35 = load i8** %tmp34, align 4 ; [#uses=1] + %tmp37 = getelementptr [117 x i32]* @rtx_length, i32 0, i32 %tmp78 ; [#uses=1] + %tmp38 = load i32* %tmp37, align 4 ; [#uses=1] + %i.011 = add i32 %tmp38, -1 ; [#uses=2] + %tmp12513 = icmp sgt i32 %i.011, -1 ; [#uses=1] + br i1 %tmp12513, label %bb, label %UnifiedReturnBlock + +bb: ; preds = %bb123, %cond_next32 + %indvar = phi i32 [ %indvar.next26, %bb123 ], [ 0, %cond_next32 ] ; [#uses=2] + %i.01.0 = sub i32 %i.011, %indvar ; [#uses=5] + %tmp42 = getelementptr i8* %tmp35, i32 %i.01.0 ; [#uses=2] + %tmp43 = load i8* %tmp42 ; [#uses=1] + switch i8 %tmp43, label %bb123 [ + i8 101, label %cond_true47 + i8 69, label %bb105.preheader + ] + +cond_true47: ; preds = %bb + %tmp52 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0 ; <%struct..0anon*> [#uses=1] + %tmp5354 = bitcast %struct..0anon* %tmp52 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=1] + %tmp55 = load %struct.rtx_def** %tmp5354 ; <%struct.rtx_def*> [#uses=1] + %tmp58 = tail call %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp55, %struct.rtx_def* %insn ) ; <%struct.rtx_def*> [#uses=1] + %tmp62 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0, i32 0 ; [#uses=1] + %tmp58.c = ptrtoint %struct.rtx_def* %tmp58 to i32 ; [#uses=1] + store i32 %tmp58.c, i32* %tmp62 + %tmp6816 = load i8* %tmp42 ; [#uses=1] + %tmp6917 = icmp eq i8 %tmp6816, 69 ; [#uses=1] + br i1 %tmp6917, label %bb105.preheader, label %bb123 + +bb105.preheader: ; preds = %cond_true47, %bb + %tmp11020 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0 ; <%struct..0anon*> [#uses=1] + %tmp11111221 = bitcast %struct..0anon* %tmp11020 to %struct.rtvec_def** ; <%struct.rtvec_def**> [#uses=3] + %tmp11322 = load %struct.rtvec_def** %tmp11111221 ; <%struct.rtvec_def*> [#uses=1] + %tmp11423 = getelementptr %struct.rtvec_def* %tmp11322, i32 0, i32 0 ; [#uses=1] + %tmp11524 = load i32* %tmp11423 ; [#uses=1] + %tmp11625 = icmp eq i32 %tmp11524, 0 ; [#uses=1] + br i1 %tmp11625, label %bb123, label %bb73 + +bb73: ; preds = %bb73, %bb105.preheader + %j.019 = phi i32 [ %tmp104, %bb73 ], [ 0, %bb105.preheader ] ; [#uses=3] + %tmp81 = load %struct.rtvec_def** %tmp11111221 ; <%struct.rtvec_def*> [#uses=2] + %tmp92 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019 ; <%struct..0anon*> [#uses=1] + %tmp9394 = bitcast %struct..0anon* %tmp92 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=1] + %tmp95 = load %struct.rtx_def** %tmp9394 ; <%struct.rtx_def*> [#uses=1] + %tmp98 = tail call %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp95, %struct.rtx_def* %insn ) ; <%struct.rtx_def*> [#uses=1] + %tmp101 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019, i32 0 ; [#uses=1] + %tmp98.c = ptrtoint %struct.rtx_def* %tmp98 to i32 ; [#uses=1] + store i32 %tmp98.c, i32* %tmp101 + %tmp104 = add i32 %j.019, 1 ; [#uses=2] + %tmp113 = load %struct.rtvec_def** %tmp11111221 ; <%struct.rtvec_def*> [#uses=1] + %tmp114 = getelementptr %struct.rtvec_def* %tmp113, i32 0, i32 0 ; [#uses=1] + %tmp115 = load i32* %tmp114 ; [#uses=1] + %tmp116 = icmp ult i32 %tmp104, %tmp115 ; [#uses=1] + br i1 %tmp116, label %bb73, label %bb123 + +bb123: ; preds = %bb73, %bb105.preheader, %cond_true47, %bb + %i.0 = add i32 %i.01.0, -1 ; [#uses=1] + %tmp125 = icmp sgt i32 %i.0, -1 ; [#uses=1] + %indvar.next26 = add i32 %indvar, 1 ; [#uses=1] + br i1 %tmp125, label %bb, label %UnifiedReturnBlock + +UnifiedReturnBlock: ; preds = %bb123, %cond_next32, %entry + %UnifiedRetVal = phi %struct.rtx_def* [ null, %entry ], [ %x, %cond_next32 ], [ %x, %bb123 ] ; <%struct.rtx_def*> [#uses=1] + ret %struct.rtx_def* %UnifiedRetVal +} From dag at cray.com Mon Nov 16 09:17:09 2009 From: dag at cray.com (David Greene) Date: Mon, 16 Nov 2009 09:17:09 -0600 Subject: [llvm-commits] [llvm] r88902 - /llvm/trunk/lib/VMCore/AsmWriter.cpp In-Reply-To: <200911160710.nAG7Aa2W023263@zion.cs.uiuc.edu> References: <200911160710.nAG7Aa2W023263@zion.cs.uiuc.edu> Message-ID: <200911160917.10088.dag@cray.com> On Monday 16 November 2009 01:10, Evan Cheng wrote: > Author: evancheng > Date: Mon Nov 16 01:10:36 2009 > New Revision: 88902 > > URL: http://llvm.org/viewvc/llvm-project?rev=88902&view=rev > Log: > Special case FixedStackPseudoSourceValueVal as well. Do we really need to > differentiate PseudoSourceValueVal from FixedStackPseudoSourceValueVal at > this level? Yes. The asm printer uses it to emit comments about spills. -Dave From baldrick at free.fr Mon Nov 16 09:26:02 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 16 Nov 2009 15:26:02 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r88912 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200911161526.nAGFQ20Z022362@zion.cs.uiuc.edu> Author: baldrick Date: Mon Nov 16 09:26:02 2009 New Revision: 88912 URL: http://llvm.org/viewvc/llvm-project?rev=88912&view=rev Log: Don't pass the name as the isSigned parameter to CreateIntCast. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=88912&r1=88911&r2=88912&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Nov 16 09:26:02 2009 @@ -4765,7 +4765,8 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. EmitMemoryBarrier(true, true, true, true); @@ -4790,8 +4791,10 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); - C[2] = Builder.CreateIntCast(C[2], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); + C[2] = Builder.CreateIntCast(C[2], Ty[0], !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -4940,7 +4943,8 @@ // Manually coerce the arg to the correct pointer type. Args[0] = Builder.CreateBitCast(Args[0], Type::getInt8PtrTy(Context)); - Args[1] = Builder.CreateIntCast(Args[1], Type::getInt32Ty(Context), false); + Args[1] = Builder.CreateIntCast(Args[1], Type::getInt32Ty(Context), + false); Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::objectsize, @@ -4958,7 +4962,8 @@ Value *Amt = Emit(TREE_VALUE(TREE_OPERAND(exp, 1)), 0); EmitBuiltinUnaryOp(Amt, Result, Intrinsic::ctlz); const Type *DestTy = ConvertType(TREE_TYPE(exp)); - Result = Builder.CreateIntCast(Result, DestTy, "cast"); + Result = Builder.CreateIntCast(Result, DestTy, !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); return true; } case BUILT_IN_CTZ: // These GCC builtins always return int. @@ -4967,7 +4972,8 @@ Value *Amt = Emit(TREE_VALUE(TREE_OPERAND(exp, 1)), 0); EmitBuiltinUnaryOp(Amt, Result, Intrinsic::cttz); const Type *DestTy = ConvertType(TREE_TYPE(exp)); - Result = Builder.CreateIntCast(Result, DestTy, "cast"); + Result = Builder.CreateIntCast(Result, DestTy, !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); return true; } case BUILT_IN_PARITYLL: @@ -4985,7 +4991,8 @@ Value *Amt = Emit(TREE_VALUE(TREE_OPERAND(exp, 1)), 0); EmitBuiltinUnaryOp(Amt, Result, Intrinsic::ctpop); const Type *DestTy = ConvertType(TREE_TYPE(exp)); - Result = Builder.CreateIntCast(Result, DestTy, "cast"); + Result = Builder.CreateIntCast(Result, DestTy, !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); return true; } case BUILT_IN_BSWAP32: @@ -4993,7 +5000,8 @@ Value *Amt = Emit(TREE_VALUE(TREE_OPERAND(exp, 1)), 0); EmitBuiltinUnaryOp(Amt, Result, Intrinsic::bswap); const Type *DestTy = ConvertType(TREE_TYPE(exp)); - Result = Builder.CreateIntCast(Result, DestTy, "cast"); + Result = Builder.CreateIntCast(Result, DestTy, !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); return true; } @@ -5287,7 +5295,8 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -5325,7 +5334,8 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -5363,7 +5373,8 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -5401,7 +5412,8 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -5439,7 +5451,8 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. @@ -5477,7 +5490,8 @@ Ty[0] = ResultTy; Ty[1] = ResultTy->getPointerTo(); C[0] = Builder.CreateBitCast(C[0], Ty[1]); - C[1] = Builder.CreateIntCast(C[1], Ty[0], "cast"); + C[1] = Builder.CreateIntCast(C[1], Ty[0], !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. From baldrick at free.fr Mon Nov 16 09:28:18 2009 From: baldrick at free.fr (Duncan Sands) Date: Mon, 16 Nov 2009 15:28:18 -0000 Subject: [llvm-commits] [llvm] r88913 - in /llvm/trunk/include/llvm/Support: Compiler.h IRBuilder.h Message-ID: <200911161528.nAGFSIpF022448@zion.cs.uiuc.edu> Author: baldrick Date: Mon Nov 16 09:28:17 2009 New Revision: 88913 URL: http://llvm.org/viewvc/llvm-project?rev=88913&view=rev Log: Make sure that if anyone passes a name by accident for the isSigned parameter of CreateIntCast then they get an error from the compiler (or from the linker with a non-gcc compiler). Another possibility is to flip the order of the DestTy and isSigned parameters, since you should then get a compiler warning if you try to use a char* for a Type*. Modified: llvm/trunk/include/llvm/Support/Compiler.h llvm/trunk/include/llvm/Support/IRBuilder.h Modified: llvm/trunk/include/llvm/Support/Compiler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Compiler.h?rev=88913&r1=88912&r2=88913&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Compiler.h (original) +++ llvm/trunk/include/llvm/Support/Compiler.h Mon Nov 16 09:28:17 2009 @@ -78,4 +78,10 @@ #define NORETURN #endif +#ifdef __GNUC__ +#define ERROR_IF_USED __attribute__((error("wrong usage"))) +#else +#define ERROR_IF_USED +#endif + #endif Modified: llvm/trunk/include/llvm/Support/IRBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=88913&r1=88912&r2=88913&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) +++ llvm/trunk/include/llvm/Support/IRBuilder.h Mon Nov 16 09:28:17 2009 @@ -709,6 +709,9 @@ return Folder.CreateIntCast(VC, DestTy, isSigned); return Insert(CastInst::CreateIntegerCast(V, DestTy, isSigned), Name); } + // Provided to resolve 'CreateIntCast(Ptr, Ptr, "...")', instead of converting + // the string to 'bool' for the isSigned parameter. + ERROR_IF_USED Value *CreateIntCast(Value *, const Type *, const char *); Value *CreateFPCast(Value *V, const Type *DestTy, const Twine &Name = "") { if (V->getType() == DestTy) return V; From dgregor at apple.com Mon Nov 16 10:28:56 2009 From: dgregor at apple.com (Douglas Gregor) Date: Mon, 16 Nov 2009 08:28:56 -0800 Subject: [llvm-commits] [llvm] r88913 - in /llvm/trunk/include/llvm/Support: Compiler.h IRBuilder.h In-Reply-To: <200911161528.nAGFSIpF022448@zion.cs.uiuc.edu> References: <200911161528.nAGFSIpF022448@zion.cs.uiuc.edu> Message-ID: <93852A99-2499-4D9E-80CC-4E6035D72F0C@apple.com> On Nov 16, 2009, at 7:28 AM, Duncan Sands wrote: > Author: baldrick > Date: Mon Nov 16 09:28:17 2009 > New Revision: 88913 > > URL: http://llvm.org/viewvc/llvm-project?rev=88913&view=rev > Log: > Make sure that if anyone passes a name by accident for the isSigned > parameter of CreateIntCast then they get an error from the compiler > (or from the linker with a non-gcc compiler). Another possibility > is to flip the order of the DestTy and isSigned parameters, since you > should then get a compiler warning if you try to use a char* for a > Type*. > > Modified: > llvm/trunk/include/llvm/Support/Compiler.h > llvm/trunk/include/llvm/Support/IRBuilder.h > > Modified: llvm/trunk/include/llvm/Support/Compiler.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Compiler.h?rev=88913&r1=88912&r2=88913&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Support/Compiler.h (original) > +++ llvm/trunk/include/llvm/Support/Compiler.h Mon Nov 16 09:28:17 > 2009 > @@ -78,4 +78,10 @@ > #define NORETURN > #endif > > +#ifdef __GNUC__ > +#define ERROR_IF_USED __attribute__((error("wrong usage"))) > +#else > +#define ERROR_IF_USED > +#endif > + > #endif I'm getting a bunch of warnings now, since the "error" attribute is only available on GCC >= 4.3. Patch coming to conditionalize this more appropriately... - Doug -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091116/1ee2775e/attachment.html From dgregor at apple.com Mon Nov 16 10:56:48 2009 From: dgregor at apple.com (Douglas Gregor) Date: Mon, 16 Nov 2009 16:56:48 -0000 Subject: [llvm-commits] [llvm] r88916 - /llvm/trunk/include/llvm/Support/Compiler.h Message-ID: <200911161656.nAGGumPg025644@zion.cs.uiuc.edu> Author: dgregor Date: Mon Nov 16 10:56:48 2009 New Revision: 88916 URL: http://llvm.org/viewvc/llvm-project?rev=88916&view=rev Log: Make ERROR_IF_USED macro work with GCC <= 4.2, Apple GCCs Modified: llvm/trunk/include/llvm/Support/Compiler.h Modified: llvm/trunk/include/llvm/Support/Compiler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Compiler.h?rev=88916&r1=88915&r2=88916&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Compiler.h (original) +++ llvm/trunk/include/llvm/Support/Compiler.h Mon Nov 16 10:56:48 2009 @@ -78,8 +78,10 @@ #define NORETURN #endif -#ifdef __GNUC__ +#if defined(__GNUC__) && ((__GNUC__ > 4)||(__GNUC__ == 4 && __GNUC_MINOR__ > 2)) #define ERROR_IF_USED __attribute__((error("wrong usage"))) +#elif defined(__APPLE__) +#define ERROR_IF_USED __attribute__((unavailable)) #else #define ERROR_IF_USED #endif From grosbach at apple.com Mon Nov 16 11:10:56 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 Nov 2009 17:10:56 -0000 Subject: [llvm-commits] [llvm] r88917 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <200911161710.nAGHAush026257@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 11:10:56 2009 New Revision: 88917 URL: http://llvm.org/viewvc/llvm-project?rev=88917&view=rev Log: Analyze has to be before checking the condition, obviously. Properly construct an iterator for prior. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=88917&r1=88916&r2=88917&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Mon Nov 16 11:10:56 2009 @@ -1772,13 +1772,15 @@ int Size = BBSizes[BBI]; MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; - // If the block is small and ends in an unconditional branch, move it. - if (Size < 50 && Cond.empty()) { - // If the block terminator isn't analyzable, don't try to move the block - if (TII->AnalyzeBranch(*BB, TBB, FBB, Cond)) - return NULL; - MachineFunction::iterator OldPrior = prior(BB); + // If the block terminator isn't analyzable, don't try to move the block + if (TII->AnalyzeBranch(*BB, TBB, FBB, Cond)) + return NULL; + + // If the block is small and ends in an unconditional branch, move it. + if (Size < 50 && Cond.empty() && BB != MF.begin()) { + MachineFunction::iterator BBi = BB; + MachineFunction::iterator OldPrior = prior(BBi); BB->moveAfter(JTBB); OldPrior->updateTerminator(); BB->updateTerminator(); From grosbach at apple.com Mon Nov 16 11:17:48 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 Nov 2009 17:17:48 -0000 Subject: [llvm-commits] [llvm] r88919 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <200911161717.nAGHHmVr026511@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 11:17:48 2009 New Revision: 88919 URL: http://llvm.org/viewvc/llvm-project?rev=88919&view=rev Log: back off for a bit. tracking down weirdness Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=88919&r1=88918&r2=88919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Mon Nov 16 11:17:48 2009 @@ -48,7 +48,7 @@ static cl::opt -AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(true), +AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(false), cl::desc("Adjust basic block layout to better use TB[BH]")); namespace { From grosbach at apple.com Mon Nov 16 11:24:45 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 Nov 2009 17:24:45 -0000 Subject: [llvm-commits] [llvm] r88921 - /llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll Message-ID: <200911161724.nAGHOjpY026824@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 11:24:45 2009 New Revision: 88921 URL: http://llvm.org/viewvc/llvm-project?rev=88921&view=rev Log: tbb opt off by default Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll?rev=88921&r1=88920&r2=88921&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll Mon Nov 16 11:24:45 2009 @@ -1,6 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s ; Thumb2 target should reorder the bb's in order to use tbb / tbh. +; XFAIL: * %struct.R_flstr = type { i32, i32, i8* } %struct._T_tstr = type { i32, %struct.R_flstr*, %struct._T_tstr* } From stoklund at 2pi.dk Mon Nov 16 11:24:57 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 16 Nov 2009 09:24:57 -0800 Subject: [llvm-commits] [llvm] r88911 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/2009-09-10-SpillComments.ll In-Reply-To: <200911161512.nAGFCNWI021792@zion.cs.uiuc.edu> References: <200911161512.nAGFCNWI021792@zion.cs.uiuc.edu> Message-ID: <3EB16C9B-912F-47B0-BB28-3584DF7DAF3D@2pi.dk> On Nov 16, 2009, at 7:12 AM, David Greene wrote: > --- llvm/trunk/test/CodeGen/X86/2009-09-10-SpillComments.ll (added) > +++ llvm/trunk/test/CodeGen/X86/2009-09-10-SpillComments.ll Mon Nov 16 09:12:23 2009 > @@ -0,0 +1,105 @@ > +; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Spill" > +; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Folded Spill" > +; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Reload" > +; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Reload Reuse" Please use FileCheck for tests like this. /jakob From bob.wilson at apple.com Mon Nov 16 11:56:14 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 16 Nov 2009 17:56:14 -0000 Subject: [llvm-commits] [llvm] r88927 - /llvm/trunk/lib/CodeGen/BranchFolding.cpp Message-ID: <200911161756.nAGHuEGB027958@zion.cs.uiuc.edu> Author: bwilson Date: Mon Nov 16 11:56:13 2009 New Revision: 88927 URL: http://llvm.org/viewvc/llvm-project?rev=88927&view=rev Log: Clean up whitespace. Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=88927&r1=88926&r2=88927&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Mon Nov 16 11:56:13 2009 @@ -52,7 +52,7 @@ // Heuristic for tail merging (and, inversely, tail duplication). // TODO: This should be replaced with a target query. static cl::opt -TailMergeSize("tail-merge-size", +TailMergeSize("tail-merge-size", cl::desc("Min number of instructions to consider tail merging"), cl::init(3), cl::Hidden); @@ -522,7 +522,7 @@ // count that as an additional common instruction for the following // heuristics. unsigned EffectiveTailLen = CommonTailLen; - if (SuccBB && MBB1 != PredBB && MBB2 != PredBB && + if (SuccBB && MBB1 != PredBB && MBB2 != PredBB && !MBB1->back().getDesc().isBarrier() && !MBB2->back().getDesc().isBarrier()) ++EffectiveTailLen; @@ -970,7 +970,7 @@ if (BranchUnAnalyzable) return CurBB->empty() || !CurBB->back().getDesc().isBarrier() || CurBB->back().getDesc().isPredicable(); - + // If there is no branch, control always falls through. if (TBB == 0) return true; @@ -1043,7 +1043,7 @@ // get into an infinite loop between duplicating and merging. When optimizing // for size, duplicate only one, because one branch instruction can be // eliminated to compensate for the duplication. - unsigned MaxDuplicateCount = + unsigned MaxDuplicateCount = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) ? 1 : (TailMergeSize - 1); @@ -1201,7 +1201,7 @@ MadeChange = true; return MadeChange; } - + // If the previous branch *only* branches to *this* block (conditional or // not) remove the branch. if (PriorTBB == MBB && PriorFBB == 0) { @@ -1401,7 +1401,7 @@ // Now we know that there was no fall-through into this block, check to // see if it has a fall-through into its successor. - bool CurFallsThru = CanFallThrough(MBB, CurUnAnalyzable, CurTBB, CurFBB, + bool CurFallsThru = CanFallThrough(MBB, CurUnAnalyzable, CurTBB, CurFBB, CurCond); bool PrevFallsThru = CanFallThrough(&PrevBB, PriorUnAnalyzable, PriorTBB, PriorFBB, PriorCond); From bob.wilson at apple.com Mon Nov 16 12:08:47 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 16 Nov 2009 18:08:47 -0000 Subject: [llvm-commits] [llvm] r88929 - /llvm/trunk/lib/CodeGen/BranchFolding.cpp Message-ID: <200911161808.nAGI8lJV028436@zion.cs.uiuc.edu> Author: bwilson Date: Mon Nov 16 12:08:46 2009 New Revision: 88929 URL: http://llvm.org/viewvc/llvm-project?rev=88929&view=rev Log: Whitespace: be consistent with pointer syntax. Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=88929&r1=88928&r2=88929&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Mon Nov 16 12:08:46 2009 @@ -423,7 +423,7 @@ // branches temporarily for tail merging). In the case where CurMBB ends // with a conditional branch to the next block, optimize by reversing the // test and conditionally branching to SuccMBB instead. -static void FixTail(MachineBasicBlock* CurMBB, MachineBasicBlock *SuccBB, +static void FixTail(MachineBasicBlock *CurMBB, MachineBasicBlock *SuccBB, const TargetInstrInfo *TII) { MachineFunction *MF = CurMBB->getParent(); MachineFunction::iterator I = next(MachineFunction::iterator(CurMBB)); @@ -591,8 +591,8 @@ /// RemoveBlocksWithHash - Remove all blocks with hash CurHash from /// MergePotentials, restoring branches at ends of blocks as appropriate. void BranchFolder::RemoveBlocksWithHash(unsigned CurHash, - MachineBasicBlock* SuccBB, - MachineBasicBlock* PredBB) { + MachineBasicBlock *SuccBB, + MachineBasicBlock *PredBB) { MPIterator CurMPIter, B; for (CurMPIter = prior(MergePotentials.end()), B = MergePotentials.begin(); CurMPIter->getHash() == CurHash; @@ -658,7 +658,7 @@ // if any, is given in PredBB. bool BranchFolder::TryTailMergeBlocks(MachineBasicBlock *SuccBB, - MachineBasicBlock* PredBB) { + MachineBasicBlock *PredBB) { bool MadeChange = false; // Except for the special cases below, tail-merge if there are at least @@ -847,7 +847,7 @@ for (MachineBasicBlock::pred_iterator P = I->pred_begin(), E2 = I->pred_end(); P != E2; ++P) { - MachineBasicBlock* PBB = *P; + MachineBasicBlock *PBB = *P; // Skip blocks that loop to themselves, can't tail merge these. if (PBB == IBB) continue; @@ -872,7 +872,7 @@ // to have a bit in the edge so we didn't have to do all this. if (IBB->isLandingPad()) { MachineFunction::iterator IP = PBB; IP++; - MachineBasicBlock* PredNextBB = NULL; + MachineBasicBlock *PredNextBB = NULL; if (IP != MF.end()) PredNextBB = IP; if (TBB == NULL) { From grosbach at apple.com Mon Nov 16 12:46:16 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 Nov 2009 10:46:16 -0800 Subject: [llvm-commits] [llvm] r88805 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp In-Reply-To: References: <200911142010.nAEKAIMp014778@zion.cs.uiuc.edu> Message-ID: <88F90AB9-C83A-4B4C-BF9F-484730623813@apple.com> On Nov 15, 2009, at 10:44 PM, Evan Cheng wrote: > Hi Jim, > > Some comments for 86999 and friends: > > /// ReorderThumb2JumpTables - Use tbb / tbh instructions to generate > smaller > /// jumptables when it's possible. > bool ARMConstantIslands::ReorderThumb2JumpTables(MachineFunction > &MF) { > > This comment is misleading. tbb / tbh are formed later, right? Yes. Excellent point. I'll clean that up. > > + // FIXME: If it's a small block terminated by an unconditional > branch, > + // try to move it; otherwise, create a new block following the jump > + // table that branches back to the actual target. This is an overly > + // simplistic heuristic here for proof-of-concept. > > What do you plan as a replacement? Jump + jump seems bad for > performance? Why not just add a unconditional branch to replace the > fall through? When we can't use a table branch instruction, we generate a jump table of branch instructions, so we have a jump+jump in that case. If we use the new fall-back situation of inserting a new jump block, then use the table branch instruction, we've not added any additional jumps for that branch target. For any forward targets of the same jump table, however, the second branch has been removed and performance will improve (this is where I suspect a good portion of our 8% gain on JSC is coming from). For example, when not using TBB, we generate code like: adr.w r2, #LJTI1_0_0 add.w r2, r2, r1, lsl #2 mov pc, r2 LJTI1_0_0: b.w LBB1_5 b.w LBB1_19 b.w LBB1_19 b.w LBB1_1 b.w LBB1_1 b.w LBB1_7 b.w LBB1_19 b.w LBB1_19 b.w LBB1_6 If we move things around and insert back-jump blocks as necessary, we get something like: tbb [pc, r1] LJTI1_0_0: .byte (LBB1_18-LJTI1_0_0)/2 .byte (LBB1_20-LJTI1_0_0)/2 .byte (LBB1_20-LJTI1_0_0)/2 .byte (LBB1_17-LJTI1_0_0)/2 .byte (LBB1_17-LJTI1_0_0)/2 .byte (LBB1_16-LJTI1_0_0)/2 .byte (LBB1_20-LJTI1_0_0)/2 .byte (LBB1_20-LJTI1_0_0)/2 .byte (LBB1_15-LJTI1_0_0)/2 In this case, LBB1_1 was unable to be moved, but the rest were relocated foward. From -stats: 3 arm-cp-islands - Number of jump table destination blocks moved 1 arm-cp-islands - Number of jump table intermediate blocks inserted Thus, for LBB_1, the performance is comparable before and after (slightly better since the adr.w and add.w instructions are no longer needed). For all other cases, the performance is significantly improved due to the direct dispatch from the TBB instruction instead of going through the secondary B.W in the table. > > + // If the block is small and ends in an unconditional branch, > move it. > + if (Size < 50 && Cond.empty()) > > Where is 50 coming from? It's entirely arbitrary. I don't believe any size restriction is necessary, really. This was just to help get a mix of cases where the blocks were moved vs. when they weren't for test coverage. I'll be removing that bit shortly, which will also greatly simplify the side data structures needed (no need to track block sizes and offsets). -Jim > > Evan > > On Nov 14, 2009, at 12:10 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Sat Nov 14 14:10:18 2009 >> New Revision: 88805 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=88805&view=rev >> Log: >> Cleanup flow, and only update the jump table we're analyzing when >> replacing a destination MBB. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp >> >> Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=88805&r1=88804&r2=88805&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Sat Nov 14 >> 14:10:18 2009 >> @@ -1749,7 +1749,7 @@ >> MachineBasicBlock *NewBB = >> AdjustJTTargetBlockForward(MBB, MI->getParent()); >> if (NewBB) >> - MJTI->ReplaceMBBInJumpTables(JTBBs[j], NewBB); >> + MJTI->ReplaceMBBInJumpTable(JTI, JTBBs[j], NewBB); >> MadeChange = true; >> } >> } >> @@ -1772,16 +1772,16 @@ >> int Size = BBSizes[BBI]; >> MachineBasicBlock *TBB = 0, *FBB = 0; >> SmallVector Cond; >> - // If the block terminator isn't analyzable, don't try to move >> the block >> - if (TII->AnalyzeBranch(*BB, TBB, FBB, Cond)) >> - return NULL; >> - >> // If the block is small and ends in an unconditional branch, move >> it. >> if (Size < 50 && Cond.empty()) { >> + // If the block terminator isn't analyzable, don't try to move >> the block >> + if (TII->AnalyzeBranch(*BB, TBB, FBB, Cond)) >> + return NULL; >> + >> MachineFunction::iterator OldPrior = prior(BB); >> BB->moveAfter(JTBB); >> OldPrior->updateTerminator(); >> - //BB->updateTerminator(); >> + BB->updateTerminator(); >> ++NumJTMoved; >> return NULL; >> } >> @@ -1792,20 +1792,22 @@ >> MachineFunction::iterator MBBI = JTBB; ++MBBI; >> MF.insert(MBBI, NewBB); >> >> + //MF.splice(MBBI, NewBB, NewBB); >> + >> // Add an unconditional branch from NewBB to BB. >> // There doesn't seem to be meaningful DebugInfo available; this >> doesn't >> // correspond directly to anything in the source. >> assert (isThumb2 && "Adjusting for TB[BH] but not in Thumb2?"); >> BuildMI(NewBB, DebugLoc::getUnknownLoc(), TII->get >> (ARM::t2B)).addMBB(BB); >> >> + // Update internal data structures to account for the newly >> inserted MBB. >> + MF.RenumberBlocks(NewBB); >> + >> // Update the CFG. >> NewBB->addSuccessor(BB); >> JTBB->removeSuccessor(BB); >> JTBB->addSuccessor(NewBB); >> >> - // Update internal data structures to account for the newly >> inserted MBB. >> - MF.RenumberBlocks(); >> - >> // Insert a size into BBSizes to align it properly with the (newly >> // renumbered) block numbers. >> BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0); >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From bob.wilson at apple.com Mon Nov 16 12:54:08 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 16 Nov 2009 18:54:08 -0000 Subject: [llvm-commits] [llvm] r88932 - /llvm/trunk/lib/CodeGen/BranchFolding.cpp Message-ID: <200911161854.nAGIs8S5030697@zion.cs.uiuc.edu> Author: bwilson Date: Mon Nov 16 12:54:08 2009 New Revision: 88932 URL: http://llvm.org/viewvc/llvm-project?rev=88932&view=rev Log: Fix some comments. Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=88932&r1=88931&r2=88932&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Mon Nov 16 12:54:08 2009 @@ -1025,8 +1025,8 @@ return MBB2I->getDesc().isCall() && !MBB1I->getDesc().isCall(); } -/// TailDuplicate - MBB unconditionally branches to SuccBB. If it is profitable, -/// duplicate SuccBB's contents in MBB to eliminate the branch. +/// TailDuplicate - If it is profitable, duplicate TailBB's contents in each +/// of its predecessors. bool BranchFolder::TailDuplicate(MachineBasicBlock *TailBB, bool PrevFallsThrough, MachineFunction &MF) { @@ -1048,7 +1048,7 @@ 1 : (TailMergeSize - 1); // Check the instructions in the block to determine whether tail-duplication - // is invalid or unlikely to be unprofitable. + // is invalid or unlikely to be profitable. unsigned i = 0; bool HasCall = false; for (MachineBasicBlock::iterator I = TailBB->begin(); @@ -1088,7 +1088,7 @@ // EH edges are ignored by AnalyzeBranch. if (PredBB->succ_size() != 1) continue; - // Don't duplicate into a fall-through predecessor unless its the + // Don't duplicate into a fall-through predecessor unless it's the // only predecessor. if (PredBB->isLayoutSuccessor(TailBB) && PrevFallsThrough && @@ -1317,7 +1317,6 @@ } } - // If this branch is the only thing in its block, see if we can forward // other blocks across it. if (CurTBB && CurCond.empty() && CurFBB == 0 && From grosbach at apple.com Mon Nov 16 12:55:48 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 Nov 2009 18:55:48 -0000 Subject: [llvm-commits] [llvm] r88933 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <200911161855.nAGItmpS030830@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 12:55:47 2009 New Revision: 88933 URL: http://llvm.org/viewvc/llvm-project?rev=88933&view=rev Log: clarify comment Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=88933&r1=88932&r2=88933&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Mon Nov 16 12:55:47 2009 @@ -1718,8 +1718,8 @@ return MadeChange; } -/// ReorderThumb2JumpTables - Use tbb / tbh instructions to generate smaller -/// jumptables when it's possible. +/// ReorderThumb2JumpTables - Adjust the function's block layout to ensure that +/// jump tables always branch forwards, since that's what tbb and tbh need. bool ARMConstantIslands::ReorderThumb2JumpTables(MachineFunction &MF) { bool MadeChange = false; From grosbach at apple.com Mon Nov 16 12:58:52 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 Nov 2009 18:58:52 -0000 Subject: [llvm-commits] [llvm] r88935 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <200911161858.nAGIwqRs031075@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 12:58:52 2009 New Revision: 88935 URL: http://llvm.org/viewvc/llvm-project?rev=88935&view=rev Log: Simplify thumb2 jump table adjustments. Remove unnecessary calculation and usage of block sizes and offsets. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=88935&r1=88934&r2=88935&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Mon Nov 16 12:58:52 2009 @@ -281,8 +281,6 @@ JumpTableFunctionScan(MF); MadeChange |= ReorderThumb2JumpTables(MF); // Data is out of date, so clear it. It'll be re-computed later. - BBSizes.clear(); - BBOffsets.clear(); T2JumpTables.clear(); // Blocks may have shifted around. Keep the numbering up to date. MF.RenumberBlocks(); @@ -438,32 +436,14 @@ /// information about the sizes of each block and the locations of all /// the jump tables. void ARMConstantIslands::JumpTableFunctionScan(MachineFunction &MF) { - unsigned Offset = 0; for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); MBBI != E; ++MBBI) { MachineBasicBlock &MBB = *MBBI; - unsigned MBBSize = 0; for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); - I != E; ++I) { - // Add instruction size to MBBSize. - MBBSize += TII->GetInstSizeInBytes(I); - - int Opc = I->getOpcode(); - if (I->getDesc().isBranch()) { - switch (Opc) { - default: - continue; // Ignore other JT branches - case ARM::t2BR_JT: - T2JumpTables.push_back(I); - continue; // Does not get an entry in ImmBranches - } - } - } - - BBSizes.push_back(MBBSize); - BBOffsets.push_back(Offset); - Offset += MBBSize; + I != E; ++I) + if (I->getDesc().isBranch() && I->getOpcode() == ARM::t2BR_JT) + T2JumpTables.push_back(I); } } @@ -1737,13 +1717,13 @@ // We prefer if target blocks for the jump table come after the jump // instruction so we can use TB[BH]. Loop through the target blocks // and try to adjust them such that that's true. - unsigned JTOffset = GetOffsetOf(MI) + 4; + int JTNumber = MI->getParent()->getNumber(); const std::vector &JTBBs = JT[JTI].MBBs; for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) { MachineBasicBlock *MBB = JTBBs[j]; - unsigned DstOffset = BBOffsets[MBB->getNumber()]; + int DTNumber = MBB->getNumber(); - if (DstOffset < JTOffset) { + if (DTNumber < JTNumber) { // The destination precedes the switch. Try to move the block forward // so we have a positive offset. MachineBasicBlock *NewBB = @@ -1763,13 +1743,10 @@ { MachineFunction &MF = *BB->getParent(); - // FIXME: If it's a small block terminated by an unconditional branch, + // If it's the destination block is terminated by an unconditional branch, // try to move it; otherwise, create a new block following the jump - // table that branches back to the actual target. This is an overly - // simplistic heuristic here for proof-of-concept. - - int BBI = BB->getNumber(); - int Size = BBSizes[BBI]; + // table that branches back to the actual target. This is a very simple + // heuristic. FIXME: We can definitely improve it. MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; @@ -1777,13 +1754,16 @@ if (TII->AnalyzeBranch(*BB, TBB, FBB, Cond)) return NULL; - // If the block is small and ends in an unconditional branch, move it. - if (Size < 50 && Cond.empty() && BB != MF.begin()) { + // If the block ends in an unconditional branch, move it. Be paranoid + // and make sure we're not trying to move the entry block of the function. + if (Cond.empty() && BB != MF.begin()) { MachineFunction::iterator BBi = BB; MachineFunction::iterator OldPrior = prior(BBi); BB->moveAfter(JTBB); OldPrior->updateTerminator(); BB->updateTerminator(); + // Update numbering to account for the block being moved. + MF.RenumberBlocks(OldPrior); ++NumJTMoved; return NULL; } @@ -1808,30 +1788,6 @@ JTBB->removeSuccessor(BB); JTBB->addSuccessor(NewBB); - // Insert a size into BBSizes to align it properly with the (newly - // renumbered) block numbers. - BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0); - - // Likewise for BBOffsets. - BBOffsets.insert(BBOffsets.begin()+NewBB->getNumber(), 0); - - // Figure out how large the first NewMBB is. - unsigned NewBBSize = 0; - for (MachineBasicBlock::iterator I = NewBB->begin(), E = NewBB->end(); - I != E; ++I) - NewBBSize += TII->GetInstSizeInBytes(I); - - unsigned NewBBI = NewBB->getNumber(); - unsigned JTBBI = JTBB->getNumber(); - // Set the size of NewBB in BBSizes. - BBSizes[NewBBI] = NewBBSize; - - // ...and adjust BBOffsets for NewBB accordingly. - BBOffsets[NewBBI] = BBOffsets[JTBBI] + BBSizes[JTBBI]; - - // All BBOffsets following these blocks must be modified. - AdjustBBOffsetsAfter(NewBB, 4); - ++NumJTInserted; return NewBB; } From evan.cheng at apple.com Mon Nov 16 13:00:07 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 16 Nov 2009 11:00:07 -0800 Subject: [llvm-commits] [llvm] r88805 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp In-Reply-To: <88F90AB9-C83A-4B4C-BF9F-484730623813@apple.com> References: <200911142010.nAEKAIMp014778@zion.cs.uiuc.edu> <88F90AB9-C83A-4B4C-BF9F-484730623813@apple.com> Message-ID: On Nov 16, 2009, at 10:46 AM, Jim Grosbach wrote: > > On Nov 15, 2009, at 10:44 PM, Evan Cheng wrote: > >> Hi Jim, >> >> Some comments for 86999 and friends: >> >> /// ReorderThumb2JumpTables - Use tbb / tbh instructions to generate smaller >> /// jumptables when it's possible. >> bool ARMConstantIslands::ReorderThumb2JumpTables(MachineFunction &MF) { >> >> This comment is misleading. tbb / tbh are formed later, right? > > Yes. Excellent point. I'll clean that up. > >> >> + // FIXME: If it's a small block terminated by an unconditional branch, >> + // try to move it; otherwise, create a new block following the jump >> + // table that branches back to the actual target. This is an overly >> + // simplistic heuristic here for proof-of-concept. >> >> What do you plan as a replacement? Jump + jump seems bad for performance? Why not just add a unconditional branch to replace the fall through? > > When we can't use a table branch instruction, we generate a jump table of branch instructions, so we have a jump+jump in that case. If That's going to be changed. It's currently this way due to a Darwin linker issue. > we use the new fall-back situation of inserting a new jump block, then use the table branch instruction, we've not added any additional jumps for that branch target. For any forward targets of the same jump table, however, the second branch has been removed and performance will improve (this is where I suspect a good portion of our 8% gain on JSC is coming from). > > For example, when not using TBB, we generate code like: > adr.w r2, #LJTI1_0_0 > add.w r2, r2, r1, lsl #2 > mov pc, r2 > LJTI1_0_0: > b.w LBB1_5 > b.w LBB1_19 > b.w LBB1_19 > b.w LBB1_1 > b.w LBB1_1 > b.w LBB1_7 > b.w LBB1_19 > b.w LBB1_19 > b.w LBB1_6 > > If we move things around and insert back-jump blocks as necessary, we get something like: > tbb [pc, r1] > LJTI1_0_0: > .byte (LBB1_18-LJTI1_0_0)/2 > .byte (LBB1_20-LJTI1_0_0)/2 > .byte (LBB1_20-LJTI1_0_0)/2 > .byte (LBB1_17-LJTI1_0_0)/2 > .byte (LBB1_17-LJTI1_0_0)/2 > .byte (LBB1_16-LJTI1_0_0)/2 > .byte (LBB1_20-LJTI1_0_0)/2 > .byte (LBB1_20-LJTI1_0_0)/2 > .byte (LBB1_15-LJTI1_0_0)/2 > > In this case, LBB1_1 was unable to be moved, but the rest were relocated foward. From -stats: > 3 arm-cp-islands - Number of jump table destination blocks moved > 1 arm-cp-islands - Number of jump table intermediate blocks inserted > > Thus, for LBB_1, the performance is comparable before and after (slightly better since the adr.w and add.w instructions are no longer needed). For all other cases, the performance is significantly improved due to the direct dispatch from the TBB instruction instead of going through the secondary B.W in the table. I believe this is not going to make jump table performance worse. The question is whether it can be better. If we simply move LBB1_1 and replace its fallthrough edge with an unconditional edge, would that be better? > > >> >> + // If the block is small and ends in an unconditional branch, move it. >> + if (Size < 50 && Cond.empty()) >> >> Where is 50 coming from? > > It's entirely arbitrary. I don't believe any size restriction is necessary, really. This was just to help get a mix of cases where the blocks were moved vs. when they weren't for test coverage. I'll be removing that bit shortly, which will also greatly simplify the side data structures needed (no need to track block sizes and offsets). Ok. Evan > > -Jim > >> >> Evan >> >> On Nov 14, 2009, at 12:10 PM, Jim Grosbach wrote: >> >>> Author: grosbach >>> Date: Sat Nov 14 14:10:18 2009 >>> New Revision: 88805 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=88805&view=rev >>> Log: >>> Cleanup flow, and only update the jump table we're analyzing when replacing a destination MBB. >>> >>> Modified: >>> llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=88805&r1=88804&r2=88805&view=diff >>> >>> ============================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Sat Nov 14 14:10:18 2009 >>> @@ -1749,7 +1749,7 @@ >>> MachineBasicBlock *NewBB = >>> AdjustJTTargetBlockForward(MBB, MI->getParent()); >>> if (NewBB) >>> - MJTI->ReplaceMBBInJumpTables(JTBBs[j], NewBB); >>> + MJTI->ReplaceMBBInJumpTable(JTI, JTBBs[j], NewBB); >>> MadeChange = true; >>> } >>> } >>> @@ -1772,16 +1772,16 @@ >>> int Size = BBSizes[BBI]; >>> MachineBasicBlock *TBB = 0, *FBB = 0; >>> SmallVector Cond; >>> - // If the block terminator isn't analyzable, don't try to move the block >>> - if (TII->AnalyzeBranch(*BB, TBB, FBB, Cond)) >>> - return NULL; >>> - >>> // If the block is small and ends in an unconditional branch, move it. >>> if (Size < 50 && Cond.empty()) { >>> + // If the block terminator isn't analyzable, don't try to move the block >>> + if (TII->AnalyzeBranch(*BB, TBB, FBB, Cond)) >>> + return NULL; >>> + >>> MachineFunction::iterator OldPrior = prior(BB); >>> BB->moveAfter(JTBB); >>> OldPrior->updateTerminator(); >>> - //BB->updateTerminator(); >>> + BB->updateTerminator(); >>> ++NumJTMoved; >>> return NULL; >>> } >>> @@ -1792,20 +1792,22 @@ >>> MachineFunction::iterator MBBI = JTBB; ++MBBI; >>> MF.insert(MBBI, NewBB); >>> >>> + //MF.splice(MBBI, NewBB, NewBB); >>> + >>> // Add an unconditional branch from NewBB to BB. >>> // There doesn't seem to be meaningful DebugInfo available; this doesn't >>> // correspond directly to anything in the source. >>> assert (isThumb2 && "Adjusting for TB[BH] but not in Thumb2?"); >>> BuildMI(NewBB, DebugLoc::getUnknownLoc(), TII->get(ARM::t2B)).addMBB(BB); >>> >>> + // Update internal data structures to account for the newly inserted MBB. >>> + MF.RenumberBlocks(NewBB); >>> + >>> // Update the CFG. >>> NewBB->addSuccessor(BB); >>> JTBB->removeSuccessor(BB); >>> JTBB->addSuccessor(NewBB); >>> >>> - // Update internal data structures to account for the newly inserted MBB. >>> - MF.RenumberBlocks(); >>> - >>> // Insert a size into BBSizes to align it properly with the (newly >>> // renumbered) block numbers. >>> BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0); >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > From daniel at zuster.org Mon Nov 16 13:06:11 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 16 Nov 2009 12:06:11 -0700 Subject: [llvm-commits] [llvm] r88913 - in /llvm/trunk/include/llvm/Support: Compiler.h IRBuilder.h In-Reply-To: <93852A99-2499-4D9E-80CC-4E6035D72F0C@apple.com> References: <200911161528.nAGFSIpF022448@zion.cs.uiuc.edu> <93852A99-2499-4D9E-80CC-4E6035D72F0C@apple.com> Message-ID: <6a8523d60911161106r291ab659w965cccea9107f7f0@mail.gmail.com> Couldn't this extra function also just be private with a DO NOT IMPLEMENT marker? - Daniel On Mon, Nov 16, 2009 at 9:28 AM, Douglas Gregor wrote: > > On Nov 16, 2009, at 7:28 AM, Duncan Sands wrote: > > Author: baldrick > Date: Mon Nov 16 09:28:17 2009 > New Revision: 88913 > > URL: http://llvm.org/viewvc/llvm-project?rev=88913&view=rev > Log: > Make sure that if anyone passes a name by accident for the isSigned > parameter of CreateIntCast then they get an error from the compiler > (or from the linker with a non-gcc compiler). ?Another possibility > is to flip the order of the DestTy and isSigned parameters, since you > should then get a compiler warning if you try to use a char* for a > Type*. > > Modified: > ???llvm/trunk/include/llvm/Support/Compiler.h > ???llvm/trunk/include/llvm/Support/IRBuilder.h > > Modified: llvm/trunk/include/llvm/Support/Compiler.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Compiler.h?rev=88913&r1=88912&r2=88913&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Support/Compiler.h (original) > +++ llvm/trunk/include/llvm/Support/Compiler.h Mon Nov 16 09:28:17 2009 > @@ -78,4 +78,10 @@ > #define NORETURN > #endif > > +#ifdef __GNUC__ > +#define ERROR_IF_USED __attribute__((error("wrong usage"))) > +#else > +#define ERROR_IF_USED > +#endif > + > #endif > > I'm getting a bunch of warnings now, since the "error" attribute is only > available on GCC >= 4.3. Patch coming to conditionalize this more > appropriately... > ??- Doug > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From dpatel at apple.com Mon Nov 16 13:20:48 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 16 Nov 2009 19:20:48 -0000 Subject: [llvm-commits] [llvm] r88939 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <200911161920.nAGJKm72032127@zion.cs.uiuc.edu> Author: dpatel Date: Mon Nov 16 13:20:48 2009 New Revision: 88939 URL: http://llvm.org/viewvc/llvm-project?rev=88939&view=rev Log: Add VISIBILITY_HIDDEN marker. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=88939&r1=88938&r2=88939&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Nov 16 13:20:48 2009 @@ -124,7 +124,7 @@ //===----------------------------------------------------------------------===// /// DbgVariable - This class is used to track local variable information. /// -class DbgVariable { +class VISIBILITY_HIDDEN DbgVariable { DIVariable Var; // Variable Descriptor. unsigned FrameIndex; // Variable frame index. DbgVariable *AbstractVar; // Abstract variable for this variable. @@ -146,7 +146,7 @@ /// DbgScope - This class is used to track scope information. /// class DbgConcreteScope; -class DbgScope { +class VISIBILITY_HIDDEN DbgScope { DbgScope *Parent; // Parent to this scope. DIDescriptor Desc; // Debug info descriptor for scope. WeakVH InlinedAtLocation; // Location at which scope is inlined. From bob.wilson at apple.com Mon Nov 16 13:33:28 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 16 Nov 2009 19:33:28 -0000 Subject: [llvm-commits] [llvm] r88940 - /llvm/trunk/lib/CodeGen/BranchFolding.cpp Message-ID: <200911161933.nAGJXSXQ032754@zion.cs.uiuc.edu> Author: bwilson Date: Mon Nov 16 13:33:27 2009 New Revision: 88940 URL: http://llvm.org/viewvc/llvm-project?rev=88940&view=rev Log: Fix a comment. Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=88940&r1=88939&r2=88940&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Mon Nov 16 13:33:27 2009 @@ -1185,7 +1185,7 @@ // If the previous block unconditionally falls through to this block and // this block has no other predecessors, move the contents of this block // into the prior block. This doesn't usually happen when SimplifyCFG - // has been used, but it can happen tail duplication eliminates all the + // has been used, but it can happen if tail duplication eliminates all the // non-branch predecessors of a block leaving only the fall-through edge. // This has to check PrevBB->succ_size() because EH edges are ignored by // AnalyzeBranch. From evan.cheng at apple.com Mon Nov 16 13:44:56 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 16 Nov 2009 11:44:56 -0800 Subject: [llvm-commits] [llvm] r88902 - /llvm/trunk/lib/VMCore/AsmWriter.cpp In-Reply-To: <200911160917.10088.dag@cray.com> References: <200911160710.nAG7Aa2W023263@zion.cs.uiuc.edu> <200911160917.10088.dag@cray.com> Message-ID: On Nov 16, 2009, at 7:17 AM, David Greene wrote: > On Monday 16 November 2009 01:10, Evan Cheng wrote: >> Author: evancheng >> Date: Mon Nov 16 01:10:36 2009 >> New Revision: 88902 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=88902&view=rev >> Log: >> Special case FixedStackPseudoSourceValueVal as well. Do we really need to >> differentiate PseudoSourceValueVal from FixedStackPseudoSourceValueVal at >> this level? > > Yes. The asm printer uses it to emit comments about spills. > > -Dave That's not quite what I am asking. Your change introduced a new Value type for a very specialized sub-type of PseudoSourceValueVal at llvm IR level. Are you sure there isn't another way to handle it? Evan From grosbach at apple.com Mon Nov 16 13:46:46 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 Nov 2009 19:46:46 -0000 Subject: [llvm-commits] [llvm] r88942 - /llvm/trunk/test/CodeGen/Thumb2/thumb2-uxt_rot.ll Message-ID: <200911161946.nAGJkkv5000822@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 13:46:46 2009 New Revision: 88942 URL: http://llvm.org/viewvc/llvm-project?rev=88942&view=rev Log: Convert to FileCheck Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-uxt_rot.ll Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-uxt_rot.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-uxt_rot.ll?rev=88942&r1=88941&r2=88942&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-uxt_rot.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-uxt_rot.ll Mon Nov 16 13:46:46 2009 @@ -1,13 +1,15 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep uxtb | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep uxtab | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep uxth | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i8 @test1(i32 %A.u) zeroext { +; CHECK: test1 +; CHECK: uxtb r0, r0 %B.u = trunc i32 %A.u to i8 ret i8 %B.u } define i32 @test2(i32 %A.u, i32 %B.u) zeroext { +; CHECK: test2 +; CHECK: uxtab r0, r0, r1 %C.u = trunc i32 %B.u to i8 %D.u = zext i8 %C.u to i32 %E.u = add i32 %A.u, %D.u @@ -15,6 +17,8 @@ } define i32 @test3(i32 %A.u) zeroext { +; CHECK: test3 +; CHECK: uxth.w r0, r0, ror #8 %B.u = lshr i32 %A.u, 8 %C.u = shl i32 %A.u, 24 %D.u = or i32 %B.u, %C.u From rafael.espindola at gmail.com Mon Nov 16 13:46:56 2009 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 16 Nov 2009 19:46:56 -0000 Subject: [llvm-commits] [llvm] r88943 - in /llvm/trunk: Makefile.config.in autoconf/configure.ac configure include/llvm/Config/config.h.cmake include/llvm/Config/config.h.in Message-ID: <200911161946.nAGJkugN000843@zion.cs.uiuc.edu> Author: rafael Date: Mon Nov 16 13:46:55 2009 New Revision: 88943 URL: http://llvm.org/viewvc/llvm-project?rev=88943&view=rev Log: Add configure options for specifying where to look for libstdc++. Modified: llvm/trunk/Makefile.config.in llvm/trunk/autoconf/configure.ac llvm/trunk/configure llvm/trunk/include/llvm/Config/config.h.cmake llvm/trunk/include/llvm/Config/config.h.in Modified: llvm/trunk/Makefile.config.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.config.in?rev=88943&r1=88942&r2=88943&view=diff ============================================================================== --- llvm/trunk/Makefile.config.in (original) +++ llvm/trunk/Makefile.config.in Mon Nov 16 13:46:55 2009 @@ -314,6 +314,10 @@ BINUTILS_INCDIR := @BINUTILS_INCDIR@ C_INCLUDE_DIRS := @C_INCLUDE_DISR@ +CXX_INCLUDE_ROOT := @CXX_INCLUDE_ROOT@ +CXX_INCLUDE_ARCH := @CXX_INCLUDE_ARCH@ +CXX_INCLUDE_32BIT_DIR = @CXX_INCLUDE_32BIT_DIR@ +CXX_INCLUDE_64BIT_DIR = @CXX_INCLUDE_64BIT_DIR@ # When ENABLE_LLVMC_DYNAMIC is enabled, LLVMC will link libCompilerDriver # dynamically. This is needed to make dynamic plugins work on some targets Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=88943&r1=88942&r2=88943&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Mon Nov 16 13:46:55 2009 @@ -674,6 +674,34 @@ AC_DEFINE_UNQUOTED(C_INCLUDE_DIRS,"$withval", [Directories clang will search for headers]) +AC_ARG_WITH(cxx-include-root, + AS_HELP_STRING([--with-cxx-include-root], + [Directory with the libstdc++ headers.]),, + withval="") +AC_DEFINE_UNQUOTED(CXX_INCLUDE_ROOT,"$withval", + [Directory with the libstdc++ headers.]) + +AC_ARG_WITH(cxx-include-arch, + AS_HELP_STRING([--with-cxx-include-arch], + [Architecture of the libstdc++ headers.]),, + withval="") +AC_DEFINE_UNQUOTED(CXX_INCLUDE_ARCH,"$withval", + [Arch the libstdc++ headers.]) + +AC_ARG_WITH(cxx-include-32bit-dir, + AS_HELP_STRING([--with-cxx-include-32bit-dir], + [32 bit multilib dir.]),, + withval="") +AC_DEFINE_UNQUOTED(CXX_INCLUDE_32BIT_DIR,"$withval", + [32 bit multilib directory.]) + +AC_ARG_WITH(cxx-include-64bit-dir, + AS_HELP_STRING([--with-cxx-include-64bit-dir], + [64 bit multilib directory.]),, + withval="") +AC_DEFINE_UNQUOTED(CXX_INCLUDE_64BIT_DIR,"$withval", + [64 bit multilib directory.]) + dnl Allow linking of LLVM with GPLv3 binutils code. AC_ARG_WITH(binutils-include, AS_HELP_STRING([--with-binutils-include], Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=88943&r1=88942&r2=88943&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Mon Nov 16 13:46:55 2009 @@ -1605,6 +1605,12 @@ is stdlib) --with-c-include-dirs Colon separated list of directories clang will search for headers + --with-cxx-include-root Directory with the libstdc++ headers. + --with-cxx-include-arch Architecture of the libstdc++ headers. + --with-cxx-include-32bit-dir + 32 bit multilib dir. + --with-cxx-include-64bit-dir + 64 bit multilib directory. --with-binutils-include Specify path to binutils/include/ containing plugin-api.h file for gold plugin. --with-tclinclude directory where tcl headers are @@ -5288,6 +5294,62 @@ +# Check whether --with-cxx-include-root was given. +if test "${with_cxx_include_root+set}" = set; then + withval=$with_cxx_include_root; +else + withval="" +fi + + +cat >>confdefs.h <<_ACEOF +#define CXX_INCLUDE_ROOT "$withval" +_ACEOF + + + +# Check whether --with-cxx-include-arch was given. +if test "${with_cxx_include_arch+set}" = set; then + withval=$with_cxx_include_arch; +else + withval="" +fi + + +cat >>confdefs.h <<_ACEOF +#define CXX_INCLUDE_ARCH "$withval" +_ACEOF + + + +# Check whether --with-cxx-include-32bit-dir was given. +if test "${with_cxx_include_32bit_dir+set}" = set; then + withval=$with_cxx_include_32bit_dir; +else + withval="" +fi + + +cat >>confdefs.h <<_ACEOF +#define CXX_INCLUDE_32BIT_DIR "$withval" +_ACEOF + + + +# Check whether --with-cxx-include-64bit-dir was given. +if test "${with_cxx_include_64bit_dir+set}" = set; then + withval=$with_cxx_include_64bit_dir; +else + withval="" +fi + + +cat >>confdefs.h <<_ACEOF +#define CXX_INCLUDE_64BIT_DIR "$withval" +_ACEOF + + + # Check whether --with-binutils-include was given. if test "${with_binutils_include+set}" = set; then withval=$with_binutils_include; @@ -11052,7 +11114,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext + echo '#line 13261 "configure"' > conftest.$ac_ext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 (eval $ac_compile) 2>&5 ac_status=$? @@ -14914,11 +14976,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:14917: $lt_compile\"" >&5) + (eval echo "\"\$as_me:14979: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:14921: \$? = $ac_status" >&5 + echo "$as_me:14983: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -15182,11 +15244,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:15185: $lt_compile\"" >&5) + (eval echo "\"\$as_me:15247: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:15189: \$? = $ac_status" >&5 + echo "$as_me:15251: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -15286,11 +15348,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:15289: $lt_compile\"" >&5) + (eval echo "\"\$as_me:15351: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:15293: \$? = $ac_status" >&5 + echo "$as_me:15355: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -17738,7 +17800,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5) + (eval echo "\"\$as_me:20271: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:20213: \$? = $ac_status" >&5 + echo "$as_me:20275: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -20310,11 +20372,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:20313: $lt_compile\"" >&5) + (eval echo "\"\$as_me:20375: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:20317: \$? = $ac_status" >&5 + echo "$as_me:20379: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -21880,11 +21942,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21883: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21945: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:21887: \$? = $ac_status" >&5 + echo "$as_me:21949: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -21984,11 +22046,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21987: $lt_compile\"" >&5) + (eval echo "\"\$as_me:22049: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:21991: \$? = $ac_status" >&5 + echo "$as_me:22053: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -24219,11 +24281,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:24222: $lt_compile\"" >&5) + (eval echo "\"\$as_me:24284: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:24226: \$? = $ac_status" >&5 + echo "$as_me:24288: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -24487,11 +24549,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:24490: $lt_compile\"" >&5) + (eval echo "\"\$as_me:24552: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:24494: \$? = $ac_status" >&5 + echo "$as_me:24556: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -24591,11 +24653,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:24594: $lt_compile\"" >&5) + (eval echo "\"\$as_me:24656: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:24598: \$? = $ac_status" >&5 + echo "$as_me:24660: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized Modified: llvm/trunk/include/llvm/Config/config.h.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.cmake?rev=88943&r1=88942&r2=88943&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.cmake (original) +++ llvm/trunk/include/llvm/Config/config.h.cmake Mon Nov 16 13:46:55 2009 @@ -12,6 +12,18 @@ /* Directories clang will search for headers */ #define C_INCLUDE_DIRS "${C_INCLUDE_DIRS}" +/* Directory clang will search for libstdc++ headers */ +#define CXX_INCLUDE_ROOT "${CXX_INCLUDE_ROOT}" + +/* Architecture of libstdc++ headers */ +#define CXX_INCLUDE_ARCH "${CXX_INCLUDE_ARCH}" + +/* 32 bit multilib directory */ +#define CXX_INCLUDE_32BIT_DIR "${CXX_INCLUDE_32BIT_DIR}" + +/* 64 bit multilib directory */ +#define CXX_INCLUDE_64BIT_DIR "${CXX_INCLUDE_64BIT_DIR}" + /* Define if position independent code is enabled */ #cmakedefine ENABLE_PIC ${ENABLE_PIC} Modified: llvm/trunk/include/llvm/Config/config.h.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.in?rev=88943&r1=88942&r2=88943&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.in (original) +++ llvm/trunk/include/llvm/Config/config.h.in Mon Nov 16 13:46:55 2009 @@ -8,6 +8,18 @@ */ #undef CRAY_STACKSEG_END +/* 32 bit multilib directory. */ +#undef CXX_INCLUDE_32BIT_DIR + +/* 64 bit multilib directory. */ +#undef CXX_INCLUDE_64BIT_DIR + +/* Arch the libstdc++ headers. */ +#undef CXX_INCLUDE_ARCH + +/* Directory with the libstdc++ headers. */ +#undef CXX_INCLUDE_ROOT + /* Define to 1 if using `alloca.c'. */ #undef C_ALLOCA From dag at cray.com Mon Nov 16 13:57:56 2009 From: dag at cray.com (David Greene) Date: Mon, 16 Nov 2009 13:57:56 -0600 Subject: [llvm-commits] [llvm] r88902 - /llvm/trunk/lib/VMCore/AsmWriter.cpp In-Reply-To: References: <200911160710.nAG7Aa2W023263@zion.cs.uiuc.edu> <200911160917.10088.dag@cray.com> Message-ID: <200911161357.56221.dag@cray.com> On Monday 16 November 2009 13:44, Evan Cheng wrote: > That's not quite what I am asking. Your change introduced a new Value type > for a very specialized sub-type of PseudoSourceValueVal at llvm IR level. > Are you sure there isn't another way to handle it? Look at X86InstrInfo::hasLoadFromStackSlot. Is there another way to get the frame index from a memory operand? If so, I'd be happy to get rid of this. -Dave From lhames at gmail.com Mon Nov 16 14:03:13 2009 From: lhames at gmail.com (Lang Hames) Date: Mon, 16 Nov 2009 20:03:13 -0000 Subject: [llvm-commits] [llvm] r88946 - /llvm/trunk/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll Message-ID: <200911162003.nAGK3E8R001580@zion.cs.uiuc.edu> Author: lhames Date: Mon Nov 16 14:03:13 2009 New Revision: 88946 URL: http://llvm.org/viewvc/llvm-project?rev=88946&view=rev Log: Added a testcase for PR5495. Added: llvm/trunk/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll Added: llvm/trunk/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll?rev=88946&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll (added) +++ llvm/trunk/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll Mon Nov 16 14:03:13 2009 @@ -0,0 +1,75 @@ +; RUN: llc < %s +; PR5495 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i386-pc-linux-gnu" + +%"struct.std::__ctype_abstract_base" = type { %"struct.std::locale::facet" } +%"struct.std::basic_ios >" = type { %"struct.std::ios_base", %"struct.std::basic_ostream >"*, i8, i8, %"struct.std::basic_streambuf >"*, %"struct.std::ctype"*, %"struct.std::__ctype_abstract_base"*, %"struct.std::__ctype_abstract_base"* } +%"struct.std::basic_istream >" = type { i32 (...)**, i32, %"struct.std::basic_ios >" } +%"struct.std::basic_ostream >" = type { i32 (...)**, %"struct.std::basic_ios >" } +%"struct.std::basic_streambuf >" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %"struct.std::locale" } +%"struct.std::ctype" = type { %"struct.std::locale::facet", i32*, i8, i32*, i32*, i16*, i8, [256 x i8], [256 x i8], i8 } +%"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, %"struct.std::ios_base::_Words"*, %"struct.std::locale" } +%"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 } +%"struct.std::ios_base::_Words" = type { i8*, i32 } +%"struct.std::locale" = type { %"struct.std::locale::_Impl"* } +%"struct.std::locale::_Impl" = type { i32, %"struct.std::locale::facet"**, i32, %"struct.std::locale::facet"**, i8** } +%"struct.std::locale::facet" = type { i32 (...)**, i32 } +%union..0._15 = type { i32 } + +declare i8* @llvm.eh.exception() nounwind readonly + +declare i8* @__cxa_begin_catch(i8*) nounwind + +declare %"struct.std::ctype"* @_ZSt9use_facetISt5ctypeIcEERKT_RKSt6locale(%"struct.std::locale"*) + +define %"struct.std::basic_istream >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_(%"struct.std::basic_istream >"* %__in, i8* nocapture %__s) { +entry: + %0 = invoke %"struct.std::ctype"* @_ZSt9use_facetISt5ctypeIcEERKT_RKSt6locale(%"struct.std::locale"* undef) + to label %invcont8 unwind label %lpad74 ; <%"struct.std::ctype"*> [#uses=0] + +invcont8: ; preds = %entry + %1 = invoke i32 undef(%"struct.std::basic_streambuf >"* undef) + to label %bb26.preheader unwind label %lpad ; [#uses=0] + +bb26.preheader: ; preds = %invcont8 + br label %invcont38 + +bb1.i100: ; preds = %invcont38 + %2 = add nsw i32 1, %__extracted.0 ; [#uses=3] + br i1 undef, label %bb.i97, label %bb1.i + +bb.i97: ; preds = %bb1.i100 + br label %invcont38 + +bb1.i: ; preds = %bb1.i100 + %3 = invoke i32 undef(%"struct.std::basic_streambuf >"* undef) + to label %invcont38 unwind label %lpad ; [#uses=0] + +invcont24: ; preds = %invcont38 + %4 = invoke i32 undef(%"struct.std::basic_streambuf >"* undef) + to label %_ZNSt15basic_streambufIcSt11char_traitsIcEE6sbumpcEv.exit.i unwind label %lpad ; [#uses=0] + +_ZNSt15basic_streambufIcSt11char_traitsIcEE6sbumpcEv.exit.i: ; preds = %invcont24 + br i1 undef, label %invcont25, label %bb.i93 + +bb.i93: ; preds = %_ZNSt15basic_streambufIcSt11char_traitsIcEE6sbumpcEv.exit.i + %5 = invoke i32 undef(%"struct.std::basic_streambuf >"* undef) + to label %invcont25 unwind label %lpad ; [#uses=0] + +invcont25: ; preds = %bb.i93, %_ZNSt15basic_streambufIcSt11char_traitsIcEE6sbumpcEv.exit.i + br label %invcont38 + +invcont38: ; preds = %invcont25, %bb1.i, %bb.i97, %bb26.preheader + %__extracted.0 = phi i32 [ 0, %bb26.preheader ], [ undef, %invcont25 ], [ %2, %bb.i97 ], [ %2, %bb1.i ] ; [#uses=1] + br i1 false, label %bb1.i100, label %invcont24 + +lpad: ; preds = %bb.i93, %invcont24, %bb1.i, %invcont8 + %__extracted.1 = phi i32 [ 0, %invcont8 ], [ %2, %bb1.i ], [ undef, %bb.i93 ], [ undef, %invcont24 ] ; [#uses=0] + %eh_ptr = call i8* @llvm.eh.exception() ; [#uses=1] + %6 = call i8* @__cxa_begin_catch(i8* %eh_ptr) nounwind ; [#uses=0] + unreachable + +lpad74: ; preds = %entry + unreachable +} From grosbach at apple.com Mon Nov 16 14:04:15 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 Nov 2009 20:04:15 -0000 Subject: [llvm-commits] [llvm] r88947 - /llvm/trunk/test/CodeGen/Thumb2/thumb2-teq2.ll Message-ID: <200911162004.nAGK4F01001627@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 14:04:15 2009 New Revision: 88947 URL: http://llvm.org/viewvc/llvm-project?rev=88947&view=rev Log: Convert to FileCheck Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-teq2.ll Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-teq2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-teq2.ll?rev=88947&r1=88946&r2=88947&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-teq2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-teq2.ll Mon Nov 16 14:04:15 2009 @@ -1,34 +1,40 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\]$} | count 4 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i1 @f1(i32 %a, i32 %b) { +; CHECK: f1 +; CHECK: teq.w r0, r1 %tmp = xor i32 %a, %b %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } define i1 @f2(i32 %a, i32 %b) { +; CHECK: f2 +; CHECK: teq.w r0, r1 %tmp = xor i32 %a, %b %tmp1 = icmp eq i32 %tmp, 0 ret i1 %tmp1 } define i1 @f3(i32 %a, i32 %b) { +; CHECK: f3 +; CHECK: teq.w r0, r1 %tmp = xor i32 %a, %b %tmp1 = icmp ne i32 0, %tmp ret i1 %tmp1 } define i1 @f4(i32 %a, i32 %b) { +; CHECK: f4 +; CHECK: teq.w r0, r1 %tmp = xor i32 %a, %b %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } define i1 @f6(i32 %a, i32 %b) { +; CHECK: f6 +; CHECK: teq.w r0, r1, lsl #5 %tmp = shl i32 %b, 5 %tmp1 = xor i32 %a, %tmp %tmp2 = icmp eq i32 %tmp1, 0 @@ -36,6 +42,8 @@ } define i1 @f7(i32 %a, i32 %b) { +; CHECK: f7 +; CHECK: teq.w r0, r1, lsr #6 %tmp = lshr i32 %b, 6 %tmp1 = xor i32 %a, %tmp %tmp2 = icmp eq i32 %tmp1, 0 @@ -43,6 +51,8 @@ } define i1 @f8(i32 %a, i32 %b) { +; CHECK: f8 +; CHECK: teq.w r0, r1, asr #7 %tmp = ashr i32 %b, 7 %tmp1 = xor i32 %a, %tmp %tmp2 = icmp eq i32 %tmp1, 0 @@ -50,6 +60,8 @@ } define i1 @f9(i32 %a, i32 %b) { +; CHECK: f9 +; CHECK: teq.w r0, r0, ror #8 %l8 = shl i32 %a, 24 %r8 = lshr i32 %a, 8 %tmp = or i32 %l8, %r8 From gohman at apple.com Mon Nov 16 14:17:37 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 16 Nov 2009 12:17:37 -0800 Subject: [llvm-commits] [llvm] r87028 - /llvm/trunk/include/llvm/Value.h In-Reply-To: <2E007F8C-185A-4FF7-93B6-580DD29F92C7@apple.com> References: <200911122104.nACL4KeC009301@zion.cs.uiuc.edu> <2E007F8C-185A-4FF7-93B6-580DD29F92C7@apple.com> Message-ID: <742619E9-6FAF-4A99-B674-EB6BB4258C8B@apple.com> PseudoSourceValue's classof should have an "|| V->getValueID() == FixedStackPseudoSourceValue", to properly reflect the isa relationship. That would have avoided the AsmPrinter problem, I believe. In the longer term, Chris has convinced me that we shouldn't have PseudoSourceValue inherit from Value anyway. It should be replaced by some kind of discriminated union which can hold a Value* or a CodeGen-specific handle. Fixing this will get rid of the unsightly layering violation of having CodeGen-specific enum values in Value.h altogether [0]. Dan [0] The degree to which it actually is a layering violation and/or if it is whose fault that is is the subject of some contention, but it's not super important. On Nov 15, 2009, at 11:12 PM, Evan Cheng wrote: > Do we really want to differentiate FixedStackPseudoSourceValueVal as a distinct subclass at the IR level? This seems wrong to me. > > Evan > > On Nov 12, 2009, at 1:04 PM, David Greene wrote: > >> Author: greened >> Date: Thu Nov 12 15:04:19 2009 >> New Revision: 87028 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=87028&view=rev >> Log: >> >> Fix a build error by providing a missing enum value. >> >> Modified: >> llvm/trunk/include/llvm/Value.h >> >> Modified: llvm/trunk/include/llvm/Value.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Value.h?rev=87028&r1=87027&r2=87028&view=diff >> >> ============================================================================== >> --- llvm/trunk/include/llvm/Value.h (original) >> +++ llvm/trunk/include/llvm/Value.h Thu Nov 12 15:04:19 2009 >> @@ -226,7 +226,9 @@ >> PseudoSourceValueVal, // This is an instance of PseudoSourceValue >> FixedStackPseudoSourceValueVal, // This is an instance of PseudoSourceValue >> InstructionVal, // This is an instance of Instruction >> - >> + FixedStackPseudoSourceValueVal, // This is an instance of >> + // FixedStackPseudoSourceValue >> + >> // Markers: >> ConstantFirstVal = FunctionVal, >> ConstantLastVal = ConstantPointerNullVal >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From gohman at apple.com Mon Nov 16 14:36:00 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 16 Nov 2009 20:36:00 -0000 Subject: [llvm-commits] [llvm] r88953 - in /llvm/trunk/lib/CodeGen/SelectionDAG: InstrEmitter.cpp InstrEmitter.h Message-ID: <200911162036.nAGKa0cY003795@zion.cs.uiuc.edu> Author: djg Date: Mon Nov 16 14:35:59 2009 New Revision: 88953 URL: http://llvm.org/viewvc/llvm-project?rev=88953&view=rev Log: Fix a typo in a comment. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=88953&r1=88952&r2=88953&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Mon Nov 16 14:35:59 2009 @@ -497,7 +497,7 @@ assert(isNew && "Node emitted out of order - early"); } -/// EmitNode - Generate machine code for an node and needed dependencies. +/// EmitNode - Generate machine code for a node and needed dependencies. /// void InstrEmitter::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, DenseMap &VRBaseMap, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h?rev=88953&r1=88952&r2=88953&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h Mon Nov 16 14:35:59 2009 @@ -97,7 +97,7 @@ /// MachineInstr. static unsigned CountOperands(SDNode *Node); - /// EmitNode - Generate machine code for an node and needed dependencies. + /// EmitNode - Generate machine code for a node and needed dependencies. /// void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, DenseMap &VRBaseMap, From gohman at apple.com Mon Nov 16 14:40:07 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 16 Nov 2009 20:40:07 -0000 Subject: [llvm-commits] [llvm] r88954 - /llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h Message-ID: <200911162040.nAGKe7tD003974@zion.cs.uiuc.edu> Author: djg Date: Mon Nov 16 14:40:06 2009 New Revision: 88954 URL: http://llvm.org/viewvc/llvm-project?rev=88954&view=rev Log: Make PseudoSourceValue's classof recognize FixedStackPseudoSourceValueVal, to respect this isa relationship. Modified: llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h Modified: llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h?rev=88954&r1=88953&r2=88954&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h (original) +++ llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h Mon Nov 16 14:40:06 2009 @@ -32,7 +32,7 @@ virtual void printCustom(raw_ostream &O) const; public: - PseudoSourceValue(enum ValueTy Subclass = PseudoSourceValueVal); + explicit PseudoSourceValue(enum ValueTy Subclass = PseudoSourceValueVal); /// isConstant - Test whether the memory pointed to by this /// PseudoSourceValue has a constant value. @@ -52,7 +52,8 @@ /// static inline bool classof(const PseudoSourceValue *) { return true; } static inline bool classof(const Value *V) { - return V->getValueID() == PseudoSourceValueVal; + return V->getValueID() == PseudoSourceValueVal || + V->getValueID() == FixedStackPseudoSourceValueVal; } /// A pseudo source value referencing a fixed stack frame entry, From gohman at apple.com Mon Nov 16 14:40:47 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 16 Nov 2009 20:40:47 -0000 Subject: [llvm-commits] [llvm] r88956 - in /llvm/trunk: include/llvm/CodeGen/MachineFunction.h lib/CodeGen/AntiDepBreaker.h Message-ID: <200911162040.nAGKelRX004029@zion.cs.uiuc.edu> Author: djg Date: Mon Nov 16 14:40:47 2009 New Revision: 88956 URL: http://llvm.org/viewvc/llvm-project?rev=88956&view=rev Log: Sink a #include to where it's actually needed. Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h llvm/trunk/lib/CodeGen/AntiDepBreaker.h Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=88956&r1=88955&r2=88956&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Mon Nov 16 14:40:47 2009 @@ -23,7 +23,6 @@ #include "llvm/Support/DebugLoc.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/Recycler.h" -#include namespace llvm { Modified: llvm/trunk/lib/CodeGen/AntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AntiDepBreaker.h?rev=88956&r1=88955&r2=88956&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/AntiDepBreaker.h Mon Nov 16 14:40:47 2009 @@ -23,6 +23,7 @@ #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallVector.h" +#include namespace llvm { From gohman at apple.com Mon Nov 16 14:41:12 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 16 Nov 2009 20:41:12 -0000 Subject: [llvm-commits] [llvm] r88957 - /llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h Message-ID: <200911162041.nAGKfCjo004052@zion.cs.uiuc.edu> Author: djg Date: Mon Nov 16 14:41:12 2009 New Revision: 88957 URL: http://llvm.org/viewvc/llvm-project?rev=88957&view=rev Log: Remove an unnecessary #include. Modified: llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h Modified: llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h?rev=88957&r1=88956&r2=88957&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h Mon Nov 16 14:41:12 2009 @@ -15,11 +15,11 @@ #define LLVM_CODEGEN_MACHINE_FUNCTION_ANALYSIS_H #include "llvm/Pass.h" -#include "llvm/Target/TargetMachine.h" namespace llvm { class MachineFunction; +class TargetMachine; /// MachineFunctionAnalysis - This class is a Pass that manages a /// MachineFunction object. From grosbach at apple.com Mon Nov 16 14:44:35 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 Nov 2009 12:44:35 -0800 Subject: [llvm-commits] [llvm] r88874 - in /llvm/trunk: lib/Target/ARM/ARM.h lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMTargetMachine.cpp test/CodeGen/ARM/spill-q.ll test/CodeGen/Thumb2/thumb2-spill-q.ll In-Reply-To: <27D3615E-CA82-4885-82D7-1DEC30D1DA1C@apple.com> References: <200911152145.nAFLjZWn002387@zion.cs.uiuc.edu> <27D3615E-CA82-4885-82D7-1DEC30D1DA1C@apple.com> Message-ID: <8B059C90-62A9-407C-AF1B-C9405F0AC464@apple.com> On Nov 15, 2009, at 7:56 PM, Chris Lattner wrote: > > On Nov 15, 2009, at 1:45 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Sun Nov 15 15:45:34 2009 >> New Revision: 88874 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=88874&view=rev >> Log: >> Detect need for autoalignment of the stack earlier to catch spills >> more >> conservatively. eliminateFrameIndex() machinery adjust to handle >> addr mode >> 6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg >> spilling > > Hi Jim, > > Please name the pass something less contracted (so it shows up in > doxygen better without context etc). Also, does it need to be an > ARM specific pass? Do other targets have this sort of issue? > X86 has the same issue and already has equivalent code. I don't see any reason why the code can't be refactored to be shared between the two and available for other targets. I'll have a look at that. As for the name, perhaps something like, "ARM Stack Required Alignment Auto-Detector"? (Removing the "ARM" once it's factored out to not be in the ARM back-end). -Jim > -Chris > >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARM.h >> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp >> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp >> llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp >> llvm/trunk/test/CodeGen/ARM/spill-q.ll >> llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll >> >> Modified: llvm/trunk/lib/Target/ARM/ARM.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=88874&r1=88873&r2=88874&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/ARM/ARM.h (original) >> +++ llvm/trunk/lib/Target/ARM/ARM.h Sun Nov 15 15:45:34 2009 >> @@ -109,6 +109,7 @@ >> FunctionPass *createNEONMoveFixPass(); >> FunctionPass *createThumb2ITBlockPass(); >> FunctionPass *createThumb2SizeReductionPass(); >> +FunctionPass *createARMMaxStackAlignmentCalculatorPass(); >> >> extern Target TheARMTarget, TheThumbTarget; >> >> >> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=88874&r1=88873&r2=88874&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Sun Nov 15 >> 15:45:34 2009 >> @@ -1132,6 +1132,7 @@ >> break; >> } >> case ARMII::AddrMode4: >> + case ARMII::AddrMode6: >> // Can't fold any offset even if it's zero. >> return false; >> case ARMII::AddrMode5: { >> >> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=88874&r1=88873&r2=88874&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Sun Nov 15 >> 15:45:34 2009 >> @@ -1170,7 +1170,8 @@ >> // as much as possible above, handle the rest, providing a >> register that is >> // SP+LargeImm. >> assert((Offset || >> - (MI.getDesc().TSFlags & ARMII::AddrModeMask) == >> ARMII::AddrMode4) && >> + (MI.getDesc().TSFlags & ARMII::AddrModeMask) == >> ARMII::AddrMode4 || >> + (MI.getDesc().TSFlags & ARMII::AddrModeMask) == >> ARMII::AddrMode6) && >> "This code isn't needed if offset already handled!"); >> >> unsigned ScratchReg = 0; >> @@ -1179,7 +1180,7 @@ >> ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); >> unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg >> (); >> if (Offset == 0) >> - // Must be addrmode4. >> + // Must be addrmode4/6. >> MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); >> else { >> ScratchReg = MF.getRegInfo().createVirtualRegister >> (ARM::GPRRegisterClass); >> @@ -1462,4 +1463,46 @@ >> emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); >> } >> >> +namespace { >> + struct MSAC : public MachineFunctionPass { >> + static char ID; >> + MSAC() : MachineFunctionPass(&ID) {} >> + >> + virtual bool runOnMachineFunction(MachineFunction &MF) { >> + MachineFrameInfo *FFI = MF.getFrameInfo(); >> + MachineRegisterInfo &RI = MF.getRegInfo(); >> + >> + // Calculate max stack alignment of all already allocated >> stack objects. >> + unsigned MaxAlign = calculateMaxStackAlignment(FFI); >> + >> + // Be over-conservative: scan over all vreg defs and find, >> whether vector >> + // registers are used. If yes - there is probability, that >> vector register >> + // will be spilled and thus stack needs to be aligned >> properly. >> + for (unsigned RegNum = >> TargetRegisterInfo::FirstVirtualRegister; >> + RegNum < RI.getLastVirtReg(); ++RegNum) >> + MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)- >> >getAlignment()); >> + >> + if (FFI->getMaxAlignment() == MaxAlign) >> + return false; >> + >> + FFI->setMaxAlignment(MaxAlign); >> + return true; >> + } >> + >> + virtual const char *getPassName() const { >> + return "ARM Maximal Stack Alignment Calculator"; >> + } >> + >> + virtual void getAnalysisUsage(AnalysisUsage &AU) const { >> + AU.setPreservesCFG(); >> + MachineFunctionPass::getAnalysisUsage(AU); >> + } >> + }; >> + >> + char MSAC::ID = 0; >> +} >> + >> +FunctionPass* >> +llvm::createARMMaxStackAlignmentCalculatorPass() { return new MSAC >> (); } >> + >> #include "ARMGenRegisterInfo.inc" >> >> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=88874&r1=88873&r2=88874&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Sun Nov 15 >> 15:45:34 2009 >> @@ -93,6 +93,10 @@ >> if (Subtarget.hasNEON()) >> PM.add(createNEONPreAllocPass()); >> >> + // Calculate and set max stack object alignment early, so we can >> decide >> + // whether we will need stack realignment (and thus FP). >> + PM.add(createARMMaxStackAlignmentCalculatorPass()); >> + >> // FIXME: temporarily disabling load / store optimization pass for >> Thumb1. >> if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) >> PM.add(createARMLoadStoreOptimizationPass(true)); >> >> Modified: llvm/trunk/test/CodeGen/ARM/spill-q.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/spill-q.ll?rev=88874&r1=88873&r2=88874&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/test/CodeGen/ARM/spill-q.ll (original) >> +++ llvm/trunk/test/CodeGen/ARM/spill-q.ll Sun Nov 15 15:45:34 2009 >> @@ -11,8 +11,9 @@ >> >> define arm_apcscc void @aaa(%quuz* %this, i8* %block) { >> ; CHECK: aaa: >> -; CHECK: vstmia sp >> -; CHECK: vldmia sp >> +; CHECK: bic sp, sp, #15 >> +; CHECK: vst1.64 {{.*}}sp @128 >> +; CHECK: vld1.64 {{.*}}sp @128 >> entry: >> %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) >> nounwind ; <<4 x float>> [#uses=1] >> store float 6.300000e+01, float* undef, align 4 >> >> Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll?rev=88874&r1=88873&r2=88874&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll (original) >> +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll Sun Nov 15 >> 15:45:34 2009 >> @@ -11,8 +11,9 @@ >> >> define arm_apcscc void @aaa(%quuz* %this, i8* %block) { >> ; CHECK: aaa: >> -; CHECK: vstmia sp >> -; CHECK: vldmia sp >> +; CHECK: bic sp, sp, #15 >> +; CHECK: vst1.64 {{.*}}sp @128 >> +; CHECK: vld1.64 {{.*}}sp @128 >> entry: >> %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) >> nounwind ; <<4 x float>> [#uses=1] >> store float 6.300000e+01, float* undef, align 4 >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From gohman at apple.com Mon Nov 16 14:45:51 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 16 Nov 2009 20:45:51 -0000 Subject: [llvm-commits] [llvm] r88959 - /llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h Message-ID: <200911162045.nAGKjpLQ004254@zion.cs.uiuc.edu> Author: djg Date: Mon Nov 16 14:45:50 2009 New Revision: 88959 URL: http://llvm.org/viewvc/llvm-project?rev=88959&view=rev Log: Revert 88957. This file uses CodeGenOpt, which is defined in TargetMachine.h. Modified: llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h Modified: llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h?rev=88959&r1=88958&r2=88959&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h Mon Nov 16 14:45:50 2009 @@ -15,11 +15,11 @@ #define LLVM_CODEGEN_MACHINE_FUNCTION_ANALYSIS_H #include "llvm/Pass.h" +#include "llvm/Target/TargetMachine.h" namespace llvm { class MachineFunction; -class TargetMachine; /// MachineFunctionAnalysis - This class is a Pass that manages a /// MachineFunction object. From grosbach at apple.com Mon Nov 16 15:03:58 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 Nov 2009 21:03:58 -0000 Subject: [llvm-commits] [llvm] r88961 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <200911162103.nAGL3w92005038@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 15:03:58 2009 New Revision: 88961 URL: http://llvm.org/viewvc/llvm-project?rev=88961&view=rev Log: make pass name a bit more clear Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=88961&r1=88960&r2=88961&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Nov 16 15:03:58 2009 @@ -1490,7 +1490,7 @@ } virtual const char *getPassName() const { - return "ARM Maximal Stack Alignment Calculator"; + return "ARM Stack Required Alignment Auto-Detector"; } virtual void getAnalysisUsage(AnalysisUsage &AU) const { From grosbach at apple.com Mon Nov 16 15:13:22 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 Nov 2009 21:13:22 -0000 Subject: [llvm-commits] [llvm] r88964 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <200911162113.nAGLDMkP005503@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 15:13:22 2009 New Revision: 88964 URL: http://llvm.org/viewvc/llvm-project?rev=88964&view=rev Log: Make the pass class name more explicit. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=88964&r1=88963&r2=88964&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Nov 16 15:13:22 2009 @@ -1464,9 +1464,9 @@ } namespace { - struct MSAC : public MachineFunctionPass { + struct MaximalStackAlignmentCalculator : public MachineFunctionPass { static char ID; - MSAC() : MachineFunctionPass(&ID) {} + MaximalStackAlignmentCalculator() : MachineFunctionPass(&ID) {} virtual bool runOnMachineFunction(MachineFunction &MF) { MachineFrameInfo *FFI = MF.getFrameInfo(); @@ -1499,10 +1499,12 @@ } }; - char MSAC::ID = 0; + char MaximalStackAlignmentCalculator::ID = 0; } FunctionPass* -llvm::createARMMaxStackAlignmentCalculatorPass() { return new MSAC(); } +llvm::createARMMaxStackAlignmentCalculatorPass() { + return new MaximalStackAlignmentCalculator(); +} #include "ARMGenRegisterInfo.inc" From dpatel at apple.com Mon Nov 16 15:24:33 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 16 Nov 2009 21:24:33 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r88967 - /llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Message-ID: <200911162124.nAGLOXQt005906@zion.cs.uiuc.edu> Author: dpatel Date: Mon Nov 16 15:24:33 2009 New Revision: 88967 URL: http://llvm.org/viewvc/llvm-project?rev=88967&view=rev Log: Use TrackingVH to hold debug info for a forward decl. Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=88967&r1=88966&r2=88967&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Mon Nov 16 15:24:33 2009 @@ -667,6 +667,7 @@ return FwdDecl; // Insert into the TypeCache so that recursive uses will find it. + llvm::TrackingVH FwdDeclNode = FwdDecl.getNode(); TypeCache[type] = WeakVH(FwdDecl.getNode()); // Convert all the elements. @@ -769,7 +770,7 @@ // Now that we have a real decl for the struct, replace anything using the // old decl with the new one. This will recursively update the debug info. - FwdDecl.replaceAllUsesWith(RealDecl); + llvm::DIDerivedType(FwdDeclNode).replaceAllUsesWith(RealDecl); return RealDecl; } From dpatel at apple.com Mon Nov 16 15:44:21 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 16 Nov 2009 21:44:21 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r88970 - /llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Message-ID: <200911162144.nAGLiL1d006683@zion.cs.uiuc.edu> Author: dpatel Date: Mon Nov 16 15:44:21 2009 New Revision: 88970 URL: http://llvm.org/viewvc/llvm-project?rev=88970&view=rev Log: Fix context for static variable. Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=88970&r1=88969&r2=88970&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Mon Nov 16 15:44:21 2009 @@ -276,8 +276,6 @@ context = TYPE_MAIN_VARIANT (TREE_TYPE (TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (decl))))); - if (context && !TYPE_P (context)) - context = NULL_TREE; if (context != NULL_TREE) return findRegion(context); } @@ -405,7 +403,7 @@ DispName = IDENTIFIER_POINTER(DECL_NAME(decl)); } - DebugFactory.CreateGlobalVariable(getOrCreateCompileUnit(Loc.file), + DebugFactory.CreateGlobalVariable(findRegion(decl), DispName, DispName, getLinkageName(decl), getOrCreateCompileUnit(Loc.file), Loc.line, From greened at obbligato.org Mon Nov 16 15:52:23 2009 From: greened at obbligato.org (David Greene) Date: Mon, 16 Nov 2009 21:52:23 -0000 Subject: [llvm-commits] [llvm] r88972 - /llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200911162152.nAGLqNP0007086@zion.cs.uiuc.edu> Author: greened Date: Mon Nov 16 15:52:23 2009 New Revision: 88972 URL: http://llvm.org/viewvc/llvm-project?rev=88972&view=rev Log: Fix an expensive-checks error. The Mask and LHSMask may not be of the same size, so don't do the transformation if they're different. Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=88972&r1=88971&r2=88972&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Mon Nov 16 15:52:23 2009 @@ -12917,29 +12917,33 @@ if (isa(RHS)) { std::vector LHSMask = getShuffleMask(LHSSVI); - std::vector NewMask; - for (unsigned i = 0, e = Mask.size(); i != e; ++i) - if (Mask[i] >= 2*e) - NewMask.push_back(2*e); - else - NewMask.push_back(LHSMask[Mask[i]]); + if (LHSMask.size() == Mask.size()) { + std::vector NewMask; + for (unsigned i = 0, e = Mask.size(); i != e; ++i) + if (Mask[i] >= 2*e) + NewMask.push_back(2*e); + else + NewMask.push_back(LHSMask[Mask[i]]); - // If the result mask is equal to the src shuffle or this shuffle mask, do - // the replacement. - if (NewMask == LHSMask || NewMask == Mask) { - unsigned LHSInNElts = - cast(LHSSVI->getOperand(0)->getType())->getNumElements(); - std::vector Elts; - for (unsigned i = 0, e = NewMask.size(); i != e; ++i) { - if (NewMask[i] >= LHSInNElts*2) { - Elts.push_back(UndefValue::get(Type::getInt32Ty(*Context))); - } else { - Elts.push_back(ConstantInt::get(Type::getInt32Ty(*Context), NewMask[i])); + // If the result mask is equal to the src shuffle or this + // shuffle mask, do the replacement. + if (NewMask == LHSMask || NewMask == Mask) { + unsigned LHSInNElts = + cast(LHSSVI->getOperand(0)->getType())-> + getNumElements(); + std::vector Elts; + for (unsigned i = 0, e = NewMask.size(); i != e; ++i) { + if (NewMask[i] >= LHSInNElts*2) { + Elts.push_back(UndefValue::get(Type::getInt32Ty(*Context))); + } else { + Elts.push_back(ConstantInt::get(Type::getInt32Ty(*Context), + NewMask[i])); + } } + return new ShuffleVectorInst(LHSSVI->getOperand(0), + LHSSVI->getOperand(1), + ConstantVector::get(Elts)); } - return new ShuffleVectorInst(LHSSVI->getOperand(0), - LHSSVI->getOperand(1), - ConstantVector::get(Elts)); } } } From dpatel at apple.com Mon Nov 16 15:53:40 2009 From: dpatel at apple.com (Devang Patel) Date: Mon, 16 Nov 2009 21:53:40 -0000 Subject: [llvm-commits] [llvm] r88973 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <200911162153.nAGLre0T007147@zion.cs.uiuc.edu> Author: dpatel Date: Mon Nov 16 15:53:40 2009 New Revision: 88973 URL: http://llvm.org/viewvc/llvm-project?rev=88973&view=rev Log: Revert r88939. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=88973&r1=88972&r2=88973&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Nov 16 15:53:40 2009 @@ -124,7 +124,7 @@ //===----------------------------------------------------------------------===// /// DbgVariable - This class is used to track local variable information. /// -class VISIBILITY_HIDDEN DbgVariable { +class DbgVariable { DIVariable Var; // Variable Descriptor. unsigned FrameIndex; // Variable frame index. DbgVariable *AbstractVar; // Abstract variable for this variable. @@ -146,7 +146,7 @@ /// DbgScope - This class is used to track scope information. /// class DbgConcreteScope; -class VISIBILITY_HIDDEN DbgScope { +class DbgScope { DbgScope *Parent; // Parent to this scope. DIDescriptor Desc; // Debug info descriptor for scope. WeakVH InlinedAtLocation; // Location at which scope is inlined. From evan.cheng at apple.com Mon Nov 16 15:56:03 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 16 Nov 2009 21:56:03 -0000 Subject: [llvm-commits] [llvm] r88974 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll Message-ID: <200911162156.nAGLu3oQ007244@zion.cs.uiuc.edu> Author: evancheng Date: Mon Nov 16 15:56:03 2009 New Revision: 88974 URL: http://llvm.org/viewvc/llvm-project?rev=88974&view=rev Log: - Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots. - Mark MOVUPSrm re-materializable. Added: llvm/trunk/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=88974&r1=88973&r2=88974&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Nov 16 15:56:03 2009 @@ -868,6 +868,7 @@ case X86::MOVSSrm: case X86::MOVSDrm: case X86::MOVAPSrm: + case X86::MOVUPSrm: case X86::MOVAPDrm: case X86::MOVDQArm: case X86::MMX_MOVD64rm: @@ -1966,8 +1967,7 @@ MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl &NewMIs) const { - bool isAligned = (RI.getStackAlignment() >= 16) || - RI.needsStackRealignment(MF); + bool isAligned = (*MMOBegin)->getAlignment() >= 16; unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); @@ -2060,8 +2060,7 @@ MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl &NewMIs) const { - bool isAligned = (RI.getStackAlignment() >= 16) || - RI.needsStackRealignment(MF); + bool isAligned = (*MMOBegin)->getAlignment() >= 16; unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); @@ -2638,17 +2637,16 @@ MachineFunction &MF = DAG.getMachineFunction(); if (FoldedLoad) { EVT VT = *RC->vt_begin(); - bool isAligned = (RI.getStackAlignment() >= 16) || - RI.needsStackRealignment(MF); + std::pair MMOs = + MF.extractLoadMemRefs(cast(N)->memoperands_begin(), + cast(N)->memoperands_end()); + bool isAligned = (*MMOs.first)->getAlignment() >= 16; Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, VT, MVT::Other, &AddrOps[0], AddrOps.size()); NewNodes.push_back(Load); // Preserve memory reference information. - std::pair MMOs = - MF.extractLoadMemRefs(cast(N)->memoperands_begin(), - cast(N)->memoperands_end()); cast(Load)->setMemRefs(MMOs.first, MMOs.second); } @@ -2676,8 +2674,11 @@ AddrOps.pop_back(); AddrOps.push_back(SDValue(NewNode, 0)); AddrOps.push_back(Chain); - bool isAligned = (RI.getStackAlignment() >= 16) || - RI.needsStackRealignment(MF); + std::pair MMOs = + MF.extractStoreMemRefs(cast(N)->memoperands_begin(), + cast(N)->memoperands_end()); + bool isAligned = (*MMOs.first)->getAlignment() >= 16; SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, TM), dl, MVT::Other, @@ -2685,10 +2686,6 @@ NewNodes.push_back(Store); // Preserve memory reference information. - std::pair MMOs = - MF.extractStoreMemRefs(cast(N)->memoperands_begin(), - cast(N)->memoperands_end()); cast(Load)->setMemRefs(MMOs.first, MMOs.second); } Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=88974&r1=88973&r2=88974&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Nov 16 15:56:03 2009 @@ -706,7 +706,7 @@ let neverHasSideEffects = 1 in def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movups\t{$src, $dst|$dst, $src}", []>; -let canFoldAsLoad = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movups\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (loadv4f32 addr:$src))]>; Added: llvm/trunk/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll?rev=88974&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll Mon Nov 16 15:56:03 2009 @@ -0,0 +1,28 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; rdar://7396984 + + at str = private constant [28 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxx\00", align 1 + +define void @t(i32 %count) ssp nounwind { +entry: +; CHECK: t: +; CHECK: movq ___stack_chk_guard at GOTPCREL(%rip) +; CHECK: movups L_str(%rip), %xmm0 + %tmp0 = alloca [60 x i8], align 1 + %tmp1 = getelementptr inbounds [60 x i8]* %tmp0, i64 0, i64 0 + br label %bb1 + +bb1: +; CHECK: LBB1_1: +; CHECK: movaps %xmm0, (%rsp) + %tmp2 = phi i32 [ %tmp3, %bb1 ], [ 0, %entry ] + call void @llvm.memcpy.i64(i8* %tmp1, i8* getelementptr inbounds ([28 x i8]* @str, i64 0, i64 0), i64 28, i32 1) + %tmp3 = add i32 %tmp2, 1 + %tmp4 = icmp eq i32 %tmp3, %count + br i1 %tmp4, label %bb2, label %bb1 + +bb2: + ret void +} + +declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind From echristo at apple.com Mon Nov 16 16:15:49 2009 From: echristo at apple.com (Eric Christopher) Date: Mon, 16 Nov 2009 14:15:49 -0800 Subject: [llvm-commits] [PATCH] Make X86-64 in the Large model always emit 64-bit calls In-Reply-To: References: <001636ed6e725660440478316be4@google.com> <0C21B7A2-76D2-48D4-8FE6-434AFC6FC5E1@apple.com> <072EB1A4-3A94-46BF-86CC-827F3F0E63E3@apple.com> Message-ID: <472518F2-8BB4-4A1C-BCD6-F5A3874E07C9@apple.com> >> > > Yep. That's what we're doing now after Jeffrey's patch. > >> If the client wants small code model, the memory manager must be able to ensure that. > > OK. I'll see what I can do to make sure this is actually working. I think we should go ahead and commit this and we'll make sure the small code model continues to work with other projects post checkin. -eric From echristo at apple.com Mon Nov 16 16:34:33 2009 From: echristo at apple.com (Eric Christopher) Date: Mon, 16 Nov 2009 22:34:33 -0000 Subject: [llvm-commits] [llvm] r88977 - in /llvm/trunk/include/llvm: ADT/StringRef.h CodeGen/AsmPrinter.h Message-ID: <200911162234.nAGMYXCx008868@zion.cs.uiuc.edu> Author: echristo Date: Mon Nov 16 16:34:32 2009 New Revision: 88977 URL: http://llvm.org/viewvc/llvm-project?rev=88977&view=rev Log: Fix unused variables warnings. Modified: llvm/trunk/include/llvm/ADT/StringRef.h llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Modified: llvm/trunk/include/llvm/ADT/StringRef.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringRef.h?rev=88977&r1=88976&r2=88977&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/StringRef.h (original) +++ llvm/trunk/include/llvm/ADT/StringRef.h Mon Nov 16 16:34:32 2009 @@ -198,7 +198,7 @@ /// find_first_of - Find the first character in the string that is \arg C, /// or npos if not found. Same as find. - size_type find_first_of(char C, size_t From = 0) const { return find(C); } + size_type find_first_of(char C, size_t = 0) const { return find(C); } /// find_first_of - Find the first character in the string that is in \arg /// Chars, or npos if not found. Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=88977&r1=88976&r2=88977&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Mon Nov 16 16:34:32 2009 @@ -180,11 +180,11 @@ /// EmitStartOfAsmFile - This virtual method can be overridden by targets /// that want to emit something at the start of their file. - virtual void EmitStartOfAsmFile(Module &M) {} + virtual void EmitStartOfAsmFile(Module &) {} /// EmitEndOfAsmFile - This virtual method can be overridden by targets that /// want to emit something at the end of their file. - virtual void EmitEndOfAsmFile(Module &M) {} + virtual void EmitEndOfAsmFile(Module &) {} /// doFinalization - Shut down the asmprinter. If you override this in your /// pass, you must make sure to call it explicitly. From daniel at zuster.org Mon Nov 16 16:37:53 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 16 Nov 2009 22:37:53 -0000 Subject: [llvm-commits] [llvm] r88978 - /llvm/trunk/Makefile.rules Message-ID: <200911162237.nAGMbrvn008988@zion.cs.uiuc.edu> Author: ddunbar Date: Mon Nov 16 16:37:52 2009 New Revision: 88978 URL: http://llvm.org/viewvc/llvm-project?rev=88978&view=rev Log: Add "Unoptimized" build (NO_DEBUG_SYMBOLS=1 ENABLE_OPTIMIZED=1), for reducing disk space, and increasing battery lifetime. :) Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=88978&r1=88977&r2=88978&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Mon Nov 16 16:37:52 2009 @@ -338,11 +338,19 @@ KEEP_SYMBOLS := 1 endif else - BuildMode := Debug - CXX.Flags += -g - C.Flags += -g - LD.Flags += -g - KEEP_SYMBOLS := 1 + ifdef NO_DEBUG_SYMBOLS + BuildMode := Unoptimized + CXX.Flags += + C.Flags += + LD.Flags += + KEEP_SYMBOLS := 1 + else + BuildMode := Debug + CXX.Flags += -g + C.Flags += -g + LD.Flags += -g + KEEP_SYMBOLS := 1 + endif endif ifeq ($(ENABLE_PROFILING),1) From daniel at zuster.org Mon Nov 16 16:38:01 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 16 Nov 2009 22:38:01 -0000 Subject: [llvm-commits] [llvm] r88979 - /llvm/trunk/Makefile Message-ID: <200911162238.nAGMc189009001@zion.cs.uiuc.edu> Author: ddunbar Date: Mon Nov 16 16:38:00 2009 New Revision: 88979 URL: http://llvm.org/viewvc/llvm-project?rev=88979&view=rev Log: Don't build examples by default, use BUILD_EXAMPLES=1 to build them. The only utility of this is testing that we keep the examples up to date, I will just make the buildbots run with this flag. Modified: llvm/trunk/Makefile Modified: llvm/trunk/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile?rev=88979&r1=88978&r2=88979&view=diff ============================================================================== --- llvm/trunk/Makefile (original) +++ llvm/trunk/Makefile Mon Nov 16 16:38:00 2009 @@ -32,7 +32,11 @@ else DIRS := lib/System lib/Support utils lib/VMCore lib tools/llvm-config \ tools runtime docs unittests - OPTIONAL_DIRS := examples projects bindings + OPTIONAL_DIRS := projects bindings +endif + +ifeq ($(BUILD_EXAMPLES),1) + OPTIONAL_DIRS += examples endif EXTRA_DIST := test unittests llvm.spec include win32 Xcode From jyasskin at google.com Mon Nov 16 16:41:33 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Mon, 16 Nov 2009 22:41:33 -0000 Subject: [llvm-commits] [llvm] r88984 - in /llvm/trunk: lib/ExecutionEngine/JIT/JITEmitter.cpp lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86JITInfo.cpp lib/Target/X86/X86TargetMachine.cpp test/Makefile unittests/ExecutionEngine/JIT/JITTest.cpp utils/lit/TestFormats.py Message-ID: <200911162241.nAGMfYYP009207@zion.cs.uiuc.edu> Author: jyasskin Date: Mon Nov 16 16:41:33 2009 New Revision: 88984 URL: http://llvm.org/viewvc/llvm-project?rev=88984&view=rev Log: Make X86-64 in the Large model always emit 64-bit calls. The large code model is documented at http://www.x86-64.org/documentation/abi.pdf and says that calls should assume their target doesn't live within the 32-bit pc-relative offset that fits in the call instruction. To do this, we turn off the global-address->target-global-address conversion in X86TargetLowering::LowerCall(). The first attempt at this broke the lazy JIT because it can separate the movabs(imm->reg) from the actual call instruction. The lazy JIT receives the address of the movabs as a relocation and needs to record the return address from the call; and then when that call happens, it needs to patch the movabs with the newly-compiled target. We could thread the call instruction into the relocation and record the movabs<->call mapping explicitly, but that seems to require at least as much new complication in the code generator as this change. To fix this, we make lazy functions _always_ go through a call stub. You'd think we'd only have to force lazy calls through a stub on difficult platforms, but that turns out to break indirect calls through a function pointer. The right fix for that is to distinguish between calls and address-of operations on uncompiled functions, but that's complex enough to leave for someone else to do. Another attempt at this defined a new CALL64i pseudo-instruction, which expanded to a 2-instruction sequence in the assembly output and was special-cased in the X86CodeEmitter's emitInstruction() function. That broke indirect calls in the same way as above. This patch also removes a hack forcing Darwin to the small code model. Without far-call-stubs, the small code model requires things of the JITMemoryManager that the DefaultJITMemoryManager can't provide. Thanks to echristo for lots of testing! Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86JITInfo.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.cpp llvm/trunk/test/Makefile llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp llvm/trunk/utils/lit/TestFormats.py Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp?rev=88984&r1=88983&r2=88984&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Mon Nov 16 16:41:33 2009 @@ -247,16 +247,6 @@ /// specified GV address. void *getGlobalValueIndirectSym(GlobalValue *V, void *GVAddress); - /// AddCallbackAtLocation - If the target is capable of rewriting an - /// instruction without the use of a stub, record the location of the use so - /// we know which function is being used at the location. - void *AddCallbackAtLocation(Function *F, void *Location) { - MutexGuard locked(TheJIT->lock); - /// Get the target-specific JIT resolver function. - state.AddCallSite(locked, Location, F); - return (void*)(intptr_t)LazyResolverFn; - } - void getRelocatableGVs(SmallVectorImpl &GVs, SmallVectorImpl &Ptrs); @@ -756,13 +746,6 @@ !MayNeedFarStub) return TheJIT->getPointerToFunction(F); - // Okay, the function has not been compiled yet, if the target callback - // mechanism is capable of rewriting the instruction directly, prefer to do - // that instead of emitting a stub. This uses the lazy resolver, so is not - // legal if lazy compilation is disabled. - if (!MayNeedFarStub && TheJIT->isCompilingLazily()) - return Resolver.AddCallbackAtLocation(F, Reference); - // Otherwise, we have to emit a stub. void *StubAddr = Resolver.getFunctionStub(F); Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=88984&r1=88983&r2=88984&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Mon Nov 16 16:41:33 2009 @@ -82,7 +82,7 @@ void emitPCRelativeBlockAddress(MachineBasicBlock *MBB); void emitGlobalAddress(GlobalValue *GV, unsigned Reloc, intptr_t Disp = 0, intptr_t PCAdj = 0, - bool MayNeedFarStub = false, bool Indirect = false); + bool Indirect = false); void emitExternalSymbolAddress(const char *ES, unsigned Reloc); void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0, intptr_t PCAdj = 0); @@ -176,7 +176,6 @@ void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, intptr_t Disp /* = 0 */, intptr_t PCAdj /* = 0 */, - bool MayNeedFarStub /* = false */, bool Indirect /* = false */) { intptr_t RelocCST = Disp; if (Reloc == X86::reloc_picrel_word) @@ -185,9 +184,9 @@ RelocCST = PCAdj; MachineRelocation MR = Indirect ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, - GV, RelocCST, MayNeedFarStub) + GV, RelocCST, false) : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, - GV, RelocCST, MayNeedFarStub); + GV, RelocCST, false); MCE.addRelocation(MR); // The relocated value will be added to the displacement if (Reloc == X86::reloc_absolute_dword) @@ -333,10 +332,9 @@ // do it, otherwise fallback to absolute (this is determined by IsPCRel). // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute - bool MayNeedFarStub = isa(RelocOp->getGlobal()); bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM); emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(), - Adj, MayNeedFarStub, Indirect); + Adj, Indirect); } else if (RelocOp->isSymbol()) { emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType); } else if (RelocOp->isCPI()) { @@ -633,14 +631,8 @@ } if (MO.isGlobal()) { - // Assume undefined functions may be outside the Small codespace. - bool MayNeedFarStub = - (Is64BitMode && - (TM.getCodeModel() == CodeModel::Large || - TM.getSubtarget().isTargetDarwin())) || - Opcode == X86::TAILJMPd; emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word, - MO.getOffset(), 0, MayNeedFarStub); + MO.getOffset(), 0); break; } @@ -681,10 +673,9 @@ if (Opcode == X86::MOV64ri) rt = X86::reloc_absolute_dword; // FIXME: add X86II flag? if (MO1.isGlobal()) { - bool MayNeedFarStub = isa(MO1.getGlobal()); bool Indirect = gvNeedsNonLazyPtr(MO1, TM); emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, - MayNeedFarStub, Indirect); + Indirect); } else if (MO1.isSymbol()) emitExternalSymbolAddress(MO1.getSymbolName(), rt); else if (MO1.isCPI()) @@ -790,10 +781,9 @@ if (Opcode == X86::MOV64ri32) rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag? if (MO1.isGlobal()) { - bool MayNeedFarStub = isa(MO1.getGlobal()); bool Indirect = gvNeedsNonLazyPtr(MO1, TM); emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, - MayNeedFarStub, Indirect); + Indirect); } else if (MO1.isSymbol()) emitExternalSymbolAddress(MO1.getSymbolName(), rt); else if (MO1.isCPI()) @@ -831,10 +821,9 @@ if (Opcode == X86::MOV64mi32) rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag? if (MO.isGlobal()) { - bool MayNeedFarStub = isa(MO.getGlobal()); bool Indirect = gvNeedsNonLazyPtr(MO, TM); emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0, - MayNeedFarStub, Indirect); + Indirect); } else if (MO.isSymbol()) emitExternalSymbolAddress(MO.getSymbolName(), rt); else if (MO.isCPI()) Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=88984&r1=88983&r2=88984&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Nov 16 16:41:33 2009 @@ -1937,9 +1937,19 @@ FPDiff, dl); } - // If the callee is a GlobalAddress node (quite common, every direct call is) - // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. - if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + bool WasGlobalOrExternal = false; + if (getTargetMachine().getCodeModel() == CodeModel::Large) { + assert(Is64Bit && "Large code model is only legal in 64-bit mode."); + // In the 64-bit large code model, we have to make all calls + // through a register, since the call instruction's 32-bit + // pc-relative offset may not be large enough to hold the whole + // address. + } else if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + WasGlobalOrExternal = true; + // If the callee is a GlobalAddress node (quite common, every direct call + // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack + // it. + // We should use extra load for direct calls to dllimported functions in // non-JIT mode. GlobalValue *GV = G->getGlobal(); @@ -1967,6 +1977,7 @@ G->getOffset(), OpFlags); } } else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) { + WasGlobalOrExternal = true; unsigned char OpFlags = 0; // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external @@ -1984,7 +1995,9 @@ Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), OpFlags); - } else if (isTailCall) { + } + + if (isTailCall && !WasGlobalOrExternal) { unsigned Opc = Is64Bit ? X86::R11 : X86::EAX; Chain = DAG.getCopyToReg(Chain, dl, Modified: llvm/trunk/lib/Target/X86/X86JITInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86JITInfo.cpp?rev=88984&r1=88983&r2=88984&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86JITInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86JITInfo.cpp Mon Nov 16 16:41:33 2009 @@ -367,8 +367,9 @@ // Rewrite the call target... so that we don't end up here every time we // execute the call. #if defined (X86_64_JIT) - if (!isStub) - *(intptr_t *)(RetAddr - 0xa) = NewVal; + assert(isStub && + "X86-64 doesn't support rewriting non-stub lazy compilation calls:" + " the call instruction varies too much."); #else *(intptr_t *)RetAddr = (intptr_t)(NewVal-RetAddr-4); #endif Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=88984&r1=88983&r2=88984&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Nov 16 16:41:33 2009 @@ -185,14 +185,8 @@ } // 64-bit JIT places everything in the same buffer except external functions. - // On Darwin, use small code model but hack the call instruction for - // externals. Elsewhere, do not assume globals are in the lower 4G. - if (Subtarget.is64Bit()) { - if (Subtarget.isTargetDarwin()) - setCodeModel(CodeModel::Small); - else + if (Subtarget.is64Bit()) setCodeModel(CodeModel::Large); - } PM.add(createX86CodeEmitterPass(*this, MCE)); @@ -211,14 +205,8 @@ } // 64-bit JIT places everything in the same buffer except external functions. - // On Darwin, use small code model but hack the call instruction for - // externals. Elsewhere, do not assume globals are in the lower 4G. - if (Subtarget.is64Bit()) { - if (Subtarget.isTargetDarwin()) - setCodeModel(CodeModel::Small); - else + if (Subtarget.is64Bit()) setCodeModel(CodeModel::Large); - } PM.add(createX86JITCodeEmitterPass(*this, JCE)); Modified: llvm/trunk/test/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Makefile?rev=88984&r1=88983&r2=88984&view=diff ============================================================================== --- llvm/trunk/test/Makefile (original) +++ llvm/trunk/test/Makefile Mon Nov 16 16:41:33 2009 @@ -77,12 +77,12 @@ # Both AuroraUX & Solaris do not have the -m flag for ulimit ifeq ($(HOST_OS),SunOS) -ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; ulimit -v 512000 ; +ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; else # !SunOS ifeq ($(HOST_OS),AuroraUX) -ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; ulimit -v 512000 ; +ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; else # !AuroraUX -ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; ulimit -m 512000 ; ulimit -v 512000 ; +ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; ulimit -m 512000 ; endif # AuroraUX endif # SunOS Modified: llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp?rev=88984&r1=88983&r2=88984&view=diff ============================================================================== --- llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp (original) +++ llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp Mon Nov 16 16:41:33 2009 @@ -26,10 +26,22 @@ #include "llvm/Support/IRBuilder.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/TypeBuilder.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetSelect.h" #include "llvm/Type.h" #include +#include + +#if HAVE_ERRNO_H +#include +#endif +#if HAVE_UNISTD_H +#include +#endif +#if _POSIX_MAPPED_FILES > 0 +#include +#endif using namespace llvm; @@ -177,6 +189,15 @@ } }; +void LoadAssemblyInto(Module *M, const char *assembly) { + SMDiagnostic Error; + bool success = NULL != ParseAssemblyString(assembly, M, Error, M->getContext()); + std::string errMsg; + raw_string_ostream os(errMsg); + Error.Print("", os); + ASSERT_TRUE(success) << os.str(); +} + class JITTest : public testing::Test { protected: virtual void SetUp() { @@ -191,12 +212,7 @@ } void LoadAssembly(const char *assembly) { - SMDiagnostic Error; - bool success = NULL != ParseAssemblyString(assembly, M, Error, Context); - std::string errMsg; - raw_string_ostream os(errMsg); - Error.Print("", os); - ASSERT_TRUE(success) << os.str(); + LoadAssemblyInto(M, assembly); } LLVMContext Context; @@ -498,6 +514,135 @@ } #endif +#if _POSIX_MAPPED_FILES > 0 && (defined (__x86_64__) || defined (_M_AMD64) || defined (_M_X64)) +class FarCallMemMgr : public RecordingJITMemoryManager { + void *MmapRegion; + size_t MmapSize; + uint8_t *NextStub; + uint8_t *NextFunction; + + public: + FarCallMemMgr() + : MmapSize(16ULL << 30) { // 16GB + MmapRegion = mmap(NULL, MmapSize, PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_PRIVATE | MAP_ANON, -1, 0); + if (MmapRegion == MAP_FAILED) { + ADD_FAILURE() << "mmap failed: " << strerror(errno); + } + // Set up the 16GB mapped region in several chunks: + // Stubs / ~5GB empty space / Function 1 / ~5GB empty space / Function 2 + // This way no two entities can use a 32-bit relative call to reach each other. + NextStub = static_cast(MmapRegion); + NextFunction = NextStub + (5ULL << 30); + + // Next, poison some of the memory so a wild call will eventually crash, + // even if memory was initialized by the OS to 0. We can't poison all of + // the memory because we want to be able to run on systems with less than + // 16GB of physical ram. + int TrapInstr = 0xCC; // INT 3 + memset(NextStub, TrapInstr, 1<<10); + for (size_t Offset = 1<<30; Offset < MmapSize; Offset += 1<<30) { + // Fill the 2KB around each GB boundary with trap instructions. This + // should ensure that we can't run into emitted functions without hitting + // the trap. + memset(NextStub + Offset - (1<<10), TrapInstr, 2<<10); + } + } + + ~FarCallMemMgr() { + EXPECT_EQ(0, munmap(MmapRegion, MmapSize)); + } + + virtual void setMemoryWritable() {} + virtual void setMemoryExecutable() {} + virtual uint8_t *startFunctionBody(const Function *F, + uintptr_t &ActualSize) { + ActualSize = 1 << 30; + uint8_t *Result = NextFunction; + NextFunction += 5ULL << 30; + return Result; + } + virtual void endFunctionBody(const Function*, uint8_t*, uint8_t*) {} + virtual uint8_t *allocateStub(const GlobalValue* F, unsigned StubSize, + unsigned Alignment) { + NextStub = reinterpret_cast( + uintptr_t(NextStub + Alignment - 1) &~ uintptr_t(Alignment - 1)); + uint8_t *Result = NextStub; + NextStub += StubSize; + return Result; + } +}; + +class FarTargetTest : public ::testing::TestWithParam { + protected: + FarTargetTest() : SavedCodeModel(TargetMachine::getCodeModel()) {} + ~FarTargetTest() { + TargetMachine::setCodeModel(SavedCodeModel); + } + + const CodeModel::Model SavedCodeModel; +}; +INSTANTIATE_TEST_CASE_P(CodeGenOpt, + FarTargetTest, + ::testing::Values(CodeGenOpt::None, + CodeGenOpt::Default)); + +TEST_P(FarTargetTest, CallToFarTarget) { + // x86-64 can only make direct calls to functions within 32 bits of + // the current PC. To call anything farther away, we have to load + // the address into a register and call through the register. The + // old JIT did this by allocating a stub for any far call. However, + // that stub needed to be within 32 bits of the callsite. Here we + // test that the JIT correctly deals with stubs and calls more than + // 32 bits away from the callsite. + + // Make sure the code generator is assuming code might be far away. + //TargetMachine::setCodeModel(CodeModel::Large); + + LLVMContext Context; + Module *M = new Module("
", Context); + ExistingModuleProvider *MP = new ExistingModuleProvider(M); + + JITMemoryManager *MemMgr = new FarCallMemMgr(); + std::string Error; + OwningPtr JIT(EngineBuilder(MP) + .setEngineKind(EngineKind::JIT) + .setErrorStr(&Error) + .setJITMemoryManager(MemMgr) + .setOptLevel(GetParam()) + .create()); + ASSERT_EQ(Error, ""); + TargetMachine::setCodeModel(CodeModel::Large); + + LoadAssemblyInto(M, + "define i32 @test() { " + " ret i32 7 " + "} " + " " + "define i32 @test_far() { " + " %result = call i32 @test() " + " ret i32 %result " + "} "); + // First, lay out a function early in memory. + Function *TestFunction = M->getFunction("test"); + int32_t (*TestFunctionPtr)() = reinterpret_cast( + (intptr_t)JIT->getPointerToFunction(TestFunction)); + ASSERT_EQ(7, TestFunctionPtr()); + + // We now lay out the far-away function. This should land >4GB away from test(). + Function *FarFunction = M->getFunction("test_far"); + int32_t (*FarFunctionPtr)() = reinterpret_cast( + (intptr_t)JIT->getPointerToFunction(FarFunction)); + + EXPECT_LT(1LL << 32, llabs(intptr_t(FarFunctionPtr) - intptr_t(TestFunctionPtr))) + << "Functions must be >32 bits apart or the test is meaningless."; + + // This used to result in a segfault in FarFunction, when its call instruction + // jumped to the wrong address. + EXPECT_EQ(7, FarFunctionPtr()); +} +#endif // Platform has far-call problem. + // This code is copied from JITEventListenerTest, but it only runs once for all // the tests in this directory. Everything seems fine, but that's strange // behavior. Modified: llvm/trunk/utils/lit/TestFormats.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/TestFormats.py?rev=88984&r1=88983&r2=88984&view=diff ============================================================================== --- llvm/trunk/utils/lit/TestFormats.py (original) +++ llvm/trunk/utils/lit/TestFormats.py Mon Nov 16 16:41:33 2009 @@ -53,8 +53,9 @@ def execute(self, test, litConfig): testPath,testName = os.path.split(test.getSourcePath()) - if not os.path.exists(testPath): - # Handle GTest typed tests, whose name includes a '/'. + while not os.path.exists(testPath): + # Handle GTest parametrized and typed tests, whose name includes + # some '/'s. testPath, namePrefix = os.path.split(testPath) testName = os.path.join(namePrefix, testName) From gohman at apple.com Mon Nov 16 16:49:38 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 16 Nov 2009 22:49:38 -0000 Subject: [llvm-commits] [llvm] r88985 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp Message-ID: <200911162249.nAGMnc7s009475@zion.cs.uiuc.edu> Author: djg Date: Mon Nov 16 16:49:38 2009 New Revision: 88985 URL: http://llvm.org/viewvc/llvm-project?rev=88985&view=rev Log: Initialize the new AsmPrinterFlags field to 0, fixing uses of uninitialized memory. Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=88985&r1=88984&r2=88985&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Mon Nov 16 16:49:38 2009 @@ -376,7 +376,7 @@ /// MachineInstr ctor - This constructor creates a dummy MachineInstr with /// TID NULL and no operands. MachineInstr::MachineInstr() - : TID(0), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), + : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) { // Make sure that we get added to a machine basicblock LeakDetector::addGarbageObject(this); @@ -396,7 +396,8 @@ /// TargetInstrDesc or the numOperands if it is not zero. (for /// instructions with variable number of operands). MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) - : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), Parent(0), + : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), + MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) { if (!NoImp && TID->getImplicitDefs()) for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) @@ -414,7 +415,7 @@ /// MachineInstr ctor - As above, but with a DebugLoc. MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl, bool NoImp) - : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), + : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) { if (!NoImp && TID->getImplicitDefs()) for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) @@ -434,7 +435,8 @@ /// basic block. /// MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid) - : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), Parent(0), + : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), + MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) { assert(MBB && "Cannot use inserting ctor with null basic block!"); if (TID->ImplicitDefs) @@ -454,7 +456,7 @@ /// MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, const TargetInstrDesc &tid) - : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), + : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) { assert(MBB && "Cannot use inserting ctor with null basic block!"); if (TID->ImplicitDefs) @@ -473,7 +475,7 @@ /// MachineInstr ctor - Copies MachineInstr arg exactly /// MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) - : TID(&MI.getDesc()), NumImplicitOps(0), + : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd), Parent(0), debugLoc(MI.getDebugLoc()) { Operands.reserve(MI.getNumOperands()); From grosbach at apple.com Mon Nov 16 17:19:29 2009 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 Nov 2009 23:19:29 -0000 Subject: [llvm-commits] [llvm] r88991 - /llvm/trunk/test/CodeGen/Thumb2/thumb2-shifter.ll Message-ID: <200911162319.nAGNJTUW010629@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 17:19:29 2009 New Revision: 88991 URL: http://llvm.org/viewvc/llvm-project?rev=88991&view=rev Log: Convert to FileCheck Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-shifter.ll Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-shifter.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-shifter.ll?rev=88991&r1=88990&r2=88991&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-shifter.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-shifter.ll Mon Nov 16 17:19:29 2009 @@ -1,22 +1,29 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep lsl -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep lsr -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep asr -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep ror -; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep mov +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; xRUN: llc < %s -march=thumb -mattr=+thumb2 | grep lsl +; xRUN: llc < %s -march=thumb -mattr=+thumb2 | grep lsr +; xRUN: llc < %s -march=thumb -mattr=+thumb2 | grep asr +; xRUN: llc < %s -march=thumb -mattr=+thumb2 | grep ror +; xRUN: llc < %s -march=thumb -mattr=+thumb2 | not grep mov define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) { +; CHECK: t2ADDrs_lsl +; CHECK: add.w r0, r0, r1, lsl #16 %A = shl i32 %Y, 16 %B = add i32 %X, %A ret i32 %B } define i32 @t2ADDrs_lsr(i32 %X, i32 %Y) { +; CHECK: t2ADDrs_lsr +; CHECK: add.w r0, r0, r1, lsr #16 %A = lshr i32 %Y, 16 %B = add i32 %X, %A ret i32 %B } define i32 @t2ADDrs_asr(i32 %X, i32 %Y) { +; CHECK: t2ADDrs_asr +; CHECK: add.w r0, r0, r1, asr #16 %A = ashr i32 %Y, 16 %B = add i32 %X, %A ret i32 %B @@ -24,6 +31,8 @@ ; i32 ror(n) = (x >> n) | (x << (32 - n)) define i32 @t2ADDrs_ror(i32 %X, i32 %Y) { +; CHECK: t2ADDrs_ror +; CHECK: add.w r0, r0, r1, ror #16 %A = lshr i32 %Y, 16 %B = shl i32 %Y, 16 %C = or i32 %B, %A @@ -32,6 +41,10 @@ } define i32 @t2ADDrs_noRegShift(i32 %X, i32 %Y, i8 %sh) { +; CHECK: t2ADDrs_noRegShift +; CHECK: uxtb r2, r2 +; CHECK: lsls r1, r2 +; CHECK: add r0, r1 %shift.upgrd.1 = zext i8 %sh to i32 %A = shl i32 %Y, %shift.upgrd.1 %B = add i32 %X, %A From jyasskin at google.com Mon Nov 16 17:32:30 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Mon, 16 Nov 2009 23:32:30 -0000 Subject: [llvm-commits] [llvm] r88994 - in /llvm/trunk: test/Makefile unittests/ExecutionEngine/JIT/JITTest.cpp Message-ID: <200911162332.nAGNWUE3011571@zion.cs.uiuc.edu> Author: jyasskin Date: Mon Nov 16 17:32:30 2009 New Revision: 88994 URL: http://llvm.org/viewvc/llvm-project?rev=88994&view=rev Log: Revert the test from r88984. It relies on being able to mmap 16GB of address space (though it only uses a small fraction of that), and the buildbots disallow that. Also add a comment to the Makefile's ulimit line warning future developers that changing it won't work. Modified: llvm/trunk/test/Makefile llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp Modified: llvm/trunk/test/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Makefile?rev=88994&r1=88993&r2=88994&view=diff ============================================================================== --- llvm/trunk/test/Makefile (original) +++ llvm/trunk/test/Makefile Mon Nov 16 17:32:30 2009 @@ -75,14 +75,16 @@ RUNTESTFLAGS += --ignore "$(strip $(IGNORE_TESTS))" endif +# ulimits like these are redundantly enforced by the buildbots, so +# just removing them here won't work. # Both AuroraUX & Solaris do not have the -m flag for ulimit ifeq ($(HOST_OS),SunOS) -ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; +ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; ulimit -v 512000 ; else # !SunOS ifeq ($(HOST_OS),AuroraUX) -ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; +ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; ulimit -v 512000 ; else # !AuroraUX -ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; ulimit -m 512000 ; +ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; ulimit -m 512000 ; ulimit -v 512000 ; endif # AuroraUX endif # SunOS Modified: llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp?rev=88994&r1=88993&r2=88994&view=diff ============================================================================== --- llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp (original) +++ llvm/trunk/unittests/ExecutionEngine/JIT/JITTest.cpp Mon Nov 16 17:32:30 2009 @@ -26,22 +26,10 @@ #include "llvm/Support/IRBuilder.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/TypeBuilder.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetSelect.h" #include "llvm/Type.h" #include -#include - -#if HAVE_ERRNO_H -#include -#endif -#if HAVE_UNISTD_H -#include -#endif -#if _POSIX_MAPPED_FILES > 0 -#include -#endif using namespace llvm; @@ -189,15 +177,6 @@ } }; -void LoadAssemblyInto(Module *M, const char *assembly) { - SMDiagnostic Error; - bool success = NULL != ParseAssemblyString(assembly, M, Error, M->getContext()); - std::string errMsg; - raw_string_ostream os(errMsg); - Error.Print("", os); - ASSERT_TRUE(success) << os.str(); -} - class JITTest : public testing::Test { protected: virtual void SetUp() { @@ -212,7 +191,12 @@ } void LoadAssembly(const char *assembly) { - LoadAssemblyInto(M, assembly); + SMDiagnostic Error; + bool success = NULL != ParseAssemblyString(assembly, M, Error, Context); + std::string errMsg; + raw_string_ostream os(errMsg); + Error.Print("", os); + ASSERT_TRUE(success) << os.str(); } LLVMContext Context; @@ -514,135 +498,6 @@ } #endif -#if _POSIX_MAPPED_FILES > 0 && (defined (__x86_64__) || defined (_M_AMD64) || defined (_M_X64)) -class FarCallMemMgr : public RecordingJITMemoryManager { - void *MmapRegion; - size_t MmapSize; - uint8_t *NextStub; - uint8_t *NextFunction; - - public: - FarCallMemMgr() - : MmapSize(16ULL << 30) { // 16GB - MmapRegion = mmap(NULL, MmapSize, PROT_READ | PROT_WRITE | PROT_EXEC, - MAP_PRIVATE | MAP_ANON, -1, 0); - if (MmapRegion == MAP_FAILED) { - ADD_FAILURE() << "mmap failed: " << strerror(errno); - } - // Set up the 16GB mapped region in several chunks: - // Stubs / ~5GB empty space / Function 1 / ~5GB empty space / Function 2 - // This way no two entities can use a 32-bit relative call to reach each other. - NextStub = static_cast(MmapRegion); - NextFunction = NextStub + (5ULL << 30); - - // Next, poison some of the memory so a wild call will eventually crash, - // even if memory was initialized by the OS to 0. We can't poison all of - // the memory because we want to be able to run on systems with less than - // 16GB of physical ram. - int TrapInstr = 0xCC; // INT 3 - memset(NextStub, TrapInstr, 1<<10); - for (size_t Offset = 1<<30; Offset < MmapSize; Offset += 1<<30) { - // Fill the 2KB around each GB boundary with trap instructions. This - // should ensure that we can't run into emitted functions without hitting - // the trap. - memset(NextStub + Offset - (1<<10), TrapInstr, 2<<10); - } - } - - ~FarCallMemMgr() { - EXPECT_EQ(0, munmap(MmapRegion, MmapSize)); - } - - virtual void setMemoryWritable() {} - virtual void setMemoryExecutable() {} - virtual uint8_t *startFunctionBody(const Function *F, - uintptr_t &ActualSize) { - ActualSize = 1 << 30; - uint8_t *Result = NextFunction; - NextFunction += 5ULL << 30; - return Result; - } - virtual void endFunctionBody(const Function*, uint8_t*, uint8_t*) {} - virtual uint8_t *allocateStub(const GlobalValue* F, unsigned StubSize, - unsigned Alignment) { - NextStub = reinterpret_cast( - uintptr_t(NextStub + Alignment - 1) &~ uintptr_t(Alignment - 1)); - uint8_t *Result = NextStub; - NextStub += StubSize; - return Result; - } -}; - -class FarTargetTest : public ::testing::TestWithParam { - protected: - FarTargetTest() : SavedCodeModel(TargetMachine::getCodeModel()) {} - ~FarTargetTest() { - TargetMachine::setCodeModel(SavedCodeModel); - } - - const CodeModel::Model SavedCodeModel; -}; -INSTANTIATE_TEST_CASE_P(CodeGenOpt, - FarTargetTest, - ::testing::Values(CodeGenOpt::None, - CodeGenOpt::Default)); - -TEST_P(FarTargetTest, CallToFarTarget) { - // x86-64 can only make direct calls to functions within 32 bits of - // the current PC. To call anything farther away, we have to load - // the address into a register and call through the register. The - // old JIT did this by allocating a stub for any far call. However, - // that stub needed to be within 32 bits of the callsite. Here we - // test that the JIT correctly deals with stubs and calls more than - // 32 bits away from the callsite. - - // Make sure the code generator is assuming code might be far away. - //TargetMachine::setCodeModel(CodeModel::Large); - - LLVMContext Context; - Module *M = new Module("
", Context); - ExistingModuleProvider *MP = new ExistingModuleProvider(M); - - JITMemoryManager *MemMgr = new FarCallMemMgr(); - std::string Error; - OwningPtr JIT(EngineBuilder(MP) - .setEngineKind(EngineKind::JIT) - .setErrorStr(&Error) - .setJITMemoryManager(MemMgr) - .setOptLevel(GetParam()) - .create()); - ASSERT_EQ(Error, ""); - TargetMachine::setCodeModel(CodeModel::Large); - - LoadAssemblyInto(M, - "define i32 @test() { " - " ret i32 7 " - "} " - " " - "define i32 @test_far() { " - " %result = call i32 @test() " - " ret i32 %result " - "} "); - // First, lay out a function early in memory. - Function *TestFunction = M->getFunction("test"); - int32_t (*TestFunctionPtr)() = reinterpret_cast( - (intptr_t)JIT->getPointerToFunction(TestFunction)); - ASSERT_EQ(7, TestFunctionPtr()); - - // We now lay out the far-away function. This should land >4GB away from test(). - Function *FarFunction = M->getFunction("test_far"); - int32_t (*FarFunctionPtr)() = reinterpret_cast( - (intptr_t)JIT->getPointerToFunction(FarFunction)); - - EXPECT_LT(1LL << 32, llabs(intptr_t(FarFunctionPtr) - intptr_t(TestFunctionPtr))) - << "Functions must be >32 bits apart or the test is meaningless."; - - // This used to result in a segfault in FarFunction, when its call instruction - // jumped to the wrong address. - EXPECT_EQ(7, FarFunctionPtr()); -} -#endif // Platform has far-call problem. - // This code is copied from JITEventListenerTest, but it only runs once for all // the tests in this directory. Everything seems fine, but that's strange // behavior. From gohman at apple.com Mon Nov 16 17:43:43 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 16 Nov 2009 23:43:43 -0000 Subject: [llvm-commits] [llvm] r88997 - /llvm/trunk/test/CodeGen/X86/tailcallstack64.ll Message-ID: <200911162343.nAGNhh69012130@zion.cs.uiuc.edu> Author: djg Date: Mon Nov 16 17:43:42 2009 New Revision: 88997 URL: http://llvm.org/viewvc/llvm-project?rev=88997&view=rev Log: Revert r87049, which was the workaround for the regression triggered by the recent FixedStackPseudoSourceValue-related changes, now that the specific bug that affected it is fixed, in r88954. Modified: llvm/trunk/test/CodeGen/X86/tailcallstack64.ll Modified: llvm/trunk/test/CodeGen/X86/tailcallstack64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tailcallstack64.ll?rev=88997&r1=88996&r2=88997&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/tailcallstack64.ll (original) +++ llvm/trunk/test/CodeGen/X86/tailcallstack64.ll Mon Nov 16 17:43:42 2009 @@ -5,10 +5,10 @@ ; CHECK: movl %edi, %eax ; Move param %in1 to temp register (%r10d). ; CHECK: movl 40(%rsp), %r10d -; Move result of addition to stack. -; CHECK: movl %eax, 40(%rsp) ; Move param %in2 to stack. ; CHECK: movl %r10d, 32(%rsp) +; Move result of addition to stack. +; CHECK: movl %eax, 40(%rsp) ; Eventually, do a TAILCALL ; CHECK: TAILCALL From gohman at apple.com Mon Nov 16 17:49:55 2009 From: gohman at apple.com (Dan Gohman) Date: Mon, 16 Nov 2009 23:49:55 -0000 Subject: [llvm-commits] [llvm] r88998 - /llvm/trunk/test/CodeGen/X86/2009-09-10-SpillComments.ll Message-ID: <200911162349.nAGNnunI012386@zion.cs.uiuc.edu> Author: djg Date: Mon Nov 16 17:49:55 2009 New Revision: 88998 URL: http://llvm.org/viewvc/llvm-project?rev=88998&view=rev Log: Fix this test - there don't appear to be any actual Reload Reuses in this testcase. Modified: llvm/trunk/test/CodeGen/X86/2009-09-10-SpillComments.ll Modified: llvm/trunk/test/CodeGen/X86/2009-09-10-SpillComments.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-09-10-SpillComments.ll?rev=88998&r1=88997&r2=88998&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-09-10-SpillComments.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-09-10-SpillComments.ll Mon Nov 16 17:49:55 2009 @@ -1,7 +1,6 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Spill" ; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Folded Spill" ; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Reload" -; RUN: llc < %s -mtriple=x86_64-unknown-linux | grep "Reload Reuse" %struct..0anon = type { i32 } %struct.rtvec_def = type { i32, [1 x %struct..0anon] } From johnny.chen at apple.com Mon Nov 16 17:57:56 2009 From: johnny.chen at apple.com (Johnny Chen) Date: Mon, 16 Nov 2009 23:57:56 -0000 Subject: [llvm-commits] [llvm] r89000 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <200911162357.nAGNvux4012768@zion.cs.uiuc.edu> Author: johnny Date: Mon Nov 16 17:57:56 2009 New Revision: 89000 URL: http://llvm.org/viewvc/llvm-project?rev=89000&view=rev Log: Set Rm bits of BX_RET to 0b1110 (R14); and set condition code bits of BRIND to 0b1110 (ALways). This is so that the disassembler decoder can distinguish among BX_RET, BRIND, and BXr9. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=89000&r1=88999&r2=89000&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Nov 16 17:57:56 2009 @@ -647,6 +647,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, "bx", "\tlr", [(ARMretflag)]> { + let Inst{3-0} = 0b1110; let Inst{7-4} = 0b0001; let Inst{19-8} = 0b111111111111; let Inst{27-20} = 0b00010010; @@ -659,6 +660,7 @@ let Inst{7-4} = 0b0001; let Inst{19-8} = 0b111111111111; let Inst{27-20} = 0b00010010; + let Inst{31-28} = 0b1110; } } From grosbach at apple.com Mon Nov 16 18:00:33 2009 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 17 Nov 2009 00:00:33 -0000 Subject: [llvm-commits] [llvm] r89001 - /llvm/trunk/test/CodeGen/Thumb2/thumb2-shifter.ll Message-ID: <200911170000.nAH00XgA012864@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 18:00:33 2009 New Revision: 89001 URL: http://llvm.org/viewvc/llvm-project?rev=89001&view=rev Log: Cleanup. Missed removing these when converting. Oops. Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-shifter.ll Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-shifter.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-shifter.ll?rev=89001&r1=89000&r2=89001&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-shifter.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-shifter.ll Mon Nov 16 18:00:33 2009 @@ -1,9 +1,4 @@ ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s -; xRUN: llc < %s -march=thumb -mattr=+thumb2 | grep lsl -; xRUN: llc < %s -march=thumb -mattr=+thumb2 | grep lsr -; xRUN: llc < %s -march=thumb -mattr=+thumb2 | grep asr -; xRUN: llc < %s -march=thumb -mattr=+thumb2 | grep ror -; xRUN: llc < %s -march=thumb -mattr=+thumb2 | not grep mov define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) { ; CHECK: t2ADDrs_lsl From grosbach at apple.com Mon Nov 16 18:03:38 2009 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 17 Nov 2009 00:03:38 -0000 Subject: [llvm-commits] [llvm] r89002 - /llvm/trunk/test/CodeGen/Thumb2/thumb2-sxt_rot.ll Message-ID: <200911170003.nAH03cuq012981@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 18:03:38 2009 New Revision: 89002 URL: http://llvm.org/viewvc/llvm-project?rev=89002&view=rev Log: Convert to FileCheck Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-sxt_rot.ll Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-sxt_rot.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-sxt_rot.ll?rev=89002&r1=89001&r2=89002&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-sxt_rot.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-sxt_rot.ll Mon Nov 16 18:03:38 2009 @@ -1,16 +1,15 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep sxtb | count 2 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep sxtb | grep ror | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep sxtab | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @test0(i8 %A) { +; CHECK: test0 +; CHECK: sxtb r0, r0 %B = sext i8 %A to i32 ret i32 %B } define i8 @test1(i32 %A) signext { +; CHECK: test1 +; CHECK: sxtb.w r0, r0, ror #8 %B = lshr i32 %A, 8 %C = shl i32 %A, 24 %D = or i32 %B, %C @@ -19,6 +18,9 @@ } define i32 @test2(i32 %A, i32 %X) signext { +; CHECK: test2 +; CHECK: lsrs r0, r0, #8 +; CHECK: sxtab r0, r1, r0 %B = lshr i32 %A, 8 %C = shl i32 %A, 24 %D = or i32 %B, %C From jyasskin at google.com Mon Nov 16 18:07:56 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Mon, 16 Nov 2009 16:07:56 -0800 Subject: [llvm-commits] [PATCH] Move stub allocation to the JITEmitter In-Reply-To: <0016e6470f36c55e08047834fde7@google.com> References: <0016e6470f36c55e08047834fde7@google.com> Message-ID: I've updated the patch to ToT at http://codereview.appspot.com/download/issue153044_2015.diff. On Thu, Nov 12, 2009 at 3:34 PM, wrote: > Reviewers: echristo_apple.com, > > Message: > This overlaps with http://codereview.appspot.com/154066 (far calls in > x86 large code model) some; I'll merge whichever gets committed second. > > I got nlewycky to confirm that the re-enabled tests do actually pass on > arm and ppc. > > Description: > * Move stub allocation inside the JITEmitter, instead of exposing a way > for each TargetJITInfo subclass to allocate its own stubs. This means > stubs aren't as exactly-sized anymore, but it lets us get rid of > TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC support > the eager JIT, fixing http://llvm.org/PR4816. > * Rename the JITEmitter's stub creation functions to describe the kind > of stub they create. So far, all of them create lazy-compilation stubs, > but they sometimes get used when far-call stubs are needed. That'll be > fixed in a future patch. > > Please review this at http://codereview.appspot.com/153044 > > Affected files: > ? M include/llvm/CodeGen/JITCodeEmitter.h > ? M include/llvm/Target/TargetJITInfo.h > ? M ? ? lib/ExecutionEngine/JIT/JITEmitter.cpp > ? M lib/Target/ARM/ARMJITInfo.cpp > ? M lib/Target/ARM/ARMJITInfo.h > ? M lib/Target/Alpha/AlphaJITInfo.cpp > ? M lib/Target/Alpha/AlphaJITInfo.h > ? M lib/Target/PowerPC/PPCJITInfo.cpp > ? M lib/Target/PowerPC/PPCJITInfo.h > ? M lib/Target/X86/X86JITInfo.cpp > ? M lib/Target/X86/X86JITInfo.h > ? M ? ? unittests/ExecutionEngine/JIT/JITTest.cpp > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From grosbach at apple.com Mon Nov 16 18:20:27 2009 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 17 Nov 2009 00:20:27 -0000 Subject: [llvm-commits] [llvm] r89007 - in /llvm/trunk/test/CodeGen/Thumb2: thumb2-select_xform.ll thumb2-smla.ll thumb2-smul.ll thumb2-str_pre.ll thumb2-uxtb.ll Message-ID: <200911170020.nAH0KRMA013728@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 18:20:26 2009 New Revision: 89007 URL: http://llvm.org/viewvc/llvm-project?rev=89007&view=rev Log: Convert to FileCheck Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-select_xform.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-smla.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-smul.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-str_pre.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-select_xform.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-select_xform.ll?rev=89007&r1=89006&r2=89007&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-select_xform.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-select_xform.ll Mon Nov 16 18:20:26 2009 @@ -1,8 +1,12 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep mov | count 3 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep mvn | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep it | count 3 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { +; CHECK: t1 +; CHECK: mvn r0, #-2147483648 +; CHECK: cmp r2, #10 +; CHECK: add.w r0, r1, r0 +; CHECK: it gt +; CHECK: movgt r0, r1 %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 2147483647 %tmp3 = add i32 %tmp2, %b @@ -10,6 +14,12 @@ } define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind { +; CHECK: t2 +; CHECK: add.w r0, r1, #-2147483648 +; CHECK: cmp r2, #10 +; CHECK: it gt +; CHECK: movgt r0, r1 + %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 2147483648 %tmp3 = add i32 %tmp2, %b @@ -17,6 +27,11 @@ } define i32 @t3(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { +; CHECK: t3 +; CHECK: sub.w r0, r1, #10 +; CHECK: cmp r2, #10 +; CHECK: it gt +; CHECK: movgt r0, r1 %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 10 %tmp3 = sub i32 %b, %tmp2 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-smla.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-smla.ll?rev=89007&r1=89006&r2=89007&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-smla.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-smla.ll Mon Nov 16 18:20:26 2009 @@ -1,7 +1,8 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep smlabt | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @f3(i32 %a, i16 %x, i32 %y) { +; CHECK: f3 +; CHECK: smlabt r0, r1, r2, r0 %tmp = sext i16 %x to i32 ; [#uses=1] %tmp2 = ashr i32 %y, 16 ; [#uses=1] %tmp3 = mul i32 %tmp2, %tmp ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-smul.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-smul.ll?rev=89007&r1=89006&r2=89007&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-smul.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-smul.ll Mon Nov 16 18:20:26 2009 @@ -1,12 +1,11 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep smulbt | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep smultt | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s @x = weak global i16 0 ; [#uses=1] @y = weak global i16 0 ; [#uses=0] define i32 @f1(i32 %y) { +; CHECK: f1 +; CHECK: smulbt r0, r1, r0 %tmp = load i16* @x ; [#uses=1] %tmp1 = add i16 %tmp, 2 ; [#uses=1] %tmp2 = sext i16 %tmp1 to i32 ; [#uses=1] @@ -16,6 +15,8 @@ } define i32 @f2(i32 %x, i32 %y) { +; CHECK: f2 +; CHECK: smultt r0, r1, r0 %tmp1 = ashr i32 %x, 16 ; [#uses=1] %tmp3 = ashr i32 %y, 16 ; [#uses=1] %tmp4 = mul i32 %tmp3, %tmp1 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-str_pre.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-str_pre.ll?rev=89007&r1=89006&r2=89007&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-str_pre.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-str_pre.ll Mon Nov 16 18:20:26 2009 @@ -1,7 +1,8 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep {str.*\\!} | count 2 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define void @test1(i32* %X, i32* %A, i32** %dest) { +; CHECK: test1 +; CHECK: str r1, [r0, #+16]! %B = load i32* %A ; [#uses=1] %Y = getelementptr i32* %X, i32 4 ; [#uses=2] store i32 %B, i32* %Y @@ -10,6 +11,8 @@ } define i16* @test2(i16* %X, i32* %A) { +; CHECK: test2 +; CHECK: strh r1, [r0, #+8]! %B = load i32* %A ; [#uses=1] %Y = getelementptr i16* %X, i32 4 ; [#uses=2] %tmp = trunc i32 %B to i16 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll?rev=89007&r1=89006&r2=89007&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll Mon Nov 16 18:20:26 2009 @@ -1,36 +1,47 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep uxt | count 10 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @test1(i32 %x) { +; CHECK: test1 +; CHECK: uxtb16.w r0, r0 %tmp1 = and i32 %x, 16711935 ; [#uses=1] ret i32 %tmp1 } define i32 @test2(i32 %x) { +; CHECK: test2 +; CHECK: uxtb16.w r0, r0, ror #8 %tmp1 = lshr i32 %x, 8 ; [#uses=1] %tmp2 = and i32 %tmp1, 16711935 ; [#uses=1] ret i32 %tmp2 } define i32 @test3(i32 %x) { +; CHECK: test3 +; CHECK: uxtb16.w r0, r0, ror #8 %tmp1 = lshr i32 %x, 8 ; [#uses=1] %tmp2 = and i32 %tmp1, 16711935 ; [#uses=1] ret i32 %tmp2 } define i32 @test4(i32 %x) { +; CHECK: test4 +; CHECK: uxtb16.w r0, r0, ror #8 %tmp1 = lshr i32 %x, 8 ; [#uses=1] %tmp6 = and i32 %tmp1, 16711935 ; [#uses=1] ret i32 %tmp6 } define i32 @test5(i32 %x) { +; CHECK: test5 +; CHECK: uxtb16.w r0, r0, ror #8 %tmp1 = lshr i32 %x, 8 ; [#uses=1] %tmp2 = and i32 %tmp1, 16711935 ; [#uses=1] ret i32 %tmp2 } define i32 @test6(i32 %x) { +; CHECK: test6 +; CHECK: uxtb16.w r0, r0, ror #16 %tmp1 = lshr i32 %x, 16 ; [#uses=1] %tmp2 = and i32 %tmp1, 255 ; [#uses=1] %tmp4 = shl i32 %x, 16 ; [#uses=1] @@ -40,6 +51,8 @@ } define i32 @test7(i32 %x) { +; CHECK: test7 +; CHECK: uxtb16.w r0, r0, ror #16 %tmp1 = lshr i32 %x, 16 ; [#uses=1] %tmp2 = and i32 %tmp1, 255 ; [#uses=1] %tmp4 = shl i32 %x, 16 ; [#uses=1] @@ -49,6 +62,8 @@ } define i32 @test8(i32 %x) { +; CHECK: test8 +; CHECK: uxtb16.w r0, r0, ror #24 %tmp1 = shl i32 %x, 8 ; [#uses=1] %tmp2 = and i32 %tmp1, 16711680 ; [#uses=1] %tmp5 = lshr i32 %x, 24 ; [#uses=1] @@ -57,6 +72,8 @@ } define i32 @test9(i32 %x) { +; CHECK: test9 +; CHECK: uxtb16.w r0, r0, ror #24 %tmp1 = lshr i32 %x, 24 ; [#uses=1] %tmp4 = shl i32 %x, 8 ; [#uses=1] %tmp5 = and i32 %tmp4, 16711680 ; [#uses=1] @@ -65,6 +82,13 @@ } define i32 @test10(i32 %p0) { +; CHECK: test10 +; CHECK: mov.w r1, #16253176 +; CHECK: and.w r0, r1, r0, lsr #7 +; CHECK: lsrs r1, r0, #5 +; CHECK: uxtb16.w r1, r1 +; CHECK: orr.w r0, r1, r0 + %tmp1 = lshr i32 %p0, 7 ; [#uses=1] %tmp2 = and i32 %tmp1, 16253176 ; [#uses=2] %tmp4 = lshr i32 %tmp2, 5 ; [#uses=1] From evan.cheng at apple.com Mon Nov 16 18:23:22 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 17 Nov 2009 00:23:22 -0000 Subject: [llvm-commits] [llvm] r89011 - in /llvm/trunk/lib/Target/X86: X86InstrInfo.cpp X86InstrSSE.td Message-ID: <200911170023.nAH0NMwS013872@zion.cs.uiuc.edu> Author: evancheng Date: Mon Nov 16 18:23:22 2009 New Revision: 89011 URL: http://llvm.org/viewvc/llvm-project?rev=89011&view=rev Log: A few more instructions that should be marked re-materializable. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=89011&r1=89010&r2=89011&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Nov 16 18:23:22 2009 @@ -869,10 +869,13 @@ case X86::MOVSDrm: case X86::MOVAPSrm: case X86::MOVUPSrm: + case X86::MOVUPSrm_Int: case X86::MOVAPDrm: case X86::MOVDQArm: case X86::MMX_MOVD64rm: - case X86::MMX_MOVQ64rm: { + case X86::MMX_MOVQ64rm: + case X86::FsMOVAPSrm: + case X86::FsMOVAPDrm: { // Loads from constant pools are trivially rematerializable. if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() && Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=89011&r1=89010&r2=89011&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Nov 16 18:23:22 2009 @@ -497,7 +497,7 @@ // Alias instruction to load FR32 from f128mem using movaps. Upper bits are // disregarded. -let canFoldAsLoad = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src), "movaps\t{$src, $dst|$dst, $src}", [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>; @@ -715,7 +715,7 @@ [(store (v4f32 VR128:$src), addr:$dst)]>; // Intrinsic forms of MOVUPS load and store -let canFoldAsLoad = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movups\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>; @@ -1256,7 +1256,7 @@ // Alias instruction to load FR64 from f128mem using movapd. Upper bits are // disregarded. -let canFoldAsLoad = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src), "movapd\t{$src, $dst|$dst, $src}", [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>; From jyasskin at google.com Mon Nov 16 18:43:13 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Tue, 17 Nov 2009 00:43:13 -0000 Subject: [llvm-commits] [llvm] r89014 - in /llvm/trunk: include/llvm/GlobalVariable.h lib/VMCore/Globals.cpp Message-ID: <200911170043.nAH0hDeK014598@zion.cs.uiuc.edu> Author: jyasskin Date: Mon Nov 16 18:43:13 2009 New Revision: 89014 URL: http://llvm.org/viewvc/llvm-project?rev=89014&view=rev Log: In GlobalVariable::setInitializer, assert that the initializer has the right type. Modified: llvm/trunk/include/llvm/GlobalVariable.h llvm/trunk/lib/VMCore/Globals.cpp Modified: llvm/trunk/include/llvm/GlobalVariable.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/GlobalVariable.h?rev=89014&r1=89013&r2=89014&view=diff ============================================================================== --- llvm/trunk/include/llvm/GlobalVariable.h (original) +++ llvm/trunk/include/llvm/GlobalVariable.h Mon Nov 16 18:43:13 2009 @@ -99,18 +99,10 @@ assert(hasInitializer() && "GV doesn't have initializer!"); return static_cast(Op<0>().get()); } - inline void setInitializer(Constant *CPV) { - if (CPV == 0) { - if (hasInitializer()) { - Op<0>().set(0); - NumOperands = 0; - } - } else { - if (!hasInitializer()) - NumOperands = 1; - Op<0>().set(CPV); - } - } + /// setInitializer - Sets the initializer for this global variable, removing + /// any existing initializer if InitVal==NULL. If this GV has type T*, the + /// initializer must have type T. + void setInitializer(Constant *InitVal); /// If the value is a global constant, its value is immutable throughout the /// runtime execution of the program. Assigning a value into the constant Modified: llvm/trunk/lib/VMCore/Globals.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Globals.cpp?rev=89014&r1=89013&r2=89014&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Globals.cpp (original) +++ llvm/trunk/lib/VMCore/Globals.cpp Mon Nov 16 18:43:13 2009 @@ -171,6 +171,21 @@ this->setOperand(0, cast(To)); } +void GlobalVariable::setInitializer(Constant *InitVal) { + if (InitVal == 0) { + if (hasInitializer()) { + Op<0>().set(0); + NumOperands = 0; + } + } else { + assert(InitVal->getType() == getType()->getElementType() && + "Initializer type must match GlobalVariable type"); + if (!hasInitializer()) + NumOperands = 1; + Op<0>().set(InitVal); + } +} + /// copyAttributesFrom - copy all additional attributes (those not needed to /// create a GlobalVariable) from the GlobalVariable Src to this one. void GlobalVariable::copyAttributesFrom(const GlobalValue *Src) { From dpatel at apple.com Mon Nov 16 18:47:06 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 17 Nov 2009 00:47:06 -0000 Subject: [llvm-commits] [llvm] r89016 - /llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Message-ID: <200911170047.nAH0l6Cd014739@zion.cs.uiuc.edu> Author: dpatel Date: Mon Nov 16 18:47:06 2009 New Revision: 89016 URL: http://llvm.org/viewvc/llvm-project?rev=89016&view=rev Log: Remove debug info attached with an instruction. Modified: llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Modified: llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp?rev=89016&r1=89015&r2=89016&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Mon Nov 16 18:47:06 2009 @@ -202,53 +202,35 @@ // llvm.dbg.region.end calls, and any globals they point to if now dead. static bool StripDebugInfo(Module &M) { + bool Changed = false; + // Remove all of the calls to the debugger intrinsics, and remove them from // the module. - Function *FuncStart = M.getFunction("llvm.dbg.func.start"); - Function *StopPoint = M.getFunction("llvm.dbg.stoppoint"); - Function *RegionStart = M.getFunction("llvm.dbg.region.start"); - Function *RegionEnd = M.getFunction("llvm.dbg.region.end"); - Function *Declare = M.getFunction("llvm.dbg.declare"); - - if (FuncStart) { - while (!FuncStart->use_empty()) { - CallInst *CI = cast(FuncStart->use_back()); - CI->eraseFromParent(); - } - FuncStart->eraseFromParent(); - } - if (StopPoint) { - while (!StopPoint->use_empty()) { - CallInst *CI = cast(StopPoint->use_back()); - CI->eraseFromParent(); - } - StopPoint->eraseFromParent(); - } - if (RegionStart) { - while (!RegionStart->use_empty()) { - CallInst *CI = cast(RegionStart->use_back()); - CI->eraseFromParent(); - } - RegionStart->eraseFromParent(); - } - if (RegionEnd) { - while (!RegionEnd->use_empty()) { - CallInst *CI = cast(RegionEnd->use_back()); - CI->eraseFromParent(); - } - RegionEnd->eraseFromParent(); - } - if (Declare) { + if (Function *Declare = M.getFunction("llvm.dbg.declare")) { while (!Declare->use_empty()) { CallInst *CI = cast(Declare->use_back()); CI->eraseFromParent(); } Declare->eraseFromParent(); + Changed = true; } NamedMDNode *NMD = M.getNamedMetadata("llvm.dbg.gv"); - if (NMD) + if (NMD) { + Changed = true; NMD->eraseFromParent(); + } + MetadataContext &TheMetadata = M.getContext().getMetadata(); + unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); + if (!MDDbgKind) + return Changed; + + for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) + for (Function::iterator FI = MI->begin(), FE = MI->end(); FI != FE; + ++FI) + for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; + ++BI) + TheMetadata.removeMD(MDDbgKind, BI); return true; } From gohman at apple.com Mon Nov 16 18:47:23 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 17 Nov 2009 00:47:23 -0000 Subject: [llvm-commits] [llvm] r89017 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200911170047.nAH0lNDT014760@zion.cs.uiuc.edu> Author: djg Date: Mon Nov 16 18:47:23 2009 New Revision: 89017 URL: http://llvm.org/viewvc/llvm-project?rev=89017&view=rev Log: Remove the optimizations that convert BRCOND and BR_CC into unconditional branches or fallthroghes. Instcombine/SimplifyCFG should be simplifying branches with known conditions. This fixes some problems caused by these transformations not updating the MachineBasicBlock CFG. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=89017&r1=89016&r2=89017&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Nov 16 18:47:23 2009 @@ -4442,14 +4442,13 @@ SDValue Chain = N->getOperand(0); SDValue N1 = N->getOperand(1); SDValue N2 = N->getOperand(2); - ConstantSDNode *N1C = dyn_cast(N1); - // never taken branch, fold to chain - if (N1C && N1C->isNullValue()) - return Chain; - // unconditional branch - if (N1C && N1C->getAPIntValue() == 1) - return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); + // If N is a constant we could fold this into a fallthrough or unconditional + // branch. However that doesn't happen very often in normal code, because + // Instcombine/SimplifyCFG should have handled the available opportunities. + // If we did this folding here, it would be necessary to update the + // MachineBasicBlock CFG, which is awkward. + // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal // on the target. if (N1.getOpcode() == ISD::SETCC && @@ -4516,22 +4515,18 @@ CondCodeSDNode *CC = cast(N->getOperand(1)); SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); + // If N is a constant we could fold this into a fallthrough or unconditional + // branch. However that doesn't happen very often in normal code, because + // Instcombine/SimplifyCFG should have handled the available opportunities. + // If we did this folding here, it would be necessary to update the + // MachineBasicBlock CFG, which is awkward. + // Use SimplifySetCC to simplify SETCC's. SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), CondLHS, CondRHS, CC->get(), N->getDebugLoc(), false); if (Simp.getNode()) AddToWorkList(Simp.getNode()); - ConstantSDNode *SCCC = dyn_cast_or_null(Simp.getNode()); - - // fold br_cc true, dest -> br dest (unconditional branch) - if (SCCC && !SCCC->isNullValue()) - return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, - N->getOperand(0), N->getOperand(4)); - // fold br_cc false, dest -> unconditional fall through - if (SCCC && SCCC->isNullValue()) - return N->getOperand(0); - // fold to a simpler setcc if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, From evan.cheng at apple.com Mon Nov 16 18:55:56 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 17 Nov 2009 00:55:56 -0000 Subject: [llvm-commits] [llvm] r89019 - in /llvm/trunk: lib/Target/X86/X86Instr64bit.td test/CodeGen/X86/2009-11-16-MachineLICM.ll Message-ID: <200911170055.nAH0tu2e015042@zion.cs.uiuc.edu> Author: evancheng Date: Mon Nov 16 18:55:55 2009 New Revision: 89019 URL: http://llvm.org/viewvc/llvm-project?rev=89019&view=rev Log: MOV64rm should be marked isReMaterializable. Added: llvm/trunk/test/CodeGen/X86/2009-11-16-MachineLICM.ll Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=89019&r1=89018&r2=89019&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Mon Nov 16 18:55:55 2009 @@ -309,7 +309,7 @@ [(set GR64:$dst, i64immSExt32:$src)]>; } -let canFoldAsLoad = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), "mov{q}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (load addr:$src))]>; Added: llvm/trunk/test/CodeGen/X86/2009-11-16-MachineLICM.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-11-16-MachineLICM.ll?rev=89019&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-11-16-MachineLICM.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-11-16-MachineLICM.ll Mon Nov 16 18:55:55 2009 @@ -0,0 +1,42 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; rdar://7395200 + + at g = common global [4 x float] zeroinitializer, align 16 ; <[4 x float]*> [#uses=4] + +define void @foo(i32 %n, float* nocapture %x) nounwind ssp { +entry: +; CHECK: foo: + %0 = icmp sgt i32 %n, 0 ; [#uses=1] + br i1 %0, label %bb.nph, label %return + +bb.nph: ; preds = %entry +; CHECK: movq _g at GOTPCREL(%rip), %rcx + %tmp = zext i32 %n to i64 ; [#uses=1] + br label %bb + +bb: ; preds = %bb, %bb.nph +; CHECK: LBB1_2: + %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; [#uses=2] + %tmp9 = shl i64 %indvar, 2 ; [#uses=4] + %tmp1016 = or i64 %tmp9, 1 ; [#uses=1] + %scevgep = getelementptr float* %x, i64 %tmp1016 ; [#uses=1] + %tmp1117 = or i64 %tmp9, 2 ; [#uses=1] + %scevgep12 = getelementptr float* %x, i64 %tmp1117 ; [#uses=1] + %tmp1318 = or i64 %tmp9, 3 ; [#uses=1] + %scevgep14 = getelementptr float* %x, i64 %tmp1318 ; [#uses=1] + %x_addr.03 = getelementptr float* %x, i64 %tmp9 ; [#uses=1] + %1 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 0), align 16 ; [#uses=1] + store float %1, float* %x_addr.03, align 4 + %2 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 1), align 4 ; [#uses=1] + store float %2, float* %scevgep, align 4 + %3 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 2), align 8 ; [#uses=1] + store float %3, float* %scevgep12, align 4 + %4 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 3), align 4 ; [#uses=1] + store float %4, float* %scevgep14, align 4 + %indvar.next = add i64 %indvar, 1 ; [#uses=2] + %exitcond = icmp eq i64 %indvar.next, %tmp ; [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} From stoklund at 2pi.dk Mon Nov 16 19:07:22 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 17 Nov 2009 01:07:22 -0000 Subject: [llvm-commits] [llvm] r89021 - in /llvm/trunk: lib/CodeGen/PHIElimination.cpp test/CodeGen/X86/2008-04-15-LiveVariableBug.ll test/CodeGen/X86/stack-color-with-reg.ll Message-ID: <200911170107.nAH17Mms015475@zion.cs.uiuc.edu> Author: stoklund Date: Mon Nov 16 19:07:22 2009 New Revision: 89021 URL: http://llvm.org/viewvc/llvm-project?rev=89021&view=rev Log: Enable -split-phi-edges by default Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89021&r1=89020&r2=89021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Mon Nov 16 19:07:22 2009 @@ -39,7 +39,7 @@ static cl::opt SplitEdges("split-phi-edges", cl::desc("Split critical edges during phi elimination"), - cl::init(false), cl::Hidden); + cl::init(true), cl::Hidden); char PHIElimination::ID = 0; static RegisterPass Modified: llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll?rev=89021&r1=89020&r2=89021&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll Mon Nov 16 19:07:22 2009 @@ -1,5 +1,9 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin -; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local + +; Globally enabling -split-phi-edges causes LiveVariables to always run. +; LiveVariables trips up the local allocator on this test. +; It doesn't understand the subtleties of subregister imp-kills. +; DONT: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local %struct.CGPoint = type { double, double } %struct.NSArray = type { %struct.NSObject } Modified: llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll?rev=89021&r1=89020&r2=89021&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll (original) +++ llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll Mon Nov 16 19:07:22 2009 @@ -1,6 +1,8 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t ; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 6 -; RUN: grep asm-printer %t | grep 177 + +; Obviously the only correct way of translating this function is with 175 instructions. Not 177 (duh!) +; RUN: grep asm-printer %t | grep 175 type { [62 x %struct.Bitvec*] } ; type %0 type { i8* } ; type %1 From evan.cheng at apple.com Mon Nov 16 19:10:26 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 16 Nov 2009 17:10:26 -0800 Subject: [llvm-commits] [llvm] r89021 - in /llvm/trunk: lib/CodeGen/PHIElimination.cpp test/CodeGen/X86/2008-04-15-LiveVariableBug.ll test/CodeGen/X86/stack-color-with-reg.ll In-Reply-To: <200911170107.nAH17Mms015475@zion.cs.uiuc.edu> References: <200911170107.nAH17Mms015475@zion.cs.uiuc.edu> Message-ID: On Nov 16, 2009, at 5:07 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Mon Nov 16 19:07:22 2009 > New Revision: 89021 > > URL: http://llvm.org/viewvc/llvm-project?rev=89021&view=rev > Log: > Enable -split-phi-edges by default > > Modified: > llvm/trunk/lib/CodeGen/PHIElimination.cpp > llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll > llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll > > Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89021&r1=89020&r2=89021&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) > +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Mon Nov 16 19:07:22 2009 > @@ -39,7 +39,7 @@ > static cl::opt > SplitEdges("split-phi-edges", > cl::desc("Split critical edges during phi elimination"), > - cl::init(false), cl::Hidden); > + cl::init(true), cl::Hidden); Any reason to keep the option around? Evan > > char PHIElimination::ID = 0; > static RegisterPass > > Modified: llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll?rev=89021&r1=89020&r2=89021&view=diff > > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll Mon Nov 16 19:07:22 2009 > @@ -1,5 +1,9 @@ > ; RUN: llc < %s -mtriple=x86_64-apple-darwin > -; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local > + > +; Globally enabling -split-phi-edges causes LiveVariables to always run. > +; LiveVariables trips up the local allocator on this test. > +; It doesn't understand the subtleties of subregister imp-kills. > +; DONT: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local > > %struct.CGPoint = type { double, double } > %struct.NSArray = type { %struct.NSObject } > > Modified: llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll?rev=89021&r1=89020&r2=89021&view=diff > > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll (original) > +++ llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll Mon Nov 16 19:07:22 2009 > @@ -1,6 +1,8 @@ > ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t > ; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 6 > -; RUN: grep asm-printer %t | grep 177 > + > +; Obviously the only correct way of translating this function is with 175 instructions. Not 177 (duh!) > +; RUN: grep asm-printer %t | grep 175 > > type { [62 x %struct.Bitvec*] } ; type %0 > type { i8* } ; type %1 > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stoklund at 2pi.dk Mon Nov 16 19:15:58 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 16 Nov 2009 17:15:58 -0800 Subject: [llvm-commits] [llvm] r89021 - in /llvm/trunk: lib/CodeGen/PHIElimination.cpp test/CodeGen/X86/2008-04-15-LiveVariableBug.ll test/CodeGen/X86/stack-color-with-reg.ll In-Reply-To: References: <200911170107.nAH17Mms015475@zion.cs.uiuc.edu> Message-ID: On Nov 16, 2009, at 5:10 PM, Evan Cheng wrote: > > On Nov 16, 2009, at 5:07 PM, Jakob Stoklund Olesen wrote: > >> Author: stoklund >> Date: Mon Nov 16 19:07:22 2009 >> New Revision: 89021 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=89021&view=rev >> Log: >> Enable -split-phi-edges by default >> >> Modified: >> llvm/trunk/lib/CodeGen/PHIElimination.cpp >> llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll >> llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll >> >> Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89021&r1=89020&r2=89021&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) >> +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Mon Nov 16 19:07:22 2009 >> @@ -39,7 +39,7 @@ >> static cl::opt >> SplitEdges("split-phi-edges", >> cl::desc("Split critical edges during phi elimination"), >> - cl::init(false), cl::Hidden); >> + cl::init(true), cl::Hidden); > > Any reason to keep the option around? Only because there is still a bit of wonkyness. Like the tests below. I'll remove it later. >> >> ============================================================================== >> --- llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll (original) >> +++ llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll Mon Nov 16 19:07:22 2009 >> @@ -1,5 +1,9 @@ >> ; RUN: llc < %s -mtriple=x86_64-apple-darwin >> -; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local >> + >> +; Globally enabling -split-phi-edges causes LiveVariables to always run. >> +; LiveVariables trips up the local allocator on this test. >> +; It doesn't understand the subtleties of subregister imp-kills. >> +; DONT: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local >> >> %struct.CGPoint = type { double, double } >> %struct.NSArray = type { %struct.NSObject } >> >> Modified: llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll?rev=89021&r1=89020&r2=89021&view=diff >> >> ============================================================================== >> --- llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll (original) >> +++ llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll Mon Nov 16 19:07:22 2009 >> @@ -1,6 +1,8 @@ >> ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t >> ; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 6 >> -; RUN: grep asm-printer %t | grep 177 >> + >> +; Obviously the only correct way of translating this function is with 175 instructions. Not 177 (duh!) >> +; RUN: grep asm-printer %t | grep 175 From grosbach at apple.com Mon Nov 16 19:21:04 2009 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 17 Nov 2009 01:21:04 -0000 Subject: [llvm-commits] [llvm] r89022 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <200911170121.nAH1L4uo016029@zion.cs.uiuc.edu> Author: grosbach Date: Mon Nov 16 19:21:04 2009 New Revision: 89022 URL: http://llvm.org/viewvc/llvm-project?rev=89022&view=rev Log: When moving a block for table jumps, make sure the prior block terminator is analyzable so it can be updated. If it's not, be safe and don't move the block. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=89022&r1=89021&r2=89022&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Mon Nov 16 19:21:04 2009 @@ -1749,21 +1749,23 @@ // heuristic. FIXME: We can definitely improve it. MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; + SmallVector CondPrior; + MachineFunction::iterator BBi = BB; + MachineFunction::iterator OldPrior = prior(BBi); // If the block terminator isn't analyzable, don't try to move the block - if (TII->AnalyzeBranch(*BB, TBB, FBB, Cond)) - return NULL; + bool B = TII->AnalyzeBranch(*BB, TBB, FBB, Cond); - // If the block ends in an unconditional branch, move it. Be paranoid + // If the block ends in an unconditional branch, move it. The prior block + // has to have an analyzable terminator for us to move this one. Be paranoid // and make sure we're not trying to move the entry block of the function. - if (Cond.empty() && BB != MF.begin()) { - MachineFunction::iterator BBi = BB; - MachineFunction::iterator OldPrior = prior(BBi); + if (!B && Cond.empty() && BB != MF.begin() && + !TII->AnalyzeBranch(*OldPrior, TBB, FBB, CondPrior)) { BB->moveAfter(JTBB); OldPrior->updateTerminator(); BB->updateTerminator(); // Update numbering to account for the block being moved. - MF.RenumberBlocks(OldPrior); + MF.RenumberBlocks(); ++NumJTMoved; return NULL; } From isanbard at gmail.com Mon Nov 16 19:23:53 2009 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 17 Nov 2009 01:23:53 -0000 Subject: [llvm-commits] [llvm] r89024 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfException.cpp DwarfException.h Message-ID: <200911170123.nAH1Nrls016147@zion.cs.uiuc.edu> Author: void Date: Mon Nov 16 19:23:53 2009 New Revision: 89024 URL: http://llvm.org/viewvc/llvm-project?rev=89024&view=rev Log: Refactor the code that creates the "dot-label" difference. This may be used in more than one place. No intended functionality change. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp?rev=89024&r1=89023&r2=89024&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Mon Nov 16 19:23:53 2009 @@ -74,6 +74,25 @@ return 0; } +/// CreateLabelDiff - Emit a label and subtract it from the expression we +/// already have. This is equivalent to emitting "foo - .", but we have to emit +/// the label for "." directly. +const MCExpr *DwarfException::CreateLabelDiff(const MCExpr *ExprRef, + const char *LabelName, + unsigned Index) { + SmallString<64> Name; + raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() + << LabelName << Asm->getFunctionNumber() + << "_" << Index; + MCSymbol *DotSym = Asm->OutContext.GetOrCreateSymbol(Name.str()); + Asm->OutStreamer.EmitLabel(DotSym); + + return MCBinaryExpr::CreateSub(ExprRef, + MCSymbolRefExpr::Create(DotSym, + Asm->OutContext), + Asm->OutContext); +} + /// EmitCIE - Emit a Common Information Entry (CIE). This holds information that /// is shared among many Frame Description Entries. There is at least one CIE /// in every non-empty .debug_frame section. @@ -176,24 +195,10 @@ // If there is a personality, we need to indicate the function's location. if (PersonalityRef) { - // If the reference to the personality function symbol is not already - // pc-relative, then we need to subtract our current address from it. Do - // this by emitting a label and subtracting it from the expression we - // already have. This is equivalent to emitting "foo - .", but we have to - // emit the label for "." directly. - if (!IsPersonalityPCRel) { - SmallString<64> Name; - raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() - << "personalityref_addr" << Asm->getFunctionNumber() << "_" << Index; - MCSymbol *DotSym = Asm->OutContext.GetOrCreateSymbol(Name.str()); - Asm->OutStreamer.EmitLabel(DotSym); - - PersonalityRef = - MCBinaryExpr::CreateSub(PersonalityRef, - MCSymbolRefExpr::Create(DotSym,Asm->OutContext), - Asm->OutContext); - } - + if (!IsPersonalityPCRel) + PersonalityRef = CreateLabelDiff(PersonalityRef, "personalityref_addr", + Index); + O << MAI->getData32bitsDirective(); PersonalityRef->print(O, MAI); Asm->EOL("Personality"); Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h?rev=89024&r1=89023&r2=89024&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h Mon Nov 16 19:23:53 2009 @@ -25,6 +25,7 @@ struct LandingPadInfo; class MachineModuleInfo; class MCAsmInfo; +class MCExpr; class Timer; class raw_ostream; @@ -172,6 +173,11 @@ const SmallVectorImpl &FirstActions); void EmitExceptionTable(); + /// CreateLabelDiff - Emit a label and subtract it from the expression we + /// already have. This is equivalent to emitting "foo - .", but we have to + /// emit the label for "." directly. + const MCExpr *CreateLabelDiff(const MCExpr *ExprRef, const char *LabelName, + unsigned Index); public: //===--------------------------------------------------------------------===// // Main entry points. From vkutuzov at accesssoftek.com Mon Nov 16 20:05:03 2009 From: vkutuzov at accesssoftek.com (Viktor Kutuzov) Date: Mon, 16 Nov 2009 18:05:03 -0800 Subject: [llvm-commits] [PATCH] LTO code generator options In-Reply-To: <38a0d8450911141921r7deec8b3k91e06950263f0485@mail.gmail.com> References: <04F6B1512E264B27AEE607542FCDD113@andreic6e7fe55> <9C7CA4093A8F41D7AD156ED3CF854D17@andreic6e7fe55> <38a0d8450911101625s5e3b7cb0m31ec0ce4d4144dc@mail.gmail.com> <38a0d8450911121059n6a0d3eb0ka34711d931c7675e@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BA@mail.accesssoftek.com>, <38a0d8450911141921r7deec8b3k91e06950263f0485@mail.gmail.com> Message-ID: <6AE1604EE3EC5F4296C096518C6B77EEFD4607BF@mail.accesssoftek.com> Please find the attached patch. Does this look like what you want to see? I have moved the check for Darwin OS insode the getArchNameForAssembler which makes it OS and Vendor independent. This is what we wanted from the beginning, aren't we? And added missed ppc64. Thanks for catching this. Thanks, Viktor. ________________________________________ From: Rafael Espindola [espindola at google.com] Sent: Saturday, November 14, 2009 7:21 PM To: Viktor Kutuzov Cc: Commit Messages and Patches for LLVM Subject: Re: [llvm-commits] [PATCH] LTO code generator options 2009/11/12 Viktor Kutuzov : > Thanks, Rafael. > > I have split this patch to a set of smaller ones. Hope this will make it easier to review. > Please find attached 2 patches: > > * one adds to the Triple class > - a new getAssemblerArchName method, and > - assignment operators for the std::string and StringRef types; > > * the other one adds to the SubtargetFeature class > - a new getDefaultSubTargetTripleFeatures method (code moved from the LTOModule class), > - AddFeatures methods, and > - hasFeature method. > > I'll send the patch that use these changes after these 2 patches will be submitted. I actually find it easier to review code when it is next to its use. Examples *) I am not sure that including a llvm::Triple = std::string is the best design. Without its use it is hard to tell. *) Looking only at getArchNameForDarwinArchTriplePart it is hard to check that it covers all cases. The attached patch was extracted from your previous one. It includes only the -arch option refactoring bits. I find it easier to read. For example, I now noticed that you forgot to handle ppc64 :-) I also adjusted it a bit for the coding style: *) Try not to nest too much, so return null early if vendor != apple *) Don't include an else after a return Would you mind completing just this part first? > Viktor. Thanks, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-lto-codegen-target-triple-asm.diff Type: application/octet-stream Size: 4772 bytes Desc: llvm-lto-codegen-target-triple-asm.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091116/3f670d7a/attachment.obj From resistor at mac.com Tue Nov 17 01:06:10 2009 From: resistor at mac.com (Owen Anderson) Date: Tue, 17 Nov 2009 07:06:10 -0000 Subject: [llvm-commits] [llvm] r89056 - /llvm/trunk/lib/Support/Timer.cpp Message-ID: <200911170706.nAH76Acl027464@zion.cs.uiuc.edu> Author: resistor Date: Tue Nov 17 01:06:10 2009 New Revision: 89056 URL: http://llvm.org/viewvc/llvm-project?rev=89056&view=rev Log: Fix a race condition in the Timer class. Modified: llvm/trunk/lib/Support/Timer.cpp Modified: llvm/trunk/lib/Support/Timer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=89056&r1=89055&r2=89056&view=diff ============================================================================== --- llvm/trunk/lib/Support/Timer.cpp (original) +++ llvm/trunk/lib/Support/Timer.cpp Tue Nov 17 01:06:10 2009 @@ -145,7 +145,7 @@ static ManagedStatic > ActiveTimers; void Timer::startTimer() { - sys::SmartScopedLock L(Lock); + sys::SmartScopedLock L(*TimerLock); Started = true; ActiveTimers->push_back(this); TimeRecord TR = getTimeRecord(true); @@ -157,7 +157,7 @@ } void Timer::stopTimer() { - sys::SmartScopedLock L(Lock); + sys::SmartScopedLock L(*TimerLock); TimeRecord TR = getTimeRecord(false); Elapsed += TR.Elapsed; UserTime += TR.UserTime; @@ -175,27 +175,11 @@ } void Timer::sum(const Timer &T) { - if (&T < this) { - T.Lock.acquire(); - Lock.acquire(); - } else { - Lock.acquire(); - T.Lock.acquire(); - } - Elapsed += T.Elapsed; UserTime += T.UserTime; SystemTime += T.SystemTime; MemUsed += T.MemUsed; PeakMem += T.PeakMem; - - if (&T < this) { - T.Lock.release(); - Lock.release(); - } else { - Lock.release(); - T.Lock.release(); - } } /// addPeakMemoryMeasurement - This method should be called whenever memory @@ -203,14 +187,12 @@ /// currently active timers, which will be printed when the timer group prints /// void Timer::addPeakMemoryMeasurement() { + sys::SmartScopedLock L(*TimerLock); size_t MemUsed = getMemUsage(); for (std::vector::iterator I = ActiveTimers->begin(), - E = ActiveTimers->end(); I != E; ++I) { - (*I)->Lock.acquire(); + E = ActiveTimers->end(); I != E; ++I) (*I)->PeakMem = std::max((*I)->PeakMem, MemUsed-(*I)->PeakMemBase); - (*I)->Lock.release(); - } } //===----------------------------------------------------------------------===// @@ -280,14 +262,7 @@ } void Timer::print(const Timer &Total, raw_ostream &OS) { - if (&Total < this) { - Total.Lock.acquire(); - Lock.acquire(); - } else { - Lock.acquire(); - Total.Lock.acquire(); - } - + sys::SmartScopedLock L(*TimerLock); if (Total.UserTime) printVal(UserTime, Total.UserTime, OS); if (Total.SystemTime) @@ -310,14 +285,6 @@ OS << Name << "\n"; Started = false; // Once printed, don't print again - - if (&Total < this) { - Total.Lock.release(); - Lock.release(); - } else { - Lock.release(); - Total.Lock.release(); - } } // GetLibSupportInfoOutputFile - Return a file stream to print our output on... From lhames at gmail.com Tue Nov 17 01:19:51 2009 From: lhames at gmail.com (Lang Hames) Date: Tue, 17 Nov 2009 07:19:51 -0000 Subject: [llvm-commits] [llvm] r89059 - /llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Message-ID: <200911170719.nAH7JpjE027981@zion.cs.uiuc.edu> Author: lhames Date: Tue Nov 17 01:19:50 2009 New Revision: 89059 URL: http://llvm.org/viewvc/llvm-project?rev=89059&view=rev Log: Fixed call to wrong constructor. Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h?rev=89059&r1=89058&r2=89059&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SlotIndexes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Tue Nov 17 01:19:50 2009 @@ -699,7 +699,7 @@ if (miItr == mbb->end()) { // If this is the last instr in the MBB then we need to fix up the bb // range: - mbbRangeItr->second.second = SlotIndex(newIndex, SlotIndex::STORE); + mbbRangeItr->second.second = SlotIndex(newEntry, SlotIndex::STORE); } // Renumber if we need to. From nicholas at mxc.ca Tue Nov 17 01:52:10 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 17 Nov 2009 07:52:10 -0000 Subject: [llvm-commits] [llvm] r89062 - /llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Message-ID: <200911170752.nAH7qAQ6029196@zion.cs.uiuc.edu> Author: nicholas Date: Tue Nov 17 01:52:09 2009 New Revision: 89062 URL: http://llvm.org/viewvc/llvm-project?rev=89062&view=rev Log: Fail less mysteriously; inform the user that their LLVM was not built with libffi support and that the interpreter can't call external functions without it. Patch by Timo Juhani Lindfors! Fixes PR5466. Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp?rev=89062&r1=89061&r2=89062&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Tue Nov 17 01:52:09 2009 @@ -284,6 +284,9 @@ else llvm_report_error("Tried to execute an unknown external function: " + F->getType()->getDescription() + " " +F->getName()); +#ifndef USE_LIBFFI + errs() << "Recompiling LLVM with --enable-libffi might help.\n"; +#endif return GenericValue(); } From baldrick at free.fr Tue Nov 17 01:54:21 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 17 Nov 2009 08:54:21 +0100 Subject: [llvm-commits] [llvm] r88979 - /llvm/trunk/Makefile In-Reply-To: <200911162238.nAGMc189009001@zion.cs.uiuc.edu> References: <200911162238.nAGMc189009001@zion.cs.uiuc.edu> Message-ID: <4B0256AD.2040909@free.fr> Hi Daniel, > Don't build examples by default, use BUILD_EXAMPLES=1 to build them. The only utility of this is testing that we keep the examples up to date, I will just make the buildbots run with this flag. is this really a good idea? If someone breaks an example, wouldn't it be better for them to discover that directly themselves rather than via a buildbot? And what about newcomers who want to build examples - aren't they going to have a hard time working out how to build the examples? Ciao, Duncan. From nicholas at mxc.ca Tue Nov 17 02:10:24 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 17 Nov 2009 00:10:24 -0800 Subject: [llvm-commits] [llvm] r88939 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp In-Reply-To: <200911161920.nAGJKm72032127@zion.cs.uiuc.edu> References: <200911161920.nAGJKm72032127@zion.cs.uiuc.edu> Message-ID: <4B025A70.9050906@mxc.ca> Devang Patel wrote: > Author: dpatel > Date: Mon Nov 16 13:20:48 2009 > New Revision: 88939 > > URL: http://llvm.org/viewvc/llvm-project?rev=88939&view=rev > Log: > Add VISIBILITY_HIDDEN marker. No. Do not do this. Are these classes supposed to be public or not? If they're not public they need to be in an anonymous namespace, and VISIBILITY_HIDDEN removed. If they are public, they shouldn't be hidden at all. The policy in LLVM is that no .cpp file should have VISIBILITY_HIDDEN symbols. I am going to revert this patch. Nick > Modified: > llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=88939&r1=88938&r2=88939&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Nov 16 13:20:48 2009 > @@ -124,7 +124,7 @@ > //===----------------------------------------------------------------------===// > /// DbgVariable - This class is used to track local variable information. > /// > -class DbgVariable { > +class VISIBILITY_HIDDEN DbgVariable { > DIVariable Var; // Variable Descriptor. > unsigned FrameIndex; // Variable frame index. > DbgVariable *AbstractVar; // Abstract variable for this variable. > @@ -146,7 +146,7 @@ > /// DbgScope - This class is used to track scope information. > /// > class DbgConcreteScope; > -class DbgScope { > +class VISIBILITY_HIDDEN DbgScope { > DbgScope *Parent; // Parent to this scope. > DIDescriptor Desc; // Debug info descriptor for scope. > WeakVH InlinedAtLocation; // Location at which scope is inlined. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From nicholas at mxc.ca Tue Nov 17 02:11:44 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 17 Nov 2009 08:11:44 -0000 Subject: [llvm-commits] [llvm] r89066 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <200911170811.nAH8Biwc029979@zion.cs.uiuc.edu> Author: nicholas Date: Tue Nov 17 02:11:44 2009 New Revision: 89066 URL: http://llvm.org/viewvc/llvm-project?rev=89066&view=rev Log: Revert r88939. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=89066&r1=89065&r2=89066&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Nov 17 02:11:44 2009 @@ -48,7 +48,7 @@ //===----------------------------------------------------------------------===// /// CompileUnit - This dwarf writer support class manages information associate /// with a source file. -class VISIBILITY_HIDDEN CompileUnit { +class CompileUnit { /// ID - File identifier for source. /// unsigned ID; @@ -241,7 +241,7 @@ /// DbgConcreteScope - This class is used to track a scope that holds concrete /// instance information. /// -class VISIBILITY_HIDDEN DbgConcreteScope : public DbgScope { +class DbgConcreteScope : public DbgScope { CompileUnit *Unit; DIE *Die; // Debug info for this concrete scope. public: From nicholas at mxc.ca Tue Nov 17 02:28:35 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 17 Nov 2009 00:28:35 -0800 Subject: [llvm-commits] [llvm] r88939 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp In-Reply-To: <4B025A70.9050906@mxc.ca> References: <200911161920.nAGJKm72032127@zion.cs.uiuc.edu> <4B025A70.9050906@mxc.ca> Message-ID: <4B025EB3.7080203@mxc.ca> Nick Lewycky wrote: > Devang Patel wrote: >> Author: dpatel >> Date: Mon Nov 16 13:20:48 2009 >> New Revision: 88939 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=88939&view=rev >> Log: >> Add VISIBILITY_HIDDEN marker. > > No. Do not do this. Okay, I didn't see pr5507 before responding here. Since I yelled at you about it, I'll apologize by fixing that bug. Sorry! Nick > Are these classes supposed to be public or not? If they're not public > they need to be in an anonymous namespace, and VISIBILITY_HIDDEN > removed. If they are public, they shouldn't be hidden at all. > > The policy in LLVM is that no .cpp file should have VISIBILITY_HIDDEN > symbols. I am going to revert this patch. > > Nick > >> Modified: >> llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp >> >> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=88939&r1=88938&r2=88939&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) >> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Nov 16 13:20:48 2009 >> @@ -124,7 +124,7 @@ >> //===----------------------------------------------------------------------===// >> /// DbgVariable - This class is used to track local variable information. >> /// >> -class DbgVariable { >> +class VISIBILITY_HIDDEN DbgVariable { >> DIVariable Var; // Variable Descriptor. >> unsigned FrameIndex; // Variable frame index. >> DbgVariable *AbstractVar; // Abstract variable for this variable. >> @@ -146,7 +146,7 @@ >> /// DbgScope - This class is used to track scope information. >> /// >> class DbgConcreteScope; >> -class DbgScope { >> +class VISIBILITY_HIDDEN DbgScope { >> DbgScope *Parent; // Parent to this scope. >> DIDescriptor Desc; // Debug info descriptor for scope. >> WeakVH InlinedAtLocation; // Location at which scope is inlined. >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From baldrick at free.fr Tue Nov 17 02:34:52 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 17 Nov 2009 08:34:52 -0000 Subject: [llvm-commits] [llvm] r89067 - in /llvm/trunk/include/llvm/Support: Compiler.h IRBuilder.h Message-ID: <200911170834.nAH8Yqdl030993@zion.cs.uiuc.edu> Author: baldrick Date: Tue Nov 17 02:34:52 2009 New Revision: 89067 URL: http://llvm.org/viewvc/llvm-project?rev=89067&view=rev Log: Following a suggestion of Daniel Dunbar, stop people passing the name as the isSigned bool to CreateIntCast by having this resolve to a call to a private method, rather than by using a gcc attribute. Modified: llvm/trunk/include/llvm/Support/Compiler.h llvm/trunk/include/llvm/Support/IRBuilder.h Modified: llvm/trunk/include/llvm/Support/Compiler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Compiler.h?rev=89067&r1=89066&r2=89067&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Compiler.h (original) +++ llvm/trunk/include/llvm/Support/Compiler.h Tue Nov 17 02:34:52 2009 @@ -78,12 +78,4 @@ #define NORETURN #endif -#if defined(__GNUC__) && ((__GNUC__ > 4)||(__GNUC__ == 4 && __GNUC_MINOR__ > 2)) -#define ERROR_IF_USED __attribute__((error("wrong usage"))) -#elif defined(__APPLE__) -#define ERROR_IF_USED __attribute__((unavailable)) -#else -#define ERROR_IF_USED -#endif - #endif Modified: llvm/trunk/include/llvm/Support/IRBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=89067&r1=89066&r2=89067&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) +++ llvm/trunk/include/llvm/Support/IRBuilder.h Tue Nov 17 02:34:52 2009 @@ -709,9 +709,11 @@ return Folder.CreateIntCast(VC, DestTy, isSigned); return Insert(CastInst::CreateIntegerCast(V, DestTy, isSigned), Name); } - // Provided to resolve 'CreateIntCast(Ptr, Ptr, "...")', instead of converting - // the string to 'bool' for the isSigned parameter. - ERROR_IF_USED Value *CreateIntCast(Value *, const Type *, const char *); +private: + // Provided to resolve 'CreateIntCast(Ptr, Ptr, "...")', giving a compile time + // error, instead of converting the string to bool for the isSigned parameter. + Value *CreateIntCast(Value *, const Type *, const char *); // DO NOT IMPLEMENT +public: Value *CreateFPCast(Value *V, const Type *DestTy, const Twine &Name = "") { if (V->getType() == DestTy) return V; From baldrick at free.fr Tue Nov 17 02:48:52 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 17 Nov 2009 09:48:52 +0100 Subject: [llvm-commits] [llvm] r88913 - in /llvm/trunk/include/llvm/Support: Compiler.h IRBuilder.h In-Reply-To: <93852A99-2499-4D9E-80CC-4E6035D72F0C@apple.com> References: <200911161528.nAGFSIpF022448@zion.cs.uiuc.edu> <93852A99-2499-4D9E-80CC-4E6035D72F0C@apple.com> Message-ID: <4B026374.6060805@free.fr> Hi Douglas, > I'm getting a bunch of warnings now, since the "error" attribute is only > available on GCC >= 4.3. Patch coming to conditionalize this more > appropriately... thanks for fixing this. In the end I went for a different approach: making the method private. Ciao, Duncan. From baldrick at free.fr Tue Nov 17 02:49:46 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 17 Nov 2009 09:49:46 +0100 Subject: [llvm-commits] [llvm] r88913 - in /llvm/trunk/include/llvm/Support: Compiler.h IRBuilder.h In-Reply-To: <6a8523d60911161106r291ab659w965cccea9107f7f0@mail.gmail.com> References: <200911161528.nAGFSIpF022448@zion.cs.uiuc.edu> <93852A99-2499-4D9E-80CC-4E6035D72F0C@apple.com> <6a8523d60911161106r291ab659w965cccea9107f7f0@mail.gmail.com> Message-ID: <4B0263AA.8050504@free.fr> Hi Daniel, > Couldn't this extra function also just be private with a DO NOT > IMPLEMENT marker? good idea - implemented in commit 89067. Ciao, Duncan. From nicholas at mxc.ca Tue Nov 17 03:17:08 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 17 Nov 2009 09:17:08 -0000 Subject: [llvm-commits] [llvm] r89075 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DIE.h DwarfDebug.cpp DwarfDebug.h DwarfException.h DwarfPrinter.h Message-ID: <200911170917.nAH9H8tl014262@zion.cs.uiuc.edu> Author: nicholas Date: Tue Nov 17 03:17:08 2009 New Revision: 89075 URL: http://llvm.org/viewvc/llvm-project?rev=89075&view=rev Log: Remove VISIBILITY_HIDDEN from the classes in this directory. Fixes bug 5507. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfPrinter.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h?rev=89075&r1=89074&r2=89075&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h Tue Nov 17 03:17:08 2009 @@ -29,7 +29,7 @@ //===--------------------------------------------------------------------===// /// DIEAbbrevData - Dwarf abbreviation data, describes the one attribute of a /// Dwarf abbreviation. - class VISIBILITY_HIDDEN DIEAbbrevData { + class DIEAbbrevData { /// Attribute - Dwarf attribute code. /// unsigned Attribute; @@ -52,7 +52,7 @@ //===--------------------------------------------------------------------===// /// DIEAbbrev - Dwarf abbreviation, describes the organization of a debug /// information object. - class VISIBILITY_HIDDEN DIEAbbrev : public FoldingSetNode { + class DIEAbbrev : public FoldingSetNode { /// Tag - Dwarf tag code. /// unsigned Tag; @@ -113,7 +113,7 @@ class CompileUnit; class DIEValue; - class VISIBILITY_HIDDEN DIE : public FoldingSetNode { + class DIE : public FoldingSetNode { protected: /// Abbrev - Buffer for constructing abbreviation. /// @@ -202,7 +202,7 @@ //===--------------------------------------------------------------------===// /// DIEValue - A debug information entry value. /// - class VISIBILITY_HIDDEN DIEValue : public FoldingSetNode { + class DIEValue : public FoldingSetNode { public: enum { isInteger, @@ -249,7 +249,7 @@ //===--------------------------------------------------------------------===// /// DIEInteger - An integer value DIE. /// - class VISIBILITY_HIDDEN DIEInteger : public DIEValue { + class DIEInteger : public DIEValue { uint64_t Integer; public: explicit DIEInteger(uint64_t I) : DIEValue(isInteger), Integer(I) {} @@ -294,7 +294,7 @@ //===--------------------------------------------------------------------===// /// DIEString - A string value DIE. /// - class VISIBILITY_HIDDEN DIEString : public DIEValue { + class DIEString : public DIEValue { const std::string Str; public: explicit DIEString(const std::string &S) : DIEValue(isString), Str(S) {} @@ -326,7 +326,7 @@ //===--------------------------------------------------------------------===// /// DIEDwarfLabel - A Dwarf internal label expression DIE. // - class VISIBILITY_HIDDEN DIEDwarfLabel : public DIEValue { + class DIEDwarfLabel : public DIEValue { const DWLabel Label; public: explicit DIEDwarfLabel(const DWLabel &L) : DIEValue(isLabel), Label(L) {} @@ -356,7 +356,7 @@ //===--------------------------------------------------------------------===// /// DIEObjectLabel - A label to an object in code or data. // - class VISIBILITY_HIDDEN DIEObjectLabel : public DIEValue { + class DIEObjectLabel : public DIEValue { const std::string Label; public: explicit DIEObjectLabel(const std::string &L) @@ -389,7 +389,7 @@ //===--------------------------------------------------------------------===// /// DIESectionOffset - A section offset DIE. /// - class VISIBILITY_HIDDEN DIESectionOffset : public DIEValue { + class DIESectionOffset : public DIEValue { const DWLabel Label; const DWLabel Section; bool IsEH : 1; @@ -428,7 +428,7 @@ //===--------------------------------------------------------------------===// /// DIEDelta - A simple label difference DIE. /// - class VISIBILITY_HIDDEN DIEDelta : public DIEValue { + class DIEDelta : public DIEValue { const DWLabel LabelHi; const DWLabel LabelLo; public: @@ -462,7 +462,7 @@ /// DIEntry - A pointer to another debug information entry. An instance of /// this class can also be used as a proxy for a debug information entry not /// yet defined (ie. types.) - class VISIBILITY_HIDDEN DIEEntry : public DIEValue { + class DIEEntry : public DIEValue { DIE *Entry; public: explicit DIEEntry(DIE *E) : DIEValue(isEntry), Entry(E) {} @@ -497,7 +497,7 @@ //===--------------------------------------------------------------------===// /// DIEBlock - A block of values. Primarily used for location expressions. // - class VISIBILITY_HIDDEN DIEBlock : public DIEValue, public DIE { + class DIEBlock : public DIEValue, public DIE { unsigned Size; // Size in bytes excluding size header. public: DIEBlock() Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=89075&r1=89074&r2=89075&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Nov 17 03:17:08 2009 @@ -145,7 +145,6 @@ //===----------------------------------------------------------------------===// /// DbgScope - This class is used to track scope information. /// -class DbgConcreteScope; class DbgScope { DbgScope *Parent; // Parent to this scope. DIDescriptor Desc; // Debug info descriptor for scope. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=89075&r1=89074&r2=89075&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Tue Nov 17 03:17:08 2009 @@ -30,9 +30,9 @@ namespace llvm { class CompileUnit; -class DbgVariable; -class DbgScope; class DbgConcreteScope; +class DbgScope; +class DbgVariable; class MachineFrameInfo; class MachineModuleInfo; class MCAsmInfo; @@ -41,7 +41,7 @@ //===----------------------------------------------------------------------===// /// SrcLineInfo - This class is used to record source line correspondence. /// -class VISIBILITY_HIDDEN SrcLineInfo { +class SrcLineInfo { unsigned Line; // Source line number. unsigned Column; // Source column. unsigned SourceID; // Source ID number. @@ -57,7 +57,7 @@ unsigned getLabelID() const { return LabelID; } }; -class VISIBILITY_HIDDEN DwarfDebug : public Dwarf { +class DwarfDebug : public Dwarf { //===--------------------------------------------------------------------===// // Attributes used to construct specific Dwarf sections. // Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h?rev=89075&r1=89074&r2=89075&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.h Tue Nov 17 03:17:08 2009 @@ -32,7 +32,7 @@ //===----------------------------------------------------------------------===// /// DwarfException - Emits Dwarf exception handling directives. /// -class VISIBILITY_HIDDEN DwarfException : public Dwarf { +class DwarfException : public Dwarf { struct FunctionEHFrameInfo { std::string FnName; unsigned Number; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfPrinter.h?rev=89075&r1=89074&r2=89075&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfPrinter.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfPrinter.h Tue Nov 17 03:17:08 2009 @@ -29,7 +29,7 @@ class TargetData; class TargetRegisterInfo; - class VISIBILITY_HIDDEN Dwarf { + class Dwarf { protected: //===-------------------------------------------------------------==---===// // Core attributes used by the DWARF printer. From evan.cheng at apple.com Tue Nov 17 03:20:28 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 17 Nov 2009 09:20:28 -0000 Subject: [llvm-commits] [llvm] r89076 - in /llvm/trunk/lib/Target/X86: X86InstrInfo.cpp X86InstrSSE.td Message-ID: <200911170920.nAH9KTob014428@zion.cs.uiuc.edu> Author: evancheng Date: Tue Nov 17 03:20:28 2009 New Revision: 89076 URL: http://llvm.org/viewvc/llvm-project?rev=89076&view=rev Log: Revert 89011. Buildbot thinks it might be breaking stuff. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=89076&r1=89075&r2=89076&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Nov 17 03:20:28 2009 @@ -869,13 +869,10 @@ case X86::MOVSDrm: case X86::MOVAPSrm: case X86::MOVUPSrm: - case X86::MOVUPSrm_Int: case X86::MOVAPDrm: case X86::MOVDQArm: case X86::MMX_MOVD64rm: - case X86::MMX_MOVQ64rm: - case X86::FsMOVAPSrm: - case X86::FsMOVAPDrm: { + case X86::MMX_MOVQ64rm: { // Loads from constant pools are trivially rematerializable. if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() && Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=89076&r1=89075&r2=89076&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Nov 17 03:20:28 2009 @@ -497,7 +497,7 @@ // Alias instruction to load FR32 from f128mem using movaps. Upper bits are // disregarded. -let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let canFoldAsLoad = 1 in def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src), "movaps\t{$src, $dst|$dst, $src}", [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>; @@ -715,7 +715,7 @@ [(store (v4f32 VR128:$src), addr:$dst)]>; // Intrinsic forms of MOVUPS load and store -let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let canFoldAsLoad = 1 in def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movups\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>; @@ -1256,7 +1256,7 @@ // Alias instruction to load FR64 from f128mem using movapd. Upper bits are // disregarded. -let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let canFoldAsLoad = 1 in def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src), "movapd\t{$src, $dst|$dst, $src}", [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>; From daniel at zuster.org Tue Nov 17 03:30:00 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 17 Nov 2009 09:30:00 -0000 Subject: [llvm-commits] [llvm] r89077 - /llvm/trunk/unittests/ADT/StringRefTest.cpp Message-ID: <200911170930.nAH9U0b0014770@zion.cs.uiuc.edu> Author: ddunbar Date: Tue Nov 17 03:29:59 2009 New Revision: 89077 URL: http://llvm.org/viewvc/llvm-project?rev=89077&view=rev Log: "XFAIL" the Split2 StringReft test with Apple gcc, which miscompiles it. - I plan on fixing/workarounding this, but until then I'd like the bots to stay green. Modified: llvm/trunk/unittests/ADT/StringRefTest.cpp Modified: llvm/trunk/unittests/ADT/StringRefTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/StringRefTest.cpp?rev=89077&r1=89076&r2=89077&view=diff ============================================================================== --- llvm/trunk/unittests/ADT/StringRefTest.cpp (original) +++ llvm/trunk/unittests/ADT/StringRefTest.cpp Tue Nov 17 03:29:59 2009 @@ -111,6 +111,11 @@ Str.rsplit('o')); } +// XFAIL for PR5482, StringRef is miscompiled by Apple gcc. +#if (!defined(__llvm__) && defined(__APPLE__) && defined(__OPTIMIZE__)) +#define SKIP_SPLIT2 +#endif +#ifndef SKIP_SPLIT2 TEST(StringRefTest, Split2) { SmallVector parts; SmallVector expected; @@ -190,6 +195,7 @@ StringRef("a,,b,c").split(parts, ",", 3, false); EXPECT_TRUE(parts == expected); } +#endif TEST(StringRefTest, StartsWith) { StringRef Str("hello"); From evan.cheng at apple.com Tue Nov 17 03:51:19 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 17 Nov 2009 09:51:19 -0000 Subject: [llvm-commits] [llvm] r89081 - in /llvm/trunk/lib/Target/X86: X86InstrInfo.cpp X86InstrSSE.td Message-ID: <200911170951.nAH9pJfx015452@zion.cs.uiuc.edu> Author: evancheng Date: Tue Nov 17 03:51:18 2009 New Revision: 89081 URL: http://llvm.org/viewvc/llvm-project?rev=89081&view=rev Log: Re-apply 89011. It's not to be blamed. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=89081&r1=89080&r2=89081&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Nov 17 03:51:18 2009 @@ -869,10 +869,13 @@ case X86::MOVSDrm: case X86::MOVAPSrm: case X86::MOVUPSrm: + case X86::MOVUPSrm_Int: case X86::MOVAPDrm: case X86::MOVDQArm: case X86::MMX_MOVD64rm: - case X86::MMX_MOVQ64rm: { + case X86::MMX_MOVQ64rm: + case X86::FsMOVAPSrm: + case X86::FsMOVAPDrm: { // Loads from constant pools are trivially rematerializable. if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() && Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=89081&r1=89080&r2=89081&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Nov 17 03:51:18 2009 @@ -497,7 +497,7 @@ // Alias instruction to load FR32 from f128mem using movaps. Upper bits are // disregarded. -let canFoldAsLoad = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src), "movaps\t{$src, $dst|$dst, $src}", [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>; @@ -715,7 +715,7 @@ [(store (v4f32 VR128:$src), addr:$dst)]>; // Intrinsic forms of MOVUPS load and store -let canFoldAsLoad = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movups\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>; @@ -1256,7 +1256,7 @@ // Alias instruction to load FR64 from f128mem using movapd. Upper bits are // disregarded. -let canFoldAsLoad = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src), "movapd\t{$src, $dst|$dst, $src}", [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>; From evan.cheng at apple.com Tue Nov 17 03:55:52 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 17 Nov 2009 09:55:52 -0000 Subject: [llvm-commits] [llvm] r89082 - in /llvm/trunk: lib/CodeGen/PHIElimination.cpp test/CodeGen/X86/2008-04-15-LiveVariableBug.ll test/CodeGen/X86/stack-color-with-reg.ll Message-ID: <200911170955.nAH9tqpP015652@zion.cs.uiuc.edu> Author: evancheng Date: Tue Nov 17 03:55:52 2009 New Revision: 89082 URL: http://llvm.org/viewvc/llvm-project?rev=89082&view=rev Log: Revert 89021. It's miscompiling llvm-gcc driver driver at -O0. Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89082&r1=89081&r2=89082&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Tue Nov 17 03:55:52 2009 @@ -39,7 +39,7 @@ static cl::opt SplitEdges("split-phi-edges", cl::desc("Split critical edges during phi elimination"), - cl::init(true), cl::Hidden); + cl::init(false), cl::Hidden); char PHIElimination::ID = 0; static RegisterPass Modified: llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll?rev=89082&r1=89081&r2=89082&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll Tue Nov 17 03:55:52 2009 @@ -1,9 +1,5 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin - -; Globally enabling -split-phi-edges causes LiveVariables to always run. -; LiveVariables trips up the local allocator on this test. -; It doesn't understand the subtleties of subregister imp-kills. -; DONT: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local +; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local %struct.CGPoint = type { double, double } %struct.NSArray = type { %struct.NSObject } Modified: llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll?rev=89082&r1=89081&r2=89082&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll (original) +++ llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll Tue Nov 17 03:55:52 2009 @@ -1,8 +1,6 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t ; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 6 - -; Obviously the only correct way of translating this function is with 175 instructions. Not 177 (duh!) -; RUN: grep asm-printer %t | grep 175 +; RUN: grep asm-printer %t | grep 177 type { [62 x %struct.Bitvec*] } ; type %0 type { i8* } ; type %1 From baldrick at free.fr Tue Nov 17 04:20:22 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 17 Nov 2009 10:20:22 -0000 Subject: [llvm-commits] [llvm] r89087 - /llvm/trunk/tools/bugpoint/ToolRunner.cpp Message-ID: <200911171020.nAHAKMa8017020@zion.cs.uiuc.edu> Author: baldrick Date: Tue Nov 17 04:20:22 2009 New Revision: 89087 URL: http://llvm.org/viewvc/llvm-project?rev=89087&view=rev Log: Make bugpoint pass -load arguments to LLI. This lets one use bugpoint with programs that depend on native shared libraries. Patch by Timo Lindfors. Modified: llvm/trunk/tools/bugpoint/ToolRunner.cpp Modified: llvm/trunk/tools/bugpoint/ToolRunner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ToolRunner.cpp?rev=89087&r1=89086&r2=89087&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/ToolRunner.cpp (original) +++ llvm/trunk/tools/bugpoint/ToolRunner.cpp Tue Nov 17 04:20:22 2009 @@ -199,14 +199,15 @@ const std::vector &SharedLibs, unsigned Timeout, unsigned MemoryLimit) { - if (!SharedLibs.empty()) - throw ToolExecutionError("LLI currently does not support " - "loading shared libraries."); - std::vector LLIArgs; LLIArgs.push_back(LLIPath.c_str()); LLIArgs.push_back("-force-interpreter=true"); + for (std::vector::const_iterator i = SharedLibs.begin(), e = SharedLibs.end(); i != e; ++i) { + LLIArgs.push_back("-load"); + LLIArgs.push_back((*i).c_str()); + } + // Add any extra LLI args. for (unsigned i = 0, e = ToolArgs.size(); i != e; ++i) LLIArgs.push_back(ToolArgs[i].c_str()); From baldrick at free.fr Tue Nov 17 04:54:25 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 17 Nov 2009 10:54:25 -0000 Subject: [llvm-commits] [llvm] r89091 - in /llvm/trunk/include/llvm/ADT: GraphTraits.h SCCIterator.h Message-ID: <200911171054.nAHAsQ7G018437@zion.cs.uiuc.edu> Author: baldrick Date: Tue Nov 17 04:54:25 2009 New Revision: 89091 URL: http://llvm.org/viewvc/llvm-project?rev=89091&view=rev Log: 1. Allow SCCIterator to work with GraphT types that are constant. 2. Allow SCCIterator to work with inverse graphs. 3. Fix an incorrect comment in GraphTraits.h (the type in the comment was given as GraphType* when it is actually const GraphType &). Patch by Patrick Alexander Simmons. Modified: llvm/trunk/include/llvm/ADT/GraphTraits.h llvm/trunk/include/llvm/ADT/SCCIterator.h Modified: llvm/trunk/include/llvm/ADT/GraphTraits.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/GraphTraits.h?rev=89091&r1=89090&r2=89091&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/GraphTraits.h (original) +++ llvm/trunk/include/llvm/ADT/GraphTraits.h Tue Nov 17 04:54:25 2009 @@ -30,7 +30,7 @@ // typedef NodeType - Type of Node in the graph // typedef ChildIteratorType - Type used to iterate over children in graph - // static NodeType *getEntryNode(GraphType *) + // static NodeType *getEntryNode(const GraphType &) // Return the entry node of the graph // static ChildIteratorType child_begin(NodeType *) Modified: llvm/trunk/include/llvm/ADT/SCCIterator.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SCCIterator.h?rev=89091&r1=89090&r2=89091&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/SCCIterator.h (original) +++ llvm/trunk/include/llvm/ADT/SCCIterator.h Tue Nov 17 04:54:25 2009 @@ -136,8 +136,8 @@ typedef scc_iterator _Self; // Provide static "constructors"... - static inline _Self begin(GraphT& G) { return _Self(GT::getEntryNode(G)); } - static inline _Self end (GraphT& G) { return _Self(); } + static inline _Self begin(const GraphT& G) { return _Self(GT::getEntryNode(G)); } + static inline _Self end (const GraphT& G) { return _Self(); } // Direct loop termination test (I.fini() is more efficient than I == end()) inline bool fini() const { @@ -186,15 +186,25 @@ // Global constructor for the SCC iterator. template -scc_iterator scc_begin(T G) { +scc_iterator scc_begin(const T& G) { return scc_iterator::begin(G); } template -scc_iterator scc_end(T G) { +scc_iterator scc_end(const T& G) { return scc_iterator::end(G); } +template +scc_iterator > scc_begin(const Inverse& G) { + return scc_iterator >::begin(G); +} + +template +scc_iterator > scc_end(const Inverse& G) { + return scc_iterator >::end(G); +} + } // End llvm namespace #endif From jay.foad at gmail.com Tue Nov 17 05:30:00 2009 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 17 Nov 2009 11:30:00 +0000 Subject: [llvm-commits] [PATCH] Fix some html formatting Message-ID: OK to apply? Thanks, Jay. -------------- next part -------------- A non-text attachment was scrubbed... Name: patch.sourceleveldebugging Type: application/octet-stream Size: 786 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091117/3e680fa0/attachment.obj From benny.kra at googlemail.com Tue Nov 17 05:50:50 2009 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 17 Nov 2009 12:50:50 +0100 Subject: [llvm-commits] [PATCH] Fix some html formatting In-Reply-To: References: Message-ID: Am 17.11.2009 um 12:30 schrieb Jay Foad: > OK to apply? Looks great to me. Please commit :) From jay.foad at gmail.com Tue Nov 17 07:13:59 2009 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 17 Nov 2009 13:13:59 -0000 Subject: [llvm-commits] [llvm] r89093 - /llvm/trunk/docs/SourceLevelDebugging.html Message-ID: <200911171313.nAHDDxwj023984@zion.cs.uiuc.edu> Author: foad Date: Tue Nov 17 07:13:59 2009 New Revision: 89093 URL: http://llvm.org/viewvc/llvm-project?rev=89093&view=rev Log: Fix HTML formatting. Modified: llvm/trunk/docs/SourceLevelDebugging.html Modified: llvm/trunk/docs/SourceLevelDebugging.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=89093&r1=89092&r2=89093&view=diff ============================================================================== --- llvm/trunk/docs/SourceLevelDebugging.html (original) +++ llvm/trunk/docs/SourceLevelDebugging.html Tue Nov 17 07:13:59 2009 @@ -774,7 +774,7 @@

This intrinsic is used to provide correspondence between the source file and the generated code. The first argument is the line number (base 1), second argument is the column number (0 if unknown) and the third argument the - source %llvm.dbg.compile_unit. + source %llvm.dbg.compile_unit. Code following a call to this intrinsic will have been defined in close proximity of the line, column and file. This information holds until the next call From baldrick at free.fr Tue Nov 17 07:16:37 2009 From: baldrick at free.fr (Duncan Sands) Date: Tue, 17 Nov 2009 13:16:37 -0000 Subject: [llvm-commits] [dragonegg] r89094 - in /dragonegg/trunk: llvm-backend.cpp llvm-convert.cpp llvm-internal.h Message-ID: <200911171316.nAHDGbLD024074@zion.cs.uiuc.edu> Author: baldrick Date: Tue Nov 17 07:16:37 2009 New Revision: 89094 URL: http://llvm.org/viewvc/llvm-project?rev=89094&view=rev Log: Rather than having gcc calculate dominfo and outputting basic blocks in dominator order (in order to see definitions of SSA names before their uses), output all basic blocks in the order they are listed in gcc, using a "placeholder" value for SSA names whenever a use is seen before the definition. The placeholder is replaced everywhere by the definition when it is eventually seen. Modified: dragonegg/trunk/llvm-backend.cpp dragonegg/trunk/llvm-convert.cpp dragonegg/trunk/llvm-internal.h Modified: dragonegg/trunk/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-backend.cpp?rev=89094&r1=89093&r2=89094&view=diff ============================================================================== --- dragonegg/trunk/llvm-backend.cpp (original) +++ dragonegg/trunk/llvm-backend.cpp Tue Nov 17 07:16:37 2009 @@ -1733,9 +1733,6 @@ // know we want to output it. DECL_DEFER_OUTPUT(current_function_decl) = 0; - // Provide the function convertor with dominators. - calculate_dominance_info(CDI_DOMINATORS); - // Convert the AST to raw/ugly LLVM code. Function *Fn; { @@ -1743,7 +1740,7 @@ Fn = Emitter.EmitFunction(); } - // Free dominator and other ssa data structures. + // Free any data structures. execute_free_datastructures(); //TODO performLateBackendInitialization(); Modified: dragonegg/trunk/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-convert.cpp?rev=89094&r1=89093&r2=89094&view=diff ============================================================================== --- dragonegg/trunk/llvm-convert.cpp (original) +++ dragonegg/trunk/llvm-convert.cpp Tue Nov 17 07:16:37 2009 @@ -75,7 +75,6 @@ #include "tree-flow.h" #include "tree-pass.h" #include "rtl.h" -#include "domwalk.h" #include "langhooks.h" extern int get_pointer_alignment (tree exp, unsigned int max_align); @@ -156,6 +155,21 @@ return align ? align : 1; } +/// getSSAPlaceholder - A fake value associated with an SSA name when the name +/// is used before being defined (this can occur because basic blocks are not +/// output in dominator order). Replaced with the correct value when the SSA +/// name's definition is encountered. +static Value *GetSSAPlaceholder(const Type *Ty) { + return new BitCastInst(UndefValue::get(Ty), Ty); +} + +/// isSSAPlaceholder - Whether this is a fake value being used as a placeholder +/// for the definition of an SSA name. +static bool isSSAPlaceholder(Value *V) { + BitCastInst *BC = dyn_cast(V); + return BC && !BC->getParent(); +} + /// NameValue - Try to name the given value after the given GCC tree node. If /// the GCC tree node has no sensible name then it does nothing. If the value /// already has a name then it is not changed. @@ -275,7 +289,7 @@ Value *TreeToLLVM::get_decl_local(tree decl) { if (!isLocalDecl(decl)) return get_decl_llvm(decl); - DenseMap >::iterator I = LocalDecls.find(decl); + DenseMap >::iterator I = LocalDecls.find(decl); if (I != LocalDecls.end()) return I->second; return NULL; @@ -287,7 +301,7 @@ if (!isLocalDecl(decl)) return make_decl_llvm(decl); - DenseMap >::iterator I = LocalDecls.find(decl); + DenseMap >::iterator I = LocalDecls.find(decl); if (I != LocalDecls.end()) return I->second; @@ -762,6 +776,21 @@ ReturnBB = BasicBlock::Create(Context, "return"); } +/// DefineSSAName - Use the given value as the definition of the given SSA name. +/// Returns the provided value as a convenience. +Value *TreeToLLVM::DefineSSAName(tree_node *reg, Value *Val) { + assert(TREE_CODE(reg) == SSA_NAME && "Not an SSA name!"); + if (Value *ExistingValue = SSANames[reg]) { + assert(isSSAPlaceholder(ExistingValue) && "Multiply defined SSA name!"); + // Replace the placeholder with the value everywhere. This also updates the + // map entry. + ExistingValue->replaceAllUsesWith(Val); + delete ExistingValue; + return Val; + } + return SSANames[reg] = Val; +} + typedef SmallVector, 8> PredVector; typedef SmallVector, 8> TreeVector; typedef SmallVector, 8> ValueVector; @@ -784,8 +813,7 @@ // If there is no corresponding LLVM basic block then the GCC basic block // was unreachable - skip this phi argument. DenseMap::iterator BI = BasicBlocks.find(bb); - if (BI == BasicBlocks.end()) - continue; + assert(BI != BasicBlocks.end() && "GCC basic block not output?"); // The incoming GCC expression. tree val = gimple_phi_arg(P.gcc_phi, i)->def; @@ -865,20 +893,6 @@ Predecessors.clear(); } - // FIXME: Because we don't support exception handling yet, we don't output GCC - // basic blocks for landing pads and so forth. This can result in LLVM basic - // blocks with no predecessors but a phi node, which the verifier rejects. - // Workaround this for the moment by replacing all such phi nodes with undef. - LocalDecls.clear(); - SSANames.clear(); - for (unsigned i = 0, e = PendingPhis.size(); i < e; ++i) { - PhiRecord &P = PendingPhis[i]; - if (P.PHI->getNumIncomingValues()) - continue; - P.PHI->replaceAllUsesWith(UndefValue::get(P.PHI->getType())); - P.PHI->eraseFromParent(); - } - PendingPhis.clear(); } @@ -950,6 +964,15 @@ // defined and all basic blocks output. PopulatePhiNodes(); +#ifndef NDEBUG + for (DenseMap >::const_iterator I = SSANames.begin(), + E = SSANames.end(); I != E; ++I) + if (isSSAPlaceholder(I->second)) { + debug_tree(I->first); + llvm_unreachable("SSA name never defined!"); + } +#endif + return Fn; } @@ -1037,11 +1060,9 @@ // The phi defines the associated ssa name. tree name = gimple_phi_result(gcc_phi); assert(TREE_CODE(name) == SSA_NAME && "PHI result not an SSA name!"); - assert(SSANames.find(name) == SSANames.end() && - "Multiply defined SSA name!"); if (flag_verbose_asm) NameValue(PHI, name); - SSANames[name] = PHI; + DefineSSAName(name, PHI); // The phi operands will be populated later - remember the phi node. PhiRecord P = { gcc_phi, PHI }; @@ -1129,25 +1150,14 @@ } } -static void emit_basic_block(struct dom_walk_data *walk_data, basic_block bb) { - ((TreeToLLVM *)walk_data->global_data)->EmitBasicBlock(bb); -} - Function *TreeToLLVM::EmitFunction() { // Set up parameters and prepare for return, for the function. StartFunctionBody(); - // Emit the body of the function by iterating over all BBs. To ensure that - // definitions of ssa names are seen before any uses, the iteration is done - // in dominator order. - struct dom_walk_data walk_data; - memset(&walk_data, 0, sizeof(struct dom_walk_data)); - walk_data.dom_direction = CDI_DOMINATORS; - walk_data.before_dom_children = emit_basic_block; - walk_data.global_data = this; - init_walk_dominator_tree(&walk_data); - walk_dominator_tree(&walk_data, ENTRY_BLOCK_PTR); - fini_walk_dominator_tree(&walk_data); + // Output the basic blocks. + basic_block bb; + FOR_EACH_BB(bb) + EmitBasicBlock(bb); // Wrap things up. return FinishFunctionBody(); @@ -2127,15 +2137,22 @@ assert(TREE_CODE(reg) == SSA_NAME && "Expected an SSA name!"); assert(is_gimple_reg_type(TREE_TYPE(reg)) && "Not of register type!"); - DenseMap >::iterator I = SSANames.find(reg); - if (I != SSANames.end()) { - assert(I->second->getType() == ConvertType(TREE_TYPE(reg)) && + // If we already found the definition of the SSA name, return it. + if (Value *ExistingValue = SSANames[reg]) { + assert(ExistingValue->getType() == ConvertType(TREE_TYPE(reg)) && "SSA name has wrong type!"); - return I->second; + if (!isSSAPlaceholder(ExistingValue)) + return ExistingValue; + } + + // If this is not the definition of the SSA name, return a placeholder value. + if (!SSA_NAME_IS_DEFAULT_DEF(reg)) { + if (Value *ExistingValue = SSANames[reg]) + return ExistingValue; + return SSANames[reg] = GetSSAPlaceholder(ConvertType(TREE_TYPE(reg))); } // This SSA name is the default definition for the underlying symbol. - assert(SSA_NAME_IS_DEFAULT_DEF(reg) && "SSA name used before being defined!"); // The underlying symbol is an SSA variable. tree var = SSA_NAME_VAR(reg); @@ -2146,7 +2163,7 @@ Value *Val = EmitSSA_NAME(var); assert(Val->getType() == ConvertType(TREE_TYPE(reg)) && "SSA name has wrong type!"); - return SSANames[reg] = Val; + return DefineSSAName(reg, Val); } // Otherwise the symbol is a VAR_DECL, PARM_DECL or RESULT_DECL. Since a @@ -2154,7 +2171,7 @@ // variable in the function is a read operation, and refers to the value // read, it has an undefined value except for PARM_DECLs. if (TREE_CODE(var) != PARM_DECL) - return UndefValue::get(ConvertType(TREE_TYPE(reg))); + return DefineSSAName(reg, UndefValue::get(ConvertType(TREE_TYPE(reg)))); // Read the initial value of the parameter and associate it with the ssa name. assert(DECL_LOCAL_IF_SET(var) && "Parameter not laid out?"); @@ -2175,7 +2192,7 @@ Def = new BitCastInst(Def, Ty, "", SSAInsertionPoint); if (flag_verbose_asm) NameValue(Def, reg); - return SSANames[reg] = Def; + return DefineSSAName(reg, Def); } /// EmitGimpleInvariantAddress - The given address is constant in this function. @@ -6391,9 +6408,6 @@ } Constant *TreeToLLVM::EmitLV_LABEL_DECL(tree exp) { - // GCC kindly diverts labels for unreachable basic blocks to reachable blocks, - // so we are not obliged to output unreachable blocks even if the original - // code took the address of one. return BlockAddress::get(Fn, getLabelDeclBlock(exp)); } @@ -6821,7 +6835,8 @@ // If the call defined any ssa names, associate them with their value. for (unsigned i = 0, e = CallResultSSANames.size(); i != e; ++i) - SSANames[CallResultSSANames[i]] = Builder.CreateLoad(CallResultSSATemps[i]); + DefineSSAName(CallResultSSANames[i], + Builder.CreateLoad(CallResultSSATemps[i])); // Give the backend a chance to upgrade the inline asm to LLVM code. This // handles some common cases that LLVM has intrinsics for, e.g. x86 bswap -> @@ -8287,10 +8302,9 @@ // If this is the definition of an ssa name, record it in the SSANames map. if (TREE_CODE(lhs) == SSA_NAME) { - assert(SSANames.find(lhs) == SSANames.end() &&"Multiply defined SSA name!"); if (flag_verbose_asm) NameValue(RHS, lhs); - SSANames[lhs] = RHS; + DefineSSAName(lhs, RHS); return; } Modified: dragonegg/trunk/llvm-internal.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-internal.h?rev=89094&r1=89093&r2=89094&view=diff ============================================================================== --- dragonegg/trunk/llvm-internal.h (original) +++ dragonegg/trunk/llvm-internal.h Tue Nov 17 07:16:37 2009 @@ -63,6 +63,7 @@ class TargetData; class DebugInfo; template class AssertingVH; + template class TrackingVH; } using namespace llvm; @@ -355,13 +356,13 @@ DenseMap BasicBlocks; /// LocalDecls - Map from local declarations to their associated LLVM values. - DenseMap > LocalDecls; + DenseMap > LocalDecls; /// PendingPhis - Phi nodes which have not yet been populated with operands. SmallVector PendingPhis; // SSANames - Map from GCC ssa names to the defining LLVM value. - DenseMap > SSANames; + DenseMap > SSANames; public: @@ -484,6 +485,10 @@ /// label. BasicBlock *getLabelDeclBlock(tree_node *LabelDecl); + /// DefineSSAName - Use the given value as the definition of the given SSA + /// name. Returns the provided value as a convenience. + Value *DefineSSAName(tree_node *reg, Value *Val); + /// EmitSSA_NAME - Return the defining value of the given SSA_NAME. /// Only creates code in the entry block. Value *EmitSSA_NAME(tree_node *reg); From ofv at wanadoo.es Tue Nov 17 09:01:37 2009 From: ofv at wanadoo.es (=?windows-1252?Q?=D3scar_Fuentes?=) Date: Tue, 17 Nov 2009 16:01:37 +0100 Subject: [llvm-commits] [llvm] r88979 - /llvm/trunk/Makefile References: <200911162238.nAGMc189009001@zion.cs.uiuc.edu> <4B0256AD.2040909@free.fr> Message-ID: <874ootci0e.fsf@telefonica.net> Duncan Sands writes: >> Don't build examples by default, use BUILD_EXAMPLES=1 to build >> them. The only utility of this is testing that we keep the examples >> up to date, I will just make the buildbots run with this flag. > > is this really a good idea? If someone breaks an example, wouldn't it > be better for them to discover that directly themselves rather than > via a buildbot? And what about newcomers who want to build examples - > aren't they going to have a hard time working out how to build the > examples? FWIW, I agree with Duncan. The defaults should be newbie-friendly. -- ?scar From nunoplopes at sapo.pt Tue Nov 17 09:35:39 2009 From: nunoplopes at sapo.pt (Nuno Lopes) Date: Tue, 17 Nov 2009 15:35:39 -0000 Subject: [llvm-commits] [llvm] r89099 - /llvm/trunk/include/llvm/ADT/StringSwitch.h Message-ID: <200911171535.nAHFZdpY029838@zion.cs.uiuc.edu> Author: nlopes Date: Tue Nov 17 09:35:39 2009 New Revision: 89099 URL: http://llvm.org/viewvc/llvm-project?rev=89099&view=rev Log: add Case() with 5 args Modified: llvm/trunk/include/llvm/ADT/StringSwitch.h Modified: llvm/trunk/include/llvm/ADT/StringSwitch.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringSwitch.h?rev=89099&r1=89098&r2=89099&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/StringSwitch.h (original) +++ llvm/trunk/include/llvm/ADT/StringSwitch.h Tue Nov 17 09:35:39 2009 @@ -83,6 +83,14 @@ const T& Value) { return Case(S0, Value).Case(S1, Value).Case(S2, Value).Case(S3, Value); } + + template + StringSwitch& Cases(const char (&S0)[N0], const char (&S1)[N1], + const char (&S2)[N2], const char (&S3)[N3], + const char (&S4)[N4], const T& Value) { + return Case(S0, Value).Case(S1, Value).Case(S2, Value).Case(S3, Value) + .Case(S4, Value); + } T Default(const T& Value) { if (ResultKnown) From espindola at google.com Tue Nov 17 10:09:52 2009 From: espindola at google.com (Rafael Espindola) Date: Tue, 17 Nov 2009 11:09:52 -0500 Subject: [llvm-commits] [PATCH] LTO code generator options In-Reply-To: <6AE1604EE3EC5F4296C096518C6B77EEFD4607BF@mail.accesssoftek.com> References: <04F6B1512E264B27AEE607542FCDD113@andreic6e7fe55> <9C7CA4093A8F41D7AD156ED3CF854D17@andreic6e7fe55> <38a0d8450911101625s5e3b7cb0m31ec0ce4d4144dc@mail.gmail.com> <38a0d8450911121059n6a0d3eb0ka34711d931c7675e@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BA@mail.accesssoftek.com> <38a0d8450911141921r7deec8b3k91e06950263f0485@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BF@mail.accesssoftek.com> Message-ID: <38a0d8450911170809j6a32716ar840b8622cfad6f17@mail.gmail.com> 2009/11/16 Viktor Kutuzov : > Please find the attached patch. > Does this look like what you want to see? > > I have moved the check for Darwin OS insode the getArchNameForAssembler which makes it OS and Vendor independent. This is what we wanted from the beginning, aren't we? > And added missed ppc64. Thanks for catching this. The patch looks good to me! Thanks a lot. > Thanks, > Viktor. Cheers, -- Rafael ?vila de Esp?ndola From bob.wilson at apple.com Tue Nov 17 11:06:18 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 17 Nov 2009 17:06:18 -0000 Subject: [llvm-commits] [llvm] r89105 - in /llvm/trunk/lib/CodeGen: BranchFolding.cpp BranchFolding.h Message-ID: <200911171706.nAHH6I7V000797@zion.cs.uiuc.edu> Author: bwilson Date: Tue Nov 17 11:06:18 2009 New Revision: 89105 URL: http://llvm.org/viewvc/llvm-project?rev=89105&view=rev Log: Perform tail duplication only once, after tail merging is complete. It was too difficult to keep the heuristics for merging and duplication consistent. Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp llvm/trunk/lib/CodeGen/BranchFolding.h Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=89105&r1=89104&r2=89105&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Nov 17 11:06:18 2009 @@ -202,6 +202,11 @@ MadeChange |= MadeChangeThisIteration; } + // Do tail duplication once after tail merging is done. Otherwise it is + // tough to avoid situations where tail duplication and tail merging undo + // each other's transformations ad infinitum. + MadeChangeThisIteration |= TailDuplicateBlocks(MF); + // See if any jump tables have become mergable or dead as the code generator // did its thing. MachineJumpTableInfo *JTI = MF.getJumpTableInfo(); @@ -1025,22 +1030,43 @@ return MBB2I->getDesc().isCall() && !MBB1I->getDesc().isCall(); } +/// TailDuplicateBlocks - Look for small blocks that are unconditionally +/// branched to and do not fall through. Tail-duplicate their instructions +/// into their predecessors to eliminate (dynamic) branches. +bool BranchFolder::TailDuplicateBlocks(MachineFunction &MF) { + bool MadeChange = false; + + // Make sure blocks are numbered in order + MF.RenumberBlocks(); + + for (MachineFunction::iterator I = ++MF.begin(), E = MF.end(); I != E; ) { + MachineBasicBlock *MBB = I++; + + // Only duplicate blocks that end with unconditional branches. + if (CanFallThrough(MBB)) + continue; + + MadeChange |= TailDuplicate(MBB, MF); + + // If it is dead, remove it. + if (MBB->pred_empty()) { + RemoveDeadBlock(MBB); + MadeChange = true; + ++NumDeadBlocks; + } + } + return MadeChange; +} + /// TailDuplicate - If it is profitable, duplicate TailBB's contents in each /// of its predecessors. bool BranchFolder::TailDuplicate(MachineBasicBlock *TailBB, - bool PrevFallsThrough, MachineFunction &MF) { // Don't try to tail-duplicate single-block loops. if (TailBB->isSuccessor(TailBB)) return false; - // Don't tail-duplicate a block which will soon be folded into its successor. - if (TailBB->succ_size() == 1 && - TailBB->succ_begin()[0]->pred_size() == 1) - return false; - - // Duplicate up to one less that the tail-merge threshold, so that we don't - // get into an infinite loop between duplicating and merging. When optimizing + // Duplicate up to one less than the tail-merge threshold. When optimizing // for size, duplicate only one, because one branch instruction can be // eliminated to compensate for the duplication. unsigned MaxDuplicateCount = @@ -1088,11 +1114,8 @@ // EH edges are ignored by AnalyzeBranch. if (PredBB->succ_size() != 1) continue; - // Don't duplicate into a fall-through predecessor unless it's the - // only predecessor. - if (PredBB->isLayoutSuccessor(TailBB) && - PrevFallsThrough && - TailBB->pred_size() != 1) + // Don't duplicate into a fall-through predecessor (at least for now). + if (PredBB->isLayoutSuccessor(TailBB) && CanFallThrough(PredBB)) continue; DEBUG(errs() << "\nTail-duplicating into PredBB: " << *PredBB @@ -1118,6 +1141,28 @@ Changed = true; } + // If TailBB was duplicated into all its predecessors except for the prior + // block, which falls through unconditionally, move the contents of this + // block into the prior block. + MachineBasicBlock &PrevBB = *prior(MachineFunction::iterator(TailBB)); + MachineBasicBlock *PriorTBB = 0, *PriorFBB = 0; + SmallVector PriorCond; + bool PriorUnAnalyzable = + TII->AnalyzeBranch(PrevBB, PriorTBB, PriorFBB, PriorCond, true); + // This has to check PrevBB->succ_size() because EH edges are ignored by + // AnalyzeBranch. + if (!PriorUnAnalyzable && PriorCond.empty() && !PriorTBB && + TailBB->pred_size() == 1 && PrevBB.succ_size() == 1 && + !TailBB->hasAddressTaken()) { + DEBUG(errs() << "\nMerging into block: " << PrevBB + << "From MBB: " << *TailBB); + PrevBB.splice(PrevBB.end(), TailBB, TailBB->begin(), TailBB->end()); + PrevBB.removeSuccessor(PrevBB.succ_begin());; + assert(PrevBB.succ_empty()); + PrevBB.transferSuccessors(TailBB); + Changed = true; + } + return Changed; } @@ -1398,26 +1443,17 @@ } } - // Now we know that there was no fall-through into this block, check to - // see if it has a fall-through into its successor. - bool CurFallsThru = CanFallThrough(MBB, CurUnAnalyzable, CurTBB, CurFBB, - CurCond); - bool PrevFallsThru = CanFallThrough(&PrevBB, PriorUnAnalyzable, - PriorTBB, PriorFBB, PriorCond); - - // If this block is small, unconditionally branched to, and does not - // fall through, tail-duplicate its instructions into its predecessors - // to eliminate a (dynamic) branch. - if (!CurFallsThru) - if (TailDuplicate(MBB, PrevFallsThru, MF)) { - MadeChange = true; - return MadeChange; - } - // If the prior block doesn't fall through into this block, and if this // block doesn't fall through into some other block, see if we can find a // place to move this block where a fall-through will happen. - if (!PrevFallsThru) { + if (!CanFallThrough(&PrevBB, PriorUnAnalyzable, + PriorTBB, PriorFBB, PriorCond)) { + + // Now we know that there was no fall-through into this block, check to + // see if it has a fall-through into its successor. + bool CurFallsThru = CanFallThrough(MBB, CurUnAnalyzable, CurTBB, CurFBB, + CurCond); + if (!MBB->isLandingPad()) { // Check all the predecessors of this block. If one of them has no fall // throughs, move this block right after it. Modified: llvm/trunk/lib/CodeGen/BranchFolding.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.h?rev=89105&r1=89104&r2=89105&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.h (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.h Tue Nov 17 11:06:18 2009 @@ -105,9 +105,8 @@ unsigned CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB, unsigned maxCommonTailLength); - bool TailDuplicate(MachineBasicBlock *TailBB, - bool PrevFallsThrough, - MachineFunction &MF); + bool TailDuplicateBlocks(MachineFunction &MF); + bool TailDuplicate(MachineBasicBlock *TailBB, MachineFunction &MF); bool OptimizeBranches(MachineFunction &MF); bool OptimizeBlock(MachineBasicBlock *MBB); From johnny.chen at apple.com Tue Nov 17 11:17:50 2009 From: johnny.chen at apple.com (Johnny Chen) Date: Tue, 17 Nov 2009 17:17:50 -0000 Subject: [llvm-commits] [llvm] r89108 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <200911171717.nAHHHoEp001291@zion.cs.uiuc.edu> Author: johnny Date: Tue Nov 17 11:17:50 2009 New Revision: 89108 URL: http://llvm.org/viewvc/llvm-project?rev=89108&view=rev Log: Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm to distinguish between them and the more generic instructions (add, mov, and ldr). Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=89108&r1=89107&r2=89108&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 17 11:17:50 2009 @@ -759,6 +759,7 @@ def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), IIC_Br, "mov\tpc, $target \n$jt", [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> { + let Inst{15-12} = 0b1111; let Inst{20} = 0; // S Bit let Inst{24-21} = 0b1101; let Inst{27-25} = 0b000; @@ -768,6 +769,7 @@ IIC_Br, "ldr\tpc, $target \n$jt", [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, imm:$id)]> { + let Inst{15-12} = 0b1111; let Inst{20} = 1; // L bit let Inst{21} = 0; // W bit let Inst{22} = 0; // B bit @@ -779,6 +781,7 @@ IIC_Br, "add\tpc, $target, $idx \n$jt", [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, imm:$id)]> { + let Inst{15-12} = 0b1111; let Inst{20} = 0; // S bit let Inst{24-21} = 0b0100; let Inst{27-25} = 0b000; From bob.wilson at apple.com Tue Nov 17 11:40:31 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 17 Nov 2009 17:40:31 -0000 Subject: [llvm-commits] [llvm] r89109 - /llvm/trunk/lib/CodeGen/BranchFolding.cpp Message-ID: <200911171740.nAHHeVxH002108@zion.cs.uiuc.edu> Author: bwilson Date: Tue Nov 17 11:40:31 2009 New Revision: 89109 URL: http://llvm.org/viewvc/llvm-project?rev=89109&view=rev Log: Update a comment, now that tail duplication happens after other branch folding optimizations. Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=89109&r1=89108&r2=89109&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Nov 17 11:40:31 2009 @@ -1230,8 +1230,8 @@ // If the previous block unconditionally falls through to this block and // this block has no other predecessors, move the contents of this block // into the prior block. This doesn't usually happen when SimplifyCFG - // has been used, but it can happen if tail duplication eliminates all the - // non-branch predecessors of a block leaving only the fall-through edge. + // has been used, but it can happen if tail merging splits a fall-through + // predecessor of a block. // This has to check PrevBB->succ_size() because EH edges are ignored by // AnalyzeBranch. if (PriorCond.empty() && !PriorTBB && MBB->pred_size() == 1 && From grosbach at apple.com Tue Nov 17 11:53:56 2009 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 17 Nov 2009 17:53:56 -0000 Subject: [llvm-commits] [llvm] r89110 - /llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <200911171753.nAHHru6E002572@zion.cs.uiuc.edu> Author: grosbach Date: Tue Nov 17 11:53:56 2009 New Revision: 89110 URL: http://llvm.org/viewvc/llvm-project?rev=89110&view=rev Log: Remove trailing whitespace Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=89110&r1=89109&r2=89110&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue Nov 17 11:53:56 2009 @@ -108,7 +108,7 @@ public: static char ID; // Pass ID, replacement for typeid - explicit LoopStrengthReduce(const TargetLowering *tli = NULL) : + explicit LoopStrengthReduce(const TargetLowering *tli = NULL) : LoopPass(&ID), TLI(tli) { } @@ -134,7 +134,7 @@ private: void OptimizeIndvars(Loop *L); - /// OptimizeLoopTermCond - Change loop terminating condition to use the + /// OptimizeLoopTermCond - Change loop terminating condition to use the /// postinc iv when possible. void OptimizeLoopTermCond(Loop *L); @@ -225,11 +225,11 @@ /// their operands subsequently dead. void LoopStrengthReduce::DeleteTriviallyDeadInstructions() { if (DeadInsts.empty()) return; - + while (!DeadInsts.empty()) { Instruction *I = dyn_cast_or_null(DeadInsts.back()); DeadInsts.pop_back(); - + if (I == 0 || !isInstructionTriviallyDead(I)) continue; @@ -240,14 +240,14 @@ DeadInsts.push_back(U); } } - + I->eraseFromParent(); Changed = true; } } -/// containsAddRecFromDifferentLoop - Determine whether expression S involves a -/// subexpression that is an AddRec from a loop other than L. An outer loop +/// containsAddRecFromDifferentLoop - Determine whether expression S involves a +/// subexpression that is an AddRec from a loop other than L. An outer loop /// of L is OK, but not an inner loop nor a disjoint loop. static bool containsAddRecFromDifferentLoop(const SCEV *S, Loop *L) { // This is very common, put it first. @@ -273,7 +273,7 @@ return containsAddRecFromDifferentLoop(DE->getLHS(), L) || containsAddRecFromDifferentLoop(DE->getRHS(), L); #if 0 - // SCEVSDivExpr has been backed out temporarily, but will be back; we'll + // SCEVSDivExpr has been backed out temporarily, but will be back; we'll // need this when it is. if (const SCEVSDivExpr *DE = dyn_cast(S)) return containsAddRecFromDifferentLoop(DE->getLHS(), L) || @@ -345,7 +345,7 @@ /// field to the Imm field (below). BasedUser values are sorted by this /// field. const SCEV *Base; - + /// Inst - The instruction using the induction variable. Instruction *Inst; @@ -369,11 +369,11 @@ // instruction for a loop and uses outside the loop that are dominated by // the loop. bool isUseOfPostIncrementedValue; - + BasedUser(IVStrideUse &IVSU, ScalarEvolution *se) : SE(se), Base(IVSU.getOffset()), Inst(IVSU.getUser()), OperandValToReplace(IVSU.getOperandValToReplace()), - Imm(SE->getIntegerSCEV(0, Base->getType())), + Imm(SE->getIntegerSCEV(0, Base->getType())), isUseOfPostIncrementedValue(IVSU.isUseOfPostIncrementedValue()) {} // Once we rewrite the code to insert the new IVs we want, update the @@ -384,8 +384,8 @@ SCEVExpander &Rewriter, Loop *L, Pass *P, LoopInfo &LI, SmallVectorImpl &DeadInsts); - - Value *InsertCodeForBaseAtPosition(const SCEV *const &NewBase, + + Value *InsertCodeForBaseAtPosition(const SCEV *const &NewBase, const Type *Ty, SCEVExpander &Rewriter, Instruction *IP, Loop *L, @@ -400,7 +400,7 @@ errs() << " Inst: " << *Inst; } -Value *BasedUser::InsertCodeForBaseAtPosition(const SCEV *const &NewBase, +Value *BasedUser::InsertCodeForBaseAtPosition(const SCEV *const &NewBase, const Type *Ty, SCEVExpander &Rewriter, Instruction *IP, Loop *L, @@ -410,10 +410,10 @@ // want to insert this expression before the user, we'd rather pull it out as // many loops as possible. Instruction *BaseInsertPt = IP; - + // Figure out the most-nested loop that IP is in. Loop *InsertLoop = LI.getLoopFor(IP->getParent()); - + // If InsertLoop is not L, and InsertLoop is nested inside of L, figure out // the preheader of the outer-most loop where NewBase is not loop invariant. if (L->contains(IP->getParent())) @@ -421,7 +421,7 @@ BaseInsertPt = InsertLoop->getLoopPreheader()->getTerminator(); InsertLoop = InsertLoop->getParentLoop(); } - + Value *Base = Rewriter.expandCodeFor(NewBase, 0, BaseInsertPt); const SCEV *NewValSCEV = SE->getUnknown(Base); @@ -447,7 +447,7 @@ if (!isa(Inst)) { // By default, insert code at the user instruction. BasicBlock::iterator InsertPt = Inst; - + // However, if the Operand is itself an instruction, the (potentially // complex) inserted code may be shared by many users. Because of this, we // want to emit code for the computation of the operand right before its old @@ -459,7 +459,7 @@ // // If this is a use outside the loop (which means after, since it is based // on a loop indvar) we use the post-incremented value, so that we don't - // artificially make the preinc value live out the bottom of the loop. + // artificially make the preinc value live out the bottom of the loop. if (!isUseOfPostIncrementedValue && L->contains(Inst->getParent())) { if (NewBasePt && isa(OperandValToReplace)) { InsertPt = NewBasePt; @@ -494,7 +494,7 @@ if (PN->getIncomingValue(i) == OperandValToReplace) { // If the original expression is outside the loop, put the replacement // code in the same place as the original expression, - // which need not be an immediate predecessor of this PHI. This way we + // which need not be an immediate predecessor of this PHI. This way we // need only one copy of it even if it is referenced multiple times in // the PHI. We don't do this when the original expression is inside the // loop because multiple copies sometimes do useful sinking of code in @@ -590,11 +590,11 @@ static void MoveLoopVariantsToImmediateField(const SCEV *&Val, const SCEV *&Imm, Loop *L, ScalarEvolution *SE) { if (Val->isLoopInvariant(L)) return; // Nothing to do. - + if (const SCEVAddExpr *SAE = dyn_cast(Val)) { SmallVector NewOps; NewOps.reserve(SAE->getNumOperands()); - + for (unsigned i = 0; i != SAE->getNumOperands(); ++i) if (!SAE->getOperand(i)->isLoopInvariant(L)) { // If this is a loop-variant expression, it must stay in the immediate @@ -612,7 +612,7 @@ // Try to pull immediates out of the start value of nested addrec's. const SCEV *Start = SARE->getStart(); MoveLoopVariantsToImmediateField(Start, Imm, L, SE); - + SmallVector Ops(SARE->op_begin(), SARE->op_end()); Ops[0] = Start; Val = SE->getAddRecExpr(Ops, SARE->getLoop()); @@ -635,11 +635,11 @@ if (const SCEVAddExpr *SAE = dyn_cast(Val)) { SmallVector NewOps; NewOps.reserve(SAE->getNumOperands()); - + for (unsigned i = 0; i != SAE->getNumOperands(); ++i) { const SCEV *NewOp = SAE->getOperand(i); MoveImmediateValues(TLI, AccessTy, NewOp, Imm, isAddress, L, SE); - + if (!NewOp->isLoopInvariant(L)) { // If this is a loop-variant expression, it must stay in the immediate // field of the expression. @@ -658,7 +658,7 @@ // Try to pull immediates out of the start value of nested addrec's. const SCEV *Start = SARE->getStart(); MoveImmediateValues(TLI, AccessTy, Start, Imm, isAddress, L, SE); - + if (Start != SARE->getStart()) { SmallVector Ops(SARE->op_begin(), SARE->op_end()); Ops[0] = Start; @@ -674,8 +674,8 @@ const SCEV *SubImm = SE->getIntegerSCEV(0, Val->getType()); const SCEV *NewOp = SME->getOperand(1); MoveImmediateValues(TLI, AccessTy, NewOp, SubImm, isAddress, L, SE); - - // If we extracted something out of the subexpressions, see if we can + + // If we extracted something out of the subexpressions, see if we can // simplify this! if (NewOp != SME->getOperand(1)) { // Scale SubImm up by "8". If the result is a target constant, we are @@ -684,7 +684,7 @@ if (fitsInAddressMode(SubImm, AccessTy, TLI, false)) { // Accumulate the immediate. Imm = SE->getAddExpr(Imm, SubImm); - + // Update what is left of 'Val'. Val = SE->getMulExpr(SME->getOperand(0), NewOp); return; @@ -732,7 +732,7 @@ SmallVector Ops(SARE->op_begin(), SARE->op_end()); Ops[0] = Zero; // Start with zero base. SubExprs.push_back(SE->getAddRecExpr(Ops, SARE->getLoop())); - + SeparateSubExprs(SubExprs, SARE->getOperand(0), SE); } @@ -742,7 +742,7 @@ } } -// This is logically local to the following function, but C++ says we have +// This is logically local to the following function, but C++ says we have // to make it file scope. struct SubExprUseData { unsigned Count; bool notAllUsesAreFree; }; @@ -780,7 +780,7 @@ // an addressing mode "for free"; such expressions are left within the loop. // struct SubExprUseData { unsigned Count; bool notAllUsesAreFree; }; std::map SubExpressionUseData; - + // UniqueSubExprs - Keep track of all of the subexpressions we see in the // order we see them. SmallVector UniqueSubExprs; @@ -797,7 +797,7 @@ if (!L->contains(Uses[i].Inst->getParent())) continue; NumUsesInsideLoop++; - + // If the base is zero (which is common), return zero now, there are no // CSEs we can find. if (Uses[i].Base == Zero) return Zero; @@ -829,13 +829,13 @@ // Now that we know how many times each is used, build Result. Iterate over // UniqueSubexprs so that we have a stable ordering. for (unsigned i = 0, e = UniqueSubExprs.size(); i != e; ++i) { - std::map::iterator I = + std::map::iterator I = SubExpressionUseData.find(UniqueSubExprs[i]); assert(I != SubExpressionUseData.end() && "Entry not found?"); - if (I->second.Count == NumUsesInsideLoop) { // Found CSE! + if (I->second.Count == NumUsesInsideLoop) { // Found CSE! if (I->second.notAllUsesAreFree) Result = SE->getAddExpr(Result, I->first); - else + else FreeResult = SE->getAddExpr(FreeResult, I->first); } else // Remove non-cse's from SubExpressionUseData. @@ -867,13 +867,13 @@ // If we found no CSE's, return now. if (Result == Zero) return Result; - + // If we still have a FreeResult, remove its subexpressions from // SubExpressionUseData. This means they will remain in the use Bases. if (FreeResult != Zero) { SeparateSubExprs(SubExprs, FreeResult, SE); for (unsigned j = 0, e = SubExprs.size(); j != e; ++j) { - std::map::iterator I = + std::map::iterator I = SubExpressionUseData.find(SubExprs[j]); SubExpressionUseData.erase(I); } @@ -900,7 +900,7 @@ SubExprs.erase(SubExprs.begin()+j); --j; --e; } - + // Finally, add the non-shared expressions together. if (SubExprs.empty()) Uses[i].Base = Zero; @@ -908,11 +908,11 @@ Uses[i].Base = SE->getAddExpr(SubExprs); SubExprs.clear(); } - + return Result; } -/// ValidScale - Check whether the given Scale is valid for all loads and +/// ValidScale - Check whether the given Scale is valid for all loads and /// stores in UsersToProcess. /// bool LoopStrengthReduce::ValidScale(bool HasBaseReg, int64_t Scale, @@ -929,7 +929,7 @@ AccessTy = getAccessType(UsersToProcess[i].Inst); else if (isa(UsersToProcess[i].Inst)) continue; - + TargetLowering::AddrMode AM; if (const SCEVConstant *SC = dyn_cast(UsersToProcess[i].Imm)) AM.BaseOffs = SC->getValue()->getSExtValue(); @@ -1001,13 +1001,13 @@ /// reuse is possible. Factors can be negative on same targets, e.g. ARM. /// /// If all uses are outside the loop, we don't require that all multiplies -/// be folded into the addressing mode, nor even that the factor be constant; -/// a multiply (executed once) outside the loop is better than another IV +/// be folded into the addressing mode, nor even that the factor be constant; +/// a multiply (executed once) outside the loop is better than another IV /// within. Well, usually. const SCEV *LoopStrengthReduce::CheckForIVReuse(bool HasBaseReg, bool AllUsesAreAddresses, bool AllUsesAreOutsideLoop, - const SCEV *const &Stride, + const SCEV *const &Stride, IVExpr &IV, const Type *Ty, const std::vector& UsersToProcess) { if (StrideNoReuse.count(Stride)) @@ -1017,7 +1017,7 @@ int64_t SInt = SC->getValue()->getSExtValue(); for (unsigned NewStride = 0, e = IU->StrideOrder.size(); NewStride != e; ++NewStride) { - std::map::iterator SI = + std::map::iterator SI = IVsByStride.find(IU->StrideOrder[NewStride]); if (SI == IVsByStride.end() || !isa(SI->first) || StrideNoReuse.count(SI->first)) @@ -1075,7 +1075,7 @@ // an existing IV if we can. for (unsigned NewStride = 0, e = IU->StrideOrder.size(); NewStride != e; ++NewStride) { - std::map::iterator SI = + std::map::iterator SI = IVsByStride.find(IU->StrideOrder[NewStride]); if (SI == IVsByStride.end() || !isa(SI->first)) continue; @@ -1095,9 +1095,9 @@ // -1*old. for (unsigned NewStride = 0, e = IU->StrideOrder.size(); NewStride != e; ++NewStride) { - std::map::iterator SI = + std::map::iterator SI = IVsByStride.find(IU->StrideOrder[NewStride]); - if (SI == IVsByStride.end()) + if (SI == IVsByStride.end()) continue; if (const SCEVMulExpr *ME = dyn_cast(SI->first)) if (const SCEVConstant *SC = dyn_cast(ME->getOperand(0))) @@ -1127,11 +1127,11 @@ static bool isNonConstantNegative(const SCEV *const &Expr) { const SCEVMulExpr *Mul = dyn_cast(Expr); if (!Mul) return false; - + // If there is a constant factor, it will be first. const SCEVConstant *SC = dyn_cast(Mul->getOperand(0)); if (!SC) return false; - + // Return true if the value is negative, this matches things like (-42 * V). return SC->getValue()->getValue().isNegative(); } @@ -1168,7 +1168,7 @@ // We now have a whole bunch of uses of like-strided induction variables, but // they might all have different bases. We want to emit one PHI node for this // stride which we fold as many common expressions (between the IVs) into as - // possible. Start by identifying the common expressions in the base values + // possible. Start by identifying the common expressions in the base values // for the strides (e.g. if we have "A+C+B" and "A+B+D" as our bases, find // "A+B"), emit it to the preheader, then remove the expression from the // UsersToProcess base values. @@ -1188,11 +1188,11 @@ if (!L->contains(UsersToProcess[i].Inst->getParent())) { UsersToProcess[i].Imm = SE->getAddExpr(UsersToProcess[i].Imm, UsersToProcess[i].Base); - UsersToProcess[i].Base = + UsersToProcess[i].Base = SE->getIntegerSCEV(0, UsersToProcess[i].Base->getType()); } else { // Not all uses are outside the loop. - AllUsesAreOutsideLoop = false; + AllUsesAreOutsideLoop = false; // Addressing modes can be folded into loads and stores. Be careful that // the store is through the expression, not of the expression though. @@ -1206,11 +1206,11 @@ if (isAddress) HasAddress = true; - + // If this use isn't an address, then not all uses are addresses. if (!isAddress && !isPHI) AllUsesAreAddresses = false; - + MoveImmediateValues(TLI, UsersToProcess[i].Inst, UsersToProcess[i].Base, UsersToProcess[i].Imm, isAddress, L, SE); } @@ -1221,7 +1221,7 @@ // for one fewer iv. if (NumPHI > 1) AllUsesAreAddresses = false; - + // There are no in-loop address uses. if (AllUsesAreAddresses && (!HasAddress && !AllUsesAreOutsideLoop)) AllUsesAreAddresses = false; @@ -1611,7 +1611,7 @@ const SCEV *RewriteFactor = SE->getIntegerSCEV(0, ReplacedTy); IVExpr ReuseIV(SE->getIntegerSCEV(0, Type::getInt32Ty(Preheader->getContext())), - SE->getIntegerSCEV(0, + SE->getIntegerSCEV(0, Type::getInt32Ty(Preheader->getContext())), 0); @@ -1629,7 +1629,7 @@ // If all uses are addresses, check if it is possible to reuse an IV. The // new IV must have a stride that is a multiple of the old stride; the // multiple must be a number that can be encoded in the scale field of the - // target addressing mode; and we must have a valid instruction after this + // target addressing mode; and we must have a valid instruction after this // substitution, including the immediate field, if any. RewriteFactor = CheckForIVReuse(HaveCommonExprs, AllUsesAreAddresses, AllUsesAreOutsideLoop, @@ -1672,7 +1672,7 @@ // We want this constant emitted into the preheader! This is just // using cast as a copy so BitCast (no-op cast) is appropriate BaseV = new BitCastInst(BaseV, BaseV->getType(), "preheaderinsert", - PreInsertPt); + PreInsertPt); } } @@ -1746,7 +1746,7 @@ assert(SE->getTypeSizeInBits(RewriteExpr->getType()) < SE->getTypeSizeInBits(ReuseIV.Base->getType()) && "Unexpected lengthening conversion!"); - typedBase = SE->getTruncateExpr(ReuseIV.Base, + typedBase = SE->getTruncateExpr(ReuseIV.Base, RewriteExpr->getType()); } RewriteExpr = SE->getMinusSCEV(RewriteExpr, typedBase); @@ -1838,7 +1838,7 @@ } } return false; -} +} namespace { // Constant strides come first which in turns are sorted by their absolute @@ -2255,7 +2255,7 @@ const SCEV *BackedgeTakenCount = SE->getBackedgeTakenCount(L); if (isa(BackedgeTakenCount)) return; - + for (unsigned Stride = 0, e = IU->StrideOrder.size(); Stride != e; ++Stride) { std::map::iterator SI = @@ -2274,13 +2274,13 @@ /* If shadow use is a int->float cast then insert a second IV to eliminate this cast. - for (unsigned i = 0; i < n; ++i) + for (unsigned i = 0; i < n; ++i) foo((double)i); is transformed into double d = 0.0; - for (unsigned i = 0; i < n; ++i, ++d) + for (unsigned i = 0; i < n; ++i, ++d) foo(d); */ if (UIToFPInst *UCast = dyn_cast(CandidateUI->getUser())) @@ -2302,7 +2302,7 @@ const Type *SrcTy = PH->getType(); int Mantissa = DestTy->getFPMantissaWidth(); - if (Mantissa == -1) continue; + if (Mantissa == -1) continue; if ((int)SE->getTypeSizeInBits(SrcTy) > Mantissa) continue; @@ -2314,12 +2314,12 @@ Entry = 1; Latch = 0; } - + ConstantInt *Init = dyn_cast(PH->getIncomingValue(Entry)); if (!Init) continue; Constant *NewInit = ConstantFP::get(DestTy, Init->getZExtValue()); - BinaryOperator *Incr = + BinaryOperator *Incr = dyn_cast(PH->getIncomingValue(Latch)); if (!Incr) continue; if (Incr->getOpcode() != Instruction::Add @@ -2346,7 +2346,7 @@ /* create new increment. '++d' in above example. */ Constant *CFP = ConstantFP::get(DestTy, C->getZExtValue()); - BinaryOperator *NewIncr = + BinaryOperator *NewIncr = BinaryOperator::Create(Incr->getOpcode() == Instruction::Add ? Instruction::FAdd : Instruction::FSub, NewPH, CFP, "IV.S.next.", Incr); @@ -2448,7 +2448,7 @@ return false; if (!isUsedByExitBranch(Cond, L)) return false; - + Value *CondOp0 = Cond->getOperand(0); const SCEV *IV = SE->getSCEV(CondOp0); const SCEVAddRecExpr *AR = dyn_cast(IV); @@ -2479,7 +2479,7 @@ return true; } -/// OptimizeLoopTermCond - Change loop terminating condition to use the +/// OptimizeLoopTermCond - Change loop terminating condition to use the /// postinc iv when possible. void LoopStrengthReduce::OptimizeLoopTermCond(Loop *L) { // Finally, get the terminating condition for the loop if possible. If we @@ -2488,7 +2488,7 @@ // one register value. BasicBlock *LatchBlock = L->getLoopLatch(); BasicBlock *ExitingBlock = L->getExitingBlock(); - + if (!ExitingBlock) // Multiple exits, just look at the exit in the latch block if there is one. ExitingBlock = LatchBlock; @@ -2566,7 +2566,7 @@ Cond = cast(Cond->clone()); Cond->setName(L->getHeader()->getName() + ".termcond"); LatchBlock->getInstList().insert(TermBr, Cond); - + // Clone the IVUse, as the old use still exists! IU->IVUsesByStride[CondStride]->addUser(CondUse->getOffset(), Cond, CondUse->getOperandValToReplace()); @@ -2638,7 +2638,7 @@ Incr->eraseFromParent(); // Substitute endval-startval for the original startval, and 0 for the - // original endval. Since we're only testing for equality this is OK even + // original endval. Since we're only testing for equality this is OK even // if the computation wraps around. BasicBlock *Preheader = L->getLoopPreheader(); Instruction *PreInsertPt = Preheader->getTerminator(); From benny.kra at googlemail.com Tue Nov 17 11:57:04 2009 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 17 Nov 2009 17:57:04 -0000 Subject: [llvm-commits] [llvm] r89111 - in /llvm/trunk/lib: Support/CommandLine.cpp System/Host.cpp Message-ID: <200911171757.nAHHv4lH002679@zion.cs.uiuc.edu> Author: d0k Date: Tue Nov 17 11:57:04 2009 New Revision: 89111 URL: http://llvm.org/viewvc/llvm-project?rev=89111&view=rev Log: Revert CPU detection code to return "generic" instead of an empty string in case of failure. The x86 target didn't like empty cpu names and broke x86 tests on non-x86 buildbots. Modified: llvm/trunk/lib/Support/CommandLine.cpp llvm/trunk/lib/System/Host.cpp Modified: llvm/trunk/lib/Support/CommandLine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=89111&r1=89110&r2=89111&view=diff ============================================================================== --- llvm/trunk/lib/Support/CommandLine.cpp (original) +++ llvm/trunk/lib/Support/CommandLine.cpp Tue Nov 17 11:57:04 2009 @@ -1154,7 +1154,7 @@ OS << " with assertions"; #endif std::string CPU = sys::getHostCPUName(); - if (CPU.empty()) CPU = "(unknown)"; + if (CPU == "generic") CPU = "(unknown)"; OS << ".\n" << " Built " << __DATE__ << " (" << __TIME__ << ").\n" << " Host: " << sys::getHostTriple() << '\n' Modified: llvm/trunk/lib/System/Host.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Host.cpp?rev=89111&r1=89110&r2=89111&view=diff ============================================================================== --- llvm/trunk/lib/System/Host.cpp (original) +++ llvm/trunk/lib/System/Host.cpp Tue Nov 17 11:57:04 2009 @@ -249,7 +249,7 @@ } default: - return ""; + return "generic"; } } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) { // FIXME: this poorly matches the generated SubtargetFeatureKV table. There @@ -289,10 +289,10 @@ case 16: return "amdfam10"; default: - return ""; + return "generic"; } } #endif - return ""; + return "generic"; } From gohman at apple.com Tue Nov 17 12:04:15 2009 From: gohman at apple.com (Dan Gohman) Date: Tue, 17 Nov 2009 18:04:15 -0000 Subject: [llvm-commits] [llvm] r89114 - /llvm/trunk/lib/CodeGen/BranchFolding.cpp Message-ID: <200911171804.nAHI4Fk6002997@zion.cs.uiuc.edu> Author: djg Date: Tue Nov 17 12:04:15 2009 New Revision: 89114 URL: http://llvm.org/viewvc/llvm-project?rev=89114&view=rev Log: Set MadeChange instead of MadeChangeThisIteration. Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=89114&r1=89113&r2=89114&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Nov 17 12:04:15 2009 @@ -205,7 +205,7 @@ // Do tail duplication once after tail merging is done. Otherwise it is // tough to avoid situations where tail duplication and tail merging undo // each other's transformations ad infinitum. - MadeChangeThisIteration |= TailDuplicateBlocks(MF); + MadeChange |= TailDuplicateBlocks(MF); // See if any jump tables have become mergable or dead as the code generator // did its thing. From evan.cheng at apple.com Tue Nov 17 12:10:11 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 17 Nov 2009 18:10:11 -0000 Subject: [llvm-commits] [llvm] r89116 - in /llvm/trunk: lib/Transforms/Scalar/LoopStrengthReduce.cpp test/Transforms/LoopStrengthReduce/icmp_use_postinc.ll Message-ID: <200911171810.nAHIABec003239@zion.cs.uiuc.edu> Author: evancheng Date: Tue Nov 17 12:10:11 2009 New Revision: 89116 URL: http://llvm.org/viewvc/llvm-project?rev=89116&view=rev Log: Generalize OptimizeLoopTermCond to optimize more loop terminating icmp to use postinc iv. Added: llvm/trunk/test/Transforms/LoopStrengthReduce/icmp_use_postinc.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=89116&r1=89115&r2=89116&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue Nov 17 12:10:11 2009 @@ -2414,7 +2414,7 @@ /// conditional branch or it's and / or with other conditions before being used /// as the condition. static bool isUsedByExitBranch(ICmpInst *Cond, Loop *L) { - BasicBlock *CondBB = Cond->getParent(); + BasicBlock *CondBB = Cond->getParent(); if (!L->isLoopExiting(CondBB)) return false; BranchInst *TermBr = dyn_cast(CondBB->getTerminator()); @@ -2482,106 +2482,119 @@ /// OptimizeLoopTermCond - Change loop terminating condition to use the /// postinc iv when possible. void LoopStrengthReduce::OptimizeLoopTermCond(Loop *L) { - // Finally, get the terminating condition for the loop if possible. If we - // can, we want to change it to use a post-incremented version of its - // induction variable, to allow coalescing the live ranges for the IV into - // one register value. BasicBlock *LatchBlock = L->getLoopLatch(); - BasicBlock *ExitingBlock = L->getExitingBlock(); + bool LatchExit = L->isLoopExiting(LatchBlock); + SmallVector ExitingBlocks; + L->getExitingBlocks(ExitingBlocks); + + for (unsigned i = 0, e = ExitingBlocks.size(); i != e; ++i) { + BasicBlock *ExitingBlock = ExitingBlocks[i]; + + // Finally, get the terminating condition for the loop if possible. If we + // can, we want to change it to use a post-incremented version of its + // induction variable, to allow coalescing the live ranges for the IV into + // one register value. - if (!ExitingBlock) - // Multiple exits, just look at the exit in the latch block if there is one. - ExitingBlock = LatchBlock; - BranchInst *TermBr = dyn_cast(ExitingBlock->getTerminator()); - if (!TermBr) - return; - if (TermBr->isUnconditional() || !isa(TermBr->getCondition())) - return; - - // Search IVUsesByStride to find Cond's IVUse if there is one. - IVStrideUse *CondUse = 0; - const SCEV *CondStride = 0; - ICmpInst *Cond = cast(TermBr->getCondition()); - if (!FindIVUserForCond(Cond, CondUse, CondStride)) - return; - - bool UsePostInc = true; - if (ExitingBlock != LatchBlock) { - if (Cond->hasOneUse()) { - // See below, we don't want the condition to be cloned. - - // If exiting block is the latch block, we know it's safe and profitable - // to transform the icmp to use post-inc iv. Otherwise do so only if it - // would not reuse another iv and its iv would be reused by other uses. - // We are optimizing for the case where the icmp is the only use of the - // iv. - IVUsersOfOneStride &StrideUses = *IU->IVUsesByStride[CondStride]; - for (ilist::iterator I = StrideUses.Users.begin(), - E = StrideUses.Users.end(); I != E; ++I) { - if (I->getUser() == Cond) - continue; - if (!I->isUseOfPostIncrementedValue()) { - UsePostInc = false; - break; + BranchInst *TermBr = dyn_cast(ExitingBlock->getTerminator()); + if (!TermBr) + continue; + // FIXME: Overly conservative, termination condition could be an 'or' etc.. + if (TermBr->isUnconditional() || !isa(TermBr->getCondition())) + continue; + + // Search IVUsesByStride to find Cond's IVUse if there is one. + IVStrideUse *CondUse = 0; + const SCEV *CondStride = 0; + ICmpInst *Cond = cast(TermBr->getCondition()); + if (!FindIVUserForCond(Cond, CondUse, CondStride)) + continue; + + // If the latch block is exiting and it's not a single block loop, it's + // not safe to use postinc iv in other exiting blocks. FIXME: overly + // conservative? How about icmp stride optimization? + bool UsePostInc = !(e > 1 && LatchExit && ExitingBlock != LatchBlock); + if (UsePostInc && ExitingBlock != LatchBlock) { + if (!Cond->hasOneUse()) + // See below, we don't want the condition to be cloned. + UsePostInc = false; + else { + // If exiting block is the latch block, we know it's safe and profitable + // to transform the icmp to use post-inc iv. Otherwise do so only if it + // would not reuse another iv and its iv would be reused by other uses. + // We are optimizing for the case where the icmp is the only use of the + // iv. + IVUsersOfOneStride &StrideUses = *IU->IVUsesByStride[CondStride]; + for (ilist::iterator I = StrideUses.Users.begin(), + E = StrideUses.Users.end(); I != E; ++I) { + if (I->getUser() == Cond) + continue; + if (!I->isUseOfPostIncrementedValue()) { + UsePostInc = false; + break; + } } } + + // If iv for the stride might be shared and any of the users use pre-inc + // iv might be used, then it's not safe to use post-inc iv. + if (UsePostInc && + isa(CondStride) && + StrideMightBeShared(CondStride, L, true)) + UsePostInc = false; } - // If iv for the stride might be shared and any of the users use pre-inc iv - // might be used, then it's not safe to use post-inc iv. - if (UsePostInc && - isa(CondStride) && - StrideMightBeShared(CondStride, L, true)) - UsePostInc = false; - } + // If the trip count is computed in terms of a max (due to ScalarEvolution + // being unable to find a sufficient guard, for example), change the loop + // comparison to use SLT or ULT instead of NE. + Cond = OptimizeMax(L, Cond, CondUse); + + // If possible, change stride and operands of the compare instruction to + // eliminate one stride. However, avoid rewriting the compare instruction + // with an iv of new stride if it's likely the new stride uses will be + // rewritten using the stride of the compare instruction. + if (ExitingBlock == LatchBlock && isa(CondStride)) { + // If the condition stride is a constant and it's the only use, we might + // want to optimize it first by turning it to count toward zero. + if (!StrideMightBeShared(CondStride, L, false) && + !ShouldCountToZero(Cond, CondUse, SE, L, TLI)) + Cond = ChangeCompareStride(L, Cond, CondUse, CondStride); + } - // If the trip count is computed in terms of a max (due to ScalarEvolution - // being unable to find a sufficient guard, for example), change the loop - // comparison to use SLT or ULT instead of NE. - Cond = OptimizeMax(L, Cond, CondUse); - - // If possible, change stride and operands of the compare instruction to - // eliminate one stride. However, avoid rewriting the compare instruction with - // an iv of new stride if it's likely the new stride uses will be rewritten - // using the stride of the compare instruction. - if (ExitingBlock == LatchBlock && isa(CondStride)) { - // If the condition stride is a constant and it's the only use, we might - // want to optimize it first by turning it to count toward zero. - if (!StrideMightBeShared(CondStride, L, false) && - !ShouldCountToZero(Cond, CondUse, SE, L, TLI)) - Cond = ChangeCompareStride(L, Cond, CondUse, CondStride); - } + if (!UsePostInc) + continue; - if (!UsePostInc) - return; + DEBUG(errs() << " Change loop exiting icmp to use postinc iv: " + << *Cond << '\n'); - // It's possible for the setcc instruction to be anywhere in the loop, and - // possible for it to have multiple users. If it is not immediately before - // the latch block branch, move it. - if (&*++BasicBlock::iterator(Cond) != (Instruction*)TermBr) { - if (Cond->hasOneUse()) { // Condition has a single use, just move it. - Cond->moveBefore(TermBr); - } else { - // Otherwise, clone the terminating condition and insert into the loopend. - Cond = cast(Cond->clone()); - Cond->setName(L->getHeader()->getName() + ".termcond"); - LatchBlock->getInstList().insert(TermBr, Cond); + // It's possible for the setcc instruction to be anywhere in the loop, and + // possible for it to have multiple users. If it is not immediately before + // the exiting block branch, move it. + if (&*++BasicBlock::iterator(Cond) != (Instruction*)TermBr) { + if (Cond->hasOneUse()) { // Condition has a single use, just move it. + Cond->moveBefore(TermBr); + } else { + // Otherwise, clone the terminating condition and insert into the + // loopend. + Cond = cast(Cond->clone()); + Cond->setName(L->getHeader()->getName() + ".termcond"); + ExitingBlock->getInstList().insert(TermBr, Cond); - // Clone the IVUse, as the old use still exists! - IU->IVUsesByStride[CondStride]->addUser(CondUse->getOffset(), Cond, + // Clone the IVUse, as the old use still exists! + IU->IVUsesByStride[CondStride]->addUser(CondUse->getOffset(), Cond, CondUse->getOperandValToReplace()); - CondUse = &IU->IVUsesByStride[CondStride]->Users.back(); + CondUse = &IU->IVUsesByStride[CondStride]->Users.back(); + } } - } - // If we get to here, we know that we can transform the setcc instruction to - // use the post-incremented version of the IV, allowing us to coalesce the - // live ranges for the IV correctly. - CondUse->setOffset(SE->getMinusSCEV(CondUse->getOffset(), CondStride)); - CondUse->setIsUseOfPostIncrementedValue(true); - Changed = true; + // If we get to here, we know that we can transform the setcc instruction to + // use the post-incremented version of the IV, allowing us to coalesce the + // live ranges for the IV correctly. + CondUse->setOffset(SE->getMinusSCEV(CondUse->getOffset(), CondStride)); + CondUse->setIsUseOfPostIncrementedValue(true); + Changed = true; - ++NumLoopCond; + ++NumLoopCond; + } } bool LoopStrengthReduce::OptimizeLoopCountIVOfStride(const SCEV* &Stride, @@ -2728,7 +2741,6 @@ } bool LoopStrengthReduce::runOnLoop(Loop *L, LPPassManager &LPM) { - IU = &getAnalysis(); LI = &getAnalysis(); DT = &getAnalysis(); Added: llvm/trunk/test/Transforms/LoopStrengthReduce/icmp_use_postinc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/icmp_use_postinc.ll?rev=89116&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopStrengthReduce/icmp_use_postinc.ll (added) +++ llvm/trunk/test/Transforms/LoopStrengthReduce/icmp_use_postinc.ll Tue Nov 17 12:10:11 2009 @@ -0,0 +1,27 @@ +; RUN: opt < %s -loop-reduce -S | FileCheck %s + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp { +entry: + br i1 undef, label %bb4.preheader, label %bb.nph8 + +bb4.preheader: ; preds = %entry + br label %bb4 + +bb1: ; preds = %bb4 + br i1 undef, label %bb.nph8, label %bb3 + +bb3: ; preds = %bb1 + %phitmp = add i32 %indvar, 1 ; [#uses=1] + br label %bb4 + +bb4: ; preds = %bb3, %bb4.preheader +; CHECK: %lsr.iv = phi +; CHECK: %lsr.iv.next = add i32 %lsr.iv, 1 +; CHECK: %0 = icmp slt i32 %lsr.iv.next, %argc + %indvar = phi i32 [ 1, %bb4.preheader ], [ %phitmp, %bb3 ] ; [#uses=2] + %0 = icmp slt i32 %indvar, %argc ; [#uses=1] + br i1 %0, label %bb1, label %bb.nph8 + +bb.nph8: ; preds = %bb4, %bb1, %entry + unreachable +} From bob.wilson at apple.com Tue Nov 17 12:30:09 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 17 Nov 2009 18:30:09 -0000 Subject: [llvm-commits] [llvm] r89121 - /llvm/trunk/lib/CodeGen/BranchFolding.cpp Message-ID: <200911171830.nAHIU9WO003938@zion.cs.uiuc.edu> Author: bwilson Date: Tue Nov 17 12:30:09 2009 New Revision: 89121 URL: http://llvm.org/viewvc/llvm-project?rev=89121&view=rev Log: Remove a special case for tail merging that seems to be both broken and unnecessary. It is broken because the "isIdenticalTo" check should be negated. If that is fixed, this code causes the CodeGen/X86/tail-opts.ll test to fail, in the dont_merge_oddly function. And, I confirmed that the regression is real -- the generated code is worse. As far as I can tell, that tail-opts.ll test is checking for what this code is supposed to handle and we're doing the right thing anyway. Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=89121&r1=89120&r2=89121&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Nov 17 12:30:09 2009 @@ -670,39 +670,6 @@ // this many instructions in common. unsigned minCommonTailLength = TailMergeSize; - // If there's a successor block, there are some cases which don't require - // new branching and as such are very likely to be profitable. - if (SuccBB) { - if (SuccBB->pred_size() == MergePotentials.size() && - !MergePotentials[0].getBlock()->empty()) { - // If all the predecessors have at least one tail instruction in common, - // merging is very likely to be a win since it won't require an increase - // in static branches, and it will decrease the static instruction count. - bool AllPredsMatch = true; - MachineBasicBlock::iterator FirstNonTerm; - unsigned MinNumTerms = CountTerminators(MergePotentials[0].getBlock(), - FirstNonTerm); - if (FirstNonTerm != MergePotentials[0].getBlock()->end()) { - for (unsigned i = 1, e = MergePotentials.size(); i != e; ++i) { - MachineBasicBlock::iterator OtherFirstNonTerm; - unsigned NumTerms = CountTerminators(MergePotentials[0].getBlock(), - OtherFirstNonTerm); - if (NumTerms < MinNumTerms) - MinNumTerms = NumTerms; - if (OtherFirstNonTerm == MergePotentials[i].getBlock()->end() || - OtherFirstNonTerm->isIdenticalTo(FirstNonTerm)) { - AllPredsMatch = false; - break; - } - } - - // If they all have an instruction in common, do any amount of merging. - if (AllPredsMatch) - minCommonTailLength = MinNumTerms + 1; - } - } - } - DEBUG(errs() << "\nTryTailMergeBlocks: "; for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i) errs() << "BB#" << MergePotentials[i].getBlock()->getNumber() From vkutuzov at accesssoftek.com Tue Nov 17 12:48:27 2009 From: vkutuzov at accesssoftek.com (Viktor Kutuzov) Date: Tue, 17 Nov 2009 18:48:27 -0000 Subject: [llvm-commits] [llvm] r89122 - in /llvm/trunk: include/llvm/ADT/Triple.h lib/Support/Triple.cpp tools/lto/LTOCodeGenerator.cpp Message-ID: <200911171848.nAHImRSq004695@zion.cs.uiuc.edu> Author: vkutuzov Date: Tue Nov 17 12:48:27 2009 New Revision: 89122 URL: http://llvm.org/viewvc/llvm-project?rev=89122&view=rev Log: Added getArchNameForAssembler method to the Triple class for which returns OS and Vendor independent target assembler arch. Modified: llvm/trunk/include/llvm/ADT/Triple.h llvm/trunk/lib/Support/Triple.cpp llvm/trunk/tools/lto/LTOCodeGenerator.cpp Modified: llvm/trunk/include/llvm/ADT/Triple.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=89122&r1=89121&r2=89122&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/Triple.h (original) +++ llvm/trunk/include/llvm/ADT/Triple.h Tue Nov 17 12:48:27 2009 @@ -239,6 +239,10 @@ /// environment components with a single string. void setOSAndEnvironmentName(StringRef Str); + /// getArchNameForAssembler - Get an architecture name that is understood by the + /// target assembler. + const char *getArchNameForAssembler(); + /// @} /// @name Static helpers for IDs. /// @{ Modified: llvm/trunk/lib/Support/Triple.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=89122&r1=89121&r2=89122&view=diff ============================================================================== --- llvm/trunk/lib/Support/Triple.cpp (original) +++ llvm/trunk/lib/Support/Triple.cpp Tue Nov 17 12:48:27 2009 @@ -179,6 +179,33 @@ return Triple::UnknownArch; } +// Returns architecture name that is unsderstood by the target assembler. +const char *Triple::getArchNameForAssembler() { + if (getOS() != Triple::Darwin && getVendor() != Triple::Apple) + return NULL; + + StringRef Str = getArchName(); + if (Str == "i386") + return "i386"; + if (Str == "x86_64") + return "x86_64"; + if (Str == "powerpc") + return "ppc"; + if (Str == "powerpc64") + return "ppc64"; + if (Str == "arm") + return "arm"; + if (Str == "armv4t" || Str == "thumbv4t") + return "armv4t"; + if (Str == "armv5" || Str == "armv5e" || Str == "thumbv5" || Str == "thumbv5e") + return "armv5"; + if (Str == "armv6" || Str == "thumbv6") + return "armv6"; + if (Str == "armv7" || Str == "thumbv7") + return "armv7"; + return NULL; +} + // void Triple::Parse() const { Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=89122&r1=89121&r2=89122&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Tue Nov 17 12:48:27 2009 @@ -24,6 +24,7 @@ #include "llvm/ModuleProvider.h" #include "llvm/PassManager.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/Triple.h" #include "llvm/Analysis/Passes.h" #include "llvm/Analysis/LoopPass.h" #include "llvm/Analysis/Verifier.h" @@ -242,51 +243,16 @@ // build argument list std::vector args; - std::string targetTriple = _linker.getModule()->getTargetTriple(); + llvm::Triple targetTriple(_linker.getModule()->getTargetTriple()); + const char *arch = targetTriple.getArchNameForAssembler(); + args.push_back(tool.c_str()); - if ( targetTriple.find("darwin") != std::string::npos ) { + + if (targetTriple.getOS() == Triple::Darwin) { // darwin specific command line options - if (strncmp(targetTriple.c_str(), "i386-apple-", 11) == 0) { - args.push_back("-arch"); - args.push_back("i386"); - } - else if (strncmp(targetTriple.c_str(), "x86_64-apple-", 13) == 0) { - args.push_back("-arch"); - args.push_back("x86_64"); - } - else if (strncmp(targetTriple.c_str(), "powerpc-apple-", 14) == 0) { - args.push_back("-arch"); - args.push_back("ppc"); - } - else if (strncmp(targetTriple.c_str(), "powerpc64-apple-", 16) == 0) { - args.push_back("-arch"); - args.push_back("ppc64"); - } - else if (strncmp(targetTriple.c_str(), "arm-apple-", 10) == 0) { - args.push_back("-arch"); - args.push_back("arm"); - } - else if ((strncmp(targetTriple.c_str(), "armv4t-apple-", 13) == 0) || - (strncmp(targetTriple.c_str(), "thumbv4t-apple-", 15) == 0)) { - args.push_back("-arch"); - args.push_back("armv4t"); - } - else if ((strncmp(targetTriple.c_str(), "armv5-apple-", 12) == 0) || - (strncmp(targetTriple.c_str(), "armv5e-apple-", 13) == 0) || - (strncmp(targetTriple.c_str(), "thumbv5-apple-", 14) == 0) || - (strncmp(targetTriple.c_str(), "thumbv5e-apple-", 15) == 0)) { - args.push_back("-arch"); - args.push_back("armv5"); - } - else if ((strncmp(targetTriple.c_str(), "armv6-apple-", 12) == 0) || - (strncmp(targetTriple.c_str(), "thumbv6-apple-", 14) == 0)) { - args.push_back("-arch"); - args.push_back("armv6"); - } - else if ((strncmp(targetTriple.c_str(), "armv7-apple-", 12) == 0) || - (strncmp(targetTriple.c_str(), "thumbv7-apple-", 14) == 0)) { + if (arch != NULL) { args.push_back("-arch"); - args.push_back("armv7"); + args.push_back(arch); } // add -static to assembler command line when code model requires if ( (_assemblerPath != NULL) && (_codeModel == LTO_CODEGEN_PIC_MODEL_STATIC) ) From grosbach at apple.com Tue Nov 17 13:05:36 2009 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 17 Nov 2009 19:05:36 -0000 Subject: [llvm-commits] [llvm] r89123 - /llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <200911171905.nAHJ5ae8005335@zion.cs.uiuc.edu> Author: grosbach Date: Tue Nov 17 13:05:35 2009 New Revision: 89123 URL: http://llvm.org/viewvc/llvm-project?rev=89123&view=rev Log: 80-column violations Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=89123&r1=89122&r2=89123&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue Nov 17 13:05:35 2009 @@ -163,7 +163,8 @@ void StrengthReduceIVUsers(Loop *L); ICmpInst *ChangeCompareStride(Loop *L, ICmpInst *Cond, - IVStrideUse* &CondUse, const SCEV* &CondStride, + IVStrideUse* &CondUse, + const SCEV* &CondStride, bool PostPass = false); bool FindIVUserForCond(ICmpInst *Cond, IVStrideUse *&CondUse, @@ -1137,8 +1138,8 @@ } /// CollectIVUsers - Transform our list of users and offsets to a bit more -/// complex table. In this new vector, each 'BasedUser' contains 'Base', the base -/// of the strided accesses, as well as the old information from Uses. We +/// complex table. In this new vector, each 'BasedUser' contains 'Base', the +/// base of the strided accesses, as well as the old information from Uses. We /// progressively move information from the Base field to the Imm field, until /// we eventually have the full access expression to rewrite the use. const SCEV *LoopStrengthReduce::CollectIVUsers(const SCEV *const &Stride, @@ -1517,9 +1518,10 @@ /// StrengthReduceIVUsersOfStride - Strength reduce all of the users of a single /// stride of IV. All of the users may have different starting values, and this /// may not be the only stride. -void LoopStrengthReduce::StrengthReduceIVUsersOfStride(const SCEV *const &Stride, - IVUsersOfOneStride &Uses, - Loop *L) { +void +LoopStrengthReduce::StrengthReduceIVUsersOfStride(const SCEV *const &Stride, + IVUsersOfOneStride &Uses, + Loop *L) { // If all the users are moved to another stride, then there is nothing to do. if (Uses.Users.empty()) return; @@ -1818,8 +1820,9 @@ /// FindIVUserForCond - If Cond has an operand that is an expression of an IV, /// set the IV user and stride information and return true, otherwise return /// false. -bool LoopStrengthReduce::FindIVUserForCond(ICmpInst *Cond, IVStrideUse *&CondUse, - const SCEV* &CondStride) { +bool LoopStrengthReduce::FindIVUserForCond(ICmpInst *Cond, + IVStrideUse *&CondUse, + const SCEV* &CondStride) { for (unsigned Stride = 0, e = IU->StrideOrder.size(); Stride != e && !CondUse; ++Stride) { std::map::iterator SI = From stoklund at 2pi.dk Tue Nov 17 13:15:51 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 17 Nov 2009 19:15:51 -0000 Subject: [llvm-commits] [llvm] r89125 - in /llvm/trunk: lib/CodeGen/PHIElimination.cpp test/CodeGen/X86/2008-04-15-LiveVariableBug.ll test/CodeGen/X86/stack-color-with-reg.ll Message-ID: <200911171915.nAHJFpwH005717@zion.cs.uiuc.edu> Author: stoklund Date: Tue Nov 17 13:15:50 2009 New Revision: 89125 URL: http://llvm.org/viewvc/llvm-project?rev=89125&view=rev Log: Enable -split-phi-edges by default, except when -regalloc=local. The local register allocator doesn't like it when LiveVariables is run. We should also disable edge splitting under -O0, but that has to wait a bit. Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89125&r1=89124&r2=89125&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Tue Nov 17 13:15:50 2009 @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/Function.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/SmallPtrSet.h" @@ -39,7 +40,7 @@ static cl::opt SplitEdges("split-phi-edges", cl::desc("Split critical edges during phi elimination"), - cl::init(false), cl::Hidden); + cl::init(true), cl::Hidden); char PHIElimination::ID = 0; static RegisterPass @@ -47,10 +48,21 @@ const PassInfo *const llvm::PHIEliminationID = &X; +namespace llvm { FunctionPass *createLocalRegisterAllocator(); } + +// Should we run edge splitting? +static bool shouldSplitEdges() { + // Edge splitting breaks the local register allocator. It cannot tolerate + // LiveVariables being run. + if (RegisterRegAlloc::getDefault() == createLocalRegisterAllocator) + return false; + return SplitEdges; +} + void llvm::PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved(); AU.addPreserved(); - if (SplitEdges) { + if (shouldSplitEdges()) { AU.addRequired(); } else { AU.setPreservesCFG(); @@ -67,7 +79,7 @@ bool Changed = false; // Split critical edges to help the coalescer - if (SplitEdges) + if (shouldSplitEdges()) for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) Changed |= SplitPHIEdges(Fn, *I); Modified: llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll?rev=89125&r1=89124&r2=89125&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll Tue Nov 17 13:15:50 2009 @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin ; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local +; PR5534 %struct.CGPoint = type { double, double } %struct.NSArray = type { %struct.NSObject } Modified: llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll?rev=89125&r1=89124&r2=89125&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll (original) +++ llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll Tue Nov 17 13:15:50 2009 @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t ; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 6 -; RUN: grep asm-printer %t | grep 177 +; RUN: grep asm-printer %t | grep 175 type { [62 x %struct.Bitvec*] } ; type %0 type { i8* } ; type %1 From evan.cheng at apple.com Tue Nov 17 13:19:01 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 17 Nov 2009 19:19:01 -0000 Subject: [llvm-commits] [llvm] r89129 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp Message-ID: <200911171919.nAHJJ1YA005865@zion.cs.uiuc.edu> Author: evancheng Date: Tue Nov 17 13:19:01 2009 New Revision: 89129 URL: http://llvm.org/viewvc/llvm-project?rev=89129&view=rev Log: Fix comment. Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=89129&r1=89128&r2=89129&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Tue Nov 17 13:19:01 2009 @@ -242,9 +242,9 @@ // to decide whether the loaded value is actually a constant. If so, we can // actually use it as a load. if (!I.isInvariantLoad(AA)) - // FIXME: we should be able to sink loads with no other side effects if - // there is nothing that can change memory from here until the end of - // block. This is a trivial form of alias analysis. + // FIXME: we should be able to hoist loads with no other side effects if + // there are no other instructions which can change memory in this loop. + // This is a trivial form of alias analysis. return false; } From evan.cheng at apple.com Tue Nov 17 13:19:59 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 17 Nov 2009 19:19:59 -0000 Subject: [llvm-commits] [llvm] r89130 - in /llvm/trunk: include/llvm/CodeGen/MachineBasicBlock.h include/llvm/CodeGen/MachineDominators.h lib/CodeGen/MachineBasicBlock.cpp Message-ID: <200911171920.nAHJK0jx005927@zion.cs.uiuc.edu> Author: evancheng Date: Tue Nov 17 13:19:59 2009 New Revision: 89130 URL: http://llvm.org/viewvc/llvm-project?rev=89130&view=rev Log: Add a WriteAsOperand for MachineBasicBlock so MachineLoopInfo dump looks sane. Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h llvm/trunk/include/llvm/CodeGen/MachineDominators.h llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=89130&r1=89129&r2=89130&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Tue Nov 17 13:19:59 2009 @@ -358,6 +358,8 @@ raw_ostream& operator<<(raw_ostream &OS, const MachineBasicBlock &MBB); +void WriteAsOperand(raw_ostream &, const MachineBasicBlock*, bool t); + //===--------------------------------------------------------------------===// // GraphTraits specializations for machine basic block graphs (machine-CFGs) //===--------------------------------------------------------------------===// Modified: llvm/trunk/include/llvm/CodeGen/MachineDominators.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineDominators.h?rev=89130&r1=89129&r2=89130&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineDominators.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineDominators.h Tue Nov 17 13:19:59 2009 @@ -23,8 +23,6 @@ namespace llvm { -inline void WriteAsOperand(raw_ostream &, const MachineBasicBlock*, bool t) { } - template<> inline void DominatorTreeBase::addRoot(MachineBasicBlock* MBB) { this->Roots.push_back(MBB); Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=89130&r1=89129&r2=89130&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Tue Nov 17 13:19:59 2009 @@ -447,3 +447,8 @@ } return MadeChange; } + +void llvm::WriteAsOperand(raw_ostream &OS, const MachineBasicBlock *MBB, + bool t) { + OS << "BB#" << MBB->getNumber(); +} From evan.cheng at apple.com Tue Nov 17 13:28:12 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 17 Nov 2009 11:28:12 -0800 Subject: [llvm-commits] [llvm] r89125 - in /llvm/trunk: lib/CodeGen/PHIElimination.cpp test/CodeGen/X86/2008-04-15-LiveVariableBug.ll test/CodeGen/X86/stack-color-with-reg.ll In-Reply-To: <200911171915.nAHJFpwH005717@zion.cs.uiuc.edu> References: <200911171915.nAHJFpwH005717@zion.cs.uiuc.edu> Message-ID: Hi Jakob, I don't think this is the right way to do it. Checking RegisterRegAlloc::getDefault() seems pretty horrible. If I understand correctly, PHI elim should not require LiveVariables. It does this: LiveVariables *LV = getAnalysisIfAvailable(); So if LV is not available, i.e. not required by the register allocator, it should not perform splitting. That should work, right? Evan On Nov 17, 2009, at 11:15 AM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Tue Nov 17 13:15:50 2009 > New Revision: 89125 > > URL: http://llvm.org/viewvc/llvm-project?rev=89125&view=rev > Log: > Enable -split-phi-edges by default, except when -regalloc=local. > > The local register allocator doesn't like it when LiveVariables is run. > We should also disable edge splitting under -O0, but that has to wait a bit. > > Modified: > llvm/trunk/lib/CodeGen/PHIElimination.cpp > llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll > llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll > > Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89125&r1=89124&r2=89125&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) > +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Tue Nov 17 13:15:50 2009 > @@ -21,6 +21,7 @@ > #include "llvm/CodeGen/MachineInstr.h" > #include "llvm/CodeGen/MachineInstrBuilder.h" > #include "llvm/CodeGen/MachineRegisterInfo.h" > +#include "llvm/CodeGen/RegAllocRegistry.h" > #include "llvm/Function.h" > #include "llvm/Target/TargetMachine.h" > #include "llvm/ADT/SmallPtrSet.h" > @@ -39,7 +40,7 @@ > static cl::opt > SplitEdges("split-phi-edges", > cl::desc("Split critical edges during phi elimination"), > - cl::init(false), cl::Hidden); > + cl::init(true), cl::Hidden); > > char PHIElimination::ID = 0; > static RegisterPass > @@ -47,10 +48,21 @@ > > const PassInfo *const llvm::PHIEliminationID = &X; > > +namespace llvm { FunctionPass *createLocalRegisterAllocator(); } > + > +// Should we run edge splitting? > +static bool shouldSplitEdges() { > + // Edge splitting breaks the local register allocator. It cannot tolerate > + // LiveVariables being run. > + if (RegisterRegAlloc::getDefault() == createLocalRegisterAllocator) > + return false; > + return SplitEdges; > +} > + > void llvm::PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const { > AU.addPreserved(); > AU.addPreserved(); > - if (SplitEdges) { > + if (shouldSplitEdges()) { > AU.addRequired(); > } else { > AU.setPreservesCFG(); > @@ -67,7 +79,7 @@ > bool Changed = false; > > // Split critical edges to help the coalescer > - if (SplitEdges) > + if (shouldSplitEdges()) > for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) > Changed |= SplitPHIEdges(Fn, *I); > > > Modified: llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll?rev=89125&r1=89124&r2=89125&view=diff > > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll Tue Nov 17 13:15:50 2009 > @@ -1,5 +1,6 @@ > ; RUN: llc < %s -mtriple=x86_64-apple-darwin > ; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local > +; PR5534 > > %struct.CGPoint = type { double, double } > %struct.NSArray = type { %struct.NSObject } > > Modified: llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll?rev=89125&r1=89124&r2=89125&view=diff > > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll (original) > +++ llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll Tue Nov 17 13:15:50 2009 > @@ -1,6 +1,6 @@ > ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t > ; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 6 > -; RUN: grep asm-printer %t | grep 177 > +; RUN: grep asm-printer %t | grep 175 > > type { [62 x %struct.Bitvec*] } ; type %0 > type { i8* } ; type %1 > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stoklund at 2pi.dk Tue Nov 17 13:39:52 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 17 Nov 2009 11:39:52 -0800 Subject: [llvm-commits] [llvm] r89125 - in /llvm/trunk: lib/CodeGen/PHIElimination.cpp test/CodeGen/X86/2008-04-15-LiveVariableBug.ll test/CodeGen/X86/stack-color-with-reg.ll In-Reply-To: References: <200911171915.nAHJFpwH005717@zion.cs.uiuc.edu> Message-ID: On Nov 17, 2009, at 11:28 AM, Evan Cheng wrote: > Hi Jakob, > > I don't think this is the right way to do it. Checking RegisterRegAlloc::getDefault() seems pretty horrible. Yes, it is pretty horrible. > If I understand correctly, PHI elim should not require LiveVariables. It does this: > LiveVariables *LV = getAnalysisIfAvailable(); Will that work if LiveVariables is scheduled to run after PHIElimination? Can we control their order? > So if LV is not available, i.e. not required by the register allocator, it should not perform splitting. That should work, right? It is certainly possible to do it that way. I suppose that calling AU.setPreservesCFG() is less important? /jakob From evan.cheng at apple.com Tue Nov 17 13:47:40 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 17 Nov 2009 11:47:40 -0800 Subject: [llvm-commits] [llvm] r89125 - in /llvm/trunk: lib/CodeGen/PHIElimination.cpp test/CodeGen/X86/2008-04-15-LiveVariableBug.ll test/CodeGen/X86/stack-color-with-reg.ll In-Reply-To: References: <200911171915.nAHJFpwH005717@zion.cs.uiuc.edu> Message-ID: On Nov 17, 2009, at 11:39 AM, Jakob Stoklund Olesen wrote: > > On Nov 17, 2009, at 11:28 AM, Evan Cheng wrote: > >> Hi Jakob, >> >> I don't think this is the right way to do it. Checking RegisterRegAlloc::getDefault() seems pretty horrible. > > Yes, it is pretty horrible. > >> If I understand correctly, PHI elim should not require LiveVariables. It does this: >> LiveVariables *LV = getAnalysisIfAvailable(); > > Will that work if LiveVariables is scheduled to run after PHIElimination? Can we control their order? No. LiveVariables is an analysis pass. Later passes may require it. But that's ok, right? If it's run later, LV should do the right thing. But key point is if whatever is requiring phi elimination does not require LV, phi elimination should not bother with anything that needs LV info. > >> So if LV is not available, i.e. not required by the register allocator, it should not perform splitting. That should work, right? > > It is certainly possible to do it that way. I suppose that calling AU.setPreservesCFG() is less important? I am not sure. Please take a look at -debug-pass=Executions. Does phi elim splitting causes more passes to be run? Evan > > /jakob > From asl at math.spbu.ru Tue Nov 17 14:04:59 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Tue, 17 Nov 2009 20:04:59 -0000 Subject: [llvm-commits] [llvm] r89137 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Message-ID: <200911172005.nAHK50we007418@zion.cs.uiuc.edu> Author: asl Date: Tue Nov 17 14:04:59 2009 New Revision: 89137 URL: http://llvm.org/viewvc/llvm-project?rev=89137&view=rev Log: Both Darwin as and GNU as violate ARM docs wrt printing of addrmode6 alignment imm (in the same way). Fix asmprinting for non-darwin platforms. Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=89137&r1=89136&r2=89137&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Tue Nov 17 14:04:59 2009 @@ -637,11 +637,8 @@ O << "[" << getRegisterName(MO1.getReg()); if (MO4.getImm()) { - if (Subtarget->isTargetDarwin()) - O << ", :"; - else - O << " @"; - O << MO4.getImm(); + // FIXME: Both darwin as and GNU as violate ARM docs here. + O << ", :" << MO4.getImm(); } O << "]"; From stoklund at 2pi.dk Tue Nov 17 14:10:09 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 17 Nov 2009 12:10:09 -0800 Subject: [llvm-commits] [llvm] r89125 - in /llvm/trunk: lib/CodeGen/PHIElimination.cpp test/CodeGen/X86/2008-04-15-LiveVariableBug.ll test/CodeGen/X86/stack-color-with-reg.ll In-Reply-To: References: <200911171915.nAHJFpwH005717@zion.cs.uiuc.edu> Message-ID: <9B6465D3-E317-46CC-A572-A6643637E7A1@2pi.dk> On Nov 17, 2009, at 11:47 AM, Evan Cheng wrote: > > On Nov 17, 2009, at 11:39 AM, Jakob Stoklund Olesen wrote: > >> >> On Nov 17, 2009, at 11:28 AM, Evan Cheng wrote: >> >>> Hi Jakob, >>> >>> I don't think this is the right way to do it. Checking RegisterRegAlloc::getDefault() seems pretty horrible. >> >> Yes, it is pretty horrible. >> >>> If I understand correctly, PHI elim should not require LiveVariables. It does this: >>> LiveVariables *LV = getAnalysisIfAvailable(); >> >> Will that work if LiveVariables is scheduled to run after PHIElimination? Can we control their order? > > No. LiveVariables is an analysis pass. Later passes may require it. But that's ok, right? If it's run later, LV should do the right thing. But key point is if whatever is requiring phi elimination does not require LV, phi elimination should not bother with anything that needs LV info. Sure, but -split-phi-edges is supposed to be an optimization, so it would be nice to know is it is enabled or not. If I don't require LiveVariables, it is run immediately before PHIElimination. I don't know why. Is it a coincidence? If the pass manager decides to run LiveVariables after PHIElimination, the -split-phi-edges optimization is silently disabled. >>> So if LV is not available, i.e. not required by the register allocator, it should not perform splitting. That should work, right? >> >> It is certainly possible to do it that way. I suppose that calling AU.setPreservesCFG() is less important? > > I am not sure. Please take a look at -debug-pass=Executions. Does phi elim splitting causes more passes to be run? It causes 'Machine Natural Loop Construction' to be run again. From evan.cheng at apple.com Tue Nov 17 14:23:12 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 17 Nov 2009 12:23:12 -0800 Subject: [llvm-commits] [llvm] r89125 - in /llvm/trunk: lib/CodeGen/PHIElimination.cpp test/CodeGen/X86/2008-04-15-LiveVariableBug.ll test/CodeGen/X86/stack-color-with-reg.ll In-Reply-To: <9B6465D3-E317-46CC-A572-A6643637E7A1@2pi.dk> References: <200911171915.nAHJFpwH005717@zion.cs.uiuc.edu> <9B6465D3-E317-46CC-A572-A6643637E7A1@2pi.dk> Message-ID: <82C19C1E-0A01-4B37-BD02-3A5EA296C260@apple.com> On Nov 17, 2009, at 12:10 PM, Jakob Stoklund Olesen wrote: > > On Nov 17, 2009, at 11:47 AM, Evan Cheng wrote: > >> >> On Nov 17, 2009, at 11:39 AM, Jakob Stoklund Olesen wrote: >> >>> >>> On Nov 17, 2009, at 11:28 AM, Evan Cheng wrote: >>> >>>> Hi Jakob, >>>> >>>> I don't think this is the right way to do it. Checking RegisterRegAlloc::getDefault() seems pretty horrible. >>> >>> Yes, it is pretty horrible. >>> >>>> If I understand correctly, PHI elim should not require LiveVariables. It does this: >>>> LiveVariables *LV = getAnalysisIfAvailable(); >>> >>> Will that work if LiveVariables is scheduled to run after PHIElimination? Can we control their order? >> >> No. LiveVariables is an analysis pass. Later passes may require it. But that's ok, right? If it's run later, LV should do the right thing. But key point is if whatever is requiring phi elimination does not require LV, phi elimination should not bother with anything that needs LV info. > > Sure, but -split-phi-edges is supposed to be an optimization, so it would be nice to know is it is enabled or not. > > If I don't require LiveVariables, it is run immediately before PHIElimination. I don't know why. Is it a coincidence? I am not sure. Please talk to Devang about this. > > If the pass manager decides to run LiveVariables after PHIElimination, the -split-phi-edges optimization is silently disabled. That's ok for now. We only want to do it when the opportunity presents itself. That happens to be all the cases we care about now. That's a lot better than running livevariables with -regalloc=local. > > >>>> So if LV is not available, i.e. not required by the register allocator, it should not perform splitting. That should work, right? >>> >>> It is certainly possible to do it that way. I suppose that calling AU.setPreservesCFG() is less important? >> >> I am not sure. Please take a look at -debug-pass=Executions. Does phi elim splitting causes more passes to be run? > > It causes 'Machine Natural Loop Construction' to be run again. Should it be preserving MachineLoopInfo? Evan -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091117/0bbb4a83/attachment.html From vkutuzov at accesssoftek.com Tue Nov 17 14:26:02 2009 From: vkutuzov at accesssoftek.com (Viktor Kutuzov) Date: Tue, 17 Nov 2009 12:26:02 -0800 Subject: [llvm-commits] [PATCH] LTO code generator options In-Reply-To: <38a0d8450911170809j6a32716ar840b8622cfad6f17@mail.gmail.com> References: <04F6B1512E264B27AEE607542FCDD113@andreic6e7fe55> <9C7CA4093A8F41D7AD156ED3CF854D17@andreic6e7fe55> <38a0d8450911101625s5e3b7cb0m31ec0ce4d4144dc@mail.gmail.com> <38a0d8450911121059n6a0d3eb0ka34711d931c7675e@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BA@mail.accesssoftek.com> <38a0d8450911141921r7deec8b3k91e06950263f0485@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BF@mail.accesssoftek.com>, <38a0d8450911170809j6a32716ar840b8622cfad6f17@mail.gmail.com> Message-ID: <6AE1604EE3EC5F4296C096518C6B77EEFD4607C4@mail.accesssoftek.com> Thanks for reviewing it, Rafael. Now while we are both on the same waive, let's go with the rest of the patches. I have tried to combine them on the same manner as the last one. The attached patch has similar OS and Vendor independent re-factoring for Subtarget features (attributes). I moved Applce-specific code from tools/lto/LTOModule.cpp to lib/Target/SubtargetFeature.cpp with related header files update. Cheers, Viktor. ________________________________________ From: Rafael Espindola [espindola at google.com] Sent: Tuesday, November 17, 2009 8:09 AM To: Viktor Kutuzov Cc: Commit Messages and Patches for LLVM Subject: Re: [llvm-commits] [PATCH] LTO code generator options 2009/11/16 Viktor Kutuzov : > Please find the attached patch. > Does this look like what you want to see? > > I have moved the check for Darwin OS insode the getArchNameForAssembler which makes it OS and Vendor independent. This is what we wanted from the beginning, aren't we? > And added missed ppc64. Thanks for catching this. The patch looks good to me! Thanks a lot. > Thanks, > Viktor. Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-lto-codegen-subtargetfeature-default_feature.diff Type: text/x-patch Size: 4471 bytes Desc: llvm-lto-codegen-subtargetfeature-default_feature.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091117/9f03d6be/attachment.bin From stoklund at 2pi.dk Tue Nov 17 14:35:02 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 17 Nov 2009 12:35:02 -0800 Subject: [llvm-commits] [llvm] r89125 - in /llvm/trunk: lib/CodeGen/PHIElimination.cpp test/CodeGen/X86/2008-04-15-LiveVariableBug.ll test/CodeGen/X86/stack-color-with-reg.ll In-Reply-To: <82C19C1E-0A01-4B37-BD02-3A5EA296C260@apple.com> References: <200911171915.nAHJFpwH005717@zion.cs.uiuc.edu> <9B6465D3-E317-46CC-A572-A6643637E7A1@2pi.dk> <82C19C1E-0A01-4B37-BD02-3A5EA296C260@apple.com> Message-ID: <38DED367-12DD-4CD7-BC1C-BD6CBBC03E73@2pi.dk> On Nov 17, 2009, at 12:23 PM, Evan Cheng wrote: > > That's ok for now. We only want to do it when the opportunity presents itself. That happens to be all the cases we care about now. That's a lot better than running livevariables with -regalloc=local. OK, I'll do it that way, then. >>> I am not sure. Please take a look at -debug-pass=Executions. Does phi elim splitting causes more passes to be run? >> >> It causes 'Machine Natural Loop Construction' to be run again. > > Should it be preserving MachineLoopInfo? Possibly. That was non-trivial to do, so I left it out. From asl at math.spbu.ru Tue Nov 17 14:38:37 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Tue, 17 Nov 2009 20:38:37 -0000 Subject: [llvm-commits] [llvm] r89138 - in /llvm/trunk/test/CodeGen: ARM/spill-q.ll Thumb2/thumb2-spill-q.ll Message-ID: <200911172038.nAHKcbEO008614@zion.cs.uiuc.edu> Author: asl Date: Tue Nov 17 14:38:36 2009 New Revision: 89138 URL: http://llvm.org/viewvc/llvm-project?rev=89138&view=rev Log: Forgot to commit test fixes Modified: llvm/trunk/test/CodeGen/ARM/spill-q.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll Modified: llvm/trunk/test/CodeGen/ARM/spill-q.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/spill-q.ll?rev=89138&r1=89137&r2=89138&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/spill-q.ll (original) +++ llvm/trunk/test/CodeGen/ARM/spill-q.ll Tue Nov 17 14:38:36 2009 @@ -12,8 +12,8 @@ define arm_apcscc void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: ; CHECK: bic sp, sp, #15 -; CHECK: vst1.64 {{.*}}sp @128 -; CHECK: vld1.64 {{.*}}sp @128 +; CHECK: vst1.64 {{.*}}sp, :128 +; CHECK: vld1.64 {{.*}}sp, :128 entry: %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1] store float 6.300000e+01, float* undef, align 4 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll?rev=89138&r1=89137&r2=89138&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll Tue Nov 17 14:38:36 2009 @@ -12,8 +12,8 @@ define arm_apcscc void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: ; CHECK: bic sp, sp, #15 -; CHECK: vst1.64 {{.*}}sp @128 -; CHECK: vld1.64 {{.*}}sp @128 +; CHECK: vst1.64 {{.*}}sp, :128 +; CHECK: vld1.64 {{.*}}sp, :128 entry: %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1] store float 6.300000e+01, float* undef, align 4 From stoklund at 2pi.dk Tue Nov 17 14:46:01 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 17 Nov 2009 20:46:01 -0000 Subject: [llvm-commits] [llvm] r89139 - /llvm/trunk/lib/CodeGen/PHIElimination.cpp Message-ID: <200911172046.nAHKk160008871@zion.cs.uiuc.edu> Author: stoklund Date: Tue Nov 17 14:46:00 2009 New Revision: 89139 URL: http://llvm.org/viewvc/llvm-project?rev=89139&view=rev Log: Never call UpdateTerminator() when AnalyzeBranch would fail. Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89139&r1=89138&r2=89139&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Tue Nov 17 14:46:00 2009 @@ -445,9 +445,21 @@ MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A, MachineBasicBlock *B) { assert(A && B && "Missing MBB end point"); - ++NumSplits; MachineFunction *MF = A->getParent(); + + // We may need to update A's terminator, but we can't do that if AnalyzeBranch + // fails. + if (A->isLayoutSuccessor(B)) { + const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); + MachineBasicBlock *TBB = 0, *FBB = 0; + SmallVector Cond; + if (!TII->AnalyzeBranch(*A, TBB, FBB, Cond)) + return NULL; + } + + ++NumSplits; + MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock(); MF->push_back(NMBB); DEBUG(errs() << "PHIElimination splitting critical edge:" From stoklund at 2pi.dk Tue Nov 17 15:23:49 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 17 Nov 2009 21:23:49 -0000 Subject: [llvm-commits] [llvm] r89142 - /llvm/trunk/lib/CodeGen/PHIElimination.cpp Message-ID: <200911172123.nAHLNnFC010239@zion.cs.uiuc.edu> Author: stoklund Date: Tue Nov 17 15:23:49 2009 New Revision: 89142 URL: http://llvm.org/viewvc/llvm-project?rev=89142&view=rev Log: Disable -split-phi-edges to unbreak the buildbots Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89142&r1=89141&r2=89142&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Tue Nov 17 15:23:49 2009 @@ -40,7 +40,7 @@ static cl::opt SplitEdges("split-phi-edges", cl::desc("Split critical edges during phi elimination"), - cl::init(true), cl::Hidden); + cl::init(false), cl::Hidden); char PHIElimination::ID = 0; static RegisterPass From grosbach at apple.com Tue Nov 17 15:24:12 2009 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 17 Nov 2009 21:24:12 -0000 Subject: [llvm-commits] [llvm] r89143 - in /llvm/trunk: lib/Target/ARM/ARMConstantIslandPass.cpp test/CodeGen/Thumb2/thumb2-jtb.ll test/CodeGen/Thumb2/thumb2-tbh.ll Message-ID: <200911172124.nAHLOClW010281@zion.cs.uiuc.edu> Author: grosbach Date: Tue Nov 17 15:24:11 2009 New Revision: 89143 URL: http://llvm.org/viewvc/llvm-project?rev=89143&view=rev Log: Enable arm jumpt table adjustment. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp llvm/trunk/test/CodeGen/Thumb2/thumb2-jtb.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=89143&r1=89142&r2=89143&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Tue Nov 17 15:24:11 2009 @@ -48,7 +48,7 @@ static cl::opt -AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(false), +AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(true), cl::desc("Adjust basic block layout to better use TB[BH]")); namespace { Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-jtb.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-jtb.ll?rev=89143&r1=89142&r2=89143&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-jtb.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-jtb.ll Tue Nov 17 15:24:11 2009 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep tbb +; RUN: llc < %s -march=thumb -mattr=+thumb2 -arm-adjust-jump-tables=0 | not grep tbb ; Do not use tbb / tbh if any destination is before the jumptable. ; rdar://7102917 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll?rev=89143&r1=89142&r2=89143&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll Tue Nov 17 15:24:11 2009 @@ -1,7 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s ; Thumb2 target should reorder the bb's in order to use tbb / tbh. -; XFAIL: * %struct.R_flstr = type { i32, i32, i8* } %struct._T_tstr = type { i32, %struct.R_flstr*, %struct._T_tstr* } From grosbach at apple.com Tue Nov 17 15:37:04 2009 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 17 Nov 2009 21:37:04 -0000 Subject: [llvm-commits] [llvm] r89145 - /llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <200911172137.nAHLb4Tm010877@zion.cs.uiuc.edu> Author: grosbach Date: Tue Nov 17 15:37:04 2009 New Revision: 89145 URL: http://llvm.org/viewvc/llvm-project?rev=89145&view=rev Log: grammar Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=89145&r1=89144&r2=89145&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue Nov 17 15:37:04 2009 @@ -2603,8 +2603,8 @@ bool LoopStrengthReduce::OptimizeLoopCountIVOfStride(const SCEV* &Stride, IVStrideUse* &CondUse, Loop *L) { - // If the only use is an icmp of an loop exiting conditional branch, then - // attempts the optimization. + // If the only use is an icmp of a loop exiting conditional branch, then + // attempt the optimization. BasedUser User = BasedUser(*CondUse, SE); assert(isa(User.Inst) && "Expecting an ICMPInst!"); ICmpInst *Cond = cast(User.Inst); From stoklund at 2pi.dk Tue Nov 17 15:52:40 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 17 Nov 2009 21:52:40 -0000 Subject: [llvm-commits] [llvm] r89150 - /llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll Message-ID: <200911172152.nAHLqe0u011414@zion.cs.uiuc.edu> Author: stoklund Date: Tue Nov 17 15:52:40 2009 New Revision: 89150 URL: http://llvm.org/viewvc/llvm-project?rev=89150&view=rev Log: Remove fragile test. Modified: llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll Modified: llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll?rev=89150&r1=89149&r2=89150&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll (original) +++ llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll Tue Nov 17 15:52:40 2009 @@ -1,6 +1,5 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t ; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 6 -; RUN: grep asm-printer %t | grep 175 type { [62 x %struct.Bitvec*] } ; type %0 type { i8* } ; type %1 From echristo at apple.com Tue Nov 17 15:58:16 2009 From: echristo at apple.com (Eric Christopher) Date: Tue, 17 Nov 2009 21:58:16 -0000 Subject: [llvm-commits] [llvm] r89151 - in /llvm/trunk: include/llvm/ExecutionEngine/ExecutionEngine.h lib/ExecutionEngine/ExecutionEngine.cpp lib/ExecutionEngine/JIT/JIT.cpp lib/ExecutionEngine/JIT/JIT.h Message-ID: <200911172158.nAHLwGMc011569@zion.cs.uiuc.edu> Author: echristo Date: Tue Nov 17 15:58:16 2009 New Revision: 89151 URL: http://llvm.org/viewvc/llvm-project?rev=89151&view=rev Log: Add ability to set code model within the execution engine builders and creation interfaces. Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp llvm/trunk/lib/ExecutionEngine/JIT/JIT.h Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h?rev=89151&r1=89150&r2=89151&view=diff ============================================================================== --- llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h (original) +++ llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Tue Nov 17 15:58:16 2009 @@ -113,7 +113,8 @@ std::string *ErrorStr, JITMemoryManager *JMM, CodeGenOpt::Level OptLevel, - bool GVsWithCode); + bool GVsWithCode, + CodeModel::Model CMM); static ExecutionEngine *(*InterpCtor)(ModuleProvider *MP, std::string *ErrorStr); @@ -173,7 +174,9 @@ JITMemoryManager *JMM = 0, CodeGenOpt::Level OptLevel = CodeGenOpt::Default, - bool GVsWithCode = true); + bool GVsWithCode = true, + CodeModel::Model CMM = + CodeModel::Default); /// addModuleProvider - Add a ModuleProvider to the list of modules that we /// can JIT from. Note that this takes ownership of the ModuleProvider: when @@ -425,6 +428,7 @@ CodeGenOpt::Level OptLevel; JITMemoryManager *JMM; bool AllocateGVsWithCode; + CodeModel::Model CMModel; /// InitEngine - Does the common initialization of default options. /// @@ -434,6 +438,7 @@ OptLevel = CodeGenOpt::Default; JMM = NULL; AllocateGVsWithCode = false; + CMModel = CodeModel::Default; } public: @@ -478,6 +483,13 @@ return *this; } + /// setCodeModel - Set the CodeModel that the ExecutionEngine target + /// data is using. Defaults to target specific default "CodeModel::Default". + EngineBuilder &setCodeModel(CodeModel::Model M) { + CMModel = M; + return *this; + } + /// setAllocateGVsWithCode - Sets whether global values should be allocated /// into the same buffer as code. For most applications this should be set /// to false. Allocating globals with code breaks freeMachineCodeForFunction Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp?rev=89151&r1=89150&r2=89151&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Tue Nov 17 15:58:16 2009 @@ -40,7 +40,8 @@ std::string *ErrorStr, JITMemoryManager *JMM, CodeGenOpt::Level OptLevel, - bool GVsWithCode) = 0; + bool GVsWithCode, + CodeModel::Model CMM) = 0; ExecutionEngine *(*ExecutionEngine::InterpCtor)(ModuleProvider *MP, std::string *ErrorStr) = 0; ExecutionEngine::EERegisterFn ExecutionEngine::ExceptionTableRegister = 0; @@ -444,7 +445,7 @@ if (ExecutionEngine::JITCtor) { ExecutionEngine *EE = ExecutionEngine::JITCtor(MP, ErrorStr, JMM, OptLevel, - AllocateGVsWithCode); + AllocateGVsWithCode, CMModel); if (EE) return EE; } } Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp?rev=89151&r1=89150&r2=89151&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.cpp Tue Nov 17 15:58:16 2009 @@ -198,15 +198,17 @@ std::string *ErrorStr, JITMemoryManager *JMM, CodeGenOpt::Level OptLevel, - bool GVsWithCode) { - return JIT::createJIT(MP, ErrorStr, JMM, OptLevel, GVsWithCode); + bool GVsWithCode, + CodeModel::Model CMM) { + return JIT::createJIT(MP, ErrorStr, JMM, OptLevel, GVsWithCode, CMM); } ExecutionEngine *JIT::createJIT(ModuleProvider *MP, std::string *ErrorStr, JITMemoryManager *JMM, CodeGenOpt::Level OptLevel, - bool GVsWithCode) { + bool GVsWithCode, + CodeModel::Model CMM) { // Make sure we can resolve symbols in the program as well. The zero arg // to the function tells DynamicLibrary to load the program, not a library. if (sys::DynamicLibrary::LoadLibraryPermanently(0, ErrorStr)) @@ -215,6 +217,7 @@ // Pick a target either via -march or by guessing the native arch. TargetMachine *TM = JIT::selectTarget(MP, ErrorStr); if (!TM || (ErrorStr && ErrorStr->length() > 0)) return 0; + TM->setCodeModel(CMM); // If the target supports JIT code generation, create a the JIT. if (TargetJITInfo *TJ = TM->getJITInfo()) { Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.h?rev=89151&r1=89150&r2=89151&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.h (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.h Tue Nov 17 15:58:16 2009 @@ -85,8 +85,10 @@ JITMemoryManager *JMM, CodeGenOpt::Level OptLevel = CodeGenOpt::Default, - bool GVsWithCode = true) { - return ExecutionEngine::createJIT(MP, Err, JMM, OptLevel, GVsWithCode); + bool GVsWithCode = true, + CodeModel::Model CMM = CodeModel::Default) { + return ExecutionEngine::createJIT(MP, Err, JMM, OptLevel, GVsWithCode, + CMM); } virtual void addModuleProvider(ModuleProvider *MP); @@ -175,7 +177,8 @@ std::string *ErrorStr, JITMemoryManager *JMM, CodeGenOpt::Level OptLevel, - bool GVsWithCode); + bool GVsWithCode, + CodeModel::Model CMM); // Run the JIT on F and return information about the generated code void runJITOnFunction(Function *F, MachineCodeInfo *MCI = 0); From echristo at apple.com Tue Nov 17 16:23:58 2009 From: echristo at apple.com (Eric Christopher) Date: Tue, 17 Nov 2009 14:23:58 -0800 Subject: [llvm-commits] [PATCH] Move stub allocation to the JITEmitter In-Reply-To: References: <0016e6470f36c55e08047834fde7@google.com> Message-ID: On Nov 16, 2009, at 4:07 PM, Jeffrey Yasskin wrote: > I've updated the patch to ToT at > http://codereview.appspot.com/download/issue153044_2015.diff. Few comments: + struct StubLayout { + size_t Size; + size_t Alignment; + }; Comment above it giving whether it's in bytes, bits, etc? +TargetJITInfo::StubLayout PPCJITInfo::getStubLayout() { + StubLayout Result = {10*4, 1}; + return Result; +} These could also use a block comment of the stub layout. I hate magic numbers. Not your fault that we have so many though :) + /// for external functions. TODO(jyasskin): Of course, external functions I think todos are for the readme file though you can reference that in your comment. Probably don't need your name though. Otherwise it looks fine, I'll run it through tests here real fast. -eric From dpatel at apple.com Tue Nov 17 16:39:08 2009 From: dpatel at apple.com (Devang Patel) Date: Tue, 17 Nov 2009 22:39:08 -0000 Subject: [llvm-commits] [llvm] r89156 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/Analysis/DebugInfo.cpp Message-ID: <200911172239.nAHMd8Ef013044@zion.cs.uiuc.edu> Author: dpatel Date: Tue Nov 17 16:39:08 2009 New Revision: 89156 URL: http://llvm.org/viewvc/llvm-project?rev=89156&view=rev Log: Remove dead code. Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h llvm/trunk/lib/Analysis/DebugInfo.cpp Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=89156&r1=89155&r2=89156&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Tue Nov 17 16:39:08 2009 @@ -468,15 +468,8 @@ Module &M; LLVMContext& VMContext; - // Cached values for uniquing and faster lookups. const Type *EmptyStructPtr; // "{}*". - Function *StopPointFn; // llvm.dbg.stoppoint - Function *FuncStartFn; // llvm.dbg.func.start - Function *RegionStartFn; // llvm.dbg.region.start - Function *RegionEndFn; // llvm.dbg.region.end Function *DeclareFn; // llvm.dbg.declare - StringMap StringCache; - DenseMap SimpleConstantCache; DIFactory(const DIFactory &); // DO NOT IMPLEMENT void operator=(const DIFactory&); // DO NOT IMPLEMENT @@ -605,23 +598,6 @@ DILocation CreateLocation(unsigned LineNo, unsigned ColumnNo, DIScope S, DILocation OrigLoc); - /// InsertStopPoint - Create a new llvm.dbg.stoppoint intrinsic invocation, - /// inserting it at the end of the specified basic block. - void InsertStopPoint(DICompileUnit CU, unsigned LineNo, unsigned ColNo, - BasicBlock *BB); - - /// InsertSubprogramStart - Create a new llvm.dbg.func.start intrinsic to - /// mark the start of the specified subprogram. - void InsertSubprogramStart(DISubprogram SP, BasicBlock *BB); - - /// InsertRegionStart - Insert a new llvm.dbg.region.start intrinsic call to - /// mark the start of a region for the specified scoping descriptor. - void InsertRegionStart(DIDescriptor D, BasicBlock *BB); - - /// InsertRegionEnd - Insert a new llvm.dbg.region.end intrinsic call to - /// mark the end of a region for the specified scoping descriptor. - void InsertRegionEnd(DIDescriptor D, BasicBlock *BB); - /// InsertDeclare - Insert a new llvm.dbg.declare intrinsic call. Instruction *InsertDeclare(llvm::Value *Storage, DIVariable D, BasicBlock *InsertAtEnd); Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=89156&r1=89155&r2=89156&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Tue Nov 17 16:39:08 2009 @@ -606,9 +606,7 @@ //===----------------------------------------------------------------------===// DIFactory::DIFactory(Module &m) - : M(m), VMContext(M.getContext()), StopPointFn(0), FuncStartFn(0), - RegionStartFn(0), RegionEndFn(0), - DeclareFn(0) { + : M(m), VMContext(M.getContext()), DeclareFn(0) { EmptyStructPtr = PointerType::getUnqual(StructType::get(VMContext)); } @@ -983,58 +981,6 @@ // DIFactory: Routines for inserting code into a function //===----------------------------------------------------------------------===// -/// InsertStopPoint - Create a new llvm.dbg.stoppoint intrinsic invocation, -/// inserting it at the end of the specified basic block. -void DIFactory::InsertStopPoint(DICompileUnit CU, unsigned LineNo, - unsigned ColNo, BasicBlock *BB) { - - // Lazily construct llvm.dbg.stoppoint function. - if (!StopPointFn) - StopPointFn = llvm::Intrinsic::getDeclaration(&M, - llvm::Intrinsic::dbg_stoppoint); - - // Invoke llvm.dbg.stoppoint - Value *Args[] = { - ConstantInt::get(llvm::Type::getInt32Ty(VMContext), LineNo), - ConstantInt::get(llvm::Type::getInt32Ty(VMContext), ColNo), - CU.getNode() - }; - CallInst::Create(StopPointFn, Args, Args+3, "", BB); -} - -/// InsertSubprogramStart - Create a new llvm.dbg.func.start intrinsic to -/// mark the start of the specified subprogram. -void DIFactory::InsertSubprogramStart(DISubprogram SP, BasicBlock *BB) { - // Lazily construct llvm.dbg.func.start. - if (!FuncStartFn) - FuncStartFn = Intrinsic::getDeclaration(&M, Intrinsic::dbg_func_start); - - // Call llvm.dbg.func.start which also implicitly sets a stoppoint. - CallInst::Create(FuncStartFn, SP.getNode(), "", BB); -} - -/// InsertRegionStart - Insert a new llvm.dbg.region.start intrinsic call to -/// mark the start of a region for the specified scoping descriptor. -void DIFactory::InsertRegionStart(DIDescriptor D, BasicBlock *BB) { - // Lazily construct llvm.dbg.region.start function. - if (!RegionStartFn) - RegionStartFn = Intrinsic::getDeclaration(&M, Intrinsic::dbg_region_start); - - // Call llvm.dbg.func.start. - CallInst::Create(RegionStartFn, D.getNode(), "", BB); -} - -/// InsertRegionEnd - Insert a new llvm.dbg.region.end intrinsic call to -/// mark the end of a region for the specified scoping descriptor. -void DIFactory::InsertRegionEnd(DIDescriptor D, BasicBlock *BB) { - // Lazily construct llvm.dbg.region.end function. - if (!RegionEndFn) - RegionEndFn = Intrinsic::getDeclaration(&M, Intrinsic::dbg_region_end); - - // Call llvm.dbg.region.end. - CallInst::Create(RegionEndFn, D.getNode(), "", BB); -} - /// InsertDeclare - Insert a new llvm.dbg.declare intrinsic call. Instruction *DIFactory::InsertDeclare(Value *Storage, DIVariable D, Instruction *InsertBefore) { From stoklund at 2pi.dk Tue Nov 17 18:02:18 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 18 Nov 2009 00:02:18 -0000 Subject: [llvm-commits] [llvm] r89167 - in /llvm/trunk: lib/CodeGen/PHIElimination.cpp test/CodeGen/X86/2009-11-17-UpdateTerminator.ll Message-ID: <200911180002.nAI02IY4016705@zion.cs.uiuc.edu> Author: stoklund Date: Tue Nov 17 18:02:18 2009 New Revision: 89167 URL: http://llvm.org/viewvc/llvm-project?rev=89167&view=rev Log: Fix inverted test and add testcase from failing self-host. Added: llvm/trunk/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89167&r1=89166&r2=89167&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Tue Nov 17 18:02:18 2009 @@ -449,14 +449,12 @@ MachineFunction *MF = A->getParent(); // We may need to update A's terminator, but we can't do that if AnalyzeBranch - // fails. - if (A->isLayoutSuccessor(B)) { - const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); - MachineBasicBlock *TBB = 0, *FBB = 0; - SmallVector Cond; - if (!TII->AnalyzeBranch(*A, TBB, FBB, Cond)) - return NULL; - } + // fails. If A uses a jump table, we won't touch it. + const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); + MachineBasicBlock *TBB = 0, *FBB = 0; + SmallVector Cond; + if (TII->AnalyzeBranch(*A, TBB, FBB, Cond)) + return NULL; ++NumSplits; @@ -474,7 +472,7 @@ // Insert unconditional "jump B" instruction in NMBB. NMBB->addSuccessor(B); - SmallVector Cond; + Cond.clear(); MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond); // Fix PHI nodes in B so they refer to NMBB instead of A Added: llvm/trunk/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll?rev=89167&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll Tue Nov 17 18:02:18 2009 @@ -0,0 +1,52 @@ +; RUN: llc -O3 < %s +; This test fails with: +; Assertion failed: (!B && "UpdateTerminators requires analyzable predecessors!"), function updateTerminator, MachineBasicBlock.cpp, line 255. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.2" + +%"struct.llvm::InlineAsm::ConstraintInfo" = type { i32, i8, i8, i8, i8, %"struct.std::vector, std::allocator >,std::allocator, std::allocator > > >" } +%"struct.std::_Vector_base >" = type { %"struct.std::_Vector_base >::_Vector_impl" } +%"struct.std::_Vector_base >::_Vector_impl" = type { %"struct.llvm::InlineAsm::ConstraintInfo"*, %"struct.llvm::InlineAsm::ConstraintInfo"*, %"struct.llvm::InlineAsm::ConstraintInfo"* } +%"struct.std::_Vector_base, std::allocator >,std::allocator, std::allocator > > >" = type { %"struct.std::_Vector_base, std::allocator >,std::allocator, std::allocator > > >::_Vector_impl" } +%"struct.std::_Vector_base, std::allocator >,std::allocator, std::allocator > > >::_Vector_impl" = type { %"struct.std::string"*, %"struct.std::string"*, %"struct.std::string"* } +%"struct.std::basic_string,std::allocator >::_Alloc_hider" = type { i8* } +%"struct.std::string" = type { %"struct.std::basic_string,std::allocator >::_Alloc_hider" } +%"struct.std::vector >" = type { %"struct.std::_Vector_base >" } +%"struct.std::vector, std::allocator >,std::allocator, std::allocator > > >" = type { %"struct.std::_Vector_base, std::allocator >,std::allocator, std::allocator > > >" } + +define zeroext i8 @_ZN4llvm9InlineAsm14ConstraintInfo5ParseENS_9StringRefERSt6vectorIS1_SaIS1_EE(%"struct.llvm::InlineAsm::ConstraintInfo"* nocapture %this, i64 %Str.0, i64 %Str.1, %"struct.std::vector >"* nocapture %ConstraintsSoFar) nounwind ssp align 2 { +entry: + br i1 undef, label %bb56, label %bb27.outer + +bb8: ; preds = %bb27.outer108, %bb13 + switch i8 undef, label %bb27.outer [ + i8 35, label %bb56 + i8 37, label %bb14 + i8 38, label %bb10 + i8 42, label %bb56 + ] + +bb27.outer: ; preds = %bb8, %entry + %I.2.ph = phi i8* [ undef, %entry ], [ %I.2.ph109, %bb8 ] ; [#uses=2] + br label %bb27.outer108 + +bb10: ; preds = %bb8 + %toBool = icmp eq i8 0, 0 ; [#uses=1] + %or.cond = and i1 undef, %toBool ; [#uses=1] + br i1 %or.cond, label %bb13, label %bb56 + +bb13: ; preds = %bb10 + br i1 undef, label %bb27.outer108, label %bb8 + +bb14: ; preds = %bb8 + ret i8 1 + +bb27.outer108: ; preds = %bb13, %bb27.outer + %I.2.ph109 = getelementptr i8* %I.2.ph, i64 undef ; [#uses=1] + %scevgep = getelementptr i8* %I.2.ph, i64 undef ; [#uses=0] + br label %bb8 + +bb56: ; preds = %bb10, %bb8, %bb8, %entry + ret i8 1 +} From gohman at apple.com Tue Nov 17 18:58:27 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 18 Nov 2009 00:58:27 -0000 Subject: [llvm-commits] [llvm] r89175 - in /llvm/trunk: include/llvm/Analysis/ValueTracking.h lib/Analysis/MemoryBuiltins.cpp lib/Analysis/ValueTracking.cpp Message-ID: <200911180058.nAI0wRjL018710@zion.cs.uiuc.edu> Author: djg Date: Tue Nov 17 18:58:27 2009 New Revision: 89175 URL: http://llvm.org/viewvc/llvm-project?rev=89175&view=rev Log: Simplify ComputeMultiple so that it doesn't depend on TargetData. Modified: llvm/trunk/include/llvm/Analysis/ValueTracking.h llvm/trunk/lib/Analysis/MemoryBuiltins.cpp llvm/trunk/lib/Analysis/ValueTracking.cpp Modified: llvm/trunk/include/llvm/Analysis/ValueTracking.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ValueTracking.h?rev=89175&r1=89174&r2=89175&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ValueTracking.h (original) +++ llvm/trunk/include/llvm/Analysis/ValueTracking.h Tue Nov 17 18:58:27 2009 @@ -68,8 +68,8 @@ /// Multiple. If unsuccessful, it returns false. Also, if V can be /// simplified to an integer, then the simplified V is returned in Val. Look /// through sext only if LookThroughSExt=true. - bool ComputeMultiple(Value *V, unsigned Base, Value *&Multiple, APInt &Val, - bool LookThroughSExt = false, const TargetData *TD = 0, + bool ComputeMultiple(Value *V, unsigned Base, Value *&Multiple, + bool LookThroughSExt = false, unsigned Depth = 0); /// CannotBeNegativeZero - Return true if we can prove that the specified FP Modified: llvm/trunk/lib/Analysis/MemoryBuiltins.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryBuiltins.cpp?rev=89175&r1=89174&r2=89175&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryBuiltins.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryBuiltins.cpp Tue Nov 17 18:58:27 2009 @@ -105,9 +105,8 @@ // return the multiple. Otherwise, return NULL. Value *MallocArg = CI->getOperand(1); Value *Multiple = NULL; - APInt Val(TD->getTypeSizeInBits(MallocArg->getType()->getScalarType()), 0); if (ComputeMultiple(MallocArg, ElementSize, Multiple, - Val, LookThroughSExt, TD)) + LookThroughSExt)) return Multiple; return NULL; Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=89175&r1=89174&r2=89175&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Tue Nov 17 18:58:27 2009 @@ -791,24 +791,19 @@ /// ComputeMultiple - This function computes the integer multiple of Base that /// equals V. If successful, it returns true and returns the multiple in -/// Multiple. If unsuccessful, it returns false. Also, if V can be -/// simplified to an integer, then the simplified V is returned in Val. It looks +/// Multiple. If unsuccessful, it returns false. It looks /// through SExt instructions only if LookThroughSExt is true. bool llvm::ComputeMultiple(Value *V, unsigned Base, Value *&Multiple, - APInt &Val, bool LookThroughSExt, - const TargetData *TD, unsigned Depth) { + bool LookThroughSExt, unsigned Depth) { const unsigned MaxDepth = 6; - assert(TD && V && "No Value?"); + assert(V && "No Value?"); assert(Depth <= MaxDepth && "Limit Search Depth"); assert(V->getType()->isInteger() && "Not integer or pointer type!"); const Type *T = V->getType(); - unsigned TSize = TD->getTypeSizeInBits(T->getScalarType()); - ConstantInt *CI = NULL; - if ((CI = dyn_cast(V))) - Val = CI->getValue(); + ConstantInt *CI = dyn_cast(V); if (Base == 0) return false; @@ -843,8 +838,8 @@ // otherwise fall through to ZExt } case Instruction::ZExt: { - return ComputeMultiple(I->getOperand(0), Base, Multiple, Val, - LookThroughSExt, TD, Depth+1); + return ComputeMultiple(I->getOperand(0), Base, Multiple, + LookThroughSExt, Depth+1); } case Instruction::Shl: case Instruction::Mul: { @@ -863,17 +858,15 @@ Value *Mul0 = NULL; Value *Mul1 = NULL; - APInt Val0(TSize, 0), Val1(TSize, 0); - bool M0 = ComputeMultiple(Op0, Base, Mul0, Val0, - LookThroughSExt, TD, Depth+1); - bool M1 = ComputeMultiple(Op1, Base, Mul1, Val1, - LookThroughSExt, TD, Depth+1); + bool M0 = ComputeMultiple(Op0, Base, Mul0, + LookThroughSExt, Depth+1); + bool M1 = ComputeMultiple(Op1, Base, Mul1, + LookThroughSExt, Depth+1); if (M0) { if (isa(Op1) && isa(Mul0)) { // V == Base * (Mul0 * Op1), so return (Mul0 * Op1) Multiple = ConstantExpr::getMul(cast(Mul0), - Val1.getBoolValue() ? ConstantInt::get(V->getContext(), Val1): cast(Op1)); return true; } @@ -890,7 +883,6 @@ if (isa(Op0) && isa(Mul1)) { // V == Base * (Mul1 * Op0), so return (Mul1 * Op0) Multiple = ConstantExpr::getMul(cast(Mul1), - Val0.getBoolValue() ? ConstantInt::get(V->getContext(), Val0): cast(Op0)); return true; } @@ -902,11 +894,6 @@ return true; } } - - if (Val0.getBoolValue() && Val1.getBoolValue()) - // Op1*Op2 was simplified, try computing multiple again. - return ComputeMultiple(ConstantInt::get(V->getContext(), Val0 * Val1), - Base, Multiple, Val, LookThroughSExt, TD, Depth+1); } } From isanbard at gmail.com Tue Nov 17 19:03:56 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 18 Nov 2009 01:03:56 -0000 Subject: [llvm-commits] [llvm] r89176 - in /llvm/trunk: include/llvm/Target/TargetData.h lib/Target/TargetData.cpp Message-ID: <200911180103.nAI13usJ018941@zion.cs.uiuc.edu> Author: void Date: Tue Nov 17 19:03:56 2009 New Revision: 89176 URL: http://llvm.org/viewvc/llvm-project?rev=89176&view=rev Log: The llvm-gcc front-end and the pass manager use two separate TargetData objects. This is probably not confined to *just* these two things. Anyway, the llvm-gcc front-end may look up the structure layout information for an abstract type. That information will be stored into a table with the FE's TD. Instruction combine can come along and also ask for information on that abstract type, but for a separate TD (the one associated with the pass manager). After the type is refined, the old structure layout information in the pass manager's TD file is out of date. If a new type is allocated in the same space as the old-unrefined type, then the structure type information in the pass manager's TD file will be wrong, but won't know it. Fix this by making the TD's structure type information an abstract type user. Modified: llvm/trunk/include/llvm/Target/TargetData.h llvm/trunk/lib/Target/TargetData.cpp Modified: llvm/trunk/include/llvm/Target/TargetData.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetData.h?rev=89176&r1=89175&r2=89176&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetData.h (original) +++ llvm/trunk/include/llvm/Target/TargetData.h Tue Nov 17 19:03:56 2009 @@ -30,6 +30,7 @@ class IntegerType; class StructType; class StructLayout; +class StructLayoutMap; class GlobalVariable; class LLVMContext; @@ -84,8 +85,8 @@ /// type and bit width were not found in the SmallVector. static const TargetAlignElem InvalidAlignmentElem; - // Opaque pointer for the StructType -> StructLayout map. - mutable void *LayoutMap; + // The StructType -> StructLayout map. + mutable StructLayoutMap *LayoutMap; //! Set/initialize target alignments void setAlignment(AlignTypeEnum align_type, unsigned char abi_align, Modified: llvm/trunk/lib/Target/TargetData.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetData.cpp?rev=89176&r1=89175&r2=89176&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetData.cpp (original) +++ llvm/trunk/lib/Target/TargetData.cpp Tue Nov 17 19:03:56 2009 @@ -17,9 +17,9 @@ //===----------------------------------------------------------------------===// #include "llvm/Target/TargetData.h" -#include "llvm/Module.h" -#include "llvm/DerivedTypes.h" #include "llvm/Constants.h" +#include "llvm/DerivedTypes.h" +#include "llvm/Module.h" #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/ManagedStatic.h" @@ -323,37 +323,130 @@ : Alignments[BestMatchIdx].PrefAlign; } -typedef DenseMapLayoutInfoTy; +typedef DenseMap LayoutInfoTy; -TargetData::~TargetData() { - if (!LayoutMap) - return; - - // Remove any layouts for this TD. - LayoutInfoTy &TheMap = *static_cast(LayoutMap); - for (LayoutInfoTy::iterator I = TheMap.begin(), E = TheMap.end(); I != E; ) { - I->second->~StructLayout(); - free(I->second); - TheMap.erase(I++); +namespace llvm { + +class StructLayoutMap : public AbstractTypeUser { + LayoutInfoTy LayoutInfo; + + /// refineAbstractType - The callback method invoked when an abstract type is + /// resolved to another type. An object must override this method to update + /// its internal state to reference NewType instead of OldType. + /// + virtual void refineAbstractType(const DerivedType *OldTy, + const Type *) { + const StructType *STy = dyn_cast(OldTy); + if (!STy) { + OldTy->removeAbstractTypeUser(this); + return; + } + + StructLayout *SL = LayoutInfo[STy]; + if (SL) { + SL->~StructLayout(); + free(SL); + LayoutInfo[STy] = NULL; + } + + OldTy->removeAbstractTypeUser(this); } - - delete static_cast(LayoutMap); + + /// typeBecameConcrete - The other case which AbstractTypeUsers must be aware + /// of is when a type makes the transition from being abstract (where it has + /// clients on its AbstractTypeUsers list) to concrete (where it does not). + /// This method notifies ATU's when this occurs for a type. + /// + virtual void typeBecameConcrete(const DerivedType *AbsTy) { + const StructType *STy = dyn_cast(AbsTy); + if (!STy) { + AbsTy->removeAbstractTypeUser(this); + return; + } + + StructLayout *SL = LayoutInfo[STy]; + if (SL) { + SL->~StructLayout(); + free(SL); + LayoutInfo[STy] = NULL; + } + + AbsTy->removeAbstractTypeUser(this); + } + + bool insert(const Type *Ty) { + if (Ty->isAbstract()) + Ty->addAbstractTypeUser(this); + return true; + } + +public: + virtual ~StructLayoutMap() { + // Remove any layouts. + for (LayoutInfoTy::iterator + I = LayoutInfo.begin(), E = LayoutInfo.end(); I != E; ++I) + if (StructLayout *SL = I->second) { + SL->~StructLayout(); + free(SL); + } + } + + inline LayoutInfoTy::iterator begin() { + return LayoutInfo.begin(); + } + inline LayoutInfoTy::iterator end() { + return LayoutInfo.end(); + } + inline LayoutInfoTy::const_iterator begin() const { + return LayoutInfo.begin(); + } + inline LayoutInfoTy::const_iterator end() const { + return LayoutInfo.end(); + } + + LayoutInfoTy::iterator find(const StructType *&Val) { + return LayoutInfo.find(Val); + } + LayoutInfoTy::const_iterator find(const StructType *&Val) const { + return LayoutInfo.find(Val); + } + + bool erase(const StructType *&Val) { + return LayoutInfo.erase(Val); + } + bool erase(LayoutInfoTy::iterator I) { + return LayoutInfo.erase(I); + } + + StructLayout *&operator[](const Type *Key) { + const StructType *STy = dyn_cast(Key); + assert(STy && "Trying to access the struct layout map with a non-struct!"); + insert(STy); + return LayoutInfo[STy]; + } + + // for debugging... + virtual void dump() const {} +}; + +} // end namespace llvm + +TargetData::~TargetData() { + delete LayoutMap; } const StructLayout *TargetData::getStructLayout(const StructType *Ty) const { if (!LayoutMap) - LayoutMap = static_cast(new LayoutInfoTy()); - - LayoutInfoTy &TheMap = *static_cast(LayoutMap); + LayoutMap = new StructLayoutMap(); - StructLayout *&SL = TheMap[Ty]; + StructLayout *&SL = (*LayoutMap)[Ty]; if (SL) return SL; // Otherwise, create the struct layout. Because it is variable length, we // malloc it, then use placement new. int NumElts = Ty->getNumElements(); StructLayout *L = - (StructLayout *)malloc(sizeof(StructLayout)+(NumElts-1)*sizeof(uint64_t)); + (StructLayout *)malloc(sizeof(StructLayout)+(NumElts-1) * sizeof(uint64_t)); // Set SL before calling StructLayout's ctor. The ctor could cause other // entries to be added to TheMap, invalidating our reference. @@ -370,13 +463,12 @@ void TargetData::InvalidateStructLayoutInfo(const StructType *Ty) const { if (!LayoutMap) return; // No cache. - LayoutInfoTy* LayoutInfo = static_cast(LayoutMap); - LayoutInfoTy::iterator I = LayoutInfo->find(Ty); - if (I == LayoutInfo->end()) return; + DenseMap::iterator I = LayoutMap->find(Ty); + if (I == LayoutMap->end()) return; I->second->~StructLayout(); free(I->second); - LayoutInfo->erase(I); + LayoutMap->erase(I); } From wendling at apple.com Tue Nov 17 19:07:52 2009 From: wendling at apple.com (Bill Wendling) Date: Tue, 17 Nov 2009 17:07:52 -0800 Subject: [llvm-commits] [llvm] r89176 - in /llvm/trunk: include/llvm/Target/TargetData.h lib/Target/TargetData.cpp In-Reply-To: <200911180103.nAI13usJ018941@zion.cs.uiuc.edu> References: <200911180103.nAI13usJ018941@zion.cs.uiuc.edu> Message-ID: The nature of this problem doesn't lend itself to a testcase, unfortunately. For instance, the testcase I got (from clang code) *passed* if I removed blank lines from the file. -bw On Nov 17, 2009, at 5:03 PM, Bill Wendling wrote: > Author: void > Date: Tue Nov 17 19:03:56 2009 > New Revision: 89176 > > URL: http://llvm.org/viewvc/llvm-project?rev=89176&view=rev > Log: > The llvm-gcc front-end and the pass manager use two separate > TargetData objects. > This is probably not confined to *just* these two things. > > Anyway, the llvm-gcc front-end may look up the structure layout > information for > an abstract type. That information will be stored into a table with > the FE's > TD. Instruction combine can come along and also ask for information > on that > abstract type, but for a separate TD (the one associated with the > pass manager). > > After the type is refined, the old structure layout information in > the pass > manager's TD file is out of date. If a new type is allocated in the > same space > as the old-unrefined type, then the structure type information in > the pass > manager's TD file will be wrong, but won't know it. > > Fix this by making the TD's structure type information an abstract > type user. > > Modified: > llvm/trunk/include/llvm/Target/TargetData.h > llvm/trunk/lib/Target/TargetData.cpp > > Modified: llvm/trunk/include/llvm/Target/TargetData.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetData.h?rev=89176&r1=89175&r2=89176&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Target/TargetData.h (original) > +++ llvm/trunk/include/llvm/Target/TargetData.h Tue Nov 17 19:03:56 > 2009 > @@ -30,6 +30,7 @@ > class IntegerType; > class StructType; > class StructLayout; > +class StructLayoutMap; > class GlobalVariable; > class LLVMContext; > > @@ -84,8 +85,8 @@ > /// type and bit width were not found in the SmallVector. > static const TargetAlignElem InvalidAlignmentElem; > > - // Opaque pointer for the StructType -> StructLayout map. > - mutable void *LayoutMap; > + // The StructType -> StructLayout map. > + mutable StructLayoutMap *LayoutMap; > > //! Set/initialize target alignments > void setAlignment(AlignTypeEnum align_type, unsigned char abi_align, > > Modified: llvm/trunk/lib/Target/TargetData.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetData.cpp?rev=89176&r1=89175&r2=89176&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/TargetData.cpp (original) > +++ llvm/trunk/lib/Target/TargetData.cpp Tue Nov 17 19:03:56 2009 > @@ -17,9 +17,9 @@ > // > = > = > = > ----------------------------------------------------------------------= > ==// > > #include "llvm/Target/TargetData.h" > -#include "llvm/Module.h" > -#include "llvm/DerivedTypes.h" > #include "llvm/Constants.h" > +#include "llvm/DerivedTypes.h" > +#include "llvm/Module.h" > #include "llvm/Support/GetElementPtrTypeIterator.h" > #include "llvm/Support/MathExtras.h" > #include "llvm/Support/ManagedStatic.h" > @@ -323,37 +323,130 @@ > : Alignments[BestMatchIdx].PrefAlign; > } > > -typedef DenseMapLayoutInfoTy; > +typedef DenseMap LayoutInfoTy; > > -TargetData::~TargetData() { > - if (!LayoutMap) > - return; > - > - // Remove any layouts for this TD. > - LayoutInfoTy &TheMap = *static_cast(LayoutMap); > - for (LayoutInfoTy::iterator I = TheMap.begin(), E = TheMap.end(); > I != E; ) { > - I->second->~StructLayout(); > - free(I->second); > - TheMap.erase(I++); > +namespace llvm { > + > +class StructLayoutMap : public AbstractTypeUser { > + LayoutInfoTy LayoutInfo; > + > + /// refineAbstractType - The callback method invoked when an > abstract type is > + /// resolved to another type. An object must override this > method to update > + /// its internal state to reference NewType instead of OldType. > + /// > + virtual void refineAbstractType(const DerivedType *OldTy, > + const Type *) { > + const StructType *STy = dyn_cast(OldTy); > + if (!STy) { > + OldTy->removeAbstractTypeUser(this); > + return; > + } > + > + StructLayout *SL = LayoutInfo[STy]; > + if (SL) { > + SL->~StructLayout(); > + free(SL); > + LayoutInfo[STy] = NULL; > + } > + > + OldTy->removeAbstractTypeUser(this); > } > - > - delete static_cast(LayoutMap); > + > + /// typeBecameConcrete - The other case which AbstractTypeUsers > must be aware > + /// of is when a type makes the transition from being abstract > (where it has > + /// clients on its AbstractTypeUsers list) to concrete (where it > does not). > + /// This method notifies ATU's when this occurs for a type. > + /// > + virtual void typeBecameConcrete(const DerivedType *AbsTy) { > + const StructType *STy = dyn_cast(AbsTy); > + if (!STy) { > + AbsTy->removeAbstractTypeUser(this); > + return; > + } > + > + StructLayout *SL = LayoutInfo[STy]; > + if (SL) { > + SL->~StructLayout(); > + free(SL); > + LayoutInfo[STy] = NULL; > + } > + > + AbsTy->removeAbstractTypeUser(this); > + } > + > + bool insert(const Type *Ty) { > + if (Ty->isAbstract()) > + Ty->addAbstractTypeUser(this); > + return true; > + } > + > +public: > + virtual ~StructLayoutMap() { > + // Remove any layouts. > + for (LayoutInfoTy::iterator > + I = LayoutInfo.begin(), E = LayoutInfo.end(); I != E; ++I) > + if (StructLayout *SL = I->second) { > + SL->~StructLayout(); > + free(SL); > + } > + } > + > + inline LayoutInfoTy::iterator begin() { > + return LayoutInfo.begin(); > + } > + inline LayoutInfoTy::iterator end() { > + return LayoutInfo.end(); > + } > + inline LayoutInfoTy::const_iterator begin() const { > + return LayoutInfo.begin(); > + } > + inline LayoutInfoTy::const_iterator end() const { > + return LayoutInfo.end(); > + } > + > + LayoutInfoTy::iterator find(const StructType *&Val) { > + return LayoutInfo.find(Val); > + } > + LayoutInfoTy::const_iterator find(const StructType *&Val) const { > + return LayoutInfo.find(Val); > + } > + > + bool erase(const StructType *&Val) { > + return LayoutInfo.erase(Val); > + } > + bool erase(LayoutInfoTy::iterator I) { > + return LayoutInfo.erase(I); > + } > + > + StructLayout *&operator[](const Type *Key) { > + const StructType *STy = dyn_cast(Key); > + assert(STy && "Trying to access the struct layout map with a > non-struct!"); > + insert(STy); > + return LayoutInfo[STy]; > + } > + > + // for debugging... > + virtual void dump() const {} > +}; > + > +} // end namespace llvm > + > +TargetData::~TargetData() { > + delete LayoutMap; > } > > const StructLayout *TargetData::getStructLayout(const StructType > *Ty) const { > if (!LayoutMap) > - LayoutMap = static_cast(new LayoutInfoTy()); > - > - LayoutInfoTy &TheMap = *static_cast(LayoutMap); > + LayoutMap = new StructLayoutMap(); > > - StructLayout *&SL = TheMap[Ty]; > + StructLayout *&SL = (*LayoutMap)[Ty]; > if (SL) return SL; > > // Otherwise, create the struct layout. Because it is variable > length, we > // malloc it, then use placement new. > int NumElts = Ty->getNumElements(); > StructLayout *L = > - (StructLayout *)malloc(sizeof(StructLayout)+(NumElts-1)*sizeof > (uint64_t)); > + (StructLayout *)malloc(sizeof(StructLayout)+(NumElts-1) * sizeof > (uint64_t)); > > // Set SL before calling StructLayout's ctor. The ctor could > cause other > // entries to be added to TheMap, invalidating our reference. > @@ -370,13 +463,12 @@ > void TargetData::InvalidateStructLayoutInfo(const StructType *Ty) > const { > if (!LayoutMap) return; // No cache. > > - LayoutInfoTy* LayoutInfo = static_cast(LayoutMap); > - LayoutInfoTy::iterator I = LayoutInfo->find(Ty); > - if (I == LayoutInfo->end()) return; > + DenseMap::iterator I = > LayoutMap->find(Ty); > + if (I == LayoutMap->end()) return; > > I->second->~StructLayout(); > free(I->second); > - LayoutInfo->erase(I); > + LayoutMap->erase(I); > } > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From jyasskin at gmail.com Tue Nov 17 21:12:09 2009 From: jyasskin at gmail.com (jyasskin at gmail.com) Date: Wed, 18 Nov 2009 03:12:09 +0000 Subject: [llvm-commits] [PATCH] Allow more than one stub to be being generated at the same time Message-ID: <0016e6470f36b3b16f04789c9bae@google.com> Reviewers: echristo_apple.com, Message: This will make it easier to fix a mistake I made in http://codereview.appspot.com/153044. http://codereview.appspot.com/download/issue156053_9.diff Please review this at http://codereview.appspot.com/156053 Affected files: M include/llvm/CodeGen/JITCodeEmitter.h M include/llvm/CodeGen/MachineCodeEmitter.h M lib/ExecutionEngine/JIT/JITEmitter.cpp M lib/Target/ARM/ARMJITInfo.cpp M lib/Target/Alpha/AlphaJITInfo.cpp M lib/Target/PowerPC/PPCJITInfo.cpp M lib/Target/X86/X86JITInfo.cpp From jyasskin at google.com Tue Nov 17 21:21:14 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Tue, 17 Nov 2009 19:21:14 -0800 Subject: [llvm-commits] [PATCH] Allow more than one stub to be being generated at the same time In-Reply-To: <0016e6470f36b3b16f04789c9bae@google.com> References: <0016e6470f36b3b16f04789c9bae@google.com> Message-ID: Nick points out that my links might have been confusing. Review http://codereview.appspot.com/156053 please. On Tue, Nov 17, 2009 at 7:12 PM, wrote: > Reviewers: echristo_apple.com, > > Message: > This will make it easier to fix a mistake I made in > http://codereview.appspot.com/153044. > > http://codereview.appspot.com/download/issue156053_9.diff > > > > Please review this at http://codereview.appspot.com/156053 > > Affected files: > ? M ? ? include/llvm/CodeGen/JITCodeEmitter.h > ? M ? ? include/llvm/CodeGen/MachineCodeEmitter.h > ? M ? ? lib/ExecutionEngine/JIT/JITEmitter.cpp > ? M ? ? lib/Target/ARM/ARMJITInfo.cpp > ? M ? ? lib/Target/Alpha/AlphaJITInfo.cpp > ? M ? ? lib/Target/PowerPC/PPCJITInfo.cpp > ? M ? ? lib/Target/X86/X86JITInfo.cpp > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From bob.wilson at apple.com Tue Nov 17 21:34:27 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 18 Nov 2009 03:34:27 -0000 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h Message-ID: <200911180334.nAI3YRPI023957@zion.cs.uiuc.edu> Author: bwilson Date: Tue Nov 17 21:34:27 2009 New Revision: 89187 URL: http://llvm.org/viewvc/llvm-project?rev=89187&view=rev Log: Add a target hook to allow changing the tail duplication limit based on the contents of the block to be duplicated. Use this for ARM Cortex A8/9 to be more aggressive tail duplicating indirect branches, since it makes it much more likely that they will be predicted in the branch target buffer. Testcase coming soon. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/CodeGen/BranchFolding.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=89187&r1=89186&r2=89187&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Nov 17 21:34:27 2009 @@ -536,6 +536,13 @@ /// length. virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const; + + /// TailDuplicationLimit - Returns the limit on the number of instructions + /// in basic block MBB beyond which it will not be tail-duplicated. + virtual unsigned TailDuplicationLimit(const MachineBasicBlock &MBB, + unsigned DefaultLimit) const { + return DefaultLimit; + } }; /// TargetInstrInfoImpl - This is the default implementation of Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=89187&r1=89186&r2=89187&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Nov 17 21:34:27 2009 @@ -1033,12 +1033,13 @@ if (TailBB->isSuccessor(TailBB)) return false; - // Duplicate up to one less than the tail-merge threshold. When optimizing - // for size, duplicate only one, because one branch instruction can be - // eliminated to compensate for the duplication. + // Set the limit on the number of instructions to duplicate, with a default + // of one less than the tail-merge threshold. When optimizing for size, + // duplicate only one, because one branch instruction can be eliminated to + // compensate for the duplication. unsigned MaxDuplicateCount = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) ? - 1 : (TailMergeSize - 1); + 1 : TII->TailDuplicationLimit(*TailBB, TailMergeSize - 1); // Check the instructions in the block to determine whether tail-duplication // is invalid or unlikely to be profitable. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=89187&r1=89186&r2=89187&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Nov 17 21:34:27 2009 @@ -1005,6 +1005,16 @@ return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI); } +unsigned ARMBaseInstrInfo::TailDuplicationLimit(const MachineBasicBlock &MBB, + unsigned DefaultLimit) const { + // If the target processor can predict indirect branches, it is highly + // desirable to duplicate them, since it can often make them predictable. + if (!MBB.empty() && isIndirectBranchOpcode(MBB.back().getOpcode()) && + getSubtarget().hasBranchTargetBuffer()) + return DefaultLimit + 2; + return DefaultLimit; +} + /// getInstrPredicate - If instruction is predicated, returns its predicate /// condition, otherwise returns AL. It also returns the condition code /// register by reference. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=89187&r1=89186&r2=89187&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Tue Nov 17 21:34:27 2009 @@ -272,6 +272,9 @@ virtual bool isIdentical(const MachineInstr *MI, const MachineInstr *Other, const MachineRegisterInfo *MRI) const; + + virtual unsigned TailDuplicationLimit(const MachineBasicBlock &MBB, + unsigned DefaultLimit) const; }; static inline Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=89187&r1=89186&r2=89187&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Tue Nov 17 21:34:27 2009 @@ -109,6 +109,8 @@ if (UseNEONFP.getPosition() == 0) UseNEONForSinglePrecisionFP = true; } + HasBranchTargetBuffer = (CPUString == "cortex-a8" || + CPUString == "cortex-a9"); } /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol. Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=89187&r1=89186&r2=89187&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Tue Nov 17 21:34:27 2009 @@ -50,6 +50,9 @@ /// determine if NEON should actually be used. bool UseNEONForSinglePrecisionFP; + /// HasBranchTargetBuffer - True if processor can predict indirect branches. + bool HasBranchTargetBuffer; + /// IsThumb - True if we are in thumb mode, false if in ARM mode. bool IsThumb; @@ -123,6 +126,8 @@ bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); } bool hasThumb2() const { return ThumbMode >= Thumb2; } + bool hasBranchTargetBuffer() const { return HasBranchTargetBuffer; } + bool isR9Reserved() const { return IsR9Reserved; } const std::string & getCPUString() const { return CPUString; } From nicholas at mxc.ca Tue Nov 17 23:43:16 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 18 Nov 2009 05:43:16 -0000 Subject: [llvm-commits] [llvm] r89198 - /llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Message-ID: <200911180543.nAI5hGwx028649@zion.cs.uiuc.edu> Author: nicholas Date: Tue Nov 17 23:43:15 2009 New Revision: 89198 URL: http://llvm.org/viewvc/llvm-project?rev=89198&view=rev Log: Fix passing of float arguments through ffi. Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp?rev=89198&r1=89197&r2=89198&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Tue Nov 17 23:43:15 2009 @@ -158,7 +158,7 @@ } case Type::FloatTyID: { float *FloatPtr = (float *) ArgDataPtr; - *FloatPtr = AV.DoubleVal; + *FloatPtr = AV.FloatVal; return ArgDataPtr; } case Type::DoubleTyID: { From jyasskin at google.com Wed Nov 18 00:07:05 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Tue, 17 Nov 2009 22:07:05 -0800 Subject: [llvm-commits] [PATCH] Move stub allocation to the JITEmitter In-Reply-To: References: <0016e6470f36c55e08047834fde7@google.com> Message-ID: On Tue, Nov 17, 2009 at 2:23 PM, Eric Christopher wrote: > > On Nov 16, 2009, at 4:07 PM, Jeffrey Yasskin wrote: > >> I've updated the patch to ToT at >> http://codereview.appspot.com/download/issue153044_2015.diff. > > Few comments: > > + ? ?struct StubLayout { > + ? ? ?size_t Size; > + ? ? ?size_t Alignment; > + ? ?}; > > > Comment above it giving whether it's in bytes, bits, etc? Done. > +TargetJITInfo::StubLayout PPCJITInfo::getStubLayout() { > + ?StubLayout Result = {10*4, 1}; > + ?return Result; > +} > > > These could also use a block comment of the stub layout. > > I hate magic numbers. Not your fault that we have so many though :) Documented. This led me to find a bug in how I'd changed emitGlobalValueIndirectSym: ARM+PIC was using that inside emitFunctionStub, which meant that it didn't work to move its stub allocation to the JITEmitter. For now, I've rolled back that part of the change. http://codereview.appspot.com/156053 will allow two "stubs" to be active at once. We may want to rename the function that allocates an indirect symbol, since it isn't a stub. > + ? ?/// for external functions. ?TODO(jyasskin): Of course, external functions > > > I think todos are for the readme file though you can reference that in your comment. Probably don't need your name though. What readme? There isn't one in the ExecutionEngine tree, and the top-level one doesn't have anything like this. I have deleted my name. I can delete the TODOs entirely if you prefer, since I should be fixing them soon. > Otherwise it looks fine, I'll run it through tests here real fast. http://codereview.appspot.com/153044 has the current patch + the multiple-stubs fix. I'll merge once I commit that one. From baldrick at free.fr Wed Nov 18 03:04:44 2009 From: baldrick at free.fr (Duncan Sands) Date: Wed, 18 Nov 2009 09:04:44 -0000 Subject: [llvm-commits] [dragonegg] r89200 - /dragonegg/trunk/llvm-convert.cpp Message-ID: <200911180904.nAI94j1i018294@zion.cs.uiuc.edu> Author: baldrick Date: Wed Nov 18 03:04:38 2009 New Revision: 89200 URL: http://llvm.org/viewvc/llvm-project?rev=89200&view=rev Log: Make DefineSSAName idempotent. This matters in the following theoretical situation: A is an SSA name for which a placeholder P is being used. The definition of SSA name B is that it is equal to A. Then the SSANames map will contain the entry B->P. Each time EmitSSA_NAME is called on the tree defining B, since we see B mapping to a placeholder (P, not created as a placeholder for B, created as a placeholder for A), we think it should not be returned, but instead the definition of B should be processed. Since B is defined to be equal to A, this results in calling DefineSSAName with the value of A, i.e. P. But the entry B->P already exists in the map. Doing a RAUW of P with P then deleting P would be very bad... Modified: dragonegg/trunk/llvm-convert.cpp Modified: dragonegg/trunk/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-convert.cpp?rev=89200&r1=89199&r2=89200&view=diff ============================================================================== --- dragonegg/trunk/llvm-convert.cpp (original) +++ dragonegg/trunk/llvm-convert.cpp Wed Nov 18 03:04:38 2009 @@ -781,11 +781,13 @@ Value *TreeToLLVM::DefineSSAName(tree_node *reg, Value *Val) { assert(TREE_CODE(reg) == SSA_NAME && "Not an SSA name!"); if (Value *ExistingValue = SSANames[reg]) { - assert(isSSAPlaceholder(ExistingValue) && "Multiply defined SSA name!"); - // Replace the placeholder with the value everywhere. This also updates the - // map entry. - ExistingValue->replaceAllUsesWith(Val); - delete ExistingValue; + if (Val != ExistingValue) { + assert(isSSAPlaceholder(ExistingValue) && "Multiply defined SSA name!"); + // Replace the placeholder with the value everywhere. This also updates + // the map entry, because it is a TrackingVH. + ExistingValue->replaceAllUsesWith(Val); + delete ExistingValue; + } return Val; } return SSANames[reg] = Val; From espindola at google.com Wed Nov 18 09:22:48 2009 From: espindola at google.com (Rafael Espindola) Date: Wed, 18 Nov 2009 10:22:48 -0500 Subject: [llvm-commits] [PATCH] LTO code generator options In-Reply-To: <6AE1604EE3EC5F4296C096518C6B77EEFD4607C4@mail.accesssoftek.com> References: <04F6B1512E264B27AEE607542FCDD113@andreic6e7fe55> <9C7CA4093A8F41D7AD156ED3CF854D17@andreic6e7fe55> <38a0d8450911101625s5e3b7cb0m31ec0ce4d4144dc@mail.gmail.com> <38a0d8450911121059n6a0d3eb0ka34711d931c7675e@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BA@mail.accesssoftek.com> <38a0d8450911141921r7deec8b3k91e06950263f0485@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BF@mail.accesssoftek.com> <38a0d8450911170809j6a32716ar840b8622cfad6f17@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607C4@mail.accesssoftek.com> Message-ID: <38a0d8450911180722j5a463fa8hec81178154deaf09@mail.gmail.com> 2009/11/17 Viktor Kutuzov : > Thanks for reviewing it, Rafael. > > Now while we are both on the same waive, let's go with the rest of the patches. Have you committed the previous one? > I have tried to combine them on the same manner as the last one. Thanks! You have + const std::string FeatureStr = + SubtargetFeatures::getDefaultSubtargetFeatures(Triple.c_str()); But getDefaultSubtargetFeatures takes a triple. You have to change the .c_str() to llvm::Triple(). I think the patch is OK with that change. Nick, can you just comment on lib/Target/SubtargetFeature.cpp being the right place to put this? I think it is, but I am not as familiar with this code. > The attached patch has similar OS and Vendor independent re-factoring for Subtarget features (attributes). > > I moved Applce-specific code from tools/lto/LTOModule.cpp to lib/Target/SubtargetFeature.cpp with related header files update. > > Cheers, > Viktor. > Cheers, -- Rafael ?vila de Esp?ndola From clattner at apple.com Wed Nov 18 10:39:26 2009 From: clattner at apple.com (Chris Lattner) Date: Wed, 18 Nov 2009 18:39:26 +0200 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: <200911180334.nAI3YRPI023957@zion.cs.uiuc.edu> References: <200911180334.nAI3YRPI023957@zion.cs.uiuc.edu> Message-ID: <43161283-1C33-4D75-BF76-FF9171C66A4F@apple.com> I understand that this is important for performance, but why isn't this a win (or at least not a loss) for all targets? Would it be reasonable to just increase the threshold (in the taildup code itself) for unconditional branches to blocks that end with an indirect jump regardless of CPU and whether the jump came from a switch or indirect goto? I guess what I'm getting at is that I'd prefer to not add yet-another target hook (particularly one where targets return an arbitrary and unitless value), and just make analyze branch smarter if needbe. If the goal is to taildup indirect branches, it would be better to look for that target independent structure rather than foist the issue onto target authors. -Chris On Nov 18, 2009, at 5:34 AM, Bob Wilson wrote: > Author: bwilson > Date: Tue Nov 17 21:34:27 2009 > New Revision: 89187 > > URL: http://llvm.org/viewvc/llvm-project?rev=89187&view=rev > Log: > Add a target hook to allow changing the tail duplication limit based > on the > contents of the block to be duplicated. Use this for ARM Cortex > A8/9 to > be more aggressive tail duplicating indirect branches, since it > makes it > much more likely that they will be predicted in the branch target > buffer. > Testcase coming soon. > > Modified: > llvm/trunk/include/llvm/Target/TargetInstrInfo.h > llvm/trunk/lib/CodeGen/BranchFolding.cpp > llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h > llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp > llvm/trunk/lib/Target/ARM/ARMSubtarget.h > > Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=89187&r1=89186&r2=89187&view=diff > > === > === > === > ===================================================================== > --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) > +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Nov 17 > 21:34:27 2009 > @@ -536,6 +536,13 @@ > /// length. > virtual unsigned getInlineAsmLength(const char *Str, > const MCAsmInfo &MAI) const; > + > + /// TailDuplicationLimit - Returns the limit on the number of > instructions > + /// in basic block MBB beyond which it will not be tail-duplicated. > + virtual unsigned TailDuplicationLimit(const MachineBasicBlock &MBB, > + unsigned DefaultLimit) > const { > + return DefaultLimit; > + } > }; > > /// TargetInstrInfoImpl - This is the default implementation of > > Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=89187&r1=89186&r2=89187&view=diff > > === > === > === > ===================================================================== > --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) > +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Nov 17 21:34:27 2009 > @@ -1033,12 +1033,13 @@ > if (TailBB->isSuccessor(TailBB)) > return false; > > - // Duplicate up to one less than the tail-merge threshold. When > optimizing > - // for size, duplicate only one, because one branch instruction > can be > - // eliminated to compensate for the duplication. > + // Set the limit on the number of instructions to duplicate, with > a default > + // of one less than the tail-merge threshold. When optimizing for > size, > + // duplicate only one, because one branch instruction can be > eliminated to > + // compensate for the duplication. > unsigned MaxDuplicateCount = > MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) ? > - 1 : (TailMergeSize - 1); > + 1 : TII->TailDuplicationLimit(*TailBB, TailMergeSize - 1); > > // Check the instructions in the block to determine whether tail- > duplication > // is invalid or unlikely to be profitable. > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=89187&r1=89186&r2=89187&view=diff > > === > === > === > ===================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Nov 17 > 21:34:27 2009 > @@ -1005,6 +1005,16 @@ > return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI); > } > > +unsigned ARMBaseInstrInfo::TailDuplicationLimit(const > MachineBasicBlock &MBB, > + unsigned > DefaultLimit) const { > + // If the target processor can predict indirect branches, it is > highly > + // desirable to duplicate them, since it can often make them > predictable. > + if (!MBB.empty() && isIndirectBranchOpcode(MBB.back().getOpcode > ()) && > + getSubtarget().hasBranchTargetBuffer()) > + return DefaultLimit + 2; > + return DefaultLimit; > +} > + > /// getInstrPredicate - If instruction is predicated, returns its > predicate > /// condition, otherwise returns AL. It also returns the condition > code > /// register by reference. > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=89187&r1=89186&r2=89187&view=diff > > === > === > === > ===================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Tue Nov 17 21:34:27 > 2009 > @@ -272,6 +272,9 @@ > > virtual bool isIdentical(const MachineInstr *MI, const > MachineInstr *Other, > const MachineRegisterInfo *MRI) const; > + > + virtual unsigned TailDuplicationLimit(const MachineBasicBlock &MBB, > + unsigned DefaultLimit) const; > }; > > static inline > > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=89187&r1=89186&r2=89187&view=diff > > === > === > === > ===================================================================== > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Tue Nov 17 21:34:27 > 2009 > @@ -109,6 +109,8 @@ > if (UseNEONFP.getPosition() == 0) > UseNEONForSinglePrecisionFP = true; > } > + HasBranchTargetBuffer = (CPUString == "cortex-a8" || > + CPUString == "cortex-a9"); > } > > /// GVIsIndirectSymbol - true if the GV will be accessed via an > indirect symbol. > > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=89187&r1=89186&r2=89187&view=diff > > === > === > === > ===================================================================== > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Tue Nov 17 21:34:27 2009 > @@ -50,6 +50,9 @@ > /// determine if NEON should actually be used. > bool UseNEONForSinglePrecisionFP; > > + /// HasBranchTargetBuffer - True if processor can predict > indirect branches. > + bool HasBranchTargetBuffer; > + > /// IsThumb - True if we are in thumb mode, false if in ARM mode. > bool IsThumb; > > @@ -123,6 +126,8 @@ > bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); } > bool hasThumb2() const { return ThumbMode >= Thumb2; } > > + bool hasBranchTargetBuffer() const { return > HasBranchTargetBuffer; } > + > bool isR9Reserved() const { return IsR9Reserved; } > > const std::string & getCPUString() const { return CPUString; } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bob.wilson at apple.com Wed Nov 18 11:29:42 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 18 Nov 2009 09:29:42 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: <43161283-1C33-4D75-BF76-FF9171C66A4F@apple.com> References: <200911180334.nAI3YRPI023957@zion.cs.uiuc.edu> <43161283-1C33-4D75-BF76-FF9171C66A4F@apple.com> Message-ID: The only disadvantage of what you suggest is code size. There is currently no limit on the number of predecessors where a block may be duplicated, so the effect of duplicating a small block can be magnified in the overall code size. (And, at least for duplicating indirect branches on ARM Cortex processors, we don't want to limit that.) On a small low-power device without sophisticated branch prediction, where code size typically matters more than usual, we'll be doing the wrong thing. But, indirect branches are not very common, so it probably doesn't really matter so much. Most modern high-performance processors will benefit from tail duplicating indirect branches, so that would be another reason to avoid the target hook. Unless someone else has another idea, I'll get rid of the tail duplication target hook. As you mention, we'll need a way to identify indirect branches. I'd prefer to add a new IsIndirectBranch target hook. This goes against your desire to avoid new target hooks, but it's nice and simple. Alternatively, we could add another bool reference argument to AnalyzeBranch. When AnalyzeBranch returns true, which currently means that it cannot understand the branch, it would set the new argument to indicate whether it is an indirect branch. That doesn't seem to fit very well with the AnalyzeBranch interface, which is already pretty complicated, so I don't like that so much. On Nov 18, 2009, at 8:39 AM, Chris Lattner wrote: > I understand that this is important for performance, but why isn't > this a win (or at least not a loss) for all targets? Would it be > reasonable to just increase the threshold (in the taildup code > itself) for unconditional branches to blocks that end with an > indirect jump regardless of CPU and whether the jump came from a > switch or indirect goto? > > I guess what I'm getting at is that I'd prefer to not add yet- > another target hook (particularly one where targets return an > arbitrary and unitless value), and just make analyze branch smarter > if needbe. If the goal is to taildup indirect branches, it would be > better to look for that target independent structure rather than > foist the issue onto target authors. > > -Chris > > On Nov 18, 2009, at 5:34 AM, Bob Wilson wrote: > >> Author: bwilson >> Date: Tue Nov 17 21:34:27 2009 >> New Revision: 89187 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=89187&view=rev >> Log: >> Add a target hook to allow changing the tail duplication limit >> based on the >> contents of the block to be duplicated. Use this for ARM Cortex >> A8/9 to >> be more aggressive tail duplicating indirect branches, since it >> makes it >> much more likely that they will be predicted in the branch target >> buffer. >> Testcase coming soon. >> >> Modified: >> llvm/trunk/include/llvm/Target/TargetInstrInfo.h >> llvm/trunk/lib/CodeGen/BranchFolding.cpp >> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp >> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h >> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp >> llvm/trunk/lib/Target/ARM/ARMSubtarget.h >> >> Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=89187&r1=89186&r2=89187&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) >> +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Nov 17 >> 21:34:27 2009 >> @@ -536,6 +536,13 @@ >> /// length. >> virtual unsigned getInlineAsmLength(const char *Str, >> const MCAsmInfo &MAI) const; >> + >> + /// TailDuplicationLimit - Returns the limit on the number of >> instructions >> + /// in basic block MBB beyond which it will not be tail- >> duplicated. >> + virtual unsigned TailDuplicationLimit(const MachineBasicBlock >> &MBB, >> + unsigned DefaultLimit) >> const { >> + return DefaultLimit; >> + } >> }; >> >> /// TargetInstrInfoImpl - This is the default implementation of >> >> Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=89187&r1=89186&r2=89187&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) >> +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Nov 17 21:34:27 2009 >> @@ -1033,12 +1033,13 @@ >> if (TailBB->isSuccessor(TailBB)) >> return false; >> >> - // Duplicate up to one less than the tail-merge threshold. When >> optimizing >> - // for size, duplicate only one, because one branch instruction >> can be >> - // eliminated to compensate for the duplication. >> + // Set the limit on the number of instructions to duplicate, >> with a default >> + // of one less than the tail-merge threshold. When optimizing >> for size, >> + // duplicate only one, because one branch instruction can be >> eliminated to >> + // compensate for the duplication. >> unsigned MaxDuplicateCount = >> MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) ? >> - 1 : (TailMergeSize - 1); >> + 1 : TII->TailDuplicationLimit(*TailBB, TailMergeSize - 1); >> >> // Check the instructions in the block to determine whether tail- >> duplication >> // is invalid or unlikely to be profitable. >> >> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=89187&r1=89186&r2=89187&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Nov 17 >> 21:34:27 2009 >> @@ -1005,6 +1005,16 @@ >> return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI); >> } >> >> +unsigned ARMBaseInstrInfo::TailDuplicationLimit(const >> MachineBasicBlock &MBB, >> + unsigned >> DefaultLimit) const { >> + // If the target processor can predict indirect branches, it is >> highly >> + // desirable to duplicate them, since it can often make them >> predictable. >> + if (!MBB.empty() && isIndirectBranchOpcode(MBB.back().getOpcode >> ()) && >> + getSubtarget().hasBranchTargetBuffer()) >> + return DefaultLimit + 2; >> + return DefaultLimit; >> +} >> + >> /// getInstrPredicate - If instruction is predicated, returns its >> predicate >> /// condition, otherwise returns AL. It also returns the condition >> code >> /// register by reference. >> >> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=89187&r1=89186&r2=89187&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) >> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Tue Nov 17 >> 21:34:27 2009 >> @@ -272,6 +272,9 @@ >> >> virtual bool isIdentical(const MachineInstr *MI, const >> MachineInstr *Other, >> const MachineRegisterInfo *MRI) const; >> + >> + virtual unsigned TailDuplicationLimit(const MachineBasicBlock >> &MBB, >> + unsigned DefaultLimit) >> const; >> }; >> >> static inline >> >> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=89187&r1=89186&r2=89187&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Tue Nov 17 21:34:27 >> 2009 >> @@ -109,6 +109,8 @@ >> if (UseNEONFP.getPosition() == 0) >> UseNEONForSinglePrecisionFP = true; >> } >> + HasBranchTargetBuffer = (CPUString == "cortex-a8" || >> + CPUString == "cortex-a9"); >> } >> >> /// GVIsIndirectSymbol - true if the GV will be accessed via an >> indirect symbol. >> >> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=89187&r1=89186&r2=89187&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) >> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Tue Nov 17 21:34:27 2009 >> @@ -50,6 +50,9 @@ >> /// determine if NEON should actually be used. >> bool UseNEONForSinglePrecisionFP; >> >> + /// HasBranchTargetBuffer - True if processor can predict >> indirect branches. >> + bool HasBranchTargetBuffer; >> + >> /// IsThumb - True if we are in thumb mode, false if in ARM mode. >> bool IsThumb; >> >> @@ -123,6 +126,8 @@ >> bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); } >> bool hasThumb2() const { return ThumbMode >= Thumb2; } >> >> + bool hasBranchTargetBuffer() const { return >> HasBranchTargetBuffer; } >> + >> bool isR9Reserved() const { return IsR9Reserved; } >> >> const std::string & getCPUString() const { return CPUString; } >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From daniel at zuster.org Wed Nov 18 11:42:17 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 18 Nov 2009 17:42:17 -0000 Subject: [llvm-commits] [llvm] r89210 - /llvm/trunk/utils/lit/TestFormats.py Message-ID: <200911181742.nAIHgHaq005160@zion.cs.uiuc.edu> Author: ddunbar Date: Wed Nov 18 11:42:17 2009 New Revision: 89210 URL: http://llvm.org/viewvc/llvm-project?rev=89210&view=rev Log: lit: Fix exclude dirs functionality. Modified: llvm/trunk/utils/lit/TestFormats.py Modified: llvm/trunk/utils/lit/TestFormats.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/TestFormats.py?rev=89210&r1=89209&r2=89210&view=diff ============================================================================== --- llvm/trunk/utils/lit/TestFormats.py (original) +++ llvm/trunk/utils/lit/TestFormats.py Wed Nov 18 11:42:17 2009 @@ -119,8 +119,9 @@ if not self.recursive: subdirs[:] = [] - if dirname == '.svn' or dirname in localConfig.excludes: - continue + subdirs[:] = [d for d in subdirs + if (d != '.svn' and + d not in localConfig.excludes)] for filename in filenames: if (not self.pattern.match(filename) or From daniel at zuster.org Wed Nov 18 11:42:22 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 18 Nov 2009 17:42:22 -0000 Subject: [llvm-commits] [llvm] r89211 - /llvm/trunk/CMakeLists.txt Message-ID: <200911181742.nAIHgMXe005175@zion.cs.uiuc.edu> Author: ddunbar Date: Wed Nov 18 11:42:22 2009 New Revision: 89211 URL: http://llvm.org/viewvc/llvm-project?rev=89211&view=rev Log: Turn LLVM_BUILD_EXAMPLES off by default in CMake builds, to match Makefiles & Clang. Modified: llvm/trunk/CMakeLists.txt Modified: llvm/trunk/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=89211&r1=89210&r2=89211&view=diff ============================================================================== --- llvm/trunk/CMakeLists.txt (original) +++ llvm/trunk/CMakeLists.txt Wed Nov 18 11:42:22 2009 @@ -323,7 +323,7 @@ add_subdirectory(tools) endif() -option(LLVM_BUILD_EXAMPLES "Build LLVM example programs." ON) +option(LLVM_BUILD_EXAMPLES "Build LLVM example programs." OFF) if(LLVM_BUILD_EXAMPLES) add_subdirectory(examples) endif () From stoklund at 2pi.dk Wed Nov 18 12:01:36 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 18 Nov 2009 18:01:36 -0000 Subject: [llvm-commits] [llvm] r89213 - in /llvm/trunk/lib/CodeGen: PHIElimination.cpp PHIElimination.h Message-ID: <200911181801.nAII1awn005877@zion.cs.uiuc.edu> Author: stoklund Date: Wed Nov 18 12:01:35 2009 New Revision: 89213 URL: http://llvm.org/viewvc/llvm-project?rev=89213&view=rev Log: Don't require LiveVariables for PHIElimination. Enable critical edge splitting when LiveVariables is available. The -split-phi-edges is now gone, and so is the hack to disable it when using the local register allocator. The PHIElimination pass no longer has LiveVariables as a prerequisite - that is what broke the local allocator. Instead we do critical edge splitting when possible - that is when LiveVariables is available. Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp llvm/trunk/lib/CodeGen/PHIElimination.h Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89213&r1=89212&r2=89213&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Wed Nov 18 12:01:35 2009 @@ -21,7 +21,6 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/Function.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/SmallPtrSet.h" @@ -37,37 +36,17 @@ STATISTIC(NumAtomic, "Number of atomic phis lowered"); STATISTIC(NumSplits, "Number of critical edges split on demand"); -static cl::opt -SplitEdges("split-phi-edges", - cl::desc("Split critical edges during phi elimination"), - cl::init(false), cl::Hidden); - char PHIElimination::ID = 0; static RegisterPass X("phi-node-elimination", "Eliminate PHI nodes for register allocation"); const PassInfo *const llvm::PHIEliminationID = &X; -namespace llvm { FunctionPass *createLocalRegisterAllocator(); } - -// Should we run edge splitting? -static bool shouldSplitEdges() { - // Edge splitting breaks the local register allocator. It cannot tolerate - // LiveVariables being run. - if (RegisterRegAlloc::getDefault() == createLocalRegisterAllocator) - return false; - return SplitEdges; -} - void llvm::PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved(); AU.addPreserved(); - if (shouldSplitEdges()) { - AU.addRequired(); - } else { - AU.setPreservesCFG(); - AU.addPreservedID(MachineLoopInfoID); - } + // rdar://7401784 This would be nice: + // AU.addPreservedID(MachineLoopInfoID); MachineFunctionPass::getAnalysisUsage(AU); } @@ -79,9 +58,9 @@ bool Changed = false; // Split critical edges to help the coalescer - if (shouldSplitEdges()) + if (LiveVariables *LV = getAnalysisIfAvailable()) for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) - Changed |= SplitPHIEdges(Fn, *I); + Changed |= SplitPHIEdges(Fn, *I, *LV); // Populate VRegPHIUseCount analyzePHINodes(Fn); @@ -361,10 +340,11 @@ } bool llvm::PHIElimination::SplitPHIEdges(MachineFunction &MF, - MachineBasicBlock &MBB) { + MachineBasicBlock &MBB, + LiveVariables &LV) { if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI) return false; // Quick exit for basic blocks without PHIs. - LiveVariables &LV = getAnalysis(); + for (MachineBasicBlock::const_iterator BBI = MBB.begin(), BBE = MBB.end(); BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) { for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { Modified: llvm/trunk/lib/CodeGen/PHIElimination.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.h?rev=89213&r1=89212&r2=89213&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.h (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.h Wed Nov 18 12:01:35 2009 @@ -90,7 +90,8 @@ void analyzePHINodes(const MachineFunction& Fn); /// Split critical edges where necessary for good coalescer performance. - bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB); + bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB, + LiveVariables &LV); /// isLiveOut - Determine if Reg is live out from MBB, when not /// considering PHI nodes. This means that Reg is either killed by From bob.wilson at apple.com Wed Nov 18 12:10:35 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 18 Nov 2009 18:10:35 -0000 Subject: [llvm-commits] [llvm] r89214 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <200911181810.nAIIAZoN006168@zion.cs.uiuc.edu> Author: bwilson Date: Wed Nov 18 12:10:35 2009 New Revision: 89214 URL: http://llvm.org/viewvc/llvm-project?rev=89214&view=rev Log: Fix a few places that were missed when we converted to unified syntax. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=89214&r1=89213&r2=89214&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 18 12:10:35 2009 @@ -608,11 +608,11 @@ [(store GPR:$src, addrmodepc:$addr)]>; def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), - Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}h\t$src, $addr", + Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrh${p}\t$src, $addr", [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), - Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}b\t$src, $addr", + Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrb${p}\t$src, $addr", [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; } } // isNotDuplicable = 1 From evan.cheng at apple.com Wed Nov 18 12:21:16 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 18 Nov 2009 10:21:16 -0800 Subject: [llvm-commits] [llvm] r89213 - in /llvm/trunk/lib/CodeGen: PHIElimination.cpp PHIElimination.h In-Reply-To: <200911181801.nAII1awn005877@zion.cs.uiuc.edu> References: <200911181801.nAII1awn005877@zion.cs.uiuc.edu> Message-ID: <72DBFF5E-6E05-455A-905A-9F75220684A1@apple.com> Thanks. Evan On Nov 18, 2009, at 10:01 AM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Wed Nov 18 12:01:35 2009 > New Revision: 89213 > > URL: http://llvm.org/viewvc/llvm-project?rev=89213&view=rev > Log: > Don't require LiveVariables for PHIElimination. Enable critical edge splitting > when LiveVariables is available. > > The -split-phi-edges is now gone, and so is the hack to disable it when using > the local register allocator. The PHIElimination pass no longer has > LiveVariables as a prerequisite - that is what broke the local allocator. > Instead we do critical edge splitting when possible - that is when > LiveVariables is available. > > Modified: > llvm/trunk/lib/CodeGen/PHIElimination.cpp > llvm/trunk/lib/CodeGen/PHIElimination.h > > Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89213&r1=89212&r2=89213&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) > +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Wed Nov 18 12:01:35 2009 > @@ -21,7 +21,6 @@ > #include "llvm/CodeGen/MachineInstr.h" > #include "llvm/CodeGen/MachineInstrBuilder.h" > #include "llvm/CodeGen/MachineRegisterInfo.h" > -#include "llvm/CodeGen/RegAllocRegistry.h" > #include "llvm/Function.h" > #include "llvm/Target/TargetMachine.h" > #include "llvm/ADT/SmallPtrSet.h" > @@ -37,37 +36,17 @@ > STATISTIC(NumAtomic, "Number of atomic phis lowered"); > STATISTIC(NumSplits, "Number of critical edges split on demand"); > > -static cl::opt > -SplitEdges("split-phi-edges", > - cl::desc("Split critical edges during phi elimination"), > - cl::init(false), cl::Hidden); > - > char PHIElimination::ID = 0; > static RegisterPass > X("phi-node-elimination", "Eliminate PHI nodes for register allocation"); > > const PassInfo *const llvm::PHIEliminationID = &X; > > -namespace llvm { FunctionPass *createLocalRegisterAllocator(); } > - > -// Should we run edge splitting? > -static bool shouldSplitEdges() { > - // Edge splitting breaks the local register allocator. It cannot tolerate > - // LiveVariables being run. > - if (RegisterRegAlloc::getDefault() == createLocalRegisterAllocator) > - return false; > - return SplitEdges; > -} > - > void llvm::PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const { > AU.addPreserved(); > AU.addPreserved(); > - if (shouldSplitEdges()) { > - AU.addRequired(); > - } else { > - AU.setPreservesCFG(); > - AU.addPreservedID(MachineLoopInfoID); > - } > + // rdar://7401784 This would be nice: > + // AU.addPreservedID(MachineLoopInfoID); > MachineFunctionPass::getAnalysisUsage(AU); > } > > @@ -79,9 +58,9 @@ > bool Changed = false; > > // Split critical edges to help the coalescer > - if (shouldSplitEdges()) > + if (LiveVariables *LV = getAnalysisIfAvailable()) > for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) > - Changed |= SplitPHIEdges(Fn, *I); > + Changed |= SplitPHIEdges(Fn, *I, *LV); > > // Populate VRegPHIUseCount > analyzePHINodes(Fn); > @@ -361,10 +340,11 @@ > } > > bool llvm::PHIElimination::SplitPHIEdges(MachineFunction &MF, > - MachineBasicBlock &MBB) { > + MachineBasicBlock &MBB, > + LiveVariables &LV) { > if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI) > return false; // Quick exit for basic blocks without PHIs. > - LiveVariables &LV = getAnalysis(); > + > for (MachineBasicBlock::const_iterator BBI = MBB.begin(), BBE = MBB.end(); > BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) { > for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { > > Modified: llvm/trunk/lib/CodeGen/PHIElimination.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.h?rev=89213&r1=89212&r2=89213&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/PHIElimination.h (original) > +++ llvm/trunk/lib/CodeGen/PHIElimination.h Wed Nov 18 12:01:35 2009 > @@ -90,7 +90,8 @@ > void analyzePHINodes(const MachineFunction& Fn); > > /// Split critical edges where necessary for good coalescer performance. > - bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB); > + bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB, > + LiveVariables &LV); > > /// isLiveOut - Determine if Reg is live out from MBB, when not > /// considering PHI nodes. This means that Reg is either killed by > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From nlewycky at google.com Wed Nov 18 12:34:33 2009 From: nlewycky at google.com (Nick Lewycky) Date: Wed, 18 Nov 2009 10:34:33 -0800 Subject: [llvm-commits] [PATCH] LTO code generator options In-Reply-To: <38a0d8450911180722j5a463fa8hec81178154deaf09@mail.gmail.com> References: <04F6B1512E264B27AEE607542FCDD113@andreic6e7fe55> <38a0d8450911101625s5e3b7cb0m31ec0ce4d4144dc@mail.gmail.com> <38a0d8450911121059n6a0d3eb0ka34711d931c7675e@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BA@mail.accesssoftek.com> <38a0d8450911141921r7deec8b3k91e06950263f0485@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BF@mail.accesssoftek.com> <38a0d8450911170809j6a32716ar840b8622cfad6f17@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607C4@mail.accesssoftek.com> <38a0d8450911180722j5a463fa8hec81178154deaf09@mail.gmail.com> Message-ID: + /// Retrieve a formated string of the default features for + /// the specified target triple. + static std::string getDefaultSubtargetFeatures(const Triple &Triple); Two t's in formatted. 2009/11/18 Rafael Espindola > 2009/11/17 Viktor Kutuzov : > > Thanks for reviewing it, Rafael. > > > > Now while we are both on the same waive, let's go with the rest of the > patches. > > Have you committed the previous one? > > > I have tried to combine them on the same manner as the last one. > > Thanks! > > You have > > + const std::string FeatureStr = > + > SubtargetFeatures::getDefaultSubtargetFeatures(Triple.c_str()); > > But getDefaultSubtargetFeatures takes a triple. You have to change the > .c_str() to llvm::Triple(). > > I think the patch is OK with that change. Nick, can you just comment > on lib/Target/SubtargetFeature.cpp being the right place to put this? > I think it is, but I am not as familiar with this code. > I'm not familiar with most of lib/Target or lib/CodeGen either, but after reading through SubtargetFeature.{cpp,h} it looks like the right place to me. Nick > > > The attached patch has similar OS and Vendor independent re-factoring for > Subtarget features (attributes). > > > > I moved Applce-specific code from tools/lto/LTOModule.cpp to > lib/Target/SubtargetFeature.cpp with related header files update. > > > > Cheers, > > Viktor. > > > > Cheers, > > -- > Rafael ?vila de Esp?ndola > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091118/380225d4/attachment.html From david_goodwin at apple.com Wed Nov 18 12:39:57 2009 From: david_goodwin at apple.com (David Goodwin) Date: Wed, 18 Nov 2009 18:39:57 -0000 Subject: [llvm-commits] [llvm] r89218 - in /llvm/trunk/lib/Target/ARM: ARM.td ARMScheduleV6.td ARMScheduleV7.td Message-ID: <200911181839.nAIIdvfv007660@zion.cs.uiuc.edu> Author: david_goodwin Date: Wed Nov 18 12:39:57 2009 New Revision: 89218 URL: http://llvm.org/viewvc/llvm-project?rev=89218&view=rev Log: Add ARMv6 itineraries. Modified: llvm/trunk/lib/Target/ARM/ARM.td llvm/trunk/lib/Target/ARM/ARMScheduleV6.td llvm/trunk/lib/Target/ARM/ARMScheduleV7.td Modified: llvm/trunk/lib/Target/ARM/ARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=89218&r1=89217&r2=89218&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td (original) +++ llvm/trunk/lib/Target/ARM/ARM.td Wed Nov 18 12:39:57 2009 @@ -89,16 +89,18 @@ def : ProcNoItin<"iwmmxt", [ArchV5TE]>; // V6 Processors. -def : ProcNoItin<"arm1136j-s", [ArchV6]>; -def : ProcNoItin<"arm1136jf-s", [ArchV6, FeatureVFP2]>; -def : ProcNoItin<"arm1176jz-s", [ArchV6]>; -def : ProcNoItin<"arm1176jzf-s", [ArchV6, FeatureVFP2]>; -def : ProcNoItin<"mpcorenovfp", [ArchV6]>; -def : ProcNoItin<"mpcore", [ArchV6, FeatureVFP2]>; +def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>; +def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2]>; +def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>; +def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2]>; +def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>; +def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2]>; // V6T2 Processors. -def : ProcNoItin<"arm1156t2-s", [ArchV6T2, FeatureThumb2]>; -def : ProcNoItin<"arm1156t2f-s", [ArchV6T2, FeatureThumb2, FeatureVFP2]>; +def : Processor<"arm1156t2-s", ARMV6Itineraries, + [ArchV6T2, FeatureThumb2]>; +def : Processor<"arm1156t2f-s", ARMV6Itineraries, + [ArchV6T2, FeatureThumb2, FeatureVFP2]>; // V7 Processors. def : Processor<"cortex-a8", CortexA8Itineraries, Modified: llvm/trunk/lib/Target/ARM/ARMScheduleV6.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleV6.td?rev=89218&r1=89217&r2=89218&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleV6.td (original) +++ llvm/trunk/lib/Target/ARM/ARMScheduleV6.td Wed Nov 18 12:39:57 2009 @@ -11,4 +11,190 @@ // //===----------------------------------------------------------------------===// -// TODO: Add model for an ARM11 +// Model based on ARM1176 +// +// Scheduling information derived from "ARM1176JZF-S Technical Reference Manual". +// +def ARMV6Itineraries : ProcessorItineraries<[ + // + // No operand cycles + InstrItinData]>, + // + // Binary Instructions that produce a result + InstrItinData], [2, 2]>, + InstrItinData], [2, 2, 2]>, + InstrItinData], [2, 2, 1]>, + InstrItinData], [3, 3, 2, 1]>, + // + // Unary Instructions that produce a result + InstrItinData], [2, 2]>, + InstrItinData], [2, 1]>, + InstrItinData], [3, 2, 1]>, + // + // Compare instructions + InstrItinData], [2]>, + InstrItinData], [2, 2]>, + InstrItinData], [2, 1]>, + InstrItinData], [3, 2, 1]>, + // + // Move instructions, unconditional + InstrItinData], [2]>, + InstrItinData], [2, 2]>, + InstrItinData], [2, 1]>, + InstrItinData], [3, 2, 1]>, + // + // Move instructions, conditional + InstrItinData], [3]>, + InstrItinData], [3, 2]>, + InstrItinData], [3, 1]>, + InstrItinData], [4, 2, 1]>, + + // Integer multiply pipeline + // + InstrItinData], [4, 1, 1]>, + InstrItinData], [4, 1, 1, 2]>, + InstrItinData], [5, 1, 1]>, + InstrItinData], [5, 1, 1, 2]>, + InstrItinData], [6, 1, 1]>, + InstrItinData], [6, 1, 1, 2]>, + + // Integer load pipeline + // + // Immediate offset + InstrItinData], [4, 1]>, + // + // Register offset + InstrItinData], [4, 1, 1]>, + // + // Scaled register offset, issues over 2 cycles + InstrItinData], [5, 2, 1]>, + // + // Immediate offset with update + InstrItinData], [4, 2, 1]>, + // + // Register offset with update + InstrItinData], [4, 2, 1, 1]>, + // + // Scaled register offset with update, issues over 2 cycles + InstrItinData], [5, 2, 2, 1]>, + + // + // Load multiple + InstrItinData]>, + + // Integer store pipeline + // + // Immediate offset + InstrItinData], [2, 1]>, + // + // Register offset + InstrItinData], [2, 1, 1]>, + + // + // Scaled register offset, issues over 2 cycles + InstrItinData], [2, 2, 1]>, + // + // Immediate offset with update + InstrItinData], [2, 2, 1]>, + // + // Register offset with update + InstrItinData], [2, 2, 1, 1]>, + // + // Scaled register offset with update, issues over 2 cycles + InstrItinData], [2, 2, 2, 1]>, + // + // Store multiple + InstrItinData]>, + + // Branch + // + // no delay slots, so the latency of a branch is unimportant + InstrItinData]>, + + // VFP + // Issue through integer pipeline, and execute in NEON unit. We assume + // RunFast mode so that NFP pipeline is used for single-precision when + // possible. + // + // FP Special Register to Integer Register File Move + InstrItinData], [3]>, + // + // Single-precision FP Unary + InstrItinData], [5, 2]>, + // + // Double-precision FP Unary + InstrItinData], [5, 2]>, + // + // Single-precision FP Compare + InstrItinData], [2, 2]>, + // + // Double-precision FP Compare + InstrItinData], [2, 2]>, + // + // Single to Double FP Convert + InstrItinData], [5, 2]>, + // + // Double to Single FP Convert + InstrItinData], [5, 2]>, + // + // Single-Precision FP to Integer Convert + InstrItinData], [9, 2]>, + // + // Double-Precision FP to Integer Convert + InstrItinData], [9, 2]>, + // + // Integer to Single-Precision FP Convert + InstrItinData], [9, 2]>, + // + // Integer to Double-Precision FP Convert + InstrItinData], [9, 2]>, + // + // Single-precision FP ALU + InstrItinData], [9, 2, 2]>, + // + // Double-precision FP ALU + InstrItinData], [9, 2, 2]>, + // + // Single-precision FP Multiply + InstrItinData], [9, 2, 2]>, + // + // Double-precision FP Multiply + InstrItinData], [9, 2, 2]>, + // + // Single-precision FP MAC + InstrItinData], [9, 2, 2, 2]>, + // + // Double-precision FP MAC + InstrItinData], [9, 2, 2, 2]>, + // + // Single-precision FP DIV + InstrItinData], [20, 2, 2]>, + // + // Double-precision FP DIV + InstrItinData], [34, 2, 2]>, + // + // Single-precision FP SQRT + InstrItinData], [20, 2, 2]>, + // + // Double-precision FP SQRT + InstrItinData], [34, 2, 2]>, + // + // Single-precision FP Load + InstrItinData], [5, 2, 2]>, + // + // Double-precision FP Load + InstrItinData], [5, 2, 2]>, + // + // FP Load Multiple + InstrItinData]>, + // + // Single-precision FP Store + InstrItinData], [2, 2, 2]>, + // + // Double-precision FP Store + // use FU_Issue to enforce the 1 load/store per cycle limit + InstrItinData], [2, 2, 2]>, + // + // FP Store Multiple + InstrItinData]> +]>; Modified: llvm/trunk/lib/Target/ARM/ARMScheduleV7.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleV7.td?rev=89218&r1=89217&r2=89218&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleV7.td (original) +++ llvm/trunk/lib/Target/ARM/ARMScheduleV7.td Wed Nov 18 12:39:57 2009 @@ -184,7 +184,7 @@ // // Single-precision FP Compare InstrItinData, - InstrStage<1, [FU_NPipe]>], [7, 1]>, + InstrStage<1, [FU_NPipe]>], [1, 1]>, // // Double-precision FP Compare InstrItinData, @@ -221,7 +221,7 @@ // // Single-precision FP ALU InstrItinData, - InstrStage<1, [FU_NPipe]>], [7, 1]>, + InstrStage<1, [FU_NPipe]>], [7, 1, 1]>, // // Double-precision FP ALU InstrItinData, @@ -230,7 +230,7 @@ // // Single-precision FP Multiply InstrItinData, - InstrStage<1, [FU_NPipe]>], [7, 1]>, + InstrStage<1, [FU_NPipe]>], [7, 1, 1]>, // // Double-precision FP Multiply InstrItinData, @@ -239,7 +239,7 @@ // // Single-precision FP MAC InstrItinData, - InstrStage<1, [FU_NPipe]>], [7, 1]>, + InstrStage<1, [FU_NPipe]>], [7, 2, 1, 1]>, // // Double-precision FP MAC InstrItinData, From gohman at apple.com Wed Nov 18 12:52:24 2009 From: gohman at apple.com (Dan Gohman) Date: Wed, 18 Nov 2009 10:52:24 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: References: <200911180334.nAI3YRPI023957@zion.cs.uiuc.edu> <43161283-1C33-4D75-BF76-FF9171C66A4F@apple.com> Message-ID: <701493E3-E27B-4EAB-9666-99B2F6EA01BC@apple.com> On Nov 18, 2009, at 9:29 AM, Bob Wilson wrote: > The only disadvantage of what you suggest is code size. There is > currently no limit on the number of predecessors where a block may be > duplicated, so the effect of duplicating a small block can be > magnified in the overall code size. (And, at least for duplicating > indirect branches on ARM Cortex processors, we don't want to limit > that.) On a small low-power device without sophisticated branch > prediction, where code size typically matters more than usual, we'll > be doing the wrong thing. But, indirect branches are not very common, > so it probably doesn't really matter so much. > > Most modern high-performance processors will benefit from tail > duplicating indirect branches, so that would be another reason to > avoid the target hook. > > Unless someone else has another idea, I'll get rid of the tail > duplication target hook. As you mention, we'll need a way to identify > indirect branches. I'd prefer to add a new IsIndirectBranch target > hook. This goes against your desire to avoid new target hooks, but > it's nice and simple. Alternatively, we could add another bool > reference argument to AnalyzeBranch. When AnalyzeBranch returns true, > which currently means that it cannot understand the branch, it would > set the new argument to indicate whether it is an indirect branch. > That doesn't seem to fit very well with the AnalyzeBranch interface, > which is already pretty complicated, so I don't like that so much. TargetInstrDesc has an isIndirectBranch flag, so you could use that if you want. However I don't know what the big problem is with the target hook; it's neither arbitrary nor unitless. Perhaps what he really meant is that the present use for the hook is too obscure to justify having the clutter of the hook in TargetInstrInfo, but I'm just guessing here. Dan > > On Nov 18, 2009, at 8:39 AM, Chris Lattner wrote: > >> I understand that this is important for performance, but why isn't >> this a win (or at least not a loss) for all targets? Would it be >> reasonable to just increase the threshold (in the taildup code >> itself) for unconditional branches to blocks that end with an >> indirect jump regardless of CPU and whether the jump came from a >> switch or indirect goto? >> >> I guess what I'm getting at is that I'd prefer to not add yet- >> another target hook (particularly one where targets return an >> arbitrary and unitless value), and just make analyze branch smarter >> if needbe. If the goal is to taildup indirect branches, it would be >> better to look for that target independent structure rather than >> foist the issue onto target authors. >> >> -Chris From evan.cheng at apple.com Wed Nov 18 13:01:10 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 18 Nov 2009 11:01:10 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: References: <200911180334.nAI3YRPI023957@zion.cs.uiuc.edu> <43161283-1C33-4D75-BF76-FF9171C66A4F@apple.com> Message-ID: On Nov 18, 2009, at 9:29 AM, Bob Wilson wrote: > The only disadvantage of what you suggest is code size. There is > currently no limit on the number of predecessors where a block may be > duplicated, so the effect of duplicating a small block can be > magnified in the overall code size. (And, at least for duplicating > indirect branches on ARM Cortex processors, we don't want to limit > that.) On a small low-power device without sophisticated branch > prediction, where code size typically matters more than usual, we'll > be doing the wrong thing. But, indirect branches are not very common, > so it probably doesn't really matter so much. > > Most modern high-performance processors will benefit from tail > duplicating indirect branches, so that would be another reason to > avoid the target hook. The "cost" of branches vary on different targets though. We really need to be sure before we eliminate the target hooks. Evan > > Unless someone else has another idea, I'll get rid of the tail > duplication target hook. As you mention, we'll need a way to identify > indirect branches. I'd prefer to add a new IsIndirectBranch target > hook. This goes against your desire to avoid new target hooks, but > it's nice and simple. Alternatively, we could add another bool > reference argument to AnalyzeBranch. When AnalyzeBranch returns true, > which currently means that it cannot understand the branch, it would > set the new argument to indicate whether it is an indirect branch. > That doesn't seem to fit very well with the AnalyzeBranch interface, > which is already pretty complicated, so I don't like that so much. > > On Nov 18, 2009, at 8:39 AM, Chris Lattner wrote: > >> I understand that this is important for performance, but why isn't >> this a win (or at least not a loss) for all targets? Would it be >> reasonable to just increase the threshold (in the taildup code >> itself) for unconditional branches to blocks that end with an >> indirect jump regardless of CPU and whether the jump came from a >> switch or indirect goto? >> >> I guess what I'm getting at is that I'd prefer to not add yet- >> another target hook (particularly one where targets return an >> arbitrary and unitless value), and just make analyze branch smarter >> if needbe. If the goal is to taildup indirect branches, it would be >> better to look for that target independent structure rather than >> foist the issue onto target authors. >> >> -Chris >> >> On Nov 18, 2009, at 5:34 AM, Bob Wilson wrote: >> >>> Author: bwilson >>> Date: Tue Nov 17 21:34:27 2009 >>> New Revision: 89187 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=89187&view=rev >>> Log: >>> Add a target hook to allow changing the tail duplication limit >>> based on the >>> contents of the block to be duplicated. Use this for ARM Cortex >>> A8/9 to >>> be more aggressive tail duplicating indirect branches, since it >>> makes it >>> much more likely that they will be predicted in the branch target >>> buffer. >>> Testcase coming soon. >>> >>> Modified: >>> llvm/trunk/include/llvm/Target/TargetInstrInfo.h >>> llvm/trunk/lib/CodeGen/BranchFolding.cpp >>> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp >>> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h >>> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp >>> llvm/trunk/lib/Target/ARM/ARMSubtarget.h >>> >>> Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=89187&r1=89186&r2=89187&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ===================================================================== >>> --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) >>> +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Nov 17 >>> 21:34:27 2009 >>> @@ -536,6 +536,13 @@ >>> /// length. >>> virtual unsigned getInlineAsmLength(const char *Str, >>> const MCAsmInfo &MAI) const; >>> + >>> + /// TailDuplicationLimit - Returns the limit on the number of >>> instructions >>> + /// in basic block MBB beyond which it will not be tail- >>> duplicated. >>> + virtual unsigned TailDuplicationLimit(const MachineBasicBlock >>> &MBB, >>> + unsigned DefaultLimit) >>> const { >>> + return DefaultLimit; >>> + } >>> }; >>> >>> /// TargetInstrInfoImpl - This is the default implementation of >>> >>> Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=89187&r1=89186&r2=89187&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ===================================================================== >>> --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) >>> +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Nov 17 21:34:27 2009 >>> @@ -1033,12 +1033,13 @@ >>> if (TailBB->isSuccessor(TailBB)) >>> return false; >>> >>> - // Duplicate up to one less than the tail-merge threshold. When >>> optimizing >>> - // for size, duplicate only one, because one branch instruction >>> can be >>> - // eliminated to compensate for the duplication. >>> + // Set the limit on the number of instructions to duplicate, >>> with a default >>> + // of one less than the tail-merge threshold. When optimizing >>> for size, >>> + // duplicate only one, because one branch instruction can be >>> eliminated to >>> + // compensate for the duplication. >>> unsigned MaxDuplicateCount = >>> MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) ? >>> - 1 : (TailMergeSize - 1); >>> + 1 : TII->TailDuplicationLimit(*TailBB, TailMergeSize - 1); >>> >>> // Check the instructions in the block to determine whether tail- >>> duplication >>> // is invalid or unlikely to be profitable. >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=89187&r1=89186&r2=89187&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ===================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Nov 17 >>> 21:34:27 2009 >>> @@ -1005,6 +1005,16 @@ >>> return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI); >>> } >>> >>> +unsigned ARMBaseInstrInfo::TailDuplicationLimit(const >>> MachineBasicBlock &MBB, >>> + unsigned >>> DefaultLimit) const { >>> + // If the target processor can predict indirect branches, it is >>> highly >>> + // desirable to duplicate them, since it can often make them >>> predictable. >>> + if (!MBB.empty() && isIndirectBranchOpcode(MBB.back().getOpcode >>> ()) && >>> + getSubtarget().hasBranchTargetBuffer()) >>> + return DefaultLimit + 2; >>> + return DefaultLimit; >>> +} >>> + >>> /// getInstrPredicate - If instruction is predicated, returns its >>> predicate >>> /// condition, otherwise returns AL. It also returns the condition >>> code >>> /// register by reference. >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=89187&r1=89186&r2=89187&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ===================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Tue Nov 17 >>> 21:34:27 2009 >>> @@ -272,6 +272,9 @@ >>> >>> virtual bool isIdentical(const MachineInstr *MI, const >>> MachineInstr *Other, >>> const MachineRegisterInfo *MRI) const; >>> + >>> + virtual unsigned TailDuplicationLimit(const MachineBasicBlock >>> &MBB, >>> + unsigned DefaultLimit) >>> const; >>> }; >>> >>> static inline >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=89187&r1=89186&r2=89187&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ===================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Tue Nov 17 21:34:27 >>> 2009 >>> @@ -109,6 +109,8 @@ >>> if (UseNEONFP.getPosition() == 0) >>> UseNEONForSinglePrecisionFP = true; >>> } >>> + HasBranchTargetBuffer = (CPUString == "cortex-a8" || >>> + CPUString == "cortex-a9"); >>> } >>> >>> /// GVIsIndirectSymbol - true if the GV will be accessed via an >>> indirect symbol. >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=89187&r1=89186&r2=89187&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ===================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Tue Nov 17 21:34:27 2009 >>> @@ -50,6 +50,9 @@ >>> /// determine if NEON should actually be used. >>> bool UseNEONForSinglePrecisionFP; >>> >>> + /// HasBranchTargetBuffer - True if processor can predict >>> indirect branches. >>> + bool HasBranchTargetBuffer; >>> + >>> /// IsThumb - True if we are in thumb mode, false if in ARM mode. >>> bool IsThumb; >>> >>> @@ -123,6 +126,8 @@ >>> bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); } >>> bool hasThumb2() const { return ThumbMode >= Thumb2; } >>> >>> + bool hasBranchTargetBuffer() const { return >>> HasBranchTargetBuffer; } >>> + >>> bool isR9Reserved() const { return IsR9Reserved; } >>> >>> const std::string & getCPUString() const { return CPUString; } >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From vkutuzov at accesssoftek.com Wed Nov 18 13:01:47 2009 From: vkutuzov at accesssoftek.com (Viktor Kutuzov) Date: Wed, 18 Nov 2009 11:01:47 -0800 Subject: [llvm-commits] [PATCH] LTO code generator options References: <04F6B1512E264B27AEE607542FCDD113@andreic6e7fe55> <9C7CA4093A8F41D7AD156ED3CF854D17@andreic6e7fe55> <38a0d8450911101625s5e3b7cb0m31ec0ce4d4144dc@mail.gmail.com> <38a0d8450911121059n6a0d3eb0ka34711d931c7675e@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BA@mail.accesssoftek.com> <38a0d8450911141921r7deec8b3k91e06950263f0485@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BF@mail.accesssoftek.com> <38a0d8450911170809j6a32716ar840b8622cfad6f17@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607C4@mail.accesssoftek.com> <38a0d8450911180722j5a463fa8hec81178154deaf09@mail.gmail.com> Message-ID: <52F1278A78004EAABFFF53449E9B4970@andreic6e7fe55> Thanks, Rafael. > Have you committed the previous one? Yes, I have. http://llvm.org/viewvc/llvm-project?view=rev&revision=89122 Best regards, Viktor ----- Original Message ----- From: "Rafael Espindola" To: "Viktor Kutuzov" Cc: "Commit Messages and Patches for LLVM" ; Sent: Wednesday, November 18, 2009 7:22 AM Subject: Re: [llvm-commits] [PATCH] LTO code generator options > 2009/11/17 Viktor Kutuzov : >> Thanks for reviewing it, Rafael. >> >> Now while we are both on the same waive, let's go with the rest of the patches. > > Have you committed the previous one? > >> I have tried to combine them on the same manner as the last one. > > Thanks! > > You have > > + const std::string FeatureStr = > + SubtargetFeatures::getDefaultSubtargetFeatures(Triple.c_str()); > > But getDefaultSubtargetFeatures takes a triple. You have to change the > .c_str() to llvm::Triple(). > > I think the patch is OK with that change. Nick, can you just comment > on lib/Target/SubtargetFeature.cpp being the right place to put this? > I think it is, but I am not as familiar with this code. > >> The attached patch has similar OS and Vendor independent re-factoring for Subtarget features (attributes). >> >> I moved Applce-specific code from tools/lto/LTOModule.cpp to lib/Target/SubtargetFeature.cpp with related header files update. >> >> Cheers, >> Viktor. >> > > Cheers, > > -- > Rafael ?vila de Esp?ndola > From bob.wilson at apple.com Wed Nov 18 13:29:37 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 18 Nov 2009 19:29:37 -0000 Subject: [llvm-commits] [llvm] r89225 - /llvm/trunk/lib/CodeGen/BranchFolding.cpp Message-ID: <200911181929.nAIJTbZ0009865@zion.cs.uiuc.edu> Author: bwilson Date: Wed Nov 18 13:29:37 2009 New Revision: 89225 URL: http://llvm.org/viewvc/llvm-project?rev=89225&view=rev Log: Add statistics for tail duplication. Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=89225&r1=89224&r2=89225&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Wed Nov 18 13:29:37 2009 @@ -41,8 +41,11 @@ STATISTIC(NumDeadBlocks, "Number of dead blocks removed"); STATISTIC(NumBranchOpts, "Number of branches optimized"); STATISTIC(NumTailMerge , "Number of block tails merged"); +STATISTIC(NumTailDups , "Number of tail duplicated blocks"); + static cl::opt FlagEnableTailMerge("enable-tail-merge", cl::init(cl::BOU_UNSET), cl::Hidden); + // Throttle for huge numbers of predecessors (compile speed problems) static cl::opt TailMergeThreshold("tail-merge-threshold", @@ -1107,6 +1110,7 @@ PredBB->addSuccessor(*I); Changed = true; + ++NumTailDups; } // If TailBB was duplicated into all its predecessors except for the prior From evan.cheng at apple.com Wed Nov 18 13:32:39 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 18 Nov 2009 11:32:39 -0800 Subject: [llvm-commits] [llvm] r89225 - /llvm/trunk/lib/CodeGen/BranchFolding.cpp In-Reply-To: <200911181929.nAIJTbZ0009865@zion.cs.uiuc.edu> References: <200911181929.nAIJTbZ0009865@zion.cs.uiuc.edu> Message-ID: <1638F085-72B9-4BEE-8D85-63A0E141CF83@apple.com> On Nov 18, 2009, at 11:29 AM, Bob Wilson wrote: > Author: bwilson > Date: Wed Nov 18 13:29:37 2009 > New Revision: 89225 > > URL: http://llvm.org/viewvc/llvm-project?rev=89225&view=rev > Log: > Add statistics for tail duplication. > > Modified: > llvm/trunk/lib/CodeGen/BranchFolding.cpp > > Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=89225&r1=89224&r2=89225&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) > +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Wed Nov 18 13:29:37 2009 > @@ -41,8 +41,11 @@ > STATISTIC(NumDeadBlocks, "Number of dead blocks removed"); > STATISTIC(NumBranchOpts, "Number of branches optimized"); > STATISTIC(NumTailMerge , "Number of block tails merged"); > +STATISTIC(NumTailDups , "Number of tail duplicated blocks"); How about number of instructions as well? :-) That tells more about code size impact. Evan > + > static cl::opt FlagEnableTailMerge("enable-tail-merge", > cl::init(cl::BOU_UNSET), cl::Hidden); > + > // Throttle for huge numbers of predecessors (compile speed problems) > static cl::opt > TailMergeThreshold("tail-merge-threshold", > @@ -1107,6 +1110,7 @@ > PredBB->addSuccessor(*I); > > Changed = true; > + ++NumTailDups; > } > > // If TailBB was duplicated into all its predecessors except for the prior > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From vkutuzov at accesssoftek.com Wed Nov 18 14:20:06 2009 From: vkutuzov at accesssoftek.com (Viktor Kutuzov) Date: Wed, 18 Nov 2009 20:20:06 -0000 Subject: [llvm-commits] [llvm] r89236 - in /llvm/trunk: include/llvm/Target/SubtargetFeature.h lib/Target/SubtargetFeature.cpp tools/lto/LTOCodeGenerator.cpp tools/lto/LTOModule.cpp tools/lto/LTOModule.h Message-ID: <200911182020.nAIKK6qq012372@zion.cs.uiuc.edu> Author: vkutuzov Date: Wed Nov 18 14:20:05 2009 New Revision: 89236 URL: http://llvm.org/viewvc/llvm-project?rev=89236&view=rev Log: Added getDefaultSubtargetFeatures method to SubtargetFeatures class which returns a correct feature string for given triple. Modified: llvm/trunk/include/llvm/Target/SubtargetFeature.h llvm/trunk/lib/Target/SubtargetFeature.cpp llvm/trunk/tools/lto/LTOCodeGenerator.cpp llvm/trunk/tools/lto/LTOModule.cpp llvm/trunk/tools/lto/LTOModule.h Modified: llvm/trunk/include/llvm/Target/SubtargetFeature.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/SubtargetFeature.h?rev=89236&r1=89235&r2=89236&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/SubtargetFeature.h (original) +++ llvm/trunk/include/llvm/Target/SubtargetFeature.h Wed Nov 18 14:20:05 2009 @@ -21,6 +21,7 @@ #include #include #include +#include "llvm/ADT/Triple.h" #include "llvm/System/DataTypes.h" namespace llvm { @@ -106,6 +107,10 @@ // Dump feature info. void dump() const; + + /// Retrieve a formatted string of the default features for + /// the specified target triple. + static std::string getDefaultSubtargetFeatures(const Triple &Triple); }; } // End namespace llvm Modified: llvm/trunk/lib/Target/SubtargetFeature.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SubtargetFeature.cpp?rev=89236&r1=89235&r2=89236&view=diff ============================================================================== --- llvm/trunk/lib/Target/SubtargetFeature.cpp (original) +++ llvm/trunk/lib/Target/SubtargetFeature.cpp Wed Nov 18 14:20:05 2009 @@ -357,3 +357,30 @@ void SubtargetFeatures::dump() const { print(errs()); } + +/// getDefaultSubtargetFeatures - Return a string listing +/// the features associated with the target triple. +/// +/// FIXME: This is an inelegant way of specifying the features of a +/// subtarget. It would be better if we could encode this information +/// into the IR. See . +/// +std::string SubtargetFeatures::getDefaultSubtargetFeatures( + const Triple& Triple) { + switch (Triple.getVendor()) { + case Triple::Apple: + switch (Triple.getArch()) { + case Triple::ppc: // powerpc-apple-* + return std::string("altivec"); + case Triple::ppc64: // powerpc64-apple-* + return std::string("64bit,altivec"); + default: + break; + } + break; + default: + break; + } + + return std::string(""); +} Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=89236&r1=89235&r2=89236&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Nov 18 14:20:05 2009 @@ -305,7 +305,8 @@ } // construct LTModule, hand over ownership of module and target - std::string FeatureStr = getFeatureString(Triple.c_str()); + const std::string FeatureStr = + SubtargetFeatures::getDefaultSubtargetFeatures(llvm::Triple(Triple)); _target = march->createTargetMachine(Triple, FeatureStr); } return false; Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=89236&r1=89235&r2=89236&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Wed Nov 18 14:20:05 2009 @@ -19,6 +19,7 @@ #include "llvm/Module.h" #include "llvm/ModuleProvider.h" #include "llvm/ADT/OwningPtr.h" +#include "llvm/ADT/Triple.h" #include "llvm/Bitcode/ReaderWriter.h" #include "llvm/Support/SystemUtils.h" #include "llvm/Support/Mangler.h" @@ -120,27 +121,6 @@ return makeLTOModule(buffer.get(), errMsg); } -/// getFeatureString - Return a string listing the features associated with the -/// target triple. -/// -/// FIXME: This is an inelegant way of specifying the features of a -/// subtarget. It would be better if we could encode this information into the -/// IR. See . -std::string getFeatureString(const char *TargetTriple) { - InitializeAllTargets(); - - SubtargetFeatures Features; - - if (strncmp(TargetTriple, "powerpc-apple-", 14) == 0) { - Features.AddFeature("altivec", true); - } else if (strncmp(TargetTriple, "powerpc64-apple-", 16) == 0) { - Features.AddFeature("64bit", true); - Features.AddFeature("altivec", true); - } - - return Features.getString(); -} - LTOModule* LTOModule::makeLTOModule(MemoryBuffer* buffer, std::string& errMsg) { @@ -161,7 +141,8 @@ return NULL; // construct LTModule, hand over ownership of module and target - std::string FeatureStr = getFeatureString(Triple.c_str()); + const std::string FeatureStr = + SubtargetFeatures::getDefaultSubtargetFeatures(llvm::Triple(Triple)); TargetMachine* target = march->createTargetMachine(Triple, FeatureStr); return new LTOModule(m.take(), target); } Modified: llvm/trunk/tools/lto/LTOModule.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.h?rev=89236&r1=89235&r2=89236&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.h (original) +++ llvm/trunk/tools/lto/LTOModule.h Wed Nov 18 14:20:05 2009 @@ -107,7 +107,5 @@ llvm::StringMap _undefines; }; -extern std::string getFeatureString(const char *TargetTriple); - #endif // LTO_MODULE_H From lhames at gmail.com Wed Nov 18 14:31:20 2009 From: lhames at gmail.com (Lang Hames) Date: Wed, 18 Nov 2009 20:31:20 -0000 Subject: [llvm-commits] [llvm] r89238 - in /llvm/trunk/lib/CodeGen: Spiller.cpp Spiller.h VirtRegRewriter.cpp Message-ID: <200911182031.nAIKVKLe012769@zion.cs.uiuc.edu> Author: lhames Date: Wed Nov 18 14:31:20 2009 New Revision: 89238 URL: http://llvm.org/viewvc/llvm-project?rev=89238&view=rev Log: Fixed the in-place spiller and trivial rewriter, which had been broken by the recent SlotIndexes work. Modified: llvm/trunk/lib/CodeGen/Spiller.cpp llvm/trunk/lib/CodeGen/Spiller.h llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Modified: llvm/trunk/lib/CodeGen/Spiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=89238&r1=89237&r2=89238&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Spiller.cpp (original) +++ llvm/trunk/lib/CodeGen/Spiller.cpp Wed Nov 18 14:31:20 2009 @@ -49,153 +49,9 @@ tii = mf->getTarget().getInstrInfo(); } - /// Ensures there is space before the given machine instruction, returns the - /// instruction's new number. - SlotIndex makeSpaceBefore(MachineInstr *mi) { - //if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) { - // FIXME: Should be updated to use rewrite-in-place methods when they're - // introduced. Currently broken. - //lis->scaleNumbering(2); - //ls->scaleNumbering(2); - //} - - SlotIndex miIdx = lis->getInstructionIndex(mi); - - //assert(lis->hasGapBeforeInstr(miIdx)); - - return miIdx; - } - - /// Ensure there is space after the given machine instruction, returns the - /// instruction's new number. - SlotIndex makeSpaceAfter(MachineInstr *mi) { - //if (!lis->hasGapAfterInstr(lis->getInstructionIndex(mi))) { - // FIXME: Should be updated to use rewrite-in-place methods when they're - // introduced. Currently broken. - // lis->scaleNumbering(2); - // ls->scaleNumbering(2); - //} - - SlotIndex miIdx = lis->getInstructionIndex(mi); - - //assert(lis->hasGapAfterInstr(miIdx)); - - return miIdx; - } - - /// Insert a store of the given vreg to the given stack slot immediately - /// after the given instruction. Returns the base index of the inserted - /// instruction. The caller is responsible for adding an appropriate - /// LiveInterval to the LiveIntervals analysis. - SlotIndex insertStoreAfter(MachineInstr *mi, unsigned ss, - unsigned vreg, - const TargetRegisterClass *trc) { - - MachineBasicBlock::iterator nextInstItr(next(mi)); - - SlotIndex miIdx = makeSpaceAfter(mi); - - tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, vreg, - true, ss, trc); - MachineBasicBlock::iterator storeInstItr(next(mi)); - MachineInstr *storeInst = &*storeInstItr; - - return lis->InsertMachineInstrInMaps(storeInst); - } - - /// Insert a store of the given vreg to the given stack slot immediately - /// before the given instructnion. Returns the base index of the inserted - /// Instruction. - SlotIndex insertStoreBefore(MachineInstr *mi, unsigned ss, - unsigned vreg, - const TargetRegisterClass *trc) { - SlotIndex miIdx = makeSpaceBefore(mi); - - tii->storeRegToStackSlot(*mi->getParent(), mi, vreg, true, ss, trc); - MachineBasicBlock::iterator storeInstItr(prior(mi)); - MachineInstr *storeInst = &*storeInstItr; - - return lis->InsertMachineInstrInMaps(storeInst); - } - - void insertStoreAfterInstOnInterval(LiveInterval *li, - MachineInstr *mi, unsigned ss, - unsigned vreg, - const TargetRegisterClass *trc) { - - SlotIndex storeInstIdx = insertStoreAfter(mi, ss, vreg, trc); - SlotIndex start = lis->getInstructionIndex(mi).getDefIndex(), - end = storeInstIdx.getUseIndex(); - - VNInfo *vni = - li->getNextValue(storeInstIdx, 0, true, lis->getVNInfoAllocator()); - vni->addKill(storeInstIdx); - DEBUG(errs() << " Inserting store range: [" << start - << ", " << end << ")\n"); - LiveRange lr(start, end, vni); - - li->addRange(lr); - } - - /// Insert a load of the given vreg from the given stack slot immediately - /// after the given instruction. Returns the base index of the inserted - /// instruction. The caller is responsibel for adding/removing an appropriate - /// range vreg's LiveInterval. - SlotIndex insertLoadAfter(MachineInstr *mi, unsigned ss, - unsigned vreg, - const TargetRegisterClass *trc) { - - MachineBasicBlock::iterator nextInstItr(next(mi)); - - SlotIndex miIdx = makeSpaceAfter(mi); - - tii->loadRegFromStackSlot(*mi->getParent(), nextInstItr, vreg, ss, trc); - MachineBasicBlock::iterator loadInstItr(next(mi)); - MachineInstr *loadInst = &*loadInstItr; - - return lis->InsertMachineInstrInMaps(loadInst); - } - - /// Insert a load of the given vreg from the given stack slot immediately - /// before the given instruction. Returns the base index of the inserted - /// instruction. The caller is responsible for adding an appropriate - /// LiveInterval to the LiveIntervals analysis. - SlotIndex insertLoadBefore(MachineInstr *mi, unsigned ss, - unsigned vreg, - const TargetRegisterClass *trc) { - SlotIndex miIdx = makeSpaceBefore(mi); - - tii->loadRegFromStackSlot(*mi->getParent(), mi, vreg, ss, trc); - MachineBasicBlock::iterator loadInstItr(prior(mi)); - MachineInstr *loadInst = &*loadInstItr; - - return lis->InsertMachineInstrInMaps(loadInst); - } - - void insertLoadBeforeInstOnInterval(LiveInterval *li, - MachineInstr *mi, unsigned ss, - unsigned vreg, - const TargetRegisterClass *trc) { - - SlotIndex loadInstIdx = insertLoadBefore(mi, ss, vreg, trc); - SlotIndex start = loadInstIdx.getDefIndex(), - end = lis->getInstructionIndex(mi).getUseIndex(); - - VNInfo *vni = - li->getNextValue(loadInstIdx, 0, true, lis->getVNInfoAllocator()); - vni->addKill(lis->getInstructionIndex(mi)); - DEBUG(errs() << " Intserting load range: [" << start - << ", " << end << ")\n"); - LiveRange lr(start, end, vni); - - li->addRange(lr); - } - - - /// Add spill ranges for every use/def of the live interval, inserting loads - /// immediately before each use, and stores after each def. No folding is - /// attempted. + /// immediately before each use, and stores after each def. No folding or + /// remat is attempted. std::vector trivialSpillEverywhere(LiveInterval *li) { DEBUG(errs() << "Spilling everywhere " << *li << "\n"); @@ -212,56 +68,77 @@ const TargetRegisterClass *trc = mri->getRegClass(li->reg); unsigned ss = vrm->assignVirt2StackSlot(li->reg); + // Iterate over reg uses/defs. for (MachineRegisterInfo::reg_iterator regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) { + // Grab the use/def instr. MachineInstr *mi = &*regItr; DEBUG(errs() << " Processing " << *mi); + // Step regItr to the next use/def instr. do { ++regItr; } while (regItr != mri->reg_end() && (&*regItr == mi)); + // Collect uses & defs for this instr. SmallVector indices; bool hasUse = false; bool hasDef = false; - for (unsigned i = 0; i != mi->getNumOperands(); ++i) { MachineOperand &op = mi->getOperand(i); - if (!op.isReg() || op.getReg() != li->reg) continue; - hasUse |= mi->getOperand(i).isUse(); hasDef |= mi->getOperand(i).isDef(); - indices.push_back(i); } + // Create a new vreg & interval for this instr. unsigned newVReg = mri->createVirtualRegister(trc); vrm->grow(); vrm->assignVirt2StackSlot(newVReg, ss); - LiveInterval *newLI = &lis->getOrCreateInterval(newVReg); newLI->weight = HUGE_VALF; + // Update the reg operands & kill flags. for (unsigned i = 0; i < indices.size(); ++i) { - mi->getOperand(indices[i]).setReg(newVReg); - - if (mi->getOperand(indices[i]).isUse()) { - mi->getOperand(indices[i]).setIsKill(true); + unsigned mopIdx = indices[i]; + MachineOperand &mop = mi->getOperand(mopIdx); + mop.setReg(newVReg); + if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) { + mop.setIsKill(true); } } - assert(hasUse || hasDef); + // Insert reload if necessary. + MachineBasicBlock::iterator miItr(mi); if (hasUse) { - insertLoadBeforeInstOnInterval(newLI, mi, ss, newVReg, trc); + tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc); + MachineInstr *loadInstr(prior(miItr)); + SlotIndex loadIndex = + lis->InsertMachineInstrInMaps(loadInstr).getDefIndex(); + SlotIndex endIndex = loadIndex.getNextIndex(); + VNInfo *loadVNI = + newLI->getNextValue(loadIndex, 0, true, lis->getVNInfoAllocator()); + loadVNI->addKill(endIndex); + newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI)); } + // Insert store if necessary. if (hasDef) { - insertStoreAfterInstOnInterval(newLI, mi, ss, newVReg, trc); + tii->storeRegToStackSlot(*mi->getParent(), next(miItr), newVReg, true, + ss, trc); + MachineInstr *storeInstr(next(miItr)); + SlotIndex storeIndex = + lis->InsertMachineInstrInMaps(storeInstr).getDefIndex(); + SlotIndex beginIndex = storeIndex.getPrevIndex(); + VNInfo *storeVNI = + newLI->getNextValue(beginIndex, 0, true, lis->getVNInfoAllocator()); + storeVNI->addKill(storeIndex); + newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI)); } added.push_back(newLI); @@ -286,55 +163,6 @@ return trivialSpillEverywhere(li); } - std::vector intraBlockSplit(LiveInterval *li, VNInfo *valno) { - std::vector spillIntervals; - - if (!valno->isDefAccurate() && !valno->isPHIDef()) { - // Early out for values which have no well defined def point. - return spillIntervals; - } - - // Ok.. we should be able to proceed... - const TargetRegisterClass *trc = mri->getRegClass(li->reg); - unsigned ss = vrm->assignVirt2StackSlot(li->reg); - vrm->grow(); - vrm->assignVirt2StackSlot(li->reg, ss); - - MachineInstr *mi = 0; - SlotIndex storeIdx = SlotIndex(); - - if (valno->isDefAccurate()) { - // If we have an accurate def we can just grab an iterator to the instr - // after the def. - mi = lis->getInstructionFromIndex(valno->def); - storeIdx = insertStoreAfter(mi, ss, li->reg, trc).getDefIndex(); - } else { - // if we get here we have a PHI def. - mi = &lis->getMBBFromIndex(valno->def)->front(); - storeIdx = insertStoreBefore(mi, ss, li->reg, trc).getDefIndex(); - } - - MachineBasicBlock *defBlock = mi->getParent(); - SlotIndex loadIdx = SlotIndex(); - - // Now we need to find the load... - MachineBasicBlock::iterator useItr(mi); - for (; !useItr->readsRegister(li->reg); ++useItr) {} - - if (useItr != defBlock->end()) { - MachineInstr *loadInst = useItr; - loadIdx = insertLoadBefore(loadInst, ss, li->reg, trc).getUseIndex(); - } - else { - MachineInstr *loadInst = &defBlock->back(); - loadIdx = insertLoadAfter(loadInst, ss, li->reg, trc).getUseIndex(); - } - - li->removeRange(storeIdx, loadIdx, true); - - return spillIntervals; - } - }; } Modified: llvm/trunk/lib/CodeGen/Spiller.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.h?rev=89238&r1=89237&r2=89238&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Spiller.h (original) +++ llvm/trunk/lib/CodeGen/Spiller.h Wed Nov 18 14:31:20 2009 @@ -34,10 +34,6 @@ /// implementation selected. virtual std::vector spill(LiveInterval *li) = 0; - /// Intra-block split. - virtual std::vector intraBlockSplit(LiveInterval *li, - VNInfo *valno) = 0; - }; /// Create and return a spiller object, as specified on the command line. Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=89238&r1=89237&r2=89238&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Wed Nov 18 14:31:20 2009 @@ -77,27 +77,38 @@ DEBUG(MF.dump()); MachineRegisterInfo *mri = &MF.getRegInfo(); + const TargetRegisterInfo *tri = MF.getTarget().getRegisterInfo(); bool changed = false; for (LiveIntervals::iterator liItr = LIs->begin(), liEnd = LIs->end(); liItr != liEnd; ++liItr) { - if (TargetRegisterInfo::isVirtualRegister(liItr->first)) { - if (VRM.hasPhys(liItr->first)) { - unsigned preg = VRM.getPhys(liItr->first); - mri->replaceRegWith(liItr->first, preg); - mri->setPhysRegUsed(preg); - changed = true; - } + const LiveInterval *li = liItr->second; + unsigned reg = li->reg; + + if (TargetRegisterInfo::isPhysicalRegister(reg)) { + if (!li->empty()) + mri->setPhysRegUsed(reg); } else { - if (!liItr->second->empty()) { - mri->setPhysRegUsed(liItr->first); + if (!VRM.hasPhys(reg)) + continue; + unsigned pReg = VRM.getPhys(reg); + mri->setPhysRegUsed(pReg); + for (MachineRegisterInfo::reg_iterator regItr = mri->reg_begin(reg), + regEnd = mri->reg_end(); regItr != regEnd;) { + MachineOperand &mop = regItr.getOperand(); + assert(mop.isReg() && mop.getReg() == reg && "reg_iterator broken?"); + ++regItr; + unsigned subRegIdx = mop.getSubReg(); + unsigned pRegOp = subRegIdx ? tri->getSubReg(pReg, subRegIdx) : pReg; + mop.setReg(pRegOp); + mop.setSubReg(0); + changed = true; } } } - DEBUG(errs() << "**** Post Machine Instrs ****\n"); DEBUG(MF.dump()); From stoklund at 2pi.dk Wed Nov 18 14:36:47 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 18 Nov 2009 20:36:47 -0000 Subject: [llvm-commits] [llvm] r89240 - in /llvm/trunk: include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/LiveIntervalAnalysis.cpp Message-ID: <200911182036.nAIKaldd012969@zion.cs.uiuc.edu> Author: stoklund Date: Wed Nov 18 14:36:47 2009 New Revision: 89240 URL: http://llvm.org/viewvc/llvm-project?rev=89240&view=rev Log: Remove the -early-coalescing option Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=89240&r1=89239&r2=89240&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Wed Nov 18 14:36:47 2009 @@ -60,9 +60,6 @@ typedef DenseMap Reg2IntervalMap; Reg2IntervalMap r2iMap_; - /// phiJoinCopies - Copy instructions which are PHI joins. - SmallVector phiJoinCopies; - /// allocatableRegs_ - A bit vector of allocatable registers. BitVector allocatableRegs_; @@ -278,13 +275,6 @@ /// computeIntervals - Compute live intervals. void computeIntervals(); - bool isSafeAndProfitableToCoalesce(LiveInterval &DstInt, - LiveInterval &SrcInt, - SmallVector &IdentCopies, - SmallVector &OtherCopies); - - void performEarlyCoalescing(); - /// handleRegisterDef - update intervals for a register def /// (calls handlePhysicalRegisterDef and /// handleVirtualRegisterDef) Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=89240&r1=89239&r2=89240&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Nov 18 14:36:47 2009 @@ -53,16 +53,9 @@ static cl::opt EnableFastSpilling("fast-spill", cl::init(false), cl::Hidden); -static cl::opt EarlyCoalescing("early-coalescing", - cl::init(false), cl::Hidden); - -static cl::opt CoalescingLimit("early-coalescing-limit", - cl::init(-1), cl::Hidden); - STATISTIC(numIntervals , "Number of original intervals"); STATISTIC(numFolds , "Number of loads/stores folded into instructions"); STATISTIC(numSplits , "Number of intervals split"); -STATISTIC(numCoalescing, "Number of early coalescing performed"); char LiveIntervals::ID = 0; static RegisterPass X("liveintervals", "Live Interval Analysis"); @@ -96,7 +89,6 @@ delete I->second; r2iMap_.clear(); - phiJoinCopies.clear(); // Release VNInfo memroy regions after all VNInfo objects are dtor'd. VNInfoAllocator.Reset(); @@ -121,7 +113,6 @@ allocatableRegs_ = tri_->getAllocatableSet(fn); computeIntervals(); - performEarlyCoalescing(); numIntervals += getNumIntervals(); @@ -409,7 +400,6 @@ // Remove the old range that we now know has an incorrect number. VNInfo *VNI = interval.getValNumInfo(0); MachineInstr *Killer = vi.Kills[0]; - phiJoinCopies.push_back(Killer); SlotIndex Start = getMBBStartIdx(Killer->getParent()); SlotIndex End = getInstructionIndex(Killer).getDefIndex(); DEBUG({ @@ -653,133 +643,6 @@ DEBUG(errs() << " +" << LR << '\n'); } -bool LiveIntervals:: -isSafeAndProfitableToCoalesce(LiveInterval &DstInt, - LiveInterval &SrcInt, - SmallVector &IdentCopies, - SmallVector &OtherCopies) { - unsigned NumIdent = 0; - for (MachineRegisterInfo::def_iterator ri = mri_->def_begin(SrcInt.reg), - re = mri_->def_end(); ri != re; ++ri) { - MachineInstr *MI = &*ri; - unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; - if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) - return false; - if (SrcReg != DstInt.reg) { - // Non-identity copy - we cannot handle overlapping intervals - if (DstInt.liveAt(getInstructionIndex(MI))) - return false; - OtherCopies.push_back(MI); - } else { - IdentCopies.push_back(MI); - ++NumIdent; - } - } - - return IdentCopies.size() > OtherCopies.size(); -} - -void LiveIntervals::performEarlyCoalescing() { - if (!EarlyCoalescing) - return; - - /// Perform early coalescing: eliminate copies which feed into phi joins - /// and whose sources are defined by the phi joins. - for (unsigned i = 0, e = phiJoinCopies.size(); i != e; ++i) { - MachineInstr *Join = phiJoinCopies[i]; - if (CoalescingLimit != -1 && (int)numCoalescing == CoalescingLimit) - break; - - unsigned PHISrc, PHIDst, SrcSubReg, DstSubReg; - bool isMove= tii_->isMoveInstr(*Join, PHISrc, PHIDst, SrcSubReg, DstSubReg); -#ifndef NDEBUG - assert(isMove && "PHI join instruction must be a move!"); -#else - isMove = isMove; -#endif - - LiveInterval &DstInt = getInterval(PHIDst); - LiveInterval &SrcInt = getInterval(PHISrc); - SmallVector IdentCopies; - SmallVector OtherCopies; - if (!isSafeAndProfitableToCoalesce(DstInt, SrcInt, - IdentCopies, OtherCopies)) - continue; - - DEBUG(errs() << "PHI Join: " << *Join); - assert(DstInt.containsOneValue() && "PHI join should have just one val#!"); - assert(std::distance(mri_->use_begin(PHISrc), mri_->use_end()) == 1 && - "PHI join src should not be used elsewhere"); - VNInfo *VNI = DstInt.getValNumInfo(0); - - // Change the non-identity copies to directly target the phi destination. - for (unsigned i = 0, e = OtherCopies.size(); i != e; ++i) { - MachineInstr *PHICopy = OtherCopies[i]; - SlotIndex MIIndex = getInstructionIndex(PHICopy); - DEBUG(errs() << "Moving: " << MIIndex << ' ' << *PHICopy); - SlotIndex DefIndex = MIIndex.getDefIndex(); - LiveRange *SLR = SrcInt.getLiveRangeContaining(DefIndex); - SlotIndex StartIndex = SLR->start; - SlotIndex EndIndex = SLR->end; - - // Delete val# defined by the now identity copy and add the range from - // beginning of the mbb to the end of the range. - SrcInt.removeValNo(SLR->valno); - DEBUG(errs() << " added range [" << StartIndex << ',' - << EndIndex << "] to reg" << DstInt.reg << '\n'); - assert (!DstInt.liveAt(StartIndex) && "Cannot coalesce when dst live!"); - VNInfo *NewVNI = DstInt.getNextValue(DefIndex, PHICopy, true, - VNInfoAllocator); - NewVNI->setHasPHIKill(true); - DstInt.addRange(LiveRange(StartIndex, EndIndex, NewVNI)); - for (unsigned j = 0, ee = PHICopy->getNumOperands(); j != ee; ++j) { - MachineOperand &MO = PHICopy->getOperand(j); - if (!MO.isReg() || MO.getReg() != PHISrc) - continue; - MO.setReg(PHIDst); - } - } - - // Now let's eliminate all the would-be identity copies. - for (unsigned i = 0, e = IdentCopies.size(); i != e; ++i) { - MachineInstr *PHICopy = IdentCopies[i]; - DEBUG(errs() << "Coalescing: " << *PHICopy); - - SlotIndex MIIndex = getInstructionIndex(PHICopy); - SlotIndex DefIndex = MIIndex.getDefIndex(); - LiveRange *SLR = SrcInt.getLiveRangeContaining(DefIndex); - SlotIndex StartIndex = SLR->start; - SlotIndex EndIndex = SLR->end; - - // Delete val# defined by the now identity copy and add the range from - // beginning of the mbb to the end of the range. - SrcInt.removeValNo(SLR->valno); - RemoveMachineInstrFromMaps(PHICopy); - PHICopy->eraseFromParent(); - DEBUG(errs() << " added range [" << StartIndex << ',' - << EndIndex << "] to reg" << DstInt.reg << '\n'); - DstInt.addRange(LiveRange(StartIndex, EndIndex, VNI)); - } - - // Remove the phi join and update the phi block liveness. - SlotIndex MIIndex = getInstructionIndex(Join); - SlotIndex UseIndex = MIIndex.getUseIndex(); - SlotIndex DefIndex = MIIndex.getDefIndex(); - LiveRange *SLR = SrcInt.getLiveRangeContaining(UseIndex); - LiveRange *DLR = DstInt.getLiveRangeContaining(DefIndex); - DLR->valno->setCopy(0); - DLR->valno->setIsDefAccurate(false); - DstInt.addRange(LiveRange(SLR->start, SLR->end, DLR->valno)); - SrcInt.removeRange(SLR->start, SLR->end); - assert(SrcInt.empty()); - removeInterval(PHISrc); - RemoveMachineInstrFromMaps(Join); - Join->eraseFromParent(); - - ++numCoalescing; - } -} - /// computeIntervals - computes the live intervals for virtual /// registers. for some ordering of the machine instructions [1,N] a /// live interval is an interval [i, j) where 1 <= i <= j < N for From stoklund at 2pi.dk Wed Nov 18 14:36:57 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 18 Nov 2009 20:36:57 -0000 Subject: [llvm-commits] [llvm] r89241 - in /llvm/trunk: include/llvm/CodeGen/MachineFunction.h lib/CodeGen/MachineVerifier.cpp Message-ID: <200911182036.nAIKavH2012987@zion.cs.uiuc.edu> Author: stoklund Date: Wed Nov 18 14:36:57 2009 New Revision: 89241 URL: http://llvm.org/viewvc/llvm-project?rev=89241&view=rev Log: Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h llvm/trunk/lib/CodeGen/MachineVerifier.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=89241&r1=89240&r2=89241&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Wed Nov 18 14:36:57 2009 @@ -233,7 +233,7 @@ /// verify - Run the current MachineFunction through the machine code /// verifier, useful for debugger use. - void verify() const; + void verify(Pass *p=NULL, bool allowDoubleDefs=false) const; // Provide accessors for the MachineBasicBlock list... typedef BasicBlockListType::iterator iterator; Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=89241&r1=89240&r2=89241&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Wed Nov 18 14:36:57 2009 @@ -42,23 +42,18 @@ using namespace llvm; namespace { - struct MachineVerifier : public MachineFunctionPass { - static char ID; // Pass ID, replacement for typeid + struct MachineVerifier { - MachineVerifier(bool allowDoubleDefs = false) : - MachineFunctionPass(&ID), + MachineVerifier(Pass *pass, bool allowDoubleDefs) : + PASS(pass), allowVirtDoubleDefs(allowDoubleDefs), allowPhysDoubleDefs(allowDoubleDefs), OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS")) - {} - - void getAnalysisUsage(AnalysisUsage &AU) const { - AU.setPreservesAll(); - MachineFunctionPass::getAnalysisUsage(AU); - } + {} bool runOnMachineFunction(MachineFunction &MF); + Pass *const PASS; const bool allowVirtDoubleDefs; const bool allowPhysDoubleDefs; @@ -112,6 +107,10 @@ // regsKilled and regsLiveOut. RegSet vregsPassed; + // Vregs that must pass through MBB because they are needed by a successor + // block. This set is disjoint from regsLiveOut. + RegSet vregsRequired; + BBInfo() : reachable(false) {} // Add register to vregsPassed if it belongs there. Return true if @@ -133,6 +132,34 @@ return changed; } + // Add register to vregsRequired if it belongs there. Return true if + // anything changed. + bool addRequired(unsigned Reg) { + if (!TargetRegisterInfo::isVirtualRegister(Reg)) + return false; + if (regsLiveOut.count(Reg)) + return false; + return vregsRequired.insert(Reg).second; + } + + // Same for a full set. + bool addRequired(const RegSet &RS) { + bool changed = false; + for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) + if (addRequired(*I)) + changed = true; + return changed; + } + + // Same for a full map. + bool addRequired(const RegMap &RM) { + bool changed = false; + for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I) + if (addRequired(I->first)) + changed = true; + return changed; + } + // Live-out registers are either in regsLiveOut or vregsPassed. bool isLiveOut(unsigned Reg) const { return regsLiveOut.count(Reg) || vregsPassed.count(Reg); @@ -146,6 +173,9 @@ return Reg < regsReserved.size() && regsReserved.test(Reg); } + // Analysis information if available + LiveVariables *LiveVars; + void visitMachineFunctionBefore(); void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB); void visitMachineInstrBefore(const MachineInstr *MI); @@ -163,20 +193,44 @@ void calcMaxRegsPassed(); void calcMinRegsPassed(); void checkPHIOps(const MachineBasicBlock *MBB); + + void calcRegsRequired(); + void verifyLiveVariables(); + }; + + struct MachineVerifierPass : public MachineFunctionPass { + static char ID; // Pass ID, replacement for typeid + bool AllowDoubleDefs; + + explicit MachineVerifierPass(bool allowDoubleDefs = false) + : MachineFunctionPass(&ID), + AllowDoubleDefs(allowDoubleDefs) {} + + void getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesAll(); + MachineFunctionPass::getAnalysisUsage(AU); + } + + bool runOnMachineFunction(MachineFunction &MF) { + MF.verify(this, AllowDoubleDefs); + return false; + } }; + } -char MachineVerifier::ID = 0; -static RegisterPass +char MachineVerifierPass::ID = 0; +static RegisterPass MachineVer("machineverifier", "Verify generated machine code"); static const PassInfo *const MachineVerifyID = &MachineVer; FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) { - return new MachineVerifier(allowPhysDoubleDefs); + return new MachineVerifierPass(allowPhysDoubleDefs); } -void MachineFunction::verify() const { - MachineVerifier().runOnMachineFunction(const_cast(*this)); +void MachineFunction::verify(Pass *p, bool allowDoubleDefs) const { + MachineVerifier(p, allowDoubleDefs) + .runOnMachineFunction(const_cast(*this)); } bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) { @@ -202,6 +256,12 @@ TRI = TM->getRegisterInfo(); MRI = &MF.getRegInfo(); + if (PASS) { + LiveVars = PASS->getAnalysisIfAvailable(); + } else { + LiveVars = NULL; + } + visitMachineFunctionBefore(); for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end(); MFI!=MFE; ++MFI) { @@ -518,8 +578,9 @@ } else if (MO->isUse()) { regsLiveInButUnused.erase(Reg); + bool isKill = false; if (MO->isKill()) { - addRegWithSubRegs(regsKilled, Reg); + isKill = true; // Tied operands on two-address instuctions MUST NOT have a flag. if (MI->isRegTiedToDefOperand(MONum)) report("Illegal kill flag on two-address instruction operand", @@ -529,8 +590,20 @@ unsigned defIdx; if (MI->isRegTiedToDefOperand(MONum, &defIdx) && MI->getOperand(defIdx).getReg() == Reg) - addRegWithSubRegs(regsKilled, Reg); + isKill = true; + } + if (isKill) { + addRegWithSubRegs(regsKilled, Reg); + + // Check that LiveVars knows this kill + if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg)) { + LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); + if (std::find(VI.Kills.begin(), + VI.Kills.end(), MI) == VI.Kills.end()) + report("Kill missing from LiveVariables", MO, MONum); + } } + // Use of a dead register. if (!regsLive.count(Reg)) { if (TargetRegisterInfo::isPhysicalRegister(Reg)) { @@ -734,6 +807,41 @@ } } +// Calculate the set of virtual registers that must be passed through each basic +// block in order to satisfy the requirements of successor blocks. This is very +// similar to calcMaxRegsPassed, only backwards. +void MachineVerifier::calcRegsRequired() { + // First push live-in regs to predecessors' vregsRequired. + DenseSet todo; + for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); + MFI != MFE; ++MFI) { + const MachineBasicBlock &MBB(*MFI); + BBInfo &MInfo = MBBInfoMap[&MBB]; + for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(), + PrE = MBB.pred_end(); PrI != PrE; ++PrI) { + BBInfo &PInfo = MBBInfoMap[*PrI]; + if (PInfo.addRequired(MInfo.vregsLiveIn)) + todo.insert(*PrI); + } + } + + // Iteratively push vregsRequired to predecessors. This will converge to the + // same final state regardless of DenseSet iteration order. + while (!todo.empty()) { + const MachineBasicBlock *MBB = *todo.begin(); + todo.erase(MBB); + BBInfo &MInfo = MBBInfoMap[MBB]; + for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), + PrE = MBB->pred_end(); PrI != PrE; ++PrI) { + if (*PrI == MBB) + continue; + BBInfo &SInfo = MBBInfoMap[*PrI]; + if (SInfo.addRequired(MInfo.vregsRequired)) + todo.insert(*PrI); + } + } +} + // Check PHI instructions at the beginning of MBB. It is assumed that // calcMinRegsPassed has been run so BBInfo::isLiveOut is valid. void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) { @@ -849,4 +957,39 @@ } } } + + // Now check LiveVariables info if available + if (LiveVars) { + calcRegsRequired(); + verifyLiveVariables(); + } } + +void MachineVerifier::verifyLiveVariables() { + assert(LiveVars && "Don't call verifyLiveVariables without LiveVars"); + for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister, + RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) { + LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); + for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); + MFI != MFE; ++MFI) { + BBInfo &MInfo = MBBInfoMap[MFI]; + + // Our vregsRequired should be identical to LiveVariables' AliveBlocks + if (MInfo.vregsRequired.count(Reg)) { + if (!VI.AliveBlocks.test(MFI->getNumber())) { + report("LiveVariables: Block missing from AliveBlocks", MFI); + *OS << "Virtual register %reg" << Reg + << " must be live through the block.\n"; + } + } else { + if (VI.AliveBlocks.test(MFI->getNumber())) { + report("LiveVariables: Block should not be in AliveBlocks", MFI); + *OS << "Virtual register %reg" << Reg + << " is not needed live through the block.\n"; + } + } + } + } +} + + From daniel at zuster.org Wed Nov 18 15:29:51 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 18 Nov 2009 21:29:51 -0000 Subject: [llvm-commits] [llvm] r89245 - in /llvm/trunk/utils/TableGen: OptParserEmitter.cpp OptParserEmitter.h TableGen.cpp Message-ID: <200911182129.nAILTp1m015264@zion.cs.uiuc.edu> Author: ddunbar Date: Wed Nov 18 15:29:51 2009 New Revision: 89245 URL: http://llvm.org/viewvc/llvm-project?rev=89245&view=rev Log: TableGen: Add initial backend for clang Driver's option parsing. Added: llvm/trunk/utils/TableGen/OptParserEmitter.cpp llvm/trunk/utils/TableGen/OptParserEmitter.h Modified: llvm/trunk/utils/TableGen/TableGen.cpp Added: llvm/trunk/utils/TableGen/OptParserEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/OptParserEmitter.cpp?rev=89245&view=auto ============================================================================== --- llvm/trunk/utils/TableGen/OptParserEmitter.cpp (added) +++ llvm/trunk/utils/TableGen/OptParserEmitter.cpp Wed Nov 18 15:29:51 2009 @@ -0,0 +1,192 @@ +//===- OptParserEmitter.cpp - Table Driven Command Line Parsing -----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "OptParserEmitter.h" +#include "Record.h" +#include "llvm/ADT/STLExtras.h" +using namespace llvm; + +static int StrCmpOptionName(const char *A, const char *B) { + char a = *A, b = *B; + while (a == b) { + if (a == '\0') + return 0; + + a = *++A; + b = *++B; + } + + if (a == '\0') // A is a prefix of B. + return 1; + if (b == '\0') // B is a prefix of A. + return -1; + + // Otherwise lexicographic. + return (a < b) ? -1 : 1; +} + +static int CompareOptionRecords(const void *Av, const void *Bv) { + const Record *A = *(Record**) Av; + const Record *B = *(Record**) Bv; + + // Compare options by name first. + if (int Cmp = StrCmpOptionName(A->getValueAsString("Name").c_str(), + B->getValueAsString("Name").c_str())) + return Cmp; + + // Then by the kind precedence; + int APrec = A->getValueAsDef("Kind")->getValueAsInt("Precedence"); + int BPrec = B->getValueAsDef("Kind")->getValueAsInt("Precedence"); + assert(APrec != BPrec && "Options are equivalent!"); + return APrec < BPrec ? -1 : 1; +} + +static const std::string getOptionName(const Record &R) { + // Use the record name unless EnumName is defined. + if (dynamic_cast(R.getValueInit("EnumName"))) + return R.getName(); + + return R.getValueAsString("EnumName"); +} + +static raw_ostream &write_cstring(raw_ostream &OS, llvm::StringRef Str) { + OS << '"'; + OS.write_escaped(Str); + OS << '"'; + return OS; +} + +void OptParserEmitter::run(raw_ostream &OS) { + // Get the option groups and options. + const std::vector &Groups = + Records.getAllDerivedDefinitions("OptionGroup"); + std::vector Opts = Records.getAllDerivedDefinitions("Option"); + + if (GenDefs) { + OS << "\ +//=== TableGen'erated File - Option Parsing Definitions ---------*- C++ -*-===//\n \ +//\n\ +// Option Parsing Definitions\n\ +//\n\ +// Automatically generated file, do not edit!\n\ +//\n\ +//===----------------------------------------------------------------------===//\n"; + } else { + OS << "\ +//=== TableGen'erated File - Option Parsing Table ---------------*- C++ -*-===//\n \ +//\n\ +// Option Parsing Definitions\n\ +//\n\ +// Automatically generated file, do not edit!\n\ +//\n\ +//===----------------------------------------------------------------------===//\n"; + } + OS << "\n"; + + array_pod_sort(Opts.begin(), Opts.end(), CompareOptionRecords); + if (GenDefs) { + OS << "#ifndef OPTION\n"; + OS << "#error \"Define OPTION prior to including this file!\"\n"; + OS << "#endif\n\n"; + + OS << "/////////\n"; + OS << "// Groups\n\n"; + for (unsigned i = 0, e = Groups.size(); i != e; ++i) { + const Record &R = *Groups[i]; + + // Start a single option entry. + OS << "OPTION("; + + // The option string. + OS << '"' << R.getValueAsString("Name") << '"'; + + // The option identifier name. + OS << ", "<< getOptionName(R); + + // The option kind. + OS << ", Group"; + + // The containing option group (if any). + OS << ", "; + if (const DefInit *DI = dynamic_cast(R.getValueInit("Group"))) + OS << getOptionName(*DI->getDef()); + else + OS << "INVALID"; + + // The other option arguments (unused for groups). + OS << ", INVALID, 0, 0, 0, 0)\n"; + } + OS << "\n"; + + OS << "//////////\n"; + OS << "// Options\n\n"; + for (unsigned i = 0, e = Opts.size(); i != e; ++i) { + const Record &R = *Opts[i]; + + // Start a single option entry. + OS << "OPTION("; + + // The option string. + write_cstring(OS, R.getValueAsString("Name")); + + // The option identifier name. + OS << ", "<< getOptionName(R); + + // The option kind. + OS << ", " << R.getValueAsDef("Kind")->getValueAsString("Name"); + + // The containing option group (if any). + OS << ", "; + if (const DefInit *DI = dynamic_cast(R.getValueInit("Group"))) + OS << getOptionName(*DI->getDef()); + else + OS << "INVALID"; + + // The option alias (if any). + OS << ", "; + if (const DefInit *DI = dynamic_cast(R.getValueInit("Alias"))) + OS << getOptionName(*DI->getDef()); + else + OS << "INVALID"; + + // The option flags. + const ListInit *LI = R.getValueAsListInit("Flags"); + if (LI->empty()) { + OS << ", 0"; + } else { + OS << ", "; + for (unsigned i = 0, e = LI->size(); i != e; ++i) { + if (i) + OS << " | "; + OS << dynamic_cast(LI->getElement(i))->getDef()->getName(); + } + } + + // The option parameter field. + OS << ", " << R.getValueAsInt("NumArgs"); + + // The option help text. + if (!dynamic_cast(R.getValueInit("HelpText"))) { + OS << ",\n"; + OS << " "; + write_cstring(OS, R.getValueAsString("HelpText")); + } else + OS << ", 0"; + + // The option meta-variable name. + OS << ", "; + if (!dynamic_cast(R.getValueInit("MetaVarName"))) + write_cstring(OS, R.getValueAsString("MetaVarName")); + else + OS << "0"; + + OS << ")\n"; + } + } +} Added: llvm/trunk/utils/TableGen/OptParserEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/OptParserEmitter.h?rev=89245&view=auto ============================================================================== --- llvm/trunk/utils/TableGen/OptParserEmitter.h (added) +++ llvm/trunk/utils/TableGen/OptParserEmitter.h Wed Nov 18 15:29:51 2009 @@ -0,0 +1,34 @@ +//===- OptParserEmitter.h - Table Driven Command Line Parsing ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef UTILS_TABLEGEN_OPTPARSEREMITTER_H +#define UTILS_TABLEGEN_OPTPARSEREMITTER_H + +#include "TableGenBackend.h" + +namespace llvm { + /// OptParserEmitter - This tablegen backend takes an input .td file + /// describing a list of options and emits a data structure for parsing and + /// working with those options when given an input command line. + class OptParserEmitter : public TableGenBackend { + RecordKeeper &Records; + bool GenDefs; + + public: + OptParserEmitter(RecordKeeper &R, bool _GenDefs) + : Records(R), GenDefs(_GenDefs) {} + + /// run - Output the option parsing information. + /// + /// \param GenHeader - Generate the header describing the option IDs.x + void run(raw_ostream &OS); + }; +} + +#endif Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=89245&r1=89244&r2=89245&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Wed Nov 18 15:29:51 2009 @@ -15,21 +15,22 @@ // //===----------------------------------------------------------------------===// -#include "Record.h" -#include "TGParser.h" +#include "AsmMatcherEmitter.h" +#include "AsmWriterEmitter.h" #include "CallingConvEmitter.h" +#include "ClangDiagnosticsEmitter.h" #include "CodeEmitterGen.h" -#include "RegisterInfoEmitter.h" -#include "InstrInfoEmitter.h" -#include "InstrEnumEmitter.h" -#include "AsmWriterEmitter.h" -#include "AsmMatcherEmitter.h" #include "DAGISelEmitter.h" #include "FastISelEmitter.h" -#include "SubtargetEmitter.h" +#include "InstrEnumEmitter.h" +#include "InstrInfoEmitter.h" #include "IntrinsicEmitter.h" #include "LLVMCConfigurationEmitter.h" -#include "ClangDiagnosticsEmitter.h" +#include "OptParserEmitter.h" +#include "Record.h" +#include "RegisterInfoEmitter.h" +#include "SubtargetEmitter.h" +#include "TGParser.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/FileUtilities.h" #include "llvm/Support/MemoryBuffer.h" @@ -50,6 +51,7 @@ GenClangDiagGroups, GenDAGISel, GenFastISel, + GenOptParserDefs, GenOptParserImpl, GenSubtarget, GenIntrinsic, GenTgtIntrinsic, @@ -84,6 +86,10 @@ "Generate a DAG instruction selector"), clEnumValN(GenFastISel, "gen-fast-isel", "Generate a \"fast\" instruction selector"), + clEnumValN(GenOptParserDefs, "gen-opt-parser-defs", + "Generate option definitions"), + clEnumValN(GenOptParserImpl, "gen-opt-parser-impl", + "Generate option parser implementation"), clEnumValN(GenSubtarget, "gen-subtarget", "Generate subtarget enumerations"), clEnumValN(GenIntrinsic, "gen-intrinsic", @@ -221,7 +227,13 @@ break; case GenClangDiagGroups: ClangDiagGroupsEmitter(Records).run(*Out); - break; + break; + case GenOptParserDefs: + OptParserEmitter(Records, true).run(*Out); + break; + case GenOptParserImpl: + OptParserEmitter(Records, false).run(*Out); + break; case GenDAGISel: DAGISelEmitter(Records).run(*Out); break; From stoklund at 2pi.dk Wed Nov 18 15:33:35 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 18 Nov 2009 21:33:35 -0000 Subject: [llvm-commits] [llvm] r89246 - in /llvm/trunk: lib/CodeGen/TwoAddressInstructionPass.cpp test/CodeGen/X86/2009-11-18-TwoAddrKill.ll Message-ID: <200911182133.nAILXZoC015458@zion.cs.uiuc.edu> Author: stoklund Date: Wed Nov 18 15:33:35 2009 New Revision: 89246 URL: http://llvm.org/viewvc/llvm-project?rev=89246&view=rev Log: Fix PR5300. When TwoAddressInstructionPass deletes a dead instruction, make sure that all register kills are accounted for. The 2-addr register does not get special treatment. Added: llvm/trunk/test/CodeGen/X86/2009-11-18-TwoAddrKill.ll Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=89246&r1=89245&r2=89246&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original) +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Wed Nov 18 15:33:35 2009 @@ -112,8 +112,7 @@ MachineBasicBlock *MBB, unsigned Dist); bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi, - MachineFunction::iterator &mbbi, - unsigned regB, unsigned regBIdx, unsigned Dist); + MachineFunction::iterator &mbbi, unsigned Dist); bool TryInstructionTransform(MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi, @@ -730,7 +729,7 @@ /// isSafeToDelete - If the specified instruction does not produce any side /// effects and all of its defs are dead, then it's safe to delete. -static bool isSafeToDelete(MachineInstr *MI, unsigned Reg, +static bool isSafeToDelete(MachineInstr *MI, const TargetInstrInfo *TII, SmallVector &Kills) { const TargetInstrDesc &TID = MI->getDesc(); @@ -745,10 +744,9 @@ continue; if (MO.isDef() && !MO.isDead()) return false; - if (MO.isUse() && MO.getReg() != Reg && MO.isKill()) + if (MO.isUse() && MO.isKill()) Kills.push_back(MO.getReg()); } - return true; } @@ -783,11 +781,10 @@ TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi, MachineFunction::iterator &mbbi, - unsigned regB, unsigned regBIdx, unsigned Dist) { // Check if the instruction has no side effects and if all its defs are dead. SmallVector Kills; - if (!isSafeToDelete(mi, regB, TII, Kills)) + if (!isSafeToDelete(mi, TII, Kills)) return false; // If this instruction kills some virtual registers, we need to @@ -810,10 +807,6 @@ LV->addVirtualRegisterKilled(Kill, NewKill); } } - - // If regB was marked as a kill, update its Kills list. - if (mi->getOperand(regBIdx).isKill()) - LV->removeVirtualRegisterKilled(regB, mi); } mbbi->erase(mi); // Nuke the old inst. @@ -842,7 +835,7 @@ // it so it doesn't clobber regB. bool regBKilled = isKilled(*mi, regB, MRI, TII); if (!regBKilled && mi->getOperand(DstIdx).isDead() && - DeleteUnusedInstr(mi, nmi, mbbi, regB, SrcIdx, Dist)) { + DeleteUnusedInstr(mi, nmi, mbbi, Dist)) { ++NumDeletes; return true; // Done with this instruction. } Added: llvm/trunk/test/CodeGen/X86/2009-11-18-TwoAddrKill.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-11-18-TwoAddrKill.ll?rev=89246&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-11-18-TwoAddrKill.ll (added) +++ llvm/trunk/test/CodeGen/X86/2009-11-18-TwoAddrKill.ll Wed Nov 18 15:33:35 2009 @@ -0,0 +1,29 @@ +; RUN: llc < %s +; PR 5300 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i386-pc-linux-gnu" + + at g_296 = external global i8, align 1 ; [#uses=1] + +define noalias i8** @func_31(i32** nocapture %int8p_33, i8** nocapture %p_34, i8* nocapture %p_35) nounwind { +entry: + %cmp.i = icmp sgt i16 undef, 234 ; [#uses=1] + %tmp17 = select i1 %cmp.i, i16 undef, i16 0 ; [#uses=2] + %conv8 = trunc i16 %tmp17 to i8 ; [#uses=3] + br i1 undef, label %cond.false.i29, label %land.lhs.true.i + +land.lhs.true.i: ; preds = %entry + %tobool5.i = icmp eq i32 undef, undef ; [#uses=1] + br i1 %tobool5.i, label %cond.false.i29, label %bar.exit + +cond.false.i29: ; preds = %land.lhs.true.i, %entry + %tmp = sub i8 0, %conv8 ; [#uses=1] + %mul.i = and i8 %conv8, %tmp ; [#uses=1] + br label %bar.exit + +bar.exit: ; preds = %cond.false.i29, %land.lhs.true.i + %call1231 = phi i8 [ %mul.i, %cond.false.i29 ], [ %conv8, %land.lhs.true.i ] ; [#uses=0] + %conv21 = trunc i16 %tmp17 to i8 ; [#uses=1] + store i8 %conv21, i8* @g_296 + ret i8** undef +} From isanbard at gmail.com Wed Nov 18 15:54:13 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 18 Nov 2009 21:54:13 -0000 Subject: [llvm-commits] [llvm] r89250 - /llvm/trunk/test/FrontendC++/2009-07-15-LineNumbers.cpp Message-ID: <200911182154.nAILsDth016464@zion.cs.uiuc.edu> Author: void Date: Wed Nov 18 15:54:13 2009 New Revision: 89250 URL: http://llvm.org/viewvc/llvm-project?rev=89250&view=rev Log: Not all ASM has # for comments. Modified: llvm/trunk/test/FrontendC++/2009-07-15-LineNumbers.cpp Modified: llvm/trunk/test/FrontendC++/2009-07-15-LineNumbers.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2009-07-15-LineNumbers.cpp?rev=89250&r1=89249&r2=89250&view=diff ============================================================================== --- llvm/trunk/test/FrontendC++/2009-07-15-LineNumbers.cpp (original) +++ llvm/trunk/test/FrontendC++/2009-07-15-LineNumbers.cpp Wed Nov 18 15:54:13 2009 @@ -1,7 +1,7 @@ // This is a regression test on debug info to make sure that we can // print line numbers in asm. // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \ -// RUN: llc --disable-fp-elim -O0 -relocation-model=pic | grep {# SrcLine 25} +// RUN: llc --disable-fp-elim -O0 -relocation-model=pic | grep {SrcLine 25} #include From jyasskin at google.com Wed Nov 18 16:04:44 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Wed, 18 Nov 2009 22:04:44 -0000 Subject: [llvm-commits] [llvm] r89252 - /llvm/trunk/include/llvm/Support/MemoryBuffer.h Message-ID: <200911182204.nAIM4iw9017046@zion.cs.uiuc.edu> Author: jyasskin Date: Wed Nov 18 16:04:44 2009 New Revision: 89252 URL: http://llvm.org/viewvc/llvm-project?rev=89252&view=rev Log: Remove spurious @verbatim. Patch by Timo Juhani Lindfors! Modified: llvm/trunk/include/llvm/Support/MemoryBuffer.h Modified: llvm/trunk/include/llvm/Support/MemoryBuffer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/MemoryBuffer.h?rev=89252&r1=89251&r2=89252&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/MemoryBuffer.h (original) +++ llvm/trunk/include/llvm/Support/MemoryBuffer.h Wed Nov 18 16:04:44 2009 @@ -24,7 +24,7 @@ /// of memory, and provides simple methods for reading files and standard input /// into a memory buffer. In addition to basic access to the characters in the /// file, this interface guarantees you can read one character past the end of -/// @verbatim the file, and that this character will read as '\0'. @endverbatim +/// the file, and that this character will read as '\0'. class MemoryBuffer { const char *BufferStart; // Start of the buffer. const char *BufferEnd; // End of the buffer. From bob.wilson at apple.com Wed Nov 18 16:12:31 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 18 Nov 2009 22:12:31 -0000 Subject: [llvm-commits] [llvm] r89254 - /llvm/trunk/lib/CodeGen/BranchFolding.cpp Message-ID: <200911182212.nAIMCVcl017401@zion.cs.uiuc.edu> Author: bwilson Date: Wed Nov 18 16:12:31 2009 New Revision: 89254 URL: http://llvm.org/viewvc/llvm-project?rev=89254&view=rev Log: Add another statistic to measure code size due to tail duplication. Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=89254&r1=89253&r2=89254&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Wed Nov 18 16:12:31 2009 @@ -42,6 +42,7 @@ STATISTIC(NumBranchOpts, "Number of branches optimized"); STATISTIC(NumTailMerge , "Number of block tails merged"); STATISTIC(NumTailDups , "Number of tail duplicated blocks"); +STATISTIC(NumInstrDups , "Additional instructions due to tail duplication"); static cl::opt FlagEnableTailMerge("enable-tail-merge", cl::init(cl::BOU_UNSET), cl::Hidden); @@ -1020,6 +1021,7 @@ // If it is dead, remove it. if (MBB->pred_empty()) { + NumInstrDups -= MBB->size(); RemoveDeadBlock(MBB); MadeChange = true; ++NumDeadBlocks; @@ -1100,6 +1102,7 @@ MachineInstr *NewMI = MF.CloneMachineInstr(I); PredBB->insert(PredBB->end(), NewMI); } + NumInstrDups += TailBB->size() - 1; // subtract one for removed branch // Update the CFG. PredBB->removeSuccessor(PredBB->succ_begin()); From bob.wilson at apple.com Wed Nov 18 16:52:37 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 18 Nov 2009 22:52:37 -0000 Subject: [llvm-commits] [llvm] r89264 - in /llvm/trunk: lib/CodeGen/BranchFolding.cpp test/CodeGen/ARM/tail-opts.ll Message-ID: <200911182252.nAIMqbqi019189@zion.cs.uiuc.edu> Author: bwilson Date: Wed Nov 18 16:52:37 2009 New Revision: 89264 URL: http://llvm.org/viewvc/llvm-project?rev=89264&view=rev Log: Tail duplication still needs to iterate. Duplicating new instructions onto the tail of a block may make that block a new candidate for duplication. Added: llvm/trunk/test/CodeGen/ARM/tail-opts.ll Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=89264&r1=89263&r2=89264&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Wed Nov 18 16:52:37 2009 @@ -197,7 +197,6 @@ MadeChange |= OptimizeImpDefsBlock(MBB); } - bool MadeChangeThisIteration = true; while (MadeChangeThisIteration) { MadeChangeThisIteration = false; @@ -206,10 +205,15 @@ MadeChange |= MadeChangeThisIteration; } - // Do tail duplication once after tail merging is done. Otherwise it is + // Do tail duplication after tail merging is done. Otherwise it is // tough to avoid situations where tail duplication and tail merging undo // each other's transformations ad infinitum. - MadeChange |= TailDuplicateBlocks(MF); + MadeChangeThisIteration = true; + while (MadeChangeThisIteration) { + MadeChangeThisIteration = false; + MadeChangeThisIteration |= TailDuplicateBlocks(MF); + MadeChange |= MadeChangeThisIteration; + } // See if any jump tables have become mergable or dead as the code generator // did its thing. Added: llvm/trunk/test/CodeGen/ARM/tail-opts.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/tail-opts.ll?rev=89264&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/tail-opts.ll (added) +++ llvm/trunk/test/CodeGen/ARM/tail-opts.ll Wed Nov 18 16:52:37 2009 @@ -0,0 +1,64 @@ +; RUN: llc < %s -march=arm -mcpu=cortex-a8 -asm-verbose=false | FileCheck %s + +declare void @bar(i32) +declare void @car(i32) +declare void @dar(i32) +declare void @ear(i32) +declare void @far(i32) +declare i1 @qux() + + at GHJK = global i32 0 + +declare i8* @choose(i8*, i8*); + +; BranchFolding should tail-duplicate the indirect jump to avoid +; redundant branching. + +; CHECK: tail_duplicate_me: +; CHECK: qux +; CHECK: qux +; CHECK: ldr r{{.}}, LCPI +; CHECK: str r +; CHECK-NEXT: bx r +; CHECK: ldr r{{.}}, LCPI +; CHECK: str r +; CHECK-NEXT: bx r +; CHECK: ldr r{{.}}, LCPI +; CHECK: str r +; CHECK-NEXT: bx r + +define void @tail_duplicate_me() nounwind { +entry: + %a = call i1 @qux() + %c = call i8* @choose(i8* blockaddress(@tail_duplicate_me, %return), + i8* blockaddress(@tail_duplicate_me, %altret)) + br i1 %a, label %A, label %next +next: + %b = call i1 @qux() + br i1 %b, label %B, label %C + +A: + call void @bar(i32 0) + store i32 0, i32* @GHJK + br label %M + +B: + call void @car(i32 1) + store i32 0, i32* @GHJK + br label %M + +C: + call void @dar(i32 2) + store i32 0, i32* @GHJK + br label %M + +M: + indirectbr i8* %c, [label %return, label %altret] + +return: + call void @ear(i32 1000) + ret void +altret: + call void @far(i32 1001) + ret void +} From isanbard at gmail.com Wed Nov 18 17:18:47 2009 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 18 Nov 2009 23:18:47 -0000 Subject: [llvm-commits] [llvm] r89270 - in /llvm/trunk/lib: CodeGen/AsmPrinter/DwarfException.cpp Target/TargetLoweringObjectFile.cpp Message-ID: <200911182318.nAINIl30020450@zion.cs.uiuc.edu> Author: void Date: Wed Nov 18 17:18:46 2009 New Revision: 89270 URL: http://llvm.org/viewvc/llvm-project?rev=89270&view=rev Log: Attempt #2: Place the EH table in the __TEXT section on MachO. It saves space. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp?rev=89270&r1=89269&r2=89270&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Wed Nov 18 17:18:46 2009 @@ -727,7 +727,8 @@ // somewhere. This predicate should be moved to a shared location that is // in target-independent code. // - if (LSDASection->getKind().isWriteable() || + if ((LSDASection->getKind().isWriteable() && + !LSDASection->getKind().isDataRel()) || Asm->TM.getRelocationModel() == Reloc::Static) TTypeFormat = dwarf::DW_EH_PE_absptr; else @@ -917,14 +918,35 @@ } // Emit the Catch TypeInfos. + const TargetLoweringObjectFile &TLOF = Asm->getObjFileLowering(); + unsigned Index = 1; + for (std::vector::const_reverse_iterator - I = TypeInfos.rbegin(), E = TypeInfos.rend(); I != E; ++I) { - const GlobalVariable *GV = *I; - PrintRelDirective(); + I = TypeInfos.rbegin(), E = TypeInfos.rend(); I != E; ++I, ++Index) { + const GlobalVariable *TI = *I; + + if (TI) { + if (!LSDASection->getKind().isDataRel() && + (TTypeFormat == dwarf::DW_EH_PE_absptr || + TI->getLinkage() == GlobalValue::InternalLinkage)) { + // Print out the unadorned name of the type info. + PrintRelDirective(); + O << Asm->Mang->getMangledName(TI); + } else { + bool IsTypeInfoIndirect = false, IsTypeInfoPCRel = false; + const MCExpr *TypeInfoRef = + TLOF.getSymbolForDwarfGlobalReference(TI, Asm->Mang, Asm->MMI, + IsTypeInfoIndirect, + IsTypeInfoPCRel); - if (GV) { - O << Asm->Mang->getMangledName(GV); + if (!IsTypeInfoPCRel) + TypeInfoRef = CreateLabelDiff(TypeInfoRef, "typeinforef_addr", Index); + + O << MAI->getData32bitsDirective(); + TypeInfoRef->print(O, MAI); + } } else { + PrintRelDirective(); O << "0x0"; } Modified: llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp?rev=89270&r1=89269&r2=89270&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp (original) +++ llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Wed Nov 18 17:18:46 2009 @@ -783,7 +783,7 @@ } // Exception Handling. - LSDASection = getMachOSection("__DATA", "__gcc_except_tab", 0, + LSDASection = getMachOSection("__TEXT", "__gcc_except_tab", 0, SectionKind::getDataRel()); EHFrameSection = getMachOSection("__TEXT", "__eh_frame", From dgregor at apple.com Wed Nov 18 17:20:09 2009 From: dgregor at apple.com (Douglas Gregor) Date: Wed, 18 Nov 2009 23:20:09 -0000 Subject: [llvm-commits] [llvm] r89272 - /llvm/trunk/utils/TableGen/CMakeLists.txt Message-ID: <200911182320.nAINK93s020531@zion.cs.uiuc.edu> Author: dgregor Date: Wed Nov 18 17:20:09 2009 New Revision: 89272 URL: http://llvm.org/viewvc/llvm-project?rev=89272&view=rev Log: De-bork CMake build Modified: llvm/trunk/utils/TableGen/CMakeLists.txt Modified: llvm/trunk/utils/TableGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=89272&r1=89271&r2=89272&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CMakeLists.txt (original) +++ llvm/trunk/utils/TableGen/CMakeLists.txt Wed Nov 18 17:20:09 2009 @@ -13,6 +13,7 @@ InstrInfoEmitter.cpp IntrinsicEmitter.cpp LLVMCConfigurationEmitter.cpp + OptParserEmitter.cpp Record.cpp RegisterInfoEmitter.cpp SubtargetEmitter.cpp From richard at xmos.com Wed Nov 18 17:20:42 2009 From: richard at xmos.com (Richard Osborne) Date: Wed, 18 Nov 2009 23:20:42 -0000 Subject: [llvm-commits] [llvm] r89273 - in /llvm/trunk: lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp lib/Target/XCore/XCoreISelLowering.cpp lib/Target/XCore/XCoreISelLowering.h lib/Target/XCore/XCoreInstrInfo.td test/CodeGen/XCore/indirectbr.ll Message-ID: <200911182320.nAINKghX020568@zion.cs.uiuc.edu> Author: friedgold Date: Wed Nov 18 17:20:42 2009 New Revision: 89273 URL: http://llvm.org/viewvc/llvm-project?rev=89273&view=rev Log: Add XCore support for indirectbr / blockaddress. Added: llvm/trunk/test/CodeGen/XCore/indirectbr.ll Modified: llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp llvm/trunk/lib/Target/XCore/XCoreISelLowering.h llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Modified: llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp?rev=89273&r1=89272&r2=89273&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp Wed Nov 18 17:20:42 2009 @@ -333,6 +333,8 @@ case MachineOperand::MO_JumpTableIndex: O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_' << MO.getIndex(); + case MachineOperand::MO_BlockAddress: + GetBlockAddressSymbol(MO.getBlockAddress())->print(O, MAI); break; default: llvm_unreachable("not implemented"); Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=89273&r1=89272&r2=89273&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Wed Nov 18 17:20:42 2009 @@ -111,7 +111,8 @@ setOperationAction(ISD::JumpTable, MVT::i32, Custom); setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); - + setOperationAction(ISD::BlockAddress, MVT::i32 , Custom); + // Thread Local Storage setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); @@ -158,6 +159,7 @@ { case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); + case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); case ISD::ConstantPool: return LowerConstantPool(Op, DAG); case ISD::JumpTable: return LowerJumpTable(Op, DAG); case ISD::LOAD: return LowerLOAD(Op, DAG); @@ -288,6 +290,17 @@ } SDValue XCoreTargetLowering:: +LowerBlockAddress(SDValue Op, SelectionDAG &DAG) +{ + DebugLoc DL = Op.getDebugLoc(); + + BlockAddress *BA = cast(Op)->getBlockAddress(); + SDValue Result = DAG.getBlockAddress(BA, DL, /*isTarget=*/true); + + return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result); +} + +SDValue XCoreTargetLowering:: LowerConstantPool(SDValue Op, SelectionDAG &DAG) { ConstantPoolSDNode *CP = cast(Op); Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.h?rev=89273&r1=89272&r2=89273&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.h Wed Nov 18 17:20:42 2009 @@ -120,6 +120,7 @@ SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); + SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=89273&r1=89272&r2=89273&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Wed Nov 18 17:20:42 2009 @@ -679,6 +679,12 @@ "ldap r11, $addr", [(set R11, (pcrelwrapper tglobaladdr:$addr))]>; +let Defs = [R11], isReMaterializable = 1 in +def LDAP_lu10_ba : _FLU10<(outs), + (ins i32imm:$addr), + "ldap r11, $addr", + [(set R11, (pcrelwrapper tblockaddress:$addr))]>; + let isCall=1, // All calls clobber the the link register and the non-callee-saved registers: Defs = [R0, R1, R2, R3, R11, LR] in { Added: llvm/trunk/test/CodeGen/XCore/indirectbr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/indirectbr.ll?rev=89273&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/XCore/indirectbr.ll (added) +++ llvm/trunk/test/CodeGen/XCore/indirectbr.ll Wed Nov 18 17:20:42 2009 @@ -0,0 +1,45 @@ +; RUN: llc < %s -march=xcore | FileCheck %s + + at nextaddr = global i8* null ; [#uses=2] + at C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] + +define internal i32 @foo(i32 %i) nounwind { +; CHECK: foo: +entry: + %0 = load i8** @nextaddr, align 4 ; [#uses=2] + %1 = icmp eq i8* %0, null ; [#uses=1] + br i1 %1, label %bb3, label %bb2 + +bb2: ; preds = %entry, %bb3 + %gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; [#uses=1] +; CHECK: bau + indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1] + +bb3: ; preds = %entry + %2 = getelementptr inbounds [5 x i8*]* @C.0.2070, i32 0, i32 %i ; [#uses=1] + %gotovar.4.0.pre = load i8** %2, align 4 ; [#uses=1] + br label %bb2 + +L5: ; preds = %bb2 + br label %L4 + +L4: ; preds = %L5, %bb2 + %res.0 = phi i32 [ 385, %L5 ], [ 35, %bb2 ] ; [#uses=1] + br label %L3 + +L3: ; preds = %L4, %bb2 + %res.1 = phi i32 [ %res.0, %L4 ], [ 5, %bb2 ] ; [#uses=1] + br label %L2 + +L2: ; preds = %L3, %bb2 + %res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ] ; [#uses=1] + %phitmp = mul i32 %res.2, 6 ; [#uses=1] + br label %L1 + +L1: ; preds = %L2, %bb2 + %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; [#uses=1] +; CHECK: ldap r11, .LBA3_foo_L5 +; CHECK: stw r11, dp[nextaddr] + store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 + ret i32 %res.3 +} From bob.wilson at apple.com Wed Nov 18 17:30:38 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 18 Nov 2009 23:30:38 -0000 Subject: [llvm-commits] [llvm] r89274 - /llvm/trunk/test/CodeGen/ARM/tail-opts.ll Message-ID: <200911182330.nAINUcNL020972@zion.cs.uiuc.edu> Author: bwilson Date: Wed Nov 18 17:30:38 2009 New Revision: 89274 URL: http://llvm.org/viewvc/llvm-project?rev=89274&view=rev Log: Fix buildbots. Modified: llvm/trunk/test/CodeGen/ARM/tail-opts.ll Modified: llvm/trunk/test/CodeGen/ARM/tail-opts.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/tail-opts.ll?rev=89274&r1=89273&r2=89274&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/tail-opts.ll (original) +++ llvm/trunk/test/CodeGen/ARM/tail-opts.ll Wed Nov 18 17:30:38 2009 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mcpu=cortex-a8 -asm-verbose=false | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 -asm-verbose=false | FileCheck %s declare void @bar(i32) declare void @car(i32) From bob.wilson at apple.com Wed Nov 18 17:48:59 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 18 Nov 2009 23:48:59 -0000 Subject: [llvm-commits] [llvm] r89275 - /llvm/trunk/lib/CodeGen/BranchFolding.cpp Message-ID: <200911182348.nAINmxvf021702@zion.cs.uiuc.edu> Author: bwilson Date: Wed Nov 18 17:48:57 2009 New Revision: 89275 URL: http://llvm.org/viewvc/llvm-project?rev=89275&view=rev Log: There should be no need to keep renumbering blocks during tail duplication. Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=89275&r1=89274&r2=89275&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Wed Nov 18 17:48:57 2009 @@ -1011,9 +1011,6 @@ bool BranchFolder::TailDuplicateBlocks(MachineFunction &MF) { bool MadeChange = false; - // Make sure blocks are numbered in order - MF.RenumberBlocks(); - for (MachineFunction::iterator I = ++MF.begin(), E = MF.end(); I != E; ) { MachineBasicBlock *MBB = I++; From vkutuzov at accesssoftek.com Wed Nov 18 17:54:25 2009 From: vkutuzov at accesssoftek.com (Viktor Kutuzov) Date: Wed, 18 Nov 2009 15:54:25 -0800 Subject: [llvm-commits] [PATCH] LTO code generator options References: <04F6B1512E264B27AEE607542FCDD113@andreic6e7fe55> <38a0d8450911101625s5e3b7cb0m31ec0ce4d4144dc@mail.gmail.com> <38a0d8450911121059n6a0d3eb0ka34711d931c7675e@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BA@mail.accesssoftek.com> <38a0d8450911141921r7deec8b3k91e06950263f0485@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BF@mail.accesssoftek.com> <38a0d8450911170809j6a32716ar840b8622cfad6f17@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607C4@mail.accesssoftek.com> <38a0d8450911180722j5a463fa8hec81178154deaf09@mail.gmail.com> Message-ID: <41BA1AA405BC4D19BA9B4FAB6543D62F@andreic6e7fe55> Thanks, Nick and Rafael! > Two t's in formatted. Fixed. >> You have to change the .c_str() to llvm::Triple(). Fixed. Patch is committed. http://llvm.org/viewvc/llvm-project?rev=89236&view=rev And while we are all on it, here is the next patch in this sequence (please find it attached). This patch adds two SubtargetFeatures::AddFeatures methods which accept a comma-separated string or already parsed command line parameters as input, SubtargetFeatures::hasFeature method which cheks if given feature is already set, and some code re-factoring to use these new methods. Best regards, Viktor ----- Original Message ----- From: Nick Lewycky To: Rafael Espindola Cc: Viktor Kutuzov ; Commit Messages and Patches for LLVM Sent: Wednesday, November 18, 2009 10:34 AM Subject: Re: [llvm-commits] [PATCH] LTO code generator options + /// Retrieve a formated string of the default features for + /// the specified target triple. + static std::string getDefaultSubtargetFeatures(const Triple &Triple); Two t's in formatted. 2009/11/18 Rafael Espindola 2009/11/17 Viktor Kutuzov : > Thanks for reviewing it, Rafael. > > Now while we are both on the same waive, let's go with the rest of the patches. Have you committed the previous one? > I have tried to combine them on the same manner as the last one. Thanks! You have + const std::string FeatureStr = + SubtargetFeatures::getDefaultSubtargetFeatures(Triple.c_str()); But getDefaultSubtargetFeatures takes a triple. You have to change the .c_str() to llvm::Triple(). I think the patch is OK with that change. Nick, can you just comment on lib/Target/SubtargetFeature.cpp being the right place to put this? I think it is, but I am not as familiar with this code. I'm not familiar with most of lib/Target or lib/CodeGen either, but after reading through SubtargetFeature.{cpp,h} it looks like the right place to me. Nick > The attached patch has similar OS and Vendor independent re-factoring for Subtarget features (attributes). > > I moved Applce-specific code from tools/lto/LTOModule.cpp to lib/Target/SubtargetFeature.cpp with related header files update. > > Cheers, > Viktor. > Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091118/d701df58/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-lto-codegen-subtargetfeature-extended_functionality.diff Type: application/octet-stream Size: 4436 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091118/d701df58/attachment.obj From daniel at zuster.org Wed Nov 18 18:04:44 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 19 Nov 2009 00:04:44 -0000 Subject: [llvm-commits] [llvm] r89278 - /llvm/trunk/include/llvm/ADT/Twine.h Message-ID: <200911190004.nAJ04jBH022505@zion.cs.uiuc.edu> Author: ddunbar Date: Wed Nov 18 18:04:43 2009 New Revision: 89278 URL: http://llvm.org/viewvc/llvm-project?rev=89278&view=rev Log: Twine: Stores kinds as uchar instead of bitfield to be friendlier to the optimizer. Modified: llvm/trunk/include/llvm/ADT/Twine.h Modified: llvm/trunk/include/llvm/ADT/Twine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Twine.h?rev=89278&r1=89277&r2=89278&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/Twine.h (original) +++ llvm/trunk/include/llvm/ADT/Twine.h Wed Nov 18 18:04:43 2009 @@ -133,9 +133,9 @@ /// Null or Empty kinds. const void *RHS; /// LHSKind - The NodeKind of the left hand side, \see getLHSKind(). - NodeKind LHSKind : 8; + unsigned char LHSKind; /// RHSKind - The NodeKind of the left hand side, \see getLHSKind(). - NodeKind RHSKind : 8; + unsigned char RHSKind; private: /// Construct a nullary twine; the kind must be NullKind or EmptyKind. @@ -209,10 +209,10 @@ } /// getLHSKind - Get the NodeKind of the left-hand side. - NodeKind getLHSKind() const { return LHSKind; } + NodeKind getLHSKind() const { return (NodeKind) LHSKind; } /// getRHSKind - Get the NodeKind of the left-hand side. - NodeKind getRHSKind() const { return RHSKind; } + NodeKind getRHSKind() const { return (NodeKind) RHSKind; } /// printOneChild - Print one child from a twine. void printOneChild(raw_ostream &OS, const void *Ptr, NodeKind Kind) const; From isanbard at gmail.com Wed Nov 18 18:09:14 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 19 Nov 2009 00:09:14 -0000 Subject: [llvm-commits] [llvm] r89279 - in /llvm/trunk/lib: CodeGen/AsmPrinter/DwarfException.cpp Target/TargetLoweringObjectFile.cpp Message-ID: <200911190009.nAJ09EsP022919@zion.cs.uiuc.edu> Author: void Date: Wed Nov 18 18:09:14 2009 New Revision: 89279 URL: http://llvm.org/viewvc/llvm-project?rev=89279&view=rev Log: The "ReadOnlyWithRel" enum seems to apply more to what Darwin does with the EH exception table than DataRel. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp?rev=89279&r1=89278&r2=89279&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Wed Nov 18 18:09:14 2009 @@ -728,7 +728,7 @@ // in target-independent code. // if ((LSDASection->getKind().isWriteable() && - !LSDASection->getKind().isDataRel()) || + !LSDASection->getKind().isReadOnlyWithRel()) || Asm->TM.getRelocationModel() == Reloc::Static) TTypeFormat = dwarf::DW_EH_PE_absptr; else @@ -922,11 +922,11 @@ unsigned Index = 1; for (std::vector::const_reverse_iterator - I = TypeInfos.rbegin(), E = TypeInfos.rend(); I != E; ++I, ++Index) { + I = TypeInfos.rbegin(), E = TypeInfos.rend(); I != E; ++I) { const GlobalVariable *TI = *I; if (TI) { - if (!LSDASection->getKind().isDataRel() && + if (!LSDASection->getKind().isReadOnlyWithRel() && (TTypeFormat == dwarf::DW_EH_PE_absptr || TI->getLinkage() == GlobalValue::InternalLinkage)) { // Print out the unadorned name of the type info. @@ -940,7 +940,8 @@ IsTypeInfoPCRel); if (!IsTypeInfoPCRel) - TypeInfoRef = CreateLabelDiff(TypeInfoRef, "typeinforef_addr", Index); + TypeInfoRef = CreateLabelDiff(TypeInfoRef, "typeinforef_addr", + Index++); O << MAI->getData32bitsDirective(); TypeInfoRef->print(O, MAI); Modified: llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp?rev=89279&r1=89278&r2=89279&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp (original) +++ llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Wed Nov 18 18:09:14 2009 @@ -784,7 +784,7 @@ // Exception Handling. LSDASection = getMachOSection("__TEXT", "__gcc_except_tab", 0, - SectionKind::getDataRel()); + SectionKind::getReadOnlyWithRel()); EHFrameSection = getMachOSection("__TEXT", "__eh_frame", MCSectionMachO::S_COALESCED | From daniel at zuster.org Wed Nov 18 18:14:53 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 19 Nov 2009 00:14:53 -0000 Subject: [llvm-commits] [llvm] r89282 - /llvm/trunk/Makefile.rules Message-ID: <200911190014.nAJ0ErRt023413@zion.cs.uiuc.edu> Author: ddunbar Date: Wed Nov 18 18:14:53 2009 New Revision: 89282 URL: http://llvm.org/viewvc/llvm-project?rev=89282&view=rev Log: Add TOOLALIAS makefile variable; this defines an alternate name for a program which the makefiles will create by symlinking the actual tool to. - For use by clang, where we want to make 'clang++' and alias for clang (which enables C++ support in the driver) - Not sure this is the best approach, alternative suggestions welcome! Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=89282&r1=89281&r2=89282&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Wed Nov 18 18:14:53 2009 @@ -736,6 +736,8 @@ Ranlib = ranlib endif +AliasTool = ln -s + #---------------------------------------------------------- # Get the list of source files and compute object file # names from them. @@ -1215,10 +1217,20 @@ #--------------------------------------------------------- # Set up variables for building a tool. #--------------------------------------------------------- +TOOLEXENAME := $(strip $(TOOLNAME))$(EXEEXT) +ifdef EXAMPLE_TOOL +ToolBuildPath := $(ExmplDir)/$(TOOLEXENAME) +else +ToolBuildPath := $(ToolDir)/$(TOOLEXENAME) +endif + +# TOOLALIAS is a name to symlink (or copy) the tool to. +ifdef TOOLALIAS ifdef EXAMPLE_TOOL -ToolBuildPath := $(ExmplDir)/$(strip $(TOOLNAME))$(EXEEXT) +ToolAliasBuildPath := $(ExmplDir)/$(strip $(TOOLALIAS))$(EXEEXT) else -ToolBuildPath := $(ToolDir)/$(strip $(TOOLNAME))$(EXEEXT) +ToolAliasBuildPath := $(ToolDir)/$(strip $(TOOLALIAS))$(EXEEXT) +endif endif #--------------------------------------------------------- @@ -1246,12 +1258,15 @@ #--------------------------------------------------------- # Provide targets for building the tools #--------------------------------------------------------- -all-local:: $(ToolBuildPath) +all-local:: $(ToolBuildPath) $(ToolAliasBuildPath) clean-local:: ifneq ($(strip $(ToolBuildPath)),) -$(Verb) $(RM) -f $(ToolBuildPath) endif +ifneq ($(strip $(ToolAliasBuildPath)),) + -$(Verb) $(RM) -f $(ToolAliasBuildPath) +endif ifdef EXAMPLE_TOOL $(ToolBuildPath): $(ExmplDir)/.dir @@ -1266,13 +1281,22 @@ $(Echo) ======= Finished Linking $(BuildMode) Executable $(TOOLNAME) \ $(StripWarnMsg) +ifneq ($(strip $(ToolAliasBuildPath)),) +$(ToolAliasBuildPath): $(ToolBuildPath) + $(Echo) Creating $(BuildMode) Alias $(TOOLALIAS) $(StripWarnMsg) + $(Verb) $(RM) -f $(ToolAliasBuildPath) + $(Verb) $(AliasTool) $(TOOLEXENAME) $(ToolAliasBuildPath) + $(Echo) ======= Finished Creating $(BuildMode) Alias $(TOOLNAME) \ + $(StripWarnMsg) +endif + ifdef NO_INSTALL install-local:: $(Echo) Install circumvented with NO_INSTALL uninstall-local:: $(Echo) Uninstall circumvented with NO_INSTALL else -DestTool = $(PROJ_bindir)/$(TOOLNAME)$(EXEEXT) +DestTool = $(PROJ_bindir)/$(TOOLEXENAME) install-local:: $(DestTool) @@ -1283,6 +1307,23 @@ uninstall-local:: $(Echo) Uninstalling $(BuildMode) $(DestTool) -$(Verb) $(RM) -f $(DestTool) + +# TOOLALIAS install. +ifdef TOOLALIAS +DestToolAlias = $(PROJ_bindir)/$(TOOLALIAS)$(EXEEXT) + +install-local:: $(DestToolAlias) + +$(DestToolAlias): $(DestTool) $(PROJ_bindir) + $(Echo) Installing $(BuildMode) $(DestToolAlias) + $(Verb) $(RM) -f $(DestToolAlias) + $(Verb) $(AliasTool) $(TOOLEXENAME) $(DestToolAlias) + +uninstall-local:: + $(Echo) Uninstalling $(BuildMode) $(DestToolAlias) + -$(Verb) $(RM) -f $(DestToolAlias) +endif + endif endif From isanbard at gmail.com Wed Nov 18 19:33:57 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 19 Nov 2009 01:33:57 -0000 Subject: [llvm-commits] [llvm] r89295 - /llvm/trunk/test/CodeGen/X86/unaligned-load.ll Message-ID: <200911190133.nAJ1XvIY026278@zion.cs.uiuc.edu> Author: void Date: Wed Nov 18 19:33:57 2009 New Revision: 89295 URL: http://llvm.org/viewvc/llvm-project?rev=89295&view=rev Log: Test from Dhrystone to make sure that we're not emitting an aligned load for a string that's aligned at 8-bytes instead of 16-bytes. Added: llvm/trunk/test/CodeGen/X86/unaligned-load.ll Added: llvm/trunk/test/CodeGen/X86/unaligned-load.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/unaligned-load.ll?rev=89295&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/unaligned-load.ll (added) +++ llvm/trunk/test/CodeGen/X86/unaligned-load.ll Wed Nov 18 19:33:57 2009 @@ -0,0 +1,28 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=dynamic-no-pic | not grep {movaps\t_.str3} +; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=dynamic-no-pic | FileCheck %s + + at .str1 = internal constant [31 x i8] c"DHRYSTONE PROGRAM, SOME STRING\00", align 8 + at .str3 = internal constant [31 x i8] c"DHRYSTONE PROGRAM, 2'ND STRING\00", align 8 + +define void @func() nounwind ssp { +entry: + %String2Loc = alloca [31 x i8], align 1 + br label %bb + +bb: + %String2Loc9 = getelementptr inbounds [31 x i8]* %String2Loc, i64 0, i64 0 + call void @llvm.memcpy.i64(i8* %String2Loc9, i8* getelementptr inbounds ([31 x i8]* @.str3, i64 0, i64 0), i64 31, i32 1) +; CHECK: movups _.str3 + br label %bb + +return: + ret void +} + +declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind + +; CHECK: .align 3 +; CHECK-NEXT: _.str1: +; CHECK-NEXT: .asciz "DHRYSTONE PROGRAM, SOME STRING" +; CHECK-NEXT: .align 3 +; CHECK-NEXT: _.str3: From grosbach at apple.com Wed Nov 18 20:02:10 2009 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 19 Nov 2009 02:02:10 -0000 Subject: [llvm-commits] [llvm] r89297 - in /llvm/trunk: include/llvm/Transforms/Utils/Local.h lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <200911190202.nAJ22ACR027438@zion.cs.uiuc.edu> Author: grosbach Date: Wed Nov 18 20:02:10 2009 New Revision: 89297 URL: http://llvm.org/viewvc/llvm-project?rev=89297&view=rev Log: Make EliminateDuplicatePHINodes() available as a utility function Modified: llvm/trunk/include/llvm/Transforms/Utils/Local.h llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/include/llvm/Transforms/Utils/Local.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/Local.h?rev=89297&r1=89296&r2=89297&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Utils/Local.h (original) +++ llvm/trunk/include/llvm/Transforms/Utils/Local.h Wed Nov 18 20:02:10 2009 @@ -107,7 +107,14 @@ /// rewriting all the predecessors to branch to the successor block and return /// true. If we can't transform, return false. bool TryToSimplifyUncondBranchFromEmptyBlock(BasicBlock *BB); - + +/// EliminateDuplicatePHINodes - Check for and eliminate duplicate PHI +/// nodes in this block. This doesn't try to be clever about PHI nodes +/// which differ only in the order of the incoming values, but instcombine +/// orders them so it usually won't matter. +/// +bool EliminateDuplicatePHINodes(BasicBlock *BB); + /// SimplifyCFG - This function is used to do simplification of a CFG. For /// example, it adjusts branches to branches to eliminate the extra hop, it /// eliminates unreachable basic blocks, and does other "peephole" optimization Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=89297&r1=89296&r2=89297&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed Nov 18 20:02:10 2009 @@ -1594,7 +1594,7 @@ /// which differ only in the order of the incoming values, but instcombine /// orders them so it usually won't matter. /// -static bool EliminateDuplicatePHINodes(BasicBlock *BB) { +bool llvm::EliminateDuplicatePHINodes(BasicBlock *BB) { bool Changed = false; // This implementation doesn't currently consider undef operands From grosbach at apple.com Wed Nov 18 20:03:18 2009 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 19 Nov 2009 02:03:18 -0000 Subject: [llvm-commits] [llvm] r89298 - /llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Message-ID: <200911190203.nAJ23IAK027479@zion.cs.uiuc.edu> Author: grosbach Date: Wed Nov 18 20:03:18 2009 New Revision: 89298 URL: http://llvm.org/viewvc/llvm-project?rev=89298&view=rev Log: Eliminate duplicate phi nodes in loops. Loop rotation, for example, can introduce these, and it's beneficial to later passes to clean them up. Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp?rev=89298&r1=89297&r2=89298&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Wed Nov 18 20:03:18 2009 @@ -305,6 +305,12 @@ } } + // If there are duplicate phi nodes (for example, from loop rotation), + // get rid of them. + for (Loop::block_iterator BB = L->block_begin(), E = L->block_end(); + BB != E; ++BB) + EliminateDuplicatePHINodes(*BB); + return Changed; } From grosbach at apple.com Wed Nov 18 20:05:44 2009 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 19 Nov 2009 02:05:44 -0000 Subject: [llvm-commits] [llvm] r89299 - /llvm/trunk/lib/Analysis/IVUsers.cpp Message-ID: <200911190205.nAJ25iBN027598@zion.cs.uiuc.edu> Author: grosbach Date: Wed Nov 18 20:05:44 2009 New Revision: 89299 URL: http://llvm.org/viewvc/llvm-project?rev=89299&view=rev Log: Teach IVUsers to keep things simpler and track loop-invariant strides only for uses inside the loop. This works better with LSR. Disabled behind -simplify-iv-users while benchmarking. Modified: llvm/trunk/lib/Analysis/IVUsers.cpp Modified: llvm/trunk/lib/Analysis/IVUsers.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IVUsers.cpp?rev=89299&r1=89298&r2=89299&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IVUsers.cpp (original) +++ llvm/trunk/lib/Analysis/IVUsers.cpp Wed Nov 18 20:05:44 2009 @@ -24,6 +24,7 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Support/CommandLine.h" #include using namespace llvm; @@ -31,6 +32,10 @@ static RegisterPass X("iv-users", "Induction Variable Users", false, true); +static cl::opt +SimplifyIVUsers("simplify-iv-users", cl::Hidden, cl::init(false), + cl::desc("Restrict IV Users to loop-invariant strides")); + Pass *llvm::createIVUsersPass() { return new IVUsers(); } @@ -208,6 +213,11 @@ if (!getSCEVStartAndStride(ISE, L, UseLoop, Start, Stride, SE, DT)) return false; // Non-reducible symbolic expression, bail out. + // Keep things simple. Don't touch loop-variant strides. + if (SimplifyIVUsers && !Stride->isLoopInvariant(L) + && L->contains(I->getParent())) + return false; + SmallPtrSet UniqueUsers; for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) { From eocallaghan at auroraux.org Wed Nov 18 20:25:50 2009 From: eocallaghan at auroraux.org (Edward O'Callaghan) Date: Thu, 19 Nov 2009 02:25:50 -0000 Subject: [llvm-commits] [llvm] r89301 - in /llvm/trunk/autoconf: config.guess config.sub Message-ID: <200911190225.nAJ2Pop6028344@zion.cs.uiuc.edu> Author: evocallaghan Date: Wed Nov 18 20:25:50 2009 New Revision: 89301 URL: http://llvm.org/viewvc/llvm-project?rev=89301&view=rev Log: autoconf config.* claims to not know about auroraux triple. Modified: llvm/trunk/autoconf/config.guess llvm/trunk/autoconf/config.sub Modified: llvm/trunk/autoconf/config.guess URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/config.guess?rev=89301&r1=89300&r2=89301&view=diff ============================================================================== --- llvm/trunk/autoconf/config.guess (original) +++ llvm/trunk/autoconf/config.guess Wed Nov 18 20:25:50 2009 @@ -333,6 +333,10 @@ sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*) echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit ;; + i86pc:AuroraUX:5.*:* | i86xen:AuroraUX:5.*:*) + AUX_ARCH="i386" + echo ${AUX_ARCH}-pc-auroraux`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*) eval $set_cc_for_build SUN_ARCH="i386" Modified: llvm/trunk/autoconf/config.sub URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/config.sub?rev=89301&r1=89300&r2=89301&view=diff ============================================================================== --- llvm/trunk/autoconf/config.sub (original) +++ llvm/trunk/autoconf/config.sub Wed Nov 18 20:25:50 2009 @@ -1256,6 +1256,9 @@ -solaris1 | -solaris1.*) os=`echo $os | sed -e 's|solaris1|sunos4|'` ;; + -auroraux) + os=-auroraux + ;; -solaris) os=-solaris2 ;; @@ -1274,7 +1277,7 @@ # -sysv* is not here because it comes later, after sysvr4. -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ | -*vms* | -sco* | -esix* | -isc* | -aix* | -cnk* | -sunos | -sunos[34]*\ - | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \ + | -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* | -sym* \ | -kopensolaris* \ | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ | -aos* | -aros* \ From grosbach at apple.com Wed Nov 18 21:09:31 2009 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 19 Nov 2009 03:09:31 -0000 Subject: [llvm-commits] [test-suite] r89302 - /test-suite/trunk/Makefile.programs Message-ID: <200911190309.nAJ39VZu030040@zion.cs.uiuc.edu> Author: grosbach Date: Wed Nov 18 21:09:31 2009 New Revision: 89302 URL: http://llvm.org/viewvc/llvm-project?rev=89302&view=rev Log: llcbeta = simplify-iv-users for ARM and Thumb Modified: test-suite/trunk/Makefile.programs Modified: test-suite/trunk/Makefile.programs URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=89302&r1=89301&r2=89302&view=diff ============================================================================== --- test-suite/trunk/Makefile.programs (original) +++ test-suite/trunk/Makefile.programs Wed Nov 18 21:09:31 2009 @@ -244,11 +244,11 @@ LLCBETAOPTION := -enable-sparc-v9-insts endif ifeq ($(ARCH),ARM) -LLCBETAOPTION := -arm-adjust-jump-tables +LLCBETAOPTION := -simplify-iv-users #-schedule-livein-copies endif ifeq ($(ARCH),THUMB) -LLCBETAOPTION := -arm-adjust-jump-tables +LLCBETAOPTION := -simplify-iv-users #-combiner-alias-analysis #-enable-thumb-reg-scavenging endif From echristo at apple.com Wed Nov 18 21:47:18 2009 From: echristo at apple.com (Eric Christopher) Date: Wed, 18 Nov 2009 19:47:18 -0800 Subject: [llvm-commits] [llvm] r89301 - in /llvm/trunk/autoconf: config.guess config.sub In-Reply-To: <200911190225.nAJ2Pop6028344@zion.cs.uiuc.edu> References: <200911190225.nAJ2Pop6028344@zion.cs.uiuc.edu> Message-ID: On Nov 18, 2009, at 6:25 PM, Edward O'Callaghan wrote: > Log: > autoconf config.* claims to not know about auroraux triple. IMO you should really really put this upstream first if you haven't. It still appears to be version 2 so it shouldn't be a problem to just bring all of config.guess and config.sub down once that's in there. It'll probably help your platform anyhow :) -eric From lhames at gmail.com Wed Nov 18 22:15:33 2009 From: lhames at gmail.com (Lang Hames) Date: Thu, 19 Nov 2009 04:15:33 -0000 Subject: [llvm-commits] [llvm] r89311 - in /llvm/trunk/lib/CodeGen: RegAllocLinearScan.cpp Spiller.cpp Spiller.h Message-ID: <200911190415.nAJ4FXOE032366@zion.cs.uiuc.edu> Author: lhames Date: Wed Nov 18 22:15:33 2009 New Revision: 89311 URL: http://llvm.org/viewvc/llvm-project?rev=89311&view=rev Log: Added a new Spiller implementation which wraps LiveIntervals::addIntervalsForSpills. All spiller calls in RegAllocLinearScan now go through the new Spiller interface. The "-new-spill-framework" command line option has been removed. To use the trivial in-place spiller you should now pass "-spiller=trivial -rewriter=trivial". (Note the trivial spiller/rewriter are only meant to serve as examples of the new in-place modification work. Enabling them will yield terrible, though hopefully functional, code). Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp llvm/trunk/lib/CodeGen/Spiller.cpp llvm/trunk/lib/CodeGen/Spiller.h Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=89311&r1=89310&r2=89311&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Nov 18 22:15:33 2009 @@ -59,11 +59,6 @@ cl::desc("Pre-register allocation live interval splitting"), cl::init(false), cl::Hidden); -static cl::opt -NewSpillFramework("new-spill-framework", - cl::desc("New spilling framework"), - cl::init(false), cl::Hidden); - static RegisterRegAlloc linearscanRegAlloc("linearscan", "linear scan register allocator", createLinearScanRegisterAllocator); @@ -441,9 +436,7 @@ vrm_ = &getAnalysis(); if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter()); - if (NewSpillFramework) { - spiller_.reset(createSpiller(mf_, li_, ls_, vrm_)); - } + spiller_.reset(createSpiller(mf_, li_, ls_, loopInfo, vrm_)); initIntervalSets(); @@ -1157,11 +1150,7 @@ SmallVector spillIs; std::vector added; - if (!NewSpillFramework) { - added = li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_); - } else { - added = spiller_->spill(cur); - } + added = spiller_->spill(cur, spillIs); std::sort(added.begin(), added.end(), LISorter()); addStackInterval(cur, ls_, li_, mri_, *vrm_); @@ -1241,11 +1230,7 @@ earliestStartInterval : sli; std::vector newIs; - if (!NewSpillFramework) { - newIs = li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_); - } else { - newIs = spiller_->spill(sli); - } + newIs = spiller_->spill(sli, spillIs); addStackInterval(sli, ls_, li_, mri_, *vrm_); std::copy(newIs.begin(), newIs.end(), std::back_inserter(added)); spilled.insert(sli->reg); Modified: llvm/trunk/lib/CodeGen/Spiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=89311&r1=89310&r2=89311&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Spiller.cpp (original) +++ llvm/trunk/lib/CodeGen/Spiller.cpp Wed Nov 18 22:15:33 2009 @@ -18,11 +18,25 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; +namespace { + enum SpillerName { trivial, standard }; +} + +static cl::opt +spillerOpt("spiller", + cl::desc("Spiller to use: (default: standard)"), + cl::Prefix, + cl::values(clEnumVal(trivial, "trivial spiller"), + clEnumVal(standard, "default spiller"), + clEnumValEnd), + cl::init(standard)); + Spiller::~Spiller() {} namespace { @@ -156,18 +170,45 @@ public: TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls, - VirtRegMap *vrm) : - SpillerBase(mf, lis, ls, vrm) {} + VirtRegMap *vrm) + : SpillerBase(mf, lis, ls, vrm) {} - std::vector spill(LiveInterval *li) { + std::vector spill(LiveInterval *li, + SmallVectorImpl &spillIs) { + // Ignore spillIs - we don't use it. return trivialSpillEverywhere(li); } }; +/// Falls back on LiveIntervals::addIntervalsForSpills. +class StandardSpiller : public Spiller { +private: + LiveIntervals *lis; + const MachineLoopInfo *loopInfo; + VirtRegMap *vrm; +public: + StandardSpiller(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls, + const MachineLoopInfo *loopInfo, VirtRegMap *vrm) + : lis(lis), loopInfo(loopInfo), vrm(vrm) {} + + /// Falls back on LiveIntervals::addIntervalsForSpills. + std::vector spill(LiveInterval *li, + SmallVectorImpl &spillIs) { + return lis->addIntervalsForSpills(*li, spillIs, loopInfo, *vrm); + } + +}; + } llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis, - LiveStacks *ls, VirtRegMap *vrm) { - return new TrivialSpiller(mf, lis, ls, vrm); + LiveStacks *ls, + const MachineLoopInfo *loopInfo, + VirtRegMap *vrm) { + switch (spillerOpt) { + case trivial: return new TrivialSpiller(mf, lis, ls, vrm); break; + case standard: return new StandardSpiller(mf, lis, ls, loopInfo, vrm); break; + default: llvm_unreachable("Unreachable!"); break; + } } Modified: llvm/trunk/lib/CodeGen/Spiller.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.h?rev=89311&r1=89310&r2=89311&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Spiller.h (original) +++ llvm/trunk/lib/CodeGen/Spiller.h Wed Nov 18 22:15:33 2009 @@ -10,6 +10,7 @@ #ifndef LLVM_CODEGEN_SPILLER_H #define LLVM_CODEGEN_SPILLER_H +#include "llvm/ADT/SmallVector.h" #include namespace llvm { @@ -19,6 +20,7 @@ class LiveStacks; class MachineFunction; class MachineInstr; + class MachineLoopInfo; class VirtRegMap; class VNInfo; @@ -32,13 +34,15 @@ /// Spill the given live range. The method used will depend on the Spiller /// implementation selected. - virtual std::vector spill(LiveInterval *li) = 0; + virtual std::vector spill(LiveInterval *li, + SmallVectorImpl &spillIs) = 0; }; /// Create and return a spiller object, as specified on the command line. Spiller* createSpiller(MachineFunction *mf, LiveIntervals *li, - LiveStacks *ls, VirtRegMap *vrm); + LiveStacks *ls, const MachineLoopInfo *loopInfo, + VirtRegMap *vrm); } #endif From bruno.cardoso at gmail.com Wed Nov 18 23:28:18 2009 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 19 Nov 2009 05:28:18 -0000 Subject: [llvm-commits] [llvm] r89316 - /llvm/trunk/lib/Target/Mips/MipsTargetObjectFile.cpp Message-ID: <200911190528.nAJ5SIMA002198@zion.cs.uiuc.edu> Author: bruno Date: Wed Nov 18 23:28:18 2009 New Revision: 89316 URL: http://llvm.org/viewvc/llvm-project?rev=89316&view=rev Log: Only use small sections for non linux targets! Modified: llvm/trunk/lib/Target/Mips/MipsTargetObjectFile.cpp Modified: llvm/trunk/lib/Target/Mips/MipsTargetObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetObjectFile.cpp?rev=89316&r1=89315&r2=89316&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetObjectFile.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetObjectFile.cpp Wed Nov 18 23:28:18 2009 @@ -8,6 +8,7 @@ //===----------------------------------------------------------------------===// #include "MipsTargetObjectFile.h" +#include "MipsSubtarget.h" #include "llvm/DerivedTypes.h" #include "llvm/GlobalVariable.h" #include "llvm/MC/MCSectionELF.h" @@ -56,6 +57,12 @@ bool MipsTargetObjectFile:: IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM, SectionKind Kind) const { + + // Only use small section for non linux targets. + const MipsSubtarget &Subtarget = TM.getSubtarget(); + if (Subtarget.isLinux()) + return false; + // Only global variables, not functions. const GlobalVariable *GVA = dyn_cast(GV); if (!GVA) From evan.cheng at apple.com Wed Nov 18 23:32:45 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 18 Nov 2009 21:32:45 -0800 Subject: [llvm-commits] [test-suite] r89302 - /test-suite/trunk/Makefile.programs In-Reply-To: <200911190309.nAJ39VZu030040@zion.cs.uiuc.edu> References: <200911190309.nAJ39VZu030040@zion.cs.uiuc.edu> Message-ID: <4CE1AABC-90E0-4886-B5DB-1B25894F7706@apple.com> x86 as well please. Evan On Nov 18, 2009, at 7:09 PM, Jim Grosbach wrote: > Author: grosbach > Date: Wed Nov 18 21:09:31 2009 > New Revision: 89302 > > URL: http://llvm.org/viewvc/llvm-project?rev=89302&view=rev > Log: > llcbeta = simplify-iv-users for ARM and Thumb > > Modified: > test-suite/trunk/Makefile.programs > > Modified: test-suite/trunk/Makefile.programs > URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=89302&r1=89301&r2=89302&view=diff > > ============================================================================== > --- test-suite/trunk/Makefile.programs (original) > +++ test-suite/trunk/Makefile.programs Wed Nov 18 21:09:31 2009 > @@ -244,11 +244,11 @@ > LLCBETAOPTION := -enable-sparc-v9-insts > endif > ifeq ($(ARCH),ARM) > -LLCBETAOPTION := -arm-adjust-jump-tables > +LLCBETAOPTION := -simplify-iv-users > #-schedule-livein-copies > endif > ifeq ($(ARCH),THUMB) > -LLCBETAOPTION := -arm-adjust-jump-tables > +LLCBETAOPTION := -simplify-iv-users > #-combiner-alias-analysis > #-enable-thumb-reg-scavenging > endif > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bruno.cardoso at gmail.com Thu Nov 19 00:06:14 2009 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 19 Nov 2009 06:06:14 -0000 Subject: [llvm-commits] [llvm] r89322 - in /llvm/trunk: lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsRegisterInfo.h lib/Target/Mips/MipsRegisterInfo.td test/CodeGen/Mips/2008-08-03-ReturnDouble.ll Message-ID: <200911190606.nAJ66ER8003651@zion.cs.uiuc.edu> Author: bruno Date: Thu Nov 19 00:06:13 2009 New Revision: 89322 URL: http://llvm.org/viewvc/llvm-project?rev=89322&view=rev Log: - Add sugregister logic to handle f64=(f32,f32). - Support mips1 like load/store of doubles: Instead of: sdc $f0, X($3) Generate: swc $f0, X($3) swc $f1, X+4($3) Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td llvm/trunk/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll Modified: llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=89322&r1=89321&r2=89322&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Thu Nov 19 00:06:13 2009 @@ -365,6 +365,8 @@ case MachineOperand::MO_ConstantPoolIndex: O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_" << MO.getIndex(); + if (MO.getOffset()) + O << "+" << MO.getOffset(); break; default: Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=89322&r1=89321&r2=89322&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Nov 19 00:06:13 2009 @@ -90,6 +90,8 @@ bool SelectAddr(SDValue Op, SDValue N, SDValue &Base, SDValue &Offset); + SDNode *SelectLoadFp64(SDValue N); + SDNode *SelectStoreFp64(SDValue N); // getI32Imm - Return a target constant with the specified // value, of type i32. @@ -198,6 +200,121 @@ return true; } +SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDValue N) { + MVT::SimpleValueType NVT = + N.getNode()->getValueType(0).getSimpleVT().SimpleTy; + + if (!Subtarget.isMips1() || NVT != MVT::f64) + return NULL; + + if (!Predicate_unindexedload(N.getNode()) || + !Predicate_load(N.getNode())) + return NULL; + + SDValue Chain = N.getOperand(0); + SDValue N1 = N.getOperand(1); + SDValue Offset0, Offset1, Base; + + if (!SelectAddr(N, N1, Offset0, Base) || + N1.getValueType() != MVT::i32) + return NULL; + + MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1); + MemRefs0[0] = cast(N)->getMemOperand(); + DebugLoc dl = N.getDebugLoc(); + + // The second load should start after for 4 bytes. + if (ConstantSDNode *C = dyn_cast(Offset0)) + Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32); + else if (ConstantPoolSDNode *CP = dyn_cast(Offset0)) + Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(), + MVT::i32, + CP->getAlignment(), + CP->getOffset()+4, + CP->getTargetFlags()); + else + return NULL; + + // Instead of: + // ldc $f0, X($3) + // Generate: + // lwc $f0, X($3) + // lwc $f1, X+4($3) + SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32, + MVT::Other, Offset0, Base, Chain); + SDValue Undef = SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF, + dl, NVT), 0); + SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPEVEN, dl, + MVT::f64, Undef, SDValue(LD0, 0)); + + SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32, + MVT::Other, Offset1, Base, SDValue(LD0, 1)); + SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPODD, dl, + MVT::f64, I0, SDValue(LD1, 0)); + + ReplaceUses(N, I1); + ReplaceUses(N.getValue(1), Chain); + cast(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1); + cast(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1); + return I1.getNode(); +} + +SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDValue N) { + + if (!Subtarget.isMips1() || + N.getOperand(1).getValueType() != MVT::f64) + return NULL; + + SDValue Chain = N.getOperand(0); + + if (!Predicate_unindexedstore(N.getNode()) || + !Predicate_store(N.getNode())) + return NULL; + + SDValue N1 = N.getOperand(1); + SDValue N2 = N.getOperand(2); + SDValue Offset0, Offset1, Base; + + if (!SelectAddr(N, N2, Offset0, Base) || + N1.getValueType() != MVT::f64 || + N2.getValueType() != MVT::i32) + return NULL; + + MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1); + MemRefs0[0] = cast(N)->getMemOperand(); + DebugLoc dl = N.getDebugLoc(); + + // Get the even and odd part from the f64 register + SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::SUBREG_FPODD, + dl, MVT::f32, N1); + SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::SUBREG_FPEVEN, + dl, MVT::f32, N1); + + // The second store should start after for 4 bytes. + if (ConstantSDNode *C = dyn_cast(Offset0)) + Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32); + else + return NULL; + + // Instead of: + // sdc $f0, X($3) + // Generate: + // swc $f0, X($3) + // swc $f1, X+4($3) + SDValue Ops0[] = { FPEven, Offset0, Base, Chain }; + Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl, + MVT::Other, Ops0, 4), 0); + cast(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1); + + SDValue Ops1[] = { FPOdd, Offset1, Base, Chain }; + Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl, + MVT::Other, Ops1, 4), 0); + cast(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1); + + ReplaceUses(N.getValue(0), Chain); + return Chain.getNode(); +} + /// Select instructions not customized! Used for /// expanded, promoted and normal instructions SDNode* MipsDAGToDAGISel::Select(SDValue N) { @@ -345,6 +462,18 @@ break; } + case ISD::LOAD: + if (SDNode *ResNode = SelectLoadFp64(N)) + return ResNode; + // Other cases are autogenerated. + break; + + case ISD::STORE: + if (SDNode *ResNode = SelectStoreFp64(N)) + return ResNode; + // Other cases are autogenerated. + break; + /// Handle direct and indirect calls when using PIC. On PIC, when /// GOT is smaller than about 64k (small code) the GA target is /// loaded with only one instruction. Otherwise GA's target must Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h?rev=89322&r1=89321&r2=89322&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h Thu Nov 19 00:06:13 2009 @@ -23,6 +23,15 @@ class TargetInstrInfo; class Type; +namespace Mips { + /// SubregIndex - The index of various sized subregister classes. Note that + /// these indices must be kept in sync with the class indices in the + /// MipsRegisterInfo.td file. + enum SubregIndex { + SUBREG_FPEVEN = 1, SUBREG_FPODD = 2 + }; +} + struct MipsRegisterInfo : public MipsGenRegisterInfo { const MipsSubtarget &Subtarget; const TargetInstrInfo &TII; Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=89322&r1=89321&r2=89322&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Thu Nov 19 00:06:13 2009 @@ -17,6 +17,12 @@ let Namespace = "Mips"; } +class MipsRegWithSubRegs subregs> + : RegisterWithSubRegs { + field bits<5> Num; + let Namespace = "Mips"; +} + // Mips CPU Registers class MipsGPRReg num, string n> : MipsReg { let Num = num; @@ -28,9 +34,9 @@ } // Mips 64-bit (aliased) FPU Registers -class AFPR num, string n, list aliases> : MipsReg { +class AFPR num, string n, list subregs> + : MipsRegWithSubRegs { let Num = num; - let Aliases = aliases; } //===----------------------------------------------------------------------===// @@ -135,6 +141,23 @@ } //===----------------------------------------------------------------------===// +// Subregister Set Definitions +//===----------------------------------------------------------------------===// + +def mips_subreg_fpeven : PatLeaf<(i32 1)>; +def mips_subreg_fpodd : PatLeaf<(i32 2)>; + +def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7, + D8, D9, D10, D11, D12, D13, D14, D15], + [F0, F2, F4, F6, F8, F10, F12, F14, + F16, F18, F20, F22, F24, F26, F28, F30]>; + +def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7, + D8, D9, D10, D11, D12, D13, D14, D15], + [F1, F3, F5, F7, F9, F11, F13, F15, + F17, F19, F21, F23, F25, F27, F29, F31]>; + +//===----------------------------------------------------------------------===// // Register Classes //===----------------------------------------------------------------------===// @@ -232,6 +255,7 @@ // Reserved D15]> { + let SubRegClassList = [FGR32, FGR32]; let MethodProtos = [{ iterator allocation_order_end(const MachineFunction &MF) const; }]; Modified: llvm/trunk/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll?rev=89322&r1=89321&r2=89322&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll Thu Nov 19 00:06:13 2009 @@ -1,7 +1,6 @@ ; Double return in abicall (default) -; RUN: llc < %s -march=mips +; RUN: llc < %s -march=mips | FileCheck %s ; PR2615 -; XFAIL: * define double @main(...) { entry: From evan.cheng at apple.com Thu Nov 19 00:31:27 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 19 Nov 2009 06:31:27 -0000 Subject: [llvm-commits] [llvm] r89325 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Message-ID: <200911190631.nAJ6VRCZ004551@zion.cs.uiuc.edu> Author: evancheng Date: Thu Nov 19 00:31:26 2009 New Revision: 89325 URL: http://llvm.org/viewvc/llvm-project?rev=89325&view=rev Log: Eliminate more * 4 in Thumb1 asm printing for consistency sake. Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=89325&r1=89324&r2=89325&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Thu Nov 19 00:31:26 2009 @@ -713,7 +713,7 @@ if (MO3.getReg()) O << ", " << getRegisterName(MO3.getReg()); else if (unsigned ImmOffs = MO2.getImm()) - O << ", #" << ImmOffs * Scale; + O << ", #+" << ImmOffs * Scale; O << "]"; } @@ -735,7 +735,7 @@ const MachineOperand &MO2 = MI->getOperand(Op+1); O << "[" << getRegisterName(MO1.getReg()); if (unsigned ImmOffs = MO2.getImm()) - O << ", #" << ImmOffs << " * 4"; + O << ", #+" << ImmOffs*4; O << "]"; } @@ -801,9 +801,9 @@ int32_t OffImm = (int32_t)MO2.getImm() / 4; // Don't print +0. if (OffImm < 0) - O << ", #-" << -OffImm << " * 4"; + O << ", #-" << -OffImm * 4; else if (OffImm > 0) - O << ", #+" << OffImm << " * 4"; + O << ", #+" << OffImm * 4; O << "]"; } From evan.cheng at apple.com Thu Nov 19 00:32:27 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 19 Nov 2009 06:32:27 -0000 Subject: [llvm-commits] [llvm] r89326 - in /llvm/trunk: lib/Target/ARM/Thumb2SizeReduction.cpp test/CodeGen/Thumb2/ldr-str-imm12.ll Message-ID: <200911190632.nAJ6WRDf004593@zion.cs.uiuc.edu> Author: evancheng Date: Thu Nov 19 00:32:27 2009 New Revision: 89326 URL: http://llvm.org/viewvc/llvm-project?rev=89326&view=rev Log: Shrink ldr / str [sp, imm0-1024] to 16-bit instructions. Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=89326&r1=89325&r2=89326&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Thu Nov 19 00:32:27 2009 @@ -105,7 +105,7 @@ // FIXME: Clean this up after splitting each Thumb load / store opcode // into multiple ones. - { ARM::t2LDRi12,ARM::tLDR, 0, 5, 0, 1, 0, 0,0, 1 }, + { ARM::t2LDRi12,ARM::tLDR, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 1 }, { ARM::t2LDRs, ARM::tLDR, 0, 0, 0, 1, 0, 0,0, 1 }, { ARM::t2LDRBi12,ARM::tLDRB, 0, 5, 0, 1, 0, 0,0, 1 }, { ARM::t2LDRBs, ARM::tLDRB, 0, 0, 0, 1, 0, 0,0, 1 }, @@ -113,7 +113,7 @@ { ARM::t2LDRHs, ARM::tLDRH, 0, 0, 0, 1, 0, 0,0, 1 }, { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 1 }, { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 1 }, - { ARM::t2STRi12,ARM::tSTR, 0, 5, 0, 1, 0, 0,0, 1 }, + { ARM::t2STRi12,ARM::tSTR, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 1 }, { ARM::t2STRs, ARM::tSTR, 0, 0, 0, 1, 0, 0,0, 1 }, { ARM::t2STRBi12,ARM::tSTRB, 0, 5, 0, 1, 0, 0,0, 1 }, { ARM::t2STRBs, ARM::tSTRB, 0, 0, 0, 1, 0, 0,0, 1 }, @@ -244,8 +244,13 @@ continue; if (isLROk && Reg == ARM::LR) continue; - if (isSPOk && Reg == ARM::SP) - continue; + if (Reg == ARM::SP) { + if (isSPOk) + continue; + if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12)) + // Special case for these ldr / str with sp as base register. + continue; + } if (!isARMLowRegister(Reg)) return false; } @@ -261,17 +266,26 @@ unsigned Scale = 1; bool HasImmOffset = false; bool HasShift = false; + bool HasOffReg = true; bool isLdStMul = false; unsigned Opc = Entry.NarrowOpc1; unsigned OpNum = 3; // First 'rest' of operands. + uint8_t ImmLimit = Entry.Imm1Limit; switch (Entry.WideOpc) { default: llvm_unreachable("Unexpected Thumb2 load / store opcode!"); case ARM::t2LDRi12: - case ARM::t2STRi12: + case ARM::t2STRi12: { + unsigned BaseReg = MI->getOperand(1).getReg(); + if (BaseReg == ARM::SP) { + Opc = Entry.NarrowOpc2; + ImmLimit = Entry.Imm2Limit; + HasOffReg = false; + } Scale = 4; HasImmOffset = true; break; + } case ARM::t2LDRBi12: case ARM::t2STRBi12: HasImmOffset = true; @@ -325,7 +339,7 @@ unsigned OffsetImm = 0; if (HasImmOffset) { OffsetImm = MI->getOperand(2).getImm(); - unsigned MaxOffset = ((1 << Entry.Imm1Limit) - 1) * Scale; + unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale; if ((OffsetImm & (Scale-1)) || OffsetImm > MaxOffset) // Make sure the immediate field fits. return false; @@ -337,7 +351,7 @@ MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc)); if (!isLdStMul) { MIB.addOperand(MI->getOperand(0)).addOperand(MI->getOperand(1)); - if (Entry.NarrowOpc1 != ARM::tLDRSB && Entry.NarrowOpc1 != ARM::tLDRSH) { + if (Opc != ARM::tLDRSB && Opc != ARM::tLDRSH) { // tLDRSB and tLDRSH do not have an immediate offset field. On the other // hand, it must have an offset register. // FIXME: Remove this special case. @@ -345,13 +359,17 @@ } assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); - MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); + if (HasOffReg) + MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); } // Transfer the rest of operands. for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum) MIB.addOperand(MI->getOperand(OpNum)); + // Transfer memoperands. + (*MIB).setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); + DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); MBB.erase(MI); Modified: llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll?rev=89326&r1=89325&r2=89326&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll Thu Nov 19 00:32:27 2009 @@ -49,6 +49,12 @@ unreachable bb420: ; preds = %bb20, %bb20 +; CHECK: bb420 +; CHECK: str r{{[0-7]}}, [sp] +; CHECK: str r{{[0-7]}}, [sp, #+4] +; CHECK: str r{{[0-7]}}, [sp, #+8] +; CHECK: ldr r{{[0-7]}}, [sp, #+28] +; CHECK: str r{{[0-7]}}, [sp, #+24] store %union.rec* null, %union.rec** @zz_hold, align 4 store %union.rec* null, %union.rec** @zz_res, align 4 store %union.rec* %x, %union.rec** @zz_hold, align 4 From evan.cheng at apple.com Thu Nov 19 00:57:41 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 19 Nov 2009 06:57:41 -0000 Subject: [llvm-commits] [llvm] r89328 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.h test/CodeGen/Thumb/pop.ll test/CodeGen/Thumb2/2009-07-21-ISelBug.ll test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll test/CodeGen/Thumb2/large-stack.ll Message-ID: <200911190657.nAJ6vfhV005402@zion.cs.uiuc.edu> Author: evancheng Date: Thu Nov 19 00:57:41 2009 New Revision: 89328 URL: http://llvm.org/viewvc/llvm-project?rev=89328&view=rev Log: More consistent thumb1 asm printing. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h llvm/trunk/test/CodeGen/Thumb/pop.ll llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll llvm/trunk/test/CodeGen/Thumb2/large-stack.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=89328&r1=89327&r2=89328&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Nov 19 00:57:41 2009 @@ -66,6 +66,11 @@ return CurDAG->getTargetConstant(V, MVT::i32); }]>; +// Scaled 4 immediate. +def t_imm_s4 : Operand { + let PrintMethod = "printThumbS4ImmOperand"; +} + // Define Thumb specific addressing modes. // t_addrmode_rr := reg + reg @@ -134,20 +139,20 @@ [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>; // PC relative add. -def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), IIC_iALUi, - "add\t$dst, pc, $rhs * 4", []>; +def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi, + "add\t$dst, pc, $rhs", []>; // ADD rd, sp, #imm8 -def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), IIC_iALUi, - "add\t$dst, $sp, $rhs * 4", []>; +def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi, + "add\t$dst, $sp, $rhs", []>; // ADD sp, sp, #imm7 -def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi, - "add\t$dst, $rhs * 4", []>; +def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, + "add\t$dst, $rhs", []>; // SUB sp, sp, #imm7 -def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi, - "sub\t$dst, $rhs * 4", []>; +def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, + "sub\t$dst, $rhs", []>; // ADD rm, sp def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, @@ -159,8 +164,8 @@ // Pseudo instruction that will expand into a tSUBspi + a copy. let usesCustomInserter = 1 in { // Expanded after instruction selection. -def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), - NoItinerary, "@ sub\t$dst, $rhs * 4", []>; +def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), + NoItinerary, "@ sub\t$dst, $rhs", []>; def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), NoItinerary, "@ add\t$dst, $rhs", []>; Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=89328&r1=89327&r2=89328&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Thu Nov 19 00:57:41 2009 @@ -110,6 +110,7 @@ const char *Modifier = 0); void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum); + void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum); void printThumbITMask(const MachineInstr *MI, int OpNum); void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum); void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum, @@ -674,6 +675,10 @@ //===--------------------------------------------------------------------===// +void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) { + O << "#" << MI->getOperand(Op).getImm() * 4; +} + void ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) { // (3 - the number of trailing zeros) is the number of then / else. Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=89328&r1=89327&r2=89328&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Thu Nov 19 00:57:41 2009 @@ -351,3 +351,8 @@ // FIXME: remove this. abort(); } + +void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum) { + // FIXME: remove this. + abort(); +} Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h?rev=89328&r1=89327&r2=89328&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h Thu Nov 19 00:57:41 2009 @@ -52,7 +52,8 @@ const char *Modifier = 0); void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum); - + + void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum); void printThumbITMask(const MCInst *MI, unsigned OpNum) {} void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum) {} void printThumbAddrModeRI5Operand(const MCInst *MI, unsigned OpNum, Modified: llvm/trunk/test/CodeGen/Thumb/pop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/pop.ll?rev=89328&r1=89327&r2=89328&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/pop.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/pop.ll Thu Nov 19 00:57:41 2009 @@ -4,7 +4,7 @@ define arm_apcscc void @t(i8* %a, ...) nounwind { ; CHECK: t: ; CHECK: pop {r3} -; CHECK-NEXT: add sp, #3 * 4 +; CHECK-NEXT: add sp, #12 ; CHECK-NEXT: bx r3 entry: %a.addr = alloca i8* Modified: llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll?rev=89328&r1=89327&r2=89328&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll Thu Nov 19 00:57:41 2009 @@ -6,7 +6,7 @@ define arm_apcscc i32 @t(i32, ...) nounwind { entry: ; CHECK: t: -; CHECK: add r7, sp, #3 * 4 +; CHECK: add r7, sp, #12 %1 = load i8** undef, align 4 ; [#uses=3] %2 = getelementptr i8* %1, i32 4 ; [#uses=1] %3 = getelementptr i8* %1, i32 8 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll?rev=89328&r1=89327&r2=89328&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll Thu Nov 19 00:57:41 2009 @@ -6,7 +6,7 @@ entry: ; CHECK: __gcov_execlp: ; CHECK: mov sp, r7 -; CHECK: sub sp, #1 * 4 +; CHECK: sub sp, #4 call arm_aapcscc void @__gcov_flush() nounwind br i1 undef, label %bb5, label %bb Modified: llvm/trunk/test/CodeGen/Thumb2/large-stack.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/large-stack.ll?rev=89328&r1=89327&r2=89328&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/large-stack.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/large-stack.ll Thu Nov 19 00:57:41 2009 @@ -2,7 +2,7 @@ define void @test1() { ; CHECK: test1: -; CHECK: sub sp, #64 * 4 +; CHECK: sub sp, #256 %tmp = alloca [ 64 x i32 ] , align 4 ret void } @@ -10,7 +10,7 @@ define void @test2() { ; CHECK: test2: ; CHECK: sub.w sp, sp, #4160 -; CHECK: sub sp, #2 * 4 +; CHECK: sub sp, #8 %tmp = alloca [ 4168 x i8 ] , align 4 ret void } @@ -18,7 +18,7 @@ define i32 @test3() { ; CHECK: test3: ; CHECK: sub.w sp, sp, #805306368 -; CHECK: sub sp, #6 * 4 +; CHECK: sub sp, #24 %retval = alloca i32, align 4 %tmp = alloca i32, align 4 %a = alloca [805306369 x i8], align 16 From daniel at zuster.org Thu Nov 19 01:18:49 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 19 Nov 2009 07:18:49 -0000 Subject: [llvm-commits] [llvm] r89329 - /llvm/trunk/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll Message-ID: <200911190718.nAJ7IoAM006116@zion.cs.uiuc.edu> Author: ddunbar Date: Thu Nov 19 01:18:49 2009 New Revision: 89329 URL: http://llvm.org/viewvc/llvm-project?rev=89329&view=rev Log: Unbreak test, Bruno please check. Modified: llvm/trunk/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll Modified: llvm/trunk/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll?rev=89329&r1=89328&r2=89329&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll Thu Nov 19 01:18:49 2009 @@ -1,5 +1,5 @@ ; Double return in abicall (default) -; RUN: llc < %s -march=mips | FileCheck %s +; RUN: llc < %s -march=mips ; PR2615 define double @main(...) { From evan.cheng at apple.com Thu Nov 19 02:16:50 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 19 Nov 2009 08:16:50 -0000 Subject: [llvm-commits] [llvm] r89337 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Message-ID: <200911190816.nAJ8Goud007995@zion.cs.uiuc.edu> Author: evancheng Date: Thu Nov 19 02:16:50 2009 New Revision: 89337 URL: http://llvm.org/viewvc/llvm-project?rev=89337&view=rev Log: 80 col violation. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=89337&r1=89336&r2=89337&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Nov 19 02:16:50 2009 @@ -1545,7 +1545,8 @@ InFlag = SDValue(ResNode, 1); ReplaceUses(SDValue(Op.getNode(), 1), InFlag); } - ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo())); + ReplaceUses(SDValue(Op.getNode(), 0), + SDValue(Chain.getNode(), Chain.getResNo())); return NULL; } case ARMISD::CMOV: { From grosser at fim.uni-passau.de Thu Nov 19 05:56:26 2009 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 19 Nov 2009 12:56:26 +0100 Subject: [llvm-commits] [patch] CMake: Do not add -ldl, but use CMAKE_DL_LIBS Message-ID: <1258631786.28275.4.camel@tobilaptop.fritz.box> Hi, I just fixed bug http://llvm.org/bugs/show_bug.cgi?id=5536 ---------------------------------------------------------------------------- CMake: Do not add -ldl, but use CMAKE_DL_LIBS This fixes BUILD_SHARED_LIBS on FreeBSD, NetBSD, and all platforms that have dlopen and dlclose in another library. For example in FreeBSD it is in libc. ---------------------------------------------------------------------------- By the way, do I have to send these patches to this mailinglist or is it enough to add them to the bug tracker? Tobi -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-CMake-Do-not-add-ldl-but-use-CMAKE_DL_LIBS.patch Type: text/x-patch Size: 1426 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091119/15660bdb/attachment.bin From eocallaghan at auroraux.org Thu Nov 19 05:59:00 2009 From: eocallaghan at auroraux.org (Edward O'Callaghan) Date: Thu, 19 Nov 2009 11:59:00 -0000 Subject: [llvm-commits] [llvm] r89339 - in /llvm/trunk: include/llvm/ADT/Triple.h lib/Support/Triple.cpp Message-ID: <200911191159.nAJBx1Sp030614@zion.cs.uiuc.edu> Author: evocallaghan Date: Thu Nov 19 05:59:00 2009 New Revision: 89339 URL: http://llvm.org/viewvc/llvm-project?rev=89339&view=rev Log: Add PS3 Triple class, Credit to John Thompson. Modified: llvm/trunk/include/llvm/ADT/Triple.h llvm/trunk/lib/Support/Triple.cpp Modified: llvm/trunk/include/llvm/ADT/Triple.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=89339&r1=89338&r2=89339&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/Triple.h (original) +++ llvm/trunk/include/llvm/ADT/Triple.h Thu Nov 19 05:59:00 2009 @@ -64,7 +64,7 @@ msp430, // MSP430: msp430 pic16, // PIC16: pic16 ppc, // PPC: powerpc - ppc64, // PPC64: powerpc64 + ppc64, // PPC64: powerpc64, ppu sparc, // Sparc: sparc systemz, // SystemZ: s390x tce, // TCE (http://tce.cs.tut.fi/): tce @@ -90,6 +90,7 @@ DragonFly, FreeBSD, Linux, + Lv2, // PS3 MinGW32, MinGW64, NetBSD, Modified: llvm/trunk/lib/Support/Triple.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=89339&r1=89338&r2=89339&view=diff ============================================================================== --- llvm/trunk/lib/Support/Triple.cpp (original) +++ llvm/trunk/lib/Support/Triple.cpp Thu Nov 19 05:59:00 2009 @@ -90,6 +90,7 @@ case DragonFly: return "dragonfly"; case FreeBSD: return "freebsd"; case Linux: return "linux"; + case Lv2: return "lv2"; case MinGW32: return "mingw32"; case MinGW64: return "mingw64"; case NetBSD: return "netbsd"; @@ -227,7 +228,7 @@ Arch = pic16; else if (ArchName == "powerpc") Arch = ppc; - else if (ArchName == "powerpc64") + else if ((ArchName == "powerpc64") || (ArchName == "ppu")) Arch = ppc64; else if (ArchName == "arm" || ArchName.startswith("armv") || @@ -293,6 +294,8 @@ OS = FreeBSD; else if (OSName.startswith("linux")) OS = Linux; + else if (OSName.startswith("lv2")) + OS = Lv2; else if (OSName.startswith("mingw32")) OS = MinGW32; else if (OSName.startswith("mingw64")) From benny.kra at googlemail.com Thu Nov 19 06:17:31 2009 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 19 Nov 2009 12:17:31 -0000 Subject: [llvm-commits] [llvm] r89341 - /llvm/trunk/lib/System/Host.cpp Message-ID: <200911191217.nAJCHVXB031280@zion.cs.uiuc.edu> Author: d0k Date: Thu Nov 19 06:17:31 2009 New Revision: 89341 URL: http://llvm.org/viewvc/llvm-project?rev=89341&view=rev Log: Unbreak x64 MSVC build. Patch by Nicolas Capens! Modified: llvm/trunk/lib/System/Host.cpp Modified: llvm/trunk/lib/System/Host.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Host.cpp?rev=89341&r1=89340&r2=89341&view=diff ============================================================================== --- llvm/trunk/lib/System/Host.cpp (original) +++ llvm/trunk/lib/System/Host.cpp Thu Nov 19 06:17:31 2009 @@ -22,6 +22,9 @@ #ifdef LLVM_ON_WIN32 #include "Win32/Host.inc" #endif +#ifdef _MSC_VER +#include +#endif //===----------------------------------------------------------------------===// // From espindola at google.com Thu Nov 19 09:23:50 2009 From: espindola at google.com (Rafael Espindola) Date: Thu, 19 Nov 2009 10:23:50 -0500 Subject: [llvm-commits] [PATCH] LTO code generator options In-Reply-To: <41BA1AA405BC4D19BA9B4FAB6543D62F@andreic6e7fe55> References: <04F6B1512E264B27AEE607542FCDD113@andreic6e7fe55> <38a0d8450911121059n6a0d3eb0ka34711d931c7675e@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BA@mail.accesssoftek.com> <38a0d8450911141921r7deec8b3k91e06950263f0485@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BF@mail.accesssoftek.com> <38a0d8450911170809j6a32716ar840b8622cfad6f17@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607C4@mail.accesssoftek.com> <38a0d8450911180722j5a463fa8hec81178154deaf09@mail.gmail.com> <41BA1AA405BC4D19BA9B4FAB6543D62F@andreic6e7fe55> Message-ID: <38a0d8450911190723g644ad4c7ife769ab35da9efb9@mail.gmail.com> > This patch adds two SubtargetFeatures::AddFeatures methods which accept a > comma-separated string or already parsed command line parameters as input, > SubtargetFeatures::hasFeature method which cheks?if given feature is already > set, and some code re-factoring to use these new methods. Can you give the StringRef::split method a try? You say features are normalized, why does hasFeature needs to convert to lowercase and strip flags? The comment about "after all explicit feature settings" is a future reference, right? I don't see any feature being set :-) The method SubtargetFeatures::AddFeatures(const cl::list &List) is not being used, is it? > Best regards, > Viktor Cheers, -- Rafael ?vila de Esp?ndola From edwintorok at gmail.com Thu Nov 19 09:39:50 2009 From: edwintorok at gmail.com (Torok Edwin) Date: Thu, 19 Nov 2009 15:39:50 -0000 Subject: [llvm-commits] [llvm] r89352 - /llvm/trunk/include/llvm/ADT/StringRef.h Message-ID: <200911191539.nAJFdpS4006590@zion.cs.uiuc.edu> Author: edwin Date: Thu Nov 19 09:39:50 2009 New Revision: 89352 URL: http://llvm.org/viewvc/llvm-project?rev=89352&view=rev Log: Workaround PR5482, because all the gcc versions that I had were miscompiling StringRef: 4.2.4, 4.3.4, 4.4.2. The workaround is to use a local min/max implementation that takes an integer param, and not a reference to integer param (like std::min does). Modified: llvm/trunk/include/llvm/ADT/StringRef.h Modified: llvm/trunk/include/llvm/ADT/StringRef.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringRef.h?rev=89352&r1=89351&r2=89352&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/StringRef.h (original) +++ llvm/trunk/include/llvm/ADT/StringRef.h Thu Nov 19 09:39:50 2009 @@ -39,6 +39,19 @@ /// The length of the string. size_t Length; + // Workaround PR5482: nearly all gcc 4.x miscompile StringRef and std::min() + // Changing the arg of min to be an integer, instead of a reference to an + // integer works around this bug. + size_t min(size_t a, size_t b) const + { + return a < b ? a : b; + } + + size_t max(size_t a, size_t b) const + { + return a > b ? a : b; + } + public: /// @name Constructors /// @{ @@ -108,7 +121,7 @@ /// is lexicographically less than, equal to, or greater than the \arg RHS. int compare(StringRef RHS) const { // Check the prefix for a mismatch. - if (int Res = memcmp(Data, RHS.Data, std::min(Length, RHS.Length))) + if (int Res = memcmp(Data, RHS.Data, min(Length, RHS.Length))) return Res < 0 ? -1 : 1; // Otherwise the prefixes match, so we only need to check the lengths. @@ -163,7 +176,7 @@ /// \return - The index of the first occurence of \arg C, or npos if not /// found. size_t find(char C, size_t From = 0) const { - for (size_t i = std::min(From, Length), e = Length; i != e; ++i) + for (size_t i = min(From, Length), e = Length; i != e; ++i) if (Data[i] == C) return i; return npos; @@ -180,7 +193,7 @@ /// \return - The index of the last occurence of \arg C, or npos if not /// found. size_t rfind(char C, size_t From = npos) const { - From = std::min(From, Length); + From = min(From, Length); size_t i = From; while (i != 0) { --i; @@ -262,8 +275,8 @@ /// exceeds the number of characters remaining in the string, the string /// suffix (starting with \arg Start) will be returned. StringRef substr(size_t Start, size_t N = npos) const { - Start = std::min(Start, Length); - return StringRef(Data + Start, std::min(N, Length - Start)); + Start = min(Start, Length); + return StringRef(Data + Start, min(N, Length - Start)); } /// slice - Return a reference to the substring from [Start, End). @@ -277,8 +290,8 @@ /// number of characters remaining in the string, the string suffix /// (starting with \arg Start) will be returned. StringRef slice(size_t Start, size_t End) const { - Start = std::min(Start, Length); - End = std::min(std::max(Start, End), Length); + Start = min(Start, Length); + End = min(max(Start, End), Length); return StringRef(Data + Start, End - Start); } From benny.kra at googlemail.com Thu Nov 19 09:48:14 2009 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 19 Nov 2009 15:48:14 -0000 Subject: [llvm-commits] [llvm] r89354 - /llvm/trunk/include/llvm/ADT/StringRef.h Message-ID: <200911191548.nAJFmEFU006914@zion.cs.uiuc.edu> Author: d0k Date: Thu Nov 19 09:48:14 2009 New Revision: 89354 URL: http://llvm.org/viewvc/llvm-project?rev=89354&view=rev Log: Remove the now obsolete algorithm include from StringRef.h. Modified: llvm/trunk/include/llvm/ADT/StringRef.h Modified: llvm/trunk/include/llvm/ADT/StringRef.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringRef.h?rev=89354&r1=89353&r2=89354&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/StringRef.h (original) +++ llvm/trunk/include/llvm/ADT/StringRef.h Thu Nov 19 09:48:14 2009 @@ -10,9 +10,9 @@ #ifndef LLVM_ADT_STRINGREF_H #define LLVM_ADT_STRINGREF_H -#include #include #include +#include #include namespace llvm { From greened at obbligato.org Thu Nov 19 09:55:49 2009 From: greened at obbligato.org (David Greene) Date: Thu, 19 Nov 2009 15:55:49 -0000 Subject: [llvm-commits] [llvm] r89356 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Message-ID: <200911191555.nAJFtnEm007165@zion.cs.uiuc.edu> Author: greened Date: Thu Nov 19 09:55:49 2009 New Revision: 89356 URL: http://llvm.org/viewvc/llvm-project?rev=89356&view=rev Log: Add support for spreading register allocation. Add a -linearscan-skip-count argument (default to 0) that tells the allocator to remember the last N registers it allocated and skip them when looking for a register candidate. This tends to spread out register usage and free up post-allocation scheduling at the cost of slightly more register pressure. The primary benefit is the ability to backschedule reloads. This is turned off by default. Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=89356&r1=89355&r2=89356&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Thu Nov 19 09:55:49 2009 @@ -64,9 +64,30 @@ createLinearScanRegisterAllocator); namespace { + // When we allocate a register, add it to a fixed-size queue of + // registers to skip in subsequent allocations. This trades a small + // amount of register pressure and increased spills for flexibility in + // the post-pass scheduler. + // + // Note that in a the number of registers used for reloading spills + // will be one greater than the value of this option. + // + // One big limitation of this is that it doesn't differentiate between + // different register classes. So on x86-64, if there is xmm register + // pressure, it can caused fewer GPRs to be held in the queue. + static cl::opt + NumRecentlyUsedRegs("linearscan-skip-count", + cl::desc("Number of registers for linearscan to remember to skip."), + cl::init(0), + cl::Hidden); + struct RALinScan : public MachineFunctionPass { static char ID; - RALinScan() : MachineFunctionPass(&ID) {} + RALinScan() : MachineFunctionPass(&ID) { + // Initialize the queue to record recently-used registers. + if (NumRecentlyUsedRegs > 0) + RecentRegs.resize(NumRecentlyUsedRegs, 0); + } typedef std::pair IntervalPtr; typedef SmallVector IntervalPtrs; @@ -132,6 +153,18 @@ std::auto_ptr spiller_; + // The queue of recently-used registers. + SmallVector RecentRegs; + + // Record that we just picked this register. + void recordRecentlyUsed(unsigned reg) { + assert(reg != 0 && "Recently used register is NOREG!"); + if (!RecentRegs.empty()) { + std::copy(RecentRegs.begin() + 1, RecentRegs.end(), RecentRegs.begin()); + RecentRegs.back() = reg; + } + } + public: virtual const char* getPassName() const { return "Linear Scan Register Allocator"; @@ -161,6 +194,12 @@ /// runOnMachineFunction - register allocate the whole function bool runOnMachineFunction(MachineFunction&); + // Determine if we skip this register due to its being recently used. + bool isRecentlyUsed(unsigned reg) const { + return std::find(RecentRegs.begin(), RecentRegs.end(), reg) != + RecentRegs.end(); + } + private: /// linearScan - the linear scan algorithm void linearScan(); @@ -833,9 +872,15 @@ namespace { struct WeightCompare { + private: + const RALinScan &Allocator; + + public: + WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {}; + typedef std::pair RegWeightPair; bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const { - return LHS.second < RHS.second; + return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first); } }; } @@ -1079,7 +1124,8 @@ e = RC->allocation_order_end(*mf_); i != e; ++i) { unsigned reg = *i; float regWeight = SpillWeights[reg]; - if (minWeight > regWeight) + // Skip recently allocated registers. + if (minWeight > regWeight && !isRecentlyUsed(reg)) Found = true; RegsWeights.push_back(std::make_pair(reg, regWeight)); } @@ -1097,7 +1143,7 @@ } // Sort all potential spill candidates by weight. - std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare()); + std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this)); minReg = RegsWeights[0].first; minWeight = RegsWeights[0].second; if (minWeight == HUGE_VALF) { @@ -1360,7 +1406,8 @@ // Ignore "downgraded" registers. if (SkipDGRegs && DowngradedRegs.count(Reg)) continue; - if (isRegAvail(Reg)) { + // Skip recently allocated registers. + if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) { FreeReg = Reg; if (FreeReg < inactiveCounts.size()) FreeRegInactiveCount = inactiveCounts[FreeReg]; @@ -1372,9 +1419,12 @@ // If there are no free regs, or if this reg has the max inactive count, // return this register. - if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) + if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) { + // Remember what register we picked so we can skip it next time. + if (FreeReg != 0) recordRecentlyUsed(FreeReg); return FreeReg; - + } + // Continue scanning the registers, looking for the one with the highest // inactive count. Alkis found that this reduced register pressure very // slightly on X86 (in rev 1.94 of this file), though this should probably be @@ -1393,6 +1443,9 @@ } } + // Remember what register we picked so we can skip it next time. + recordRecentlyUsed(FreeReg); + return FreeReg; } From benny.kra at googlemail.com Thu Nov 19 10:04:42 2009 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 19 Nov 2009 16:04:42 -0000 Subject: [llvm-commits] [llvm] r89357 - /llvm/trunk/unittests/ADT/StringRefTest.cpp Message-ID: <200911191604.nAJG4g9f007499@zion.cs.uiuc.edu> Author: d0k Date: Thu Nov 19 10:04:41 2009 New Revision: 89357 URL: http://llvm.org/viewvc/llvm-project?rev=89357&view=rev Log: Reenable Split2 StringRef test with Apple gcc. Modified: llvm/trunk/unittests/ADT/StringRefTest.cpp Modified: llvm/trunk/unittests/ADT/StringRefTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/StringRefTest.cpp?rev=89357&r1=89356&r2=89357&view=diff ============================================================================== --- llvm/trunk/unittests/ADT/StringRefTest.cpp (original) +++ llvm/trunk/unittests/ADT/StringRefTest.cpp Thu Nov 19 10:04:41 2009 @@ -111,11 +111,6 @@ Str.rsplit('o')); } -// XFAIL for PR5482, StringRef is miscompiled by Apple gcc. -#if (!defined(__llvm__) && defined(__APPLE__) && defined(__OPTIMIZE__)) -#define SKIP_SPLIT2 -#endif -#ifndef SKIP_SPLIT2 TEST(StringRefTest, Split2) { SmallVector parts; SmallVector expected; @@ -195,7 +190,6 @@ StringRef("a,,b,c").split(parts, ",", 3, false); EXPECT_TRUE(parts == expected); } -#endif TEST(StringRefTest, StartsWith) { StringRef Str("hello"); From grosbach at apple.com Thu Nov 19 10:06:21 2009 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 19 Nov 2009 16:06:21 -0000 Subject: [llvm-commits] [test-suite] r89358 - /test-suite/trunk/Makefile.programs Message-ID: <200911191606.nAJG6LPc007564@zion.cs.uiuc.edu> Author: grosbach Date: Thu Nov 19 10:06:21 2009 New Revision: 89358 URL: http://llvm.org/viewvc/llvm-project?rev=89358&view=rev Log: llcbeta = simplify-iv-users for x86 Modified: test-suite/trunk/Makefile.programs Modified: test-suite/trunk/Makefile.programs URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=89358&r1=89357&r2=89358&view=diff ============================================================================== --- test-suite/trunk/Makefile.programs (original) +++ test-suite/trunk/Makefile.programs Thu Nov 19 10:06:21 2009 @@ -223,12 +223,14 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86_64) -LLCBETAOPTION := -combiner-alias-analysis +LLCBETAOPTION := -simplify-iv-users +#-combiner-alias-analysis #-pre-alloc-split #-remat-pic-stub-load endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -combiner-alias-analysis +LLCBETAOPTION := -simplify-iv-users +#-combiner-alias-analysis #-pre-alloc-split #-remat-pic-stub-load #-combiner-global-alias-analysis From grosbach at apple.com Thu Nov 19 10:07:07 2009 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 19 Nov 2009 08:07:07 -0800 Subject: [llvm-commits] [test-suite] r89302 - /test-suite/trunk/Makefile.programs In-Reply-To: <4CE1AABC-90E0-4886-B5DB-1B25894F7706@apple.com> References: <200911190309.nAJ39VZu030040@zion.cs.uiuc.edu> <4CE1AABC-90E0-4886-B5DB-1B25894F7706@apple.com> Message-ID: <45C7597B-AE37-4F41-B374-7D094CA94C13@apple.com> Good point. Done. -jim On Nov 18, 2009, at 9:32 PM, Evan Cheng wrote: > x86 as well please. > > Evan > > On Nov 18, 2009, at 7:09 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Wed Nov 18 21:09:31 2009 >> New Revision: 89302 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=89302&view=rev >> Log: >> llcbeta = simplify-iv-users for ARM and Thumb >> >> Modified: >> test-suite/trunk/Makefile.programs >> >> Modified: test-suite/trunk/Makefile.programs >> URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=89302&r1=89301&r2=89302&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- test-suite/trunk/Makefile.programs (original) >> +++ test-suite/trunk/Makefile.programs Wed Nov 18 21:09:31 2009 >> @@ -244,11 +244,11 @@ >> LLCBETAOPTION := -enable-sparc-v9-insts >> endif >> ifeq ($(ARCH),ARM) >> -LLCBETAOPTION := -arm-adjust-jump-tables >> +LLCBETAOPTION := -simplify-iv-users >> #-schedule-livein-copies >> endif >> ifeq ($(ARCH),THUMB) >> -LLCBETAOPTION := -arm-adjust-jump-tables >> +LLCBETAOPTION := -simplify-iv-users >> #-combiner-alias-analysis >> #-enable-thumb-reg-scavenging >> endif >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From benny.kra at googlemail.com Thu Nov 19 10:08:04 2009 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 19 Nov 2009 16:08:04 -0000 Subject: [llvm-commits] [llvm] r89359 - /llvm/trunk/include/llvm/ADT/STLExtras.h Message-ID: <200911191608.nAJG84UN007622@zion.cs.uiuc.edu> Author: d0k Date: Thu Nov 19 10:08:04 2009 New Revision: 89359 URL: http://llvm.org/viewvc/llvm-project?rev=89359&view=rev Log: cstdlib is not automatically included with StringRef anymore. Modified: llvm/trunk/include/llvm/ADT/STLExtras.h Modified: llvm/trunk/include/llvm/ADT/STLExtras.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/STLExtras.h?rev=89359&r1=89358&r2=89359&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/STLExtras.h (original) +++ llvm/trunk/include/llvm/ADT/STLExtras.h Thu Nov 19 10:08:04 2009 @@ -18,6 +18,7 @@ #define LLVM_ADT_STLEXTRAS_H #include // for std::size_t +#include // for qsort #include #include #include // for std::pair From gohman at apple.com Thu Nov 19 10:35:11 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 19 Nov 2009 16:35:11 -0000 Subject: [llvm-commits] [llvm] r89360 - /llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td Message-ID: <200911191635.nAJGZBqn008682@zion.cs.uiuc.edu> Author: djg Date: Thu Nov 19 10:35:11 2009 New Revision: 89360 URL: http://llvm.org/viewvc/llvm-project?rev=89360&view=rev Log: Fix a typo in a comment. Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td?rev=89360&r1=89359&r2=89360&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td Thu Nov 19 10:35:11 2009 @@ -44,7 +44,7 @@ let Num = num; } -// Ywo halves of 32-bit register +// Two halves of 32-bit register multiclass Rss group, bits<3> num, string n> { def H : Rs; def L : Rs; From foldr at codedgers.com Thu Nov 19 11:28:01 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Thu, 19 Nov 2009 18:28:01 +0100 Subject: [llvm-commits] [PATCH] Move the handling of CommaSeparated options into ProvideOption. Message-ID: <1258651681-11782-1-git-send-email-foldr@codedgers.com> Makes '--comma-separated val1,val2' mean the same thing as '--comma-separated=val1,val2' (that is, 'val1' and 'val2' are not lumped together as 'val1,val2'). Also declutters the main loop a bit. --- lib/Support/CommandLine.cpp | 56 +++++++++++++++++++++++++----------------- 1 files changed, 33 insertions(+), 23 deletions(-) diff --git a/lib/Support/CommandLine.cpp b/lib/Support/CommandLine.cpp index e8496c7..0560c81 100644 --- a/lib/Support/CommandLine.cpp +++ b/lib/Support/CommandLine.cpp @@ -177,7 +177,37 @@ static Option *LookupOption(StringRef &Arg, StringRef &Value, return I->second; } +/// CommaSeparateAndAddOccurence - A wrapper around Handler->addOccurence() that +/// does special handling for cl::CommaSeparated options. +static bool CommaSeparateAndAddOccurence(Option *Handler, unsigned pos, + StringRef ArgName, + StringRef Value, bool MultiArg = false) +{ + // Check to see if this option accepts a comma separated list of values. If + // it does, we have to split up the value into multiple values. + if (Handler->getMiscFlags() & CommaSeparated) { + StringRef Val(Value); + StringRef::size_type Pos = Val.find(','); + + while (Pos != StringRef::npos) { + // Process the portion before the comma. + if (Handler->addOccurrence(pos, ArgName, Val.substr(0, Pos), MultiArg)) + return true; + // Erase the portion before the comma, AND the comma. + Val = Val.substr(Pos+1); + Value.substr(Pos+1); // Increment the original value pointer as well. + // Check for another comma. + Pos = Val.find(','); + } + + Value = Val; + } + + if (Handler->addOccurrence(pos, ArgName, Value, MultiArg)) + return true; + return false; +} /// ProvideOption - For Value, this differentiates between an empty value ("") /// and a null value (StringRef()). The later is accepted for arguments that @@ -219,13 +249,13 @@ static inline bool ProvideOption(Option *Handler, StringRef ArgName, // If this isn't a multi-arg option, just run the handler. if (NumAdditionalVals == 0) - return Handler->addOccurrence(i, ArgName, Value); + return CommaSeparateAndAddOccurence(Handler, i, ArgName, Value); // If it is, run the handle several times. bool MultiArg = false; if (Value.data()) { - if (Handler->addOccurrence(i, ArgName, Value, MultiArg)) + if (CommaSeparateAndAddOccurence(Handler, i, ArgName, Value, MultiArg)) return true; --NumAdditionalVals; MultiArg = true; @@ -236,7 +266,7 @@ static inline bool ProvideOption(Option *Handler, StringRef ArgName, return Handler->error("not enough values!"); Value = argv[++i]; - if (Handler->addOccurrence(i, ArgName, Value, MultiArg)) + if (CommaSeparateAndAddOccurence(Handler, i, ArgName, Value, MultiArg)) return true; MultiArg = true; --NumAdditionalVals; @@ -627,26 +657,6 @@ void cl::ParseCommandLineOptions(int argc, char **argv, continue; } - // Check to see if this option accepts a comma separated list of values. If - // it does, we have to split up the value into multiple values. - if (Handler->getMiscFlags() & CommaSeparated) { - StringRef Val(Value); - StringRef::size_type Pos = Val.find(','); - - while (Pos != StringRef::npos) { - // Process the portion before the comma. - ErrorParsing |= ProvideOption(Handler, ArgName, Val.substr(0, Pos), - argc, argv, i); - // Erase the portion before the comma, AND the comma. - Val = Val.substr(Pos+1); - Value.substr(Pos+1); // Increment the original value pointer as well. - - // Check for another comma. - Pos = Val.find(','); - } - Value = Val; - } - // If this is a named positional argument, just remember that it is the // active one... if (Handler->getFormattingFlag() == cl::Positional) -- 1.6.5.2 From foldr at codedgers.com Thu Nov 19 11:29:25 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Thu, 19 Nov 2009 17:29:25 -0000 Subject: [llvm-commits] [llvm] r89363 - /llvm/trunk/tools/llvmc/example/Hello/Hello.cpp Message-ID: <200911191729.nAJHTPJT010351@zion.cs.uiuc.edu> Author: foldr Date: Thu Nov 19 11:29:25 2009 New Revision: 89363 URL: http://llvm.org/viewvc/llvm-project?rev=89363&view=rev Log: Make example/Hello compile again. Modified: llvm/trunk/tools/llvmc/example/Hello/Hello.cpp Modified: llvm/trunk/tools/llvmc/example/Hello/Hello.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/Hello/Hello.cpp?rev=89363&r1=89362&r2=89363&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/example/Hello/Hello.cpp (original) +++ llvm/trunk/tools/llvmc/example/Hello/Hello.cpp Thu Nov 19 11:29:25 2009 @@ -17,6 +17,10 @@ namespace { struct MyPlugin : public llvmc::BasePlugin { + + void PreprocessOptions() const + {} + void PopulateLanguageMap(llvmc::LanguageMap&) const { outs() << "Hello!\n"; } From foldr at codedgers.com Thu Nov 19 11:29:37 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Thu, 19 Nov 2009 17:29:37 -0000 Subject: [llvm-commits] [llvm] r89364 - /llvm/trunk/lib/Support/CommandLine.cpp Message-ID: <200911191729.nAJHTbl0010366@zion.cs.uiuc.edu> Author: foldr Date: Thu Nov 19 11:29:36 2009 New Revision: 89364 URL: http://llvm.org/viewvc/llvm-project?rev=89364&view=rev Log: Trailing whitespace. Modified: llvm/trunk/lib/Support/CommandLine.cpp Modified: llvm/trunk/lib/Support/CommandLine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=89364&r1=89363&r2=89364&view=diff ============================================================================== --- llvm/trunk/lib/Support/CommandLine.cpp (original) +++ llvm/trunk/lib/Support/CommandLine.cpp Thu Nov 19 11:29:36 2009 @@ -156,9 +156,9 @@ const StringMap &OptionsMap) { // Reject all dashes. if (Arg.empty()) return 0; - + size_t EqualPos = Arg.find('='); - + // If we have an equals sign, remember the value. if (EqualPos == StringRef::npos) { // Look up the option. @@ -171,7 +171,7 @@ StringMap::const_iterator I = OptionsMap.find(Arg.substr(0, EqualPos)); if (I == OptionsMap.end()) return 0; - + Value = Arg.substr(EqualPos+1); Arg = Arg.substr(0, EqualPos); return I->second; @@ -209,7 +209,7 @@ break; case ValueOptional: break; - + default: errs() << ProgramName << ": Bad ValueMask flag! CommandLine usage error:" @@ -235,7 +235,7 @@ if (i+1 >= argc) return Handler->error("not enough values!"); Value = argv[++i]; - + if (Handler->addOccurrence(i, ArgName, Value, MultiArg)) return true; MultiArg = true; @@ -298,7 +298,7 @@ size_t Length = 0; Option *PGOpt = getOptionPred(Arg, Length, isPrefixedOrGrouping, OptionsMap); if (PGOpt == 0) return 0; - + // If the option is a prefixed option, then the value is simply the // rest of the name... so fall through to later processing, by // setting up the argument name flags and value fields. @@ -308,16 +308,16 @@ assert(OptionsMap.count(Arg) && OptionsMap.find(Arg)->second == PGOpt); return PGOpt; } - + // This must be a grouped option... handle them now. Grouping options can't // have values. assert(isGrouping(PGOpt) && "Broken getOptionPred!"); - + do { // Move current arg name out of Arg into OneArgName. StringRef OneArgName = Arg.substr(0, Length); Arg = Arg.substr(Length); - + // Because ValueRequired is an invalid flag for grouped arguments, // we don't need to pass argc/argv in. assert(PGOpt->getValueExpectedFlag() != cl::ValueRequired && @@ -325,11 +325,11 @@ int Dummy; ErrorParsing |= ProvideOption(PGOpt, OneArgName, StringRef(), 0, 0, Dummy); - + // Get the next grouping option. PGOpt = getOptionPred(Arg, Length, isGrouping, OptionsMap); } while (PGOpt && Length != Arg.size()); - + // Return the last option with Arg cut down to just the last one. return PGOpt; } @@ -366,17 +366,17 @@ WorkStr = WorkStr.substr(Pos); continue; } - + // Find position of first delimiter. size_t Pos = WorkStr.find_first_of(Delims); if (Pos == StringRef::npos) Pos = WorkStr.size(); - + // Everything from 0 to Pos is the next word to copy. char *NewStr = (char*)malloc(Pos+1); memcpy(NewStr, WorkStr.data(), Pos); NewStr[Pos] = 0; OutputVector.push_back(NewStr); - + WorkStr = WorkStr.substr(Pos); } } @@ -563,7 +563,7 @@ ProvidePositionalOption(ActivePositionalArg, argv[i], i); continue; // We are done! } - + if (!PositionalOpts.empty()) { PositionalVals.push_back(std::make_pair(argv[i],i)); @@ -593,7 +593,7 @@ // Eat leading dashes. while (!ArgName.empty() && ArgName[0] == '-') ArgName = ArgName.substr(1); - + Handler = LookupOption(ArgName, Value, Opts); if (!Handler || Handler->getFormattingFlag() != cl::Positional) { ProvidePositionalOption(ActivePositionalArg, argv[i], i); @@ -605,7 +605,7 @@ // Eat leading dashes. while (!ArgName.empty() && ArgName[0] == '-') ArgName = ArgName.substr(1); - + Handler = LookupOption(ArgName, Value, Opts); // Check to see if this "option" is really a prefixed or grouped argument. @@ -881,7 +881,7 @@ Value = true; return false; } - + if (Arg == "false" || Arg == "FALSE" || Arg == "False" || Arg == "0") { Value = false; return false; @@ -903,7 +903,7 @@ Value = BOU_FALSE; return false; } - + return O.error("'" + Arg + "' is invalid value for boolean argument! Try 0 or 1"); } @@ -1020,7 +1020,7 @@ static int OptNameCompare(const void *LHS, const void *RHS) { typedef std::pair pair_ty; - + return strcmp(((pair_ty*)LHS)->first, ((pair_ty*)RHS)->first); } @@ -1054,11 +1054,11 @@ // Ignore really-hidden options. if (I->second->getOptionHiddenFlag() == ReallyHidden) continue; - + // Unless showhidden is set, ignore hidden flags. if (I->second->getOptionHiddenFlag() == Hidden && !ShowHidden) continue; - + // If we've already seen this option, don't add it to the list again. if (!OptionSet.insert(I->second)) continue; @@ -1066,7 +1066,7 @@ Opts.push_back(std::pair(I->getKey().data(), I->second)); } - + // Sort the options list alphabetically. qsort(Opts.data(), Opts.size(), sizeof(Opts[0]), OptNameCompare); @@ -1164,7 +1164,7 @@ std::vector > Targets; size_t Width = 0; - for (TargetRegistry::iterator it = TargetRegistry::begin(), + for (TargetRegistry::iterator it = TargetRegistry::begin(), ie = TargetRegistry::end(); it != ie; ++it) { Targets.push_back(std::make_pair(it->getName(), &*it)); Width = std::max(Width, strlen(Targets.back().first)); @@ -1183,7 +1183,7 @@ } void operator=(bool OptionWasSpecified) { if (!OptionWasSpecified) return; - + if (OverrideVersionPrinter == 0) { print(); exit(1); From sabre at nondot.org Thu Nov 19 11:35:02 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 19 Nov 2009 09:35:02 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: References: <701493E3-E27B-4EAB-9666-99B2F6EA01BC@apple.com> Message-ID: Apologies for the last email being rambling, and in advance for this one also being rambling. :) My basic perspective is that I want to sink as much logic into the target-independent code as possible and have the fewest number of target hooks reasonable. This is for three reasons: 1. Porting to a new target is easier with fewer target hooks, and they get better codegen 'out of the box' by specifying primitives instead of having to tweak tons of knobs. 2. A single and well tuned implementation of something in target independent code is better than having a few well tuned impls in some targets and missing or just wrong impls in others. For example, this xform is definitely profitable on X86 chips as well, probably many others. 3. Less target-specific code to maintain and push around as the compiler moves forward. anyway, these are just general principles why I don't like new target hooks when they can be avoided. More details: > On Nov 18, 2009, at 9:29 AM, Bob Wilson wrote: >> The only disadvantage of what you suggest is code size. There is >> currently no limit on the number of predecessors where a block may be >> duplicated, so the effect of duplicating a small block can be >> magnified in the overall code size. Right. However, the implementation for ARM doesn't consider this at all. Also, this cost is not something that should need target-specific information to quantify. >> (And, at least for duplicating >> indirect branches on ARM Cortex processors, we don't want to limit >> that.) Why not?? >> On a small low-power device without sophisticated branch >> prediction, where code size typically matters more than usual, we'll >> be doing the wrong thing. But, indirect branches are not very common, >> so it probably doesn't really matter so much. They are fairly common in switch statements that codegen to jump tables, but not anyway near as common as normal branches. >> Most modern high-performance processors will benefit from tail >> duplicating indirect branches, so that would be another reason to >> avoid the target hook. Right. I would also like the target hook much better if it was of the form "DoesBranchPredictionOfIndirectCallsBasedOnPC" or something like that. This predicate makes it *really really* obvious what it doing. By returning a 'cost' with no real units, the target author has no "truth" they just fiddle around until the 'right thing happens'. Given the documentation, it's very unclear (as a target author) why you'd want to specify the hook you added. I much prefer very simple hooks that return an _aspect of the micro architecture_ rather than having hooks that _implement pieces of codegen passes_. The later is the approach that GCC took and is one of the major reasons it is difficult to change the algorithms in the GCC backend. >> >> Unless someone else has another idea, I'll get rid of the tail >> duplication target hook. As you mention, we'll need a way to identify >> indirect branches. I'd prefer to add a new IsIndirectBranch target >> hook. This goes against your desire to avoid new target hooks, but >> it's nice and simple. Using the extant isIndirectBranch flag would be best, but even adding this sort of target hook would be somewhat ok. At least this would be a property of the architecture. If we can avoid it, I'd definitely prefer to of course. Dan wrote: > However I don't know what the big problem is > with the target hook; it's neither arbitrary nor unitless. Perhaps > what he really meant is that the present use for the hook is too > obscure to justify having the clutter of the hook in TargetInstrInfo, > but I'm just guessing here. What is the units that it returns? As a target author, how do I know to return +2 or +4 or +1234? Thanks for working on this Bob! -Chris From bob.wilson at apple.com Thu Nov 19 12:11:11 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 19 Nov 2009 10:11:11 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: References: <701493E3-E27B-4EAB-9666-99B2F6EA01BC@apple.com> Message-ID: On Nov 19, 2009, at 9:35 AM, Chris Lattner wrote: > Apologies for the last email being rambling, and in advance for this > one also being rambling. :) > > My basic perspective is that I want to sink as much logic into the > target-independent code as possible and have the fewest number of > target hooks reasonable. This is for three reasons: > > 1. Porting to a new target is easier with fewer target hooks, and > they get better codegen 'out of the box' by specifying primitives > instead of having to tweak tons of knobs. I disagree. It is good to have knobs to tweak. As long as the defaults are set to values that work well for most targets, having more knobs does not make it harder to port to a new target. It does increase the overall complexity and documentation burden, though. In this particular case, I left the default set to match the previous behavior. We could easily change that once we find out what works best on most of the targets we support. > > 2. A single and well tuned implementation of something in target > independent code is better than having a few well tuned impls in > some targets and missing or just wrong impls in others. For > example, this xform is definitely profitable on X86 chips as well, > probably many others. Right. There is a single implementation of tail duplication here. It's just a question of tuning it for different targets. It is not possible (in general) to have it tuned ideally for all targets. For that matter, we haven't really tuned it for ARM yet. I've started looking at trying it for X86. I suppose that after further experimentation, we may discover that in practice the same tuning works well enough on all the targets we care about. I don't know whether that will be true or not, but based on your comments, let's assume that it will. If we discover later that it doesn't work well, we can always add the target hook at that time. > > 3. Less target-specific code to maintain and push around as the > compiler moves forward. > > anyway, these are just general principles why I don't like new > target hooks when they can be avoided. More details: > >> On Nov 18, 2009, at 9:29 AM, Bob Wilson wrote: >>> The only disadvantage of what you suggest is code size. There is >>> currently no limit on the number of predecessors where a block may >>> be >>> duplicated, so the effect of duplicating a small block can be >>> magnified in the overall code size. > > Right. However, the implementation for ARM doesn't consider this at > all. Also, this cost is not something that should need target- > specific information to quantify. It's easy to measure the change in code size but hard to weigh that against the performance benefit. That part is very target-specific. > >>> (And, at least for duplicating >>> indirect branches on ARM Cortex processors, we don't want to limit >>> that.) > > Why not?? Because it is such a dramatic performance win for ARM Cortex, and perhaps more importantly, I can't think of a way to limit it that might not also miss cases where we really want to get the performance. I don't expect indirect branches to be so common that the code size matters. > >>> On a small low-power device without sophisticated branch >>> prediction, where code size typically matters more than usual, we'll >>> be doing the wrong thing. But, indirect branches are not very >>> common, >>> so it probably doesn't really matter so much. > > They are fairly common in switch statements that codegen to jump > tables, but not anyway near as common as normal branches. For ARM we currently use different instruction patterns for jump tables and indirect branches. So, the special case we're doing for tail duplication does not apply to jump tables. We might have to be more conservative if we can't distinguish those on other targets. > >>> Most modern high-performance processors will benefit from tail >>> duplicating indirect branches, so that would be another reason to >>> avoid the target hook. > > Right. I would also like the target hook much better if it was of > the form "DoesBranchPredictionOfIndirectCallsBasedOnPC" or something > like that. This predicate makes it *really really* obvious what it > doing. By returning a 'cost' with no real units, the target author > has no "truth" they just fiddle around until the 'right thing > happens'. Given the documentation, it's very unclear (as a target > author) why you'd want to specify the hook you added. > > I much prefer very simple hooks that return an _aspect of the micro > architecture_ rather than having hooks that _implement pieces of > codegen passes_. The later is the approach that GCC took and is one > of the major reasons it is difficult to change the algorithms in the > GCC backend. Doesn't that go against your desire to have fewer target hooks? I tried to make the tail duplication hook very general, since it seems conceivable that we may want to adjust the cost metric based on other characteristics of the target. If we add very specific target hooks, we may end up with more of them. I admit that "obviousness" advantage of using very specific hooks. > >>> >>> Unless someone else has another idea, I'll get rid of the tail >>> duplication target hook. As you mention, we'll need a way to >>> identify >>> indirect branches. I'd prefer to add a new IsIndirectBranch target >>> hook. This goes against your desire to avoid new target hooks, but >>> it's nice and simple. > > Using the extant isIndirectBranch flag would be best, but even > adding this sort of target hook would be somewhat ok. At least this > would be a property of the architecture. If we can avoid it, I'd > definitely prefer to of course. The isIndirectBranch flag would not allow us to distinguish jump table branches. > > Dan wrote: >> However I don't know what the big problem is >> with the target hook; it's neither arbitrary nor unitless. Perhaps >> what he really meant is that the present use for the hook is too >> obscure to justify having the clutter of the hook in TargetInstrInfo, >> but I'm just guessing here. > > What is the units that it returns? As a target author, how do I > know to return +2 or +4 or +1234? It returns the maximum number of instructions in a basic block that will be tail duplicated. From daniel at zuster.org Thu Nov 19 12:22:16 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 19 Nov 2009 18:22:16 -0000 Subject: [llvm-commits] [llvm] r89368 - /llvm/trunk/utils/TableGen/OptParserEmitter.cpp Message-ID: <200911191822.nAJIMGHD012386@zion.cs.uiuc.edu> Author: ddunbar Date: Thu Nov 19 12:22:16 2009 New Revision: 89368 URL: http://llvm.org/viewvc/llvm-project?rev=89368&view=rev Log: TableGen/OptParser: When ordering options, make "sentinel" options appear before everything else. Modified: llvm/trunk/utils/TableGen/OptParserEmitter.cpp Modified: llvm/trunk/utils/TableGen/OptParserEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/OptParserEmitter.cpp?rev=89368&r1=89367&r2=89368&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/OptParserEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/OptParserEmitter.cpp Thu Nov 19 12:22:16 2009 @@ -35,9 +35,16 @@ const Record *A = *(Record**) Av; const Record *B = *(Record**) Bv; - // Compare options by name first. - if (int Cmp = StrCmpOptionName(A->getValueAsString("Name").c_str(), - B->getValueAsString("Name").c_str())) + // Sentinel options preceed all others and are only ordered by precedence. + bool ASent = A->getValueAsDef("Kind")->getValueAsBit("Sentinel"); + bool BSent = B->getValueAsDef("Kind")->getValueAsBit("Sentinel"); + if (ASent != BSent) + return ASent ? -1 : 1; + + // Compare options by name, unless they are sentinels. + if (!ASent) + if (int Cmp = StrCmpOptionName(A->getValueAsString("Name").c_str(), + B->getValueAsString("Name").c_str())) return Cmp; // Then by the kind precedence; From grosbach at apple.com Thu Nov 19 12:23:20 2009 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 19 Nov 2009 18:23:20 -0000 Subject: [llvm-commits] [llvm] r89369 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <200911191823.nAJINKGR012422@zion.cs.uiuc.edu> Author: grosbach Date: Thu Nov 19 12:23:19 2009 New Revision: 89369 URL: http://llvm.org/viewvc/llvm-project?rev=89369&view=rev Log: fix typo Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=89369&r1=89368&r2=89369&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Thu Nov 19 12:23:19 2009 @@ -550,7 +550,7 @@ case ARM::LEApcrel: // This takes a SoImm, which is 8 bit immediate rotated. We'll // pretend the maximum offset is 255 * 4. Since each instruction - // 4 byte wide, this is always correct. We'llc heck for other + // 4 byte wide, this is always correct. We'll check for other // displacements that fits in a SoImm as well. Bits = 8; Scale = 4; From daniel at zuster.org Thu Nov 19 12:53:18 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 19 Nov 2009 18:53:18 -0000 Subject: [llvm-commits] [llvm] r89372 - /llvm/trunk/lib/Support/StringRef.cpp Message-ID: <200911191853.nAJIrIGG013548@zion.cs.uiuc.edu> Author: ddunbar Date: Thu Nov 19 12:53:18 2009 New Revision: 89372 URL: http://llvm.org/viewvc/llvm-project?rev=89372&view=rev Log: Use StringRef::min instead of std::min. Modified: llvm/trunk/lib/Support/StringRef.cpp Modified: llvm/trunk/lib/Support/StringRef.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/StringRef.cpp?rev=89372&r1=89371&r2=89372&view=diff ============================================================================== --- llvm/trunk/lib/Support/StringRef.cpp (original) +++ llvm/trunk/lib/Support/StringRef.cpp Thu Nov 19 12:53:18 2009 @@ -23,7 +23,7 @@ /// compare_lower - Compare strings, ignoring case. int StringRef::compare_lower(StringRef RHS) const { - for (size_t I = 0, E = std::min(Length, RHS.Length); I != E; ++I) { + for (size_t I = 0, E = min(Length, RHS.Length); I != E; ++I) { char LHC = ascii_tolower(Data[I]); char RHC = ascii_tolower(RHS.Data[I]); if (LHC != RHC) @@ -48,7 +48,7 @@ size_t N = Str.size(); if (N > Length) return npos; - for (size_t e = Length - N + 1, i = std::min(From, e); i != e; ++i) + for (size_t e = Length - N + 1, i = min(From, e); i != e; ++i) if (substr(i, N).equals(Str)) return i; return npos; @@ -76,7 +76,7 @@ /// Note: O(size() * Chars.size()) StringRef::size_type StringRef::find_first_of(StringRef Chars, size_t From) const { - for (size_type i = std::min(From, Length), e = Length; i != e; ++i) + for (size_type i = min(From, Length), e = Length; i != e; ++i) if (Chars.find(Data[i]) != npos) return i; return npos; @@ -85,7 +85,7 @@ /// find_first_not_of - Find the first character in the string that is not /// \arg C or npos if not found. StringRef::size_type StringRef::find_first_not_of(char C, size_t From) const { - for (size_type i = std::min(From, Length), e = Length; i != e; ++i) + for (size_type i = min(From, Length), e = Length; i != e; ++i) if (Data[i] != C) return i; return npos; @@ -97,7 +97,7 @@ /// Note: O(size() * Chars.size()) StringRef::size_type StringRef::find_first_not_of(StringRef Chars, size_t From) const { - for (size_type i = std::min(From, Length), e = Length; i != e; ++i) + for (size_type i = min(From, Length), e = Length; i != e; ++i) if (Chars.find(Data[i]) == npos) return i; return npos; From gohman at apple.com Thu Nov 19 13:00:10 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 19 Nov 2009 19:00:10 -0000 Subject: [llvm-commits] [llvm] r89374 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/2008-07-22-LoadGlobalConstant.ll Message-ID: <200911191900.nAJJ0As9013798@zion.cs.uiuc.edu> Author: djg Date: Thu Nov 19 13:00:10 2009 New Revision: 89374 URL: http://llvm.org/viewvc/llvm-project?rev=89374&view=rev Log: Enable hoisting of loads from constant memory by default. In cases where they are lowered to instruction sequences more complex than a simple load, such that CodeGen cannot rematerialize them, a reload from a spill slot is likely to be cheaper than the complex sequence. Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp llvm/trunk/test/Transforms/LICM/2008-07-22-LoadGlobalConstant.ll Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=89374&r1=89373&r2=89374&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Thu Nov 19 13:00:10 2009 @@ -63,15 +63,6 @@ DisablePromotion("disable-licm-promotion", cl::Hidden, cl::desc("Disable memory promotion in LICM pass")); -// This feature is currently disabled by default because CodeGen is not yet -// capable of rematerializing these constants in PIC mode, so it can lead to -// degraded performance. Compile test/CodeGen/X86/remat-constant.ll with -// -relocation-model=pic to see an example of this. -static cl::opt -EnableLICMConstantMotion("enable-licm-constant-variables", cl::Hidden, - cl::desc("Enable hoisting/sinking of constant " - "global variables")); - namespace { struct LICM : public LoopPass { static char ID; // Pass identification, replacement for typeid @@ -383,8 +374,7 @@ // Loads from constant memory are always safe to move, even if they end up // in the same alias set as something that ends up being modified. - if (EnableLICMConstantMotion && - AA->pointsToConstantMemory(LI->getOperand(0))) + if (AA->pointsToConstantMemory(LI->getOperand(0))) return true; // Don't hoist loads which have may-aliased stores in loop. Modified: llvm/trunk/test/Transforms/LICM/2008-07-22-LoadGlobalConstant.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/2008-07-22-LoadGlobalConstant.ll?rev=89374&r1=89373&r2=89374&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LICM/2008-07-22-LoadGlobalConstant.ll (original) +++ llvm/trunk/test/Transforms/LICM/2008-07-22-LoadGlobalConstant.ll Thu Nov 19 13:00:10 2009 @@ -1,4 +1,4 @@ -; RUN: opt < %s -licm -enable-licm-constant-variables -S | FileCheck %s +; RUN: opt < %s -licm -S | FileCheck %s @a = external constant float* From greened at obbligato.org Thu Nov 19 13:09:39 2009 From: greened at obbligato.org (David Greene) Date: Thu, 19 Nov 2009 19:09:39 -0000 Subject: [llvm-commits] [llvm] r89376 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Message-ID: <200911191909.nAJJ9dqr014146@zion.cs.uiuc.edu> Author: greened Date: Thu Nov 19 13:09:39 2009 New Revision: 89376 URL: http://llvm.org/viewvc/llvm-project?rev=89376&view=rev Log: Fix a small bug. Fix one case we missed to make sure we reserve registers from allocation. Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=89376&r1=89375&r2=89376&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Thu Nov 19 13:09:39 2009 @@ -1435,7 +1435,7 @@ if (SkipDGRegs && DowngradedRegs.count(Reg)) continue; if (isRegAvail(Reg) && Reg < inactiveCounts.size() && - FreeRegInactiveCount < inactiveCounts[Reg]) { + FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) { FreeReg = Reg; FreeRegInactiveCount = inactiveCounts[Reg]; if (FreeRegInactiveCount == MaxInactiveCount) From johnny.chen at apple.com Thu Nov 19 13:20:17 2009 From: johnny.chen at apple.com (Johnny Chen) Date: Thu, 19 Nov 2009 19:20:17 -0000 Subject: [llvm-commits] [llvm] r89377 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td Message-ID: <200911191920.nAJJKHmV014543@zion.cs.uiuc.edu> Author: johnny Date: Thu Nov 19 13:20:17 2009 New Revision: 89377 URL: http://llvm.org/viewvc/llvm-project?rev=89377&view=rev Log: Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not fully specified at this level. Subclasses of NLdStLN can specify selective bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside ARMInstrNEON.td. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=89377&r1=89376&r2=89377&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Nov 19 13:20:17 2009 @@ -1245,6 +1245,17 @@ let Inst{7-4} = op7_4; } +// With selective bit(s) from op7_4 specified by subclasses. +class NLdStLN op21_20, bits<4> op11_8, + dag oops, dag iops, InstrItinClass itin, + string asm, string cstr, list pattern> + : NeonI { + let Inst{31-24} = 0b11110100; + let Inst{23} = op23; + let Inst{21-20} = op21_20; + let Inst{11-8} = op11_8; +} + class NDataI pattern> : NeonI { Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=89377&r1=89376&r2=89377&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Nov 19 13:20:17 2009 @@ -280,66 +280,107 @@ // VLD2LN : Vector Load (single 2-element structure to one lane) class VLD2LN op11_8, string OpcodeStr> - : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), - IIC_VLD2, - !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"), - "$src1 = $dst1, $src2 = $dst2", []>; + : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2), + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), + IIC_VLD2, + !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"), + "$src1 = $dst1, $src2 = $dst2", []>; +// vld2 to single-spaced registers. def VLD2LNd8 : VLD2LN<0b0001, "vld2.8">; -def VLD2LNd16 : VLD2LN<0b0101, "vld2.16">; -def VLD2LNd32 : VLD2LN<0b1001, "vld2.32">; +def VLD2LNd16 : VLD2LN<0b0101, "vld2.16"> { + let Inst{5} = 0; +} +def VLD2LNd32 : VLD2LN<0b1001, "vld2.32"> { + let Inst{6} = 0; +} // vld2 to double-spaced even registers. -def VLD2LNq16a: VLD2LN<0b0101, "vld2.16">; -def VLD2LNq32a: VLD2LN<0b1001, "vld2.32">; +def VLD2LNq16a: VLD2LN<0b0101, "vld2.16"> { + let Inst{5} = 1; +} +def VLD2LNq32a: VLD2LN<0b1001, "vld2.32"> { + let Inst{6} = 1; +} // vld2 to double-spaced odd registers. -def VLD2LNq16b: VLD2LN<0b0101, "vld2.16">; -def VLD2LNq32b: VLD2LN<0b1001, "vld2.32">; +def VLD2LNq16b: VLD2LN<0b0101, "vld2.16"> { + let Inst{5} = 1; +} +def VLD2LNq32b: VLD2LN<0b1001, "vld2.32"> { + let Inst{6} = 1; +} // VLD3LN : Vector Load (single 3-element structure to one lane) class VLD3LN op11_8, string OpcodeStr> - : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, - nohash_imm:$lane), IIC_VLD3, - !strconcat(OpcodeStr, - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"), - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>; - -def VLD3LNd8 : VLD3LN<0b0010, "vld3.8">; -def VLD3LNd16 : VLD3LN<0b0110, "vld3.16">; -def VLD3LNd32 : VLD3LN<0b1010, "vld3.32">; + : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, + nohash_imm:$lane), IIC_VLD3, + !strconcat(OpcodeStr, + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"), + "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>; + +// vld3 to single-spaced registers. +def VLD3LNd8 : VLD3LN<0b0010, "vld3.8"> { + let Inst{4} = 0; +} +def VLD3LNd16 : VLD3LN<0b0110, "vld3.16"> { + let Inst{5-4} = 0b00; +} +def VLD3LNd32 : VLD3LN<0b1010, "vld3.32"> { + let Inst{6-4} = 0b000; +} // vld3 to double-spaced even registers. -def VLD3LNq16a: VLD3LN<0b0110, "vld3.16">; -def VLD3LNq32a: VLD3LN<0b1010, "vld3.32">; +def VLD3LNq16a: VLD3LN<0b0110, "vld3.16"> { + let Inst{5-4} = 0b10; +} +def VLD3LNq32a: VLD3LN<0b1010, "vld3.32"> { + let Inst{6-4} = 0b100; +} // vld3 to double-spaced odd registers. -def VLD3LNq16b: VLD3LN<0b0110, "vld3.16">; -def VLD3LNq32b: VLD3LN<0b1010, "vld3.32">; +def VLD3LNq16b: VLD3LN<0b0110, "vld3.16"> { + let Inst{5-4} = 0b10; +} +def VLD3LNq32b: VLD3LN<0b1010, "vld3.32"> { + let Inst{6-4} = 0b100; +} // VLD4LN : Vector Load (single 4-element structure to one lane) class VLD4LN op11_8, string OpcodeStr> - : NLdSt<1,0b10,op11_8,0b0000, - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, - nohash_imm:$lane), IIC_VLD4, - !strconcat(OpcodeStr, - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"), - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>; + : NLdStLN<1,0b10,op11_8, + (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, + nohash_imm:$lane), IIC_VLD4, + !strconcat(OpcodeStr, + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"), + "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>; +// vld4 to single-spaced registers. def VLD4LNd8 : VLD4LN<0b0011, "vld4.8">; -def VLD4LNd16 : VLD4LN<0b0111, "vld4.16">; -def VLD4LNd32 : VLD4LN<0b1011, "vld4.32">; +def VLD4LNd16 : VLD4LN<0b0111, "vld4.16"> { + let Inst{5} = 0; +} +def VLD4LNd32 : VLD4LN<0b1011, "vld4.32"> { + let Inst{6} = 0; +} // vld4 to double-spaced even registers. -def VLD4LNq16a: VLD4LN<0b0111, "vld4.16">; -def VLD4LNq32a: VLD4LN<0b1011, "vld4.32">; +def VLD4LNq16a: VLD4LN<0b0111, "vld4.16"> { + let Inst{5} = 1; +} +def VLD4LNq32a: VLD4LN<0b1011, "vld4.32"> { + let Inst{6} = 1; +} // vld4 to double-spaced odd registers. -def VLD4LNq16b: VLD4LN<0b0111, "vld4.16">; -def VLD4LNq32b: VLD4LN<0b1011, "vld4.32">; +def VLD4LNq16b: VLD4LN<0b0111, "vld4.16"> { + let Inst{5} = 1; +} +def VLD4LNq32b: VLD4LN<0b1011, "vld4.32"> { + let Inst{6} = 1; +} // VLD1DUP : Vector Load (single element to all lanes) // VLD2DUP : Vector Load (single 2-element structure to all lanes) @@ -463,64 +504,105 @@ // VST2LN : Vector Store (single 2-element structure from one lane) class VST2LN op11_8, string OpcodeStr> - : NLdSt<1,0b00,op11_8,0b0000, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), - IIC_VST, - !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"), - "", []>; + : NLdStLN<1,0b00,op11_8, (outs), + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), + IIC_VST, + !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"), + "", []>; +// vst2 to single-spaced registers. def VST2LNd8 : VST2LN<0b0001, "vst2.8">; -def VST2LNd16 : VST2LN<0b0101, "vst2.16">; -def VST2LNd32 : VST2LN<0b1001, "vst2.32">; +def VST2LNd16 : VST2LN<0b0101, "vst2.16"> { + let Inst{5} = 0; +} +def VST2LNd32 : VST2LN<0b1001, "vst2.32"> { + let Inst{6} = 0; +} // vst2 to double-spaced even registers. -def VST2LNq16a: VST2LN<0b0101, "vst2.16">; -def VST2LNq32a: VST2LN<0b1001, "vst2.32">; +def VST2LNq16a: VST2LN<0b0101, "vst2.16"> { + let Inst{5} = 1; +} +def VST2LNq32a: VST2LN<0b1001, "vst2.32"> { + let Inst{6} = 1; +} // vst2 to double-spaced odd registers. -def VST2LNq16b: VST2LN<0b0101, "vst2.16">; -def VST2LNq32b: VST2LN<0b1001, "vst2.32">; +def VST2LNq16b: VST2LN<0b0101, "vst2.16"> { + let Inst{5} = 1; +} +def VST2LNq32b: VST2LN<0b1001, "vst2.32"> { + let Inst{6} = 1; +} // VST3LN : Vector Store (single 3-element structure from one lane) class VST3LN op11_8, string OpcodeStr> - : NLdSt<1,0b00,op11_8,0b0000, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, - nohash_imm:$lane), IIC_VST, - !strconcat(OpcodeStr, - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>; - -def VST3LNd8 : VST3LN<0b0010, "vst3.8">; -def VST3LNd16 : VST3LN<0b0110, "vst3.16">; -def VST3LNd32 : VST3LN<0b1010, "vst3.32">; + : NLdStLN<1,0b00,op11_8, (outs), + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, + nohash_imm:$lane), IIC_VST, + !strconcat(OpcodeStr, + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>; + +// vst3 to single-spaced registers. +def VST3LNd8 : VST3LN<0b0010, "vst3.8"> { + let Inst{4} = 0; +} +def VST3LNd16 : VST3LN<0b0110, "vst3.16"> { + let Inst{5-4} = 0b00; +} +def VST3LNd32 : VST3LN<0b1010, "vst3.32"> { + let Inst{6-4} = 0b000; +} // vst3 to double-spaced even registers. -def VST3LNq16a: VST3LN<0b0110, "vst3.16">; -def VST3LNq32a: VST3LN<0b1010, "vst3.32">; +def VST3LNq16a: VST3LN<0b0110, "vst3.16"> { + let Inst{5-4} = 0b10; +} +def VST3LNq32a: VST3LN<0b1010, "vst3.32"> { + let Inst{6-4} = 0b100; +} // vst3 to double-spaced odd registers. -def VST3LNq16b: VST3LN<0b0110, "vst3.16">; -def VST3LNq32b: VST3LN<0b1010, "vst3.32">; +def VST3LNq16b: VST3LN<0b0110, "vst3.16"> { + let Inst{5-4} = 0b10; +} +def VST3LNq32b: VST3LN<0b1010, "vst3.32"> { + let Inst{6-4} = 0b100; +} // VST4LN : Vector Store (single 4-element structure from one lane) class VST4LN op11_8, string OpcodeStr> - : NLdSt<1,0b00,op11_8,0b0000, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, - nohash_imm:$lane), IIC_VST, - !strconcat(OpcodeStr, - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"), - "", []>; + : NLdStLN<1,0b00,op11_8, (outs), + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, + nohash_imm:$lane), IIC_VST, + !strconcat(OpcodeStr, + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"), + "", []>; +// vst4 to single-spaced registers. def VST4LNd8 : VST4LN<0b0011, "vst4.8">; -def VST4LNd16 : VST4LN<0b0111, "vst4.16">; -def VST4LNd32 : VST4LN<0b1011, "vst4.32">; +def VST4LNd16 : VST4LN<0b0111, "vst4.16"> { + let Inst{5} = 0; +} +def VST4LNd32 : VST4LN<0b1011, "vst4.32"> { + let Inst{6} = 0; +} // vst4 to double-spaced even registers. -def VST4LNq16a: VST4LN<0b0111, "vst4.16">; -def VST4LNq32a: VST4LN<0b1011, "vst4.32">; +def VST4LNq16a: VST4LN<0b0111, "vst4.16"> { + let Inst{5} = 1; +} +def VST4LNq32a: VST4LN<0b1011, "vst4.32"> { + let Inst{6} = 1; +} // vst4 to double-spaced odd registers. -def VST4LNq16b: VST4LN<0b0111, "vst4.16">; -def VST4LNq32b: VST4LN<0b1011, "vst4.32">; +def VST4LNq16b: VST4LN<0b0111, "vst4.16"> { + let Inst{5} = 1; +} +def VST4LNq32b: VST4LN<0b1011, "vst4.32"> { + let Inst{6} = 1; +} } // mayStore = 1, hasExtraSrcRegAllocReq = 1 From isanbard at gmail.com Thu Nov 19 13:21:09 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 19 Nov 2009 19:21:09 -0000 Subject: [llvm-commits] [llvm] r89379 - in /llvm/trunk/lib: CodeGen/AsmPrinter/DwarfException.cpp Target/TargetLoweringObjectFile.cpp Message-ID: <200911191921.nAJJL9e7014600@zion.cs.uiuc.edu> Author: void Date: Thu Nov 19 13:21:09 2009 New Revision: 89379 URL: http://llvm.org/viewvc/llvm-project?rev=89379&view=rev Log: Reverting the EH table patches. $ svn merge -c -89279 https://llvm.org/svn/llvm-project/llvm/trunk --- Reverse-merging r89279 into '.': U lib/CodeGen/AsmPrinter/DwarfException.cpp U lib/Target/TargetLoweringObjectFile.cpp $ svn merge -c -89270 https://llvm.org/svn/llvm-project/llvm/trunk --- Reverse-merging r89270 into '.': G lib/CodeGen/AsmPrinter/DwarfException.cpp G lib/Target/TargetLoweringObjectFile.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp?rev=89379&r1=89378&r2=89379&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Thu Nov 19 13:21:09 2009 @@ -727,8 +727,7 @@ // somewhere. This predicate should be moved to a shared location that is // in target-independent code. // - if ((LSDASection->getKind().isWriteable() && - !LSDASection->getKind().isReadOnlyWithRel()) || + if (LSDASection->getKind().isWriteable() || Asm->TM.getRelocationModel() == Reloc::Static) TTypeFormat = dwarf::DW_EH_PE_absptr; else @@ -918,36 +917,14 @@ } // Emit the Catch TypeInfos. - const TargetLoweringObjectFile &TLOF = Asm->getObjFileLowering(); - unsigned Index = 1; - for (std::vector::const_reverse_iterator I = TypeInfos.rbegin(), E = TypeInfos.rend(); I != E; ++I) { - const GlobalVariable *TI = *I; - - if (TI) { - if (!LSDASection->getKind().isReadOnlyWithRel() && - (TTypeFormat == dwarf::DW_EH_PE_absptr || - TI->getLinkage() == GlobalValue::InternalLinkage)) { - // Print out the unadorned name of the type info. - PrintRelDirective(); - O << Asm->Mang->getMangledName(TI); - } else { - bool IsTypeInfoIndirect = false, IsTypeInfoPCRel = false; - const MCExpr *TypeInfoRef = - TLOF.getSymbolForDwarfGlobalReference(TI, Asm->Mang, Asm->MMI, - IsTypeInfoIndirect, - IsTypeInfoPCRel); - - if (!IsTypeInfoPCRel) - TypeInfoRef = CreateLabelDiff(TypeInfoRef, "typeinforef_addr", - Index++); + const GlobalVariable *GV = *I; + PrintRelDirective(); - O << MAI->getData32bitsDirective(); - TypeInfoRef->print(O, MAI); - } + if (GV) { + O << Asm->Mang->getMangledName(GV); } else { - PrintRelDirective(); O << "0x0"; } Modified: llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp?rev=89379&r1=89378&r2=89379&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp (original) +++ llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Thu Nov 19 13:21:09 2009 @@ -783,8 +783,8 @@ } // Exception Handling. - LSDASection = getMachOSection("__TEXT", "__gcc_except_tab", 0, - SectionKind::getReadOnlyWithRel()); + LSDASection = getMachOSection("__DATA", "__gcc_except_tab", 0, + SectionKind::getDataRel()); EHFrameSection = getMachOSection("__TEXT", "__eh_frame", MCSectionMachO::S_COALESCED | From evan.cheng at apple.com Thu Nov 19 13:36:55 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 19 Nov 2009 11:36:55 -0800 Subject: [llvm-commits] [llvm] r89356 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp In-Reply-To: <200911191555.nAJFtnEm007165@zion.cs.uiuc.edu> References: <200911191555.nAJFtnEm007165@zion.cs.uiuc.edu> Message-ID: On Nov 19, 2009, at 7:55 AM, David Greene wrote: > > > + // The queue of recently-used registers. > + SmallVector RecentRegs; Why the odd sized vector? > + > + // Record that we just picked this register. > + void recordRecentlyUsed(unsigned reg) { > + assert(reg != 0 && "Recently used register is NOREG!"); > + if (!RecentRegs.empty()) { > + std::copy(RecentRegs.begin() + 1, RecentRegs.end(), RecentRegs.begin()); > + RecentRegs.back() = reg; This seems extremely slow? Why not pop front and push back? Or just use a fixed size array and keep rotating the begin and end pointers? Evan > + } > + } > + > public: > virtual const char* getPassName() const { > return "Linear Scan Register Allocator"; > @@ -161,6 +194,12 @@ > /// runOnMachineFunction - register allocate the whole function > bool runOnMachineFunction(MachineFunction&); > > + // Determine if we skip this register due to its being recently used. > + bool isRecentlyUsed(unsigned reg) const { > + return std::find(RecentRegs.begin(), RecentRegs.end(), reg) != > + RecentRegs.end(); > + } > + > private: > /// linearScan - the linear scan algorithm > void linearScan(); > @@ -833,9 +872,15 @@ > > namespace { > struct WeightCompare { > + private: > + const RALinScan &Allocator; > + > + public: > + WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {}; > + > typedef std::pair RegWeightPair; > bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const { > - return LHS.second < RHS.second; > + return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first); > } > }; > } > @@ -1079,7 +1124,8 @@ > e = RC->allocation_order_end(*mf_); i != e; ++i) { > unsigned reg = *i; > float regWeight = SpillWeights[reg]; > - if (minWeight > regWeight) > + // Skip recently allocated registers. > + if (minWeight > regWeight && !isRecentlyUsed(reg)) > Found = true; > RegsWeights.push_back(std::make_pair(reg, regWeight)); > } > @@ -1097,7 +1143,7 @@ > } > > // Sort all potential spill candidates by weight. > - std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare()); > + std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this)); > minReg = RegsWeights[0].first; > minWeight = RegsWeights[0].second; > if (minWeight == HUGE_VALF) { > @@ -1360,7 +1406,8 @@ > // Ignore "downgraded" registers. > if (SkipDGRegs && DowngradedRegs.count(Reg)) > continue; > - if (isRegAvail(Reg)) { > + // Skip recently allocated registers. > + if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) { > FreeReg = Reg; > if (FreeReg < inactiveCounts.size()) > FreeRegInactiveCount = inactiveCounts[FreeReg]; > @@ -1372,9 +1419,12 @@ > > // If there are no free regs, or if this reg has the max inactive count, > // return this register. > - if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) > + if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) { > + // Remember what register we picked so we can skip it next time. > + if (FreeReg != 0) recordRecentlyUsed(FreeReg); > return FreeReg; > - > + } > + > // Continue scanning the registers, looking for the one with the highest > // inactive count. Alkis found that this reduced register pressure very > // slightly on X86 (in rev 1.94 of this file), though this should probably be > @@ -1393,6 +1443,9 @@ > } > } > > + // Remember what register we picked so we can skip it next time. > + recordRecentlyUsed(FreeReg); > + > return FreeReg; > } > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stoklund at 2pi.dk Thu Nov 19 13:42:16 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 19 Nov 2009 19:42:16 -0000 Subject: [llvm-commits] [llvm] r89381 - /llvm/trunk/lib/CodeGen/PHIElimination.cpp Message-ID: <200911191942.nAJJgGvI015336@zion.cs.uiuc.edu> Author: stoklund Date: Thu Nov 19 13:42:16 2009 New Revision: 89381 URL: http://llvm.org/viewvc/llvm-project?rev=89381&view=rev Log: Place new basic blocks immediately after their predecessor when splitting critical edges in PHIElimination. This has a huge impact on regalloc performance, and we recover almost all of the 10% compile time regression that edge splitting introduced. Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89381&r1=89380&r2=89381&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Thu Nov 19 13:42:16 2009 @@ -439,21 +439,21 @@ ++NumSplits; MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock(); - MF->push_back(NMBB); + MF->insert(next(MachineFunction::iterator(A)), NMBB); DEBUG(errs() << "PHIElimination splitting critical edge:" " BB#" << A->getNumber() << " -- BB#" << NMBB->getNumber() << " -- BB#" << B->getNumber() << '\n'); A->ReplaceUsesOfBlockWith(B, NMBB); - // If A may fall through to B, we may have to insert a branch. - if (A->isLayoutSuccessor(B)) - A->updateTerminator(); + A->updateTerminator(); - // Insert unconditional "jump B" instruction in NMBB. + // Insert unconditional "jump B" instruction in NMBB if necessary. NMBB->addSuccessor(B); - Cond.clear(); - MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond); + if (!NMBB->isLayoutSuccessor(B)) { + Cond.clear(); + MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond); + } // Fix PHI nodes in B so they refer to NMBB instead of A for (MachineBasicBlock::iterator i = B->begin(), e = B->end(); From bob.wilson at apple.com Thu Nov 19 13:42:40 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 19 Nov 2009 11:42:40 -0800 Subject: [llvm-commits] [llvm] r89377 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td In-Reply-To: <200911191920.nAJJKHmV014543@zion.cs.uiuc.edu> References: <200911191920.nAJJKHmV014543@zion.cs.uiuc.edu> Message-ID: <9F2BD57D-299A-4267-BF7C-A2969C90E75B@apple.com> This is fine for now. Is there any reason why we can't revert it (and similar changes that went in a while back) once pr5470 is fixed? We should be able to specify that some of the opcode bits are undefined without having to define separate instruction classes. I will try to fix that PR asap. On Nov 19, 2009, at 11:20 AM, Johnny Chen wrote: > Author: johnny > Date: Thu Nov 19 13:20:17 2009 > New Revision: 89377 > > URL: http://llvm.org/viewvc/llvm-project?rev=89377&view=rev > Log: > Added NLdStLN which is similar to NLdSt with the exception that > op7_4 is not > fully specified at this level. Subclasses of NLdStLN can specify > selective > bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* > inside > ARMInstrNEON.td. > > Modified: > llvm/trunk/lib/Target/ARM/ARMInstrFormats.td > llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=89377&r1=89376&r2=89377&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Nov 19 13:20:17 > 2009 > @@ -1245,6 +1245,17 @@ > let Inst{7-4} = op7_4; > } > > +// With selective bit(s) from op7_4 specified by subclasses. > +class NLdStLN op21_20, bits<4> op11_8, > + dag oops, dag iops, InstrItinClass itin, > + string asm, string cstr, list pattern> > + : NeonI pattern> { > + let Inst{31-24} = 0b11110100; > + let Inst{23} = op23; > + let Inst{21-20} = op21_20; > + let Inst{11-8} = op11_8; > +} > + > class NDataI string asm, string cstr, list pattern> > : NeonI pattern> { > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=89377&r1=89376&r2=89377&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Nov 19 13:20:17 2009 > @@ -280,66 +280,107 @@ > > // VLD2LN : Vector Load (single 2-element structure to one lane) > class VLD2LN op11_8, string OpcodeStr> > - : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2), > - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm: > $lane), > - IIC_VLD2, > - !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, > $addr"), > - "$src1 = $dst1, $src2 = $dst2", []>; > + : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2), > + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm: > $lane), > + IIC_VLD2, > + !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\ > \}, $addr"), > + "$src1 = $dst1, $src2 = $dst2", []>; > > +// vld2 to single-spaced registers. > def VLD2LNd8 : VLD2LN<0b0001, "vld2.8">; > -def VLD2LNd16 : VLD2LN<0b0101, "vld2.16">; > -def VLD2LNd32 : VLD2LN<0b1001, "vld2.32">; > +def VLD2LNd16 : VLD2LN<0b0101, "vld2.16"> { > + let Inst{5} = 0; > +} > +def VLD2LNd32 : VLD2LN<0b1001, "vld2.32"> { > + let Inst{6} = 0; > +} > > // vld2 to double-spaced even registers. > -def VLD2LNq16a: VLD2LN<0b0101, "vld2.16">; > -def VLD2LNq32a: VLD2LN<0b1001, "vld2.32">; > +def VLD2LNq16a: VLD2LN<0b0101, "vld2.16"> { > + let Inst{5} = 1; > +} > +def VLD2LNq32a: VLD2LN<0b1001, "vld2.32"> { > + let Inst{6} = 1; > +} > > // vld2 to double-spaced odd registers. > -def VLD2LNq16b: VLD2LN<0b0101, "vld2.16">; > -def VLD2LNq32b: VLD2LN<0b1001, "vld2.32">; > +def VLD2LNq16b: VLD2LN<0b0101, "vld2.16"> { > + let Inst{5} = 1; > +} > +def VLD2LNq32b: VLD2LN<0b1001, "vld2.32"> { > + let Inst{6} = 1; > +} > > // VLD3LN : Vector Load (single 3-element structure to one lane) > class VLD3LN op11_8, string OpcodeStr> > - : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2, DPR: > $dst3), > - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, > - nohash_imm:$lane), IIC_VLD3, > - !strconcat(OpcodeStr, > - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"), > - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>; > - > -def VLD3LNd8 : VLD3LN<0b0010, "vld3.8">; > -def VLD3LNd16 : VLD3LN<0b0110, "vld3.16">; > -def VLD3LNd32 : VLD3LN<0b1010, "vld3.32">; > + : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), > + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, > + nohash_imm:$lane), IIC_VLD3, > + !strconcat(OpcodeStr, > + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"), > + "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>; > + > +// vld3 to single-spaced registers. > +def VLD3LNd8 : VLD3LN<0b0010, "vld3.8"> { > + let Inst{4} = 0; > +} > +def VLD3LNd16 : VLD3LN<0b0110, "vld3.16"> { > + let Inst{5-4} = 0b00; > +} > +def VLD3LNd32 : VLD3LN<0b1010, "vld3.32"> { > + let Inst{6-4} = 0b000; > +} > > // vld3 to double-spaced even registers. > -def VLD3LNq16a: VLD3LN<0b0110, "vld3.16">; > -def VLD3LNq32a: VLD3LN<0b1010, "vld3.32">; > +def VLD3LNq16a: VLD3LN<0b0110, "vld3.16"> { > + let Inst{5-4} = 0b10; > +} > +def VLD3LNq32a: VLD3LN<0b1010, "vld3.32"> { > + let Inst{6-4} = 0b100; > +} > > // vld3 to double-spaced odd registers. > -def VLD3LNq16b: VLD3LN<0b0110, "vld3.16">; > -def VLD3LNq32b: VLD3LN<0b1010, "vld3.32">; > +def VLD3LNq16b: VLD3LN<0b0110, "vld3.16"> { > + let Inst{5-4} = 0b10; > +} > +def VLD3LNq32b: VLD3LN<0b1010, "vld3.32"> { > + let Inst{6-4} = 0b100; > +} > > // VLD4LN : Vector Load (single 4-element structure to one lane) > class VLD4LN op11_8, string OpcodeStr> > - : NLdSt<1,0b10,op11_8,0b0000, > - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), > - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, > DPR:$src4, > - nohash_imm:$lane), IIC_VLD4, > - !strconcat(OpcodeStr, > - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\ > \}, $addr"), > - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = > $dst4", []>; > + : NLdStLN<1,0b10,op11_8, > + (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), > + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, > DPR:$src4, > + nohash_imm:$lane), IIC_VLD4, > + !strconcat(OpcodeStr, > + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4 > [$lane]\\}, $addr"), > + "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = > $dst4", []>; > > +// vld4 to single-spaced registers. > def VLD4LNd8 : VLD4LN<0b0011, "vld4.8">; > -def VLD4LNd16 : VLD4LN<0b0111, "vld4.16">; > -def VLD4LNd32 : VLD4LN<0b1011, "vld4.32">; > +def VLD4LNd16 : VLD4LN<0b0111, "vld4.16"> { > + let Inst{5} = 0; > +} > +def VLD4LNd32 : VLD4LN<0b1011, "vld4.32"> { > + let Inst{6} = 0; > +} > > // vld4 to double-spaced even registers. > -def VLD4LNq16a: VLD4LN<0b0111, "vld4.16">; > -def VLD4LNq32a: VLD4LN<0b1011, "vld4.32">; > +def VLD4LNq16a: VLD4LN<0b0111, "vld4.16"> { > + let Inst{5} = 1; > +} > +def VLD4LNq32a: VLD4LN<0b1011, "vld4.32"> { > + let Inst{6} = 1; > +} > > // vld4 to double-spaced odd registers. > -def VLD4LNq16b: VLD4LN<0b0111, "vld4.16">; > -def VLD4LNq32b: VLD4LN<0b1011, "vld4.32">; > +def VLD4LNq16b: VLD4LN<0b0111, "vld4.16"> { > + let Inst{5} = 1; > +} > +def VLD4LNq32b: VLD4LN<0b1011, "vld4.32"> { > + let Inst{6} = 1; > +} > > // VLD1DUP : Vector Load (single element to all lanes) > // VLD2DUP : Vector Load (single 2-element structure to all lanes) > @@ -463,64 +504,105 @@ > > // VST2LN : Vector Store (single 2-element structure from one > lane) > class VST2LN op11_8, string OpcodeStr> > - : NLdSt<1,0b00,op11_8,0b0000, (outs), > - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm: > $lane), > - IIC_VST, > - !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, > $addr"), > - "", []>; > + : NLdStLN<1,0b00,op11_8, (outs), > + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm: > $lane), > + IIC_VST, > + !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\ > \}, $addr"), > + "", []>; > > +// vst2 to single-spaced registers. > def VST2LNd8 : VST2LN<0b0001, "vst2.8">; > -def VST2LNd16 : VST2LN<0b0101, "vst2.16">; > -def VST2LNd32 : VST2LN<0b1001, "vst2.32">; > +def VST2LNd16 : VST2LN<0b0101, "vst2.16"> { > + let Inst{5} = 0; > +} > +def VST2LNd32 : VST2LN<0b1001, "vst2.32"> { > + let Inst{6} = 0; > +} > > // vst2 to double-spaced even registers. > -def VST2LNq16a: VST2LN<0b0101, "vst2.16">; > -def VST2LNq32a: VST2LN<0b1001, "vst2.32">; > +def VST2LNq16a: VST2LN<0b0101, "vst2.16"> { > + let Inst{5} = 1; > +} > +def VST2LNq32a: VST2LN<0b1001, "vst2.32"> { > + let Inst{6} = 1; > +} > > // vst2 to double-spaced odd registers. > -def VST2LNq16b: VST2LN<0b0101, "vst2.16">; > -def VST2LNq32b: VST2LN<0b1001, "vst2.32">; > +def VST2LNq16b: VST2LN<0b0101, "vst2.16"> { > + let Inst{5} = 1; > +} > +def VST2LNq32b: VST2LN<0b1001, "vst2.32"> { > + let Inst{6} = 1; > +} > > // VST3LN : Vector Store (single 3-element structure from one > lane) > class VST3LN op11_8, string OpcodeStr> > - : NLdSt<1,0b00,op11_8,0b0000, (outs), > - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, > - nohash_imm:$lane), IIC_VST, > - !strconcat(OpcodeStr, > - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), > "", []>; > - > -def VST3LNd8 : VST3LN<0b0010, "vst3.8">; > -def VST3LNd16 : VST3LN<0b0110, "vst3.16">; > -def VST3LNd32 : VST3LN<0b1010, "vst3.32">; > + : NLdStLN<1,0b00,op11_8, (outs), > + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, > + nohash_imm:$lane), IIC_VST, > + !strconcat(OpcodeStr, > + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, > $addr"), "", []>; > + > +// vst3 to single-spaced registers. > +def VST3LNd8 : VST3LN<0b0010, "vst3.8"> { > + let Inst{4} = 0; > +} > +def VST3LNd16 : VST3LN<0b0110, "vst3.16"> { > + let Inst{5-4} = 0b00; > +} > +def VST3LNd32 : VST3LN<0b1010, "vst3.32"> { > + let Inst{6-4} = 0b000; > +} > > // vst3 to double-spaced even registers. > -def VST3LNq16a: VST3LN<0b0110, "vst3.16">; > -def VST3LNq32a: VST3LN<0b1010, "vst3.32">; > +def VST3LNq16a: VST3LN<0b0110, "vst3.16"> { > + let Inst{5-4} = 0b10; > +} > +def VST3LNq32a: VST3LN<0b1010, "vst3.32"> { > + let Inst{6-4} = 0b100; > +} > > // vst3 to double-spaced odd registers. > -def VST3LNq16b: VST3LN<0b0110, "vst3.16">; > -def VST3LNq32b: VST3LN<0b1010, "vst3.32">; > +def VST3LNq16b: VST3LN<0b0110, "vst3.16"> { > + let Inst{5-4} = 0b10; > +} > +def VST3LNq32b: VST3LN<0b1010, "vst3.32"> { > + let Inst{6-4} = 0b100; > +} > > // VST4LN : Vector Store (single 4-element structure from one > lane) > class VST4LN op11_8, string OpcodeStr> > - : NLdSt<1,0b00,op11_8,0b0000, (outs), > - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, > DPR:$src4, > - nohash_imm:$lane), IIC_VST, > - !strconcat(OpcodeStr, > - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\ > \}, $addr"), > - "", []>; > + : NLdStLN<1,0b00,op11_8, (outs), > + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, > DPR:$src4, > + nohash_imm:$lane), IIC_VST, > + !strconcat(OpcodeStr, > + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4 > [$lane]\\}, $addr"), > + "", []>; > > +// vst4 to single-spaced registers. > def VST4LNd8 : VST4LN<0b0011, "vst4.8">; > -def VST4LNd16 : VST4LN<0b0111, "vst4.16">; > -def VST4LNd32 : VST4LN<0b1011, "vst4.32">; > +def VST4LNd16 : VST4LN<0b0111, "vst4.16"> { > + let Inst{5} = 0; > +} > +def VST4LNd32 : VST4LN<0b1011, "vst4.32"> { > + let Inst{6} = 0; > +} > > // vst4 to double-spaced even registers. > -def VST4LNq16a: VST4LN<0b0111, "vst4.16">; > -def VST4LNq32a: VST4LN<0b1011, "vst4.32">; > +def VST4LNq16a: VST4LN<0b0111, "vst4.16"> { > + let Inst{5} = 1; > +} > +def VST4LNq32a: VST4LN<0b1011, "vst4.32"> { > + let Inst{6} = 1; > +} > > // vst4 to double-spaced odd registers. > -def VST4LNq16b: VST4LN<0b0111, "vst4.16">; > -def VST4LNq32b: VST4LN<0b1011, "vst4.32">; > +def VST4LNq16b: VST4LN<0b0111, "vst4.16"> { > + let Inst{5} = 1; > +} > +def VST4LNq32b: VST4LN<0b1011, "vst4.32"> { > + let Inst{6} = 1; > +} > > } // mayStore = 1, hasExtraSrcRegAllocReq = 1 > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From vkutuzov at accesssoftek.com Thu Nov 19 13:44:28 2009 From: vkutuzov at accesssoftek.com (Viktor Kutuzov) Date: Thu, 19 Nov 2009 11:44:28 -0800 Subject: [llvm-commits] [PATCH] LTO code generator options References: <04F6B1512E264B27AEE607542FCDD113@andreic6e7fe55> <38a0d8450911121059n6a0d3eb0ka34711d931c7675e@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BA@mail.accesssoftek.com> <38a0d8450911141921r7deec8b3k91e06950263f0485@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BF@mail.accesssoftek.com> <38a0d8450911170809j6a32716ar840b8622cfad6f17@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607C4@mail.accesssoftek.com> <38a0d8450911180722j5a463fa8hec81178154deaf09@mail.gmail.com> <41BA1AA405BC4D19BA9B4FAB6543D62F@andreic6e7fe55> <38a0d8450911190723g644ad4c7ife769ab35da9efb9@mail.gmail.com> Message-ID: Hello Rafael, > Can you give the StringRef::split method a try? StringRef::split would do. The issue here is: SubtargetFeatures class uses std::strings and has a helper method Split which is used in few other places. I'm trying to follow this. I don't like the idea to use StringRef::split only in this particular place. However, I wouldn't mind to re-factor the SubtargetFeatures class to use StringRef instead of std::strings and prepare another patch. Shell I do so? > You say features are normalized, why does hasFeature needs to convert > to lowercase and strip flags? Features are normalized inside the SubtargetFeatures class. hasFeature gets a string which also should be normalized to compare with the already normalized features. We need to strip the flag because we do not care was this feature set on or off, we simply want to know if it was set or not. But if you have the question, I'll better add a comment there to clarify this. How about something like this: "Normalize the given string to compare with the normalized features, and strip the flag since we are checking was this feature set at all without checking was it set on or off."? > The comment about "after all explicit feature settings" is a future > reference, right? I don't see any feature being set :-) You are right. This is a future reference. Next patch will add explicit settings of cpu and attributes. We just need to get there. :) > The method SubtargetFeatures::AddFeatures(const cl::list > &List) is not being used, is it? I didn't find a way to add the usage in this patch without adding a lot of other changes to get it work. This will be in the next patch and the usage will look like this in the LTOCodeGenerator.cpp file: ... +static cl::list MAttrs("mattr", + cl::CommaSeparated, + cl::desc("Target specific attributes (see -mattr=help for details)"), + cl::value_desc("a1,+a2,-a3,...")); + ... bool LTOCodeGenerator::determineTarget(std::string& errMsg) ... + // Prepare subtarget feature set for the given command line options. + SubtargetFeatures features; ... + if (!MAttrs.empty()) + features.AddFeatures(MAttrs); + + // Set the rest of features by default. + // Note: Please keep this after all explict feature settings to make sure + // defaults will not override explicitly set options. + features.AddFeatures(SubtargetFeatures::getDefaultSubTargetTripleFeatures(_targetTriple)); ... Which also fill that "keep this after all explict feature settings" comment with meaning. Is it Ok to ssubmit this patch? Cheers, Viktor ----- Original Message ----- From: "Rafael Espindola" To: "Viktor Kutuzov" Cc: "Nick Lewycky" ; "Commit Messages and Patches for LLVM" Sent: Thursday, November 19, 2009 7:23 AM Subject: Re: [llvm-commits] [PATCH] LTO code generator options >> This patch adds two SubtargetFeatures::AddFeatures methods which accept a >> comma-separated string or already parsed command line parameters as input, >> SubtargetFeatures::hasFeature method which cheks if given feature is already >> set, and some code re-factoring to use these new methods. > > Can you give the StringRef::split method a try? > > You say features are normalized, why does hasFeature needs to convert > to lowercase and strip flags? > > The comment about "after all explicit feature settings" is a future > reference, right? I don't see any feature being set :-) > > The method SubtargetFeatures::AddFeatures(const cl::list > &List) is not being used, is it? > >> Best regards, >> Viktor > > Cheers, > -- > Rafael ?vila de Esp?ndola > From johnny.chen at apple.com Thu Nov 19 14:01:37 2009 From: johnny.chen at apple.com (Johnny Chen) Date: Thu, 19 Nov 2009 12:01:37 -0800 Subject: [llvm-commits] [llvm] r89377 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td In-Reply-To: <9F2BD57D-299A-4267-BF7C-A2969C90E75B@apple.com> References: <200911191920.nAJJKHmV014543@zion.cs.uiuc.edu> <9F2BD57D-299A-4267-BF7C-A2969C90E75B@apple.com> Message-ID: <53A487A4-FAB5-4AEE-BD5A-F54301B3FE3E@apple.com> Hi Bob, If there is a more elegant way to specify this information, I'm more than willing to revert the patch. However, I see no other way to specify that, for example: // VST4LN : Vector Store (single 4-element structure from one lane) class VST4LN op11_8, string OpcodeStr> : NLdStLN<1,0b00,op11_8, (outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VST, !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"), "", []>; // vst4 to single-spaced registers. def VST4LNd8 : VST4LN<0b0011, "vst4.8">; def VST4LNd16 : VST4LN<0b0111, "vst4.16"> { let Inst{5} = 0; } def VST4LNd32 : VST4LN<0b1011, "vst4.32"> { let Inst{6} = 0; } // vst4 to double-spaced even registers. def VST4LNq16a: VST4LN<0b0111, "vst4.16"> { let Inst{5} = 1; } def VST4LNq32a: VST4LN<0b1011, "vst4.32"> { let Inst{6} = 1; } // vst4 to double-spaced odd registers. def VST4LNq16b: VST4LN<0b0111, "vst4.16"> { let Inst{5} = 1; } def VST4LNq32b: VST4LN<0b1011, "vst4.32"> { let Inst{6} = 1; } That is, the selective bit position(s) to overwrite vary depending on the data size of the instructions. How do I view pr5470? Thanks. On Nov 19, 2009, at 11:42 AM, Bob Wilson wrote: > This is fine for now. Is there any reason why we can't revert it (and similar changes that went in a while back) once pr5470 is fixed? We should be able to specify that some of the opcode bits are undefined without having to define separate instruction classes. > > I will try to fix that PR asap. > > On Nov 19, 2009, at 11:20 AM, Johnny Chen wrote: > >> Author: johnny >> Date: Thu Nov 19 13:20:17 2009 >> New Revision: 89377 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=89377&view=rev >> Log: >> Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not >> fully specified at this level. Subclasses of NLdStLN can specify selective >> bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside >> ARMInstrNEON.td. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td >> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=89377&r1=89376&r2=89377&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Nov 19 13:20:17 2009 >> @@ -1245,6 +1245,17 @@ >> let Inst{7-4} = op7_4; >> } >> >> +// With selective bit(s) from op7_4 specified by subclasses. >> +class NLdStLN op21_20, bits<4> op11_8, >> + dag oops, dag iops, InstrItinClass itin, >> + string asm, string cstr, list pattern> >> + : NeonI { >> + let Inst{31-24} = 0b11110100; >> + let Inst{23} = op23; >> + let Inst{21-20} = op21_20; >> + let Inst{11-8} = op11_8; >> +} >> + >> class NDataI> string asm, string cstr, list pattern> >> : NeonI { >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=89377&r1=89376&r2=89377&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Nov 19 13:20:17 2009 >> @@ -280,66 +280,107 @@ >> >> // VLD2LN : Vector Load (single 2-element structure to one lane) >> class VLD2LN op11_8, string OpcodeStr> >> - : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2), >> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), >> - IIC_VLD2, >> - !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"), >> - "$src1 = $dst1, $src2 = $dst2", []>; >> + : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2), >> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), >> + IIC_VLD2, >> + !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"), >> + "$src1 = $dst1, $src2 = $dst2", []>; >> >> +// vld2 to single-spaced registers. >> def VLD2LNd8 : VLD2LN<0b0001, "vld2.8">; >> -def VLD2LNd16 : VLD2LN<0b0101, "vld2.16">; >> -def VLD2LNd32 : VLD2LN<0b1001, "vld2.32">; >> +def VLD2LNd16 : VLD2LN<0b0101, "vld2.16"> { >> + let Inst{5} = 0; >> +} >> +def VLD2LNd32 : VLD2LN<0b1001, "vld2.32"> { >> + let Inst{6} = 0; >> +} >> >> // vld2 to double-spaced even registers. >> -def VLD2LNq16a: VLD2LN<0b0101, "vld2.16">; >> -def VLD2LNq32a: VLD2LN<0b1001, "vld2.32">; >> +def VLD2LNq16a: VLD2LN<0b0101, "vld2.16"> { >> + let Inst{5} = 1; >> +} >> +def VLD2LNq32a: VLD2LN<0b1001, "vld2.32"> { >> + let Inst{6} = 1; >> +} >> >> // vld2 to double-spaced odd registers. >> -def VLD2LNq16b: VLD2LN<0b0101, "vld2.16">; >> -def VLD2LNq32b: VLD2LN<0b1001, "vld2.32">; >> +def VLD2LNq16b: VLD2LN<0b0101, "vld2.16"> { >> + let Inst{5} = 1; >> +} >> +def VLD2LNq32b: VLD2LN<0b1001, "vld2.32"> { >> + let Inst{6} = 1; >> +} >> >> // VLD3LN : Vector Load (single 3-element structure to one lane) >> class VLD3LN op11_8, string OpcodeStr> >> - : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), >> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, >> - nohash_imm:$lane), IIC_VLD3, >> - !strconcat(OpcodeStr, >> - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"), >> - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>; >> - >> -def VLD3LNd8 : VLD3LN<0b0010, "vld3.8">; >> -def VLD3LNd16 : VLD3LN<0b0110, "vld3.16">; >> -def VLD3LNd32 : VLD3LN<0b1010, "vld3.32">; >> + : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), >> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, >> + nohash_imm:$lane), IIC_VLD3, >> + !strconcat(OpcodeStr, >> + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"), >> + "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>; >> + >> +// vld3 to single-spaced registers. >> +def VLD3LNd8 : VLD3LN<0b0010, "vld3.8"> { >> + let Inst{4} = 0; >> +} >> +def VLD3LNd16 : VLD3LN<0b0110, "vld3.16"> { >> + let Inst{5-4} = 0b00; >> +} >> +def VLD3LNd32 : VLD3LN<0b1010, "vld3.32"> { >> + let Inst{6-4} = 0b000; >> +} >> >> // vld3 to double-spaced even registers. >> -def VLD3LNq16a: VLD3LN<0b0110, "vld3.16">; >> -def VLD3LNq32a: VLD3LN<0b1010, "vld3.32">; >> +def VLD3LNq16a: VLD3LN<0b0110, "vld3.16"> { >> + let Inst{5-4} = 0b10; >> +} >> +def VLD3LNq32a: VLD3LN<0b1010, "vld3.32"> { >> + let Inst{6-4} = 0b100; >> +} >> >> // vld3 to double-spaced odd registers. >> -def VLD3LNq16b: VLD3LN<0b0110, "vld3.16">; >> -def VLD3LNq32b: VLD3LN<0b1010, "vld3.32">; >> +def VLD3LNq16b: VLD3LN<0b0110, "vld3.16"> { >> + let Inst{5-4} = 0b10; >> +} >> +def VLD3LNq32b: VLD3LN<0b1010, "vld3.32"> { >> + let Inst{6-4} = 0b100; >> +} >> >> // VLD4LN : Vector Load (single 4-element structure to one lane) >> class VLD4LN op11_8, string OpcodeStr> >> - : NLdSt<1,0b10,op11_8,0b0000, >> - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), >> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, >> - nohash_imm:$lane), IIC_VLD4, >> - !strconcat(OpcodeStr, >> - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"), >> - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>; >> + : NLdStLN<1,0b10,op11_8, >> + (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), >> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, >> + nohash_imm:$lane), IIC_VLD4, >> + !strconcat(OpcodeStr, >> + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"), >> + "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>; >> >> +// vld4 to single-spaced registers. >> def VLD4LNd8 : VLD4LN<0b0011, "vld4.8">; >> -def VLD4LNd16 : VLD4LN<0b0111, "vld4.16">; >> -def VLD4LNd32 : VLD4LN<0b1011, "vld4.32">; >> +def VLD4LNd16 : VLD4LN<0b0111, "vld4.16"> { >> + let Inst{5} = 0; >> +} >> +def VLD4LNd32 : VLD4LN<0b1011, "vld4.32"> { >> + let Inst{6} = 0; >> +} >> >> // vld4 to double-spaced even registers. >> -def VLD4LNq16a: VLD4LN<0b0111, "vld4.16">; >> -def VLD4LNq32a: VLD4LN<0b1011, "vld4.32">; >> +def VLD4LNq16a: VLD4LN<0b0111, "vld4.16"> { >> + let Inst{5} = 1; >> +} >> +def VLD4LNq32a: VLD4LN<0b1011, "vld4.32"> { >> + let Inst{6} = 1; >> +} >> >> // vld4 to double-spaced odd registers. >> -def VLD4LNq16b: VLD4LN<0b0111, "vld4.16">; >> -def VLD4LNq32b: VLD4LN<0b1011, "vld4.32">; >> +def VLD4LNq16b: VLD4LN<0b0111, "vld4.16"> { >> + let Inst{5} = 1; >> +} >> +def VLD4LNq32b: VLD4LN<0b1011, "vld4.32"> { >> + let Inst{6} = 1; >> +} >> >> // VLD1DUP : Vector Load (single element to all lanes) >> // VLD2DUP : Vector Load (single 2-element structure to all lanes) >> @@ -463,64 +504,105 @@ >> >> // VST2LN : Vector Store (single 2-element structure from one lane) >> class VST2LN op11_8, string OpcodeStr> >> - : NLdSt<1,0b00,op11_8,0b0000, (outs), >> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), >> - IIC_VST, >> - !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"), >> - "", []>; >> + : NLdStLN<1,0b00,op11_8, (outs), >> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), >> + IIC_VST, >> + !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"), >> + "", []>; >> >> +// vst2 to single-spaced registers. >> def VST2LNd8 : VST2LN<0b0001, "vst2.8">; >> -def VST2LNd16 : VST2LN<0b0101, "vst2.16">; >> -def VST2LNd32 : VST2LN<0b1001, "vst2.32">; >> +def VST2LNd16 : VST2LN<0b0101, "vst2.16"> { >> + let Inst{5} = 0; >> +} >> +def VST2LNd32 : VST2LN<0b1001, "vst2.32"> { >> + let Inst{6} = 0; >> +} >> >> // vst2 to double-spaced even registers. >> -def VST2LNq16a: VST2LN<0b0101, "vst2.16">; >> -def VST2LNq32a: VST2LN<0b1001, "vst2.32">; >> +def VST2LNq16a: VST2LN<0b0101, "vst2.16"> { >> + let Inst{5} = 1; >> +} >> +def VST2LNq32a: VST2LN<0b1001, "vst2.32"> { >> + let Inst{6} = 1; >> +} >> >> // vst2 to double-spaced odd registers. >> -def VST2LNq16b: VST2LN<0b0101, "vst2.16">; >> -def VST2LNq32b: VST2LN<0b1001, "vst2.32">; >> +def VST2LNq16b: VST2LN<0b0101, "vst2.16"> { >> + let Inst{5} = 1; >> +} >> +def VST2LNq32b: VST2LN<0b1001, "vst2.32"> { >> + let Inst{6} = 1; >> +} >> >> // VST3LN : Vector Store (single 3-element structure from one lane) >> class VST3LN op11_8, string OpcodeStr> >> - : NLdSt<1,0b00,op11_8,0b0000, (outs), >> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, >> - nohash_imm:$lane), IIC_VST, >> - !strconcat(OpcodeStr, >> - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>; >> - >> -def VST3LNd8 : VST3LN<0b0010, "vst3.8">; >> -def VST3LNd16 : VST3LN<0b0110, "vst3.16">; >> -def VST3LNd32 : VST3LN<0b1010, "vst3.32">; >> + : NLdStLN<1,0b00,op11_8, (outs), >> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, >> + nohash_imm:$lane), IIC_VST, >> + !strconcat(OpcodeStr, >> + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>; >> + >> +// vst3 to single-spaced registers. >> +def VST3LNd8 : VST3LN<0b0010, "vst3.8"> { >> + let Inst{4} = 0; >> +} >> +def VST3LNd16 : VST3LN<0b0110, "vst3.16"> { >> + let Inst{5-4} = 0b00; >> +} >> +def VST3LNd32 : VST3LN<0b1010, "vst3.32"> { >> + let Inst{6-4} = 0b000; >> +} >> >> // vst3 to double-spaced even registers. >> -def VST3LNq16a: VST3LN<0b0110, "vst3.16">; >> -def VST3LNq32a: VST3LN<0b1010, "vst3.32">; >> +def VST3LNq16a: VST3LN<0b0110, "vst3.16"> { >> + let Inst{5-4} = 0b10; >> +} >> +def VST3LNq32a: VST3LN<0b1010, "vst3.32"> { >> + let Inst{6-4} = 0b100; >> +} >> >> // vst3 to double-spaced odd registers. >> -def VST3LNq16b: VST3LN<0b0110, "vst3.16">; >> -def VST3LNq32b: VST3LN<0b1010, "vst3.32">; >> +def VST3LNq16b: VST3LN<0b0110, "vst3.16"> { >> + let Inst{5-4} = 0b10; >> +} >> +def VST3LNq32b: VST3LN<0b1010, "vst3.32"> { >> + let Inst{6-4} = 0b100; >> +} >> >> // VST4LN : Vector Store (single 4-element structure from one lane) >> class VST4LN op11_8, string OpcodeStr> >> - : NLdSt<1,0b00,op11_8,0b0000, (outs), >> - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, >> - nohash_imm:$lane), IIC_VST, >> - !strconcat(OpcodeStr, >> - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"), >> - "", []>; >> + : NLdStLN<1,0b00,op11_8, (outs), >> + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, >> + nohash_imm:$lane), IIC_VST, >> + !strconcat(OpcodeStr, >> + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"), >> + "", []>; >> >> +// vst4 to single-spaced registers. >> def VST4LNd8 : VST4LN<0b0011, "vst4.8">; >> -def VST4LNd16 : VST4LN<0b0111, "vst4.16">; >> -def VST4LNd32 : VST4LN<0b1011, "vst4.32">; >> +def VST4LNd16 : VST4LN<0b0111, "vst4.16"> { >> + let Inst{5} = 0; >> +} >> +def VST4LNd32 : VST4LN<0b1011, "vst4.32"> { >> + let Inst{6} = 0; >> +} >> >> // vst4 to double-spaced even registers. >> -def VST4LNq16a: VST4LN<0b0111, "vst4.16">; >> -def VST4LNq32a: VST4LN<0b1011, "vst4.32">; >> +def VST4LNq16a: VST4LN<0b0111, "vst4.16"> { >> + let Inst{5} = 1; >> +} >> +def VST4LNq32a: VST4LN<0b1011, "vst4.32"> { >> + let Inst{6} = 1; >> +} >> >> // vst4 to double-spaced odd registers. >> -def VST4LNq16b: VST4LN<0b0111, "vst4.16">; >> -def VST4LNq32b: VST4LN<0b1011, "vst4.32">; >> +def VST4LNq16b: VST4LN<0b0111, "vst4.16"> { >> + let Inst{5} = 1; >> +} >> +def VST4LNq32b: VST4LN<0b1011, "vst4.32"> { >> + let Inst{6} = 1; >> +} >> >> } // mayStore = 1, hasExtraSrcRegAllocReq = 1 >> >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From baldrick at free.fr Thu Nov 19 14:48:15 2009 From: baldrick at free.fr (Duncan Sands) Date: Thu, 19 Nov 2009 20:48:15 -0000 Subject: [llvm-commits] [llvm] r89385 - /llvm/trunk/unittests/ADT/ValueMapTest.cpp Message-ID: <200911192048.nAJKmFcs017598@zion.cs.uiuc.edu> Author: baldrick Date: Thu Nov 19 14:48:14 2009 New Revision: 89385 URL: http://llvm.org/viewvc/llvm-project?rev=89385&view=rev Log: Only run this mutex test if threading is enabled. This fixes PR5395. Modified: llvm/trunk/unittests/ADT/ValueMapTest.cpp Modified: llvm/trunk/unittests/ADT/ValueMapTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/ValueMapTest.cpp?rev=89385&r1=89384&r2=89385&view=diff ============================================================================== --- llvm/trunk/unittests/ADT/ValueMapTest.cpp (original) +++ llvm/trunk/unittests/ADT/ValueMapTest.cpp Thu Nov 19 14:48:14 2009 @@ -11,6 +11,7 @@ #include "llvm/Instructions.h" #include "llvm/LLVMContext.h" #include "llvm/ADT/OwningPtr.h" +#include "llvm/Config/config.h" #include "gtest/gtest.h" @@ -193,6 +194,7 @@ } static sys::Mutex *getMutex(const ExtraData &Data) { return Data.M; } }; +#if ENABLE_THREADS TYPED_TEST(ValueMapTest, LocksMutex) { sys::Mutex M(false); // Not recursive. bool CalledRAUW = false, CalledDeleted = false; @@ -205,6 +207,7 @@ EXPECT_TRUE(CalledRAUW); EXPECT_TRUE(CalledDeleted); } +#endif template struct NoFollow : ValueMapConfig { From bob.wilson at apple.com Thu Nov 19 15:02:12 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 19 Nov 2009 13:02:12 -0800 Subject: [llvm-commits] [llvm] r89377 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td In-Reply-To: <53A487A4-FAB5-4AEE-BD5A-F54301B3FE3E@apple.com> References: <200911191920.nAJJKHmV014543@zion.cs.uiuc.edu> <9F2BD57D-299A-4267-BF7C-A2969C90E75B@apple.com> <53A487A4-FAB5-4AEE-BD5A-F54301B3FE3E@apple.com> Message-ID: On Nov 19, 2009, at 12:01 PM, Johnny Chen wrote: > Hi Bob, > > If there is a more elegant way to specify this information, I'm more > than willing to revert the patch. > However, I see no other way to specify that, for example: > > // VST4LN : Vector Store (single 4-element structure from one > lane) > class VST4LN op11_8, string OpcodeStr> > : NLdStLN<1,0b00,op11_8, (outs), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, > DPR:$src4, > nohash_imm:$lane), IIC_VST, > !strconcat(OpcodeStr, > "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\ > \}, $addr"), > "", []>; We should be able to use NLdSt and set op7_4 to "{?,?,?,?}". The rest of your change would stay the same. > How do I view pr5470? http://llvm.org/bugs/show_bug.cgi?id=5470 From dag at cray.com Thu Nov 19 15:10:53 2009 From: dag at cray.com (David Greene) Date: Thu, 19 Nov 2009 15:10:53 -0600 Subject: [llvm-commits] [llvm] r89356 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp In-Reply-To: References: <200911191555.nAJFtnEm007165@zion.cs.uiuc.edu> Message-ID: <200911191510.53618.dag@cray.com> On Thursday 19 November 2009 13:36, Evan Cheng wrote: > On Nov 19, 2009, at 7:55 AM, David Greene wrote: > > + // The queue of recently-used registers. > > + SmallVector RecentRegs; > > Why the odd sized vector? Why not? We have the queue sized to three in our code. I can change it if you'd like. It's an arbitrary choice. > > + > > + // Record that we just picked this register. > > + void recordRecentlyUsed(unsigned reg) { > > + assert(reg != 0 && "Recently used register is NOREG!"); > > + if (!RecentRegs.empty()) { > > + std::copy(RecentRegs.begin() + 1, RecentRegs.end(), > > RecentRegs.begin()); + RecentRegs.back() = reg; > > This seems extremely slow? Why not pop front and push back? Or just use a > fixed size array and keep rotating the begin and end pointers? pop_front on a vector is no faster than the copy and might actually be slower. Perhaps this should be a list<> or deque<>. What do you think? -Dave From ofv at wanadoo.es Thu Nov 19 15:15:42 2009 From: ofv at wanadoo.es (=?windows-1252?Q?=D3scar_Fuentes?=) Date: Thu, 19 Nov 2009 22:15:42 +0100 Subject: [llvm-commits] [llvm] r89211 - /llvm/trunk/CMakeLists.txt References: <200911181742.nAIHgMXe005175@zion.cs.uiuc.edu> Message-ID: <87lji25i81.fsf@telefonica.net> Hello Daniel. Daniel Dunbar writes: > URL: http://llvm.org/viewvc/llvm-project?rev=89211&view=rev > Log: > Turn LLVM_BUILD_EXAMPLES off by default in CMake builds, to match Makefiles & > Clang. What's the rationale for this? (And wouldn't it warrant the corresponding update of docs/CMake.html, where default values for variables are listed?) -- ?scar From johnny.chen at apple.com Thu Nov 19 15:29:33 2009 From: johnny.chen at apple.com (Johnny Chen) Date: Thu, 19 Nov 2009 13:29:33 -0800 Subject: [llvm-commits] [llvm] r89377 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td In-Reply-To: References: <200911191920.nAJJKHmV014543@zion.cs.uiuc.edu> <9F2BD57D-299A-4267-BF7C-A2969C90E75B@apple.com> <53A487A4-FAB5-4AEE-BD5A-F54301B3FE3E@apple.com> Message-ID: OK. Thanks! On Nov 19, 2009, at 1:02 PM, Bob Wilson wrote: > > On Nov 19, 2009, at 12:01 PM, Johnny Chen wrote: > >> Hi Bob, >> >> If there is a more elegant way to specify this information, I'm more than willing to revert the patch. >> However, I see no other way to specify that, for example: >> >> // VST4LN : Vector Store (single 4-element structure from one lane) >> class VST4LN op11_8, string OpcodeStr> >> : NLdStLN<1,0b00,op11_8, (outs), >> (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, >> nohash_imm:$lane), IIC_VST, >> !strconcat(OpcodeStr, >> "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"), >> "", []>; > > We should be able to use NLdSt and set op7_4 to "{?,?,?,?}". The rest of your change would stay the same. > >> How do I view pr5470? > > http://llvm.org/bugs/show_bug.cgi?id=5470 From gohman at apple.com Thu Nov 19 15:34:08 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 19 Nov 2009 21:34:08 -0000 Subject: [llvm-commits] [llvm] r89389 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp Message-ID: <200911192134.nAJLY8cS019293@zion.cs.uiuc.edu> Author: djg Date: Thu Nov 19 15:34:07 2009 New Revision: 89389 URL: http://llvm.org/viewvc/llvm-project?rev=89389&view=rev Log: Comparing a pointer with null is not a capture. Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CaptureTracking.cpp?rev=89389&r1=89388&r2=89389&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CaptureTracking.cpp (original) +++ llvm/trunk/lib/Analysis/CaptureTracking.cpp Thu Nov 19 15:34:07 2009 @@ -98,6 +98,11 @@ Worklist.push_back(U); } break; + case Instruction::ICmp: + // Comparing the pointer against null does not count as a capture. + if (isa(I->getOperand(1))) + break; + return true; default: // Something else - be conservative and say it is captured. return true; From evan.cheng at apple.com Thu Nov 19 15:45:23 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 19 Nov 2009 21:45:23 -0000 Subject: [llvm-commits] [llvm] r89396 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Message-ID: <200911192145.nAJLjNAg019758@zion.cs.uiuc.edu> Author: evancheng Date: Thu Nov 19 15:45:22 2009 New Revision: 89396 URL: http://llvm.org/viewvc/llvm-project?rev=89396&view=rev Log: Refactor cmov selection code out to a separate function. No functionality change. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=89396&r1=89395&r2=89396&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Nov 19 15:45:22 2009 @@ -149,6 +149,9 @@ /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM. SDNode *SelectV6T2BitfieldExtractOp(SDValue Op, unsigned Opc); + /// SelectCMOVOp - Select CMOV instructions for ARM. + SDNode *SelectCMOVOp(SDValue Op); + /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, @@ -1302,6 +1305,123 @@ return NULL; } +SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) { + EVT VT = Op.getValueType(); + SDValue N0 = Op.getOperand(0); + SDValue N1 = Op.getOperand(1); + SDValue N2 = Op.getOperand(2); + SDValue N3 = Op.getOperand(3); + SDValue InFlag = Op.getOperand(4); + assert(N2.getOpcode() == ISD::Constant); + assert(N3.getOpcode() == ISD::Register); + + if (!Subtarget->isThumb1Only() && VT == MVT::i32) { + // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) + // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) + // Pattern complexity = 18 cost = 1 size = 0 + SDValue CPTmp0; + SDValue CPTmp1; + SDValue CPTmp2; + if (Subtarget->isThumb()) { + if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) { + unsigned SOVal = cast(CPTmp1)->getZExtValue(); + unsigned SOShOp = ARM_AM::getSORegShOp(SOVal); + unsigned Opc = 0; + switch (SOShOp) { + case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break; + case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break; + case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break; + case ARM_AM::ror: Opc = ARM::t2MOVCCror; break; + default: + llvm_unreachable("Unknown so_reg opcode!"); + break; + } + SDValue SOShImm = + CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32); + SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) + cast(N2)->getZExtValue()), + MVT::i32); + SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag }; + return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6); + } + } else { + if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) { + SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) + cast(N2)->getZExtValue()), + MVT::i32); + SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag }; + return CurDAG->SelectNodeTo(Op.getNode(), + ARM::MOVCCs, MVT::i32, Ops, 7); + } + } + + // Pattern: (ARMcmov:i32 GPR:i32:$false, + // (imm:i32)<>:$true, + // (imm:i32):$cc) + // Emits: (MOVCCi:i32 GPR:i32:$false, + // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc) + // Pattern complexity = 10 cost = 1 size = 0 + if (N3.getOpcode() == ISD::Constant) { + if (Subtarget->isThumb()) { + if (Predicate_t2_so_imm(N3.getNode())) { + SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) + cast(N1)->getZExtValue()), + MVT::i32); + SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) + cast(N2)->getZExtValue()), + MVT::i32); + SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag }; + return CurDAG->SelectNodeTo(Op.getNode(), + ARM::t2MOVCCi, MVT::i32, Ops, 5); + } + } else { + if (Predicate_so_imm(N3.getNode())) { + SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) + cast(N1)->getZExtValue()), + MVT::i32); + SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) + cast(N2)->getZExtValue()), + MVT::i32); + SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag }; + return CurDAG->SelectNodeTo(Op.getNode(), + ARM::MOVCCi, MVT::i32, Ops, 5); + } + } + } + } + + // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) + // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) + // Pattern complexity = 6 cost = 1 size = 0 + // + // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) + // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) + // Pattern complexity = 6 cost = 11 size = 0 + // + // Also FCPYScc and FCPYDcc. + SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) + cast(N2)->getZExtValue()), + MVT::i32); + SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag }; + unsigned Opc = 0; + switch (VT.getSimpleVT().SimpleTy) { + default: assert(false && "Illegal conditional move type!"); + break; + case MVT::i32: + Opc = Subtarget->isThumb() + ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo) + : ARM::MOVCCr; + break; + case MVT::f32: + Opc = ARM::VMOVScc; + break; + case MVT::f64: + Opc = ARM::VMOVDcc; + break; + } + return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5); +} + SDNode *ARMDAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.getNode(); DebugLoc dl = N->getDebugLoc(); @@ -1549,122 +1669,8 @@ SDValue(Chain.getNode(), Chain.getResNo())); return NULL; } - case ARMISD::CMOV: { - EVT VT = Op.getValueType(); - SDValue N0 = Op.getOperand(0); - SDValue N1 = Op.getOperand(1); - SDValue N2 = Op.getOperand(2); - SDValue N3 = Op.getOperand(3); - SDValue InFlag = Op.getOperand(4); - assert(N2.getOpcode() == ISD::Constant); - assert(N3.getOpcode() == ISD::Register); - - if (!Subtarget->isThumb1Only() && VT == MVT::i32) { - // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) - // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) - // Pattern complexity = 18 cost = 1 size = 0 - SDValue CPTmp0; - SDValue CPTmp1; - SDValue CPTmp2; - if (Subtarget->isThumb()) { - if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) { - unsigned SOVal = cast(CPTmp1)->getZExtValue(); - unsigned SOShOp = ARM_AM::getSORegShOp(SOVal); - unsigned Opc = 0; - switch (SOShOp) { - case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break; - case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break; - case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break; - case ARM_AM::ror: Opc = ARM::t2MOVCCror; break; - default: - llvm_unreachable("Unknown so_reg opcode!"); - break; - } - SDValue SOShImm = - CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32); - SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) - cast(N2)->getZExtValue()), - MVT::i32); - SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag }; - return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6); - } - } else { - if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) { - SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) - cast(N2)->getZExtValue()), - MVT::i32); - SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag }; - return CurDAG->SelectNodeTo(Op.getNode(), - ARM::MOVCCs, MVT::i32, Ops, 7); - } - } - - // Pattern: (ARMcmov:i32 GPR:i32:$false, - // (imm:i32)<>:$true, - // (imm:i32):$cc) - // Emits: (MOVCCi:i32 GPR:i32:$false, - // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc) - // Pattern complexity = 10 cost = 1 size = 0 - if (N3.getOpcode() == ISD::Constant) { - if (Subtarget->isThumb()) { - if (Predicate_t2_so_imm(N3.getNode())) { - SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) - cast(N1)->getZExtValue()), - MVT::i32); - SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) - cast(N2)->getZExtValue()), - MVT::i32); - SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag }; - return CurDAG->SelectNodeTo(Op.getNode(), - ARM::t2MOVCCi, MVT::i32, Ops, 5); - } - } else { - if (Predicate_so_imm(N3.getNode())) { - SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) - cast(N1)->getZExtValue()), - MVT::i32); - SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) - cast(N2)->getZExtValue()), - MVT::i32); - SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag }; - return CurDAG->SelectNodeTo(Op.getNode(), - ARM::MOVCCi, MVT::i32, Ops, 5); - } - } - } - } - - // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) - // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) - // Pattern complexity = 6 cost = 1 size = 0 - // - // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) - // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) - // Pattern complexity = 6 cost = 11 size = 0 - // - // Also FCPYScc and FCPYDcc. - SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) - cast(N2)->getZExtValue()), - MVT::i32); - SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag }; - unsigned Opc = 0; - switch (VT.getSimpleVT().SimpleTy) { - default: assert(false && "Illegal conditional move type!"); - break; - case MVT::i32: - Opc = Subtarget->isThumb() - ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo) - : ARM::MOVCCr; - break; - case MVT::f32: - Opc = ARM::VMOVScc; - break; - case MVT::f64: - Opc = ARM::VMOVDcc; - break; - } - return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5); - } + case ARMISD::CMOV: + return SelectCMOVOp(Op); case ARMISD::CNEG: { EVT VT = Op.getValueType(); SDValue N0 = Op.getOperand(0); From evan.cheng at apple.com Thu Nov 19 15:51:48 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 19 Nov 2009 13:51:48 -0800 Subject: [llvm-commits] [llvm] r89356 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp In-Reply-To: <200911191510.53618.dag@cray.com> References: <200911191555.nAJFtnEm007165@zion.cs.uiuc.edu> <200911191510.53618.dag@cray.com> Message-ID: On Nov 19, 2009, at 1:10 PM, David Greene wrote: > On Thursday 19 November 2009 13:36, Evan Cheng wrote: >> On Nov 19, 2009, at 7:55 AM, David Greene wrote: >>> + // The queue of recently-used registers. >>> + SmallVector RecentRegs; >> >> Why the odd sized vector? > > Why not? We have the queue sized to three in our code. I can > change it if you'd like. It's an arbitrary choice. It seems strange. > >>> + >>> + // Record that we just picked this register. >>> + void recordRecentlyUsed(unsigned reg) { >>> + assert(reg != 0 && "Recently used register is NOREG!"); >>> + if (!RecentRegs.empty()) { >>> + std::copy(RecentRegs.begin() + 1, RecentRegs.end(), >>> RecentRegs.begin()); + RecentRegs.back() = reg; >> >> This seems extremely slow? Why not pop front and push back? Or just use a >> fixed size array and keep rotating the begin and end pointers? > > pop_front on a vector is no faster than the copy and might actually be slower. > Perhaps this should be a list<> or deque<>. What do you think? deque is slow. Why not just a fixed sized array and rotate the head and tail pointers? Evan > > -Dave > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Thu Nov 19 15:57:48 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 19 Nov 2009 21:57:48 -0000 Subject: [llvm-commits] [llvm] r89398 - in /llvm/trunk: include/llvm/Analysis/CaptureTracking.h lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/CaptureTracking.cpp lib/Transforms/IPO/FunctionAttrs.cpp test/Transforms/GVN/nonescaping-malloc.ll Message-ID: <200911192157.nAJLvmkD020251@zion.cs.uiuc.edu> Author: djg Date: Thu Nov 19 15:57:48 2009 New Revision: 89398 URL: http://llvm.org/viewvc/llvm-project?rev=89398&view=rev Log: Extend CaptureTracking to indicate when a value is never stored, even if it is not ultimately captured. Teach BasicAliasAnalysis that a local object address which does not escape and is never stored does not alias with a value resulting from a load. Added: llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll Modified: llvm/trunk/include/llvm/Analysis/CaptureTracking.h llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/lib/Analysis/CaptureTracking.cpp llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Modified: llvm/trunk/include/llvm/Analysis/CaptureTracking.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CaptureTracking.h?rev=89398&r1=89397&r2=89398&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/CaptureTracking.h (original) +++ llvm/trunk/include/llvm/Analysis/CaptureTracking.h Thu Nov 19 15:57:48 2009 @@ -21,8 +21,12 @@ /// by the enclosing function (which is required to exist). This routine can /// be expensive, so consider caching the results. The boolean ReturnCaptures /// specifies whether returning the value (or part of it) from the function + /// counts as capturing it or not. The boolean StoreCaptures specified whether + /// storing the value (or part of it) into memory anywhere automatically /// counts as capturing it or not. - bool PointerMayBeCaptured(const Value *V, bool ReturnCaptures); + bool PointerMayBeCaptured(const Value *V, + bool ReturnCaptures, + bool StoreCaptures); } // end namespace llvm Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=89398&r1=89397&r2=89398&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Thu Nov 19 15:57:48 2009 @@ -79,7 +79,12 @@ static bool isNonEscapingLocalObject(const Value *V) { // If this is a local allocation, check to see if it escapes. if (isa(V) || isNoAliasCall(V)) - return !PointerMayBeCaptured(V, false); + // Set StoreCaptures to True so that we can assume in our callers that the + // pointer is not the result of a load instruction. Currently + // PointerMayBeCaptured doesn't have any special analysis for the + // StoreCaptures=false case; if it did, our callers could be refined to be + // more precise. + return !PointerMayBeCaptured(V, false, /*StoreCaptures=*/true); // If this is an argument that corresponds to a byval or noalias argument, // then it has not escaped before entering the function. Check if it escapes @@ -89,7 +94,7 @@ // Don't bother analyzing arguments already known not to escape. if (A->hasNoCaptureAttr()) return true; - return !PointerMayBeCaptured(V, false); + return !PointerMayBeCaptured(V, false, /*StoreCaptures=*/true); } return false; } @@ -683,15 +688,19 @@ (V2Size != ~0U && isObjectSmallerThan(O1, V2Size, *TD))) return NoAlias; - // If one pointer is the result of a call/invoke and the other is a + // If one pointer is the result of a call/invoke or load and the other is a // non-escaping local object, then we know the object couldn't escape to a - // point where the call could return it. - if ((isa(O1) || isa(O1)) && - isNonEscapingLocalObject(O2) && O1 != O2) - return NoAlias; - if ((isa(O2) || isa(O2)) && - isNonEscapingLocalObject(O1) && O1 != O2) - return NoAlias; + // point where the call could return it. The load case works because + // isNonEscapingLocalObject considers all stores to be escapes (it + // passes true for the StoreCaptures argument to PointerMayBeCaptured). + if (O1 != O2) { + if ((isa(O1) || isa(O1) || isa(O1)) && + isNonEscapingLocalObject(O2)) + return NoAlias; + if ((isa(O2) || isa(O2) || isa(O2)) && + isNonEscapingLocalObject(O1)) + return NoAlias; + } if (!isa(V1) && isa(V2)) { std::swap(V1, V2); Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CaptureTracking.cpp?rev=89398&r1=89397&r2=89398&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CaptureTracking.cpp (original) +++ llvm/trunk/lib/Analysis/CaptureTracking.cpp Thu Nov 19 15:57:48 2009 @@ -28,8 +28,11 @@ /// by the enclosing function (which is required to exist). This routine can /// be expensive, so consider caching the results. The boolean ReturnCaptures /// specifies whether returning the value (or part of it) from the function +/// counts as capturing it or not. The boolean StoreCaptures specified whether +/// storing the value (or part of it) into memory anywhere automatically /// counts as capturing it or not. -bool llvm::PointerMayBeCaptured(const Value *V, bool ReturnCaptures) { +bool llvm::PointerMayBeCaptured(const Value *V, + bool ReturnCaptures, bool StoreCaptures) { assert(isa(V->getType()) && "Capture is for pointers only!"); SmallVector Worklist; SmallSet Visited; @@ -82,7 +85,11 @@ break; case Instruction::Store: if (V == I->getOperand(0)) - // Stored the pointer - it may be captured. + // Stored the pointer - conservatively assume it may be captured. + // TODO: If StoreCaptures is not true, we could do Fancy analysis + // to determine whether this store is not actually an escape point. + // In that case, BasicAliasAnalysis should be updated as well to + // take advantage of this. return true; // Storing to the pointee does not cause the pointer to be captured. break; Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=89398&r1=89397&r2=89398&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Thu Nov 19 15:57:48 2009 @@ -212,7 +212,7 @@ for (Function::arg_iterator A = F->arg_begin(), E = F->arg_end(); A!=E; ++A) if (isa(A->getType()) && !A->hasNoCaptureAttr() && - !PointerMayBeCaptured(A, true)) { + !PointerMayBeCaptured(A, true, /*StoreCaptures=*/false)) { A->addAttr(Attribute::NoCapture); ++NumNoCapture; Changed = true; @@ -280,7 +280,7 @@ return false; // Did not come from an allocation. } - if (PointerMayBeCaptured(RetVal, false)) + if (PointerMayBeCaptured(RetVal, false, /*StoreCaptures=*/false)) return false; } Added: llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll?rev=89398&view=auto ============================================================================== --- llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll (added) +++ llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll Thu Nov 19 15:57:48 2009 @@ -0,0 +1,108 @@ +; RUN: opt < %s -gvn -stats |& grep {Number of loads deleted} +; rdar://7363102 + +; GVN should be able to eliminate load %tmp22.i, because it is redundant with +; load %tmp8.i. This requires being able to prove that %tmp7.i doesn't +; alias the malloc'd value %tmp.i20.i.i, which it can do since %tmp7.i +; is derived from %tmp5.i which is computed from a load, and %tmp.i20.i.i +; is never stored and does not escape. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-apple-darwin10.0" + +%"struct.llvm::MallocAllocator" = type <{ i8 }> +%"struct.llvm::StringMap" = type { %"struct.llvm::StringMapImpl", %"struct.llvm::MallocAllocator" } +%"struct.llvm::StringMapEntry" = type { %"struct.llvm::StringMapEntryBase", i8* } +%"struct.llvm::StringMapEntryBase" = type { i32 } +%"struct.llvm::StringMapImpl" = type { %"struct.llvm::StringMapImpl::ItemBucket"*, i32, i32, i32, i32 } +%"struct.llvm::StringMapImpl::ItemBucket" = type { i32, %"struct.llvm::StringMapEntryBase"* } +%"struct.llvm::StringRef" = type { i8*, i64 } + +define %"struct.llvm::StringMapEntry"* @_Z3fooRN4llvm9StringMapIPvNS_15MallocAllocatorEEEPKc(%"struct.llvm::StringMap"* %X, i8* %P) ssp { +entry: + %tmp = alloca %"struct.llvm::StringRef", align 8 ; <%"struct.llvm::StringRef"*> [#uses=3] + %tmp.i = getelementptr inbounds %"struct.llvm::StringRef"* %tmp, i64 0, i32 0 ; [#uses=1] + store i8* %P, i8** %tmp.i, align 8 + %tmp1.i = call i64 @strlen(i8* %P) nounwind readonly ; [#uses=1] + %tmp2.i = getelementptr inbounds %"struct.llvm::StringRef"* %tmp, i64 0, i32 1 ; [#uses=1] + store i64 %tmp1.i, i64* %tmp2.i, align 8 + %tmp1 = call %"struct.llvm::StringMapEntry"* @_ZN4llvm9StringMapIPvNS_15MallocAllocatorEE16GetOrCreateValueERKNS_9StringRefE(%"struct.llvm::StringMap"* %X, %"struct.llvm::StringRef"* %tmp) ssp ; <%"struct.llvm::StringMapEntry"*> [#uses=1] + ret %"struct.llvm::StringMapEntry"* %tmp1 +} + +declare i64 @strlen(i8* nocapture) nounwind readonly + +declare noalias i8* @malloc(i64) nounwind + +declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind + +declare i32 @_ZN4llvm13StringMapImpl15LookupBucketForENS_9StringRefE(%"struct.llvm::StringMapImpl"*, i64, i64) + +define linkonce_odr %"struct.llvm::StringMapEntry"* @_ZN4llvm9StringMapIPvNS_15MallocAllocatorEE16GetOrCreateValueERKNS_9StringRefE(%"struct.llvm::StringMap"* %this, %"struct.llvm::StringRef"* nocapture %Key) ssp align 2 { +entry: + %elt = bitcast %"struct.llvm::StringRef"* %Key to i64* ; [#uses=1] + %val = load i64* %elt ; [#uses=3] + %tmp = getelementptr inbounds %"struct.llvm::StringRef"* %Key, i64 0, i32 1 ; [#uses=1] + %val2 = load i64* %tmp ; [#uses=2] + %tmp2.i = getelementptr inbounds %"struct.llvm::StringMap"* %this, i64 0, i32 0 ; <%"struct.llvm::StringMapImpl"*> [#uses=1] + %tmp3.i = tail call i32 @_ZN4llvm13StringMapImpl15LookupBucketForENS_9StringRefE(%"struct.llvm::StringMapImpl"* %tmp2.i, i64 %val, i64 %val2) ; [#uses=1] + %tmp4.i = getelementptr inbounds %"struct.llvm::StringMap"* %this, i64 0, i32 0, i32 0 ; <%"struct.llvm::StringMapImpl::ItemBucket"**> [#uses=1] + %tmp5.i = load %"struct.llvm::StringMapImpl::ItemBucket"** %tmp4.i, align 8 ; <%"struct.llvm::StringMapImpl::ItemBucket"*> [#uses=1] + %tmp6.i = zext i32 %tmp3.i to i64 ; [#uses=1] + %tmp7.i = getelementptr inbounds %"struct.llvm::StringMapImpl::ItemBucket"* %tmp5.i, i64 %tmp6.i, i32 1 ; <%"struct.llvm::StringMapEntryBase"**> [#uses=2] + %tmp8.i = load %"struct.llvm::StringMapEntryBase"** %tmp7.i, align 8 ; <%"struct.llvm::StringMapEntryBase"*> [#uses=3] + %tmp9.i = icmp eq %"struct.llvm::StringMapEntryBase"* %tmp8.i, null ; [#uses=1] + %tmp13.i = icmp eq %"struct.llvm::StringMapEntryBase"* %tmp8.i, inttoptr (i64 -1 to %"struct.llvm::StringMapEntryBase"*) ; [#uses=1] + %or.cond.i = or i1 %tmp9.i, %tmp13.i ; [#uses=1] + br i1 %or.cond.i, label %bb4.i, label %bb6.i + +bb4.i: ; preds = %entry + %tmp41.i = inttoptr i64 %val to i8* ; [#uses=2] + %tmp4.i35.i = getelementptr inbounds i8* %tmp41.i, i64 %val2 ; [#uses=1] + %tmp.i.i = ptrtoint i8* %tmp4.i35.i to i64 ; [#uses=1] + %tmp1.i.i = trunc i64 %tmp.i.i to i32 ; [#uses=1] + %tmp3.i.i = trunc i64 %val to i32 ; [#uses=1] + %tmp4.i.i = sub i32 %tmp1.i.i, %tmp3.i.i ; [#uses=3] + %tmp5.i.i = add i32 %tmp4.i.i, 17 ; [#uses=1] + %tmp8.i.i = zext i32 %tmp5.i.i to i64 ; [#uses=1] + %tmp.i20.i.i = tail call noalias i8* @malloc(i64 %tmp8.i.i) nounwind ; [#uses=7] + %tmp10.i.i = bitcast i8* %tmp.i20.i.i to %"struct.llvm::StringMapEntry"* ; <%"struct.llvm::StringMapEntry"*> [#uses=2] + %tmp12.i.i = icmp eq i8* %tmp.i20.i.i, null ; [#uses=1] + br i1 %tmp12.i.i, label %_ZN4llvm14StringMapEntryIPvE6CreateINS_15MallocAllocatorES1_EEPS2_PKcS7_RT_T0_.exit.i, label %bb.i.i + +bb.i.i: ; preds = %bb4.i + %tmp.i.i.i.i = bitcast i8* %tmp.i20.i.i to i32* ; [#uses=1] + store i32 %tmp4.i.i, i32* %tmp.i.i.i.i, align 4 + %tmp1.i19.i.i = getelementptr inbounds i8* %tmp.i20.i.i, i64 8 ; [#uses=1] + %0 = bitcast i8* %tmp1.i19.i.i to i8** ; [#uses=1] + store i8* null, i8** %0, align 8 + br label %_ZN4llvm14StringMapEntryIPvE6CreateINS_15MallocAllocatorES1_EEPS2_PKcS7_RT_T0_.exit.i + +_ZN4llvm14StringMapEntryIPvE6CreateINS_15MallocAllocatorES1_EEPS2_PKcS7_RT_T0_.exit.i: ; preds = %bb4.i, %bb.i.i + %tmp.i18.i.i = getelementptr inbounds i8* %tmp.i20.i.i, i64 16 ; [#uses=1] + %tmp15.i.i = zext i32 %tmp4.i.i to i64 ; [#uses=2] + tail call void @llvm.memcpy.i64(i8* %tmp.i18.i.i, i8* %tmp41.i, i64 %tmp15.i.i, i32 1) nounwind + %tmp.i18.sum.i.i = add i64 %tmp15.i.i, 16 ; [#uses=1] + %tmp17.i.i = getelementptr inbounds i8* %tmp.i20.i.i, i64 %tmp.i18.sum.i.i ; [#uses=1] + store i8 0, i8* %tmp17.i.i, align 1 + %tmp.i.i.i = getelementptr inbounds i8* %tmp.i20.i.i, i64 8 ; [#uses=1] + %1 = bitcast i8* %tmp.i.i.i to i8** ; [#uses=1] + store i8* null, i8** %1, align 8 + %tmp22.i = load %"struct.llvm::StringMapEntryBase"** %tmp7.i, align 8 ; <%"struct.llvm::StringMapEntryBase"*> [#uses=1] + %tmp24.i = icmp eq %"struct.llvm::StringMapEntryBase"* %tmp22.i, inttoptr (i64 -1 to %"struct.llvm::StringMapEntryBase"*) ; [#uses=1] + br i1 %tmp24.i, label %bb9.i, label %_ZN4llvm9StringMapIPvNS_15MallocAllocatorEE16GetOrCreateValueIS1_EERNS_14StringMapEntryIS1_EENS_9StringRefET_.exit + +bb6.i: ; preds = %entry + %tmp16.i = bitcast %"struct.llvm::StringMapEntryBase"* %tmp8.i to %"struct.llvm::StringMapEntry"* ; <%"struct.llvm::StringMapEntry"*> [#uses=1] + ret %"struct.llvm::StringMapEntry"* %tmp16.i + +bb9.i: ; preds = %_ZN4llvm14StringMapEntryIPvE6CreateINS_15MallocAllocatorES1_EEPS2_PKcS7_RT_T0_.exit.i + %tmp25.i = getelementptr inbounds %"struct.llvm::StringMap"* %this, i64 0, i32 0, i32 3 ; [#uses=2] + %tmp26.i = load i32* %tmp25.i, align 8 ; [#uses=1] + %tmp27.i = add i32 %tmp26.i, -1 ; [#uses=1] + store i32 %tmp27.i, i32* %tmp25.i, align 8 + ret %"struct.llvm::StringMapEntry"* %tmp10.i.i + +_ZN4llvm9StringMapIPvNS_15MallocAllocatorEE16GetOrCreateValueIS1_EERNS_14StringMapEntryIS1_EENS_9StringRefET_.exit: ; preds = %_ZN4llvm14StringMapEntryIPvE6CreateINS_15MallocAllocatorES1_EEPS2_PKcS7_RT_T0_.exit.i + ret %"struct.llvm::StringMapEntry"* %tmp10.i.i +} From grosbach at apple.com Thu Nov 19 17:10:28 2009 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 19 Nov 2009 23:10:28 -0000 Subject: [llvm-commits] [llvm] r89403 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <200911192310.nAJNASND022655@zion.cs.uiuc.edu> Author: grosbach Date: Thu Nov 19 17:10:28 2009 New Revision: 89403 URL: http://llvm.org/viewvc/llvm-project?rev=89403&view=rev Log: When placing constant islands and adjusting for alignment padding, inline assembly can confuse things utterly, as it's assumed that instructions in inline assembly are 4 bytes wide. For Thumb mode, that's often not true, so the calculations for when alignment padding will be present get thrown off, ultimately leading to out of range constant pool entry references. Making more conservative assumptions that padding may be necessary when inline asm is present avoids this situation. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=89403&r1=89402&r2=89403&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Thu Nov 19 17:10:28 2009 @@ -162,6 +162,9 @@ /// the branch fix up pass. bool HasFarJump; + /// HasInlineAsm - True if the function contains inline assembly. + bool HasInlineAsm; + const TargetInstrInfo *TII; const ARMSubtarget *STI; ARMFunctionInfo *AFI; @@ -218,10 +221,45 @@ unsigned GetOffsetOf(MachineInstr *MI) const; void dumpBBs(); void verify(MachineFunction &MF); + void verifySizes(MachineFunction &MF); }; char ARMConstantIslands::ID = 0; } +// verifySizes - Recalculate BB sizes from scratch and validate that the result +// matches the values we've been using. +void ARMConstantIslands::verifySizes(MachineFunction &MF) { + unsigned Offset = 0; + for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); + MBBI != E; ++MBBI) { + MachineBasicBlock &MBB = *MBBI; + unsigned MBBSize = 0; + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); + I != E; ++I) { + // Add instruction size to MBBSize. + MBBSize += TII->GetInstSizeInBytes(I); + } + // In thumb mode, if this block is a constpool island, we may need padding + // so it's aligned on 4 byte boundary. + if (isThumb && + !MBB.empty() && + MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY && + ((Offset%4) != 0 || HasInlineAsm)) + MBBSize += 2; + Offset += MBBSize; + + DEBUG(errs() << "block #" << MBB.getNumber() << ": " + << MBBSize << " bytes (expecting " << BBSizes[MBB.getNumber()] + << (MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY ? + " CONSTANTPOOL" : "") << ")\n"); +#ifndef NDEBUG + if (MBBSize != BBSizes[MBB.getNumber()]) + MBB.dump(); +#endif + assert (MBBSize == BBSizes[MBB.getNumber()] && "block size mismatch!"); + } +} + /// verify - check BBOffsets, BBSizes, alignment of islands void ARMConstantIslands::verify(MachineFunction &MF) { assert(BBOffsets.size() == BBSizes.size()); @@ -236,11 +274,17 @@ if (!MBB->empty() && MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) { unsigned MBBId = MBB->getNumber(); - assert((BBOffsets[MBBId]%4 == 0 && BBSizes[MBBId]%4 == 0) || + assert(HasInlineAsm || + (BBOffsets[MBBId]%4 == 0 && BBSizes[MBBId]%4 == 0) || (BBOffsets[MBBId]%4 != 0 && BBSizes[MBBId]%4 != 0)); } } #endif + for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) { + CPUser &U = CPUsers[i]; + unsigned UserOffset = GetOffsetOf(U.MI) + (isThumb ? 4 : 8); + assert (CPEIsInRange(U.MI, UserOffset, U.CPEMI, U.MaxDisp, U.NegOk, true)); + } } /// print block size and offset information - debugging @@ -269,6 +313,7 @@ isThumb2 = AFI->isThumb2Function(); HasFarJump = false; + HasInlineAsm = false; // Renumber all of the machine basic blocks in the function, guaranteeing that // the numbers agree with the position of the block in the function. @@ -347,6 +392,7 @@ // After a while, this might be made debug-only, but it is not expensive. verify(MF); + verifySizes(MF); // If LR has been forced spilled and no far jumps (i.e. BL) has been issued. // Undo the spill / restore of LR if possible. @@ -452,6 +498,19 @@ /// and finding all of the constant pool users. void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF, const std::vector &CPEMIs) { + // First thing, see if the function has any inline assembly in it. If so, + // we have to be conservative about alignment assumptions, as we don't + // know for sure the size of any instructions in the inline assembly. + for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); + MBBI != E; ++MBBI) { + MachineBasicBlock &MBB = *MBBI; + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); + I != E; ++I) + if (I->getOpcode() == ARM::INLINEASM) + HasInlineAsm = true; + } + + // Now go back through the instructions and build up our data structures unsigned Offset = 0; for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); MBBI != E; ++MBBI) { @@ -481,7 +540,7 @@ // A Thumb1 table jump may involve padding; for the offsets to // be right, functions containing these must be 4-byte aligned. AFI->setAlign(2U); - if ((Offset+MBBSize)%4 != 0) + if ((Offset+MBBSize)%4 != 0 || HasInlineAsm) // FIXME: Add a pseudo ALIGN instruction instead. MBBSize += 2; // padding continue; // Does not get an entry in ImmBranches @@ -609,7 +668,7 @@ if (isThumb && !MBB.empty() && MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY && - (Offset%4) != 0) + ((Offset%4) != 0 || HasInlineAsm)) MBBSize += 2; BBSizes.push_back(MBBSize); @@ -633,7 +692,7 @@ // alignment padding, and compensate if so. if (isThumb && MI->getOpcode() == ARM::CONSTPOOL_ENTRY && - Offset%4 != 0) + (Offset%4 != 0 || HasInlineAsm)) Offset += 2; // Sum instructions before MI in MBB. @@ -829,7 +888,7 @@ MachineInstr *CPEMI, unsigned MaxDisp, bool NegOk, bool DoDump) { unsigned CPEOffset = GetOffsetOf(CPEMI); - assert(CPEOffset%4 == 0 && "Misaligned CPE"); + assert((CPEOffset%4 == 0 || HasInlineAsm) && "Misaligned CPE"); if (DoDump) { DEBUG(errs() << "User of CPE#" << CPEMI->getOperand(0).getImm() @@ -870,7 +929,7 @@ if (!isThumb) continue; MachineBasicBlock *MBB = MBBI; - if (!MBB->empty()) { + if (!MBB->empty() && !HasInlineAsm) { // Constant pool entries require padding. if (MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) { unsigned OldOffset = BBOffsets[i] - delta; @@ -1226,7 +1285,7 @@ BBOffsets[NewIsland->getNumber()] = BBOffsets[NewMBB->getNumber()]; // Compensate for .align 2 in thumb mode. - if (isThumb && BBOffsets[NewIsland->getNumber()]%4 != 0) + if (isThumb && (BBOffsets[NewIsland->getNumber()]%4 != 0 || HasInlineAsm)) Size += 2; // Increase the size of the island block to account for the new entry. BBSizes[NewIsland->getNumber()] += Size; From david_goodwin at apple.com Thu Nov 19 17:12:37 2009 From: david_goodwin at apple.com (David Goodwin) Date: Thu, 19 Nov 2009 23:12:37 -0000 Subject: [llvm-commits] [llvm] r89404 - in /llvm/trunk/lib/CodeGen: AggressiveAntiDepBreaker.cpp AggressiveAntiDepBreaker.h Message-ID: <200911192312.nAJNCcFE022729@zion.cs.uiuc.edu> Author: david_goodwin Date: Thu Nov 19 17:12:37 2009 New Revision: 89404 URL: http://llvm.org/viewvc/llvm-project?rev=89404&view=rev Log: Fix a couple of problems with maintaining liveness information for antidep breaking. Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=89404&r1=89403&r2=89404&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Thu Nov 19 17:12:37 2009 @@ -33,6 +33,16 @@ cl::desc("Maximum number of anti-dependency breaking passes"), cl::init(1), cl::Hidden); +// If DebugDiv > 0 then only break antidep with (ID % DebugDiv) == DebugMod +static cl::opt +DebugDiv("agg-antidep-debugdiv", + cl::desc("Debug control for aggressive anti-dep breaker"), + cl::init(0), cl::Hidden); +static cl::opt +DebugMod("agg-antidep-debugmod", + cl::desc("Debug control for aggressive anti-dep breaker"), + cl::init(0), cl::Hidden); + AggressiveAntiDepState::AggressiveAntiDepState(MachineBasicBlock *BB) : GroupNodes(TargetRegisterInfo::FirstVirtualRegister, 0) { // Initialize all registers to be in their own group. Initially we @@ -332,7 +342,8 @@ } void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx, - const char *tag) { + const char *tag, const char *header, + const char *footer) { unsigned *KillIndices = State->GetKillIndices(); unsigned *DefIndices = State->GetDefIndices(); std::multimap& @@ -343,6 +354,8 @@ DefIndices[Reg] = ~0u; RegRefs.erase(Reg); State->LeaveGroup(Reg); + DEBUG(if (header != NULL) { + errs() << header << TRI->getName(Reg); header = NULL; }); DEBUG(errs() << "->g" << State->GetGroup(Reg) << tag); } // Repeat for subregisters. @@ -354,10 +367,14 @@ DefIndices[SubregReg] = ~0u; RegRefs.erase(SubregReg); State->LeaveGroup(SubregReg); + DEBUG(if (header != NULL) { + errs() << header << TRI->getName(Reg); header = NULL; }); DEBUG(errs() << " " << TRI->getName(SubregReg) << "->g" << State->GetGroup(SubregReg) << tag); } } + + DEBUG(if ((header == NULL) && (footer != NULL)) errs() << footer); } void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Count, @@ -377,9 +394,7 @@ unsigned Reg = MO.getReg(); if (Reg == 0) continue; - DEBUG(errs() << "\tDead Def: " << TRI->getName(Reg)); - HandleLastUse(Reg, Count + 1, ""); - DEBUG(errs() << '\n'); + HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n"); } DEBUG(errs() << "\tDef Groups:"); @@ -427,15 +442,17 @@ if (!MO.isReg() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; - // Ignore passthru registers for liveness... - if (PassthruRegs.count(Reg) != 0) continue; + // Ignore KILLs and passthru registers for liveness... + if ((MI->getOpcode() == TargetInstrInfo::KILL) || + (PassthruRegs.count(Reg) != 0)) + continue; - // Update def for Reg and subregs. + // Update def for Reg and aliases. DefIndices[Reg] = Count; - for (const unsigned *Subreg = TRI->getSubRegisters(Reg); - *Subreg; ++Subreg) { - unsigned SubregReg = *Subreg; - DefIndices[SubregReg] = Count; + for (const unsigned *Alias = TRI->getAliasSet(Reg); + *Alias; ++Alias) { + unsigned AliasReg = *Alias; + DefIndices[AliasReg] = Count; } } } @@ -610,6 +627,18 @@ return false; } +#ifndef NDEBUG + // If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod + if (DebugDiv > 0) { + static int renamecnt = 0; + if (renamecnt++ % DebugDiv != DebugMod) + return false; + + errs() << "*** Performing rename " << TRI->getName(SuperReg) << + " for debug ***\n"; + } +#endif + if (RenameOrder.count(SuperRC) == 0) RenameOrder.insert(RenameOrderType::value_type(SuperRC, RE)); @@ -629,17 +658,18 @@ // If Reg is dead and Reg's most recent def is not before // SuperRegs's kill, it's safe to replace SuperReg with Reg. We - // must also check all subregisters of Reg. + // must also check all aliases of Reg. because we can't define a + // register when any sub or super is already live. if (State->IsLive(Reg) || (KillIndices[SuperReg] > DefIndices[Reg])) { DEBUG(errs() << "(live)"); continue; } else { bool found = false; - for (const unsigned *Subreg = TRI->getSubRegisters(Reg); - *Subreg; ++Subreg) { - unsigned SubregReg = *Subreg; - if (State->IsLive(SubregReg) || (KillIndices[SuperReg] > DefIndices[SubregReg])) { - DEBUG(errs() << "(subreg " << TRI->getName(SubregReg) << " live)"); + for (const unsigned *Alias = TRI->getAliasSet(Reg); + *Alias; ++Alias) { + unsigned AliasReg = *Alias; + if (State->IsLive(AliasReg) || (KillIndices[SuperReg] > DefIndices[AliasReg])) { + DEBUG(errs() << "(alias " << TRI->getName(AliasReg) << " live)"); found = true; break; } Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=89404&r1=89403&r2=89404&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Thu Nov 19 17:12:37 2009 @@ -175,7 +175,9 @@ /// return that register and all subregisters. void GetPassthruRegs(MachineInstr *MI, std::set& PassthruRegs); - void HandleLastUse(unsigned Reg, unsigned KillIdx, const char *tag); + void HandleLastUse(unsigned Reg, unsigned KillIdx, const char *tag, + const char *header =NULL, const char *footer =NULL); + void PrescanInstruction(MachineInstr *MI, unsigned Count, std::set& PassthruRegs); void ScanInstruction(MachineInstr *MI, unsigned Count); From ofv at wanadoo.es Thu Nov 19 17:21:43 2009 From: ofv at wanadoo.es (Oscar Fuentes) Date: Thu, 19 Nov 2009 23:21:43 -0000 Subject: [llvm-commits] [llvm] r89406 - in /llvm/trunk: cmake/modules/LLVMConfig.cmake lib/System/CMakeLists.txt Message-ID: <200911192321.nAJNLhQM023086@zion.cs.uiuc.edu> Author: ofv Date: Thu Nov 19 17:21:43 2009 New Revision: 89406 URL: http://llvm.org/viewvc/llvm-project?rev=89406&view=rev Log: Use CMAKE_DL_LIBS instead of raw library name. Fixes bug 5536. Patch by Tobias Grosser! Modified: llvm/trunk/cmake/modules/LLVMConfig.cmake llvm/trunk/lib/System/CMakeLists.txt Modified: llvm/trunk/cmake/modules/LLVMConfig.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMConfig.cmake?rev=89406&r1=89405&r2=89406&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMConfig.cmake (original) +++ llvm/trunk/cmake/modules/LLVMConfig.cmake Thu Nov 19 17:21:43 2009 @@ -5,7 +5,7 @@ set(system_libs ${system_libs} imagehlp psapi) elseif( CMAKE_HOST_UNIX ) if( HAVE_LIBDL ) - set(system_libs ${system_libs} dl) + set(system_libs ${system_libs} ${CMAKE_DL_LIBS}) endif() if( LLVM_ENABLE_THREADS AND HAVE_LIBPTHREAD ) set(system_libs ${system_libs} pthread) Modified: llvm/trunk/lib/System/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/CMakeLists.txt?rev=89406&r1=89405&r2=89406&view=diff ============================================================================== --- llvm/trunk/lib/System/CMakeLists.txt (original) +++ llvm/trunk/lib/System/CMakeLists.txt Thu Nov 19 17:21:43 2009 @@ -42,5 +42,5 @@ ) if( BUILD_SHARED_LIBS AND NOT WIN32 ) - target_link_libraries(LLVMSystem dl) + target_link_libraries(LLVMSystem ${CMAKE_DL_LIBS}) endif() From ofv at wanadoo.es Thu Nov 19 17:26:28 2009 From: ofv at wanadoo.es (=?windows-1252?Q?=D3scar_Fuentes?=) Date: Fri, 20 Nov 2009 00:26:28 +0100 Subject: [llvm-commits] [patch] CMake: Do not add -ldl, but use CMAKE_DL_LIBS References: <1258631786.28275.4.camel@tobilaptop.fritz.box> Message-ID: <87fx8a5c63.fsf@telefonica.net> Tobias Grosser writes: > I just fixed bug http://llvm.org/bugs/show_bug.cgi?id=5536 Just committed your patch, thanks. > By the way, do I have to send these patches to this mailinglist or is > it enough to add them to the bug tracker? Adding the patch to the bug report should be enough, as that activity is reflected on the llvm-bugs mailing list, but I see that no message was sent there. I need to check this. -- ?scar From jyasskin at google.com Thu Nov 19 17:42:58 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Thu, 19 Nov 2009 23:42:58 -0000 Subject: [llvm-commits] [llvm] r89410 - /llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200911192342.nAJNgwRL023832@zion.cs.uiuc.edu> Author: jyasskin Date: Thu Nov 19 17:42:58 2009 New Revision: 89410 URL: http://llvm.org/viewvc/llvm-project?rev=89410&view=rev Log: Try to fix JITTest.FarCallToKnownFunction on ARM and PPC. Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp?rev=89410&r1=89409&r2=89410&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JITEmitter.cpp Thu Nov 19 17:42:58 2009 @@ -736,17 +736,21 @@ return FnStub; } - // Otherwise if we have code, go ahead and return that. - void *ResultPtr = TheJIT->getPointerToGlobalIfAvailable(F); - if (ResultPtr) return ResultPtr; - - // If this is an external function pointer, we can force the JIT to - // 'compile' it, which really just adds it to the map. - if (F->isDeclaration() && !F->hasNotBeenReadFromBitcode() && - !MayNeedFarStub) - return TheJIT->getPointerToFunction(F); + // If we know the target can handle arbitrary-distance calls, try to + // return a direct pointer. + if (!MayNeedFarStub) { + // If we have code, go ahead and return that. + void *ResultPtr = TheJIT->getPointerToGlobalIfAvailable(F); + if (ResultPtr) return ResultPtr; + + // If this is an external function pointer, we can force the JIT to + // 'compile' it, which really just adds it to the map. + if (F->isDeclaration() && !F->hasNotBeenReadFromBitcode()) + return TheJIT->getPointerToFunction(F); + } - // Otherwise, we have to emit a stub. + // Otherwise, we may need a to emit a stub, and, conservatively, we + // always do so. void *StubAddr = Resolver.getFunctionStub(F); // Add the stub to the current function's list of referenced stubs, so we can From gohman at apple.com Thu Nov 19 17:53:49 2009 From: gohman at apple.com (Dan Gohman) Date: Thu, 19 Nov 2009 23:53:49 -0000 Subject: [llvm-commits] [llvm] r89411 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp Message-ID: <200911192353.nAJNrnT8024233@zion.cs.uiuc.edu> Author: djg Date: Thu Nov 19 17:53:49 2009 New Revision: 89411 URL: http://llvm.org/viewvc/llvm-project?rev=89411&view=rev Log: Refine this to only apply to null in the default address space. Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CaptureTracking.cpp?rev=89411&r1=89410&r2=89411&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CaptureTracking.cpp (original) +++ llvm/trunk/lib/Analysis/CaptureTracking.cpp Thu Nov 19 17:53:49 2009 @@ -107,8 +107,10 @@ break; case Instruction::ICmp: // Comparing the pointer against null does not count as a capture. - if (isa(I->getOperand(1))) - break; + if (ConstantPointerNull *CPN = + dyn_cast(I->getOperand(1))) + if (CPN->getType()->getAddressSpace() == 0) + break; return true; default: // Something else - be conservative and say it is captured. From bob.wilson at apple.com Thu Nov 19 17:53:52 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 19 Nov 2009 15:53:52 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: References: <701493E3-E27B-4EAB-9666-99B2F6EA01BC@apple.com> Message-ID: <16600E75-AC60-43A9-9E4C-BA0FC8F94440@apple.com> Hi Chris, An update so you don't think I'm ignoring you.... I want to try some experiments on x86 before changing anything. I'm currently blocked by . I'll take another look at it once that is resolved. On Nov 19, 2009, at 10:11 AM, Bob Wilson wrote: > > On Nov 19, 2009, at 9:35 AM, Chris Lattner wrote: > >> Apologies for the last email being rambling, and in advance for this >> one also being rambling. :) >> >> My basic perspective is that I want to sink as much logic into the >> target-independent code as possible and have the fewest number of >> target hooks reasonable. This is for three reasons: >> >> 1. Porting to a new target is easier with fewer target hooks, and >> they get better codegen 'out of the box' by specifying primitives >> instead of having to tweak tons of knobs. > > I disagree. It is good to have knobs to tweak. As long as the > defaults are set to values that work well for most targets, having > more knobs does not make it harder to port to a new target. It does > increase the overall complexity and documentation burden, though. > > In this particular case, I left the default set to match the previous > behavior. We could easily change that once we find out what works > best on most of the targets we support. > >> >> 2. A single and well tuned implementation of something in target >> independent code is better than having a few well tuned impls in >> some targets and missing or just wrong impls in others. For >> example, this xform is definitely profitable on X86 chips as well, >> probably many others. > > Right. There is a single implementation of tail duplication here. > It's just a question of tuning it for different targets. It is not > possible (in general) to have it tuned ideally for all targets. For > that matter, we haven't really tuned it for ARM yet. I've started > looking at trying it for X86. > > I suppose that after further experimentation, we may discover that in > practice the same tuning works well enough on all the targets we care > about. I don't know whether that will be true or not, but based on > your comments, let's assume that it will. If we discover later that > it doesn't work well, we can always add the target hook at that time. > >> >> 3. Less target-specific code to maintain and push around as the >> compiler moves forward. >> >> anyway, these are just general principles why I don't like new >> target hooks when they can be avoided. More details: >> >>> On Nov 18, 2009, at 9:29 AM, Bob Wilson wrote: >>>> The only disadvantage of what you suggest is code size. There is >>>> currently no limit on the number of predecessors where a block may >>>> be >>>> duplicated, so the effect of duplicating a small block can be >>>> magnified in the overall code size. >> >> Right. However, the implementation for ARM doesn't consider this at >> all. Also, this cost is not something that should need target- >> specific information to quantify. > > It's easy to measure the change in code size but hard to weigh that > against the performance benefit. That part is very target-specific. > >> >>>> (And, at least for duplicating >>>> indirect branches on ARM Cortex processors, we don't want to limit >>>> that.) >> >> Why not?? > > Because it is such a dramatic performance win for ARM Cortex, and > perhaps more importantly, I can't think of a way to limit it that > might not also miss cases where we really want to get the > performance. I don't expect indirect branches to be so common that > the code size matters. > >> >>>> On a small low-power device without sophisticated branch >>>> prediction, where code size typically matters more than usual, >>>> we'll >>>> be doing the wrong thing. But, indirect branches are not very >>>> common, >>>> so it probably doesn't really matter so much. >> >> They are fairly common in switch statements that codegen to jump >> tables, but not anyway near as common as normal branches. > > For ARM we currently use different instruction patterns for jump > tables and indirect branches. So, the special case we're doing for > tail duplication does not apply to jump tables. We might have to be > more conservative if we can't distinguish those on other targets. > >> >>>> Most modern high-performance processors will benefit from tail >>>> duplicating indirect branches, so that would be another reason to >>>> avoid the target hook. >> >> Right. I would also like the target hook much better if it was of >> the form "DoesBranchPredictionOfIndirectCallsBasedOnPC" or something >> like that. This predicate makes it *really really* obvious what it >> doing. By returning a 'cost' with no real units, the target author >> has no "truth" they just fiddle around until the 'right thing >> happens'. Given the documentation, it's very unclear (as a target >> author) why you'd want to specify the hook you added. >> >> I much prefer very simple hooks that return an _aspect of the micro >> architecture_ rather than having hooks that _implement pieces of >> codegen passes_. The later is the approach that GCC took and is one >> of the major reasons it is difficult to change the algorithms in the >> GCC backend. > > Doesn't that go against your desire to have fewer target hooks? I > tried to make the tail duplication hook very general, since it seems > conceivable that we may want to adjust the cost metric based on other > characteristics of the target. If we add very specific target hooks, > we may end up with more of them. > > I admit that "obviousness" advantage of using very specific hooks. > >> >>>> >>>> Unless someone else has another idea, I'll get rid of the tail >>>> duplication target hook. As you mention, we'll need a way to >>>> identify >>>> indirect branches. I'd prefer to add a new IsIndirectBranch target >>>> hook. This goes against your desire to avoid new target hooks, but >>>> it's nice and simple. >> >> Using the extant isIndirectBranch flag would be best, but even >> adding this sort of target hook would be somewhat ok. At least this >> would be a property of the architecture. If we can avoid it, I'd >> definitely prefer to of course. > > The isIndirectBranch flag would not allow us to distinguish jump table > branches. > >> >> Dan wrote: >>> However I don't know what the big problem is >>> with the target hook; it's neither arbitrary nor unitless. Perhaps >>> what he really meant is that the present use for the hook is too >>> obscure to justify having the clutter of the hook in >>> TargetInstrInfo, >>> but I'm just guessing here. >> >> What is the units that it returns? As a target author, how do I >> know to return +2 or +4 or +1234? > > It returns the maximum number of instructions in a basic block that > will be tail duplicated. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Thu Nov 19 18:17:59 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 19 Nov 2009 16:17:59 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: References: <701493E3-E27B-4EAB-9666-99B2F6EA01BC@apple.com> Message-ID: On Nov 19, 2009, at 9:35 AM, Chris Lattner wrote: > Apologies for the last email being rambling, and in advance for this one also being rambling. :) > > My basic perspective is that I want to sink as much logic into the target-independent code as possible and have the fewest number of target hooks reasonable. This is for three reasons: > > 1. Porting to a new target is easier with fewer target hooks, and they get better codegen 'out of the box' by specifying primitives instead of having to tweak tons of knobs. That's an idealistic way of looking at it. One that's almost guaranteed to get us no where when we want the best possible performance and code size for all targets. I agree the default behavior (i.e. without target hooks) should be reasonable. That is, if no target data is provided the optimization shouldn't punish the user. But we really need some target specific data. To me, the right way to implement this is actually having even more accurate machine model. Perhaps we need to consult target scheduling itineraries and use "branch cost". But even that is not quite enough. Evan > > 2. A single and well tuned implementation of something in target independent code is better than having a few well tuned impls in some targets and missing or just wrong impls in others. For example, this xform is definitely profitable on X86 chips as well, probably many others. > > 3. Less target-specific code to maintain and push around as the compiler moves forward. > > anyway, these are just general principles why I don't like new target hooks when they can be avoided. More details: > >> On Nov 18, 2009, at 9:29 AM, Bob Wilson wrote: >>> The only disadvantage of what you suggest is code size. There is >>> currently no limit on the number of predecessors where a block may be >>> duplicated, so the effect of duplicating a small block can be >>> magnified in the overall code size. > > Right. However, the implementation for ARM doesn't consider this at all. Also, this cost is not something that should need target-specific information to quantify. > >>> (And, at least for duplicating >>> indirect branches on ARM Cortex processors, we don't want to limit >>> that.) > > Why not?? > >>> On a small low-power device without sophisticated branch >>> prediction, where code size typically matters more than usual, we'll >>> be doing the wrong thing. But, indirect branches are not very common, >>> so it probably doesn't really matter so much. > > They are fairly common in switch statements that codegen to jump tables, but not anyway near as common as normal branches. > >>> Most modern high-performance processors will benefit from tail >>> duplicating indirect branches, so that would be another reason to >>> avoid the target hook. > > Right. I would also like the target hook much better if it was of the form "DoesBranchPredictionOfIndirectCallsBasedOnPC" or something like that. This predicate makes it *really really* obvious what it doing. By returning a 'cost' with no real units, the target author has no "truth" they just fiddle around until the 'right thing happens'. Given the documentation, it's very unclear (as a target author) why you'd want to specify the hook you added. > > I much prefer very simple hooks that return an _aspect of the micro architecture_ rather than having hooks that _implement pieces of codegen passes_. The later is the approach that GCC took and is one of the major reasons it is difficult to change the algorithms in the GCC backend. > >>> >>> Unless someone else has another idea, I'll get rid of the tail >>> duplication target hook. As you mention, we'll need a way to identify >>> indirect branches. I'd prefer to add a new IsIndirectBranch target >>> hook. This goes against your desire to avoid new target hooks, but >>> it's nice and simple. > > Using the extant isIndirectBranch flag would be best, but even adding this sort of target hook would be somewhat ok. At least this would be a property of the architecture. If we can avoid it, I'd definitely prefer to of course. > > Dan wrote: >> However I don't know what the big problem is >> with the target hook; it's neither arbitrary nor unitless. Perhaps >> what he really meant is that the present use for the hook is too >> obscure to justify having the clutter of the hook in TargetInstrInfo, >> but I'm just guessing here. > > What is the units that it returns? As a target author, how do I know to return +2 or +4 or +1234? > > Thanks for working on this Bob! > > -Chris > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Thu Nov 19 18:22:00 2009 From: echristo at apple.com (Eric Christopher) Date: Fri, 20 Nov 2009 00:22:00 -0000 Subject: [llvm-commits] [llvm] r89414 - /llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp Message-ID: <200911200022.nAK0M2xN025235@zion.cs.uiuc.edu> Author: echristo Date: Thu Nov 19 18:21:55 2009 New Revision: 89414 URL: http://llvm.org/viewvc/llvm-project?rev=89414&view=rev Log: Update comment to reflect instruction. Modified: llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp?rev=89414&r1=89413&r2=89414&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp Thu Nov 19 18:21:55 2009 @@ -177,7 +177,7 @@ if (!sys::Memory::setRangeWritable((void*)Addr, 16)) { llvm_unreachable("ERROR: Unable to mark stub writable"); } - JCE.emitWordLE(0xe59fc004); // ldr pc, [pc, #+4] + JCE.emitWordLE(0xe59fc004); // ldr ip, [pc, #+4] JCE.emitWordLE(0xe08fc00c); // L_func$scv: add ip, pc, ip JCE.emitWordLE(0xe59cf000); // ldr pc, [ip] JCE.emitWordLE(LazyPtr - (Addr+4+8)); // func - (L_func$scv+8) From isanbard at gmail.com Thu Nov 19 18:31:50 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 20 Nov 2009 00:31:50 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r89415 - in /llvm-gcc-4.2/trunk/gcc: config/darwin.h llvm-backend.cpp Message-ID: <200911200031.nAK0VpKv025598@zion.cs.uiuc.edu> Author: void Date: Thu Nov 19 18:31:31 2009 New Revision: 89415 URL: http://llvm.org/viewvc/llvm-project?rev=89415&view=rev Log: Adjust the alignment of strings so that they aren't over aligned. We only need them aligned to 8-bytes instead of 16-bytes for 64-bit. And 4 instead of 8 in 32-bit. Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.h llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.h?rev=89415&r1=89414&r2=89415&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/darwin.h Thu Nov 19 18:31:31 2009 @@ -698,10 +698,21 @@ char *N = (char *)alloca(strlen(fmt) + 37); \ sprintf(N, fmt, i++); \ GV->setName(N); \ + GV->setAlignment(TARGET_64BIT ? 8 : 4); \ } \ } while (0) /* LLVM LOCAL - end radar 6389998 */ +/* LLVM LOCAL - begin radar 7291825 */ +/* Give a constant string a sufficient alignment for the platform. */ +#define TARGET_ADJUST_CSTRING_ALIGN(GV) \ + do { \ + if (GV->hasInternalLinkage()) { \ + GV->setAlignment(TARGET_64BIT ? 8 : 4); \ + } \ + } while (0) +/* LLVM LOCAL - end radar 7291825 */ + #endif /* LLVM LOCAL end */ Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=89415&r1=89414&r2=89415&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Thu Nov 19 18:31:31 2009 @@ -1408,8 +1408,16 @@ unsigned TargetAlign = getTargetData().getABITypeAlignment(GV->getType()->getElementType()); if (DECL_USER_ALIGN(decl) || - 8 * TargetAlign < (unsigned)DECL_ALIGN(decl)) + 8 * TargetAlign < (unsigned)DECL_ALIGN(decl)) { GV->setAlignment(DECL_ALIGN(decl) / 8); + } +#ifdef TARGET_ADJUST_CSTRING_ALIGN + else if (DECL_INITIAL(decl) != error_mark_node && // uninitialized? + DECL_INITIAL(decl) && + TREE_CODE(DECL_INITIAL(decl)) == STRING_CST) { + TARGET_ADJUST_CSTRING_ALIGN(GV); + } +#endif } // Handle used decls From isanbard at gmail.com Thu Nov 19 18:32:17 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 20 Nov 2009 00:32:17 -0000 Subject: [llvm-commits] [llvm] r89417 - /llvm/trunk/test/FrontendC/cstring-align.c Message-ID: <200911200032.nAK0WHVh025635@zion.cs.uiuc.edu> Author: void Date: Thu Nov 19 18:32:16 2009 New Revision: 89417 URL: http://llvm.org/viewvc/llvm-project?rev=89417&view=rev Log: Testcase for r89415. Added: llvm/trunk/test/FrontendC/cstring-align.c Added: llvm/trunk/test/FrontendC/cstring-align.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/cstring-align.c?rev=89417&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/cstring-align.c (added) +++ llvm/trunk/test/FrontendC/cstring-align.c Thu Nov 19 18:32:16 2009 @@ -0,0 +1,16 @@ +// RUN: %llvmgcc %s -c -Os -m32 -emit-llvm -o - | llc -march=x86 -mtriple=i386-apple-darwin10 | FileCheck %s -check-prefix=DARWIN32 +// RUN: %llvmgcc %s -c -Os -m64 -emit-llvm -o - | llc -march=x86 -mtriple=i386-apple-darwin10 | FileCheck %s -check-prefix=DARWIN64 + +extern void func(const char *, const char *); + +void long_function_name() { + func("%s: the function name", __func__); +} + +// DARWIN64: .align 3 +// DARWIN64: ___func__. +// DARWIN64: .asciz "long_function_name" + +// DARWIN32: .align 2 +// DARWIN32: ___func__. +// DARWIN32: .asciz "long_function_name" From isanbard at gmail.com Thu Nov 19 18:40:25 2009 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 20 Nov 2009 00:40:25 -0000 Subject: [llvm-commits] [llvm] r89418 - /llvm/trunk/test/FrontendC/cstring-align.c Message-ID: <200911200040.nAK0eQVY025883@zion.cs.uiuc.edu> Author: void Date: Thu Nov 19 18:40:21 2009 New Revision: 89418 URL: http://llvm.org/viewvc/llvm-project?rev=89418&view=rev Log: Specify proper arch and triple for 64-bit. Modified: llvm/trunk/test/FrontendC/cstring-align.c Modified: llvm/trunk/test/FrontendC/cstring-align.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/cstring-align.c?rev=89418&r1=89417&r2=89418&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/cstring-align.c (original) +++ llvm/trunk/test/FrontendC/cstring-align.c Thu Nov 19 18:40:21 2009 @@ -1,5 +1,5 @@ // RUN: %llvmgcc %s -c -Os -m32 -emit-llvm -o - | llc -march=x86 -mtriple=i386-apple-darwin10 | FileCheck %s -check-prefix=DARWIN32 -// RUN: %llvmgcc %s -c -Os -m64 -emit-llvm -o - | llc -march=x86 -mtriple=i386-apple-darwin10 | FileCheck %s -check-prefix=DARWIN64 +// RUN: %llvmgcc %s -c -Os -m64 -emit-llvm -o - | llc -march=x86_64 -mtriple=x86_64-apple-darwin10 | FileCheck %s -check-prefix=DARWIN64 extern void func(const char *, const char *); From gohman at apple.com Thu Nov 19 18:43:15 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 00:43:15 -0000 Subject: [llvm-commits] [llvm] r89419 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp Message-ID: <200911200043.nAK0hFV3025963@zion.cs.uiuc.edu> Author: djg Date: Thu Nov 19 18:43:11 2009 New Revision: 89419 URL: http://llvm.org/viewvc/llvm-project?rev=89419&view=rev Log: Use isVoidTy(). Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CaptureTracking.cpp?rev=89419&r1=89418&r2=89419&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CaptureTracking.cpp (original) +++ llvm/trunk/lib/Analysis/CaptureTracking.cpp Thu Nov 19 18:43:11 2009 @@ -56,8 +56,7 @@ // Not captured if the callee is readonly, doesn't return a copy through // its return value and doesn't unwind (a readonly function can leak bits // by throwing an exception or not depending on the input value). - if (CS.onlyReadsMemory() && CS.doesNotThrow() && - I->getType() == Type::getVoidTy(V->getContext())) + if (CS.onlyReadsMemory() && CS.doesNotThrow() && I->getType()->isVoidTy()) break; // Not captured if only passed via 'nocapture' arguments. Note that From gohman at apple.com Thu Nov 19 18:50:52 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 00:50:52 -0000 Subject: [llvm-commits] [llvm] r89421 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp Message-ID: <200911200050.nAK0or7J026222@zion.cs.uiuc.edu> Author: djg Date: Thu Nov 19 18:50:47 2009 New Revision: 89421 URL: http://llvm.org/viewvc/llvm-project?rev=89421&view=rev Log: Refine the capture tracking rules for comparisons to be more careful about crazy methods of capturing pointers using comparisons. Comparisons of identified objects with null in the default address space are not captures. And, comparisons of two pointers within the same identified object are not captures. Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CaptureTracking.cpp?rev=89421&r1=89420&r2=89421&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CaptureTracking.cpp (original) +++ llvm/trunk/lib/Analysis/CaptureTracking.cpp Thu Nov 19 18:50:47 2009 @@ -19,6 +19,7 @@ #include "llvm/Analysis/CaptureTracking.h" #include "llvm/Instructions.h" #include "llvm/Value.h" +#include "llvm/Analysis/AliasAnalysis.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/CallSite.h" @@ -104,13 +105,25 @@ Worklist.push_back(U); } break; - case Instruction::ICmp: - // Comparing the pointer against null does not count as a capture. - if (ConstantPointerNull *CPN = - dyn_cast(I->getOperand(1))) - if (CPN->getType()->getAddressSpace() == 0) - break; + case Instruction::ICmp: { + // Don't count comparisons of the original value against null as captures. + // This allows us to ignore comparisons of malloc results with null, + // for example. + if (isIdentifiedObject(V)) + if (ConstantPointerNull *CPN = + dyn_cast(I->getOperand(1))) + if (CPN->getType()->getAddressSpace() == 0) + break; + // Don't count comparisons of two pointers within the same identified + // object as captures. + Value *O0 = I->getOperand(0)->getUnderlyingObject(); + if (isIdentifiedObject(O0) && + O0 == I->getOperand(1)->getUnderlyingObject()) + break; + // Otherwise, be conservative. There are crazy ways to capture pointers + // using comparisons. return true; + } default: // Something else - be conservative and say it is captured. return true; From lhames at gmail.com Thu Nov 19 18:53:30 2009 From: lhames at gmail.com (Lang Hames) Date: Fri, 20 Nov 2009 00:53:30 -0000 Subject: [llvm-commits] [llvm] r89422 - in /llvm/trunk/lib/CodeGen: RegAllocLinearScan.cpp Spiller.cpp Spiller.h Message-ID: <200911200053.nAK0rURU026323@zion.cs.uiuc.edu> Author: lhames Date: Thu Nov 19 18:53:30 2009 New Revision: 89422 URL: http://llvm.org/viewvc/llvm-project?rev=89422&view=rev Log: Removed references to LiveStacks from Spiller.* . They're no longer needed. Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp llvm/trunk/lib/CodeGen/Spiller.cpp llvm/trunk/lib/CodeGen/Spiller.h Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=89422&r1=89421&r2=89422&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Thu Nov 19 18:53:30 2009 @@ -475,7 +475,7 @@ vrm_ = &getAnalysis(); if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter()); - spiller_.reset(createSpiller(mf_, li_, ls_, loopInfo, vrm_)); + spiller_.reset(createSpiller(mf_, li_, loopInfo, vrm_)); initIntervalSets(); Modified: llvm/trunk/lib/CodeGen/Spiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=89422&r1=89421&r2=89422&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Spiller.cpp (original) +++ llvm/trunk/lib/CodeGen/Spiller.cpp Thu Nov 19 18:53:30 2009 @@ -12,7 +12,6 @@ #include "Spiller.h" #include "VirtRegMap.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" -#include "llvm/CodeGen/LiveStackAnalysis.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -47,16 +46,14 @@ MachineFunction *mf; LiveIntervals *lis; - LiveStacks *ls; MachineFrameInfo *mfi; MachineRegisterInfo *mri; const TargetInstrInfo *tii; VirtRegMap *vrm; /// Construct a spiller base. - SpillerBase(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls, - VirtRegMap *vrm) : - mf(mf), lis(lis), ls(ls), vrm(vrm) + SpillerBase(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm) + : mf(mf), lis(lis), vrm(vrm) { mfi = mf->getFrameInfo(); mri = &mf->getRegInfo(); @@ -169,9 +166,8 @@ class TrivialSpiller : public SpillerBase { public: - TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls, - VirtRegMap *vrm) - : SpillerBase(mf, lis, ls, vrm) {} + TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm) + : SpillerBase(mf, lis, vrm) {} std::vector spill(LiveInterval *li, SmallVectorImpl &spillIs) { @@ -188,7 +184,7 @@ const MachineLoopInfo *loopInfo; VirtRegMap *vrm; public: - StandardSpiller(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls, + StandardSpiller(MachineFunction *mf, LiveIntervals *lis, const MachineLoopInfo *loopInfo, VirtRegMap *vrm) : lis(lis), loopInfo(loopInfo), vrm(vrm) {} @@ -203,12 +199,11 @@ } llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis, - LiveStacks *ls, const MachineLoopInfo *loopInfo, VirtRegMap *vrm) { switch (spillerOpt) { - case trivial: return new TrivialSpiller(mf, lis, ls, vrm); break; - case standard: return new StandardSpiller(mf, lis, ls, loopInfo, vrm); break; + case trivial: return new TrivialSpiller(mf, lis, vrm); break; + case standard: return new StandardSpiller(mf, lis, loopInfo, vrm); break; default: llvm_unreachable("Unreachable!"); break; } } Modified: llvm/trunk/lib/CodeGen/Spiller.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.h?rev=89422&r1=89421&r2=89422&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Spiller.h (original) +++ llvm/trunk/lib/CodeGen/Spiller.h Thu Nov 19 18:53:30 2009 @@ -41,8 +41,7 @@ /// Create and return a spiller object, as specified on the command line. Spiller* createSpiller(MachineFunction *mf, LiveIntervals *li, - LiveStacks *ls, const MachineLoopInfo *loopInfo, - VirtRegMap *vrm); + const MachineLoopInfo *loopInfo, VirtRegMap *vrm); } #endif From evan.cheng at apple.com Thu Nov 19 18:54:04 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 20 Nov 2009 00:54:04 -0000 Subject: [llvm-commits] [llvm] r89423 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp test/CodeGen/ARM/remat.ll test/CodeGen/ARM/select-imm.ll Message-ID: <200911200054.nAK0s4gt026350@zion.cs.uiuc.edu> Author: evancheng Date: Thu Nov 19 18:54:03 2009 New Revision: 89423 URL: http://llvm.org/viewvc/llvm-project?rev=89423&view=rev Log: Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. Added: llvm/trunk/test/CodeGen/ARM/select-imm.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/test/CodeGen/ARM/remat.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=89423&r1=89422&r2=89423&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Nov 19 18:54:03 2009 @@ -151,6 +151,18 @@ /// SelectCMOVOp - Select CMOV instructions for ARM. SDNode *SelectCMOVOp(SDValue Op); + SDNode *SelectT2CMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal, + ARMCC::CondCodes CCVal, SDValue CCR, + SDValue InFlag); + SDNode *SelectARMCMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal, + ARMCC::CondCodes CCVal, SDValue CCR, + SDValue InFlag); + SDNode *SelectT2CMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal, + ARMCC::CondCodes CCVal, SDValue CCR, + SDValue InFlag); + SDNode *SelectARMCMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal, + ARMCC::CondCodes CCVal, SDValue CCR, + SDValue InFlag); /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. @@ -1305,15 +1317,92 @@ return NULL; } +SDNode *ARMDAGToDAGISel:: +SelectT2CMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal, + ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { + SDValue CPTmp0; + SDValue CPTmp1; + if (SelectT2ShifterOperandReg(Op, TrueVal, CPTmp0, CPTmp1)) { + unsigned SOVal = cast(CPTmp1)->getZExtValue(); + unsigned SOShOp = ARM_AM::getSORegShOp(SOVal); + unsigned Opc = 0; + switch (SOShOp) { + case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break; + case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break; + case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break; + case ARM_AM::ror: Opc = ARM::t2MOVCCror; break; + default: + llvm_unreachable("Unknown so_reg opcode!"); + break; + } + SDValue SOShImm = + CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32); + SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); + SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag }; + return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6); + } + return 0; +} + +SDNode *ARMDAGToDAGISel:: +SelectARMCMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal, + ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { + SDValue CPTmp0; + SDValue CPTmp1; + SDValue CPTmp2; + if (SelectShifterOperandReg(Op, TrueVal, CPTmp0, CPTmp1, CPTmp2)) { + SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); + SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag }; + return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7); + } + return 0; +} + +SDNode *ARMDAGToDAGISel:: +SelectT2CMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal, + ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { + ConstantSDNode *T = dyn_cast(TrueVal); + if (!T) + return 0; + + if (Predicate_t2_so_imm(TrueVal.getNode())) { + SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); + SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); + SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; + return CurDAG->SelectNodeTo(Op.getNode(), + ARM::t2MOVCCi, MVT::i32, Ops, 5); + } + return 0; +} + +SDNode *ARMDAGToDAGISel:: +SelectARMCMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal, + ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { + ConstantSDNode *T = dyn_cast(TrueVal); + if (!T) + return 0; + + if (Predicate_so_imm(TrueVal.getNode())) { + SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); + SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); + SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; + return CurDAG->SelectNodeTo(Op.getNode(), + ARM::MOVCCi, MVT::i32, Ops, 5); + } + return 0; +} + SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) { EVT VT = Op.getValueType(); - SDValue N0 = Op.getOperand(0); - SDValue N1 = Op.getOperand(1); - SDValue N2 = Op.getOperand(2); - SDValue N3 = Op.getOperand(3); + SDValue FalseVal = Op.getOperand(0); + SDValue TrueVal = Op.getOperand(1); + SDValue CC = Op.getOperand(2); + SDValue CCR = Op.getOperand(3); SDValue InFlag = Op.getOperand(4); - assert(N2.getOpcode() == ISD::Constant); - assert(N3.getOpcode() == ISD::Register); + assert(CC.getOpcode() == ISD::Constant); + assert(CCR.getOpcode() == ISD::Register); + ARMCC::CondCodes CCVal = + (ARMCC::CondCodes)cast(CC)->getZExtValue(); if (!Subtarget->isThumb1Only() && VT == MVT::i32) { // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) @@ -1323,36 +1412,21 @@ SDValue CPTmp1; SDValue CPTmp2; if (Subtarget->isThumb()) { - if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) { - unsigned SOVal = cast(CPTmp1)->getZExtValue(); - unsigned SOShOp = ARM_AM::getSORegShOp(SOVal); - unsigned Opc = 0; - switch (SOShOp) { - case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break; - case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break; - case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break; - case ARM_AM::ror: Opc = ARM::t2MOVCCror; break; - default: - llvm_unreachable("Unknown so_reg opcode!"); - break; - } - SDValue SOShImm = - CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32); - SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) - cast(N2)->getZExtValue()), - MVT::i32); - SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag }; - return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6); - } + SDNode *Res = SelectT2CMOVShiftOp(Op, FalseVal, TrueVal, + CCVal, CCR, InFlag); + if (!Res) + Res = SelectT2CMOVShiftOp(Op, TrueVal, FalseVal, + ARMCC::getOppositeCondition(CCVal), CCR, InFlag); + if (Res) + return Res; } else { - if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) { - SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) - cast(N2)->getZExtValue()), - MVT::i32); - SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag }; - return CurDAG->SelectNodeTo(Op.getNode(), - ARM::MOVCCs, MVT::i32, Ops, 7); - } + SDNode *Res = SelectARMCMOVShiftOp(Op, FalseVal, TrueVal, + CCVal, CCR, InFlag); + if (!Res) + Res = SelectARMCMOVShiftOp(Op, TrueVal, FalseVal, + ARMCC::getOppositeCondition(CCVal), CCR, InFlag); + if (Res) + return Res; } // Pattern: (ARMcmov:i32 GPR:i32:$false, @@ -1361,32 +1435,22 @@ // Emits: (MOVCCi:i32 GPR:i32:$false, // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc) // Pattern complexity = 10 cost = 1 size = 0 - if (N3.getOpcode() == ISD::Constant) { - if (Subtarget->isThumb()) { - if (Predicate_t2_so_imm(N3.getNode())) { - SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) - cast(N1)->getZExtValue()), - MVT::i32); - SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) - cast(N2)->getZExtValue()), - MVT::i32); - SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag }; - return CurDAG->SelectNodeTo(Op.getNode(), - ARM::t2MOVCCi, MVT::i32, Ops, 5); - } - } else { - if (Predicate_so_imm(N3.getNode())) { - SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) - cast(N1)->getZExtValue()), - MVT::i32); - SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) - cast(N2)->getZExtValue()), - MVT::i32); - SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag }; - return CurDAG->SelectNodeTo(Op.getNode(), - ARM::MOVCCi, MVT::i32, Ops, 5); - } - } + if (Subtarget->isThumb()) { + SDNode *Res = SelectT2CMOVSoImmOp(Op, FalseVal, TrueVal, + CCVal, CCR, InFlag); + if (!Res) + Res = SelectT2CMOVSoImmOp(Op, TrueVal, FalseVal, + ARMCC::getOppositeCondition(CCVal), CCR, InFlag); + if (Res) + return Res; + } else { + SDNode *Res = SelectARMCMOVSoImmOp(Op, FalseVal, TrueVal, + CCVal, CCR, InFlag); + if (!Res) + Res = SelectARMCMOVSoImmOp(Op, TrueVal, FalseVal, + ARMCC::getOppositeCondition(CCVal), CCR, InFlag); + if (Res) + return Res; } } @@ -1399,10 +1463,8 @@ // Pattern complexity = 6 cost = 11 size = 0 // // Also FCPYScc and FCPYDcc. - SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) - cast(N2)->getZExtValue()), - MVT::i32); - SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag }; + SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32); + SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag }; unsigned Opc = 0; switch (VT.getSimpleVT().SimpleTy) { default: assert(false && "Illegal conditional move type!"); Modified: llvm/trunk/test/CodeGen/ARM/remat.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/remat.ll?rev=89423&r1=89422&r2=89423&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/remat.ll (original) +++ llvm/trunk/test/CodeGen/ARM/remat.ll Thu Nov 19 18:54:03 2009 @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 5 +; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 3 %struct.CONTENTBOX = type { i32, i32, i32, i32, i32 } %struct.LOCBOX = type { i32, i32, i32, i32 } Added: llvm/trunk/test/CodeGen/ARM/select-imm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select-imm.ll?rev=89423&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/select-imm.ll (added) +++ llvm/trunk/test/CodeGen/ARM/select-imm.ll Thu Nov 19 18:54:03 2009 @@ -0,0 +1,48 @@ +; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s --check-prefix=T2 + +define arm_apcscc i32 @t1(i32 %c) nounwind readnone { +entry: +; ARM: t1: +; ARM: mov r1, #101 +; ARM: orr r1, r1, #1, 24 +; ARM: movgt r0, #123 + +; T2: t1: +; T2: movw r0, #357 +; T2: movgt r0, #123 + + %0 = icmp sgt i32 %c, 1 + %1 = select i1 %0, i32 123, i32 357 + ret i32 %1 +} + +define arm_apcscc i32 @t2(i32 %c) nounwind readnone { +entry: +; ARM: t2: +; ARM: mov r1, #101 +; ARM: orr r1, r1, #1, 24 +; ARM: movle r0, #123 + +; T2: t2: +; T2: movw r0, #357 +; T2: movle r0, #123 + + %0 = icmp sgt i32 %c, 1 + %1 = select i1 %0, i32 357, i32 123 + ret i32 %1 +} + +define arm_apcscc i32 @t3(i32 %a) nounwind readnone { +entry: +; ARM: t3: +; ARM: mov r0, #0 +; ARM: moveq r0, #1 + +; T2: t3: +; T2: mov r0, #0 +; T2: moveq r0, #1 + %0 = icmp eq i32 %a, 160 + %1 = zext i1 %0 to i32 + ret i32 %1 +} From scallanan at apple.com Thu Nov 19 19:00:15 2009 From: scallanan at apple.com (Sean Callanan) Date: Thu, 19 Nov 2009 17:00:15 -0800 Subject: [llvm-commits] Instruction fixes Message-ID: <1B17A8DA-F1CF-4155-A000-893BC242D682@apple.com> During the testing of the disassembler, I encountered many instructions that were missing, malformed, had missing forms, or had missing qualifiers. I went through and added these to the instruction tables, and fixed the test cases as needed. This patch affects no patterns. It only addresses assembly, operand width (in certain cases) and cosmetic/style issues. Please find the patch attached. It has received a preliminary vetting from Eric Christopher , and I am now submitting it for inclusion into LLVM proper. The change log is below. Sean -------------- next part -------------- A non-text attachment was scrubbed... Name: Instructions patch 11-19-2009.diff Type: application/octet-stream Size: 142441 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091119/bd58d659/attachment.obj -------------- next part -------------- ? 2009-11-19 Sean Callanan * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added qualifier; added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * if-tail-dup.ll: Fixed testcase to reflect jump qualifier * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov and jump qualifiers * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect jump and call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier From gohman at apple.com Thu Nov 19 19:09:34 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 01:09:34 -0000 Subject: [llvm-commits] [llvm] r89426 - in /llvm/trunk: lib/Analysis/LoopInfo.cpp test/Transforms/LoopUnroll/shifted-tripcount.ll Message-ID: <200911200109.nAK19YKI026946@zion.cs.uiuc.edu> Author: djg Date: Thu Nov 19 19:09:34 2009 New Revision: 89426 URL: http://llvm.org/viewvc/llvm-project?rev=89426&view=rev Log: Teach getSmallConstantTripMultiple about Shl operators. Added: llvm/trunk/test/Transforms/LoopUnroll/shifted-tripcount.ll Modified: llvm/trunk/lib/Analysis/LoopInfo.cpp Modified: llvm/trunk/lib/Analysis/LoopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopInfo.cpp?rev=89426&r1=89425&r2=89426&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LoopInfo.cpp (original) +++ llvm/trunk/lib/Analysis/LoopInfo.cpp Thu Nov 19 19:09:34 2009 @@ -243,6 +243,11 @@ case BinaryOperator::Mul: Result = dyn_cast(BO->getOperand(1)); break; + case BinaryOperator::Shl: + if (ConstantInt *CI = dyn_cast(BO->getOperand(1))) + if (CI->getValue().getActiveBits() <= 5) + return 1u << CI->getZExtValue(); + break; default: break; } Added: llvm/trunk/test/Transforms/LoopUnroll/shifted-tripcount.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnroll/shifted-tripcount.ll?rev=89426&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopUnroll/shifted-tripcount.ll (added) +++ llvm/trunk/test/Transforms/LoopUnroll/shifted-tripcount.ll Thu Nov 19 19:09:34 2009 @@ -0,0 +1,28 @@ +; RUN: opt < %s -loop-unroll -unroll-count=2 -S | FileCheck %s + +; LoopUnroll should unroll this loop into one big basic block. + +; CHECK: for.body: +; CHECK: %i.013 = phi i64 [ 0, %entry ], [ %tmp16.1, %for.body ] +; CHECK: br i1 %exitcond.1, label %for.end, label %for.body + +define void @foo(double* nocapture %p, i64 %n) nounwind { +entry: + %mul10 = shl i64 %n, 1 ; [#uses=2] + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.013 = phi i64 [ %tmp16, %for.body ], [ 0, %entry ] ; [#uses=2] + %arrayidx7 = getelementptr double* %p, i64 %i.013 ; [#uses=2] + %tmp16 = add i64 %i.013, 1 ; [#uses=3] + %arrayidx = getelementptr double* %p, i64 %tmp16 ; [#uses=1] + %tmp4 = load double* %arrayidx ; [#uses=1] + %tmp8 = load double* %arrayidx7 ; [#uses=1] + %mul9 = fmul double %tmp8, %tmp4 ; [#uses=1] + store double %mul9, double* %arrayidx7 + %exitcond = icmp eq i64 %tmp16, %mul10 ; [#uses=1] + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} From dalej at apple.com Thu Nov 19 19:09:41 2009 From: dalej at apple.com (Dale Johannesen) Date: Thu, 19 Nov 2009 17:09:41 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r89415 - in /llvm-gcc-4.2/trunk/gcc: config/darwin.h llvm-backend.cpp In-Reply-To: <200911200031.nAK0VpKv025598@zion.cs.uiuc.edu> References: <200911200031.nAK0VpKv025598@zion.cs.uiuc.edu> Message-ID: On Nov 19, 2009, at 4:31 PMPST, Bill Wendling wrote: > Author: void > Date: Thu Nov 19 18:31:31 2009 > New Revision: 89415 > > URL: http://llvm.org/viewvc/llvm-project?rev=89415&view=rev > Log: > Adjust the alignment of strings so that they aren't over aligned. We > only need > them aligned to 8-bytes instead of 16-bytes for 64-bit. And 4 > instead of 8 in > 32-bit. Maybe so, but I bet there is a good reason it was the way it was. Did you do any performance measurements? From echristo at apple.com Thu Nov 19 19:11:41 2009 From: echristo at apple.com (Eric Christopher) Date: Thu, 19 Nov 2009 17:11:41 -0800 Subject: [llvm-commits] Instruction fixes In-Reply-To: <1B17A8DA-F1CF-4155-A000-893BC242D682@apple.com> References: <1B17A8DA-F1CF-4155-A000-893BC242D682@apple.com> Message-ID: <1363C2A2-FC17-4FE8-9709-C143D2AA357B@apple.com> On Nov 19, 2009, at 5:00 PM, Sean Callanan wrote: > Obviously looks ok to me. :) One thing I just noticed was the whitespace changes in the test matching, perhaps a regexp for "some whitespace here" instead? -eric From stoklund at 2pi.dk Thu Nov 19 19:17:03 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 20 Nov 2009 01:17:03 -0000 Subject: [llvm-commits] [llvm] r89428 - in /llvm/trunk: include/llvm/CodeGen/MachineBasicBlock.h lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/MachineBasicBlock.cpp lib/CodeGen/MachineLICM.cpp lib/CodeGen/MachineVerifier.cpp lib/CodeGen/SimpleRegisterCoalescing.cpp lib/CodeGen/VirtRegRewriter.cpp Message-ID: <200911200117.nAK1H3JO027284@zion.cs.uiuc.edu> Author: stoklund Date: Thu Nov 19 19:17:03 2009 New Revision: 89428 URL: http://llvm.org/viewvc/llvm-project?rev=89428&view=rev Log: Add MachineBasicBlock::getName, and use it in place of getBasicBlock()->getName. Fix debug code that assumes getBasicBlock never returns NULL. Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/CodeGen/MachineLICM.cpp llvm/trunk/lib/CodeGen/MachineVerifier.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=89428&r1=89427&r2=89428&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Thu Nov 19 19:17:03 2009 @@ -92,10 +92,15 @@ public: /// getBasicBlock - Return the LLVM basic block that this instance - /// corresponded to originally. + /// corresponded to originally. Note that this may be NULL if this instance + /// does not correspond directly to an LLVM basic block. /// const BasicBlock *getBasicBlock() const { return BB; } + /// getName - Return the name of the corresponding LLVM basic block, or + /// "(null)". + StringRef getName() const; + /// hasAddressTaken - Test whether this block is potentially the target /// of an indirect branch. bool hasAddressTaken() const { return AddressTaken; } Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=89428&r1=89427&r2=89428&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Nov 19 19:17:03 2009 @@ -136,7 +136,7 @@ for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); mbbi != mbbe; ++mbbi) { - OS << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; + OS << mbbi->getName() << ":\n"; for (MachineBasicBlock::iterator mii = mbbi->begin(), mie = mbbi->end(); mii != mie; ++mii) { OS << getInstructionIndex(mii) << '\t' << *mii; @@ -658,7 +658,7 @@ MachineBasicBlock *MBB = MBBI; // Track the index of the current machine instr. SlotIndex MIIndex = getMBBStartIdx(MBB); - DEBUG(errs() << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); + DEBUG(errs() << MBB->getName() << ":\n"); MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end(); Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=89428&r1=89427&r2=89428&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Thu Nov 19 19:17:03 2009 @@ -172,6 +172,13 @@ os << " %reg" << RegNo; } +StringRef MachineBasicBlock::getName() const { + if (const BasicBlock *LBB = getBasicBlock()) + return LBB->getName(); + else + return "(null)"; +} + void MachineBasicBlock::print(raw_ostream &OS) const { const MachineFunction *MF = getParent(); if (!MF) { Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=89428&r1=89427&r2=89428&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Thu Nov 19 19:17:03 2009 @@ -487,10 +487,10 @@ errs() << "Hoisting " << *MI; if (CurPreheader->getBasicBlock()) errs() << " to MachineBasicBlock " - << CurPreheader->getBasicBlock()->getName(); + << CurPreheader->getName(); if (MI->getParent()->getBasicBlock()) errs() << " from MachineBasicBlock " - << MI->getParent()->getBasicBlock()->getName(); + << MI->getParent()->getName(); errs() << "\n"; }); Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=89428&r1=89427&r2=89428&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Thu Nov 19 19:17:03 2009 @@ -305,7 +305,7 @@ void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) { assert(MBB); report(msg, MBB->getParent()); - *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr() + *OS << "- basic block: " << MBB->getName() << " " << (void*)MBB << " (BB#" << MBB->getNumber() << ")\n"; } Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=89428&r1=89427&r2=89428&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Nov 19 19:17:03 2009 @@ -2380,7 +2380,7 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB, std::vector &TryAgain) { - DEBUG(errs() << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); + DEBUG(errs() << MBB->getName() << ":\n"); std::vector VirtCopies; std::vector PhysCopies; Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=89428&r1=89427&r2=89428&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Thu Nov 19 19:17:03 2009 @@ -1600,7 +1600,7 @@ std::vector &KillOps) { DEBUG(errs() << "\n**** Local spiller rewriting MBB '" - << MBB.getBasicBlock()->getName() << "':\n"); + << MBB.getName() << "':\n"); MachineFunction &MF = *MBB.getParent(); From gohman at apple.com Thu Nov 19 19:34:03 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 01:34:03 -0000 Subject: [llvm-commits] [llvm] r89434 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp Message-ID: <200911200134.nAK1Y38v027923@zion.cs.uiuc.edu> Author: djg Date: Thu Nov 19 19:34:03 2009 New Revision: 89434 URL: http://llvm.org/viewvc/llvm-project?rev=89434&view=rev Log: Simplify this code; it's not necessary to check isIdentifiedObject here because if the results from getUnderlyingObject match, the values must be from the same underlying object, even if we don't know what that object is. Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CaptureTracking.cpp?rev=89434&r1=89433&r2=89434&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CaptureTracking.cpp (original) +++ llvm/trunk/lib/Analysis/CaptureTracking.cpp Thu Nov 19 19:34:03 2009 @@ -105,7 +105,7 @@ Worklist.push_back(U); } break; - case Instruction::ICmp: { + case Instruction::ICmp: // Don't count comparisons of the original value against null as captures. // This allows us to ignore comparisons of malloc results with null, // for example. @@ -114,16 +114,14 @@ dyn_cast(I->getOperand(1))) if (CPN->getType()->getAddressSpace() == 0) break; - // Don't count comparisons of two pointers within the same identified - // object as captures. - Value *O0 = I->getOperand(0)->getUnderlyingObject(); - if (isIdentifiedObject(O0) && - O0 == I->getOperand(1)->getUnderlyingObject()) + // Don't count comparisons of two pointers within the same object + // as captures. + if (I->getOperand(0)->getUnderlyingObject() == + I->getOperand(1)->getUnderlyingObject()) break; // Otherwise, be conservative. There are crazy ways to capture pointers // using comparisons. return true; - } default: // Something else - be conservative and say it is captured. return true; From gohman at apple.com Thu Nov 19 20:03:44 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 02:03:44 -0000 Subject: [llvm-commits] [llvm] r89439 - /llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Message-ID: <200911200203.nAK23ico028988@zion.cs.uiuc.edu> Author: djg Date: Thu Nov 19 20:03:44 2009 New Revision: 89439 URL: http://llvm.org/viewvc/llvm-project?rev=89439&view=rev Log: Add an experimental option to run gep-splitting and no-load GVN just before codegen. Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=89439&r1=89438&r2=89439&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu Nov 19 20:03:44 2009 @@ -66,6 +66,11 @@ EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \"fast\" instruction selector")); +// Enable or disable an experimental optimization to split GEPs +// and run a special GVN pass which does not examine loads, in +// an effort to factor out redundancy implicit in complex GEPs. +static cl::opt EnableSplitGEPGVN("split-gep-gvn", cl::Hidden, + cl::desc("Split GEPs and run no-load GVN")); LLVMTargetMachine::LLVMTargetMachine(const Target &T, const std::string &TargetTriple) @@ -223,6 +228,12 @@ CodeGenOpt::Level OptLevel) { // Standard LLVM-Level Passes. + // Optionally, tun split-GEPs and no-load GVN. + if (EnableSplitGEPGVN) { + PM.add(createGEPSplitterPass()); + PM.add(createGVNPass(/*NoPRE=*/false, /*NoLoads=*/true)); + } + // Run loop strength reduction before anything else. if (OptLevel != CodeGenOpt::None && !DisableLSR) { PM.add(createLoopStrengthReducePass(getTargetLowering())); From evan.cheng at apple.com Thu Nov 19 20:06:06 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 19 Nov 2009 18:06:06 -0800 Subject: [llvm-commits] [llvm] r89403 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp In-Reply-To: <200911192310.nAJNASND022655@zion.cs.uiuc.edu> References: <200911192310.nAJNASND022655@zion.cs.uiuc.edu> Message-ID: Do we have to run verifySizes in release mode? That will slow things down. Evan On Nov 19, 2009, at 3:10 PM, Jim Grosbach wrote: > Author: grosbach > Date: Thu Nov 19 17:10:28 2009 > New Revision: 89403 > > URL: http://llvm.org/viewvc/llvm-project?rev=89403&view=rev > Log: > When placing constant islands and adjusting for alignment padding, inline > assembly can confuse things utterly, as it's assumed that instructions in > inline assembly are 4 bytes wide. For Thumb mode, that's often not true, > so the calculations for when alignment padding will be present get thrown off, > ultimately leading to out of range constant pool entry references. Making > more conservative assumptions that padding may be necessary when inline asm > is present avoids this situation. > > > Modified: > llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=89403&r1=89402&r2=89403&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Thu Nov 19 17:10:28 2009 > @@ -162,6 +162,9 @@ > /// the branch fix up pass. > bool HasFarJump; > > + /// HasInlineAsm - True if the function contains inline assembly. > + bool HasInlineAsm; > + > const TargetInstrInfo *TII; > const ARMSubtarget *STI; > ARMFunctionInfo *AFI; > @@ -218,10 +221,45 @@ > unsigned GetOffsetOf(MachineInstr *MI) const; > void dumpBBs(); > void verify(MachineFunction &MF); > + void verifySizes(MachineFunction &MF); > }; > char ARMConstantIslands::ID = 0; > } > > +// verifySizes - Recalculate BB sizes from scratch and validate that the result > +// matches the values we've been using. > +void ARMConstantIslands::verifySizes(MachineFunction &MF) { > + unsigned Offset = 0; > + for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); > + MBBI != E; ++MBBI) { > + MachineBasicBlock &MBB = *MBBI; > + unsigned MBBSize = 0; > + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); > + I != E; ++I) { > + // Add instruction size to MBBSize. > + MBBSize += TII->GetInstSizeInBytes(I); > + } > + // In thumb mode, if this block is a constpool island, we may need padding > + // so it's aligned on 4 byte boundary. > + if (isThumb && > + !MBB.empty() && > + MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY && > + ((Offset%4) != 0 || HasInlineAsm)) > + MBBSize += 2; > + Offset += MBBSize; > + > + DEBUG(errs() << "block #" << MBB.getNumber() << ": " > + << MBBSize << " bytes (expecting " << BBSizes[MBB.getNumber()] > + << (MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY ? > + " CONSTANTPOOL" : "") << ")\n"); > +#ifndef NDEBUG > + if (MBBSize != BBSizes[MBB.getNumber()]) > + MBB.dump(); > +#endif > + assert (MBBSize == BBSizes[MBB.getNumber()] && "block size mismatch!"); > + } > +} > + > /// verify - check BBOffsets, BBSizes, alignment of islands > void ARMConstantIslands::verify(MachineFunction &MF) { > assert(BBOffsets.size() == BBSizes.size()); > @@ -236,11 +274,17 @@ > if (!MBB->empty() && > MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) { > unsigned MBBId = MBB->getNumber(); > - assert((BBOffsets[MBBId]%4 == 0 && BBSizes[MBBId]%4 == 0) || > + assert(HasInlineAsm || > + (BBOffsets[MBBId]%4 == 0 && BBSizes[MBBId]%4 == 0) || > (BBOffsets[MBBId]%4 != 0 && BBSizes[MBBId]%4 != 0)); > } > } > #endif > + for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) { > + CPUser &U = CPUsers[i]; > + unsigned UserOffset = GetOffsetOf(U.MI) + (isThumb ? 4 : 8); > + assert (CPEIsInRange(U.MI, UserOffset, U.CPEMI, U.MaxDisp, U.NegOk, true)); > + } > } > > /// print block size and offset information - debugging > @@ -269,6 +313,7 @@ > isThumb2 = AFI->isThumb2Function(); > > HasFarJump = false; > + HasInlineAsm = false; > > // Renumber all of the machine basic blocks in the function, guaranteeing that > // the numbers agree with the position of the block in the function. > @@ -347,6 +392,7 @@ > > // After a while, this might be made debug-only, but it is not expensive. > verify(MF); > + verifySizes(MF); > > // If LR has been forced spilled and no far jumps (i.e. BL) has been issued. > // Undo the spill / restore of LR if possible. > @@ -452,6 +498,19 @@ > /// and finding all of the constant pool users. > void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF, > const std::vector &CPEMIs) { > + // First thing, see if the function has any inline assembly in it. If so, > + // we have to be conservative about alignment assumptions, as we don't > + // know for sure the size of any instructions in the inline assembly. > + for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); > + MBBI != E; ++MBBI) { > + MachineBasicBlock &MBB = *MBBI; > + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); > + I != E; ++I) > + if (I->getOpcode() == ARM::INLINEASM) > + HasInlineAsm = true; > + } > + > + // Now go back through the instructions and build up our data structures > unsigned Offset = 0; > for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); > MBBI != E; ++MBBI) { > @@ -481,7 +540,7 @@ > // A Thumb1 table jump may involve padding; for the offsets to > // be right, functions containing these must be 4-byte aligned. > AFI->setAlign(2U); > - if ((Offset+MBBSize)%4 != 0) > + if ((Offset+MBBSize)%4 != 0 || HasInlineAsm) > // FIXME: Add a pseudo ALIGN instruction instead. > MBBSize += 2; // padding > continue; // Does not get an entry in ImmBranches > @@ -609,7 +668,7 @@ > if (isThumb && > !MBB.empty() && > MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY && > - (Offset%4) != 0) > + ((Offset%4) != 0 || HasInlineAsm)) > MBBSize += 2; > > BBSizes.push_back(MBBSize); > @@ -633,7 +692,7 @@ > // alignment padding, and compensate if so. > if (isThumb && > MI->getOpcode() == ARM::CONSTPOOL_ENTRY && > - Offset%4 != 0) > + (Offset%4 != 0 || HasInlineAsm)) > Offset += 2; > > // Sum instructions before MI in MBB. > @@ -829,7 +888,7 @@ > MachineInstr *CPEMI, unsigned MaxDisp, > bool NegOk, bool DoDump) { > unsigned CPEOffset = GetOffsetOf(CPEMI); > - assert(CPEOffset%4 == 0 && "Misaligned CPE"); > + assert((CPEOffset%4 == 0 || HasInlineAsm) && "Misaligned CPE"); > > if (DoDump) { > DEBUG(errs() << "User of CPE#" << CPEMI->getOperand(0).getImm() > @@ -870,7 +929,7 @@ > if (!isThumb) > continue; > MachineBasicBlock *MBB = MBBI; > - if (!MBB->empty()) { > + if (!MBB->empty() && !HasInlineAsm) { > // Constant pool entries require padding. > if (MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) { > unsigned OldOffset = BBOffsets[i] - delta; > @@ -1226,7 +1285,7 @@ > > BBOffsets[NewIsland->getNumber()] = BBOffsets[NewMBB->getNumber()]; > // Compensate for .align 2 in thumb mode. > - if (isThumb && BBOffsets[NewIsland->getNumber()]%4 != 0) > + if (isThumb && (BBOffsets[NewIsland->getNumber()]%4 != 0 || HasInlineAsm)) > Size += 2; > // Increase the size of the island block to account for the new entry. > BBSizes[NewIsland->getNumber()] += Size; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Thu Nov 19 20:10:27 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 20 Nov 2009 02:10:27 -0000 Subject: [llvm-commits] [llvm] r89440 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/Thumb2/machine-licm.ll Message-ID: <200911200210.nAK2AReq029199@zion.cs.uiuc.edu> Author: evancheng Date: Thu Nov 19 20:10:27 2009 New Revision: 89440 URL: http://llvm.org/viewvc/llvm-project?rev=89440&view=rev Log: Also CSE non-pic load from constant pools. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=89440&r1=89439&r2=89440&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Nov 19 20:10:27 2009 @@ -978,7 +978,10 @@ const MachineInstr *MI1, const MachineRegisterInfo *MRI) const { int Opcode = MI0->getOpcode(); - if (Opcode == ARM::t2LDRpci_pic || Opcode == ARM::tLDRpci_pic) { + if (Opcode == ARM::t2LDRpci || + Opcode == ARM::t2LDRpci_pic || + Opcode == ARM::tLDRpci || + Opcode == ARM::tLDRpci_pic) { if (MI1->getOpcode() != Opcode) return false; if (MI0->getNumOperands() != MI1->getNumOperands()) Modified: llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll?rev=89440&r1=89439&r2=89440&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Thu Nov 19 20:10:27 2009 @@ -1,4 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC ; rdar://7353541 ; rdar://7354376 @@ -17,12 +18,20 @@ bb.nph: ; preds = %entry ; CHECK: BB#1 ; CHECK: ldr.n r2, LCPI1_0 -; CHECK: add r2, pc ; CHECK: ldr r{{[0-9]+}}, [r2] ; CHECK: LBB1_2 ; CHECK: LCPI1_0: ; CHECK-NOT: LCPI1_1: ; CHECK: .section + +; PIC: BB#1 +; PIC: ldr.n r2, LCPI1_0 +; PIC: add r2, pc +; PIC: ldr r{{[0-9]+}}, [r2] +; PIC: LBB1_2 +; PIC: LCPI1_0: +; PIC-NOT: LCPI1_1: +; PIC: .section %.pre = load i32* @GV, align 4 ; [#uses=1] br label %bb From grosbach at apple.com Thu Nov 19 20:18:53 2009 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 19 Nov 2009 18:18:53 -0800 Subject: [llvm-commits] [llvm] r89403 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp In-Reply-To: References: <200911192310.nAJNASND022655@zion.cs.uiuc.edu> Message-ID: <76369418-3903-4073-B620-620DDB968AFD@apple.com> No, it can definitely be restricted to just debug mode. Honestly, upon reflection, I'm not sure it's adding much value at all. I was using it to help validate my assumptions while tracking this problem down, but it didn't really end up helping much. What do you think? -Jim On Nov 19, 2009, at 6:06 PM, Evan Cheng wrote: > Do we have to run verifySizes in release mode? That will slow things > down. > > Evan > > On Nov 19, 2009, at 3:10 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Thu Nov 19 17:10:28 2009 >> New Revision: 89403 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=89403&view=rev >> Log: >> When placing constant islands and adjusting for alignment padding, >> inline >> assembly can confuse things utterly, as it's assumed that >> instructions in >> inline assembly are 4 bytes wide. For Thumb mode, that's often not >> true, >> so the calculations for when alignment padding will be present get >> thrown off, >> ultimately leading to out of range constant pool entry references. >> Making >> more conservative assumptions that padding may be necessary when >> inline asm >> is present avoids this situation. >> >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp >> >> Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=89403&r1=89402&r2=89403&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Thu Nov 19 >> 17:10:28 2009 >> @@ -162,6 +162,9 @@ >> /// the branch fix up pass. >> bool HasFarJump; >> >> + /// HasInlineAsm - True if the function contains inline >> assembly. >> + bool HasInlineAsm; >> + >> const TargetInstrInfo *TII; >> const ARMSubtarget *STI; >> ARMFunctionInfo *AFI; >> @@ -218,10 +221,45 @@ >> unsigned GetOffsetOf(MachineInstr *MI) const; >> void dumpBBs(); >> void verify(MachineFunction &MF); >> + void verifySizes(MachineFunction &MF); >> }; >> char ARMConstantIslands::ID = 0; >> } >> >> +// verifySizes - Recalculate BB sizes from scratch and validate >> that the result >> +// matches the values we've been using. >> +void ARMConstantIslands::verifySizes(MachineFunction &MF) { >> + unsigned Offset = 0; >> + for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); >> + MBBI != E; ++MBBI) { >> + MachineBasicBlock &MBB = *MBBI; >> + unsigned MBBSize = 0; >> + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); >> + I != E; ++I) { >> + // Add instruction size to MBBSize. >> + MBBSize += TII->GetInstSizeInBytes(I); >> + } >> + // In thumb mode, if this block is a constpool island, we may >> need padding >> + // so it's aligned on 4 byte boundary. >> + if (isThumb && >> + !MBB.empty() && >> + MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY && >> + ((Offset%4) != 0 || HasInlineAsm)) >> + MBBSize += 2; >> + Offset += MBBSize; >> + >> + DEBUG(errs() << "block #" << MBB.getNumber() << ": " >> + << MBBSize << " bytes (expecting " << BBSizes >> [MBB.getNumber()] >> + << (MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY ? >> + " CONSTANTPOOL" : "") << ")\n"); >> +#ifndef NDEBUG >> + if (MBBSize != BBSizes[MBB.getNumber()]) >> + MBB.dump(); >> +#endif >> + assert (MBBSize == BBSizes[MBB.getNumber()] && "block size >> mismatch!"); >> + } >> +} >> + >> /// verify - check BBOffsets, BBSizes, alignment of islands >> void ARMConstantIslands::verify(MachineFunction &MF) { >> assert(BBOffsets.size() == BBSizes.size()); >> @@ -236,11 +274,17 @@ >> if (!MBB->empty() && >> MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) { >> unsigned MBBId = MBB->getNumber(); >> - assert((BBOffsets[MBBId]%4 == 0 && BBSizes[MBBId]%4 == 0) || >> + assert(HasInlineAsm || >> + (BBOffsets[MBBId]%4 == 0 && BBSizes[MBBId]%4 == 0) || >> (BBOffsets[MBBId]%4 != 0 && BBSizes[MBBId]%4 != 0)); >> } >> } >> #endif >> + for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) { >> + CPUser &U = CPUsers[i]; >> + unsigned UserOffset = GetOffsetOf(U.MI) + (isThumb ? 4 : 8); >> + assert (CPEIsInRange(U.MI, UserOffset, U.CPEMI, U.MaxDisp, >> U.NegOk, true)); >> + } >> } >> >> /// print block size and offset information - debugging >> @@ -269,6 +313,7 @@ >> isThumb2 = AFI->isThumb2Function(); >> >> HasFarJump = false; >> + HasInlineAsm = false; >> >> // Renumber all of the machine basic blocks in the function, >> guaranteeing that >> // the numbers agree with the position of the block in the function. >> @@ -347,6 +392,7 @@ >> >> // After a while, this might be made debug-only, but it is not >> expensive. >> verify(MF); >> + verifySizes(MF); >> >> // If LR has been forced spilled and no far jumps (i.e. BL) has >> been issued. >> // Undo the spill / restore of LR if possible. >> @@ -452,6 +498,19 @@ >> /// and finding all of the constant pool users. >> void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF, >> const std::vector >> &CPEMIs) { >> + // First thing, see if the function has any inline assembly in >> it. If so, >> + // we have to be conservative about alignment assumptions, as we >> don't >> + // know for sure the size of any instructions in the inline >> assembly. >> + for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); >> + MBBI != E; ++MBBI) { >> + MachineBasicBlock &MBB = *MBBI; >> + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); >> + I != E; ++I) >> + if (I->getOpcode() == ARM::INLINEASM) >> + HasInlineAsm = true; >> + } >> + >> + // Now go back through the instructions and build up our data >> structures >> unsigned Offset = 0; >> for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); >> MBBI != E; ++MBBI) { >> @@ -481,7 +540,7 @@ >> // A Thumb1 table jump may involve padding; for the >> offsets to >> // be right, functions containing these must be 4-byte >> aligned. >> AFI->setAlign(2U); >> - if ((Offset+MBBSize)%4 != 0) >> + if ((Offset+MBBSize)%4 != 0 || HasInlineAsm) >> // FIXME: Add a pseudo ALIGN instruction instead. >> MBBSize += 2; // padding >> continue; // Does not get an entry in ImmBranches >> @@ -609,7 +668,7 @@ >> if (isThumb && >> !MBB.empty() && >> MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY && >> - (Offset%4) != 0) >> + ((Offset%4) != 0 || HasInlineAsm)) >> MBBSize += 2; >> >> BBSizes.push_back(MBBSize); >> @@ -633,7 +692,7 @@ >> // alignment padding, and compensate if so. >> if (isThumb && >> MI->getOpcode() == ARM::CONSTPOOL_ENTRY && >> - Offset%4 != 0) >> + (Offset%4 != 0 || HasInlineAsm)) >> Offset += 2; >> >> // Sum instructions before MI in MBB. >> @@ -829,7 +888,7 @@ >> MachineInstr *CPEMI, unsigned >> MaxDisp, >> bool NegOk, bool DoDump) { >> unsigned CPEOffset = GetOffsetOf(CPEMI); >> - assert(CPEOffset%4 == 0 && "Misaligned CPE"); >> + assert((CPEOffset%4 == 0 || HasInlineAsm) && "Misaligned CPE"); >> >> if (DoDump) { >> DEBUG(errs() << "User of CPE#" << CPEMI->getOperand(0).getImm() >> @@ -870,7 +929,7 @@ >> if (!isThumb) >> continue; >> MachineBasicBlock *MBB = MBBI; >> - if (!MBB->empty()) { >> + if (!MBB->empty() && !HasInlineAsm) { >> // Constant pool entries require padding. >> if (MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) { >> unsigned OldOffset = BBOffsets[i] - delta; >> @@ -1226,7 +1285,7 @@ >> >> BBOffsets[NewIsland->getNumber()] = BBOffsets[NewMBB->getNumber()]; >> // Compensate for .align 2 in thumb mode. >> - if (isThumb && BBOffsets[NewIsland->getNumber()]%4 != 0) >> + if (isThumb && (BBOffsets[NewIsland->getNumber()]%4 != 0 || >> HasInlineAsm)) >> Size += 2; >> // Increase the size of the island block to account for the new >> entry. >> BBSizes[NewIsland->getNumber()] += Size; >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From evan.cheng at apple.com Thu Nov 19 20:26:58 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 19 Nov 2009 18:26:58 -0800 Subject: [llvm-commits] [llvm] r89403 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp In-Reply-To: <76369418-3903-4073-B620-620DDB968AFD@apple.com> References: <200911192310.nAJNASND022655@zion.cs.uiuc.edu> <76369418-3903-4073-B620-620DDB968AFD@apple.com> Message-ID: <5E7D3936-FEAC-49F9-B2D1-0806E23F960C@apple.com> On Nov 19, 2009, at 6:18 PM, Jim Grosbach wrote: > No, it can definitely be restricted to just debug mode. Honestly, upon reflection, I'm not sure it's adding much value at all. I was using it to help validate my assumptions while tracking this problem down, but it didn't really end up helping much. What do you think? In that case, please remove it. Thanks. Evan > > -Jim > > > On Nov 19, 2009, at 6:06 PM, Evan Cheng wrote: > >> Do we have to run verifySizes in release mode? That will slow things down. >> >> Evan >> >> On Nov 19, 2009, at 3:10 PM, Jim Grosbach wrote: >> >>> Author: grosbach >>> Date: Thu Nov 19 17:10:28 2009 >>> New Revision: 89403 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=89403&view=rev >>> Log: >>> When placing constant islands and adjusting for alignment padding, inline >>> assembly can confuse things utterly, as it's assumed that instructions in >>> inline assembly are 4 bytes wide. For Thumb mode, that's often not true, >>> so the calculations for when alignment padding will be present get thrown off, >>> ultimately leading to out of range constant pool entry references. Making >>> more conservative assumptions that padding may be necessary when inline asm >>> is present avoids this situation. >>> >>> >>> Modified: >>> llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=89403&r1=89402&r2=89403&view=diff >>> >>> ============================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Thu Nov 19 17:10:28 2009 >>> @@ -162,6 +162,9 @@ >>> /// the branch fix up pass. >>> bool HasFarJump; >>> >>> + /// HasInlineAsm - True if the function contains inline assembly. >>> + bool HasInlineAsm; >>> + >>> const TargetInstrInfo *TII; >>> const ARMSubtarget *STI; >>> ARMFunctionInfo *AFI; >>> @@ -218,10 +221,45 @@ >>> unsigned GetOffsetOf(MachineInstr *MI) const; >>> void dumpBBs(); >>> void verify(MachineFunction &MF); >>> + void verifySizes(MachineFunction &MF); >>> }; >>> char ARMConstantIslands::ID = 0; >>> } >>> >>> +// verifySizes - Recalculate BB sizes from scratch and validate that the result >>> +// matches the values we've been using. >>> +void ARMConstantIslands::verifySizes(MachineFunction &MF) { >>> + unsigned Offset = 0; >>> + for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); >>> + MBBI != E; ++MBBI) { >>> + MachineBasicBlock &MBB = *MBBI; >>> + unsigned MBBSize = 0; >>> + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); >>> + I != E; ++I) { >>> + // Add instruction size to MBBSize. >>> + MBBSize += TII->GetInstSizeInBytes(I); >>> + } >>> + // In thumb mode, if this block is a constpool island, we may need padding >>> + // so it's aligned on 4 byte boundary. >>> + if (isThumb && >>> + !MBB.empty() && >>> + MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY && >>> + ((Offset%4) != 0 || HasInlineAsm)) >>> + MBBSize += 2; >>> + Offset += MBBSize; >>> + >>> + DEBUG(errs() << "block #" << MBB.getNumber() << ": " >>> + << MBBSize << " bytes (expecting " << BBSizes[MBB.getNumber()] >>> + << (MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY ? >>> + " CONSTANTPOOL" : "") << ")\n"); >>> +#ifndef NDEBUG >>> + if (MBBSize != BBSizes[MBB.getNumber()]) >>> + MBB.dump(); >>> +#endif >>> + assert (MBBSize == BBSizes[MBB.getNumber()] && "block size mismatch!"); >>> + } >>> +} >>> + >>> /// verify - check BBOffsets, BBSizes, alignment of islands >>> void ARMConstantIslands::verify(MachineFunction &MF) { >>> assert(BBOffsets.size() == BBSizes.size()); >>> @@ -236,11 +274,17 @@ >>> if (!MBB->empty() && >>> MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) { >>> unsigned MBBId = MBB->getNumber(); >>> - assert((BBOffsets[MBBId]%4 == 0 && BBSizes[MBBId]%4 == 0) || >>> + assert(HasInlineAsm || >>> + (BBOffsets[MBBId]%4 == 0 && BBSizes[MBBId]%4 == 0) || >>> (BBOffsets[MBBId]%4 != 0 && BBSizes[MBBId]%4 != 0)); >>> } >>> } >>> #endif >>> + for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) { >>> + CPUser &U = CPUsers[i]; >>> + unsigned UserOffset = GetOffsetOf(U.MI) + (isThumb ? 4 : 8); >>> + assert (CPEIsInRange(U.MI, UserOffset, U.CPEMI, U.MaxDisp, U.NegOk, true)); >>> + } >>> } >>> >>> /// print block size and offset information - debugging >>> @@ -269,6 +313,7 @@ >>> isThumb2 = AFI->isThumb2Function(); >>> >>> HasFarJump = false; >>> + HasInlineAsm = false; >>> >>> // Renumber all of the machine basic blocks in the function, guaranteeing that >>> // the numbers agree with the position of the block in the function. >>> @@ -347,6 +392,7 @@ >>> >>> // After a while, this might be made debug-only, but it is not expensive. >>> verify(MF); >>> + verifySizes(MF); >>> >>> // If LR has been forced spilled and no far jumps (i.e. BL) has been issued. >>> // Undo the spill / restore of LR if possible. >>> @@ -452,6 +498,19 @@ >>> /// and finding all of the constant pool users. >>> void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF, >>> const std::vector &CPEMIs) { >>> + // First thing, see if the function has any inline assembly in it. If so, >>> + // we have to be conservative about alignment assumptions, as we don't >>> + // know for sure the size of any instructions in the inline assembly. >>> + for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); >>> + MBBI != E; ++MBBI) { >>> + MachineBasicBlock &MBB = *MBBI; >>> + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); >>> + I != E; ++I) >>> + if (I->getOpcode() == ARM::INLINEASM) >>> + HasInlineAsm = true; >>> + } >>> + >>> + // Now go back through the instructions and build up our data structures >>> unsigned Offset = 0; >>> for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); >>> MBBI != E; ++MBBI) { >>> @@ -481,7 +540,7 @@ >>> // A Thumb1 table jump may involve padding; for the offsets to >>> // be right, functions containing these must be 4-byte aligned. >>> AFI->setAlign(2U); >>> - if ((Offset+MBBSize)%4 != 0) >>> + if ((Offset+MBBSize)%4 != 0 || HasInlineAsm) >>> // FIXME: Add a pseudo ALIGN instruction instead. >>> MBBSize += 2; // padding >>> continue; // Does not get an entry in ImmBranches >>> @@ -609,7 +668,7 @@ >>> if (isThumb && >>> !MBB.empty() && >>> MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY && >>> - (Offset%4) != 0) >>> + ((Offset%4) != 0 || HasInlineAsm)) >>> MBBSize += 2; >>> >>> BBSizes.push_back(MBBSize); >>> @@ -633,7 +692,7 @@ >>> // alignment padding, and compensate if so. >>> if (isThumb && >>> MI->getOpcode() == ARM::CONSTPOOL_ENTRY && >>> - Offset%4 != 0) >>> + (Offset%4 != 0 || HasInlineAsm)) >>> Offset += 2; >>> >>> // Sum instructions before MI in MBB. >>> @@ -829,7 +888,7 @@ >>> MachineInstr *CPEMI, unsigned MaxDisp, >>> bool NegOk, bool DoDump) { >>> unsigned CPEOffset = GetOffsetOf(CPEMI); >>> - assert(CPEOffset%4 == 0 && "Misaligned CPE"); >>> + assert((CPEOffset%4 == 0 || HasInlineAsm) && "Misaligned CPE"); >>> >>> if (DoDump) { >>> DEBUG(errs() << "User of CPE#" << CPEMI->getOperand(0).getImm() >>> @@ -870,7 +929,7 @@ >>> if (!isThumb) >>> continue; >>> MachineBasicBlock *MBB = MBBI; >>> - if (!MBB->empty()) { >>> + if (!MBB->empty() && !HasInlineAsm) { >>> // Constant pool entries require padding. >>> if (MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) { >>> unsigned OldOffset = BBOffsets[i] - delta; >>> @@ -1226,7 +1285,7 @@ >>> >>> BBOffsets[NewIsland->getNumber()] = BBOffsets[NewMBB->getNumber()]; >>> // Compensate for .align 2 in thumb mode. >>> - if (isThumb && BBOffsets[NewIsland->getNumber()]%4 != 0) >>> + if (isThumb && (BBOffsets[NewIsland->getNumber()]%4 != 0 || HasInlineAsm)) >>> Size += 2; >>> // Increase the size of the island block to account for the new entry. >>> BBSizes[NewIsland->getNumber()] += Size; >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > From grosbach at apple.com Thu Nov 19 20:32:07 2009 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 20 Nov 2009 02:32:07 -0000 Subject: [llvm-commits] [llvm] r89443 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <200911200232.nAK2W7sY029941@zion.cs.uiuc.edu> Author: grosbach Date: Thu Nov 19 20:32:06 2009 New Revision: 89443 URL: http://llvm.org/viewvc/llvm-project?rev=89443&view=rev Log: Remove verifySizes() since it's not adding much value. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=89443&r1=89442&r2=89443&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Thu Nov 19 20:32:06 2009 @@ -221,45 +221,10 @@ unsigned GetOffsetOf(MachineInstr *MI) const; void dumpBBs(); void verify(MachineFunction &MF); - void verifySizes(MachineFunction &MF); }; char ARMConstantIslands::ID = 0; } -// verifySizes - Recalculate BB sizes from scratch and validate that the result -// matches the values we've been using. -void ARMConstantIslands::verifySizes(MachineFunction &MF) { - unsigned Offset = 0; - for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); - MBBI != E; ++MBBI) { - MachineBasicBlock &MBB = *MBBI; - unsigned MBBSize = 0; - for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); - I != E; ++I) { - // Add instruction size to MBBSize. - MBBSize += TII->GetInstSizeInBytes(I); - } - // In thumb mode, if this block is a constpool island, we may need padding - // so it's aligned on 4 byte boundary. - if (isThumb && - !MBB.empty() && - MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY && - ((Offset%4) != 0 || HasInlineAsm)) - MBBSize += 2; - Offset += MBBSize; - - DEBUG(errs() << "block #" << MBB.getNumber() << ": " - << MBBSize << " bytes (expecting " << BBSizes[MBB.getNumber()] - << (MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY ? - " CONSTANTPOOL" : "") << ")\n"); -#ifndef NDEBUG - if (MBBSize != BBSizes[MBB.getNumber()]) - MBB.dump(); -#endif - assert (MBBSize == BBSizes[MBB.getNumber()] && "block size mismatch!"); - } -} - /// verify - check BBOffsets, BBSizes, alignment of islands void ARMConstantIslands::verify(MachineFunction &MF) { assert(BBOffsets.size() == BBSizes.size()); @@ -392,7 +357,6 @@ // After a while, this might be made debug-only, but it is not expensive. verify(MF); - verifySizes(MF); // If LR has been forced spilled and no far jumps (i.e. BL) has been issued. // Undo the spill / restore of LR if possible. From gohman at apple.com Thu Nov 19 20:51:27 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 02:51:27 -0000 Subject: [llvm-commits] [llvm] r89444 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGISel.h lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp test/CodeGen/X86/tailcall-fastisel.ll Message-ID: <200911200251.nAK2pSP1030585@zion.cs.uiuc.edu> Author: djg Date: Thu Nov 19 20:51:26 2009 New Revision: 89444 URL: http://llvm.org/viewvc/llvm-project?rev=89444&view=rev Log: Fix fast-isel to avoid selecting the return instruction if a tail call has been encountered. Added: llvm/trunk/test/CodeGen/X86/tailcall-fastisel.ll Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=89444&r1=89443&r2=89444&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Thu Nov 19 20:51:26 2009 @@ -127,7 +127,8 @@ void SelectBasicBlock(BasicBlock *LLVMBB, BasicBlock::iterator Begin, - BasicBlock::iterator End); + BasicBlock::iterator End, + bool &HadTailCall); void CodeGenAndEmitDAG(); void LowerArguments(BasicBlock *BB); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=89444&r1=89443&r2=89444&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Nov 19 20:51:26 2009 @@ -376,7 +376,8 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, BasicBlock::iterator Begin, - BasicBlock::iterator End) { + BasicBlock::iterator End, + bool &HadTailCall) { SDL->setCurrentBasicBlock(BB); MetadataContext &TheMetadata = LLVMBB->getParent()->getContext().getMetadata(); unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); @@ -421,6 +422,7 @@ // Final step, emit the lowered DAG as machine code. CodeGenAndEmitDAG(); + HadTailCall = SDL->HasTailCall; SDL->clear(); } @@ -797,7 +799,16 @@ } SDL->setCurDebugLoc(FastIS->getCurDebugLoc()); - SelectBasicBlock(LLVMBB, BI, next(BI)); + + bool HadTailCall = false; + SelectBasicBlock(LLVMBB, BI, next(BI), HadTailCall); + + // If the call was emitted as a tail call, we're done with the block. + if (HadTailCall) { + BI = End; + break; + } + // If the instruction was codegen'd with multiple blocks, // inform the FastISel object where to resume inserting. FastIS->setCurrentBlock(BB); @@ -827,7 +838,8 @@ // If FastISel is run and it has known DebugLoc then use it. if (FastIS && !FastIS->getCurDebugLoc().isUnknown()) SDL->setCurDebugLoc(FastIS->getCurDebugLoc()); - SelectBasicBlock(LLVMBB, BI, End); + bool HadTailCall; + SelectBasicBlock(LLVMBB, BI, End, HadTailCall); } FinishBasicBlock(); Added: llvm/trunk/test/CodeGen/X86/tailcall-fastisel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tailcall-fastisel.ll?rev=89444&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/tailcall-fastisel.ll (added) +++ llvm/trunk/test/CodeGen/X86/tailcall-fastisel.ll Thu Nov 19 20:51:26 2009 @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=x86-64 -tailcallopt -fast-isel | grep TAILCALL + +; Fast-isel shouldn't attempt to handle this tail call, and it should +; cleanly terminate instruction selection in the block after it's +; done to avoid emitting invalid MachineInstrs. + +%0 = type { i64, i32, i8* } + +define fastcc i8* @"visit_array_aux<`Reference>"(%0 %arg, i32 %arg1) nounwind { +fail: ; preds = %entry + %tmp20 = tail call fastcc i8* @"visit_array_aux<`Reference>"(%0 %arg, i32 undef) ; [#uses=1] + ret i8* %tmp20 +} From daniel at zuster.org Thu Nov 19 20:52:08 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 20 Nov 2009 02:52:08 -0000 Subject: [llvm-commits] [llvm] r89445 - /llvm/trunk/test/FrontendC/cstring-align.c Message-ID: <200911200252.nAK2q99s030633@zion.cs.uiuc.edu> Author: ddunbar Date: Thu Nov 19 20:52:08 2009 New Revision: 89445 URL: http://llvm.org/viewvc/llvm-project?rev=89445&view=rev Log: Fix -march= name for x86-64. Modified: llvm/trunk/test/FrontendC/cstring-align.c Modified: llvm/trunk/test/FrontendC/cstring-align.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/cstring-align.c?rev=89445&r1=89444&r2=89445&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/cstring-align.c (original) +++ llvm/trunk/test/FrontendC/cstring-align.c Thu Nov 19 20:52:08 2009 @@ -1,5 +1,5 @@ // RUN: %llvmgcc %s -c -Os -m32 -emit-llvm -o - | llc -march=x86 -mtriple=i386-apple-darwin10 | FileCheck %s -check-prefix=DARWIN32 -// RUN: %llvmgcc %s -c -Os -m64 -emit-llvm -o - | llc -march=x86_64 -mtriple=x86_64-apple-darwin10 | FileCheck %s -check-prefix=DARWIN64 +// RUN: %llvmgcc %s -c -Os -m64 -emit-llvm -o - | llc -march=x86-64 -mtriple=x86_64-apple-darwin10 | FileCheck %s -check-prefix=DARWIN64 extern void func(const char *, const char *); From sabre at nondot.org Fri Nov 20 00:18:54 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 19 Nov 2009 22:18:54 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: References: <701493E3-E27B-4EAB-9666-99B2F6EA01BC@apple.com> Message-ID: On Nov 19, 2009, at 4:17 PM, Evan Cheng wrote: > > On Nov 19, 2009, at 9:35 AM, Chris Lattner wrote: > >> Apologies for the last email being rambling, and in advance for this one also being rambling. :) >> >> My basic perspective is that I want to sink as much logic into the target-independent code as possible and have the fewest number of target hooks reasonable. This is for three reasons: >> >> 1. Porting to a new target is easier with fewer target hooks, and they get better codegen 'out of the box' by specifying primitives instead of having to tweak tons of knobs. > > That's an idealistic way of looking at it. Yes of course. As I said, it is the guiding principle. Are you claiming that it is better to add target hooks that we don't *really need*? I'm not saying we should have no target hooks, just that we should try hard to avoid them :) > To me, the right way to implement this is actually having even more accurate machine model. Yes. I really don't like target hooks that "implement pieces of algorithms, like the tail dupe one does. I'm not opposed to exposing more information about the architecture. -Chris From sabre at nondot.org Fri Nov 20 00:19:30 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 19 Nov 2009 22:19:30 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: <16600E75-AC60-43A9-9E4C-BA0FC8F94440@apple.com> References: <701493E3-E27B-4EAB-9666-99B2F6EA01BC@apple.com> <16600E75-AC60-43A9-9E4C-BA0FC8F94440@apple.com> Message-ID: On Nov 19, 2009, at 3:53 PM, Bob Wilson wrote: > Hi Chris, > > An update so you don't think I'm ignoring you.... I want to try some experiments on x86 before changing anything. I'm currently blocked by . I'll take another look at it once that is resolved. No problem Bob, I'm in no hurry here :), please don't drop it though. -Chris From sabre at nondot.org Fri Nov 20 00:28:25 2009 From: sabre at nondot.org (Chris Lattner) Date: Thu, 19 Nov 2009 22:28:25 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: References: <701493E3-E27B-4EAB-9666-99B2F6EA01BC@apple.com> Message-ID: On Nov 19, 2009, at 10:11 AM, Bob Wilson wrote: > On Nov 19, 2009, at 9:35 AM, Chris Lattner wrote: >> Apologies for the last email being rambling, and in advance for this one also being rambling. :) >> >> My basic perspective is that I want to sink as much logic into the target-independent code as possible and have the fewest number of target hooks reasonable. This is for three reasons: >> >> 1. Porting to a new target is easier with fewer target hooks, and they get better codegen 'out of the box' by specifying primitives instead of having to tweak tons of knobs. > > I disagree. It is good to have knobs to tweak. As long as the defaults are set to values that work well for most targets, having more knobs does not make it harder to port to a new target. It does increase the overall complexity and documentation burden, though. On general principle, I disagree. "Knobs" add to maintenance burden, documentation, and learning the code base. If we can get the same effect with fewer knobs, we're better off. >> I much prefer very simple hooks that return an _aspect of the micro architecture_ rather than having hooks that _implement pieces of codegen passes_. The later is the approach that GCC took and is one of the major reasons it is difficult to change the algorithms in the GCC backend. > > Doesn't that go against your desire to have fewer target hooks? I tried to make the tail duplication hook very general, since it seems conceivable that we may want to adjust the cost metric based on other characteristics of the target. If we add very specific target hooks, we may end up with more of them. While I don't like things like isMoveInstr, I'm not opposed to them either. While they are technically target hooks (and if you don't implement them, you get atrocious code!) isMoveInstr is well defined and exposes an aspect of the architecture to the target independent parts of the code. I guess what I really don't like is target hooks that implement pieces of algorithms (of which I would like to have zero). Beyond that I have a general goal of reducing target hooks, but the goal is to keep them to a reasonable minimum, not eliminate them completely. If a new target hook adds value and describes the architecture, I'm not opposed to it. Particularly if it could be derived from the .td files some day (like isMoveInstr). >> 2. A single and well tuned implementation of something in target independent code is better than having a few well tuned impls in some targets and missing or just wrong impls in others. For example, this xform is definitely profitable on X86 chips as well, probably many others. > > Right. There is a single implementation of tail duplication here. It's just a question of tuning it for different targets. It is not possible (in general) to have it tuned ideally for all targets. For that matter, we haven't really tuned it for ARM yet. I've started looking at trying it for X86. Sure, but the hook you implemented for ARM is not well tuned yet, and will grow in complexity as/if it does. >> >>>> (And, at least for duplicating >>>> indirect branches on ARM Cortex processors, we don't want to limit >>>> that.) >> >> Why not?? > > Because it is such a dramatic performance win for ARM Cortex, and perhaps more importantly, I can't think of a way to limit it that might not also miss cases where we really want to get the performance. I don't expect indirect branches to be so common that the code size matters. I don't really buy this. Are you really claiming that duplicating a 10K instruction basic block is worth it? In reality there has to be a balance, even for ARM. This is also likely to be a huge win for X86 but this is just like jump threading: while eliminating correlated branches is *always* a win from the dynamic instruction count perspective, we balance the benefit with the code size cost. I don't see how this case is any different. >>>> On a small low-power device without sophisticated branch >>>> prediction, where code size typically matters more than usual, we'll >>>> be doing the wrong thing. But, indirect branches are not very common, >>>> so it probably doesn't really matter so much. >> >> They are fairly common in switch statements that codegen to jump tables, but not anyway near as common as normal branches. > > For ARM we currently use different instruction patterns for jump tables and indirect branches. So, the special case we're doing for tail duplication does not apply to jump tables. We might have to be more conservative if we can't distinguish those on other targets. In practice, must jump table indirect gotos are preceded by a conditional branch that checks the "range" of the table anyway, so it won't matter. However, if that weren't the case, this optimization would be just as useful for switches as indbr's. Ideally the same code *should* apply to both. >>>> Unless someone else has another idea, I'll get rid of the tail >>>> duplication target hook. As you mention, we'll need a way to identify >>>> indirect branches. I'd prefer to add a new IsIndirectBranch target >>>> hook. This goes against your desire to avoid new target hooks, but >>>> it's nice and simple. >> >> Using the extant isIndirectBranch flag would be best, but even adding this sort of target hook would be somewhat ok. At least this would be a property of the architecture. If we can avoid it, I'd definitely prefer to of course. > > The isIndirectBranch flag would not allow us to distinguish jump table branches. I don't think we want to :). Why do we want to? >> Dan wrote: >>> However I don't know what the big problem is >>> with the target hook; it's neither arbitrary nor unitless. Perhaps >>> what he really meant is that the present use for the hook is too >>> obscure to justify having the clutter of the hook in TargetInstrInfo, >>> but I'm just guessing here. >> >> What is the units that it returns? As a target author, how do I know to return +2 or +4 or +1234? > > It returns the maximum number of instructions in a basic block that will be tail duplicated. And why is +2 the "right" amount? Because it happens to be enough to get one particular testcase that you care about, or because of some fundamental property of the architecture? -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091119/46eee448/attachment.html From bob.wilson at apple.com Fri Nov 20 00:52:27 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 19 Nov 2009 22:52:27 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: References: <701493E3-E27B-4EAB-9666-99B2F6EA01BC@apple.com> Message-ID: <4F246C8B-FDED-4DDA-95F1-DE2D11F216CB@apple.com> On Nov 19, 2009, at 10:28 PM, Chris Lattner wrote: > > I don't really buy this. Are you really claiming that duplicating a > 10K instruction basic block is worth it? In reality there has to be > a balance, even for ARM. This is also likely to be a huge win for > X86 but this is just like jump threading: while eliminating > correlated branches is *always* a win from the dynamic instruction > count perspective, we balance the benefit with the code size cost. > I don't see how this case is any different. The size of the block is definitely limited -- the whole point of the target hook is to adjust that limit. The aspect that we don't limit is the number of predecessors where we may duplicate that block. More on this below.... > In practice, must jump table indirect gotos are preceded by a > conditional branch that checks the "range" of the table anyway, so > it won't matter. However, if that weren't the case, this > optimization would be just as useful for switches as indbr's. > Ideally the same code *should* apply to both. Not necessarily. Our implementation of indirect branches artificially combines all the indirect branches in a function into a single branch. That has a very bad effect on branch prediction. The main reason we need to do this aggressive tail duplication for indirect branches is to essentially undo that transformation. The same thing is not true of jump tables. More below... > >>>>> Unless someone else has another idea, I'll get rid of the tail >>>>> duplication target hook. As you mention, we'll need a way to >>>>> identify >>>>> indirect branches. I'd prefer to add a new IsIndirectBranch >>>>> target >>>>> hook. This goes against your desire to avoid new target hooks, >>>>> but >>>>> it's nice and simple. >>> >>> Using the extant isIndirectBranch flag would be best, but even >>> adding this sort of target hook would be somewhat ok. At least >>> this would be a property of the architecture. If we can avoid it, >>> I'd definitely prefer to of course. >> >> The isIndirectBranch flag would not allow us to distinguish jump >> table branches. > > I don't think we want to :). Why do we want to? Indirect branches (i.e., "computed gotos", not jump tables) are most often used for interpreters. Besides the "undo the front end's factoring of the CFG" motivation for treating indirect branches specially, there is more to it than that. It is quite common for an interpreter to see common patterns in the operations it handles. (This is especially true for certain benchmarks we care about.) The typical interpreter loop has a chunk of code to handle each operation, ending with an indirect branch to go to the next operation. When there are patterns in the order of interpreted operations, those indirect branches become predictable -- but only if they are duplicated into the separate chunks of code for each operation. Applying this intuition to the code size question above, if an interpreter loop handles 1000 different operations, we would still want to duplicate the indirect branches into every one of those 1000 chunks of code, as long as the code being duplicated is "small enough". (I am thinking here of processors that can predict those branches and where the branch misprediction penalty is significant. You would want to make a different tradeoff for a processor with no branch prediction.) > And why is +2 the "right" amount? Because it happens to be enough > to get one particular testcase that you care about, or because of > some fundamental property of the architecture? It is for the same reason that -tail-merge-size defaults to "3". ;-) The default limit for tail duplication is "tail-merge-size" - 1. That is also completely arbitrary. We pick values that work well for the code we have measured and that we care about. There's nothing fundamental about them. From isanbard at gmail.com Fri Nov 20 00:57:34 2009 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 19 Nov 2009 22:57:34 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r89415 - in /llvm-gcc-4.2/trunk/gcc: config/darwin.h llvm-backend.cpp In-Reply-To: References: <200911200031.nAK0VpKv025598@zion.cs.uiuc.edu> Message-ID: On Nov 19, 2009, at 5:09 PM, Dale Johannesen wrote: > > On Nov 19, 2009, at 4:31 PMPST, Bill Wendling wrote: > >> Author: void >> Date: Thu Nov 19 18:31:31 2009 >> New Revision: 89415 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=89415&view=rev >> Log: >> Adjust the alignment of strings so that they aren't over aligned. We only need >> them aligned to 8-bytes instead of 16-bytes for 64-bit. And 4 instead of 8 in >> 32-bit. > > Maybe so, but I bet there is a good reason it was the way it was. Did you do any performance measurements? > No. Evan noticed that GCC was doing it with lesser alignments and that that caused bigger files and stuff... -bw From nicholas at mxc.ca Fri Nov 20 01:15:48 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 19 Nov 2009 23:15:48 -0800 Subject: [llvm-commits] [llvm] r89398 - in /llvm/trunk: include/llvm/Analysis/CaptureTracking.h lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/CaptureTracking.cpp lib/Transforms/IPO/FunctionAttrs.cpp test/Transforms/GVN/nonescaping-malloc.ll In-Reply-To: <200911192157.nAJLvmkD020251@zion.cs.uiuc.edu> References: <200911192157.nAJLvmkD020251@zion.cs.uiuc.edu> Message-ID: <4B064224.3040404@mxc.ca> Dan Gohman wrote: > Author: djg > Date: Thu Nov 19 15:57:48 2009 > New Revision: 89398 > > URL: http://llvm.org/viewvc/llvm-project?rev=89398&view=rev > Log: > Extend CaptureTracking to indicate when a value is never stored, even > if it is not ultimately captured. Teach BasicAliasAnalysis that a > local object address which does not escape and is never stored does > not alias with a value resulting from a load. > > Added: > llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll > Modified: > llvm/trunk/include/llvm/Analysis/CaptureTracking.h > llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp > llvm/trunk/lib/Analysis/CaptureTracking.cpp > llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp > > Modified: llvm/trunk/include/llvm/Analysis/CaptureTracking.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CaptureTracking.h?rev=89398&r1=89397&r2=89398&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Analysis/CaptureTracking.h (original) > +++ llvm/trunk/include/llvm/Analysis/CaptureTracking.h Thu Nov 19 15:57:48 2009 > @@ -21,8 +21,12 @@ > /// by the enclosing function (which is required to exist). This routine can > /// be expensive, so consider caching the results. The boolean ReturnCaptures > /// specifies whether returning the value (or part of it) from the function > + /// counts as capturing it or not. The boolean StoreCaptures specified whether > + /// storing the value (or part of it) into memory anywhere automatically > /// counts as capturing it or not. > - bool PointerMayBeCaptured(const Value *V, bool ReturnCaptures); > + bool PointerMayBeCaptured(const Value *V, > + bool ReturnCaptures, > + bool StoreCaptures); I completely do not understand this. The fact that store implies capture has always been a missed opportunity; if it stores to something that never escapes, and the loads of it never escape, then it's not captured. (Note that you need to track 'pointer depth' as %p is stored into %q is stored into %r, etc.) Duncan (IIRC) actually implemented this behaviour early on and we removed it because it was likely to be slow and didn't seem to provide any performance benefit at the time. In any event, either I'm misunderstanding what you're doing here, or it doesn't belong in the API. Nick > } // end namespace llvm > > > Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=89398&r1=89397&r2=89398&view=diff > > ============================================================================== > --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) > +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Thu Nov 19 15:57:48 2009 > @@ -79,7 +79,12 @@ > static bool isNonEscapingLocalObject(const Value *V) { > // If this is a local allocation, check to see if it escapes. > if (isa(V) || isNoAliasCall(V)) > - return !PointerMayBeCaptured(V, false); > + // Set StoreCaptures to True so that we can assume in our callers that the > + // pointer is not the result of a load instruction. Currently > + // PointerMayBeCaptured doesn't have any special analysis for the > + // StoreCaptures=false case; if it did, our callers could be refined to be > + // more precise. > + return !PointerMayBeCaptured(V, false, /*StoreCaptures=*/true); > > // If this is an argument that corresponds to a byval or noalias argument, > // then it has not escaped before entering the function. Check if it escapes > @@ -89,7 +94,7 @@ > // Don't bother analyzing arguments already known not to escape. > if (A->hasNoCaptureAttr()) > return true; > - return !PointerMayBeCaptured(V, false); > + return !PointerMayBeCaptured(V, false, /*StoreCaptures=*/true); > } > return false; > } > @@ -683,15 +688,19 @@ > (V2Size != ~0U&& isObjectSmallerThan(O1, V2Size, *TD))) > return NoAlias; > > - // If one pointer is the result of a call/invoke and the other is a > + // If one pointer is the result of a call/invoke or load and the other is a > // non-escaping local object, then we know the object couldn't escape to a > - // point where the call could return it. > - if ((isa(O1) || isa(O1))&& > - isNonEscapingLocalObject(O2)&& O1 != O2) > - return NoAlias; > - if ((isa(O2) || isa(O2))&& > - isNonEscapingLocalObject(O1)&& O1 != O2) > - return NoAlias; > + // point where the call could return it. The load case works because > + // isNonEscapingLocalObject considers all stores to be escapes (it > + // passes true for the StoreCaptures argument to PointerMayBeCaptured). > + if (O1 != O2) { > + if ((isa(O1) || isa(O1) || isa(O1))&& > + isNonEscapingLocalObject(O2)) > + return NoAlias; > + if ((isa(O2) || isa(O2) || isa(O2))&& > + isNonEscapingLocalObject(O1)) > + return NoAlias; > + } > > if (!isa(V1)&& isa(V2)) { > std::swap(V1, V2); > > Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CaptureTracking.cpp?rev=89398&r1=89397&r2=89398&view=diff > > ============================================================================== > --- llvm/trunk/lib/Analysis/CaptureTracking.cpp (original) > +++ llvm/trunk/lib/Analysis/CaptureTracking.cpp Thu Nov 19 15:57:48 2009 > @@ -28,8 +28,11 @@ > /// by the enclosing function (which is required to exist). This routine can > /// be expensive, so consider caching the results. The boolean ReturnCaptures > /// specifies whether returning the value (or part of it) from the function > +/// counts as capturing it or not. The boolean StoreCaptures specified whether > +/// storing the value (or part of it) into memory anywhere automatically > /// counts as capturing it or not. > -bool llvm::PointerMayBeCaptured(const Value *V, bool ReturnCaptures) { > +bool llvm::PointerMayBeCaptured(const Value *V, > + bool ReturnCaptures, bool StoreCaptures) { > assert(isa(V->getType())&& "Capture is for pointers only!"); > SmallVector Worklist; > SmallSet Visited; > @@ -82,7 +85,11 @@ > break; > case Instruction::Store: > if (V == I->getOperand(0)) > - // Stored the pointer - it may be captured. > + // Stored the pointer - conservatively assume it may be captured. > + // TODO: If StoreCaptures is not true, we could do Fancy analysis > + // to determine whether this store is not actually an escape point. > + // In that case, BasicAliasAnalysis should be updated as well to > + // take advantage of this. > return true; > // Storing to the pointee does not cause the pointer to be captured. > break; > > Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=89398&r1=89397&r2=89398&view=diff > > ============================================================================== > --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) > +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Thu Nov 19 15:57:48 2009 > @@ -212,7 +212,7 @@ > > for (Function::arg_iterator A = F->arg_begin(), E = F->arg_end(); A!=E; ++A) > if (isa(A->getType())&& !A->hasNoCaptureAttr()&& > - !PointerMayBeCaptured(A, true)) { > + !PointerMayBeCaptured(A, true, /*StoreCaptures=*/false)) { > A->addAttr(Attribute::NoCapture); > ++NumNoCapture; > Changed = true; > @@ -280,7 +280,7 @@ > return false; // Did not come from an allocation. > } > > - if (PointerMayBeCaptured(RetVal, false)) > + if (PointerMayBeCaptured(RetVal, false, /*StoreCaptures=*/false)) > return false; > } > > > Added: llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll?rev=89398&view=auto > > ============================================================================== > --- llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll (added) > +++ llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll Thu Nov 19 15:57:48 2009 > @@ -0,0 +1,108 @@ > +; RUN: opt< %s -gvn -stats |& grep {Number of loads deleted} > +; rdar://7363102 > + > +; GVN should be able to eliminate load %tmp22.i, because it is redundant with > +; load %tmp8.i. This requires being able to prove that %tmp7.i doesn't > +; alias the malloc'd value %tmp.i20.i.i, which it can do since %tmp7.i > +; is derived from %tmp5.i which is computed from a load, and %tmp.i20.i.i > +; is never stored and does not escape. > + > +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" > +target triple = "x86_64-apple-darwin10.0" > + > +%"struct.llvm::MallocAllocator" = type<{ i8 }> > +%"struct.llvm::StringMap" = type { %"struct.llvm::StringMapImpl", %"struct.llvm::MallocAllocator" } > +%"struct.llvm::StringMapEntry" = type { %"struct.llvm::StringMapEntryBase", i8* } > +%"struct.llvm::StringMapEntryBase" = type { i32 } > +%"struct.llvm::StringMapImpl" = type { %"struct.llvm::StringMapImpl::ItemBucket"*, i32, i32, i32, i32 } > +%"struct.llvm::StringMapImpl::ItemBucket" = type { i32, %"struct.llvm::StringMapEntryBase"* } > +%"struct.llvm::StringRef" = type { i8*, i64 } > + > +define %"struct.llvm::StringMapEntry"* @_Z3fooRN4llvm9StringMapIPvNS_15MallocAllocatorEEEPKc(%"struct.llvm::StringMap"* %X, i8* %P) ssp { > +entry: > + %tmp = alloca %"struct.llvm::StringRef", align 8 ;<%"struct.llvm::StringRef"*> [#uses=3] > + %tmp.i = getelementptr inbounds %"struct.llvm::StringRef"* %tmp, i64 0, i32 0 ; [#uses=1] > + store i8* %P, i8** %tmp.i, align 8 > + %tmp1.i = call i64 @strlen(i8* %P) nounwind readonly ; [#uses=1] > + %tmp2.i = getelementptr inbounds %"struct.llvm::StringRef"* %tmp, i64 0, i32 1 ; [#uses=1] > + store i64 %tmp1.i, i64* %tmp2.i, align 8 > + %tmp1 = call %"struct.llvm::StringMapEntry"* @_ZN4llvm9StringMapIPvNS_15MallocAllocatorEE16GetOrCreateValueERKNS_9StringRefE(%"struct.llvm::StringMap"* %X, %"struct.llvm::StringRef"* %tmp) ssp ;<%"struct.llvm::StringMapEntry"*> [#uses=1] > + ret %"struct.llvm::StringMapEntry"* %tmp1 > +} > + > +declare i64 @strlen(i8* nocapture) nounwind readonly > + > +declare noalias i8* @malloc(i64) nounwind > + > +declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind > + > +declare i32 @_ZN4llvm13StringMapImpl15LookupBucketForENS_9StringRefE(%"struct.llvm::StringMapImpl"*, i64, i64) > + > +define linkonce_odr %"struct.llvm::StringMapEntry"* @_ZN4llvm9StringMapIPvNS_15MallocAllocatorEE16GetOrCreateValueERKNS_9StringRefE(%"struct.llvm::StringMap"* %this, %"struct.llvm::StringRef"* nocapture %Key) ssp align 2 { > +entry: > + %elt = bitcast %"struct.llvm::StringRef"* %Key to i64* ; [#uses=1] > + %val = load i64* %elt ; [#uses=3] > + %tmp = getelementptr inbounds %"struct.llvm::StringRef"* %Key, i64 0, i32 1 ; [#uses=1] > + %val2 = load i64* %tmp ; [#uses=2] > + %tmp2.i = getelementptr inbounds %"struct.llvm::StringMap"* %this, i64 0, i32 0 ;<%"struct.llvm::StringMapImpl"*> [#uses=1] > + %tmp3.i = tail call i32 @_ZN4llvm13StringMapImpl15LookupBucketForENS_9StringRefE(%"struct.llvm::StringMapImpl"* %tmp2.i, i64 %val, i64 %val2) ; [#uses=1] > + %tmp4.i = getelementptr inbounds %"struct.llvm::StringMap"* %this, i64 0, i32 0, i32 0 ;<%"struct.llvm::StringMapImpl::ItemBucket"**> [#uses=1] > + %tmp5.i = load %"struct.llvm::StringMapImpl::ItemBucket"** %tmp4.i, align 8 ;<%"struct.llvm::StringMapImpl::ItemBucket"*> [#uses=1] > + %tmp6.i = zext i32 %tmp3.i to i64 ; [#uses=1] > + %tmp7.i = getelementptr inbounds %"struct.llvm::StringMapImpl::ItemBucket"* %tmp5.i, i64 %tmp6.i, i32 1 ;<%"struct.llvm::StringMapEntryBase"**> [#uses=2] > + %tmp8.i = load %"struct.llvm::StringMapEntryBase"** %tmp7.i, align 8 ;<%"struct.llvm::StringMapEntryBase"*> [#uses=3] > + %tmp9.i = icmp eq %"struct.llvm::StringMapEntryBase"* %tmp8.i, null ; [#uses=1] > + %tmp13.i = icmp eq %"struct.llvm::StringMapEntryBase"* %tmp8.i, inttoptr (i64 -1 to %"struct.llvm::StringMapEntryBase"*) ; [#uses=1] > + %or.cond.i = or i1 %tmp9.i, %tmp13.i ; [#uses=1] > + br i1 %or.cond.i, label %bb4.i, label %bb6.i > + > +bb4.i: ; preds = %entry > + %tmp41.i = inttoptr i64 %val to i8* ; [#uses=2] > + %tmp4.i35.i = getelementptr inbounds i8* %tmp41.i, i64 %val2 ; [#uses=1] > + %tmp.i.i = ptrtoint i8* %tmp4.i35.i to i64 ; [#uses=1] > + %tmp1.i.i = trunc i64 %tmp.i.i to i32 ; [#uses=1] > + %tmp3.i.i = trunc i64 %val to i32 ; [#uses=1] > + %tmp4.i.i = sub i32 %tmp1.i.i, %tmp3.i.i ; [#uses=3] > + %tmp5.i.i = add i32 %tmp4.i.i, 17 ; [#uses=1] > + %tmp8.i.i = zext i32 %tmp5.i.i to i64 ; [#uses=1] > + %tmp.i20.i.i = tail call noalias i8* @malloc(i64 %tmp8.i.i) nounwind ; [#uses=7] > + %tmp10.i.i = bitcast i8* %tmp.i20.i.i to %"struct.llvm::StringMapEntry"* ;<%"struct.llvm::StringMapEntry"*> [#uses=2] > + %tmp12.i.i = icmp eq i8* %tmp.i20.i.i, null ; [#uses=1] > + br i1 %tmp12.i.i, label %_ZN4llvm14StringMapEntryIPvE6CreateINS_15MallocAllocatorES1_EEPS2_PKcS7_RT_T0_.exit.i, label %bb.i.i > + > +bb.i.i: ; preds = %bb4.i > + %tmp.i.i.i.i = bitcast i8* %tmp.i20.i.i to i32* ; [#uses=1] > + store i32 %tmp4.i.i, i32* %tmp.i.i.i.i, align 4 > + %tmp1.i19.i.i = getelementptr inbounds i8* %tmp.i20.i.i, i64 8 ; [#uses=1] > + %0 = bitcast i8* %tmp1.i19.i.i to i8** ; [#uses=1] > + store i8* null, i8** %0, align 8 > + br label %_ZN4llvm14StringMapEntryIPvE6CreateINS_15MallocAllocatorES1_EEPS2_PKcS7_RT_T0_.exit.i > + > +_ZN4llvm14StringMapEntryIPvE6CreateINS_15MallocAllocatorES1_EEPS2_PKcS7_RT_T0_.exit.i: ; preds = %bb4.i, %bb.i.i > + %tmp.i18.i.i = getelementptr inbounds i8* %tmp.i20.i.i, i64 16 ; [#uses=1] > + %tmp15.i.i = zext i32 %tmp4.i.i to i64 ; [#uses=2] > + tail call void @llvm.memcpy.i64(i8* %tmp.i18.i.i, i8* %tmp41.i, i64 %tmp15.i.i, i32 1) nounwind > + %tmp.i18.sum.i.i = add i64 %tmp15.i.i, 16 ; [#uses=1] > + %tmp17.i.i = getelementptr inbounds i8* %tmp.i20.i.i, i64 %tmp.i18.sum.i.i ; [#uses=1] > + store i8 0, i8* %tmp17.i.i, align 1 > + %tmp.i.i.i = getelementptr inbounds i8* %tmp.i20.i.i, i64 8 ; [#uses=1] > + %1 = bitcast i8* %tmp.i.i.i to i8** ; [#uses=1] > + store i8* null, i8** %1, align 8 > + %tmp22.i = load %"struct.llvm::StringMapEntryBase"** %tmp7.i, align 8 ;<%"struct.llvm::StringMapEntryBase"*> [#uses=1] > + %tmp24.i = icmp eq %"struct.llvm::StringMapEntryBase"* %tmp22.i, inttoptr (i64 -1 to %"struct.llvm::StringMapEntryBase"*) ; [#uses=1] > + br i1 %tmp24.i, label %bb9.i, label %_ZN4llvm9StringMapIPvNS_15MallocAllocatorEE16GetOrCreateValueIS1_EERNS_14StringMapEntryIS1_EENS_9StringRefET_.exit > + > +bb6.i: ; preds = %entry > + %tmp16.i = bitcast %"struct.llvm::StringMapEntryBase"* %tmp8.i to %"struct.llvm::StringMapEntry"* ;<%"struct.llvm::StringMapEntry"*> [#uses=1] > + ret %"struct.llvm::StringMapEntry"* %tmp16.i > + > +bb9.i: ; preds = %_ZN4llvm14StringMapEntryIPvE6CreateINS_15MallocAllocatorES1_EEPS2_PKcS7_RT_T0_.exit.i > + %tmp25.i = getelementptr inbounds %"struct.llvm::StringMap"* %this, i64 0, i32 0, i32 3 ; [#uses=2] > + %tmp26.i = load i32* %tmp25.i, align 8 ; [#uses=1] > + %tmp27.i = add i32 %tmp26.i, -1 ; [#uses=1] > + store i32 %tmp27.i, i32* %tmp25.i, align 8 > + ret %"struct.llvm::StringMapEntry"* %tmp10.i.i > + > +_ZN4llvm9StringMapIPvNS_15MallocAllocatorEE16GetOrCreateValueIS1_EERNS_14StringMapEntryIS1_EENS_9StringRefET_.exit: ; preds = %_ZN4llvm14StringMapEntryIPvE6CreateINS_15MallocAllocatorES1_EEPS2_PKcS7_RT_T0_.exit.i > + ret %"struct.llvm::StringMapEntry"* %tmp10.i.i > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From baldrick at free.fr Fri Nov 20 02:03:05 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 20 Nov 2009 09:03:05 +0100 Subject: [llvm-commits] [llvm] r89389 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp In-Reply-To: <200911192134.nAJLY8cS019293@zion.cs.uiuc.edu> References: <200911192134.nAJLY8cS019293@zion.cs.uiuc.edu> Message-ID: <4B064D39.9080301@free.fr> Hi Dan, > Comparing a pointer with null is not a capture. this is wrong, given our current definition of capture (which is extremely conservative, and not defined in terms of pointer aliasing rules): any method which allows you to end up with a new pointer that holds the contents of the original pointer is capture, even if this involves chopping the original pointer into bits and reassembling them somewhere else. I think the C language standard says that in this case, you are allowed to assume that the new pointer does not alias the original pointer, but it was decided (i.e. Chris decreed) to use the language independent definition "no bits escape". Proviso: when determining if some bits of a pointer may be captured, you are allowed to assume that no bits of it were already captured. So how does comparison with null allow you to capture a pointer P? Easy! n = 0 loop: Q = GEP P, -n if (Q == null) break; n = n + 1; goto loop; captured_value = GEP null, n Ciao, Duncan. From baldrick at free.fr Fri Nov 20 02:16:13 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 20 Nov 2009 09:16:13 +0100 Subject: [llvm-commits] [llvm] r89398 - in /llvm/trunk: include/llvm/Analysis/CaptureTracking.h lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/CaptureTracking.cpp lib/Transforms/IPO/FunctionAttrs.cpp test/Transforms/GVN/nonescaping-malloc.ll In-Reply-To: <4B064224.3040404@mxc.ca> References: <200911192157.nAJLvmkD020251@zion.cs.uiuc.edu> <4B064224.3040404@mxc.ca> Message-ID: <4B06504D.8090804@free.fr> Hi, > Duncan (IIRC) actually implemented this behaviour early on and we > removed it because it was likely to be slow and didn't seem to provide > any performance benefit at the time. yes, IIRC, when run over the entire testsuite it resulted in three additional functions being marked nocapture, and having these functions marked nocapture resulted in no optimization improvements. Since it was hard to do the analysis correctly, I removed it as being more trouble than it was worth. Ciao, Duncan. From benny.kra at googlemail.com Fri Nov 20 03:53:28 2009 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 20 Nov 2009 09:53:28 -0000 Subject: [llvm-commits] [llvm] r89452 - /llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll Message-ID: <200911200953.nAK9rSB7026688@zion.cs.uiuc.edu> Author: d0k Date: Fri Nov 20 03:53:25 2009 New Revision: 89452 URL: http://llvm.org/viewvc/llvm-project?rev=89452&view=rev Log: Try to work around grep's "Binary file (standard input) matches" complaints seen on ppc buildbot. Modified: llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll Modified: llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll?rev=89452&r1=89451&r2=89452&view=diff ============================================================================== --- llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll (original) +++ llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll Fri Nov 20 03:53:25 2009 @@ -1,4 +1,4 @@ -; RUN: opt < %s -gvn -stats |& grep {Number of loads deleted} +; RUN: opt < %s -gvn -stats -disable-output |& grep {Number of loads deleted} ; rdar://7363102 ; GVN should be able to eliminate load %tmp22.i, because it is redundant with From baldrick at free.fr Fri Nov 20 04:45:11 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 20 Nov 2009 10:45:11 -0000 Subject: [llvm-commits] [llvm] r89454 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeTypes.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h test/CodeGen/Generic/2009-11-20-NewNode.ll Message-ID: <200911201045.nAKAjBu9029031@zion.cs.uiuc.edu> Author: baldrick Date: Fri Nov 20 04:45:10 2009 New Revision: 89454 URL: http://llvm.org/viewvc/llvm-project?rev=89454&view=rev Log: Fix PR5558, which was caused by a wrong fix for PR3393 (see commit 63048), which was an expensive checks failure due to a bug in the checking. This patch in essence reverts the original fix for PR3393, and refixes it by a tweak to the way expensive checking is done. Added: llvm/trunk/test/CodeGen/Generic/2009-11-20-NewNode.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=89454&r1=89453&r2=89454&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Fri Nov 20 04:45:10 2009 @@ -64,8 +64,12 @@ // The final node obtained by mapping by ReplacedValues is not marked NewNode. // Note that ReplacedValues should be applied iteratively. - // Note that the ReplacedValues map may also map deleted nodes. By iterating - // over the DAG we only consider non-deleted nodes. + // Note that the ReplacedValues map may also map deleted nodes (by iterating + // over the DAG we never dereference deleted nodes). This means that it may + // also map nodes marked NewNode if the deallocated memory was reallocated as + // another node, and that new node was not seen by the LegalizeTypes machinery + // (for example because it was created but not used). In general, we cannot + // distinguish between new nodes and deleted nodes. SmallVector NewNodes; for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), E = DAG.allnodes_end(); I != E; ++I) { @@ -114,7 +118,11 @@ Mapped |= 128; if (I->getNodeId() != Processed) { - if (Mapped != 0) { + // Since we allow ReplacedValues to map deleted nodes, it may map nodes + // marked NewNode too, since a deleted node may have been reallocated as + // another node that has not been seen by the LegalizeTypes machinery. + if ((I->getNodeId() == NewNode && Mapped > 1) || + (I->getNodeId() != NewNode && Mapped != 0)) { errs() << "Unprocessed value in a map!"; Failed = true; } @@ -320,16 +328,12 @@ continue; // The node morphed - this is equivalent to legalizing by replacing every - // value of N with the corresponding value of M. So do that now. However - // there is no need to remember the replacement - morphing will make sure - // it is never used non-trivially. + // value of N with the corresponding value of M. So do that now. assert(N->getNumValues() == M->getNumValues() && "Node morphing changed the number of results!"); for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) - // Replacing the value takes care of remapping the new value. Do the - // replacement without recording it in ReplacedValues. This does not - // expunge From but that is fine - it is not really a new node. - ReplaceValueWithHelper(SDValue(N, i), SDValue(M, i)); + // Replacing the value takes care of remapping the new value. + ReplaceValueWith(SDValue(N, i), SDValue(M, i)); assert(N->getNodeId() == NewNode && "Unexpected node state!"); // The node continues to live on as part of the NewNode fungus that // grows on top of the useful nodes. Nothing more needs to be done @@ -666,14 +670,14 @@ } -/// ReplaceValueWithHelper - Internal helper for ReplaceValueWith. Updates the -/// DAG causing any uses of From to use To instead, but without expunging From -/// or recording the replacement in ReplacedValues. Do not call directly unless -/// you really know what you are doing! -void DAGTypeLegalizer::ReplaceValueWithHelper(SDValue From, SDValue To) { +/// ReplaceValueWith - The specified value was legalized to the specified other +/// value. Update the DAG and NodeIds replacing any uses of From to use To +/// instead. +void DAGTypeLegalizer::ReplaceValueWith(SDValue From, SDValue To) { assert(From.getNode() != To.getNode() && "Potential legalization loop!"); // If expansion produced new nodes, make sure they are properly marked. + ExpungeNode(From.getNode()); AnalyzeNewValue(To); // Expunges To. // Anything that used the old node should now use the new one. Note that this @@ -682,6 +686,10 @@ NodeUpdateListener NUL(*this, NodesToAnalyze); DAG.ReplaceAllUsesOfValueWith(From, To, &NUL); + // The old node may still be present in a map like ExpandedIntegers or + // PromotedIntegers. Inform maps about the replacement. + ReplacedValues[From] = To; + // Process the list of nodes that need to be reanalyzed. while (!NodesToAnalyze.empty()) { SDNode *N = NodesToAnalyze.back(); @@ -712,25 +720,6 @@ } } -/// ReplaceValueWith - The specified value was legalized to the specified other -/// value. Update the DAG and NodeIds replacing any uses of From to use To -/// instead. -void DAGTypeLegalizer::ReplaceValueWith(SDValue From, SDValue To) { - assert(From.getNode()->getNodeId() == ReadyToProcess && - "Only the node being processed may be remapped!"); - - // If expansion produced new nodes, make sure they are properly marked. - ExpungeNode(From.getNode()); - AnalyzeNewValue(To); // Expunges To. - - // The old node may still be present in a map like ExpandedIntegers or - // PromotedIntegers. Inform maps about the replacement. - ReplacedValues[From] = To; - - // Do the replacement. - ReplaceValueWithHelper(From, To); -} - void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) { assert(Result.getValueType() == TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) && "Invalid type for promoted integer"); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=89454&r1=89453&r2=89454&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Fri Nov 20 04:45:10 2009 @@ -196,7 +196,6 @@ DebugLoc dl); SDValue PromoteTargetBoolean(SDValue Bool, EVT VT); void ReplaceValueWith(SDValue From, SDValue To); - void ReplaceValueWithHelper(SDValue From, SDValue To); void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi); void SplitInteger(SDValue Op, EVT LoVT, EVT HiVT, SDValue &Lo, SDValue &Hi); Added: llvm/trunk/test/CodeGen/Generic/2009-11-20-NewNode.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2009-11-20-NewNode.ll?rev=89454&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2009-11-20-NewNode.ll (added) +++ llvm/trunk/test/CodeGen/Generic/2009-11-20-NewNode.ll Fri Nov 20 04:45:10 2009 @@ -0,0 +1,37 @@ +; RUN: llc -march=msp430 %s +; RUN: llc -march=pic16 %s +; PR5558 + +define i64 @_strtoll_r(i16 %base) nounwind { +entry: + br i1 undef, label %if.then, label %if.end27 + +if.then: ; preds = %do.end + br label %if.end27 + +if.end27: ; preds = %if.then, %do.end + %cond66 = select i1 undef, i64 -9223372036854775808, i64 9223372036854775807 ; [#uses=3] + %conv69 = sext i16 %base to i64 ; [#uses=1] + %div = udiv i64 %cond66, %conv69 ; [#uses=1] + br label %for.cond + +for.cond: ; preds = %if.end116, %if.end27 + br i1 undef, label %if.then152, label %if.then93 + +if.then93: ; preds = %for.cond + br i1 undef, label %if.end116, label %if.then152 + +if.end116: ; preds = %if.then93 + %cmp123 = icmp ugt i64 undef, %div ; [#uses=1] + %or.cond = or i1 undef, %cmp123 ; [#uses=0] + br label %for.cond + +if.then152: ; preds = %if.then93, %for.cond + br i1 undef, label %if.end182, label %if.then172 + +if.then172: ; preds = %if.then152 + ret i64 %cond66 + +if.end182: ; preds = %if.then152 + ret i64 %cond66 +} From baldrick at free.fr Fri Nov 20 05:19:56 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 20 Nov 2009 12:19:56 +0100 Subject: [llvm-commits] [llvm] r89434 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp In-Reply-To: <200911200134.nAK1Y38v027923@zion.cs.uiuc.edu> References: <200911200134.nAK1Y38v027923@zion.cs.uiuc.edu> Message-ID: <4B067B5C.4000308@free.fr> Hi Dan, > + // Don't count comparisons of two pointers within the same object > + // as captures. > + if (I->getOperand(0)->getUnderlyingObject() == > + I->getOperand(1)->getUnderlyingObject()) I think this bit is ok if you only do equality/inequality comparisons, but is wrong if you allow inequality comparisons. The reason is that this Q = GEP P, -n if (Q == null) break; (see example from previous email) is equivalent to this Q = GEP P, -(n+1) if (Q > P) break; and here you are comparing pointers with the same underlying object. Ciao, Duncan. From baldrick at free.fr Fri Nov 20 05:53:11 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 20 Nov 2009 12:53:11 +0100 Subject: [llvm-commits] [llvm] r89421 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp In-Reply-To: <200911200050.nAK0or7J026222@zion.cs.uiuc.edu> References: <200911200050.nAK0or7J026222@zion.cs.uiuc.edu> Message-ID: <4B068327.1070103@free.fr> Hi Dan, > + // Don't count comparisons of the original value against null as captures. > + // This allows us to ignore comparisons of malloc results with null, > + // for example. > + if (isIdentifiedObject(V)) > + if (ConstantPointerNull *CPN = > + dyn_cast(I->getOperand(1))) > + if (CPN->getType()->getAddressSpace() == 0) > + break; I think this is wrong, consider the following pseudocode example: i1 equals_null (i8* %P noalias) { return %P == 0 } Thanks to your change, this function will be marked nocapture, because a noalias parameter counts as an identified object. Now consider i8* @capture (i8* %P noalias) { n = 0 loop: %Q = GEP %P, -n if (equals_null(%Q)) break; n = n + 1; goto loop; return GEP null, n } I think it is correct to pass %Q to equals_null given that %P is noalias. So this example shows that %P can be captured even though CaptureTracking says it is not with your change. A variant of this is to have %P be some noalias value like the return value of malloc. Ciao, Duncan. From baldrick at free.fr Fri Nov 20 07:19:51 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 20 Nov 2009 13:19:51 -0000 Subject: [llvm-commits] [llvm] r89456 - /llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200911201319.nAKDJpOH001832@zion.cs.uiuc.edu> Author: baldrick Date: Fri Nov 20 07:19:51 2009 New Revision: 89456 URL: http://llvm.org/viewvc/llvm-project?rev=89456&view=rev Log: Fix PR5563, an expensive checks failure when running on tests/Transforms/InstCombine/shufflemask-undef.ll. If anyone cares, the use of 2*e here (and the equivalent all over the place in instcombine) seems wrong, though harmless: it should really be twice the length of the input vector. I think shufflevector used to require that the mask have the same length as the input, but I don't think that's true any more. I don't care enough about vectors to do anything about this... Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=89456&r1=89455&r2=89456&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Fri Nov 20 07:19:51 2009 @@ -12920,7 +12920,7 @@ if (LHSMask.size() == Mask.size()) { std::vector NewMask; for (unsigned i = 0, e = Mask.size(); i != e; ++i) - if (Mask[i] >= 2*e) + if (Mask[i] >= e) NewMask.push_back(2*e); else NewMask.push_back(LHSMask[Mask[i]]); From dag at cray.com Fri Nov 20 08:50:14 2009 From: dag at cray.com (David Greene) Date: Fri, 20 Nov 2009 08:50:14 -0600 Subject: [llvm-commits] [llvm] r89356 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp In-Reply-To: References: <200911191555.nAJFtnEm007165@zion.cs.uiuc.edu> <200911191510.53618.dag@cray.com> Message-ID: <200911200850.15570.dag@cray.com> On Thursday 19 November 2009 15:51, Evan Cheng wrote: > deque is slow. Why not just a fixed sized array and rotate the head and > tail pointers? Ok, good idea. -Dave From espindola at google.com Fri Nov 20 09:22:21 2009 From: espindola at google.com (Rafael Espindola) Date: Fri, 20 Nov 2009 10:22:21 -0500 Subject: [llvm-commits] [PATCH] LTO code generator options In-Reply-To: References: <04F6B1512E264B27AEE607542FCDD113@andreic6e7fe55> <38a0d8450911141921r7deec8b3k91e06950263f0485@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BF@mail.accesssoftek.com> <38a0d8450911170809j6a32716ar840b8622cfad6f17@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607C4@mail.accesssoftek.com> <38a0d8450911180722j5a463fa8hec81178154deaf09@mail.gmail.com> <41BA1AA405BC4D19BA9B4FAB6543D62F@andreic6e7fe55> <38a0d8450911190723g644ad4c7ife769ab35da9efb9@mail.gmail.com> Message-ID: <38a0d8450911200722i5efa690ci6ab671d71b5f40dc@mail.gmail.com> > StringRef::split would do. > The issue here is: SubtargetFeatures class uses std::strings and has a > helper method Split which is used in few other places. > I'm trying to follow this. I don't like the idea to use StringRef::split > only in this particular place. > However, I wouldn't mind to re-factor the SubtargetFeatures class to use > StringRef instead of std::strings and prepare another patch. Shell I do so? You don't need to. If Split is used elsewhere I agree it is better to use it in here too. >> You say features are normalized, why does hasFeature needs to convert >> to lowercase and strip flags? > > Features are normalized inside the SubtargetFeatures class. hasFeature gets > a string which also should be normalized to compare with the already > normalized features. > We need to strip the flag because we do not care was this feature set on or > off, we simply want to know if it was set or not. > But if you have the question, I'll better add a comment there to clarify > this. How about something like this: "Normalize the given string to compare > with the normalized features, and strip the flag since we are checking was > this feature set at all without checking was it set on or off."? I think I am still missing something. First on the flag, what is the expected result of doing AddFeature("foo", true); AddFeature("foo", false). The patch implements a "first one wins". Is that correct? Assuming that is the desired behavior I understand the calls to StripFlag, but the call to LowercaseString still looks redundant: *) hasFeature is called only from AddFeature *) the string passed to it was generated with PrependFlag(LowercaseString(String), IsEnabled) A comment explaining this should do. >> The comment about "after all explicit feature settings" is a future >> reference, right? I don't see any feature being set :-) > > You are right. This is a future reference. Next patch will add explicit > settings of cpu and attributes. We just need to get there. :) > >> The method SubtargetFeatures::AddFeatures(const cl::list >> &List) is not being used, is it? > > I didn't find a way to add the usage in this patch without adding a lot of > other changes to get it work. This will be in the next patch and the usage > will look like this in the LTOCodeGenerator.cpp file: > > ... > +static cl::list MAttrs("mattr", > + ?cl::CommaSeparated, > + ?cl::desc("Target specific attributes (see -mattr=help for details)"), > + ?cl::value_desc("a1,+a2,-a3,...")); > + > ... > > bool LTOCodeGenerator::determineTarget(std::string& errMsg) > ... > + ? ? ? ?// Prepare subtarget feature set for the given command line > options. > + ? ? ? ?SubtargetFeatures features; > ... > + ? ? ? ?if (!MAttrs.empty()) > + ? ? ? ? ? ?features.AddFeatures(MAttrs); > + > + ? ? ? ?// Set the rest of features by default. > + ? ? ? ?// Note: Please keep this after all explict feature settings to > make sure > + ? ? ? ?// defaults will not override explicitly set options. > + > ?features.AddFeatures(SubtargetFeatures::getDefaultSubTargetTripleFeatures(_targetTriple)); > ... > > Which also fill that "keep this after all explict feature settings" comment > with meaning. > > Is it Ok to ssubmit this patch? OK with the comment explaining the addFeature, hasFeature behavior. > Cheers, > Viktor Cheers, -- Rafael ?vila de Esp?ndola From jyasskin at google.com Fri Nov 20 10:32:52 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Fri, 20 Nov 2009 08:32:52 -0800 Subject: [llvm-commits] [llvm] r86914 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h include/llvm/Metadata.h lib/Analysis/DebugInfo.cpp lib/VMCore/Metadata.cpp In-Reply-To: <200911120050.nAC0owVT014507@zion.cs.uiuc.edu> References: <200911120050.nAC0owVT014507@zion.cs.uiuc.edu> Message-ID: Hi Devang. This is inconvenient when I want to pass a string in from a std::string, PyString, or from Function::getName(). I don't think it's worth it just to let users pass 0 instead of "". On Wed, Nov 11, 2009 at 4:50 PM, Devang Patel wrote: > Author: dpatel > Date: Wed Nov 11 18:50:58 2009 > New Revision: 86914 > > URL: http://llvm.org/viewvc/llvm-project?rev=86914&view=rev > Log: > Do not use StringRef in DebugInfo interface. > This allows StringRef to skip controversial if(str) check in constructor. > Buildbots, wait for corresponding clang and llvm-gcc FE check-ins! > > Modified: > ? ?llvm/trunk/include/llvm/Analysis/DebugInfo.h > ? ?llvm/trunk/include/llvm/Metadata.h > ? ?llvm/trunk/lib/Analysis/DebugInfo.cpp > ? ?llvm/trunk/lib/VMCore/Metadata.cpp > > Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=86914&r1=86913&r2=86914&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) > +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Wed Nov 11 18:50:58 2009 > @@ -496,26 +496,26 @@ > ? ? /// CreateCompileUnit - Create a new descriptor for the specified compile > ? ? /// unit. > ? ? DICompileUnit CreateCompileUnit(unsigned LangID, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Filenae, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Directory, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Producer, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Filename, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Directory, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Producer, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool isMain = false, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool isOptimized = false, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char *Flags = "", > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned RunTimeVer = 0); > > ? ? /// CreateEnumerator - Create a single enumerator value. > - ? ?DIEnumerator CreateEnumerator(StringRef Name, uint64_t Val); > + ? ?DIEnumerator CreateEnumerator(const char * Name, uint64_t Val); > > ? ? /// CreateBasicType - Create a basic type like int, float, etc. > - ? ?DIBasicType CreateBasicType(DIDescriptor Context, StringRef Name, > + ? ?DIBasicType CreateBasicType(DIDescriptor Context, const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, unsigned LineNumber, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint64_t SizeInBits, uint64_t AlignInBits, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint64_t OffsetInBits, unsigned Flags, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned Encoding); > > ? ? /// CreateBasicType - Create a basic type like int, float, etc. > - ? ?DIBasicType CreateBasicTypeEx(DIDescriptor Context, StringRef Name, > + ? ?DIBasicType CreateBasicTypeEx(DIDescriptor Context, const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, unsigned LineNumber, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Constant *SizeInBits, Constant *AlignInBits, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Constant *OffsetInBits, unsigned Flags, > @@ -524,7 +524,7 @@ > ? ? /// CreateDerivedType - Create a derived type like const qualified type, > ? ? /// pointer, typedef, etc. > ? ? DIDerivedType CreateDerivedType(unsigned Tag, DIDescriptor Context, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint64_t SizeInBits, uint64_t AlignInBits, > @@ -534,7 +534,7 @@ > ? ? /// CreateDerivedType - Create a derived type like const qualified type, > ? ? /// pointer, typedef, etc. > ? ? DIDerivedType CreateDerivedTypeEx(unsigned Tag, DIDescriptor Context, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Constant *SizeInBits, Constant *AlignInBits, > @@ -543,7 +543,7 @@ > > ? ? /// CreateCompositeType - Create a composite type like array, struct, etc. > ? ? DICompositeType CreateCompositeType(unsigned Tag, DIDescriptor Context, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint64_t SizeInBits, > @@ -555,7 +555,7 @@ > > ? ? /// CreateCompositeType - Create a composite type like array, struct, etc. > ? ? DICompositeType CreateCompositeTypeEx(unsigned Tag, DIDescriptor Context, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Constant *SizeInBits, > @@ -567,25 +567,25 @@ > > ? ? /// CreateSubprogram - Create a new descriptor for the specified subprogram. > ? ? /// See comments in DISubprogram for descriptions of these fields. > - ? ?DISubprogram CreateSubprogram(DIDescriptor Context, StringRef Name, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef DisplayName, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef LinkageName, > + ? ?DISubprogram CreateSubprogram(DIDescriptor Context, const char * Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * DisplayName, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * LinkageName, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, unsigned LineNo, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DIType Type, bool isLocalToUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool isDefinition); > > ? ? /// CreateGlobalVariable - Create a new descriptor for the specified global. > ? ? DIGlobalVariable > - ? ?CreateGlobalVariable(DIDescriptor Context, StringRef Name, > - ? ? ? ? ? ? ? ? ? ? ? ? StringRef DisplayName, > - ? ? ? ? ? ? ? ? ? ? ? ? StringRef LinkageName, > + ? ?CreateGlobalVariable(DIDescriptor Context, const char * Name, > + ? ? ? ? ? ? ? ? ? ? ? ? const char * DisplayName, > + ? ? ? ? ? ? ? ? ? ? ? ? const char * LinkageName, > ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNo, DIType Type, bool isLocalToUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ?bool isDefinition, llvm::GlobalVariable *GV); > > ? ? /// CreateVariable - Create a new descriptor for the specified variable. > ? ? DIVariable CreateVariable(unsigned Tag, DIDescriptor Context, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, unsigned LineNo, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DIType Type); > > > Modified: llvm/trunk/include/llvm/Metadata.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Metadata.h?rev=86914&r1=86913&r2=86914&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Metadata.h (original) > +++ llvm/trunk/include/llvm/Metadata.h Wed Nov 11 18:50:58 2009 > @@ -60,6 +60,7 @@ > > ?public: > ? static MDString *get(LLVMContext &Context, StringRef Str); > + ?static MDString *get(LLVMContext &Context, const char *Str); > > ? StringRef getString() const { return Str; } > > > Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=86914&r1=86913&r2=86914&view=diff > > ============================================================================== > --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) > +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Wed Nov 11 18:50:58 2009 > @@ -653,9 +653,9 @@ > ?/// CreateCompileUnit - Create a new descriptor for the specified compile > ?/// unit. ?Note that this does not unique compile units within the module. > ?DICompileUnit DIFactory::CreateCompileUnit(unsigned LangID, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Filename, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Directory, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Producer, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Filename, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Directory, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Producer, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool isMain, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool isOptimized, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char *Flags, > @@ -677,7 +677,7 @@ > ?} > > ?/// CreateEnumerator - Create a single enumerator value. > -DIEnumerator DIFactory::CreateEnumerator(StringRef Name, uint64_t Val){ > +DIEnumerator DIFactory::CreateEnumerator(const char * Name, uint64_t Val){ > ? Value *Elts[] = { > ? ? GetTagConstant(dwarf::DW_TAG_enumerator), > ? ? MDString::get(VMContext, Name), > @@ -689,7 +689,7 @@ > > ?/// CreateBasicType - Create a basic type like int, float, etc. > ?DIBasicType DIFactory::CreateBasicType(DIDescriptor Context, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t SizeInBits, > @@ -714,7 +714,7 @@ > > ?/// CreateBasicType - Create a basic type like int, float, etc. > ?DIBasicType DIFactory::CreateBasicTypeEx(DIDescriptor Context, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Constant *SizeInBits, > @@ -741,7 +741,7 @@ > ?/// pointer, typedef, etc. > ?DIDerivedType DIFactory::CreateDerivedType(unsigned Tag, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DIDescriptor Context, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t SizeInBits, > @@ -769,7 +769,7 @@ > ?/// pointer, typedef, etc. > ?DIDerivedType DIFactory::CreateDerivedTypeEx(unsigned Tag, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DIDescriptor Context, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Constant *SizeInBits, > @@ -796,7 +796,7 @@ > ?/// CreateCompositeType - Create a composite type like array, struct, etc. > ?DICompositeType DIFactory::CreateCompositeType(unsigned Tag, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DIDescriptor Context, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t SizeInBits, > @@ -828,7 +828,7 @@ > ?/// CreateCompositeType - Create a composite type like array, struct, etc. > ?DICompositeType DIFactory::CreateCompositeTypeEx(unsigned Tag, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DIDescriptor Context, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Constant *SizeInBits, > @@ -861,9 +861,9 @@ > ?/// See comments in DISubprogram for descriptions of these fields. ?This > ?/// method does not unique the generated descriptors. > ?DISubprogram DIFactory::CreateSubprogram(DIDescriptor Context, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef DisplayName, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef LinkageName, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * DisplayName, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * LinkageName, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNo, DIType Type, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool isLocalToUnit, > @@ -887,9 +887,9 @@ > > ?/// CreateGlobalVariable - Create a new descriptor for the specified global. > ?DIGlobalVariable > -DIFactory::CreateGlobalVariable(DIDescriptor Context, StringRef Name, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef DisplayName, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef LinkageName, > +DIFactory::CreateGlobalVariable(DIDescriptor Context, const char * Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * DisplayName, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * LinkageName, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNo, DIType Type,bool isLocalToUnit, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool isDefinition, llvm::GlobalVariable *Val) { > @@ -921,7 +921,7 @@ > > ?/// CreateVariable - Create a new descriptor for the specified variable. > ?DIVariable DIFactory::CreateVariable(unsigned Tag, DIDescriptor Context, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, unsigned LineNo, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DIType Type) { > ? Value *Elts[] = { > > Modified: llvm/trunk/lib/VMCore/Metadata.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=86914&r1=86913&r2=86914&view=diff > > ============================================================================== > --- llvm/trunk/lib/VMCore/Metadata.cpp (original) > +++ llvm/trunk/lib/VMCore/Metadata.cpp Wed Nov 11 18:50:58 2009 > @@ -39,6 +39,17 @@ > ? ? new MDString(Context, Entry.getKey()); > ?} > > +MDString *MDString::get(LLVMContext &Context, const char *Str) { > + ?LLVMContextImpl *pImpl = Context.pImpl; > + ?StringMapEntry &Entry = > + ? ?pImpl->MDStringCache.GetOrCreateValue(Str ? StringRef(Str) : StringRef()); > + ?MDString *&S = Entry.getValue(); > + ?if (S) return S; > + > + ?return S = > + ? ?new MDString(Context, Entry.getKey()); > +} > + > ?//===----------------------------------------------------------------------===// > ?// MDNode implementation. > ?// > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From jyasskin at google.com Fri Nov 20 10:53:13 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Fri, 20 Nov 2009 08:53:13 -0800 Subject: [llvm-commits] [llvm] r89156 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/Analysis/DebugInfo.cpp In-Reply-To: <200911172239.nAHMd8Ef013044@zion.cs.uiuc.edu> References: <200911172239.nAHMd8Ef013044@zion.cs.uiuc.edu> Message-ID: They weren't quite dead: I was calling them. :) Could you update http://llvm.org/docs/SourceLevelDebugging.html to describe the new state of the world and how to upgrade? On Tue, Nov 17, 2009 at 2:39 PM, Devang Patel wrote: > Author: dpatel > Date: Tue Nov 17 16:39:08 2009 > New Revision: 89156 > > URL: http://llvm.org/viewvc/llvm-project?rev=89156&view=rev > Log: > Remove dead code. > > Modified: > ? ?llvm/trunk/include/llvm/Analysis/DebugInfo.h > ? ?llvm/trunk/lib/Analysis/DebugInfo.cpp > > Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=89156&r1=89155&r2=89156&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) > +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Tue Nov 17 16:39:08 2009 > @@ -468,15 +468,8 @@ > ? ? Module &M; > ? ? LLVMContext& VMContext; > > - ? ?// Cached values for uniquing and faster lookups. > ? ? const Type *EmptyStructPtr; // "{}*". > - ? ?Function *StopPointFn; ? // llvm.dbg.stoppoint > - ? ?Function *FuncStartFn; ? // llvm.dbg.func.start > - ? ?Function *RegionStartFn; // llvm.dbg.region.start > - ? ?Function *RegionEndFn; ? // llvm.dbg.region.end > ? ? Function *DeclareFn; ? ? // llvm.dbg.declare > - ? ?StringMap StringCache; > - ? ?DenseMap SimpleConstantCache; > > ? ? DIFactory(const DIFactory &); ? ? // DO NOT IMPLEMENT > ? ? void operator=(const DIFactory&); // DO NOT IMPLEMENT > @@ -605,23 +598,6 @@ > ? ? DILocation CreateLocation(unsigned LineNo, unsigned ColumnNo, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DIScope S, DILocation OrigLoc); > > - ? ?/// InsertStopPoint - Create a new llvm.dbg.stoppoint intrinsic invocation, > - ? ?/// inserting it at the end of the specified basic block. > - ? ?void InsertStopPoint(DICompileUnit CU, unsigned LineNo, unsigned ColNo, > - ? ? ? ? ? ? ? ? ? ? ? ? BasicBlock *BB); > - > - ? ?/// InsertSubprogramStart - Create a new llvm.dbg.func.start intrinsic to > - ? ?/// mark the start of the specified subprogram. > - ? ?void InsertSubprogramStart(DISubprogram SP, BasicBlock *BB); > - > - ? ?/// InsertRegionStart - Insert a new llvm.dbg.region.start intrinsic call to > - ? ?/// mark the start of a region for the specified scoping descriptor. > - ? ?void InsertRegionStart(DIDescriptor D, BasicBlock *BB); > - > - ? ?/// InsertRegionEnd - Insert a new llvm.dbg.region.end intrinsic call to > - ? ?/// mark the end of a region for the specified scoping descriptor. > - ? ?void InsertRegionEnd(DIDescriptor D, BasicBlock *BB); > - > ? ? /// InsertDeclare - Insert a new llvm.dbg.declare intrinsic call. > ? ? Instruction *InsertDeclare(llvm::Value *Storage, DIVariable D, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?BasicBlock *InsertAtEnd); > > Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=89156&r1=89155&r2=89156&view=diff > > ============================================================================== > --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) > +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Tue Nov 17 16:39:08 2009 > @@ -606,9 +606,7 @@ > ?//===----------------------------------------------------------------------===// > > ?DIFactory::DIFactory(Module &m) > - ?: M(m), VMContext(M.getContext()), StopPointFn(0), FuncStartFn(0), > - ? ?RegionStartFn(0), RegionEndFn(0), > - ? ?DeclareFn(0) { > + ?: M(m), VMContext(M.getContext()), DeclareFn(0) { > ? EmptyStructPtr = PointerType::getUnqual(StructType::get(VMContext)); > ?} > > @@ -983,58 +981,6 @@ > ?// DIFactory: Routines for inserting code into a function > ?//===----------------------------------------------------------------------===// > > -/// InsertStopPoint - Create a new llvm.dbg.stoppoint intrinsic invocation, > -/// inserting it at the end of the specified basic block. > -void DIFactory::InsertStopPoint(DICompileUnit CU, unsigned LineNo, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned ColNo, BasicBlock *BB) { > - > - ?// Lazily construct llvm.dbg.stoppoint function. > - ?if (!StopPointFn) > - ? ?StopPointFn = llvm::Intrinsic::getDeclaration(&M, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?llvm::Intrinsic::dbg_stoppoint); > - > - ?// Invoke llvm.dbg.stoppoint > - ?Value *Args[] = { > - ? ?ConstantInt::get(llvm::Type::getInt32Ty(VMContext), LineNo), > - ? ?ConstantInt::get(llvm::Type::getInt32Ty(VMContext), ColNo), > - ? ?CU.getNode() > - ?}; > - ?CallInst::Create(StopPointFn, Args, Args+3, "", BB); > -} > - > -/// InsertSubprogramStart - Create a new llvm.dbg.func.start intrinsic to > -/// mark the start of the specified subprogram. > -void DIFactory::InsertSubprogramStart(DISubprogram SP, BasicBlock *BB) { > - ?// Lazily construct llvm.dbg.func.start. > - ?if (!FuncStartFn) > - ? ?FuncStartFn = Intrinsic::getDeclaration(&M, Intrinsic::dbg_func_start); > - > - ?// Call llvm.dbg.func.start which also implicitly sets a stoppoint. > - ?CallInst::Create(FuncStartFn, SP.getNode(), "", BB); > -} > - > -/// InsertRegionStart - Insert a new llvm.dbg.region.start intrinsic call to > -/// mark the start of a region for the specified scoping descriptor. > -void DIFactory::InsertRegionStart(DIDescriptor D, BasicBlock *BB) { > - ?// Lazily construct llvm.dbg.region.start function. > - ?if (!RegionStartFn) > - ? ?RegionStartFn = Intrinsic::getDeclaration(&M, Intrinsic::dbg_region_start); > - > - ?// Call llvm.dbg.func.start. > - ?CallInst::Create(RegionStartFn, D.getNode(), "", BB); > -} > - > -/// InsertRegionEnd - Insert a new llvm.dbg.region.end intrinsic call to > -/// mark the end of a region for the specified scoping descriptor. > -void DIFactory::InsertRegionEnd(DIDescriptor D, BasicBlock *BB) { > - ?// Lazily construct llvm.dbg.region.end function. > - ?if (!RegionEndFn) > - ? ?RegionEndFn = Intrinsic::getDeclaration(&M, Intrinsic::dbg_region_end); > - > - ?// Call llvm.dbg.region.end. > - ?CallInst::Create(RegionEndFn, D.getNode(), "", BB); > -} > - > ?/// InsertDeclare - Insert a new llvm.dbg.declare intrinsic call. > ?Instruction *DIFactory::InsertDeclare(Value *Storage, DIVariable D, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Instruction *InsertBefore) { > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From dpatel at apple.com Fri Nov 20 11:20:42 2009 From: dpatel at apple.com (Devang Patel) Date: Fri, 20 Nov 2009 09:20:42 -0800 Subject: [llvm-commits] [llvm] r86914 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h include/llvm/Metadata.h lib/Analysis/DebugInfo.cpp lib/VMCore/Metadata.cpp In-Reply-To: References: <200911120050.nAC0owVT014507@zion.cs.uiuc.edu> Message-ID: <9DC587FF-9855-4F2E-BC34-5A40A9233CEA@apple.com> Hi! On Nov 20, 2009, at 8:32 AM, Jeffrey Yasskin wrote: > Hi Devang. This is inconvenient when I want to pass a string in from a > std::string, PyString, or from Function::getName(). I don't think it's > worth it just to let users pass 0 instead of "". The debugger and other tools consuming DWARF info are not expecting to see "". If StringRef are used then 1) The DwarfWriter needs to check for "" 2) The clients needs to check for optional arguments. If const char * are used then only clients needs to get pointer to the string. My preferred approach was to let StringRef handle null for optional arguments, but it has performance implications. I am not tied to one position, but prefer a approach that makes either DwarfWriter OR clients responsible to do the right thing. - Devang > > On Wed, Nov 11, 2009 at 4:50 PM, Devang Patel > wrote: >> Author: dpatel >> Date: Wed Nov 11 18:50:58 2009 >> New Revision: 86914 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=86914&view=rev >> Log: >> Do not use StringRef in DebugInfo interface. >> This allows StringRef to skip controversial if(str) check in >> constructor. >> Buildbots, wait for corresponding clang and llvm-gcc FE check-ins! >> >> Modified: >> llvm/trunk/include/llvm/Analysis/DebugInfo.h >> llvm/trunk/include/llvm/Metadata.h >> llvm/trunk/lib/Analysis/DebugInfo.cpp >> llvm/trunk/lib/VMCore/Metadata.cpp >> >> Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=86914&r1=86913&r2=86914&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) >> +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Wed Nov 11 >> 18:50:58 2009 >> @@ -496,26 +496,26 @@ >> /// CreateCompileUnit - Create a new descriptor for the >> specified compile >> /// unit. >> DICompileUnit CreateCompileUnit(unsigned LangID, >> - StringRef Filenae, >> - StringRef Directory, >> - StringRef Producer, >> + const char * Filename, >> + const char * Directory, >> + const char * Producer, >> bool isMain = false, >> bool isOptimized = false, >> const char *Flags = "", >> unsigned RunTimeVer = 0); >> >> /// CreateEnumerator - Create a single enumerator value. >> - DIEnumerator CreateEnumerator(StringRef Name, uint64_t Val); >> + DIEnumerator CreateEnumerator(const char * Name, uint64_t Val); >> >> /// CreateBasicType - Create a basic type like int, float, etc. >> - DIBasicType CreateBasicType(DIDescriptor Context, StringRef >> Name, >> + DIBasicType CreateBasicType(DIDescriptor Context, const char * >> Name, >> DICompileUnit CompileUnit, unsigned >> LineNumber, >> uint64_t SizeInBits, uint64_t >> AlignInBits, >> uint64_t OffsetInBits, unsigned >> Flags, >> unsigned Encoding); >> >> /// CreateBasicType - Create a basic type like int, float, etc. >> - DIBasicType CreateBasicTypeEx(DIDescriptor Context, StringRef >> Name, >> + DIBasicType CreateBasicTypeEx(DIDescriptor Context, const char >> * Name, >> DICompileUnit CompileUnit, unsigned >> LineNumber, >> Constant *SizeInBits, Constant >> *AlignInBits, >> Constant *OffsetInBits, unsigned >> Flags, >> @@ -524,7 +524,7 @@ >> /// CreateDerivedType - Create a derived type like const >> qualified type, >> /// pointer, typedef, etc. >> DIDerivedType CreateDerivedType(unsigned Tag, DIDescriptor >> Context, >> - StringRef Name, >> + const char * Name, >> DICompileUnit CompileUnit, >> unsigned LineNumber, >> uint64_t SizeInBits, uint64_t >> AlignInBits, >> @@ -534,7 +534,7 @@ >> /// CreateDerivedType - Create a derived type like const >> qualified type, >> /// pointer, typedef, etc. >> DIDerivedType CreateDerivedTypeEx(unsigned Tag, DIDescriptor >> Context, >> - StringRef Name, >> + const char * Name, >> DICompileUnit CompileUnit, >> unsigned LineNumber, >> Constant *SizeInBits, Constant >> *AlignInBits, >> @@ -543,7 +543,7 @@ >> >> /// CreateCompositeType - Create a composite type like array, >> struct, etc. >> DICompositeType CreateCompositeType(unsigned Tag, DIDescriptor >> Context, >> - StringRef Name, >> + const char * Name, >> DICompileUnit CompileUnit, >> unsigned LineNumber, >> uint64_t SizeInBits, >> @@ -555,7 +555,7 @@ >> >> /// CreateCompositeType - Create a composite type like array, >> struct, etc. >> DICompositeType CreateCompositeTypeEx(unsigned Tag, >> DIDescriptor Context, >> - StringRef Name, >> + const char * Name, >> DICompileUnit CompileUnit, >> unsigned LineNumber, >> Constant *SizeInBits, >> @@ -567,25 +567,25 @@ >> >> /// CreateSubprogram - Create a new descriptor for the >> specified subprogram. >> /// See comments in DISubprogram for descriptions of these >> fields. >> - DISubprogram CreateSubprogram(DIDescriptor Context, StringRef >> Name, >> - StringRef DisplayName, >> - StringRef LinkageName, >> + DISubprogram CreateSubprogram(DIDescriptor Context, const char >> * Name, >> + const char * DisplayName, >> + const char * LinkageName, >> DICompileUnit CompileUnit, >> unsigned LineNo, >> DIType Type, bool isLocalToUnit, >> bool isDefinition); >> >> /// CreateGlobalVariable - Create a new descriptor for the >> specified global. >> DIGlobalVariable >> - CreateGlobalVariable(DIDescriptor Context, StringRef Name, >> - StringRef DisplayName, >> - StringRef LinkageName, >> + CreateGlobalVariable(DIDescriptor Context, const char * Name, >> + const char * DisplayName, >> + const char * LinkageName, >> DICompileUnit CompileUnit, >> unsigned LineNo, DIType Type, bool >> isLocalToUnit, >> bool isDefinition, llvm::GlobalVariable >> *GV); >> >> /// CreateVariable - Create a new descriptor for the specified >> variable. >> DIVariable CreateVariable(unsigned Tag, DIDescriptor Context, >> - StringRef Name, >> + const char * Name, >> DICompileUnit CompileUnit, unsigned >> LineNo, >> DIType Type); >> >> >> Modified: llvm/trunk/include/llvm/Metadata.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Metadata.h?rev=86914&r1=86913&r2=86914&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/include/llvm/Metadata.h (original) >> +++ llvm/trunk/include/llvm/Metadata.h Wed Nov 11 18:50:58 2009 >> @@ -60,6 +60,7 @@ >> >> public: >> static MDString *get(LLVMContext &Context, StringRef Str); >> + static MDString *get(LLVMContext &Context, const char *Str); >> >> StringRef getString() const { return Str; } >> >> >> Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=86914&r1=86913&r2=86914&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) >> +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Wed Nov 11 18:50:58 2009 >> @@ -653,9 +653,9 @@ >> /// CreateCompileUnit - Create a new descriptor for the specified >> compile >> /// unit. Note that this does not unique compile units within the >> module. >> DICompileUnit DIFactory::CreateCompileUnit(unsigned LangID, >> - StringRef Filename, >> - StringRef Directory, >> - StringRef Producer, >> + const char * Filename, >> + const char * Directory, >> + const char * Producer, >> bool isMain, >> bool isOptimized, >> const char *Flags, >> @@ -677,7 +677,7 @@ >> } >> >> /// CreateEnumerator - Create a single enumerator value. >> -DIEnumerator DIFactory::CreateEnumerator(StringRef Name, uint64_t >> Val){ >> +DIEnumerator DIFactory::CreateEnumerator(const char * Name, >> uint64_t Val){ >> Value *Elts[] = { >> GetTagConstant(dwarf::DW_TAG_enumerator), >> MDString::get(VMContext, Name), >> @@ -689,7 +689,7 @@ >> >> /// CreateBasicType - Create a basic type like int, float, etc. >> DIBasicType DIFactory::CreateBasicType(DIDescriptor Context, >> - StringRef Name, >> + const char * Name, >> DICompileUnit CompileUnit, >> unsigned LineNumber, >> uint64_t SizeInBits, >> @@ -714,7 +714,7 @@ >> >> /// CreateBasicType - Create a basic type like int, float, etc. >> DIBasicType DIFactory::CreateBasicTypeEx(DIDescriptor Context, >> - StringRef Name, >> + const char * Name, >> DICompileUnit CompileUnit, >> unsigned LineNumber, >> Constant *SizeInBits, >> @@ -741,7 +741,7 @@ >> /// pointer, typedef, etc. >> DIDerivedType DIFactory::CreateDerivedType(unsigned Tag, >> DIDescriptor Context, >> - StringRef Name, >> + const char * Name, >> DICompileUnit CompileUnit, >> unsigned LineNumber, >> uint64_t SizeInBits, >> @@ -769,7 +769,7 @@ >> /// pointer, typedef, etc. >> DIDerivedType DIFactory::CreateDerivedTypeEx(unsigned Tag, >> DIDescriptor Context, >> - StringRef Name, >> + const char * Name, >> DICompileUnit >> CompileUnit, >> unsigned LineNumber, >> Constant *SizeInBits, >> @@ -796,7 +796,7 @@ >> /// CreateCompositeType - Create a composite type like array, >> struct, etc. >> DICompositeType DIFactory::CreateCompositeType(unsigned Tag, >> DIDescriptor Context, >> - StringRef Name, >> + const char * Name, >> DICompileUnit >> CompileUnit, >> unsigned LineNumber, >> uint64_t SizeInBits, >> @@ -828,7 +828,7 @@ >> /// CreateCompositeType - Create a composite type like array, >> struct, etc. >> DICompositeType DIFactory::CreateCompositeTypeEx(unsigned Tag, >> DIDescriptor >> Context, >> - StringRef Name, >> + const char * Name, >> DICompileUnit >> CompileUnit, >> unsigned LineNumber, >> Constant >> *SizeInBits, >> @@ -861,9 +861,9 @@ >> /// See comments in DISubprogram for descriptions of these >> fields. This >> /// method does not unique the generated descriptors. >> DISubprogram DIFactory::CreateSubprogram(DIDescriptor Context, >> - StringRef Name, >> - StringRef DisplayName, >> - StringRef LinkageName, >> + const char * Name, >> + const char * DisplayName, >> + const char * LinkageName, >> DICompileUnit CompileUnit, >> unsigned LineNo, DIType >> Type, >> bool isLocalToUnit, >> @@ -887,9 +887,9 @@ >> >> /// CreateGlobalVariable - Create a new descriptor for the >> specified global. >> DIGlobalVariable >> -DIFactory::CreateGlobalVariable(DIDescriptor Context, StringRef >> Name, >> - StringRef DisplayName, >> - StringRef LinkageName, >> +DIFactory::CreateGlobalVariable(DIDescriptor Context, const char * >> Name, >> + const char * DisplayName, >> + const char * LinkageName, >> DICompileUnit CompileUnit, >> unsigned LineNo, DIType Type,bool >> isLocalToUnit, >> bool isDefinition, >> llvm::GlobalVariable *Val) { >> @@ -921,7 +921,7 @@ >> >> /// CreateVariable - Create a new descriptor for the specified >> variable. >> DIVariable DIFactory::CreateVariable(unsigned Tag, DIDescriptor >> Context, >> - StringRef Name, >> + const char * Name, >> DICompileUnit CompileUnit, >> unsigned LineNo, >> DIType Type) { >> Value *Elts[] = { >> >> Modified: llvm/trunk/lib/VMCore/Metadata.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=86914&r1=86913&r2=86914&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/VMCore/Metadata.cpp (original) >> +++ llvm/trunk/lib/VMCore/Metadata.cpp Wed Nov 11 18:50:58 2009 >> @@ -39,6 +39,17 @@ >> new MDString(Context, Entry.getKey()); >> } >> >> +MDString *MDString::get(LLVMContext &Context, const char *Str) { >> + LLVMContextImpl *pImpl = Context.pImpl; >> + StringMapEntry &Entry = >> + pImpl->MDStringCache.GetOrCreateValue(Str ? StringRef(Str) : >> StringRef()); >> + MDString *&S = Entry.getValue(); >> + if (S) return S; >> + >> + return S = >> + new MDString(Context, Entry.getKey()); >> +} >> + >> // >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> // MDNode implementation. >> // >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> From dpatel at apple.com Fri Nov 20 11:22:27 2009 From: dpatel at apple.com (Devang Patel) Date: Fri, 20 Nov 2009 09:22:27 -0800 Subject: [llvm-commits] [llvm] r89156 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/Analysis/DebugInfo.cpp In-Reply-To: References: <200911172239.nAHMd8Ef013044@zion.cs.uiuc.edu> Message-ID: <5D8EF250-53C1-4D42-80AA-CF08B1D75D51@apple.com> On Nov 20, 2009, at 8:53 AM, Jeffrey Yasskin wrote: > They weren't quite dead: I was calling them. :) oops. I didn't realize. Feel free to bring this back for short term while you update your client. > Could you update > http://llvm.org/docs/SourceLevelDebugging.html to describe the new > state of the world and how to upgrade? I was waiting for Victor to finish up llvm.dbg.var work before updating document, because this is still a work in progress. But since someone is reading docs for mainline, I'll do a quick pass sooner :) - Devang > > On Tue, Nov 17, 2009 at 2:39 PM, Devang Patel > wrote: >> Author: dpatel >> Date: Tue Nov 17 16:39:08 2009 >> New Revision: 89156 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=89156&view=rev >> Log: >> Remove dead code. >> >> Modified: >> llvm/trunk/include/llvm/Analysis/DebugInfo.h >> llvm/trunk/lib/Analysis/DebugInfo.cpp >> >> Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=89156&r1=89155&r2=89156&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) >> +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Tue Nov 17 >> 16:39:08 2009 >> @@ -468,15 +468,8 @@ >> Module &M; >> LLVMContext& VMContext; >> >> - // Cached values for uniquing and faster lookups. >> const Type *EmptyStructPtr; // "{}*". >> - Function *StopPointFn; // llvm.dbg.stoppoint >> - Function *FuncStartFn; // llvm.dbg.func.start >> - Function *RegionStartFn; // llvm.dbg.region.start >> - Function *RegionEndFn; // llvm.dbg.region.end >> Function *DeclareFn; // llvm.dbg.declare >> - StringMap StringCache; >> - DenseMap SimpleConstantCache; >> >> DIFactory(const DIFactory &); // DO NOT IMPLEMENT >> void operator=(const DIFactory&); // DO NOT IMPLEMENT >> @@ -605,23 +598,6 @@ >> DILocation CreateLocation(unsigned LineNo, unsigned ColumnNo, >> DIScope S, DILocation OrigLoc); >> >> - /// InsertStopPoint - Create a new llvm.dbg.stoppoint >> intrinsic invocation, >> - /// inserting it at the end of the specified basic block. >> - void InsertStopPoint(DICompileUnit CU, unsigned LineNo, >> unsigned ColNo, >> - BasicBlock *BB); >> - >> - /// InsertSubprogramStart - Create a new llvm.dbg.func.start >> intrinsic to >> - /// mark the start of the specified subprogram. >> - void InsertSubprogramStart(DISubprogram SP, BasicBlock *BB); >> - >> - /// InsertRegionStart - Insert a new llvm.dbg.region.start >> intrinsic call to >> - /// mark the start of a region for the specified scoping >> descriptor. >> - void InsertRegionStart(DIDescriptor D, BasicBlock *BB); >> - >> - /// InsertRegionEnd - Insert a new llvm.dbg.region.end >> intrinsic call to >> - /// mark the end of a region for the specified scoping >> descriptor. >> - void InsertRegionEnd(DIDescriptor D, BasicBlock *BB); >> - >> /// InsertDeclare - Insert a new llvm.dbg.declare intrinsic call. >> Instruction *InsertDeclare(llvm::Value *Storage, DIVariable D, >> BasicBlock *InsertAtEnd); >> >> Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=89156&r1=89155&r2=89156&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) >> +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Tue Nov 17 16:39:08 2009 >> @@ -606,9 +606,7 @@ >> // >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> >> DIFactory::DIFactory(Module &m) >> - : M(m), VMContext(M.getContext()), StopPointFn(0), FuncStartFn(0), >> - RegionStartFn(0), RegionEndFn(0), >> - DeclareFn(0) { >> + : M(m), VMContext(M.getContext()), DeclareFn(0) { >> EmptyStructPtr = >> PointerType::getUnqual(StructType::get(VMContext)); >> } >> >> @@ -983,58 +981,6 @@ >> // DIFactory: Routines for inserting code into a function >> // >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> >> -/// InsertStopPoint - Create a new llvm.dbg.stoppoint intrinsic >> invocation, >> -/// inserting it at the end of the specified basic block. >> -void DIFactory::InsertStopPoint(DICompileUnit CU, unsigned LineNo, >> - unsigned ColNo, BasicBlock *BB) { >> - >> - // Lazily construct llvm.dbg.stoppoint function. >> - if (!StopPointFn) >> - StopPointFn = llvm::Intrinsic::getDeclaration(&M, >> - >> llvm::Intrinsic::dbg_stoppoint); >> - >> - // Invoke llvm.dbg.stoppoint >> - Value *Args[] = { >> - ConstantInt::get(llvm::Type::getInt32Ty(VMContext), LineNo), >> - ConstantInt::get(llvm::Type::getInt32Ty(VMContext), ColNo), >> - CU.getNode() >> - }; >> - CallInst::Create(StopPointFn, Args, Args+3, "", BB); >> -} >> - >> -/// InsertSubprogramStart - Create a new llvm.dbg.func.start >> intrinsic to >> -/// mark the start of the specified subprogram. >> -void DIFactory::InsertSubprogramStart(DISubprogram SP, BasicBlock >> *BB) { >> - // Lazily construct llvm.dbg.func.start. >> - if (!FuncStartFn) >> - FuncStartFn = Intrinsic::getDeclaration(&M, >> Intrinsic::dbg_func_start); >> - >> - // Call llvm.dbg.func.start which also implicitly sets a >> stoppoint. >> - CallInst::Create(FuncStartFn, SP.getNode(), "", BB); >> -} >> - >> -/// InsertRegionStart - Insert a new llvm.dbg.region.start >> intrinsic call to >> -/// mark the start of a region for the specified scoping descriptor. >> -void DIFactory::InsertRegionStart(DIDescriptor D, BasicBlock *BB) { >> - // Lazily construct llvm.dbg.region.start function. >> - if (!RegionStartFn) >> - RegionStartFn = Intrinsic::getDeclaration(&M, >> Intrinsic::dbg_region_start); >> - >> - // Call llvm.dbg.func.start. >> - CallInst::Create(RegionStartFn, D.getNode(), "", BB); >> -} >> - >> -/// InsertRegionEnd - Insert a new llvm.dbg.region.end intrinsic >> call to >> -/// mark the end of a region for the specified scoping descriptor. >> -void DIFactory::InsertRegionEnd(DIDescriptor D, BasicBlock *BB) { >> - // Lazily construct llvm.dbg.region.end function. >> - if (!RegionEndFn) >> - RegionEndFn = Intrinsic::getDeclaration(&M, >> Intrinsic::dbg_region_end); >> - >> - // Call llvm.dbg.region.end. >> - CallInst::Create(RegionEndFn, D.getNode(), "", BB); >> -} >> - >> /// InsertDeclare - Insert a new llvm.dbg.declare intrinsic call. >> Instruction *DIFactory::InsertDeclare(Value *Storage, DIVariable D, >> Instruction *InsertBefore) { >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> From foldr at codedgers.com Fri Nov 20 11:23:18 2009 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Fri, 20 Nov 2009 17:23:18 -0000 Subject: [llvm-commits] [llvm] r89463 - /llvm/trunk/lib/Support/CommandLine.cpp Message-ID: <200911201723.nAKHNIKv011164@zion.cs.uiuc.edu> Author: foldr Date: Fri Nov 20 11:23:17 2009 New Revision: 89463 URL: http://llvm.org/viewvc/llvm-project?rev=89463&view=rev Log: Move the handling of CommaSeparated options into ProvideOption. Makes '--comma-separated val1,val2' mean the same thing as '--comma-separated=val1,val2' (that is, 'val1' and 'val2' are not lumped together as 'val1,val2'). Also declutters the main loop a bit. Modified: llvm/trunk/lib/Support/CommandLine.cpp Modified: llvm/trunk/lib/Support/CommandLine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=89463&r1=89462&r2=89463&view=diff ============================================================================== --- llvm/trunk/lib/Support/CommandLine.cpp (original) +++ llvm/trunk/lib/Support/CommandLine.cpp Fri Nov 20 11:23:17 2009 @@ -177,7 +177,37 @@ return I->second; } +/// CommaSeparateAndAddOccurence - A wrapper around Handler->addOccurence() that +/// does special handling of cl::CommaSeparated options. +static bool CommaSeparateAndAddOccurence(Option *Handler, unsigned pos, + StringRef ArgName, + StringRef Value, bool MultiArg = false) +{ + // Check to see if this option accepts a comma separated list of values. If + // it does, we have to split up the value into multiple values. + if (Handler->getMiscFlags() & CommaSeparated) { + StringRef Val(Value); + StringRef::size_type Pos = Val.find(','); + + while (Pos != StringRef::npos) { + // Process the portion before the comma. + if (Handler->addOccurrence(pos, ArgName, Val.substr(0, Pos), MultiArg)) + return true; + // Erase the portion before the comma, AND the comma. + Val = Val.substr(Pos+1); + Value.substr(Pos+1); // Increment the original value pointer as well. + // Check for another comma. + Pos = Val.find(','); + } + + Value = Val; + } + if (Handler->addOccurrence(pos, ArgName, Value, MultiArg)) + return true; + + return false; +} /// ProvideOption - For Value, this differentiates between an empty value ("") /// and a null value (StringRef()). The later is accepted for arguments that @@ -219,13 +249,13 @@ // If this isn't a multi-arg option, just run the handler. if (NumAdditionalVals == 0) - return Handler->addOccurrence(i, ArgName, Value); + return CommaSeparateAndAddOccurence(Handler, i, ArgName, Value); // If it is, run the handle several times. bool MultiArg = false; if (Value.data()) { - if (Handler->addOccurrence(i, ArgName, Value, MultiArg)) + if (CommaSeparateAndAddOccurence(Handler, i, ArgName, Value, MultiArg)) return true; --NumAdditionalVals; MultiArg = true; @@ -236,7 +266,7 @@ return Handler->error("not enough values!"); Value = argv[++i]; - if (Handler->addOccurrence(i, ArgName, Value, MultiArg)) + if (CommaSeparateAndAddOccurence(Handler, i, ArgName, Value, MultiArg)) return true; MultiArg = true; --NumAdditionalVals; @@ -627,26 +657,6 @@ continue; } - // Check to see if this option accepts a comma separated list of values. If - // it does, we have to split up the value into multiple values. - if (Handler->getMiscFlags() & CommaSeparated) { - StringRef Val(Value); - StringRef::size_type Pos = Val.find(','); - - while (Pos != StringRef::npos) { - // Process the portion before the comma. - ErrorParsing |= ProvideOption(Handler, ArgName, Val.substr(0, Pos), - argc, argv, i); - // Erase the portion before the comma, AND the comma. - Val = Val.substr(Pos+1); - Value.substr(Pos+1); // Increment the original value pointer as well. - - // Check for another comma. - Pos = Val.find(','); - } - Value = Val; - } - // If this is a named positional argument, just remember that it is the // active one... if (Handler->getFormattingFlag() == cl::Positional) From jyasskin at google.com Fri Nov 20 11:45:22 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Fri, 20 Nov 2009 09:45:22 -0800 Subject: [llvm-commits] [llvm] r89156 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/Analysis/DebugInfo.cpp In-Reply-To: <5D8EF250-53C1-4D42-80AA-CF08B1D75D51@apple.com> References: <200911172239.nAHMd8Ef013044@zion.cs.uiuc.edu> <5D8EF250-53C1-4D42-80AA-CF08B1D75D51@apple.com> Message-ID: On Fri, Nov 20, 2009 at 9:22 AM, Devang Patel wrote: > > On Nov 20, 2009, at 8:53 AM, Jeffrey Yasskin wrote: > >> They weren't quite dead: I was calling them. :) > > oops. I didn't realize. Feel free to bring this back for short term while > you update your client. Well, I assume the intrinsics they insert no longer actually do what they used to do, and so I should replace them with something. I just want to know what to replace them with. I figured out that InsertStopPoint turned into IRBuilder::SetCurrentDebugLocation( DIFactory::CreateLocation(line_number, col_number, DISubprogram, DILocation(NULL)).getNode()); (is DILocation(NULL) really the best way to anchor the DILocation chain?) But I can't find what to replace InsertSubprogramStart and InsertRegionEnd with. Did they just go away? Did they go away temporarily until llvm.dbg.var is ready? I'm updating Unladen Swallow as I merge from llvm head, so I'd rather change it now than have to commit to LLVM and re-merge. >> Could you update >> http://llvm.org/docs/SourceLevelDebugging.html to describe the new >> state of the world and how to upgrade? > > I was waiting for Victor to finish up llvm.dbg.var work before updating > document, because this is still a work in progress. But since someone is > reading docs for mainline, I'll do a quick pass sooner :) Thanks! Jeffrey From gohman at apple.com Fri Nov 20 11:50:21 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 17:50:21 -0000 Subject: [llvm-commits] [llvm] r89468 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp Message-ID: <200911201750.nAKHoLQc012184@zion.cs.uiuc.edu> Author: djg Date: Fri Nov 20 11:50:21 2009 New Revision: 89468 URL: http://llvm.org/viewvc/llvm-project?rev=89468&view=rev Log: Revert the rule that considers comparisons between two pointers in the same object to be a non-capture; Duncan pointed out a way that such a comparison could be a capture. Make the rule that considers a comparison against null more specific, and only consider noalias return values compared against null. This still supports test/Transforms/GVN/nonescaping-malloc.ll, and is not susceptible to the problem Duncan pointed out with noalias arguments. Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CaptureTracking.cpp?rev=89468&r1=89467&r2=89468&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CaptureTracking.cpp (original) +++ llvm/trunk/lib/Analysis/CaptureTracking.cpp Fri Nov 20 11:50:21 2009 @@ -106,19 +106,14 @@ } break; case Instruction::ICmp: - // Don't count comparisons of the original value against null as captures. - // This allows us to ignore comparisons of malloc results with null, - // for example. - if (isIdentifiedObject(V)) + // Don't count comparisons of a no-alias return value against null as + // captures. This allows us to ignore comparisons of malloc results + // with null, for example. + if (isNoAliasCall(V)) if (ConstantPointerNull *CPN = dyn_cast(I->getOperand(1))) if (CPN->getType()->getAddressSpace() == 0) break; - // Don't count comparisons of two pointers within the same object - // as captures. - if (I->getOperand(0)->getUnderlyingObject() == - I->getOperand(1)->getUnderlyingObject()) - break; // Otherwise, be conservative. There are crazy ways to capture pointers // using comparisons. return true; From gohman at apple.com Fri Nov 20 11:52:38 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 09:52:38 -0800 Subject: [llvm-commits] [llvm] r89434 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp In-Reply-To: <4B067B5C.4000308@free.fr> References: <200911200134.nAK1Y38v027923@zion.cs.uiuc.edu> <4B067B5C.4000308@free.fr> Message-ID: On Nov 20, 2009, at 3:19 AM, Duncan Sands wrote: > > Q = GEP P, -(n+1) > if (Q > P) > break; Hi Duncan, thanks for pointing these out. I removed the same-object rule, which wasn't essential to my original testcase, and refined the null comparison rule to only apply to noalias return values, which is still sufficient for the original testcase. Dan From devang.patel at gmail.com Fri Nov 20 11:56:10 2009 From: devang.patel at gmail.com (Devang Patel) Date: Fri, 20 Nov 2009 09:56:10 -0800 Subject: [llvm-commits] [llvm] r89156 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/Analysis/DebugInfo.cpp In-Reply-To: References: <200911172239.nAHMd8Ef013044@zion.cs.uiuc.edu> <5D8EF250-53C1-4D42-80AA-CF08B1D75D51@apple.com> Message-ID: <352a1fb20911200956x3790cf5cv912ad4be60c00d3f@mail.gmail.com> Hi, On Fri, Nov 20, 2009 at 9:45 AM, Jeffrey Yasskin wrote: > On Fri, Nov 20, 2009 at 9:22 AM, Devang Patel wrote: >> >> On Nov 20, 2009, at 8:53 AM, Jeffrey Yasskin wrote: >> >>> They weren't quite dead: I was calling them. :) >> >> oops. I didn't realize. Feel free to bring this back for short term while >> you update your client. > > Well, I assume the intrinsics they insert no longer actually do what > they used to do, and so I should replace them with something. I just > want to know what to replace them with. I figured out that > InsertStopPoint turned into > ? ? ? ?IRBuilder::SetCurrentDebugLocation( > ? ? ? ? ? ?DIFactory::CreateLocation(line_number, col_number, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DISubprogram, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DILocation(NULL)).getNode()); > (is DILocation(NULL) really the best way to anchor the DILocation chain?) We can overload CreateLocation to accept orig location as MDNode * directly. > > But I can't find what to replace InsertSubprogramStart and > InsertRegionEnd with. Did they just go away? Yes. Location info collected during CreateLocation() has scope info. The DwarfWriter scans all instruction's scope info and figures out where the function (or lexical scope) starts & ends. - Devang > Did they go away > temporarily until llvm.dbg.var is ready? > I'm updating Unladen Swallow as I merge from llvm head, so I'd rather > change it now than have to commit to LLVM and re-merge. > >>> Could you update >>> http://llvm.org/docs/SourceLevelDebugging.html to describe the new >>> state of the world and how to upgrade? >> >> I was waiting for Victor to finish up llvm.dbg.var work before updating >> document, because this is still a work in progress. But since someone is >> reading docs for mainline, I'll do a quick pass sooner :) > > Thanks! > Jeffrey > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- - Devang From baldrick at free.fr Fri Nov 20 11:59:52 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 20 Nov 2009 18:59:52 +0100 Subject: [llvm-commits] [llvm] r89468 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp In-Reply-To: <200911201750.nAKHoLQc012184@zion.cs.uiuc.edu> References: <200911201750.nAKHoLQc012184@zion.cs.uiuc.edu> Message-ID: <4B06D918.20607@free.fr> Hi Dan, > + // Don't count comparisons of a no-alias return value against null as > + // captures. This allows us to ignore comparisons of malloc results > + // with null, for example. > + if (isNoAliasCall(V)) > if (ConstantPointerNull *CPN = > dyn_cast(I->getOperand(1))) > if (CPN->getType()->getAddressSpace() == 0) > break; for a little more generality you could do: isNoAliasCall(V->stripPointerCasts()) Ciao, Duncan. From baldrick at free.fr Fri Nov 20 12:04:50 2009 From: baldrick at free.fr (Duncan Sands) Date: Fri, 20 Nov 2009 19:04:50 +0100 Subject: [llvm-commits] [llvm] r89434 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp In-Reply-To: References: <200911200134.nAK1Y38v027923@zion.cs.uiuc.edu> <4B067B5C.4000308@free.fr> Message-ID: <4B06DA42.9000305@free.fr> Hi Dan, > Hi Duncan, thanks for pointing these out. I removed the same-object rule, > which wasn't essential to my original testcase, and refined the null > comparison rule to only apply to noalias return values, which is still > sufficient for the original testcase. sorry for annoying you with all these crazy examples! Personally I would be happy with a notion of pointer capture based on alias analysis (i.e. a pointer escapes if there is some other pointer which might alias it), with rules saying that dissecting pointers and reconstructing them from the pieces "doesn't count", i.e. you are allowed to say that the new one doesn't alias the original, and thus that the original was not captured. But Chris rejected this - perhaps we should gang up on him? :) Ciao, Duncan. From jyasskin at google.com Fri Nov 20 12:22:51 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Fri, 20 Nov 2009 10:22:51 -0800 Subject: [llvm-commits] [llvm] r86914 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h include/llvm/Metadata.h lib/Analysis/DebugInfo.cpp lib/VMCore/Metadata.cpp In-Reply-To: <9DC587FF-9855-4F2E-BC34-5A40A9233CEA@apple.com> References: <200911120050.nAC0owVT014507@zion.cs.uiuc.edu> <9DC587FF-9855-4F2E-BC34-5A40A9233CEA@apple.com> Message-ID: On Fri, Nov 20, 2009 at 9:20 AM, Devang Patel wrote: > Hi! > > On Nov 20, 2009, at 8:32 AM, Jeffrey Yasskin wrote: > >> Hi Devang. This is inconvenient when I want to pass a string in from a >> std::string, PyString, or from Function::getName(). I don't think it's >> worth it just to let users pass 0 instead of "". > > The debugger and other tools consuming DWARF info are not expecting to see > "". > > If StringRef are used then > 1) The DwarfWriter needs to check for "" DwarfDebug::CreateGlobalVariableDIE currently does: const char *LinkageName = GV.getLinkageName(); if (LinkageName) { ... If getLinkageName returned a StringRef, DwarfDebug could use "if (!LinkageName.empty())" instead. getLinkageName calls getStringField, which actually jumps through hoops to _avoid_ returning a StringRef, and to canonicalize "" to NULL ... which means that even today if the CreateFoo functions took StringRef, users could pass "", and DwarfDebug's current code would work. > 2) The clients needs to check for optional arguments. I don't understand: callers of CreateGlobalVariable, for example, already have to pass something for LinkageName. It's not defaulted. And if it were defaulted, defaulting to "" would be as easy as defaulting to NULL. If you're talking about clients like gdb, it's clearly a win to write less debug information when a field isn't present, but "" should count as not present. > If const char * are used then only clients needs to get pointer to the > string. > > My preferred approach was to let StringRef handle null for optional > arguments, but it has performance implications. I think my position on StringRef is that StringRef() should equal either StringRef(NULL) or StringRef(""). If we like people using NULL for "no data", then StringRef(NULL) should work. If not?if we don't think there's a use for two "no data" representations, which is my position?then StringRef() should ==StringRef(""), which allows DwarfDebug to only handle one case again, even if it wants to pull the data out of the StringRef. ... but that's not particularly important for debug info. > I am not tied to one position, but prefer a approach that makes either > DwarfWriter OR clients responsible to do the right thing. > > - > Devang >> >> On Wed, Nov 11, 2009 at 4:50 PM, Devang Patel wrote: >>> >>> Author: dpatel >>> Date: Wed Nov 11 18:50:58 2009 >>> New Revision: 86914 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=86914&view=rev >>> Log: >>> Do not use StringRef in DebugInfo interface. >>> This allows StringRef to skip controversial if(str) check in constructor. >>> Buildbots, wait for corresponding clang and llvm-gcc FE check-ins! >>> >>> Modified: >>> ? llvm/trunk/include/llvm/Analysis/DebugInfo.h >>> ? llvm/trunk/include/llvm/Metadata.h >>> ? llvm/trunk/lib/Analysis/DebugInfo.cpp >>> ? llvm/trunk/lib/VMCore/Metadata.cpp >>> >>> Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h >>> URL: >>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=86914&r1=86913&r2=86914&view=diff >>> >>> >>> ============================================================================== >>> --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) >>> +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Wed Nov 11 18:50:58 2009 >>> @@ -496,26 +496,26 @@ >>> ? ?/// CreateCompileUnit - Create a new descriptor for the specified >>> compile >>> ? ?/// unit. >>> ? ?DICompileUnit CreateCompileUnit(unsigned LangID, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Filenae, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Directory, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Producer, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Filename, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Directory, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Producer, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool isMain = false, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool isOptimized = false, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char *Flags = "", >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned RunTimeVer = 0); >>> >>> ? ?/// CreateEnumerator - Create a single enumerator value. >>> - ? ?DIEnumerator CreateEnumerator(StringRef Name, uint64_t Val); >>> + ? ?DIEnumerator CreateEnumerator(const char * Name, uint64_t Val); >>> >>> ? ?/// CreateBasicType - Create a basic type like int, float, etc. >>> - ? ?DIBasicType CreateBasicType(DIDescriptor Context, StringRef Name, >>> + ? ?DIBasicType CreateBasicType(DIDescriptor Context, const char * Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, unsigned >>> LineNumber, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t SizeInBits, uint64_t AlignInBits, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t OffsetInBits, unsigned Flags, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned Encoding); >>> >>> ? ?/// CreateBasicType - Create a basic type like int, float, etc. >>> - ? ?DIBasicType CreateBasicTypeEx(DIDescriptor Context, StringRef Name, >>> + ? ?DIBasicType CreateBasicTypeEx(DIDescriptor Context, const char * >>> Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, unsigned >>> LineNumber, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Constant *SizeInBits, Constant >>> *AlignInBits, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Constant *OffsetInBits, unsigned Flags, >>> @@ -524,7 +524,7 @@ >>> ? ?/// CreateDerivedType - Create a derived type like const qualified >>> type, >>> ? ?/// pointer, typedef, etc. >>> ? ?DIDerivedType CreateDerivedType(unsigned Tag, DIDescriptor Context, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t SizeInBits, uint64_t >>> AlignInBits, >>> @@ -534,7 +534,7 @@ >>> ? ?/// CreateDerivedType - Create a derived type like const qualified >>> type, >>> ? ?/// pointer, typedef, etc. >>> ? ?DIDerivedType CreateDerivedTypeEx(unsigned Tag, DIDescriptor Context, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Constant *SizeInBits, Constant >>> *AlignInBits, >>> @@ -543,7 +543,7 @@ >>> >>> ? ?/// CreateCompositeType - Create a composite type like array, struct, >>> etc. >>> ? ?DICompositeType CreateCompositeType(unsigned Tag, DIDescriptor >>> Context, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t SizeInBits, >>> @@ -555,7 +555,7 @@ >>> >>> ? ?/// CreateCompositeType - Create a composite type like array, struct, >>> etc. >>> ? ?DICompositeType CreateCompositeTypeEx(unsigned Tag, DIDescriptor >>> Context, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Constant *SizeInBits, >>> @@ -567,25 +567,25 @@ >>> >>> ? ?/// CreateSubprogram - Create a new descriptor for the specified >>> subprogram. >>> ? ?/// See comments in DISubprogram for descriptions of these fields. >>> - ? ?DISubprogram CreateSubprogram(DIDescriptor Context, StringRef Name, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef DisplayName, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef LinkageName, >>> + ? ?DISubprogram CreateSubprogram(DIDescriptor Context, const char * >>> Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * DisplayName, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * LinkageName, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, unsigned >>> LineNo, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DIType Type, bool isLocalToUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool isDefinition); >>> >>> ? ?/// CreateGlobalVariable - Create a new descriptor for the specified >>> global. >>> ? ?DIGlobalVariable >>> - ? ?CreateGlobalVariable(DIDescriptor Context, StringRef Name, >>> - ? ? ? ? ? ? ? ? ? ? ? ? StringRef DisplayName, >>> - ? ? ? ? ? ? ? ? ? ? ? ? StringRef LinkageName, >>> + ? ?CreateGlobalVariable(DIDescriptor Context, const char * Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? const char * DisplayName, >>> + ? ? ? ? ? ? ? ? ? ? ? ? const char * LinkageName, >>> ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNo, DIType Type, bool isLocalToUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? bool isDefinition, llvm::GlobalVariable *GV); >>> >>> ? ?/// CreateVariable - Create a new descriptor for the specified >>> variable. >>> ? ?DIVariable CreateVariable(unsigned Tag, DIDescriptor Context, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, unsigned LineNo, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DIType Type); >>> >>> >>> Modified: llvm/trunk/include/llvm/Metadata.h >>> URL: >>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Metadata.h?rev=86914&r1=86913&r2=86914&view=diff >>> >>> >>> ============================================================================== >>> --- llvm/trunk/include/llvm/Metadata.h (original) >>> +++ llvm/trunk/include/llvm/Metadata.h Wed Nov 11 18:50:58 2009 >>> @@ -60,6 +60,7 @@ >>> >>> ?public: >>> ?static MDString *get(LLVMContext &Context, StringRef Str); >>> + ?static MDString *get(LLVMContext &Context, const char *Str); >>> >>> ?StringRef getString() const { return Str; } >>> >>> >>> Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp >>> URL: >>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=86914&r1=86913&r2=86914&view=diff >>> >>> >>> ============================================================================== >>> --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) >>> +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Wed Nov 11 18:50:58 2009 >>> @@ -653,9 +653,9 @@ >>> ?/// CreateCompileUnit - Create a new descriptor for the specified >>> compile >>> ?/// unit. ?Note that this does not unique compile units within the >>> module. >>> ?DICompileUnit DIFactory::CreateCompileUnit(unsigned LangID, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Filename, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Directory, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Producer, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Filename, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Directory, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Producer, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool isMain, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool isOptimized, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char *Flags, >>> @@ -677,7 +677,7 @@ >>> ?} >>> >>> ?/// CreateEnumerator - Create a single enumerator value. >>> -DIEnumerator DIFactory::CreateEnumerator(StringRef Name, uint64_t Val){ >>> +DIEnumerator DIFactory::CreateEnumerator(const char * Name, uint64_t >>> Val){ >>> ?Value *Elts[] = { >>> ? ?GetTagConstant(dwarf::DW_TAG_enumerator), >>> ? ?MDString::get(VMContext, Name), >>> @@ -689,7 +689,7 @@ >>> >>> ?/// CreateBasicType - Create a basic type like int, float, etc. >>> ?DIBasicType DIFactory::CreateBasicType(DIDescriptor Context, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint64_t SizeInBits, >>> @@ -714,7 +714,7 @@ >>> >>> ?/// CreateBasicType - Create a basic type like int, float, etc. >>> ?DIBasicType DIFactory::CreateBasicTypeEx(DIDescriptor Context, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Constant *SizeInBits, >>> @@ -741,7 +741,7 @@ >>> ?/// pointer, typedef, etc. >>> ?DIDerivedType DIFactory::CreateDerivedType(unsigned Tag, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DIDescriptor Context, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint64_t SizeInBits, >>> @@ -769,7 +769,7 @@ >>> ?/// pointer, typedef, etc. >>> ?DIDerivedType DIFactory::CreateDerivedTypeEx(unsigned Tag, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DIDescriptor Context, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Constant *SizeInBits, >>> @@ -796,7 +796,7 @@ >>> ?/// CreateCompositeType - Create a composite type like array, struct, >>> etc. >>> ?DICompositeType DIFactory::CreateCompositeType(unsigned Tag, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DIDescriptor Context, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint64_t SizeInBits, >>> @@ -828,7 +828,7 @@ >>> ?/// CreateCompositeType - Create a composite type like array, struct, >>> etc. >>> ?DICompositeType DIFactory::CreateCompositeTypeEx(unsigned Tag, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DIDescriptor Context, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit >>> CompileUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Constant *SizeInBits, >>> @@ -861,9 +861,9 @@ >>> ?/// See comments in DISubprogram for descriptions of these fields. ?This >>> ?/// method does not unique the generated descriptors. >>> ?DISubprogram DIFactory::CreateSubprogram(DIDescriptor Context, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef DisplayName, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef LinkageName, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * DisplayName, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * LinkageName, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNo, DIType Type, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool isLocalToUnit, >>> @@ -887,9 +887,9 @@ >>> >>> ?/// CreateGlobalVariable - Create a new descriptor for the specified >>> global. >>> ?DIGlobalVariable >>> -DIFactory::CreateGlobalVariable(DIDescriptor Context, StringRef Name, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef DisplayName, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef LinkageName, >>> +DIFactory::CreateGlobalVariable(DIDescriptor Context, const char * Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * DisplayName, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * LinkageName, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNo, DIType Type,bool >>> isLocalToUnit, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool isDefinition, llvm::GlobalVariable >>> *Val) { >>> @@ -921,7 +921,7 @@ >>> >>> ?/// CreateVariable - Create a new descriptor for the specified variable. >>> ?DIVariable DIFactory::CreateVariable(unsigned Tag, DIDescriptor Context, >>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, unsigned >>> LineNo, >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DIType Type) { >>> ?Value *Elts[] = { >>> >>> Modified: llvm/trunk/lib/VMCore/Metadata.cpp >>> URL: >>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=86914&r1=86913&r2=86914&view=diff >>> >>> >>> ============================================================================== >>> --- llvm/trunk/lib/VMCore/Metadata.cpp (original) >>> +++ llvm/trunk/lib/VMCore/Metadata.cpp Wed Nov 11 18:50:58 2009 >>> @@ -39,6 +39,17 @@ >>> ? ?new MDString(Context, Entry.getKey()); >>> ?} >>> >>> +MDString *MDString::get(LLVMContext &Context, const char *Str) { >>> + ?LLVMContextImpl *pImpl = Context.pImpl; >>> + ?StringMapEntry &Entry = >>> + ? ?pImpl->MDStringCache.GetOrCreateValue(Str ? StringRef(Str) : >>> StringRef()); >>> + ?MDString *&S = Entry.getValue(); >>> + ?if (S) return S; >>> + >>> + ?return S = >>> + ? ?new MDString(Context, Entry.getKey()); >>> +} >>> + >>> >>> ?//===----------------------------------------------------------------------===// >>> ?// MDNode implementation. >>> ?// >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> > > From jyasskin at google.com Fri Nov 20 12:25:20 2009 From: jyasskin at google.com (Jeffrey Yasskin) Date: Fri, 20 Nov 2009 10:25:20 -0800 Subject: [llvm-commits] [llvm] r89156 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/Analysis/DebugInfo.cpp In-Reply-To: <352a1fb20911200956x3790cf5cv912ad4be60c00d3f@mail.gmail.com> References: <200911172239.nAHMd8Ef013044@zion.cs.uiuc.edu> <5D8EF250-53C1-4D42-80AA-CF08B1D75D51@apple.com> <352a1fb20911200956x3790cf5cv912ad4be60c00d3f@mail.gmail.com> Message-ID: On Fri, Nov 20, 2009 at 9:56 AM, Devang Patel wrote: > Hi, > > On Fri, Nov 20, 2009 at 9:45 AM, Jeffrey Yasskin wrote: >> On Fri, Nov 20, 2009 at 9:22 AM, Devang Patel wrote: >>> >>> On Nov 20, 2009, at 8:53 AM, Jeffrey Yasskin wrote: >>> >>>> They weren't quite dead: I was calling them. :) >>> >>> oops. I didn't realize. Feel free to bring this back for short term while >>> you update your client. >> >> Well, I assume the intrinsics they insert no longer actually do what >> they used to do, and so I should replace them with something. I just >> want to know what to replace them with. I figured out that >> InsertStopPoint turned into >> ? ? ? ?IRBuilder::SetCurrentDebugLocation( >> ? ? ? ? ? ?DIFactory::CreateLocation(line_number, col_number, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DISubprogram, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DILocation(NULL)).getNode()); >> (is DILocation(NULL) really the best way to anchor the DILocation chain?) > > We can overload CreateLocation to accept orig location as MDNode * directly. And then just "NULL" would terminate the chain? I'd suggest defaulting that argument too. :) >> >> But I can't find what to replace InsertSubprogramStart and >> InsertRegionEnd with. Did they just go away? > > Yes. Location info collected during CreateLocation() has scope info. > The DwarfWriter scans all instruction's scope info and figures out > where the function (or lexical scope) starts & ends. Ah, ok, that's easier anyway. I'll change it in Unladen. Thanks! From stoklund at 2pi.dk Fri Nov 20 12:54:59 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 20 Nov 2009 18:54:59 -0000 Subject: [llvm-commits] [llvm] r89470 - /llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Message-ID: <200911201854.nAKIsx3C014538@zion.cs.uiuc.edu> Author: stoklund Date: Fri Nov 20 12:54:59 2009 New Revision: 89470 URL: http://llvm.org/viewvc/llvm-project?rev=89470&view=rev Log: More consistent labelling of basic blocks in debug output Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=89470&r1=89469&r2=89470&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Fri Nov 20 12:54:59 2009 @@ -136,7 +136,8 @@ for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); mbbi != mbbe; ++mbbi) { - OS << mbbi->getName() << ":\n"; + OS << "BB#" << mbbi->getNumber() + << ":\t\t# derived from " << mbbi->getName() << "\n"; for (MachineBasicBlock::iterator mii = mbbi->begin(), mie = mbbi->end(); mii != mie; ++mii) { OS << getInstructionIndex(mii) << '\t' << *mii; From david_goodwin at apple.com Fri Nov 20 13:32:48 2009 From: david_goodwin at apple.com (David Goodwin) Date: Fri, 20 Nov 2009 19:32:48 -0000 Subject: [llvm-commits] [llvm] r89471 - in /llvm/trunk: include/llvm/CodeGen/LatencyPriorityQueue.h include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/AggressiveAntiDepBreaker.cpp lib/CodeGen/AggressiveAntiDepBreaker.h lib/CodeGen/AntiDepBreaker.h lib/CodeGen/CriticalAntiDepBreaker.cpp lib/CodeGen/CriticalAntiDepBreaker.h lib/CodeGen/LatencyPriorityQueue.cpp lib/CodeGen/PostRASchedulerList.cpp lib/CodeGen/ScheduleDAG.cpp Message-ID: <200911201932.nAKJWmcE016211@zion.cs.uiuc.edu> Author: david_goodwin Date: Fri Nov 20 13:32:48 2009 New Revision: 89471 URL: http://llvm.org/viewvc/llvm-project?rev=89471&view=rev Log: Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks. Modified: llvm/trunk/include/llvm/CodeGen/LatencyPriorityQueue.h llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h llvm/trunk/lib/CodeGen/AntiDepBreaker.h llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h llvm/trunk/lib/CodeGen/LatencyPriorityQueue.cpp llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/LatencyPriorityQueue.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LatencyPriorityQueue.h?rev=89471&r1=89470&r2=89471&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LatencyPriorityQueue.h (original) +++ llvm/trunk/include/llvm/CodeGen/LatencyPriorityQueue.h Fri Nov 20 13:32:48 2009 @@ -40,18 +40,11 @@ /// mobility. std::vector NumNodesSolelyBlocking; - /// IgnoreAntiDep - Ignore anti-dependencies - bool IgnoreAntiDep; - /// Queue - The queue. PriorityQueue, latency_sort> Queue; public: - LatencyPriorityQueue() : IgnoreAntiDep(false), Queue(latency_sort(this)) { - } - - void setIgnoreAntiDep(bool ignore) { - IgnoreAntiDep = ignore; + LatencyPriorityQueue() : Queue(latency_sort(this)) { } void initNodes(std::vector &sunits) { @@ -72,7 +65,7 @@ unsigned getLatency(unsigned NodeNum) const { assert(NodeNum < (*SUnits).size()); - return (*SUnits)[NodeNum].getHeight(IgnoreAntiDep); + return (*SUnits)[NodeNum].getHeight(); } unsigned getNumSolelyBlockNodes(unsigned NodeNum) const { Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=89471&r1=89470&r2=89471&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Fri Nov 20 13:32:48 2009 @@ -340,34 +340,30 @@ void removePred(const SDep &D); /// getDepth - Return the depth of this node, which is the length of the - /// maximum path up to any node with has no predecessors. If IgnoreAntiDep - /// is true, ignore anti-dependence edges. - unsigned getDepth(bool IgnoreAntiDep=false) const { + /// maximum path up to any node with has no predecessors. + unsigned getDepth() const { if (!isDepthCurrent) - const_cast(this)->ComputeDepth(IgnoreAntiDep); + const_cast(this)->ComputeDepth(); return Depth; } /// getHeight - Return the height of this node, which is the length of the - /// maximum path down to any node with has no successors. If IgnoreAntiDep - /// is true, ignore anti-dependence edges. - unsigned getHeight(bool IgnoreAntiDep=false) const { + /// maximum path down to any node with has no successors. + unsigned getHeight() const { if (!isHeightCurrent) - const_cast(this)->ComputeHeight(IgnoreAntiDep); + const_cast(this)->ComputeHeight(); return Height; } /// setDepthToAtLeast - If NewDepth is greater than this node's /// depth value, set it to be the new depth value. This also - /// recursively marks successor nodes dirty. If IgnoreAntiDep is - /// true, ignore anti-dependence edges. - void setDepthToAtLeast(unsigned NewDepth, bool IgnoreAntiDep=false); + /// recursively marks successor nodes dirty. + void setDepthToAtLeast(unsigned NewDepth); /// setDepthToAtLeast - If NewDepth is greater than this node's /// depth value, set it to be the new height value. This also - /// recursively marks predecessor nodes dirty. If IgnoreAntiDep is - /// true, ignore anti-dependence edges. - void setHeightToAtLeast(unsigned NewHeight, bool IgnoreAntiDep=false); + /// recursively marks predecessor nodes dirty. + void setHeightToAtLeast(unsigned NewHeight); /// setDepthDirty - Set a flag in this node to indicate that its /// stored Depth value will require recomputation the next time @@ -400,8 +396,8 @@ void print(raw_ostream &O, const ScheduleDAG *G) const; private: - void ComputeDepth(bool IgnoreAntiDep); - void ComputeHeight(bool IgnoreAntiDep); + void ComputeDepth(); + void ComputeHeight(); }; //===--------------------------------------------------------------------===// Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=89471&r1=89470&r2=89471&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Fri Nov 20 13:32:48 2009 @@ -28,11 +28,6 @@ #include "llvm/Support/raw_ostream.h" using namespace llvm; -static cl::opt -AntiDepTrials("agg-antidep-trials", - cl::desc("Maximum number of anti-dependency breaking passes"), - cl::init(1), cl::Hidden); - // If DebugDiv > 0 then only break antidep with (ID % DebugDiv) == DebugMod static cl::opt DebugDiv("agg-antidep-debugdiv", @@ -118,7 +113,7 @@ MRI(MF.getRegInfo()), TRI(MF.getTarget().getRegisterInfo()), AllocatableSet(TRI->getAllocatableSet(MF)), - State(NULL), SavedState(NULL) { + State(NULL) { /* Collect a bitset of all registers that are only broken if they are on the critical path. */ for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) { @@ -138,13 +133,6 @@ AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() { delete State; - delete SavedState; -} - -unsigned AggressiveAntiDepBreaker::GetMaxTrials() { - if (AntiDepTrials <= 0) - return 1; - return AntiDepTrials; } void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) { @@ -216,8 +204,6 @@ void AggressiveAntiDepBreaker::FinishBlock() { delete State; State = NULL; - delete SavedState; - SavedState = NULL; } void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, @@ -251,10 +237,6 @@ } } DEBUG(errs() << '\n'); - - // We're starting a new schedule region so forget any saved state. - delete SavedState; - SavedState = NULL; } bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI, @@ -293,27 +275,20 @@ } } -/// AntiDepEdges - Return in Edges the anti- and output- -/// dependencies on Regs in SU that we want to consider for breaking. -static void AntiDepEdges(SUnit *SU, - const AntiDepBreaker::AntiDepRegVector& Regs, - std::vector& Edges) { - AntiDepBreaker::AntiDepRegSet RegSet; - for (unsigned i = 0, e = Regs.size(); i < e; ++i) - RegSet.insert(Regs[i]); - +/// AntiDepEdges - Return in Edges the anti- and output- dependencies +/// in SU that we want to consider for breaking. +static void AntiDepEdges(SUnit *SU, std::vector& Edges) { + SmallSet RegSet; for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end(); P != PE; ++P) { if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) { unsigned Reg = P->getReg(); - if (RegSet.count(Reg) != 0) { + if (RegSet.count(Reg) == 0) { Edges.push_back(&*P); - RegSet.erase(Reg); + RegSet.insert(Reg); } } } - - assert(RegSet.empty() && "Expected all antidep registers to be found"); } /// CriticalPathStep - Return the next SUnit after SU on the bottom-up @@ -698,7 +673,6 @@ /// unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( std::vector& SUnits, - CandidateMap& Candidates, MachineBasicBlock::iterator& Begin, MachineBasicBlock::iterator& End, unsigned InsertPosIndex) { @@ -711,16 +685,6 @@ // so just duck out immediately if the block is empty. if (SUnits.empty()) return 0; - // Manage saved state to enable multiple passes... - if (AntiDepTrials > 1) { - if (SavedState == NULL) { - SavedState = new AggressiveAntiDepState(*State); - } else { - delete State; - State = new AggressiveAntiDepState(*SavedState); - } - } - // For each regclass the next register to use for renaming. RenameOrderType RenameOrder; @@ -749,21 +713,14 @@ CriticalPathMI = CriticalPathSU->getInstr(); } - // Even if there are no anti-dependencies we still need to go - // through the instructions to update Def, Kills, etc. #ifndef NDEBUG - if (Candidates.empty()) { - DEBUG(errs() << "\n===== No anti-dependency candidates\n"); - } else { - DEBUG(errs() << "\n===== Attempting to break " << Candidates.size() << - " anti-dependencies\n"); - DEBUG(errs() << "Available regs:"); - for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { - if (!State->IsLive(Reg)) - DEBUG(errs() << " " << TRI->getName(Reg)); - } - DEBUG(errs() << '\n'); + DEBUG(errs() << "\n===== Aggressive anti-dependency breaking\n"); + DEBUG(errs() << "Available regs:"); + for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { + if (!State->IsLive(Reg)) + DEBUG(errs() << " " << TRI->getName(Reg)); } + DEBUG(errs() << '\n'); #endif // Attempt to break anti-dependence edges. Walk the instructions @@ -784,14 +741,11 @@ // Process the defs in MI... PrescanInstruction(MI, Count, PassthruRegs); - // The the dependence edges that represent anti- and output- + // The dependence edges that represent anti- and output- // dependencies that are candidates for breaking. std::vector Edges; SUnit *PathSU = MISUnitMap[MI]; - AntiDepBreaker::CandidateMap::iterator - citer = Candidates.find(PathSU); - if (citer != Candidates.end()) - AntiDepEdges(PathSU, citer->second, Edges); + AntiDepEdges(PathSU, Edges); // If MI is not on the critical path, then we don't rename // registers in the CriticalPathSet. @@ -847,12 +801,32 @@ // anti-dependency since those edges would prevent such // units from being scheduled past each other // regardless. + // + // Also, if there are dependencies on other SUnits with the + // same register as the anti-dependency, don't attempt to + // break it. for (SUnit::pred_iterator P = PathSU->Preds.begin(), PE = PathSU->Preds.end(); P != PE; ++P) { - if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti)) { + if (P->getSUnit() == NextSU ? + (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) : + (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) { + AntiDepReg = 0; + break; + } + } + for (SUnit::pred_iterator P = PathSU->Preds.begin(), + PE = PathSU->Preds.end(); P != PE; ++P) { + if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) && + (P->getKind() != SDep::Output)) { DEBUG(errs() << " (real dependency)\n"); AntiDepReg = 0; break; + } else if ((P->getSUnit() != NextSU) && + (P->getKind() == SDep::Data) && + (P->getReg() == AntiDepReg)) { + DEBUG(errs() << " (other dependency)\n"); + AntiDepReg = 0; + break; } } Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=89471&r1=89470&r2=89471&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Fri Nov 20 13:32:48 2009 @@ -27,12 +27,11 @@ #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallSet.h" +#include namespace llvm { /// Class AggressiveAntiDepState - /// Contains all the state necessary for anti-dep breaking. We place - /// into a separate class so be can conveniently save/restore it to - /// enable multi-pass anti-dep breaking. + /// Contains all the state necessary for anti-dep breaking. class AggressiveAntiDepState { public: /// RegisterReference - Information about a register reference @@ -126,23 +125,11 @@ /// registers. AggressiveAntiDepState *State; - /// SavedState - The state for the start of an anti-dep - /// region. Used to restore the state at the beginning of each - /// pass - AggressiveAntiDepState *SavedState; - public: AggressiveAntiDepBreaker(MachineFunction& MFi, TargetSubtarget::RegClassVector& CriticalPathRCs); ~AggressiveAntiDepBreaker(); - /// GetMaxTrials - As anti-dependencies are broken, additional - /// dependencies may be exposed, so multiple passes are required. - unsigned GetMaxTrials(); - - /// NeedCandidates - Candidates required. - bool NeedCandidates() { return true; } - /// Start - Initialize anti-dep breaking for a new basic block. void StartBlock(MachineBasicBlock *BB); @@ -150,7 +137,6 @@ /// of the ScheduleDAG and break them by renaming registers. /// unsigned BreakAntiDependencies(std::vector& SUnits, - CandidateMap& Candidates, MachineBasicBlock::iterator& Begin, MachineBasicBlock::iterator& End, unsigned InsertPosIndex); Modified: llvm/trunk/lib/CodeGen/AntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AntiDepBreaker.h?rev=89471&r1=89470&r2=89471&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/AntiDepBreaker.h Fri Nov 20 13:32:48 2009 @@ -21,9 +21,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/ADT/SmallSet.h" -#include "llvm/ADT/SmallVector.h" -#include +#include namespace llvm { @@ -32,20 +30,8 @@ /// anti-dependencies. class AntiDepBreaker { public: - typedef SmallSet AntiDepRegSet; - typedef SmallVector AntiDepRegVector; - typedef std::map CandidateMap; - virtual ~AntiDepBreaker(); - /// GetMaxTrials - Return the maximum number of anti-dependence - /// breaking attempts that will be made for a block. - virtual unsigned GetMaxTrials() =0; - - /// NeedCandidates - Return true if the schedule must provide - /// candidates with BreakAntiDependencies(). - virtual bool NeedCandidates() =0; - /// Start - Initialize anti-dep breaking for a new basic block. virtual void StartBlock(MachineBasicBlock *BB) =0; @@ -54,7 +40,6 @@ /// the number of anti-dependencies broken. /// virtual unsigned BreakAntiDependencies(std::vector& SUnits, - CandidateMap& Candidates, MachineBasicBlock::iterator& Begin, MachineBasicBlock::iterator& End, unsigned InsertPosIndex) =0; Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=89471&r1=89470&r2=89471&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Fri Nov 20 13:32:48 2009 @@ -316,7 +316,6 @@ unsigned CriticalAntiDepBreaker:: BreakAntiDependencies(std::vector& SUnits, - CandidateMap& Candidates, MachineBasicBlock::iterator& Begin, MachineBasicBlock::iterator& End, unsigned InsertPosIndex) { Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h?rev=89471&r1=89470&r2=89471&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h Fri Nov 20 13:32:48 2009 @@ -25,6 +25,7 @@ #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallSet.h" +#include namespace llvm { class CriticalAntiDepBreaker : public AntiDepBreaker { @@ -64,13 +65,6 @@ CriticalAntiDepBreaker(MachineFunction& MFi); ~CriticalAntiDepBreaker(); - /// GetMaxTrials - Critical path anti-dependence breaking requires - /// only a single pass - unsigned GetMaxTrials() { return 1; } - - /// NeedCandidates - Candidates not needed. - bool NeedCandidates() { return false; } - /// Start - Initialize anti-dep breaking for a new basic block. void StartBlock(MachineBasicBlock *BB); @@ -78,7 +72,6 @@ /// of the ScheduleDAG and break them by renaming registers. /// unsigned BreakAntiDependencies(std::vector& SUnits, - CandidateMap& Candidates, MachineBasicBlock::iterator& Begin, MachineBasicBlock::iterator& End, unsigned InsertPosIndex); Modified: llvm/trunk/lib/CodeGen/LatencyPriorityQueue.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LatencyPriorityQueue.cpp?rev=89471&r1=89470&r2=89471&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LatencyPriorityQueue.cpp (original) +++ llvm/trunk/lib/CodeGen/LatencyPriorityQueue.cpp Fri Nov 20 13:32:48 2009 @@ -55,10 +55,6 @@ SUnit *OnlyAvailablePred = 0; for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { - if (IgnoreAntiDep && - ((I->getKind() == SDep::Anti) || (I->getKind() == SDep::Output))) - continue; - SUnit &Pred = *I->getSUnit(); if (!Pred.isScheduled) { // We found an available, but not scheduled, predecessor. If it's the @@ -78,10 +74,6 @@ unsigned NumNodesBlocking = 0; for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { - if (IgnoreAntiDep && - ((I->getKind() == SDep::Anti) || (I->getKind() == SDep::Output))) - continue; - if (getSingleUnscheduledPred(I->getSUnit()) == SU) ++NumNodesBlocking; } @@ -98,10 +90,6 @@ void LatencyPriorityQueue::ScheduledNode(SUnit *SU) { for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { - if (IgnoreAntiDep && - ((I->getKind() == SDep::Anti) || (I->getKind() == SDep::Output))) - continue; - AdjustPriorityOfUnscheduledPreds(I->getSUnit()); } } Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=89471&r1=89470&r2=89471&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Fri Nov 20 13:32:48 2009 @@ -175,11 +175,10 @@ void FixupKills(MachineBasicBlock *MBB); private: - void ReleaseSucc(SUnit *SU, SDep *SuccEdge, bool IgnoreAntiDep); - void ReleaseSuccessors(SUnit *SU, bool IgnoreAntiDep); - void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle, bool IgnoreAntiDep); - void ListScheduleTopDown( - AntiDepBreaker::CandidateMap *AntiDepCandidates); + void ReleaseSucc(SUnit *SU, SDep *SuccEdge); + void ReleaseSuccessors(SUnit *SU); + void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle); + void ListScheduleTopDown(); void StartBlockForKills(MachineBasicBlock *BB); // ToggleKillFlag - Toggle a register operand kill flag. Other @@ -322,50 +321,24 @@ BuildSchedGraph(AA); if (AntiDepBreak != NULL) { - AntiDepBreaker::CandidateMap AntiDepCandidates; - const bool NeedCandidates = AntiDepBreak->NeedCandidates(); + unsigned Broken = + AntiDepBreak->BreakAntiDependencies(SUnits, Begin, InsertPos, + InsertPosIndex); - for (unsigned i = 0, Trials = AntiDepBreak->GetMaxTrials(); - i < Trials; ++i) { - DEBUG(errs() << "\n********** Break Anti-Deps, Trial " << - i << " **********\n"); - - // If candidates are required, then schedule forward ignoring - // anti-dependencies to collect the candidate operands for - // anti-dependence breaking. The candidates will be the def - // operands for the anti-dependencies that if broken would allow - // an improved schedule - if (NeedCandidates) { - DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) - SUnits[su].dumpAll(this)); - - AntiDepCandidates.clear(); - AvailableQueue.initNodes(SUnits); - ListScheduleTopDown(&AntiDepCandidates); - AvailableQueue.releaseState(); - } - - unsigned Broken = - AntiDepBreak->BreakAntiDependencies(SUnits, AntiDepCandidates, - Begin, InsertPos, InsertPosIndex); - + if (Broken != 0) { // We made changes. Update the dependency graph. // Theoretically we could update the graph in place: // When a live range is changed to use a different register, remove // the def's anti-dependence *and* output-dependence edges due to // that register, and add new anti-dependence and output-dependence // edges based on the next live range of the register. - if ((Broken != 0) || NeedCandidates) { - SUnits.clear(); - Sequence.clear(); - EntrySU = SUnit(); - ExitSU = SUnit(); - BuildSchedGraph(AA); - } - + SUnits.clear(); + Sequence.clear(); + EntrySU = SUnit(); + ExitSU = SUnit(); + BuildSchedGraph(AA); + NumFixedAnti += Broken; - if (Broken == 0) - break; } } @@ -374,7 +347,7 @@ SUnits[su].dumpAll(this)); AvailableQueue.initNodes(SUnits); - ListScheduleTopDown(NULL); + ListScheduleTopDown(); AvailableQueue.releaseState(); } @@ -573,8 +546,7 @@ /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to /// the PendingQueue if the count reaches zero. Also update its cycle bound. -void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge, - bool IgnoreAntiDep) { +void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) { SUnit *SuccSU = SuccEdge->getSUnit(); #ifndef NDEBUG @@ -590,8 +562,7 @@ // Compute how many cycles it will be before this actually becomes // available. This is the max of the start time of all predecessors plus // their latencies. - SuccSU->setDepthToAtLeast(SU->getDepth(IgnoreAntiDep) + - SuccEdge->getLatency(), IgnoreAntiDep); + SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency()); // If all the node's predecessors are scheduled, this node is ready // to be scheduled. Ignore the special ExitSU node. @@ -600,40 +571,34 @@ } /// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors. -void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU, bool IgnoreAntiDep) { +void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) { for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { - if (IgnoreAntiDep && - ((I->getKind() == SDep::Anti) || (I->getKind() == SDep::Output))) - continue; - ReleaseSucc(SU, &*I, IgnoreAntiDep); + ReleaseSucc(SU, &*I); } } /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending /// count of its successors. If a successor pending count is zero, add it to /// the Available queue. -void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle, - bool IgnoreAntiDep) { +void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { DEBUG(errs() << "*** Scheduling [" << CurCycle << "]: "); DEBUG(SU->dump(this)); Sequence.push_back(SU); - assert(CurCycle >= SU->getDepth(IgnoreAntiDep) && + assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!"); - SU->setDepthToAtLeast(CurCycle, IgnoreAntiDep); + SU->setDepthToAtLeast(CurCycle); - ReleaseSuccessors(SU, IgnoreAntiDep); + ReleaseSuccessors(SU); SU->isScheduled = true; AvailableQueue.ScheduledNode(SU); } /// ListScheduleTopDown - The main loop of list scheduling for top-down /// schedulers. -void SchedulePostRATDList::ListScheduleTopDown( - AntiDepBreaker::CandidateMap *AntiDepCandidates) { +void SchedulePostRATDList::ListScheduleTopDown() { unsigned CurCycle = 0; - const bool IgnoreAntiDep = (AntiDepCandidates != NULL); // We're scheduling top-down but we're visiting the regions in // bottom-up order, so we don't know the hazards at the start of a @@ -641,33 +606,13 @@ // blocks are a single region). HazardRec->Reset(); - // If ignoring anti-dependencies, the Schedule DAG still has Anti - // dep edges, but we ignore them for scheduling purposes - AvailableQueue.setIgnoreAntiDep(IgnoreAntiDep); - // Release any successors of the special Entry node. - ReleaseSuccessors(&EntrySU, IgnoreAntiDep); + ReleaseSuccessors(&EntrySU); - // Add all leaves to Available queue. If ignoring antideps we also - // adjust the predecessor count for each node to not include antidep - // edges. + // Add all leaves to Available queue. for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { // It is available if it has no predecessors. bool available = SUnits[i].Preds.empty(); - // If we are ignoring anti-dependencies then a node that has only - // anti-dep predecessors is available. - if (!available && IgnoreAntiDep) { - available = true; - for (SUnit::const_pred_iterator I = SUnits[i].Preds.begin(), - E = SUnits[i].Preds.end(); I != E; ++I) { - if ((I->getKind() != SDep::Anti) && (I->getKind() != SDep::Output)) { - available = false; - } else { - SUnits[i].NumPredsLeft -= 1; - } - } - } - if (available) { AvailableQueue.push(&SUnits[i]); SUnits[i].isAvailable = true; @@ -687,21 +632,21 @@ // so, add them to the available queue. unsigned MinDepth = ~0u; for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) { - if (PendingQueue[i]->getDepth(IgnoreAntiDep) <= CurCycle) { + if (PendingQueue[i]->getDepth() <= CurCycle) { AvailableQueue.push(PendingQueue[i]); PendingQueue[i]->isAvailable = true; PendingQueue[i] = PendingQueue.back(); PendingQueue.pop_back(); --i; --e; - } else if (PendingQueue[i]->getDepth(IgnoreAntiDep) < MinDepth) - MinDepth = PendingQueue[i]->getDepth(IgnoreAntiDep); + } else if (PendingQueue[i]->getDepth() < MinDepth) + MinDepth = PendingQueue[i]->getDepth(); } DEBUG(errs() << "\n*** Examining Available\n"; LatencyPriorityQueue q = AvailableQueue; while (!q.empty()) { SUnit *su = q.pop(); - errs() << "Height " << su->getHeight(IgnoreAntiDep) << ": "; + errs() << "Height " << su->getHeight() << ": "; su->dump(this); }); @@ -731,30 +676,8 @@ // If we found a node to schedule... if (FoundSUnit) { - // If we are ignoring anti-dependencies and the SUnit we are - // scheduling has an antidep predecessor that has not been - // scheduled, then we will need to break that antidep if we want - // to get this schedule when not ignoring anti-dependencies. - if (IgnoreAntiDep) { - AntiDepBreaker::AntiDepRegVector AntiDepRegs; - for (SUnit::const_pred_iterator I = FoundSUnit->Preds.begin(), - E = FoundSUnit->Preds.end(); I != E; ++I) { - if (((I->getKind() == SDep::Anti) || - (I->getKind() == SDep::Output)) && - !I->getSUnit()->isScheduled) - AntiDepRegs.push_back(I->getReg()); - } - - if (AntiDepRegs.size() > 0) { - DEBUG(errs() << "*** AntiDep Candidate: "); - DEBUG(FoundSUnit->dump(this)); - AntiDepCandidates->insert( - AntiDepBreaker::CandidateMap::value_type(FoundSUnit, AntiDepRegs)); - } - } - // ... schedule the node... - ScheduleNodeTopDown(FoundSUnit, CurCycle, IgnoreAntiDep); + ScheduleNodeTopDown(FoundSUnit, CurCycle); HazardRec->EmitInstruction(FoundSUnit); CycleHasInsts = true; @@ -775,8 +698,7 @@ // just advance the current cycle and try again. DEBUG(errs() << "*** Stall in cycle " << CurCycle << '\n'); HazardRec->AdvanceCycle(); - if (!IgnoreAntiDep) - ++NumStalls; + ++NumStalls; } else { // Otherwise, we have no instructions to issue and we have instructions // that will fault if we don't do this right. This is the case for @@ -784,8 +706,7 @@ DEBUG(errs() << "*** Emitting noop in cycle " << CurCycle << '\n'); HazardRec->EmitNoop(); Sequence.push_back(0); // NULL here means noop - if (!IgnoreAntiDep) - ++NumNoops; + ++NumNoops; } ++CurCycle; Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp?rev=89471&r1=89470&r2=89471&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Fri Nov 20 13:32:48 2009 @@ -183,8 +183,8 @@ /// setDepthToAtLeast - Update this node's successors to reflect the /// fact that this node's depth just increased. /// -void SUnit::setDepthToAtLeast(unsigned NewDepth, bool IgnoreAntiDep) { - if (NewDepth <= getDepth(IgnoreAntiDep)) +void SUnit::setDepthToAtLeast(unsigned NewDepth) { + if (NewDepth <= getDepth()) return; setDepthDirty(); Depth = NewDepth; @@ -194,8 +194,8 @@ /// setHeightToAtLeast - Update this node's predecessors to reflect the /// fact that this node's height just increased. /// -void SUnit::setHeightToAtLeast(unsigned NewHeight, bool IgnoreAntiDep) { - if (NewHeight <= getHeight(IgnoreAntiDep)) +void SUnit::setHeightToAtLeast(unsigned NewHeight) { + if (NewHeight <= getHeight()) return; setHeightDirty(); Height = NewHeight; @@ -204,7 +204,7 @@ /// ComputeDepth - Calculate the maximal path from the node to the exit. /// -void SUnit::ComputeDepth(bool IgnoreAntiDep) { +void SUnit::ComputeDepth() { SmallVector WorkList; WorkList.push_back(this); do { @@ -214,10 +214,6 @@ unsigned MaxPredDepth = 0; for (SUnit::const_pred_iterator I = Cur->Preds.begin(), E = Cur->Preds.end(); I != E; ++I) { - if (IgnoreAntiDep && - ((I->getKind() == SDep::Anti) || (I->getKind() == SDep::Output))) - continue; - SUnit *PredSU = I->getSUnit(); if (PredSU->isDepthCurrent) MaxPredDepth = std::max(MaxPredDepth, @@ -241,7 +237,7 @@ /// ComputeHeight - Calculate the maximal path from the node to the entry. /// -void SUnit::ComputeHeight(bool IgnoreAntiDep) { +void SUnit::ComputeHeight() { SmallVector WorkList; WorkList.push_back(this); do { @@ -251,10 +247,6 @@ unsigned MaxSuccHeight = 0; for (SUnit::const_succ_iterator I = Cur->Succs.begin(), E = Cur->Succs.end(); I != E; ++I) { - if (IgnoreAntiDep && - ((I->getKind() == SDep::Anti) || (I->getKind() == SDep::Output))) - continue; - SUnit *SuccSU = I->getSUnit(); if (SuccSU->isHeightCurrent) MaxSuccHeight = std::max(MaxSuccHeight, From gohman at apple.com Fri Nov 20 13:32:51 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 11:32:51 -0800 Subject: [llvm-commits] [llvm] r89398 - in /llvm/trunk: include/llvm/Analysis/CaptureTracking.h lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/CaptureTracking.cpp lib/Transforms/IPO/FunctionAttrs.cpp test/Transforms/GVN/nonescaping-malloc.ll In-Reply-To: <4B064224.3040404@mxc.ca> References: <200911192157.nAJLvmkD020251@zion.cs.uiuc.edu> <4B064224.3040404@mxc.ca> Message-ID: <326CEB09-B8FF-4353-8C09-4C430A8FFFB2@apple.com> On Nov 19, 2009, at 11:15 PM, Nick Lewycky wrote: > Dan Gohman wrote: >> Author: djg >> Date: Thu Nov 19 15:57:48 2009 >> New Revision: 89398 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=89398&view=rev >> Log: >> Extend CaptureTracking to indicate when a value is never stored, even >> if it is not ultimately captured. Teach BasicAliasAnalysis that a >> local object address which does not escape and is never stored does >> not alias with a value resulting from a load. >> >> Added: >> llvm/trunk/test/Transforms/GVN/nonescaping-malloc.ll >> Modified: >> llvm/trunk/include/llvm/Analysis/CaptureTracking.h >> llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp >> llvm/trunk/lib/Analysis/CaptureTracking.cpp >> llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp >> >> Modified: llvm/trunk/include/llvm/Analysis/CaptureTracking.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CaptureTracking.h?rev=89398&r1=89397&r2=89398&view=diff >> >> ============================================================================== >> --- llvm/trunk/include/llvm/Analysis/CaptureTracking.h (original) >> +++ llvm/trunk/include/llvm/Analysis/CaptureTracking.h Thu Nov 19 15:57:48 2009 >> @@ -21,8 +21,12 @@ >> /// by the enclosing function (which is required to exist). This routine can >> /// be expensive, so consider caching the results. The boolean ReturnCaptures >> /// specifies whether returning the value (or part of it) from the function >> + /// counts as capturing it or not. The boolean StoreCaptures specified whether >> + /// storing the value (or part of it) into memory anywhere automatically >> /// counts as capturing it or not. >> - bool PointerMayBeCaptured(const Value *V, bool ReturnCaptures); >> + bool PointerMayBeCaptured(const Value *V, >> + bool ReturnCaptures, >> + bool StoreCaptures); > > I completely do not understand this. The fact that store implies capture has always been a missed opportunity; if it stores to something that never escapes, and the loads of it never escape, then it's not captured. (Note that you need to track 'pointer depth' as %p is stored into %q is stored into %r, etc.) > > Duncan (IIRC) actually implemented this behaviour early on and we removed it because it was likely to be slow and didn't seem to provide any performance benefit at the time. > > In any event, either I'm misunderstanding what you're doing here, or it doesn't belong in the API. I didn't put any logic in PointerMayBeCaptured to implement the !StoreCaptures case, so currently the flag doesn't do anything. But, I did put code in BasicAA which benefits from being able to assume that a locally allocated object address which never escapes is never in memory, and thus is never the result of a load. I added the flag to PointerMayBeCaptured in order to allow BasicAA to make its assumption explicit. For an example of what I was thinking about, see the testcase: test/Transforms/GVN/nonescaping-malloc.ll Dan From gohman at apple.com Fri Nov 20 13:33:17 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 19:33:17 -0000 Subject: [llvm-commits] [llvm] r89472 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp Message-ID: <200911201933.nAKJXHBi016251@zion.cs.uiuc.edu> Author: djg Date: Fri Nov 20 13:33:16 2009 New Revision: 89472 URL: http://llvm.org/viewvc/llvm-project?rev=89472&view=rev Log: Use stripPointerCasts(). Thanks Duncan! Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CaptureTracking.cpp?rev=89472&r1=89471&r2=89472&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CaptureTracking.cpp (original) +++ llvm/trunk/lib/Analysis/CaptureTracking.cpp Fri Nov 20 13:33:16 2009 @@ -109,7 +109,7 @@ // Don't count comparisons of a no-alias return value against null as // captures. This allows us to ignore comparisons of malloc results // with null, for example. - if (isNoAliasCall(V)) + if (isNoAliasCall(V->stripPointerCasts())) if (ConstantPointerNull *CPN = dyn_cast(I->getOperand(1))) if (CPN->getType()->getAddressSpace() == 0) From grosbach at apple.com Fri Nov 20 13:37:38 2009 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 20 Nov 2009 19:37:38 -0000 Subject: [llvm-commits] [llvm] r89473 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Message-ID: <200911201937.nAKJbc1Z016608@zion.cs.uiuc.edu> Author: grosbach Date: Fri Nov 20 13:37:38 2009 New Revision: 89473 URL: http://llvm.org/viewvc/llvm-project?rev=89473&view=rev Log: The verify() call of CPEIsInRange() isn't right for the assertion check of constant pool ranges, as CPEIsInRange() makes conservative assumptions about the potential alignment changes from branch adjustments. The verification, on the other hand, runs after those branch adjustments are made, so the effects on alignment are known and already taken into account. The sanity check in verify should check the range directly instead. Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=89473&r1=89472&r2=89473&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Fri Nov 20 13:37:38 2009 @@ -244,12 +244,15 @@ (BBOffsets[MBBId]%4 != 0 && BBSizes[MBBId]%4 != 0)); } } -#endif for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) { CPUser &U = CPUsers[i]; unsigned UserOffset = GetOffsetOf(U.MI) + (isThumb ? 4 : 8); - assert (CPEIsInRange(U.MI, UserOffset, U.CPEMI, U.MaxDisp, U.NegOk, true)); + unsigned CPEOffset = GetOffsetOf(U.CPEMI); + unsigned Disp = UserOffset < CPEOffset ? CPEOffset - UserOffset : + UserOffset - CPEOffset; + assert(Disp <= U.MaxDisp || "Constant pool entry out of range!"); } +#endif } /// print block size and offset information - debugging From evan.cheng at apple.com Fri Nov 20 13:55:38 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 20 Nov 2009 19:55:38 -0000 Subject: [llvm-commits] [llvm] r89477 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp Message-ID: <200911201955.nAKJtcbQ017677@zion.cs.uiuc.edu> Author: evancheng Date: Fri Nov 20 13:55:37 2009 New Revision: 89477 URL: http://llvm.org/viewvc/llvm-project?rev=89477&view=rev Log: Add option -licm-const-load to hoist all loads from constant memory. Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=89477&r1=89476&r2=89477&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Fri Nov 20 13:55:37 2009 @@ -34,11 +34,16 @@ #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/Statistic.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; +static cl::opt HoistLdConst("licm-const-load", + cl::desc("LICM load from constant memory"), + cl::init(false), cl::Hidden); + STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops"); STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed"); @@ -97,7 +102,7 @@ /// IsProfitableToHoist - Return true if it is potentially profitable to /// hoist the given loop invariant. - bool IsProfitableToHoist(MachineInstr &MI); + bool IsProfitableToHoist(MachineInstr &MI, bool &isConstLd); /// HoistRegion - Walk the specified region of the CFG (defined by all /// blocks dominated by the specified block, and that are in the current @@ -107,6 +112,10 @@ /// void HoistRegion(MachineDomTreeNode *N); + /// isLoadFromConstantMemory - Return true if the given instruction is a + /// load from constant memory. + bool isLoadFromConstantMemory(MachineInstr *MI); + /// ExtractHoistableLoad - Unfold a load from the given machineinstr if /// the load itself could be hoisted. Return the unfolded and hoistable /// load, or null if the load couldn't be unfolded or if it wouldn't @@ -338,17 +347,45 @@ return false; } +/// isLoadFromConstantMemory - Return true if the given instruction is a +/// load from constant memory. Machine LICM will hoist these even if they are +/// not re-materializable. +bool MachineLICM::isLoadFromConstantMemory(MachineInstr *MI) { + if (!MI->getDesc().mayLoad()) return false; + if (!MI->hasOneMemOperand()) return false; + MachineMemOperand *MMO = *MI->memoperands_begin(); + if (MMO->isVolatile()) return false; + if (!MMO->getValue()) return false; + const PseudoSourceValue *PSV = dyn_cast(MMO->getValue()); + if (PSV) { + MachineFunction &MF = *MI->getParent()->getParent(); + return PSV->isConstant(MF.getFrameInfo()); + } else { + return AA->pointsToConstantMemory(MMO->getValue()); + } +} + /// IsProfitableToHoist - Return true if it is potentially profitable to hoist /// the given loop invariant. -bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) { +bool MachineLICM::IsProfitableToHoist(MachineInstr &MI, bool &isConstLd) { + isConstLd = false; + if (MI.getOpcode() == TargetInstrInfo::IMPLICIT_DEF) return false; // FIXME: For now, only hoist re-materilizable instructions. LICM will // increase register pressure. We want to make sure it doesn't increase // spilling. - if (!TII->isTriviallyReMaterializable(&MI, AA)) - return false; + // Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting + // these tend to help performance in low register pressure situation. The + // trade off is it may cause spill in high pressure situation. It will end up + // adding a store in the loop preheader. But the reload is no more expensive. + // The side benefit is these loads are frequently CSE'ed. + if (!TII->isTriviallyReMaterializable(&MI, AA)) { + if (!HoistLdConst || !isLoadFromConstantMemory(&MI)) + return false; + isConstLd = true; + } // If result(s) of this instruction is used by PHIs, then don't hoist it. // The presence of joins makes it difficult for current register allocator @@ -368,18 +405,9 @@ // If not, we may be able to unfold a load and hoist that. // First test whether the instruction is loading from an amenable // memory location. - if (!MI->getDesc().mayLoad()) return 0; - if (!MI->hasOneMemOperand()) return 0; - MachineMemOperand *MMO = *MI->memoperands_begin(); - if (MMO->isVolatile()) return 0; - MachineFunction &MF = *MI->getParent()->getParent(); - if (!MMO->getValue()) return 0; - if (const PseudoSourceValue *PSV = - dyn_cast(MMO->getValue())) { - if (!PSV->isConstant(MF.getFrameInfo())) return 0; - } else { - if (!AA->pointsToConstantMemory(MMO->getValue())) return 0; - } + if (!isLoadFromConstantMemory(MI)) + return 0; + // Next determine the register class for a temporary register. unsigned LoadRegIndex; unsigned NewOpc = @@ -393,6 +421,8 @@ const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI); // Ok, we're unfolding. Create a temporary register and do the unfold. unsigned Reg = RegInfo->createVirtualRegister(RC); + + MachineFunction &MF = *MI->getParent()->getParent(); SmallVector NewMIs; bool Success = TII->unfoldMemoryOperand(MF, MI, Reg, @@ -409,7 +439,9 @@ MBB->insert(MI, NewMIs[1]); // If unfolding produced a load that wasn't loop-invariant or profitable to // hoist, discard the new instructions and bail. - if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) { + bool isConstLd; + if (!IsLoopInvariantInst(*NewMIs[0]) || + !IsProfitableToHoist(*NewMIs[0], isConstLd)) { NewMIs[0]->eraseFromParent(); NewMIs[1]->eraseFromParent(); return 0; @@ -475,7 +507,9 @@ /// void MachineLICM::Hoist(MachineInstr *MI) { // First check whether we should hoist this instruction. - if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) { + bool isConstLd; + if (!IsLoopInvariantInst(*MI) || + !IsProfitableToHoist(*MI, isConstLd)) { // If not, try unfolding a hoistable load. MI = ExtractHoistableLoad(MI); if (!MI) return; @@ -484,7 +518,10 @@ // Now move the instructions to the predecessor, inserting it before any // terminator instructions. DEBUG({ - errs() << "Hoisting " << *MI; + errs() << "Hoisting "; + if (isConstLd) + errs() << "load from constant mem "; + errs() << *MI; if (CurPreheader->getBasicBlock()) errs() << " to MachineBasicBlock " << CurPreheader->getName(); From evan.cheng at apple.com Fri Nov 20 13:57:15 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 20 Nov 2009 19:57:15 -0000 Subject: [llvm-commits] [llvm] r89478 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMInstrVFP.td test/CodeGen/ARM/remat-2.ll test/CodeGen/Thumb2/cross-rc-coalescing-2.ll test/CodeGen/Thumb2/ldr-str-imm12.ll Message-ID: <200911201957.nAKJvGqr017773@zion.cs.uiuc.edu> Author: evancheng Date: Fri Nov 20 13:57:15 2009 New Revision: 89478 URL: http://llvm.org/viewvc/llvm-project?rev=89478&view=rev Log: Remat VLDRD from constpool. Clean up some instruction property specifications. Added: llvm/trunk/test/CodeGen/ARM/remat-2.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/ARMInstrVFP.td llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=89478&r1=89477&r2=89478&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Nov 20 13:57:15 2009 @@ -581,7 +581,6 @@ [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; let AddedComplexity = 10 in { -let canFoldAsLoad = 1 in def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr", [(set GPR:$dst, (load addrmodepc:$addr))]>; @@ -801,13 +800,14 @@ // // Load -let canFoldAsLoad = 1, isReMaterializable = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr, "ldr", "\t$dst, $addr", [(set GPR:$dst, (load addrmode2:$addr))]>; // Special LDR for loads from non-pc-relative constpools. -let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in +let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, + mayHaveSideEffects = 1 in def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr, "ldr", "\t$dst, $addr", []>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=89478&r1=89477&r2=89478&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Nov 20 13:57:15 2009 @@ -296,7 +296,7 @@ // Load Store Instructions. // -let canFoldAsLoad = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr, "ldr", "\t$dst, $addr", [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>; @@ -332,13 +332,14 @@ // Load tconstpool // FIXME: Use ldr.n to work around a Darwin assembler bug. -let canFoldAsLoad = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi, "ldr", ".n\t$dst, $addr", [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>; // Special LDR for loads from non-pc-relative constpools. -let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in +let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, + mayHaveSideEffects = 1 in def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi, "ldr", "\t$dst, $addr", []>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=89478&r1=89477&r2=89478&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Nov 20 13:57:15 2009 @@ -471,7 +471,7 @@ // // Load -let canFoldAsLoad = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>; // Loads with zero extension @@ -1183,7 +1183,7 @@ // Pseudo instruction that combines ldr from constpool and add pc. This should // be expanded into two instructions late to allow if-conversion and // scheduling. -let isReMaterializable = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), NoItinerary, "@ ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc", [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=89478&r1=89477&r2=89478&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Fri Nov 20 13:57:15 2009 @@ -54,7 +54,7 @@ // Load / store Instructions. // -let canFoldAsLoad = 1 in { +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr), IIC_fpLoad64, "vldr", ".64\t$dst, $addr", [(set DPR:$dst, (load addrmode5:$addr))]>; Added: llvm/trunk/test/CodeGen/ARM/remat-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/remat-2.ll?rev=89478&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/remat-2.ll (added) +++ llvm/trunk/test/CodeGen/ARM/remat-2.ll Fri Nov 20 13:57:15 2009 @@ -0,0 +1,65 @@ +; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -stats -info-output-file - | grep "Number of re-materialization" + +define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +entry: + br i1 undef, label %smvp.exit, label %bb.i3 + +bb.i3: ; preds = %bb.i3, %bb134 + br i1 undef, label %smvp.exit, label %bb.i3 + +smvp.exit: ; preds = %bb.i3 + %0 = fmul double undef, 2.400000e-03 ; [#uses=2] + br i1 undef, label %bb138.preheader, label %bb159 + +bb138.preheader: ; preds = %smvp.exit + br label %bb138 + +bb138: ; preds = %bb138, %bb138.preheader + br i1 undef, label %bb138, label %bb145.loopexit + +bb142: ; preds = %bb.nph218.bb.nph218.split_crit_edge, %phi0.exit + %1 = fmul double undef, -1.200000e-03 ; [#uses=1] + %2 = fadd double undef, %1 ; [#uses=1] + %3 = fmul double %2, undef ; [#uses=1] + %4 = fsub double 0.000000e+00, %3 ; [#uses=1] + br i1 %14, label %phi1.exit, label %bb.i35 + +bb.i35: ; preds = %bb142 + %5 = call arm_apcscc double @sin(double %15) nounwind readonly ; [#uses=1] + %6 = fmul double %5, 0x4031740AFA84AD8A ; [#uses=1] + %7 = fsub double 1.000000e+00, undef ; [#uses=1] + %8 = fdiv double %7, 6.000000e-01 ; [#uses=1] + br label %phi1.exit + +phi1.exit: ; preds = %bb.i35, %bb142 + %.pn = phi double [ %6, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; [#uses=0] + %9 = phi double [ %8, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; [#uses=1] + %10 = fmul double undef, %9 ; [#uses=0] + br i1 %14, label %phi0.exit, label %bb.i + +bb.i: ; preds = %phi1.exit + unreachable + +phi0.exit: ; preds = %phi1.exit + %11 = fsub double %4, undef ; [#uses=1] + %12 = fadd double 0.000000e+00, %11 ; [#uses=1] + store double %12, double* undef, align 4 + br label %bb142 + +bb145.loopexit: ; preds = %bb138 + br i1 undef, label %bb.nph218.bb.nph218.split_crit_edge, label %bb159 + +bb.nph218.bb.nph218.split_crit_edge: ; preds = %bb145.loopexit + %13 = fmul double %0, 0x401921FB54442D18 ; [#uses=1] + %14 = fcmp ugt double %0, 6.000000e-01 ; [#uses=2] + %15 = fdiv double %13, 6.000000e-01 ; [#uses=1] + br label %bb142 + +bb159: ; preds = %bb145.loopexit, %smvp.exit, %bb134 + unreachable + +bb166: ; preds = %bb127 + unreachable +} + +declare arm_apcscc double @sin(double) nounwind readonly Modified: llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll?rev=89478&r1=89477&r2=89478&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll Fri Nov 20 13:57:15 2009 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 4 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 6 define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll?rev=89478&r1=89477&r2=89478&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll Fri Nov 20 13:57:15 2009 @@ -22,8 +22,7 @@ define arm_apcscc %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind { entry: -; CHECK: ldr.w r9, [r7, #+32] -; CHECK-NEXT : str.w r9, [sp, #+28] +; CHECK: ldr.w r9, [r7, #+28] %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] %ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] br i1 false, label %bb, label %bb20 @@ -53,7 +52,6 @@ ; CHECK: str r{{[0-7]}}, [sp] ; CHECK: str r{{[0-7]}}, [sp, #+4] ; CHECK: str r{{[0-7]}}, [sp, #+8] -; CHECK: ldr r{{[0-7]}}, [sp, #+28] ; CHECK: str r{{[0-7]}}, [sp, #+24] store %union.rec* null, %union.rec** @zz_hold, align 4 store %union.rec* null, %union.rec** @zz_res, align 4 From echristo at apple.com Fri Nov 20 13:57:38 2009 From: echristo at apple.com (Eric Christopher) Date: Fri, 20 Nov 2009 19:57:38 -0000 Subject: [llvm-commits] [llvm] r89479 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Message-ID: <200911201957.nAKJvcR4017793@zion.cs.uiuc.edu> Author: echristo Date: Fri Nov 20 13:57:37 2009 New Revision: 89479 URL: http://llvm.org/viewvc/llvm-project?rev=89479&view=rev Log: Add some rough optimizations for checking routines. Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=89479&r1=89478&r2=89479&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Fri Nov 20 13:57:37 2009 @@ -81,6 +81,9 @@ Value *EmitMemCpy(Value *Dst, Value *Src, Value *Len, unsigned Align, IRBuilder<> &B); + Value *EmitMemMove(Value *Dst, Value *Src, Value *Len, + unsigned Align, IRBuilder<> &B); + /// EmitMemChr - Emit a call to the memchr function. This assumes that Ptr is /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. Value *EmitMemChr(Value *Ptr, Value *Val, Value *Len, IRBuilder<> &B); @@ -160,6 +163,22 @@ ConstantInt::get(Type::getInt32Ty(*Context), Align)); } +/// EmitMemMOve - Emit a call to the memmove function to the builder. This +/// always expects that the size has type 'intptr_t' and Dst/Src are pointers. +Value *LibCallOptimization::EmitMemMove(Value *Dst, Value *Src, Value *Len, + unsigned Align, IRBuilder<> &B) { + Module *M = Caller->getParent(); + Intrinsic::ID IID = Intrinsic::memmove; + const Type *Tys[1]; + Tys[0] = TD->getIntPtrType(*Context); + Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); + Value *Dst = CastToCStr(CI->getOperand(1), B); + Value *Src = CastToCStr(CI->getOperand(2), B); + Value *Size = CI->getOperand(3); + Value *Align = ConstantInt::get(Type::getInt32Ty(*Context), 1); + return B.CreateCall4(MemMove, Dst, Src, Size, Align); +} + /// EmitMemChr - Emit a call to the memchr function. This assumes that Ptr is /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. Value *LibCallOptimization::EmitMemChr(Value *Ptr, Value *Val, @@ -1010,16 +1029,7 @@ return 0; // memmove(x, y, n) -> llvm.memmove(x, y, n, 1) - Module *M = Caller->getParent(); - Intrinsic::ID IID = Intrinsic::memmove; - const Type *Tys[1]; - Tys[0] = TD->getIntPtrType(*Context); - Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); - Value *Dst = CastToCStr(CI->getOperand(1), B); - Value *Src = CastToCStr(CI->getOperand(2), B); - Value *Size = CI->getOperand(3); - Value *Align = ConstantInt::get(Type::getInt32Ty(*Context), 1); - B.CreateCall4(MemMove, Dst, Src, Size, Align); + EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3), 1, B); return CI->getOperand(1); } }; @@ -1048,6 +1058,96 @@ }; //===----------------------------------------------------------------------===// +// Object Size Checking Optimizations +//===----------------------------------------------------------------------===// +//===---------------------------------------===// +// 'memcpy_chk' Optimizations + +struct MemCpyChkOpt : public LibCallOptimization { + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { + // These optimizations require TargetData. + if (!TD) return 0; + + const FunctionType *FT = Callee->getFunctionType(); + if (FT->getNumParams() != 4 || FT->getReturnType() != FT->getParamType(0) || + !isa(FT->getParamType(0)) || + !isa(FT->getParamType(1)) || + !isa(FT->getParamType(3)) || + FT->getParamType(2) != TD->getIntPtrType(*Context)) + return 0; + + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); + if (!SizeCI) + return 0; + if (SizeCI->isAllOnesValue()) { + EmitMemCpy(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3), 1, B); + return CI->getOperand(1); + } + + return 0; + } +}; + +//===---------------------------------------===// +// 'memset_chk' Optimizations + +struct MemSetChkOpt : public LibCallOptimization { + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { + // These optimizations require TargetData. + if (!TD) return 0; + + const FunctionType *FT = Callee->getFunctionType(); + if (FT->getNumParams() != 4 || FT->getReturnType() != FT->getParamType(0) || + !isa(FT->getParamType(0)) || + !isa(FT->getParamType(1)) || + !isa(FT->getParamType(3)) || + FT->getParamType(2) != TD->getIntPtrType(*Context)) + return 0; + + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); + if (!SizeCI) + return 0; + if (SizeCI->isAllOnesValue()) { + Value *Val = B.CreateIntCast(CI->getOperand(2), Type::getInt8Ty(*Context), + false); + EmitMemSet(CI->getOperand(1), Val, CI->getOperand(3), B); + return CI->getOperand(1); + } + + return 0; + } +}; + +//===---------------------------------------===// +// 'memmove_chk' Optimizations + +struct MemMoveChkOpt : public LibCallOptimization { + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { + // These optimizations require TargetData. + if (!TD) return 0; + + const FunctionType *FT = Callee->getFunctionType(); + if (FT->getNumParams() != 4 || FT->getReturnType() != FT->getParamType(0) || + !isa(FT->getParamType(0)) || + !isa(FT->getParamType(1)) || + !isa(FT->getParamType(3)) || + FT->getParamType(2) != TD->getIntPtrType(*Context)) + return 0; + + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); + if (!SizeCI) + return 0; + if (SizeCI->isAllOnesValue()) { + EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3), + 1, B); + return CI->getOperand(1); + } + + return 0; + } +}; + +//===----------------------------------------------------------------------===// // Math Library Optimizations //===----------------------------------------------------------------------===// @@ -1586,7 +1686,10 @@ // Formatting and IO Optimizations SPrintFOpt SPrintF; PrintFOpt PrintF; FWriteOpt FWrite; FPutsOpt FPuts; FPrintFOpt FPrintF; + + // Object Size Checking SizeOpt ObjectSize; + MemCpyChkOpt MemCpyChk; MemSetChkOpt MemSetChk; MemMoveChkOpt MemMoveChk; bool Modified; // This is only used by doInitialization. public: @@ -1693,8 +1796,12 @@ Optimizations["fputs"] = &FPuts; Optimizations["fprintf"] = &FPrintF; - // Miscellaneous - Optimizations["llvm.objectsize"] = &ObjectSize; + // Object Size Checking + Optimizations["llvm.objectsize.i32"] = &ObjectSize; + Optimizations["llvm.objectsize.i64"] = &ObjectSize; + Optimizations["__memcpy_chk"] = &MemCpyChk; + Optimizations["__memset_chk"] = &MemSetChk; + Optimizations["__memmove_chk"] = &MemMoveChk; } From evan.cheng at apple.com Fri Nov 20 14:06:37 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 20 Nov 2009 12:06:37 -0800 Subject: [llvm-commits] [llvm] r89479 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: <200911201957.nAKJvcR4017793@zion.cs.uiuc.edu> References: <200911201957.nAKJvcR4017793@zion.cs.uiuc.edu> Message-ID: <728B5ADD-7F00-4178-AF90-EB228254A160@apple.com> This breaks the build? /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/Transforms/Scalar/SimplifyLibCalls.cpp: In member function 'llvm::Value*::LibCallOptimization::EmitMemMove(llvm::Value*,\ llvm::Value*, llvm::Value*, unsigned int, llvm::IRBuilder >&)': /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/Transforms/Scalar/SimplifyLibCalls.cpp:175: error: declaration of 'llvm::Value* Dst' shadows a parameter /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/Transforms/Scalar/SimplifyLibCalls.cpp:175: error: 'CI' was not declared in this scope /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/Transforms/Scalar/SimplifyLibCalls.cpp:176: error: declaration of 'llvm::Value* Src' shadows a parameter /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/Transforms/Scalar/SimplifyLibCalls.cpp:178: error: declaration of 'llvm::Value* Align' shadows a parameter Evan On Nov 20, 2009, at 11:57 AM, Eric Christopher wrote: > Author: echristo > Date: Fri Nov 20 13:57:37 2009 > New Revision: 89479 > > URL: http://llvm.org/viewvc/llvm-project?rev=89479&view=rev > Log: > Add some rough optimizations for checking routines. > > Modified: > llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp > > Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=89479&r1=89478&r2=89479&view=diff > > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Fri Nov 20 13:57:37 2009 > @@ -81,6 +81,9 @@ > Value *EmitMemCpy(Value *Dst, Value *Src, Value *Len, > unsigned Align, IRBuilder<> &B); > > + Value *EmitMemMove(Value *Dst, Value *Src, Value *Len, > + unsigned Align, IRBuilder<> &B); > + > /// EmitMemChr - Emit a call to the memchr function. This assumes that Ptr is > /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. > Value *EmitMemChr(Value *Ptr, Value *Val, Value *Len, IRBuilder<> &B); > @@ -160,6 +163,22 @@ > ConstantInt::get(Type::getInt32Ty(*Context), Align)); > } > > +/// EmitMemMOve - Emit a call to the memmove function to the builder. This > +/// always expects that the size has type 'intptr_t' and Dst/Src are pointers. > +Value *LibCallOptimization::EmitMemMove(Value *Dst, Value *Src, Value *Len, > + unsigned Align, IRBuilder<> &B) { > + Module *M = Caller->getParent(); > + Intrinsic::ID IID = Intrinsic::memmove; > + const Type *Tys[1]; > + Tys[0] = TD->getIntPtrType(*Context); > + Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); > + Value *Dst = CastToCStr(CI->getOperand(1), B); > + Value *Src = CastToCStr(CI->getOperand(2), B); > + Value *Size = CI->getOperand(3); > + Value *Align = ConstantInt::get(Type::getInt32Ty(*Context), 1); > + return B.CreateCall4(MemMove, Dst, Src, Size, Align); > +} > + > /// EmitMemChr - Emit a call to the memchr function. This assumes that Ptr is > /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. > Value *LibCallOptimization::EmitMemChr(Value *Ptr, Value *Val, > @@ -1010,16 +1029,7 @@ > return 0; > > // memmove(x, y, n) -> llvm.memmove(x, y, n, 1) > - Module *M = Caller->getParent(); > - Intrinsic::ID IID = Intrinsic::memmove; > - const Type *Tys[1]; > - Tys[0] = TD->getIntPtrType(*Context); > - Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); > - Value *Dst = CastToCStr(CI->getOperand(1), B); > - Value *Src = CastToCStr(CI->getOperand(2), B); > - Value *Size = CI->getOperand(3); > - Value *Align = ConstantInt::get(Type::getInt32Ty(*Context), 1); > - B.CreateCall4(MemMove, Dst, Src, Size, Align); > + EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3), 1, B); > return CI->getOperand(1); > } > }; > @@ -1048,6 +1058,96 @@ > }; > > //===----------------------------------------------------------------------===// > +// Object Size Checking Optimizations > +//===----------------------------------------------------------------------===// > +//===---------------------------------------===// > +// 'memcpy_chk' Optimizations > + > +struct MemCpyChkOpt : public LibCallOptimization { > + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { > + // These optimizations require TargetData. > + if (!TD) return 0; > + > + const FunctionType *FT = Callee->getFunctionType(); > + if (FT->getNumParams() != 4 || FT->getReturnType() != FT->getParamType(0) || > + !isa(FT->getParamType(0)) || > + !isa(FT->getParamType(1)) || > + !isa(FT->getParamType(3)) || > + FT->getParamType(2) != TD->getIntPtrType(*Context)) > + return 0; > + > + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); > + if (!SizeCI) > + return 0; > + if (SizeCI->isAllOnesValue()) { > + EmitMemCpy(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3), 1, B); > + return CI->getOperand(1); > + } > + > + return 0; > + } > +}; > + > +//===---------------------------------------===// > +// 'memset_chk' Optimizations > + > +struct MemSetChkOpt : public LibCallOptimization { > + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { > + // These optimizations require TargetData. > + if (!TD) return 0; > + > + const FunctionType *FT = Callee->getFunctionType(); > + if (FT->getNumParams() != 4 || FT->getReturnType() != FT->getParamType(0) || > + !isa(FT->getParamType(0)) || > + !isa(FT->getParamType(1)) || > + !isa(FT->getParamType(3)) || > + FT->getParamType(2) != TD->getIntPtrType(*Context)) > + return 0; > + > + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); > + if (!SizeCI) > + return 0; > + if (SizeCI->isAllOnesValue()) { > + Value *Val = B.CreateIntCast(CI->getOperand(2), Type::getInt8Ty(*Context), > + false); > + EmitMemSet(CI->getOperand(1), Val, CI->getOperand(3), B); > + return CI->getOperand(1); > + } > + > + return 0; > + } > +}; > + > +//===---------------------------------------===// > +// 'memmove_chk' Optimizations > + > +struct MemMoveChkOpt : public LibCallOptimization { > + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { > + // These optimizations require TargetData. > + if (!TD) return 0; > + > + const FunctionType *FT = Callee->getFunctionType(); > + if (FT->getNumParams() != 4 || FT->getReturnType() != FT->getParamType(0) || > + !isa(FT->getParamType(0)) || > + !isa(FT->getParamType(1)) || > + !isa(FT->getParamType(3)) || > + FT->getParamType(2) != TD->getIntPtrType(*Context)) > + return 0; > + > + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); > + if (!SizeCI) > + return 0; > + if (SizeCI->isAllOnesValue()) { > + EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3), > + 1, B); > + return CI->getOperand(1); > + } > + > + return 0; > + } > +}; > + > +//===----------------------------------------------------------------------===// > // Math Library Optimizations > //===----------------------------------------------------------------------===// > > @@ -1586,7 +1686,10 @@ > // Formatting and IO Optimizations > SPrintFOpt SPrintF; PrintFOpt PrintF; > FWriteOpt FWrite; FPutsOpt FPuts; FPrintFOpt FPrintF; > + > + // Object Size Checking > SizeOpt ObjectSize; > + MemCpyChkOpt MemCpyChk; MemSetChkOpt MemSetChk; MemMoveChkOpt MemMoveChk; > > bool Modified; // This is only used by doInitialization. > public: > @@ -1693,8 +1796,12 @@ > Optimizations["fputs"] = &FPuts; > Optimizations["fprintf"] = &FPrintF; > > - // Miscellaneous > - Optimizations["llvm.objectsize"] = &ObjectSize; > + // Object Size Checking > + Optimizations["llvm.objectsize.i32"] = &ObjectSize; > + Optimizations["llvm.objectsize.i64"] = &ObjectSize; > + Optimizations["__memcpy_chk"] = &MemCpyChk; > + Optimizations["__memset_chk"] = &MemSetChk; > + Optimizations["__memmove_chk"] = &MemMoveChk; > } > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From daniel at zuster.org Fri Nov 20 14:17:30 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 20 Nov 2009 20:17:30 -0000 Subject: [llvm-commits] [llvm] r89482 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Message-ID: <200911202017.nAKKHU5v018579@zion.cs.uiuc.edu> Author: ddunbar Date: Fri Nov 20 14:17:30 2009 New Revision: 89482 URL: http://llvm.org/viewvc/llvm-project?rev=89482&view=rev Log: Revert "Add some rough optimizations for checking routines.", it buildeth not. Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=89482&r1=89481&r2=89482&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Fri Nov 20 14:17:30 2009 @@ -81,9 +81,6 @@ Value *EmitMemCpy(Value *Dst, Value *Src, Value *Len, unsigned Align, IRBuilder<> &B); - Value *EmitMemMove(Value *Dst, Value *Src, Value *Len, - unsigned Align, IRBuilder<> &B); - /// EmitMemChr - Emit a call to the memchr function. This assumes that Ptr is /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. Value *EmitMemChr(Value *Ptr, Value *Val, Value *Len, IRBuilder<> &B); @@ -163,22 +160,6 @@ ConstantInt::get(Type::getInt32Ty(*Context), Align)); } -/// EmitMemMOve - Emit a call to the memmove function to the builder. This -/// always expects that the size has type 'intptr_t' and Dst/Src are pointers. -Value *LibCallOptimization::EmitMemMove(Value *Dst, Value *Src, Value *Len, - unsigned Align, IRBuilder<> &B) { - Module *M = Caller->getParent(); - Intrinsic::ID IID = Intrinsic::memmove; - const Type *Tys[1]; - Tys[0] = TD->getIntPtrType(*Context); - Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); - Value *Dst = CastToCStr(CI->getOperand(1), B); - Value *Src = CastToCStr(CI->getOperand(2), B); - Value *Size = CI->getOperand(3); - Value *Align = ConstantInt::get(Type::getInt32Ty(*Context), 1); - return B.CreateCall4(MemMove, Dst, Src, Size, Align); -} - /// EmitMemChr - Emit a call to the memchr function. This assumes that Ptr is /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. Value *LibCallOptimization::EmitMemChr(Value *Ptr, Value *Val, @@ -1029,7 +1010,16 @@ return 0; // memmove(x, y, n) -> llvm.memmove(x, y, n, 1) - EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3), 1, B); + Module *M = Caller->getParent(); + Intrinsic::ID IID = Intrinsic::memmove; + const Type *Tys[1]; + Tys[0] = TD->getIntPtrType(*Context); + Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); + Value *Dst = CastToCStr(CI->getOperand(1), B); + Value *Src = CastToCStr(CI->getOperand(2), B); + Value *Size = CI->getOperand(3); + Value *Align = ConstantInt::get(Type::getInt32Ty(*Context), 1); + B.CreateCall4(MemMove, Dst, Src, Size, Align); return CI->getOperand(1); } }; @@ -1058,96 +1048,6 @@ }; //===----------------------------------------------------------------------===// -// Object Size Checking Optimizations -//===----------------------------------------------------------------------===// -//===---------------------------------------===// -// 'memcpy_chk' Optimizations - -struct MemCpyChkOpt : public LibCallOptimization { - virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { - // These optimizations require TargetData. - if (!TD) return 0; - - const FunctionType *FT = Callee->getFunctionType(); - if (FT->getNumParams() != 4 || FT->getReturnType() != FT->getParamType(0) || - !isa(FT->getParamType(0)) || - !isa(FT->getParamType(1)) || - !isa(FT->getParamType(3)) || - FT->getParamType(2) != TD->getIntPtrType(*Context)) - return 0; - - ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); - if (!SizeCI) - return 0; - if (SizeCI->isAllOnesValue()) { - EmitMemCpy(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3), 1, B); - return CI->getOperand(1); - } - - return 0; - } -}; - -//===---------------------------------------===// -// 'memset_chk' Optimizations - -struct MemSetChkOpt : public LibCallOptimization { - virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { - // These optimizations require TargetData. - if (!TD) return 0; - - const FunctionType *FT = Callee->getFunctionType(); - if (FT->getNumParams() != 4 || FT->getReturnType() != FT->getParamType(0) || - !isa(FT->getParamType(0)) || - !isa(FT->getParamType(1)) || - !isa(FT->getParamType(3)) || - FT->getParamType(2) != TD->getIntPtrType(*Context)) - return 0; - - ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); - if (!SizeCI) - return 0; - if (SizeCI->isAllOnesValue()) { - Value *Val = B.CreateIntCast(CI->getOperand(2), Type::getInt8Ty(*Context), - false); - EmitMemSet(CI->getOperand(1), Val, CI->getOperand(3), B); - return CI->getOperand(1); - } - - return 0; - } -}; - -//===---------------------------------------===// -// 'memmove_chk' Optimizations - -struct MemMoveChkOpt : public LibCallOptimization { - virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { - // These optimizations require TargetData. - if (!TD) return 0; - - const FunctionType *FT = Callee->getFunctionType(); - if (FT->getNumParams() != 4 || FT->getReturnType() != FT->getParamType(0) || - !isa(FT->getParamType(0)) || - !isa(FT->getParamType(1)) || - !isa(FT->getParamType(3)) || - FT->getParamType(2) != TD->getIntPtrType(*Context)) - return 0; - - ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); - if (!SizeCI) - return 0; - if (SizeCI->isAllOnesValue()) { - EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3), - 1, B); - return CI->getOperand(1); - } - - return 0; - } -}; - -//===----------------------------------------------------------------------===// // Math Library Optimizations //===----------------------------------------------------------------------===// @@ -1686,10 +1586,7 @@ // Formatting and IO Optimizations SPrintFOpt SPrintF; PrintFOpt PrintF; FWriteOpt FWrite; FPutsOpt FPuts; FPrintFOpt FPrintF; - - // Object Size Checking SizeOpt ObjectSize; - MemCpyChkOpt MemCpyChk; MemSetChkOpt MemSetChk; MemMoveChkOpt MemMoveChk; bool Modified; // This is only used by doInitialization. public: @@ -1796,12 +1693,8 @@ Optimizations["fputs"] = &FPuts; Optimizations["fprintf"] = &FPrintF; - // Object Size Checking - Optimizations["llvm.objectsize.i32"] = &ObjectSize; - Optimizations["llvm.objectsize.i64"] = &ObjectSize; - Optimizations["__memcpy_chk"] = &MemCpyChk; - Optimizations["__memset_chk"] = &MemSetChk; - Optimizations["__memmove_chk"] = &MemMoveChk; + // Miscellaneous + Optimizations["llvm.objectsize"] = &ObjectSize; } From gohman at apple.com Fri Nov 20 14:19:14 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 20:19:14 -0000 Subject: [llvm-commits] [llvm] r89483 - in /llvm/trunk: lib/Transforms/Scalar/SCCP.cpp test/Transforms/IPConstantProp/dangling-block-address.ll Message-ID: <200911202019.nAKKJEcx018640@zion.cs.uiuc.edu> Author: djg Date: Fri Nov 20 14:19:14 2009 New Revision: 89483 URL: http://llvm.org/viewvc/llvm-project?rev=89483&view=rev Log: Fix IPSCCP's code for deleting dead blocks to tolerate outstanding blockaddress users. This fixes PR5569. Added: llvm/trunk/test/Transforms/IPConstantProp/dangling-block-address.ll Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=89483&r1=89482&r2=89483&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Fri Nov 20 14:19:14 2009 @@ -1869,8 +1869,12 @@ for (unsigned i = 0, e = BlocksToErase.size(); i != e; ++i) { // If there are any PHI nodes in this successor, drop entries for BB now. BasicBlock *DeadBB = BlocksToErase[i]; - while (!DeadBB->use_empty()) { - Instruction *I = cast(DeadBB->use_back()); + for (Value::use_iterator UI = DeadBB->use_begin(), UE = DeadBB->use_end(); + UI != UE; ) { + // Ignore blockaddress users; BasicBlock's dtor will handle them. + Instruction *I = dyn_cast(*UI++); + if (!I) continue; + bool Folded = ConstantFoldTerminator(I->getParent()); if (!Folded) { // The constant folder may not have been able to fold the terminator Added: llvm/trunk/test/Transforms/IPConstantProp/dangling-block-address.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IPConstantProp/dangling-block-address.ll?rev=89483&view=auto ============================================================================== --- llvm/trunk/test/Transforms/IPConstantProp/dangling-block-address.ll (added) +++ llvm/trunk/test/Transforms/IPConstantProp/dangling-block-address.ll Fri Nov 20 14:19:14 2009 @@ -0,0 +1,42 @@ +; RUN: opt < %s -internalize -ipsccp -S | FileCheck %s +; PR5569 + +; IPSCCP should prove that the blocks are dead and delete them, and +; properly handle the dangling blockaddress constants. + +; CHECK: @bar.l = internal constant [2 x i8*] [i8* inttoptr (i32 1 to i8*), i8* inttoptr (i32 1 to i8*)] + + at code = global [5 x i32] [i32 0, i32 0, i32 0, i32 0, i32 1], align 4 ; <[5 x i32]*> [#uses=0] + at bar.l = internal constant [2 x i8*] [i8* blockaddress(@bar, %lab0), i8* blockaddress(@bar, %end)] ; <[2 x i8*]*> [#uses=1] + +define void @foo(i32 %x) nounwind readnone { +entry: + %b = alloca i32, align 4 ; [#uses=1] + volatile store i32 -1, i32* %b + ret void +} + +define void @bar(i32* nocapture %pc) nounwind readonly { +entry: + br label %indirectgoto + +lab0: ; preds = %indirectgoto + %indvar.next = add i32 %indvar, 1 ; [#uses=1] + br label %indirectgoto + +end: ; preds = %indirectgoto + ret void + +indirectgoto: ; preds = %lab0, %entry + %indvar = phi i32 [ %indvar.next, %lab0 ], [ 0, %entry ] ; [#uses=2] + %pc.addr.0 = getelementptr i32* %pc, i32 %indvar ; [#uses=1] + %tmp1.pn = load i32* %pc.addr.0 ; [#uses=1] + %indirect.goto.dest.in = getelementptr inbounds [2 x i8*]* @bar.l, i32 0, i32 %tmp1.pn ; [#uses=1] + %indirect.goto.dest = load i8** %indirect.goto.dest.in ; [#uses=1] + indirectbr i8* %indirect.goto.dest, [label %lab0, label %end] +} + +define i32 @main() nounwind readnone { +entry: + ret i32 0 +} From echristo at apple.com Fri Nov 20 14:21:52 2009 From: echristo at apple.com (Eric Christopher) Date: Fri, 20 Nov 2009 12:21:52 -0800 Subject: [llvm-commits] [llvm] r89479 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: <728B5ADD-7F00-4178-AF90-EB228254A160@apple.com> References: <200911201957.nAKJvcR4017793@zion.cs.uiuc.edu> <728B5ADD-7F00-4178-AF90-EB228254A160@apple.com> Message-ID: Um oops. Can you please revert? Apparently I forgot to save the file when building and testing the last time. Sorry again. -eric On Nov 20, 2009, at 12:06 PM, Evan Cheng wrote: > This breaks the build? > > /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/ > Transforms/Scalar/SimplifyLibCalls.cpp: In member function > 'llvm::Value*::LibCallOptimization::EmitMemMove > (llvm::Value*,\ > llvm::Value*, llvm::Value*, unsigned int, llvm::IRBuilder llvm::ConstantFolder, llvm::IRBuilderDefaultInserter >&)': > /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/ > Transforms/Scalar/SimplifyLibCalls.cpp:175: error: declaration of > 'llvm::Value* Dst' shadows a parameter > /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/ > Transforms/Scalar/SimplifyLibCalls.cpp:175: error: 'CI' was not > declared in this scope > /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/ > Transforms/Scalar/SimplifyLibCalls.cpp:176: error: declaration of > 'llvm::Value* Src' shadows a parameter > /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/ > Transforms/Scalar/SimplifyLibCalls.cpp:178: error: declaration of > 'llvm::Value* Align' shadows a parameter > > Evan > On Nov 20, 2009, at 11:57 AM, Eric Christopher wrote: > >> Author: echristo >> Date: Fri Nov 20 13:57:37 2009 >> New Revision: 89479 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=89479&view=rev >> Log: >> Add some rough optimizations for checking routines. >> >> Modified: >> llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp >> >> Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=89479&r1=89478&r2=89479&view=diff >> >> === >> === >> === >> ===================================================================== >> --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) >> +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Fri Nov >> 20 13:57:37 2009 >> @@ -81,6 +81,9 @@ >> Value *EmitMemCpy(Value *Dst, Value *Src, Value *Len, >> unsigned Align, IRBuilder<> &B); >> >> + Value *EmitMemMove(Value *Dst, Value *Src, Value *Len, >> + unsigned Align, IRBuilder<> &B); >> + >> /// EmitMemChr - Emit a call to the memchr function. This assumes >> that Ptr is >> /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. >> Value *EmitMemChr(Value *Ptr, Value *Val, Value *Len, IRBuilder<> >> &B); >> @@ -160,6 +163,22 @@ >> ConstantInt::get(Type::getInt32Ty(*Context), >> Align)); >> } >> >> +/// EmitMemMOve - Emit a call to the memmove function to the >> builder. This >> +/// always expects that the size has type 'intptr_t' and Dst/Src >> are pointers. >> +Value *LibCallOptimization::EmitMemMove(Value *Dst, Value *Src, >> Value *Len, >> + unsigned Align, IRBuilder<> &B) { >> + Module *M = Caller->getParent(); >> + Intrinsic::ID IID = Intrinsic::memmove; >> + const Type *Tys[1]; >> + Tys[0] = TD->getIntPtrType(*Context); >> + Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); >> + Value *Dst = CastToCStr(CI->getOperand(1), B); >> + Value *Src = CastToCStr(CI->getOperand(2), B); >> + Value *Size = CI->getOperand(3); >> + Value *Align = ConstantInt::get(Type::getInt32Ty(*Context), 1); >> + return B.CreateCall4(MemMove, Dst, Src, Size, Align); >> +} >> + >> /// EmitMemChr - Emit a call to the memchr function. This assumes >> that Ptr is >> /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. >> Value *LibCallOptimization::EmitMemChr(Value *Ptr, Value *Val, >> @@ -1010,16 +1029,7 @@ >> return 0; >> >> // memmove(x, y, n) -> llvm.memmove(x, y, n, 1) >> - Module *M = Caller->getParent(); >> - Intrinsic::ID IID = Intrinsic::memmove; >> - const Type *Tys[1]; >> - Tys[0] = TD->getIntPtrType(*Context); >> - Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); >> - Value *Dst = CastToCStr(CI->getOperand(1), B); >> - Value *Src = CastToCStr(CI->getOperand(2), B); >> - Value *Size = CI->getOperand(3); >> - Value *Align = ConstantInt::get(Type::getInt32Ty(*Context), 1); >> - B.CreateCall4(MemMove, Dst, Src, Size, Align); >> + EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI- >> >getOperand(3), 1, B); >> return CI->getOperand(1); >> } >> }; >> @@ -1048,6 +1058,96 @@ >> }; >> >> // >> === >> --- >> ------------------------------------------------------------------- >> ===// >> +// Object Size Checking Optimizations >> +// >> === >> --- >> ------------------------------------------------------------------- >> ===// >> +//===---------------------------------------===// >> +// 'memcpy_chk' Optimizations >> + >> +struct MemCpyChkOpt : public LibCallOptimization { >> + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, >> IRBuilder<> &B) { >> + // These optimizations require TargetData. >> + if (!TD) return 0; >> + >> + const FunctionType *FT = Callee->getFunctionType(); >> + if (FT->getNumParams() != 4 || FT->getReturnType() != FT- >> >getParamType(0) || >> + !isa(FT->getParamType(0)) || >> + !isa(FT->getParamType(1)) || >> + !isa(FT->getParamType(3)) || >> + FT->getParamType(2) != TD->getIntPtrType(*Context)) >> + return 0; >> + >> + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); >> + if (!SizeCI) >> + return 0; >> + if (SizeCI->isAllOnesValue()) { >> + EmitMemCpy(CI->getOperand(1), CI->getOperand(2), CI- >> >getOperand(3), 1, B); >> + return CI->getOperand(1); >> + } >> + >> + return 0; >> + } >> +}; >> + >> +//===---------------------------------------===// >> +// 'memset_chk' Optimizations >> + >> +struct MemSetChkOpt : public LibCallOptimization { >> + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, >> IRBuilder<> &B) { >> + // These optimizations require TargetData. >> + if (!TD) return 0; >> + >> + const FunctionType *FT = Callee->getFunctionType(); >> + if (FT->getNumParams() != 4 || FT->getReturnType() != FT- >> >getParamType(0) || >> + !isa(FT->getParamType(0)) || >> + !isa(FT->getParamType(1)) || >> + !isa(FT->getParamType(3)) || >> + FT->getParamType(2) != TD->getIntPtrType(*Context)) >> + return 0; >> + >> + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); >> + if (!SizeCI) >> + return 0; >> + if (SizeCI->isAllOnesValue()) { >> + Value *Val = B.CreateIntCast(CI->getOperand(2), >> Type::getInt8Ty(*Context), >> + false); >> + EmitMemSet(CI->getOperand(1), Val, CI->getOperand(3), B); >> + return CI->getOperand(1); >> + } >> + >> + return 0; >> + } >> +}; >> + >> +//===---------------------------------------===// >> +// 'memmove_chk' Optimizations >> + >> +struct MemMoveChkOpt : public LibCallOptimization { >> + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, >> IRBuilder<> &B) { >> + // These optimizations require TargetData. >> + if (!TD) return 0; >> + >> + const FunctionType *FT = Callee->getFunctionType(); >> + if (FT->getNumParams() != 4 || FT->getReturnType() != FT- >> >getParamType(0) || >> + !isa(FT->getParamType(0)) || >> + !isa(FT->getParamType(1)) || >> + !isa(FT->getParamType(3)) || >> + FT->getParamType(2) != TD->getIntPtrType(*Context)) >> + return 0; >> + >> + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); >> + if (!SizeCI) >> + return 0; >> + if (SizeCI->isAllOnesValue()) { >> + EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI- >> >getOperand(3), >> + 1, B); >> + return CI->getOperand(1); >> + } >> + >> + return 0; >> + } >> +}; >> + >> +// >> === >> --- >> ------------------------------------------------------------------- >> ===// >> // Math Library Optimizations >> // >> === >> --- >> ------------------------------------------------------------------- >> ===// >> >> @@ -1586,7 +1686,10 @@ >> // Formatting and IO Optimizations >> SPrintFOpt SPrintF; PrintFOpt PrintF; >> FWriteOpt FWrite; FPutsOpt FPuts; FPrintFOpt FPrintF; >> + >> + // Object Size Checking >> SizeOpt ObjectSize; >> + MemCpyChkOpt MemCpyChk; MemSetChkOpt MemSetChk; MemMoveChkOpt >> MemMoveChk; >> >> bool Modified; // This is only used by doInitialization. >> public: >> @@ -1693,8 +1796,12 @@ >> Optimizations["fputs"] = &FPuts; >> Optimizations["fprintf"] = &FPrintF; >> >> - // Miscellaneous >> - Optimizations["llvm.objectsize"] = &ObjectSize; >> + // Object Size Checking >> + Optimizations["llvm.objectsize.i32"] = &ObjectSize; >> + Optimizations["llvm.objectsize.i64"] = &ObjectSize; >> + Optimizations["__memcpy_chk"] = &MemCpyChk; >> + Optimizations["__memset_chk"] = &MemSetChk; >> + Optimizations["__memmove_chk"] = &MemMoveChk; >> } >> >> >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From echristo at apple.com Fri Nov 20 14:22:39 2009 From: echristo at apple.com (Eric Christopher) Date: Fri, 20 Nov 2009 12:22:39 -0800 Subject: [llvm-commits] [llvm] r89482 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: <200911202017.nAKKHU5v018579@zion.cs.uiuc.edu> References: <200911202017.nAKKHU5v018579@zion.cs.uiuc.edu> Message-ID: <103E36ED-44B8-46B0-A72D-012D988EBBCD@apple.com> Thanks. Sorry about that. -eric On Nov 20, 2009, at 12:17 PM, Daniel Dunbar wrote: > Author: ddunbar > Date: Fri Nov 20 14:17:30 2009 > New Revision: 89482 > > URL: http://llvm.org/viewvc/llvm-project?rev=89482&view=rev > Log: > Revert "Add some rough optimizations for checking routines.", it > buildeth not. > > Modified: > llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp > > Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=89482&r1=89481&r2=89482&view=diff > > === > === > === > ===================================================================== > --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Fri Nov 20 > 14:17:30 2009 > @@ -81,9 +81,6 @@ > Value *EmitMemCpy(Value *Dst, Value *Src, Value *Len, > unsigned Align, IRBuilder<> &B); > > - Value *EmitMemMove(Value *Dst, Value *Src, Value *Len, > - unsigned Align, IRBuilder<> &B); > - > /// EmitMemChr - Emit a call to the memchr function. This assumes > that Ptr is > /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. > Value *EmitMemChr(Value *Ptr, Value *Val, Value *Len, IRBuilder<> > &B); > @@ -163,22 +160,6 @@ > ConstantInt::get(Type::getInt32Ty(*Context), > Align)); > } > > -/// EmitMemMOve - Emit a call to the memmove function to the > builder. This > -/// always expects that the size has type 'intptr_t' and Dst/Src > are pointers. > -Value *LibCallOptimization::EmitMemMove(Value *Dst, Value *Src, > Value *Len, > - unsigned Align, IRBuilder<> &B) { > - Module *M = Caller->getParent(); > - Intrinsic::ID IID = Intrinsic::memmove; > - const Type *Tys[1]; > - Tys[0] = TD->getIntPtrType(*Context); > - Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); > - Value *Dst = CastToCStr(CI->getOperand(1), B); > - Value *Src = CastToCStr(CI->getOperand(2), B); > - Value *Size = CI->getOperand(3); > - Value *Align = ConstantInt::get(Type::getInt32Ty(*Context), 1); > - return B.CreateCall4(MemMove, Dst, Src, Size, Align); > -} > - > /// EmitMemChr - Emit a call to the memchr function. This assumes > that Ptr is > /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. > Value *LibCallOptimization::EmitMemChr(Value *Ptr, Value *Val, > @@ -1029,7 +1010,16 @@ > return 0; > > // memmove(x, y, n) -> llvm.memmove(x, y, n, 1) > - EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI->getOperand > (3), 1, B); > + Module *M = Caller->getParent(); > + Intrinsic::ID IID = Intrinsic::memmove; > + const Type *Tys[1]; > + Tys[0] = TD->getIntPtrType(*Context); > + Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); > + Value *Dst = CastToCStr(CI->getOperand(1), B); > + Value *Src = CastToCStr(CI->getOperand(2), B); > + Value *Size = CI->getOperand(3); > + Value *Align = ConstantInt::get(Type::getInt32Ty(*Context), 1); > + B.CreateCall4(MemMove, Dst, Src, Size, Align); > return CI->getOperand(1); > } > }; > @@ -1058,96 +1048,6 @@ > }; > > // > === > --- > ------------------------------------------------------------------- > ===// > -// Object Size Checking Optimizations > -// > === > --- > ------------------------------------------------------------------- > ===// > -//===---------------------------------------===// > -// 'memcpy_chk' Optimizations > - > -struct MemCpyChkOpt : public LibCallOptimization { > - virtual Value *CallOptimizer(Function *Callee, CallInst *CI, > IRBuilder<> &B) { > - // These optimizations require TargetData. > - if (!TD) return 0; > - > - const FunctionType *FT = Callee->getFunctionType(); > - if (FT->getNumParams() != 4 || FT->getReturnType() != FT- > >getParamType(0) || > - !isa(FT->getParamType(0)) || > - !isa(FT->getParamType(1)) || > - !isa(FT->getParamType(3)) || > - FT->getParamType(2) != TD->getIntPtrType(*Context)) > - return 0; > - > - ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); > - if (!SizeCI) > - return 0; > - if (SizeCI->isAllOnesValue()) { > - EmitMemCpy(CI->getOperand(1), CI->getOperand(2), CI- > >getOperand(3), 1, B); > - return CI->getOperand(1); > - } > - > - return 0; > - } > -}; > - > -//===---------------------------------------===// > -// 'memset_chk' Optimizations > - > -struct MemSetChkOpt : public LibCallOptimization { > - virtual Value *CallOptimizer(Function *Callee, CallInst *CI, > IRBuilder<> &B) { > - // These optimizations require TargetData. > - if (!TD) return 0; > - > - const FunctionType *FT = Callee->getFunctionType(); > - if (FT->getNumParams() != 4 || FT->getReturnType() != FT- > >getParamType(0) || > - !isa(FT->getParamType(0)) || > - !isa(FT->getParamType(1)) || > - !isa(FT->getParamType(3)) || > - FT->getParamType(2) != TD->getIntPtrType(*Context)) > - return 0; > - > - ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); > - if (!SizeCI) > - return 0; > - if (SizeCI->isAllOnesValue()) { > - Value *Val = B.CreateIntCast(CI->getOperand(2), > Type::getInt8Ty(*Context), > - false); > - EmitMemSet(CI->getOperand(1), Val, CI->getOperand(3), B); > - return CI->getOperand(1); > - } > - > - return 0; > - } > -}; > - > -//===---------------------------------------===// > -// 'memmove_chk' Optimizations > - > -struct MemMoveChkOpt : public LibCallOptimization { > - virtual Value *CallOptimizer(Function *Callee, CallInst *CI, > IRBuilder<> &B) { > - // These optimizations require TargetData. > - if (!TD) return 0; > - > - const FunctionType *FT = Callee->getFunctionType(); > - if (FT->getNumParams() != 4 || FT->getReturnType() != FT- > >getParamType(0) || > - !isa(FT->getParamType(0)) || > - !isa(FT->getParamType(1)) || > - !isa(FT->getParamType(3)) || > - FT->getParamType(2) != TD->getIntPtrType(*Context)) > - return 0; > - > - ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); > - if (!SizeCI) > - return 0; > - if (SizeCI->isAllOnesValue()) { > - EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI- > >getOperand(3), > - 1, B); > - return CI->getOperand(1); > - } > - > - return 0; > - } > -}; > - > -// > === > --- > ------------------------------------------------------------------- > ===// > // Math Library Optimizations > // > === > --- > ------------------------------------------------------------------- > ===// > > @@ -1686,10 +1586,7 @@ > // Formatting and IO Optimizations > SPrintFOpt SPrintF; PrintFOpt PrintF; > FWriteOpt FWrite; FPutsOpt FPuts; FPrintFOpt FPrintF; > - > - // Object Size Checking > SizeOpt ObjectSize; > - MemCpyChkOpt MemCpyChk; MemSetChkOpt MemSetChk; MemMoveChkOpt > MemMoveChk; > > bool Modified; // This is only used by doInitialization. > public: > @@ -1796,12 +1693,8 @@ > Optimizations["fputs"] = &FPuts; > Optimizations["fprintf"] = &FPrintF; > > - // Object Size Checking > - Optimizations["llvm.objectsize.i32"] = &ObjectSize; > - Optimizations["llvm.objectsize.i64"] = &ObjectSize; > - Optimizations["__memcpy_chk"] = &MemCpyChk; > - Optimizations["__memset_chk"] = &MemSetChk; > - Optimizations["__memmove_chk"] = &MemMoveChk; > + // Miscellaneous > + Optimizations["llvm.objectsize"] = &ObjectSize; > } > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Fri Nov 20 14:23:56 2009 From: echristo at apple.com (Eric Christopher) Date: Fri, 20 Nov 2009 12:23:56 -0800 Subject: [llvm-commits] [llvm] r89479 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: References: <200911201957.nAKJvcR4017793@zion.cs.uiuc.edu> <728B5ADD-7F00-4178-AF90-EB228254A160@apple.com> Message-ID: <07D62920-E024-4226-A37E-B202A2C48B08@apple.com> Looks like Daniel got it. -eric On Nov 20, 2009, at 12:21 PM, Eric Christopher wrote: > Um oops. Can you please revert? Apparently I forgot to save the file > when building and testing the last time. > > Sorry again. > > -eric > > > > On Nov 20, 2009, at 12:06 PM, Evan Cheng wrote: > >> This breaks the build? >> >> /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/ >> Transforms/Scalar/SimplifyLibCalls.cpp: In member function >> 'llvm::Value*::LibCallOptimization::EmitMemMove >> (llvm::Value*,\ >> llvm::Value*, llvm::Value*, unsigned int, llvm::IRBuilder> llvm::ConstantFolder, llvm::IRBuilderDefaultInserter >&)': >> /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/ >> Transforms/Scalar/SimplifyLibCalls.cpp:175: error: declaration of >> 'llvm::Value* Dst' shadows a parameter >> /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/ >> Transforms/Scalar/SimplifyLibCalls.cpp:175: error: 'CI' was not >> declared in this scope >> /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/ >> Transforms/Scalar/SimplifyLibCalls.cpp:176: error: declaration of >> 'llvm::Value* Src' shadows a parameter >> /tmp/llvmCore_Embedded.roots/llvmCore_Embedded~obj/src/lib/ >> Transforms/Scalar/SimplifyLibCalls.cpp:178: error: declaration of >> 'llvm::Value* Align' shadows a parameter >> >> Evan >> On Nov 20, 2009, at 11:57 AM, Eric Christopher wrote: >> >>> Author: echristo >>> Date: Fri Nov 20 13:57:37 2009 >>> New Revision: 89479 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=89479&view=rev >>> Log: >>> Add some rough optimizations for checking routines. >>> >>> Modified: >>> llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp >>> >>> Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=89479&r1=89478&r2=89479&view=diff >>> >>> === >>> === >>> === >>> === >>> ================================================================== >>> --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) >>> +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Fri Nov >>> 20 13:57:37 2009 >>> @@ -81,6 +81,9 @@ >>> Value *EmitMemCpy(Value *Dst, Value *Src, Value *Len, >>> unsigned Align, IRBuilder<> &B); >>> >>> + Value *EmitMemMove(Value *Dst, Value *Src, Value *Len, >>> + unsigned Align, IRBuilder<> &B); >>> + >>> /// EmitMemChr - Emit a call to the memchr function. This assumes >>> that Ptr is >>> /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. >>> Value *EmitMemChr(Value *Ptr, Value *Val, Value *Len, IRBuilder<> >>> &B); >>> @@ -160,6 +163,22 @@ >>> ConstantInt::get(Type::getInt32Ty(*Context), >>> Align)); >>> } >>> >>> +/// EmitMemMOve - Emit a call to the memmove function to the >>> builder. This >>> +/// always expects that the size has type 'intptr_t' and Dst/Src >>> are pointers. >>> +Value *LibCallOptimization::EmitMemMove(Value *Dst, Value *Src, >>> Value *Len, >>> + unsigned Align, IRBuilder<> &B) { >>> + Module *M = Caller->getParent(); >>> + Intrinsic::ID IID = Intrinsic::memmove; >>> + const Type *Tys[1]; >>> + Tys[0] = TD->getIntPtrType(*Context); >>> + Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); >>> + Value *Dst = CastToCStr(CI->getOperand(1), B); >>> + Value *Src = CastToCStr(CI->getOperand(2), B); >>> + Value *Size = CI->getOperand(3); >>> + Value *Align = ConstantInt::get(Type::getInt32Ty(*Context), 1); >>> + return B.CreateCall4(MemMove, Dst, Src, Size, Align); >>> +} >>> + >>> /// EmitMemChr - Emit a call to the memchr function. This assumes >>> that Ptr is >>> /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. >>> Value *LibCallOptimization::EmitMemChr(Value *Ptr, Value *Val, >>> @@ -1010,16 +1029,7 @@ >>> return 0; >>> >>> // memmove(x, y, n) -> llvm.memmove(x, y, n, 1) >>> - Module *M = Caller->getParent(); >>> - Intrinsic::ID IID = Intrinsic::memmove; >>> - const Type *Tys[1]; >>> - Tys[0] = TD->getIntPtrType(*Context); >>> - Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); >>> - Value *Dst = CastToCStr(CI->getOperand(1), B); >>> - Value *Src = CastToCStr(CI->getOperand(2), B); >>> - Value *Size = CI->getOperand(3); >>> - Value *Align = ConstantInt::get(Type::getInt32Ty(*Context), 1); >>> - B.CreateCall4(MemMove, Dst, Src, Size, Align); >>> + EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI- >>>> getOperand(3), 1, B); >>> return CI->getOperand(1); >>> } >>> }; >>> @@ -1048,6 +1058,96 @@ >>> }; >>> >>> // >>> === >>> --- >>> ------------------------------------------------------------------- >>> ===// >>> +// Object Size Checking Optimizations >>> +// >>> === >>> --- >>> ------------------------------------------------------------------- >>> ===// >>> +//===---------------------------------------===// >>> +// 'memcpy_chk' Optimizations >>> + >>> +struct MemCpyChkOpt : public LibCallOptimization { >>> + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, >>> IRBuilder<> &B) { >>> + // These optimizations require TargetData. >>> + if (!TD) return 0; >>> + >>> + const FunctionType *FT = Callee->getFunctionType(); >>> + if (FT->getNumParams() != 4 || FT->getReturnType() != FT- >>>> getParamType(0) || >>> + !isa(FT->getParamType(0)) || >>> + !isa(FT->getParamType(1)) || >>> + !isa(FT->getParamType(3)) || >>> + FT->getParamType(2) != TD->getIntPtrType(*Context)) >>> + return 0; >>> + >>> + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); >>> + if (!SizeCI) >>> + return 0; >>> + if (SizeCI->isAllOnesValue()) { >>> + EmitMemCpy(CI->getOperand(1), CI->getOperand(2), CI- >>>> getOperand(3), 1, B); >>> + return CI->getOperand(1); >>> + } >>> + >>> + return 0; >>> + } >>> +}; >>> + >>> +//===---------------------------------------===// >>> +// 'memset_chk' Optimizations >>> + >>> +struct MemSetChkOpt : public LibCallOptimization { >>> + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, >>> IRBuilder<> &B) { >>> + // These optimizations require TargetData. >>> + if (!TD) return 0; >>> + >>> + const FunctionType *FT = Callee->getFunctionType(); >>> + if (FT->getNumParams() != 4 || FT->getReturnType() != FT- >>>> getParamType(0) || >>> + !isa(FT->getParamType(0)) || >>> + !isa(FT->getParamType(1)) || >>> + !isa(FT->getParamType(3)) || >>> + FT->getParamType(2) != TD->getIntPtrType(*Context)) >>> + return 0; >>> + >>> + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); >>> + if (!SizeCI) >>> + return 0; >>> + if (SizeCI->isAllOnesValue()) { >>> + Value *Val = B.CreateIntCast(CI->getOperand(2), >>> Type::getInt8Ty(*Context), >>> + false); >>> + EmitMemSet(CI->getOperand(1), Val, CI->getOperand(3), B); >>> + return CI->getOperand(1); >>> + } >>> + >>> + return 0; >>> + } >>> +}; >>> + >>> +//===---------------------------------------===// >>> +// 'memmove_chk' Optimizations >>> + >>> +struct MemMoveChkOpt : public LibCallOptimization { >>> + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, >>> IRBuilder<> &B) { >>> + // These optimizations require TargetData. >>> + if (!TD) return 0; >>> + >>> + const FunctionType *FT = Callee->getFunctionType(); >>> + if (FT->getNumParams() != 4 || FT->getReturnType() != FT- >>>> getParamType(0) || >>> + !isa(FT->getParamType(0)) || >>> + !isa(FT->getParamType(1)) || >>> + !isa(FT->getParamType(3)) || >>> + FT->getParamType(2) != TD->getIntPtrType(*Context)) >>> + return 0; >>> + >>> + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); >>> + if (!SizeCI) >>> + return 0; >>> + if (SizeCI->isAllOnesValue()) { >>> + EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI- >>>> getOperand(3), >>> + 1, B); >>> + return CI->getOperand(1); >>> + } >>> + >>> + return 0; >>> + } >>> +}; >>> + >>> +// >>> === >>> --- >>> ------------------------------------------------------------------- >>> ===// >>> // Math Library Optimizations >>> // >>> === >>> --- >>> ------------------------------------------------------------------- >>> ===// >>> >>> @@ -1586,7 +1686,10 @@ >>> // Formatting and IO Optimizations >>> SPrintFOpt SPrintF; PrintFOpt PrintF; >>> FWriteOpt FWrite; FPutsOpt FPuts; FPrintFOpt FPrintF; >>> + >>> + // Object Size Checking >>> SizeOpt ObjectSize; >>> + MemCpyChkOpt MemCpyChk; MemSetChkOpt MemSetChk; MemMoveChkOpt >>> MemMoveChk; >>> >>> bool Modified; // This is only used by doInitialization. >>> public: >>> @@ -1693,8 +1796,12 @@ >>> Optimizations["fputs"] = &FPuts; >>> Optimizations["fprintf"] = &FPrintF; >>> >>> - // Miscellaneous >>> - Optimizations["llvm.objectsize"] = &ObjectSize; >>> + // Object Size Checking >>> + Optimizations["llvm.objectsize.i32"] = &ObjectSize; >>> + Optimizations["llvm.objectsize.i64"] = &ObjectSize; >>> + Optimizations["__memcpy_chk"] = &MemCpyChk; >>> + Optimizations["__memset_chk"] = &MemSetChk; >>> + Optimizations["__memmove_chk"] = &MemMoveChk; >>> } >>> >>> >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Fri Nov 20 14:51:19 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 20:51:19 -0000 Subject: [llvm-commits] [llvm] r89484 - in /llvm/trunk: include/llvm/Analysis/LoopInfo.h lib/Transforms/Utils/LoopSimplify.cpp test/Transforms/LoopRotate/indirectbr.ll test/Transforms/LoopSimplify/indirectbr.ll Message-ID: <200911202051.nAKKpJdK019923@zion.cs.uiuc.edu> Author: djg Date: Fri Nov 20 14:51:18 2009 New Revision: 89484 URL: http://llvm.org/viewvc/llvm-project?rev=89484&view=rev Log: Make Loop::getLoopLatch() work on loops which don't have preheaders, as it may be used in contexts where preheader insertion may have failed due to an indirectbr. Make LoopSimplify's LoopSimplify::SeparateNestedLoop properly fail in the case that it would require splitting an indirectbr edge. These fix PR5502. Added: llvm/trunk/test/Transforms/LoopRotate/indirectbr.ll Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp llvm/trunk/test/Transforms/LoopSimplify/indirectbr.ll Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=89484&r1=89483&r2=89484&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Fri Nov 20 14:51:18 2009 @@ -269,8 +269,6 @@ /// getLoopLatch - If there is a single latch block for this loop, return it. /// A latch block is a block that contains a branch back to the header. - /// A loop header in normal form has two edges into it: one from a preheader - /// and one from a latch block. BlockT *getLoopLatch() const { BlockT *Header = getHeader(); typedef GraphTraits > InvBlockTraits; @@ -278,20 +276,12 @@ InvBlockTraits::child_begin(Header); typename InvBlockTraits::ChildIteratorType PE = InvBlockTraits::child_end(Header); - if (PI == PE) return 0; // no preds? - BlockT *Latch = 0; - if (contains(*PI)) - Latch = *PI; - ++PI; - if (PI == PE) return 0; // only one pred? - - if (contains(*PI)) { - if (Latch) return 0; // multiple backedges - Latch = *PI; - } - ++PI; - if (PI != PE) return 0; // more than two preds + for (; PI != PE; ++PI) + if (contains(*PI)) { + if (Latch) return 0; + Latch = *PI; + } return Latch; } Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp?rev=89484&r1=89483&r2=89484&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Fri Nov 20 14:51:18 2009 @@ -477,8 +477,13 @@ SmallVector OuterLoopPreds; for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) if (PN->getIncomingValue(i) != PN || - !L->contains(PN->getIncomingBlock(i))) + !L->contains(PN->getIncomingBlock(i))) { + // We can't split indirectbr edges. + if (isa(PN->getIncomingBlock(i)->getTerminator())) + return 0; + OuterLoopPreds.push_back(PN->getIncomingBlock(i)); + } BasicBlock *Header = L->getHeader(); BasicBlock *NewBB = SplitBlockPredecessors(Header, &OuterLoopPreds[0], Added: llvm/trunk/test/Transforms/LoopRotate/indirectbr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopRotate/indirectbr.ll?rev=89484&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopRotate/indirectbr.ll (added) +++ llvm/trunk/test/Transforms/LoopRotate/indirectbr.ll Fri Nov 20 14:51:18 2009 @@ -0,0 +1,43 @@ +; RUN: opt < %s -S -loop-rotate -disable-output -verify-loop-info -verify-dom-info +; PR5502 + +define void @z80_do_opcodes() nounwind { +entry: + br label %while.cond + +while.cond: ; preds = %end_opcode, %entry + br label %while.body + +while.body: ; preds = %while.cond + br label %indirectgoto + +run_opcode: ; preds = %indirectgoto + %tmp276 = load i8* undef ; [#uses=1] + br label %indirectgoto + +if.else295: ; preds = %divide_late + br label %end_opcode + +end_opcode: ; preds = %indirectgoto, %sw.default42406, %sw.default, %if.else295 + %opcode.2 = phi i8 [ %opcode.0, %indirectgoto ], [ 0, %sw.default42406 ], [ undef, %sw.default ], [ %opcode.0, %if.else295 ] ; [#uses=0] + switch i32 undef, label %while.cond [ + i32 221, label %sw.bb11691 + i32 253, label %sw.bb30351 + ] + +sw.bb11691: ; preds = %end_opcode + br label %sw.default + +sw.default: ; preds = %sw.bb11691 + br label %end_opcode + +sw.bb30351: ; preds = %end_opcode + br label %sw.default42406 + +sw.default42406: ; preds = %sw.bb30351 + br label %end_opcode + +indirectgoto: ; preds = %run_opcode, %while.body + %opcode.0 = phi i8 [ undef, %while.body ], [ %tmp276, %run_opcode ] ; [#uses=2] + indirectbr i8* undef, [label %run_opcode, label %if.else295, label %end_opcode] +} Modified: llvm/trunk/test/Transforms/LoopSimplify/indirectbr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopSimplify/indirectbr.ll?rev=89484&r1=89483&r2=89484&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LoopSimplify/indirectbr.ll (original) +++ llvm/trunk/test/Transforms/LoopSimplify/indirectbr.ll Fri Nov 20 14:51:18 2009 @@ -81,3 +81,20 @@ %y = phi i64 [ %z, %L0 ], [ 1, %entry ] ret i64 %y } + +define void @pr5502() nounwind { +entry: + br label %while.cond + +while.cond: + br i1 undef, label %while.body, label %while.end + +while.body: + indirectbr i8* undef, [label %end_opcode, label %end_opcode] + +end_opcode: + br i1 false, label %end_opcode, label %while.cond + +while.end: + ret void +} From dpatel at apple.com Fri Nov 20 15:05:37 2009 From: dpatel at apple.com (Devang Patel) Date: Fri, 20 Nov 2009 21:05:37 -0000 Subject: [llvm-commits] [llvm] r89487 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <200911202105.nAKL5bJe020587@zion.cs.uiuc.edu> Author: dpatel Date: Fri Nov 20 15:05:37 2009 New Revision: 89487 URL: http://llvm.org/viewvc/llvm-project?rev=89487&view=rev Log: There is no need to emit source location info for DW_TAG_pointer_type. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=89487&r1=89486&r2=89487&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri Nov 20 15:05:37 2009 @@ -929,7 +929,7 @@ AddUInt(&Buffer, dwarf::DW_AT_byte_size, 0, Size); // Add source line info if available and TyDesc is not a forward declaration. - if (!DTy.isForwardDecl()) + if (!DTy.isForwardDecl() && Tag != dwarf::DW_TAG_pointer_type) AddSourceLine(&Buffer, &DTy); } From greened at obbligato.org Fri Nov 20 15:13:27 2009 From: greened at obbligato.org (David Greene) Date: Fri, 20 Nov 2009 21:13:27 -0000 Subject: [llvm-commits] [llvm] r89489 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Message-ID: <200911202113.nAKLDR9d020896@zion.cs.uiuc.edu> Author: greened Date: Fri Nov 20 15:13:27 2009 New Revision: 89489 URL: http://llvm.org/viewvc/llvm-project?rev=89489&view=rev Log: Cleanups. Make things a little more efficient as suggested by Evan. Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=89489&r1=89488&r2=89489&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Fri Nov 20 15:13:27 2009 @@ -87,6 +87,7 @@ // Initialize the queue to record recently-used registers. if (NumRecentlyUsedRegs > 0) RecentRegs.resize(NumRecentlyUsedRegs, 0); + RecentNext = RecentRegs.begin(); } typedef std::pair IntervalPtr; @@ -154,14 +155,16 @@ std::auto_ptr spiller_; // The queue of recently-used registers. - SmallVector RecentRegs; + SmallVector RecentRegs; + SmallVector::iterator RecentNext; // Record that we just picked this register. void recordRecentlyUsed(unsigned reg) { assert(reg != 0 && "Recently used register is NOREG!"); if (!RecentRegs.empty()) { - std::copy(RecentRegs.begin() + 1, RecentRegs.end(), RecentRegs.begin()); - RecentRegs.back() = reg; + *RecentNext++ = reg; + if (RecentNext == RecentRegs.end()) + RecentNext = RecentRegs.begin(); } } From dpatel at apple.com Fri Nov 20 15:37:22 2009 From: dpatel at apple.com (Devang Patel) Date: Fri, 20 Nov 2009 21:37:22 -0000 Subject: [llvm-commits] [llvm] r89490 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <200911202137.nAKLbNWb021887@zion.cs.uiuc.edu> Author: dpatel Date: Fri Nov 20 15:37:22 2009 New Revision: 89490 URL: http://llvm.org/viewvc/llvm-project?rev=89490&view=rev Log: Do not hold on to a map slot while new entries may be inserted into the map. Use ValueMap, instead of std::map. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=89490&r1=89489&r2=89490&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri Nov 20 15:37:22 2009 @@ -60,12 +60,12 @@ /// GVToDieMap - Tracks the mapping of unit level debug informaton /// variables to debug information entries. /// FIXME : Rename GVToDieMap -> NodeToDieMap - std::map GVToDieMap; + ValueMap GVToDieMap; /// GVToDIEEntryMap - Tracks the mapping of unit level debug informaton /// descriptors to debug information entries using a DIEEntry proxy. /// FIXME : Rename - std::map GVToDIEEntryMap; + ValueMap GVToDIEEntryMap; /// Globals - A map of globally visible named entities for this unit. /// @@ -81,7 +81,7 @@ // Accessors. unsigned getID() const { return ID; } - DIE* getDie() const { return Die; } + DIE* getCUDie() const { return Die; } StringMap &getGlobals() { return Globals; } /// hasContent - Return true if this compile unit has something to write out. @@ -92,14 +92,22 @@ /// void AddGlobal(const std::string &Name, DIE *Die) { Globals[Name] = Die; } - /// getDieMapSlotFor - Returns the debug information entry map slot for the + /// getDIE - Returns the debug information entry map slot for the /// specified debug variable. - DIE *&getDieMapSlotFor(MDNode *N) { return GVToDieMap[N]; } + DIE *getDIE(MDNode *N) { return GVToDieMap.lookup(N); } + + /// insertDIE - Insert DIE into the map. + void insertDIE(MDNode *N, DIE *D) { + GVToDieMap.insert(std::make_pair(N, D)); + } - /// getDIEEntrySlotFor - Returns the debug information entry proxy slot for - /// the specified debug variable. - DIEEntry *&getDIEEntrySlotFor(MDNode *N) { - return GVToDIEEntryMap[N]; + /// getDIEEntry - Returns the debug information entry for the speciefied + /// debug variable. + DIEEntry *getDIEEntry(MDNode *N) { return GVToDIEEntryMap.lookup(N); } + + /// insertDIEEntry - Insert debug information entry into the map. + void insertDIEEntry(MDNode *N, DIEEntry *E) { + GVToDIEEntryMap.insert(std::make_pair(N, E)); } /// AddDie - Adds or interns the DIE to the compile unit. @@ -846,7 +854,7 @@ return; // Check for pre-existence. - DIEEntry *&Slot = DW_Unit->getDIEEntrySlotFor(Ty.getNode()); + DIEEntry *Slot = DW_Unit->getDIEEntry(Ty.getNode()); // If it exists then use the existing value. if (Slot) { @@ -856,6 +864,7 @@ // Set up proxy. Slot = CreateDIEEntry(); + DW_Unit->insertDIEEntry(Ty.getNode(), Slot); // Construct type. DIE Buffer(dwarf::DW_TAG_base_type); @@ -872,7 +881,7 @@ DIE *Die = NULL; DIDescriptor Context = Ty.getContext(); if (!Context.isNull()) - Die = DW_Unit->getDieMapSlotFor(Context.getNode()); + Die = DW_Unit->getDIE(Context.getNode()); if (Die) { DIE *Child = new DIE(Buffer); @@ -1236,8 +1245,7 @@ } // DW_TAG_inlined_subroutine may refer to this DIE. - DIE *&Slot = DW_Unit->getDieMapSlotFor(SP.getNode()); - Slot = SPDie; + DW_Unit->insertDIE(SP.getNode(), SPDie); return SPDie; } @@ -1407,7 +1415,7 @@ DIE *DwarfDebug::UpdateSubprogramScopeDIE(MDNode *SPNode) { - DIE *SPDie = ModuleCU->getDieMapSlotFor(SPNode); + DIE *SPDie = ModuleCU->getDIE(SPNode); assert (SPDie && "Unable to find subprogram DIE!"); AddLabel(SPDie, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr, DWLabel("func_begin", SubprogramCount)); @@ -1475,7 +1483,7 @@ DIE *ScopeDIE = new DIE(dwarf::DW_TAG_inlined_subroutine); DISubprogram InlinedSP = getDISubprogram(DS.getNode()); - DIE *&OriginDIE = ModuleCU->getDieMapSlotFor(InlinedSP.getNode()); + DIE *OriginDIE = ModuleCU->getDIE(InlinedSP.getNode()); assert (OriginDIE && "Unable to find Origin DIE!"); AddDIEEntry(ScopeDIE, dwarf::DW_AT_abstract_origin, dwarf::DW_FORM_ref4, OriginDIE); @@ -1540,7 +1548,7 @@ if (AbsDIE) { DIScope DS(Scope->getScopeNode()); DISubprogram InlinedSP = getDISubprogram(DS.getNode()); - DIE *&OriginSPDIE = ModuleCU->getDieMapSlotFor(InlinedSP.getNode()); + DIE *OriginSPDIE = ModuleCU->getDIE(InlinedSP.getNode()); (void) OriginSPDIE; assert (OriginSPDIE && "Unable to find Origin DIE for the SP!"); DIE *AbsDIE = DV->getAbstractVariable()->getDIE(); @@ -1591,7 +1599,7 @@ ScopeDIE = ConstructInlinedScopeDIE(Scope); else if (DS.isSubprogram()) { if (Scope->isAbstractScope()) - ScopeDIE = ModuleCU->getDieMapSlotFor(DS.getNode()); + ScopeDIE = ModuleCU->getDIE(DS.getNode()); else ScopeDIE = UpdateSubprogramScopeDIE(DS.getNode()); } @@ -1705,17 +1713,16 @@ return; // Check for pre-existence. - DIE *&Slot = ModuleCU->getDieMapSlotFor(DI_GV.getNode()); - if (Slot) + if (ModuleCU->getDIE(DI_GV.getNode())) return; DIE *VariableDie = CreateGlobalVariableDIE(ModuleCU, DI_GV); // Add to map. - Slot = VariableDie; + ModuleCU->insertDIE(N, VariableDie); // Add to context owner. - ModuleCU->getDie()->AddChild(VariableDie); + ModuleCU->getCUDie()->AddChild(VariableDie); // Expose as global. FIXME - need to check external flag. ModuleCU->AddGlobal(DI_GV.getName(), VariableDie); @@ -1726,8 +1733,7 @@ DISubprogram SP(N); // Check for pre-existence. - DIE *&Slot = ModuleCU->getDieMapSlotFor(N); - if (Slot) + if (ModuleCU->getDIE(N)) return; if (!SP.isDefinition()) @@ -1738,10 +1744,10 @@ DIE *SubprogramDie = CreateSubprogramDIE(ModuleCU, SP); // Add to map. - Slot = SubprogramDie; + ModuleCU->insertDIE(N, SubprogramDie); // Add to context owner. - ModuleCU->getDie()->AddChild(SubprogramDie); + ModuleCU->getCUDie()->AddChild(SubprogramDie); // Expose as global. ModuleCU->AddGlobal(SP.getName(), SubprogramDie); @@ -2290,7 +2296,7 @@ sizeof(int32_t) + // Offset Into Abbrev. Section sizeof(int8_t); // Pointer Size (in bytes) - SizeAndOffsetDie(ModuleCU->getDie(), Offset, true); + SizeAndOffsetDie(ModuleCU->getCUDie(), Offset, true); CompileUnitOffsets[ModuleCU] = 0; } @@ -2402,7 +2408,7 @@ /// EmitDebugInfo / EmitDebugInfoPerCU - Emit the debug info section. /// void DwarfDebug::EmitDebugInfoPerCU(CompileUnit *Unit) { - DIE *Die = Unit->getDie(); + DIE *Die = Unit->getCUDie(); // Emit the compile units header. EmitLabel("info_begin", Unit->getID()); From scallanan at apple.com Fri Nov 20 15:40:28 2009 From: scallanan at apple.com (Sean Callanan) Date: Fri, 20 Nov 2009 21:40:28 -0000 Subject: [llvm-commits] [llvm] r89491 - in /llvm/trunk: include/llvm/IntrinsicsX86.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/palignr-2.ll Message-ID: <200911202140.nAKLeSO8022061@zion.cs.uiuc.edu> Author: spyffe Date: Fri Nov 20 15:40:28 2009 New Revision: 89491 URL: http://llvm.org/viewvc/llvm-project?rev=89491&view=rev Log: Fixed PALIGNR to take 8-bit rotations in all cases. Also fixed the corresponding testcase, and the PALIGNR intrinsic (tested for correctness with llvm-gcc). Modified: llvm/trunk/include/llvm/IntrinsicsX86.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/palignr-2.ll Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=89491&r1=89490&r2=89491&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Fri Nov 20 15:40:28 2009 @@ -673,10 +673,10 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_ssse3_palign_r : GCCBuiltin<"__builtin_ia32_palignr">, Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, - llvm_v1i64_ty, llvm_i16_ty], [IntrNoMem]>; + llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; def int_x86_ssse3_palign_r_128 : GCCBuiltin<"__builtin_ia32_palignr128">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, - llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; + llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>; } //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=89491&r1=89490&r2=89491&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Nov 20 15:40:28 2009 @@ -2820,40 +2820,40 @@ let Constraints = "$src1 = $dst" in { def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), - (ins VR64:$src1, VR64:$src2, i16imm:$src3), + (ins VR64:$src1, VR64:$src2, i8imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>; def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), - (ins VR64:$src1, i64mem:$src2, i16imm:$src3), + (ins VR64:$src1, i64mem:$src2, i8imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>; def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst), - (ins VR128:$src1, VR128:$src2, i32imm:$src3), + (ins VR128:$src1, VR128:$src2, i8imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, OpSize; def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst), - (ins VR128:$src1, i128mem:$src2, i32imm:$src3), + (ins VR128:$src1, i128mem:$src2, i8imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, OpSize; } // palignr patterns. -def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i16 imm:$src3)), +def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i8 imm:$src3)), (PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>, Requires<[HasSSSE3]>; def : Pat<(int_x86_ssse3_palign_r VR64:$src1, (memop64 addr:$src2), - (i16 imm:$src3)), + (i8 imm:$src3)), (PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>, Requires<[HasSSSE3]>; -def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i32 imm:$src3)), +def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i8 imm:$src3)), (PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm:$src3))>, Requires<[HasSSSE3]>; def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, (memopv2i64 addr:$src2), - (i32 imm:$src3)), + (i8 imm:$src3)), (PALIGNR128rm VR128:$src1, addr:$src2, (BYTE_imm imm:$src3))>, Requires<[HasSSSE3]>; Modified: llvm/trunk/test/CodeGen/X86/palignr-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/palignr-2.ll?rev=89491&r1=89490&r2=89491&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/palignr-2.ll (original) +++ llvm/trunk/test/CodeGen/X86/palignr-2.ll Fri Nov 20 15:40:28 2009 @@ -9,12 +9,12 @@ entry: ; CHECK: t1: ; palignr $3, %xmm1, %xmm0 - %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i32 24) nounwind readnone + %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i8 24) nounwind readnone store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16 ret void } -declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i32) nounwind readnone +declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone define void @t2() nounwind ssp { entry: @@ -22,7 +22,7 @@ ; palignr $4, _b, %xmm0 %0 = load <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1] %1 = load <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1] - %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i32 32) nounwind readnone + %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) nounwind readnone store <2 x i64> %2, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16 ret void } From mikael.lepisto at tut.fi Fri Nov 20 16:04:12 2009 From: mikael.lepisto at tut.fi (=?ISO-8859-1?Q?Mikael_Lepist=F6?=) Date: Sat, 21 Nov 2009 00:04:12 +0200 Subject: [llvm-commits] [PATCH] fix compiling llvm-gcc against installed llvm, tested with rev 89457 Message-ID: <825CF204-986A-492F-8AE9-4B5B0473CF3E@tut.fi> Hi, Here is patch again (I sent this also few weeks ago) for allowing compilation of llvm-gcc against llvm installation directory. For some reason it never got applied during llvm-2.6 release hurries. Before patch compiling llvm-gcc against llvm worked only if llvm includes and libs were installed in same prefix. However e.g. in debian deb packages have includes and libs installed in different prefix. Patch allows compiling llvm-gcc against any installation, as long as llvm-config --includedir and llvm-config --libdir points to correct places. I tried that after patch building llvm-gcc still works: against llvm install directory against llvm objdir when objdir == srcdir against llvm objdir when objdir != srcdir I also tested building llvm-gcc without enable-llvm. Mikael Lepist? -------------- next part -------------- A non-text attachment was scrubbed... Name: building-llvm-gcc-towards-installed-llvm-directory.patch Type: application/octet-stream Size: 2001 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091121/1eabd19f/attachment.obj -------------- next part -------------- From scallanan at apple.com Fri Nov 20 16:06:50 2009 From: scallanan at apple.com (Sean Callanan) Date: Fri, 20 Nov 2009 14:06:50 -0800 Subject: [llvm-commits] [llvm] r89491 - in /llvm/trunk: include/llvm/IntrinsicsX86.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/palignr-2.ll In-Reply-To: <200911202140.nAKLeSO8022061@zion.cs.uiuc.edu> References: <200911202140.nAKLeSO8022061@zion.cs.uiuc.edu> Message-ID: <2850F318-028A-4F9E-BBF9-E1048F97ED2A@apple.com> Looks like I broke the clang testsuite. Reverting. Seam On Nov 20, 2009, at 1:40 PM, Sean Callanan wrote: > Author: spyffe > Date: Fri Nov 20 15:40:28 2009 > New Revision: 89491 > > URL: http://llvm.org/viewvc/llvm-project?rev=89491&view=rev > Log: > Fixed PALIGNR to take 8-bit rotations in all cases. > Also fixed the corresponding testcase, and the PALIGNR > intrinsic (tested for correctness with llvm-gcc). > > Modified: > llvm/trunk/include/llvm/IntrinsicsX86.td > llvm/trunk/lib/Target/X86/X86InstrSSE.td > llvm/trunk/test/CodeGen/X86/palignr-2.ll > > Modified: llvm/trunk/include/llvm/IntrinsicsX86.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=89491&r1=89490&r2=89491&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) > +++ llvm/trunk/include/llvm/IntrinsicsX86.td Fri Nov 20 15:40:28 2009 > @@ -673,10 +673,10 @@ > let TargetPrefix = "x86" in { // All intrinsics start with > "llvm.x86.". > def int_x86_ssse3_palign_r : > GCCBuiltin<"__builtin_ia32_palignr">, > Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, > - llvm_v1i64_ty, llvm_i16_ty], [IntrNoMem]>; > + llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; > def int_x86_ssse3_palign_r_128 : > GCCBuiltin<"__builtin_ia32_palignr128">, > Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, > - llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; > + llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>; > } > > // > = > = > = > ----------------------------------------------------------------------= > ==// > > Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=89491&r1=89490&r2=89491&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Nov 20 15:40:28 2009 > @@ -2820,40 +2820,40 @@ > > let Constraints = "$src1 = $dst" in { > def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), > - (ins VR64:$src1, VR64:$src2, i16imm: > $src3), > + (ins VR64:$src1, VR64:$src2, i8imm:$src3), > "palignr\t{$src3, $src2, $dst|$dst, > $src2, $src3}", > []>; > def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), > - (ins VR64:$src1, i64mem:$src2, i16imm: > $src3), > + (ins VR64:$src1, i64mem:$src2, i8imm: > $src3), > "palignr\t{$src3, $src2, $dst|$dst, > $src2, $src3}", > []>; > > def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst), > - (ins VR128:$src1, VR128:$src2, i32imm: > $src3), > + (ins VR128:$src1, VR128:$src2, i8imm: > $src3), > "palignr\t{$src3, $src2, $dst|$dst, > $src2, $src3}", > []>, OpSize; > def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst), > - (ins VR128:$src1, i128mem:$src2, i32imm: > $src3), > + (ins VR128:$src1, i128mem:$src2, i8imm: > $src3), > "palignr\t{$src3, $src2, $dst|$dst, > $src2, $src3}", > []>, OpSize; > } > > // palignr patterns. > -def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i16 imm: > $src3)), > +def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i8 imm: > $src3)), > (PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>, > Requires<[HasSSSE3]>; > def : Pat<(int_x86_ssse3_palign_r VR64:$src1, > (memop64 addr:$src2), > - (i16 imm:$src3)), > + (i8 imm:$src3)), > (PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>, > Requires<[HasSSSE3]>; > > -def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, > (i32 imm:$src3)), > +def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i8 > imm:$src3)), > (PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm: > $src3))>, > Requires<[HasSSSE3]>; > def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, > (memopv2i64 addr:$src2), > - (i32 imm:$src3)), > + (i8 imm:$src3)), > (PALIGNR128rm VR128:$src1, addr:$src2, (BYTE_imm imm: > $src3))>, > Requires<[HasSSSE3]>; > > > Modified: llvm/trunk/test/CodeGen/X86/palignr-2.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/palignr-2.ll?rev=89491&r1=89490&r2=89491&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/test/CodeGen/X86/palignr-2.ll (original) > +++ llvm/trunk/test/CodeGen/X86/palignr-2.ll Fri Nov 20 15:40:28 2009 > @@ -9,12 +9,12 @@ > entry: > ; CHECK: t1: > ; palignr $3, %xmm1, %xmm0 > - %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> > %a, <2 x i64> %b, i32 24) nounwind readnone > + %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> > %a, <2 x i64> %b, i8 24) nounwind readnone > store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x > i64>*), align 16 > ret void > } > > -declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x > i64>, i32) nounwind readnone > +declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x > i64>, i8) nounwind readnone > > define void @t2() nounwind ssp { > entry: > @@ -22,7 +22,7 @@ > ; palignr $4, _b, %xmm0 > %0 = load <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align > 16 ; <<2 x i64>> [#uses=1] > %1 = load <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align > 16 ; <<2 x i64>> [#uses=1] > - %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> > %1, <2 x i64> %0, i32 32) nounwind readnone > + %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> > %1, <2 x i64> %0, i8 32) nounwind readnone > store <2 x i64> %2, <2 x i64>* bitcast ([4 x i32]* @c to <2 x > i64>*), align 16 > ret void > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From scallanan at apple.com Fri Nov 20 16:09:28 2009 From: scallanan at apple.com (Sean Callanan) Date: Fri, 20 Nov 2009 22:09:28 -0000 Subject: [llvm-commits] [llvm] r89495 - in /llvm/trunk: include/llvm/IntrinsicsX86.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/palignr-2.ll Message-ID: <200911202209.nAKM9SOp023203@zion.cs.uiuc.edu> Author: spyffe Date: Fri Nov 20 16:09:28 2009 New Revision: 89495 URL: http://llvm.org/viewvc/llvm-project?rev=89495&view=rev Log: Reverting PALIGNR fix until I figure out how this broke the Clang testsuite. Modified: llvm/trunk/include/llvm/IntrinsicsX86.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/palignr-2.ll Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=89495&r1=89494&r2=89495&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Fri Nov 20 16:09:28 2009 @@ -673,10 +673,10 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_ssse3_palign_r : GCCBuiltin<"__builtin_ia32_palignr">, Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, - llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; + llvm_v1i64_ty, llvm_i16_ty], [IntrNoMem]>; def int_x86_ssse3_palign_r_128 : GCCBuiltin<"__builtin_ia32_palignr128">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, - llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>; + llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; } //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=89495&r1=89494&r2=89495&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Nov 20 16:09:28 2009 @@ -2820,40 +2820,40 @@ let Constraints = "$src1 = $dst" in { def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), - (ins VR64:$src1, VR64:$src2, i8imm:$src3), + (ins VR64:$src1, VR64:$src2, i16imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>; def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), - (ins VR64:$src1, i64mem:$src2, i8imm:$src3), + (ins VR64:$src1, i64mem:$src2, i16imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>; def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst), - (ins VR128:$src1, VR128:$src2, i8imm:$src3), + (ins VR128:$src1, VR128:$src2, i32imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, OpSize; def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst), - (ins VR128:$src1, i128mem:$src2, i8imm:$src3), + (ins VR128:$src1, i128mem:$src2, i32imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, OpSize; } // palignr patterns. -def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i8 imm:$src3)), +def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i16 imm:$src3)), (PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>, Requires<[HasSSSE3]>; def : Pat<(int_x86_ssse3_palign_r VR64:$src1, (memop64 addr:$src2), - (i8 imm:$src3)), + (i16 imm:$src3)), (PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>, Requires<[HasSSSE3]>; -def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i8 imm:$src3)), +def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i32 imm:$src3)), (PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm:$src3))>, Requires<[HasSSSE3]>; def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, (memopv2i64 addr:$src2), - (i8 imm:$src3)), + (i32 imm:$src3)), (PALIGNR128rm VR128:$src1, addr:$src2, (BYTE_imm imm:$src3))>, Requires<[HasSSSE3]>; Modified: llvm/trunk/test/CodeGen/X86/palignr-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/palignr-2.ll?rev=89495&r1=89494&r2=89495&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/palignr-2.ll (original) +++ llvm/trunk/test/CodeGen/X86/palignr-2.ll Fri Nov 20 16:09:28 2009 @@ -9,12 +9,12 @@ entry: ; CHECK: t1: ; palignr $3, %xmm1, %xmm0 - %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i8 24) nounwind readnone + %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i32 24) nounwind readnone store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16 ret void } -declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone +declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i32) nounwind readnone define void @t2() nounwind ssp { entry: @@ -22,7 +22,7 @@ ; palignr $4, _b, %xmm0 %0 = load <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1] %1 = load <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1] - %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) nounwind readnone + %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i32 32) nounwind readnone store <2 x i64> %2, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16 ret void } From dalej at apple.com Fri Nov 20 16:16:41 2009 From: dalej at apple.com (Dale Johannesen) Date: Fri, 20 Nov 2009 22:16:41 -0000 Subject: [llvm-commits] [llvm] r89496 - in /llvm/trunk: lib/Target/PowerPC/PPCISelDAGToDAG.cpp test/CodeGen/PowerPC/rlwimi-keep-rsh.ll Message-ID: <200911202216.nAKMGfTo023435@zion.cs.uiuc.edu> Author: johannes Date: Fri Nov 20 16:16:40 2009 New Revision: 89496 URL: http://llvm.org/viewvc/llvm-project?rev=89496&view=rev Log: Remove an incorrect overaggressive optimization (PPC specific). Added: llvm/trunk/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=89496&r1=89495&r2=89496&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Nov 20 16:16:40 2009 @@ -443,8 +443,7 @@ unsigned MB, ME; if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) { - SDValue Tmp1, Tmp2, Tmp3; - bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF; + SDValue Tmp1, Tmp2; if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && isInt32Immediate(Op1.getOperand(1), Value)) { @@ -461,10 +460,9 @@ Op1 = Op1.getOperand(0); } } - - Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0; + SH &= 31; - SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB), + SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); } Added: llvm/trunk/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll?rev=89496&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll (added) +++ llvm/trunk/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll Fri Nov 20 16:16:40 2009 @@ -0,0 +1,28 @@ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s +; Formerly dropped the RHS of %tmp6 when constructing rlwimi. +; 7346117 + + at foo = external global i32 + +define void @xxx(i32 %a, i32 %b, i32 %c, i32 %d) nounwind optsize { +; CHECK: _xxx: +; CHECK: or +; CHECK: and +; CHECK: rlwimi +entry: + %tmp0 = ashr i32 %d, 31 + %tmp1 = and i32 %tmp0, 255 + %tmp2 = xor i32 %tmp1, 255 + %tmp3 = ashr i32 %b, 31 + %tmp4 = ashr i32 %a, 4 + %tmp5 = or i32 %tmp3, %tmp4 + %tmp6 = and i32 %tmp2, %tmp5 + %tmp7 = shl i32 %c, 8 + %tmp8 = or i32 %tmp6, %tmp7 + store i32 %tmp8, i32* @foo, align 4 + br label %return + +return: + ret void +; CHECK: blr +} \ No newline at end of file From dag at cray.com Fri Nov 20 16:22:37 2009 From: dag at cray.com (David Greene) Date: Fri, 20 Nov 2009 16:22:37 -0600 Subject: [llvm-commits] [PATCH] More Spill Annotations Message-ID: <200911201622.37994.dag@cray.com> This patch adds information to spill/reload comments as to whether they are vector or scalar. This is helpful when doing static code analysis of performance issues and other things. It's only implemented for X86. Experts on other architectures will have to fill things in. Please review. Thanks! -Dave Index: include/llvm/Target/TargetInstrInfo.h =================================================================== --- include/llvm/Target/TargetInstrInfo.h (revision 89484) +++ include/llvm/Target/TargetInstrInfo.h (working copy) @@ -142,6 +142,23 @@ return false; } + /// isVectorInstr - Return true if the instruction is a vector operation. + virtual bool isVectorInstr(const MachineInstr& MI) const { + return false; + } + + /// isVectorOperand - Return true if the operand is of vector type. + virtual bool isVectorOperand(const MachineInstr &MI, + const MachineOperand *MO) const { + return false; + } + + /// isVectorOperand - Return true if the mem operand is of vector type. + virtual bool isVectorOperand(const MachineInstr &MI, + const MachineMemOperand *MMO) const { + return false; + } + /// isIdentityCopy - Return true if the instruction is a copy (or /// extract_subreg, insert_subreg, subreg_to_reg) where the source and /// destination registers are the same. @@ -182,11 +199,13 @@ /// hasLoadFromStackSlot - If the specified machine instruction has /// a load from a stack slot, return true along with the FrameIndex - /// of the loaded stack slot. If not, return false. Unlike + /// of the loaded stack slot and the machine mem operand containing + /// the reference. If not, return false. Unlike /// isLoadFromStackSlot, this returns true for any instructions that /// loads from the stack. This is just a hint, as some cases may be /// missed. virtual bool hasLoadFromStackSlot(const MachineInstr *MI, + const MachineMemOperand *&MMO, int &FrameIndex) const { return 0; } @@ -205,17 +224,18 @@ /// stack locations as well. This uses a heuristic so it isn't /// reliable for correctness. virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, - int &FrameIndex) const { + int &FrameIndex) const { return 0; } /// hasStoreToStackSlot - If the specified machine instruction has a /// store to a stack slot, return true along with the FrameIndex of - /// the loaded stack slot. If not, return false. Unlike - /// isStoreToStackSlot, this returns true for any instructions that - /// loads from the stack. This is just a hint, as some cases may be - /// missed. + /// the loaded stack slot and the machine mem operand containing the + /// reference. If not, return false. Unlike isStoreToStackSlot, + /// this returns true for any instructions that loads from the + /// stack. This is just a hint, as some cases may be missed. virtual bool hasStoreToStackSlot(const MachineInstr *MI, + const MachineMemOperand *&MMO, int &FrameIndex) const { return 0; } Index: lib/CodeGen/AsmPrinter/AsmPrinter.cpp =================================================================== --- lib/CodeGen/AsmPrinter/AsmPrinter.cpp (revision 89484) +++ lib/CodeGen/AsmPrinter/AsmPrinter.cpp (working copy) @@ -1854,35 +1854,46 @@ // We assume a single instruction only has a spill or reload, not // both. + const MachineMemOperand *MMO; if (TM.getInstrInfo()->isLoadFromStackSlotPostFE(&MI, FI)) { if (FrameInfo->isSpillSlotObjectIndex(FI)) { + MMO = *MI.memoperands_begin(); + bool isVector = TM.getInstrInfo()->isVectorOperand(MI, MMO); if (Newline) O << '\n'; O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << " Reload"; + O << MAI->getCommentString() << (isVector? " Vector" : " Scalar") + << " Reload"; Newline = true; } } - else if (TM.getInstrInfo()->hasLoadFromStackSlot(&MI, FI)) { + else if (TM.getInstrInfo()->hasLoadFromStackSlot(&MI, MMO, FI)) { if (FrameInfo->isSpillSlotObjectIndex(FI)) { + bool isVector = TM.getInstrInfo()->isVectorOperand(MI, MMO); if (Newline) O << '\n'; O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << " Folded Reload"; + O << MAI->getCommentString() << (isVector? " Vector" : " Scalar") + << " Folded Reload"; Newline = true; } } else if (TM.getInstrInfo()->isStoreToStackSlotPostFE(&MI, FI)) { if (FrameInfo->isSpillSlotObjectIndex(FI)) { + MMO = *MI.memoperands_begin(); + bool isVector = TM.getInstrInfo()->isVectorOperand(MI, MMO); if (Newline) O << '\n'; O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << " Spill"; + O << MAI->getCommentString() << (isVector? " Vector" : " Scalar") + << " Spill"; Newline = true; } } - else if (TM.getInstrInfo()->hasStoreToStackSlot(&MI, FI)) { + else if (TM.getInstrInfo()->hasStoreToStackSlot(&MI, MMO, FI)) { if (FrameInfo->isSpillSlotObjectIndex(FI)) { + bool isVector = TM.getInstrInfo()->isVectorOperand(MI, MMO); if (Newline) O << '\n'; O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << " Folded Spill"; + O << MAI->getCommentString() << (isVector? " Vector" : " Scalar") + << " Folded Spill"; Newline = true; } } @@ -1892,9 +1903,11 @@ if (TM.getInstrInfo()->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) { if (MI.getAsmPrinterFlag(ReloadReuse)) { + bool isVector = TM.getInstrInfo()->isVectorInstr(MI); if (Newline) O << '\n'; O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << " Reload Reuse"; + O << MAI->getCommentString() << (isVector? " Vector" : " Scalar") + << " Reload Reuse"; Newline = true; } } Index: lib/Target/X86/X86InstrInfo.cpp =================================================================== --- lib/Target/X86/X86InstrInfo.cpp (revision 89484) +++ lib/Target/X86/X86InstrInfo.cpp (working copy) @@ -34,6 +34,7 @@ #include "llvm/MC/MCAsmInfo.h" #include +#include using namespace llvm; @@ -711,6 +712,393 @@ } } +bool X86InstrInfo::isVectorInstr(const MachineInstr &MI) const{ + // Handle special cases here. + switch(MI.getOpcode()) { + case X86::MOVDDUPrr: + case X86::MOVDDUPrm: + case X86::MOVSHDUPrr: + case X86::MOVSHDUPrm: + case X86::MOVSLDUPrr: + case X86::MOVSLDUPrm: + case X86::MPSADBWrri: // "PS" is lucky. Be explicit. + case X86::MPSADBWrmi: + return true; + case X86::MMX_MOVQ2DQrr: + return false; + } + + // Look for the common cases. + const TargetInstrDesc &InstrDesc = get(MI.getOpcode()); + const char *Name = InstrDesc.getName(); + if (std::strstr(Name, "PS") != 0 // SSE packed single + || std::strstr(Name, "PD") != 0 // SSE packed double + || std::strstr(Name, "DQ") != 0 // SSE packed integer + || Name[0] == 'P' // MMX/SSE packed integer + || Name[0] == 'V' && Name[1] == 'P') // AVX packed integer + return true; + + return false; +} + +bool X86InstrInfo::isVectorOperand(const MachineInstr &MI, + const MachineOperand *MO) const { + // Handle special cases here. These are for mixed vector/scalar + // instructions. + if (MO->getType() != MachineOperand::MO_Register + && MO->getType() != MachineOperand::MO_FrameIndex + && MO->getType() != MachineOperand::MO_ExternalSymbol + && MO->getType() != MachineOperand::MO_GlobalAddress) + return false; + + // Operands that are part of memory addresses are never vector. + // Come Larrabee, we will need to handle vector address operands so + // this will get more complicated. + for (unsigned OpNum = 0; OpNum < MI.getNumOperands(); ++OpNum) { + if (&MI.getOperand(OpNum) == MO) { + switch(MI.getOpcode()) { + case X86::EXTRACTPSmr: + case X86::EXTRACTPSrr: + return OpNum == MI.getNumExplicitOperands() - 1; + case X86::INSERTPSrm: + case X86::INSERTPSrr: + return OpNum == 0; + case X86::MOVDDUPrm: + case X86::MOVDDUPrr: + return OpNum == 0; + case X86::MOVHPDmr: + return OpNum == MI.getNumExplicitOperands() - 1; + case X86::MOVHPDrm: + // Address operands are never vector. + return false; + case X86::MOVLPDmr: + return OpNum == MI.getNumExplicitOperands() - 1; + case X86::MOVLPDrr: + case X86::MOVLPDrm: + return OpNum == 0; + case X86::MOVMSKPDrr: + case X86::MOVMSKPSrr: + return OpNum == 1; + case X86::PBLENDVBrr0: + case X86::PBLENDVBrm0: + return !(MO->isReg() && MO->isImplicit()); + case X86::PCMPESTRIrr: + case X86::PCMPESTRIrm: + case X86::PCMPESTRIArr: + case X86::PCMPESTRIArm: + case X86::PCMPESTRICrr: + case X86::PCMPESTRICrm: + case X86::PCMPESTRIOrr: + case X86::PCMPESTRIOrm: + case X86::PCMPESTRISrr: + case X86::PCMPESTRISrm: + case X86::PCMPESTRIZrr: + case X86::PCMPESTRIZrm: + case X86::PCMPESTRM128MEM: + case X86::PCMPESTRM128REG: + case X86::PCMPESTRM128rr: + case X86::PCMPESTRM128rm: + case X86::PCMPISTRIrr: + case X86::PCMPISTRIrm: + case X86::PCMPISTRIArr: + case X86::PCMPISTRIArm: + case X86::PCMPISTRICrr: + case X86::PCMPISTRICrm: + case X86::PCMPISTRIOrr: + case X86::PCMPISTRIOrm: + case X86::PCMPISTRISrr: + case X86::PCMPISTRISrm: + case X86::PCMPISTRIZrr: + case X86::PCMPISTRIZrm: + case X86::PCMPISTRM128MEM: + case X86::PCMPISTRM128REG: + case X86::PCMPISTRM128rr: + case X86::PCMPISTRM128rm: + return !(MO->isReg() && MO->isImplicit()); + case X86::PEXTRBrr: + case X86::MMX_PEXTRWri: + case X86::PEXTRWri: + case X86::PEXTRDrr: + case X86::PEXTRQrr: + case X86::PEXTRBmr: + case X86::PEXTRWmr: + case X86::PEXTRDmr: + case X86::PEXTRQmr: + // Account for the immediate operand. + return OpNum == MI.getNumExplicitOperands() - 2; + case X86::PINSRBrr: + case X86::PINSRBrm: + case X86::MMX_PINSRWrri: + case X86::PINSRWrri: + case X86::MMX_PINSRWrmi: + case X86::PINSRWrmi: + case X86::PINSRDrr: + case X86::PINSRDrm: + case X86::PINSRQrr: + case X86::PINSRQrm: + return OpNum == 0; + case X86::PMOVMSKBrr: + return OpNum == 1; + case X86::MMX_PSLLWrr: + case X86::MMX_PSLLWri: + case X86::MMX_PSLLWrm: + case X86::PSLLWrr: + case X86::PSLLWri: + case X86::PSLLWrm: + case X86::MMX_PSLLDrr: + case X86::MMX_PSLLDri: + case X86::MMX_PSLLDrm: + case X86::PSLLDrr: + case X86::PSLLDri: + case X86::PSLLDrm: + case X86::MMX_PSLLQrr: + case X86::MMX_PSLLQri: + case X86::MMX_PSLLQrm: + case X86::PSLLQrr: + case X86::PSLLQri: + case X86::PSLLQrm: + case X86::MMX_PSRAWrr: + case X86::MMX_PSRAWri: + case X86::MMX_PSRAWrm: + case X86::PSRAWrr: + case X86::PSRAWri: + case X86::PSRAWrm: + case X86::MMX_PSRADrr: + case X86::MMX_PSRADri: + case X86::MMX_PSRADrm: + case X86::PSRADrr: + case X86::PSRADri: + case X86::PSRADrm: + case X86::MMX_PSRLWrr: + case X86::MMX_PSRLWri: + case X86::MMX_PSRLWrm: + case X86::PSRLWrr: + case X86::PSRLWri: + case X86::PSRLWrm: + case X86::MMX_PSRLDrr: + case X86::MMX_PSRLDri: + case X86::MMX_PSRLDrm: + case X86::PSRLDrr: + case X86::PSRLDri: + case X86::PSRLDrm: + case X86::MMX_PSRLQrr: + case X86::MMX_PSRLQri: + case X86::MMX_PSRLQrm: + case X86::PSRLQrr: + case X86::PSRLQri: + case X86::PSRLQrm: + return OpNum == 0; + case X86::PTESTrr: + case X86::PTESTrm: + return !(MO->isReg() && MO->isImplicit()); + case X86::UNPCKLPDrr: + case X86::UNPCKLPDrm: + return OpNum == 0; + } + return isVectorInstr(MI); + } + } + + assert(0 && "Did not find operand in instruction!"); + + return false; +} + +bool X86InstrInfo::isVectorOperand(const MachineInstr &MI, + const MachineMemOperand *MMO) const { + bool found = false; + for (MachineInstr::mmo_iterator m = MI.memoperands_begin(), + mend = MI.memoperands_end(); + m != mend; + ++m) { + if (*m == MMO) + found = true; + } + + if (!found) + assert(0 && "Wrong machine mem operands for instruction!"); + + // Handle special cases here. These are for mixed vector/scalar + // instructions. + switch(MI.getOpcode()) { + case X86::EXTRACTPSrr: + assert(0 && "Wrong machine mem operand for instruction!"); + return false; + case X86::EXTRACTPSmr: + assert(MMO->isStore() && "Wrong machine mem operand for instruction!"); + return false; + case X86::INSERTPSrr: + assert(0 && "Wrong machine mem operand for instruction!"); + return false; + case X86::INSERTPSrm: + assert(MMO->isLoad() && "Wrong machine mem operand for instruction!"); + return false; + case X86::MOVDDUPrr: + assert(0 && "Wrong machine mem operand for instruction!"); + return false; + case X86::MOVDDUPrm: + assert(MMO->isLoad() && "Wrong machine mem operand for instruction!"); + return false; + case X86::MOVHPDmr: + assert(MMO->isStore() && "Wrong machine mem operand for instruction!"); + return false; + case X86::MOVHPDrm: + assert(MMO->isLoad() && "Wrong machine mem operand for instruction!"); + return false; + case X86::MOVLPDmr: + assert(MMO->isStore() && "Wrong machine mem operand for instruction!"); + return false; + case X86::MOVLPDrr: + assert(0 && "Wrong machine mem operand for instruction!"); + return false; + case X86::MOVLPDrm: + assert(MMO->isLoad() && "Wrong machine mem operand for instruction!"); + return false; + case X86::MOVMSKPDrr: + case X86::MOVMSKPSrr: + assert(0 && "Wrong machine mem operand for instruction!"); + return false; + case X86::PBLENDVBrr0: + assert(0 && "Wrong machine mem operand for instruction!"); + return false; + case X86::PBLENDVBrm0: + assert(MMO->isLoad() && "Wrong machine mem operand for instruction!"); + return true; + case X86::PCMPESTRIrm: + case X86::PCMPESTRIArm: + case X86::PCMPESTRICrm: + case X86::PCMPESTRIOrm: + case X86::PCMPESTRISrm: + case X86::PCMPESTRIZrm: + case X86::PCMPESTRM128MEM: + case X86::PCMPESTRM128rm: + case X86::PCMPISTRIrm: + case X86::PCMPISTRIArm: + case X86::PCMPISTRICrm: + case X86::PCMPISTRIOrm: + case X86::PCMPISTRISrm: + case X86::PCMPISTRIZrm: + case X86::PCMPISTRM128MEM: + case X86::PCMPISTRM128rm: + assert(MMO->isLoad() && "Wrong machine mem operand for instruction!"); + return false; + case X86::PCMPESTRIrr: + case X86::PCMPESTRIArr: + case X86::PCMPESTRICrr: + case X86::PCMPESTRIOrr: + case X86::PCMPESTRISrr: + case X86::PCMPESTRIZrr: + case X86::PCMPESTRM128REG: + case X86::PCMPESTRM128rr: + case X86::PCMPISTRIrr: + case X86::PCMPISTRIArr: + case X86::PCMPISTRICrr: + case X86::PCMPISTRIOrr: + case X86::PCMPISTRISrr: + case X86::PCMPISTRIZrr: + case X86::PCMPISTRM128REG: + case X86::PCMPISTRM128rr: + assert(0 && "Wrong machine mem operand for instruction!"); + return false; + case X86::PEXTRBrr: + case X86::MMX_PEXTRWri: + case X86::PEXTRWri: + case X86::PEXTRDrr: + case X86::PEXTRQrr: + assert(0 && "Wrong machine mem operand for instruction!"); + return false; + case X86::PEXTRBmr: + case X86::PEXTRWmr: + case X86::PEXTRDmr: + case X86::PEXTRQmr: + assert(MMO->isStore() && "Wrong machine mem operand for instruction!"); + return false; + case X86::PINSRBrr: + case X86::MMX_PINSRWrri: + case X86::PINSRWrri: + case X86::PINSRDrr: + case X86::PINSRQrr: + assert(MMO->isStore() && "Wrong machine mem operand for instruction!"); + return false; + case X86::PINSRBrm: + case X86::MMX_PINSRWrmi: + case X86::PINSRWrmi: + case X86::PINSRDrm: + case X86::PINSRQrm: + assert(MMO->isLoad() && "Wrong machine mem operand for instruction!"); + return false; + case X86::PMOVMSKBrr: + assert(0 && "Wrong machine mem operand for instruction!"); + return false; + case X86::MMX_PSLLWrm: + case X86::PSLLWrm: + case X86::MMX_PSLLDrm: + case X86::PSLLDrm: + case X86::MMX_PSLLQrm: + case X86::PSLLQrm: + case X86::MMX_PSRAWrm: + case X86::PSRAWrm: + case X86::MMX_PSRADrm: + case X86::PSRADrm: + case X86::MMX_PSRLWrm: + case X86::PSRLWrm: + case X86::MMX_PSRLDrm: + case X86::PSRLDrm: + case X86::MMX_PSRLQrm: + case X86::PSRLQrm: + assert(MMO->isLoad() && "Wrong machine mem operand for instruction!"); + return false; + case X86::MMX_PSLLWrr: + case X86::MMX_PSLLWri: + case X86::PSLLWrr: + case X86::PSLLWri: + case X86::MMX_PSLLDrr: + case X86::MMX_PSLLDri: + case X86::PSLLDrr: + case X86::PSLLDri: + case X86::MMX_PSLLQrr: + case X86::MMX_PSLLQri: + case X86::PSLLQrr: + case X86::PSLLQri: + case X86::MMX_PSRAWrr: + case X86::MMX_PSRAWri: + case X86::PSRAWrr: + case X86::PSRAWri: + case X86::MMX_PSRADrr: + case X86::MMX_PSRADri: + case X86::PSRADrr: + case X86::PSRADri: + case X86::MMX_PSRLWrr: + case X86::MMX_PSRLWri: + case X86::PSRLWrr: + case X86::PSRLWri: + case X86::MMX_PSRLDrr: + case X86::MMX_PSRLDri: + case X86::PSRLDrr: + case X86::PSRLDri: + case X86::MMX_PSRLQrr: + case X86::MMX_PSRLQri: + case X86::PSRLQrr: + case X86::PSRLQri: + assert(0 && "Wrong machine mem operand for instruction!"); + return false; + case X86::PTESTrr: + assert(0 && "Wrong machine mem operand for instruction!"); + return false; + case X86::PTESTrm: + assert(MMO->isLoad() && "Wrong machine mem operand for instruction!"); + return false; + case X86::UNPCKLPDrr: + assert(0 && "Wrong machine mem operand for instruction!"); + return false; + case X86::UNPCKLPDrm: + assert(MMO->isLoad() && "Wrong machine mem operand for instruction!"); + return false; + } + + return isVectorInstr(MI); +} + /// isFrameOperand - Return true and the FrameIndex if the specified /// operand and follow operands form a reference to the stack frame. bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, @@ -783,12 +1171,14 @@ if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) return Reg; // Check for post-frame index elimination operations - return hasLoadFromStackSlot(MI, FrameIndex); + const MachineMemOperand *Dummy; + return hasLoadFromStackSlot(MI, Dummy, FrameIndex); } return 0; } bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, + const MachineMemOperand *&MMO, int &FrameIndex) const { for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), oe = MI->memoperands_end(); @@ -798,6 +1188,7 @@ if (const FixedStackPseudoSourceValue *Value = dyn_cast((*o)->getValue())) { FrameIndex = Value->getFrameIndex(); + MMO = *o; return true; } } @@ -819,12 +1210,14 @@ if ((Reg = isStoreToStackSlot(MI, FrameIndex))) return Reg; // Check for post-frame index elimination operations - return hasStoreToStackSlot(MI, FrameIndex); + const MachineMemOperand *Dummy; + return hasStoreToStackSlot(MI, Dummy, FrameIndex); } return 0; } bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI, + const MachineMemOperand *&MMO, int &FrameIndex) const { for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), oe = MI->memoperands_end(); @@ -834,6 +1227,7 @@ if (const FixedStackPseudoSourceValue *Value = dyn_cast((*o)->getValue())) { FrameIndex = Value->getFrameIndex(); + MMO = *o; return true; } } Index: lib/Target/X86/X86InstrInfo.h =================================================================== --- lib/Target/X86/X86InstrInfo.h (revision 89484) +++ lib/Target/X86/X86InstrInfo.h (working copy) @@ -448,6 +448,17 @@ unsigned &SrcReg, unsigned &DstReg, unsigned &SrcSubIdx, unsigned &DstSubIdx) const; + /// isVectorInstr - Return true if the instruction is a vector operation. + virtual bool isVectorInstr(const MachineInstr& MI) const; + + /// isVectorOperand - Return true if the operand is of vector type.. + virtual bool isVectorOperand(const MachineInstr& MI, + const MachineOperand *MO) const; + + /// isVectorOperand - Return true if the mem operand is of vector type.. + virtual bool isVectorOperand(const MachineInstr& MI, + const MachineMemOperand *MMO) const; + unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination /// stack locations as well. This uses a heuristic so it isn't @@ -457,11 +468,14 @@ /// hasLoadFromStackSlot - If the specified machine instruction has /// a load from a stack slot, return true along with the FrameIndex - /// of the loaded stack slot. If not, return false. Unlike + /// of the loaded stack slot and the machine mem operand containing + /// the reference. If not, return false. Unlike /// isLoadFromStackSlot, this returns true for any instructions that /// loads from the stack. This is a hint only and may not catch all /// cases. - bool hasLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; + bool hasLoadFromStackSlot(const MachineInstr *MI, + const MachineMemOperand *&MMO, + int &FrameIndex) const; unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination @@ -472,11 +486,13 @@ /// hasStoreToStackSlot - If the specified machine instruction has a /// store to a stack slot, return true along with the FrameIndex of - /// the loaded stack slot. If not, return false. Unlike - /// isStoreToStackSlot, this returns true for any instructions that - /// loads from the stack. This is a hint only and may not catch all - /// cases. - bool hasStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; + /// the loaded stack slot and the machine mem operand containing the + /// reference. If not, return false. Unlike isStoreToStackSlot, + /// this returns true for any instructions that loads from the + /// stack. This is a hint only and may not catch all cases. + bool hasStoreToStackSlot(const MachineInstr *MI, + const MachineMemOperand *&MMO, + int &FrameIndex) const; bool isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const; Index: test/CodeGen/X86/2009-11-20-VectorSpillComments.ll =================================================================== --- test/CodeGen/X86/2009-11-20-VectorSpillComments.ll (revision 0) +++ test/CodeGen/X86/2009-11-20-VectorSpillComments.ll (revision 0) @@ -0,0 +1,19 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s +; CHECK: Vector Spill +; CHECK: Vector Reload +; CHECK: Vector Folded Reload +; CHECK: Scalar Spill +; CHECK: Scalar Folded Reload + +define <8 x i32> @foo(<8 x i32> %t, <8 x i32> %u) { + %m = srem <8 x i32> %t, %u + ret <8 x i32> %m +} +define <8 x i32> @bar(<8 x i32> %t, <8 x i32> %u) { + %m = urem <8 x i32> %t, %u + ret <8 x i32> %m +} +define <8 x float> @qux(<8 x float> %t, <8 x float> %u) { + %m = frem <8 x float> %t, %u + ret <8 x float> %m +} From scallanan at apple.com Fri Nov 20 16:28:42 2009 From: scallanan at apple.com (Sean Callanan) Date: Fri, 20 Nov 2009 22:28:42 -0000 Subject: [llvm-commits] [llvm] r89500 - in /llvm/trunk: include/llvm/IntrinsicsX86.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/palignr-2.ll Message-ID: <200911202228.nAKMShWY023966@zion.cs.uiuc.edu> Author: spyffe Date: Fri Nov 20 16:28:42 2009 New Revision: 89500 URL: http://llvm.org/viewvc/llvm-project?rev=89500&view=rev Log: Recommitting PALIGNR shift width fixes. Thanks to Daniel Dunbar for fixing clang intrinsics: http://llvm.org/viewvc/llvm-project?view=rev&revision=89499 Modified: llvm/trunk/include/llvm/IntrinsicsX86.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/palignr-2.ll Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=89500&r1=89499&r2=89500&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Fri Nov 20 16:28:42 2009 @@ -673,10 +673,10 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_ssse3_palign_r : GCCBuiltin<"__builtin_ia32_palignr">, Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, - llvm_v1i64_ty, llvm_i16_ty], [IntrNoMem]>; + llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; def int_x86_ssse3_palign_r_128 : GCCBuiltin<"__builtin_ia32_palignr128">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, - llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; + llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>; } //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=89500&r1=89499&r2=89500&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Nov 20 16:28:42 2009 @@ -2820,40 +2820,40 @@ let Constraints = "$src1 = $dst" in { def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), - (ins VR64:$src1, VR64:$src2, i16imm:$src3), + (ins VR64:$src1, VR64:$src2, i8imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>; def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), - (ins VR64:$src1, i64mem:$src2, i16imm:$src3), + (ins VR64:$src1, i64mem:$src2, i8imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>; def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst), - (ins VR128:$src1, VR128:$src2, i32imm:$src3), + (ins VR128:$src1, VR128:$src2, i8imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, OpSize; def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst), - (ins VR128:$src1, i128mem:$src2, i32imm:$src3), + (ins VR128:$src1, i128mem:$src2, i8imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, OpSize; } // palignr patterns. -def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i16 imm:$src3)), +def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i8 imm:$src3)), (PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>, Requires<[HasSSSE3]>; def : Pat<(int_x86_ssse3_palign_r VR64:$src1, (memop64 addr:$src2), - (i16 imm:$src3)), + (i8 imm:$src3)), (PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>, Requires<[HasSSSE3]>; -def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i32 imm:$src3)), +def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i8 imm:$src3)), (PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm:$src3))>, Requires<[HasSSSE3]>; def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, (memopv2i64 addr:$src2), - (i32 imm:$src3)), + (i8 imm:$src3)), (PALIGNR128rm VR128:$src1, addr:$src2, (BYTE_imm imm:$src3))>, Requires<[HasSSSE3]>; Modified: llvm/trunk/test/CodeGen/X86/palignr-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/palignr-2.ll?rev=89500&r1=89499&r2=89500&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/palignr-2.ll (original) +++ llvm/trunk/test/CodeGen/X86/palignr-2.ll Fri Nov 20 16:28:42 2009 @@ -9,12 +9,12 @@ entry: ; CHECK: t1: ; palignr $3, %xmm1, %xmm0 - %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i32 24) nounwind readnone + %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i8 24) nounwind readnone store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16 ret void } -declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i32) nounwind readnone +declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone define void @t2() nounwind ssp { entry: @@ -22,7 +22,7 @@ ; palignr $4, _b, %xmm0 %0 = load <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1] %1 = load <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1] - %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i32 32) nounwind readnone + %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) nounwind readnone store <2 x i64> %2, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16 ret void } From gohman at apple.com Fri Nov 20 17:18:13 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 23:18:13 -0000 Subject: [llvm-commits] [llvm] r89506 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/Target/PowerPC/ lib/Target/X86/ lib/Target/X86/AsmPrinter/ lib/Target/XCore/ Message-ID: <200911202318.nAKNIEjm026045@zion.cs.uiuc.edu> Author: djg Date: Fri Nov 20 17:18:13 2009 New Revision: 89506 URL: http://llvm.org/viewvc/llvm-project?rev=89506&view=rev Log: Target-independent support for TargetFlags on BlockAddress operands, and support for blockaddresses in x86-32 PIC mode. Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h llvm/trunk/include/llvm/CodeGen/MachineOperand.h llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.h llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86Subtarget.cpp llvm/trunk/lib/Target/X86/X86Subtarget.h llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Fri Nov 20 17:18:13 2009 @@ -345,9 +345,11 @@ /// GetBlockAddressSymbol - Return the MCSymbol used to satisfy BlockAddress /// uses of the specified basic block. - MCSymbol *GetBlockAddressSymbol(const BlockAddress *BA) const; + MCSymbol *GetBlockAddressSymbol(const BlockAddress *BA, + const char *Suffix = "") const; MCSymbol *GetBlockAddressSymbol(const Function *F, - const BasicBlock *BB) const; + const BasicBlock *BB, + const char *Suffix = "") const; /// EmitBasicBlockStart - This method prints the label for the specified /// MachineBasicBlock, an alignment (if present) and a comment describing Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Fri Nov 20 17:18:13 2009 @@ -435,10 +435,12 @@ Op.setTargetFlags(TargetFlags); return Op; } - static MachineOperand CreateBA(BlockAddress *BA) { + static MachineOperand CreateBA(BlockAddress *BA, + unsigned char TargetFlags = 0) { MachineOperand Op(MachineOperand::MO_BlockAddress); Op.Contents.OffsetedInfo.Val.BA = BA; Op.setOffset(0); // Offset is always 0. + Op.setTargetFlags(TargetFlags); return Op; } Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Fri Nov 20 17:18:13 2009 @@ -326,8 +326,8 @@ unsigned Line, unsigned Col, MDNode *CU); SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root, unsigned LabelID); - SDValue getBlockAddress(BlockAddress *BA, DebugLoc dl, - bool isTarget = false); + SDValue getBlockAddress(BlockAddress *BA, EVT VT, + bool isTarget = false, unsigned char TargetFlags = 0); SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) { return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Fri Nov 20 17:18:13 2009 @@ -2029,12 +2029,16 @@ class BlockAddressSDNode : public SDNode { BlockAddress *BA; + unsigned char TargetFlags; friend class SelectionDAG; - BlockAddressSDNode(unsigned NodeTy, DebugLoc dl, EVT VT, BlockAddress *ba) - : SDNode(NodeTy, dl, getSDVTList(VT)), BA(ba) { + BlockAddressSDNode(unsigned NodeTy, EVT VT, BlockAddress *ba, + unsigned char Flags) + : SDNode(NodeTy, DebugLoc::getUnknownLoc(), getSDVTList(VT)), + BA(ba), TargetFlags(Flags) { } public: BlockAddress *getBlockAddress() const { return BA; } + unsigned char getTargetFlags() const { return TargetFlags; } static bool classof(const BlockAddressSDNode *) { return true; } static bool classof(const SDNode *N) { Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Fri Nov 20 17:18:13 2009 @@ -1630,12 +1630,14 @@ return true; } -MCSymbol *AsmPrinter::GetBlockAddressSymbol(const BlockAddress *BA) const { - return GetBlockAddressSymbol(BA->getFunction(), BA->getBasicBlock()); +MCSymbol *AsmPrinter::GetBlockAddressSymbol(const BlockAddress *BA, + const char *Suffix) const { + return GetBlockAddressSymbol(BA->getFunction(), BA->getBasicBlock(), Suffix); } MCSymbol *AsmPrinter::GetBlockAddressSymbol(const Function *F, - const BasicBlock *BB) const { + const BasicBlock *BB, + const char *Suffix) const { assert(BB->hasName() && "Address of anonymous basic block not supported yet!"); @@ -1647,7 +1649,8 @@ SmallString<60> Name; raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "BA" << FuncName.size() << '_' << FuncName << '_' - << Mang->makeNameProper(BB->getName()); + << Mang->makeNameProper(BB->getName()) + << Suffix; return OutContext.GetOrCreateSymbol(Name.str()); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Fri Nov 20 17:18:13 2009 @@ -350,7 +350,8 @@ MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), ES->getTargetFlags())); } else if (BlockAddressSDNode *BA = dyn_cast(Op)) { - MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress())); + MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), + BA->getTargetFlags())); } else { assert(Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Flag && Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Nov 20 17:18:13 2009 @@ -462,7 +462,8 @@ } case ISD::TargetBlockAddress: case ISD::BlockAddress: { - ID.AddPointer(cast(N)); + ID.AddPointer(cast(N)->getBlockAddress()); + ID.AddInteger(cast(N)->getTargetFlags()); break; } } // end switch (N->getOpcode()) @@ -1323,18 +1324,20 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getBlockAddress(BlockAddress *BA, DebugLoc DL, - bool isTarget) { +SDValue SelectionDAG::getBlockAddress(BlockAddress *BA, EVT VT, + bool isTarget, + unsigned char TargetFlags) { unsigned Opc = isTarget ? ISD::TargetBlockAddress : ISD::BlockAddress; FoldingSetNodeID ID; - AddNodeIDNode(ID, Opc, getVTList(TLI.getPointerTy()), 0, 0); + AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); ID.AddPointer(BA); + ID.AddInteger(TargetFlags); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); SDNode *N = NodeAllocator.Allocate(); - new (N) BlockAddressSDNode(Opc, DL, TLI.getPointerTy(), BA); + new (N) BlockAddressSDNode(Opc, VT, BA, TargetFlags); CSEMap.InsertNode(N, IP); AllNodes.push_back(N); return SDValue(N, 0); @@ -5810,6 +5813,8 @@ OS << ", "; WriteAsOperand(OS, BA->getBlockAddress()->getBasicBlock(), false); OS << ">"; + if (unsigned int TF = BA->getTargetFlags()) + OS << " [TF=" << TF << ']'; } } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Fri Nov 20 17:18:13 2009 @@ -884,7 +884,7 @@ } if (BlockAddress *BA = dyn_cast(C)) - return DAG.getBlockAddress(BA, getCurDebugLoc()); + return DAG.getBlockAddress(BA, VT); const VectorType *VecTy = cast(V->getType()); unsigned NumElements = VecTy->getNumElements(); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Nov 20 17:18:13 2009 @@ -1174,7 +1174,7 @@ DebugLoc DL = Op.getDebugLoc(); BlockAddress *BA = cast(Op)->getBlockAddress(); - SDValue TgtBA = DAG.getBlockAddress(BA, DL, /*isTarget=*/true); + SDValue TgtBA = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true); SDValue Zero = DAG.getConstant(0, PtrVT); SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, TgtBA, Zero); SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, TgtBA, Zero); Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Fri Nov 20 17:18:13 2009 @@ -43,7 +43,6 @@ Twine(AsmPrinter.getFunctionNumber())+"$pb"); } - /// LowerGlobalAddressOperand - Lower an MO_GlobalAddress operand to an /// MCOperand. MCSymbol *X86MCInstLower:: @@ -231,6 +230,19 @@ return Ctx.GetOrCreateSymbol(Name.str()); } +MCSymbol *X86MCInstLower:: +GetBlockAddressSymbol(const MachineOperand &MO) const { + const char *Suffix = ""; + switch (MO.getTargetFlags()) { + default: llvm_unreachable("Unknown target flag on BA operand"); + case X86II::MO_NO_FLAG: // No flag. + case X86II::MO_PIC_BASE_OFFSET: // Doesn't modify symbol name. + case X86II::MO_GOTOFF: Suffix = "@GOTOFF"; break; + } + + return AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress(), Suffix); +} + MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const { // FIXME: We would like an efficient form for this, so we don't have to do a @@ -331,8 +343,7 @@ MCOp = LowerSymbolOperand(MO, GetConstantPoolIndexSymbol(MO)); break; case MachineOperand::MO_BlockAddress: - MCOp = LowerSymbolOperand(MO, AsmPrinter.GetBlockAddressSymbol( - MO.getBlockAddress())); + MCOp = LowerSymbolOperand(MO, GetBlockAddressSymbol(MO)); break; } Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.h?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.h (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.h Fri Nov 20 17:18:13 2009 @@ -43,6 +43,7 @@ MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const; MCSymbol *GetJumpTableSymbol(const MachineOperand &MO) const; MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const; + MCSymbol *GetBlockAddressSymbol(const MachineOperand &MO) const; MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const; private: Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Nov 20 17:18:13 2009 @@ -252,8 +252,8 @@ else if (AM.JT != -1) Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags); else if (AM.BlockAddr) - Disp = CurDAG->getBlockAddress(AM.BlockAddr, DebugLoc()/*MVT::i32*/, - true /*AM.SymbolFlags*/); + Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32, + true, AM.SymbolFlags); else Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32); @@ -777,7 +777,7 @@ AM.SymbolFlags = J->getTargetFlags(); } else { AM.BlockAddr = cast(N0)->getBlockAddress(); - //AM.SymbolFlags = cast(N0)->getTargetFlags(); + AM.SymbolFlags = cast(N0)->getTargetFlags(); } if (N.getOpcode() == X86ISD::WrapperRIP) @@ -808,7 +808,7 @@ AM.SymbolFlags = J->getTargetFlags(); } else { AM.BlockAddr = cast(N0)->getBlockAddress(); - //AM.SymbolFlags = cast(N0)->getTargetFlags(); + AM.SymbolFlags = cast(N0)->getTargetFlags(); } return false; } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Nov 20 17:18:13 2009 @@ -4722,18 +4722,27 @@ SDValue X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) { - unsigned WrapperKind = X86ISD::Wrapper; + // Create the TargetBlockAddressAddress node. + unsigned char OpFlags = + Subtarget->ClassifyBlockAddressReference(); CodeModel::Model M = getTargetMachine().getCodeModel(); + BlockAddress *BA = cast(Op)->getBlockAddress(); + DebugLoc dl = Op.getDebugLoc(); + SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), + /*isTarget=*/true, OpFlags); + if (Subtarget->isPICStyleRIPRel() && (M == CodeModel::Small || M == CodeModel::Kernel)) - WrapperKind = X86ISD::WrapperRIP; - - DebugLoc DL = Op.getDebugLoc(); - - BlockAddress *BA = cast(Op)->getBlockAddress(); - SDValue Result = DAG.getBlockAddress(BA, DL, /*isTarget=*/true); + Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); + else + Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); - Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); + // With PIC, the address is actually $g + Offset. + if (isGlobalRelativeToPICBase(OpFlags)) { + Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), + DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), + Result); + } return Result; } Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Fri Nov 20 17:18:13 2009 @@ -28,6 +28,21 @@ #include #endif +/// ClassifyBlockAddressReference - Classify a blockaddress reference for the +/// current subtarget according to how we should reference it in a non-pcrel +/// context. +unsigned char X86Subtarget:: +ClassifyBlockAddressReference() const { + if (isPICStyleGOT()) // 32-bit ELF targets. + return X86II::MO_GOTOFF; + + if (isPICStyleStubPIC()) // Darwin/32 in PIC mode. + return X86II::MO_PIC_BASE_OFFSET; + + // Direct static reference to label. + return X86II::MO_NO_FLAG; +} + /// ClassifyGlobalReference - Classify a global variable reference for the /// current subtarget according to how we should reference it in a non-pcrel /// context. Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Fri Nov 20 17:18:13 2009 @@ -199,6 +199,11 @@ unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM)const; + /// ClassifyBlockAddressReference - Classify a blockaddress reference for the + /// current subtarget according to how we should reference it in a non-pcrel + /// context. + unsigned char ClassifyBlockAddressReference() const; + /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls /// to immediate address. bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const; Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=89506&r1=89505&r2=89506&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Fri Nov 20 17:18:13 2009 @@ -295,7 +295,7 @@ DebugLoc DL = Op.getDebugLoc(); BlockAddress *BA = cast(Op)->getBlockAddress(); - SDValue Result = DAG.getBlockAddress(BA, DL, /*isTarget=*/true); + SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true); return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result); } From gohman at apple.com Fri Nov 20 17:21:00 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 23:21:00 -0000 Subject: [llvm-commits] [llvm] r89507 - /llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp Message-ID: <200911202321.nAKNL0Ak026150@zion.cs.uiuc.edu> Author: djg Date: Fri Nov 20 17:21:00 2009 New Revision: 89507 URL: http://llvm.org/viewvc/llvm-project?rev=89507&view=rev Log: Update for new getBlockAddress signature. Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp?rev=89507&r1=89506&r2=89507&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp Fri Nov 20 17:21:00 2009 @@ -312,8 +312,8 @@ else if (AM.JT != -1) Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/); else if (AM.BlockAddr) - Disp = CurDAG->getBlockAddress(AM.BlockAddr, DebugLoc()/*MVT::i32*/, - true /*AM.SymbolFlags*/); + Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32, + true, 0/*AM.SymbolFlags*/); else Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16); From gohman at apple.com Fri Nov 20 17:30:32 2009 From: gohman at apple.com (Dan Gohman) Date: Fri, 20 Nov 2009 23:30:32 -0000 Subject: [llvm-commits] [llvm] r89509 - /llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Message-ID: <200911202330.nAKNUWdx026463@zion.cs.uiuc.edu> Author: djg Date: Fri Nov 20 17:30:32 2009 New Revision: 89509 URL: http://llvm.org/viewvc/llvm-project?rev=89509&view=rev Log: Fix a thinko that caused spurious @GOTOFFs. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp?rev=89509&r1=89508&r2=89509&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Fri Nov 20 17:30:32 2009 @@ -235,8 +235,8 @@ const char *Suffix = ""; switch (MO.getTargetFlags()) { default: llvm_unreachable("Unknown target flag on BA operand"); - case X86II::MO_NO_FLAG: // No flag. - case X86II::MO_PIC_BASE_OFFSET: // Doesn't modify symbol name. + case X86II::MO_NO_FLAG: break; // No flag. + case X86II::MO_PIC_BASE_OFFSET: break; // Doesn't modify symbol name. case X86II::MO_GOTOFF: Suffix = "@GOTOFF"; break; } From evan.cheng at apple.com Fri Nov 20 17:31:34 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 20 Nov 2009 23:31:34 -0000 Subject: [llvm-commits] [llvm] r89510 - in /llvm/trunk: lib/CodeGen/MachineLICM.cpp test/CodeGen/Thumb2/machine-licm.ll test/CodeGen/X86/2009-10-08-MachineLICMBug.ll test/CodeGen/X86/pic-load-remat.ll Message-ID: <200911202331.nAKNVZTO026503@zion.cs.uiuc.edu> Author: evancheng Date: Fri Nov 20 17:31:34 2009 New Revision: 89510 URL: http://llvm.org/viewvc/llvm-project?rev=89510&view=rev Log: Enable hoisting load from constant memories. Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll llvm/trunk/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll llvm/trunk/test/CodeGen/X86/pic-load-remat.ll Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=89510&r1=89509&r2=89510&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Fri Nov 20 17:31:34 2009 @@ -34,16 +34,11 @@ #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/Statistic.h" -#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; -static cl::opt HoistLdConst("licm-const-load", - cl::desc("LICM load from constant memory"), - cl::init(false), cl::Hidden); - STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops"); STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed"); @@ -102,7 +97,7 @@ /// IsProfitableToHoist - Return true if it is potentially profitable to /// hoist the given loop invariant. - bool IsProfitableToHoist(MachineInstr &MI, bool &isConstLd); + bool IsProfitableToHoist(MachineInstr &MI); /// HoistRegion - Walk the specified region of the CFG (defined by all /// blocks dominated by the specified block, and that are in the current @@ -367,9 +362,7 @@ /// IsProfitableToHoist - Return true if it is potentially profitable to hoist /// the given loop invariant. -bool MachineLICM::IsProfitableToHoist(MachineInstr &MI, bool &isConstLd) { - isConstLd = false; - +bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) { if (MI.getOpcode() == TargetInstrInfo::IMPLICIT_DEF) return false; @@ -382,9 +375,8 @@ // adding a store in the loop preheader. But the reload is no more expensive. // The side benefit is these loads are frequently CSE'ed. if (!TII->isTriviallyReMaterializable(&MI, AA)) { - if (!HoistLdConst || !isLoadFromConstantMemory(&MI)) + if (!isLoadFromConstantMemory(&MI)) return false; - isConstLd = true; } // If result(s) of this instruction is used by PHIs, then don't hoist it. @@ -439,9 +431,7 @@ MBB->insert(MI, NewMIs[1]); // If unfolding produced a load that wasn't loop-invariant or profitable to // hoist, discard the new instructions and bail. - bool isConstLd; - if (!IsLoopInvariantInst(*NewMIs[0]) || - !IsProfitableToHoist(*NewMIs[0], isConstLd)) { + if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) { NewMIs[0]->eraseFromParent(); NewMIs[1]->eraseFromParent(); return 0; @@ -507,9 +497,7 @@ /// void MachineLICM::Hoist(MachineInstr *MI) { // First check whether we should hoist this instruction. - bool isConstLd; - if (!IsLoopInvariantInst(*MI) || - !IsProfitableToHoist(*MI, isConstLd)) { + if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) { // If not, try unfolding a hoistable load. MI = ExtractHoistableLoad(MI); if (!MI) return; @@ -518,10 +506,7 @@ // Now move the instructions to the predecessor, inserting it before any // terminator instructions. DEBUG({ - errs() << "Hoisting "; - if (isConstLd) - errs() << "load from constant mem "; - errs() << *MI; + errs() << "Hoisting " << *MI; if (CurPreheader->getBasicBlock()) errs() << " to MachineBasicBlock " << CurPreheader->getName(); Modified: llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll?rev=89510&r1=89509&r2=89510&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Fri Nov 20 17:31:34 2009 @@ -18,7 +18,9 @@ bb.nph: ; preds = %entry ; CHECK: BB#1 ; CHECK: ldr.n r2, LCPI1_0 -; CHECK: ldr r{{[0-9]+}}, [r2] +; CHECK: ldr r3, [r2] +; CHECK: ldr r3, [r3] +; CHECK: ldr r2, [r2] ; CHECK: LBB1_2 ; CHECK: LCPI1_0: ; CHECK-NOT: LCPI1_1: @@ -27,7 +29,9 @@ ; PIC: BB#1 ; PIC: ldr.n r2, LCPI1_0 ; PIC: add r2, pc -; PIC: ldr r{{[0-9]+}}, [r2] +; PIC: ldr r3, [r2] +; PIC: ldr r3, [r3] +; PIC: ldr r2, [r2] ; PIC: LBB1_2 ; PIC: LCPI1_0: ; PIC-NOT: LCPI1_1: Modified: llvm/trunk/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll?rev=89510&r1=89509&r2=89510&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll Fri Nov 20 17:31:34 2009 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -stats |& grep {machine-licm} | grep 1 +; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -stats |& grep {machine-licm} | grep 2 ; rdar://7274692 %0 = type { [125 x i32] } Modified: llvm/trunk/test/CodeGen/X86/pic-load-remat.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pic-load-remat.ll?rev=89510&r1=89509&r2=89510&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pic-load-remat.ll (original) +++ llvm/trunk/test/CodeGen/X86/pic-load-remat.ll Fri Nov 20 17:31:34 2009 @@ -1,10 +1,4 @@ ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -relocation-model=pic | grep psllw | grep pb -; XFAIL: * - -; This is XFAIL'd because MachineLICM is now hoisting all of the loads, and the pic -; base appears killed in the entry block when remat is making its decisions. Remat's -; simple heuristic decides against rematting because it doesn't want to extend the -; live-range of the pic base; this isn't necessarily optimal. define void @f() nounwind { entry: From david_goodwin at apple.com Fri Nov 20 17:33:54 2009 From: david_goodwin at apple.com (David Goodwin) Date: Fri, 20 Nov 2009 23:33:54 -0000 Subject: [llvm-commits] [llvm] r89511 - in /llvm/trunk: include/llvm/Target/TargetRegisterInfo.h lib/CodeGen/AggressiveAntiDepBreaker.cpp Message-ID: <200911202333.nAKNXsAU026581@zion.cs.uiuc.edu> Author: david_goodwin Date: Fri Nov 20 17:33:54 2009 New Revision: 89511 URL: http://llvm.org/viewvc/llvm-project?rev=89511&view=rev Log: Restructure code to allow renaming of multiple-register groups for anti-dep breaking. Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=89511&r1=89510&r2=89511&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Fri Nov 20 17:33:54 2009 @@ -465,7 +465,7 @@ virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; /// getSubRegIndex - For a given register pair, return the sub-register index - /// if they are second register is a sub-register of the second. Return zero + /// if the are second register is a sub-register of the first. Return zero /// otherwise. virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=89511&r1=89510&r2=89511&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Fri Nov 20 17:33:54 2009 @@ -587,79 +587,108 @@ return false; } +#ifndef NDEBUG + // If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod + if (DebugDiv > 0) { + static int renamecnt = 0; + if (renamecnt++ % DebugDiv != DebugMod) + return false; + + errs() << "*** Performing rename " << TRI->getName(SuperReg) << + " for debug ***\n"; + } +#endif + // Check each possible rename register for SuperReg in round-robin // order. If that register is available, and the corresponding // registers are available for the other group subregisters, then we // can use those registers to rename. - BitVector SuperBV = RenameRegisterMap[SuperReg]; const TargetRegisterClass *SuperRC = TRI->getPhysicalRegisterRegClass(SuperReg, MVT::Other); const TargetRegisterClass::iterator RB = SuperRC->allocation_order_begin(MF); const TargetRegisterClass::iterator RE = SuperRC->allocation_order_end(MF); if (RB == RE) { - DEBUG(errs() << "\tEmpty Regclass!!\n"); + DEBUG(errs() << "\tEmpty Super Regclass!!\n"); return false; } -#ifndef NDEBUG - // If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod - if (DebugDiv > 0) { - static int renamecnt = 0; - if (renamecnt++ % DebugDiv != DebugMod) - return false; - - errs() << "*** Performing rename " << TRI->getName(SuperReg) << - " for debug ***\n"; - } -#endif + DEBUG(errs() << "\tFind Registers:"); if (RenameOrder.count(SuperRC) == 0) RenameOrder.insert(RenameOrderType::value_type(SuperRC, RE)); - DEBUG(errs() << "\tFind Register:"); - const TargetRegisterClass::iterator OrigR = RenameOrder[SuperRC]; const TargetRegisterClass::iterator EndR = ((OrigR == RE) ? RB : OrigR); TargetRegisterClass::iterator R = OrigR; do { if (R == RB) R = RE; --R; - const unsigned Reg = *R; + const unsigned NewSuperReg = *R; // Don't replace a register with itself. - if (Reg == SuperReg) continue; + if (NewSuperReg == SuperReg) continue; - DEBUG(errs() << " " << TRI->getName(Reg)); - - // If Reg is dead and Reg's most recent def is not before - // SuperRegs's kill, it's safe to replace SuperReg with Reg. We - // must also check all aliases of Reg. because we can't define a - // register when any sub or super is already live. - if (State->IsLive(Reg) || (KillIndices[SuperReg] > DefIndices[Reg])) { - DEBUG(errs() << "(live)"); - continue; - } else { - bool found = false; - for (const unsigned *Alias = TRI->getAliasSet(Reg); - *Alias; ++Alias) { - unsigned AliasReg = *Alias; - if (State->IsLive(AliasReg) || (KillIndices[SuperReg] > DefIndices[AliasReg])) { - DEBUG(errs() << "(alias " << TRI->getName(AliasReg) << " live)"); - found = true; - break; + DEBUG(errs() << " [" << TRI->getName(NewSuperReg) << ':'); + RenameMap.clear(); + + // For each referenced group register (which must be a SuperReg or + // a subregister of SuperReg), find the corresponding subregister + // of NewSuperReg and make sure it is free to be renamed. + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + unsigned Reg = Regs[i]; + unsigned NewReg = 0; + if (Reg == SuperReg) { + NewReg = NewSuperReg; + } else { + unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); + if (NewSubRegIdx != 0) + NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx); + } + + DEBUG(errs() << " " << TRI->getName(NewReg)); + + // Check if Reg can be renamed to NewReg. + BitVector BV = RenameRegisterMap[Reg]; + if (!BV.test(NewReg)) { + DEBUG(errs() << "(no rename)"); + goto next_super_reg; + } + + // If NewReg is dead and NewReg's most recent def is not before + // Regs's kill, it's safe to replace Reg with NewReg. We + // must also check all aliases of NewReg, because we can't define a + // register when any sub or super is already live. + if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) { + DEBUG(errs() << "(live)"); + goto next_super_reg; + } else { + bool found = false; + for (const unsigned *Alias = TRI->getAliasSet(NewReg); + *Alias; ++Alias) { + unsigned AliasReg = *Alias; + if (State->IsLive(AliasReg) || (KillIndices[Reg] > DefIndices[AliasReg])) { + DEBUG(errs() << "(alias " << TRI->getName(AliasReg) << " live)"); + found = true; + break; + } } + if (found) + goto next_super_reg; } - if (found) - continue; + + // Record that 'Reg' can be renamed to 'NewReg'. + RenameMap.insert(std::pair(Reg, NewReg)); } - if (Reg != 0) { - DEBUG(errs() << '\n'); - RenameOrder.erase(SuperRC); - RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); - RenameMap.insert(std::pair(SuperReg, Reg)); - return true; - } + // If we fall-out here, then every register in the group can be + // renamed, as recorded in RenameMap. + RenameOrder.erase(SuperRC); + RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); + DEBUG(errs() << "]\n"); + return true; + + next_super_reg: + DEBUG(errs() << ']'); } while (R != EndR); DEBUG(errs() << '\n'); From scallanan at apple.com Fri Nov 20 17:53:19 2009 From: scallanan at apple.com (Sean Callanan) Date: Fri, 20 Nov 2009 15:53:19 -0800 Subject: [llvm-commits] Instruction fixes In-Reply-To: <1B17A8DA-F1CF-4155-A000-893BC242D682@apple.com> References: <1B17A8DA-F1CF-4155-A000-893BC242D682@apple.com> Message-ID: I went through and fixed up the Clang tests too. Here's the patch for those. Sean -------------- next part -------------- A non-text attachment was scrubbed... Name: Instructions patch for Clang 11-20-2009.diff Type: application/octet-stream Size: 13408 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091120/5165b2eb/attachment.obj -------------- next part -------------- On Nov 19, 2009, at 5:00 PM, Sean Callanan wrote: > During the testing of the disassembler, I encountered many > instructions that were missing, malformed, had missing forms, or had > missing qualifiers. I went through and added these to the > instruction tables, and fixed the test cases as needed. > > This patch affects no patterns. It only addresses assembly, operand > width (in certain cases) and cosmetic/style issues. > > Please find the patch attached. It has received a preliminary > vetting from Eric Christopher , and I am now > submitting it for inclusion into LLVM proper. > > The change log is below. > > Sean > > > ? > 2009-11-19 Sean Callanan > * X86Instr64bit.td > (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) > Added > (CALL, CMOV) Added qualifiers > (JMP) Added PC-relative jump instruction > (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate > that it is 64-bit only (ambiguous since it has no > REX prefix) > (MOV) Added rr form going the other way, which is encoded > differently > (MOV) Changed immediates to offsets, which is more correct; > also fixed MOV64o64a to have to a 64-bit offset > (MOV) Fixed qualifiers > (MOV) Added debug-register and condition-register moves > (MOVZX) Added more forms > (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which > (as with MOV) are encoded differently > (ROL) Made REX.W required > (BT) Uncommented mr form for disassembly only > (CVT__2__) Added several missing non-intrinsic forms > (LXADD, XCHG) Reordered operands to make more sense for > MRMSrcMem > (XCHG) Added register-to-register forms > (XADD, CMPXCHG, XCHG) Added non-locked forms > * X86InstrSSE.td > (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) > Added > * X86InstrFPStack.td > (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, > FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, > FYL2X, > FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, > FPREM, > FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, > FXRSTOR) > Added > (FCOM, FCOMP) Added qualifiers > (FSTENV, FSAVE, FSTSW) Fixed opcode names > (FNSTSW) Added implicit register operand > * X86InstrInfo.td > (opaque512mem) Added for FXSAVE/FXRSTOR > (offset8, offset16, offset32, offset64) Added for MOV > (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, > LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, > LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, > LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, > CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, > SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, > VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, > VMWRITE, VMXOFF, VMXON) Added > (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier > (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, > JGE, JLE, JG, JCXZ) Added qualifier; added 32-bit forms > (MOV) Changed some immediate forms to offset forms > (MOV) Added reversed reg-reg forms, which are encoded > differently > (MOV) Added debug-register and condition-register moves > (CMOV) Added qualifiers > (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV > (BT) Uncommented memory-register forms for disassembler > (MOVSX, MOVZX) Added forms > (XCHG, LXADD) Made operand order make sense for MRMSrcMem > (XCHG) Added register-register forms > (XADD, CMPXCHG) Added unlocked forms > * X86InstrMMX.td > (MMX_MOVD, MMV_MOVQ) Added forms > * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table > change > > * X86RegisterInfo.td: Added debug and condition register sets > * if-tail-dup.ll: Fixed testcase to reflect jump qualifier > * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier > * peep-test-3.ll: Fixed testcase to reflect test qualifier > * cmov.ll: Fixed testcase to reflect cmov and jump qualifiers > * loop-blocks.ll: Fixed testcase to reflect call qualifier > * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier > * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call > qualifier > * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier > * live-out-reg-info.ll: Fixed testcase to reflect test qualifier > * tail-opts.ll: Fixed testcase to reflect jump and call qualifiers > * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier > * bss-pagealigned.ll: Fixed testcase to reflect call qualifier > * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier > * widen_load-1.ll: Fixed testcase to reflect call > qualifier_______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Fri Nov 20 17:56:52 2009 From: echristo at apple.com (Eric Christopher) Date: Fri, 20 Nov 2009 15:56:52 -0800 Subject: [llvm-commits] Instruction fixes In-Reply-To: References: <1B17A8DA-F1CF-4155-A000-893BC242D682@apple.com> Message-ID: <743AFE3B-9818-434E-A01B-53283C5172EF@apple.com> On Nov 20, 2009, at 3:53 PM, Sean Callanan wrote: > Looks good, and another reason to avoid asm in clang test results :) -eric From vkutuzov at accesssoftek.com Fri Nov 20 18:00:03 2009 From: vkutuzov at accesssoftek.com (Viktor Kutuzov) Date: Sat, 21 Nov 2009 00:00:03 -0000 Subject: [llvm-commits] [llvm] r89516 - in /llvm/trunk: include/llvm/Target/SubtargetFeature.h lib/Target/SubtargetFeature.cpp tools/lto/LTOCodeGenerator.cpp Message-ID: <200911210000.nAL003q6027547@zion.cs.uiuc.edu> Author: vkutuzov Date: Fri Nov 20 18:00:02 2009 New Revision: 89516 URL: http://llvm.org/viewvc/llvm-project?rev=89516&view=rev Log: Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods. Modified: llvm/trunk/include/llvm/Target/SubtargetFeature.h llvm/trunk/lib/Target/SubtargetFeature.cpp llvm/trunk/tools/lto/LTOCodeGenerator.cpp Modified: llvm/trunk/include/llvm/Target/SubtargetFeature.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/SubtargetFeature.h?rev=89516&r1=89515&r2=89516&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/SubtargetFeature.h (original) +++ llvm/trunk/include/llvm/Target/SubtargetFeature.h Fri Nov 20 18:00:02 2009 @@ -22,6 +22,7 @@ #include #include #include "llvm/ADT/Triple.h" +#include "llvm/Support/CommandLine.h" #include "llvm/System/DataTypes.h" namespace llvm { @@ -93,6 +94,12 @@ /// Adding Features. void AddFeature(const std::string &String, bool IsEnabled = true); + /// Add a set of features from the comma-separated string. + void AddFeatures(const std::string &String); + + /// Add a set of features from the parsed command line parameters. + void AddFeatures(const cl::list &List); + /// Get feature bits. uint32_t getBits(const SubtargetFeatureKV *CPUTable, size_t CPUTableSize, Modified: llvm/trunk/lib/Target/SubtargetFeature.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SubtargetFeature.cpp?rev=89516&r1=89515&r2=89516&view=diff ============================================================================== --- llvm/trunk/lib/Target/SubtargetFeature.cpp (original) +++ llvm/trunk/lib/Target/SubtargetFeature.cpp Fri Nov 20 18:00:02 2009 @@ -110,6 +110,33 @@ } } +/// Add a set of features from the comma-separated string. +void SubtargetFeatures::AddFeatures(const std::string &String) +{ + std::vector _Features; + + Split(_Features, String); + // Nothing is specified. + if (_Features.size() == 0) + return; + + for (std::vector::iterator it = _Features.begin(), + end = _Features.end(); it != end; ++it) { + // AddFeature will take care of feature string normalization. + AddFeature(*it); + } +} + +/// Add a set of features from the parsed command line parameters. +void SubtargetFeatures::AddFeatures(const cl::list &List) +{ + for (cl::list::const_iterator it = List.begin(), + end = List.end(); it != end; ++it) { + // AddFeature will take care of feature string normalization. + AddFeature(*it); + } +} + /// Find KV in array using binary search. template const T *Find(const std::string &S, const T *A, size_t L) { // Make the lower bound element we're looking for Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=89516&r1=89515&r2=89516&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Fri Nov 20 18:00:02 2009 @@ -304,10 +304,17 @@ break; } + // Prepare subtarget feature set for the given command line options. + SubtargetFeatures features; + + // Set the rest of features by default. + // Note: Please keep this after all explict feature settings to make sure + // defaults will not override explicitly set options. + features.AddFeatures( + SubtargetFeatures::getDefaultSubtargetFeatures(llvm::Triple(Triple))); + // construct LTModule, hand over ownership of module and target - const std::string FeatureStr = - SubtargetFeatures::getDefaultSubtargetFeatures(llvm::Triple(Triple)); - _target = march->createTargetMachine(Triple, FeatureStr); + _target = march->createTargetMachine(Triple, features.getString()); } return false; } From dpatel at apple.com Fri Nov 20 18:31:03 2009 From: dpatel at apple.com (Devang Patel) Date: Sat, 21 Nov 2009 00:31:03 -0000 Subject: [llvm-commits] [llvm] r89518 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DIE.cpp DIE.h DwarfDebug.cpp DwarfDebug.h Message-ID: <200911210031.nAL0V3Tb028464@zion.cs.uiuc.edu> Author: dpatel Date: Fri Nov 20 18:31:03 2009 New Revision: 89518 URL: http://llvm.org/viewvc/llvm-project?rev=89518&view=rev Log: There is no need to use FoldingSet to unique DIEs. DIEs are created from MDNode, which are already uniqued. And DwarfDebug already uses ValueMaps to find and use existing DIE for a given MDNode. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp?rev=89518&r1=89517&r2=89518&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp Fri Nov 20 18:31:03 2009 @@ -113,18 +113,6 @@ Abbrev.AddFirstAttribute(dwarf::DW_AT_sibling, dwarf::DW_FORM_ref4); } -/// Profile - Used to gather unique data for the value folding set. -/// -void DIE::Profile(FoldingSetNodeID &ID) { - Abbrev.Profile(ID); - - for (unsigned i = 0, N = Children.size(); i < N; ++i) - ID.AddPointer(Children[i]); - - for (unsigned j = 0, M = Values.size(); j < M; ++j) - ID.AddPointer(Values[j]); -} - #ifndef NDEBUG void DIE::print(raw_ostream &O, unsigned IncIndent) { IndentCount += IncIndent; @@ -231,16 +219,6 @@ return 0; } -/// Profile - Used to gather unique data for the value folding set. -/// -void DIEInteger::Profile(FoldingSetNodeID &ID, unsigned Int) { - ID.AddInteger(isInteger); - ID.AddInteger(Int); -} -void DIEInteger::Profile(FoldingSetNodeID &ID) { - Profile(ID, Integer); -} - #ifndef NDEBUG void DIEInteger::print(raw_ostream &O) { O << "Int: " << (int64_t)Integer @@ -258,16 +236,6 @@ D->getAsm()->EmitString(Str); } -/// Profile - Used to gather unique data for the value folding set. -/// -void DIEString::Profile(FoldingSetNodeID &ID, const std::string &Str) { - ID.AddInteger(isString); - ID.AddString(Str); -} -void DIEString::Profile(FoldingSetNodeID &ID) { - Profile(ID, Str); -} - #ifndef NDEBUG void DIEString::print(raw_ostream &O) { O << "Str: \"" << Str << "\""; @@ -292,16 +260,6 @@ return TD->getPointerSize(); } -/// Profile - Used to gather unique data for the value folding set. -/// -void DIEDwarfLabel::Profile(FoldingSetNodeID &ID, const DWLabel &Label) { - ID.AddInteger(isLabel); - Label.Profile(ID); -} -void DIEDwarfLabel::Profile(FoldingSetNodeID &ID) { - Profile(ID, Label); -} - #ifndef NDEBUG void DIEDwarfLabel::print(raw_ostream &O) { O << "Lbl: "; @@ -327,16 +285,6 @@ return TD->getPointerSize(); } -/// Profile - Used to gather unique data for the value folding set. -/// -void DIEObjectLabel::Profile(FoldingSetNodeID &ID, const std::string &Label) { - ID.AddInteger(isAsIsLabel); - ID.AddString(Label); -} -void DIEObjectLabel::Profile(FoldingSetNodeID &ID) { - Profile(ID, Label.c_str()); -} - #ifndef NDEBUG void DIEObjectLabel::print(raw_ostream &O) { O << "Obj: " << Label; @@ -363,20 +311,6 @@ return TD->getPointerSize(); } -/// Profile - Used to gather unique data for the value folding set. -/// -void DIESectionOffset::Profile(FoldingSetNodeID &ID, const DWLabel &Label, - const DWLabel &Section) { - ID.AddInteger(isSectionOffset); - Label.Profile(ID); - Section.Profile(ID); - // IsEH and UseSet are specific to the Label/Section that we will emit the - // offset for; so Label/Section are enough for uniqueness. -} -void DIESectionOffset::Profile(FoldingSetNodeID &ID) { - Profile(ID, Label, Section); -} - #ifndef NDEBUG void DIESectionOffset::print(raw_ostream &O) { O << "Off: "; @@ -405,18 +339,6 @@ return TD->getPointerSize(); } -/// Profile - Used to gather unique data for the value folding set. -/// -void DIEDelta::Profile(FoldingSetNodeID &ID, const DWLabel &LabelHi, - const DWLabel &LabelLo) { - ID.AddInteger(isDelta); - LabelHi.Profile(ID); - LabelLo.Profile(ID); -} -void DIEDelta::Profile(FoldingSetNodeID &ID) { - Profile(ID, LabelHi, LabelLo); -} - #ifndef NDEBUG void DIEDelta::print(raw_ostream &O) { O << "Del: "; @@ -436,21 +358,6 @@ D->getAsm()->EmitInt32(Entry->getOffset()); } -/// Profile - Used to gather unique data for the value folding set. -/// -void DIEEntry::Profile(FoldingSetNodeID &ID, DIE *Entry) { - ID.AddInteger(isEntry); - ID.AddPointer(Entry); -} -void DIEEntry::Profile(FoldingSetNodeID &ID) { - ID.AddInteger(isEntry); - - if (Entry) - ID.AddPointer(Entry); - else - ID.AddPointer(this); -} - #ifndef NDEBUG void DIEEntry::print(raw_ostream &O) { O << format("Die: 0x%lx", (long)(intptr_t)Entry); @@ -505,11 +412,6 @@ return 0; } -void DIEBlock::Profile(FoldingSetNodeID &ID) { - ID.AddInteger(isBlock); - DIE::Profile(ID); -} - #ifndef NDEBUG void DIEBlock::print(raw_ostream &O) { O << "Blk: "; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h?rev=89518&r1=89517&r2=89518&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h Fri Nov 20 18:31:03 2009 @@ -113,7 +113,7 @@ class CompileUnit; class DIEValue; - class DIE : public FoldingSetNode { + class DIE { protected: /// Abbrev - Buffer for constructing abbreviation. /// @@ -189,10 +189,6 @@ Children.clear(); } - /// Profile - Used to gather unique data for the value folding set. - /// - void Profile(FoldingSetNodeID &ID) ; - #ifndef NDEBUG void print(raw_ostream &O, unsigned IncIndent = 0); void dump(); @@ -202,7 +198,7 @@ //===--------------------------------------------------------------------===// /// DIEValue - A debug information entry value. /// - class DIEValue : public FoldingSetNode { + class DIEValue { public: enum { isInteger, @@ -233,10 +229,6 @@ /// virtual unsigned SizeOf(const TargetData *TD, unsigned Form) const = 0; - /// Profile - Used to gather unique data for the value folding set. - /// - virtual void Profile(FoldingSetNodeID &ID) = 0; - // Implement isa/cast/dyncast. static bool classof(const DIEValue *) { return true; } @@ -277,10 +269,6 @@ /// virtual unsigned SizeOf(const TargetData *TD, unsigned Form) const; - /// Profile - Used to gather unique data for the value folding set. - /// - static void Profile(FoldingSetNodeID &ID, unsigned Int); - virtual void Profile(FoldingSetNodeID &ID); // Implement isa/cast/dyncast. static bool classof(const DIEInteger *) { return true; } @@ -309,11 +297,6 @@ return Str.size() + sizeof(char); // sizeof('\0'); } - /// Profile - Used to gather unique data for the value folding set. - /// - static void Profile(FoldingSetNodeID &ID, const std::string &Str); - virtual void Profile(FoldingSetNodeID &ID); - // Implement isa/cast/dyncast. static bool classof(const DIEString *) { return true; } static bool classof(const DIEValue *S) { return S->getType() == isString; } @@ -339,11 +322,6 @@ /// virtual unsigned SizeOf(const TargetData *TD, unsigned Form) const; - /// Profile - Used to gather unique data for the value folding set. - /// - static void Profile(FoldingSetNodeID &ID, const DWLabel &Label); - virtual void Profile(FoldingSetNodeID &ID); - // Implement isa/cast/dyncast. static bool classof(const DIEDwarfLabel *) { return true; } static bool classof(const DIEValue *L) { return L->getType() == isLabel; } @@ -370,11 +348,6 @@ /// virtual unsigned SizeOf(const TargetData *TD, unsigned Form) const; - /// Profile - Used to gather unique data for the value folding set. - /// - static void Profile(FoldingSetNodeID &ID, const std::string &Label); - virtual void Profile(FoldingSetNodeID &ID); - // Implement isa/cast/dyncast. static bool classof(const DIEObjectLabel *) { return true; } static bool classof(const DIEValue *L) { @@ -408,12 +381,6 @@ /// virtual unsigned SizeOf(const TargetData *TD, unsigned Form) const; - /// Profile - Used to gather unique data for the value folding set. - /// - static void Profile(FoldingSetNodeID &ID, const DWLabel &Label, - const DWLabel &Section); - virtual void Profile(FoldingSetNodeID &ID); - // Implement isa/cast/dyncast. static bool classof(const DIESectionOffset *) { return true; } static bool classof(const DIEValue *D) { @@ -443,12 +410,6 @@ /// virtual unsigned SizeOf(const TargetData *TD, unsigned Form) const; - /// Profile - Used to gather unique data for the value folding set. - /// - static void Profile(FoldingSetNodeID &ID, const DWLabel &LabelHi, - const DWLabel &LabelLo); - virtual void Profile(FoldingSetNodeID &ID); - // Implement isa/cast/dyncast. static bool classof(const DIEDelta *) { return true; } static bool classof(const DIEValue *D) { return D->getType() == isDelta; } @@ -480,11 +441,6 @@ return sizeof(int32_t); } - /// Profile - Used to gather unique data for the value folding set. - /// - static void Profile(FoldingSetNodeID &ID, DIE *Entry); - virtual void Profile(FoldingSetNodeID &ID); - // Implement isa/cast/dyncast. static bool classof(const DIEEntry *) { return true; } static bool classof(const DIEValue *E) { return E->getType() == isEntry; } @@ -525,10 +481,6 @@ /// virtual unsigned SizeOf(const TargetData *TD, unsigned Form) const; - /// Profile - Used to gather unique data for the value folding set. - /// - virtual void Profile(FoldingSetNodeID &ID); - // Implement isa/cast/dyncast. static bool classof(const DIEBlock *) { return true; } static bool classof(const DIEValue *E) { return E->getType() == isBlock; } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=89518&r1=89517&r2=89518&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri Nov 20 18:31:03 2009 @@ -39,9 +39,7 @@ /// Configuration values for initial hash set sizes (log2). /// -static const unsigned InitDiesSetSize = 9; // log2(512) static const unsigned InitAbbreviationsSetSize = 9; // log2(512) -static const unsigned InitValuesSetSize = 9; // log2(512) namespace llvm { @@ -57,6 +55,9 @@ /// DIE *Die; + /// IndexTyDie - An anonymous type for index type. + DIE *IndexTyDie; + /// GVToDieMap - Tracks the mapping of unit level debug informaton /// variables to debug information entries. /// FIXME : Rename GVToDieMap -> NodeToDieMap @@ -71,13 +72,10 @@ /// StringMap Globals; - /// DiesSet - Used to uniquely define dies within the compile unit. - /// - FoldingSet DiesSet; public: CompileUnit(unsigned I, DIE *D) - : ID(I), Die(D), DiesSet(InitDiesSetSize) {} - ~CompileUnit() { delete Die; } + : ID(I), Die(D), IndexTyDie(0) {} + ~CompileUnit() { delete Die; delete IndexTyDie; } // Accessors. unsigned getID() const { return ID; } @@ -112,21 +110,20 @@ /// AddDie - Adds or interns the DIE to the compile unit. /// - DIE *AddDie(DIE &Buffer) { - FoldingSetNodeID ID; - Buffer.Profile(ID); - void *Where; - DIE *Die = DiesSet.FindNodeOrInsertPos(ID, Where); - - if (!Die) { - Die = new DIE(Buffer); - DiesSet.InsertNode(Die, Where); - this->Die->AddChild(Die); - Buffer.Detach(); - } + void AddDie(DIE *Buffer) { + this->Die->AddChild(Buffer); + } - return Die; + // getIndexTyDie - Get an anonymous type for index type. + DIE *getIndexTyDie() { + return IndexTyDie; } + + // setIndexTyDie - Set D as anonymous type for index which can be reused later. + void setIndexTyDie(DIE *D) { + IndexTyDie = D; + } + }; //===----------------------------------------------------------------------===// @@ -271,7 +268,7 @@ DwarfDebug::DwarfDebug(raw_ostream &OS, AsmPrinter *A, const MCAsmInfo *T) : Dwarf(OS, A, T, "dbg"), ModuleCU(0), AbbreviationsSet(InitAbbreviationsSetSize), Abbreviations(), - ValuesSet(InitValuesSetSize), Values(), StringPool(), + Values(), StringPool(), SectionSourceLines(), didInitial(false), shouldEmit(false), CurrentFnDbgScope(0), DebugTimer(0) { if (TimePassesIsEnabled) @@ -311,22 +308,7 @@ /// CreateDIEEntry - Creates a new DIEEntry to be a proxy for a debug /// information entry. DIEEntry *DwarfDebug::CreateDIEEntry(DIE *Entry) { - DIEEntry *Value; - - if (Entry) { - FoldingSetNodeID ID; - DIEEntry::Profile(ID, Entry); - void *Where; - Value = static_cast(ValuesSet.FindNodeOrInsertPos(ID, Where)); - - if (Value) return Value; - - Value = new DIEEntry(Entry); - ValuesSet.InsertNode(Value, Where); - } else { - Value = new DIEEntry(Entry); - } - + DIEEntry *Value = new DIEEntry(Entry); Values.push_back(Value); return Value; } @@ -335,10 +317,6 @@ /// void DwarfDebug::SetDIEEntry(DIEEntry *Value, DIE *Entry) { Value->setEntry(Entry); - - // Add to values set if not already there. If it is, we merely have a - // duplicate in the values list (no harm.) - ValuesSet.GetOrInsertNode(Value); } /// AddUInt - Add an unsigned integer attribute data and value. @@ -346,18 +324,8 @@ void DwarfDebug::AddUInt(DIE *Die, unsigned Attribute, unsigned Form, uint64_t Integer) { if (!Form) Form = DIEInteger::BestForm(false, Integer); - - FoldingSetNodeID ID; - DIEInteger::Profile(ID, Integer); - void *Where; - DIEValue *Value = ValuesSet.FindNodeOrInsertPos(ID, Where); - - if (!Value) { - Value = new DIEInteger(Integer); - ValuesSet.InsertNode(Value, Where); - Values.push_back(Value); - } - + DIEValue *Value = new DIEInteger(Integer); + Values.push_back(Value); Die->AddValue(Attribute, Form, Value); } @@ -366,18 +334,8 @@ void DwarfDebug::AddSInt(DIE *Die, unsigned Attribute, unsigned Form, int64_t Integer) { if (!Form) Form = DIEInteger::BestForm(true, Integer); - - FoldingSetNodeID ID; - DIEInteger::Profile(ID, (uint64_t)Integer); - void *Where; - DIEValue *Value = ValuesSet.FindNodeOrInsertPos(ID, Where); - - if (!Value) { - Value = new DIEInteger(Integer); - ValuesSet.InsertNode(Value, Where); - Values.push_back(Value); - } - + DIEValue *Value = new DIEInteger(Integer); + Values.push_back(Value); Die->AddValue(Attribute, Form, Value); } @@ -385,17 +343,8 @@ /// void DwarfDebug::AddString(DIE *Die, unsigned Attribute, unsigned Form, const std::string &String) { - FoldingSetNodeID ID; - DIEString::Profile(ID, String); - void *Where; - DIEValue *Value = ValuesSet.FindNodeOrInsertPos(ID, Where); - - if (!Value) { - Value = new DIEString(String); - ValuesSet.InsertNode(Value, Where); - Values.push_back(Value); - } - + DIEValue *Value = new DIEString(String); + Values.push_back(Value); Die->AddValue(Attribute, Form, Value); } @@ -403,17 +352,8 @@ /// void DwarfDebug::AddLabel(DIE *Die, unsigned Attribute, unsigned Form, const DWLabel &Label) { - FoldingSetNodeID ID; - DIEDwarfLabel::Profile(ID, Label); - void *Where; - DIEValue *Value = ValuesSet.FindNodeOrInsertPos(ID, Where); - - if (!Value) { - Value = new DIEDwarfLabel(Label); - ValuesSet.InsertNode(Value, Where); - Values.push_back(Value); - } - + DIEValue *Value = new DIEDwarfLabel(Label); + Values.push_back(Value); Die->AddValue(Attribute, Form, Value); } @@ -421,17 +361,8 @@ /// void DwarfDebug::AddObjectLabel(DIE *Die, unsigned Attribute, unsigned Form, const std::string &Label) { - FoldingSetNodeID ID; - DIEObjectLabel::Profile(ID, Label); - void *Where; - DIEValue *Value = ValuesSet.FindNodeOrInsertPos(ID, Where); - - if (!Value) { - Value = new DIEObjectLabel(Label); - ValuesSet.InsertNode(Value, Where); - Values.push_back(Value); - } - + DIEValue *Value = new DIEObjectLabel(Label); + Values.push_back(Value); Die->AddValue(Attribute, Form, Value); } @@ -440,17 +371,8 @@ void DwarfDebug::AddSectionOffset(DIE *Die, unsigned Attribute, unsigned Form, const DWLabel &Label, const DWLabel &Section, bool isEH, bool useSet) { - FoldingSetNodeID ID; - DIESectionOffset::Profile(ID, Label, Section); - void *Where; - DIEValue *Value = ValuesSet.FindNodeOrInsertPos(ID, Where); - - if (!Value) { - Value = new DIESectionOffset(Label, Section, isEH, useSet); - ValuesSet.InsertNode(Value, Where); - Values.push_back(Value); - } - + DIEValue *Value = new DIESectionOffset(Label, Section, isEH, useSet); + Values.push_back(Value); Die->AddValue(Attribute, Form, Value); } @@ -458,17 +380,8 @@ /// void DwarfDebug::AddDelta(DIE *Die, unsigned Attribute, unsigned Form, const DWLabel &Hi, const DWLabel &Lo) { - FoldingSetNodeID ID; - DIEDelta::Profile(ID, Hi, Lo); - void *Where; - DIEValue *Value = ValuesSet.FindNodeOrInsertPos(ID, Where); - - if (!Value) { - Value = new DIEDelta(Hi, Lo); - ValuesSet.InsertNode(Value, Where); - Values.push_back(Value); - } - + DIEValue *Value = new DIEDelta(Hi, Lo); + Values.push_back(Value); Die->AddValue(Attribute, Form, Value); } @@ -477,22 +390,8 @@ void DwarfDebug::AddBlock(DIE *Die, unsigned Attribute, unsigned Form, DIEBlock *Block) { Block->ComputeSize(TD); - FoldingSetNodeID ID; - Block->Profile(ID); - void *Where; - DIEValue *Value = ValuesSet.FindNodeOrInsertPos(ID, Where); - - if (!Value) { - Value = Block; - ValuesSet.InsertNode(Value, Where); - Values.push_back(Value); - } else { - // Already exists, reuse the previous one. - delete Block; - Block = cast(Value); - } - - Die->AddValue(Attribute, Block->BestForm(), Value); + Values.push_back(Block); + Die->AddValue(Attribute, Block->BestForm(), Block); } /// AddSourceLine - Add location information to specified debug information @@ -867,14 +766,14 @@ DW_Unit->insertDIEEntry(Ty.getNode(), Slot); // Construct type. - DIE Buffer(dwarf::DW_TAG_base_type); + DIE *Buffer = new DIE(dwarf::DW_TAG_base_type); if (Ty.isBasicType()) - ConstructTypeDIE(DW_Unit, Buffer, DIBasicType(Ty.getNode())); + ConstructTypeDIE(DW_Unit, *Buffer, DIBasicType(Ty.getNode())); else if (Ty.isCompositeType()) - ConstructTypeDIE(DW_Unit, Buffer, DICompositeType(Ty.getNode())); + ConstructTypeDIE(DW_Unit, *Buffer, DICompositeType(Ty.getNode())); else { assert(Ty.isDerivedType() && "Unknown kind of DIType"); - ConstructTypeDIE(DW_Unit, Buffer, DIDerivedType(Ty.getNode())); + ConstructTypeDIE(DW_Unit, *Buffer, DIDerivedType(Ty.getNode())); } // Add debug information entry to entity and appropriate context. @@ -883,16 +782,11 @@ if (!Context.isNull()) Die = DW_Unit->getDIE(Context.getNode()); - if (Die) { - DIE *Child = new DIE(Buffer); - Die->AddChild(Child); - Buffer.Detach(); - SetDIEEntry(Slot, Child); - } else { - Die = DW_Unit->AddDie(Buffer); - SetDIEEntry(Slot, Die); - } - + if (Die) + Die->AddChild(Buffer); + else + DW_Unit->AddDie(Buffer); + SetDIEEntry(Slot, Buffer); Entity->AddValue(dwarf::DW_AT_type, dwarf::DW_FORM_ref4, Slot); } @@ -1076,18 +970,23 @@ AddType(DW_Unit, &Buffer, CTy->getTypeDerivedFrom()); DIArray Elements = CTy->getTypeArray(); - // Construct an anonymous type for index type. - DIE IdxBuffer(dwarf::DW_TAG_base_type); - AddUInt(&IdxBuffer, dwarf::DW_AT_byte_size, 0, sizeof(int32_t)); - AddUInt(&IdxBuffer, dwarf::DW_AT_encoding, dwarf::DW_FORM_data1, - dwarf::DW_ATE_signed); - DIE *IndexTy = DW_Unit->AddDie(IdxBuffer); + // Get an anonymous type for index type. + DIE *IdxTy = DW_Unit->getIndexTyDie(); + if (!IdxTy) { + // Construct an anonymous type for index type. + IdxTy = new DIE(dwarf::DW_TAG_base_type); + AddUInt(IdxTy, dwarf::DW_AT_byte_size, 0, sizeof(int32_t)); + AddUInt(IdxTy, dwarf::DW_AT_encoding, dwarf::DW_FORM_data1, + dwarf::DW_ATE_signed); + DW_Unit->AddDie(IdxTy); + DW_Unit->setIndexTyDie(IdxTy); + } // Add subranges to array type. for (unsigned i = 0, N = Elements.getNumElements(); i < N; ++i) { DIDescriptor Element = Elements.getElement(i); if (Element.getTag() == dwarf::DW_TAG_subrange_type) - ConstructSubrangeDIE(Buffer, DISubrange(Element.getNode()), IndexTy); + ConstructSubrangeDIE(Buffer, DISubrange(Element.getNode()), IdxTy); } } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=89518&r1=89517&r2=89518&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Fri Nov 20 18:31:03 2009 @@ -106,10 +106,6 @@ /// Lines - List of of source line correspondence. std::vector Lines; - /// ValuesSet - Used to uniquely define values. - /// - FoldingSet ValuesSet; - /// Values - A list of all the unique values in use. /// std::vector Values; From dalej at apple.com Fri Nov 20 18:53:23 2009 From: dalej at apple.com (Dale Johannesen) Date: Sat, 21 Nov 2009 00:53:23 -0000 Subject: [llvm-commits] [llvm] r89521 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/PowerPC/vec_buildvector_loadstore.ll Message-ID: <200911210053.nAL0rNaV029570@zion.cs.uiuc.edu> Author: johannes Date: Fri Nov 20 18:53:23 2009 New Revision: 89521 URL: http://llvm.org/viewvc/llvm-project?rev=89521&view=rev Log: When generating a vector the really slow way, via loads and stores, handle the case where the element size is not a valid target type correctly (PPC). Added: llvm/trunk/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=89521&r1=89520&r2=89521&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Nov 20 18:53:23 2009 @@ -1517,6 +1517,7 @@ // Create the stack frame object. EVT VT = Node->getValueType(0); EVT OpVT = Node->getOperand(0).getValueType(); + EVT EltVT = VT.getVectorElementType(); DebugLoc dl = Node->getDebugLoc(); SDValue FIPtr = DAG.CreateStackTemporary(VT); int FI = cast(FIPtr.getNode())->getIndex(); @@ -1524,7 +1525,7 @@ // Emit a store of each element to the stack slot. SmallVector Stores; - unsigned TypeByteSize = OpVT.getSizeInBits() / 8; + unsigned TypeByteSize = EltVT.getSizeInBits() / 8; // Store (in the right endianness) the elements to memory. for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { // Ignore undef elements. @@ -1535,8 +1536,13 @@ SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); - Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i), - Idx, SV, Offset)); + // If EltVT smaller than OpVT, only store the bits necessary. + if (EltVT.bitsLT(OpVT)) + Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, + Node->getOperand(i), Idx, SV, Offset, EltVT)); + else + Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, + Node->getOperand(i), Idx, SV, Offset)); } SDValue StoreChain; Added: llvm/trunk/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll?rev=89521&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll (added) +++ llvm/trunk/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll Fri Nov 20 18:53:23 2009 @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mattr=+altivec | FileCheck %s +; Formerly this did byte loads and word stores. + at a = external global <16 x i8> + at b = external global <16 x i8> + at c = external global <16 x i8> + +define void @foo() nounwind ssp { +; CHECK: _foo: +; CHECK-NOT: stw +entry: + %tmp0 = load <16 x i8>* @a, align 16 + %tmp180.i = extractelement <16 x i8> %tmp0, i32 0 ; [#uses=1] + %tmp181.i = insertelement <16 x i8> , i8 %tmp180.i, i32 2 ; <<16 x i8>> [#uses=1] + %tmp182.i = extractelement <16 x i8> %tmp0, i32 1 ; [#uses=1] + %tmp183.i = insertelement <16 x i8> %tmp181.i, i8 %tmp182.i, i32 3 ; <<16 x i8>> [#uses=1] + %tmp184.i = insertelement <16 x i8> %tmp183.i, i8 0, i32 4 ; <<16 x i8>> [#uses=1] + %tmp185.i = insertelement <16 x i8> %tmp184.i, i8 0, i32 5 ; <<16 x i8>> [#uses=1] + %tmp186.i = extractelement <16 x i8> %tmp0, i32 4 ; [#uses=1] + %tmp187.i = insertelement <16 x i8> %tmp185.i, i8 %tmp186.i, i32 6 ; <<16 x i8>> [#uses=1] + %tmp188.i = extractelement <16 x i8> %tmp0, i32 5 ; [#uses=1] + %tmp189.i = insertelement <16 x i8> %tmp187.i, i8 %tmp188.i, i32 7 ; <<16 x i8>> [#uses=1] + %tmp190.i = insertelement <16 x i8> %tmp189.i, i8 0, i32 8 ; <<16 x i8>> [#uses=1] + %tmp191.i = insertelement <16 x i8> %tmp190.i, i8 0, i32 9 ; <<16 x i8>> [#uses=1] + %tmp192.i = extractelement <16 x i8> %tmp0, i32 8 ; [#uses=1] + %tmp193.i = insertelement <16 x i8> %tmp191.i, i8 %tmp192.i, i32 10 ; <<16 x i8>> [#uses=1] + %tmp194.i = extractelement <16 x i8> %tmp0, i32 9 ; [#uses=1] + %tmp195.i = insertelement <16 x i8> %tmp193.i, i8 %tmp194.i, i32 11 ; <<16 x i8>> [#uses=1] + %tmp196.i = insertelement <16 x i8> %tmp195.i, i8 0, i32 12 ; <<16 x i8>> [#uses=1] + %tmp197.i = insertelement <16 x i8> %tmp196.i, i8 0, i32 13 ; <<16 x i8>> [#uses=1] +%tmp201 = shufflevector <16 x i8> %tmp197.i, <16 x i8> %tmp0, <16 x i32> ; ModuleID = 'try.c' + store <16 x i8> %tmp201, <16 x i8>* @c, align 16 + br label %return + +return: ; preds = %bb2 + ret void +; CHECK: blr +} From dpatel at apple.com Fri Nov 20 18:54:03 2009 From: dpatel at apple.com (Devang Patel) Date: Sat, 21 Nov 2009 00:54:03 -0000 Subject: [llvm-commits] [llvm] r89522 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <200911210054.nAL0s3lc029603@zion.cs.uiuc.edu> Author: dpatel Date: Fri Nov 20 18:54:03 2009 New Revision: 89522 URL: http://llvm.org/viewvc/llvm-project?rev=89522&view=rev Log: Remove dead code. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=89522&r1=89521&r2=89522&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri Nov 20 18:54:03 2009 @@ -241,21 +241,6 @@ } #endif -//===----------------------------------------------------------------------===// -/// DbgConcreteScope - This class is used to track a scope that holds concrete -/// instance information. -/// -class DbgConcreteScope : public DbgScope { - CompileUnit *Unit; - DIE *Die; // Debug info for this concrete scope. -public: - DbgConcreteScope(DIDescriptor D) : DbgScope(NULL, D) {} - - // Accessors. - DIE *getDie() const { return Die; } - void setDie(DIE *D) { Die = D; } -}; - DbgScope::~DbgScope() { for (unsigned i = 0, N = Scopes.size(); i < N; ++i) delete Scopes[i]; From echristo at apple.com Fri Nov 20 19:01:30 2009 From: echristo at apple.com (Eric Christopher) Date: Sat, 21 Nov 2009 01:01:30 -0000 Subject: [llvm-commits] [llvm] r89523 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Message-ID: <200911210101.nAL11UDE029891@zion.cs.uiuc.edu> Author: echristo Date: Fri Nov 20 19:01:30 2009 New Revision: 89523 URL: http://llvm.org/viewvc/llvm-project?rev=89523&view=rev Log: Add more optimizations for object size checking, enable handling of object size intrinsic and verify return type is correct. Collect various code in one place. Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=89523&r1=89522&r2=89523&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Fri Nov 20 19:01:30 2009 @@ -81,6 +81,11 @@ Value *EmitMemCpy(Value *Dst, Value *Src, Value *Len, unsigned Align, IRBuilder<> &B); + /// EmitMemMove - Emit a call to the memmove function to the builder. This + /// always expects that the size has type 'intptr_t' and Dst/Src are pointers. + Value *EmitMemMove(Value *Dst, Value *Src, Value *Len, + unsigned Align, IRBuilder<> &B); + /// EmitMemChr - Emit a call to the memchr function. This assumes that Ptr is /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. Value *EmitMemChr(Value *Ptr, Value *Val, Value *Len, IRBuilder<> &B); @@ -160,6 +165,21 @@ ConstantInt::get(Type::getInt32Ty(*Context), Align)); } +/// EmitMemMOve - Emit a call to the memmove function to the builder. This +/// always expects that the size has type 'intptr_t' and Dst/Src are pointers. +Value *LibCallOptimization::EmitMemMove(Value *Dst, Value *Src, Value *Len, + unsigned Align, IRBuilder<> &B) { + Module *M = Caller->getParent(); + Intrinsic::ID IID = Intrinsic::memmove; + const Type *Tys[1]; + Tys[0] = TD->getIntPtrType(*Context); + Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); + Value *D = CastToCStr(Dst, B); + Value *S = CastToCStr(Src, B); + Value *A = ConstantInt::get(Type::getInt32Ty(*Context), Align); + return B.CreateCall4(MemMove, D, S, Len, A); +} + /// EmitMemChr - Emit a call to the memchr function. This assumes that Ptr is /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. Value *LibCallOptimization::EmitMemChr(Value *Ptr, Value *Val, @@ -512,27 +532,6 @@ } //===----------------------------------------------------------------------===// -// Miscellaneous LibCall/Intrinsic Optimizations -//===----------------------------------------------------------------------===// - -namespace { -struct SizeOpt : public LibCallOptimization { - virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { - // TODO: We can do more with this, but delaying to here should be no change - // in behavior. - ConstantInt *Const = dyn_cast(CI->getOperand(2)); - - if (!Const) return 0; - - if (Const->getZExtValue() < 2) - return Constant::getAllOnesValue(Const->getType()); - else - return ConstantInt::get(Const->getType(), 0); - } -}; -} - -//===----------------------------------------------------------------------===// // String and Memory LibCall Optimizations //===----------------------------------------------------------------------===// @@ -1010,16 +1009,7 @@ return 0; // memmove(x, y, n) -> llvm.memmove(x, y, n, 1) - Module *M = Caller->getParent(); - Intrinsic::ID IID = Intrinsic::memmove; - const Type *Tys[1]; - Tys[0] = TD->getIntPtrType(*Context); - Value *MemMove = Intrinsic::getDeclaration(M, IID, Tys, 1); - Value *Dst = CastToCStr(CI->getOperand(1), B); - Value *Src = CastToCStr(CI->getOperand(2), B); - Value *Size = CI->getOperand(3); - Value *Align = ConstantInt::get(Type::getInt32Ty(*Context), 1); - B.CreateCall4(MemMove, Dst, Src, Size, Align); + EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3), 1, B); return CI->getOperand(1); } }; @@ -1048,6 +1038,118 @@ }; //===----------------------------------------------------------------------===// +// Object Size Checking Optimizations +//===----------------------------------------------------------------------===// + +//===---------------------------------------===// +// 'object size' +namespace { +struct SizeOpt : public LibCallOptimization { + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { + // TODO: We can do more with this, but delaying to here should be no change + // in behavior. + ConstantInt *Const = dyn_cast(CI->getOperand(2)); + + if (!Const) return 0; + + const Type *Ty = Callee->getFunctionType()->getReturnType(); + + if (Const->getZExtValue() < 2) + return Constant::getAllOnesValue(Ty); + else + return ConstantInt::get(Ty, 0); + } +}; +} + +//===---------------------------------------===// +// 'memcpy_chk' Optimizations + +struct MemCpyChkOpt : public LibCallOptimization { + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { + // These optimizations require TargetData. + if (!TD) return 0; + + const FunctionType *FT = Callee->getFunctionType(); + if (FT->getNumParams() != 4 || FT->getReturnType() != FT->getParamType(0) || + !isa(FT->getParamType(0)) || + !isa(FT->getParamType(1)) || + !isa(FT->getParamType(3)) || + FT->getParamType(2) != TD->getIntPtrType(*Context)) + return 0; + + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); + if (!SizeCI) + return 0; + if (SizeCI->isAllOnesValue()) { + EmitMemCpy(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3), 1, B); + return CI->getOperand(1); + } + + return 0; + } +}; + +//===---------------------------------------===// +// 'memset_chk' Optimizations + +struct MemSetChkOpt : public LibCallOptimization { + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { + // These optimizations require TargetData. + if (!TD) return 0; + + const FunctionType *FT = Callee->getFunctionType(); + if (FT->getNumParams() != 4 || FT->getReturnType() != FT->getParamType(0) || + !isa(FT->getParamType(0)) || + !isa(FT->getParamType(1)) || + !isa(FT->getParamType(3)) || + FT->getParamType(2) != TD->getIntPtrType(*Context)) + return 0; + + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); + if (!SizeCI) + return 0; + if (SizeCI->isAllOnesValue()) { + Value *Val = B.CreateIntCast(CI->getOperand(2), Type::getInt8Ty(*Context), + false); + EmitMemSet(CI->getOperand(1), Val, CI->getOperand(3), B); + return CI->getOperand(1); + } + + return 0; + } +}; + +//===---------------------------------------===// +// 'memmove_chk' Optimizations + +struct MemMoveChkOpt : public LibCallOptimization { + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { + // These optimizations require TargetData. + if (!TD) return 0; + + const FunctionType *FT = Callee->getFunctionType(); + if (FT->getNumParams() != 4 || FT->getReturnType() != FT->getParamType(0) || + !isa(FT->getParamType(0)) || + !isa(FT->getParamType(1)) || + !isa(FT->getParamType(3)) || + FT->getParamType(2) != TD->getIntPtrType(*Context)) + return 0; + + ConstantInt *SizeCI = dyn_cast(CI->getOperand(4)); + if (!SizeCI) + return 0; + if (SizeCI->isAllOnesValue()) { + EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3), + 1, B); + return CI->getOperand(1); + } + + return 0; + } +}; + +//===----------------------------------------------------------------------===// // Math Library Optimizations //===----------------------------------------------------------------------===// @@ -1356,7 +1458,7 @@ if (FormatStr == "%c" && CI->getNumOperands() > 2 && isa(CI->getOperand(2)->getType())) { Value *Res = EmitPutChar(CI->getOperand(2), B); - + if (CI->use_empty()) return CI; return B.CreateIntCast(Res, CI->getType(), true); } @@ -1586,7 +1688,10 @@ // Formatting and IO Optimizations SPrintFOpt SPrintF; PrintFOpt PrintF; FWriteOpt FWrite; FPutsOpt FPuts; FPrintFOpt FPrintF; + + // Object Size Checking SizeOpt ObjectSize; + MemCpyChkOpt MemCpyChk; MemSetChkOpt MemSetChk; MemMoveChkOpt MemMoveChk; bool Modified; // This is only used by doInitialization. public: @@ -1692,9 +1797,13 @@ Optimizations["fwrite"] = &FWrite; Optimizations["fputs"] = &FPuts; Optimizations["fprintf"] = &FPrintF; - - // Miscellaneous - Optimizations["llvm.objectsize"] = &ObjectSize; + + // Object Size Checking + Optimizations["llvm.objectsize.i32"] = &ObjectSize; + Optimizations["llvm.objectsize.i64"] = &ObjectSize; + Optimizations["__memcpy_chk"] = &MemCpyChk; + Optimizations["__memset_chk"] = &MemSetChk; + Optimizations["__memmove_chk"] = &MemMoveChk; } From echristo at apple.com Fri Nov 20 19:08:00 2009 From: echristo at apple.com (Eric Christopher) Date: Fri, 20 Nov 2009 17:08:00 -0800 Subject: [llvm-commits] [PATCH] Allow more than one stub to be being generated at the same time In-Reply-To: <0016e6470f36b3b16f04789c9bae@google.com> References: <0016e6470f36b3b16f04789c9bae@google.com> Message-ID: <1A9CE212-1898-4367-9313-5D4F2043F64B@apple.com> On Nov 17, 2009, at 7:12 PM, jyasskin at gmail.com wrote: > Reviewers: echristo_apple.com, > > Message: > This will make it easier to fix a mistake I made in > http://codereview.appspot.com/153044. > > http://codereview.appspot.com/download/issue156053_9.diff > > Looks ok to me. -eric From echristo at apple.com Fri Nov 20 19:08:25 2009 From: echristo at apple.com (Eric Christopher) Date: Fri, 20 Nov 2009 17:08:25 -0800 Subject: [llvm-commits] [PATCH] Move stub allocation to the JITEmitter In-Reply-To: References: <0016e6470f36c55e08047834fde7@google.com> Message-ID: On Nov 17, 2009, at 10:07 PM, Jeffrey Yasskin wrote: > > http://codereview.appspot.com/153044 has the current patch + the > multiple-stubs fix. I'll merge once I commit that one. Go ahead and commit, I've looked at both :) -eric From daniel at zuster.org Fri Nov 20 20:01:24 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sat, 21 Nov 2009 02:01:24 -0000 Subject: [llvm-commits] [llvm] r89529 - /llvm/trunk/include/llvm/ADT/SmallString.h Message-ID: <200911210201.nAL21ODo031854@zion.cs.uiuc.edu> Author: ddunbar Date: Fri Nov 20 20:01:24 2009 New Revision: 89529 URL: http://llvm.org/viewvc/llvm-project?rev=89529&view=rev Log: Allow SmallString to implicitly convert to StringRef. Modified: llvm/trunk/include/llvm/ADT/SmallString.h Modified: llvm/trunk/include/llvm/ADT/SmallString.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallString.h?rev=89529&r1=89528&r2=89529&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/SmallString.h (original) +++ llvm/trunk/include/llvm/ADT/SmallString.h Fri Nov 20 20:01:24 2009 @@ -38,12 +38,15 @@ // Extra methods. StringRef str() const { return StringRef(this->begin(), this->size()); } + // Implicit conversion to StringRef. + operator StringRef() const { return str(); } + const char *c_str() { this->push_back(0); this->pop_back(); return this->data(); } - + // Extra operators. const SmallString &operator=(StringRef RHS) { this->clear(); From stoklund at 2pi.dk Fri Nov 20 20:05:22 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 21 Nov 2009 02:05:22 -0000 Subject: [llvm-commits] [llvm] r89530 - in /llvm/trunk: include/llvm/CodeGen/LiveVariables.h lib/CodeGen/LiveVariables.cpp lib/CodeGen/PHIElimination.cpp lib/CodeGen/PHIElimination.h Message-ID: <200911210205.nAL25M36031984@zion.cs.uiuc.edu> Author: stoklund Date: Fri Nov 20 20:05:21 2009 New Revision: 89530 URL: http://llvm.org/viewvc/llvm-project?rev=89530&view=rev Log: Be more clever about calculating live variables through new basic blocks. When splitting a critical edge, the registers live through the edge are: - Used in a PHI instruction, or - Live out from the predecessor, and - Live in to the successor. This allows the coalescer to eliminate even more phi joins. Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h llvm/trunk/lib/CodeGen/LiveVariables.cpp llvm/trunk/lib/CodeGen/PHIElimination.cpp llvm/trunk/lib/CodeGen/PHIElimination.h Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveVariables.h?rev=89530&r1=89529&r2=89530&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveVariables.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveVariables.h Fri Nov 20 20:05:21 2009 @@ -107,6 +107,13 @@ /// findKill - Find a kill instruction in MBB. Return NULL if none is found. MachineInstr *findKill(const MachineBasicBlock *MBB) const; + /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through + /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in + /// MBB, it is not considered live in. + bool isLiveIn(const MachineBasicBlock &MBB, + unsigned Reg, + MachineRegisterInfo &MRI); + void dump() const; }; @@ -267,11 +274,17 @@ void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, MachineInstr *MI); - /// addNewBlock - Add a new basic block BB as an empty succcessor to - /// DomBB. All variables that are live out of DomBB will be marked as passing - /// live through BB. This method assumes that the machine code is still in SSA - /// form. - void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB); + bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) { + return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI); + } + + /// addNewBlock - Add a new basic block BB between DomBB and SuccBB. All + /// variables that are live out of DomBB and live into SuccBB will be marked + /// as passing live through BB. This method assumes that the machine code is + /// still in SSA form. + void addNewBlock(MachineBasicBlock *BB, + MachineBasicBlock *DomBB, + MachineBasicBlock *SuccBB); }; } // End llvm namespace Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=89530&r1=89529&r2=89530&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Fri Nov 20 20:05:21 2009 @@ -656,35 +656,45 @@ .push_back(BBI->getOperand(i).getReg()); } +bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB, + unsigned Reg, + MachineRegisterInfo &MRI) { + unsigned Num = MBB.getNumber(); + + // Reg is live-through. + if (AliveBlocks.test(Num)) + return true; + + // Registers defined in MBB cannot be live in. + const MachineInstr *Def = MRI.getVRegDef(Reg); + if (Def && Def->getParent() == &MBB) + return false; + + // Reg was not defined in MBB, was it killed here? + return findKill(&MBB); +} + /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All /// variables that are live out of DomBB will be marked as passing live through /// BB. void LiveVariables::addNewBlock(MachineBasicBlock *BB, - MachineBasicBlock *DomBB) { + MachineBasicBlock *DomBB, + MachineBasicBlock *SuccBB) { const unsigned NumNew = BB->getNumber(); - const unsigned NumDom = DomBB->getNumber(); + + // All registers used by PHI nodes in SuccBB must be live through BB. + for (MachineBasicBlock::const_iterator BBI = SuccBB->begin(), + BBE = SuccBB->end(); + BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) + for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) + if (BBI->getOperand(i+1).getMBB() == BB) + getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew); // Update info for all live variables for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister, E = MRI->getLastVirtReg()+1; Reg != E; ++Reg) { VarInfo &VI = getVarInfo(Reg); - - // Anything live through DomBB is also live through BB. - if (VI.AliveBlocks.test(NumDom)) { + if (!VI.AliveBlocks.test(NumNew) && VI.isLiveIn(*SuccBB, Reg, *MRI)) VI.AliveBlocks.set(NumNew); - continue; - } - - // Variables not defined in DomBB cannot be live out. - const MachineInstr *Def = MRI->getVRegDef(Reg); - if (!Def || Def->getParent() != DomBB) - continue; - - // Killed by DomBB? - if (VI.findKill(DomBB)) - continue; - - // This register is defined in DomBB and live out - VI.AliveBlocks.set(NumNew); } } Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89530&r1=89529&r2=89530&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Fri Nov 20 20:05:21 2009 @@ -353,7 +353,7 @@ // We break edges when registers are live out from the predecessor block // (not considering PHI nodes). If the register is live in to this block // anyway, we would gain nothing from splitting. - if (isLiveOut(Reg, *PreMBB, LV) && !isLiveIn(Reg, MBB, LV)) + if (!LV.isLiveIn(Reg, MBB) && isLiveOut(Reg, *PreMBB, LV)) SplitCriticalEdge(PreMBB, &MBB); } } @@ -406,22 +406,6 @@ return false; } -bool llvm::PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock &MBB, - LiveVariables &LV) { - LiveVariables::VarInfo &VI = LV.getVarInfo(Reg); - - if (VI.AliveBlocks.test(MBB.getNumber())) - return true; - - // defined in MBB? - const MachineInstr *Def = MRI->getVRegDef(Reg); - if (Def && Def->getParent() == &MBB) - return false; - - // killed in MBB? - return VI.findKill(&MBB); -} - MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A, MachineBasicBlock *B) { assert(A && B && "Missing MBB end point"); @@ -463,7 +447,7 @@ i->getOperand(ni+1).setMBB(NMBB); if (LiveVariables *LV=getAnalysisIfAvailable()) - LV->addNewBlock(NMBB, A); + LV->addNewBlock(NMBB, A, B); if (MachineDominatorTree *MDT=getAnalysisIfAvailable()) MDT->addNewBlock(NMBB, A); Modified: llvm/trunk/lib/CodeGen/PHIElimination.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.h?rev=89530&r1=89529&r2=89530&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.h (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.h Fri Nov 20 20:05:21 2009 @@ -99,12 +99,6 @@ bool isLiveOut(unsigned Reg, const MachineBasicBlock &MBB, LiveVariables &LV); - /// isLiveIn - Determine if Reg is live in to MBB, not considering PHI - /// source registers. This means that Reg is either killed by MBB or passes - /// through it. - bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB, - LiveVariables &LV); - /// SplitCriticalEdge - Split a critical edge from A to B by /// inserting a new MBB. Update branches in A and PHI instructions /// in B. Return the new block. From stoklund at 2pi.dk Fri Nov 20 20:05:31 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 21 Nov 2009 02:05:31 -0000 Subject: [llvm-commits] [llvm] r89531 - /llvm/trunk/test/CodeGen/Generic/2009-11-20-NewNode.ll Message-ID: <200911210205.nAL25VDp032003@zion.cs.uiuc.edu> Author: stoklund Date: Fri Nov 20 20:05:31 2009 New Revision: 89531 URL: http://llvm.org/viewvc/llvm-project?rev=89531&view=rev Log: Don't leave temporary files in the test directory. Modified: llvm/trunk/test/CodeGen/Generic/2009-11-20-NewNode.ll Modified: llvm/trunk/test/CodeGen/Generic/2009-11-20-NewNode.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2009-11-20-NewNode.ll?rev=89531&r1=89530&r2=89531&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2009-11-20-NewNode.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2009-11-20-NewNode.ll Fri Nov 20 20:05:31 2009 @@ -1,5 +1,5 @@ -; RUN: llc -march=msp430 %s -; RUN: llc -march=pic16 %s +; RUN: llc -march=msp430 < %s +; RUN: llc -march=pic16 < %s ; PR5558 define i64 @_strtoll_r(i16 %base) nounwind { From evan.cheng at apple.com Fri Nov 20 20:32:35 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 21 Nov 2009 02:32:35 -0000 Subject: [llvm-commits] [llvm] r89535 - /llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Message-ID: <200911210232.nAL2WZrN000395@zion.cs.uiuc.edu> Author: evancheng Date: Fri Nov 20 20:32:35 2009 New Revision: 89535 URL: http://llvm.org/viewvc/llvm-project?rev=89535&view=rev Log: Maintain stylistic consistency. Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=89535&r1=89534&r2=89535&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Fri Nov 20 20:32:35 2009 @@ -656,7 +656,9 @@ MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, - unsigned Reg) const {return false;} + unsigned Reg) const { + return false; + } /// eliminateFrameIndex - This method must be overriden to eliminate abstract /// frame indices from instructions which may use them. The instruction From dpatel at apple.com Fri Nov 20 20:46:56 2009 From: dpatel at apple.com (Devang Patel) Date: Sat, 21 Nov 2009 02:46:56 -0000 Subject: [llvm-commits] [llvm] r89536 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ lib/Target/XCore/ Message-ID: <200911210246.nAL2kvBW000834@zion.cs.uiuc.edu> Author: dpatel Date: Fri Nov 20 20:46:55 2009 New Revision: 89536 URL: http://llvm.org/viewvc/llvm-project?rev=89536&view=rev Log: We are not using DBG_STOPPOINT anymore. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=89536&r1=89535&r2=89536&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Fri Nov 20 20:46:55 2009 @@ -322,8 +322,6 @@ unsigned char TargetFlags = 0); SDValue getValueType(EVT); SDValue getRegister(unsigned Reg, EVT VT); - SDValue getDbgStopPoint(DebugLoc DL, SDValue Root, - unsigned Line, unsigned Col, MDNode *CU); SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root, unsigned LabelID); SDValue getBlockAddress(BlockAddress *BA, EVT VT, Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=89536&r1=89535&r2=89536&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Fri Nov 20 20:46:55 2009 @@ -546,12 +546,6 @@ // HANDLENODE node - Used as a handle for various purposes. HANDLENODE, - // DBG_STOPPOINT - This node is used to represent a source location for - // debug info. It takes token chain as input, and carries a line number, - // column number, and a pointer to a CompileUnit object identifying - // the containing compilation unit. It produces a token chain as output. - DBG_STOPPOINT, - // DEBUG_LOC - This node is used to represent source line information // embedded in the code. It takes a token chain as input, then a line // number, then a column then a file id (provided by MachineModuleInfo.) It @@ -2004,29 +1998,6 @@ } }; -class DbgStopPointSDNode : public SDNode { - SDUse Chain; - unsigned Line; - unsigned Column; - MDNode *CU; - friend class SelectionDAG; - DbgStopPointSDNode(SDValue ch, unsigned l, unsigned c, - MDNode *cu) - : SDNode(ISD::DBG_STOPPOINT, DebugLoc::getUnknownLoc(), - getSDVTList(MVT::Other)), Line(l), Column(c), CU(cu) { - InitOperands(&Chain, ch); - } -public: - unsigned getLine() const { return Line; } - unsigned getColumn() const { return Column; } - MDNode *getCompileUnit() const { return CU; } - - static bool classof(const DbgStopPointSDNode *) { return true; } - static bool classof(const SDNode *N) { - return N->getOpcode() == ISD::DBG_STOPPOINT; - } -}; - class BlockAddressSDNode : public SDNode { BlockAddress *BA; unsigned char TargetFlags; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=89536&r1=89535&r2=89536&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Nov 20 20:46:55 2009 @@ -158,7 +158,6 @@ SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); SDValue ExpandBUILD_VECTOR(SDNode *Node); SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); - SDValue ExpandDBG_STOPPOINT(SDNode *Node); void ExpandDYNAMIC_STACKALLOC(SDNode *Node, SmallVectorImpl &Results); SDValue ExpandFCOPYSIGN(SDNode *Node); @@ -1596,37 +1595,6 @@ AbsVal); } -SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) { - DebugLoc dl = Node->getDebugLoc(); - DwarfWriter *DW = DAG.getDwarfWriter(); - bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, - MVT::Other); - bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); - - const DbgStopPointSDNode *DSP = cast(Node); - MDNode *CU_Node = DSP->getCompileUnit(); - if (DW && (useDEBUG_LOC || useLABEL)) { - - unsigned Line = DSP->getLine(); - unsigned Col = DSP->getColumn(); - - if (OptLevel == CodeGenOpt::None) { - // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it - // won't hurt anything. - if (useDEBUG_LOC) { - return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0), - DAG.getConstant(Line, MVT::i32), - DAG.getConstant(Col, MVT::i32), - DAG.getSrcValue(CU_Node)); - } else { - unsigned ID = DW->RecordSourceLine(Line, Col, CU_Node); - return DAG.getLabel(ISD::DBG_LABEL, dl, Node->getOperand(0), ID); - } - } - } - return Node->getOperand(0); -} - void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, SmallVectorImpl &Results) { unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); @@ -2282,9 +2250,6 @@ case ISD::VAEND: Results.push_back(Node->getOperand(0)); break; - case ISD::DBG_STOPPOINT: - Results.push_back(ExpandDBG_STOPPOINT(Node)); - break; case ISD::DYNAMIC_STACKALLOC: ExpandDYNAMIC_STACKALLOC(Node, Results); break; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=89536&r1=89535&r2=89536&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Nov 20 20:46:55 2009 @@ -393,13 +393,7 @@ case ISD::Register: ID.AddInteger(cast(N)->getReg()); break; - case ISD::DBG_STOPPOINT: { - const DbgStopPointSDNode *DSP = cast(N); - ID.AddInteger(DSP->getLine()); - ID.AddInteger(DSP->getColumn()); - ID.AddPointer(DSP->getCompileUnit()); - break; - } + case ISD::SRCVALUE: ID.AddPointer(cast(N)->getValue()); break; @@ -510,7 +504,6 @@ default: break; case ISD::HANDLENODE: case ISD::DBG_LABEL: - case ISD::DBG_STOPPOINT: case ISD::EH_LABEL: return true; // Never CSE these nodes. } @@ -1297,16 +1290,6 @@ return SDValue(N, 0); } -SDValue SelectionDAG::getDbgStopPoint(DebugLoc DL, SDValue Root, - unsigned Line, unsigned Col, - MDNode *CU) { - SDNode *N = NodeAllocator.Allocate(); - new (N) DbgStopPointSDNode(Root, Line, Col, CU); - N->setDebugLoc(DL); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, SDValue Root, unsigned LabelID) { @@ -5590,7 +5573,6 @@ case ISD::CTLZ: return "ctlz"; // Debug info - case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; case ISD::DEBUG_LOC: return "debug_loc"; // Trampolines Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=89536&r1=89535&r2=89536&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Nov 20 20:46:55 2009 @@ -356,7 +356,6 @@ setOperationAction(ISD::UDIVREM, MVT::i32, Expand); // Support label based line numbers. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=89536&r1=89535&r2=89536&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Fri Nov 20 20:46:55 2009 @@ -128,7 +128,6 @@ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote); // We don't have line number support yet. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp?rev=89536&r1=89535&r2=89536&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp Fri Nov 20 20:46:55 2009 @@ -115,7 +115,6 @@ setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); // We don't have line number support yet. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=89536&r1=89535&r2=89536&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Fri Nov 20 20:46:55 2009 @@ -388,7 +388,6 @@ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); // Support label based line numbers. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); // We want to legalize GlobalAddress and ConstantPool nodes into the Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=89536&r1=89535&r2=89536&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Nov 20 20:46:55 2009 @@ -133,7 +133,6 @@ setOperationAction(ISD::FEXP, MVT::f32, Expand); // We don't have line number support yet. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=89536&r1=89535&r2=89536&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Nov 20 20:46:55 2009 @@ -183,7 +183,6 @@ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); // Support label based line numbers. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=89536&r1=89535&r2=89536&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Fri Nov 20 20:46:55 2009 @@ -645,7 +645,6 @@ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); // We don't have line number support yet. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); @@ -663,7 +662,6 @@ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); // No debug info support yet. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=89536&r1=89535&r2=89536&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Nov 20 20:46:55 2009 @@ -373,8 +373,6 @@ setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); } - // Use the default ISD::DBG_STOPPOINT. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); // FIXME - use subtarget debug flags if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() && Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=89536&r1=89535&r2=89536&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Fri Nov 20 20:46:55 2009 @@ -143,7 +143,6 @@ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); // Debug - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); maxStoresPerMemset = 4; From dpatel at apple.com Fri Nov 20 20:48:09 2009 From: dpatel at apple.com (Devang Patel) Date: Sat, 21 Nov 2009 02:48:09 -0000 Subject: [llvm-commits] [llvm] r89537 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DIE.cpp DIE.h DwarfDebug.cpp DwarfDebug.h DwarfWriter.cpp Message-ID: <200911210248.nAL2m9cv000894@zion.cs.uiuc.edu> Author: dpatel Date: Fri Nov 20 20:48:08 2009 New Revision: 89537 URL: http://llvm.org/viewvc/llvm-project?rev=89537&view=rev Log: Cosmetic changes, which were long overdue, in DwarfDebug.cpp. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp?rev=89537&r1=89536&r2=89537&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp Fri Nov 20 20:48:08 2009 @@ -105,9 +105,9 @@ delete Children[i]; } -/// AddSiblingOffset - Add a sibling offset field to the front of the DIE. +/// addSiblingOffset - Add a sibling offset field to the front of the DIE. /// -void DIE::AddSiblingOffset() { +void DIE::addSiblingOffset() { DIEInteger *DI = new DIEInteger(0); Values.insert(Values.begin(), DI); Abbrev.AddFirstAttribute(dwarf::DW_AT_sibling, dwarf::DW_FORM_ref4); Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h?rev=89537&r1=89536&r2=89537&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h Fri Nov 20 20:48:08 2009 @@ -161,34 +161,28 @@ void setSize(unsigned S) { Size = S; } void setAbstractCompileUnit(CompileUnit *CU) { AbstractCU = CU; } - /// AddValue - Add a value and attributes to a DIE. + /// addValue - Add a value and attributes to a DIE. /// - void AddValue(unsigned Attribute, unsigned Form, DIEValue *Value) { + void addValue(unsigned Attribute, unsigned Form, DIEValue *Value) { Abbrev.AddAttribute(Attribute, Form); Values.push_back(Value); } /// SiblingOffset - Return the offset of the debug information entry's /// sibling. - unsigned SiblingOffset() const { return Offset + Size; } + unsigned getSiblingOffset() const { return Offset + Size; } - /// AddSiblingOffset - Add a sibling offset field to the front of the DIE. + /// addSiblingOffset - Add a sibling offset field to the front of the DIE. /// - void AddSiblingOffset(); + void addSiblingOffset(); - /// AddChild - Add a child to the DIE. + /// addChild - Add a child to the DIE. /// - void AddChild(DIE *Child) { + void addChild(DIE *Child) { Abbrev.setChildrenFlag(dwarf::DW_CHILDREN_yes); Children.push_back(Child); } - /// Detach - Detaches objects connected to it after copying. - /// - void Detach() { - Children.clear(); - } - #ifndef NDEBUG void print(raw_ostream &O, unsigned IncIndent = 0); void dump(); Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=89537&r1=89536&r2=89537&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri Nov 20 20:48:08 2009 @@ -53,7 +53,7 @@ /// Die - Compile unit debug information entry. /// - DIE *Die; + DIE *CUDie; /// IndexTyDie - An anonymous type for index type. DIE *IndexTyDie; @@ -74,21 +74,21 @@ public: CompileUnit(unsigned I, DIE *D) - : ID(I), Die(D), IndexTyDie(0) {} - ~CompileUnit() { delete Die; delete IndexTyDie; } + : ID(I), CUDie(D), IndexTyDie(0) {} + ~CompileUnit() { delete CUDie; delete IndexTyDie; } // Accessors. unsigned getID() const { return ID; } - DIE* getCUDie() const { return Die; } + DIE* getCUDie() const { return CUDie; } StringMap &getGlobals() { return Globals; } /// hasContent - Return true if this compile unit has something to write out. /// - bool hasContent() const { return !Die->getChildren().empty(); } + bool hasContent() const { return !CUDie->getChildren().empty(); } - /// AddGlobal - Add a new global entity to the compile unit. + /// addGlobal - Add a new global entity to the compile unit. /// - void AddGlobal(const std::string &Name, DIE *Die) { Globals[Name] = Die; } + void addGlobal(const std::string &Name, DIE *Die) { Globals[Name] = Die; } /// getDIE - Returns the debug information entry map slot for the /// specified debug variable. @@ -108,10 +108,10 @@ GVToDIEEntryMap.insert(std::make_pair(N, E)); } - /// AddDie - Adds or interns the DIE to the compile unit. + /// addDie - Adds or interns the DIE to the compile unit. /// - void AddDie(DIE *Buffer) { - this->Die->AddChild(Buffer); + void addDie(DIE *Buffer) { + this->CUDie->addChild(Buffer); } // getIndexTyDie - Get an anonymous type for index type. @@ -192,15 +192,15 @@ bool isAbstractScope() const { return AbstractScope; } const MachineInstr *getFirstInsn() { return FirstInsn; } - /// AddScope - Add a scope to the scope. + /// addScope - Add a scope to the scope. /// - void AddScope(DbgScope *S) { Scopes.push_back(S); } + void addScope(DbgScope *S) { Scopes.push_back(S); } - /// AddVariable - Add a variable to the scope. + /// addVariable - Add a variable to the scope. /// - void AddVariable(DbgVariable *V) { Variables.push_back(V); } + void addVariable(DbgVariable *V) { Variables.push_back(V); } - void FixInstructionMarkers() { + void fixInstructionMarkers() { assert (getFirstInsn() && "First instruction is missing!"); if (getLastInsn()) return; @@ -211,7 +211,7 @@ assert (!Scopes.empty() && "Inner most scope does not have last insn!"); DbgScope *L = Scopes.back(); if (!L->getLastInsn()) - L->FixInstructionMarkers(); + L->fixInstructionMarkers(); setLastInsn(L->getLastInsn()); } @@ -253,7 +253,7 @@ DwarfDebug::DwarfDebug(raw_ostream &OS, AsmPrinter *A, const MCAsmInfo *T) : Dwarf(OS, A, T, "dbg"), ModuleCU(0), AbbreviationsSet(InitAbbreviationsSetSize), Abbreviations(), - Values(), StringPool(), + DIEValues(), StringPool(), SectionSourceLines(), didInitial(false), shouldEmit(false), CurrentFnDbgScope(0), DebugTimer(0) { if (TimePassesIsEnabled) @@ -261,15 +261,15 @@ getDwarfTimerGroup()); } DwarfDebug::~DwarfDebug() { - for (unsigned j = 0, M = Values.size(); j < M; ++j) - delete Values[j]; + for (unsigned j = 0, M = DIEValues.size(); j < M; ++j) + delete DIEValues[j]; delete DebugTimer; } -/// AssignAbbrevNumber - Define a unique number for the abbreviation. +/// assignAbbrevNumber - Define a unique number for the abbreviation. /// -void DwarfDebug::AssignAbbrevNumber(DIEAbbrev &Abbrev) { +void DwarfDebug::assignAbbrevNumber(DIEAbbrev &Abbrev) { // Profile the node so that we can make it unique. FoldingSetNodeID ID; Abbrev.Profile(ID); @@ -290,126 +290,120 @@ } } -/// CreateDIEEntry - Creates a new DIEEntry to be a proxy for a debug +/// createDIEEntry - Creates a new DIEEntry to be a proxy for a debug /// information entry. -DIEEntry *DwarfDebug::CreateDIEEntry(DIE *Entry) { +DIEEntry *DwarfDebug::createDIEEntry(DIE *Entry) { DIEEntry *Value = new DIEEntry(Entry); - Values.push_back(Value); + DIEValues.push_back(Value); return Value; } -/// SetDIEEntry - Set a DIEEntry once the debug information entry is defined. +/// addUInt - Add an unsigned integer attribute data and value. /// -void DwarfDebug::SetDIEEntry(DIEEntry *Value, DIE *Entry) { - Value->setEntry(Entry); -} - -/// AddUInt - Add an unsigned integer attribute data and value. -/// -void DwarfDebug::AddUInt(DIE *Die, unsigned Attribute, +void DwarfDebug::addUInt(DIE *Die, unsigned Attribute, unsigned Form, uint64_t Integer) { if (!Form) Form = DIEInteger::BestForm(false, Integer); DIEValue *Value = new DIEInteger(Integer); - Values.push_back(Value); - Die->AddValue(Attribute, Form, Value); + DIEValues.push_back(Value); + Die->addValue(Attribute, Form, Value); } -/// AddSInt - Add an signed integer attribute data and value. +/// addSInt - Add an signed integer attribute data and value. /// -void DwarfDebug::AddSInt(DIE *Die, unsigned Attribute, +void DwarfDebug::addSInt(DIE *Die, unsigned Attribute, unsigned Form, int64_t Integer) { if (!Form) Form = DIEInteger::BestForm(true, Integer); DIEValue *Value = new DIEInteger(Integer); - Values.push_back(Value); - Die->AddValue(Attribute, Form, Value); + DIEValues.push_back(Value); + Die->addValue(Attribute, Form, Value); } -/// AddString - Add a string attribute data and value. +/// addString - Add a string attribute data and value. /// -void DwarfDebug::AddString(DIE *Die, unsigned Attribute, unsigned Form, +void DwarfDebug::addString(DIE *Die, unsigned Attribute, unsigned Form, const std::string &String) { DIEValue *Value = new DIEString(String); - Values.push_back(Value); - Die->AddValue(Attribute, Form, Value); + DIEValues.push_back(Value); + Die->addValue(Attribute, Form, Value); } -/// AddLabel - Add a Dwarf label attribute data and value. +/// addLabel - Add a Dwarf label attribute data and value. /// -void DwarfDebug::AddLabel(DIE *Die, unsigned Attribute, unsigned Form, +void DwarfDebug::addLabel(DIE *Die, unsigned Attribute, unsigned Form, const DWLabel &Label) { DIEValue *Value = new DIEDwarfLabel(Label); - Values.push_back(Value); - Die->AddValue(Attribute, Form, Value); + DIEValues.push_back(Value); + Die->addValue(Attribute, Form, Value); } -/// AddObjectLabel - Add an non-Dwarf label attribute data and value. +/// addObjectLabel - Add an non-Dwarf label attribute data and value. /// -void DwarfDebug::AddObjectLabel(DIE *Die, unsigned Attribute, unsigned Form, +void DwarfDebug::addObjectLabel(DIE *Die, unsigned Attribute, unsigned Form, const std::string &Label) { DIEValue *Value = new DIEObjectLabel(Label); - Values.push_back(Value); - Die->AddValue(Attribute, Form, Value); + DIEValues.push_back(Value); + Die->addValue(Attribute, Form, Value); } -/// AddSectionOffset - Add a section offset label attribute data and value. +/// addSectionOffset - Add a section offset label attribute data and value. /// -void DwarfDebug::AddSectionOffset(DIE *Die, unsigned Attribute, unsigned Form, +void DwarfDebug::addSectionOffset(DIE *Die, unsigned Attribute, unsigned Form, const DWLabel &Label, const DWLabel &Section, bool isEH, bool useSet) { DIEValue *Value = new DIESectionOffset(Label, Section, isEH, useSet); - Values.push_back(Value); - Die->AddValue(Attribute, Form, Value); + DIEValues.push_back(Value); + Die->addValue(Attribute, Form, Value); } -/// AddDelta - Add a label delta attribute data and value. +/// addDelta - Add a label delta attribute data and value. /// -void DwarfDebug::AddDelta(DIE *Die, unsigned Attribute, unsigned Form, +void DwarfDebug::addDelta(DIE *Die, unsigned Attribute, unsigned Form, const DWLabel &Hi, const DWLabel &Lo) { DIEValue *Value = new DIEDelta(Hi, Lo); - Values.push_back(Value); - Die->AddValue(Attribute, Form, Value); + DIEValues.push_back(Value); + Die->addValue(Attribute, Form, Value); } -/// AddBlock - Add block data. +/// addBlock - Add block data. /// -void DwarfDebug::AddBlock(DIE *Die, unsigned Attribute, unsigned Form, +void DwarfDebug::addBlock(DIE *Die, unsigned Attribute, unsigned Form, DIEBlock *Block) { Block->ComputeSize(TD); - Values.push_back(Block); - Die->AddValue(Attribute, Block->BestForm(), Block); + DIEValues.push_back(Block); + Die->addValue(Attribute, Block->BestForm(), Block); } -/// AddSourceLine - Add location information to specified debug information +/// addSourceLine - Add location information to specified debug information /// entry. -void DwarfDebug::AddSourceLine(DIE *Die, const DIVariable *V) { +void DwarfDebug::addSourceLine(DIE *Die, const DIVariable *V) { // If there is no compile unit specified, don't add a line #. if (V->getCompileUnit().isNull()) return; unsigned Line = V->getLineNumber(); - unsigned FileID = FindCompileUnit(V->getCompileUnit()).getID(); + unsigned FileID = findCompileUnit(V->getCompileUnit()).getID(); assert(FileID && "Invalid file id"); - AddUInt(Die, dwarf::DW_AT_decl_file, 0, FileID); - AddUInt(Die, dwarf::DW_AT_decl_line, 0, Line); + addUInt(Die, dwarf::DW_AT_decl_file, 0, FileID); + addUInt(Die, dwarf::DW_AT_decl_line, 0, Line); } -/// AddSourceLine - Add location information to specified debug information +/// addSourceLine - Add location information to specified debug information /// entry. -void DwarfDebug::AddSourceLine(DIE *Die, const DIGlobal *G) { +void DwarfDebug::addSourceLine(DIE *Die, const DIGlobal *G) { // If there is no compile unit specified, don't add a line #. if (G->getCompileUnit().isNull()) return; unsigned Line = G->getLineNumber(); - unsigned FileID = FindCompileUnit(G->getCompileUnit()).getID(); + unsigned FileID = findCompileUnit(G->getCompileUnit()).getID(); assert(FileID && "Invalid file id"); - AddUInt(Die, dwarf::DW_AT_decl_file, 0, FileID); - AddUInt(Die, dwarf::DW_AT_decl_line, 0, Line); + addUInt(Die, dwarf::DW_AT_decl_file, 0, FileID); + addUInt(Die, dwarf::DW_AT_decl_line, 0, Line); } -/// AddSourceLine - Add location information to specified debug information +/// addSourceLine - Add location information to specified debug information /// entry. -void DwarfDebug::AddSourceLine(DIE *Die, const DISubprogram *SP) { +void DwarfDebug::addSourceLine(DIE *Die, const DISubprogram *SP) { // If there is no compile unit specified, don't add a line #. if (SP->getCompileUnit().isNull()) return; @@ -419,25 +413,25 @@ unsigned Line = SP->getLineNumber(); - unsigned FileID = FindCompileUnit(SP->getCompileUnit()).getID(); + unsigned FileID = findCompileUnit(SP->getCompileUnit()).getID(); assert(FileID && "Invalid file id"); - AddUInt(Die, dwarf::DW_AT_decl_file, 0, FileID); - AddUInt(Die, dwarf::DW_AT_decl_line, 0, Line); + addUInt(Die, dwarf::DW_AT_decl_file, 0, FileID); + addUInt(Die, dwarf::DW_AT_decl_line, 0, Line); } -/// AddSourceLine - Add location information to specified debug information +/// addSourceLine - Add location information to specified debug information /// entry. -void DwarfDebug::AddSourceLine(DIE *Die, const DIType *Ty) { +void DwarfDebug::addSourceLine(DIE *Die, const DIType *Ty) { // If there is no compile unit specified, don't add a line #. DICompileUnit CU = Ty->getCompileUnit(); if (CU.isNull()) return; unsigned Line = Ty->getLineNumber(); - unsigned FileID = FindCompileUnit(CU).getID(); + unsigned FileID = findCompileUnit(CU).getID(); assert(FileID && "Invalid file id"); - AddUInt(Die, dwarf::DW_AT_decl_file, 0, FileID); - AddUInt(Die, dwarf::DW_AT_decl_line, 0, Line); + addUInt(Die, dwarf::DW_AT_decl_file, 0, FileID); + addUInt(Die, dwarf::DW_AT_decl_line, 0, Line); } /* Byref variables, in Blocks, are declared by the programmer as @@ -463,12 +457,12 @@ side, the Debug Information Entry for the variable VarName needs to have a DW_AT_location that tells the debugger how to unwind through the pointers and __Block_byref_x_VarName struct to find the actual - value of the variable. The function AddBlockByrefType does this. */ + value of the variable. The function addBlockByrefType does this. */ /// Find the type the programmer originally declared the variable to be /// and return that type. /// -DIType DwarfDebug::GetBlockByrefType(DIType Ty, std::string Name) { +DIType DwarfDebug::getBlockByrefType(DIType Ty, std::string Name) { DIType subType = Ty; unsigned tag = Ty.getTag(); @@ -495,12 +489,12 @@ return Ty; } -/// AddComplexAddress - Start with the address based on the location provided, +/// addComplexAddress - Start with the address based on the location provided, /// and generate the DWARF information necessary to find the actual variable /// given the extra address information encoded in the DIVariable, starting from /// the starting location. Add the DWARF information to the die. /// -void DwarfDebug::AddComplexAddress(DbgVariable *&DV, DIE *Die, +void DwarfDebug::addComplexAddress(DbgVariable *&DV, DIE *Die, unsigned Attribute, const MachineLocation &Location) { const DIVariable &VD = DV->getVariable(); @@ -513,36 +507,36 @@ if (Location.isReg()) { if (Reg < 32) { - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + Reg); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + Reg); } else { Reg = Reg - dwarf::DW_OP_reg0; - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg); - AddUInt(Block, 0, dwarf::DW_FORM_udata, Reg); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg); + addUInt(Block, 0, dwarf::DW_FORM_udata, Reg); } } else { if (Reg < 32) - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg); else { - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_bregx); - AddUInt(Block, 0, dwarf::DW_FORM_udata, Reg); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_bregx); + addUInt(Block, 0, dwarf::DW_FORM_udata, Reg); } - AddUInt(Block, 0, dwarf::DW_FORM_sdata, Location.getOffset()); + addUInt(Block, 0, dwarf::DW_FORM_sdata, Location.getOffset()); } for (unsigned i = 0, N = VD.getNumAddrElements(); i < N; ++i) { uint64_t Element = VD.getAddrElement(i); if (Element == DIFactory::OpPlus) { - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst); - AddUInt(Block, 0, dwarf::DW_FORM_udata, VD.getAddrElement(++i)); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst); + addUInt(Block, 0, dwarf::DW_FORM_udata, VD.getAddrElement(++i)); } else if (Element == DIFactory::OpDeref) { - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_deref); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_deref); } else llvm_unreachable("unknown DIFactory Opcode"); } // Now attach the location information to the DIE. - AddBlock(Die, Attribute, 0, Block); + addBlock(Die, Attribute, 0, Block); } /* Byref variables, in Blocks, are declared by the programmer as "SomeType @@ -554,7 +548,7 @@ However, as far as the original *programmer* is concerned, the variable should still have type 'SomeType', as originally declared. - The function GetBlockByrefType dives into the __Block_byref_x_VarName + The function getBlockByrefType dives into the __Block_byref_x_VarName struct to find the original type of the variable, which is then assigned to the variable's Debug Information Entry as its real type. So far, so good. However now the debugger will expect the variable VarName to have the type @@ -599,13 +593,13 @@ That is what this function does. */ -/// AddBlockByrefAddress - Start with the address based on the location +/// addBlockByrefAddress - Start with the address based on the location /// provided, and generate the DWARF information necessary to find the /// actual Block variable (navigating the Block struct) based on the /// starting location. Add the DWARF information to the die. For /// more information, read large comment just above here. /// -void DwarfDebug::AddBlockByrefAddress(DbgVariable *&DV, DIE *Die, +void DwarfDebug::addBlockByrefAddress(DbgVariable *&DV, DIE *Die, unsigned Attribute, const MachineLocation &Location) { const DIVariable &VD = DV->getVariable(); @@ -658,107 +652,107 @@ if (Location.isReg()) { if (Reg < 32) - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + Reg); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + Reg); else { Reg = Reg - dwarf::DW_OP_reg0; - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg); - AddUInt(Block, 0, dwarf::DW_FORM_udata, Reg); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg); + addUInt(Block, 0, dwarf::DW_FORM_udata, Reg); } } else { if (Reg < 32) - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg); else { - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_bregx); - AddUInt(Block, 0, dwarf::DW_FORM_udata, Reg); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_bregx); + addUInt(Block, 0, dwarf::DW_FORM_udata, Reg); } - AddUInt(Block, 0, dwarf::DW_FORM_sdata, Location.getOffset()); + addUInt(Block, 0, dwarf::DW_FORM_sdata, Location.getOffset()); } // If we started with a pointer to the __Block_byref... struct, then // the first thing we need to do is dereference the pointer (DW_OP_deref). if (isPointer) - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_deref); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_deref); // Next add the offset for the '__forwarding' field: // DW_OP_plus_uconst ForwardingFieldOffset. Note there's no point in // adding the offset if it's 0. if (forwardingFieldOffset > 0) { - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst); - AddUInt(Block, 0, dwarf::DW_FORM_udata, forwardingFieldOffset); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst); + addUInt(Block, 0, dwarf::DW_FORM_udata, forwardingFieldOffset); } // Now dereference the __forwarding field to get to the real __Block_byref // struct: DW_OP_deref. - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_deref); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_deref); // Now that we've got the real __Block_byref... struct, add the offset // for the variable's field to get to the location of the actual variable: // DW_OP_plus_uconst varFieldOffset. Again, don't add if it's 0. if (varFieldOffset > 0) { - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst); - AddUInt(Block, 0, dwarf::DW_FORM_udata, varFieldOffset); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst); + addUInt(Block, 0, dwarf::DW_FORM_udata, varFieldOffset); } // Now attach the location information to the DIE. - AddBlock(Die, Attribute, 0, Block); + addBlock(Die, Attribute, 0, Block); } -/// AddAddress - Add an address attribute to a die based on the location +/// addAddress - Add an address attribute to a die based on the location /// provided. -void DwarfDebug::AddAddress(DIE *Die, unsigned Attribute, +void DwarfDebug::addAddress(DIE *Die, unsigned Attribute, const MachineLocation &Location) { unsigned Reg = RI->getDwarfRegNum(Location.getReg(), false); DIEBlock *Block = new DIEBlock(); if (Location.isReg()) { if (Reg < 32) { - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + Reg); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + Reg); } else { - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_regx); - AddUInt(Block, 0, dwarf::DW_FORM_udata, Reg); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_regx); + addUInt(Block, 0, dwarf::DW_FORM_udata, Reg); } } else { if (Reg < 32) { - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg); } else { - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_bregx); - AddUInt(Block, 0, dwarf::DW_FORM_udata, Reg); + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_bregx); + addUInt(Block, 0, dwarf::DW_FORM_udata, Reg); } - AddUInt(Block, 0, dwarf::DW_FORM_sdata, Location.getOffset()); + addUInt(Block, 0, dwarf::DW_FORM_sdata, Location.getOffset()); } - AddBlock(Die, Attribute, 0, Block); + addBlock(Die, Attribute, 0, Block); } -/// AddType - Add a new type attribute to the specified entity. -void DwarfDebug::AddType(CompileUnit *DW_Unit, DIE *Entity, DIType Ty) { +/// addType - Add a new type attribute to the specified entity. +void DwarfDebug::addType(CompileUnit *DW_Unit, DIE *Entity, DIType Ty) { if (Ty.isNull()) return; // Check for pre-existence. - DIEEntry *Slot = DW_Unit->getDIEEntry(Ty.getNode()); + DIEEntry *Entry = DW_Unit->getDIEEntry(Ty.getNode()); // If it exists then use the existing value. - if (Slot) { - Entity->AddValue(dwarf::DW_AT_type, dwarf::DW_FORM_ref4, Slot); + if (Entry) { + Entity->addValue(dwarf::DW_AT_type, dwarf::DW_FORM_ref4, Entry); return; } // Set up proxy. - Slot = CreateDIEEntry(); - DW_Unit->insertDIEEntry(Ty.getNode(), Slot); + Entry = createDIEEntry(); + DW_Unit->insertDIEEntry(Ty.getNode(), Entry); // Construct type. DIE *Buffer = new DIE(dwarf::DW_TAG_base_type); if (Ty.isBasicType()) - ConstructTypeDIE(DW_Unit, *Buffer, DIBasicType(Ty.getNode())); + constructTypeDIE(DW_Unit, *Buffer, DIBasicType(Ty.getNode())); else if (Ty.isCompositeType()) - ConstructTypeDIE(DW_Unit, *Buffer, DICompositeType(Ty.getNode())); + constructTypeDIE(DW_Unit, *Buffer, DICompositeType(Ty.getNode())); else { assert(Ty.isDerivedType() && "Unknown kind of DIType"); - ConstructTypeDIE(DW_Unit, *Buffer, DIDerivedType(Ty.getNode())); + constructTypeDIE(DW_Unit, *Buffer, DIDerivedType(Ty.getNode())); } // Add debug information entry to entity and appropriate context. @@ -768,31 +762,31 @@ Die = DW_Unit->getDIE(Context.getNode()); if (Die) - Die->AddChild(Buffer); + Die->addChild(Buffer); else - DW_Unit->AddDie(Buffer); - SetDIEEntry(Slot, Buffer); - Entity->AddValue(dwarf::DW_AT_type, dwarf::DW_FORM_ref4, Slot); + DW_Unit->addDie(Buffer); + Entry->setEntry(Buffer); + Entity->addValue(dwarf::DW_AT_type, dwarf::DW_FORM_ref4, Entry); } -/// ConstructTypeDIE - Construct basic type die from DIBasicType. -void DwarfDebug::ConstructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, +/// constructTypeDIE - Construct basic type die from DIBasicType. +void DwarfDebug::constructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, DIBasicType BTy) { // Get core information. const char *Name = BTy.getName(); Buffer.setTag(dwarf::DW_TAG_base_type); - AddUInt(&Buffer, dwarf::DW_AT_encoding, dwarf::DW_FORM_data1, + addUInt(&Buffer, dwarf::DW_AT_encoding, dwarf::DW_FORM_data1, BTy.getEncoding()); // Add name if not anonymous or intermediate type. if (Name) - AddString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); + addString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); uint64_t Size = BTy.getSizeInBits() >> 3; - AddUInt(&Buffer, dwarf::DW_AT_byte_size, 0, Size); + addUInt(&Buffer, dwarf::DW_AT_byte_size, 0, Size); } -/// ConstructTypeDIE - Construct derived type die from DIDerivedType. -void DwarfDebug::ConstructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, +/// constructTypeDIE - Construct derived type die from DIDerivedType. +void DwarfDebug::constructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, DIDerivedType DTy) { // Get core information. const char *Name = DTy.getName(); @@ -806,23 +800,23 @@ // Map to main type, void will not have a type. DIType FromTy = DTy.getTypeDerivedFrom(); - AddType(DW_Unit, &Buffer, FromTy); + addType(DW_Unit, &Buffer, FromTy); // Add name if not anonymous or intermediate type. if (Name && Tag != dwarf::DW_TAG_pointer_type) - AddString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); + addString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); // Add size if non-zero (derived types might be zero-sized.) if (Size) - AddUInt(&Buffer, dwarf::DW_AT_byte_size, 0, Size); + addUInt(&Buffer, dwarf::DW_AT_byte_size, 0, Size); // Add source line info if available and TyDesc is not a forward declaration. if (!DTy.isForwardDecl() && Tag != dwarf::DW_TAG_pointer_type) - AddSourceLine(&Buffer, &DTy); + addSourceLine(&Buffer, &DTy); } -/// ConstructTypeDIE - Construct type DIE from DICompositeType. -void DwarfDebug::ConstructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, +/// constructTypeDIE - Construct type DIE from DICompositeType. +void DwarfDebug::constructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, DICompositeType CTy) { // Get core information. const char *Name = CTy.getName(); @@ -834,7 +828,7 @@ switch (Tag) { case dwarf::DW_TAG_vector_type: case dwarf::DW_TAG_array_type: - ConstructArrayTypeDIE(DW_Unit, Buffer, &CTy); + constructArrayTypeDIE(DW_Unit, Buffer, &CTy); break; case dwarf::DW_TAG_enumeration_type: { DIArray Elements = CTy.getTypeArray(); @@ -844,8 +838,8 @@ DIE *ElemDie = NULL; DIEnumerator Enum(Elements.getElement(i).getNode()); if (!Enum.isNull()) { - ElemDie = ConstructEnumTypeDIE(DW_Unit, &Enum); - Buffer.AddChild(ElemDie); + ElemDie = constructEnumTypeDIE(DW_Unit, &Enum); + Buffer.addChild(ElemDie); } } } @@ -854,17 +848,17 @@ // Add return type. DIArray Elements = CTy.getTypeArray(); DIDescriptor RTy = Elements.getElement(0); - AddType(DW_Unit, &Buffer, DIType(RTy.getNode())); + addType(DW_Unit, &Buffer, DIType(RTy.getNode())); // Add prototype flag. - AddUInt(&Buffer, dwarf::DW_AT_prototyped, dwarf::DW_FORM_flag, 1); + addUInt(&Buffer, dwarf::DW_AT_prototyped, dwarf::DW_FORM_flag, 1); // Add arguments. for (unsigned i = 1, N = Elements.getNumElements(); i < N; ++i) { DIE *Arg = new DIE(dwarf::DW_TAG_formal_parameter); DIDescriptor Ty = Elements.getElement(i); - AddType(DW_Unit, Arg, DIType(Ty.getNode())); - Buffer.AddChild(Arg); + addType(DW_Unit, Arg, DIType(Ty.getNode())); + Buffer.addChild(Arg); } } break; @@ -885,20 +879,20 @@ continue; DIE *ElemDie = NULL; if (Element.getTag() == dwarf::DW_TAG_subprogram) - ElemDie = CreateSubprogramDIE(DW_Unit, + ElemDie = createSubprogramDIE(DW_Unit, DISubprogram(Element.getNode())); else - ElemDie = CreateMemberDIE(DW_Unit, + ElemDie = createMemberDIE(DW_Unit, DIDerivedType(Element.getNode())); - Buffer.AddChild(ElemDie); + Buffer.addChild(ElemDie); } if (CTy.isAppleBlockExtension()) - AddUInt(&Buffer, dwarf::DW_AT_APPLE_block, dwarf::DW_FORM_flag, 1); + addUInt(&Buffer, dwarf::DW_AT_APPLE_block, dwarf::DW_FORM_flag, 1); unsigned RLang = CTy.getRunTimeLang(); if (RLang) - AddUInt(&Buffer, dwarf::DW_AT_APPLE_runtime_class, + addUInt(&Buffer, dwarf::DW_AT_APPLE_runtime_class, dwarf::DW_FORM_data1, RLang); break; } @@ -908,51 +902,51 @@ // Add name if not anonymous or intermediate type. if (Name) - AddString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); + addString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); if (Tag == dwarf::DW_TAG_enumeration_type || Tag == dwarf::DW_TAG_structure_type || Tag == dwarf::DW_TAG_union_type) { // Add size if non-zero (derived types might be zero-sized.) if (Size) - AddUInt(&Buffer, dwarf::DW_AT_byte_size, 0, Size); + addUInt(&Buffer, dwarf::DW_AT_byte_size, 0, Size); else { // Add zero size if it is not a forward declaration. if (CTy.isForwardDecl()) - AddUInt(&Buffer, dwarf::DW_AT_declaration, dwarf::DW_FORM_flag, 1); + addUInt(&Buffer, dwarf::DW_AT_declaration, dwarf::DW_FORM_flag, 1); else - AddUInt(&Buffer, dwarf::DW_AT_byte_size, 0, 0); + addUInt(&Buffer, dwarf::DW_AT_byte_size, 0, 0); } // Add source line info if available. if (!CTy.isForwardDecl()) - AddSourceLine(&Buffer, &CTy); + addSourceLine(&Buffer, &CTy); } } -/// ConstructSubrangeDIE - Construct subrange DIE from DISubrange. -void DwarfDebug::ConstructSubrangeDIE(DIE &Buffer, DISubrange SR, DIE *IndexTy){ +/// constructSubrangeDIE - Construct subrange DIE from DISubrange. +void DwarfDebug::constructSubrangeDIE(DIE &Buffer, DISubrange SR, DIE *IndexTy){ int64_t L = SR.getLo(); int64_t H = SR.getHi(); DIE *DW_Subrange = new DIE(dwarf::DW_TAG_subrange_type); - AddDIEEntry(DW_Subrange, dwarf::DW_AT_type, dwarf::DW_FORM_ref4, IndexTy); + addDIEEntry(DW_Subrange, dwarf::DW_AT_type, dwarf::DW_FORM_ref4, IndexTy); if (L) - AddSInt(DW_Subrange, dwarf::DW_AT_lower_bound, 0, L); + addSInt(DW_Subrange, dwarf::DW_AT_lower_bound, 0, L); if (H) - AddSInt(DW_Subrange, dwarf::DW_AT_upper_bound, 0, H); + addSInt(DW_Subrange, dwarf::DW_AT_upper_bound, 0, H); - Buffer.AddChild(DW_Subrange); + Buffer.addChild(DW_Subrange); } -/// ConstructArrayTypeDIE - Construct array type DIE from DICompositeType. -void DwarfDebug::ConstructArrayTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, +/// constructArrayTypeDIE - Construct array type DIE from DICompositeType. +void DwarfDebug::constructArrayTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, DICompositeType *CTy) { Buffer.setTag(dwarf::DW_TAG_array_type); if (CTy->getTag() == dwarf::DW_TAG_vector_type) - AddUInt(&Buffer, dwarf::DW_AT_GNU_vector, dwarf::DW_FORM_flag, 1); + addUInt(&Buffer, dwarf::DW_AT_GNU_vector, dwarf::DW_FORM_flag, 1); // Emit derived type. - AddType(DW_Unit, &Buffer, CTy->getTypeDerivedFrom()); + addType(DW_Unit, &Buffer, CTy->getTypeDerivedFrom()); DIArray Elements = CTy->getTypeArray(); // Get an anonymous type for index type. @@ -960,10 +954,10 @@ if (!IdxTy) { // Construct an anonymous type for index type. IdxTy = new DIE(dwarf::DW_TAG_base_type); - AddUInt(IdxTy, dwarf::DW_AT_byte_size, 0, sizeof(int32_t)); - AddUInt(IdxTy, dwarf::DW_AT_encoding, dwarf::DW_FORM_data1, + addUInt(IdxTy, dwarf::DW_AT_byte_size, 0, sizeof(int32_t)); + addUInt(IdxTy, dwarf::DW_AT_encoding, dwarf::DW_FORM_data1, dwarf::DW_ATE_signed); - DW_Unit->AddDie(IdxTy); + DW_Unit->addDie(IdxTy); DW_Unit->setIndexTyDie(IdxTy); } @@ -971,29 +965,29 @@ for (unsigned i = 0, N = Elements.getNumElements(); i < N; ++i) { DIDescriptor Element = Elements.getElement(i); if (Element.getTag() == dwarf::DW_TAG_subrange_type) - ConstructSubrangeDIE(Buffer, DISubrange(Element.getNode()), IdxTy); + constructSubrangeDIE(Buffer, DISubrange(Element.getNode()), IdxTy); } } -/// ConstructEnumTypeDIE - Construct enum type DIE from DIEnumerator. -DIE *DwarfDebug::ConstructEnumTypeDIE(CompileUnit *DW_Unit, DIEnumerator *ETy) { +/// constructEnumTypeDIE - Construct enum type DIE from DIEnumerator. +DIE *DwarfDebug::constructEnumTypeDIE(CompileUnit *DW_Unit, DIEnumerator *ETy) { DIE *Enumerator = new DIE(dwarf::DW_TAG_enumerator); const char *Name = ETy->getName(); - AddString(Enumerator, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); + addString(Enumerator, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); int64_t Value = ETy->getEnumValue(); - AddSInt(Enumerator, dwarf::DW_AT_const_value, dwarf::DW_FORM_sdata, Value); + addSInt(Enumerator, dwarf::DW_AT_const_value, dwarf::DW_FORM_sdata, Value); return Enumerator; } -/// CreateGlobalVariableDIE - Create new DIE using GV. -DIE *DwarfDebug::CreateGlobalVariableDIE(CompileUnit *DW_Unit, +/// createGlobalVariableDIE - Create new DIE using GV. +DIE *DwarfDebug::createGlobalVariableDIE(CompileUnit *DW_Unit, const DIGlobalVariable &GV) { // If the global variable was optmized out then no need to create debug info entry. if (!GV.getGlobal()) return NULL; if (!GV.getDisplayName()) return NULL; DIE *GVDie = new DIE(dwarf::DW_TAG_variable); - AddString(GVDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, + addString(GVDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, GV.getDisplayName()); const char *LinkageName = GV.getLinkageName(); @@ -1004,44 +998,44 @@ // __asm__ attribute. if (LinkageName[0] == 1) LinkageName = &LinkageName[1]; - AddString(GVDie, dwarf::DW_AT_MIPS_linkage_name, dwarf::DW_FORM_string, + addString(GVDie, dwarf::DW_AT_MIPS_linkage_name, dwarf::DW_FORM_string, LinkageName); } - AddType(DW_Unit, GVDie, GV.getType()); + addType(DW_Unit, GVDie, GV.getType()); if (!GV.isLocalToUnit()) - AddUInt(GVDie, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1); - AddSourceLine(GVDie, &GV); + addUInt(GVDie, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1); + addSourceLine(GVDie, &GV); // Add address. DIEBlock *Block = new DIEBlock(); - AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_addr); - AddObjectLabel(Block, 0, dwarf::DW_FORM_udata, + addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_addr); + addObjectLabel(Block, 0, dwarf::DW_FORM_udata, Asm->Mang->getMangledName(GV.getGlobal())); - AddBlock(GVDie, dwarf::DW_AT_location, 0, Block); + addBlock(GVDie, dwarf::DW_AT_location, 0, Block); return GVDie; } -/// CreateMemberDIE - Create new member DIE. -DIE *DwarfDebug::CreateMemberDIE(CompileUnit *DW_Unit, const DIDerivedType &DT){ +/// createMemberDIE - Create new member DIE. +DIE *DwarfDebug::createMemberDIE(CompileUnit *DW_Unit, const DIDerivedType &DT){ DIE *MemberDie = new DIE(DT.getTag()); if (const char *Name = DT.getName()) - AddString(MemberDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); + addString(MemberDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); - AddType(DW_Unit, MemberDie, DT.getTypeDerivedFrom()); + addType(DW_Unit, MemberDie, DT.getTypeDerivedFrom()); - AddSourceLine(MemberDie, &DT); + addSourceLine(MemberDie, &DT); DIEBlock *MemLocationDie = new DIEBlock(); - AddUInt(MemLocationDie, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst); + addUInt(MemLocationDie, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst); uint64_t Size = DT.getSizeInBits(); uint64_t FieldSize = DT.getOriginalTypeSize(); if (Size != FieldSize) { // Handle bitfield. - AddUInt(MemberDie, dwarf::DW_AT_byte_size, 0, DT.getOriginalTypeSize()>>3); - AddUInt(MemberDie, dwarf::DW_AT_bit_size, 0, DT.getSizeInBits()); + addUInt(MemberDie, dwarf::DW_AT_byte_size, 0, DT.getOriginalTypeSize()>>3); + addUInt(MemberDie, dwarf::DW_AT_bit_size, 0, DT.getSizeInBits()); uint64_t Offset = DT.getOffsetInBits(); uint64_t FieldOffset = Offset; @@ -1052,37 +1046,37 @@ // Maybe we need to work from the other end. if (TD->isLittleEndian()) Offset = FieldSize - (Offset + Size); - AddUInt(MemberDie, dwarf::DW_AT_bit_offset, 0, Offset); + addUInt(MemberDie, dwarf::DW_AT_bit_offset, 0, Offset); // Here WD_AT_data_member_location points to the anonymous // field that includes this bit field. - AddUInt(MemLocationDie, 0, dwarf::DW_FORM_udata, FieldOffset >> 3); + addUInt(MemLocationDie, 0, dwarf::DW_FORM_udata, FieldOffset >> 3); } else // This is not a bitfield. - AddUInt(MemLocationDie, 0, dwarf::DW_FORM_udata, DT.getOffsetInBits() >> 3); + addUInt(MemLocationDie, 0, dwarf::DW_FORM_udata, DT.getOffsetInBits() >> 3); - AddBlock(MemberDie, dwarf::DW_AT_data_member_location, 0, MemLocationDie); + addBlock(MemberDie, dwarf::DW_AT_data_member_location, 0, MemLocationDie); if (DT.isProtected()) - AddUInt(MemberDie, dwarf::DW_AT_accessibility, 0, + addUInt(MemberDie, dwarf::DW_AT_accessibility, 0, dwarf::DW_ACCESS_protected); else if (DT.isPrivate()) - AddUInt(MemberDie, dwarf::DW_AT_accessibility, 0, + addUInt(MemberDie, dwarf::DW_AT_accessibility, 0, dwarf::DW_ACCESS_private); return MemberDie; } -/// CreateSubprogramDIE - Create new DIE using SP. -DIE *DwarfDebug::CreateSubprogramDIE(CompileUnit *DW_Unit, +/// createSubprogramDIE - Create new DIE using SP. +DIE *DwarfDebug::createSubprogramDIE(CompileUnit *DW_Unit, const DISubprogram &SP, bool IsConstructor, bool IsInlined) { DIE *SPDie = new DIE(dwarf::DW_TAG_subprogram); const char * Name = SP.getName(); - AddString(SPDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); + addString(SPDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); const char *LinkageName = SP.getLinkageName(); if (LinkageName) { @@ -1091,10 +1085,10 @@ // symbol names and symbol whose name is replaced using GCC's __asm__ attribute. if (LinkageName[0] == 1) LinkageName = &LinkageName[1]; - AddString(SPDie, dwarf::DW_AT_MIPS_linkage_name, dwarf::DW_FORM_string, + addString(SPDie, dwarf::DW_AT_MIPS_linkage_name, dwarf::DW_FORM_string, LinkageName); } - AddSourceLine(SPDie, &SP); + addSourceLine(SPDie, &SP); DICompositeType SPTy = SP.getType(); DIArray Args = SPTy.getTypeArray(); @@ -1103,28 +1097,28 @@ unsigned Lang = SP.getCompileUnit().getLanguage(); if (Lang == dwarf::DW_LANG_C99 || Lang == dwarf::DW_LANG_C89 || Lang == dwarf::DW_LANG_ObjC) - AddUInt(SPDie, dwarf::DW_AT_prototyped, dwarf::DW_FORM_flag, 1); + addUInt(SPDie, dwarf::DW_AT_prototyped, dwarf::DW_FORM_flag, 1); // Add Return Type. unsigned SPTag = SPTy.getTag(); if (!IsConstructor) { if (Args.isNull() || SPTag != dwarf::DW_TAG_subroutine_type) - AddType(DW_Unit, SPDie, SPTy); + addType(DW_Unit, SPDie, SPTy); else - AddType(DW_Unit, SPDie, DIType(Args.getElement(0).getNode())); + addType(DW_Unit, SPDie, DIType(Args.getElement(0).getNode())); } if (!SP.isDefinition()) { - AddUInt(SPDie, dwarf::DW_AT_declaration, dwarf::DW_FORM_flag, 1); + addUInt(SPDie, dwarf::DW_AT_declaration, dwarf::DW_FORM_flag, 1); // Add arguments. Do not add arguments for subprogram definition. They will // be handled through RecordVariable. if (SPTag == dwarf::DW_TAG_subroutine_type) for (unsigned i = 1, N = Args.getNumElements(); i < N; ++i) { DIE *Arg = new DIE(dwarf::DW_TAG_formal_parameter); - AddType(DW_Unit, Arg, DIType(Args.getElement(i).getNode())); - AddUInt(Arg, dwarf::DW_AT_artificial, dwarf::DW_FORM_flag, 1); // ?? - SPDie->AddChild(Arg); + addType(DW_Unit, Arg, DIType(Args.getElement(i).getNode())); + addUInt(Arg, dwarf::DW_AT_artificial, dwarf::DW_FORM_flag, 1); // ?? + SPDie->addChild(Arg); } } @@ -1133,18 +1127,18 @@ return SPDie; } -/// FindCompileUnit - Get the compile unit for the given descriptor. +/// findCompileUnit - Get the compile unit for the given descriptor. /// -CompileUnit &DwarfDebug::FindCompileUnit(DICompileUnit Unit) const { +CompileUnit &DwarfDebug::findCompileUnit(DICompileUnit Unit) const { DenseMap::const_iterator I = CompileUnitMap.find(Unit.getNode()); assert(I != CompileUnitMap.end() && "Missing compile unit."); return *I->second; } -/// CreateDbgScopeVariable - Create a new scope variable. +/// createDbgScopeVariable - Create a new scope variable. /// -DIE *DwarfDebug::CreateDbgScopeVariable(DbgVariable *DV, CompileUnit *Unit) { +DIE *DwarfDebug::createDbgScopeVariable(DbgVariable *DV, CompileUnit *Unit) { // Get the descriptor. const DIVariable &VD = DV->getVariable(); const char *Name = VD.getName(); @@ -1168,18 +1162,18 @@ // Define variable debug information entry. DIE *VariableDie = new DIE(Tag); - AddString(VariableDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); + addString(VariableDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); // Add source line info if available. - AddSourceLine(VariableDie, &VD); + addSourceLine(VariableDie, &VD); // Add variable type. // FIXME: isBlockByrefVariable should be reformulated in terms of complex // addresses instead. if (VD.isBlockByrefVariable()) - AddType(Unit, VariableDie, GetBlockByrefType(VD.getType(), Name)); + addType(Unit, VariableDie, getBlockByrefType(VD.getType(), Name)); else - AddType(Unit, VariableDie, VD.getType()); + addType(Unit, VariableDie, VD.getType()); // Add variable address. // Variables for abstract instances of inlined functions don't get a @@ -1190,11 +1184,11 @@ if (VD.hasComplexAddress()) - AddComplexAddress(DV, VariableDie, dwarf::DW_AT_location, Location); + addComplexAddress(DV, VariableDie, dwarf::DW_AT_location, Location); else if (VD.isBlockByrefVariable()) - AddBlockByrefAddress(DV, VariableDie, dwarf::DW_AT_location, Location); + addBlockByrefAddress(DV, VariableDie, dwarf::DW_AT_location, Location); else - AddAddress(VariableDie, dwarf::DW_AT_location, Location); + addAddress(VariableDie, dwarf::DW_AT_location, Location); return VariableDie; } @@ -1225,13 +1219,13 @@ IL.getOrigLocation().getNode()); assert (Parent && "Unable to find Parent scope!"); NScope->setParent(Parent); - Parent->AddScope(NScope); + Parent->addScope(NScope); } else if (DIDescriptor(N).isLexicalBlock()) { DILexicalBlock DB(N); if (!DB.getContext().isNull()) { Parent = getUpdatedDbgScope(DB.getContext().getNode(), MI, InlinedAt); NScope->setParent(Parent); - Parent->AddScope(NScope); + Parent->addScope(NScope); } } @@ -1271,7 +1265,7 @@ AScope = new DbgScope(Parent, DIDescriptor(N), NULL); if (Parent) - Parent->AddScope(AScope); + Parent->addScope(AScope); AScope->setAbstractScope(); AbstractScopes[N] = AScope; if (DIDescriptor(N).isSubprogram()) @@ -1297,19 +1291,23 @@ llvm_unreachable("Unexpected Descriptor!"); } -DIE *DwarfDebug::UpdateSubprogramScopeDIE(MDNode *SPNode) { +/// updateSubprogramScopeDIE - Find DIE for the given subprogram and +/// attach appropriate DW_AT_low_pc and DW_AT_high_pc attributes. +/// If there are global variables in this scope then create and insert +/// DIEs for these variables. +DIE *DwarfDebug::updateSubprogramScopeDIE(MDNode *SPNode) { DIE *SPDie = ModuleCU->getDIE(SPNode); assert (SPDie && "Unable to find subprogram DIE!"); - AddLabel(SPDie, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr, + addLabel(SPDie, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr, DWLabel("func_begin", SubprogramCount)); - AddLabel(SPDie, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr, + addLabel(SPDie, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr, DWLabel("func_end", SubprogramCount)); MachineLocation Location(RI->getFrameRegister(*MF)); - AddAddress(SPDie, dwarf::DW_AT_frame_base, Location); + addAddress(SPDie, dwarf::DW_AT_frame_base, Location); if (!DISubprogram(SPNode).isLocalToUnit()) - AddUInt(SPDie, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1); + addUInt(SPDie, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1); // If there are global variables at this scope then add their dies. for (SmallVector::iterator SGI = ScopedGVs.begin(), @@ -1318,15 +1316,17 @@ if (!N) continue; DIGlobalVariable GV(N); if (GV.getContext().getNode() == SPNode) { - DIE *ScopedGVDie = CreateGlobalVariableDIE(ModuleCU, GV); + DIE *ScopedGVDie = createGlobalVariableDIE(ModuleCU, GV); if (ScopedGVDie) - SPDie->AddChild(ScopedGVDie); + SPDie->addChild(ScopedGVDie); } } return SPDie; } -DIE *DwarfDebug::ConstructLexicalScopeDIE(DbgScope *Scope) { +/// constructLexicalScope - Construct new DW_TAG_lexical_block +/// for this scope and attach DW_AT_low_pc/DW_AT_high_pc labels. +DIE *DwarfDebug::constructLexicalScopeDIE(DbgScope *Scope) { unsigned StartID = MMI->MappedLabel(Scope->getStartLabelID()); unsigned EndID = MMI->MappedLabel(Scope->getEndLabelID()); @@ -1338,11 +1338,11 @@ if (Scope->isAbstractScope()) return ScopeDIE; - AddLabel(ScopeDIE, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr, + addLabel(ScopeDIE, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr, StartID ? DWLabel("label", StartID) : DWLabel("func_begin", SubprogramCount)); - AddLabel(ScopeDIE, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr, + addLabel(ScopeDIE, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr, EndID ? DWLabel("label", EndID) : DWLabel("func_end", SubprogramCount)); @@ -1352,7 +1352,10 @@ return ScopeDIE; } -DIE *DwarfDebug::ConstructInlinedScopeDIE(DbgScope *Scope) { +/// constructInlinedScopeDIE - This scope represents inlined body of +/// a function. Construct DIE to represent this concrete inlined copy +/// of the function. +DIE *DwarfDebug::constructInlinedScopeDIE(DbgScope *Scope) { unsigned StartID = MMI->MappedLabel(Scope->getStartLabelID()); unsigned EndID = MMI->MappedLabel(Scope->getEndLabelID()); assert (StartID && "Invalid starting label for an inlined scope!"); @@ -1369,12 +1372,12 @@ DISubprogram InlinedSP = getDISubprogram(DS.getNode()); DIE *OriginDIE = ModuleCU->getDIE(InlinedSP.getNode()); assert (OriginDIE && "Unable to find Origin DIE!"); - AddDIEEntry(ScopeDIE, dwarf::DW_AT_abstract_origin, + addDIEEntry(ScopeDIE, dwarf::DW_AT_abstract_origin, dwarf::DW_FORM_ref4, OriginDIE); - AddLabel(ScopeDIE, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr, + addLabel(ScopeDIE, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr, DWLabel("label", StartID)); - AddLabel(ScopeDIE, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr, + addLabel(ScopeDIE, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr, DWLabel("label", EndID)); InlinedSubprogramDIEs.insert(OriginDIE); @@ -1392,13 +1395,15 @@ StringPool.insert(InlinedSP.getName()); StringPool.insert(InlinedSP.getLinkageName()); DILocation DL(Scope->getInlinedAt()); - AddUInt(ScopeDIE, dwarf::DW_AT_call_file, 0, ModuleCU->getID()); - AddUInt(ScopeDIE, dwarf::DW_AT_call_line, 0, DL.getLineNumber()); + addUInt(ScopeDIE, dwarf::DW_AT_call_file, 0, ModuleCU->getID()); + addUInt(ScopeDIE, dwarf::DW_AT_call_line, 0, DL.getLineNumber()); return ScopeDIE; } -DIE *DwarfDebug::ConstructVariableDIE(DbgVariable *DV, + +/// constructVariableDIE - Construct a DIE for the given DbgVariable. +DIE *DwarfDebug::constructVariableDIE(DbgVariable *DV, DbgScope *Scope, CompileUnit *Unit) { // Get the descriptor. const DIVariable &VD = DV->getVariable(); @@ -1437,20 +1442,20 @@ assert (OriginSPDIE && "Unable to find Origin DIE for the SP!"); DIE *AbsDIE = DV->getAbstractVariable()->getDIE(); assert (AbsDIE && "Unable to find Origin DIE for the Variable!"); - AddDIEEntry(VariableDie, dwarf::DW_AT_abstract_origin, + addDIEEntry(VariableDie, dwarf::DW_AT_abstract_origin, dwarf::DW_FORM_ref4, AbsDIE); } else { - AddString(VariableDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); - AddSourceLine(VariableDie, &VD); + addString(VariableDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name); + addSourceLine(VariableDie, &VD); // Add variable type. // FIXME: isBlockByrefVariable should be reformulated in terms of complex // addresses instead. if (VD.isBlockByrefVariable()) - AddType(Unit, VariableDie, GetBlockByrefType(VD.getType(), Name)); + addType(Unit, VariableDie, getBlockByrefType(VD.getType(), Name)); else - AddType(Unit, VariableDie, VD.getType()); + addType(Unit, VariableDie, VD.getType()); } // Add variable address. @@ -1461,17 +1466,19 @@ if (VD.hasComplexAddress()) - AddComplexAddress(DV, VariableDie, dwarf::DW_AT_location, Location); + addComplexAddress(DV, VariableDie, dwarf::DW_AT_location, Location); else if (VD.isBlockByrefVariable()) - AddBlockByrefAddress(DV, VariableDie, dwarf::DW_AT_location, Location); + addBlockByrefAddress(DV, VariableDie, dwarf::DW_AT_location, Location); else - AddAddress(VariableDie, dwarf::DW_AT_location, Location); + addAddress(VariableDie, dwarf::DW_AT_location, Location); } DV->setDIE(VariableDie); return VariableDie; } -DIE *DwarfDebug::ConstructScopeDIE(DbgScope *Scope) { + +/// constructScopeDIE - Construct a DIE for this scope. +DIE *DwarfDebug::constructScopeDIE(DbgScope *Scope) { if (!Scope) return NULL; DIScope DS(Scope->getScopeNode()); @@ -1480,33 +1487,33 @@ DIE *ScopeDIE = NULL; if (Scope->getInlinedAt()) - ScopeDIE = ConstructInlinedScopeDIE(Scope); + ScopeDIE = constructInlinedScopeDIE(Scope); else if (DS.isSubprogram()) { if (Scope->isAbstractScope()) ScopeDIE = ModuleCU->getDIE(DS.getNode()); else - ScopeDIE = UpdateSubprogramScopeDIE(DS.getNode()); + ScopeDIE = updateSubprogramScopeDIE(DS.getNode()); } else { - ScopeDIE = ConstructLexicalScopeDIE(Scope); + ScopeDIE = constructLexicalScopeDIE(Scope); if (!ScopeDIE) return NULL; } // Add variables to scope. SmallVector &Variables = Scope->getVariables(); for (unsigned i = 0, N = Variables.size(); i < N; ++i) { - DIE *VariableDIE = ConstructVariableDIE(Variables[i], Scope, ModuleCU); + DIE *VariableDIE = constructVariableDIE(Variables[i], Scope, ModuleCU); if (VariableDIE) - ScopeDIE->AddChild(VariableDIE); + ScopeDIE->addChild(VariableDIE); } // Add nested scopes. SmallVector &Scopes = Scope->getScopes(); for (unsigned j = 0, M = Scopes.size(); j < M; ++j) { // Define the Scope debug information entry. - DIE *NestedDIE = ConstructScopeDIE(Scopes[j]); + DIE *NestedDIE = constructScopeDIE(Scopes[j]); if (NestedDIE) - ScopeDIE->AddChild(NestedDIE); + ScopeDIE->addChild(NestedDIE); } return ScopeDIE; } @@ -1549,33 +1556,33 @@ return SrcId; } -void DwarfDebug::ConstructCompileUnit(MDNode *N) { +void DwarfDebug::constructCompileUnit(MDNode *N) { DICompileUnit DIUnit(N); const char *FN = DIUnit.getFilename(); const char *Dir = DIUnit.getDirectory(); unsigned ID = GetOrCreateSourceID(Dir, FN); DIE *Die = new DIE(dwarf::DW_TAG_compile_unit); - AddSectionOffset(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4, + addSectionOffset(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4, DWLabel("section_line", 0), DWLabel("section_line", 0), false); - AddString(Die, dwarf::DW_AT_producer, dwarf::DW_FORM_string, + addString(Die, dwarf::DW_AT_producer, dwarf::DW_FORM_string, DIUnit.getProducer()); - AddUInt(Die, dwarf::DW_AT_language, dwarf::DW_FORM_data1, + addUInt(Die, dwarf::DW_AT_language, dwarf::DW_FORM_data1, DIUnit.getLanguage()); - AddString(Die, dwarf::DW_AT_name, dwarf::DW_FORM_string, FN); + addString(Die, dwarf::DW_AT_name, dwarf::DW_FORM_string, FN); if (Dir) - AddString(Die, dwarf::DW_AT_comp_dir, dwarf::DW_FORM_string, Dir); + addString(Die, dwarf::DW_AT_comp_dir, dwarf::DW_FORM_string, Dir); if (DIUnit.isOptimized()) - AddUInt(Die, dwarf::DW_AT_APPLE_optimized, dwarf::DW_FORM_flag, 1); + addUInt(Die, dwarf::DW_AT_APPLE_optimized, dwarf::DW_FORM_flag, 1); if (const char *Flags = DIUnit.getFlags()) - AddString(Die, dwarf::DW_AT_APPLE_flags, dwarf::DW_FORM_string, Flags); + addString(Die, dwarf::DW_AT_APPLE_flags, dwarf::DW_FORM_string, Flags); unsigned RVer = DIUnit.getRunTimeVersion(); if (RVer) - AddUInt(Die, dwarf::DW_AT_APPLE_major_runtime_vers, + addUInt(Die, dwarf::DW_AT_APPLE_major_runtime_vers, dwarf::DW_FORM_data1, RVer); CompileUnit *Unit = new CompileUnit(ID, Die); @@ -1589,7 +1596,7 @@ CompileUnits.push_back(Unit); } -void DwarfDebug::ConstructGlobalVariableDIE(MDNode *N) { +void DwarfDebug::constructGlobalVariableDIE(MDNode *N) { DIGlobalVariable DI_GV(N); // If debug information is malformed then ignore it. @@ -1600,20 +1607,20 @@ if (ModuleCU->getDIE(DI_GV.getNode())) return; - DIE *VariableDie = CreateGlobalVariableDIE(ModuleCU, DI_GV); + DIE *VariableDie = createGlobalVariableDIE(ModuleCU, DI_GV); // Add to map. ModuleCU->insertDIE(N, VariableDie); // Add to context owner. - ModuleCU->getCUDie()->AddChild(VariableDie); + ModuleCU->getCUDie()->addChild(VariableDie); // Expose as global. FIXME - need to check external flag. - ModuleCU->AddGlobal(DI_GV.getName(), VariableDie); + ModuleCU->addGlobal(DI_GV.getName(), VariableDie); return; } -void DwarfDebug::ConstructSubprogram(MDNode *N) { +void DwarfDebug::constructSubprogramDIE(MDNode *N) { DISubprogram SP(N); // Check for pre-existence. @@ -1625,23 +1632,23 @@ // class type. return; - DIE *SubprogramDie = CreateSubprogramDIE(ModuleCU, SP); + DIE *SubprogramDie = createSubprogramDIE(ModuleCU, SP); // Add to map. ModuleCU->insertDIE(N, SubprogramDie); // Add to context owner. - ModuleCU->getCUDie()->AddChild(SubprogramDie); + ModuleCU->getCUDie()->addChild(SubprogramDie); // Expose as global. - ModuleCU->AddGlobal(SP.getName(), SubprogramDie); + ModuleCU->addGlobal(SP.getName(), SubprogramDie); return; } -/// BeginModule - Emit all Dwarf sections that should come prior to the +/// beginModule - Emit all Dwarf sections that should come prior to the /// content. Create global DIEs and emit initial debug info sections. /// This is inovked by the target AsmPrinter. -void DwarfDebug::BeginModule(Module *M, MachineModuleInfo *mmi) { +void DwarfDebug::beginModule(Module *M, MachineModuleInfo *mmi) { this->M = M; if (TimePassesIsEnabled) @@ -1656,7 +1663,7 @@ // Create all the compile unit DIEs. for (DebugInfoFinder::iterator I = DbgFinder.compile_unit_begin(), E = DbgFinder.compile_unit_end(); I != E; ++I) - ConstructCompileUnit(*I); + constructCompileUnit(*I); if (CompileUnits.empty()) { if (TimePassesIsEnabled) @@ -1677,13 +1684,13 @@ if (GV.getContext().getNode() != GV.getCompileUnit().getNode()) ScopedGVs.push_back(*I); else - ConstructGlobalVariableDIE(*I); + constructGlobalVariableDIE(*I); } // Create DIEs for each subprogram. for (DebugInfoFinder::iterator I = DbgFinder.subprogram_begin(), E = DbgFinder.subprogram_end(); I != E; ++I) - ConstructSubprogram(*I); + constructSubprogramDIE(*I); MMI = mmi; shouldEmit = true; @@ -1709,15 +1716,15 @@ } // Emit initial sections - EmitInitial(); + emitInitial(); if (TimePassesIsEnabled) DebugTimer->stopTimer(); } -/// EndModule - Emit all Dwarf sections that should come after the content. +/// endModule - Emit all Dwarf sections that should come after the content. /// -void DwarfDebug::EndModule() { +void DwarfDebug::endModule() { if (!ModuleCU) return; @@ -1728,7 +1735,7 @@ for (SmallPtrSet::iterator AI = InlinedSubprogramDIEs.begin(), AE = InlinedSubprogramDIEs.end(); AI != AE; ++AI) { DIE *ISP = *AI; - AddUInt(ISP, dwarf::DW_AT_inline, 0, dwarf::DW_INL_inlined); + addUInt(ISP, dwarf::DW_AT_inline, 0, dwarf::DW_INL_inlined); } // Standard sections final addresses. @@ -1744,45 +1751,45 @@ } // Emit common frame information. - EmitCommonDebugFrame(); + emitCommonDebugFrame(); // Emit function debug frame information for (std::vector::iterator I = DebugFrames.begin(), E = DebugFrames.end(); I != E; ++I) - EmitFunctionDebugFrame(*I); + emitFunctionDebugFrame(*I); // Compute DIE offsets and sizes. - SizeAndOffsets(); + computeSizeAndOffsets(); // Emit all the DIEs into a debug info section - EmitDebugInfo(); + emitDebugInfo(); // Corresponding abbreviations into a abbrev section. - EmitAbbreviations(); + emitAbbreviations(); // Emit source line correspondence into a debug line section. - EmitDebugLines(); + emitDebugLines(); // Emit info into a debug pubnames section. - EmitDebugPubNames(); + emitDebugPubNames(); // Emit info into a debug str section. - EmitDebugStr(); + emitDebugStr(); // Emit info into a debug loc section. - EmitDebugLoc(); + emitDebugLoc(); // Emit info into a debug aranges section. EmitDebugARanges(); // Emit info into a debug ranges section. - EmitDebugRanges(); + emitDebugRanges(); // Emit info into a debug macinfo section. - EmitDebugMacInfo(); + emitDebugMacInfo(); // Emit inline info. - EmitDebugInlineInfo(); + emitDebugInlineInfo(); if (TimePassesIsEnabled) DebugTimer->stopTimer(); @@ -1801,13 +1808,13 @@ return NULL; AbsDbgVariable = new DbgVariable(Var, FrameIdx); - Scope->AddVariable(AbsDbgVariable); + Scope->addVariable(AbsDbgVariable); AbstractVariables[Var.getNode()] = AbsDbgVariable; return AbsDbgVariable; } -/// CollectVariableInfo - Populate DbgScope entries with variables' info. -void DwarfDebug::CollectVariableInfo() { +/// collectVariableInfo - Populate DbgScope entries with variables' info. +void DwarfDebug::collectVariableInfo() { if (!MMI) return; MachineModuleInfo::VariableDbgInfoMapTy &VMap = MMI->getVariableDbgInfo(); @@ -1829,14 +1836,14 @@ continue; DbgVariable *RegVar = new DbgVariable(DV, VP.first); - Scope->AddVariable(RegVar); + Scope->addVariable(RegVar); if (DbgVariable *AbsDbgVariable = findAbstractVariable(DV, VP.first, ScopeLoc)) RegVar->setAbstractVariable(AbsDbgVariable); } } -/// BeginScope - Process beginning of a scope starting at Label. -void DwarfDebug::BeginScope(const MachineInstr *MI, unsigned Label) { +/// beginScope - Process beginning of a scope starting at Label. +void DwarfDebug::beginScope(const MachineInstr *MI, unsigned Label) { InsnToDbgScopeMapTy::iterator I = DbgScopeBeginMap.find(MI); if (I == DbgScopeBeginMap.end()) return; @@ -1846,8 +1853,8 @@ (*SDI)->setStartLabelID(Label); } -/// EndScope - Process end of a scope. -void DwarfDebug::EndScope(const MachineInstr *MI) { +/// endScope - Process end of a scope. +void DwarfDebug::endScope(const MachineInstr *MI) { InsnToDbgScopeMapTy::iterator I = DbgScopeEndMap.find(MI); if (I == DbgScopeEndMap.end()) return; @@ -1886,9 +1893,9 @@ createDbgScope(DL.getScope().getNode(), DL.getOrigLocation().getNode()); } -/// ExtractScopeInformation - Scan machine instructions in this function +/// extractScopeInformation - Scan machine instructions in this function /// and collect DbgScopes. Return true, if atleast one scope was found. -bool DwarfDebug::ExtractScopeInformation(MachineFunction *MF) { +bool DwarfDebug::extractScopeInformation(MachineFunction *MF) { // If scope information was extracted using .dbg intrinsics then there is not // any need to extract these information by scanning each instruction. if (!DbgScopeMap.empty()) @@ -1939,7 +1946,7 @@ if (DI->second->isAbstractScope()) continue; assert (DI->second->getFirstInsn() && "Invalid first instruction!"); - DI->second->FixInstructionMarkers(); + DI->second->fixInstructionMarkers(); assert (DI->second->getLastInsn() && "Invalid last instruction!"); } @@ -1973,9 +1980,9 @@ return !DbgScopeMap.empty(); } -/// BeginFunction - Gather pre-function debug information. Assumes being +/// beginFunction - Gather pre-function debug information. Assumes being /// emitted immediately after the function entry point. -void DwarfDebug::BeginFunction(MachineFunction *MF) { +void DwarfDebug::beginFunction(MachineFunction *MF) { this->MF = MF; if (!ShouldEmitDwarfDebug()) return; @@ -1983,9 +1990,10 @@ if (TimePassesIsEnabled) DebugTimer->startTimer(); - if (!ExtractScopeInformation(MF)) + if (!extractScopeInformation(MF)) return; - CollectVariableInfo(); + + collectVariableInfo(); // Begin accumulating function debug information. MMI->BeginFunction(MF); @@ -2001,9 +2009,9 @@ unsigned LabelID = 0; DISubprogram SP = getDISubprogram(DLT.Scope); if (!SP.isNull()) - LabelID = RecordSourceLine(SP.getLineNumber(), 0, DLT.Scope); + LabelID = recordSourceLine(SP.getLineNumber(), 0, DLT.Scope); else - LabelID = RecordSourceLine(DLT.Line, DLT.Col, DLT.Scope); + LabelID = recordSourceLine(DLT.Line, DLT.Col, DLT.Scope); Asm->printLabel(LabelID); O << '\n'; } @@ -2011,9 +2019,9 @@ DebugTimer->stopTimer(); } -/// EndFunction - Gather and emit post-function debug information. +/// endFunction - Gather and emit post-function debug information. /// -void DwarfDebug::EndFunction(MachineFunction *MF) { +void DwarfDebug::endFunction(MachineFunction *MF) { if (!ShouldEmitDwarfDebug()) return; if (TimePassesIsEnabled) @@ -2039,9 +2047,9 @@ // Construct abstract scopes. for (SmallVector::iterator AI = AbstractScopesList.begin(), AE = AbstractScopesList.end(); AI != AE; ++AI) - ConstructScopeDIE(*AI); + constructScopeDIE(*AI); - ConstructScopeDIE(CurrentFnDbgScope); + constructScopeDIE(CurrentFnDbgScope); DebugFrames.push_back(FunctionDebugFrameInfo(SubprogramCount, MMI->getFrameMoves())); @@ -2062,10 +2070,10 @@ DebugTimer->stopTimer(); } -/// RecordSourceLine - Records location information and associates it with a +/// recordSourceLine - Records location information and associates it with a /// label. Returns a unique label ID used to generate a label and provide /// correspondence to the source line list. -unsigned DwarfDebug::RecordSourceLine(unsigned Line, unsigned Col, +unsigned DwarfDebug::recordSourceLine(unsigned Line, unsigned Col, MDNode *S) { if (!MMI) return 0; @@ -2124,17 +2132,17 @@ // Emit Methods //===----------------------------------------------------------------------===// -/// SizeAndOffsetDie - Compute the size and offset of a DIE. +/// computeSizeAndOffset - Compute the size and offset of a DIE. /// -unsigned DwarfDebug::SizeAndOffsetDie(DIE *Die, unsigned Offset, bool Last) { +unsigned DwarfDebug::computeSizeAndOffset(DIE *Die, unsigned Offset, bool Last) { // Get the children. const std::vector &Children = Die->getChildren(); // If not last sibling and has children then add sibling offset attribute. - if (!Last && !Children.empty()) Die->AddSiblingOffset(); + if (!Last && !Children.empty()) Die->addSiblingOffset(); // Record the abbreviation. - AssignAbbrevNumber(Die->getAbbrev()); + assignAbbrevNumber(Die->getAbbrev()); // Get the abbreviation for this DIE. unsigned AbbrevNumber = Die->getAbbrevNumber(); @@ -2160,7 +2168,7 @@ "Children flag not set"); for (unsigned j = 0, M = Children.size(); j < M; ++j) - Offset = SizeAndOffsetDie(Children[j], Offset, (j + 1) == M); + Offset = computeSizeAndOffset(Children[j], Offset, (j + 1) == M); // End of children marker. Offset += sizeof(int8_t); @@ -2170,9 +2178,9 @@ return Offset; } -/// SizeAndOffsets - Compute the size and offset of all the DIEs. +/// computeSizeAndOffsets - Compute the size and offset of all the DIEs. /// -void DwarfDebug::SizeAndOffsets() { +void DwarfDebug::computeSizeAndOffsets() { // Compute size of compile unit header. static unsigned Offset = sizeof(int32_t) + // Length of Compilation Unit Info @@ -2180,13 +2188,13 @@ sizeof(int32_t) + // Offset Into Abbrev. Section sizeof(int8_t); // Pointer Size (in bytes) - SizeAndOffsetDie(ModuleCU->getCUDie(), Offset, true); + computeSizeAndOffset(ModuleCU->getCUDie(), Offset, true); CompileUnitOffsets[ModuleCU] = 0; } -/// EmitInitial - Emit initial Dwarf declarations. This is necessary for cc +/// emitInitial - Emit initial Dwarf declarations. This is necessary for cc /// tools to recognize the object file contains Dwarf information. -void DwarfDebug::EmitInitial() { +void DwarfDebug::emitInitial() { // Check to see if we already emitted intial headers. if (didInitial) return; didInitial = true; @@ -2228,9 +2236,9 @@ EmitLabel("data_begin", 0); } -/// EmitDIE - Recusively Emits a debug information entry. +/// emitDIE - Recusively Emits a debug information entry. /// -void DwarfDebug::EmitDIE(DIE *Die) { +void DwarfDebug::emitDIE(DIE *Die) { // Get the abbreviation for this DIE. unsigned AbbrevNumber = Die->getAbbrevNumber(); const DIEAbbrev *Abbrev = Abbreviations[AbbrevNumber - 1]; @@ -2260,7 +2268,7 @@ switch (Attr) { case dwarf::DW_AT_sibling: - Asm->EmitInt32(Die->SiblingOffset()); + Asm->EmitInt32(Die->getSiblingOffset()); break; case dwarf::DW_AT_abstract_origin: { DIEEntry *E = cast(Values[i]); @@ -2283,15 +2291,15 @@ const std::vector &Children = Die->getChildren(); for (unsigned j = 0, M = Children.size(); j < M; ++j) - EmitDIE(Children[j]); + emitDIE(Children[j]); Asm->EmitInt8(0); Asm->EOL("End Of Children Mark"); } } -/// EmitDebugInfo / EmitDebugInfoPerCU - Emit the debug info section. +/// emitDebugInfo / emitDebugInfoPerCU - Emit the debug info section. /// -void DwarfDebug::EmitDebugInfoPerCU(CompileUnit *Unit) { +void DwarfDebug::emitDebugInfoPerCU(CompileUnit *Unit) { DIE *Die = Unit->getCUDie(); // Emit the compile units header. @@ -2310,7 +2318,7 @@ Asm->EOL("Offset Into Abbrev. Section"); Asm->EmitInt8(TD->getPointerSize()); Asm->EOL("Address Size (in bytes)"); - EmitDIE(Die); + emitDIE(Die); // FIXME - extra padding for gdb bug. Asm->EmitInt8(0); Asm->EOL("Extra Pad For GDB"); Asm->EmitInt8(0); Asm->EOL("Extra Pad For GDB"); @@ -2321,17 +2329,17 @@ Asm->EOL(); } -void DwarfDebug::EmitDebugInfo() { +void DwarfDebug::emitDebugInfo() { // Start debug info section. Asm->OutStreamer.SwitchSection( Asm->getObjFileLowering().getDwarfInfoSection()); - EmitDebugInfoPerCU(ModuleCU); + emitDebugInfoPerCU(ModuleCU); } -/// EmitAbbreviations - Emit the abbreviation section. +/// emitAbbreviations - Emit the abbreviation section. /// -void DwarfDebug::EmitAbbreviations() const { +void DwarfDebug::emitAbbreviations() const { // Check to see if it is worth the effort. if (!Abbreviations.empty()) { // Start the debug abbrev section. @@ -2363,10 +2371,10 @@ } } -/// EmitEndOfLineMatrix - Emit the last address of the section and the end of +/// emitEndOfLineMatrix - Emit the last address of the section and the end of /// the line matrix. /// -void DwarfDebug::EmitEndOfLineMatrix(unsigned SectionEnd) { +void DwarfDebug::emitEndOfLineMatrix(unsigned SectionEnd) { // Define last address of section. Asm->EmitInt8(0); Asm->EOL("Extended Op"); Asm->EmitInt8(TD->getPointerSize() + 1); Asm->EOL("Op size"); @@ -2379,9 +2387,9 @@ Asm->EmitInt8(1); Asm->EOL(); } -/// EmitDebugLines - Emit source line information. +/// emitDebugLines - Emit source line information. /// -void DwarfDebug::EmitDebugLines() { +void DwarfDebug::emitDebugLines() { // If the target is using .loc/.file, the assembler will be emitting the // .debug_line table automatically. if (MAI->hasDotLocAndDotFile()) @@ -2530,22 +2538,22 @@ } } - EmitEndOfLineMatrix(j + 1); + emitEndOfLineMatrix(j + 1); } if (SecSrcLinesSize == 0) // Because we're emitting a debug_line section, we still need a line // table. The linker and friends expect it to exist. If there's nothing to // put into it, emit an empty table. - EmitEndOfLineMatrix(1); + emitEndOfLineMatrix(1); EmitLabel("line_end", 0); Asm->EOL(); } -/// EmitCommonDebugFrame - Emit common frame info into a debug frame section. +/// emitCommonDebugFrame - Emit common frame info into a debug frame section. /// -void DwarfDebug::EmitCommonDebugFrame() { +void DwarfDebug::emitCommonDebugFrame() { if (!MAI->doesDwarfRequireFrameSection()) return; @@ -2588,10 +2596,10 @@ Asm->EOL(); } -/// EmitFunctionDebugFrame - Emit per function frame info into a debug frame +/// emitFunctionDebugFrame - Emit per function frame info into a debug frame /// section. void -DwarfDebug::EmitFunctionDebugFrame(const FunctionDebugFrameInfo&DebugFrameInfo){ +DwarfDebug::emitFunctionDebugFrame(const FunctionDebugFrameInfo&DebugFrameInfo){ if (!MAI->doesDwarfRequireFrameSection()) return; @@ -2624,7 +2632,7 @@ Asm->EOL(); } -void DwarfDebug::EmitDebugPubNamesPerCU(CompileUnit *Unit) { +void DwarfDebug::emitDebugPubNamesPerCU(CompileUnit *Unit) { EmitDifference("pubnames_end", Unit->getID(), "pubnames_begin", Unit->getID(), true); Asm->EOL("Length of Public Names Info"); @@ -2657,19 +2665,19 @@ Asm->EOL(); } -/// EmitDebugPubNames - Emit visible names into a debug pubnames section. +/// emitDebugPubNames - Emit visible names into a debug pubnames section. /// -void DwarfDebug::EmitDebugPubNames() { +void DwarfDebug::emitDebugPubNames() { // Start the dwarf pubnames section. Asm->OutStreamer.SwitchSection( Asm->getObjFileLowering().getDwarfPubNamesSection()); - EmitDebugPubNamesPerCU(ModuleCU); + emitDebugPubNamesPerCU(ModuleCU); } -/// EmitDebugStr - Emit visible names into a debug str section. +/// emitDebugStr - Emit visible names into a debug str section. /// -void DwarfDebug::EmitDebugStr() { +void DwarfDebug::emitDebugStr() { // Check to see if it is worth the effort. if (!StringPool.empty()) { // Start the dwarf str section. @@ -2691,9 +2699,9 @@ } } -/// EmitDebugLoc - Emit visible names into a debug loc section. +/// emitDebugLoc - Emit visible names into a debug loc section. /// -void DwarfDebug::EmitDebugLoc() { +void DwarfDebug::emitDebugLoc() { // Start the dwarf loc section. Asm->OutStreamer.SwitchSection( Asm->getObjFileLowering().getDwarfLocSection()); @@ -2737,18 +2745,18 @@ Asm->EOL(); } -/// EmitDebugRanges - Emit visible names into a debug ranges section. +/// emitDebugRanges - Emit visible names into a debug ranges section. /// -void DwarfDebug::EmitDebugRanges() { +void DwarfDebug::emitDebugRanges() { // Start the dwarf ranges section. Asm->OutStreamer.SwitchSection( Asm->getObjFileLowering().getDwarfRangesSection()); Asm->EOL(); } -/// EmitDebugMacInfo - Emit visible names into a debug macinfo section. +/// emitDebugMacInfo - Emit visible names into a debug macinfo section. /// -void DwarfDebug::EmitDebugMacInfo() { +void DwarfDebug::emitDebugMacInfo() { if (const MCSection *LineInfo = Asm->getObjFileLowering().getDwarfMacroInfoSection()) { // Start the dwarf macinfo section. @@ -2757,7 +2765,7 @@ } } -/// EmitDebugInlineInfo - Emit inline info using following format. +/// emitDebugInlineInfo - Emit inline info using following format. /// Section Header: /// 1. length of section /// 2. Dwarf version number @@ -2775,7 +2783,7 @@ /// inlined instance; the die_offset points to the inlined_subroutine die in the /// __debug_info section, and the low_pc is the starting address for the /// inlining instance. -void DwarfDebug::EmitDebugInlineInfo() { +void DwarfDebug::emitDebugInlineInfo() { if (!MAI->doesDwarfUsesInlineInfoSection()) return; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=89537&r1=89536&r2=89537&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Fri Nov 20 20:48:08 2009 @@ -106,9 +106,9 @@ /// Lines - List of of source line correspondence. std::vector Lines; - /// Values - A list of all the unique values in use. + /// DIEValues - A list of all the unique values in use. /// - std::vector Values; + std::vector DIEValues; /// StringPool - A UniqueVector of strings used by indirect references. /// @@ -225,137 +225,133 @@ return SourceIds.size(); } - /// AssignAbbrevNumber - Define a unique number for the abbreviation. + /// assignAbbrevNumber - Define a unique number for the abbreviation. /// - void AssignAbbrevNumber(DIEAbbrev &Abbrev); + void assignAbbrevNumber(DIEAbbrev &Abbrev); - /// CreateDIEEntry - Creates a new DIEEntry to be a proxy for a debug + /// createDIEEntry - Creates a new DIEEntry to be a proxy for a debug /// information entry. - DIEEntry *CreateDIEEntry(DIE *Entry = NULL); + DIEEntry *createDIEEntry(DIE *Entry = NULL); - /// SetDIEEntry - Set a DIEEntry once the debug information entry is defined. + /// addUInt - Add an unsigned integer attribute data and value. /// - void SetDIEEntry(DIEEntry *Value, DIE *Entry); + void addUInt(DIE *Die, unsigned Attribute, unsigned Form, uint64_t Integer); - /// AddUInt - Add an unsigned integer attribute data and value. + /// addSInt - Add an signed integer attribute data and value. /// - void AddUInt(DIE *Die, unsigned Attribute, unsigned Form, uint64_t Integer); + void addSInt(DIE *Die, unsigned Attribute, unsigned Form, int64_t Integer); - /// AddSInt - Add an signed integer attribute data and value. + /// addString - Add a string attribute data and value. /// - void AddSInt(DIE *Die, unsigned Attribute, unsigned Form, int64_t Integer); - - /// AddString - Add a string attribute data and value. - /// - void AddString(DIE *Die, unsigned Attribute, unsigned Form, + void addString(DIE *Die, unsigned Attribute, unsigned Form, const std::string &String); - /// AddLabel - Add a Dwarf label attribute data and value. + /// addLabel - Add a Dwarf label attribute data and value. /// - void AddLabel(DIE *Die, unsigned Attribute, unsigned Form, + void addLabel(DIE *Die, unsigned Attribute, unsigned Form, const DWLabel &Label); - /// AddObjectLabel - Add an non-Dwarf label attribute data and value. + /// addObjectLabel - Add an non-Dwarf label attribute data and value. /// - void AddObjectLabel(DIE *Die, unsigned Attribute, unsigned Form, + void addObjectLabel(DIE *Die, unsigned Attribute, unsigned Form, const std::string &Label); - /// AddSectionOffset - Add a section offset label attribute data and value. + /// addSectionOffset - Add a section offset label attribute data and value. /// - void AddSectionOffset(DIE *Die, unsigned Attribute, unsigned Form, + void addSectionOffset(DIE *Die, unsigned Attribute, unsigned Form, const DWLabel &Label, const DWLabel &Section, bool isEH = false, bool useSet = true); - /// AddDelta - Add a label delta attribute data and value. + /// addDelta - Add a label delta attribute data and value. /// - void AddDelta(DIE *Die, unsigned Attribute, unsigned Form, + void addDelta(DIE *Die, unsigned Attribute, unsigned Form, const DWLabel &Hi, const DWLabel &Lo); - /// AddDIEEntry - Add a DIE attribute data and value. + /// addDIEEntry - Add a DIE attribute data and value. /// - void AddDIEEntry(DIE *Die, unsigned Attribute, unsigned Form, DIE *Entry) { - Die->AddValue(Attribute, Form, CreateDIEEntry(Entry)); + void addDIEEntry(DIE *Die, unsigned Attribute, unsigned Form, DIE *Entry) { + Die->addValue(Attribute, Form, createDIEEntry(Entry)); } - /// AddBlock - Add block data. + /// addBlock - Add block data. /// - void AddBlock(DIE *Die, unsigned Attribute, unsigned Form, DIEBlock *Block); + void addBlock(DIE *Die, unsigned Attribute, unsigned Form, DIEBlock *Block); - /// AddSourceLine - Add location information to specified debug information + /// addSourceLine - Add location information to specified debug information /// entry. - void AddSourceLine(DIE *Die, const DIVariable *V); - void AddSourceLine(DIE *Die, const DIGlobal *G); - void AddSourceLine(DIE *Die, const DISubprogram *SP); - void AddSourceLine(DIE *Die, const DIType *Ty); + void addSourceLine(DIE *Die, const DIVariable *V); + void addSourceLine(DIE *Die, const DIGlobal *G); + void addSourceLine(DIE *Die, const DISubprogram *SP); + void addSourceLine(DIE *Die, const DIType *Ty); - /// AddAddress - Add an address attribute to a die based on the location + /// addAddress - Add an address attribute to a die based on the location /// provided. - void AddAddress(DIE *Die, unsigned Attribute, + void addAddress(DIE *Die, unsigned Attribute, const MachineLocation &Location); - /// AddComplexAddress - Start with the address based on the location provided, + /// addComplexAddress - Start with the address based on the location provided, /// and generate the DWARF information necessary to find the actual variable /// (navigating the extra location information encoded in the type) based on /// the starting location. Add the DWARF information to the die. /// - void AddComplexAddress(DbgVariable *&DV, DIE *Die, unsigned Attribute, + void addComplexAddress(DbgVariable *&DV, DIE *Die, unsigned Attribute, const MachineLocation &Location); - // FIXME: Should be reformulated in terms of AddComplexAddress. - /// AddBlockByrefAddress - Start with the address based on the location + // FIXME: Should be reformulated in terms of addComplexAddress. + /// addBlockByrefAddress - Start with the address based on the location /// provided, and generate the DWARF information necessary to find the /// actual Block variable (navigating the Block struct) based on the /// starting location. Add the DWARF information to the die. Obsolete, - /// please use AddComplexAddress instead. + /// please use addComplexAddress instead. /// - void AddBlockByrefAddress(DbgVariable *&DV, DIE *Die, unsigned Attribute, + void addBlockByrefAddress(DbgVariable *&DV, DIE *Die, unsigned Attribute, const MachineLocation &Location); - /// AddType - Add a new type attribute to the specified entity. - void AddType(CompileUnit *DW_Unit, DIE *Entity, DIType Ty); + /// addType - Add a new type attribute to the specified entity. + void addType(CompileUnit *DW_Unit, DIE *Entity, DIType Ty); - /// ConstructTypeDIE - Construct basic type die from DIBasicType. - void ConstructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, + /// constructTypeDIE - Construct basic type die from DIBasicType. + void constructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, DIBasicType BTy); - /// ConstructTypeDIE - Construct derived type die from DIDerivedType. - void ConstructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, + /// constructTypeDIE - Construct derived type die from DIDerivedType. + void constructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, DIDerivedType DTy); - /// ConstructTypeDIE - Construct type DIE from DICompositeType. - void ConstructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, + /// constructTypeDIE - Construct type DIE from DICompositeType. + void constructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, DICompositeType CTy); - /// ConstructSubrangeDIE - Construct subrange DIE from DISubrange. - void ConstructSubrangeDIE(DIE &Buffer, DISubrange SR, DIE *IndexTy); + /// constructSubrangeDIE - Construct subrange DIE from DISubrange. + void constructSubrangeDIE(DIE &Buffer, DISubrange SR, DIE *IndexTy); - /// ConstructArrayTypeDIE - Construct array type DIE from DICompositeType. - void ConstructArrayTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, + /// constructArrayTypeDIE - Construct array type DIE from DICompositeType. + void constructArrayTypeDIE(CompileUnit *DW_Unit, DIE &Buffer, DICompositeType *CTy); - /// ConstructEnumTypeDIE - Construct enum type DIE from DIEnumerator. - DIE *ConstructEnumTypeDIE(CompileUnit *DW_Unit, DIEnumerator *ETy); + /// constructEnumTypeDIE - Construct enum type DIE from DIEnumerator. + DIE *constructEnumTypeDIE(CompileUnit *DW_Unit, DIEnumerator *ETy); - /// CreateGlobalVariableDIE - Create new DIE using GV. - DIE *CreateGlobalVariableDIE(CompileUnit *DW_Unit, + /// createGlobalVariableDIE - Create new DIE using GV. + DIE *createGlobalVariableDIE(CompileUnit *DW_Unit, const DIGlobalVariable &GV); - /// CreateMemberDIE - Create new member DIE. - DIE *CreateMemberDIE(CompileUnit *DW_Unit, const DIDerivedType &DT); + /// createMemberDIE - Create new member DIE. + DIE *createMemberDIE(CompileUnit *DW_Unit, const DIDerivedType &DT); - /// CreateSubprogramDIE - Create new DIE using SP. - DIE *CreateSubprogramDIE(CompileUnit *DW_Unit, + /// createSubprogramDIE - Create new DIE using SP. + DIE *createSubprogramDIE(CompileUnit *DW_Unit, const DISubprogram &SP, bool IsConstructor = false, bool IsInlined = false); - /// FindCompileUnit - Get the compile unit for the given descriptor. + /// findCompileUnit - Get the compile unit for the given descriptor. /// - CompileUnit &FindCompileUnit(DICompileUnit Unit) const; + CompileUnit &findCompileUnit(DICompileUnit Unit) const; - /// CreateDbgScopeVariable - Create a new scope variable. + /// createDbgScopeVariable - Create a new scope variable. /// - DIE *CreateDbgScopeVariable(DbgVariable *DV, CompileUnit *Unit); + DIE *createDbgScopeVariable(DbgVariable *DV, CompileUnit *Unit); /// getUpdatedDbgScope - Find or create DbgScope assicated with /// the instruction. Initialize scope and update scope hierarchy. @@ -370,88 +366,97 @@ DbgVariable *findAbstractVariable(DIVariable &Var, unsigned FrameIdx, DILocation &Loc); - DIE *UpdateSubprogramScopeDIE(MDNode *SPNode); - DIE *ConstructLexicalScopeDIE(DbgScope *Scope); - DIE *ConstructScopeDIE(DbgScope *Scope); - DIE *ConstructInlinedScopeDIE(DbgScope *Scope); - DIE *ConstructVariableDIE(DbgVariable *DV, DbgScope *S, CompileUnit *Unit); - - /// ConstructDbgScope - Construct the components of a scope. - /// - void ConstructDbgScope(DbgScope *ParentScope, - unsigned ParentStartID, unsigned ParentEndID, - DIE *ParentDie, CompileUnit *Unit); + /// updateSubprogramScopeDIE - Find DIE for the given subprogram and + /// attach appropriate DW_AT_low_pc and DW_AT_high_pc attributes. + /// If there are global variables in this scope then create and insert + /// DIEs for these variables. + DIE *updateSubprogramScopeDIE(MDNode *SPNode); + + /// constructLexicalScope - Construct new DW_TAG_lexical_block + /// for this scope and attach DW_AT_low_pc/DW_AT_high_pc labels. + DIE *constructLexicalScopeDIE(DbgScope *Scope); + + /// constructInlinedScopeDIE - This scope represents inlined body of + /// a function. Construct DIE to represent this concrete inlined copy + /// of the function. + DIE *constructInlinedScopeDIE(DbgScope *Scope); + + /// constructVariableDIE - Construct a DIE for the given DbgVariable. + DIE *constructVariableDIE(DbgVariable *DV, DbgScope *S, CompileUnit *Unit); - /// EmitInitial - Emit initial Dwarf declarations. This is necessary for cc + /// constructScopeDIE - Construct a DIE for this scope. + DIE *constructScopeDIE(DbgScope *Scope); + + /// emitInitial - Emit initial Dwarf declarations. This is necessary for cc /// tools to recognize the object file contains Dwarf information. - void EmitInitial(); + void emitInitial(); - /// EmitDIE - Recusively Emits a debug information entry. + /// emitDIE - Recusively Emits a debug information entry. /// - void EmitDIE(DIE *Die); + void emitDIE(DIE *Die); - /// SizeAndOffsetDie - Compute the size and offset of a DIE. + /// computeSizeAndOffset - Compute the size and offset of a DIE. /// - unsigned SizeAndOffsetDie(DIE *Die, unsigned Offset, bool Last); + unsigned computeSizeAndOffset(DIE *Die, unsigned Offset, bool Last); - /// SizeAndOffsets - Compute the size and offset of all the DIEs. + /// computeSizeAndOffsets - Compute the size and offset of all the DIEs. /// - void SizeAndOffsets(); + void computeSizeAndOffsets(); - /// EmitDebugInfo / EmitDebugInfoPerCU - Emit the debug info section. + /// EmitDebugInfo / emitDebugInfoPerCU - Emit the debug info section. /// - void EmitDebugInfoPerCU(CompileUnit *Unit); + void emitDebugInfoPerCU(CompileUnit *Unit); - void EmitDebugInfo(); + void emitDebugInfo(); - /// EmitAbbreviations - Emit the abbreviation section. + /// emitAbbreviations - Emit the abbreviation section. /// - void EmitAbbreviations() const; + void emitAbbreviations() const; - /// EmitEndOfLineMatrix - Emit the last address of the section and the end of + /// emitEndOfLineMatrix - Emit the last address of the section and the end of /// the line matrix. /// - void EmitEndOfLineMatrix(unsigned SectionEnd); + void emitEndOfLineMatrix(unsigned SectionEnd); - /// EmitDebugLines - Emit source line information. + /// emitDebugLines - Emit source line information. /// - void EmitDebugLines(); + void emitDebugLines(); - /// EmitCommonDebugFrame - Emit common frame info into a debug frame section. + /// emitCommonDebugFrame - Emit common frame info into a debug frame section. /// - void EmitCommonDebugFrame(); + void emitCommonDebugFrame(); - /// EmitFunctionDebugFrame - Emit per function frame info into a debug frame + /// emitFunctionDebugFrame - Emit per function frame info into a debug frame /// section. - void EmitFunctionDebugFrame(const FunctionDebugFrameInfo &DebugFrameInfo); + void emitFunctionDebugFrame(const FunctionDebugFrameInfo &DebugFrameInfo); - void EmitDebugPubNamesPerCU(CompileUnit *Unit); + void emitDebugPubNamesPerCU(CompileUnit *Unit); - /// EmitDebugPubNames - Emit visible names into a debug pubnames section. + /// emitDebugPubNames - Emit visible names into a debug pubnames section. /// - void EmitDebugPubNames(); + void emitDebugPubNames(); - /// EmitDebugStr - Emit visible names into a debug str section. + /// emitDebugStr - Emit visible names into a debug str section. /// - void EmitDebugStr(); + void emitDebugStr(); - /// EmitDebugLoc - Emit visible names into a debug loc section. + /// emitDebugLoc - Emit visible names into a debug loc section. /// - void EmitDebugLoc(); + void emitDebugLoc(); /// EmitDebugARanges - Emit visible names into a debug aranges section. /// void EmitDebugARanges(); - /// EmitDebugRanges - Emit visible names into a debug ranges section. + /// emitDebugRanges - Emit visible names into a debug ranges section. /// - void EmitDebugRanges(); + void emitDebugRanges(); - /// EmitDebugMacInfo - Emit visible names into a debug macinfo section. + /// emitDebugMacInfo - Emit visible names into a debug macinfo section. /// - void EmitDebugMacInfo(); + void emitDebugMacInfo(); - /// EmitDebugInlineInfo - Emit inline info using following format. + /// emitDebugInlineInfo - Emit inline info using following format. /// Section Header: /// 1. length of section /// 2. Dwarf version number @@ -469,7 +474,7 @@ /// inlined instance; the die_offset points to the inlined_subroutine die in /// the __debug_info section, and the low_pc is the starting address for the /// inlining instance. - void EmitDebugInlineInfo(); + void emitDebugInlineInfo(); /// GetOrCreateSourceID - Look up the source id with the given directory and /// source file names. If none currently exists, create a new id and insert it @@ -478,17 +483,17 @@ unsigned GetOrCreateSourceID(const char *DirName, const char *FileName); - void ConstructCompileUnit(MDNode *N); + void constructCompileUnit(MDNode *N); - void ConstructGlobalVariableDIE(MDNode *N); + void constructGlobalVariableDIE(MDNode *N); - void ConstructSubprogram(MDNode *N); + void constructSubprogramDIE(MDNode *N); // FIXME: This should go away in favor of complex addresses. /// Find the type the programmer originally declared the variable to be /// and return that type. Obsolete, use GetComplexAddrType instead. /// - DIType GetBlockByrefType(DIType Ty, std::string Name); + DIType getBlockByrefType(DIType Ty, std::string Name); public: //===--------------------------------------------------------------------===// @@ -501,30 +506,30 @@ /// be emitted. bool ShouldEmitDwarfDebug() const { return shouldEmit; } - /// BeginModule - Emit all Dwarf sections that should come prior to the + /// beginModule - Emit all Dwarf sections that should come prior to the /// content. - void BeginModule(Module *M, MachineModuleInfo *MMI); + void beginModule(Module *M, MachineModuleInfo *MMI); - /// EndModule - Emit all Dwarf sections that should come after the content. + /// endModule - Emit all Dwarf sections that should come after the content. /// - void EndModule(); + void endModule(); - /// BeginFunction - Gather pre-function debug information. Assumes being + /// beginFunction - Gather pre-function debug information. Assumes being /// emitted immediately after the function entry point. - void BeginFunction(MachineFunction *MF); + void beginFunction(MachineFunction *MF); - /// EndFunction - Gather and emit post-function debug information. + /// endFunction - Gather and emit post-function debug information. /// - void EndFunction(MachineFunction *MF); + void endFunction(MachineFunction *MF); - /// RecordSourceLine - Records location information and associates it with a + /// recordSourceLine - Records location information and associates it with a /// label. Returns a unique label ID used to generate a label and provide /// correspondence to the source line list. - unsigned RecordSourceLine(unsigned Line, unsigned Col, MDNode *Scope); + unsigned recordSourceLine(unsigned Line, unsigned Col, MDNode *Scope); - /// getRecordSourceLineCount - Return the number of source lines in the debug + /// getSourceLineCount - Return the number of source lines in the debug /// info. - unsigned getRecordSourceLineCount() const { + unsigned getSourceLineCount() const { return Lines.size(); } @@ -536,22 +541,18 @@ unsigned getOrCreateSourceID(const std::string &DirName, const std::string &FileName); - /// ExtractScopeInformation - Scan machine instructions in this function + /// extractScopeInformation - Scan machine instructions in this function /// and collect DbgScopes. Return true, if atleast one scope was found. - bool ExtractScopeInformation(MachineFunction *MF); - - /// CollectVariableInfo - Populate DbgScope entries with variables' info. - void CollectVariableInfo(); + bool extractScopeInformation(MachineFunction *MF); - /// SetDbgScopeEndLabels - Update DbgScope end labels for the scopes that - /// end with this machine instruction. - void SetDbgScopeEndLabels(const MachineInstr *MI, unsigned Label); + /// collectVariableInfo - Populate DbgScope entries with variables' info. + void collectVariableInfo(); - /// BeginScope - Process beginning of a scope starting at Label. - void BeginScope(const MachineInstr *MI, unsigned Label); + /// beginScope - Process beginning of a scope starting at Label. + void beginScope(const MachineInstr *MI, unsigned Label); - /// EndScope - Prcess end of a scope. - void EndScope(const MachineInstr *MI); + /// endScope - Prcess end of a scope. + void endScope(const MachineInstr *MI); }; } // End of namespace llvm Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=89537&r1=89536&r2=89537&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Fri Nov 20 20:48:08 2009 @@ -43,14 +43,14 @@ DE = new DwarfException(OS, A, T); DD = new DwarfDebug(OS, A, T); DE->BeginModule(M, MMI); - DD->BeginModule(M, MMI); + DD->beginModule(M, MMI); } /// EndModule - Emit all Dwarf sections that should come after the content. /// void DwarfWriter::EndModule() { DE->EndModule(); - DD->EndModule(); + DD->endModule(); delete DD; DD = 0; delete DE; DE = 0; } @@ -59,13 +59,13 @@ /// emitted immediately after the function entry point. void DwarfWriter::BeginFunction(MachineFunction *MF) { DE->BeginFunction(MF); - DD->BeginFunction(MF); + DD->beginFunction(MF); } /// EndFunction - Gather and emit post-function debug information. /// void DwarfWriter::EndFunction(MachineFunction *MF) { - DD->EndFunction(MF); + DD->endFunction(MF); DE->EndFunction(); if (MachineModuleInfo *MMI = DD->getMMI() ? DD->getMMI() : DE->getMMI()) @@ -78,12 +78,12 @@ /// correspondence to the source line list. unsigned DwarfWriter::RecordSourceLine(unsigned Line, unsigned Col, MDNode *Scope) { - return DD->RecordSourceLine(Line, Col, Scope); + return DD->recordSourceLine(Line, Col, Scope); } /// getRecordSourceLineCount - Count source lines. unsigned DwarfWriter::getRecordSourceLineCount() { - return DD->getRecordSourceLineCount(); + return DD->getSourceLineCount(); } /// ShouldEmitDwarfDebug - Returns true if Dwarf debugging declarations should @@ -93,8 +93,8 @@ } void DwarfWriter::BeginScope(const MachineInstr *MI, unsigned L) { - DD->BeginScope(MI, L); + DD->beginScope(MI, L); } void DwarfWriter::EndScope(const MachineInstr *MI) { - DD->EndScope(MI); + DD->endScope(MI); } From evan.cheng at apple.com Fri Nov 20 21:00:19 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 20 Nov 2009 19:00:19 -0800 Subject: [llvm-commits] [llvm] r89530 - in /llvm/trunk: include/llvm/CodeGen/LiveVariables.h lib/CodeGen/LiveVariables.cpp lib/CodeGen/PHIElimination.cpp lib/CodeGen/PHIElimination.h In-Reply-To: <200911210205.nAL25M36031984@zion.cs.uiuc.edu> References: <200911210205.nAL25M36031984@zion.cs.uiuc.edu> Message-ID: <8A286274-6E3F-43FB-B7E0-DC5A3AD36CD4@apple.com> Does this fix the cfrac failure? Evan On Nov 20, 2009, at 6:05 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Fri Nov 20 20:05:21 2009 > New Revision: 89530 > > URL: http://llvm.org/viewvc/llvm-project?rev=89530&view=rev > Log: > Be more clever about calculating live variables through new basic blocks. > > When splitting a critical edge, the registers live through the edge are: > > - Used in a PHI instruction, or > - Live out from the predecessor, and > - Live in to the successor. > > This allows the coalescer to eliminate even more phi joins. > > Modified: > llvm/trunk/include/llvm/CodeGen/LiveVariables.h > llvm/trunk/lib/CodeGen/LiveVariables.cpp > llvm/trunk/lib/CodeGen/PHIElimination.cpp > llvm/trunk/lib/CodeGen/PHIElimination.h > > Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveVariables.h?rev=89530&r1=89529&r2=89530&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/CodeGen/LiveVariables.h (original) > +++ llvm/trunk/include/llvm/CodeGen/LiveVariables.h Fri Nov 20 20:05:21 2009 > @@ -107,6 +107,13 @@ > /// findKill - Find a kill instruction in MBB. Return NULL if none is found. > MachineInstr *findKill(const MachineBasicBlock *MBB) const; > > + /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through > + /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in > + /// MBB, it is not considered live in. > + bool isLiveIn(const MachineBasicBlock &MBB, > + unsigned Reg, > + MachineRegisterInfo &MRI); > + > void dump() const; > }; > > @@ -267,11 +274,17 @@ > void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, > MachineInstr *MI); > > - /// addNewBlock - Add a new basic block BB as an empty succcessor to > - /// DomBB. All variables that are live out of DomBB will be marked as passing > - /// live through BB. This method assumes that the machine code is still in SSA > - /// form. > - void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB); > + bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) { > + return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI); > + } > + > + /// addNewBlock - Add a new basic block BB between DomBB and SuccBB. All > + /// variables that are live out of DomBB and live into SuccBB will be marked > + /// as passing live through BB. This method assumes that the machine code is > + /// still in SSA form. > + void addNewBlock(MachineBasicBlock *BB, > + MachineBasicBlock *DomBB, > + MachineBasicBlock *SuccBB); > }; > > } // End llvm namespace > > Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=89530&r1=89529&r2=89530&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original) > +++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Fri Nov 20 20:05:21 2009 > @@ -656,35 +656,45 @@ > .push_back(BBI->getOperand(i).getReg()); > } > > +bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB, > + unsigned Reg, > + MachineRegisterInfo &MRI) { > + unsigned Num = MBB.getNumber(); > + > + // Reg is live-through. > + if (AliveBlocks.test(Num)) > + return true; > + > + // Registers defined in MBB cannot be live in. > + const MachineInstr *Def = MRI.getVRegDef(Reg); > + if (Def && Def->getParent() == &MBB) > + return false; > + > + // Reg was not defined in MBB, was it killed here? > + return findKill(&MBB); > +} > + > /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All > /// variables that are live out of DomBB will be marked as passing live through > /// BB. > void LiveVariables::addNewBlock(MachineBasicBlock *BB, > - MachineBasicBlock *DomBB) { > + MachineBasicBlock *DomBB, > + MachineBasicBlock *SuccBB) { > const unsigned NumNew = BB->getNumber(); > - const unsigned NumDom = DomBB->getNumber(); > + > + // All registers used by PHI nodes in SuccBB must be live through BB. > + for (MachineBasicBlock::const_iterator BBI = SuccBB->begin(), > + BBE = SuccBB->end(); > + BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) > + for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) > + if (BBI->getOperand(i+1).getMBB() == BB) > + getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew); > > // Update info for all live variables > for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister, > E = MRI->getLastVirtReg()+1; Reg != E; ++Reg) { > VarInfo &VI = getVarInfo(Reg); > - > - // Anything live through DomBB is also live through BB. > - if (VI.AliveBlocks.test(NumDom)) { > + if (!VI.AliveBlocks.test(NumNew) && VI.isLiveIn(*SuccBB, Reg, *MRI)) > VI.AliveBlocks.set(NumNew); > - continue; > - } > - > - // Variables not defined in DomBB cannot be live out. > - const MachineInstr *Def = MRI->getVRegDef(Reg); > - if (!Def || Def->getParent() != DomBB) > - continue; > - > - // Killed by DomBB? > - if (VI.findKill(DomBB)) > - continue; > - > - // This register is defined in DomBB and live out > - VI.AliveBlocks.set(NumNew); > } > } > > Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89530&r1=89529&r2=89530&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) > +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Fri Nov 20 20:05:21 2009 > @@ -353,7 +353,7 @@ > // We break edges when registers are live out from the predecessor block > // (not considering PHI nodes). If the register is live in to this block > // anyway, we would gain nothing from splitting. > - if (isLiveOut(Reg, *PreMBB, LV) && !isLiveIn(Reg, MBB, LV)) > + if (!LV.isLiveIn(Reg, MBB) && isLiveOut(Reg, *PreMBB, LV)) > SplitCriticalEdge(PreMBB, &MBB); > } > } > @@ -406,22 +406,6 @@ > return false; > } > > -bool llvm::PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock &MBB, > - LiveVariables &LV) { > - LiveVariables::VarInfo &VI = LV.getVarInfo(Reg); > - > - if (VI.AliveBlocks.test(MBB.getNumber())) > - return true; > - > - // defined in MBB? > - const MachineInstr *Def = MRI->getVRegDef(Reg); > - if (Def && Def->getParent() == &MBB) > - return false; > - > - // killed in MBB? > - return VI.findKill(&MBB); > -} > - > MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A, > MachineBasicBlock *B) { > assert(A && B && "Missing MBB end point"); > @@ -463,7 +447,7 @@ > i->getOperand(ni+1).setMBB(NMBB); > > if (LiveVariables *LV=getAnalysisIfAvailable()) > - LV->addNewBlock(NMBB, A); > + LV->addNewBlock(NMBB, A, B); > > if (MachineDominatorTree *MDT=getAnalysisIfAvailable()) > MDT->addNewBlock(NMBB, A); > > Modified: llvm/trunk/lib/CodeGen/PHIElimination.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.h?rev=89530&r1=89529&r2=89530&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/PHIElimination.h (original) > +++ llvm/trunk/lib/CodeGen/PHIElimination.h Fri Nov 20 20:05:21 2009 > @@ -99,12 +99,6 @@ > bool isLiveOut(unsigned Reg, const MachineBasicBlock &MBB, > LiveVariables &LV); > > - /// isLiveIn - Determine if Reg is live in to MBB, not considering PHI > - /// source registers. This means that Reg is either killed by MBB or passes > - /// through it. > - bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB, > - LiveVariables &LV); > - > /// SplitCriticalEdge - Split a critical edge from A to B by > /// inserting a new MBB. Update branches in A and PHI instructions > /// in B. Return the new block. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stoklund at 2pi.dk Fri Nov 20 21:02:47 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 20 Nov 2009 19:02:47 -0800 Subject: [llvm-commits] [llvm] r89530 - in /llvm/trunk: include/llvm/CodeGen/LiveVariables.h lib/CodeGen/LiveVariables.cpp lib/CodeGen/PHIElimination.cpp lib/CodeGen/PHIElimination.h In-Reply-To: <8A286274-6E3F-43FB-B7E0-DC5A3AD36CD4@apple.com> References: <200911210205.nAL25M36031984@zion.cs.uiuc.edu> <8A286274-6E3F-43FB-B7E0-DC5A3AD36CD4@apple.com> Message-ID: <63D8E2FE-2C69-4D3E-AE54-A9520A3D4A73@2pi.dk> On Nov 20, 2009, at 7:00 PM, Evan Cheng wrote: > Does this fix the cfrac failure? No, I am still looking into that. From evan.cheng at apple.com Fri Nov 20 22:17:08 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 20 Nov 2009 20:17:08 -0800 Subject: [llvm-commits] [llvm] r89530 - in /llvm/trunk: include/llvm/CodeGen/LiveVariables.h lib/CodeGen/LiveVariables.cpp lib/CodeGen/PHIElimination.cpp lib/CodeGen/PHIElimination.h In-Reply-To: <63D8E2FE-2C69-4D3E-AE54-A9520A3D4A73@2pi.dk> References: <200911210205.nAL25M36031984@zion.cs.uiuc.edu> <8A286274-6E3F-43FB-B7E0-DC5A3AD36CD4@apple.com> <63D8E2FE-2C69-4D3E-AE54-A9520A3D4A73@2pi.dk> Message-ID: <71D3D953-F3C5-46CA-B46A-04D227CCAB70@apple.com> Ok, thanks. Evan On Nov 20, 2009, at 7:02 PM, Jakob Stoklund Olesen wrote: > > On Nov 20, 2009, at 7:00 PM, Evan Cheng wrote: > >> Does this fix the cfrac failure? > > No, I am still looking into that. > > From evan.cheng at apple.com Sat Nov 21 00:20:27 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 21 Nov 2009 06:20:27 -0000 Subject: [llvm-commits] [llvm] r89541 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/IfConversion.cpp Message-ID: <200911210620.nAL6KRUp007236@zion.cs.uiuc.edu> Author: evancheng Date: Sat Nov 21 00:20:26 2009 New Revision: 89541 URL: http://llvm.org/viewvc/llvm-project?rev=89541&view=rev Log: Allow target to disable if-converting predicable instructions. e.g. NEON instructions under ARM mode. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/CodeGen/IfConversion.cpp Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=89541&r1=89540&r2=89541&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sat Nov 21 00:20:26 2009 @@ -514,6 +514,13 @@ return false; } + /// isPredicable - Return true if the specified instruction can be predicated. + /// By default, this returns true for every instruction with a + /// PredicateOperand. + virtual bool isPredicable(MachineInstr *MI) const { + return MI->getDesc().isPredicable(); + } + /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine /// instruction that defines the specified register class. virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=89541&r1=89540&r2=89541&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Sat Nov 21 00:20:26 2009 @@ -608,7 +608,7 @@ if (TII->DefinesPredicate(I, PredDefs)) BBI.ClobbersPred = true; - if (!TID.isPredicable()) { + if (!TII->isPredicable(I)) { BBI.IsUnpredicable = true; return; } From evan.cheng at apple.com Sat Nov 21 00:21:52 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 21 Nov 2009 06:21:52 -0000 Subject: [llvm-commits] [llvm] r89542 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMBaseInstrInfo.h ARMISelDAGToDAG.cpp ARMInstrFormats.td ARMInstrNEON.td NEONMoveFix.cpp Message-ID: <200911210621.nAL6LqMA007301@zion.cs.uiuc.edu> Author: evancheng Date: Sat Nov 21 00:21:52 2009 New Revision: 89542 URL: http://llvm.org/viewvc/llvm-project?rev=89542&view=rev Log: Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=89542&r1=89541&r2=89542&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Nov 21 00:21:52 2009 @@ -39,6 +39,10 @@ EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv")); +static cl::opt +PredicateNEON("predicate-neon", cl::Hidden, + cl::desc("Allow NEON instructions to be predicated")); + ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), Subtarget(STI) { @@ -402,6 +406,21 @@ return Found; } +/// isPredicable - Return true if the specified instruction can be predicated. +/// By default, this returns true for every instruction with a +/// PredicateOperand. +bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { + const TargetInstrDesc &TID = MI->getDesc(); + if (!TID.isPredicable()) + return false; + + if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { + ARMFunctionInfo *AFI = + MI->getParent()->getParent()->getInfo(); + return PredicateNEON && AFI->isThumb2Function(); + } + return true; +} /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing static unsigned getNumJTEntries(const std::vector &JT, @@ -647,11 +666,13 @@ SrcRC == ARM::DPR_VFP2RegisterClass || SrcRC == ARM::DPR_8RegisterClass) { // Always use neon reg-reg move if source or dest is NEON-only regclass. - BuildMI(MBB, I, DL, get(ARM::VMOVDneon), DestReg).addReg(SrcReg); + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVDneon), + DestReg).addReg(SrcReg)); } else if (DestRC == ARM::QPRRegisterClass || DestRC == ARM::QPR_VFP2RegisterClass || DestRC == ARM::QPR_8RegisterClass) { - BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg); + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVQ), + DestReg).addReg(SrcReg)); } else { return false; } @@ -695,13 +716,14 @@ // FIXME: Neon instructions should support predicates if (Align >= 16 && (getRegisterInfo().needsStackRealignment(MF))) { - BuildMI(MBB, I, DL, get(ARM::VST1q64)) - .addFrameIndex(FI).addImm(0).addImm(0).addImm(128).addMemOperand(MMO) - .addReg(SrcReg, getKillRegState(isKill)); + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) + .addFrameIndex(FI).addImm(0).addImm(0).addImm(128) + .addMemOperand(MMO) + .addReg(SrcReg, getKillRegState(isKill))); } else { - BuildMI(MBB, I, DL, get(ARM::VSTRQ)). - addReg(SrcReg, getKillRegState(isKill)) - .addFrameIndex(FI).addImm(0).addMemOperand(MMO); + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRQ)). + addReg(SrcReg, getKillRegState(isKill)) + .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); } } } @@ -740,11 +762,12 @@ // FIXME: Neon instructions should support predicates if (Align >= 16 && (getRegisterInfo().needsStackRealignment(MF))) { - BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) - .addFrameIndex(FI).addImm(0).addImm(0).addImm(128).addMemOperand(MMO); + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) + .addFrameIndex(FI).addImm(0).addImm(0).addImm(128) + .addMemOperand(MMO)); } else { - BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0). - addMemOperand(MMO); + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg) + .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); } } } Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=89542&r1=89541&r2=89542&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Sat Nov 21 00:21:52 2009 @@ -220,6 +220,8 @@ virtual bool DefinesPredicate(MachineInstr *MI, std::vector &Pred) const; + virtual bool isPredicable(MachineInstr *MI) const; + /// GetInstSize - Returns the size of the specified MachineInstr. /// virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const; Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=89542&r1=89541&r2=89542&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Sat Nov 21 00:21:52 2009 @@ -1049,12 +1049,15 @@ case MVT::v4i32: OpcodeIndex = 2; break; } + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); + SDValue PredReg = CurDAG->getRegister(0, MVT::i32); if (is64BitVector) { unsigned Opc = DOpcodes[OpcodeIndex]; - const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, Chain }; + const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, + Pred, PredReg, Chain }; std::vector ResTys(NumVecs, VT); ResTys.push_back(MVT::Other); - return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5); + return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 7); } EVT RegVT = GetNEONSubregVT(VT); @@ -1062,10 +1065,11 @@ // Quad registers are directly supported for VLD2, // loading 2 pairs of D regs. unsigned Opc = QOpcodes0[OpcodeIndex]; - const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, Chain }; + const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, + Pred, PredReg, Chain }; std::vector ResTys(4, VT); ResTys.push_back(MVT::Other); - SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5); + SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 7); Chain = SDValue(VLd, 4); // Combine the even and odd subregs to produce the result. @@ -1086,15 +1090,16 @@ // Load the even subregs. unsigned Opc = QOpcodes0[OpcodeIndex]; - const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Align, Chain }; - SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 5); + const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Align, + Pred, PredReg, Chain }; + SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 7); Chain = SDValue(VLdA, NumVecs+1); // Load the odd subregs. Opc = QOpcodes1[OpcodeIndex]; const SDValue OpsB[] = { SDValue(VLdA, NumVecs), MemUpdate, MemOpc, - Align, Chain }; - SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 5); + Align, Pred, PredReg, Chain }; + SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 7); Chain = SDValue(VLdB, NumVecs+1); // Combine the even and odd subregs to produce the result. @@ -1138,6 +1143,9 @@ case MVT::v4i32: OpcodeIndex = 2; break; } + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); + SDValue PredReg = CurDAG->getRegister(0, MVT::i32); + SmallVector Ops; Ops.push_back(MemAddr); Ops.push_back(MemUpdate); @@ -1148,8 +1156,10 @@ unsigned Opc = DOpcodes[OpcodeIndex]; for (unsigned Vec = 0; Vec < NumVecs; ++Vec) Ops.push_back(N->getOperand(Vec+3)); + Ops.push_back(Pred); + Ops.push_back(PredReg); Ops.push_back(Chain); - return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5); + return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+7); } EVT RegVT = GetNEONSubregVT(VT); @@ -1163,8 +1173,10 @@ Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT, N->getOperand(Vec+3))); } + Ops.push_back(Pred); + Ops.push_back(PredReg); Ops.push_back(Chain); - return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 9); + return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 11); } // Otherwise, quad registers are stored with two separate instructions, @@ -1177,10 +1189,12 @@ for (unsigned Vec = 0; Vec < NumVecs; ++Vec) Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT, N->getOperand(Vec+3))); + Ops.push_back(Pred); + Ops.push_back(PredReg); Ops.push_back(Chain); unsigned Opc = QOpcodes0[OpcodeIndex]; SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), - MVT::Other, Ops.data(), NumVecs+5); + MVT::Other, Ops.data(), NumVecs+7); Chain = SDValue(VStA, 1); // Store the odd subregs. @@ -1188,10 +1202,12 @@ for (unsigned Vec = 0; Vec < NumVecs; ++Vec) Ops[Vec+4] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT, N->getOperand(Vec+3)); - Ops[NumVecs+4] = Chain; + Ops[NumVecs+4] = Pred; + Ops[NumVecs+5] = PredReg; + Ops[NumVecs+6] = Chain; Opc = QOpcodes1[OpcodeIndex]; SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), - MVT::Other, Ops.data(), NumVecs+5); + MVT::Other, Ops.data(), NumVecs+7); Chain = SDValue(VStB, 1); ReplaceUses(SDValue(N, 0), Chain); return NULL; @@ -1239,6 +1255,9 @@ case MVT::v4i32: OpcodeIndex = 1; break; } + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); + SDValue PredReg = CurDAG->getRegister(0, MVT::i32); + SmallVector Ops; Ops.push_back(MemAddr); Ops.push_back(MemUpdate); @@ -1264,15 +1283,17 @@ N->getOperand(Vec+3))); } Ops.push_back(getI32Imm(Lane)); + Ops.push_back(Pred); + Ops.push_back(PredReg); Ops.push_back(Chain); if (!IsLoad) - return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5); + return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+7); std::vector ResTys(NumVecs, RegVT); ResTys.push_back(MVT::Other); SDNode *VLdLn = - CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+5); + CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+7); // For a 64-bit vector load to D registers, nothing more needs to be done. if (is64BitVector) return VLdLn; @@ -1297,7 +1318,7 @@ return NULL; unsigned Shl_imm = 0; - if (isOpcWithIntImmediate(Op.getOperand(0).getNode(), ISD::SHL, Shl_imm)){ + if (isOpcWithIntImmediate(Op.getOperand(0).getNode(), ISD::SHL, Shl_imm)) { assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!"); unsigned Srl_imm = 0; if (isInt32Immediate(Op.getOperand(1), Srl_imm)) { @@ -1519,7 +1540,7 @@ SDNode *ResNode; if (Subtarget->isThumb1Only()) { - SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32); + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other, @@ -1775,8 +1796,10 @@ case MVT::v4f32: case MVT::v4i32: Opc = ARM::VZIPq32; break; } - return CurDAG->getMachineNode(Opc, dl, VT, VT, - N->getOperand(0), N->getOperand(1)); + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); + SDValue PredReg = CurDAG->getRegister(0, MVT::i32); + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; + return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); } case ARMISD::VUZP: { unsigned Opc = 0; @@ -1792,8 +1815,10 @@ case MVT::v4f32: case MVT::v4i32: Opc = ARM::VUZPq32; break; } - return CurDAG->getMachineNode(Opc, dl, VT, VT, - N->getOperand(0), N->getOperand(1)); + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); + SDValue PredReg = CurDAG->getRegister(0, MVT::i32); + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; + return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); } case ARMISD::VTRN: { unsigned Opc = 0; @@ -1809,8 +1834,10 @@ case MVT::v4f32: case MVT::v4i32: Opc = ARM::VTRNq32; break; } - return CurDAG->getMachineNode(Opc, dl, VT, VT, - N->getOperand(0), N->getOperand(1)); + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); + SDValue PredReg = CurDAG->getRegister(0, MVT::i32); + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; + return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); } case ISD::INTRINSIC_VOID: Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=89542&r1=89541&r2=89542&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Sat Nov 21 00:21:52 2009 @@ -1217,27 +1217,30 @@ // class NeonI pattern> + string opc, string asm, string cstr, list pattern> : InstARM { let OutOperandList = oops; - let InOperandList = iops; - let AsmString = asm; + let InOperandList = !con(iops, (ops pred:$p)); + let AsmString = !strconcat(opc, !strconcat("${p}", asm)); let Pattern = pattern; list Predicates = [HasNEON]; } -class NI pattern> - : NeonI { +class NI pattern> + : NeonI { } -class NI4 pattern> - : NeonI { +class NI4 pattern> + : NeonI { } class NLdSt op21_20, bits<4> op11_8, bits<4> op7_4, dag oops, dag iops, InstrItinClass itin, - string asm, string cstr, list pattern> - : NeonI { + string opc, string asm, string cstr, list pattern> + : NeonI { let Inst{31-24} = 0b11110100; let Inst{23} = op23; let Inst{21-20} = op21_20; @@ -1248,8 +1251,8 @@ // With selective bit(s) from op7_4 specified by subclasses. class NLdStLN op21_20, bits<4> op11_8, dag oops, dag iops, InstrItinClass itin, - string asm, string cstr, list pattern> - : NeonI { + string opc, string asm, string cstr, list pattern> + : NeonI { let Inst{31-24} = 0b11110100; let Inst{23} = op23; let Inst{21-20} = op21_20; @@ -1257,8 +1260,9 @@ } class NDataI pattern> - : NeonI { + string opc, string asm, string cstr, list pattern> + : NeonI { let Inst{31-25} = 0b1111001; } @@ -1266,8 +1270,8 @@ class N1ModImm op21_19, bits<4> op11_8, bit op7, bit op6, bit op5, bit op4, dag oops, dag iops, InstrItinClass itin, - string asm, string cstr, list pattern> - : NDataI { + string opc, string asm, string cstr, list pattern> + : NDataI { let Inst{23} = op23; let Inst{21-19} = op21_19; let Inst{11-8} = op11_8; @@ -1281,8 +1285,8 @@ class N2V op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, - string asm, string cstr, list pattern> - : NDataI { + string opc, string asm, string cstr, list pattern> + : NDataI { let Inst{24-23} = op24_23; let Inst{21-20} = op21_20; let Inst{19-18} = op19_18; @@ -1296,8 +1300,8 @@ // Inst{19-16} is specified by subclasses. class N2VDup op24_23, bits<2> op21_20, bits<5> op11_7, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, - string asm, string cstr, list pattern> - : NDataI { + string opc, string asm, string cstr, list pattern> + : NDataI { let Inst{24-23} = op24_23; let Inst{21-20} = op21_20; let Inst{11-7} = op11_7; @@ -1308,8 +1312,8 @@ // NEON 2 vector register with immediate. class N2VImm op11_8, bit op7, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, - string asm, string cstr, list pattern> - : NDataI { + string opc, string asm, string cstr, list pattern> + : NDataI { let Inst{24} = op24; let Inst{23} = op23; let Inst{11-8} = op11_8; @@ -1321,8 +1325,8 @@ // NEON 3 vector register format. class N3V op21_20, bits<4> op11_8, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, - string asm, string cstr, list pattern> - : NDataI { + string opc, string asm, string cstr, list pattern> + : NDataI { let Inst{24} = op24; let Inst{23} = op23; let Inst{21-20} = op21_20; @@ -1336,8 +1340,8 @@ // concatenation of the operands and is left unspecified. class N3VImm op21_20, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, - string asm, string cstr, list pattern> - : NDataI { + string opc, string asm, string cstr, list pattern> + : NDataI { let Inst{24} = op24; let Inst{23} = op23; let Inst{21-20} = op21_20; Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=89542&r1=89541&r2=89542&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Sat Nov 21 00:21:52 2009 @@ -124,7 +124,7 @@ def VLDMD : NI<(outs), (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), IIC_fpLoadm, - "vldm${addr:submode} ${addr:base}, $dst1", + "vldm", "${addr:submode} ${addr:base}, $dst1", []> { let Inst{27-25} = 0b110; let Inst{20} = 1; @@ -134,7 +134,7 @@ def VLDMS : NI<(outs), (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), IIC_fpLoadm, - "vldm${addr:submode} ${addr:base}, $dst1", + "vldm", "${addr:submode} ${addr:base}, $dst1", []> { let Inst{27-25} = 0b110; let Inst{20} = 1; @@ -146,7 +146,7 @@ // Use vldmia to load a Q register as a D register pair. def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoadm, - "vldmia\t$addr, ${dst:dregpair}", + "vldmia", "\t$addr, ${dst:dregpair}", [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> { let Inst{27-25} = 0b110; let Inst{24} = 0; // P bit @@ -158,7 +158,7 @@ // Use vstmia to store a Q register as a D register pair. def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem, - "vstmia\t$addr, ${src:dregpair}", + "vstmia", "\t$addr, ${src:dregpair}", [(store (v2f64 QPR:$src), addrmode4:$addr)]> { let Inst{27-25} = 0b110; let Inst{24} = 0; // P bit @@ -170,11 +170,11 @@ // VLD1 : Vector Load (multiple single elements) class VLD1D op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp> : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1, - !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), "", + OpcodeStr, "\t\\{$dst\\}, $addr", "", [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>; class VLD1Q op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp> : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1, - !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), "", + OpcodeStr, "\t${dst:dregpair}, $addr", "", [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>; def VLD1d8 : VLD1D<0b0000, "vld1.8", v8i8, int_arm_neon_vld1>; @@ -195,12 +195,12 @@ class VLD2D op7_4, string OpcodeStr> : NLdSt<0,0b10,0b1000,op7_4, (outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr), IIC_VLD2, - !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), "", []>; + OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr", "", []>; class VLD2Q op7_4, string OpcodeStr> : NLdSt<0,0b10,0b0011,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), (ins addrmode6:$addr), IIC_VLD2, - !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), + OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "", []>; def VLD2d8 : VLD2D<0b0000, "vld2.8">; @@ -208,7 +208,7 @@ def VLD2d32 : VLD2D<0b1000, "vld2.32">; def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr), IIC_VLD1, - "vld1.64\t\\{$dst1,$dst2\\}, $addr", "", []>; + "vld1.64", "\t\\{$dst1,$dst2\\}, $addr", "", []>; def VLD2q8 : VLD2Q<0b0000, "vld2.8">; def VLD2q16 : VLD2Q<0b0100, "vld2.16">; @@ -218,11 +218,11 @@ class VLD3D op7_4, string OpcodeStr> : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr), IIC_VLD3, - !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>; + OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr", "", []>; class VLD3WB op7_4, string OpcodeStr> : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb), (ins addrmode6:$addr), IIC_VLD3, - !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), + OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr", "$addr.addr = $wb", []>; def VLD3d8 : VLD3D<0b0000, "vld3.8">; @@ -231,7 +231,7 @@ def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr), IIC_VLD1, - "vld1.64\t\\{$dst1,$dst2,$dst3\\}, $addr", "", []>; + "vld1.64", "\t\\{$dst1,$dst2,$dst3\\}, $addr", "", []>; // vld3 to double-spaced even registers. def VLD3q8a : VLD3WB<0b0000, "vld3.8">; @@ -248,13 +248,13 @@ : NLdSt<0,0b10,0b0000,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), (ins addrmode6:$addr), IIC_VLD4, - !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), + OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "", []>; class VLD4WB op7_4, string OpcodeStr> : NLdSt<0,0b10,0b0001,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), (ins addrmode6:$addr), IIC_VLD4, - !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), + OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "$addr.addr = $wb", []>; def VLD4d8 : VLD4D<0b0000, "vld4.8">; @@ -263,7 +263,7 @@ def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), (ins addrmode6:$addr), IIC_VLD1, - "vld1.64\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "", []>; + "vld1.64", "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "", []>; // vld4 to double-spaced even registers. def VLD4q8a : VLD4WB<0b0000, "vld4.8">; @@ -283,7 +283,7 @@ : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, - !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"), + OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr", "$src1 = $dst1, $src2 = $dst2", []>; // vld2 to single-spaced registers. @@ -316,8 +316,8 @@ : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VLD3, - !strconcat(OpcodeStr, - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"), + OpcodeStr, + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr", "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>; // vld3 to single-spaced registers. @@ -353,8 +353,8 @@ (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VLD4, - !strconcat(OpcodeStr, - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"), + OpcodeStr, + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr", "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>; // vld4 to single-spaced registers. @@ -392,11 +392,11 @@ // VST1 : Vector Store (multiple single elements) class VST1D op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp> : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST, - !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), "", + OpcodeStr, "\t\\{$src\\}, $addr", "", [(IntOp addrmode6:$addr, (Ty DPR:$src))]>; class VST1Q op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp> : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST, - !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "", + OpcodeStr, "\t${src:dregpair}, $addr", "", [(IntOp addrmode6:$addr, (Ty QPR:$src))]>; let hasExtraSrcRegAllocReq = 1 in { @@ -419,12 +419,12 @@ class VST2D op7_4, string OpcodeStr> : NLdSt<0,0b00,0b1000,op7_4, (outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST, - !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>; + OpcodeStr, "\t\\{$src1,$src2\\}, $addr", "", []>; class VST2Q op7_4, string OpcodeStr> : NLdSt<0,0b00,0b0011,op7_4, (outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST, - !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), + OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr", "", []>; def VST2d8 : VST2D<0b0000, "vst2.8">; @@ -432,7 +432,7 @@ def VST2d32 : VST2D<0b1000, "vst2.32">; def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST, - "vst1.64\t\\{$src1,$src2\\}, $addr", "", []>; + "vst1.64", "\t\\{$src1,$src2\\}, $addr", "", []>; def VST2q8 : VST2Q<0b0000, "vst2.8">; def VST2q16 : VST2Q<0b0100, "vst2.16">; @@ -442,11 +442,11 @@ class VST3D op7_4, string OpcodeStr> : NLdSt<0,0b00,0b0100,op7_4, (outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST, - !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>; + OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr", "", []>; class VST3WB op7_4, string OpcodeStr> : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST, - !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), + OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr", "$addr.addr = $wb", []>; def VST3d8 : VST3D<0b0000, "vst3.8">; @@ -455,7 +455,7 @@ def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST, - "vst1.64\t\\{$src1,$src2,$src3\\}, $addr", "", []>; + "vst1.64", "\t\\{$src1,$src2,$src3\\}, $addr", "", []>; // vst3 to double-spaced even registers. def VST3q8a : VST3WB<0b0000, "vst3.8">; @@ -472,13 +472,13 @@ : NLdSt<0,0b00,0b0000,op7_4, (outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST, - !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), + OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr", "", []>; class VST4WB op7_4, string OpcodeStr> : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST, - !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), + OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr", "$addr.addr = $wb", []>; def VST4d8 : VST4D<0b0000, "vst4.8">; @@ -487,7 +487,7 @@ def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST, - "vst1.64\t\\{$src1,$src2,$src3,$src4\\}, $addr", "", []>; + "vst1.64", "\t\\{$src1,$src2,$src3,$src4\\}, $addr", "", []>; // vst4 to double-spaced even registers. def VST4q8a : VST4WB<0b0000, "vst4.8">; @@ -507,7 +507,7 @@ : NLdStLN<1,0b00,op11_8, (outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST, - !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"), + OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr", "", []>; // vst2 to single-spaced registers. @@ -540,8 +540,8 @@ : NLdStLN<1,0b00,op11_8, (outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VST, - !strconcat(OpcodeStr, - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>; + OpcodeStr, + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr", "", []>; // vst3 to single-spaced registers. def VST3LNd8 : VST3LN<0b0010, "vst3.8"> { @@ -575,8 +575,8 @@ : NLdStLN<1,0b00,op11_8, (outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VST, - !strconcat(OpcodeStr, - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"), + OpcodeStr, + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr", "", []>; // vst4 to single-spaced registers. @@ -655,13 +655,13 @@ bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode OpNode> : N2V; class N2VQ op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode OpNode> : N2V; // Basic 2-register operations, scalar single-precision. @@ -670,7 +670,7 @@ ValueType ResTy, ValueType OpTy, SDNode OpNode> : N2V; + IIC_VUNAD, OpcodeStr, "\t$dst, $src", "", []>; class N2VDsPat : NEONFPPat<(ResTy (OpNode SPR:$a)), @@ -684,14 +684,14 @@ InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N2V; class N2VQInt op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N2V; // Basic 2-register intrinsics, scalar single-precision @@ -701,7 +701,7 @@ ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N2V; + OpcodeStr, "\t$dst, $src", "", []>; class N2VDIntsPat : NEONFPPat<(f32 (OpNode SPR:$a)), @@ -715,7 +715,7 @@ InstrItinClass itin, string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp> : N2V; // Long 2-register intrinsics (currently only used for VMOVL). @@ -724,20 +724,20 @@ InstrItinClass itin, string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp> : N2V; // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register. class N2VDShuffle op19_18, bits<5> op11_7, string OpcodeStr> : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2), (ins DPR:$src1, DPR:$src2), IIC_VPERMD, - !strconcat(OpcodeStr, "\t$dst1, $dst2"), + OpcodeStr, "\t$dst1, $dst2", "$src1 = $dst1, $src2 = $dst2", []>; class N2VQShuffle op19_18, bits<5> op11_7, InstrItinClass itin, string OpcodeStr> : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2), (ins QPR:$src1, QPR:$src2), itin, - !strconcat(OpcodeStr, "\t$dst1, $dst2"), + OpcodeStr, "\t$dst1, $dst2", "$src1 = $dst1, $src2 = $dst2", []>; // Basic 3-register operations, both double- and quad-register. @@ -746,7 +746,7 @@ SDNode OpNode, bit Commutable> : N3V { let isCommutable = Commutable; } @@ -754,7 +754,7 @@ InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode ShOp> : N3V<0, 1, op21_20, op11_8, 1, 0, (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", [(set (Ty DPR:$dst), (Ty (ShOp (Ty DPR:$src1), (Ty (NEONvduplane (Ty DPR_VFP2:$src2), @@ -766,7 +766,7 @@ : N3V<0, 1, op21_20, op11_8, 1, 0, (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane), IIC_VMULi16D, - !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", + OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", [(set (Ty DPR:$dst), (Ty (ShOp (Ty DPR:$src1), (Ty (NEONvduplane (Ty DPR_8:$src2), @@ -779,7 +779,7 @@ SDNode OpNode, bit Commutable> : N3V { let isCommutable = Commutable; } @@ -788,7 +788,7 @@ ValueType ResTy, ValueType OpTy, SDNode ShOp> : N3V<1, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", [(set (ResTy QPR:$dst), (ResTy (ShOp (ResTy QPR:$src1), (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2), @@ -800,7 +800,7 @@ : N3V<1, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane), IIC_VMULi16Q, - !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", + OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", [(set (ResTy QPR:$dst), (ResTy (ShOp (ResTy QPR:$src1), (ResTy (NEONvduplane (OpTy DPR_8:$src2), @@ -814,7 +814,7 @@ SDNode OpNode, bit Commutable> : N3V { + OpcodeStr, "\t$dst, $src1, $src2", "", []> { let isCommutable = Commutable; } class N3VDsPat @@ -830,7 +830,7 @@ Intrinsic IntOp, bit Commutable> : N3V { let isCommutable = Commutable; } @@ -838,7 +838,7 @@ string OpcodeStr, ValueType Ty, Intrinsic IntOp> : N3V<0, 1, op21_20, op11_8, 1, 0, (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", [(set (Ty DPR:$dst), (Ty (IntOp (Ty DPR:$src1), (Ty (NEONvduplane (Ty DPR_VFP2:$src2), @@ -849,7 +849,7 @@ string OpcodeStr, ValueType Ty, Intrinsic IntOp> : N3V<0, 1, op21_20, op11_8, 1, 0, (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane), - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", [(set (Ty DPR:$dst), (Ty (IntOp (Ty DPR:$src1), (Ty (NEONvduplane (Ty DPR_8:$src2), @@ -862,7 +862,7 @@ Intrinsic IntOp, bit Commutable> : N3V { let isCommutable = Commutable; } @@ -870,7 +870,7 @@ string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N3V<1, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", [(set (ResTy QPR:$dst), (ResTy (IntOp (ResTy QPR:$src1), (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2), @@ -881,7 +881,7 @@ string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N3V<1, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane), - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", [(set (ResTy QPR:$dst), (ResTy (IntOp (ResTy QPR:$src1), (ResTy (NEONvduplane (OpTy DPR_8:$src2), @@ -895,7 +895,7 @@ ValueType Ty, SDNode MulOp, SDNode OpNode> : N3V; class N3VDMulOpSL op21_20, bits<4> op11_8, InstrItinClass itin, @@ -903,7 +903,7 @@ : N3V<0, 1, op21_20, op11_8, 1, 0, (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin, - !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", + OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst", [(set (Ty DPR:$dst), (Ty (ShOp (Ty DPR:$src1), (Ty (MulOp DPR:$src2, @@ -914,7 +914,7 @@ : N3V<0, 1, op21_20, op11_8, 1, 0, (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin, - !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", + OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst", [(set (Ty DPR:$dst), (Ty (ShOp (Ty DPR:$src1), (Ty (MulOp DPR:$src2, @@ -926,7 +926,7 @@ SDNode MulOp, SDNode OpNode> : N3V; class N3VQMulOpSL op21_20, bits<4> op11_8, InstrItinClass itin, @@ -935,7 +935,7 @@ : N3V<1, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin, - !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", + OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst", [(set (ResTy QPR:$dst), (ResTy (ShOp (ResTy QPR:$src1), (ResTy (MulOp QPR:$src2, @@ -947,7 +947,7 @@ : N3V<1, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin, - !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", + OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst", [(set (ResTy QPR:$dst), (ResTy (ShOp (ResTy QPR:$src1), (ResTy (MulOp QPR:$src2, @@ -961,7 +961,7 @@ : N3V; + OpcodeStr, "\t$dst, $src2, $src3", "$src1 = $dst", []>; class N3VDMulOpsPat : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))), @@ -978,7 +978,7 @@ ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N3V; class N3VQInt3 op21_20, bits<4> op11_8, bit op4, @@ -986,7 +986,7 @@ ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N3V; @@ -997,7 +997,7 @@ ValueType TyQ, ValueType TyD, Intrinsic IntOp> : N3V; class N3VLInt3SL op21_20, bits<4> op11_8, InstrItinClass itin, @@ -1005,7 +1005,7 @@ : N3V : N3V { let isCommutable = Commutable; } @@ -1042,7 +1042,7 @@ Intrinsic IntOp, bit Commutable> : N3V { let isCommutable = Commutable; } @@ -1050,7 +1050,7 @@ string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N3V : N3V : N3V { let isCommutable = Commutable; } @@ -1082,13 +1082,13 @@ bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N2V; class N2VQPLInt op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N2V; // Pairwise long 2-register accumulate intrinsics, @@ -1099,14 +1099,14 @@ ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N2V; class N2VQPLInt2 op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N2V; // Shift by immediate, @@ -1115,13 +1115,13 @@ InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode OpNode> : N2VImm; class N2VQSh op11_8, bit op7, bit op4, InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode OpNode> : N2VImm; // Long shift by immediate. @@ -1129,7 +1129,7 @@ string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode OpNode> : N2VImm; @@ -1139,7 +1139,7 @@ ValueType ResTy, ValueType OpTy, SDNode OpNode> : N2VImm; @@ -1149,14 +1149,14 @@ string OpcodeStr, ValueType Ty, SDNode ShOp> : N2VImm; class N2VQShAdd op11_8, bit op7, bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> : N2VImm; @@ -1166,13 +1166,13 @@ string OpcodeStr, ValueType Ty, SDNode ShOp> : N2VImm; class N2VQShIns op11_8, bit op7, bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> : N2VImm; // Convert, with fractional bits immediate, @@ -1182,14 +1182,14 @@ Intrinsic IntOp> : N2VImm; class N2VCvtQ op11_8, bit op7, bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N2VImm; //===----------------------------------------------------------------------===// @@ -1213,24 +1213,27 @@ def v8i8 : N3VD; def v4i16 : N3VD; + !strconcat(OpcodeStr, "16"), v4i16, v4i16, OpNode, Commutable>; def v2i32 : N3VD; + !strconcat(OpcodeStr, "32"), v2i32, v2i32, OpNode, Commutable>; // 128-bit vector types. def v16i8 : N3VQ; + !strconcat(OpcodeStr, "8"), v16i8, v16i8, OpNode, Commutable>; def v8i16 : N3VQ; + !strconcat(OpcodeStr, "16"), v8i16, v8i16, OpNode, Commutable>; def v4i32 : N3VQ; + !strconcat(OpcodeStr, "32"), v4i32, v4i32, OpNode, Commutable>; } multiclass N3VSL_HS op11_8, string OpcodeStr, SDNode ShOp> { def v4i16 : N3VDSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v4i16, ShOp>; - def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, !strconcat(OpcodeStr, "32"), v2i32, ShOp>; - def v8i16 : N3VQSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v8i16, v4i16, ShOp>; - def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, !strconcat(OpcodeStr, "32"), v4i32, v2i32, ShOp>; + def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, !strconcat(OpcodeStr, "32"), + v2i32, ShOp>; + def v8i16 : N3VQSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), + v8i16, v4i16, ShOp>; + def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, !strconcat(OpcodeStr, "32"), + v4i32, v2i32, ShOp>; } // ....then also with element size 64 bits: @@ -1282,15 +1285,19 @@ InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { // 64-bit vector types. - def v4i16 : N3VDInt; - def v2i32 : N3VDInt; // 128-bit vector types. - def v8i16 : N3VQInt; - def v4i32 : N3VQInt; } @@ -1298,10 +1305,14 @@ InstrItinClass itinD16, InstrItinClass itinD32, InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, Intrinsic IntOp> { - def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, !strconcat(OpcodeStr, "16"), v4i16, IntOp>; - def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, !strconcat(OpcodeStr, "32"), v2i32, IntOp>; - def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, !strconcat(OpcodeStr, "16"), v8i16, v4i16, IntOp>; - def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, !strconcat(OpcodeStr, "32"), v4i32, v2i32, IntOp>; + def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, + !strconcat(OpcodeStr, "16"), v4i16, IntOp>; + def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, + !strconcat(OpcodeStr, "32"), v2i32, IntOp>; + def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, + !strconcat(OpcodeStr, "16"), v8i16, v4i16, IntOp>; + def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, + !strconcat(OpcodeStr, "32"), v4i32, v2i32, IntOp>; } // ....then also with element size of 8 bits: @@ -1312,9 +1323,9 @@ : N3VInt_HS { def v8i8 : N3VDInt; + !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp, Commutable>; def v16i8 : N3VQInt; + !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp, Commutable>; } // ....then also with element size of 64 bits: @@ -1325,9 +1336,9 @@ : N3VInt_QHS { def v1i64 : N3VDInt; + !strconcat(OpcodeStr,"64"), v1i64, v1i64, IntOp, Commutable>; def v2i64 : N3VQInt; + !strconcat(OpcodeStr,"64"), v2i64, v2i64, IntOp, Commutable>; } @@ -1707,12 +1718,17 @@ // Vector Add Operations. // VADD : Vector Add (integer and floating-point) -defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd.i", add, 1>; -def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd.f32", v2f32, v2f32, fadd, 1>; -def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd.f32", v4f32, v4f32, fadd, 1>; +defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd.i", + add, 1>; +def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd.f32", + v2f32, v2f32, fadd, 1>; +def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd.f32", + v4f32, v4f32, fadd, 1>; // VADDL : Vector Add Long (Q = D + D) -defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl.s", int_arm_neon_vaddls, 1>; -defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl.u", int_arm_neon_vaddlu, 1>; +defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl.s", + int_arm_neon_vaddls, 1>; +defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl.u", + int_arm_neon_vaddlu, 1>; // VADDW : Vector Add Wide (Q = Q + D) defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>; defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>; @@ -1739,14 +1755,16 @@ // Vector Multiply Operations. // VMUL : Vector Multiply (integer, polynomial and floating-point) -defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, IIC_VMULi16Q, - IIC_VMULi32Q, "vmul.i", mul, 1>; -def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul.p8", v8i8, v8i8, - int_arm_neon_vmulp, 1>; -def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul.p8", v16i8, v16i8, - int_arm_neon_vmulp, 1>; -def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul.f32", v2f32, v2f32, fmul, 1>; -def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul.f32", v4f32, v4f32, fmul, 1>; +defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, + IIC_VMULi16Q, IIC_VMULi32Q, "vmul.i", mul, 1>; +def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul.p8", + v8i8, v8i8, int_arm_neon_vmulp, 1>; +def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul.p8", + v16i8, v16i8, int_arm_neon_vmulp, 1>; +def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul.f32", + v2f32, v2f32, fmul, 1>; +def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul.f32", + v4f32, v4f32, fmul, 1>; defm VMULsl : N3VSL_HS<0b1000, "vmul.i", mul>; def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul.f32", v2f32, fmul>; def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul.f32", v4f32, v2f32, fmul>; @@ -1777,16 +1795,18 @@ IIC_VMULi16Q, IIC_VMULi32Q, "vqdmulh.s", int_arm_neon_vqdmulh>; def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1), - (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), + (v8i16 (NEONvduplane (v8i16 QPR:$src2), + imm:$lane)))), (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1), (v4i16 (EXTRACT_SUBREG QPR:$src2, - (DSubReg_i16_reg imm:$lane))), + (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))>; def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1), - (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))), + (v4i32 (NEONvduplane (v4i32 QPR:$src2), + imm:$lane)))), (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1), (v2i32 (EXTRACT_SUBREG QPR:$src2, - (DSubReg_i32_reg imm:$lane))), + (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half @@ -1797,41 +1817,53 @@ IIC_VMULi16Q, IIC_VMULi32Q, "vqrdmulh.s", int_arm_neon_vqrdmulh>; def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1), - (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), + (v8i16 (NEONvduplane (v8i16 QPR:$src2), + imm:$lane)))), (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1), (v4i16 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))>; def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1), - (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))), + (v4i32 (NEONvduplane (v4i32 QPR:$src2), + imm:$lane)))), (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1), (v2i32 (EXTRACT_SUBREG QPR:$src2, - (DSubReg_i32_reg imm:$lane))), + (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D) -defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls, 1>; -defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu, 1>; -def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull.p8", v8i16, v8i8, - int_arm_neon_vmullp, 1>; -defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls>; -defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu>; +defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull.s", + int_arm_neon_vmulls, 1>; +defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull.u", + int_arm_neon_vmullu, 1>; +def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull.p8", + v8i16, v8i8, int_arm_neon_vmullp, 1>; +defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull.s", + int_arm_neon_vmulls>; +defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull.u", + int_arm_neon_vmullu>; // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D) -defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull, 1>; -defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull>; +defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull.s", + int_arm_neon_vqdmull, 1>; +defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull.s", + int_arm_neon_vqdmull>; // Vector Multiply-Accumulate and Multiply-Subtract Operations. // VMLA : Vector Multiply Accumulate (integer and floating-point) defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>; -def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>; -def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla.f32", v4f32, fmul, fadd>; +def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", + v2f32, fmul, fadd>; +def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla.f32", + v4f32, fmul, fadd>; defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D, IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>; -def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>; -def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla.f32", v4f32, v2f32, fmul, fadd>; +def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla.f32", + v2f32, fmul, fadd>; +def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla.f32", + v4f32, v2f32, fmul, fadd>; def : Pat<(v8i16 (add (v8i16 QPR:$src1), (mul (v8i16 QPR:$src2), @@ -1848,7 +1880,7 @@ (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), (v2i32 (EXTRACT_SUBREG QPR:$src3, - (DSubReg_i32_reg imm:$lane))), + (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; def : Pat<(v4f32 (fadd (v4f32 QPR:$src1), @@ -1874,12 +1906,16 @@ // VMLS : Vector Multiply Subtract (integer and floating-point) defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>; -def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>; -def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls.f32", v4f32, fmul, fsub>; +def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", + v2f32, fmul, fsub>; +def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls.f32", + v4f32, fmul, fsub>; defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D, IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>; -def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>; -def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls.f32", v4f32, v2f32, fmul, fsub>; +def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls.f32", + v2f32, fmul, fsub>; +def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls.f32", + v4f32, v2f32, fmul, fsub>; def : Pat<(v8i16 (sub (v8i16 QPR:$src1), (mul (v8i16 QPR:$src2), @@ -1892,7 +1928,7 @@ def : Pat<(v4i32 (sub (v4i32 QPR:$src1), (mul (v4i32 QPR:$src2), - (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))), + (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))), (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), (v2i32 (EXTRACT_SUBREG QPR:$src3, @@ -1901,7 +1937,7 @@ def : Pat<(v4f32 (fsub (v4f32 QPR:$src1), (fmul (v4f32 QPR:$src2), - (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))), + (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))), (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2), (v2f32 (EXTRACT_SUBREG QPR:$src3, @@ -1922,25 +1958,34 @@ // Vector Subtract Operations. // VSUB : Vector Subtract (integer and floating-point) -defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, "vsub.i", sub, 0>; -def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub.f32", v2f32, v2f32, fsub, 0>; -def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub.f32", v4f32, v4f32, fsub, 0>; +defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, + "vsub.i", sub, 0>; +def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub.f32", + v2f32, v2f32, fsub, 0>; +def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub.f32", + v4f32, v4f32, fsub, 0>; // VSUBL : Vector Subtract Long (Q = D - D) -defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl.s", int_arm_neon_vsubls, 1>; -defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl.u", int_arm_neon_vsublu, 1>; +defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl.s", + int_arm_neon_vsubls, 1>; +defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl.u", + int_arm_neon_vsublu, 1>; // VSUBW : Vector Subtract Wide (Q = Q - D) defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>; defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>; // VHSUB : Vector Halving Subtract -defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, - IIC_VBINi4Q, "vhsub.s", int_arm_neon_vhsubs, 0>; -defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, - IIC_VBINi4Q, "vhsub.u", int_arm_neon_vhsubu, 0>; +defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, + IIC_VBINi4Q, IIC_VBINi4Q, + "vhsub.s", int_arm_neon_vhsubs, 0>; +defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, + IIC_VBINi4Q, IIC_VBINi4Q, + "vhsub.u", int_arm_neon_vhsubu, 0>; // VQSUB : Vector Saturing Subtract -defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, - IIC_VBINi4Q, "vqsub.s", int_arm_neon_vqsubs, 0>; -defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, - IIC_VBINi4Q, "vqsub.u", int_arm_neon_vqsubu, 0>; +defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, + IIC_VBINi4Q, IIC_VBINi4Q, + "vqsub.s", int_arm_neon_vqsubs, 0>; +defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, + IIC_VBINi4Q, IIC_VBINi4Q, + "vqsub.u", int_arm_neon_vqsubu, 0>; // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q) defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>; // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q) @@ -1951,32 +1996,38 @@ // VCEQ : Vector Compare Equal defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, "vceq.i", NEONvceq, 1>; -def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq.f32", v2i32, v2f32, NEONvceq, 1>; -def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq.f32", v4i32, v4f32, NEONvceq, 1>; +def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq.f32", v2i32, v2f32, + NEONvceq, 1>; +def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq.f32", v4i32, v4f32, + NEONvceq, 1>; // VCGE : Vector Compare Greater Than or Equal defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, "vcge.s", NEONvcge, 0>; defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, "vcge.u", NEONvcgeu, 0>; -def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge.f32", v2i32, v2f32, NEONvcge, 0>; -def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge.f32", v4i32, v4f32, NEONvcge, 0>; +def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge.f32", + v2i32, v2f32, NEONvcge, 0>; +def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge.f32", v4i32, v4f32, + NEONvcge, 0>; // VCGT : Vector Compare Greater Than defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, "vcgt.s", NEONvcgt, 0>; defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, "vcgt.u", NEONvcgtu, 0>; -def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>; -def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>; +def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt.f32", v2i32, v2f32, + NEONvcgt, 0>; +def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt.f32", v4i32, v4f32, + NEONvcgt, 0>; // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE) -def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge.f32", v2i32, v2f32, - int_arm_neon_vacged, 0>; -def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge.f32", v4i32, v4f32, - int_arm_neon_vacgeq, 0>; +def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge.f32", + v2i32, v2f32, int_arm_neon_vacged, 0>; +def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge.f32", + v4i32, v4f32, int_arm_neon_vacgeq, 0>; // VACGT : Vector Absolute Compare Greater Than (aka VCAGT) -def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt.f32", v2i32, v2f32, - int_arm_neon_vacgtd, 0>; -def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt.f32", v4i32, v4f32, - int_arm_neon_vacgtq, 0>; +def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt.f32", + v2i32, v2f32, int_arm_neon_vacgtd, 0>; +def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt.f32", + v4i32, v4f32, int_arm_neon_vacgtq, 0>; // VTST : Vector Test Bits defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, "vtst.i", NEONvtst, 1>; @@ -1984,49 +2035,55 @@ // Vector Bitwise Operations. // VAND : Vector Bitwise AND -def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", v2i32, v2i32, and, 1>; -def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", v4i32, v4i32, and, 1>; +def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", + v2i32, v2i32, and, 1>; +def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", + v4i32, v4i32, and, 1>; // VEOR : Vector Bitwise Exclusive OR -def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", v2i32, v2i32, xor, 1>; -def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", v4i32, v4i32, xor, 1>; +def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", + v2i32, v2i32, xor, 1>; +def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", + v4i32, v4i32, xor, 1>; // VORR : Vector Bitwise OR -def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", v2i32, v2i32, or, 1>; -def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", v4i32, v4i32, or, 1>; +def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", + v2i32, v2i32, or, 1>; +def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", + v4i32, v4i32, or, 1>; // VBIC : Vector Bitwise Bit Clear (AND NOT) def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VBINiD, - "vbic\t$dst, $src1, $src2", "", + "vbic", "\t$dst, $src1, $src2", "", [(set DPR:$dst, (v2i32 (and DPR:$src1, (vnot_conv DPR:$src2))))]>; def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINiQ, - "vbic\t$dst, $src1, $src2", "", + "vbic", "\t$dst, $src1, $src2", "", [(set QPR:$dst, (v4i32 (and QPR:$src1, (vnot_conv QPR:$src2))))]>; // VORN : Vector Bitwise OR NOT def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VBINiD, - "vorn\t$dst, $src1, $src2", "", + "vorn", "\t$dst, $src1, $src2", "", [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot_conv DPR:$src2))))]>; def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINiQ, - "vorn\t$dst, $src1, $src2", "", + "vorn", "\t$dst, $src1, $src2", "", [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot_conv QPR:$src2))))]>; // VMVN : Vector Bitwise NOT def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0, (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD, - "vmvn\t$dst, $src", "", + "vmvn", "\t$dst, $src", "", [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>; def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0, (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD, - "vmvn\t$dst, $src", "", + "vmvn", "\t$dst, $src", "", [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>; def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>; def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>; @@ -2034,13 +2091,13 @@ // VBSL : Vector Bitwise Select def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD, - "vbsl\t$dst, $src2, $src3", "$src1 = $dst", + "vbsl", "\t$dst, $src2, $src3", "$src1 = $dst", [(set DPR:$dst, (v2i32 (or (and DPR:$src2, DPR:$src1), (and DPR:$src3, (vnot_conv DPR:$src1)))))]>; def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ, - "vbsl\t$dst, $src2, $src3", "$src1 = $dst", + "vbsl", "\t$dst, $src2, $src3", "$src1 = $dst", [(set QPR:$dst, (v4i32 (or (and QPR:$src2, QPR:$src1), (and QPR:$src3, (vnot_conv QPR:$src1)))))]>; @@ -2056,18 +2113,22 @@ // Vector Absolute Differences. // VABD : Vector Absolute Difference -defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, - IIC_VBINi4Q, "vabd.s", int_arm_neon_vabds, 0>; -defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, - IIC_VBINi4Q, "vabd.u", int_arm_neon_vabdu, 0>; -def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND, "vabd.f32", v2f32, v2f32, - int_arm_neon_vabds, 0>; -def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vabd.f32", v4f32, v4f32, - int_arm_neon_vabds, 0>; +defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, + IIC_VBINi4Q, IIC_VBINi4Q, + "vabd.s", int_arm_neon_vabds, 0>; +defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, + IIC_VBINi4Q, IIC_VBINi4Q, + "vabd.u", int_arm_neon_vabdu, 0>; +def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND, + "vabd.f32", v2f32, v2f32, int_arm_neon_vabds, 0>; +def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ, + "vabd.f32", v4f32, v4f32, int_arm_neon_vabds, 0>; // VABDL : Vector Absolute Difference Long (Q = | D - D |) -defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q, "vabdl.s", int_arm_neon_vabdls, 0>; -defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q, "vabdl.u", int_arm_neon_vabdlu, 0>; +defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q, + "vabdl.s", int_arm_neon_vabdls, 0>; +defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q, + "vabdl.u", int_arm_neon_vabdlu, 0>; // VABA : Vector Absolute Difference and Accumulate defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba.s", int_arm_neon_vabas>; @@ -2318,11 +2379,11 @@ class VNEGD size, string OpcodeStr, ValueType Ty> : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src), - IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "", + IIC_VSHLiD, OpcodeStr, "\t$dst, $src", "", [(set DPR:$dst, (Ty (vneg DPR:$src)))]>; class VNEGQ size, string OpcodeStr, ValueType Ty> : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src), - IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "", + IIC_VSHLiD, OpcodeStr, "\t$dst, $src", "", [(set QPR:$dst, (Ty (vneg QPR:$src)))]>; // VNEG : Vector Negate @@ -2336,11 +2397,11 @@ // VNEG : Vector Negate (floating-point) def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0, (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD, - "vneg.f32\t$dst, $src", "", + "vneg.f32", "\t$dst, $src", "", [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>; def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0, (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ, - "vneg.f32\t$dst, $src", "", + "vneg.f32", "\t$dst, $src", "", [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>; def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>; @@ -2378,9 +2439,9 @@ // VMOV : Vector Move (Register) def VMOVDneon: N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src), - IIC_VMOVD, "vmov\t$dst, $src", "", []>; + IIC_VMOVD, "vmov", "\t$dst, $src", "", []>; def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src), - IIC_VMOVD, "vmov\t$dst, $src", "", []>; + IIC_VMOVD, "vmov", "\t$dst, $src", "", []>; // VMOV : Vector Move (Immediate) @@ -2421,38 +2482,38 @@ def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst), (ins h8imm:$SIMM), IIC_VMOVImm, - "vmov.i8\t$dst, $SIMM", "", + "vmov.i8", "\t$dst, $SIMM", "", [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>; def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst), (ins h8imm:$SIMM), IIC_VMOVImm, - "vmov.i8\t$dst, $SIMM", "", + "vmov.i8", "\t$dst, $SIMM", "", [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>; def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst), (ins h16imm:$SIMM), IIC_VMOVImm, - "vmov.i16\t$dst, $SIMM", "", + "vmov.i16", "\t$dst, $SIMM", "", [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>; def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst), (ins h16imm:$SIMM), IIC_VMOVImm, - "vmov.i16\t$dst, $SIMM", "", + "vmov.i16", "\t$dst, $SIMM", "", [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>; def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst), (ins h32imm:$SIMM), IIC_VMOVImm, - "vmov.i32\t$dst, $SIMM", "", + "vmov.i32", "\t$dst, $SIMM", "", [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>; def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst), (ins h32imm:$SIMM), IIC_VMOVImm, - "vmov.i32\t$dst, $SIMM", "", + "vmov.i32", "\t$dst, $SIMM", "", [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>; def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst), (ins h64imm:$SIMM), IIC_VMOVImm, - "vmov.i64\t$dst, $SIMM", "", + "vmov.i64", "\t$dst, $SIMM", "", [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>; def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst), (ins h64imm:$SIMM), IIC_VMOVImm, - "vmov.i64\t$dst, $SIMM", "", + "vmov.i64", "\t$dst, $SIMM", "", [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>; // VMOV : Vector Get Lane (move scalar to ARM core register) @@ -2624,13 +2685,13 @@ class VDUPLND : N2VDup<0b11, 0b11, 0b11000, 0, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD, - !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", + OpcodeStr, "\t$dst, $src[$lane]", "", [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>; class VDUPLNQ : N2VDup<0b11, 0b11, 0b11000, 1, 0, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD, - !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", + OpcodeStr, "\t$dst, $src[$lane]", "", [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>; // Inst{19-16} is partially specified depending on the element size. @@ -2663,14 +2724,14 @@ def VDUPfdf : N2VDup<0b11, 0b11, 0b11000, 0, 0, (outs DPR:$dst), (ins SPR:$src), - IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "", + IIC_VMOVD, "vdup.32", "\t$dst, ${src:lane}", "", [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]> { let Inst{18-16} = 0b100; } def VDUPfqf : N2VDup<0b11, 0b11, 0b11000, 1, 0, (outs QPR:$dst), (ins SPR:$src), - IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "", + IIC_VMOVD, "vdup.32", "\t$dst, ${src:lane}", "", [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]> { let Inst{18-16} = 0b100; } @@ -2745,12 +2806,12 @@ class VREV64D op19_18, string OpcodeStr, ValueType Ty> : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst), (ins DPR:$src), IIC_VMOVD, - !strconcat(OpcodeStr, "\t$dst, $src"), "", + OpcodeStr, "\t$dst, $src", "", [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>; class VREV64Q op19_18, string OpcodeStr, ValueType Ty> : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst), (ins QPR:$src), IIC_VMOVD, - !strconcat(OpcodeStr, "\t$dst, $src"), "", + OpcodeStr, "\t$dst, $src", "", [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>; def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>; @@ -2768,12 +2829,12 @@ class VREV32D op19_18, string OpcodeStr, ValueType Ty> : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst), (ins DPR:$src), IIC_VMOVD, - !strconcat(OpcodeStr, "\t$dst, $src"), "", + OpcodeStr, "\t$dst, $src", "", [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>; class VREV32Q op19_18, string OpcodeStr, ValueType Ty> : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst), (ins QPR:$src), IIC_VMOVD, - !strconcat(OpcodeStr, "\t$dst, $src"), "", + OpcodeStr, "\t$dst, $src", "", [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>; def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>; @@ -2787,12 +2848,12 @@ class VREV16D op19_18, string OpcodeStr, ValueType Ty> : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst), (ins DPR:$src), IIC_VMOVD, - !strconcat(OpcodeStr, "\t$dst, $src"), "", + OpcodeStr, "\t$dst, $src", "", [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>; class VREV16Q op19_18, string OpcodeStr, ValueType Ty> : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst), (ins QPR:$src), IIC_VMOVD, - !strconcat(OpcodeStr, "\t$dst, $src"), "", + OpcodeStr, "\t$dst, $src", "", [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>; def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>; @@ -2805,14 +2866,14 @@ class VEXTd : N3VImm<0,1,0b11,0,0, (outs DPR:$dst), (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD, - !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "", + OpcodeStr, "\t$dst, $lhs, $rhs, $index", "", [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs), (Ty DPR:$rhs), imm:$index)))]>; class VEXTq : N3VImm<0,1,0b11,1,0, (outs QPR:$dst), (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ, - !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "", + OpcodeStr, "\t$dst, $lhs, $rhs, $index", "", [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs), (Ty QPR:$rhs), imm:$index)))]>; @@ -2862,25 +2923,25 @@ def VTBL1 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst), (ins DPR:$tbl1, DPR:$src), IIC_VTB1, - "vtbl.8\t$dst, \\{$tbl1\\}, $src", "", + "vtbl.8", "\t$dst, \\{$tbl1\\}, $src", "", [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>; let hasExtraSrcRegAllocReq = 1 in { def VTBL2 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst), (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2, - "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "", + "vtbl.8", "\t$dst, \\{$tbl1,$tbl2\\}, $src", "", [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>; def VTBL3 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst), (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3, - "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "", + "vtbl.8", "\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "", [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>; def VTBL4 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst), (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4, - "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "", + "vtbl.8", "\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "", [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>; } // hasExtraSrcRegAllocReq = 1 @@ -2889,26 +2950,26 @@ def VTBX1 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1, - "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst", + "vtbx.8", "\t$dst, \\{$tbl1\\}, $src", "$orig = $dst", [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1 DPR:$orig, DPR:$tbl1, DPR:$src)))]>; let hasExtraSrcRegAllocReq = 1 in { def VTBX2 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2, - "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst", + "vtbx.8", "\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst", [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>; def VTBX3 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3, - "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst", + "vtbx.8", "\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst", [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>; def VTBX4 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4, - "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst", + "vtbx.8", "\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst", [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>; } // hasExtraSrcRegAllocReq = 1 @@ -2958,7 +3019,7 @@ let neverHasSideEffects = 1 in def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0, (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD, - "vneg.f32\t$dst, $src", "", []>; + "vneg.f32", "\t$dst, $src", "", []>; def : N2VDIntsPat; // Vector Convert between single-precision FP and integer Modified: llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp?rev=89542&r1=89541&r2=89542&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp (original) +++ llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp Sat Nov 21 00:21:52 2009 @@ -81,8 +81,8 @@ // afterwards // - The imp-defs / imp-uses are superregs only, we don't care about // them. - BuildMI(MBB, *MI, MI->getDebugLoc(), - TII->get(ARM::VMOVDneon), DestReg).addReg(SrcReg); + AddDefaultPred(BuildMI(MBB, *MI, MI->getDebugLoc(), + TII->get(ARM::VMOVDneon), DestReg).addReg(SrcReg)); MBB.erase(MI); MachineBasicBlock::iterator I = prior(NextMII); MI = &*I; From evan.cheng at apple.com Sat Nov 21 00:24:14 2009 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 20 Nov 2009 22:24:14 -0800 Subject: [llvm-commits] [llvm] r89542 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMBaseInstrInfo.h ARMISelDAGToDAG.cpp ARMInstrFormats.td ARMInstrNEON.td NEONMoveFix.cpp In-Reply-To: <200911210621.nAL6LqMA007301@zion.cs.uiuc.edu> References: <200911210621.nAL6LqMA007301@zion.cs.uiuc.edu> Message-ID: Also added -predicate-neon to if-convert NEON instructions. Evan On Nov 20, 2009, at 10:21 PM, Evan Cheng wrote: > Author: evancheng > Date: Sat Nov 21 00:21:52 2009 > New Revision: 89542 > > URL: http://llvm.org/viewvc/llvm-project?rev=89542&view=rev > Log: > Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td. > > Modified: > llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h > llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp > llvm/trunk/lib/Target/ARM/ARMInstrFormats.td > llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=89542&r1=89541&r2=89542&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Nov 21 00:21:52 2009 > @@ -39,6 +39,10 @@ > EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, > cl::desc("Enable ARM 2-addr to 3-addr conv")); > > +static cl::opt > +PredicateNEON("predicate-neon", cl::Hidden, > + cl::desc("Allow NEON instructions to be predicated")); > + > ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) > : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), > Subtarget(STI) { > @@ -402,6 +406,21 @@ > return Found; > } > > +/// isPredicable - Return true if the specified instruction can be predicated. > +/// By default, this returns true for every instruction with a > +/// PredicateOperand. > +bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { > + const TargetInstrDesc &TID = MI->getDesc(); > + if (!TID.isPredicable()) > + return false; > + > + if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { > + ARMFunctionInfo *AFI = > + MI->getParent()->getParent()->getInfo(); > + return PredicateNEON && AFI->isThumb2Function(); > + } > + return true; > +} > > /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing > static unsigned getNumJTEntries(const std::vector &JT, > @@ -647,11 +666,13 @@ > SrcRC == ARM::DPR_VFP2RegisterClass || > SrcRC == ARM::DPR_8RegisterClass) { > // Always use neon reg-reg move if source or dest is NEON-only regclass. > - BuildMI(MBB, I, DL, get(ARM::VMOVDneon), DestReg).addReg(SrcReg); > + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVDneon), > + DestReg).addReg(SrcReg)); > } else if (DestRC == ARM::QPRRegisterClass || > DestRC == ARM::QPR_VFP2RegisterClass || > DestRC == ARM::QPR_8RegisterClass) { > - BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg); > + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVQ), > + DestReg).addReg(SrcReg)); > } else { > return false; > } > @@ -695,13 +716,14 @@ > // FIXME: Neon instructions should support predicates > if (Align >= 16 > && (getRegisterInfo().needsStackRealignment(MF))) { > - BuildMI(MBB, I, DL, get(ARM::VST1q64)) > - .addFrameIndex(FI).addImm(0).addImm(0).addImm(128).addMemOperand(MMO) > - .addReg(SrcReg, getKillRegState(isKill)); > + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) > + .addFrameIndex(FI).addImm(0).addImm(0).addImm(128) > + .addMemOperand(MMO) > + .addReg(SrcReg, getKillRegState(isKill))); > } else { > - BuildMI(MBB, I, DL, get(ARM::VSTRQ)). > - addReg(SrcReg, getKillRegState(isKill)) > - .addFrameIndex(FI).addImm(0).addMemOperand(MMO); > + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRQ)). > + addReg(SrcReg, getKillRegState(isKill)) > + .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); > } > } > } > @@ -740,11 +762,12 @@ > // FIXME: Neon instructions should support predicates > if (Align >= 16 > && (getRegisterInfo().needsStackRealignment(MF))) { > - BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) > - .addFrameIndex(FI).addImm(0).addImm(0).addImm(128).addMemOperand(MMO); > + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) > + .addFrameIndex(FI).addImm(0).addImm(0).addImm(128) > + .addMemOperand(MMO)); > } else { > - BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0). > - addMemOperand(MMO); > + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg) > + .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); > } > } > } > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=89542&r1=89541&r2=89542&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Sat Nov 21 00:21:52 2009 > @@ -220,6 +220,8 @@ > virtual bool DefinesPredicate(MachineInstr *MI, > std::vector &Pred) const; > > + virtual bool isPredicable(MachineInstr *MI) const; > + > /// GetInstSize - Returns the size of the specified MachineInstr. > /// > virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const; > > Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=89542&r1=89541&r2=89542&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Sat Nov 21 00:21:52 2009 > @@ -1049,12 +1049,15 @@ > case MVT::v4i32: OpcodeIndex = 2; break; > } > > + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); > + SDValue PredReg = CurDAG->getRegister(0, MVT::i32); > if (is64BitVector) { > unsigned Opc = DOpcodes[OpcodeIndex]; > - const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, Chain }; > + const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, > + Pred, PredReg, Chain }; > std::vector ResTys(NumVecs, VT); > ResTys.push_back(MVT::Other); > - return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5); > + return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 7); > } > > EVT RegVT = GetNEONSubregVT(VT); > @@ -1062,10 +1065,11 @@ > // Quad registers are directly supported for VLD2, > // loading 2 pairs of D regs. > unsigned Opc = QOpcodes0[OpcodeIndex]; > - const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, Chain }; > + const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, > + Pred, PredReg, Chain }; > std::vector ResTys(4, VT); > ResTys.push_back(MVT::Other); > - SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5); > + SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 7); > Chain = SDValue(VLd, 4); > > // Combine the even and odd subregs to produce the result. > @@ -1086,15 +1090,16 @@ > > // Load the even subregs. > unsigned Opc = QOpcodes0[OpcodeIndex]; > - const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Align, Chain }; > - SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 5); > + const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Align, > + Pred, PredReg, Chain }; > + SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 7); > Chain = SDValue(VLdA, NumVecs+1); > > // Load the odd subregs. > Opc = QOpcodes1[OpcodeIndex]; > const SDValue OpsB[] = { SDValue(VLdA, NumVecs), MemUpdate, MemOpc, > - Align, Chain }; > - SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 5); > + Align, Pred, PredReg, Chain }; > + SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 7); > Chain = SDValue(VLdB, NumVecs+1); > > // Combine the even and odd subregs to produce the result. > @@ -1138,6 +1143,9 @@ > case MVT::v4i32: OpcodeIndex = 2; break; > } > > + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); > + SDValue PredReg = CurDAG->getRegister(0, MVT::i32); > + > SmallVector Ops; > Ops.push_back(MemAddr); > Ops.push_back(MemUpdate); > @@ -1148,8 +1156,10 @@ > unsigned Opc = DOpcodes[OpcodeIndex]; > for (unsigned Vec = 0; Vec < NumVecs; ++Vec) > Ops.push_back(N->getOperand(Vec+3)); > + Ops.push_back(Pred); > + Ops.push_back(PredReg); > Ops.push_back(Chain); > - return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5); > + return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+7); > } > > EVT RegVT = GetNEONSubregVT(VT); > @@ -1163,8 +1173,10 @@ > Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT, > N->getOperand(Vec+3))); > } > + Ops.push_back(Pred); > + Ops.push_back(PredReg); > Ops.push_back(Chain); > - return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 9); > + return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 11); > } > > // Otherwise, quad registers are stored with two separate instructions, > @@ -1177,10 +1189,12 @@ > for (unsigned Vec = 0; Vec < NumVecs; ++Vec) > Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT, > N->getOperand(Vec+3))); > + Ops.push_back(Pred); > + Ops.push_back(PredReg); > Ops.push_back(Chain); > unsigned Opc = QOpcodes0[OpcodeIndex]; > SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), > - MVT::Other, Ops.data(), NumVecs+5); > + MVT::Other, Ops.data(), NumVecs+7); > Chain = SDValue(VStA, 1); > > // Store the odd subregs. > @@ -1188,10 +1202,12 @@ > for (unsigned Vec = 0; Vec < NumVecs; ++Vec) > Ops[Vec+4] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT, > N->getOperand(Vec+3)); > - Ops[NumVecs+4] = Chain; > + Ops[NumVecs+4] = Pred; > + Ops[NumVecs+5] = PredReg; > + Ops[NumVecs+6] = Chain; > Opc = QOpcodes1[OpcodeIndex]; > SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), > - MVT::Other, Ops.data(), NumVecs+5); > + MVT::Other, Ops.data(), NumVecs+7); > Chain = SDValue(VStB, 1); > ReplaceUses(SDValue(N, 0), Chain); > return NULL; > @@ -1239,6 +1255,9 @@ > case MVT::v4i32: OpcodeIndex = 1; break; > } > > + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); > + SDValue PredReg = CurDAG->getRegister(0, MVT::i32); > + > SmallVector Ops; > Ops.push_back(MemAddr); > Ops.push_back(MemUpdate); > @@ -1264,15 +1283,17 @@ > N->getOperand(Vec+3))); > } > Ops.push_back(getI32Imm(Lane)); > + Ops.push_back(Pred); > + Ops.push_back(PredReg); > Ops.push_back(Chain); > > if (!IsLoad) > - return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5); > + return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+7); > > std::vector ResTys(NumVecs, RegVT); > ResTys.push_back(MVT::Other); > SDNode *VLdLn = > - CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+5); > + CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+7); > // For a 64-bit vector load to D registers, nothing more needs to be done. > if (is64BitVector) > return VLdLn; > @@ -1297,7 +1318,7 @@ > return NULL; > > unsigned Shl_imm = 0; > - if (isOpcWithIntImmediate(Op.getOperand(0).getNode(), ISD::SHL, Shl_imm)){ > + if (isOpcWithIntImmediate(Op.getOperand(0).getNode(), ISD::SHL, Shl_imm)) { > assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!"); > unsigned Srl_imm = 0; > if (isInt32Immediate(Op.getOperand(1), Srl_imm)) { > @@ -1519,7 +1540,7 @@ > > SDNode *ResNode; > if (Subtarget->isThumb1Only()) { > - SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32); > + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); > SDValue PredReg = CurDAG->getRegister(0, MVT::i32); > SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; > ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other, > @@ -1775,8 +1796,10 @@ > case MVT::v4f32: > case MVT::v4i32: Opc = ARM::VZIPq32; break; > } > - return CurDAG->getMachineNode(Opc, dl, VT, VT, > - N->getOperand(0), N->getOperand(1)); > + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); > + SDValue PredReg = CurDAG->getRegister(0, MVT::i32); > + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; > + return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); > } > case ARMISD::VUZP: { > unsigned Opc = 0; > @@ -1792,8 +1815,10 @@ > case MVT::v4f32: > case MVT::v4i32: Opc = ARM::VUZPq32; break; > } > - return CurDAG->getMachineNode(Opc, dl, VT, VT, > - N->getOperand(0), N->getOperand(1)); > + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); > + SDValue PredReg = CurDAG->getRegister(0, MVT::i32); > + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; > + return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); > } > case ARMISD::VTRN: { > unsigned Opc = 0; > @@ -1809,8 +1834,10 @@ > case MVT::v4f32: > case MVT::v4i32: Opc = ARM::VTRNq32; break; > } > - return CurDAG->getMachineNode(Opc, dl, VT, VT, > - N->getOperand(0), N->getOperand(1)); > + SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); > + SDValue PredReg = CurDAG->getRegister(0, MVT::i32); > + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; > + return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); > } > > case ISD::INTRINSIC_VOID: > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=89542&r1=89541&r2=89542&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Sat Nov 21 00:21:52 2009 > @@ -1217,27 +1217,30 @@ > // > > class NeonI - string asm, string cstr, list pattern> > + string opc, string asm, string cstr, list pattern> > : InstARM { > let OutOperandList = oops; > - let InOperandList = iops; > - let AsmString = asm; > + let InOperandList = !con(iops, (ops pred:$p)); > + let AsmString = !strconcat(opc, !strconcat("${p}", asm)); > let Pattern = pattern; > list Predicates = [HasNEON]; > } > > -class NI pattern> > - : NeonI { > +class NI + list pattern> > + : NeonI + pattern> { > } > > -class NI4 pattern> > - : NeonI { > +class NI4 + list pattern> > + : NeonI { > } > > class NLdSt op21_20, bits<4> op11_8, bits<4> op7_4, > dag oops, dag iops, InstrItinClass itin, > - string asm, string cstr, list pattern> > - : NeonI { > + string opc, string asm, string cstr, list pattern> > + : NeonI { > let Inst{31-24} = 0b11110100; > let Inst{23} = op23; > let Inst{21-20} = op21_20; > @@ -1248,8 +1251,8 @@ > // With selective bit(s) from op7_4 specified by subclasses. > class NLdStLN op21_20, bits<4> op11_8, > dag oops, dag iops, InstrItinClass itin, > - string asm, string cstr, list pattern> > - : NeonI { > + string opc, string asm, string cstr, list pattern> > + : NeonI { > let Inst{31-24} = 0b11110100; > let Inst{23} = op23; > let Inst{21-20} = op21_20; > @@ -1257,8 +1260,9 @@ > } > > class NDataI - string asm, string cstr, list pattern> > - : NeonI { > + string opc, string asm, string cstr, list pattern> > + : NeonI + cstr, pattern> { > let Inst{31-25} = 0b1111001; > } > > @@ -1266,8 +1270,8 @@ > class N1ModImm op21_19, bits<4> op11_8, bit op7, bit op6, > bit op5, bit op4, > dag oops, dag iops, InstrItinClass itin, > - string asm, string cstr, list pattern> > - : NDataI { > + string opc, string asm, string cstr, list pattern> > + : NDataI { > let Inst{23} = op23; > let Inst{21-19} = op21_19; > let Inst{11-8} = op11_8; > @@ -1281,8 +1285,8 @@ > class N2V op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, > bits<5> op11_7, bit op6, bit op4, > dag oops, dag iops, InstrItinClass itin, > - string asm, string cstr, list pattern> > - : NDataI { > + string opc, string asm, string cstr, list pattern> > + : NDataI { > let Inst{24-23} = op24_23; > let Inst{21-20} = op21_20; > let Inst{19-18} = op19_18; > @@ -1296,8 +1300,8 @@ > // Inst{19-16} is specified by subclasses. > class N2VDup op24_23, bits<2> op21_20, bits<5> op11_7, bit op6, bit op4, > dag oops, dag iops, InstrItinClass itin, > - string asm, string cstr, list pattern> > - : NDataI { > + string opc, string asm, string cstr, list pattern> > + : NDataI { > let Inst{24-23} = op24_23; > let Inst{21-20} = op21_20; > let Inst{11-7} = op11_7; > @@ -1308,8 +1312,8 @@ > // NEON 2 vector register with immediate. > class N2VImm op11_8, bit op7, bit op6, bit op4, > dag oops, dag iops, InstrItinClass itin, > - string asm, string cstr, list pattern> > - : NDataI { > + string opc, string asm, string cstr, list pattern> > + : NDataI { > let Inst{24} = op24; > let Inst{23} = op23; > let Inst{11-8} = op11_8; > @@ -1321,8 +1325,8 @@ > // NEON 3 vector register format. > class N3V op21_20, bits<4> op11_8, bit op6, bit op4, > dag oops, dag iops, InstrItinClass itin, > - string asm, string cstr, list pattern> > - : NDataI { > + string opc, string asm, string cstr, list pattern> > + : NDataI { > let Inst{24} = op24; > let Inst{23} = op23; > let Inst{21-20} = op21_20; > @@ -1336,8 +1340,8 @@ > // concatenation of the operands and is left unspecified. > class N3VImm op21_20, bit op6, bit op4, > dag oops, dag iops, InstrItinClass itin, > - string asm, string cstr, list pattern> > - : NDataI { > + string opc, string asm, string cstr, list pattern> > + : NDataI { > let Inst{24} = op24; > let Inst{23} = op23; > let Inst{21-20} = op21_20; > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=89542&r1=89541&r2=89542&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Sat Nov 21 00:21:52 2009 > @@ -124,7 +124,7 @@ > def VLDMD : NI<(outs), > (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), > IIC_fpLoadm, > - "vldm${addr:submode} ${addr:base}, $dst1", > + "vldm", "${addr:submode} ${addr:base}, $dst1", > []> { > let Inst{27-25} = 0b110; > let Inst{20} = 1; > @@ -134,7 +134,7 @@ > def VLDMS : NI<(outs), > (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), > IIC_fpLoadm, > - "vldm${addr:submode} ${addr:base}, $dst1", > + "vldm", "${addr:submode} ${addr:base}, $dst1", > []> { > let Inst{27-25} = 0b110; > let Inst{20} = 1; > @@ -146,7 +146,7 @@ > // Use vldmia to load a Q register as a D register pair. > def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), > IIC_fpLoadm, > - "vldmia\t$addr, ${dst:dregpair}", > + "vldmia", "\t$addr, ${dst:dregpair}", > [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> { > let Inst{27-25} = 0b110; > let Inst{24} = 0; // P bit > @@ -158,7 +158,7 @@ > // Use vstmia to store a Q register as a D register pair. > def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), > IIC_fpStorem, > - "vstmia\t$addr, ${src:dregpair}", > + "vstmia", "\t$addr, ${src:dregpair}", > [(store (v2f64 QPR:$src), addrmode4:$addr)]> { > let Inst{27-25} = 0b110; > let Inst{24} = 0; // P bit > @@ -170,11 +170,11 @@ > // VLD1 : Vector Load (multiple single elements) > class VLD1D op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp> > : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1, > - !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), "", > + OpcodeStr, "\t\\{$dst\\}, $addr", "", > [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>; > class VLD1Q op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp> > : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1, > - !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), "", > + OpcodeStr, "\t${dst:dregpair}, $addr", "", > [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>; > > def VLD1d8 : VLD1D<0b0000, "vld1.8", v8i8, int_arm_neon_vld1>; > @@ -195,12 +195,12 @@ > class VLD2D op7_4, string OpcodeStr> > : NLdSt<0,0b10,0b1000,op7_4, (outs DPR:$dst1, DPR:$dst2), > (ins addrmode6:$addr), IIC_VLD2, > - !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), "", []>; > + OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr", "", []>; > class VLD2Q op7_4, string OpcodeStr> > : NLdSt<0,0b10,0b0011,op7_4, > (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), > (ins addrmode6:$addr), IIC_VLD2, > - !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), > + OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", > "", []>; > > def VLD2d8 : VLD2D<0b0000, "vld2.8">; > @@ -208,7 +208,7 @@ > def VLD2d32 : VLD2D<0b1000, "vld2.32">; > def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2), > (ins addrmode6:$addr), IIC_VLD1, > - "vld1.64\t\\{$dst1,$dst2\\}, $addr", "", []>; > + "vld1.64", "\t\\{$dst1,$dst2\\}, $addr", "", []>; > > def VLD2q8 : VLD2Q<0b0000, "vld2.8">; > def VLD2q16 : VLD2Q<0b0100, "vld2.16">; > @@ -218,11 +218,11 @@ > class VLD3D op7_4, string OpcodeStr> > : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), > (ins addrmode6:$addr), IIC_VLD3, > - !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>; > + OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr", "", []>; > class VLD3WB op7_4, string OpcodeStr> > : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb), > (ins addrmode6:$addr), IIC_VLD3, > - !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), > + OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr", > "$addr.addr = $wb", []>; > > def VLD3d8 : VLD3D<0b0000, "vld3.8">; > @@ -231,7 +231,7 @@ > def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100, > (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), > (ins addrmode6:$addr), IIC_VLD1, > - "vld1.64\t\\{$dst1,$dst2,$dst3\\}, $addr", "", []>; > + "vld1.64", "\t\\{$dst1,$dst2,$dst3\\}, $addr", "", []>; > > // vld3 to double-spaced even registers. > def VLD3q8a : VLD3WB<0b0000, "vld3.8">; > @@ -248,13 +248,13 @@ > : NLdSt<0,0b10,0b0000,op7_4, > (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), > (ins addrmode6:$addr), IIC_VLD4, > - !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), > + OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", > "", []>; > class VLD4WB op7_4, string OpcodeStr> > : NLdSt<0,0b10,0b0001,op7_4, > (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), > (ins addrmode6:$addr), IIC_VLD4, > - !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), > + OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", > "$addr.addr = $wb", []>; > > def VLD4d8 : VLD4D<0b0000, "vld4.8">; > @@ -263,7 +263,7 @@ > def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100, > (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), > (ins addrmode6:$addr), IIC_VLD1, > - "vld1.64\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "", []>; > + "vld1.64", "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "", []>; > > // vld4 to double-spaced even registers. > def VLD4q8a : VLD4WB<0b0000, "vld4.8">; > @@ -283,7 +283,7 @@ > : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), > IIC_VLD2, > - !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"), > + OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr", > "$src1 = $dst1, $src2 = $dst2", []>; > > // vld2 to single-spaced registers. > @@ -316,8 +316,8 @@ > : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, > nohash_imm:$lane), IIC_VLD3, > - !strconcat(OpcodeStr, > - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"), > + OpcodeStr, > + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr", > "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>; > > // vld3 to single-spaced registers. > @@ -353,8 +353,8 @@ > (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, > nohash_imm:$lane), IIC_VLD4, > - !strconcat(OpcodeStr, > - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"), > + OpcodeStr, > + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr", > "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>; > > // vld4 to single-spaced registers. > @@ -392,11 +392,11 @@ > // VST1 : Vector Store (multiple single elements) > class VST1D op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp> > : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST, > - !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), "", > + OpcodeStr, "\t\\{$src\\}, $addr", "", > [(IntOp addrmode6:$addr, (Ty DPR:$src))]>; > class VST1Q op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp> > : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST, > - !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "", > + OpcodeStr, "\t${src:dregpair}, $addr", "", > [(IntOp addrmode6:$addr, (Ty QPR:$src))]>; > > let hasExtraSrcRegAllocReq = 1 in { > @@ -419,12 +419,12 @@ > class VST2D op7_4, string OpcodeStr> > : NLdSt<0,0b00,0b1000,op7_4, (outs), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST, > - !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>; > + OpcodeStr, "\t\\{$src1,$src2\\}, $addr", "", []>; > class VST2Q op7_4, string OpcodeStr> > : NLdSt<0,0b00,0b0011,op7_4, (outs), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), > IIC_VST, > - !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), > + OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr", > "", []>; > > def VST2d8 : VST2D<0b0000, "vst2.8">; > @@ -432,7 +432,7 @@ > def VST2d32 : VST2D<0b1000, "vst2.32">; > def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST, > - "vst1.64\t\\{$src1,$src2\\}, $addr", "", []>; > + "vst1.64", "\t\\{$src1,$src2\\}, $addr", "", []>; > > def VST2q8 : VST2Q<0b0000, "vst2.8">; > def VST2q16 : VST2Q<0b0100, "vst2.16">; > @@ -442,11 +442,11 @@ > class VST3D op7_4, string OpcodeStr> > : NLdSt<0,0b00,0b0100,op7_4, (outs), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST, > - !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>; > + OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr", "", []>; > class VST3WB op7_4, string OpcodeStr> > : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST, > - !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), > + OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr", > "$addr.addr = $wb", []>; > > def VST3d8 : VST3D<0b0000, "vst3.8">; > @@ -455,7 +455,7 @@ > def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), > IIC_VST, > - "vst1.64\t\\{$src1,$src2,$src3\\}, $addr", "", []>; > + "vst1.64", "\t\\{$src1,$src2,$src3\\}, $addr", "", []>; > > // vst3 to double-spaced even registers. > def VST3q8a : VST3WB<0b0000, "vst3.8">; > @@ -472,13 +472,13 @@ > : NLdSt<0,0b00,0b0000,op7_4, (outs), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), > IIC_VST, > - !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), > + OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr", > "", []>; > class VST4WB op7_4, string OpcodeStr> > : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), > IIC_VST, > - !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), > + OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr", > "$addr.addr = $wb", []>; > > def VST4d8 : VST4D<0b0000, "vst4.8">; > @@ -487,7 +487,7 @@ > def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, > DPR:$src4), IIC_VST, > - "vst1.64\t\\{$src1,$src2,$src3,$src4\\}, $addr", "", []>; > + "vst1.64", "\t\\{$src1,$src2,$src3,$src4\\}, $addr", "", []>; > > // vst4 to double-spaced even registers. > def VST4q8a : VST4WB<0b0000, "vst4.8">; > @@ -507,7 +507,7 @@ > : NLdStLN<1,0b00,op11_8, (outs), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), > IIC_VST, > - !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"), > + OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr", > "", []>; > > // vst2 to single-spaced registers. > @@ -540,8 +540,8 @@ > : NLdStLN<1,0b00,op11_8, (outs), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, > nohash_imm:$lane), IIC_VST, > - !strconcat(OpcodeStr, > - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>; > + OpcodeStr, > + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr", "", []>; > > // vst3 to single-spaced registers. > def VST3LNd8 : VST3LN<0b0010, "vst3.8"> { > @@ -575,8 +575,8 @@ > : NLdStLN<1,0b00,op11_8, (outs), > (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, > nohash_imm:$lane), IIC_VST, > - !strconcat(OpcodeStr, > - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"), > + OpcodeStr, > + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr", > "", []>; > > // vst4 to single-spaced registers. > @@ -655,13 +655,13 @@ > bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, > ValueType ResTy, ValueType OpTy, SDNode OpNode> > : N2V - (ins DPR:$src), IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "", > + (ins DPR:$src), IIC_VUNAD, OpcodeStr, "\t$dst, $src", "", > [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>; > class N2VQ op24_23, bits<2> op21_20, bits<2> op19_18, > bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, > ValueType ResTy, ValueType OpTy, SDNode OpNode> > : N2V - (ins QPR:$src), IIC_VUNAQ, !strconcat(OpcodeStr, "\t$dst, $src"), "", > + (ins QPR:$src), IIC_VUNAQ, OpcodeStr, "\t$dst, $src", "", > [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>; > > // Basic 2-register operations, scalar single-precision. > @@ -670,7 +670,7 @@ > ValueType ResTy, ValueType OpTy, SDNode OpNode> > : N2V (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), > - IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>; > + IIC_VUNAD, OpcodeStr, "\t$dst, $src", "", []>; > > class N2VDsPat > : NEONFPPat<(ResTy (OpNode SPR:$a)), > @@ -684,14 +684,14 @@ > InstrItinClass itin, string OpcodeStr, > ValueType ResTy, ValueType OpTy, Intrinsic IntOp> > : N2V - (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "", > + (ins DPR:$src), itin, OpcodeStr, "\t$dst, $src", "", > [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>; > class N2VQInt op24_23, bits<2> op21_20, bits<2> op19_18, > bits<2> op17_16, bits<5> op11_7, bit op4, > InstrItinClass itin, string OpcodeStr, > ValueType ResTy, ValueType OpTy, Intrinsic IntOp> > : N2V - (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "", > + (ins QPR:$src), itin, OpcodeStr, "\t$dst, $src", "", > [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>; > > // Basic 2-register intrinsics, scalar single-precision > @@ -701,7 +701,7 @@ > ValueType ResTy, ValueType OpTy, Intrinsic IntOp> > : N2V (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), itin, > - !strconcat(OpcodeStr, "\t$dst, $src"), "", []>; > + OpcodeStr, "\t$dst, $src", "", []>; > > class N2VDIntsPat > : NEONFPPat<(f32 (OpNode SPR:$a)), > @@ -715,7 +715,7 @@ > InstrItinClass itin, string OpcodeStr, > ValueType TyD, ValueType TyQ, Intrinsic IntOp> > : N2V - (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "", > + (ins QPR:$src), itin, OpcodeStr, "\t$dst, $src", "", > [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>; > > // Long 2-register intrinsics (currently only used for VMOVL). > @@ -724,20 +724,20 @@ > InstrItinClass itin, string OpcodeStr, > ValueType TyQ, ValueType TyD, Intrinsic IntOp> > : N2V - (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "", > + (ins DPR:$src), itin, OpcodeStr, "\t$dst, $src", "", > [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>; > > // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register. > class N2VDShuffle op19_18, bits<5> op11_7, string OpcodeStr> > : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2), > (ins DPR:$src1, DPR:$src2), IIC_VPERMD, > - !strconcat(OpcodeStr, "\t$dst1, $dst2"), > + OpcodeStr, "\t$dst1, $dst2", > "$src1 = $dst1, $src2 = $dst2", []>; > class N2VQShuffle op19_18, bits<5> op11_7, > InstrItinClass itin, string OpcodeStr> > : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2), > (ins QPR:$src1, QPR:$src2), itin, > - !strconcat(OpcodeStr, "\t$dst1, $dst2"), > + OpcodeStr, "\t$dst1, $dst2", > "$src1 = $dst1, $src2 = $dst2", []>; > > // Basic 3-register operations, both double- and quad-register. > @@ -746,7 +746,7 @@ > SDNode OpNode, bit Commutable> > : N3V (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin, > - !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", > + OpcodeStr, "\t$dst, $src1, $src2", "", > [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> { > let isCommutable = Commutable; > } > @@ -754,7 +754,7 @@ > InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode ShOp> > : N3V<0, 1, op21_20, op11_8, 1, 0, > (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), > - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", > + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", > [(set (Ty DPR:$dst), > (Ty (ShOp (Ty DPR:$src1), > (Ty (NEONvduplane (Ty DPR_VFP2:$src2), > @@ -766,7 +766,7 @@ > : N3V<0, 1, op21_20, op11_8, 1, 0, > (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane), > IIC_VMULi16D, > - !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", > + OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", > [(set (Ty DPR:$dst), > (Ty (ShOp (Ty DPR:$src1), > (Ty (NEONvduplane (Ty DPR_8:$src2), > @@ -779,7 +779,7 @@ > SDNode OpNode, bit Commutable> > : N3V (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin, > - !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", > + OpcodeStr, "\t$dst, $src1, $src2", "", > [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> { > let isCommutable = Commutable; > } > @@ -788,7 +788,7 @@ > ValueType ResTy, ValueType OpTy, SDNode ShOp> > : N3V<1, 1, op21_20, op11_8, 1, 0, > (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), > - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", > + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", > [(set (ResTy QPR:$dst), > (ResTy (ShOp (ResTy QPR:$src1), > (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2), > @@ -800,7 +800,7 @@ > : N3V<1, 1, op21_20, op11_8, 1, 0, > (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane), > IIC_VMULi16Q, > - !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", > + OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", > [(set (ResTy QPR:$dst), > (ResTy (ShOp (ResTy QPR:$src1), > (ResTy (NEONvduplane (OpTy DPR_8:$src2), > @@ -814,7 +814,7 @@ > SDNode OpNode, bit Commutable> > : N3V (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND, > - !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> { > + OpcodeStr, "\t$dst, $src1, $src2", "", []> { > let isCommutable = Commutable; > } > class N3VDsPat > @@ -830,7 +830,7 @@ > Intrinsic IntOp, bit Commutable> > : N3V (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin, > - !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", > + OpcodeStr, "\t$dst, $src1, $src2", "", > [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> { > let isCommutable = Commutable; > } > @@ -838,7 +838,7 @@ > string OpcodeStr, ValueType Ty, Intrinsic IntOp> > : N3V<0, 1, op21_20, op11_8, 1, 0, > (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), > - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", > + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", > [(set (Ty DPR:$dst), > (Ty (IntOp (Ty DPR:$src1), > (Ty (NEONvduplane (Ty DPR_VFP2:$src2), > @@ -849,7 +849,7 @@ > string OpcodeStr, ValueType Ty, Intrinsic IntOp> > : N3V<0, 1, op21_20, op11_8, 1, 0, > (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane), > - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", > + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", > [(set (Ty DPR:$dst), > (Ty (IntOp (Ty DPR:$src1), > (Ty (NEONvduplane (Ty DPR_8:$src2), > @@ -862,7 +862,7 @@ > Intrinsic IntOp, bit Commutable> > : N3V (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin, > - !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", > + OpcodeStr, "\t$dst, $src1, $src2", "", > [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> { > let isCommutable = Commutable; > } > @@ -870,7 +870,7 @@ > string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> > : N3V<1, 1, op21_20, op11_8, 1, 0, > (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), > - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", > + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", > [(set (ResTy QPR:$dst), > (ResTy (IntOp (ResTy QPR:$src1), > (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2), > @@ -881,7 +881,7 @@ > string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> > : N3V<1, 1, op21_20, op11_8, 1, 0, > (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane), > - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", > + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", > [(set (ResTy QPR:$dst), > (ResTy (IntOp (ResTy QPR:$src1), > (ResTy (NEONvduplane (OpTy DPR_8:$src2), > @@ -895,7 +895,7 @@ > ValueType Ty, SDNode MulOp, SDNode OpNode> > : N3V (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin, > - !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $src3", "$src1 = $dst", > [(set DPR:$dst, (Ty (OpNode DPR:$src1, > (Ty (MulOp DPR:$src2, DPR:$src3)))))]>; > class N3VDMulOpSL op21_20, bits<4> op11_8, InstrItinClass itin, > @@ -903,7 +903,7 @@ > : N3V<0, 1, op21_20, op11_8, 1, 0, > (outs DPR:$dst), > (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin, > - !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst", > [(set (Ty DPR:$dst), > (Ty (ShOp (Ty DPR:$src1), > (Ty (MulOp DPR:$src2, > @@ -914,7 +914,7 @@ > : N3V<0, 1, op21_20, op11_8, 1, 0, > (outs DPR:$dst), > (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin, > - !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst", > [(set (Ty DPR:$dst), > (Ty (ShOp (Ty DPR:$src1), > (Ty (MulOp DPR:$src2, > @@ -926,7 +926,7 @@ > SDNode MulOp, SDNode OpNode> > : N3V (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin, > - !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $src3", "$src1 = $dst", > [(set QPR:$dst, (Ty (OpNode QPR:$src1, > (Ty (MulOp QPR:$src2, QPR:$src3)))))]>; > class N3VQMulOpSL op21_20, bits<4> op11_8, InstrItinClass itin, > @@ -935,7 +935,7 @@ > : N3V<1, 1, op21_20, op11_8, 1, 0, > (outs QPR:$dst), > (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin, > - !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst", > [(set (ResTy QPR:$dst), > (ResTy (ShOp (ResTy QPR:$src1), > (ResTy (MulOp QPR:$src2, > @@ -947,7 +947,7 @@ > : N3V<1, 1, op21_20, op11_8, 1, 0, > (outs QPR:$dst), > (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin, > - !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst", > [(set (ResTy QPR:$dst), > (ResTy (ShOp (ResTy QPR:$src1), > (ResTy (MulOp QPR:$src2, > @@ -961,7 +961,7 @@ > : N3V (outs DPR_VFP2:$dst), > (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin, > - !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>; > + OpcodeStr, "\t$dst, $src2, $src3", "$src1 = $dst", []>; > > class N3VDMulOpsPat > : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))), > @@ -978,7 +978,7 @@ > ValueType ResTy, ValueType OpTy, Intrinsic IntOp> > : N3V (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin, > - !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $src3", "$src1 = $dst", > [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), > (OpTy DPR:$src2), (OpTy DPR:$src3))))]>; > class N3VQInt3 op21_20, bits<4> op11_8, bit op4, > @@ -986,7 +986,7 @@ > ValueType ResTy, ValueType OpTy, Intrinsic IntOp> > : N3V (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin, > - !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $src3", "$src1 = $dst", > [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), > (OpTy QPR:$src2), (OpTy QPR:$src3))))]>; > > @@ -997,7 +997,7 @@ > ValueType TyQ, ValueType TyD, Intrinsic IntOp> > : N3V (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin, > - !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $src3", "$src1 = $dst", > [(set QPR:$dst, > (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>; > class N3VLInt3SL op21_20, bits<4> op11_8, InstrItinClass itin, > @@ -1005,7 +1005,7 @@ > : N3V (outs QPR:$dst), > (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin, > - !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst", > [(set (ResTy QPR:$dst), > (ResTy (IntOp (ResTy QPR:$src1), > (OpTy DPR:$src2), > @@ -1017,7 +1017,7 @@ > : N3V (outs QPR:$dst), > (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin, > - !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst", > [(set (ResTy QPR:$dst), > (ResTy (IntOp (ResTy QPR:$src1), > (OpTy DPR:$src2), > @@ -1031,7 +1031,7 @@ > Intrinsic IntOp, bit Commutable> > : N3V (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D, > - !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", > + OpcodeStr, "\t$dst, $src1, $src2", "", > [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> { > let isCommutable = Commutable; > } > @@ -1042,7 +1042,7 @@ > Intrinsic IntOp, bit Commutable> > : N3V (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin, > - !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", > + OpcodeStr, "\t$dst, $src1, $src2", "", > [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> { > let isCommutable = Commutable; > } > @@ -1050,7 +1050,7 @@ > string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp> > : N3V (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), > - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", > + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", > [(set (ResTy QPR:$dst), > (ResTy (IntOp (OpTy DPR:$src1), > (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2), > @@ -1060,7 +1060,7 @@ > Intrinsic IntOp> > : N3V (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane), > - itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "", > + itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "", > [(set (ResTy QPR:$dst), > (ResTy (IntOp (OpTy DPR:$src1), > (OpTy (NEONvduplane (OpTy DPR_8:$src2), > @@ -1072,7 +1072,7 @@ > Intrinsic IntOp, bit Commutable> > : N3V (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD, > - !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", > + OpcodeStr, "\t$dst, $src1, $src2", "", > [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> { > let isCommutable = Commutable; > } > @@ -1082,13 +1082,13 @@ > bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, > ValueType ResTy, ValueType OpTy, Intrinsic IntOp> > : N2V - (ins DPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "", > + (ins DPR:$src), IIC_VSHLiD, OpcodeStr, "\t$dst, $src", "", > [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>; > class N2VQPLInt op24_23, bits<2> op21_20, bits<2> op19_18, > bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, > ValueType ResTy, ValueType OpTy, Intrinsic IntOp> > : N2V - (ins QPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "", > + (ins QPR:$src), IIC_VSHLiD, OpcodeStr, "\t$dst, $src", "", > [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>; > > // Pairwise long 2-register accumulate intrinsics, > @@ -1099,14 +1099,14 @@ > ValueType ResTy, ValueType OpTy, Intrinsic IntOp> > : N2V (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD, > - !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2", "$src1 = $dst", > [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>; > class N2VQPLInt2 op24_23, bits<2> op21_20, bits<2> op19_18, > bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, > ValueType ResTy, ValueType OpTy, Intrinsic IntOp> > : N2V (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ, > - !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2", "$src1 = $dst", > [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>; > > // Shift by immediate, > @@ -1115,13 +1115,13 @@ > InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode OpNode> > : N2VImm (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin, > - !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", > + OpcodeStr, "\t$dst, $src, $SIMM", "", > [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>; > class N2VQSh op11_8, bit op7, bit op4, > InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode OpNode> > : N2VImm (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin, > - !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", > + OpcodeStr, "\t$dst, $src, $SIMM", "", > [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>; > > // Long shift by immediate. > @@ -1129,7 +1129,7 @@ > string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode OpNode> > : N2VImm (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD, > - !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", > + OpcodeStr, "\t$dst, $src, $SIMM", "", > [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src), > (i32 imm:$SIMM))))]>; > > @@ -1139,7 +1139,7 @@ > ValueType ResTy, ValueType OpTy, SDNode OpNode> > : N2VImm (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin, > - !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", > + OpcodeStr, "\t$dst, $src, $SIMM", "", > [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src), > (i32 imm:$SIMM))))]>; > > @@ -1149,14 +1149,14 @@ > string OpcodeStr, ValueType Ty, SDNode ShOp> > : N2VImm (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD, > - !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $SIMM", "$src1 = $dst", > [(set DPR:$dst, (Ty (add DPR:$src1, > (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>; > class N2VQShAdd op11_8, bit op7, bit op4, > string OpcodeStr, ValueType Ty, SDNode ShOp> > : N2VImm (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD, > - !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $SIMM", "$src1 = $dst", > [(set QPR:$dst, (Ty (add QPR:$src1, > (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>; > > @@ -1166,13 +1166,13 @@ > string OpcodeStr, ValueType Ty, SDNode ShOp> > : N2VImm (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD, > - !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $SIMM", "$src1 = $dst", > [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>; > class N2VQShIns op11_8, bit op7, bit op4, > string OpcodeStr, ValueType Ty, SDNode ShOp> > : N2VImm (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ, > - !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", > + OpcodeStr, "\t$dst, $src2, $SIMM", "$src1 = $dst", > [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>; > > // Convert, with fractional bits immediate, > @@ -1182,14 +1182,14 @@ > Intrinsic IntOp> > : N2VImm (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD, > - !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", > + OpcodeStr, "\t$dst, $src, $SIMM", "", > [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>; > class N2VCvtQ op11_8, bit op7, bit op4, > string OpcodeStr, ValueType ResTy, ValueType OpTy, > Intrinsic IntOp> > : N2VImm (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ, > - !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", > + OpcodeStr, "\t$dst, $src, $SIMM", "", > [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>; > > //===----------------------------------------------------------------------===// > @@ -1213,24 +1213,27 @@ > def v8i8 : N3VD !strconcat(OpcodeStr, "8"), v8i8, v8i8, OpNode, Commutable>; > def v4i16 : N3VD - !strconcat(OpcodeStr, "16"), v4i16, v4i16, OpNode, Commutable>; > + !strconcat(OpcodeStr, "16"), v4i16, v4i16, OpNode, Commutable>; > def v2i32 : N3VD - !strconcat(OpcodeStr, "32"), v2i32, v2i32, OpNode, Commutable>; > + !strconcat(OpcodeStr, "32"), v2i32, v2i32, OpNode, Commutable>; > > // 128-bit vector types. > def v16i8 : N3VQ - !strconcat(OpcodeStr, "8"), v16i8, v16i8, OpNode, Commutable>; > + !strconcat(OpcodeStr, "8"), v16i8, v16i8, OpNode, Commutable>; > def v8i16 : N3VQ - !strconcat(OpcodeStr, "16"), v8i16, v8i16, OpNode, Commutable>; > + !strconcat(OpcodeStr, "16"), v8i16, v8i16, OpNode, Commutable>; > def v4i32 : N3VQ - !strconcat(OpcodeStr, "32"), v4i32, v4i32, OpNode, Commutable>; > + !strconcat(OpcodeStr, "32"), v4i32, v4i32, OpNode, Commutable>; > } > > multiclass N3VSL_HS op11_8, string OpcodeStr, SDNode ShOp> { > def v4i16 : N3VDSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v4i16, ShOp>; > - def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, !strconcat(OpcodeStr, "32"), v2i32, ShOp>; > - def v8i16 : N3VQSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v8i16, v4i16, ShOp>; > - def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, !strconcat(OpcodeStr, "32"), v4i32, v2i32, ShOp>; > + def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, !strconcat(OpcodeStr, "32"), > + v2i32, ShOp>; > + def v8i16 : N3VQSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), > + v8i16, v4i16, ShOp>; > + def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, !strconcat(OpcodeStr, "32"), > + v4i32, v2i32, ShOp>; > } > > // ....then also with element size 64 bits: > @@ -1282,15 +1285,19 @@ > InstrItinClass itinQ16, InstrItinClass itinQ32, > string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { > // 64-bit vector types. > - def v4i16 : N3VDInt + def v4i16 : N3VDInt + !strconcat(OpcodeStr,"16"), > v4i16, v4i16, IntOp, Commutable>; > - def v2i32 : N3VDInt + def v2i32 : N3VDInt + !strconcat(OpcodeStr,"32"), > v2i32, v2i32, IntOp, Commutable>; > > // 128-bit vector types. > - def v8i16 : N3VQInt + def v8i16 : N3VQInt + !strconcat(OpcodeStr,"16"), > v8i16, v8i16, IntOp, Commutable>; > - def v4i32 : N3VQInt + def v4i32 : N3VQInt + !strconcat(OpcodeStr,"32"), > v4i32, v4i32, IntOp, Commutable>; > } > > @@ -1298,10 +1305,14 @@ > InstrItinClass itinD16, InstrItinClass itinD32, > InstrItinClass itinQ16, InstrItinClass itinQ32, > string OpcodeStr, Intrinsic IntOp> { > - def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, !strconcat(OpcodeStr, "16"), v4i16, IntOp>; > - def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, !strconcat(OpcodeStr, "32"), v2i32, IntOp>; > - def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, !strconcat(OpcodeStr, "16"), v8i16, v4i16, IntOp>; > - def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, !strconcat(OpcodeStr, "32"), v4i32, v2i32, IntOp>; > + def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, > + !strconcat(OpcodeStr, "16"), v4i16, IntOp>; > + def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, > + !strconcat(OpcodeStr, "32"), v2i32, IntOp>; > + def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, > + !strconcat(OpcodeStr, "16"), v8i16, v4i16, IntOp>; > + def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, > + !strconcat(OpcodeStr, "32"), v4i32, v2i32, IntOp>; > } > > // ....then also with element size of 8 bits: > @@ -1312,9 +1323,9 @@ > : N3VInt_HS OpcodeStr, IntOp, Commutable> { > def v8i8 : N3VDInt - !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp, Commutable>; > + !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp, Commutable>; > def v16i8 : N3VQInt - !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp, Commutable>; > + !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp, Commutable>; > } > > // ....then also with element size of 64 bits: > @@ -1325,9 +1336,9 @@ > : N3VInt_QHS OpcodeStr, IntOp, Commutable> { > def v1i64 : N3VDInt - !strconcat(OpcodeStr,"64"), v1i64, v1i64, IntOp, Commutable>; > + !strconcat(OpcodeStr,"64"), v1i64, v1i64, IntOp, Commutable>; > def v2i64 : N3VQInt - !strconcat(OpcodeStr,"64"), v2i64, v2i64, IntOp, Commutable>; > + !strconcat(OpcodeStr,"64"), v2i64, v2i64, IntOp, Commutable>; > } > > > @@ -1707,12 +1718,17 @@ > // Vector Add Operations. > > // VADD : Vector Add (integer and floating-point) > -defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd.i", add, 1>; > -def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd.f32", v2f32, v2f32, fadd, 1>; > -def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd.f32", v4f32, v4f32, fadd, 1>; > +defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd.i", > + add, 1>; > +def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd.f32", > + v2f32, v2f32, fadd, 1>; > +def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd.f32", > + v4f32, v4f32, fadd, 1>; > // VADDL : Vector Add Long (Q = D + D) > -defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl.s", int_arm_neon_vaddls, 1>; > -defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl.u", int_arm_neon_vaddlu, 1>; > +defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl.s", > + int_arm_neon_vaddls, 1>; > +defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl.u", > + int_arm_neon_vaddlu, 1>; > // VADDW : Vector Add Wide (Q = Q + D) > defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>; > defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>; > @@ -1739,14 +1755,16 @@ > // Vector Multiply Operations. > > // VMUL : Vector Multiply (integer, polynomial and floating-point) > -defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, IIC_VMULi16Q, > - IIC_VMULi32Q, "vmul.i", mul, 1>; > -def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul.p8", v8i8, v8i8, > - int_arm_neon_vmulp, 1>; > -def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul.p8", v16i8, v16i8, > - int_arm_neon_vmulp, 1>; > -def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul.f32", v2f32, v2f32, fmul, 1>; > -def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul.f32", v4f32, v4f32, fmul, 1>; > +defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, > + IIC_VMULi16Q, IIC_VMULi32Q, "vmul.i", mul, 1>; > +def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul.p8", > + v8i8, v8i8, int_arm_neon_vmulp, 1>; > +def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul.p8", > + v16i8, v16i8, int_arm_neon_vmulp, 1>; > +def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul.f32", > + v2f32, v2f32, fmul, 1>; > +def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul.f32", > + v4f32, v4f32, fmul, 1>; > defm VMULsl : N3VSL_HS<0b1000, "vmul.i", mul>; > def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul.f32", v2f32, fmul>; > def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul.f32", v4f32, v2f32, fmul>; > @@ -1777,16 +1795,18 @@ > IIC_VMULi16Q, IIC_VMULi32Q, > "vqdmulh.s", int_arm_neon_vqdmulh>; > def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1), > - (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), > + (v8i16 (NEONvduplane (v8i16 QPR:$src2), > + imm:$lane)))), > (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1), > (v4i16 (EXTRACT_SUBREG QPR:$src2, > - (DSubReg_i16_reg imm:$lane))), > + (DSubReg_i16_reg imm:$lane))), > (SubReg_i16_lane imm:$lane)))>; > def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1), > - (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))), > + (v4i32 (NEONvduplane (v4i32 QPR:$src2), > + imm:$lane)))), > (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1), > (v2i32 (EXTRACT_SUBREG QPR:$src2, > - (DSubReg_i32_reg imm:$lane))), > + (DSubReg_i32_reg imm:$lane))), > (SubReg_i32_lane imm:$lane)))>; > > // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half > @@ -1797,41 +1817,53 @@ > IIC_VMULi16Q, IIC_VMULi32Q, > "vqrdmulh.s", int_arm_neon_vqrdmulh>; > def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1), > - (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), > + (v8i16 (NEONvduplane (v8i16 QPR:$src2), > + imm:$lane)))), > (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1), > (v4i16 (EXTRACT_SUBREG QPR:$src2, > (DSubReg_i16_reg imm:$lane))), > (SubReg_i16_lane imm:$lane)))>; > def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1), > - (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))), > + (v4i32 (NEONvduplane (v4i32 QPR:$src2), > + imm:$lane)))), > (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1), > (v2i32 (EXTRACT_SUBREG QPR:$src2, > - (DSubReg_i32_reg imm:$lane))), > + (DSubReg_i32_reg imm:$lane))), > (SubReg_i32_lane imm:$lane)))>; > > // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D) > -defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls, 1>; > -defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu, 1>; > -def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull.p8", v8i16, v8i8, > - int_arm_neon_vmullp, 1>; > -defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls>; > -defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu>; > +defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull.s", > + int_arm_neon_vmulls, 1>; > +defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull.u", > + int_arm_neon_vmullu, 1>; > +def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull.p8", > + v8i16, v8i8, int_arm_neon_vmullp, 1>; > +defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull.s", > + int_arm_neon_vmulls>; > +defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull.u", > + int_arm_neon_vmullu>; > > // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D) > -defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull, 1>; > -defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull>; > +defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull.s", > + int_arm_neon_vqdmull, 1>; > +defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull.s", > + int_arm_neon_vqdmull>; > > // Vector Multiply-Accumulate and Multiply-Subtract Operations. > > // VMLA : Vector Multiply Accumulate (integer and floating-point) > defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, > IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>; > -def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>; > -def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla.f32", v4f32, fmul, fadd>; > +def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", > + v2f32, fmul, fadd>; > +def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla.f32", > + v4f32, fmul, fadd>; > defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D, > IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>; > -def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>; > -def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla.f32", v4f32, v2f32, fmul, fadd>; > +def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla.f32", > + v2f32, fmul, fadd>; > +def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla.f32", > + v4f32, v2f32, fmul, fadd>; > > def : Pat<(v8i16 (add (v8i16 QPR:$src1), > (mul (v8i16 QPR:$src2), > @@ -1848,7 +1880,7 @@ > (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), > (v4i32 QPR:$src2), > (v2i32 (EXTRACT_SUBREG QPR:$src3, > - (DSubReg_i32_reg imm:$lane))), > + (DSubReg_i32_reg imm:$lane))), > (SubReg_i32_lane imm:$lane)))>; > > def : Pat<(v4f32 (fadd (v4f32 QPR:$src1), > @@ -1874,12 +1906,16 @@ > // VMLS : Vector Multiply Subtract (integer and floating-point) > defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, > IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>; > -def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>; > -def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls.f32", v4f32, fmul, fsub>; > +def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", > + v2f32, fmul, fsub>; > +def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls.f32", > + v4f32, fmul, fsub>; > defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D, > IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>; > -def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>; > -def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls.f32", v4f32, v2f32, fmul, fsub>; > +def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls.f32", > + v2f32, fmul, fsub>; > +def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls.f32", > + v4f32, v2f32, fmul, fsub>; > > def : Pat<(v8i16 (sub (v8i16 QPR:$src1), > (mul (v8i16 QPR:$src2), > @@ -1892,7 +1928,7 @@ > > def : Pat<(v4i32 (sub (v4i32 QPR:$src1), > (mul (v4i32 QPR:$src2), > - (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))), > + (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))), > (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), > (v4i32 QPR:$src2), > (v2i32 (EXTRACT_SUBREG QPR:$src3, > @@ -1901,7 +1937,7 @@ > > def : Pat<(v4f32 (fsub (v4f32 QPR:$src1), > (fmul (v4f32 QPR:$src2), > - (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))), > + (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))), > (v4f32 (VMLSslfq (v4f32 QPR:$src1), > (v4f32 QPR:$src2), > (v2f32 (EXTRACT_SUBREG QPR:$src3, > @@ -1922,25 +1958,34 @@ > // Vector Subtract Operations. > > // VSUB : Vector Subtract (integer and floating-point) > -defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, "vsub.i", sub, 0>; > -def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub.f32", v2f32, v2f32, fsub, 0>; > -def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub.f32", v4f32, v4f32, fsub, 0>; > +defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, > + "vsub.i", sub, 0>; > +def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub.f32", > + v2f32, v2f32, fsub, 0>; > +def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub.f32", > + v4f32, v4f32, fsub, 0>; > // VSUBL : Vector Subtract Long (Q = D - D) > -defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl.s", int_arm_neon_vsubls, 1>; > -defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl.u", int_arm_neon_vsublu, 1>; > +defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl.s", > + int_arm_neon_vsubls, 1>; > +defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl.u", > + int_arm_neon_vsublu, 1>; > // VSUBW : Vector Subtract Wide (Q = Q - D) > defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>; > defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>; > // VHSUB : Vector Halving Subtract > -defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, > - IIC_VBINi4Q, "vhsub.s", int_arm_neon_vhsubs, 0>; > -defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, > - IIC_VBINi4Q, "vhsub.u", int_arm_neon_vhsubu, 0>; > +defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, > + IIC_VBINi4Q, IIC_VBINi4Q, > + "vhsub.s", int_arm_neon_vhsubs, 0>; > +defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, > + IIC_VBINi4Q, IIC_VBINi4Q, > + "vhsub.u", int_arm_neon_vhsubu, 0>; > // VQSUB : Vector Saturing Subtract > -defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, > - IIC_VBINi4Q, "vqsub.s", int_arm_neon_vqsubs, 0>; > -defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, > - IIC_VBINi4Q, "vqsub.u", int_arm_neon_vqsubu, 0>; > +defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, > + IIC_VBINi4Q, IIC_VBINi4Q, > + "vqsub.s", int_arm_neon_vqsubs, 0>; > +defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, > + IIC_VBINi4Q, IIC_VBINi4Q, > + "vqsub.u", int_arm_neon_vqsubu, 0>; > // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q) > defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>; > // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q) > @@ -1951,32 +1996,38 @@ > // VCEQ : Vector Compare Equal > defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, > IIC_VBINi4Q, "vceq.i", NEONvceq, 1>; > -def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq.f32", v2i32, v2f32, NEONvceq, 1>; > -def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq.f32", v4i32, v4f32, NEONvceq, 1>; > +def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq.f32", v2i32, v2f32, > + NEONvceq, 1>; > +def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq.f32", v4i32, v4f32, > + NEONvceq, 1>; > // VCGE : Vector Compare Greater Than or Equal > defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, > IIC_VBINi4Q, "vcge.s", NEONvcge, 0>; > defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, > IIC_VBINi4Q, "vcge.u", NEONvcgeu, 0>; > -def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge.f32", v2i32, v2f32, NEONvcge, 0>; > -def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge.f32", v4i32, v4f32, NEONvcge, 0>; > +def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge.f32", > + v2i32, v2f32, NEONvcge, 0>; > +def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge.f32", v4i32, v4f32, > + NEONvcge, 0>; > // VCGT : Vector Compare Greater Than > defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, > IIC_VBINi4Q, "vcgt.s", NEONvcgt, 0>; > defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, > IIC_VBINi4Q, "vcgt.u", NEONvcgtu, 0>; > -def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>; > -def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>; > +def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt.f32", v2i32, v2f32, > + NEONvcgt, 0>; > +def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt.f32", v4i32, v4f32, > + NEONvcgt, 0>; > // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE) > -def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge.f32", v2i32, v2f32, > - int_arm_neon_vacged, 0>; > -def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge.f32", v4i32, v4f32, > - int_arm_neon_vacgeq, 0>; > +def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge.f32", > + v2i32, v2f32, int_arm_neon_vacged, 0>; > +def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge.f32", > + v4i32, v4f32, int_arm_neon_vacgeq, 0>; > // VACGT : Vector Absolute Compare Greater Than (aka VCAGT) > -def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt.f32", v2i32, v2f32, > - int_arm_neon_vacgtd, 0>; > -def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt.f32", v4i32, v4f32, > - int_arm_neon_vacgtq, 0>; > +def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt.f32", > + v2i32, v2f32, int_arm_neon_vacgtd, 0>; > +def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt.f32", > + v4i32, v4f32, int_arm_neon_vacgtq, 0>; > // VTST : Vector Test Bits > defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, > IIC_VBINi4Q, "vtst.i", NEONvtst, 1>; > @@ -1984,49 +2035,55 @@ > // Vector Bitwise Operations. > > // VAND : Vector Bitwise AND > -def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", v2i32, v2i32, and, 1>; > -def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", v4i32, v4i32, and, 1>; > +def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", > + v2i32, v2i32, and, 1>; > +def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", > + v4i32, v4i32, and, 1>; > > // VEOR : Vector Bitwise Exclusive OR > -def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", v2i32, v2i32, xor, 1>; > -def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", v4i32, v4i32, xor, 1>; > +def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", > + v2i32, v2i32, xor, 1>; > +def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", > + v4i32, v4i32, xor, 1>; > > // VORR : Vector Bitwise OR > -def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", v2i32, v2i32, or, 1>; > -def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", v4i32, v4i32, or, 1>; > +def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", > + v2i32, v2i32, or, 1>; > +def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", > + v4i32, v4i32, or, 1>; > > // VBIC : Vector Bitwise Bit Clear (AND NOT) > def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), > (ins DPR:$src1, DPR:$src2), IIC_VBINiD, > - "vbic\t$dst, $src1, $src2", "", > + "vbic", "\t$dst, $src1, $src2", "", > [(set DPR:$dst, (v2i32 (and DPR:$src1, > (vnot_conv DPR:$src2))))]>; > def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), > (ins QPR:$src1, QPR:$src2), IIC_VBINiQ, > - "vbic\t$dst, $src1, $src2", "", > + "vbic", "\t$dst, $src1, $src2", "", > [(set QPR:$dst, (v4i32 (and QPR:$src1, > (vnot_conv QPR:$src2))))]>; > > // VORN : Vector Bitwise OR NOT > def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst), > (ins DPR:$src1, DPR:$src2), IIC_VBINiD, > - "vorn\t$dst, $src1, $src2", "", > + "vorn", "\t$dst, $src1, $src2", "", > [(set DPR:$dst, (v2i32 (or DPR:$src1, > (vnot_conv DPR:$src2))))]>; > def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst), > (ins QPR:$src1, QPR:$src2), IIC_VBINiQ, > - "vorn\t$dst, $src1, $src2", "", > + "vorn", "\t$dst, $src1, $src2", "", > [(set QPR:$dst, (v4i32 (or QPR:$src1, > (vnot_conv QPR:$src2))))]>; > > // VMVN : Vector Bitwise NOT > def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0, > (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD, > - "vmvn\t$dst, $src", "", > + "vmvn", "\t$dst, $src", "", > [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>; > def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0, > (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD, > - "vmvn\t$dst, $src", "", > + "vmvn", "\t$dst, $src", "", > [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>; > def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>; > def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>; > @@ -2034,13 +2091,13 @@ > // VBSL : Vector Bitwise Select > def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), > (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD, > - "vbsl\t$dst, $src2, $src3", "$src1 = $dst", > + "vbsl", "\t$dst, $src2, $src3", "$src1 = $dst", > [(set DPR:$dst, > (v2i32 (or (and DPR:$src2, DPR:$src1), > (and DPR:$src3, (vnot_conv DPR:$src1)))))]>; > def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), > (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ, > - "vbsl\t$dst, $src2, $src3", "$src1 = $dst", > + "vbsl", "\t$dst, $src2, $src3", "$src1 = $dst", > [(set QPR:$dst, > (v4i32 (or (and QPR:$src2, QPR:$src1), > (and QPR:$src3, (vnot_conv QPR:$src1)))))]>; > @@ -2056,18 +2113,22 @@ > // Vector Absolute Differences. > > // VABD : Vector Absolute Difference > -defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, > - IIC_VBINi4Q, "vabd.s", int_arm_neon_vabds, 0>; > -defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, > - IIC_VBINi4Q, "vabd.u", int_arm_neon_vabdu, 0>; > -def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND, "vabd.f32", v2f32, v2f32, > - int_arm_neon_vabds, 0>; > -def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vabd.f32", v4f32, v4f32, > - int_arm_neon_vabds, 0>; > +defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, > + IIC_VBINi4Q, IIC_VBINi4Q, > + "vabd.s", int_arm_neon_vabds, 0>; > +defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, > + IIC_VBINi4Q, IIC_VBINi4Q, > + "vabd.u", int_arm_neon_vabdu, 0>; > +def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND, > + "vabd.f32", v2f32, v2f32, int_arm_neon_vabds, 0>; > +def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ, > + "vabd.f32", v4f32, v4f32, int_arm_neon_vabds, 0>; > > // VABDL : Vector Absolute Difference Long (Q = | D - D |) > -defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q, "vabdl.s", int_arm_neon_vabdls, 0>; > -defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q, "vabdl.u", int_arm_neon_vabdlu, 0>; > +defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q, > + "vabdl.s", int_arm_neon_vabdls, 0>; > +defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q, > + "vabdl.u", int_arm_neon_vabdlu, 0>; > > // VABA : Vector Absolute Difference and Accumulate > defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba.s", int_arm_neon_vabas>; > @@ -2318,11 +2379,11 @@ > > class VNEGD size, string OpcodeStr, ValueType Ty> > : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src), > - IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "", > + IIC_VSHLiD, OpcodeStr, "\t$dst, $src", "", > [(set DPR:$dst, (Ty (vneg DPR:$src)))]>; > class VNEGQ size, string OpcodeStr, ValueType Ty> > : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src), > - IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "", > + IIC_VSHLiD, OpcodeStr, "\t$dst, $src", "", > [(set QPR:$dst, (Ty (vneg QPR:$src)))]>; > > // VNEG : Vector Negate > @@ -2336,11 +2397,11 @@ > // VNEG : Vector Negate (floating-point) > def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0, > (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD, > - "vneg.f32\t$dst, $src", "", > + "vneg.f32", "\t$dst, $src", "", > [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>; > def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0, > (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ, > - "vneg.f32\t$dst, $src", "", > + "vneg.f32", "\t$dst, $src", "", > [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>; > > def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>; > @@ -2378,9 +2439,9 @@ > // VMOV : Vector Move (Register) > > def VMOVDneon: N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src), > - IIC_VMOVD, "vmov\t$dst, $src", "", []>; > + IIC_VMOVD, "vmov", "\t$dst, $src", "", []>; > def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src), > - IIC_VMOVD, "vmov\t$dst, $src", "", []>; > + IIC_VMOVD, "vmov", "\t$dst, $src", "", []>; > > // VMOV : Vector Move (Immediate) > > @@ -2421,38 +2482,38 @@ > > def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst), > (ins h8imm:$SIMM), IIC_VMOVImm, > - "vmov.i8\t$dst, $SIMM", "", > + "vmov.i8", "\t$dst, $SIMM", "", > [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>; > def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst), > (ins h8imm:$SIMM), IIC_VMOVImm, > - "vmov.i8\t$dst, $SIMM", "", > + "vmov.i8", "\t$dst, $SIMM", "", > [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>; > > def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst), > (ins h16imm:$SIMM), IIC_VMOVImm, > - "vmov.i16\t$dst, $SIMM", "", > + "vmov.i16", "\t$dst, $SIMM", "", > [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>; > def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst), > (ins h16imm:$SIMM), IIC_VMOVImm, > - "vmov.i16\t$dst, $SIMM", "", > + "vmov.i16", "\t$dst, $SIMM", "", > [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>; > > def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst), > (ins h32imm:$SIMM), IIC_VMOVImm, > - "vmov.i32\t$dst, $SIMM", "", > + "vmov.i32", "\t$dst, $SIMM", "", > [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>; > def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst), > (ins h32imm:$SIMM), IIC_VMOVImm, > - "vmov.i32\t$dst, $SIMM", "", > + "vmov.i32", "\t$dst, $SIMM", "", > [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>; > > def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst), > (ins h64imm:$SIMM), IIC_VMOVImm, > - "vmov.i64\t$dst, $SIMM", "", > + "vmov.i64", "\t$dst, $SIMM", "", > [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>; > def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst), > (ins h64imm:$SIMM), IIC_VMOVImm, > - "vmov.i64\t$dst, $SIMM", "", > + "vmov.i64", "\t$dst, $SIMM", "", > [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>; > > // VMOV : Vector Get Lane (move scalar to ARM core register) > @@ -2624,13 +2685,13 @@ > class VDUPLND > : N2VDup<0b11, 0b11, 0b11000, 0, 0, > (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD, > - !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", > + OpcodeStr, "\t$dst, $src[$lane]", "", > [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>; > > class VDUPLNQ > : N2VDup<0b11, 0b11, 0b11000, 1, 0, > (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD, > - !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", > + OpcodeStr, "\t$dst, $src[$lane]", "", > [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>; > > // Inst{19-16} is partially specified depending on the element size. > @@ -2663,14 +2724,14 @@ > > def VDUPfdf : N2VDup<0b11, 0b11, 0b11000, 0, 0, > (outs DPR:$dst), (ins SPR:$src), > - IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "", > + IIC_VMOVD, "vdup.32", "\t$dst, ${src:lane}", "", > [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]> { > let Inst{18-16} = 0b100; > } > > def VDUPfqf : N2VDup<0b11, 0b11, 0b11000, 1, 0, > (outs QPR:$dst), (ins SPR:$src), > - IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "", > + IIC_VMOVD, "vdup.32", "\t$dst, ${src:lane}", "", > [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]> { > let Inst{18-16} = 0b100; > } > @@ -2745,12 +2806,12 @@ > class VREV64D op19_18, string OpcodeStr, ValueType Ty> > : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst), > (ins DPR:$src), IIC_VMOVD, > - !strconcat(OpcodeStr, "\t$dst, $src"), "", > + OpcodeStr, "\t$dst, $src", "", > [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>; > class VREV64Q op19_18, string OpcodeStr, ValueType Ty> > : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst), > (ins QPR:$src), IIC_VMOVD, > - !strconcat(OpcodeStr, "\t$dst, $src"), "", > + OpcodeStr, "\t$dst, $src", "", > [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>; > > def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>; > @@ -2768,12 +2829,12 @@ > class VREV32D op19_18, string OpcodeStr, ValueType Ty> > : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst), > (ins DPR:$src), IIC_VMOVD, > - !strconcat(OpcodeStr, "\t$dst, $src"), "", > + OpcodeStr, "\t$dst, $src", "", > [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>; > class VREV32Q op19_18, string OpcodeStr, ValueType Ty> > : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst), > (ins QPR:$src), IIC_VMOVD, > - !strconcat(OpcodeStr, "\t$dst, $src"), "", > + OpcodeStr, "\t$dst, $src", "", > [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>; > > def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>; > @@ -2787,12 +2848,12 @@ > class VREV16D op19_18, string OpcodeStr, ValueType Ty> > : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst), > (ins DPR:$src), IIC_VMOVD, > - !strconcat(OpcodeStr, "\t$dst, $src"), "", > + OpcodeStr, "\t$dst, $src", "", > [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>; > class VREV16Q op19_18, string OpcodeStr, ValueType Ty> > : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst), > (ins QPR:$src), IIC_VMOVD, > - !strconcat(OpcodeStr, "\t$dst, $src"), "", > + OpcodeStr, "\t$dst, $src", "", > [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>; > > def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>; > @@ -2805,14 +2866,14 @@ > class VEXTd > : N3VImm<0,1,0b11,0,0, (outs DPR:$dst), > (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD, > - !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "", > + OpcodeStr, "\t$dst, $lhs, $rhs, $index", "", > [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs), > (Ty DPR:$rhs), imm:$index)))]>; > > class VEXTq > : N3VImm<0,1,0b11,1,0, (outs QPR:$dst), > (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ, > - !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "", > + OpcodeStr, "\t$dst, $lhs, $rhs, $index", "", > [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs), > (Ty QPR:$rhs), imm:$index)))]>; > > @@ -2862,25 +2923,25 @@ > def VTBL1 > : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst), > (ins DPR:$tbl1, DPR:$src), IIC_VTB1, > - "vtbl.8\t$dst, \\{$tbl1\\}, $src", "", > + "vtbl.8", "\t$dst, \\{$tbl1\\}, $src", "", > [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>; > let hasExtraSrcRegAllocReq = 1 in { > def VTBL2 > : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst), > (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2, > - "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "", > + "vtbl.8", "\t$dst, \\{$tbl1,$tbl2\\}, $src", "", > [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2 > DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>; > def VTBL3 > : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst), > (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3, > - "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "", > + "vtbl.8", "\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "", > [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3 > DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>; > def VTBL4 > : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst), > (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4, > - "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "", > + "vtbl.8", "\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "", > [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2, > DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>; > } // hasExtraSrcRegAllocReq = 1 > @@ -2889,26 +2950,26 @@ > def VTBX1 > : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst), > (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1, > - "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst", > + "vtbx.8", "\t$dst, \\{$tbl1\\}, $src", "$orig = $dst", > [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1 > DPR:$orig, DPR:$tbl1, DPR:$src)))]>; > let hasExtraSrcRegAllocReq = 1 in { > def VTBX2 > : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst), > (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2, > - "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst", > + "vtbx.8", "\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst", > [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2 > DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>; > def VTBX3 > : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst), > (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3, > - "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst", > + "vtbx.8", "\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst", > [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1, > DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>; > def VTBX4 > : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1, > DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4, > - "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst", > + "vtbx.8", "\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst", > [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1, > DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>; > } // hasExtraSrcRegAllocReq = 1 > @@ -2958,7 +3019,7 @@ > let neverHasSideEffects = 1 in > def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0, > (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD, > - "vneg.f32\t$dst, $src", "", []>; > + "vneg.f32", "\t$dst, $src", "", []>; > def : N2VDIntsPat; > > // Vector Convert between single-precision FP and integer > > Modified: llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp?rev=89542&r1=89541&r2=89542&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp (original) > +++ llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp Sat Nov 21 00:21:52 2009 > @@ -81,8 +81,8 @@ > // afterwards > // - The imp-defs / imp-uses are superregs only, we don't care about > // them. > - BuildMI(MBB, *MI, MI->getDebugLoc(), > - TII->get(ARM::VMOVDneon), DestReg).addReg(SrcReg); > + AddDefaultPred(BuildMI(MBB, *MI, MI->getDebugLoc(), > + TII->get(ARM::VMOVDneon), DestReg).addReg(SrcReg)); > MBB.erase(MI); > MachineBasicBlock::iterator I = prior(NextMII); > MI = &*I; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Sat Nov 21 01:56:01 2009 From: baldrick at free.fr (Duncan Sands) Date: Sat, 21 Nov 2009 08:56:01 +0100 Subject: [llvm-commits] [llvm] r89521 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/PowerPC/vec_buildvector_loadstore.ll In-Reply-To: <200911210053.nAL0rNaV029570@zion.cs.uiuc.edu> References: <200911210053.nAL0rNaV029570@zion.cs.uiuc.edu> Message-ID: <4B079D11.70503@free.fr> Hi Dale, > + // If EltVT smaller than OpVT, only store the bits necessary. > + if (EltVT.bitsLT(OpVT)) > + Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, > + Node->getOperand(i), Idx, SV, Offset, EltVT)); > + else > + Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, > + Node->getOperand(i), Idx, SV, Offset)); there is no need for the test, you can always use getTruncStore. If the store is not actually truncating it is automagically turned into an ordinary store. Ciao, Duncan. From baldrick at free.fr Sat Nov 21 01:58:57 2009 From: baldrick at free.fr (Duncan Sands) Date: Sat, 21 Nov 2009 08:58:57 +0100 Subject: [llvm-commits] [llvm] r89523 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: <200911210101.nAL11UDE029891@zion.cs.uiuc.edu> References: <200911210101.nAL11UDE029891@zion.cs.uiuc.edu> Message-ID: <4B079DC1.3080005@free.fr> Hi Eric, > + Optimizations["llvm.objectsize.i32"] = &ObjectSize; > + Optimizations["llvm.objectsize.i64"] = &ObjectSize; these are not libcalls, they are llvm intrinsics. Why not just simplify them in instcombine? Ciao, Duncan. From baldrick at free.fr Sat Nov 21 02:00:15 2009 From: baldrick at free.fr (Duncan Sands) Date: Sat, 21 Nov 2009 09:00:15 +0100 Subject: [llvm-commits] [llvm] r89523 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: <200911210101.nAL11UDE029891@zion.cs.uiuc.edu> References: <200911210101.nAL11UDE029891@zion.cs.uiuc.edu> Message-ID: <4B079E0F.9090808@free.fr> > +struct SizeOpt : public LibCallOptimization { > + virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) { > + // TODO: We can do more with this, but delaying to here should be no change > + // in behavior. > + ConstantInt *Const = dyn_cast(CI->getOperand(2)); > + > + if (!Const) return 0; PS: do you need to check the prototype here, or is it guaranteed to be correct since this is an intrinsic? Ciao, D. From baldrick at free.fr Sat Nov 21 03:52:13 2009 From: baldrick at free.fr (Duncan Sands) Date: Sat, 21 Nov 2009 09:52:13 -0000 Subject: [llvm-commits] [dragonegg] r89559 - /dragonegg/trunk/llvm-backend.cpp Message-ID: <200911210952.nAL9qDar027929@zion.cs.uiuc.edu> Author: baldrick Date: Sat Nov 21 03:52:13 2009 New Revision: 89559 URL: http://llvm.org/viewvc/llvm-project?rev=89559&view=rev Log: Add assertions checking that globals we output have the same size as the corresponding gcc declaration. I'm pretty sure we get this wrong from time to time, when DECL_SIZE differs from the type size. These asserts are there to find examples of this. Modified: dragonegg/trunk/llvm-backend.cpp Modified: dragonegg/trunk/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-backend.cpp?rev=89559&r1=89558&r2=89559&view=diff ============================================================================== --- dragonegg/trunk/llvm-backend.cpp (original) +++ dragonegg/trunk/llvm-backend.cpp Sat Nov 21 03:52:13 2009 @@ -272,6 +272,18 @@ return 200; } +// SizeOfGlobalMatchesDecl - Whether the size of the given global value +// is the same as that of the given GCC declaration. +static bool SizeOfGlobalMatchesDecl(GlobalValue *GV, tree decl) { + const Type *Ty = GV->getType()->getElementType(); + if (!DECL_SIZE(decl) || !Ty->isSized()) + return true; + if (!isInt64(DECL_SIZE(decl), true)) + return false; + return TheTarget->getTargetData()->getTypeAllocSizeInBits(Ty) == + getInt64(DECL_SIZE(decl), true); +} + #ifndef LLVM_TARGET_NAME #error LLVM_TARGET_NAME macro not specified #endif @@ -1049,6 +1061,7 @@ GV->isConstant(), GV->getLinkage(), 0, GV->getName()); + assert(SizeOfGlobalMatchesDecl(NGV, decl) && "Global has wrong size!"); NGV->setVisibility(GV->getVisibility()); NGV->setSection(GV->getSection()); NGV->setAlignment(GV->getAlignment()); @@ -1126,6 +1139,7 @@ GV->isConstant(), GlobalValue::ExternalLinkage, 0, GV->getName()); + assert(SizeOfGlobalMatchesDecl(NGV, decl) && "Global has wrong size!"); GV->replaceAllUsesWith(TheFolder->CreateBitCast(NGV, GV->getType())); changeLLVMConstant(GV, NGV); delete GV; @@ -1494,6 +1508,7 @@ if (TREE_CODE(decl) == VAR_DECL && DECL_THREAD_LOCAL_P(decl)) GV->setThreadLocal(true); + assert(SizeOfGlobalMatchesDecl(GV, decl) && "Global has wrong size!"); return SET_DECL_LLVM(decl, GV); } //TODO timevar_pop(TV_LLVM_GLOBALS); From sabre at nondot.org Sat Nov 21 08:41:20 2009 From: sabre at nondot.org (Chris Lattner) Date: Sat, 21 Nov 2009 06:41:20 -0800 Subject: [llvm-commits] [llvm] r89434 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp In-Reply-To: <4B06DA42.9000305@free.fr> References: <200911200134.nAK1Y38v027923@zion.cs.uiuc.edu> <4B067B5C.4000308@free.fr> <4B06DA42.9000305@free.fr> Message-ID: <931DCC42-C5FF-4105-A89B-60573C76403C@nondot.org> On Nov 20, 2009, at 10:04 AM, Duncan Sands wrote: > Hi Dan, > >> Hi Duncan, thanks for pointing these out. I removed the same-object rule, >> which wasn't essential to my original testcase, and refined the null >> comparison rule to only apply to noalias return values, which is still >> sufficient for the original testcase. > > sorry for annoying you with all these crazy examples! Personally I would > be happy with a notion of pointer capture based on alias analysis (i.e. > a pointer escapes if there is some other pointer which might alias it), > with rules saying that dissecting pointers and reconstructing them from > the pieces "doesn't count", i.e. you are allowed to say that the new one > doesn't alias the original, and thus that the original was not captured. > But Chris rejected this - perhaps we should gang up on him? :) The only case I'm really concerned about are things like PointerIntPair that bitmangle things into the low bits of pointers. -Chris From sabre at nondot.org Sat Nov 21 08:49:02 2009 From: sabre at nondot.org (Chris Lattner) Date: Sat, 21 Nov 2009 06:49:02 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: <4F246C8B-FDED-4DDA-95F1-DE2D11F216CB@apple.com> References: <701493E3-E27B-4EAB-9666-99B2F6EA01BC@apple.com> <4F246C8B-FDED-4DDA-95F1-DE2D11F216CB@apple.com> Message-ID: <84E8057C-E9D9-443F-9CC1-549BFC1DE82C@nondot.org> On Nov 19, 2009, at 10:52 PM, Bob Wilson wrote: > On Nov 19, 2009, at 10:28 PM, Chris Lattner wrote: >> >> I don't really buy this. Are you really claiming that duplicating a 10K instruction basic block is worth it? In reality there has to be a balance, even for ARM. This is also likely to be a huge win for X86 but this is just like jump threading: while eliminating correlated branches is *always* a win from the dynamic instruction count perspective, we balance the benefit with the code size cost. I don't see how this case is any different. > > The size of the block is definitely limited -- the whole point of the target hook is to adjust that limit. The aspect that we don't limit is the number of predecessors where we may duplicate that block. Right ... so there is no limit to the amount duplicated... >> In practice, must jump table indirect gotos are preceded by a conditional branch that checks the "range" of the table anyway, so it won't matter. However, if that weren't the case, this optimization would be just as useful for switches as indbr's. Ideally the same code *should* apply to both. > > Not necessarily. Our implementation of indirect branches artificially combines all the indirect branches in a function into a single branch. That has a very bad effect on branch prediction. The main reason we need to do this aggressive tail duplication for indirect branches is to essentially undo that transformation. I don't see how that is related. I'm not debating that this is important for indbr's. :) I'm saying that it is just as important for switches in the uncommon case when they are structurally the same. I'm arguing here that code structure is what matters, not the target ISA. >>>> Using the extant isIndirectBranch flag would be best, but even adding this sort of target hook would be somewhat ok. At least this would be a property of the architecture. If we can avoid it, I'd definitely prefer to of course. >>> >>> The isIndirectBranch flag would not allow us to distinguish jump table branches. >> >> I don't think we want to :). Why do we want to? > > Indirect branches (i.e., "computed gotos", not jump tables) are most often used for interpreters. Uh, switches are commonly used by interpreters also. The portable kind of interpreter :) > Besides the "undo the front end's factoring of the CFG" motivation for treating indirect branches specially, there is more to it than that. It is quite common for an interpreter to see common patterns in the operations it handles. (This is especially true for certain benchmarks we care about.) This is also very true of switch statements! > The typical interpreter loop has a chunk of code to handle each operation, ending with an indirect branch to go to the next operation. When there are patterns in the order of interpreted operations, those indirect branches become predictable -- but only if they are duplicated into the separate chunks of code for each operation. Again, I don't see how this is any different for a switch in a loop vs an indirectbr in a loop. > Applying this intuition to the code size question above, if an interpreter loop handles 1000 different operations, we would still want to duplicate the indirect branches into every one of those 1000 chunks of code, as long as the code being duplicated is "small enough". (I am thinking here of processors that can predict those branches and where the branch misprediction penalty is significant. You would want to make a different tradeoff for a processor with no branch prediction.) No, I don't see it this way. What you're saying is that it is "worth it" to pay a code size cost to get a performance win in this case, because the win is high. I am not debating this at all! This is a completely acceptable tradeoff, I just want it factored the right way. I'd be very happy if the code in taildupe said "if the block ends in an indirect goto operation, and if "it is profitable to dupliate indirect gotos for the target" then increase the threshold a bit. I don't like asking the target how much to increase the threshold. "How much to increase the threshold" is not asking a target property. Asking "is it profitable to duplicate indirect gotos" is. >> And why is +2 the "right" amount? Because it happens to be enough to get one particular testcase that you care about, or because of some fundamental property of the architecture? > > It is for the same reason that -tail-merge-size defaults to "3". ;-) > > The default limit for tail duplication is "tail-merge-size" - 1. That is also completely arbitrary. We pick values that work well for the code we have measured and that we care about. There's nothing fundamental about them. Right. So now instead of having one arbitrary place (in the tail dupe code) to change in the future, we have that one, plus one per target! -Chris From clattner at apple.com Sat Nov 21 09:18:11 2009 From: clattner at apple.com (Chris Lattner) Date: Sat, 21 Nov 2009 07:18:11 -0800 Subject: [llvm-commits] [llvm] r89487 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp In-Reply-To: <200911202105.nAKL5bJe020587@zion.cs.uiuc.edu> References: <200911202105.nAKL5bJe020587@zion.cs.uiuc.edu> Message-ID: <56E0813A-560E-4810-9B9F-457E0853AB17@apple.com> On Nov 20, 2009, at 1:05 PM, Devang Patel wrote: > Author: dpatel > Date: Fri Nov 20 15:05:37 2009 > New Revision: 89487 > > URL: http://llvm.org/viewvc/llvm-project?rev=89487&view=rev > Log: > There is no need to emit source location info for DW_TAG_pointer_type. This seems like a strange special case. Why are pointers special here? -Chris > > Modified: > llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=89487&r1=89486&r2=89487&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri Nov 20 15:05:37 2009 > @@ -929,7 +929,7 @@ > AddUInt(&Buffer, dwarf::DW_AT_byte_size, 0, Size); > > // Add source line info if available and TyDesc is not a forward declaration. > - if (!DTy.isForwardDecl()) > + if (!DTy.isForwardDecl() && Tag != dwarf::DW_TAG_pointer_type) > AddSourceLine(&Buffer, &DTy); > } > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Sat Nov 21 09:20:22 2009 From: clattner at apple.com (Chris Lattner) Date: Sat, 21 Nov 2009 07:20:22 -0800 Subject: [llvm-commits] [llvm] r89434 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp In-Reply-To: <4B067B5C.4000308@free.fr> References: <200911200134.nAK1Y38v027923@zion.cs.uiuc.edu> <4B067B5C.4000308@free.fr> Message-ID: <8D3D5932-9CE2-47D7-A3EA-77FAF058B7A6@apple.com> On Nov 20, 2009, at 3:19 AM, Duncan Sands wrote: > Hi Dan, > >> + // Don't count comparisons of two pointers within the same object >> + // as captures. >> + if (I->getOperand(0)->getUnderlyingObject() == >> + I->getOperand(1)->getUnderlyingObject()) > > I think this bit is ok if you only do equality/inequality comparisons, but > is wrong if you allow inequality comparisons. The reason is that this Isn't this safe with an inbounds gep? -Chris > > Q = GEP P, -n > if (Q == null) > break; > > (see example from previous email) is equivalent to this > > Q = GEP P, -(n+1) > if (Q > P) > break; > > and here you are comparing pointers with the same underlying object. > > Ciao, > > Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Sat Nov 21 09:21:49 2009 From: clattner at apple.com (Chris Lattner) Date: Sat, 21 Nov 2009 07:21:49 -0800 Subject: [llvm-commits] [llvm] r89421 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp In-Reply-To: <4B068327.1070103@free.fr> References: <200911200050.nAK0or7J026222@zion.cs.uiuc.edu> <4B068327.1070103@free.fr> Message-ID: <784C47FB-FB86-404E-B39F-8EAF9C4A98E0@apple.com> On Nov 20, 2009, at 3:53 AM, Duncan Sands wrote: > Hi Dan, > >> + // Don't count comparisons of the original value against null as captures. >> + // This allows us to ignore comparisons of malloc results with null, >> + // for example. >> + if (isIdentifiedObject(V)) >> + if (ConstantPointerNull *CPN = >> + dyn_cast(I->getOperand(1))) >> + if (CPN->getType()->getAddressSpace() == 0) >> + break; > > I think this is wrong, consider the following pseudocode example: While this example is "possible" I really don't think this is worth worrying about. It is not valid C code, is not likely to exist in practice, etc. Beyond that, comparison against null is really common and we really do want "nocapture" in this cases. -Chris > > i1 equals_null (i8* %P noalias) { > return %P == 0 > } > > Thanks to your change, this function will be marked nocapture, because > a noalias parameter counts as an identified object. > > Now consider > > i8* @capture (i8* %P noalias) { > n = 0 > loop: > %Q = GEP %P, -n > if (equals_null(%Q)) > break; > n = n + 1; > goto loop; > return GEP null, n > } > > I think it is correct to pass %Q to equals_null given that %P is noalias. > So this example shows that %P can be captured even though CaptureTracking > says it is not with your change. A variant of this is to have %P be some > noalias value like the return value of malloc. > > Ciao, > > Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Sat Nov 21 09:47:29 2009 From: baldrick at free.fr (Duncan Sands) Date: Sat, 21 Nov 2009 16:47:29 +0100 Subject: [llvm-commits] [llvm] r89434 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp In-Reply-To: <8D3D5932-9CE2-47D7-A3EA-77FAF058B7A6@apple.com> References: <200911200134.nAK1Y38v027923@zion.cs.uiuc.edu> <4B067B5C.4000308@free.fr> <8D3D5932-9CE2-47D7-A3EA-77FAF058B7A6@apple.com> Message-ID: <4B080B91.9070200@free.fr> Hi Chris, >>> + // Don't count comparisons of two pointers within the same object >>> + // as captures. >>> + if (I->getOperand(0)->getUnderlyingObject() == >>> + I->getOperand(1)->getUnderlyingObject()) >> I think this bit is ok if you only do equality/inequality comparisons, but >> is wrong if you allow inequality comparisons. The reason is that this > > Isn't this safe with an inbounds gep? I think it is safe. That said, instcombine would doubtless have simplified such comparisons into comparisons on the GEP indices anyway, so allowing this case probably doesn't buy you anything. Ciao, Duncan. From baldrick at free.fr Sat Nov 21 09:53:19 2009 From: baldrick at free.fr (Duncan Sands) Date: Sat, 21 Nov 2009 16:53:19 +0100 Subject: [llvm-commits] [llvm] r89421 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp In-Reply-To: <784C47FB-FB86-404E-B39F-8EAF9C4A98E0@apple.com> References: <200911200050.nAK0or7J026222@zion.cs.uiuc.edu> <4B068327.1070103@free.fr> <784C47FB-FB86-404E-B39F-8EAF9C4A98E0@apple.com> Message-ID: <4B080CEF.5060301@free.fr> Hi Chris, >> I think this is wrong, consider the following pseudocode example: > > While this example is "possible" I really don't think this is worth worrying about. It is not valid C code, is not likely to exist in practice, etc. Beyond that, comparison against null is really common and we really do want "nocapture" in this cases. well, it's a slippery slope :) Dan later changed this to only allow comparisons against malloc return values and other noalias function results. Ciao, Duncan. From echristo at apple.com Sat Nov 21 13:32:32 2009 From: echristo at apple.com (Eric Christopher) Date: Sat, 21 Nov 2009 11:32:32 -0800 Subject: [llvm-commits] [llvm] r89523 - /llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp In-Reply-To: <4B079DC1.3080005@free.fr> References: <200911210101.nAL11UDE029891@zion.cs.uiuc.edu> <4B079DC1.3080005@free.fr> Message-ID: <8F1B903A-E349-4307-881B-603B267EE70C@apple.com> On Nov 20, 2009, at 11:58 PM, Duncan Sands wrote: > Hi Eric, > >> + Optimizations["llvm.objectsize.i32"] = &ObjectSize; >> + Optimizations["llvm.objectsize.i64"] = &ObjectSize; > > these are not libcalls, they are llvm intrinsics. Why not just > simplify them in instcombine? I'm not sure, ultimately, how it's going to come out and right now this keeps it all in one area. (i.e. I'm not sure if object size is going to be its own pass or whether instcombine is fine, or...) > PS: do you need to check the prototype here, or is it guaranteed to be correct > since this is an intrinsic? Guaranteed since it is an intrinsic afaik. -eric From bob.wilson at apple.com Sat Nov 21 15:01:59 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Sat, 21 Nov 2009 13:01:59 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: <84E8057C-E9D9-443F-9CC1-549BFC1DE82C@nondot.org> References: <701493E3-E27B-4EAB-9666-99B2F6EA01BC@apple.com> <4F246C8B-FDED-4DDA-95F1-DE2D11F216CB@apple.com> <84E8057C-E9D9-443F-9CC1-549BFC1DE82C@nondot.org> Message-ID: <32E102EC-EC9F-4956-9B11-3D55E67481CE@apple.com> On Nov 21, 2009, at 6:49 AM, Chris Lattner wrote: > > This is a completely acceptable tradeoff, I just want it factored the right way. I'd be very happy if the code in taildupe said "if the block ends in an indirect goto operation, and if "it is profitable to dupliate indirect gotos for the target" then increase the threshold a bit. I don't like asking the target how much to increase the threshold. "How much to increase the threshold" is not asking a target property. Asking "is it profitable to duplicate indirect gotos" is. Factoring it in the way you suggest sounds good to me. I will do that. I see your point about switches being used for interpreters. I wasn't trying to say otherwise. I'm just not sure that this transformation will be a win for switches in general, and switches are used for lots of things besides interpreters. My experience with indirect branches is that they're used much less frequently and interpreters are the most common use. I was trying to reduce the risk of breaking something by limiting this change to the one specific case that I know about. I'm not sure we've really solved this problem yet, anyway. The current solution seems to be very sensitive to minor changes in the code. We run tail merging very late, so small differences in register allocation, scheduling, etc. will change what tail merging does. If tail merging is very successful, then tail duplication has to be very aggressive to get the result we need. For example, if tail merging creates a new block with a common tail of a dozen instructions, and that block is a predecessor of the indirect branch block, it is no problem to tail duplicate the indirect branch into the common tail, but what we really need is to get the new "common tail + indirect branch" duplicated back one more level. It won't help to tell tail merging not to merge blocks ending with indirect branches, because the indirect branch is in a separate block when we run tail merging. I suppose we could disable tail merging entirely at -O3, but I'm still trying to better understand the situation before proposing anything like that. From grosbach at apple.com Sat Nov 21 15:40:09 2009 From: grosbach at apple.com (Jim Grosbach) Date: Sat, 21 Nov 2009 21:40:09 -0000 Subject: [llvm-commits] [llvm] r89562 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp test/CodeGen/ARM/hello.ll test/CodeGen/ARM/ifcvt5.ll test/CodeGen/ARM/insn-sched1.ll test/CodeGen/Thumb2/thumb2-ifcvt1.ll test/CodeGen/Thumb2/thumb2-ifcvt2.ll Message-ID: <200911212140.nALLe9PL020242@zion.cs.uiuc.edu> Author: grosbach Date: Sat Nov 21 15:40:08 2009 New Revision: 89562 URL: http://llvm.org/viewvc/llvm-project?rev=89562&view=rev Log: Darwin requires a frame pointer for all non-leaf functions to support correct backtraces. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/test/CodeGen/ARM/hello.ll llvm/trunk/test/CodeGen/ARM/ifcvt5.ll llvm/trunk/test/CodeGen/ARM/insn-sched1.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=89562&r1=89561&r2=89562&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Sat Nov 21 15:40:08 2009 @@ -222,6 +222,7 @@ BitVector Reserved(getNumRegs()); Reserved.set(ARM::SP); Reserved.set(ARM::PC); + // FP is reserved on Darwin even if we're not using it in this function. if (STI.isTargetDarwin() || hasFP(MF)) Reserved.set(FramePtr); // Some targets reserve R9. @@ -239,6 +240,7 @@ return true; case ARM::R7: case ARM::R11: + // FP is reserved on Darwin even if we're not using it in this function. if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) return true; break; @@ -492,7 +494,8 @@ /// bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); - return (NoFramePointerElim || + return ((STI.isTargetDarwin() && MFI->hasCalls()) || + NoFramePointerElim || needsStackRealignment(MF) || MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()); Modified: llvm/trunk/test/CodeGen/ARM/hello.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/hello.ll?rev=89562&r1=89561&r2=89562&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/hello.ll (original) +++ llvm/trunk/test/CodeGen/ARM/hello.ll Sat Nov 21 15:40:08 2009 @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | count 1 ; RUN: llc < %s -mtriple=arm-linux-gnu --disable-fp-elim | \ ; RUN: grep mov | count 3 -; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 2 +; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 3 @str = internal constant [12 x i8] c"Hello World\00" Modified: llvm/trunk/test/CodeGen/ARM/ifcvt5.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt5.ll?rev=89562&r1=89561&r2=89562&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ifcvt5.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ifcvt5.ll Sat Nov 21 15:40:08 2009 @@ -1,5 +1,7 @@ ; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s +; XFAIL: * + @x = external global i32* ; [#uses=1] define void @foo(i32 %a) { Modified: llvm/trunk/test/CodeGen/ARM/insn-sched1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/insn-sched1.ll?rev=89562&r1=89561&r2=89562&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/insn-sched1.ll (original) +++ llvm/trunk/test/CodeGen/ARM/insn-sched1.ll Sat Nov 21 15:40:08 2009 @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+v6 ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 |\ -; RUN: grep mov | count 3 +; RUN: grep mov | count 4 define i32 @test(i32 %x) { %tmp = trunc i32 %x to i16 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll?rev=89562&r1=89561&r2=89562&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll Sat Nov 21 15:40:08 2009 @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s +; XFAIL: * define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK: t1: Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll?rev=89562&r1=89561&r2=89562&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll Sat Nov 21 15:40:08 2009 @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s +; XFAIL: * define void @foo(i32 %X, i32 %Y) { entry: From bob.wilson at apple.com Sat Nov 21 16:39:27 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Sat, 21 Nov 2009 22:39:27 -0000 Subject: [llvm-commits] [llvm] r89565 - /llvm/trunk/utils/TableGen/Record.h Message-ID: <200911212239.nALMdSNQ022230@zion.cs.uiuc.edu> Author: bwilson Date: Sat Nov 21 16:39:27 2009 New Revision: 89565 URL: http://llvm.org/viewvc/llvm-project?rev=89565&view=rev Log: Avoid a redundant assertion. Modified: llvm/trunk/utils/TableGen/Record.h Modified: llvm/trunk/utils/TableGen/Record.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.h?rev=89565&r1=89564&r2=89565&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.h (original) +++ llvm/trunk/utils/TableGen/Record.h Sat Nov 21 16:39:27 2009 @@ -1276,13 +1276,12 @@ } void removeValue(StringRef Name) { - assert(getValue(Name) && "Cannot remove an entry that does not exist!"); for (unsigned i = 0, e = Values.size(); i != e; ++i) if (Values[i].getName() == Name) { Values.erase(Values.begin()+i); return; } - assert(0 && "Name does not exist in record!"); + assert(0 && "Cannot remove an entry that does not exist!"); } bool isSubClassOf(const Record *R) const { From bob.wilson at apple.com Sat Nov 21 16:44:20 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Sat, 21 Nov 2009 22:44:20 -0000 Subject: [llvm-commits] [llvm] r89566 - in /llvm/trunk/utils/TableGen: Record.cpp Record.h Message-ID: <200911212244.nALMiKvj022420@zion.cs.uiuc.edu> Author: bwilson Date: Sat Nov 21 16:44:20 2009 New Revision: 89566 URL: http://llvm.org/viewvc/llvm-project?rev=89566&view=rev Log: Fix some spelling in comments. Modified: llvm/trunk/utils/TableGen/Record.cpp llvm/trunk/utils/TableGen/Record.h Modified: llvm/trunk/utils/TableGen/Record.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=89566&r1=89565&r2=89566&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.cpp (original) +++ llvm/trunk/utils/TableGen/Record.cpp Sat Nov 21 16:44:20 2009 @@ -1109,7 +1109,7 @@ if (IRV && IRV->getName() != getName()) return 0; RecordVal *RV = R.getValue(getName()); - assert(RV && "Reference to a non-existant variable?"); + assert(RV && "Reference to a non-existent variable?"); assert(dynamic_cast(RV->getValue())); BitsInit *BI = (BitsInit*)RV->getValue(); @@ -1127,7 +1127,7 @@ if (IRV && IRV->getName() != getName()) return 0; RecordVal *RV = R.getValue(getName()); - assert(RV && "Reference to a non-existant variable?"); + assert(RV && "Reference to a non-existent variable?"); ListInit *LI = dynamic_cast(RV->getValue()); if (!LI) { VarInit *VI = dynamic_cast(RV->getValue()); @@ -1165,7 +1165,7 @@ } /// resolveReferences - This method is used by classes that refer to other -/// variables which may not be defined at the time they expression is formed. +/// variables which may not be defined at the time the expression is formed. /// If a value is set for the variable later, this method will be called on /// users of the value to allow the value to propagate out. /// Modified: llvm/trunk/utils/TableGen/Record.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.h?rev=89566&r1=89565&r2=89566&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.h (original) +++ llvm/trunk/utils/TableGen/Record.h Sat Nov 21 16:44:20 2009 @@ -508,7 +508,7 @@ } /// resolveReferences - This method is used by classes that refer to other - /// variables which may not be defined at the time they expression is formed. + /// variables which may not be defined at the time the expression is formed. /// If a value is set for the variable later, this method will be called on /// users of the value to allow the value to propagate out. /// From grosbach at apple.com Sat Nov 21 17:12:12 2009 From: grosbach at apple.com (Jim Grosbach) Date: Sat, 21 Nov 2009 23:12:12 -0000 Subject: [llvm-commits] [llvm] r89567 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <200911212312.nALNCCZi023401@zion.cs.uiuc.edu> Author: grosbach Date: Sat Nov 21 17:12:12 2009 New Revision: 89567 URL: http://llvm.org/viewvc/llvm-project?rev=89567&view=rev Log: remove trailing whitespace Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=89567&r1=89566&r2=89567&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Sat Nov 21 17:12:12 2009 @@ -93,7 +93,7 @@ /// getDIE - Returns the debug information entry map slot for the /// specified debug variable. DIE *getDIE(MDNode *N) { return GVToDieMap.lookup(N); } - + /// insertDIE - Insert DIE into the map. void insertDIE(MDNode *N, DIE *D) { GVToDieMap.insert(std::make_pair(N, D)); @@ -152,7 +152,7 @@ /// class DbgScope { DbgScope *Parent; // Parent to this scope. - DIDescriptor Desc; // Debug info descriptor for scope. + DIDescriptor Desc; // Debug info descriptor for scope. WeakVH InlinedAtLocation; // Location at which scope is inlined. bool AbstractScope; // Abstract Scope unsigned StartLabelID; // Label ID of the beginning of scope. @@ -167,7 +167,7 @@ public: DbgScope(DbgScope *P, DIDescriptor D, MDNode *I = 0) : Parent(P), Desc(D), InlinedAtLocation(I), AbstractScope(false), - StartLabelID(0), EndLabelID(0), + StartLabelID(0), EndLabelID(0), LastInsn(0), FirstInsn(0), IndentLevel(0) {} virtual ~DbgScope(); @@ -175,7 +175,7 @@ DbgScope *getParent() const { return Parent; } void setParent(DbgScope *P) { Parent = P; } DIDescriptor getDesc() const { return Desc; } - MDNode *getInlinedAt() const { + MDNode *getInlinedAt() const { return dyn_cast_or_null(InlinedAtLocation); } MDNode *getScopeNode() const { return Desc.getNode(); } @@ -204,7 +204,7 @@ assert (getFirstInsn() && "First instruction is missing!"); if (getLastInsn()) return; - + // If a scope does not have an instruction to mark an end then use // the end of last child scope. SmallVector &Scopes = getScopes(); @@ -761,9 +761,9 @@ if (!Context.isNull()) Die = DW_Unit->getDIE(Context.getNode()); - if (Die) + if (Die) Die->addChild(Buffer); - else + else DW_Unit->addDie(Buffer); Entry->setEntry(Buffer); Entity->addValue(dwarf::DW_AT_type, dwarf::DW_FORM_ref4, Entry); @@ -987,7 +987,7 @@ if (!GV.getDisplayName()) return NULL; DIE *GVDie = new DIE(dwarf::DW_TAG_variable); - addString(GVDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, + addString(GVDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, GV.getDisplayName()); const char *LinkageName = GV.getLinkageName(); @@ -1168,7 +1168,7 @@ addSourceLine(VariableDie, &VD); // Add variable type. - // FIXME: isBlockByrefVariable should be reformulated in terms of complex + // FIXME: isBlockByrefVariable should be reformulated in terms of complex // addresses instead. if (VD.isBlockByrefVariable()) addType(Unit, VariableDie, getBlockByrefType(VD.getType(), Name)); @@ -1181,8 +1181,8 @@ MachineLocation Location; Location.set(RI->getFrameRegister(*MF), RI->getFrameIndexOffset(*MF, DV->getFrameIndex())); - - + + if (VD.hasComplexAddress()) addComplexAddress(DV, VariableDie, dwarf::DW_AT_location, Location); else if (VD.isBlockByrefVariable()) @@ -1215,7 +1215,7 @@ DbgScope *Parent = NULL; if (GetConcreteScope) { DILocation IL(InlinedAt); - Parent = getUpdatedDbgScope(IL.getScope().getNode(), MI, + Parent = getUpdatedDbgScope(IL.getScope().getNode(), MI, IL.getOrigLocation().getNode()); assert (Parent && "Unable to find Parent scope!"); NScope->setParent(Parent); @@ -1251,7 +1251,7 @@ DbgScope *AScope = AbstractScopes.lookup(N); if (AScope) return AScope; - + DbgScope *Parent = NULL; DIDescriptor Scope(N); @@ -1279,7 +1279,7 @@ if (D.isNull()) return DISubprogram(); - if (D.isCompileUnit()) + if (D.isCompileUnit()) return DISubprogram(); if (D.isSubprogram()) @@ -1291,7 +1291,7 @@ llvm_unreachable("Unexpected Descriptor!"); } -/// updateSubprogramScopeDIE - Find DIE for the given subprogram and +/// updateSubprogramScopeDIE - Find DIE for the given subprogram and /// attach appropriate DW_AT_low_pc and DW_AT_high_pc attributes. /// If there are global variables in this scope then create and insert /// DIEs for these variables. @@ -1305,12 +1305,12 @@ DWLabel("func_end", SubprogramCount)); MachineLocation Location(RI->getFrameRegister(*MF)); addAddress(SPDie, dwarf::DW_AT_frame_base, Location); - + if (!DISubprogram(SPNode).isLocalToUnit()) addUInt(SPDie, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1); // If there are global variables at this scope then add their dies. - for (SmallVector::iterator SGI = ScopedGVs.begin(), + for (SmallVector::iterator SGI = ScopedGVs.begin(), SGE = ScopedGVs.end(); SGI != SGE; ++SGI) { MDNode *N = dyn_cast_or_null(*SGI); if (!N) continue; @@ -1324,7 +1324,7 @@ return SPDie; } -/// constructLexicalScope - Construct new DW_TAG_lexical_block +/// constructLexicalScope - Construct new DW_TAG_lexical_block /// for this scope and attach DW_AT_low_pc/DW_AT_high_pc labels. DIE *DwarfDebug::constructLexicalScopeDIE(DbgScope *Scope) { unsigned StartID = MMI->MappedLabel(Scope->getStartLabelID()); @@ -1339,12 +1339,12 @@ return ScopeDIE; addLabel(ScopeDIE, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr, - StartID ? - DWLabel("label", StartID) + StartID ? + DWLabel("label", StartID) : DWLabel("func_begin", SubprogramCount)); addLabel(ScopeDIE, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr, - EndID ? - DWLabel("label", EndID) + EndID ? + DWLabel("label", EndID) : DWLabel("func_end", SubprogramCount)); @@ -1403,7 +1403,7 @@ /// constructVariableDIE - Construct a DIE for the given DbgVariable. -DIE *DwarfDebug::constructVariableDIE(DbgVariable *DV, +DIE *DwarfDebug::constructVariableDIE(DbgVariable *DV, DbgScope *Scope, CompileUnit *Unit) { // Get the descriptor. const DIVariable &VD = DV->getVariable(); @@ -1433,7 +1433,7 @@ DIE *AbsDIE = NULL; if (DbgVariable *AV = DV->getAbstractVariable()) AbsDIE = AV->getDIE(); - + if (AbsDIE) { DIScope DS(Scope->getScopeNode()); DISubprogram InlinedSP = getDISubprogram(DS.getNode()); @@ -1450,7 +1450,7 @@ addSourceLine(VariableDie, &VD); // Add variable type. - // FIXME: isBlockByrefVariable should be reformulated in terms of complex + // FIXME: isBlockByrefVariable should be reformulated in terms of complex // addresses instead. if (VD.isBlockByrefVariable()) addType(Unit, VariableDie, getBlockByrefType(VD.getType(), Name)); @@ -1463,8 +1463,8 @@ MachineLocation Location; Location.set(RI->getFrameRegister(*MF), RI->getFrameIndexOffset(*MF, DV->getFrameIndex())); - - + + if (VD.hasComplexAddress()) addComplexAddress(DV, VariableDie, dwarf::DW_AT_location, Location); else if (VD.isBlockByrefVariable()) @@ -1503,7 +1503,7 @@ SmallVector &Variables = Scope->getVariables(); for (unsigned i = 0, N = Variables.size(); i < N; ++i) { DIE *VariableDIE = constructVariableDIE(Variables[i], Scope, ModuleCU); - if (VariableDIE) + if (VariableDIE) ScopeDIE->addChild(VariableDIE); } @@ -1512,7 +1512,7 @@ for (unsigned j = 0, M = Scopes.size(); j < M; ++j) { // Define the Scope debug information entry. DIE *NestedDIE = constructScopeDIE(Scopes[j]); - if (NestedDIE) + if (NestedDIE) ScopeDIE->addChild(NestedDIE); } return ScopeDIE; @@ -1830,7 +1830,7 @@ DbgScope *Scope = ConcreteScopes.lookup(ScopeLoc.getOrigLocation().getNode()); if (!Scope) - Scope = DbgScopeMap.lookup(ScopeLoc.getScope().getNode()); + Scope = DbgScopeMap.lookup(ScopeLoc.getScope().getNode()); // If variable scope is not found then skip this variable. if (!Scope) continue; @@ -1849,7 +1849,7 @@ return; ScopeVector &SD = DbgScopeBeginMap[MI]; for (ScopeVector::iterator SDI = SD.begin(), SDE = SD.end(); - SDI != SDE; ++SDI) + SDI != SDE; ++SDI) (*SDI)->setStartLabelID(Label); } @@ -1864,7 +1864,7 @@ SmallVector &SD = I->second; for (SmallVector::iterator SDI = SD.begin(), SDE = SD.end(); - SDI != SDE; ++SDI) + SDI != SDE; ++SDI) (*SDI)->setEndLabelID(Label); return; } @@ -1878,7 +1878,7 @@ return; WScope = new DbgScope(NULL, DIDescriptor(Scope), NULL); DbgScopeMap.insert(std::make_pair(Scope, WScope)); - if (DIDescriptor(Scope).isLexicalBlock()) + if (DIDescriptor(Scope).isLexicalBlock()) createDbgScope(DILexicalBlock(Scope).getContext().getNode(), NULL); return; } @@ -1912,7 +1912,7 @@ DebugLocTuple DLT = MF->getDebugLocTuple(DL); if (!DLT.Scope) continue; // There is no need to create another DIE for compile unit. For all - // other scopes, create one DbgScope now. This will be translated + // other scopes, create one DbgScope now. This will be translated // into a scope DIE at the end. if (DIDescriptor(DLT.Scope).isCompileUnit()) continue; createDbgScope(DLT.Scope, DLT.InlinedAtLoc); @@ -1931,7 +1931,7 @@ DebugLocTuple DLT = MF->getDebugLocTuple(DL); if (!DLT.Scope) continue; // There is no need to create another DIE for compile unit. For all - // other scopes, create one DbgScope now. This will be translated + // other scopes, create one DbgScope now. This will be translated // into a scope DIE at the end. if (DIDescriptor(DLT.Scope).isCompileUnit()) continue; DbgScope *Scope = getUpdatedDbgScope(DLT.Scope, MInsn, DLT.InlinedAtLoc); @@ -2046,7 +2046,7 @@ // Construct abstract scopes. for (SmallVector::iterator AI = AbstractScopesList.begin(), - AE = AbstractScopesList.end(); AI != AE; ++AI) + AE = AbstractScopesList.end(); AI != AE; ++AI) constructScopeDIE(*AI); constructScopeDIE(CurrentFnDbgScope); @@ -2073,7 +2073,7 @@ /// recordSourceLine - Records location information and associates it with a /// label. Returns a unique label ID used to generate a label and provide /// correspondence to the source line list. -unsigned DwarfDebug::recordSourceLine(unsigned Line, unsigned Col, +unsigned DwarfDebug::recordSourceLine(unsigned Line, unsigned Col, MDNode *S) { if (!MMI) return 0; @@ -2804,7 +2804,7 @@ for (SmallVector::iterator I = InlinedSPNodes.begin(), E = InlinedSPNodes.end(); I != E; ++I) { - + // for (ValueMap >::iterator // I = InlineInfo.begin(), E = InlineInfo.end(); I != E; ++I) { MDNode *Node = *I; @@ -2829,7 +2829,7 @@ } Asm->EOL("MIPS linkage name"); -// Asm->EmitString(Name); +// Asm->EmitString(Name); EmitSectionOffset("string", "section_str", StringPool.idFor(Name), false, true); Asm->EOL("Function name"); From grosbach at apple.com Sat Nov 21 17:34:10 2009 From: grosbach at apple.com (Jim Grosbach) Date: Sat, 21 Nov 2009 23:34:10 -0000 Subject: [llvm-commits] [llvm] r89568 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp test/CodeGen/ARM/hello.ll test/CodeGen/ARM/ifcvt5.ll test/CodeGen/ARM/insn-sched1.ll test/CodeGen/Thumb2/thumb2-ifcvt1.ll test/CodeGen/Thumb2/thumb2-ifcvt2.ll Message-ID: <200911212334.nALNYACr024114@zion.cs.uiuc.edu> Author: grosbach Date: Sat Nov 21 17:34:09 2009 New Revision: 89568 URL: http://llvm.org/viewvc/llvm-project?rev=89568&view=rev Log: Revert 89562. We're being sneakier than I was giving us credit for, and this isn't necessary. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/test/CodeGen/ARM/hello.ll llvm/trunk/test/CodeGen/ARM/ifcvt5.ll llvm/trunk/test/CodeGen/ARM/insn-sched1.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=89568&r1=89567&r2=89568&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Sat Nov 21 17:34:09 2009 @@ -222,7 +222,6 @@ BitVector Reserved(getNumRegs()); Reserved.set(ARM::SP); Reserved.set(ARM::PC); - // FP is reserved on Darwin even if we're not using it in this function. if (STI.isTargetDarwin() || hasFP(MF)) Reserved.set(FramePtr); // Some targets reserve R9. @@ -240,7 +239,6 @@ return true; case ARM::R7: case ARM::R11: - // FP is reserved on Darwin even if we're not using it in this function. if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) return true; break; @@ -494,8 +492,7 @@ /// bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); - return ((STI.isTargetDarwin() && MFI->hasCalls()) || - NoFramePointerElim || + return (NoFramePointerElim || needsStackRealignment(MF) || MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()); Modified: llvm/trunk/test/CodeGen/ARM/hello.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/hello.ll?rev=89568&r1=89567&r2=89568&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/hello.ll (original) +++ llvm/trunk/test/CodeGen/ARM/hello.ll Sat Nov 21 17:34:09 2009 @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | count 1 ; RUN: llc < %s -mtriple=arm-linux-gnu --disable-fp-elim | \ ; RUN: grep mov | count 3 -; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 3 +; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 2 @str = internal constant [12 x i8] c"Hello World\00" Modified: llvm/trunk/test/CodeGen/ARM/ifcvt5.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt5.ll?rev=89568&r1=89567&r2=89568&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ifcvt5.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ifcvt5.ll Sat Nov 21 17:34:09 2009 @@ -1,7 +1,5 @@ ; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s -; XFAIL: * - @x = external global i32* ; [#uses=1] define void @foo(i32 %a) { Modified: llvm/trunk/test/CodeGen/ARM/insn-sched1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/insn-sched1.ll?rev=89568&r1=89567&r2=89568&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/insn-sched1.ll (original) +++ llvm/trunk/test/CodeGen/ARM/insn-sched1.ll Sat Nov 21 17:34:09 2009 @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+v6 ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 |\ -; RUN: grep mov | count 4 +; RUN: grep mov | count 3 define i32 @test(i32 %x) { %tmp = trunc i32 %x to i16 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll?rev=89568&r1=89567&r2=89568&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll Sat Nov 21 17:34:09 2009 @@ -1,5 +1,4 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s -; XFAIL: * define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK: t1: Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll?rev=89568&r1=89567&r2=89568&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll Sat Nov 21 17:34:09 2009 @@ -1,5 +1,4 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s -; XFAIL: * define void @foo(i32 %X, i32 %Y) { entry: From asl at math.spbu.ru Sat Nov 21 19:12:49 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Sun, 22 Nov 2009 01:12:49 -0000 Subject: [llvm-commits] [llvm] r89571 - /llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.cpp Message-ID: <200911220112.nAM1Cn3P027206@zion.cs.uiuc.edu> Author: asl Date: Sat Nov 21 19:12:49 2009 New Revision: 89571 URL: http://llvm.org/viewvc/llvm-project?rev=89571&view=rev Log: Use semicolon as assembler comment string Modified: llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.cpp Modified: llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.cpp?rev=89571&r1=89570&r2=89571&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.cpp Sat Nov 21 19:12:49 2009 @@ -19,6 +19,7 @@ WeakRefDirective ="\t.weak\t"; SetDirective = "\t.set\t"; PCSymbol="."; + CommentString = ";"; AlignmentIsInBytes = false; AllowNameToStartWithDigit = true; From asl at math.spbu.ru Sat Nov 21 19:13:39 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Sun, 22 Nov 2009 01:13:39 -0000 Subject: [llvm-commits] [llvm] r89572 - /llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Message-ID: <200911220113.nAM1DdP8027239@zion.cs.uiuc.edu> Author: asl Date: Sat Nov 21 19:13:39 2009 New Revision: 89572 URL: http://llvm.org/viewvc/llvm-project?rev=89572&view=rev Log: Use 2-byte alignment for functions. 4 bytes are clear overkill here. Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=89572&r1=89571&r2=89572&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Sat Nov 21 19:13:39 2009 @@ -162,7 +162,7 @@ /// getFunctionAlignment - Return the Log2 alignment of this function. unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const { - return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4; + return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2; } //===----------------------------------------------------------------------===// From asl at math.spbu.ru Sat Nov 21 19:13:54 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Sun, 22 Nov 2009 01:13:54 -0000 Subject: [llvm-commits] [llvm] r89573 - /llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td Message-ID: <200911220113.nAM1DsKq027258@zion.cs.uiuc.edu> Author: asl Date: Sat Nov 21 19:13:54 2009 New Revision: 89573 URL: http://llvm.org/viewvc/llvm-project?rev=89573&view=rev Log: Drop unsupported imm operands Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td?rev=89573&r1=89572&r2=89573&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td (original) +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td Sat Nov 21 19:13:54 2009 @@ -823,37 +823,6 @@ "cmp.w\t{$src1, $src2}", [(MSP430cmp (load addr:$src1), GR16:$src2), (implicit SRW)]>; -def CMP8mi0 : Pseudo<(outs), (ins memsrc:$src1), - "cmp.b\t{$src1, #0}", - [(MSP430cmp (load addr:$src1), (i8 0)), (implicit SRW)]>; -def CMP16mi0: Pseudo<(outs), (ins memsrc:$src1), - "cmp.w\t{$src1, #0}", - [(MSP430cmp (load addr:$src1), (i16 0)), (implicit SRW)]>; -def CMP8mi1 : Pseudo<(outs), (ins memsrc:$src1), - "cmp.b\t{$src1, #1}", - [(MSP430cmp (load addr:$src1), (i8 1)), (implicit SRW)]>; -def CMP16mi1: Pseudo<(outs), (ins memsrc:$src1), - "cmp.w\t{$src1, #1}", - [(MSP430cmp (load addr:$src1), (i16 1)), (implicit SRW)]>; -def CMP8mi2 : Pseudo<(outs), (ins memsrc:$src1), - "cmp.b\t{$src1, #2}", - [(MSP430cmp (load addr:$src1), (i8 2)), (implicit SRW)]>; -def CMP16mi2: Pseudo<(outs), (ins memsrc:$src1), - "cmp.w\t{$src1, #2}", - [(MSP430cmp (load addr:$src1), (i16 2)), (implicit SRW)]>; -def CMP8mi4 : Pseudo<(outs), (ins memsrc:$src1), - "cmp.b\t{$src1, #4}", - [(MSP430cmp (load addr:$src1), (i8 4)), (implicit SRW)]>; -def CMP16mi4: Pseudo<(outs), (ins memsrc:$src1), - "cmp.w\t{$src1, #4}", - [(MSP430cmp (load addr:$src1), (i16 4)), (implicit SRW)]>; -def CMP8mi8 : Pseudo<(outs), (ins memsrc:$src1), - "cmp.b\t{$src1, #8}", - [(MSP430cmp (load addr:$src1), (i8 8)), (implicit SRW)]>; -def CMP16mi8: Pseudo<(outs), (ins memsrc:$src1), - "cmp.w\t{$src1, #8}", - [(MSP430cmp (load addr:$src1), (i16 8)), (implicit SRW)]>; - } // Defs = [SRW] //===----------------------------------------------------------------------===// From asl at math.spbu.ru Sat Nov 21 19:14:09 2009 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Sun, 22 Nov 2009 01:14:09 -0000 Subject: [llvm-commits] [llvm] r89574 - /llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Message-ID: <200911220114.nAM1E93p027275@zion.cs.uiuc.edu> Author: asl Date: Sat Nov 21 19:14:08 2009 New Revision: 89574 URL: http://llvm.org/viewvc/llvm-project?rev=89574&view=rev Log: Minor optimization: when doing eq/ne comparions and RHS is a constant - swap operands, this will allow us to fold imm into comparison. Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=89574&r1=89573&r2=89574&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Sat Nov 21 19:14:08 2009 @@ -594,9 +594,17 @@ default: llvm_unreachable("Invalid integer condition!"); case ISD::SETEQ: TCC = MSP430CC::COND_E; // aka COND_Z + // Minor optimization: if RHS is a constant, swap operands, then the + // constant can be folded into comparison. + if (RHS.getOpcode() == ISD::Constant) + std::swap(LHS, RHS); break; case ISD::SETNE: TCC = MSP430CC::COND_NE; // aka COND_NZ + // Minor optimization: if RHS is a constant, swap operands, then the + // constant can be folded into comparison. + if (RHS.getOpcode() == ISD::Constant) + std::swap(LHS, RHS); break; case ISD::SETULE: std::swap(LHS, RHS); // FALLTHROUGH From grosbach at apple.com Sat Nov 21 20:32:29 2009 From: grosbach at apple.com (Jim Grosbach) Date: Sun, 22 Nov 2009 02:32:29 -0000 Subject: [llvm-commits] [llvm] r89576 - in /llvm/trunk/lib/Target/ARM: ARMBaseRegisterInfo.cpp ARMBaseRegisterInfo.h Message-ID: <200911220232.nAM2WULB029549@zion.cs.uiuc.edu> Author: grosbach Date: Sat Nov 21 20:32:29 2009 New Revision: 89576 URL: http://llvm.org/viewvc/llvm-project?rev=89576&view=rev Log: Generate more correct debug info for frame indices. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=89576&r1=89575&r2=89576&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Sat Nov 21 20:32:29 2009 @@ -799,6 +799,53 @@ return ARM::SP; } +int +ARMBaseRegisterInfo::getFrameIndexReference(MachineFunction &MF, int FI, + unsigned &FrameReg) const { + const MachineFrameInfo *MFI = MF.getFrameInfo(); + ARMFunctionInfo *AFI = MF.getInfo(); + int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); + bool isFixed = MFI->isFixedObjectIndex(FI); + + if (AFI->isGPRCalleeSavedArea1Frame(FI)) + Offset -= AFI->getGPRCalleeSavedArea1Offset(); + else if (AFI->isGPRCalleeSavedArea2Frame(FI)) + Offset -= AFI->getGPRCalleeSavedArea2Offset(); + else if (AFI->isDPRCalleeSavedAreaFrame(FI)) + Offset -= AFI->getDPRCalleeSavedAreaOffset(); + else if (needsStackRealignment(MF)) { + // When dynamically realigning the stack, use the frame pointer for + // parameters, and the stack pointer for locals. + assert (hasFP(MF) && "dynamic stack realignment without a FP!"); + if (isFixed) { + FrameReg = getFrameRegister(MF); + Offset -= AFI->getFramePtrSpillOffset(); + } + } else if (hasFP(MF) && AFI->hasStackFrame()) { + if (isFixed || MFI->hasVarSizedObjects()) { + // Use frame pointer to reference fixed objects unless this is a + // frameless function. + FrameReg = getFrameRegister(MF); + Offset -= AFI->getFramePtrSpillOffset(); + } else if (AFI->isThumb2Function()) { + // In Thumb2 mode, the negative offset is very limited. + int FPOffset = Offset - AFI->getFramePtrSpillOffset(); + if (FPOffset >= -255 && FPOffset < 0) { + FrameReg = getFrameRegister(MF); + Offset = FPOffset; + } + } + } + return Offset; +} + + +int +ARMBaseRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { + unsigned FrameReg; + return getFrameIndexReference(MF, FI, FrameReg); +} + unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { llvm_unreachable("What is the exception register"); return 0; @@ -1118,42 +1165,10 @@ unsigned FrameReg = ARM::SP; int FrameIndex = MI.getOperand(i).getIndex(); int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj; - bool isFixed = MFI->isFixedObjectIndex(FrameIndex); - // When doing dynamic stack realignment, all of these need to change(?) - if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) - Offset -= AFI->getGPRCalleeSavedArea1Offset(); - else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) - Offset -= AFI->getGPRCalleeSavedArea2Offset(); - else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) - Offset -= AFI->getDPRCalleeSavedAreaOffset(); - else if (needsStackRealignment(MF)) { - // When dynamically realigning the stack, use the frame pointer for - // parameters, and the stack pointer for locals. - assert (hasFP(MF) && "dynamic stack realignment without a FP!"); - if (isFixed) { - FrameReg = getFrameRegister(MF); - Offset -= AFI->getFramePtrSpillOffset(); - // When referencing from the frame pointer, stack pointer adjustments - // don't matter. - SPAdj = 0; - } - } else if (hasFP(MF) && AFI->hasStackFrame()) { - assert(SPAdj == 0 && "Unexpected stack offset!"); - if (isFixed || MFI->hasVarSizedObjects()) { - // Use frame pointer to reference fixed objects unless this is a - // frameless function. - FrameReg = getFrameRegister(MF); - Offset -= AFI->getFramePtrSpillOffset(); - } else if (AFI->isThumb2Function()) { - // In Thumb2 mode, the negative offset is very limited. - int FPOffset = Offset - AFI->getFramePtrSpillOffset(); - if (FPOffset >= -255 && FPOffset < 0) { - FrameReg = getFrameRegister(MF); - Offset = FPOffset; - } - } - } + Offset = getFrameIndexReference(MF, FrameIndex, FrameReg); + if (FrameReg != ARM::SP) + SPAdj = 0; // Modify MI as necessary to handle as much of 'Offset' as possible bool Done = false; Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=89576&r1=89575&r2=89576&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Sat Nov 21 20:32:29 2009 @@ -106,6 +106,9 @@ // Debug information queries. unsigned getRARegister() const; unsigned getFrameRegister(const MachineFunction &MF) const; + int getFrameIndexReference(MachineFunction &MF, int FI, + unsigned &FrameReg) const; + int getFrameIndexOffset(MachineFunction &MF, int FI) const; // Exception handling queries. unsigned getEHExceptionRegister() const; From nicholas at mxc.ca Sat Nov 21 20:38:11 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 22 Nov 2009 02:38:11 -0000 Subject: [llvm-commits] [llvm] r89577 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Message-ID: <200911220238.nAM2cBHb029736@zion.cs.uiuc.edu> Author: nicholas Date: Sat Nov 21 20:38:11 2009 New Revision: 89577 URL: http://llvm.org/viewvc/llvm-project?rev=89577&view=rev Log: Remove dead code. While there, also turn a few 'T* ' into 'T *' to match the rest of the file. Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=89577&r1=89576&r2=89577&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Sat Nov 21 20:38:11 2009 @@ -117,10 +117,6 @@ Pointer = Inst->getOperand(1); // calls to free() erase the entire structure PointerSize = ~0ULL; - } else if (isFreeCall(Inst)) { - Pointer = Inst->getOperand(0); - // calls to free() erase the entire structure - PointerSize = ~0ULL; } else if (isa(Inst) || isa(Inst)) { // Debug intrinsics don't cause dependences. if (isa(Inst)) continue; @@ -174,7 +170,7 @@ getPointerDependencyFrom(Value *MemPtr, uint64_t MemSize, bool isLoad, BasicBlock::iterator ScanIt, BasicBlock *BB) { - Value* invariantTag = 0; + Value *invariantTag = 0; // Walk backwards through the basic block, looking for dependencies. while (ScanIt != BB->begin()) { @@ -185,12 +181,12 @@ if (invariantTag == Inst) { invariantTag = 0; continue; - } else if (IntrinsicInst* II = dyn_cast(Inst)) { + } else if (IntrinsicInst *II = dyn_cast(Inst)) { // If we pass an invariant-end marker, then we've just entered an // invariant region and can start ignoring dependencies. if (II->getIntrinsicID() == Intrinsic::invariant_end) { uint64_t invariantSize = ~0ULL; - if (ConstantInt* CI = dyn_cast(II->getOperand(2))) + if (ConstantInt *CI = dyn_cast(II->getOperand(2))) invariantSize = CI->getZExtValue(); AliasAnalysis::AliasResult R = @@ -205,7 +201,7 @@ } else if (II->getIntrinsicID() == Intrinsic::lifetime_start || II->getIntrinsicID() == Intrinsic::lifetime_end) { uint64_t invariantSize = ~0ULL; - if (ConstantInt* CI = dyn_cast(II->getOperand(1))) + if (ConstantInt *CI = dyn_cast(II->getOperand(1))) invariantSize = CI->getZExtValue(); AliasAnalysis::AliasResult R = From bob.wilson at apple.com Sat Nov 21 21:58:57 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Sun, 22 Nov 2009 03:58:57 -0000 Subject: [llvm-commits] [llvm] r89581 - in /llvm/trunk: test/TableGen/UnsetBitInit.td utils/TableGen/Record.cpp Message-ID: <200911220358.nAM3wwMm032199@zion.cs.uiuc.edu> Author: bwilson Date: Sat Nov 21 21:58:57 2009 New Revision: 89581 URL: http://llvm.org/viewvc/llvm-project?rev=89581&view=rev Log: Fix pr5470. Tablegen handles template arguments by temporarily setting their values, resolving references to them, and then removing the definitions. If a template argument is set to an undefined value, we need to resolve references to that argument to an explicit undefined value. The current code leaves the reference to the template argument as it is, which causes an assertion failure later when the definition of the template argument is removed. Added: llvm/trunk/test/TableGen/UnsetBitInit.td Modified: llvm/trunk/utils/TableGen/Record.cpp Added: llvm/trunk/test/TableGen/UnsetBitInit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/UnsetBitInit.td?rev=89581&view=auto ============================================================================== --- llvm/trunk/test/TableGen/UnsetBitInit.td (added) +++ llvm/trunk/test/TableGen/UnsetBitInit.td Sat Nov 21 21:58:57 2009 @@ -0,0 +1,10 @@ +// RUN: tblgen %s +class x { + field bits<32> A; +} + +class y B> : x { + let A{21-20} = B; +} + +def z : y<{0,?}>; Modified: llvm/trunk/utils/TableGen/Record.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=89581&r1=89580&r2=89581&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.cpp (original) +++ llvm/trunk/utils/TableGen/Record.cpp Sat Nov 21 21:58:57 2009 @@ -490,8 +490,11 @@ if (Elt >= getSize()) return 0; // Out of range reference. Init *E = getElement(Elt); - if (!dynamic_cast(E)) // If the element is set - return E; // Replace the VarListElementInit with it. + // If the element is set to some value, or if we are resolving a reference + // to a specific variable and that variable is explicitly unset, then + // replace the VarListElementInit with it. + if (IRV || !dynamic_cast(E)) + return E; return 0; } @@ -1116,8 +1119,11 @@ assert(Bit < BI->getNumBits() && "Bit reference out of range!"); Init *B = BI->getBit(Bit); - if (!dynamic_cast(B)) // If the bit is not set... - return B; // Replace the VarBitInit with it. + // If the bit is set to some value, or if we are resolving a reference to a + // specific variable and that variable is explicitly unset, then replace the + // VarBitInit with it. + if (IRV || !dynamic_cast(B)) + return B; return 0; } @@ -1138,8 +1144,11 @@ if (Elt >= LI->getSize()) return 0; // Out of range reference. Init *E = LI->getElement(Elt); - if (!dynamic_cast(E)) // If the element is set - return E; // Replace the VarListElementInit with it. + // If the element is set to some value, or if we are resolving a reference + // to a specific variable and that variable is explicitly unset, then + // replace the VarListElementInit with it. + if (IRV || !dynamic_cast(E)) + return E; return 0; } @@ -1246,8 +1255,11 @@ if (Elt >= LI->getSize()) return 0; Init *E = LI->getElement(Elt); - if (!dynamic_cast(E)) // If the bit is set... - return E; // Replace the VarListElementInit with it. + // If the element is set to some value, or if we are resolving a + // reference to a specific variable and that variable is explicitly + // unset, then replace the VarListElementInit with it. + if (RV || !dynamic_cast(E)) + return E; } return 0; } From bob.wilson at apple.com Sat Nov 21 22:24:43 2009 From: bob.wilson at apple.com (Bob Wilson) Date: Sun, 22 Nov 2009 04:24:43 -0000 Subject: [llvm-commits] [llvm] r89582 - in /llvm/trunk/utils/TableGen: Record.cpp Record.h TGParser.cpp Message-ID: <200911220424.nAM4OiBt000546@zion.cs.uiuc.edu> Author: bwilson Date: Sat Nov 21 22:24:42 2009 New Revision: 89582 URL: http://llvm.org/viewvc/llvm-project?rev=89582&view=rev Log: Fix whitespace. Modified: llvm/trunk/utils/TableGen/Record.cpp llvm/trunk/utils/TableGen/Record.h llvm/trunk/utils/TableGen/TGParser.cpp Modified: llvm/trunk/utils/TableGen/Record.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=89582&r1=89581&r2=89582&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.cpp (original) +++ llvm/trunk/utils/TableGen/Record.cpp Sat Nov 21 22:24:42 2009 @@ -274,7 +274,7 @@ } -/// resolveTypes - Find a common type that T1 and T2 convert to. +/// resolveTypes - Find a common type that T1 and T2 convert to. /// Return 0 if no such type exists. /// RecTy *llvm::resolveTypes(RecTy *T1, RecTy *T2) { @@ -284,7 +284,8 @@ RecordRecTy *RecTy1 = dynamic_cast(T1); if (RecTy1) { // See if T2 inherits from a type T1 also inherits from - const std::vector &T1SuperClasses = RecTy1->getRecord()->getSuperClasses(); + const std::vector &T1SuperClasses = + RecTy1->getRecord()->getSuperClasses(); for(std::vector::const_iterator i = T1SuperClasses.begin(), iend = T1SuperClasses.end(); i != iend; @@ -302,8 +303,9 @@ RecordRecTy *RecTy2 = dynamic_cast(T2); if (RecTy2) { // See if T1 inherits from a type T2 also inherits from - const std::vector &T2SuperClasses = RecTy2->getRecord()->getSuperClasses(); - for(std::vector::const_iterator i = T2SuperClasses.begin(), + const std::vector &T2SuperClasses = + RecTy2->getRecord()->getSuperClasses(); + for (std::vector::const_iterator i = T2SuperClasses.begin(), iend = T2SuperClasses.end(); i != iend; ++i) { @@ -486,7 +488,7 @@ } Init *ListInit::resolveListElementReference(Record &R, const RecordVal *IRV, - unsigned Elt) { + unsigned Elt) { if (Elt >= getSize()) return 0; // Out of range reference. Init *E = getElement(Elt); @@ -508,30 +510,30 @@ } Init *OpInit::resolveBitReference(Record &R, const RecordVal *IRV, - unsigned Bit) { + unsigned Bit) { Init *Folded = Fold(&R, 0); if (Folded != this) { TypedInit *Typed = dynamic_cast(Folded); if (Typed) { return Typed->resolveBitReference(R, IRV, Bit); - } + } } - + return 0; } Init *OpInit::resolveListElementReference(Record &R, const RecordVal *IRV, - unsigned Elt) { + unsigned Elt) { Init *Folded = Fold(&R, 0); if (Folded != this) { TypedInit *Typed = dynamic_cast(Folded); if (Typed) { return Typed->resolveListElementReference(R, IRV, Elt); - } + } } - + return 0; } @@ -549,8 +551,7 @@ if (LHSd) { return new StringInit(LHSd->getDef()->getName()); } - } - else { + } else { StringInit *LHSs = dynamic_cast(LHS); if (LHSs) { std::string Name = LHSs->getValue(); @@ -582,15 +583,15 @@ if (CurMultiClass->Rec.isTemplateArg(MCName)) { const RecordVal *RV = CurMultiClass->Rec.getValue(MCName); assert(RV && "Template arg doesn't exist??"); - + if (RV->getType() != getType()) { throw "type mismatch in nameconcat"; } - + return new VarInit(MCName, RV->getType()); } } - + if (Record *D = Records.getDef(Name)) return new DefInit(D); @@ -619,7 +620,8 @@ assert(0 && "Empty list in cdr"); return 0; } - ListInit *Result = new ListInit(LHSl->begin()+1, LHSl->end(), LHSl->getType()); + ListInit *Result = new ListInit(LHSl->begin()+1, LHSl->end(), + LHSl->getType()); return Result; } break; @@ -629,8 +631,7 @@ if (LHSl) { if (LHSl->getSize() == 0) { return new IntInit(1); - } - else { + } else { return new IntInit(0); } } @@ -638,12 +639,11 @@ if (LHSs) { if (LHSs->getValue().empty()) { return new IntInit(1); - } - else { + } else { return new IntInit(0); } } - + break; } } @@ -652,7 +652,7 @@ Init *UnOpInit::resolveReferences(Record &R, const RecordVal *RV) { Init *lhs = LHS->resolveReferences(R, RV); - + if (LHS != lhs) return (new UnOpInit(getOpcode(), lhs, getType()))->Fold(&R, 0); return Fold(&R, 0); @@ -742,7 +742,7 @@ } return new VarInit(Name, RV->getType()); } - + std::string TemplateArgName = CurRec->getName()+":"+Name; if (CurRec->isTemplateArg(TemplateArgName)) { const RecordVal *RV = CurRec->getValue(TemplateArgName); @@ -765,7 +765,7 @@ if (RV->getType() != getType()) { throw "type mismatch in nameconcat"; } - + return new VarInit(MCName, RV->getType()); } } @@ -804,7 +804,7 @@ Init *BinOpInit::resolveReferences(Record &R, const RecordVal *RV) { Init *lhs = LHS->resolveReferences(R, RV); Init *rhs = RHS->resolveReferences(R, RV); - + if (LHS != lhs || RHS != rhs) return (new BinOpInit(getOpcode(), lhs, rhs, getType()))->Fold(&R, 0); return Fold(&R, 0); @@ -818,7 +818,7 @@ case SRA: Result = "!sra"; break; case SRL: Result = "!srl"; break; case STRCONCAT: Result = "!strconcat"; break; - case NAMECONCAT: + case NAMECONCAT: Result = "!nameconcat<" + getType()->getAsString() + ">"; break; } return Result + "(" + LHS->getAsString() + ", " + RHS->getAsString() + ")"; @@ -840,8 +840,7 @@ CurRec, CurMultiClass); if (Result != 0) { return Result; - } - else { + } else { return 0; } } @@ -854,15 +853,12 @@ Type, CurRec, CurMultiClass); if (Result != 0) { NewOperands.push_back(Result); - } - else { + } else { NewOperands.push_back(Arg); } - } - else if (LHS->getAsString() == RHSo->getOperand(i)->getAsString()) { + } else if (LHS->getAsString() == RHSo->getOperand(i)->getAsString()) { NewOperands.push_back(Arg); - } - else { + } else { NewOperands.push_back(RHSo->getOperand(i)); } } @@ -942,8 +938,7 @@ // First, replace the foreach variable with the list item if (LHS->getAsString() == RHSo->getOperand(i)->getAsString()) { NewOperands.push_back(Item); - } - else { + } else { NewOperands.push_back(RHSo->getOperand(i)); } } @@ -1010,7 +1005,7 @@ } } break; - } + } case FOREACH: { Init *Result = ForeachHelper(LHS, MHS, RHS, getType(), @@ -1026,8 +1021,7 @@ if (LHSi) { if (LHSi->getValue()) { return MHS; - } - else { + } else { return RHS; } } @@ -1047,15 +1041,16 @@ // Short-circuit if (Value->getValue()) { Init *mhs = MHS->resolveReferences(R, RV); - return (new TernOpInit(getOpcode(), lhs, mhs, RHS, getType()))->Fold(&R, 0); - } - else { + return (new TernOpInit(getOpcode(), lhs, mhs, + RHS, getType()))->Fold(&R, 0); + } else { Init *rhs = RHS->resolveReferences(R, RV); - return (new TernOpInit(getOpcode(), lhs, MHS, rhs, getType()))->Fold(&R, 0); + return (new TernOpInit(getOpcode(), lhs, MHS, + rhs, getType()))->Fold(&R, 0); } } } - + Init *mhs = MHS->resolveReferences(R, RV); Init *rhs = RHS->resolveReferences(R, RV); @@ -1068,10 +1063,10 @@ std::string Result; switch (Opc) { case SUBST: Result = "!subst"; break; - case FOREACH: Result = "!foreach"; break; - case IF: Result = "!if"; break; + case FOREACH: Result = "!foreach"; break; + case IF: Result = "!if"; break; } - return Result + "(" + LHS->getAsString() + ", " + MHS->getAsString() + ", " + return Result + "(" + LHS->getAsString() + ", " + MHS->getAsString() + ", " + RHS->getAsString() + ")"; } @@ -1140,7 +1135,7 @@ assert(VI && "Invalid list element!"); return new VarListElementInit(VI, Elt); } - + if (Elt >= LI->getSize()) return 0; // Out of range reference. Init *E = LI->getElement(Elt); @@ -1283,12 +1278,12 @@ std::vector NewArgs; for (unsigned i = 0, e = Args.size(); i != e; ++i) NewArgs.push_back(Args[i]->resolveReferences(R, RV)); - + Init *Op = Val->resolveReferences(R, RV); - + if (Args != NewArgs || Op != Val) return new DagInit(Op, "", NewArgs, ArgNames); - + return this; } @@ -1457,7 +1452,7 @@ /// its value as a vector of records, throwing an exception if the field does /// not exist or if the value is not the right type. /// -std::vector +std::vector Record::getValueAsListOfDefs(StringRef FieldName) const { ListInit *List = getValueAsListInit(FieldName); std::vector Defs; @@ -1492,7 +1487,7 @@ /// its value as a vector of integers, throwing an exception if the field does /// not exist or if the value is not the right type. /// -std::vector +std::vector Record::getValueAsListOfInts(StringRef FieldName) const { ListInit *List = getValueAsListInit(FieldName); std::vector Ints; @@ -1560,7 +1555,7 @@ if (R == 0 || R->getValue() == 0) throw "Record `" + getName() + "' does not have a field named `" + FieldName.str() + "'!\n"; - + if (const CodeInit *CI = dynamic_cast(R->getValue())) return CI->getValue(); throw "Record `" + getName() + "', field `" + FieldName.str() + @@ -1571,7 +1566,7 @@ void MultiClass::dump() const { errs() << "Record:\n"; Rec.dump(); - + errs() << "Defs:\n"; for (RecordVector::const_iterator r = DefPrototypes.begin(), rend = DefPrototypes.end(); Modified: llvm/trunk/utils/TableGen/Record.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.h?rev=89582&r1=89581&r2=89582&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.h (original) +++ llvm/trunk/utils/TableGen/Record.h Sat Nov 21 22:24:42 2009 @@ -22,7 +22,7 @@ namespace llvm { class raw_ostream; - + // RecTy subclasses. class BitRecTy; class BitsRecTy; @@ -443,7 +443,7 @@ virtual bool baseClassOf(const RecordRecTy *RHS) const; }; -/// resolveTypes - Find a common type that T1 and T2 convert to. +/// resolveTypes - Find a common type that T1 and T2 convert to. /// Return 0 if no such type exists. /// RecTy *resolveTypes(RecTy *T1, RecTy *T2); @@ -731,7 +731,7 @@ } Record *getElementAsRecord(unsigned i) const; - + Init *convertInitListSlice(const std::vector &Elements); virtual Init *convertInitializerTo(RecTy *Ty) { @@ -792,7 +792,7 @@ virtual Init *convertInitializerTo(RecTy *Ty) { return Ty->convertValue(this); } - + virtual Init *resolveBitReference(Record &R, const RecordVal *RV, unsigned Bit); virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, @@ -825,7 +825,7 @@ assert(i == 0 && "Invalid operand id for unary operator"); return getOperand(); } - + UnaryOp getOpcode() const { return Opc; } Init *getOperand() const { return LHS; } @@ -834,7 +834,7 @@ Init *Fold(Record *CurRec, MultiClass *CurMultiClass); virtual Init *resolveReferences(Record &R, const RecordVal *RV); - + /// getFieldType - This method is used to implement the FieldInit class. /// Implementors of this method should return the type of the named field if /// they are of record type. @@ -856,7 +856,7 @@ BinOpInit(BinaryOp opc, Init *lhs, Init *rhs, RecTy *Type) : OpInit(Type), Opc(opc), LHS(lhs), RHS(rhs) { } - + // Clone - Clone this operator, replacing arguments with the new list virtual OpInit *clone(std::vector &Operands) { assert(Operands.size() == 2 && @@ -869,8 +869,7 @@ assert((i == 0 || i == 1) && "Invalid operand id for binary operator"); if (i == 0) { return getLHS(); - } - else { + } else { return getRHS(); } } @@ -884,7 +883,7 @@ Init *Fold(Record *CurRec, MultiClass *CurMultiClass); virtual Init *resolveReferences(Record &R, const RecordVal *RV); - + virtual std::string getAsString() const; }; @@ -900,7 +899,7 @@ TernOpInit(TernaryOp opc, Init *lhs, Init *mhs, Init *rhs, RecTy *Type) : OpInit(Type), Opc(opc), LHS(lhs), MHS(mhs), RHS(rhs) { } - + // Clone - Clone this operator, replacing arguments with the new list virtual OpInit *clone(std::vector &Operands) { assert(Operands.size() == 3 && @@ -915,11 +914,9 @@ "Invalid operand id for ternary operator"); if (i == 0) { return getLHS(); - } - else if (i == 1) { + } else if (i == 1) { return getMHS(); - } - else { + } else { return getRHS(); } } @@ -932,9 +929,9 @@ // Fold - If possible, fold this to a simpler init. Return this if not // possible to fold. Init *Fold(Record *CurRec, MultiClass *CurMultiClass); - + virtual Init *resolveReferences(Record &R, const RecordVal *RV); - + virtual std::string getAsString() const; }; @@ -1106,7 +1103,7 @@ std::vector Args; std::vector ArgNames; public: - DagInit(Init *V, std::string VN, + DagInit(Init *V, std::string VN, const std::vector > &args) : TypedInit(new DagRecTy), Val(V), ValName(VN) { Args.reserve(args.size()); @@ -1116,11 +1113,11 @@ ArgNames.push_back(args[i].second); } } - DagInit(Init *V, std::string VN, const std::vector &args, + DagInit(Init *V, std::string VN, const std::vector &args, const std::vector &argNames) - : TypedInit(new DagRecTy), Val(V), ValName(VN), Args(args), ArgNames(argNames) { - } - + : TypedInit(new DagRecTy), Val(V), ValName(VN), Args(args), + ArgNames(argNames) { } + virtual Init *convertInitializerTo(RecTy *Ty) { return Ty->convertValue(this); } @@ -1143,7 +1140,7 @@ assert(Num < Args.size() && "Arg number out of range!"); Args[Num] = I; } - + virtual Init *resolveReferences(Record &R, const RecordVal *RV); virtual std::string getAsString() const; @@ -1174,13 +1171,12 @@ assert(0 && "Illegal bit reference off dag"); return 0; } - + virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, unsigned Elt) { assert(0 && "Illegal element reference off dag"); return 0; } - }; //===----------------------------------------------------------------------===// @@ -1231,17 +1227,17 @@ std::vector SuperClasses; public: - explicit Record(const std::string &N, SMLoc loc) : + explicit Record(const std::string &N, SMLoc loc) : ID(LastID++), Name(N), Loc(loc) {} ~Record() {} - + unsigned getID() const { return ID; } const std::string &getName() const { return Name; } void setName(const std::string &Name); // Also updates RecordKeeper. - + SMLoc getLoc() const { return Loc; } - + const std::vector &getTemplateArgs() const { return TemplateArgs; } @@ -1353,7 +1349,7 @@ /// not exist or if the value is not the right type. /// std::vector getValueAsListOfInts(StringRef FieldName) const; - + /// getValueAsDef - This method looks up the specified field and returns its /// value as a Record, throwing an exception if the field does not exist or if /// the value is not the right type. @@ -1377,7 +1373,7 @@ /// the value is not the right type. /// DagInit *getValueAsDag(StringRef FieldName) const; - + /// getValueAsCode - This method looks up the specified field and returns /// its value as the string data in a CodeInit, throwing an exception if the /// field does not exist or if the value is not a code object. @@ -1441,7 +1437,7 @@ assert(Defs.count(Name) && "Def does not exist!"); Defs.erase(Name); } - + //===--------------------------------------------------------------------===// // High-level helper methods, useful for tablegen backends... @@ -1463,7 +1459,7 @@ } }; -/// LessRecordFieldName - Sorting predicate to sort record pointers by their +/// LessRecordFieldName - Sorting predicate to sort record pointers by their /// name field. /// struct LessRecordFieldName { @@ -1478,19 +1474,18 @@ std::string Message; public: TGError(SMLoc loc, const std::string &message) : Loc(loc), Message(message) {} - + SMLoc getLoc() const { return Loc; } const std::string &getMessage() const { return Message; } }; - - + + raw_ostream &operator<<(raw_ostream &OS, const RecordKeeper &RK); extern RecordKeeper Records; void PrintError(SMLoc ErrorLoc, const std::string &Msg); - } // End llvm namespace #endif Modified: llvm/trunk/utils/TableGen/TGParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGParser.cpp?rev=89582&r1=89581&r2=89582&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TGParser.cpp (original) +++ llvm/trunk/utils/TableGen/TGParser.cpp Sat Nov 21 22:24:42 2009 @@ -44,9 +44,9 @@ void SubMultiClassReference::dump() const { errs() << "Multiclass:\n"; - + MC->dump(); - + errs() << "Template args:\n"; for (std::vector::const_iterator i = TemplateArgs.begin(), iend = TemplateArgs.end(); @@ -61,13 +61,13 @@ bool TGParser::AddValue(Record *CurRec, SMLoc Loc, const RecordVal &RV) { if (CurRec == 0) CurRec = &CurMultiClass->Rec; - + if (RecordVal *ERV = CurRec->getValue(RV.getName())) { // The value already exists in the class, treat this as a set. if (ERV->setValue(RV.getValue())) return Error(Loc, "New definition of '" + RV.getName() + "' of type '" + RV.getType()->getAsString() + "' is incompatible with " + - "previous definition of type '" + + "previous definition of type '" + ERV->getType()->getAsString() + "'"); } else { CurRec->addValue(RV); @@ -77,7 +77,7 @@ /// SetValue - /// Return true on error, false on success. -bool TGParser::SetValue(Record *CurRec, SMLoc Loc, const std::string &ValName, +bool TGParser::SetValue(Record *CurRec, SMLoc Loc, const std::string &ValName, const std::vector &BitList, Init *V) { if (!V) return false; @@ -93,7 +93,7 @@ if (VarInit *VI = dynamic_cast(V)) if (VI->getName() == ValName) return false; - + // If we are assigning to a subset of the bits in the value... then we must be // assigning to a field of BitsRecTy, which must have a BitsInit // initializer. @@ -109,7 +109,7 @@ V->convertInitializerTo(new BitsRecTy(BitList.size())); return Error(Loc, "Initializer is not compatible with bit range"); } - + // We should have a BitsInit type now. BitsInit *BInit = dynamic_cast(BI); assert(BInit != 0); @@ -133,8 +133,8 @@ } if (RV->setValue(V)) - return Error(Loc, "Value '" + ValName + "' of type '" + - RV->getType()->getAsString() + + return Error(Loc, "Value '" + ValName + "' of type '" + + RV->getType()->getAsString() + "' is incompatible with initializer '" + V->getAsString() +"'"); return false; } @@ -154,25 +154,25 @@ // Ensure that an appropriate number of template arguments are specified. if (TArgs.size() < SubClass.TemplateArgs.size()) return Error(SubClass.RefLoc, "More template args specified than expected"); - + // Loop over all of the template arguments, setting them to the specified // value or leaving them as the default if necessary. for (unsigned i = 0, e = TArgs.size(); i != e; ++i) { if (i < SubClass.TemplateArgs.size()) { // If a value is specified for this template arg, set it now. - if (SetValue(CurRec, SubClass.RefLoc, TArgs[i], std::vector(), + if (SetValue(CurRec, SubClass.RefLoc, TArgs[i], std::vector(), SubClass.TemplateArgs[i])) return true; - + // Resolve it next. CurRec->resolveReferencesTo(CurRec->getValue(TArgs[i])); - + // Now remove it. CurRec->removeValue(TArgs[i]); } else if (!CurRec->getValue(TArgs[i])->getValue()->isComplete()) { return Error(SubClass.RefLoc,"Value not specified for template argument #" - + utostr(i) + " (" + TArgs[i] + ") of subclass '" + + + utostr(i) + " (" + TArgs[i] + ") of subclass '" + SC->getName() + "'!"); } } @@ -186,7 +186,7 @@ "Already subclass of '" + SCs[i]->getName() + "'!\n"); CurRec->addSuperClass(SCs[i]); } - + if (CurRec->isSubClassOf(SC)) return Error(SubClass.RefLoc, "Already subclass of '" + SC->getName() + "'!\n"); @@ -291,7 +291,7 @@ /// isObjectStart - Return true if this is a valid first token for an Object. static bool isObjectStart(tgtok::TokKind K) { return K == tgtok::Class || K == tgtok::Def || - K == tgtok::Defm || K == tgtok::Let || K == tgtok::MultiClass; + K == tgtok::Defm || K == tgtok::Let || K == tgtok::MultiClass; } /// ParseObjectName - If an object name is specified, return it. Otherwise, @@ -305,7 +305,7 @@ Lex.Lex(); return Ret; } - + static unsigned AnonCounter = 0; return "anonymous."+utostr(AnonCounter++); } @@ -321,11 +321,11 @@ TokError("expected name for ClassID"); return 0; } - + Record *Result = Records.getClass(Lex.getCurStrVal()); if (Result == 0) TokError("Couldn't find class '" + Lex.getCurStrVal() + "'"); - + Lex.Lex(); return Result; } @@ -354,17 +354,16 @@ TokError("expected multiclass name"); return 0; } - + MultiClass *MC = MultiClasses[Lex.getCurStrVal()]; if (MC == 0) { TokError("Couldn't find multiclass '" + Lex.getCurStrVal() + "'"); return 0; } - + Lex.Lex(); return &MC->Rec; -} - +} /// ParseSubClassReference - Parse a reference to a subclass or to a templated @@ -377,37 +376,37 @@ ParseSubClassReference(Record *CurRec, bool isDefm) { SubClassReference Result; Result.RefLoc = Lex.getLoc(); - + if (isDefm) Result.Rec = ParseDefmID(); else Result.Rec = ParseClassID(); if (Result.Rec == 0) return Result; - + // If there is no template arg list, we're done. if (Lex.getCode() != tgtok::less) return Result; Lex.Lex(); // Eat the '<' - + if (Lex.getCode() == tgtok::greater) { TokError("subclass reference requires a non-empty list of template values"); Result.Rec = 0; return Result; } - + Result.TemplateArgs = ParseValueList(CurRec, Result.Rec); if (Result.TemplateArgs.empty()) { Result.Rec = 0; // Error parsing value list. return Result; } - + if (Lex.getCode() != tgtok::greater) { TokError("expected '>' in template value list"); Result.Rec = 0; return Result; } Lex.Lex(); - + return Result; } @@ -464,12 +463,12 @@ } int64_t Start = Lex.getCurIntVal(); int64_t End; - + if (Start < 0) return TokError("invalid range, cannot be negative"); - + switch (Lex.Lex()) { // eat first character. - default: + default: Ranges.push_back(Start); return false; case tgtok::minus: @@ -483,10 +482,10 @@ End = -Lex.getCurIntVal(); break; } - if (End < 0) + if (End < 0) return TokError("invalid range, cannot be negative"); Lex.Lex(); - + // Add to the range. if (Start < End) { for (; Start <= End; ++Start) @@ -504,7 +503,7 @@ /// std::vector TGParser::ParseRangeList() { std::vector Result; - + // Parse the first piece. if (ParseRangePiece(Result)) return std::vector(); @@ -524,14 +523,14 @@ bool TGParser::ParseOptionalRangeList(std::vector &Ranges) { if (Lex.getCode() != tgtok::less) return false; - + SMLoc StartLoc = Lex.getLoc(); Lex.Lex(); // eat the '<' - + // Parse the range list. Ranges = ParseRangeList(); if (Ranges.empty()) return true; - + if (Lex.getCode() != tgtok::greater) { TokError("expected '>' at end of range list"); return Error(StartLoc, "to match this '<'"); @@ -546,14 +545,14 @@ bool TGParser::ParseOptionalBitList(std::vector &Ranges) { if (Lex.getCode() != tgtok::l_brace) return false; - + SMLoc StartLoc = Lex.getLoc(); Lex.Lex(); // eat the '{' - + // Parse the range list. Ranges = ParseRangeList(); if (Ranges.empty()) return true; - + if (Lex.getCode() != tgtok::r_brace) { TokError("expected '}' at end of bit list"); return Error(StartLoc, "to match this '{'"); @@ -610,7 +609,7 @@ Lex.Lex(); // Eat '<' RecTy *SubType = ParseType(); if (SubType == 0) return 0; - + if (Lex.getCode() != tgtok::greater) { TokError("expected '>' at end of list type"); return 0; @@ -618,7 +617,7 @@ Lex.Lex(); // Eat '>' return new ListRecTy(SubType); } - } + } } /// ParseIDValue - Parse an ID as a value and decode what it means. @@ -639,12 +638,12 @@ /// ParseIDValue - This is just like ParseIDValue above, but it assumes the ID /// has already been read. -Init *TGParser::ParseIDValue(Record *CurRec, +Init *TGParser::ParseIDValue(Record *CurRec, const std::string &Name, SMLoc NameLoc) { if (CurRec) { if (const RecordVal *RV = CurRec->getValue(Name)) return new VarInit(Name, RV->getType()); - + std::string TemplateArgName = CurRec->getName()+":"+Name; if (CurRec->isTemplateArg(TemplateArgName)) { const RecordVal *RV = CurRec->getValue(TemplateArgName); @@ -652,7 +651,7 @@ return new VarInit(TemplateArgName, RV->getType()); } } - + if (CurMultiClass) { std::string MCName = CurMultiClass->Rec.getName()+"::"+Name; if (CurMultiClass->Rec.isTemplateArg(MCName)) { @@ -661,7 +660,7 @@ return new VarInit(MCName, RV->getType()); } } - + if (Record *D = Records.getDef(Name)) return new DefInit(D); @@ -748,7 +747,7 @@ TokError("expected list type argumnet in unary operator"); return 0; } - + if (LHSl && LHSl->getSize() == 0) { TokError("empty list argument in unary operator"); return 0; @@ -762,12 +761,10 @@ } if (Code == UnOpInit::CAR) { Type = Itemt->getType(); - } - else { + } else { Type = new ListRecTy(Itemt->getType()); } - } - else { + } else { assert(LHSt && "expected list type argument in unary operator"); ListRecTy *LType = dynamic_cast(LHSt->getType()); if (LType == 0) { @@ -776,8 +773,7 @@ } if (Code == UnOpInit::CAR) { Type = LType->getElementType(); - } - else { + } else { Type = LType; } } @@ -793,7 +789,7 @@ } case tgtok::XConcat: - case tgtok::XSRA: + case tgtok::XSRA: case tgtok::XSRL: case tgtok::XSHL: case tgtok::XStrConcat: @@ -804,32 +800,32 @@ switch (Lex.getCode()) { default: assert(0 && "Unhandled code!"); - case tgtok::XConcat: + case tgtok::XConcat: Lex.Lex(); // eat the operation Code = BinOpInit::CONCAT; Type = new DagRecTy(); break; - case tgtok::XSRA: + case tgtok::XSRA: Lex.Lex(); // eat the operation Code = BinOpInit::SRA; Type = new IntRecTy(); break; - case tgtok::XSRL: + case tgtok::XSRL: Lex.Lex(); // eat the operation Code = BinOpInit::SRL; Type = new IntRecTy(); break; - case tgtok::XSHL: + case tgtok::XSHL: Lex.Lex(); // eat the operation Code = BinOpInit::SHL; Type = new IntRecTy(); break; - case tgtok::XStrConcat: + case tgtok::XStrConcat: Lex.Lex(); // eat the operation Code = BinOpInit::STRCONCAT; Type = new StringRecTy(); break; - case tgtok::XNameConcat: + case tgtok::XNameConcat: Lex.Lex(); // eat the operation Code = BinOpInit::NAMECONCAT; @@ -856,7 +852,7 @@ return 0; } Lex.Lex(); // eat the ',' - + Init *RHS = ParseValue(CurRec); if (RHS == 0) return 0; @@ -903,7 +899,7 @@ return 0; } Lex.Lex(); // eat the ',' - + Init *MHS = ParseValue(CurRec); if (MHS == 0) return 0; @@ -912,7 +908,7 @@ return 0; } Lex.Lex(); // eat the ',' - + Init *RHS = ParseValue(CurRec); if (RHS == 0) return 0; @@ -933,11 +929,9 @@ } if (MHSt->getType()->typeIsConvertibleTo(RHSt->getType())) { Type = RHSt->getType(); - } - else if (RHSt->getType()->typeIsConvertibleTo(MHSt->getType())) { + } else if (RHSt->getType()->typeIsConvertibleTo(MHSt->getType())) { Type = MHSt->getType(); - } - else { + } else { TokError("inconsistent types for !if"); return 0; } @@ -962,7 +956,8 @@ break; } } - return (new TernOpInit(Code, LHS, MHS, RHS, Type))->Fold(CurRec, CurMultiClass); + return (new TernOpInit(Code, LHS, MHS, RHS, Type))->Fold(CurRec, + CurMultiClass); } } TokError("could not parse operation"); @@ -1025,25 +1020,25 @@ case tgtok::StrVal: { std::string Val = Lex.getCurStrVal(); Lex.Lex(); - + // Handle multiple consecutive concatenated strings. while (Lex.getCode() == tgtok::StrVal) { Val += Lex.getCurStrVal(); Lex.Lex(); } - + R = new StringInit(Val); break; } case tgtok::CodeFragment: - R = new CodeInit(Lex.getCurStrVal()); Lex.Lex(); break; + R = new CodeInit(Lex.getCurStrVal()); Lex.Lex(); break; case tgtok::question: R = new UnsetInit(); Lex.Lex(); break; case tgtok::Id: { SMLoc NameLoc = Lex.getLoc(); std::string Name = Lex.getCurStrVal(); if (Lex.Lex() != tgtok::less) // consume the Id. return ParseIDValue(CurRec, Name, NameLoc); // Value ::= IDValue - + // Value ::= ID '<' ValueListNE '>' if (Lex.Lex() == tgtok::greater) { TokError("expected non-empty value list"); @@ -1061,13 +1056,13 @@ std::vector ValueList = ParseValueList(CurRec, Class); if (ValueList.empty()) return 0; - + if (Lex.getCode() != tgtok::greater) { TokError("expected '>' at end of value list"); return 0; } Lex.Lex(); // eat the '>' - + // Create the new record, set it as CurRec temporarily. static unsigned AnonCounter = 0; Record *NewRec = new Record("anonymous.val."+utostr(AnonCounter++),NameLoc); @@ -1080,15 +1075,15 @@ return 0; NewRec->resolveReferences(); Records.addDef(NewRec); - + // The result of the expression is a reference to the new record. return new DefInit(NewRec); - } + } case tgtok::l_brace: { // Value ::= '{' ValueList '}' SMLoc BraceLoc = Lex.getLoc(); Lex.Lex(); // eat the '{' std::vector Vals; - + if (Lex.getCode() != tgtok::r_brace) { Vals = ParseValueList(CurRec); if (Vals.empty()) return 0; @@ -1098,7 +1093,7 @@ return 0; } Lex.Lex(); // eat the '}' - + BitsInit *Result = new BitsInit(Vals.size()); for (unsigned i = 0, e = Vals.size(); i != e; ++i) { Init *Bit = Vals[i]->convertInitializerTo(new BitRecTy()); @@ -1114,23 +1109,24 @@ case tgtok::l_square: { // Value ::= '[' ValueList ']' Lex.Lex(); // eat the '[' std::vector Vals; - + RecTy *DeducedEltTy = 0; ListRecTy *GivenListTy = 0; - + if (ItemType != 0) { ListRecTy *ListType = dynamic_cast(ItemType); if (ListType == 0) { std::stringstream s; - s << "Type mismatch for list, expected list type, got " + s << "Type mismatch for list, expected list type, got " << ItemType->getAsString(); TokError(s.str()); } GivenListTy = ListType; - } + } if (Lex.getCode() != tgtok::r_square) { - Vals = ParseValueList(CurRec, 0, GivenListTy ? GivenListTy->getElementType() : 0); + Vals = ParseValueList(CurRec, 0, + GivenListTy ? GivenListTy->getElementType() : 0); if (Vals.empty()) return 0; } if (Lex.getCode() != tgtok::r_square) { @@ -1173,8 +1169,7 @@ TokError("Incompatible types in list elements"); return 0; } - } - else { + } else { EltTy = TArg->getType(); } } @@ -1196,8 +1191,7 @@ return 0; } DeducedEltTy = GivenListTy->getElementType(); - } - else { + } else { // Make sure the deduced type is compatible with the given type if (GivenListTy) { if (!EltTy->typeIsConvertibleTo(GivenListTy->getElementType())) { @@ -1207,7 +1201,7 @@ } DeducedEltTy = EltTy; } - + return new ListInit(Vals, DeducedEltTy); } case tgtok::l_paren: { // Value ::= '(' IDValue DagArgList ')' @@ -1218,13 +1212,12 @@ TokError("expected identifier in dag init"); return 0; } - + Init *Operator = 0; if (Lex.getCode() == tgtok::Id) { Operator = ParseIDValue(CurRec); if (Operator == 0) return 0; - } - else { + } else { Operator = ParseOperation(CurRec); if (Operator == 0) return 0; } @@ -1239,29 +1232,29 @@ OperatorName = Lex.getCurStrVal(); Lex.Lex(); // eat the VarName. } - + std::vector > DagArgs; if (Lex.getCode() != tgtok::r_paren) { DagArgs = ParseDagArgList(CurRec); if (DagArgs.empty()) return 0; } - + if (Lex.getCode() != tgtok::r_paren) { TokError("expected ')' in dag init"); return 0; } Lex.Lex(); // eat the ')' - + return new DagInit(Operator, OperatorName, DagArgs); break; } - + case tgtok::XCar: case tgtok::XCdr: case tgtok::XNull: case tgtok::XCast: // Value ::= !unop '(' Value ')' case tgtok::XConcat: - case tgtok::XSRA: + case tgtok::XSRA: case tgtok::XSRL: case tgtok::XSHL: case tgtok::XStrConcat: @@ -1273,7 +1266,7 @@ break; } } - + return R; } @@ -1287,7 +1280,7 @@ Init *TGParser::ParseValue(Record *CurRec, RecTy *ItemType) { Init *Result = ParseSimpleValue(CurRec, ItemType); if (Result == 0) return 0; - + // Parse the suffixes now if present. while (1) { switch (Lex.getCode()) { @@ -1297,7 +1290,7 @@ Lex.Lex(); // eat the '{' std::vector Ranges = ParseRangeList(); if (Ranges.empty()) return 0; - + // Reverse the bitlist. std::reverse(Ranges.begin(), Ranges.end()); Result = Result->convertInitializerBitRange(Ranges); @@ -1305,7 +1298,7 @@ Error(CurlyLoc, "Invalid bit range for value"); return 0; } - + // Eat the '}'. if (Lex.getCode() != tgtok::r_brace) { TokError("expected '}' at end of bit range list"); @@ -1319,13 +1312,13 @@ Lex.Lex(); // eat the '[' std::vector Ranges = ParseRangeList(); if (Ranges.empty()) return 0; - + Result = Result->convertInitListSlice(Ranges); if (Result == 0) { Error(SquareLoc, "Invalid range for list slice"); return 0; } - + // Eat the ']'. if (Lex.getCode() != tgtok::r_square) { TokError("expected ']' at end of list slice"); @@ -1355,14 +1348,14 @@ /// /// ParseDagArgList ::= Value (':' VARNAME)? /// ParseDagArgList ::= ParseDagArgList ',' Value (':' VARNAME)? -std::vector > +std::vector > TGParser::ParseDagArgList(Record *CurRec) { std::vector > Result; - + while (1) { Init *Val = ParseValue(CurRec); if (Val == 0) return std::vector >(); - + // If the variable name is present, add it. std::string VarName; if (Lex.getCode() == tgtok::colon) { @@ -1373,13 +1366,13 @@ VarName = Lex.getCurStrVal(); Lex.Lex(); // eat the VarName. } - + Result.push_back(std::make_pair(Val, VarName)); - + if (Lex.getCode() != tgtok::comma) break; - Lex.Lex(); // eat the ',' + Lex.Lex(); // eat the ',' } - + return Result; } @@ -1390,7 +1383,8 @@ /// /// ValueList ::= Value (',' Value) /// -std::vector TGParser::ParseValueList(Record *CurRec, Record *ArgsRec, RecTy *EltTy) { +std::vector TGParser::ParseValueList(Record *CurRec, Record *ArgsRec, + RecTy *EltTy) { std::vector Result; RecTy *ItemType = EltTy; unsigned int ArgN = 0; @@ -1403,16 +1397,16 @@ } Result.push_back(ParseValue(CurRec, ItemType)); if (Result.back() == 0) return std::vector(); - + while (Lex.getCode() == tgtok::comma) { Lex.Lex(); // Eat the comma - + if (ArgsRec != 0 && EltTy == 0) { const std::vector &TArgs = ArgsRec->getTemplateArgs(); if (ArgN >= TArgs.size()) { TokError("too many template arguments"); return std::vector(); - } + } const RecordVal *RV = ArgsRec->getValue(TArgs[ArgN]); assert(RV && "Template argument record not found??"); ItemType = RV->getType(); @@ -1421,12 +1415,11 @@ Result.push_back(ParseValue(CurRec, ItemType)); if (Result.back() == 0) return std::vector(); } - + return Result; } - /// ParseDeclaration - Read a declaration, returning the name of field ID, or an /// empty string on error. This can happen in a number of different context's, /// including within a def or in the template args for a def (which which case @@ -1437,24 +1430,24 @@ /// /// Declaration ::= FIELD? Type ID ('=' Value)? /// -std::string TGParser::ParseDeclaration(Record *CurRec, +std::string TGParser::ParseDeclaration(Record *CurRec, bool ParsingTemplateArgs) { // Read the field prefix if present. bool HasField = Lex.getCode() == tgtok::Field; if (HasField) Lex.Lex(); - + RecTy *Type = ParseType(); if (Type == 0) return ""; - + if (Lex.getCode() != tgtok::Id) { TokError("Expected identifier in declaration"); return ""; } - + SMLoc IdLoc = Lex.getLoc(); std::string DeclName = Lex.getCurStrVal(); Lex.Lex(); - + if (ParsingTemplateArgs) { if (CurRec) { DeclName = CurRec->getName() + ":" + DeclName; @@ -1464,11 +1457,11 @@ if (CurMultiClass) DeclName = CurMultiClass->Rec.getName() + "::" + DeclName; } - + // Add the value. if (AddValue(CurRec, IdLoc, RecordVal(DeclName, Type, HasField))) return ""; - + // If a value is present, parse it. if (Lex.getCode() == tgtok::equal) { Lex.Lex(); @@ -1478,7 +1471,7 @@ SetValue(CurRec, ValLoc, DeclName, std::vector(), Val)) return ""; } - + return DeclName; } @@ -1488,30 +1481,30 @@ /// these are the template args for a multiclass. /// /// TemplateArgList ::= '<' Declaration (',' Declaration)* '>' -/// +/// bool TGParser::ParseTemplateArgList(Record *CurRec) { assert(Lex.getCode() == tgtok::less && "Not a template arg list!"); Lex.Lex(); // eat the '<' - + Record *TheRecToAddTo = CurRec ? CurRec : &CurMultiClass->Rec; - + // Read the first declaration. std::string TemplArg = ParseDeclaration(CurRec, true/*templateargs*/); if (TemplArg.empty()) return true; - + TheRecToAddTo->addTemplateArg(TemplArg); - + while (Lex.getCode() == tgtok::comma) { Lex.Lex(); // eat the ',' - + // Read the following declarations. TemplArg = ParseDeclaration(CurRec, true/*templateargs*/); if (TemplArg.empty()) return true; TheRecToAddTo->addTemplateArg(TemplArg); } - + if (Lex.getCode() != tgtok::greater) return TokError("expected '>' at end of template argument list"); Lex.Lex(); // eat the '>'. @@ -1525,9 +1518,9 @@ /// BodyItem ::= LET ID OptionalBitList '=' Value ';' bool TGParser::ParseBodyItem(Record *CurRec) { if (Lex.getCode() != tgtok::Let) { - if (ParseDeclaration(CurRec, false).empty()) + if (ParseDeclaration(CurRec, false).empty()) return true; - + if (Lex.getCode() != tgtok::semi) return TokError("expected ';' after declaration"); Lex.Lex(); @@ -1537,33 +1530,33 @@ // LET ID OptionalRangeList '=' Value ';' if (Lex.Lex() != tgtok::Id) return TokError("expected field identifier after let"); - + SMLoc IdLoc = Lex.getLoc(); std::string FieldName = Lex.getCurStrVal(); Lex.Lex(); // eat the field name. - + std::vector BitList; - if (ParseOptionalBitList(BitList)) + if (ParseOptionalBitList(BitList)) return true; std::reverse(BitList.begin(), BitList.end()); - + if (Lex.getCode() != tgtok::equal) return TokError("expected '=' in let expression"); Lex.Lex(); // eat the '='. - + RecordVal *Field = CurRec->getValue(FieldName); if (Field == 0) return TokError("Value '" + FieldName + "' unknown!"); RecTy *Type = Field->getType(); - + Init *Val = ParseValue(CurRec, Type); if (Val == 0) return true; - + if (Lex.getCode() != tgtok::semi) return TokError("expected ';' after let expression"); Lex.Lex(); - + return SetValue(CurRec, IdLoc, FieldName, BitList, Val); } @@ -1580,12 +1573,12 @@ Lex.Lex(); return false; } - + if (Lex.getCode() != tgtok::l_brace) return TokError("Expected ';' or '{' to start body"); // Eat the '{'. Lex.Lex(); - + while (Lex.getCode() != tgtok::r_brace) if (ParseBodyItem(CurRec)) return true; @@ -1608,17 +1601,17 @@ // If there is a baseclass list, read it. if (Lex.getCode() == tgtok::colon) { Lex.Lex(); - + // Read all of the subclasses. SubClassReference SubClass = ParseSubClassReference(CurRec, false); while (1) { // Check for error. if (SubClass.Rec == 0) return true; - + // Add it. if (AddSubClass(CurRec, SubClass)) return true; - + if (Lex.getCode() != tgtok::comma) break; Lex.Lex(); // eat ','. SubClass = ParseSubClassReference(CurRec, false); @@ -1631,7 +1624,7 @@ if (SetValue(CurRec, LetStack[i][j].Loc, LetStack[i][j].Name, LetStack[i][j].Bits, LetStack[i][j].Value)) return true; - + return ParseBody(CurRec); } @@ -1644,14 +1637,14 @@ llvm::Record *TGParser::ParseDef(MultiClass *CurMultiClass) { SMLoc DefLoc = Lex.getLoc(); assert(Lex.getCode() == tgtok::Def && "Unknown tok"); - Lex.Lex(); // Eat the 'def' token. + Lex.Lex(); // Eat the 'def' token. // Parse ObjectName and make a record for it. Record *CurRec = new Record(ParseObjectName(), DefLoc); - + if (!CurMultiClass) { // Top-level def definition. - + // Ensure redefinition doesn't happen. if (Records.getDef(CurRec->getName())) { Error(DefLoc, "def '" + CurRec->getName() + "' already defined"); @@ -1668,13 +1661,13 @@ } CurMultiClass->DefPrototypes.push_back(CurRec); } - + if (ParseObjectBody(CurRec)) return 0; - + if (CurMultiClass == 0) // Def's in multiclasses aren't really defs. CurRec->resolveReferences(); - + // If ObjectBody has template arguments, it's an error. assert(CurRec->getTemplateArgs().empty() && "How'd this get template args?"); return CurRec; @@ -1688,10 +1681,10 @@ bool TGParser::ParseClass() { assert(Lex.getCode() == tgtok::Class && "Unexpected token!"); Lex.Lex(); - + if (Lex.getCode() != tgtok::Id) return TokError("expected class name after 'class' keyword"); - + Record *CurRec = Records.getClass(Lex.getCurStrVal()); if (CurRec) { // If the body was previously defined, this is an error. @@ -1705,7 +1698,7 @@ Records.addClass(CurRec); } Lex.Lex(); // eat the name. - + // If there are template args, parse them. if (Lex.getCode() == tgtok::less) if (ParseTemplateArgList(CurRec)) @@ -1723,7 +1716,7 @@ /// std::vector TGParser::ParseLetList() { std::vector Result; - + while (1) { if (Lex.getCode() != tgtok::Id) { TokError("expected identifier in let definition"); @@ -1731,29 +1724,29 @@ } std::string Name = Lex.getCurStrVal(); SMLoc NameLoc = Lex.getLoc(); - Lex.Lex(); // Eat the identifier. + Lex.Lex(); // Eat the identifier. // Check for an optional RangeList. std::vector Bits; - if (ParseOptionalRangeList(Bits)) + if (ParseOptionalRangeList(Bits)) return std::vector(); std::reverse(Bits.begin(), Bits.end()); - + if (Lex.getCode() != tgtok::equal) { TokError("expected '=' in let expression"); return std::vector(); } Lex.Lex(); // eat the '='. - + Init *Val = ParseValue(0); if (Val == 0) return std::vector(); - + // Now that we have everything, add the record. Result.push_back(LetRecord(Name, Bits, Val, NameLoc)); - + if (Lex.getCode() != tgtok::comma) return Result; - Lex.Lex(); // eat the comma. + Lex.Lex(); // eat the comma. } } @@ -1766,7 +1759,7 @@ bool TGParser::ParseTopLevelLet() { assert(Lex.getCode() == tgtok::Let && "Unexpected token"); Lex.Lex(); - + // Add this entry to the let stack. std::vector LetInfo = ParseLetList(); if (LetInfo.empty()) return true; @@ -1775,7 +1768,7 @@ if (Lex.getCode() != tgtok::In) return TokError("expected 'in' at end of top-level 'let'"); Lex.Lex(); - + // If this is a scalar let, just handle it now if (Lex.getCode() != tgtok::l_brace) { // LET LetList IN Object @@ -1785,18 +1778,18 @@ SMLoc BraceLoc = Lex.getLoc(); // Otherwise, this is a group let. Lex.Lex(); // eat the '{'. - + // Parse the object list. if (ParseObjectList()) return true; - + if (Lex.getCode() != tgtok::r_brace) { TokError("expected '}' at end of top level let command"); return Error(BraceLoc, "to match this '{'"); } Lex.Lex(); } - + // Outside this let scope, this let block is not active. LetStack.pop_back(); return false; @@ -1807,15 +1800,15 @@ /// MultiClassDef ::= DefInst /// bool TGParser::ParseMultiClassDef(MultiClass *CurMC) { - if (Lex.getCode() != tgtok::Def) + if (Lex.getCode() != tgtok::Def) return TokError("expected 'def' in multiclass body"); Record *D = ParseDef(CurMC); if (D == 0) return true; - + // Copy the template arguments for the multiclass into the def. const std::vector &TArgs = CurMC->Rec.getTemplateArgs(); - + for (unsigned i = 0, e = TArgs.size(); i != e; ++i) { const RecordVal *RV = CurMC->Rec.getValue(TArgs[i]); assert(RV && "Template arg doesn't exist?"); @@ -1837,13 +1830,13 @@ if (Lex.getCode() != tgtok::Id) return TokError("expected identifier after multiclass for name"); std::string Name = Lex.getCurStrVal(); - + if (MultiClasses.count(Name)) return TokError("multiclass '" + Name + "' already defined"); - + CurMultiClass = MultiClasses[Name] = new MultiClass(Name, Lex.getLoc()); Lex.Lex(); // Eat the identifier. - + // If there are template args, parse them. if (Lex.getCode() == tgtok::less) if (ParseTemplateArgList(0)) @@ -1877,23 +1870,21 @@ if (Lex.getCode() != tgtok::l_brace) { if (!inherits) return TokError("expected '{' in multiclass definition"); + else if (Lex.getCode() != tgtok::semi) + return TokError("expected ';' in multiclass definition"); else - if (Lex.getCode() != tgtok::semi) - return TokError("expected ';' in multiclass definition"); - else - Lex.Lex(); // eat the ';'. - } - else { + Lex.Lex(); // eat the ';'. + } else { if (Lex.Lex() == tgtok::r_brace) // eat the '{'. return TokError("multiclass must contain at least one def"); - + while (Lex.getCode() != tgtok::r_brace) if (ParseMultiClassDef(CurMultiClass)) return true; - + Lex.Lex(); // eat the '}'. } - + CurMultiClass = 0; return false; } @@ -1906,12 +1897,12 @@ assert(Lex.getCode() == tgtok::Defm && "Unexpected token!"); if (Lex.Lex() != tgtok::Id) // eat the defm. return TokError("expected identifier after defm"); - + SMLoc DefmPrefixLoc = Lex.getLoc(); std::string DefmPrefix = Lex.getCurStrVal(); if (Lex.Lex() != tgtok::colon) return TokError("expected ':' after defm identifier"); - + // eat the colon. Lex.Lex(); @@ -1926,7 +1917,7 @@ // template parameters. MultiClass *MC = MultiClasses[Ref.Rec->getName()]; assert(MC && "Didn't lookup multiclass correctly?"); - std::vector &TemplateVals = Ref.TemplateArgs; + std::vector &TemplateVals = Ref.TemplateArgs; // Verify that the correct number of template arguments were specified. const std::vector &TArgs = MC->Rec.getTemplateArgs(); @@ -1943,8 +1934,7 @@ std::string::size_type idx = DefName.find("#NAME#"); if (idx != std::string::npos) { DefName.replace(idx, 6, DefmPrefix); - } - else { + } else { // Add the suffix to the defm name to get the new name. DefName = DefmPrefix + DefName; } @@ -1991,8 +1981,8 @@ // Ensure redefinition doesn't happen. if (Records.getDef(CurRec->getName())) - return Error(DefmPrefixLoc, "def '" + CurRec->getName() + - "' already defined, instantiating defm with subdef '" + + return Error(DefmPrefixLoc, "def '" + CurRec->getName() + + "' already defined, instantiating defm with subdef '" + DefProto->getName() + "'"); Records.addDef(CurRec); CurRec->resolveReferences(); @@ -2008,7 +1998,7 @@ if (Lex.getCode() != tgtok::semi) return TokError("expected ';' at end of defm"); Lex.Lex(); - + return false; } @@ -2040,15 +2030,14 @@ return false; } - bool TGParser::ParseFile() { Lex.Lex(); // Prime the lexer. if (ParseObjectList()) return true; - + // If we have unread input at the end of the file, report it. if (Lex.getCode() == tgtok::Eof) return false; - + return TokError("Unexpected input at top level"); } From eocallaghan at auroraux.org Sun Nov 22 05:45:45 2009 From: eocallaghan at auroraux.org (Edward O'Callaghan) Date: Sun, 22 Nov 2009 11:45:45 -0000 Subject: [llvm-commits] [llvm] r89584 - in /llvm/trunk/test/CodeGen: ARM/bic.ll ARM/fptoint.ll ARM/fsubs.ll ARM/mls.ll PIC16/2009-07-17-PR4566-pic16.ll PowerPC/bswap-load-store.ll X86/2009-03-13-PHIElimBug.ll X86/2009-03-16-PHIElimInLPad.ll X86/fp_constant_op.ll X86/tailcall-stackalign.ll X86/trunc-to-bool.ll Message-ID: <200911221145.nAMBjj49017745@zion.cs.uiuc.edu> Author: evocallaghan Date: Sun Nov 22 05:45:44 2009 New Revision: 89584 URL: http://llvm.org/viewvc/llvm-project?rev=89584&view=rev Log: Convert a few tests to FileCheck for PR5307. Modified: llvm/trunk/test/CodeGen/ARM/bic.ll llvm/trunk/test/CodeGen/ARM/fptoint.ll llvm/trunk/test/CodeGen/ARM/fsubs.ll llvm/trunk/test/CodeGen/ARM/mls.ll llvm/trunk/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll llvm/trunk/test/CodeGen/PowerPC/bswap-load-store.ll llvm/trunk/test/CodeGen/X86/2009-03-13-PHIElimBug.ll llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll llvm/trunk/test/CodeGen/X86/fp_constant_op.ll llvm/trunk/test/CodeGen/X86/tailcall-stackalign.ll llvm/trunk/test/CodeGen/X86/trunc-to-bool.ll Modified: llvm/trunk/test/CodeGen/ARM/bic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bic.ll?rev=89584&r1=89583&r2=89584&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/bic.ll (original) +++ llvm/trunk/test/CodeGen/ARM/bic.ll Sun Nov 22 05:45:44 2009 @@ -6,8 +6,12 @@ ret i32 %tmp1 } +; CHECK: bic r0, r0, r1 + define i32 @f2(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 %tmp1 = and i32 %tmp, %a ret i32 %tmp1 } + +; CHECK: bic r0, r0, r1 Modified: llvm/trunk/test/CodeGen/ARM/fptoint.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fptoint.ll?rev=89584&r1=89583&r2=89584&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fptoint.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fptoint.ll Sun Nov 22 05:45:44 2009 @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | grep -E {vmov\\W*r\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | not grep fmrrd +; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s @i = weak global i32 0 ; [#uses=2] @u = weak global i32 0 ; [#uses=2] @@ -45,3 +44,7 @@ store i16 %tmp, i16* null ret void } + +; CHECK: vmov d0, r0, r1 +; CHECK-NOT: fmrrd + Modified: llvm/trunk/test/CodeGen/ARM/fsubs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fsubs.ll?rev=89584&r1=89583&r2=89584&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fsubs.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fsubs.ll Sun Nov 22 05:45:44 2009 @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vsub.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vsub.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vsub.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 define float @test(float %a, float %b) { entry: @@ -8,3 +8,6 @@ ret float %0 } +; VFP2: vsub.f32 s0, s1, s0 +; NFP1: vsub.f32 d0, d1, d0 +; NFP0: vsub.f32 s0, s1, s0 Modified: llvm/trunk/test/CodeGen/ARM/mls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/mls.ll?rev=89584&r1=89583&r2=89584&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/mls.ll (original) +++ llvm/trunk/test/CodeGen/ARM/mls.ll Sun Nov 22 05:45:44 2009 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6t2 | grep {mls\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1 +; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s define i32 @f1(i32 %a, i32 %b, i32 %c) { %tmp1 = mul i32 %a, %b @@ -12,3 +12,5 @@ %tmp2 = sub i32 %tmp1, %c ret i32 %tmp2 } + +; CHECK: mls r0, r0, r1, r2 Modified: llvm/trunk/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll?rev=89584&r1=89583&r2=89584&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll (original) +++ llvm/trunk/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll Sun Nov 22 05:45:44 2009 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=pic16 | grep {movf \\+ at i + 0, \\+W} +; RUN: llc < %s -march=pic16 | FileCheck %s target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-f32:32:32" target triple = "pic16-" @@ -27,3 +27,5 @@ store i8 %conv8, i8* %tmp9 ret void } + +; CHECK: movf @i + 0, W Modified: llvm/trunk/test/CodeGen/PowerPC/bswap-load-store.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/bswap-load-store.ll?rev=89584&r1=89583&r2=89584&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/bswap-load-store.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/bswap-load-store.ll Sun Nov 22 05:45:44 2009 @@ -1,11 +1,6 @@ -; RUN: llc < %s -march=ppc32 | \ -; RUN: grep {stwbrx\\|lwbrx\\|sthbrx\\|lhbrx} | count 4 -; RUN: llc < %s -march=ppc32 | not grep rlwinm -; RUN: llc < %s -march=ppc32 | not grep rlwimi -; RUN: llc < %s -march=ppc64 | \ -; RUN: grep {stwbrx\\|lwbrx\\|sthbrx\\|lhbrx} | count 4 -; RUN: llc < %s -march=ppc64 | not grep rlwinm -; RUN: llc < %s -march=ppc64 | not grep rlwimi +; RUN: llc < %s -march=ppc32 | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -march=ppc64 | FileCheck %s -check-prefix=X64 + define void @STWBRX(i32 %i, i8* %ptr, i32 %off) { %tmp1 = getelementptr i8* %ptr, i32 %off ; [#uses=1] @@ -43,3 +38,18 @@ declare i16 @llvm.bswap.i16(i16) + +; X32: stwbrx 3, 4, 5 +; X32: lwbrx 3, 3, 4 +; X32: sthbrx 3, 4, 5 +; X32: lhbrx 3, 3, 4 +; X32-NOT: rlwinm +; X32-NOT: rlwimi + +; X32: stwbrx 3, 4, 5 +; X32: lwbrx 3, 3, 4 +; X32: sthbrx 3, 4, 5 +; X32: lhbrx 3, 3, 4 +; X64-NOT: rlwinm +; X64-NOT: rlwimi + Modified: llvm/trunk/test/CodeGen/X86/2009-03-13-PHIElimBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-13-PHIElimBug.ll?rev=89584&r1=89583&r2=89584&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-03-13-PHIElimBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-03-13-PHIElimBug.ll Sun Nov 22 05:45:44 2009 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep -A 2 {call.*f} | grep movl +; RUN: llc < %s -march=x86 | FileCheck %s ; Check the register copy comes after the call to f and before the call to g ; PR3784 @@ -26,3 +26,7 @@ %y = phi i32 [ %a, %entry ], [ %aa, %cont ] ; [#uses=1] ret i32 %y } + +; CHECK: call{{.*}}f +; CHECK-NEXT: Llabel1: +; CHECK-NEXT: movl %eax, %esi Modified: llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll?rev=89584&r1=89583&r2=89584&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll Sun Nov 22 05:45:44 2009 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -asm-verbose | grep -A 1 lpad | grep Llabel +; RUN: llc < %s -march=x86 -asm-verbose | FileCheck %s ; Check that register copies in the landing pad come after the EH_LABEL declare i32 @f() @@ -19,3 +19,6 @@ %v = phi i32 [ %x, %entry ], [ %a, %cont ] ; [#uses=1] ret i32 %v } + +; CHECK: lpad +; CHECK-NEXT: Llabel Modified: llvm/trunk/test/CodeGen/X86/fp_constant_op.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp_constant_op.ll?rev=89584&r1=89583&r2=89584&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fp_constant_op.ll (original) +++ llvm/trunk/test/CodeGen/X86/fp_constant_op.ll Sun Nov 22 05:45:44 2009 @@ -1,6 +1,4 @@ -; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=i486 | \ -; RUN: grep {fadd\\|fsub\\|fdiv\\|fmul} | not grep -i ST - +; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=i486 | FileCheck %s ; Test that the load of the constant is folded into the operation. @@ -8,11 +6,14 @@ %tmp.1 = fadd double %P, 1.230000e+02 ; [#uses=1] ret double %tmp.1 } +; CHECK: fadd {{[^sS][^tT]}} +; CHECK: fadd {{[^sS][^tT]}} define double @foo_mul(double %P) { %tmp.1 = fmul double %P, 1.230000e+02 ; [#uses=1] ret double %tmp.1 } +; CHECK: fmul {{[^sS][^tT]}} define double @foo_sub(double %P) { %tmp.1 = fsub double %P, 1.230000e+02 ; [#uses=1] @@ -33,3 +34,9 @@ %tmp.1 = fdiv double 1.230000e+02, %P ; [#uses=1] ret double %tmp.1 } + + +; CHECK: fsub {{[^sS][^tT]}} +; CHECK: fdiv {{[^sS][^tT]}} +; CHECK: fdiv {{[^sS][^tT]}} + Modified: llvm/trunk/test/CodeGen/X86/tailcall-stackalign.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tailcall-stackalign.ll?rev=89584&r1=89583&r2=89584&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/tailcall-stackalign.ll (original) +++ llvm/trunk/test/CodeGen/X86/tailcall-stackalign.ll Sun Nov 22 05:45:44 2009 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i686-unknown-linux -tailcallopt | grep -A 1 call | grep -A 1 tailcaller | grep subl | grep 12 +; RUN: llc < %s -mtriple=i686-unknown-linux -tailcallopt | FileCheck %s ; Linux has 8 byte alignment so the params cause stack size 20 when tailcallopt ; is enabled, ensure that a normal fastcc call has matching stack size @@ -19,6 +19,5 @@ ret i32 0 } - - - +; CHECK: call tailcaller +; CHECK-NEXT: subl $12 Modified: llvm/trunk/test/CodeGen/X86/trunc-to-bool.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/trunc-to-bool.ll?rev=89584&r1=89583&r2=89584&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/trunc-to-bool.ll (original) +++ llvm/trunk/test/CodeGen/X86/trunc-to-bool.ll Sun Nov 22 05:45:44 2009 @@ -1,13 +1,13 @@ ; An integer truncation to i1 should be done with an and instruction to make ; sure only the LSBit survives. Test that this is the case both for a returned ; value and as the operand of a branch. -; RUN: llc < %s -march=x86 | grep {\\(and\\)\\|\\(test.*\\\$1\\)} | \ -; RUN: count 5 +; RUN: llc < %s -march=x86 | FileCheck %s define i1 @test1(i32 %X) zeroext { %Y = trunc i32 %X to i1 ret i1 %Y } +; CHECK: andl $1, %eax define i1 @test2(i32 %val, i32 %mask) { entry: @@ -20,6 +20,7 @@ ret_false: ret i1 false } +; CHECK: testb $1, %al define i32 @test3(i8* %ptr) { %val = load i8* %ptr @@ -30,6 +31,7 @@ cond_false: ret i32 42 } +; CHECK: testb $1, %al define i32 @test4(i8* %ptr) { %tmp = ptrtoint i8* %ptr to i1 @@ -39,6 +41,7 @@ cond_false: ret i32 42 } +; CHECK: testb $1, %al define i32 @test6(double %d) { %tmp = fptosi double %d to i1 @@ -48,4 +51,4 @@ cond_false: ret i32 42 } - +; CHECK: testb $1, %al From eocallaghan at auroraux.org Sun Nov 22 06:50:05 2009 From: eocallaghan at auroraux.org (Edward O'Callaghan) Date: Sun, 22 Nov 2009 12:50:05 -0000 Subject: [llvm-commits] [llvm] r89586 - in /llvm/trunk/test/CodeGen: ARM/fptoint.ll PowerPC/bswap-load-store.ll X86/fp_constant_op.ll Message-ID: <200911221250.nAMCo5nI019541@zion.cs.uiuc.edu> Author: evocallaghan Date: Sun Nov 22 06:50:05 2009 New Revision: 89586 URL: http://llvm.org/viewvc/llvm-project?rev=89586&view=rev Log: Fix for bad FileCheck converts in revision 89584. Modified: llvm/trunk/test/CodeGen/ARM/fptoint.ll llvm/trunk/test/CodeGen/PowerPC/bswap-load-store.ll llvm/trunk/test/CodeGen/X86/fp_constant_op.ll Modified: llvm/trunk/test/CodeGen/ARM/fptoint.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fptoint.ll?rev=89586&r1=89585&r2=89586&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fptoint.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fptoint.ll Sun Nov 22 06:50:05 2009 @@ -44,7 +44,6 @@ store i16 %tmp, i16* null ret void } - -; CHECK: vmov d0, r0, r1 -; CHECK-NOT: fmrrd +; CHECK: foo9: +; CHECK: vmov r0, s0 Modified: llvm/trunk/test/CodeGen/PowerPC/bswap-load-store.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/bswap-load-store.ll?rev=89586&r1=89585&r2=89586&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/bswap-load-store.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/bswap-load-store.ll Sun Nov 22 06:50:05 2009 @@ -39,17 +39,13 @@ declare i16 @llvm.bswap.i16(i16) -; X32: stwbrx 3, 4, 5 -; X32: lwbrx 3, 3, 4 -; X32: sthbrx 3, 4, 5 -; X32: lhbrx 3, 3, 4 -; X32-NOT: rlwinm -; X32-NOT: rlwimi +; X32: stwbrx +; X32: lwbrx +; X32: sthbrx +; X32: lhbrx -; X32: stwbrx 3, 4, 5 -; X32: lwbrx 3, 3, 4 -; X32: sthbrx 3, 4, 5 -; X32: lhbrx 3, 3, 4 -; X64-NOT: rlwinm -; X64-NOT: rlwimi +; X64: stwbrx +; X64: lwbrx +; X64: sthbrx +; X64: lhbrx Modified: llvm/trunk/test/CodeGen/X86/fp_constant_op.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp_constant_op.ll?rev=89586&r1=89585&r2=89586&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fp_constant_op.ll (original) +++ llvm/trunk/test/CodeGen/X86/fp_constant_op.ll Sun Nov 22 06:50:05 2009 @@ -6,37 +6,41 @@ %tmp.1 = fadd double %P, 1.230000e+02 ; [#uses=1] ret double %tmp.1 } -; CHECK: fadd {{[^sS][^tT]}} -; CHECK: fadd {{[^sS][^tT]}} +; CHECK: foo_add: +; CHECK: fadd DWORD PTR define double @foo_mul(double %P) { %tmp.1 = fmul double %P, 1.230000e+02 ; [#uses=1] ret double %tmp.1 } -; CHECK: fmul {{[^sS][^tT]}} +; CHECK: foo_mul: +; CHECK: fmul DWORD PTR define double @foo_sub(double %P) { %tmp.1 = fsub double %P, 1.230000e+02 ; [#uses=1] ret double %tmp.1 } +; CHECK: foo_sub: +; CHECK: fadd DWORD PTR define double @foo_subr(double %P) { %tmp.1 = fsub double 1.230000e+02, %P ; [#uses=1] ret double %tmp.1 } +; CHECK: foo_subr: +; CHECK: fsub QWORD PTR define double @foo_div(double %P) { %tmp.1 = fdiv double %P, 1.230000e+02 ; [#uses=1] ret double %tmp.1 } +; CHECK: foo_div: +; CHECK: fdiv DWORD PTR define double @foo_divr(double %P) { %tmp.1 = fdiv double 1.230000e+02, %P ; [#uses=1] ret double %tmp.1 } - - -; CHECK: fsub {{[^sS][^tT]}} -; CHECK: fdiv {{[^sS][^tT]}} -; CHECK: fdiv {{[^sS][^tT]}} +; CHECK: foo_divr: +; CHECK: fdiv QWORD PTR From eocallaghan at auroraux.org Sun Nov 22 07:09:48 2009 From: eocallaghan at auroraux.org (Edward O'Callaghan) Date: Sun, 22 Nov 2009 13:09:48 -0000 Subject: [llvm-commits] [llvm] r89588 - /llvm/trunk/test/CodeGen/ARM/bic.ll Message-ID: <200911221309.nAMD9m0u020100@zion.cs.uiuc.edu> Author: evocallaghan Date: Sun Nov 22 07:09:48 2009 New Revision: 89588 URL: http://llvm.org/viewvc/llvm-project?rev=89588&view=rev Log: Forgot to alter RUN line when converting to FileCheck. Modified: llvm/trunk/test/CodeGen/ARM/bic.ll Modified: llvm/trunk/test/CodeGen/ARM/bic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bic.ll?rev=89588&r1=89587&r2=89588&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/bic.ll (original) +++ llvm/trunk/test/CodeGen/ARM/bic.ll Sun Nov 22 07:09:48 2009 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | grep {bic\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*} | count 2 +; RUN: llc < %s -march=arm | FileCheck %s define i32 @f1(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 From benny.kra at googlemail.com Sun Nov 22 07:16:36 2009 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Sun, 22 Nov 2009 13:16:36 -0000 Subject: [llvm-commits] [llvm] r89589 - /llvm/trunk/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll Message-ID: <200911221316.nAMDGapk020302@zion.cs.uiuc.edu> Author: d0k Date: Sun Nov 22 07:16:36 2009 New Revision: 89589 URL: http://llvm.org/viewvc/llvm-project?rev=89589&view=rev Log: Convert test to FileCheck. Modified: llvm/trunk/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll Modified: llvm/trunk/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll?rev=89589&r1=89588&r2=89589&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll Sun Nov 22 07:16:36 2009 @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=x86 -enable-eh -asm-verbose -o - | \ -; RUN: grep -A 3 {Llabel138.*Region start} | grep {3.*Action} +; RUN: llc < %s -march=x86 -enable-eh -asm-verbose -o - | FileCheck %s ; PR1422 ; PR1508 @@ -2864,3 +2863,8 @@ declare i32 @memcmp(i8*, i8*, i32, ...) declare void @report__result() + +; CHECK: {{Llabel138.*Region start}} +; CHECK-NEXT: Region length +; CHECK-NEXT: Landing pad +; CHECK-NEXT: {{3.*Action}} From clattner at apple.com Sun Nov 22 07:38:02 2009 From: clattner at apple.com (Chris Lattner) Date: Sun, 22 Nov 2009 05:38:02 -0800 Subject: [llvm-commits] [llvm] r89421 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp In-Reply-To: <4B080CEF.5060301@free.fr> References: <200911200050.nAK0or7J026222@zion.cs.uiuc.edu> <4B068327.1070103@free.fr> <784C47FB-FB86-404E-B39F-8EAF9C4A98E0@apple.com> <4B080CEF.5060301@free.fr> Message-ID: <6A5CF08E-94EF-4893-81CC-5AEF0A19EB25@apple.com> On Nov 21, 2009, at 7:53 AM, Duncan Sands wrote: > Hi Chris, > >>> I think this is wrong, consider the following pseudocode example: >> While this example is "possible" I really don't think this is worth worrying about. It is not valid C code, is not likely to exist in practice, etc. Beyond that, comparison against null is really common and we really do want "nocapture" in this cases. > > well, it's a slippery slope :) Dan later changed this to only allow > comparisons against malloc return values and other noalias function > results. Is such paranoia really worthwhile? Doing such a thing introduces an 'abstraction penalty' where malloc wrappers now get pessimized where direct calls to malloc don't. -Chris From clattner at apple.com Sun Nov 22 08:00:04 2009 From: clattner at apple.com (Chris Lattner) Date: Sun, 22 Nov 2009 06:00:04 -0800 Subject: [llvm-commits] [llvm] r89403 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp In-Reply-To: <200911192310.nAJNASND022655@zion.cs.uiuc.edu> References: <200911192310.nAJNASND022655@zion.cs.uiuc.edu> Message-ID: On Nov 19, 2009, at 3:10 PM, Jim Grosbach wrote: > Author: grosbach > Date: Thu Nov 19 17:10:28 2009 > New Revision: 89403 > > URL: http://llvm.org/viewvc/llvm-project?rev=89403&view=rev > Log: > When placing constant islands and adjusting for alignment padding, inline > assembly can confuse things utterly, as it's assumed that instructions in > inline assembly are 4 bytes wide. For Thumb mode, that's often not true, > so the calculations for when alignment padding will be present get thrown off, > ultimately leading to out of range constant pool entry references. Making > more conservative assumptions that padding may be necessary when inline asm > is present avoids this situation. Are you sure that this is the right thing to do? GCC inline asm precisely specifies how the size of an inline asm is computed: http://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#Extended-Asm (6.39.1) If some inline asm isn't working with this algorithm, then the inline asm is wrong and should be fixed. -Chris From clattner at apple.com Sun Nov 22 08:03:04 2009 From: clattner at apple.com (Chris Lattner) Date: Sun, 22 Nov 2009 06:03:04 -0800 Subject: [llvm-commits] [llvm] r89516 - in /llvm/trunk: include/llvm/Target/SubtargetFeature.h lib/Target/SubtargetFeature.cpp tools/lto/LTOCodeGenerator.cpp In-Reply-To: <200911210000.nAL003q6027547@zion.cs.uiuc.edu> References: <200911210000.nAL003q6027547@zion.cs.uiuc.edu> Message-ID: On Nov 20, 2009, at 4:00 PM, Viktor Kutuzov wrote: > Author: vkutuzov > Date: Fri Nov 20 18:00:02 2009 > New Revision: 89516 > > URL: http://llvm.org/viewvc/llvm-project?rev=89516&view=rev > Log: > Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods. Ok, a couple comments below: > +++ llvm/trunk/include/llvm/Target/SubtargetFeature.h Fri Nov 20 18:00:02 2009 > @@ -22,6 +22,7 @@ > #include > #include > #include "llvm/ADT/Triple.h" > +#include "llvm/Support/CommandLine.h" > #include "llvm/System/DataTypes.h" Please drop this #include. > @@ -93,6 +94,12 @@ > /// Adding Features. > void AddFeature(const std::string &String, bool IsEnabled = true); > > + /// Add a set of features from the comma-separated string. > + void AddFeatures(const std::string &String); This should take a StringRef instead of std::string. > + > + /// Add a set of features from the parsed command line parameters. > + void AddFeatures(const cl::list &List); cl::list inherits from std::vector, so you should be able to pass in a std::vector directly. However, it would be much much better to expose this as taking an array of StringRef's and require the caller to do the unpacking. -Chris From sabre at nondot.org Sun Nov 22 08:06:47 2009 From: sabre at nondot.org (Chris Lattner) Date: Sun, 22 Nov 2009 06:06:47 -0800 Subject: [llvm-commits] [llvm] r89187 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h In-Reply-To: <32E102EC-EC9F-4956-9B11-3D55E67481CE@apple.com> References: <701493E3-E27B-4EAB-9666-99B2F6EA01BC@apple.com> <4F246C8B-FDED-4DDA-95F1-DE2D11F216CB@apple.com> <84E8057C-E9D9-443F-9CC1-549BFC1DE82C@nondot.org> <32E102EC-EC9F-4956-9B11-3D55E67481CE@apple.com> Message-ID: On Nov 21, 2009, at 1:01 PM, Bob Wilson wrote: > > On Nov 21, 2009, at 6:49 AM, Chris Lattner wrote: >> >> This is a completely acceptable tradeoff, I just want it factored the right way. I'd be very happy if the code in taildupe said "if the block ends in an indirect goto operation, and if "it is profitable to dupliate indirect gotos for the target" then increase the threshold a bit. I don't like asking the target how much to increase the threshold. "How much to increase the threshold" is not asking a target property. Asking "is it profitable to duplicate indirect gotos" is. > > Factoring it in the way you suggest sounds good to me. I will do that. Thanks Bob. > I see your point about switches being used for interpreters. I wasn't trying to say otherwise. I'm just not sure that this transformation will be a win for switches in general, and switches This won't kick in for jump table switches because of the extra range check before them. However, if that branch got jump threaded or deleted as redundant in the future, the xform could/should apply in theory. > are used for lots of things besides interpreters. My experience with indirect branches is that they're used much less frequently and interpreters are the most common use. I was trying to reduce the risk of breaking something by limiting this change to the one specific case that I know about. Don't live in fear, do the right thing :). If it turns out to cause a problem in the future, we can track it down and reevaluate it then. > I'm not sure we've really solved this problem yet, anyway. The current solution seems to be very sensitive to minor changes in the code. We run tail merging very late, so small differences in register allocation, scheduling, etc. will change what tail merging does. If tail merging is very successful, then tail duplication has to be very aggressive to get the result we need. For example, if tail merging creates a new block with a common tail of a dozen instructions, and that block is a predecessor of the indirect branch block, it is no problem to tail duplicate the indirect branch into the common tail, but what we really need is to get the new "common tail + indirect branch" duplicated back one more level. It won't help to tell tail merging not to merge blocks ending with indirect branches, because the indirect branch is in a separate block when we run tail merging. I suppose we could disable tail merging entirely at -O3, but I'm still trying to better understand the situation before proposing anything like that. I don't know any of the details, but it sounds like the code should be considering the complete tail length (in # instrs), ignoring the fact that the tail may be broken across multiple blocks. If you really want to handle indbr's, maybe start from indbrs scanning backward through all the fall throughs and look for any uncond brs that jump into the tail at any point. At that case you could consider duplicating the entire tail. If taildup is useful for other cases that are more than one instruction, it seems reasonable to make the algorithm always work this way. -Chris From clattner at apple.com Sun Nov 22 08:09:31 2009 From: clattner at apple.com (Chris Lattner) Date: Sun, 22 Nov 2009 06:09:31 -0800 Subject: [llvm-commits] [llvm] r89530 - in /llvm/trunk: include/llvm/CodeGen/LiveVariables.h lib/CodeGen/LiveVariables.cpp lib/CodeGen/PHIElimination.cpp lib/CodeGen/PHIElimination.h In-Reply-To: <200911210205.nAL25M36031984@zion.cs.uiuc.edu> References: <200911210205.nAL25M36031984@zion.cs.uiuc.edu> Message-ID: <58E5E7B6-3416-472E-8C1A-363DDDE5A930@apple.com> On Nov 20, 2009, at 6:05 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Fri Nov 20 20:05:21 2009 > New Revision: 89530 > > URL: http://llvm.org/viewvc/llvm-project?rev=89530&view=rev > Log: > Be more clever about calculating live variables through new basic blocks. > > When splitting a critical edge, the registers live through the edge are: > > - Used in a PHI instruction, or > - Live out from the predecessor, and > - Live in to the successor. > > This allows the coalescer to eliminate even more phi joins. Hi Jakob, I haven't looked at the code at all, but I want to bring up one subtlety of critical edge splitting. In switches which have multiple edges to the same destination (on different values), these edges are always critical. However, they should be split together as a unit, not individually. I don't know if your code considers this or not, but this is the idea behind the "SplitEdgeNicely" logic that appears in a couple places. -Chris > > Modified: > llvm/trunk/include/llvm/CodeGen/LiveVariables.h > llvm/trunk/lib/CodeGen/LiveVariables.cpp > llvm/trunk/lib/CodeGen/PHIElimination.cpp > llvm/trunk/lib/CodeGen/PHIElimination.h > > Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveVariables.h?rev=89530&r1=89529&r2=89530&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/CodeGen/LiveVariables.h (original) > +++ llvm/trunk/include/llvm/CodeGen/LiveVariables.h Fri Nov 20 20:05:21 2009 > @@ -107,6 +107,13 @@ > /// findKill - Find a kill instruction in MBB. Return NULL if none is found. > MachineInstr *findKill(const MachineBasicBlock *MBB) const; > > + /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through > + /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in > + /// MBB, it is not considered live in. > + bool isLiveIn(const MachineBasicBlock &MBB, > + unsigned Reg, > + MachineRegisterInfo &MRI); > + > void dump() const; > }; > > @@ -267,11 +274,17 @@ > void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, > MachineInstr *MI); > > - /// addNewBlock - Add a new basic block BB as an empty succcessor to > - /// DomBB. All variables that are live out of DomBB will be marked as passing > - /// live through BB. This method assumes that the machine code is still in SSA > - /// form. > - void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB); > + bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) { > + return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI); > + } > + > + /// addNewBlock - Add a new basic block BB between DomBB and SuccBB. All > + /// variables that are live out of DomBB and live into SuccBB will be marked > + /// as passing live through BB. This method assumes that the machine code is > + /// still in SSA form. > + void addNewBlock(MachineBasicBlock *BB, > + MachineBasicBlock *DomBB, > + MachineBasicBlock *SuccBB); > }; > > } // End llvm namespace > > Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=89530&r1=89529&r2=89530&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original) > +++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Fri Nov 20 20:05:21 2009 > @@ -656,35 +656,45 @@ > .push_back(BBI->getOperand(i).getReg()); > } > > +bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB, > + unsigned Reg, > + MachineRegisterInfo &MRI) { > + unsigned Num = MBB.getNumber(); > + > + // Reg is live-through. > + if (AliveBlocks.test(Num)) > + return true; > + > + // Registers defined in MBB cannot be live in. > + const MachineInstr *Def = MRI.getVRegDef(Reg); > + if (Def && Def->getParent() == &MBB) > + return false; > + > + // Reg was not defined in MBB, was it killed here? > + return findKill(&MBB); > +} > + > /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All > /// variables that are live out of DomBB will be marked as passing live through > /// BB. > void LiveVariables::addNewBlock(MachineBasicBlock *BB, > - MachineBasicBlock *DomBB) { > + MachineBasicBlock *DomBB, > + MachineBasicBlock *SuccBB) { > const unsigned NumNew = BB->getNumber(); > - const unsigned NumDom = DomBB->getNumber(); > + > + // All registers used by PHI nodes in SuccBB must be live through BB. > + for (MachineBasicBlock::const_iterator BBI = SuccBB->begin(), > + BBE = SuccBB->end(); > + BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) > + for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) > + if (BBI->getOperand(i+1).getMBB() == BB) > + getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew); > > // Update info for all live variables > for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister, > E = MRI->getLastVirtReg()+1; Reg != E; ++Reg) { > VarInfo &VI = getVarInfo(Reg); > - > - // Anything live through DomBB is also live through BB. > - if (VI.AliveBlocks.test(NumDom)) { > + if (!VI.AliveBlocks.test(NumNew) && VI.isLiveIn(*SuccBB, Reg, *MRI)) > VI.AliveBlocks.set(NumNew); > - continue; > - } > - > - // Variables not defined in DomBB cannot be live out. > - const MachineInstr *Def = MRI->getVRegDef(Reg); > - if (!Def || Def->getParent() != DomBB) > - continue; > - > - // Killed by DomBB? > - if (VI.findKill(DomBB)) > - continue; > - > - // This register is defined in DomBB and live out > - VI.AliveBlocks.set(NumNew); > } > } > > Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=89530&r1=89529&r2=89530&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) > +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Fri Nov 20 20:05:21 2009 > @@ -353,7 +353,7 @@ > // We break edges when registers are live out from the predecessor block > // (not considering PHI nodes). If the register is live in to this block > // anyway, we would gain nothing from splitting. > - if (isLiveOut(Reg, *PreMBB, LV) && !isLiveIn(Reg, MBB, LV)) > + if (!LV.isLiveIn(Reg, MBB) && isLiveOut(Reg, *PreMBB, LV)) > SplitCriticalEdge(PreMBB, &MBB); > } > } > @@ -406,22 +406,6 @@ > return false; > } > > -bool llvm::PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock &MBB, > - LiveVariables &LV) { > - LiveVariables::VarInfo &VI = LV.getVarInfo(Reg); > - > - if (VI.AliveBlocks.test(MBB.getNumber())) > - return true; > - > - // defined in MBB? > - const MachineInstr *Def = MRI->getVRegDef(Reg); > - if (Def && Def->getParent() == &MBB) > - return false; > - > - // killed in MBB? > - return VI.findKill(&MBB); > -} > - > MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A, > MachineBasicBlock *B) { > assert(A && B && "Missing MBB end point"); > @@ -463,7 +447,7 @@ > i->getOperand(ni+1).setMBB(NMBB); > > if (LiveVariables *LV=getAnalysisIfAvailable()) > - LV->addNewBlock(NMBB, A); > + LV->addNewBlock(NMBB, A, B); > > if (MachineDominatorTree *MDT=getAnalysisIfAvailable()) > MDT->addNewBlock(NMBB, A); > > Modified: llvm/trunk/lib/CodeGen/PHIElimination.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.h?rev=89530&r1=89529&r2=89530&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/PHIElimination.h (original) > +++ llvm/trunk/lib/CodeGen/PHIElimination.h Fri Nov 20 20:05:21 2009 > @@ -99,12 +99,6 @@ > bool isLiveOut(unsigned Reg, const MachineBasicBlock &MBB, > LiveVariables &LV); > > - /// isLiveIn - Determine if Reg is live in to MBB, not considering PHI > - /// source registers. This means that Reg is either killed by MBB or passes > - /// through it. > - bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB, > - LiveVariables &LV); > - > /// SplitCriticalEdge - Split a critical edge from A to B by > /// inserting a new MBB. Update branches in A and PHI instructions > /// in B. Return the new block. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From eocallaghan at auroraux.org Sun Nov 22 08:23:33 2009 From: eocallaghan at auroraux.org (Edward O'Callaghan) Date: Sun, 22 Nov 2009 14:23:33 -0000 Subject: [llvm-commits] [llvm] r89593 - in /llvm/trunk/test/CodeGen/ARM: fabss.ll fadds.ll fdivs.ll fmacs.ll fmscs.ll fmuls.ll fnegs.ll Message-ID: <200911221423.nAMENXL0022630@zion.cs.uiuc.edu> Author: evocallaghan Date: Sun Nov 22 08:23:33 2009 New Revision: 89593 URL: http://llvm.org/viewvc/llvm-project?rev=89593&view=rev Log: Convert ARM tests to FileCheck for PR5307. Modified: llvm/trunk/test/CodeGen/ARM/fabss.ll llvm/trunk/test/CodeGen/ARM/fadds.ll llvm/trunk/test/CodeGen/ARM/fdivs.ll llvm/trunk/test/CodeGen/ARM/fmacs.ll llvm/trunk/test/CodeGen/ARM/fmscs.ll llvm/trunk/test/CodeGen/ARM/fmuls.ll llvm/trunk/test/CodeGen/ARM/fnegs.ll Modified: llvm/trunk/test/CodeGen/ARM/fabss.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fabss.ll?rev=89593&r1=89592&r2=89593&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fabss.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fabss.ll Sun Nov 22 08:23:33 2009 @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vabs.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vabs.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vabs.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vabs.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vabs.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %a, float %b) { entry: @@ -13,3 +13,16 @@ } declare float @fabsf(float) + +; VFP2: test: +; VFP2: vabs.f32 s1, s1 + +; NFP1: test: +; NFP1: vabs.f32 d1, d1 +; NFP0: test: +; NFP0: vabs.f32 s1, s1 + +; CORTEXA8: test: +; CORTEXA8: vabs.f32 d1, d1 +; CORTEXA9: test: +; CORTEXA9: vabs.f32 s1, s1 Modified: llvm/trunk/test/CodeGen/ARM/fadds.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fadds.ll?rev=89593&r1=89592&r2=89593&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fadds.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fadds.ll Sun Nov 22 08:23:33 2009 @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vadd.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vadd.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vadd.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vadd.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vadd.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %a, float %b) { entry: @@ -10,3 +10,15 @@ ret float %0 } +; VFP2: test: +; VFP2: vadd.f32 s0, s1, s0 + +; NFP1: test: +; NFP1: vadd.f32 d0, d1, d0 +; NFP0: test: +; NFP0: vadd.f32 s0, s1, s0 + +; CORTEXA8: test: +; CORTEXA8: vadd.f32 d0, d1, d0 +; CORTEXA9: test: +; CORTEXA9: vadd.f32 s0, s1, s0 Modified: llvm/trunk/test/CodeGen/ARM/fdivs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fdivs.ll?rev=89593&r1=89592&r2=89593&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fdivs.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fdivs.ll Sun Nov 22 08:23:33 2009 @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vdiv.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vdiv.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vdiv.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vdiv.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vdiv.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %a, float %b) { entry: @@ -10,3 +10,15 @@ ret float %0 } +; VFP2: test: +; VFP2: vdiv.f32 s0, s1, s0 + +; NFP1: test: +; NFP1: vdiv.f32 s0, s1, s0 +; NFP0: test: +; NFP0: vdiv.f32 s0, s1, s0 + +; CORTEXA8: test: +; CORTEXA8: vdiv.f32 s0, s1, s0 +; CORTEXA9: test: +; CORTEXA9: vdiv.f32 s0, s1, s0 Modified: llvm/trunk/test/CodeGen/ARM/fmacs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fmacs.ll?rev=89593&r1=89592&r2=89593&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fmacs.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fmacs.ll Sun Nov 22 08:23:33 2009 @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vmla.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vmla.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vmla.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %acc, float %a, float %b) { entry: @@ -11,3 +11,15 @@ ret float %1 } +; VFP2: test: +; VFP2: vmla.f32 s2, s1, s0 + +; NFP1: test: +; NFP1: vmul.f32 d0, d1, d0 +; NFP0: test: +; NFP0: vmla.f32 s2, s1, s0 + +; CORTEXA8: test: +; CORTEXA8: vmul.f32 d0, d1, d0 +; CORTEXA9: test: +; CORTEXA9: vmla.f32 s2, s1, s0 Modified: llvm/trunk/test/CodeGen/ARM/fmscs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fmscs.ll?rev=89593&r1=89592&r2=89593&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fmscs.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fmscs.ll Sun Nov 22 08:23:33 2009 @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vnmls.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vnmls.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vnmls.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vnmls.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vnmls.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %acc, float %a, float %b) { entry: @@ -11,3 +11,15 @@ ret float %1 } +; VFP2: test: +; VFP2: vnmls.f32 s2, s1, s0 + +; NFP1: test: +; NFP1: vnmls.f32 s2, s1, s0 +; NFP0: test: +; NFP0: vnmls.f32 s2, s1, s0 + +; CORTEXA8: test: +; CORTEXA8: vnmls.f32 s2, s1, s0 +; CORTEXA9: test: +; CORTEXA9: vnmls.f32 s2, s1, s0 Modified: llvm/trunk/test/CodeGen/ARM/fmuls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fmuls.ll?rev=89593&r1=89592&r2=89593&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fmuls.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fmuls.ll Sun Nov 22 08:23:33 2009 @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vmul.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vmul.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vmul.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %a, float %b) { entry: @@ -10,3 +10,15 @@ ret float %0 } +; VFP2: test: +; VFP2: vmul.f32 s0, s1, s0 + +; NFP1: test: +; NFP1: vmul.f32 d0, d1, d0 +; NFP0: test: +; NFP0: vmul.f32 s0, s1, s0 + +; CORTEXA8: test: +; CORTEXA8: vmul.f32 d0, d1, d0 +; CORTEXA9: test: +; CORTEXA9: vmul.f32 s0, s1, s0 Modified: llvm/trunk/test/CodeGen/ARM/fnegs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fnegs.ll?rev=89593&r1=89592&r2=89593&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fnegs.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fnegs.ll Sun Nov 22 08:23:33 2009 @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vneg.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vneg.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vneg.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vneg.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 2 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vneg.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test1(float* %a) { entry: @@ -13,6 +13,20 @@ %retval = select i1 %3, float %1, float %0 ; [#uses=1] ret float %retval } +; VFP2: test1: +; VFP2: vneg.f32 s1, s0 + +; NFP1: test1: +; NFP1: vneg.f32 d1, d0 + +; NFP0: test1: +; NFP0: vneg.f32 s1, s0 + +; CORTEXA8: test1: +; CORTEXA8: vneg.f32 d1, d0 + +; CORTEXA9: test1: +; CORTEXA9: vneg.f32 s1, s0 define float @test2(float* %a) { entry: @@ -23,3 +37,18 @@ %retval = select i1 %3, float %1, float %0 ; [#uses=1] ret float %retval } +; VFP2: test2: +; VFP2: vneg.f32 s1, s0 + +; NFP1: test2: +; NFP1: vneg.f32 d1, d0 + +; NFP0: test2: +; NFP0: vneg.f32 s1, s0 + +; CORTEXA8: test2: +; CORTEXA8: vneg.f32 d1, d0 + +; CORTEXA9: test2: +; CORTEXA9: vneg.f32 s1, s0 + From clattner at apple.com Sun Nov 22 08:58:41 2009 From: clattner at apple.com (Chris Lattner) Date: Sun, 22 Nov 2009 06:58:41 -0800 Subject: [llvm-commits] [llvm] r88874 - in /llvm/trunk: lib/Target/ARM/ARM.h lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMTargetMachine.cpp test/CodeGen/ARM/spill-q.ll test/CodeGen/Thumb2/thumb2-spill-q.ll In-Reply-To: <8B059C90-62A9-407C-AF1B-C9405F0AC464@apple.com> References: <200911152145.nAFLjZWn002387@zion.cs.uiuc.edu> <27D3615E-CA82-4885-82D7-1DEC30D1DA1C@apple.com> <8B059C90-62A9-407C-AF1B-C9405F0AC464@apple.com> Message-ID: On Nov 16, 2009, at 12:44 PM, Jim Grosbach wrote: >> >> Hi Jim, >> >> Please name the pass something less contracted (so it shows up in doxygen better without context etc). Also, does it need to be an ARM specific pass? Do other targets have this sort of issue? >> > > X86 has the same issue and already has equivalent code. I don't see any reason why the code can't be refactored to be shared between the two and available for other targets. I'll have a look at that. > > As for the name, perhaps something like, "ARM Stack Required Alignment Auto-Detector"? (Removing the "ARM" once it's factored out to not be in the ARM back-end). Sounds great to me, thanks! -Chris From clattner at apple.com Sun Nov 22 09:03:41 2009 From: clattner at apple.com (Chris Lattner) Date: Sun, 22 Nov 2009 07:03:41 -0800 Subject: [llvm-commits] [llvm] r89017 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <200911170047.nAH0lNDT014760@zion.cs.uiuc.edu> References: <200911170047.nAH0lNDT014760@zion.cs.uiuc.edu> Message-ID: <09153601-5501-4785-A425-36C9F665A22F@apple.com> On Nov 16, 2009, at 4:47 PM, Dan Gohman wrote: > Author: djg > Date: Mon Nov 16 18:47:23 2009 > New Revision: 89017 > > URL: http://llvm.org/viewvc/llvm-project?rev=89017&view=rev > Log: > Remove the optimizations that convert BRCOND and BR_CC into > unconditional branches or fallthroghes. Instcombine/SimplifyCFG > should be simplifying branches with known conditions. > > This fixes some problems caused by these transformations not > updating the MachineBasicBlock CFG. Did you verify that this change doesn't result in any codegen change on something large like 403.gcc? It would also be useful to check something like crafty on x86-32 and ppc32. -Chris > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=89017&r1=89016&r2=89017&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Nov 16 18:47:23 2009 > @@ -4442,14 +4442,13 @@ > SDValue Chain = N->getOperand(0); > SDValue N1 = N->getOperand(1); > SDValue N2 = N->getOperand(2); > - ConstantSDNode *N1C = dyn_cast(N1); > > - // never taken branch, fold to chain > - if (N1C && N1C->isNullValue()) > - return Chain; > - // unconditional branch > - if (N1C && N1C->getAPIntValue() == 1) > - return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); > + // If N is a constant we could fold this into a fallthrough or unconditional > + // branch. However that doesn't happen very often in normal code, because > + // Instcombine/SimplifyCFG should have handled the available opportunities. > + // If we did this folding here, it would be necessary to update the > + // MachineBasicBlock CFG, which is awkward. > + > // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal > // on the target. > if (N1.getOpcode() == ISD::SETCC && > @@ -4516,22 +4515,18 @@ > CondCodeSDNode *CC = cast(N->getOperand(1)); > SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); > > + // If N is a constant we could fold this into a fallthrough or unconditional > + // branch. However that doesn't happen very often in normal code, because > + // Instcombine/SimplifyCFG should have handled the available opportunities. > + // If we did this folding here, it would be necessary to update the > + // MachineBasicBlock CFG, which is awkward. > + > // Use SimplifySetCC to simplify SETCC's. > SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), > CondLHS, CondRHS, CC->get(), N->getDebugLoc(), > false); > if (Simp.getNode()) AddToWorkList(Simp.getNode()); > > - ConstantSDNode *SCCC = dyn_cast_or_null(Simp.getNode()); > - > - // fold br_cc true, dest -> br dest (unconditional branch) > - if (SCCC && !SCCC->isNullValue()) > - return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, > - N->getOperand(0), N->getOperand(4)); > - // fold br_cc false, dest -> unconditional fall through > - if (SCCC && SCCC->isNullValue()) > - return N->getOperand(0); > - > // fold to a simpler setcc > if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) > return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From benny.kra at googlemail.com Sun Nov 22 09:15:53 2009 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Sun, 22 Nov 2009 15:15:53 -0000 Subject: [llvm-commits] [llvm] r89594 - /llvm/trunk/test/CodeGen/X86/trunc-to-bool.ll Message-ID: <200911221515.nAMFFrvD024373@zion.cs.uiuc.edu> Author: d0k Date: Sun Nov 22 09:15:52 2009 New Revision: 89594 URL: http://llvm.org/viewvc/llvm-project?rev=89594&view=rev Log: Turns out stuff gets allocated to different registers depending on the subtarget. Modified: llvm/trunk/test/CodeGen/X86/trunc-to-bool.ll Modified: llvm/trunk/test/CodeGen/X86/trunc-to-bool.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/trunc-to-bool.ll?rev=89594&r1=89593&r2=89594&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/trunc-to-bool.ll (original) +++ llvm/trunk/test/CodeGen/X86/trunc-to-bool.ll Sun Nov 22 09:15:52 2009 @@ -51,4 +51,4 @@ cond_false: ret i32 42 } -; CHECK: testb $1, %al +; CHECK: testb $1 From eocallaghan at auroraux.org Sun Nov 22 09:18:27 2009 From: eocallaghan at auroraux.org (Edward O'Callaghan) Date: Sun, 22 Nov 2009 15:18:27 -0000 Subject: [llvm-commits] [llvm] r89595 - in /llvm/trunk/test/CodeGen/Thumb2: thumb2-add3.ll thumb2-and2.ll thumb2-cmn.ll thumb2-mla.ll thumb2-mls.ll thumb2-orn2.ll thumb2-ror.ll thumb2-rsb.ll thumb2-rsb2.ll thumb2-sub2.ll thumb2-teq.ll thumb2-tst.ll Message-ID: <200911221518.nAMFIRit024499@zion.cs.uiuc.edu> Author: evocallaghan Date: Sun Nov 22 09:18:27 2009 New Revision: 89595 URL: http://llvm.org/viewvc/llvm-project?rev=89595&view=rev Log: Convert Thumb2 tests to FileCheck for PR5307. Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-add3.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-and2.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-cmn.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-mla.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-orn2.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-ror.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-rsb.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-rsb2.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-sub2.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-teq.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-tst.ll Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-add3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-add3.ll?rev=89595&r1=89594&r2=89595&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-add3.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-add3.ll Sun Nov 22 09:18:27 2009 @@ -1,6 +1,9 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {addw\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#4095} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @f1(i32 %a) { %tmp = add i32 %a, 4095 ret i32 %tmp } + +; CHECK: f1: +; CHECK: addw r0, r0, #4095 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-and2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-and2.ll?rev=89595&r1=89594&r2=89595&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-and2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-and2.ll Sun Nov 22 09:18:27 2009 @@ -1,31 +1,41 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#171\\|#1179666\\|#872428544\\|#1448498774\\|#66846720} | count 5 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; 171 = 0x000000ab define i32 @f1(i32 %a) { %tmp = and i32 %a, 171 ret i32 %tmp } +; CHECK: f1: +; CHECK: and r0, r0, #171 ; 1179666 = 0x00120012 define i32 @f2(i32 %a) { %tmp = and i32 %a, 1179666 ret i32 %tmp } +; CHECK: f2: +; CHECK: and r0, r0, #1179666 ; 872428544 = 0x34003400 define i32 @f3(i32 %a) { %tmp = and i32 %a, 872428544 ret i32 %tmp } +; CHECK: f3: +; CHECK: and r0, r0, #872428544 ; 1448498774 = 0x56565656 define i32 @f4(i32 %a) { %tmp = and i32 %a, 1448498774 ret i32 %tmp } +; CHECK: f4: +; CHECK: and r0, r0, #1448498774 ; 66846720 = 0x03fc0000 define i32 @f5(i32 %a) { %tmp = and i32 %a, 66846720 ret i32 %tmp } +; CHECK: f5: +; CHECK: and r0, r0, #66846720 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-cmn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-cmn.ll?rev=89595&r1=89594&r2=89595&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-cmn.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-cmn.ll Sun Nov 22 09:18:27 2009 @@ -1,32 +1,36 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\]$} | count 4 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i1 @f1(i32 %a, i32 %b) { %nb = sub i32 0, %b %tmp = icmp ne i32 %a, %nb ret i1 %tmp } +; CHECK: f1: +; CHECK: cmn.w r0, r1 define i1 @f2(i32 %a, i32 %b) { %nb = sub i32 0, %b %tmp = icmp ne i32 %nb, %a ret i1 %tmp } +; CHECK: f2: +; CHECK: cmn.w r0, r1 define i1 @f3(i32 %a, i32 %b) { %nb = sub i32 0, %b %tmp = icmp eq i32 %a, %nb ret i1 %tmp } +; CHECK: f3: +; CHECK: cmn.w r0, r1 define i1 @f4(i32 %a, i32 %b) { %nb = sub i32 0, %b %tmp = icmp eq i32 %nb, %a ret i1 %tmp } +; CHECK: f4: +; CHECK: cmn.w r0, r1 define i1 @f5(i32 %a, i32 %b) { %tmp = shl i32 %b, 5 @@ -34,6 +38,8 @@ %tmp1 = icmp eq i32 %nb, %a ret i1 %tmp1 } +; CHECK: f5: +; CHECK: cmn.w r0, r1, lsl #5 define i1 @f6(i32 %a, i32 %b) { %tmp = lshr i32 %b, 6 @@ -41,6 +47,8 @@ %tmp1 = icmp ne i32 %nb, %a ret i1 %tmp1 } +; CHECK: f6: +; CHECK: cmn.w r0, r1, lsr #6 define i1 @f7(i32 %a, i32 %b) { %tmp = ashr i32 %b, 7 @@ -48,6 +56,8 @@ %tmp1 = icmp eq i32 %a, %nb ret i1 %tmp1 } +; CHECK: f7: +; CHECK: cmn.w r0, r1, asr #7 define i1 @f8(i32 %a, i32 %b) { %l8 = shl i32 %a, 24 @@ -57,3 +67,6 @@ %tmp1 = icmp ne i32 %a, %nb ret i1 %tmp1 } +; CHECK: f8: +; CHECK: cmn.w r0, r0, ror #8 + Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-mla.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mla.ll?rev=89595&r1=89594&r2=89595&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-mla.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mla.ll Sun Nov 22 09:18:27 2009 @@ -1,13 +1,17 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {mla\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 2 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @f1(i32 %a, i32 %b, i32 %c) { %tmp1 = mul i32 %a, %b %tmp2 = add i32 %c, %tmp1 ret i32 %tmp2 } +; CHECK: f1: +; CHECK: mla r0, r0, r1, r2 define i32 @f2(i32 %a, i32 %b, i32 %c) { %tmp1 = mul i32 %a, %b %tmp2 = add i32 %tmp1, %c ret i32 %tmp2 } +; CHECK: f2: +; CHECK: mla r0, r0, r1, r2 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll?rev=89595&r1=89594&r2=89595&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mls.ll Sun Nov 22 09:18:27 2009 @@ -1,10 +1,12 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {mls\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @f1(i32 %a, i32 %b, i32 %c) { %tmp1 = mul i32 %a, %b %tmp2 = sub i32 %c, %tmp1 ret i32 %tmp2 } +; CHECK: f1: +; CHECK: mls r0, r0, r1, r2 ; sub doesn't commute, so no mls for this one define i32 @f2(i32 %a, i32 %b, i32 %c) { @@ -12,3 +14,6 @@ %tmp2 = sub i32 %tmp1, %c ret i32 %tmp2 } +; CHECK: f2: +; CHECK: muls r0, r1 + Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-orn2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-orn2.ll?rev=89595&r1=89594&r2=89595&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-orn2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-orn2.ll Sun Nov 22 09:18:27 2009 @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*#\[0-9\]*} |\ -; RUN: grep {#187\\|#11141290\\|#-872363008\\|#1114112} | count 4 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + ; 0x000000bb = 187 define i32 @f1(i32 %a) { @@ -7,6 +7,8 @@ %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f1: +; CHECK: orn r0, r0, #187 ; 0x00aa00aa = 11141290 define i32 @f2(i32 %a) { @@ -14,6 +16,8 @@ %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f2: +; CHECK: orn r0, r0, #11141290 ; 0xcc00cc00 = 3422604288 define i32 @f3(i32 %a) { @@ -21,6 +25,8 @@ %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f3: +; CHECK: orn r0, r0, #-872363008 ; 0x00110000 = 1114112 define i32 @f5(i32 %a) { @@ -28,3 +34,5 @@ %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f5: +; CHECK: orn r0, r0, #1114112 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ror.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ror.ll?rev=89595&r1=89594&r2=89595&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-ror.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ror.ll Sun Nov 22 09:18:27 2009 @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {ror\\.w\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*#\[0-9\]*} | grep 22 | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + define i32 @f1(i32 %a) { %l8 = shl i32 %a, 10 @@ -6,3 +7,5 @@ %tmp = or i32 %l8, %r8 ret i32 %tmp } +; CHECK: f1: +; CHECK: ror.w r0, r0, #22 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-rsb.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-rsb.ll?rev=89595&r1=89594&r2=89595&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-rsb.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-rsb.ll Sun Nov 22 09:18:27 2009 @@ -1,30 +1,35 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s -define i32 @f2(i32 %a, i32 %b) { +define i32 @f1(i32 %a, i32 %b) { %tmp = shl i32 %b, 5 %tmp1 = sub i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f1: +; CHECK: rsb r0, r0, r1, lsl #5 -define i32 @f3(i32 %a, i32 %b) { +define i32 @f2(i32 %a, i32 %b) { %tmp = lshr i32 %b, 6 %tmp1 = sub i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f2: +; CHECK: rsb r0, r0, r1, lsr #6 -define i32 @f4(i32 %a, i32 %b) { +define i32 @f3(i32 %a, i32 %b) { %tmp = ashr i32 %b, 7 %tmp1 = sub i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f3: +; CHECK: rsb r0, r0, r1, asr #7 -define i32 @f5(i32 %a, i32 %b) { +define i32 @f4(i32 %a, i32 %b) { %l8 = shl i32 %a, 24 %r8 = lshr i32 %a, 8 %tmp = or i32 %l8, %r8 %tmp1 = sub i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f4: +; CHECK: rsb r0, r0, r0, ror #8 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-rsb2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-rsb2.ll?rev=89595&r1=89594&r2=89595&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-rsb2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-rsb2.ll Sun Nov 22 09:18:27 2009 @@ -1,31 +1,41 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#171\\|#1179666\\|#872428544\\|#1448498774\\|#66846720} | count 5 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; 171 = 0x000000ab define i32 @f1(i32 %a) { %tmp = sub i32 171, %a ret i32 %tmp } +; CHECK: f1: +; CHECK: rsb.w r0, r0, #171 ; 1179666 = 0x00120012 define i32 @f2(i32 %a) { %tmp = sub i32 1179666, %a ret i32 %tmp } +; CHECK: f2: +; CHECK: rsb.w r0, r0, #1179666 ; 872428544 = 0x34003400 define i32 @f3(i32 %a) { %tmp = sub i32 872428544, %a ret i32 %tmp } +; CHECK: f3: +; CHECK: rsb.w r0, r0, #872428544 ; 1448498774 = 0x56565656 define i32 @f4(i32 %a) { %tmp = sub i32 1448498774, %a ret i32 %tmp } +; CHECK: f4: +; CHECK: rsb.w r0, r0, #1448498774 ; 66846720 = 0x03fc0000 define i32 @f5(i32 %a) { %tmp = sub i32 66846720, %a ret i32 %tmp } +; CHECK: f5: +; CHECK: rsb.w r0, r0, #66846720 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-sub2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-sub2.ll?rev=89595&r1=89594&r2=89595&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-sub2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-sub2.ll Sun Nov 22 09:18:27 2009 @@ -1,6 +1,8 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {subw\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#4095} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @f1(i32 %a) { %tmp = sub i32 %a, 4095 ret i32 %tmp } +; CHECK: f1: +; CHECK: subw r0, r0, #4095 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-teq.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-teq.ll?rev=89595&r1=89594&r2=89595&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-teq.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-teq.ll Sun Nov 22 09:18:27 2009 @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*#\[0-9\]*} | \ -; RUN: grep {#187\\|#11141290\\|#-872363008\\|#1114112\\|#-572662307} | count 10 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + ; 0x000000bb = 187 define i1 @f1(i32 %a) { @@ -7,6 +7,8 @@ %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f1: +; CHECK: teq.w r0, #187 ; 0x000000bb = 187 define i1 @f2(i32 %a) { @@ -14,6 +16,8 @@ %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } +; CHECK: f2: +; CHECK: teq.w r0, #187 ; 0x00aa00aa = 11141290 define i1 @f3(i32 %a) { @@ -21,6 +25,8 @@ %tmp1 = icmp eq i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f3: +; CHECK: teq.w r0, #11141290 ; 0x00aa00aa = 11141290 define i1 @f4(i32 %a) { @@ -28,6 +34,8 @@ %tmp1 = icmp ne i32 0, %tmp ret i1 %tmp1 } +; CHECK: f4: +; CHECK: teq.w r0, #11141290 ; 0xcc00cc00 = 3422604288 define i1 @f5(i32 %a) { @@ -35,6 +43,8 @@ %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f5: +; CHECK: teq.w r0, #-872363008 ; 0xcc00cc00 = 3422604288 define i1 @f6(i32 %a) { @@ -42,6 +52,8 @@ %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } +; CHECK: f6: +; CHECK: teq.w r0, #-872363008 ; 0xdddddddd = 3722304989 define i1 @f7(i32 %a) { @@ -49,6 +61,8 @@ %tmp1 = icmp eq i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f7: +; CHECK: teq.w r0, #-572662307 ; 0xdddddddd = 3722304989 define i1 @f8(i32 %a) { @@ -56,6 +70,8 @@ %tmp1 = icmp ne i32 0, %tmp ret i1 %tmp1 } +; CHECK: f8: +; CHECK: teq.w r0, #-572662307 ; 0x00110000 = 1114112 define i1 @f9(i32 %a) { @@ -63,6 +79,8 @@ %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f9: +; CHECK: teq.w r0, #1114112 ; 0x00110000 = 1114112 define i1 @f10(i32 %a) { @@ -70,3 +88,6 @@ %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } +; CHECK: f10: +; CHECK: teq.w r0, #1114112 + Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-tst.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-tst.ll?rev=89595&r1=89594&r2=89595&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-tst.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-tst.ll Sun Nov 22 09:18:27 2009 @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {tst\\.w\\W*r\[0-9\],\\W*#\[0-9\]*} | \ -; RUN: grep {#187\\|#11141290\\|#-872363008\\|#1114112\\|#-572662307} | count 10 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + ; 0x000000bb = 187 define i1 @f1(i32 %a) { @@ -7,6 +7,8 @@ %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f1: +; CHECK: tst.w r0, #187 ; 0x000000bb = 187 define i1 @f2(i32 %a) { @@ -14,6 +16,8 @@ %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } +; CHECK: f2: +; CHECK: tst.w r0, #187 ; 0x00aa00aa = 11141290 define i1 @f3(i32 %a) { @@ -21,6 +25,8 @@ %tmp1 = icmp eq i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f3: +; CHECK: tst.w r0, #11141290 ; 0x00aa00aa = 11141290 define i1 @f4(i32 %a) { @@ -28,6 +34,8 @@ %tmp1 = icmp ne i32 0, %tmp ret i1 %tmp1 } +; CHECK: f4: +; CHECK: tst.w r0, #11141290 ; 0xcc00cc00 = 3422604288 define i1 @f5(i32 %a) { @@ -35,6 +43,8 @@ %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f5: +; CHECK: tst.w r0, #-872363008 ; 0xcc00cc00 = 3422604288 define i1 @f6(i32 %a) { @@ -42,6 +52,8 @@ %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } +; CHECK: f6: +; CHECK: tst.w r0, #-872363008 ; 0xdddddddd = 3722304989 define i1 @f7(i32 %a) { @@ -49,6 +61,8 @@ %tmp1 = icmp eq i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f7: +; CHECK: tst.w r0, #-572662307 ; 0xdddddddd = 3722304989 define i1 @f8(i32 %a) { @@ -56,6 +70,8 @@ %tmp1 = icmp ne i32 0, %tmp ret i1 %tmp1 } +; CHECK: f8: +; CHECK: tst.w r0, #-572662307 ; 0x00110000 = 1114112 define i1 @f9(i32 %a) { @@ -63,6 +79,8 @@ %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f9: +; CHECK: tst.w r0, #1114112 ; 0x00110000 = 1114112 define i1 @f10(i32 %a) { @@ -70,3 +88,5 @@ %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } +; CHECK: f10: +; CHECK: tst.w r0, #1114112 From eocallaghan at auroraux.org Sun Nov 22 09:35:28 2009 From: eocallaghan at auroraux.org (Edward O'Callaghan) Date: Sun, 22 Nov 2009 15:35:28 -0000 Subject: [llvm-commits] [llvm] r89596 - in /llvm/trunk/test/CodeGen/Thumb2: thumb2-orn.ll thumb2-orr2.ll Message-ID: <200911221535.nAMFZSwp025093@zion.cs.uiuc.edu> Author: evocallaghan Date: Sun Nov 22 09:35:28 2009 New Revision: 89596 URL: http://llvm.org/viewvc/llvm-project?rev=89596&view=rev Log: Miss two, PR5307. Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-orn.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-orr2.ll Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-orn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-orn.ll?rev=89596&r1=89595&r2=89596&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-orn.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-orn.ll Sun Nov 22 09:35:28 2009 @@ -1,32 +1,37 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*$} | count 4 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + define i32 @f1(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 %tmp1 = or i32 %a, %tmp ret i32 %tmp1 } +; CHECK: f1: +; CHECK: orn r0, r0, r1 define i32 @f2(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 %tmp1 = or i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f2: +; CHECK: orn r0, r0, r1 define i32 @f3(i32 %a, i32 %b) { %tmp = xor i32 4294967295, %b %tmp1 = or i32 %a, %tmp ret i32 %tmp1 } +; CHECK: f3: +; CHECK: orn r0, r0, r1 define i32 @f4(i32 %a, i32 %b) { %tmp = xor i32 4294967295, %b %tmp1 = or i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f4: +; CHECK: orn r0, r0, r1 define i32 @f5(i32 %a, i32 %b) { %tmp = shl i32 %b, 5 @@ -34,6 +39,8 @@ %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f5: +; CHECK: orn r0, r0, r1, lsl #5 define i32 @f6(i32 %a, i32 %b) { %tmp = lshr i32 %b, 6 @@ -41,6 +48,8 @@ %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f6: +; CHECK: orn r0, r0, r1, lsr #6 define i32 @f7(i32 %a, i32 %b) { %tmp = ashr i32 %b, 7 @@ -48,6 +57,8 @@ %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f7: +; CHECK: orn r0, r0, r1, asr #7 define i32 @f8(i32 %a, i32 %b) { %l8 = shl i32 %a, 24 @@ -57,3 +68,5 @@ %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f8: +; CHECK: orn r0, r0, r0, ror #8 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-orr2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-orr2.ll?rev=89596&r1=89595&r2=89596&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-orr2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-orr2.ll Sun Nov 22 09:35:28 2009 @@ -1,31 +1,42 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orr\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*#\[0-9\]*} | grep {#187\\|#11141290\\|#-872363008\\|#1145324612\\|#1114112} | count 5 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + ; 0x000000bb = 187 define i32 @f1(i32 %a) { %tmp2 = or i32 %a, 187 ret i32 %tmp2 } +; CHECK: f1: +; CHECK: orr r0, r0, #187 ; 0x00aa00aa = 11141290 define i32 @f2(i32 %a) { %tmp2 = or i32 %a, 11141290 ret i32 %tmp2 } +; CHECK: f2: +; CHECK: orr r0, r0, #11141290 ; 0xcc00cc00 = 3422604288 define i32 @f3(i32 %a) { %tmp2 = or i32 %a, 3422604288 ret i32 %tmp2 } +; CHECK: f3: +; CHECK: orr r0, r0, #-872363008 ; 0x44444444 = 1145324612 define i32 @f4(i32 %a) { %tmp2 = or i32 %a, 1145324612 ret i32 %tmp2 } +; CHECK: f4: +; CHECK: orr r0, r0, #1145324612 ; 0x00110000 = 1114112 define i32 @f5(i32 %a) { %tmp2 = or i32 %a, 1114112 ret i32 %tmp2 } +; CHECK: f5: +; CHECK: orr r0, r0, #1114112 From sabre at nondot.org Sun Nov 22 10:01:44 2009 From: sabre at nondot.org (Chris Lattner) Date: Sun, 22 Nov 2009 16:01:44 -0000 Subject: [llvm-commits] [llvm] r89599 - in /llvm/trunk: docs/AliasAnalysis.html include/llvm/Analysis/AliasAnalysis.h include/llvm/Analysis/LibCallAliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/AliasDebugger.cpp lib/Analysis/AliasSetTracker.cpp lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/IPA/Andersens.cpp lib/Analysis/IPA/GlobalsModRef.cpp Message-ID: <200911221601.nAMG1jR6025885@zion.cs.uiuc.edu> Author: lattner Date: Sun Nov 22 10:01:44 2009 New Revision: 89599 URL: http://llvm.org/viewvc/llvm-project?rev=89599&view=rev Log: Remove the AliasAnalysis::getMustAliases method, which is dead. The hasNoModRefInfoForCalls isn't worth it as a filter because basicaa provides m/r info and everything chains to it, so remove it. Modified: llvm/trunk/docs/AliasAnalysis.html llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h llvm/trunk/lib/Analysis/AliasAnalysis.cpp llvm/trunk/lib/Analysis/AliasDebugger.cpp llvm/trunk/lib/Analysis/AliasSetTracker.cpp llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/lib/Analysis/IPA/Andersens.cpp llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp Modified: llvm/trunk/docs/AliasAnalysis.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AliasAnalysis.html?rev=89599&r1=89598&r2=89599&view=diff ============================================================================== --- llvm/trunk/docs/AliasAnalysis.html (original) +++ llvm/trunk/docs/AliasAnalysis.html Sun Nov 22 10:01:44 2009 @@ -225,12 +225,7 @@ call sites (CS1 & CS2), returns NoModRef if the two calls refer to disjoint memory locations, Ref if CS1 reads memory written by CS2, Mod if CS1 writes to memory read or written by CS2, or ModRef if CS1 might read or write memory -accessed by CS2. Note that this relation is not commutative. Clients that use -this method should be predicated on the hasNoModRefInfoForCalls() -method, which indicates whether or not an analysis can provide mod/ref -information for function call pairs (most can not). If this predicate is false, -the client shouldn't waste analysis time querying the getModRefInfo -method many times.

+accessed by CS2. Note that this relation is not commutative.

@@ -251,21 +246,6 @@
- The getMustAliases method -
- -
- -

The getMustAliases method returns all values that are known to -always must alias a pointer. This information can be provided in some cases for -important objects like the null pointer and global values. Knowing that a -pointer always points to a particular function allows indirect calls to be -turned into direct calls, for example.

- -
- - -
The pointsToConstantMemory method
Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=89599&r1=89598&r2=89599&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Sun Nov 22 10:01:44 2009 @@ -94,14 +94,6 @@ virtual AliasResult alias(const Value *V1, unsigned V1Size, const Value *V2, unsigned V2Size); - /// getMustAliases - If there are any pointers known that must alias this - /// pointer, return them now. This allows alias-set based alias analyses to - /// perform a form a value numbering (which is exposed by load-vn). If an - /// alias analysis supports this, it should ADD any must aliased pointers to - /// the specified vector. - /// - virtual void getMustAliases(Value *P, std::vector &RetVals); - /// pointsToConstantMemory - If the specified pointer is known to point into /// constant global memory, return true. This allows disambiguation of store /// instructions from constant pointers. @@ -262,14 +254,6 @@ /// virtual ModRefResult getModRefInfo(CallSite CS1, CallSite CS2); - /// hasNoModRefInfoForCalls - Return true if the analysis has no mod/ref - /// information for pairs of function calls (other than "pure" and "const" - /// functions). This can be used by clients to avoid many pointless queries. - /// Remember that if you override this and chain to another analysis, you must - /// make sure that it doesn't have mod/ref info either. - /// - virtual bool hasNoModRefInfoForCalls() const; - public: /// Convenience functions... ModRefResult getModRefInfo(LoadInst *L, Value *P, unsigned Size); Modified: llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h?rev=89599&r1=89598&r2=89599&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h Sun Nov 22 10:01:44 2009 @@ -49,9 +49,6 @@ return false; } - /// hasNoModRefInfoForCalls - We can provide mod/ref information against - /// non-escaping allocations. - virtual bool hasNoModRefInfoForCalls() const { return false; } private: ModRefResult AnalyzeLibCallDetails(const LibCallFunctionInfo *FI, CallSite CS, Value *P, unsigned Size); Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=89599&r1=89598&r2=89599&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Sun Nov 22 10:01:44 2009 @@ -49,21 +49,11 @@ return AA->alias(V1, V1Size, V2, V2Size); } -void AliasAnalysis::getMustAliases(Value *P, std::vector &RetVals) { - assert(AA && "AA didn't call InitializeAliasAnalysis in its run method!"); - return AA->getMustAliases(P, RetVals); -} - bool AliasAnalysis::pointsToConstantMemory(const Value *P) { assert(AA && "AA didn't call InitializeAliasAnalysis in its run method!"); return AA->pointsToConstantMemory(P); } -bool AliasAnalysis::hasNoModRefInfoForCalls() const { - assert(AA && "AA didn't call InitializeAliasAnalysis in its run method!"); - return AA->hasNoModRefInfoForCalls(); -} - void AliasAnalysis::deleteValue(Value *V) { assert(AA && "AA didn't call InitializeAliasAnalysis in its run method!"); AA->deleteValue(V); Modified: llvm/trunk/lib/Analysis/AliasDebugger.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasDebugger.cpp?rev=89599&r1=89598&r2=89599&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasDebugger.cpp (original) +++ llvm/trunk/lib/Analysis/AliasDebugger.cpp Sun Nov 22 10:01:44 2009 @@ -90,11 +90,6 @@ return AliasAnalysis::getModRefInfo(CS1,CS2); } - void getMustAliases(Value *P, std::vector &RetVals) { - assert(Vals.find(P) != Vals.end() && "Never seen value in AA before"); - return AliasAnalysis::getMustAliases(P, RetVals); - } - bool pointsToConstantMemory(const Value *P) { assert(Vals.find(P) != Vals.end() && "Never seen value in AA before"); return AliasAnalysis::pointsToConstantMemory(P); Modified: llvm/trunk/lib/Analysis/AliasSetTracker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasSetTracker.cpp?rev=89599&r1=89598&r2=89599&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasSetTracker.cpp (original) +++ llvm/trunk/lib/Analysis/AliasSetTracker.cpp Sun Nov 22 10:01:44 2009 @@ -153,9 +153,6 @@ // Check the call sites list and invoke list... if (!CallSites.empty()) { - if (AA.hasNoModRefInfoForCalls()) - return true; - for (unsigned i = 0, e = CallSites.size(); i != e; ++i) if (AA.getModRefInfo(CallSites[i], const_cast(Ptr), Size) != AliasAnalysis::NoModRef) @@ -169,9 +166,6 @@ if (AA.doesNotAccessMemory(CS)) return false; - if (AA.hasNoModRefInfoForCalls()) - return true; - for (unsigned i = 0, e = CallSites.size(); i != e; ++i) if (AA.getModRefInfo(CallSites[i], CS) != AliasAnalysis::NoModRef || AA.getModRefInfo(CS, CallSites[i]) != AliasAnalysis::NoModRef) Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=89599&r1=89598&r2=89599&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Sun Nov 22 10:01:44 2009 @@ -164,7 +164,6 @@ llvm_unreachable("This method may not be called on this function!"); } - virtual void getMustAliases(Value *P, std::vector &RetVals) { } virtual bool pointsToConstantMemory(const Value *P) { return false; } virtual ModRefResult getModRefInfo(CallSite CS, Value *P, unsigned Size) { return ModRef; @@ -172,7 +171,6 @@ virtual ModRefResult getModRefInfo(CallSite CS1, CallSite CS2) { return ModRef; } - virtual bool hasNoModRefInfoForCalls() const { return true; } virtual void deleteValue(Value *V) {} virtual void copyValue(Value *From, Value *To) {} @@ -211,10 +209,6 @@ ModRefResult getModRefInfo(CallSite CS, Value *P, unsigned Size); ModRefResult getModRefInfo(CallSite CS1, CallSite CS2); - /// hasNoModRefInfoForCalls - We can provide mod/ref information against - /// non-escaping allocations. - virtual bool hasNoModRefInfoForCalls() const { return false; } - /// pointsToConstantMemory - Chase pointers until we find a (constant /// global) or not. bool pointsToConstantMemory(const Value *P); Modified: llvm/trunk/lib/Analysis/IPA/Andersens.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/Andersens.cpp?rev=89599&r1=89598&r2=89599&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/Andersens.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/Andersens.cpp Sun Nov 22 10:01:44 2009 @@ -484,7 +484,6 @@ const Value *V2, unsigned V2Size); virtual ModRefResult getModRefInfo(CallSite CS, Value *P, unsigned Size); virtual ModRefResult getModRefInfo(CallSite CS1, CallSite CS2); - void getMustAliases(Value *P, std::vector &RetVals); bool pointsToConstantMemory(const Value *P); virtual void deleteValue(Value *V) { @@ -680,32 +679,6 @@ return AliasAnalysis::getModRefInfo(CS1,CS2); } -/// getMustAlias - We can provide must alias information if we know that a -/// pointer can only point to a specific function or the null pointer. -/// Unfortunately we cannot determine must-alias information for global -/// variables or any other memory memory objects because we do not track whether -/// a pointer points to the beginning of an object or a field of it. -void Andersens::getMustAliases(Value *P, std::vector &RetVals) { - Node *N = &GraphNodes[FindNode(getNode(P))]; - if (N->PointsTo->count() == 1) { - Node *Pointee = &GraphNodes[N->PointsTo->find_first()]; - // If a function is the only object in the points-to set, then it must be - // the destination. Note that we can't handle global variables here, - // because we don't know if the pointer is actually pointing to a field of - // the global or to the beginning of it. - if (Value *V = Pointee->getValue()) { - if (Function *F = dyn_cast(V)) - RetVals.push_back(F); - } else { - // If the object in the points-to set is the null object, then the null - // pointer is a must alias. - if (Pointee == &GraphNodes[NullObject]) - RetVals.push_back(Constant::getNullValue(P->getType())); - } - } - AliasAnalysis::getMustAliases(P, RetVals); -} - /// pointsToConstantMemory - If we can determine that this pointer only points /// to constant memory, return true. In practice, this means that if the /// pointer can only point to constant globals, functions, or the null pointer, Modified: llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp?rev=89599&r1=89598&r2=89599&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp Sun Nov 22 10:01:44 2009 @@ -111,7 +111,6 @@ ModRefResult getModRefInfo(CallSite CS1, CallSite CS2) { return AliasAnalysis::getModRefInfo(CS1,CS2); } - bool hasNoModRefInfoForCalls() const { return false; } /// getModRefBehavior - Return the behavior of the specified function if /// called from the specified call site. The call site may be null in which From sabre at nondot.org Sun Nov 22 10:05:05 2009 From: sabre at nondot.org (Chris Lattner) Date: Sun, 22 Nov 2009 16:05:05 -0000 Subject: [llvm-commits] [llvm] r89600 - /llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <200911221605.nAMG55nq025996@zion.cs.uiuc.edu> Author: lattner Date: Sun Nov 22 10:05:05 2009 New Revision: 89600 URL: http://llvm.org/viewvc/llvm-project?rev=89600&view=rev Log: reduce indentation, no functionality change. Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=89600&r1=89599&r2=89600&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Sun Nov 22 10:05:05 2009 @@ -275,95 +275,101 @@ // AliasAnalysis::ModRefResult BasicAliasAnalysis::getModRefInfo(CallSite CS, Value *P, unsigned Size) { - if (!isa(P)) { - const Value *Object = P->getUnderlyingObject(); - - // If this is a tail call and P points to a stack location, we know that - // the tail call cannot access or modify the local stack. - // We cannot exclude byval arguments here; these belong to the caller of - // the current function not to the current function, and a tail callee - // may reference them. - if (isa(Object)) - if (CallInst *CI = dyn_cast(CS.getInstruction())) - if (CI->isTailCall()) - return NoModRef; + // Don't do anything smart for constant pointers. + // FIXME: WHY? + if (isa(P)) + return AliasAnalysis::getModRefInfo(CS, P, Size); + + const Value *Object = P->getUnderlyingObject(); + + // If this is a tail call and P points to a stack location, we know that + // the tail call cannot access or modify the local stack. + // We cannot exclude byval arguments here; these belong to the caller of + // the current function not to the current function, and a tail callee + // may reference them. + if (isa(Object)) + if (CallInst *CI = dyn_cast(CS.getInstruction())) + if (CI->isTailCall()) + return NoModRef; + + // If the pointer is to a locally allocated object that does not escape, + // then the call can not mod/ref the pointer unless the call takes the + // argument without capturing it. + if (isNonEscapingLocalObject(Object) && CS.getInstruction() != Object) { + bool passedAsArg = false; + // TODO: Eventually only check 'nocapture' arguments. + for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); + CI != CE; ++CI) + if (isa((*CI)->getType()) && + alias(cast(CI), ~0U, P, ~0U) != NoAlias) + passedAsArg = true; - // If the pointer is to a locally allocated object that does not escape, - // then the call can not mod/ref the pointer unless the call takes the - // argument without capturing it. - if (isNonEscapingLocalObject(Object) && CS.getInstruction() != Object) { - bool passedAsArg = false; - // TODO: Eventually only check 'nocapture' arguments. - for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); - CI != CE; ++CI) - if (isa((*CI)->getType()) && - alias(cast(CI), ~0U, P, ~0U) != NoAlias) - passedAsArg = true; - - if (!passedAsArg) + if (!passedAsArg) + return NoModRef; + } + + // Finally, handle specific knowledge of intrinsics. + IntrinsicInst *II = dyn_cast(CS.getInstruction()); + if (II == 0) + return AliasAnalysis::getModRefInfo(CS, P, Size); + + switch (II->getIntrinsicID()) { + default: break; + case Intrinsic::memcpy: + case Intrinsic::memmove: { + unsigned Len = ~0U; + if (ConstantInt *LenCI = dyn_cast(II->getOperand(3))) + Len = LenCI->getZExtValue(); + Value *Dest = II->getOperand(1); + Value *Src = II->getOperand(2); + if (alias(Dest, Len, P, Size) == NoAlias) { + if (alias(Src, Len, P, Size) == NoAlias) return NoModRef; + return Ref; } - - if (IntrinsicInst *II = dyn_cast(CS.getInstruction())) { - switch (II->getIntrinsicID()) { - default: break; - case Intrinsic::memcpy: - case Intrinsic::memmove: { - unsigned Len = ~0U; - if (ConstantInt *LenCI = dyn_cast(II->getOperand(3))) - Len = LenCI->getZExtValue(); - Value *Dest = II->getOperand(1); - Value *Src = II->getOperand(2); - if (alias(Dest, Len, P, Size) == NoAlias) { - if (alias(Src, Len, P, Size) == NoAlias) - return NoModRef; - return Ref; - } - } - break; - case Intrinsic::memset: - if (ConstantInt *LenCI = dyn_cast(II->getOperand(3))) { - unsigned Len = LenCI->getZExtValue(); - Value *Dest = II->getOperand(1); - if (alias(Dest, Len, P, Size) == NoAlias) - return NoModRef; - } - break; - case Intrinsic::atomic_cmp_swap: - case Intrinsic::atomic_swap: - case Intrinsic::atomic_load_add: - case Intrinsic::atomic_load_sub: - case Intrinsic::atomic_load_and: - case Intrinsic::atomic_load_nand: - case Intrinsic::atomic_load_or: - case Intrinsic::atomic_load_xor: - case Intrinsic::atomic_load_max: - case Intrinsic::atomic_load_min: - case Intrinsic::atomic_load_umax: - case Intrinsic::atomic_load_umin: - if (TD) { - Value *Op1 = II->getOperand(1); - unsigned Op1Size = TD->getTypeStoreSize(Op1->getType()); - if (alias(Op1, Op1Size, P, Size) == NoAlias) - return NoModRef; - } - break; - case Intrinsic::lifetime_start: - case Intrinsic::lifetime_end: - case Intrinsic::invariant_start: { - unsigned PtrSize = cast(II->getOperand(1))->getZExtValue(); - if (alias(II->getOperand(2), PtrSize, P, Size) == NoAlias) - return NoModRef; - } - break; - case Intrinsic::invariant_end: { - unsigned PtrSize = cast(II->getOperand(2))->getZExtValue(); - if (alias(II->getOperand(3), PtrSize, P, Size) == NoAlias) - return NoModRef; - } - break; - } + break; + } + case Intrinsic::memset: + if (ConstantInt *LenCI = dyn_cast(II->getOperand(3))) { + unsigned Len = LenCI->getZExtValue(); + Value *Dest = II->getOperand(1); + if (alias(Dest, Len, P, Size) == NoAlias) + return NoModRef; } + break; + case Intrinsic::atomic_cmp_swap: + case Intrinsic::atomic_swap: + case Intrinsic::atomic_load_add: + case Intrinsic::atomic_load_sub: + case Intrinsic::atomic_load_and: + case Intrinsic::atomic_load_nand: + case Intrinsic::atomic_load_or: + case Intrinsic::atomic_load_xor: + case Intrinsic::atomic_load_max: + case Intrinsic::atomic_load_min: + case Intrinsic::atomic_load_umax: + case Intrinsic::atomic_load_umin: + if (TD) { + Value *Op1 = II->getOperand(1); + unsigned Op1Size = TD->getTypeStoreSize(Op1->getType()); + if (alias(Op1, Op1Size, P, Size) == NoAlias) + return NoModRef; + } + break; + case Intrinsic::lifetime_start: + case Intrinsic::lifetime_end: + case Intrinsic::invariant_start: { + unsigned PtrSize = cast(II->getOperand(1))->getZExtValue(); + if (alias(II->getOperand(2), PtrSize, P, Size) == NoAlias) + return NoModRef; + break; + } + case Intrinsic::invariant_end: { + unsigned PtrSize = cast(II->getOperand(2))->getZExtValue(); + if (alias(II->getOperand(3), PtrSize, P, Size) == NoAlias) + return NoModRef; + break; + } } // The AliasAnalysis base class has some smarts, lets use them. From sabre at nondot.org Sun Nov 22 10:15:59 2009 From: sabre at nondot.org (Chris Lattner) Date: Sun, 22 Nov 2009 16:15:59 -0000 Subject: [llvm-commits] [llvm] r89601 - in /llvm/trunk: lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/modref.ll Message-ID: <200911221615.nAMGFxt8026355@zion.cs.uiuc.edu> Author: lattner Date: Sun Nov 22 10:15:59 2009 New Revision: 89601 URL: http://llvm.org/viewvc/llvm-project?rev=89601&view=rev Log: remove a silly condition that doesn't make a lot of sense anymore. Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/test/Analysis/BasicAA/modref.ll Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=89601&r1=89600&r2=89601&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Sun Nov 22 10:15:59 2009 @@ -275,11 +275,6 @@ // AliasAnalysis::ModRefResult BasicAliasAnalysis::getModRefInfo(CallSite CS, Value *P, unsigned Size) { - // Don't do anything smart for constant pointers. - // FIXME: WHY? - if (isa(P)) - return AliasAnalysis::getModRefInfo(CS, P, Size); - const Value *Object = P->getUnderlyingObject(); // If this is a tail call and P points to a stack location, we know that Modified: llvm/trunk/test/Analysis/BasicAA/modref.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/modref.ll?rev=89601&r1=89600&r2=89601&view=diff ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/modref.ll (original) +++ llvm/trunk/test/Analysis/BasicAA/modref.ll Sun Nov 22 10:15:59 2009 @@ -90,3 +90,20 @@ ret void ; CHECK: ret void } + + at G1 = external global i32 + at G2 = external global [4000 x i32] + +define i32 @test4(i8* %P, i8 %X) { + %tmp = load i32* @G1 + call void @llvm.memset.i32(i8* bitcast ([4000 x i32]* @G2 to i8*), i8 0, i32 4000, i32 1) + %tmp2 = load i32* @G1 + %sub = sub i32 %tmp2, %tmp + ret i32 %sub +; CHECK: @test4 +; CHECK: load i32* @G +; CHECK: memset.i32 +; CHECK-NOT: load +; CHECK: sub i32 %tmp, %tmp +} + From sabre at nondot.org Sun Nov 22 10:16:48 2009 From: sabre at nondot.org (Chris Lattner) Date: Sun, 22 Nov 2009 16:16:48 -0000 Subject: [llvm-commits] [llvm] r89602 - /llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <200911221616.nAMGGm5b026391@zion.cs.uiuc.edu> Author: lattner Date: Sun Nov 22 10:16:48 2009 New Revision: 89602 URL: http://llvm.org/viewvc/llvm-project?rev=89602&view=rev Log: add fixme for dubious code. Duncan, what do you think? Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=89602&r1=89601&r2=89602&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Sun Nov 22 10:16:48 2009 @@ -263,6 +263,7 @@ bool BasicAliasAnalysis::pointsToConstantMemory(const Value *P) { if (const GlobalVariable *GV = dyn_cast(P->getUnderlyingObject())) + // FIXME: shouldn't this require GV to be "ODR"? return GV->isConstant(); return false; } From daniel at zuster.org Sun Nov 22 11:41:23 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 09:41:23 -0800 Subject: [llvm-commits] [llvm] r89516 - in /llvm/trunk: include/llvm/Target/SubtargetFeature.h lib/Target/SubtargetFeature.cpp tools/lto/LTOCodeGenerator.cpp In-Reply-To: References: <200911210000.nAL003q6027547@zion.cs.uiuc.edu> Message-ID: <6a8523d60911220941u6e633e0dhd4ee9da39dedb2ce@mail.gmail.com> On Sun, Nov 22, 2009 at 6:03 AM, Chris Lattner wrote: > > On Nov 20, 2009, at 4:00 PM, Viktor Kutuzov wrote: > >> Author: vkutuzov >> Date: Fri Nov 20 18:00:02 2009 >> New Revision: 89516 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=89516&view=rev >> Log: >> Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods. I don't think this code belongs in SubtargetFeatures at all. All it is doing is calling AddFeature on each string, the client is perfectly capable of doing this, which obviates thinking about how best to pass the vector. Similarly, AddFeatures shouldn't impose some kind of discipline like comma separate strings, clients should handle this if it is what they have (and StringRef::split makes it easy for them to split the string). - Daniel > Ok, a couple comments below: > >> +++ llvm/trunk/include/llvm/Target/SubtargetFeature.h Fri Nov 20 18:00:02 2009 >> @@ -22,6 +22,7 @@ >> #include >> #include >> #include "llvm/ADT/Triple.h" >> +#include "llvm/Support/CommandLine.h" >> #include "llvm/System/DataTypes.h" > > Please drop this #include. > >> @@ -93,6 +94,12 @@ >> ? /// Adding Features. >> ? void AddFeature(const std::string &String, bool IsEnabled = true); >> >> + ?/// Add a set of features from the comma-separated string. >> + ?void AddFeatures(const std::string &String); > > This should take a StringRef instead of std::string. > >> + >> + ?/// Add a set of features from the parsed command line parameters. >> + ?void AddFeatures(const cl::list &List); > > cl::list inherits from std::vector, so you should be able to pass in a std::vector directly. ?However, it would be much much better to expose this as taking an array of StringRef's and require the caller to do the unpacking. > > -Chris > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From daniel at zuster.org Sun Nov 22 12:06:17 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 10:06:17 -0800 Subject: [llvm-commits] [llvm] r86914 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h include/llvm/Metadata.h lib/Analysis/DebugInfo.cpp lib/VMCore/Metadata.cpp In-Reply-To: References: <200911120050.nAC0owVT014507@zion.cs.uiuc.edu> <9DC587FF-9855-4F2E-BC34-5A40A9233CEA@apple.com> Message-ID: <6a8523d60911221006y2058abd4m977ec8d3e13cbea8@mail.gmail.com> On Fri, Nov 20, 2009 at 10:22 AM, Jeffrey Yasskin wrote: > On Fri, Nov 20, 2009 at 9:20 AM, Devang Patel wrote: >> Hi! >> >> On Nov 20, 2009, at 8:32 AM, Jeffrey Yasskin wrote: >> >>> Hi Devang. This is inconvenient when I want to pass a string in from a >>> std::string, PyString, or from Function::getName(). I don't think it's >>> worth it just to let users pass 0 instead of "". >> >> The debugger and other tools consuming DWARF info are not expecting to see >> "". >> >> If StringRef are used then >> 1) The DwarfWriter needs to check for "" > > DwarfDebug::CreateGlobalVariableDIE currently does: > ?const char *LinkageName = GV.getLinkageName(); > ?if (LinkageName) { ... > > If getLinkageName returned a StringRef, DwarfDebug could use "if > (!LinkageName.empty())" instead. getLinkageName calls getStringField, > which actually jumps through hoops to _avoid_ returning a StringRef, > and to canonicalize "" to NULL ... which means that even today if the > CreateFoo functions took StringRef, users could pass "", and > DwarfDebug's current code would work. Right. Part of the problem here may be that DebugInfo tried to use StringRef from the top down, generally an API has to move to using StringRef from the bottom up -- particularly because once you have a StringRef, you aren't guaranteed it is a C string. Thus you need to start by making the APIs at the bottom able to handle StringRef, and then move upwards. As Jeffrey points out, if debug info is already ignoring "" then it would "just work" by using .empty(), on null stringrefs. >> 2) The clients needs to check for optional arguments. > > I don't understand: callers of CreateGlobalVariable, for example, > already have to pass something for LinkageName. It's not defaulted. > And if it were defaulted, defaulting to "" would be as easy as > defaulting to NULL. > > If you're talking about clients like gdb, it's clearly a win to write > less debug information when a field isn't present, but "" should count > as not present. > >> If const char * are used then only clients needs to get pointer to the >> string. >> >> My preferred approach was to let StringRef handle null for optional >> arguments, but it has performance implications. > > I think my position on StringRef is that StringRef() should equal > either StringRef(NULL) or StringRef(""). If we like people using NULL > for "no data", then StringRef(NULL) should work. If not?if we don't > think there's a use for two "no data" representations, which is my > position?then StringRef() should ==StringRef(""), which allows > DwarfDebug to only handle one case again, even if it wants to pull the > data out of the StringRef. > ... but that's not particularly important for debug info. StringRef() equals StringRef(0). StringRef is a "ref", so you get what you put in. (StringRef(p).data() == p). - Daniel >> I am not tied to one position, but prefer a approach that makes either >> DwarfWriter OR clients responsible to do the right thing. >> >> - >> Devang >>> >>> On Wed, Nov 11, 2009 at 4:50 PM, Devang Patel wrote: >>>> >>>> Author: dpatel >>>> Date: Wed Nov 11 18:50:58 2009 >>>> New Revision: 86914 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=86914&view=rev >>>> Log: >>>> Do not use StringRef in DebugInfo interface. >>>> This allows StringRef to skip controversial if(str) check in constructor. >>>> Buildbots, wait for corresponding clang and llvm-gcc FE check-ins! >>>> >>>> Modified: >>>> ? llvm/trunk/include/llvm/Analysis/DebugInfo.h >>>> ? llvm/trunk/include/llvm/Metadata.h >>>> ? llvm/trunk/lib/Analysis/DebugInfo.cpp >>>> ? llvm/trunk/lib/VMCore/Metadata.cpp >>>> >>>> Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h >>>> URL: >>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=86914&r1=86913&r2=86914&view=diff >>>> >>>> >>>> ============================================================================== >>>> --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) >>>> +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Wed Nov 11 18:50:58 2009 >>>> @@ -496,26 +496,26 @@ >>>> ? ?/// CreateCompileUnit - Create a new descriptor for the specified >>>> compile >>>> ? ?/// unit. >>>> ? ?DICompileUnit CreateCompileUnit(unsigned LangID, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Filenae, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Directory, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Producer, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Filename, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Directory, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Producer, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool isMain = false, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool isOptimized = false, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char *Flags = "", >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned RunTimeVer = 0); >>>> >>>> ? ?/// CreateEnumerator - Create a single enumerator value. >>>> - ? ?DIEnumerator CreateEnumerator(StringRef Name, uint64_t Val); >>>> + ? ?DIEnumerator CreateEnumerator(const char * Name, uint64_t Val); >>>> >>>> ? ?/// CreateBasicType - Create a basic type like int, float, etc. >>>> - ? ?DIBasicType CreateBasicType(DIDescriptor Context, StringRef Name, >>>> + ? ?DIBasicType CreateBasicType(DIDescriptor Context, const char * Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, unsigned >>>> LineNumber, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t SizeInBits, uint64_t AlignInBits, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t OffsetInBits, unsigned Flags, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned Encoding); >>>> >>>> ? ?/// CreateBasicType - Create a basic type like int, float, etc. >>>> - ? ?DIBasicType CreateBasicTypeEx(DIDescriptor Context, StringRef Name, >>>> + ? ?DIBasicType CreateBasicTypeEx(DIDescriptor Context, const char * >>>> Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, unsigned >>>> LineNumber, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Constant *SizeInBits, Constant >>>> *AlignInBits, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Constant *OffsetInBits, unsigned Flags, >>>> @@ -524,7 +524,7 @@ >>>> ? ?/// CreateDerivedType - Create a derived type like const qualified >>>> type, >>>> ? ?/// pointer, typedef, etc. >>>> ? ?DIDerivedType CreateDerivedType(unsigned Tag, DIDescriptor Context, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t SizeInBits, uint64_t >>>> AlignInBits, >>>> @@ -534,7 +534,7 @@ >>>> ? ?/// CreateDerivedType - Create a derived type like const qualified >>>> type, >>>> ? ?/// pointer, typedef, etc. >>>> ? ?DIDerivedType CreateDerivedTypeEx(unsigned Tag, DIDescriptor Context, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Constant *SizeInBits, Constant >>>> *AlignInBits, >>>> @@ -543,7 +543,7 @@ >>>> >>>> ? ?/// CreateCompositeType - Create a composite type like array, struct, >>>> etc. >>>> ? ?DICompositeType CreateCompositeType(unsigned Tag, DIDescriptor >>>> Context, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t SizeInBits, >>>> @@ -555,7 +555,7 @@ >>>> >>>> ? ?/// CreateCompositeType - Create a composite type like array, struct, >>>> etc. >>>> ? ?DICompositeType CreateCompositeTypeEx(unsigned Tag, DIDescriptor >>>> Context, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNumber, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Constant *SizeInBits, >>>> @@ -567,25 +567,25 @@ >>>> >>>> ? ?/// CreateSubprogram - Create a new descriptor for the specified >>>> subprogram. >>>> ? ?/// See comments in DISubprogram for descriptions of these fields. >>>> - ? ?DISubprogram CreateSubprogram(DIDescriptor Context, StringRef Name, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef DisplayName, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef LinkageName, >>>> + ? ?DISubprogram CreateSubprogram(DIDescriptor Context, const char * >>>> Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * DisplayName, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * LinkageName, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, unsigned >>>> LineNo, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DIType Type, bool isLocalToUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool isDefinition); >>>> >>>> ? ?/// CreateGlobalVariable - Create a new descriptor for the specified >>>> global. >>>> ? ?DIGlobalVariable >>>> - ? ?CreateGlobalVariable(DIDescriptor Context, StringRef Name, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? StringRef DisplayName, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? StringRef LinkageName, >>>> + ? ?CreateGlobalVariable(DIDescriptor Context, const char * Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? const char * DisplayName, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? const char * LinkageName, >>>> ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNo, DIType Type, bool isLocalToUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? bool isDefinition, llvm::GlobalVariable *GV); >>>> >>>> ? ?/// CreateVariable - Create a new descriptor for the specified >>>> variable. >>>> ? ?DIVariable CreateVariable(unsigned Tag, DIDescriptor Context, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, unsigned LineNo, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DIType Type); >>>> >>>> >>>> Modified: llvm/trunk/include/llvm/Metadata.h >>>> URL: >>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Metadata.h?rev=86914&r1=86913&r2=86914&view=diff >>>> >>>> >>>> ============================================================================== >>>> --- llvm/trunk/include/llvm/Metadata.h (original) >>>> +++ llvm/trunk/include/llvm/Metadata.h Wed Nov 11 18:50:58 2009 >>>> @@ -60,6 +60,7 @@ >>>> >>>> ?public: >>>> ?static MDString *get(LLVMContext &Context, StringRef Str); >>>> + ?static MDString *get(LLVMContext &Context, const char *Str); >>>> >>>> ?StringRef getString() const { return Str; } >>>> >>>> >>>> Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp >>>> URL: >>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=86914&r1=86913&r2=86914&view=diff >>>> >>>> >>>> ============================================================================== >>>> --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) >>>> +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Wed Nov 11 18:50:58 2009 >>>> @@ -653,9 +653,9 @@ >>>> ?/// CreateCompileUnit - Create a new descriptor for the specified >>>> compile >>>> ?/// unit. ?Note that this does not unique compile units within the >>>> module. >>>> ?DICompileUnit DIFactory::CreateCompileUnit(unsigned LangID, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Filename, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Directory, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Producer, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Filename, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Directory, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Producer, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool isMain, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool isOptimized, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char *Flags, >>>> @@ -677,7 +677,7 @@ >>>> ?} >>>> >>>> ?/// CreateEnumerator - Create a single enumerator value. >>>> -DIEnumerator DIFactory::CreateEnumerator(StringRef Name, uint64_t Val){ >>>> +DIEnumerator DIFactory::CreateEnumerator(const char * Name, uint64_t >>>> Val){ >>>> ?Value *Elts[] = { >>>> ? ?GetTagConstant(dwarf::DW_TAG_enumerator), >>>> ? ?MDString::get(VMContext, Name), >>>> @@ -689,7 +689,7 @@ >>>> >>>> ?/// CreateBasicType - Create a basic type like int, float, etc. >>>> ?DIBasicType DIFactory::CreateBasicType(DIDescriptor Context, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint64_t SizeInBits, >>>> @@ -714,7 +714,7 @@ >>>> >>>> ?/// CreateBasicType - Create a basic type like int, float, etc. >>>> ?DIBasicType DIFactory::CreateBasicTypeEx(DIDescriptor Context, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Constant *SizeInBits, >>>> @@ -741,7 +741,7 @@ >>>> ?/// pointer, typedef, etc. >>>> ?DIDerivedType DIFactory::CreateDerivedType(unsigned Tag, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DIDescriptor Context, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint64_t SizeInBits, >>>> @@ -769,7 +769,7 @@ >>>> ?/// pointer, typedef, etc. >>>> ?DIDerivedType DIFactory::CreateDerivedTypeEx(unsigned Tag, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DIDescriptor Context, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Constant *SizeInBits, >>>> @@ -796,7 +796,7 @@ >>>> ?/// CreateCompositeType - Create a composite type like array, struct, >>>> etc. >>>> ?DICompositeType DIFactory::CreateCompositeType(unsigned Tag, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DIDescriptor Context, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint64_t SizeInBits, >>>> @@ -828,7 +828,7 @@ >>>> ?/// CreateCompositeType - Create a composite type like array, struct, >>>> etc. >>>> ?DICompositeType DIFactory::CreateCompositeTypeEx(unsigned Tag, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DIDescriptor Context, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit >>>> CompileUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNumber, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Constant *SizeInBits, >>>> @@ -861,9 +861,9 @@ >>>> ?/// See comments in DISubprogram for descriptions of these fields. ?This >>>> ?/// method does not unique the generated descriptors. >>>> ?DISubprogram DIFactory::CreateSubprogram(DIDescriptor Context, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef DisplayName, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef LinkageName, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * DisplayName, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * LinkageName, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned LineNo, DIType Type, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool isLocalToUnit, >>>> @@ -887,9 +887,9 @@ >>>> >>>> ?/// CreateGlobalVariable - Create a new descriptor for the specified >>>> global. >>>> ?DIGlobalVariable >>>> -DIFactory::CreateGlobalVariable(DIDescriptor Context, StringRef Name, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef DisplayName, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef LinkageName, >>>> +DIFactory::CreateGlobalVariable(DIDescriptor Context, const char * Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * DisplayName, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const char * LinkageName, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DICompileUnit CompileUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned LineNo, DIType Type,bool >>>> isLocalToUnit, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool isDefinition, llvm::GlobalVariable >>>> *Val) { >>>> @@ -921,7 +921,7 @@ >>>> >>>> ?/// CreateVariable - Create a new descriptor for the specified variable. >>>> ?DIVariable DIFactory::CreateVariable(unsigned Tag, DIDescriptor Context, >>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef Name, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const char * Name, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DICompileUnit CompileUnit, unsigned >>>> LineNo, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DIType Type) { >>>> ?Value *Elts[] = { >>>> >>>> Modified: llvm/trunk/lib/VMCore/Metadata.cpp >>>> URL: >>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=86914&r1=86913&r2=86914&view=diff >>>> >>>> >>>> ============================================================================== >>>> --- llvm/trunk/lib/VMCore/Metadata.cpp (original) >>>> +++ llvm/trunk/lib/VMCore/Metadata.cpp Wed Nov 11 18:50:58 2009 >>>> @@ -39,6 +39,17 @@ >>>> ? ?new MDString(Context, Entry.getKey()); >>>> ?} >>>> >>>> +MDString *MDString::get(LLVMContext &Context, const char *Str) { >>>> + ?LLVMContextImpl *pImpl = Context.pImpl; >>>> + ?StringMapEntry &Entry = >>>> + ? ?pImpl->MDStringCache.GetOrCreateValue(Str ? StringRef(Str) : >>>> StringRef()); >>>> + ?MDString *&S = Entry.getValue(); >>>> + ?if (S) return S; >>>> + >>>> + ?return S = >>>> + ? ?new MDString(Context, Entry.getKey()); >>>> +} >>>> + >>>> >>>> ?//===----------------------------------------------------------------------===// >>>> ?// MDNode implementation. >>>> ?// >>>> >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>> >> >> > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From daniel at zuster.org Sun Nov 22 12:08:46 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 10:08:46 -0800 Subject: [llvm-commits] [PATCH] LTO code generator options In-Reply-To: <38a0d8450911200722i5efa690ci6ab671d71b5f40dc@mail.gmail.com> References: <04F6B1512E264B27AEE607542FCDD113@andreic6e7fe55> <6AE1604EE3EC5F4296C096518C6B77EEFD4607BF@mail.accesssoftek.com> <38a0d8450911170809j6a32716ar840b8622cfad6f17@mail.gmail.com> <6AE1604EE3EC5F4296C096518C6B77EEFD4607C4@mail.accesssoftek.com> <38a0d8450911180722j5a463fa8hec81178154deaf09@mail.gmail.com> <41BA1AA405BC4D19BA9B4FAB6543D62F@andreic6e7fe55> <38a0d8450911190723g644ad4c7ife769ab35da9efb9@mail.gmail.com> <38a0d8450911200722i5efa690ci6ab671d71b5f40dc@mail.gmail.com> Message-ID: <6a8523d60911221008t431f5662v369a3ebd910a8696@mail.gmail.com> On Fri, Nov 20, 2009 at 7:22 AM, Rafael Espindola wrote: >> StringRef::split would do. >> The issue here is: SubtargetFeatures class uses std::strings and has a >> helper method Split which is used in few other places. >> I'm trying to follow this. I don't like the idea to use StringRef::split >> only in this particular place. >> However, I wouldn't mind to re-factor the SubtargetFeatures class to use >> StringRef instead of std::strings and prepare another patch. Shell I do so? Please! > You don't need to. If Split is used elsewhere I agree it is better to > use it in here too. Uh, why? We should kill off duplicate code. - Daniel >>> You say features are normalized, why does hasFeature needs to convert >>> to lowercase and strip flags? >> >> Features are normalized inside the SubtargetFeatures class. hasFeature gets >> a string which also should be normalized to compare with the already >> normalized features. >> We need to strip the flag because we do not care was this feature set on or >> off, we simply want to know if it was set or not. >> But if you have the question, I'll better add a comment there to clarify >> this. How about something like this: "Normalize the given string to compare >> with the normalized features, and strip the flag since we are checking was >> this feature set at all without checking was it set on or off."? > > I think I am still missing something. First on the flag, what is the > expected result of doing AddFeature("foo", true); AddFeature("foo", > false). The patch implements a "first one wins". Is that correct? > Assuming that is the desired behavior I understand the calls to > StripFlag, but the call to LowercaseString still looks redundant: > > *) hasFeature is called only from AddFeature > *) the string passed to it was generated with > PrependFlag(LowercaseString(String), IsEnabled) > > A comment explaining this should do. > >>> The comment about "after all explicit feature settings" is a future >>> reference, right? I don't see any feature being set :-) >> >> You are right. This is a future reference. Next patch will add explicit >> settings of cpu and attributes. We just need to get there. :) >> >>> The method SubtargetFeatures::AddFeatures(const cl::list >>> &List) is not being used, is it? >> >> I didn't find a way to add the usage in this patch without adding a lot of >> other changes to get it work. This will be in the next patch and the usage >> will look like this in the LTOCodeGenerator.cpp file: >> >> ... >> +static cl::list MAttrs("mattr", >> + ?cl::CommaSeparated, >> + ?cl::desc("Target specific attributes (see -mattr=help for details)"), >> + ?cl::value_desc("a1,+a2,-a3,...")); >> + >> ... >> >> bool LTOCodeGenerator::determineTarget(std::string& errMsg) >> ... >> + ? ? ? ?// Prepare subtarget feature set for the given command line >> options. >> + ? ? ? ?SubtargetFeatures features; >> ... >> + ? ? ? ?if (!MAttrs.empty()) >> + ? ? ? ? ? ?features.AddFeatures(MAttrs); >> + >> + ? ? ? ?// Set the rest of features by default. >> + ? ? ? ?// Note: Please keep this after all explict feature settings to >> make sure >> + ? ? ? ?// defaults will not override explicitly set options. >> + >> ?features.AddFeatures(SubtargetFeatures::getDefaultSubTargetTripleFeatures(_targetTriple)); >> ... >> >> Which also fill that "keep this after all explict feature settings" comment >> with meaning. >> >> Is it Ok to ssubmit this patch? > > OK with the comment explaining the addFeature, hasFeature behavior. > >> Cheers, >> Viktor > > > Cheers, > -- > Rafael ?vila de Esp?ndola > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From stoklund at 2pi.dk Sun Nov 22 12:11:20 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sun, 22 Nov 2009 10:11:20 -0800 Subject: [llvm-commits] [llvm] r89530 - in /llvm/trunk: include/llvm/CodeGen/LiveVariables.h lib/CodeGen/LiveVariables.cpp lib/CodeGen/PHIElimination.cpp lib/CodeGen/PHIElimination.h In-Reply-To: <58E5E7B6-3416-472E-8C1A-363DDDE5A930@apple.com> References: <200911210205.nAL25M36031984@zion.cs.uiuc.edu> <58E5E7B6-3416-472E-8C1A-363DDDE5A930@apple.com> Message-ID: <8F6DD22D-65D7-478C-8F62-FAF933194FE1@2pi.dk> On Nov 22, 2009, at 6:09 AM, Chris Lattner wrote: > > I haven't looked at the code at all, but I want to bring up one subtlety of critical edge splitting. In switches which have multiple edges to the same destination (on different values), these edges are always critical. However, they should be split together as a unit, not individually. I don't know if your code considers this or not, but this is the idea behind the "SplitEdgeNicely" logic that appears in a couple places. I hadn't considered that issue, but I think I have managed to avoid it. At the machine code level, switches become either branching trees or jumptable branches. In the first case, the switch has been converted to if/else code, and the issue disappears. In the second case I leave the edge alone because AnalyzeBranch fails. I don't want to start tampering with jump tables because I think they can be shared. Thanks, /jakob -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091122/c95e093c/attachment.bin From daniel at zuster.org Sun Nov 22 12:21:37 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 10:21:37 -0800 Subject: [llvm-commits] [llvm] r89211 - /llvm/trunk/CMakeLists.txt In-Reply-To: <87lji25i81.fsf@telefonica.net> References: <200911181742.nAIHgMXe005175@zion.cs.uiuc.edu> <87lji25i81.fsf@telefonica.net> Message-ID: <6a8523d60911221021t75d68290j30060188af1734ca@mail.gmail.com> On Thu, Nov 19, 2009 at 1:15 PM, ?scar Fuentes wrote: > Hello Daniel. > > Daniel Dunbar writes: > >> URL: http://llvm.org/viewvc/llvm-project?rev=89211&view=rev >> Log: >> Turn LLVM_BUILD_EXAMPLES off by default in CMake builds, to match Makefiles & >> Clang. > > What's the rationale for this? > > (And wouldn't it warrant the corresponding update of docs/CMake.html, > where default values for variables are listed?) The rationale for changing the default (for cmake and make, I assume we agree they should have the same default) is that most people building LLVM don't care about the examples (because they are developers), and this greatly increases cycle times because of the sheer number of link steps it adds. Having examples be "optional" builds for people exploring LLVM seems reasonable to me, the only value I see in building them regularly is to prevent them from being out-dated, but I will change (one, fast) buildbot to maintain that. I will update the doc. - Daniel > -- > ?scar > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From daniel at zuster.org Sun Nov 22 12:27:44 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 18:27:44 -0000 Subject: [llvm-commits] [llvm] r89606 - /llvm/trunk/include/llvm/Support/NoFolder.h Message-ID: <200911221827.nAMIRiEv030653@zion.cs.uiuc.edu> Author: ddunbar Date: Sun Nov 22 12:27:43 2009 New Revision: 89606 URL: http://llvm.org/viewvc/llvm-project?rev=89606&view=rev Log: Use ExtractElementInst::Create instead of new; patch by Artur Pietrek! Modified: llvm/trunk/include/llvm/Support/NoFolder.h Modified: llvm/trunk/include/llvm/Support/NoFolder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/NoFolder.h?rev=89606&r1=89605&r2=89606&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/NoFolder.h (original) +++ llvm/trunk/include/llvm/Support/NoFolder.h Sun Nov 22 12:27:43 2009 @@ -174,7 +174,7 @@ } Value *CreateExtractElement(Constant *Vec, Constant *Idx) const { - return new ExtractElementInst(Vec, Idx); + return ExtractElementInst::Create(Vec, Idx); } Value *CreateInsertElement(Constant *Vec, Constant *NewElt, From daniel at zuster.org Sun Nov 22 12:27:51 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 18:27:51 -0000 Subject: [llvm-commits] [llvm] r89607 - /llvm/trunk/docs/CMake.html Message-ID: <200911221827.nAMIRpJd030669@zion.cs.uiuc.edu> Author: ddunbar Date: Sun Nov 22 12:27:51 2009 New Revision: 89607 URL: http://llvm.org/viewvc/llvm-project?rev=89607&view=rev Log: Update doc re: LLVM_BUILD_EXAMPLES. Modified: llvm/trunk/docs/CMake.html Modified: llvm/trunk/docs/CMake.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CMake.html?rev=89607&r1=89606&r2=89607&view=diff ============================================================================== --- llvm/trunk/docs/CMake.html (original) +++ llvm/trunk/docs/CMake.html Sun Nov 22 12:27:51 2009 @@ -254,7 +254,7 @@
Build LLVM tools. Defaults to ON.
LLVM_BUILD_EXAMPLES:BOOL
-
Build LLVM examples. Defaults to ON.
+
Build LLVM examples. Defaults to OFF.
LLVM_ENABLE_THREADS:BOOL
Build with threads support, if available. Defaults to ON.
From stoklund at 2pi.dk Sun Nov 22 12:28:04 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sun, 22 Nov 2009 18:28:04 -0000 Subject: [llvm-commits] [llvm] r89608 - /llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Message-ID: <200911221828.nAMIS4ZY030686@zion.cs.uiuc.edu> Author: stoklund Date: Sun Nov 22 12:28:04 2009 New Revision: 89608 URL: http://llvm.org/viewvc/llvm-project?rev=89608&view=rev Log: Teach MachineBasicBlock::updateTerminator() to handle a failing TII->ReverseBranchCondition(Cond) call. This fixes the MallocBench/cfrac test case regression. Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=89608&r1=89607&r2=89608&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Sun Nov 22 12:28:04 2009 @@ -279,8 +279,9 @@ // successors is its layout successor, rewrite it to a fallthrough // conditional branch. if (isLayoutSuccessor(TBB)) { + if (TII->ReverseBranchCondition(Cond)) + return; TII->RemoveBranch(*this); - TII->ReverseBranchCondition(Cond); TII->InsertBranch(*this, FBB, 0, Cond); } else if (isLayoutSuccessor(FBB)) { TII->RemoveBranch(*this); @@ -292,8 +293,13 @@ MachineBasicBlock *MBBB = *next(succ_begin()); if (MBBA == TBB) std::swap(MBBB, MBBA); if (isLayoutSuccessor(TBB)) { + if (TII->ReverseBranchCondition(Cond)) { + // We can't reverse the condition, add an unconditional branch. + Cond.clear(); + TII->InsertBranch(*this, MBBA, 0, Cond); + return; + } TII->RemoveBranch(*this); - TII->ReverseBranchCondition(Cond); TII->InsertBranch(*this, MBBA, 0, Cond); } else if (!isLayoutSuccessor(MBBA)) { TII->RemoveBranch(*this); From grosbach at apple.com Sun Nov 22 12:28:26 2009 From: grosbach at apple.com (Jim Grosbach) Date: Sun, 22 Nov 2009 10:28:26 -0800 Subject: [llvm-commits] [llvm] r89403 - /llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp In-Reply-To: References: <200911192310.nAJNASND022655@zion.cs.uiuc.edu> Message-ID: <6A655B82-5A9A-4854-A1C8-98E2DF7EE8E7@apple.com> On Nov 22, 2009, at 6:00 AM, Chris Lattner wrote: > > On Nov 19, 2009, at 3:10 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Thu Nov 19 17:10:28 2009 >> New Revision: 89403 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=89403&view=rev >> Log: >> When placing constant islands and adjusting for alignment padding, >> inline >> assembly can confuse things utterly, as it's assumed that >> instructions in >> inline assembly are 4 bytes wide. For Thumb mode, that's often not >> true, >> so the calculations for when alignment padding will be present get >> thrown off, >> ultimately leading to out of range constant pool entry references. >> Making >> more conservative assumptions that padding may be necessary when >> inline asm >> is present avoids this situation. > > Are you sure that this is the right thing to do? GCC inline asm > precisely specifies how the size of an inline asm is computed: > http://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#Extended-Asm > (6.39.1) > > If some inline asm isn't working with this algorithm, then the > inline asm is wrong and should be fixed. Yes, I believe this is the correct approach. The algorithm described is, "The estimate is formed by counting the number of statements in the pattern of the asm and multiplying that by the length of the longest instruction on that processor." This is exactly what we do, and gets us close, but it is still an estimate. To do better, we'll need to actually parse the assembly code to determine whether it's a 16 or a 32 bit instruction. In Thumb2, that's a non- trivial thing, and I suspect we don't want to go down that path, at least right now. What's happening here is that the inline asm is actually shorter than the estimate since it's a 16-bit instruction, and is also not located between the constant pool reference and the constant pool entry. Since it's different in size than what the estimate believes, our calculations for when alignment padding will be inserted are now off, leading to problems. This patch adjusts those padding calculations to know that in the presence of inline assembly, we're dealing with an estimate and therefore can't make assumptions about alignment padding. -Jim From daniel at zuster.org Sun Nov 22 12:45:48 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 10:45:48 -0800 Subject: [llvm-commits] [llvm] r89111 - in /llvm/trunk/lib: Support/CommandLine.cpp System/Host.cpp In-Reply-To: <200911171757.nAHHv4lH002679@zion.cs.uiuc.edu> References: <200911171757.nAHHv4lH002679@zion.cs.uiuc.edu> Message-ID: <6a8523d60911221045v806143k6dab555c3c83a628@mail.gmail.com> Hi Benjamin, I didn't see these failures, can you point me at what was failing? I would rather the API behave as it is currently documented, and that clients sort this out, although maybe it isn't worth worrying about. - Daniel On Tue, Nov 17, 2009 at 9:57 AM, Benjamin Kramer wrote: > Author: d0k > Date: Tue Nov 17 11:57:04 2009 > New Revision: 89111 > > URL: http://llvm.org/viewvc/llvm-project?rev=89111&view=rev > Log: > Revert CPU detection code to return "generic" instead of an empty string in case > of failure. The x86 target didn't like empty cpu names and broke x86 tests on > non-x86 buildbots. > > Modified: > ? ?llvm/trunk/lib/Support/CommandLine.cpp > ? ?llvm/trunk/lib/System/Host.cpp > > Modified: llvm/trunk/lib/Support/CommandLine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=89111&r1=89110&r2=89111&view=diff > > ============================================================================== > --- llvm/trunk/lib/Support/CommandLine.cpp (original) > +++ llvm/trunk/lib/Support/CommandLine.cpp Tue Nov 17 11:57:04 2009 > @@ -1154,7 +1154,7 @@ > ? ? OS << " with assertions"; > ?#endif > ? ? std::string CPU = sys::getHostCPUName(); > - ? ?if (CPU.empty()) CPU = "(unknown)"; > + ? ?if (CPU == "generic") CPU = "(unknown)"; > ? ? OS << ".\n" > ? ? ? ?<< " ?Built " << __DATE__ << " (" << __TIME__ << ").\n" > ? ? ? ?<< " ?Host: " << sys::getHostTriple() << '\n' > > Modified: llvm/trunk/lib/System/Host.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Host.cpp?rev=89111&r1=89110&r2=89111&view=diff > > ============================================================================== > --- llvm/trunk/lib/System/Host.cpp (original) > +++ llvm/trunk/lib/System/Host.cpp Tue Nov 17 11:57:04 2009 > @@ -249,7 +249,7 @@ > ? ? } > > ? ? default: > - ? ? ?return ""; > + ? ? ?return "generic"; > ? ? } > ? } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) { > ? ? // FIXME: this poorly matches the generated SubtargetFeatureKV table. ?There > @@ -289,10 +289,10 @@ > ? ? ? case 16: > ? ? ? ? return "amdfam10"; > ? ? default: > - ? ? ?return ""; > + ? ? ?return "generic"; > ? ? } > ? } > ?#endif > > - ?return ""; > + ?return "generic"; > ?} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From nicholas at mxc.ca Sun Nov 22 12:51:04 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 22 Nov 2009 10:51:04 -0800 Subject: [llvm-commits] [llvm] r89211 - /llvm/trunk/CMakeLists.txt In-Reply-To: <6a8523d60911221021t75d68290j30060188af1734ca@mail.gmail.com> References: <200911181742.nAIHgMXe005175@zion.cs.uiuc.edu> <87lji25i81.fsf@telefonica.net> <6a8523d60911221021t75d68290j30060188af1734ca@mail.gmail.com> Message-ID: <4B098818.4000506@mxc.ca> Daniel Dunbar wrote: > On Thu, Nov 19, 2009 at 1:15 PM, ?scar Fuentes wrote: >> Hello Daniel. >> >> Daniel Dunbar writes: >> >>> URL: http://llvm.org/viewvc/llvm-project?rev=89211&view=rev >>> Log: >>> Turn LLVM_BUILD_EXAMPLES off by default in CMake builds, to match Makefiles& >>> Clang. >> >> What's the rationale for this? >> >> (And wouldn't it warrant the corresponding update of docs/CMake.html, >> where default values for variables are listed?) > > The rationale for changing the default (for cmake and make, I assume > we agree they should have the same default) is that most people > building LLVM don't care about the examples (because they are > developers), and this greatly increases cycle times because of the > sheer number of link steps it adds. Having examples be "optional" > builds for people exploring LLVM seems reasonable to me, the only > value I see in building them regularly is to prevent them from being > out-dated, but I will change (one, fast) buildbot to maintain that. > > I will update the doc. The rationale for copying each Kaleidoscope chapter into the examples/ directory was to make sure that our examples on the website don't get out of date when someone changes the API. This just means that people will run make and make check, commit, and then discover that their change somehow broke the buildbots. It'd be nice to notice and resolve the breakage before committing. Nick From daniel at zuster.org Sun Nov 22 12:55:37 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 10:55:37 -0800 Subject: [llvm-commits] [llvm] r88979 - /llvm/trunk/Makefile In-Reply-To: <4B0256AD.2040909@free.fr> References: <200911162238.nAGMc189009001@zion.cs.uiuc.edu> <4B0256AD.2040909@free.fr> Message-ID: <6a8523d60911221055m6389806q789720c839e93a82@mail.gmail.com> On Mon, Nov 16, 2009 at 11:54 PM, Duncan Sands wrote: > Hi Daniel, > >> Don't build examples by default, use BUILD_EXAMPLES=1 to build them. The >> only utility of this is testing that we keep the examples up to date, I will >> just make the buildbots run with this flag. > > is this really a good idea? Yes, I think so. I don't think the examples break that often. Additionally, developers changing APIs widely are already probably using grep or other tools to find the code to fix, and can always test the examples directly. > ?If someone breaks an example, wouldn't it be > better > for them to discover that directly themselves rather than via a buildbot? No, this optimizes for the rare case (single developer, breaking single build) at the expensive of the extraordinarily common case (many many developers and buildbots, rebuilding llvm). > ?And > what about newcomers who want to build examples - aren't they going to have > a > hard time working out how to build the examples? Probably not, I think its pretty common to have optional code that isn't built by default. Frequently located in the examples directory. I'll add some more docs if you think I should and point me to where you would like them. Also viable would be to change this setting for releases. - Daniel > Ciao, > > Duncan. > From daniel at zuster.org Sun Nov 22 12:57:51 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 10:57:51 -0800 Subject: [llvm-commits] [llvm] r88979 - /llvm/trunk/Makefile In-Reply-To: <874ootci0e.fsf@telefonica.net> References: <200911162238.nAGMc189009001@zion.cs.uiuc.edu> <4B0256AD.2040909@free.fr> <874ootci0e.fsf@telefonica.net> Message-ID: <6a8523d60911221057m7c8f0698gfbfaa2d915f3856e@mail.gmail.com> On Tue, Nov 17, 2009 at 7:01 AM, ?scar Fuentes wrote: > Duncan Sands writes: > >>> Don't ?build ?examples ?by ?default, use ?BUILD_EXAMPLES=1 ?to ?build >>> them. The only ?utility of this is testing that ?we keep the examples >>> up to date, I will just make the buildbots run with this flag. >> >> is this really a good idea? ?If someone breaks an example, wouldn't it >> be better for them to discover that directly themselves rather than >> via a buildbot? ?And what about newcomers who want to build examples - >> aren't they going to have a hard time working out how to build the >> examples? > > FWIW, I agree with Duncan. > > The defaults should be newbie-friendly. The majority of people doing LLVM builds (by volume) are developers, not newbies. Even newbies aren't likely to care to build the examples that often, if they actually start using LLVM. - Daniel > -- > ?scar > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From ofv at wanadoo.es Sun Nov 22 13:01:45 2009 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Sun, 22 Nov 2009 20:01:45 +0100 Subject: [llvm-commits] [llvm] r89211 - /llvm/trunk/CMakeLists.txt References: <200911181742.nAIHgMXe005175@zion.cs.uiuc.edu> <87lji25i81.fsf@telefonica.net> <6a8523d60911221021t75d68290j30060188af1734ca@mail.gmail.com> Message-ID: <87pr7a4c4m.fsf@telefonica.net> Daniel Dunbar writes: >>> URL: http://llvm.org/viewvc/llvm-project?rev=89211&view=rev >>> Log: >>> Turn LLVM_BUILD_EXAMPLES off by default in CMake builds, to match Makefiles & >>> Clang. >> >> What's the rationale for this? >> >> (And wouldn't it warrant the corresponding update of docs/CMake.html, >> where default values for variables are listed?) > > The rationale for changing the default (for cmake and make, I assume > we agree they should have the same default) is that most people > building LLVM don't care about the examples (because they are > developers), and this greatly increases cycle times because of the > sheer number of link steps it adds. Having examples be "optional" > builds for people exploring LLVM seems reasonable to me, the only > value I see in building them regularly is to prevent them from being > out-dated, but I will change (one, fast) buildbot to maintain that. I do not agree with this policy. IMHO making things as straightforward as possible for people exploring LLVM is more important than removing little annoyances for developers (and having to write -DLLVM_BUILD_EXAMPLES=OFF when you configure a fresh checkout is a little annoyance). But this is just IMHO. One compromise that we can easily implement (at least on the cmake build) is to default to OFF when building from a svn checkout and ON otherwise. What do you think? > I will update the doc. Thanks. -- ?scar From anton at korobeynikov.info Sun Nov 22 13:06:23 2009 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Sun, 22 Nov 2009 22:06:23 +0300 Subject: [llvm-commits] [llvm] r89530 - in /llvm/trunk: include/llvm/CodeGen/LiveVariables.h lib/CodeGen/LiveVariables.cpp lib/CodeGen/PHIElimination.cpp lib/CodeGen/PHIElimination.h In-Reply-To: <8F6DD22D-65D7-478C-8F62-FAF933194FE1@2pi.dk> References: <200911210205.nAL25M36031984@zion.cs.uiuc.edu> <58E5E7B6-3416-472E-8C1A-363DDDE5A930@apple.com> <8F6DD22D-65D7-478C-8F62-FAF933194FE1@2pi.dk> Message-ID: Hello, Jakob > At the machine code level, switches become either branching trees or jumptable branches. No :) There are 4 different "patterns" used currently for switch lowering: 1. Direct comparison (used for small switches) 2. Jumpt tables (used for dense switches) 3. Bit-tests (used for switches with not so big range span and going into few destinations) 4. Branch trees combining 1 / 2 / 3 -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From benny.kra at googlemail.com Sun Nov 22 13:06:36 2009 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Sun, 22 Nov 2009 20:06:36 +0100 Subject: [llvm-commits] [llvm] r89111 - in /llvm/trunk/lib: Support/CommandLine.cpp System/Host.cpp In-Reply-To: <6a8523d60911221045v806143k6dab555c3c83a628@mail.gmail.com> References: <200911171757.nAHHv4lH002679@zion.cs.uiuc.edu> <6a8523d60911221045v806143k6dab555c3c83a628@mail.gmail.com> Message-ID: <4A222DFC-290F-4019-9DF6-2BBA0017B941@gmail.com> Am 22.11.2009 um 19:45 schrieb Daniel Dunbar: > Hi Benjamin, > > I didn't see these failures, can you point me at what was failing? I > would rather the API behave as it is currently documented, and that > clients sort this out, although maybe it isn't worth worrying about. > > - Daniel Many x86 tests (about 200 iirc) were failing on our arm and ppc linux buildbots with a message like "'' is not a valid CPU". You probably didn't notice it because both had a failing unit test at that time. From grosbach at apple.com Sun Nov 22 13:20:36 2009 From: grosbach at apple.com (Jim Grosbach) Date: Sun, 22 Nov 2009 19:20:36 -0000 Subject: [llvm-commits] [llvm] r89612 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <200911221920.nAMJKbrU032596@zion.cs.uiuc.edu> Author: grosbach Date: Sun Nov 22 13:20:36 2009 New Revision: 89612 URL: http://llvm.org/viewvc/llvm-project?rev=89612&view=rev Log: 80-column cleanup Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=89612&r1=89611&r2=89612&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Sun Nov 22 13:20:36 2009 @@ -119,7 +119,8 @@ return IndexTyDie; } - // setIndexTyDie - Set D as anonymous type for index which can be reused later. + // setIndexTyDie - Set D as anonymous type for index which can be reused + // later. void setIndexTyDie(DIE *D) { IndexTyDie = D; } @@ -982,7 +983,8 @@ /// createGlobalVariableDIE - Create new DIE using GV. DIE *DwarfDebug::createGlobalVariableDIE(CompileUnit *DW_Unit, const DIGlobalVariable &GV) { - // If the global variable was optmized out then no need to create debug info entry. + // If the global variable was optmized out then no need to create debug info + // entry. if (!GV.getGlobal()) return NULL; if (!GV.getDisplayName()) return NULL; @@ -1080,9 +1082,10 @@ const char *LinkageName = SP.getLinkageName(); if (LinkageName) { - // Skip special LLVM prefix that is used to inform the asm printer to not emit - // usual symbol prefix before the symbol name. This happens for Objective-C - // symbol names and symbol whose name is replaced using GCC's __asm__ attribute. + // Skip special LLVM prefix that is used to inform the asm printer to not + // emit usual symbol prefix before the symbol name. This happens for + // Objective-C symbol names and symbol whose name is replaced using GCC's + // __asm__ attribute. if (LinkageName[0] == 1) LinkageName = &LinkageName[1]; addString(SPDie, dwarf::DW_AT_MIPS_linkage_name, dwarf::DW_FORM_string, @@ -1387,7 +1390,8 @@ I = InlineInfo.find(InlinedSP.getNode()); if (I == InlineInfo.end()) { - InlineInfo[InlinedSP.getNode()].push_back(std::make_pair(StartID, ScopeDIE)); + InlineInfo[InlinedSP.getNode()].push_back(std::make_pair(StartID, + ScopeDIE)); InlinedSPNodes.push_back(InlinedSP.getNode()); } else I->second.push_back(std::make_pair(StartID, ScopeDIE)); @@ -1796,7 +1800,8 @@ } /// findAbstractVariable - Find abstract variable, if any, associated with Var. -DbgVariable *DwarfDebug::findAbstractVariable(DIVariable &Var, unsigned FrameIdx, +DbgVariable *DwarfDebug::findAbstractVariable(DIVariable &Var, + unsigned FrameIdx, DILocation &ScopeLoc) { DbgVariable *AbsDbgVariable = AbstractVariables.lookup(Var.getNode()); @@ -1837,7 +1842,8 @@ DbgVariable *RegVar = new DbgVariable(DV, VP.first); Scope->addVariable(RegVar); - if (DbgVariable *AbsDbgVariable = findAbstractVariable(DV, VP.first, ScopeLoc)) + if (DbgVariable *AbsDbgVariable = findAbstractVariable(DV, VP.first, + ScopeLoc)) RegVar->setAbstractVariable(AbsDbgVariable); } } @@ -2134,7 +2140,8 @@ /// computeSizeAndOffset - Compute the size and offset of a DIE. /// -unsigned DwarfDebug::computeSizeAndOffset(DIE *Die, unsigned Offset, bool Last) { +unsigned +DwarfDebug::computeSizeAndOffset(DIE *Die, unsigned Offset, bool Last) { // Get the children. const std::vector &Children = Die->getChildren(); @@ -2808,7 +2815,8 @@ // for (ValueMap >::iterator // I = InlineInfo.begin(), E = InlineInfo.end(); I != E; ++I) { MDNode *Node = *I; - ValueMap >::iterator II = InlineInfo.find(Node); + ValueMap >::iterator II + = InlineInfo.find(Node); SmallVector &Labels = II->second; DISubprogram SP(Node); const char *LName = SP.getLinkageName(); From stoklund at 2pi.dk Sun Nov 22 13:26:25 2009 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sun, 22 Nov 2009 11:26:25 -0800 Subject: [llvm-commits] [llvm] r89530 - in /llvm/trunk: include/llvm/CodeGen/LiveVariables.h lib/CodeGen/LiveVariables.cpp lib/CodeGen/PHIElimination.cpp lib/CodeGen/PHIElimination.h In-Reply-To: References: <200911210205.nAL25M36031984@zion.cs.uiuc.edu> <58E5E7B6-3416-472E-8C1A-363DDDE5A930@apple.com> <8F6DD22D-65D7-478C-8F62-FAF933194FE1@2pi.dk> Message-ID: On Nov 22, 2009, at 11:06 AM, Anton Korobeynikov wrote: > Hello, Jakob > >> At the machine code level, switches become either branching trees or jumptable branches. > No :) There are 4 different "patterns" used currently for switch lowering: > > 1. Direct comparison (used for small switches) > 2. Jumpt tables (used for dense switches) > 3. Bit-tests (used for switches with not so big range span and going > into few destinations) > 4. Branch trees combining 1 / 2 / 3 Sure, fair enough. My point was that after lowering you have a number of basic blocks terminated by either conditional branches or jump tables. The conditional branches don't have multiple edges to the same successor, and I don't touch jump tables. /jakob -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20091122/14c22926/attachment.bin From eli.friedman at gmail.com Sun Nov 22 13:54:32 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Sun, 22 Nov 2009 14:54:32 -0500 Subject: [llvm-commits] [llvm] r89602 - /llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp In-Reply-To: <200911221616.nAMGGm5b026391@zion.cs.uiuc.edu> References: <200911221616.nAMGGm5b026391@zion.cs.uiuc.edu> Message-ID: On Sun, Nov 22, 2009 at 11:16 AM, Chris Lattner wrote: > --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) > +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Sun Nov 22 10:16:48 2009 > @@ -263,6 +263,7 @@ > ?bool BasicAliasAnalysis::pointsToConstantMemory(const Value *P) { > ? if (const GlobalVariable *GV = > ? ? ? ? dyn_cast(P->getUnderlyingObject())) > + ? ?// FIXME: shouldn't this require GV to be "ODR"? > ? ? return GV->isConstant(); > ? return false; > ?} I don't think it legal for a non-constant to override a constant. (This isn't looking at the initializer.) -Eli From eli.friedman at gmail.com Sun Nov 22 13:57:28 2009 From: eli.friedman at gmail.com (Eli Friedman) Date: Sun, 22 Nov 2009 14:57:28 -0500 Subject: [llvm-commits] [llvm] r89602 - /llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp In-Reply-To: References: <200911221616.nAMGGm5b026391@zion.cs.uiuc.edu> Message-ID: On Sun, Nov 22, 2009 at 2:54 PM, Eli Friedman wrote: > On Sun, Nov 22, 2009 at 11:16 AM, Chris Lattner wrote: >> --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) >> +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Sun Nov 22 10:16:48 2009 >> @@ -263,6 +263,7 @@ >> ?bool BasicAliasAnalysis::pointsToConstantMemory(const Value *P) { >> ? if (const GlobalVariable *GV = >> ? ? ? ? dyn_cast(P->getUnderlyingObject())) >> + ? ?// FIXME: shouldn't this require GV to be "ODR"? >> ? ? return GV->isConstant(); >> ? return false; >> ?} > > I don't think it legal for a non-constant to override a constant. > (This isn't looking at the initializer.) Erm, more precisely, it isn't legal to modify a global that is marked constant in any module. -Eli From grosbach at apple.com Sun Nov 22 14:05:32 2009 From: grosbach at apple.com (Jim Grosbach) Date: Sun, 22 Nov 2009 20:05:32 -0000 Subject: [llvm-commits] [llvm] r89618 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <200911222005.nAMK5Xv9001662@zion.cs.uiuc.edu> Author: grosbach Date: Sun Nov 22 14:05:32 2009 New Revision: 89618 URL: http://llvm.org/viewvc/llvm-project?rev=89618&view=rev Log: Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info can get bogus values. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=89618&r1=89617&r2=89618&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Sun Nov 22 14:05:32 2009 @@ -807,6 +807,7 @@ int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); bool isFixed = MFI->isFixedObjectIndex(FI); + FrameReg = ARM::SP; if (AFI->isGPRCalleeSavedArea1Frame(FI)) Offset -= AFI->getGPRCalleeSavedArea1Offset(); else if (AFI->isGPRCalleeSavedArea2Frame(FI)) @@ -1162,9 +1163,9 @@ assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); } - unsigned FrameReg = ARM::SP; int FrameIndex = MI.getOperand(i).getIndex(); int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj; + unsigned FrameReg; Offset = getFrameIndexReference(MF, FrameIndex, FrameReg); if (FrameReg != ARM::SP) From grosbach at apple.com Sun Nov 22 14:14:00 2009 From: grosbach at apple.com (Jim Grosbach) Date: Sun, 22 Nov 2009 20:14:00 -0000 Subject: [llvm-commits] [llvm] r89620 - in /llvm/trunk: include/llvm/Target/TargetRegisterInfo.h lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <200911222014.nAMKE0MF002018@zion.cs.uiuc.edu> Author: grosbach Date: Sun Nov 22 14:14:00 2009 New Revision: 89620 URL: http://llvm.org/viewvc/llvm-project?rev=89620&view=rev Log: Add getFrameIndexReference() to TargetRegisterInfo, which allows targets to tell debug info which base register to use to reference a frame index on a per-index basis. This is useful, for example, in the presence of dynamic stack realignment when local variables are indexed via the stack pointer and stack-based arguments via the frame pointer. Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=89620&r1=89619&r2=89620&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Sun Nov 22 14:14:00 2009 @@ -698,6 +698,18 @@ /// the stack frame of the specified index. virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const; + /// getFrameIndexReference - This method should return the base register + /// and offset used to reference a frame index location. The offset is + /// returned directly, and the base register is returned via FrameReg. + virtual int getFrameIndexReference(MachineFunction &MF, int FI, + unsigned &FrameReg) const { + // By default, assume all frame indices are referenced via whatever + // getFrameRegister() says. The target can override this if it's doing + // something different. + FrameReg = getFrameRegister(MF); + return getFrameIndexOffset(MF, FI); + } + /// getRARegister - This method should return the register where the return /// address can be found. virtual unsigned getRARegister() const = 0; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=89620&r1=89619&r2=89620&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Sun Nov 22 14:14:00 2009 @@ -1182,8 +1182,9 @@ // Variables for abstract instances of inlined functions don't get a // location. MachineLocation Location; - Location.set(RI->getFrameRegister(*MF), - RI->getFrameIndexOffset(*MF, DV->getFrameIndex())); + unsigned FrameReg; + int Offset = RI->getFrameIndexReference(*MF, DV->getFrameIndex(), FrameReg); + Location.set(FrameReg, Offset); if (VD.hasComplexAddress()) @@ -1465,9 +1466,9 @@ // Add variable address. if (!Scope->isAbstractScope()) { MachineLocation Location; - Location.set(RI->getFrameRegister(*MF), - RI->getFrameIndexOffset(*MF, DV->getFrameIndex())); - + unsigned FrameReg; + int Offset = RI->getFrameIndexReference(*MF, DV->getFrameIndex(), FrameReg); + Location.set(FrameReg, Offset); if (VD.hasComplexAddress()) addComplexAddress(DV, VariableDie, dwarf::DW_AT_location, Location); From nicholas at mxc.ca Sun Nov 22 14:20:02 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 22 Nov 2009 12:20:02 -0800 Subject: [llvm-commits] [llvm] r89602 - /llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp In-Reply-To: References: <200911221616.nAMGGm5b026391@zion.cs.uiuc.edu> Message-ID: <4B099CF2.7020402@mxc.ca> Eli Friedman wrote: > On Sun, Nov 22, 2009 at 2:54 PM, Eli Friedman wrote: >> On Sun, Nov 22, 2009 at 11:16 AM, Chris Lattner wrote: >>> --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) >>> +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Sun Nov 22 10:16:48 2009 >>> @@ -263,6 +263,7 @@ >>> bool BasicAliasAnalysis::pointsToConstantMemory(const Value *P) { >>> if (const GlobalVariable *GV = >>> dyn_cast(P->getUnderlyingObject())) >>> + // FIXME: shouldn't this require GV to be "ODR"? >>> return GV->isConstant(); >>> return false; >>> } >> >> I don't think it legal for a non-constant to override a constant. >> (This isn't looking at the initializer.) > > Erm, more precisely, it isn't legal to modify a global that is marked > constant in any module. So we could optimize GlobalVariables with constant initializers into having _odr linkage (where applicable of course)? Nick From nicholas at mxc.ca Sun Nov 22 15:31:40 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 22 Nov 2009 13:31:40 -0800 Subject: [llvm-commits] [llvm] r88910 - /llvm/trunk/lib/VMCore/Core.cpp In-Reply-To: <200911161315.nAGDFTMi017583@zion.cs.uiuc.edu> References: <200911161315.nAGDFTMi017583@zion.cs.uiuc.edu> Message-ID: <4B09ADBC.3010807@mxc.ca> Duncan Sands wrote: > Author: baldrick > Date: Mon Nov 16 07:15:28 2009 > New Revision: 88910 > > URL: http://llvm.org/viewvc/llvm-project?rev=88910&view=rev > Log: > BuildIntCast takes an additional parameter, isSigned. That's not right. include/llvm-c/Core.h says: LLVMValueRef LLVMBuildIntCast(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name); Also, this is the C API, so you can't fix this by changing the signature on the C function, if it's ever been through a release. This is breaking make check with the Ocaml bindings: FAIL: /home/nicholas/llvm-commit/test/Bindings/Ocaml/analysis.ml Failed with exit(2) at line 1 while running: /usr/bin/ocamlopt -cc "g++ -Wall -D_FILE_OFFSET_BITS=64 -D_REENTRANT" -I /home/nicholas/llvm-commit/Debug/lib/ocaml -warn-error A llvm.cmxa llvm_analysis.cmxa /home/nicholas/llvm-commit/test/Bindings/Ocaml/analysis.ml -o analysis.ml.tmp /usr/bin/ld: /home/nicholas/llvm-commit/Debug/lib/ocaml/libllvm.a(llvm_ocaml.o): in function llvm_build_intcast:llvm_ocaml.c:1388: error: undefined reference to 'LLVMBuildIntCast' collect2: ld returned 1 exit status File "caml_startup", line 1, characters 0-1: Error: Error during linking FAIL: /home/nicholas/llvm-commit/test/Bindings/Ocaml/bitreader.ml Failed with exit(2) at line 1 while running: /usr/bin/ocamlopt -cc "g++ -Wall -D_FILE_OFFSET_BITS=64 -D_REENTRANT" -I /home/nicholas/llvm-commit/Debug/lib/ocaml -warn-error A llvm.cmxa llvm_bitreader.cmxa llvm_bitwriter.cmxa /home/nicholas/llvm-commit/test/Bindings/Ocaml/bitreader.ml -o bitreader.ml.tmp /usr/bin/ld: /home/nicholas/llvm-commit/Debug/lib/ocaml/libllvm.a(llvm_ocaml.o): in function llvm_build_intcast:llvm_ocaml.c:1388: error: undefined reference to 'LLVMBuildIntCast' collect2: ld returned 1 exit status File "caml_startup", line 1, characters 0-1: Error: Error during linking FAIL: /home/nicholas/llvm-commit/test/Bindings/Ocaml/bitwriter.ml Failed with exit(2) at line 1 while running: /usr/bin/ocamlopt -cc "g++ -Wall -D_FILE_OFFSET_BITS=64 -D_REENTRANT" -I /home/nicholas/llvm-commit/Debug/lib/ocaml -warn-error A llvm.cmxa llvm_bitwriter.cmxa /home/nicholas/llvm-commit/test/Bindings/Ocaml/bitwriter.ml -o bitwriter.ml.tmp /usr/bin/ld: /home/nicholas/llvm-commit/Debug/lib/ocaml/libllvm.a(llvm_ocaml.o): in function llvm_build_intcast:llvm_ocaml.c:1388: error: undefined reference to 'LLVMBuildIntCast' collect2: ld returned 1 exit status File "caml_startup", line 1, characters 0-1: Error: Error during linking FAIL: /home/nicholas/llvm-commit/test/Bindings/Ocaml/executionengine.ml Failed with exit(2) at line 1 while running: /usr/bin/ocamlopt -cc "g++ -Wall -D_FILE_OFFSET_BITS=64 -D_REENTRANT" -I /home/nicholas/llvm-commit/Debug/lib/ocaml -warn-error A llvm.cmxa llvm_target.cmxa llvm_executionengine.cmxa /home/nicholas/llvm-commit/test/Bindings/Ocaml/executionengine.ml -o executionengine.ml.tmp /usr/bin/ld: /home/nicholas/llvm-commit/Debug/lib/ocaml/libllvm.a(llvm_ocaml.o): in function llvm_build_intcast:llvm_ocaml.c:1388: error: undefined reference to 'LLVMBuildIntCast' collect2: ld returned 1 exit status File "caml_startup", line 1, characters 0-1: Error: Error during linking FAIL: /home/nicholas/llvm-commit/test/Bindings/Ocaml/scalar_opts.ml Failed with exit(2) at line 1 while running: /usr/bin/ocamlopt -cc "g++ -Wall -D_FILE_OFFSET_BITS=64 -D_REENTRANT" -I /home/nicholas/llvm-commit/Debug/lib/ocaml -warn-error A llvm.cmxa llvm_scalar_opts.cmxa llvm_target.cmxa /home/nicholas/llvm-commit/test/Bindings/Ocaml/scalar_opts.ml -o scalar_opts.ml.tmp /usr/bin/ld: /home/nicholas/llvm-commit/Debug/lib/ocaml/libllvm.a(llvm_ocaml.o): in function llvm_build_intcast:llvm_ocaml.c:1388: error: undefined reference to 'LLVMBuildIntCast' collect2: ld returned 1 exit status File "caml_startup", line 1, characters 0-1: Error: Error during linking FAIL: /home/nicholas/llvm-commit/test/Bindings/Ocaml/target.ml Failed with exit(2) at line 1 while running: /usr/bin/ocamlopt -cc "g++ -Wall -D_FILE_OFFSET_BITS=64 -D_REENTRANT" -I /home/nicholas/llvm-commit/Debug/lib/ocaml -warn-error A llvm.cmxa llvm_target.cmxa /home/nicholas/llvm-commit/test/Bindings/Ocaml/target.ml -o target.ml.tmp /usr/bin/ld: /home/nicholas/llvm-commit/Debug/lib/ocaml/libllvm.a(llvm_ocaml.o): in function llvm_build_intcast:llvm_ocaml.c:1388: error: undefined reference to 'LLVMBuildIntCast' collect2: ld returned 1 exit status File "caml_startup", line 1, characters 0-1: Error: Error during linking FAIL: /home/nicholas/llvm-commit/test/Bindings/Ocaml/vmcore.ml Failed with exit(2) at line 1 while running: /usr/bin/ocamlopt -cc "g++ -Wall -D_FILE_OFFSET_BITS=64 -D_REENTRANT" -I /home/nicholas/llvm-commit/Debug/lib/ocaml -warn-error A llvm.cmxa llvm_analysis.cmxa llvm_bitwriter.cmxa /home/nicholas/llvm-commit/test/Bindings/Ocaml/vmcore.ml -o vmcore.ml.tmp /usr/bin/ld: /home/nicholas/llvm-commit/Debug/lib/ocaml/libllvm.a(llvm_ocaml.o): in function llvm_build_intcast:llvm_ocaml.c:1388: error: undefined reference to 'LLVMBuildIntCast' collect2: ld returned 1 exit status File "caml_startup", line 1, characters 0-1: Error: Error during linking Nick > Modified: > llvm/trunk/lib/VMCore/Core.cpp > > Modified: llvm/trunk/lib/VMCore/Core.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=88910&r1=88909&r2=88910&view=diff > > ============================================================================== > --- llvm/trunk/lib/VMCore/Core.cpp (original) > +++ llvm/trunk/lib/VMCore/Core.cpp Mon Nov 16 07:15:28 2009 > @@ -1860,8 +1860,9 @@ > } > > LLVMValueRef LLVMBuildIntCast(LLVMBuilderRef B, LLVMValueRef Val, > - LLVMTypeRef DestTy, const char *Name) { > - return wrap(unwrap(B)->CreateIntCast(unwrap(Val), unwrap(DestTy), Name)); > + LLVMTypeRef DestTy, int isSigned, > + const char *Name) { > + return wrap(unwrap(B)->CreateIntCast(unwrap(Val), unwrap(DestTy), isSigned, Name)); > } > > LLVMValueRef LLVMBuildFPCast(LLVMBuilderRef B, LLVMValueRef Val, > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From daniel at zuster.org Sun Nov 22 16:07:51 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 22:07:51 -0000 Subject: [llvm-commits] [llvm] r89626 - in /llvm/trunk: docs/CommandGuide/FileCheck.pod utils/FileCheck/FileCheck.cpp Message-ID: <200911222207.nAMM7pis006331@zion.cs.uiuc.edu> Author: ddunbar Date: Sun Nov 22 16:07:50 2009 New Revision: 89626 URL: http://llvm.org/viewvc/llvm-project?rev=89626&view=rev Log: Allow '_' in FileCheck variable names, it is nice to have at least one separate character. - Chris, OK? Modified: llvm/trunk/docs/CommandGuide/FileCheck.pod llvm/trunk/utils/FileCheck/FileCheck.cpp Modified: llvm/trunk/docs/CommandGuide/FileCheck.pod URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CommandGuide/FileCheck.pod?rev=89626&r1=89625&r2=89626&view=diff ============================================================================== --- llvm/trunk/docs/CommandGuide/FileCheck.pod (original) +++ llvm/trunk/docs/CommandGuide/FileCheck.pod Sun Nov 22 16:07:50 2009 @@ -224,7 +224,7 @@ the variables "REGISTER". The second line verifies that whatever is in REGISTER occurs later in the file after an "andw". FileCheck variable references are always contained in [[ ]] pairs, are named, and their names can be -formed with the regex "[a-zA-Z][a-zA-Z0-9]*". If a colon follows the +formed with the regex "[a-zA-Z_][a-zA-Z0-9_]*". If a colon follows the name, then it is a definition of the variable, if not, it is a use. FileCheck variables can be defined multiple times, and uses always get the Modified: llvm/trunk/utils/FileCheck/FileCheck.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/FileCheck/FileCheck.cpp?rev=89626&r1=89625&r2=89626&view=diff ============================================================================== --- llvm/trunk/utils/FileCheck/FileCheck.cpp (original) +++ llvm/trunk/utils/FileCheck/FileCheck.cpp Sun Nov 22 16:07:50 2009 @@ -140,7 +140,7 @@ // Named RegEx matches. These are of two forms: [[foo:.*]] which matches .* // (or some other regex) and assigns it to the FileCheck variable 'foo'. The // second form is [[foo]] which is a reference to foo. The variable name - // itself must be of the form "[a-zA-Z][0-9a-zA-Z]*", otherwise we reject + // itself must be of the form "[a-zA-Z_][0-9a-zA-Z_]*", otherwise we reject // it. This is to catch some common errors. if (PatternStr.size() >= 2 && PatternStr[0] == '[' && PatternStr[1] == '[') { @@ -167,7 +167,8 @@ // Verify that the name is well formed. for (unsigned i = 0, e = Name.size(); i != e; ++i) - if ((Name[i] < 'a' || Name[i] > 'z') && + if (Name[i] != '_' && + (Name[i] < 'a' || Name[i] > 'z') && (Name[i] < 'A' || Name[i] > 'Z') && (Name[i] < '0' || Name[i] > '9')) { SM.PrintMessage(SMLoc::getFromPointer(Name.data()+i), From daniel at zuster.org Sun Nov 22 16:08:00 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 22:08:00 -0000 Subject: [llvm-commits] [llvm] r89627 - in /llvm/trunk: include/llvm/Support/SourceMgr.h lib/Support/SourceMgr.cpp Message-ID: <200911222208.nAMM80WV006355@zion.cs.uiuc.edu> Author: ddunbar Date: Sun Nov 22 16:08:00 2009 New Revision: 89627 URL: http://llvm.org/viewvc/llvm-project?rev=89627&view=rev Log: SourceMgr: Add ShowLine argument to PrintMessage, to allow suppressing the source line output. Modified: llvm/trunk/include/llvm/Support/SourceMgr.h llvm/trunk/lib/Support/SourceMgr.cpp Modified: llvm/trunk/include/llvm/Support/SourceMgr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/SourceMgr.h?rev=89627&r1=89626&r2=89627&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/SourceMgr.h (original) +++ llvm/trunk/include/llvm/Support/SourceMgr.h Sun Nov 22 16:08:00 2009 @@ -120,7 +120,9 @@ /// /// @param Type - If non-null, the kind of message (e.g., "error") which is /// prefixed to the message. - void PrintMessage(SMLoc Loc, const std::string &Msg, const char *Type) const; + /// @param ShowLine - Should the diagnostic show the source line. + void PrintMessage(SMLoc Loc, const std::string &Msg, const char *Type, + bool ShowLine = true) const; /// GetMessage - Return an SMDiagnostic at the specified location with the @@ -128,8 +130,10 @@ /// /// @param Type - If non-null, the kind of message (e.g., "error") which is /// prefixed to the message. + /// @param ShowLine - Should the diagnostic show the source line. SMDiagnostic GetMessage(SMLoc Loc, - const std::string &Msg, const char *Type) const; + const std::string &Msg, const char *Type, + bool ShowLine = true) const; private: @@ -143,12 +147,15 @@ std::string Filename; int LineNo, ColumnNo; std::string Message, LineContents; + unsigned ShowLine : 1; + public: SMDiagnostic() : LineNo(0), ColumnNo(0) {} SMDiagnostic(const std::string &FN, int Line, int Col, - const std::string &Msg, const std::string &LineStr) + const std::string &Msg, const std::string &LineStr, + bool showline = true) : Filename(FN), LineNo(Line), ColumnNo(Col), Message(Msg), - LineContents(LineStr) {} + LineContents(LineStr), ShowLine(showline) {} void Print(const char *ProgName, raw_ostream &S); }; Modified: llvm/trunk/lib/Support/SourceMgr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SourceMgr.cpp?rev=89627&r1=89626&r2=89627&view=diff ============================================================================== --- llvm/trunk/lib/Support/SourceMgr.cpp (original) +++ llvm/trunk/lib/Support/SourceMgr.cpp Sun Nov 22 16:08:00 2009 @@ -136,7 +136,7 @@ /// @param Type - If non-null, the kind of message (e.g., "error") which is /// prefixed to the message. SMDiagnostic SourceMgr::GetMessage(SMLoc Loc, const std::string &Msg, - const char *Type) const { + const char *Type, bool ShowLine) const { // First thing to do: find the current buffer containing the specified // location. @@ -144,18 +144,22 @@ assert(CurBuf != -1 && "Invalid or unspecified location!"); MemoryBuffer *CurMB = getBufferInfo(CurBuf).Buffer; - - + // Scan backward to find the start of the line. const char *LineStart = Loc.getPointer(); - while (LineStart != CurMB->getBufferStart() && + while (LineStart != CurMB->getBufferStart() && LineStart[-1] != '\n' && LineStart[-1] != '\r') --LineStart; - // Get the end of the line. - const char *LineEnd = Loc.getPointer(); - while (LineEnd != CurMB->getBufferEnd() && - LineEnd[0] != '\n' && LineEnd[0] != '\r') - ++LineEnd; + + std::string LineStr; + if (ShowLine) { + // Get the end of the line. + const char *LineEnd = Loc.getPointer(); + while (LineEnd != CurMB->getBufferEnd() && + LineEnd[0] != '\n' && LineEnd[0] != '\r') + ++LineEnd; + LineStr = std::string(LineStart, LineEnd); + } std::string PrintedMsg; if (Type) { @@ -163,22 +167,21 @@ PrintedMsg += ": "; } PrintedMsg += Msg; - - // Print out the line. + return SMDiagnostic(CurMB->getBufferIdentifier(), FindLineNumber(Loc, CurBuf), Loc.getPointer()-LineStart, PrintedMsg, - std::string(LineStart, LineEnd)); + LineStr, ShowLine); } void SourceMgr::PrintMessage(SMLoc Loc, const std::string &Msg, - const char *Type) const { + const char *Type, bool ShowLine) const { raw_ostream &OS = errs(); int CurBuf = FindBufferContainingLoc(Loc); assert(CurBuf != -1 && "Invalid or unspecified location!"); PrintIncludeStack(getBufferInfo(CurBuf).IncludeLoc, OS); - GetMessage(Loc, Msg, Type).Print(0, OS); + GetMessage(Loc, Msg, Type, ShowLine).Print(0, OS); } //===----------------------------------------------------------------------===// @@ -201,8 +204,8 @@ } S << ": " << Message << '\n'; - - if (LineNo != -1 && ColumnNo != -1) { + + if (LineNo != -1 && ColumnNo != -1 && ShowLine) { S << LineContents << '\n'; // Print out spaces/tabs before the caret. From daniel at zuster.org Sun Nov 22 16:08:06 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 22:08:06 -0000 Subject: [llvm-commits] [llvm] r89628 - /llvm/trunk/utils/FileCheck/FileCheck.cpp Message-ID: <200911222208.nAMM86DG006372@zion.cs.uiuc.edu> Author: ddunbar Date: Sun Nov 22 16:08:06 2009 New Revision: 89628 URL: http://llvm.org/viewvc/llvm-project?rev=89628&view=rev Log: FileCheck: When a string using variable references fails to match, print additional information about the current definitions of the variables used in the string. Modified: llvm/trunk/utils/FileCheck/FileCheck.cpp Modified: llvm/trunk/utils/FileCheck/FileCheck.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/FileCheck/FileCheck.cpp?rev=89628&r1=89627&r2=89628&view=diff ============================================================================== --- llvm/trunk/utils/FileCheck/FileCheck.cpp (original) +++ llvm/trunk/utils/FileCheck/FileCheck.cpp Sun Nov 22 16:08:06 2009 @@ -23,6 +23,7 @@ #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" #include "llvm/System/Signals.h" +#include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringMap.h" #include using namespace llvm; @@ -82,7 +83,12 @@ /// variables and is updated if this match defines new values. size_t Match(StringRef Buffer, size_t &MatchLen, StringMap &VariableTable) const; - + + /// PrintFailureInfo - Print additional information about a failure to match + /// involving this pattern. + void PrintFailureInfo(const SourceMgr &SM, StringRef Buffer, + const StringMap &VariableTable) const; + private: static void AddFixedStringToRegEx(StringRef FixedStr, std::string &TheStr); bool AddRegExToRegEx(StringRef RegExStr, unsigned &CurParen, SourceMgr &SM); @@ -276,9 +282,15 @@ unsigned InsertOffset = 0; for (unsigned i = 0, e = VariableUses.size(); i != e; ++i) { + StringMap::iterator it = + VariableTable.find(VariableUses[i].first); + // If the variable is undefined, return an error. + if (it == VariableTable.end()) + return StringRef::npos; + // Look up the value and escape it so that we can plop it into the regex. std::string Value; - AddFixedStringToRegEx(VariableTable[VariableUses[i].first], Value); + AddFixedStringToRegEx(it->second, Value); // Plop it into the regex at the adjusted offset. TmpStr.insert(TmpStr.begin()+VariableUses[i].second+InsertOffset, @@ -310,6 +322,36 @@ return FullMatch.data()-Buffer.data(); } +void Pattern::PrintFailureInfo(const SourceMgr &SM, StringRef Buffer, + const StringMap &VariableTable) const{ + // If this is a fixed string, do nothing. + if (!FixedStr.empty()) + return; + + // If this was a regular expression using variables, print the current + // variable values. + if (!VariableUses.empty()) { + for (unsigned i = 0, e = VariableUses.size(); i != e; ++i) { + StringRef Var = VariableUses[i].first; + StringMap::const_iterator it = VariableTable.find(Var); + SmallString<256> Msg; + raw_svector_ostream OS(Msg); + + // Check for undefined variable references. + if (it == VariableTable.end()) { + OS << "uses undefined variable \""; + OS.write_escaped(Var) << "\"";; + } else { + OS << "with variable \""; + OS.write_escaped(Var) << "\" equal to \""; + OS.write_escaped(it->second) << "\""; + } + + SM.PrintMessage(SMLoc::getFromPointer(Buffer.data()), OS.str(), "note", + /*ShowLine=*/false); + } + } +} //===----------------------------------------------------------------------===// // Check Strings. @@ -478,7 +520,8 @@ } static void PrintCheckFailed(const SourceMgr &SM, const CheckString &CheckStr, - StringRef Buffer) { + StringRef Buffer, + StringMap &VariableTable) { // Otherwise, we have an error, emit an error message. SM.PrintMessage(CheckStr.Loc, "expected string not found in input", "error"); @@ -489,6 +532,9 @@ SM.PrintMessage(SMLoc::getFromPointer(Buffer.data()), "scanning from here", "note"); + + // Allow the pattern to print additional information if desired. + CheckStr.Pat.PrintFailureInfo(SM, Buffer, VariableTable); } /// CountNumNewlinesBetween - Count the number of newlines in the specified @@ -559,7 +605,7 @@ // If we didn't find a match, reject the input. if (Buffer.empty()) { - PrintCheckFailed(SM, CheckStr, SearchFrom); + PrintCheckFailed(SM, CheckStr, SearchFrom, VariableTable); return 1; } From daniel at zuster.org Sun Nov 22 16:09:26 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 14:09:26 -0800 Subject: [llvm-commits] [llvm] r89211 - /llvm/trunk/CMakeLists.txt In-Reply-To: <4B098818.4000506@mxc.ca> References: <200911181742.nAIHgMXe005175@zion.cs.uiuc.edu> <87lji25i81.fsf@telefonica.net> <6a8523d60911221021t75d68290j30060188af1734ca@mail.gmail.com> <4B098818.4000506@mxc.ca> Message-ID: <6a8523d60911221409o474ae2atb51155eab3f56890@mail.gmail.com> On Sun, Nov 22, 2009 at 10:51 AM, Nick Lewycky wrote: > Daniel Dunbar wrote: >> >> On Thu, Nov 19, 2009 at 1:15 PM, ?scar Fuentes ?wrote: >>> >>> Hello Daniel. >>> >>> Daniel Dunbar ?writes: >>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=89211&view=rev >>>> Log: >>>> Turn LLVM_BUILD_EXAMPLES off by default in CMake builds, to match >>>> Makefiles& >>>> Clang. >>> >>> What's the rationale for this? >>> >>> (And wouldn't it warrant the corresponding update of docs/CMake.html, >>> where default values for variables are listed?) >> >> The rationale for changing the default (for cmake and make, I assume >> we agree they should have the same default) is that most people >> building LLVM don't care about the examples (because they are >> developers), and this greatly increases cycle times because of the >> sheer number of link steps it adds. Having examples be "optional" >> builds for people exploring LLVM seems reasonable to me, the only >> value I see in building them regularly is to prevent them from being >> out-dated, but I will change (one, fast) buildbot to maintain that. >> >> I will update the doc. > > The rationale for copying each Kaleidoscope chapter into the examples/ > directory was to make sure that our examples on the website don't get out of > date when someone changes the API. I agree this is good. > This just means that people will run make and make check, commit, and then > discover that their change somehow broke the buildbots. It'd be nice to > notice and resolve the breakage before committing. I explained my view on this with my reply to Duncan, and there is no counterargument here. I can quite easily argue that the increased cycle time of the buildbots (and the corresponding improvement in blamelist accuracy) as a group more than makes up for the rare times when someone breaks an example. - Daniel From daniel at zuster.org Sun Nov 22 16:11:29 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 14:11:29 -0800 Subject: [llvm-commits] [llvm] r89211 - /llvm/trunk/CMakeLists.txt In-Reply-To: <87pr7a4c4m.fsf@telefonica.net> References: <200911181742.nAIHgMXe005175@zion.cs.uiuc.edu> <87lji25i81.fsf@telefonica.net> <6a8523d60911221021t75d68290j30060188af1734ca@mail.gmail.com> <87pr7a4c4m.fsf@telefonica.net> Message-ID: <6a8523d60911221411n6b09928dy8609cfa8624a1b80@mail.gmail.com> On Sun, Nov 22, 2009 at 11:01 AM, ?scar Fuentes wrote: > Daniel Dunbar writes: > >>>> URL: http://llvm.org/viewvc/llvm-project?rev=89211&view=rev >>>> Log: >>>> Turn LLVM_BUILD_EXAMPLES off by default in CMake builds, to match Makefiles & >>>> Clang. >>> >>> What's the rationale for this? >>> >>> (And wouldn't it warrant the corresponding update of docs/CMake.html, >>> where default values for variables are listed?) >> >> The rationale for changing the default (for cmake and make, I assume >> we agree they should have the same default) is that most people >> building LLVM don't care about the examples (because they are >> developers), and this greatly increases cycle times because of the >> sheer number of link steps it adds. Having examples be "optional" >> builds for people exploring LLVM seems reasonable to me, the only >> value I see in building them regularly is to prevent them from being >> out-dated, but I will change (one, fast) buildbot to maintain that. > > I do not agree with this policy. IMHO making things as straightforward > as possible for people exploring LLVM is more important than removing > little annoyances for developers (and having to write > -DLLVM_BUILD_EXAMPLES=OFF when you configure a fresh checkout is a > little annoyance). But this is just IMHO. > > One compromise that we can easily implement (at least on the cmake > build) is to default to OFF when building from a svn checkout and ON > otherwise. What do you think? I would rather change it in releases, since we already make this distinction in version tags. And I'm not actually yet convinced it is even the right default. Imagine we have tons and tons of examples, do I as a newbie want them all to be built? Probably not, I'd rather get the build done, and go type make in examples/TheOneThingIAmInterested in. - Daniel From nicholas at mxc.ca Sun Nov 22 16:27:54 2009 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 22 Nov 2009 14:27:54 -0800 Subject: [llvm-commits] [llvm] r89211 - /llvm/trunk/CMakeLists.txt In-Reply-To: <6a8523d60911221409o474ae2atb51155eab3f56890@mail.gmail.com> References: <200911181742.nAIHgMXe005175@zion.cs.uiuc.edu> <87lji25i81.fsf@telefonica.net> <6a8523d60911221021t75d68290j30060188af1734ca@mail.gmail.com> <4B098818.4000506@mxc.ca> <6a8523d60911221409o474ae2atb51155eab3f56890@mail.gmail.com> Message-ID: <4B09BAEA.2030207@mxc.ca> Daniel Dunbar wrote: > On Sun, Nov 22, 2009 at 10:51 AM, Nick Lewycky wrote: >> Daniel Dunbar wrote: >>> >>> On Thu, Nov 19, 2009 at 1:15 PM, ?scar Fuentes wrote: >>>> >>>> Hello Daniel. >>>> >>>> Daniel Dunbar writes: >>>> >>>>> URL: http://llvm.org/viewvc/llvm-project?rev=89211&view=rev >>>>> Log: >>>>> Turn LLVM_BUILD_EXAMPLES off by default in CMake builds, to match >>>>> Makefiles& >>>>> Clang. >>>> >>>> What's the rationale for this? >>>> >>>> (And wouldn't it warrant the corresponding update of docs/CMake.html, >>>> where default values for variables are listed?) >>> >>> The rationale for changing the default (for cmake and make, I assume >>> we agree they should have the same default) is that most people >>> building LLVM don't care about the examples (because they are >>> developers), and this greatly increases cycle times because of the >>> sheer number of link steps it adds. Having examples be "optional" >>> builds for people exploring LLVM seems reasonable to me, the only >>> value I see in building them regularly is to prevent them from being >>> out-dated, but I will change (one, fast) buildbot to maintain that. >>> >>> I will update the doc. >> >> The rationale for copying each Kaleidoscope chapter into the examples/ >> directory was to make sure that our examples on the website don't get out of >> date when someone changes the API. > > I agree this is good. > >> This just means that people will run make and make check, commit, and then >> discover that their change somehow broke the buildbots. It'd be nice to >> notice and resolve the breakage before committing. > > I explained my view on this with my reply to Duncan, and there is no > counterargument here. I can quite easily argue that the increased > cycle time of the buildbots (and the corresponding improvement in > blamelist accuracy) as a group more than makes up for the rare times > when someone breaks an example. I know. I'm not convinced that it is so rare, else we wouldn't have needed to add it in the first place. I realize that at least getting it caught by the buildbots is better than the situation from before they were added (nobody noticing until a new users complains on our IRC channel) but I remain an unfan of this change -- just not strongly enough to strongly enough to keep pushing back on it. Whoever cares the most wins, I guess :) Hopefully it won't lead to too many reversions of otherwise good changes. Nick From daniel at zuster.org Sun Nov 22 16:59:26 2009 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 22 Nov 2009 22:59:26 -0000 Subject: [llvm-commits] [llvm] r89631 - /llvm/trunk/utils/FileCheck/FileCheck.cpp Message-ID: <200911222259.nAMMxQMf008055@zion.cs.uiuc.edu> Author: ddunbar Date: Sun Nov 22 16:59:26 2009 New Revision: 89631 URL: http://llvm.org/viewvc/llvm-project?rev=89631&view=rev Log: FileCheck, PR5239: Try to find the intended match on failures, but looking for a good nearby fuzzy match. Frequently the input is nearly correct, and just showing the user the a nearby sensible match is enough to diagnose the problem. - The "fuzzyness" is pretty simple and arbitrary, but worked on my three test cases. If you encounter problems, or places you think FileCheck should have guessed but didn't, please add test cases to PR5239. For example, previously FileCheck would report this: -- t.cpp:21:55: error: expected string not found in input // CHECK: define void @_Z2f25f2_s1([[i64_i64_ty]] %a0) ^ :19:30: note: scanning from here define void @_Z2f15f1_s1(%1) nounwind { ^ :19:30: note: with variable "i64_i64_ty" equal to "%0" -- and now it also reports this: -- :27:1: note: possible intended match here define void @_Z2f25f2_s1(%0) nounwind { ^ -- which makes it clear that the CHECK just has an extra ' %a0' in it, without having to check the input. Modified: llvm/trunk/utils/FileCheck/FileCheck.cpp Modified: llvm/trunk/utils/FileCheck/FileCheck.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/FileCheck/FileCheck.cpp?rev=89631&r1=89630&r2=89631&view=diff ============================================================================== --- llvm/trunk/utils/FileCheck/FileCheck.cpp (original) +++ llvm/trunk/utils/FileCheck/FileCheck.cpp Sun Nov 22 16:59:26 2009 @@ -92,6 +92,12 @@ private: static void AddFixedStringToRegEx(StringRef FixedStr, std::string &TheStr); bool AddRegExToRegEx(StringRef RegExStr, unsigned &CurParen, SourceMgr &SM); + + /// ComputeMatchDistance - Compute an arbitrary estimate for the quality of + /// matching this pattern at the start of \arg Buffer; a distance of zero + /// should correspond to a perfect match. + unsigned ComputeMatchDistance(StringRef Buffer, + const StringMap &VariableTable) const; }; @@ -322,12 +328,28 @@ return FullMatch.data()-Buffer.data(); } +unsigned Pattern::ComputeMatchDistance(StringRef Buffer, + const StringMap &VariableTable) const { + // Just compute the number of matching characters. For regular expressions, we + // just compare against the regex itself and hope for the best. + // + // FIXME: One easy improvement here is have the regex lib generate a single + // example regular expression which matches, and use that as the example + // string. + StringRef ExampleString(FixedStr); + if (ExampleString.empty()) + ExampleString = RegExStr; + + unsigned Distance = 0; + for (unsigned i = 0, e = ExampleString.size(); i != e; ++i) + if (Buffer.substr(i, 1) != ExampleString.substr(i, 1)) + ++Distance; + + return Distance; +} + void Pattern::PrintFailureInfo(const SourceMgr &SM, StringRef Buffer, const StringMap &VariableTable) const{ - // If this is a fixed string, do nothing. - if (!FixedStr.empty()) - return; - // If this was a regular expression using variables, print the current // variable values. if (!VariableUses.empty()) { @@ -351,6 +373,40 @@ /*ShowLine=*/false); } } + + // Attempt to find the closest/best fuzzy match. Usually an error happens + // because some string in the output didn't exactly match. In these cases, we + // would like to show the user a best guess at what "should have" matched, to + // save them having to actually check the input manually. + size_t NumLinesForward = 0; + size_t Best = StringRef::npos; + double BestQuality = 0; + + // Use an arbitrary 4k limit on how far we will search. + for (size_t i = 0, e = std::min(4096, int(Buffer.size())); i != e; ++i) { + if (Buffer[i] == '\n') + ++NumLinesForward; + + // Compute the "quality" of this match as an arbitrary combination of the + // match distance and the number of lines skipped to get to this match. + unsigned Distance = ComputeMatchDistance(Buffer.substr(i), VariableTable); + double Quality = Distance + (NumLinesForward / 100.); + + if (Quality < BestQuality || Best == StringRef::npos) { + Best = i; + BestQuality = Quality; + } + } + + if (BestQuality < 50) { + // Print the "possible intended match here" line if we found something + // reasonable. + SM.PrintMessage(SMLoc::getFromPointer(Buffer.data() + Best), + "possible intended match here", "note"); + + // FIXME: If we wanted to be really friendly we would show why the match + // failed, as it can be hard to spot simple one character differences. + } } //===----------------------------------------------------------------------===// From ofv at wanadoo.es Sun Nov 22 17:25:36 2009 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Mon, 23 Nov 2009 00:25:36 +0100 Subject: [llvm-commits] [llvm] r89211 - /llvm/trunk/CMakeLists.txt References: <200911181742.nAIHgMXe005175@zion.cs.uiuc.edu> <87lji25i81.fsf@telefonica.net> <6a8523d60911221021t75d68290j30060188af1734ca@mail.gmail.com> <87pr7a4c4m.fsf@telefonica.net> <6a8523d60911221411n6b09928dy8609cfa8624a1b80@mail.gmail.com> Message-ID: <878wdy3zwv.fsf@telefonica.net> Daniel Dunbar writes: >> One compromise that we can easily implement (at least on the cmake >> build) is to default to OFF when building from a svn checkout and ON >> otherwise. What do you think? > > I would rather change it in releases, since we already make this > distinction in version tags. And I'm not actually yet convinced it is > even the right default. Imagine we have tons and tons of examples, do > I as a newbie want them all to be built? Probably not, I'd rather get > the build done, and go type make in examples/TheOneThingIAmInterested > in. Right now, on the cmake build, this is not possible, as LLVM_BUILD_EXAMPLES=OFF turns off the generation of targets (i.e. makefiles) for that part of the source tree. The fix is easy, though, and consists on adding EXCLUDE_FROM_ALL to the add_executable that is invoked by add_llvm_executable when it is called from add_llvm_example. Hmmm, I think I'll implement that for add_llvm_tool too. Usually I'm just interested on the libraries and set LLVM_BUILD_TOOLS to OFF but sometimes I need some specific tool (opt and llvm-as, typically) and this would save a reconfigure. -- ?scar From ofv at wanadoo.es Sun Nov 22 18:21:44 2009 From: ofv at wanadoo.es (Oscar Fuentes) Date: Mon, 23 Nov 2009 00:21:44 -0000 Subject: [llvm-commits] [llvm] r89635 - in /llvm/trunk: CMakeLists.txt cmake/modules/AddLLVM.cmake docs/CMake.html Message-ID: <200911230021.nAN0LisT011026@zion.cs.uiuc.edu> Author: ofv Date: Sun Nov 22 18:21:43 2009 New Revision: 89635 URL: http://llvm.org/viewvc/llvm-project?rev=89635&view=rev Log: CMake: generate targets for tools and examples even when LLVM_BUILD_TOOLS or LLVM_BUILD_EXAMPLES are OFF. Modified: llvm/trunk/CMakeLists.txt llvm/trunk/cmake/modules/AddLLVM.cmake llvm/trunk/docs/CMake.html Modified: llvm/trunk/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=89635&r1=89634&r2=89635&view=diff ============================================================================== --- llvm/trunk/CMakeLists.txt (original) +++ llvm/trunk/CMakeLists.txt Sun Nov 22 18:21:43 2009 @@ -319,14 +319,10 @@ add_subdirectory(projects) option(LLVM_BUILD_TOOLS "Build LLVM tool programs." ON) -if(LLVM_BUILD_TOOLS) - add_subdirectory(tools) -endif() +add_subdirectory(tools) option(LLVM_BUILD_EXAMPLES "Build LLVM example programs." OFF) -if(LLVM_BUILD_EXAMPLES) - add_subdirectory(examples) -endif () +add_subdirectory(examples) install(DIRECTORY include/ DESTINATION include Modified: llvm/trunk/cmake/modules/AddLLVM.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=89635&r1=89634&r2=89635&view=diff ============================================================================== --- llvm/trunk/cmake/modules/AddLLVM.cmake (original) +++ llvm/trunk/cmake/modules/AddLLVM.cmake Sun Nov 22 18:21:43 2009 @@ -46,7 +46,12 @@ macro(add_llvm_executable name) llvm_process_sources( ALL_FILES ${ARGN} ) - add_executable(${name} ${ALL_FILES}) + if( EXCLUDE_FROM_ALL ) + add_executable(${name} EXCLUDE_FROM_ALL ${ALL_FILES}) + else() + add_executable(${name} ${ALL_FILES}) + endif() + set(EXCLUDE_FROM_ALL OFF) if( LLVM_USED_LIBS ) foreach(lib ${LLVM_USED_LIBS}) target_link_libraries( ${name} ${lib} ) @@ -67,17 +72,23 @@ macro(add_llvm_tool name) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_TOOLS_BINARY_DIR}) + if( LLVM_BUILD_TOOLS ) + install(TARGETS ${name} RUNTIME DESTINATION bin) + else() + set(EXCLUDE_FROM_ALL ON) + endif() add_llvm_executable(${name} ${ARGN}) - install(TARGETS ${name} - RUNTIME DESTINATION bin) endmacro(add_llvm_tool name) macro(add_llvm_example name) # set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_EXAMPLES_BINARY_DIR}) + if( LLVM_BUILD_EXAMPLES ) + install(TARGETS ${name} RUNTIME DESTINATION examples) + else() + set(EXCLUDE_FROM_ALL ON) + endif() add_llvm_executable(${name} ${ARGN}) - install(TARGETS ${name} - RUNTIME DESTINATION examples) endmacro(add_llvm_example name) Modified: llvm/trunk/docs/CMake.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CMake.html?rev=89635&r1=89634&r2=89635&view=diff ============================================================================== --- llvm/trunk/docs/CMake.html (original) +++ llvm/trunk/docs/CMake.html Sun Nov 22 18:21:43 2009 @@ -251,10 +251,16 @@ -DLLVM_TARGETS_TO_BUILD="X86;PowerPC;Alpha".
LLVM_BUILD_TOOLS:BOOL
-
Build LLVM tools. Defaults to ON.
+
Build LLVM tools. Defaults to ON. Targets for building each tool + are generated in any case. You can build an tool separately by + invoking its target. For example, you can build llvm-as + with a makefile-based system executing make llvm-as on the + root of your build directory.
LLVM_BUILD_EXAMPLES:BOOL
-
Build LLVM examples. Defaults to OFF.
+
Build LLVM examples. Defaults to OFF. Targets for building each + example are generated in any case. See documentation + for LLVM_BUILD_TOOLS above for more details.
LLVM_ENABLE_THREADS:BOOL
Build with threads support, if available. Defaults to ON.
From ofv at wanadoo.es Sun Nov 22 18:32:42 2009 From: ofv at wanadoo.es (Oscar Fuentes) Date: Mon, 23 Nov 2009 00:32:42 -0000 Subject: [llvm-commits] [llvm] r89636 - /llvm/trunk/cmake/modules/AddLLVM.cmake Message-ID: <200911230032.nAN0Wgoh011570@zion.cs.uiuc.edu> Author: ofv Date: Sun Nov 22 18:32:42 2009 New Revision: 89636 URL: http://llvm.org/viewvc/llvm-project?rev=89636&view=rev Log: CMake: Do not try to install a target before it is defined. Modified: llvm/trunk/cmake/modules/AddLLVM.cmake Modified: llvm/trunk/cmake/modules/AddLLVM.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=89636&r1=89635&r2=89636&view=diff ============================================================================== --- llvm/trunk/cmake/modules/AddLLVM.cmake (original) +++ llvm/trunk/cmake/modules/AddLLVM.cmake Sun Nov 22 18:32:42 2009 @@ -72,23 +72,25 @@ macro(add_llvm_tool name) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_TOOLS_BINARY_DIR}) - if( LLVM_BUILD_TOOLS ) - install(TARGETS ${name} RUNTIME DESTINATION bin) - else() + if( NOT LLVM_BUILD_TOOLS ) set(EXCLUDE_FROM_ALL ON) endif() add_llvm_executable(${name} ${ARGN}) + if( LLVM_BUILD_TOOLS ) + install(TARGETS ${name} RUNTIME DESTINATION bin) + endif() endmacro(add_llvm_tool name) macro(add_llvm_example name) # set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_EXAMPLES_BINARY_DIR}) - if( LLVM_BUILD_EXAMPLES ) - install(TARGETS ${name} RUNTIME DESTINATION examples) - else() + if( NOT LLVM_BUILD_EXAMPLES ) set(EXCLUDE_FROM_ALL ON) endif() add_llvm_executable(${name} ${ARGN}) + if( LLVM_BUILD_EXAMPLES ) + install(TARGETS ${name} RUNTIME DESTINATION examples) + endif() endmacro(add_llvm_example name) From ofv at wanadoo.es Sun Nov 22 18:40:39 2009 From: ofv at wanadoo.es (Oscar Fuentes) Date: Mon, 23 Nov 2009 00:40:39 -0000 Subject: [llvm-commits] [llvm] r89637 - /llvm/trunk/cmake/modules/LLVMLibDeps.cmake Message-ID: <200911230040.nAN0edSl011951@zion.cs.uiuc.edu> Author: ofv Date: Sun Nov 22 18:40:39 2009 New Revision: 89637 URL: http://llvm.org/viewvc/llvm-project?rev=89637&view=rev Log: CMake: Updated library dependencies. Modified: llvm/trunk/cmake/modules/LLVML