From jyasskin at google.com  Mon Mar 22 00:23:38 2010
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Mon, 22 Mar 2010 05:23:38 -0000
Subject: [llvm-commits] [llvm] r99160 - in /llvm/trunk:
 lib/VMCore/ConstantsContext.h lib/VMCore/LLVMContextImpl.cpp
 tools/bugpoint/BugDriver.cpp tools/bugpoint/BugDriver.h
Message-ID: <20100322052338.207252A6C12C@llvm.org>

Author: jyasskin
Date: Mon Mar 22 00:23:37 2010
New Revision: 99160

URL: http://llvm.org/viewvc/llvm-project?rev=99160&view=rev
Log:
Free all Constants in ~LLVMConstantImpl.  We avoid assertion failures
by dropping all references from all constants that can use other
constants before trying to destroy any of them.

I also had to free bugpoint's Module in ~BugDriver().


Modified:
    llvm/trunk/lib/VMCore/ConstantsContext.h
    llvm/trunk/lib/VMCore/LLVMContextImpl.cpp
    llvm/trunk/tools/bugpoint/BugDriver.cpp
    llvm/trunk/tools/bugpoint/BugDriver.h

Modified: llvm/trunk/lib/VMCore/ConstantsContext.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantsContext.h?rev=99160&r1=99159&r2=99160&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/ConstantsContext.h (original)
+++ llvm/trunk/lib/VMCore/ConstantsContext.h Mon Mar 22 00:23:37 2010
@@ -600,8 +600,8 @@
   void freeConstants() {
     for (typename MapTy::iterator I=Map.begin(), E=Map.end();
          I != E; ++I) {
-      if (I->second->use_empty())
-        delete I->second;
+      // Asserts that use_empty().
+      delete I->second;
     }
   }
     

Modified: llvm/trunk/lib/VMCore/LLVMContextImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContextImpl.cpp?rev=99160&r1=99159&r2=99160&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/LLVMContextImpl.cpp (original)
+++ llvm/trunk/lib/VMCore/LLVMContextImpl.cpp Mon Mar 22 00:23:37 2010
@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "LLVMContextImpl.h"
+#include <algorithm>
 
 LLVMContextImpl::LLVMContextImpl(LLVMContext &C)
   : TheTrueVal(0), TheFalseVal(0),
@@ -34,10 +35,32 @@
   OpaqueTypes.insert(AlwaysOpaqueTy);
 }
 
+namespace {
+struct DropReferences {
+  // Takes the value_type of a ConstantUniqueMap's internal map, whose 'second'
+  // is a Constant*.
+  template<typename PairT>
+  void operator()(const PairT &P) {
+    P.second->dropAllReferences();
+  }
+};
+}
+
 LLVMContextImpl::~LLVMContextImpl() {
+  std::for_each(ExprConstants.map_begin(), ExprConstants.map_end(),
+                DropReferences());
+  std::for_each(ArrayConstants.map_begin(), ArrayConstants.map_end(),
+                DropReferences());
+  std::for_each(StructConstants.map_begin(), StructConstants.map_end(),
+                DropReferences());
+  std::for_each(UnionConstants.map_begin(), UnionConstants.map_end(),
+                DropReferences());
+  std::for_each(VectorConstants.map_begin(), VectorConstants.map_end(),
+                DropReferences());
   ExprConstants.freeConstants();
   ArrayConstants.freeConstants();
   StructConstants.freeConstants();
+  UnionConstants.freeConstants();
   VectorConstants.freeConstants();
   AggZeroConstants.freeConstants();
   NullPtrConstants.freeConstants();
@@ -45,13 +68,11 @@
   InlineAsms.freeConstants();
   for (IntMapTy::iterator I = IntConstants.begin(), E = IntConstants.end(); 
        I != E; ++I) {
-    if (I->second->use_empty())
-      delete I->second;
+    delete I->second;
   }
   for (FPMapTy::iterator I = FPConstants.begin(), E = FPConstants.end(); 
        I != E; ++I) {
-    if (I->second->use_empty())
-      delete I->second;
+    delete I->second;
   }
   AlwaysOpaqueTy->dropRef();
   for (OpaqueTypesTy::iterator I = OpaqueTypes.begin(), E = OpaqueTypes.end();

Modified: llvm/trunk/tools/bugpoint/BugDriver.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/BugDriver.cpp?rev=99160&r1=99159&r2=99160&view=diff
==============================================================================
--- llvm/trunk/tools/bugpoint/BugDriver.cpp (original)
+++ llvm/trunk/tools/bugpoint/BugDriver.cpp Mon Mar 22 00:23:37 2010
@@ -75,6 +75,10 @@
     run_as_child(as_child), run_find_bugs(find_bugs), Timeout(timeout), 
     MemoryLimit(memlimit), UseValgrind(use_valgrind) {}
 
+BugDriver::~BugDriver() {
+  delete Program;
+}
+
 
 /// ParseInputFile - Given a bitcode or assembly input filename, parse and
 /// return it, or return null if not possible.

Modified: llvm/trunk/tools/bugpoint/BugDriver.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/BugDriver.h?rev=99160&r1=99159&r2=99160&view=diff
==============================================================================
--- llvm/trunk/tools/bugpoint/BugDriver.h (original)
+++ llvm/trunk/tools/bugpoint/BugDriver.h Mon Mar 22 00:23:37 2010
@@ -65,6 +65,7 @@
   BugDriver(const char *toolname, bool as_child, bool find_bugs,
             unsigned timeout, unsigned memlimit, bool use_valgrind,
             LLVMContext& ctxt);
+  ~BugDriver();
 
   const char *getToolName() const { return ToolName; }
 




From daniel at zuster.org  Mon Mar 22 02:18:15 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 07:18:15 -0000
Subject: [llvm-commits] [zorg] r99161 - in /zorg/trunk/lnt: README.txt
 lnt/viewer/app.py lnt/viewer/zorg.cgi lnt/viewer/zorg.wsgi
Message-ID: <20100322071815.7D47B2A6C12C@llvm.org>

Author: ddunbar
Date: Mon Mar 22 02:18:15 2010
New Revision: 99161

URL: http://llvm.org/viewvc/llvm-project?rev=99161&view=rev
Log:
LNT: Drop CGI support, install is now as easy as 1, 2, 3... 4. :)

Removed:
    zorg/trunk/lnt/lnt/viewer/zorg.cgi
    zorg/trunk/lnt/lnt/viewer/zorg.wsgi
Modified:
    zorg/trunk/lnt/README.txt
    zorg/trunk/lnt/lnt/viewer/app.py

Modified: zorg/trunk/lnt/README.txt
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/README.txt?rev=99161&r1=99160&r2=99161&view=diff
==============================================================================
--- zorg/trunk/lnt/README.txt (original)
+++ zorg/trunk/lnt/README.txt Mon Mar 22 02:18:15 2010
@@ -5,9 +5,9 @@
 infrastructure. This is technically version "3.0" of the LLVM nightly test
 architecture.
 
-LNT is written in Python and implements a (old-school) Quixote web-app,
-available by CGI and WSGI, and utilities for submitting data via LLVM's
-NewNightlyTest.pl in conjunction with LLVM's test-suite repository.
+LNT is written in Python and implements a WSGI web app on top of Quixote, along
+with utilities for submitting data via LLVM's NewNightlyTest.pl in conjunction
+with LLVM's test-suite repository.
 
 The infrastructure has the following layout:
 
@@ -64,13 +64,6 @@
     If running in a virtualenv you will need to configure that as well; see the
     `modwsgi wiki <http://code.google.com/p/modwsgi/wiki/VirtualEnvironments>`_.
 
- 5. Add a link or copy of the zorg.cgi app in the appropriate place if you want
-    to use the CGI script. The WSGI app is significantly faster, but currently
-    can't handle submissions.
-
- 6. Create a zorg/lnt/viewer/resources/graphs directory, which the app uses to
-    hold temporary files, and make sure it is writable by the Apache user.
-
 
 Development Instructions
 ------------------------

Modified: zorg/trunk/lnt/lnt/viewer/app.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/app.py?rev=99161&r1=99160&r2=99161&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/app.py (original)
+++ zorg/trunk/lnt/lnt/viewer/app.py Mon Mar 22 02:18:15 2010
@@ -1,18 +1,10 @@
 import os
 import sys
 
-def create_publisher(configPath=None):
+def create_publisher(configPath):
     import warnings
     warnings.simplefilter("ignore", category=DeprecationWarning)
 
-    if configPath is None:
-        # We expect the config file to be adjacent to the absolute path of
-        # the cgi script.
-        #
-        # FIXME: This behavior is deprecated and should be removed.
-        configPath = os.path.join(os.path.dirname(os.path.realpath(__file__)),
-                                  "zorg.cfg")
-
     configData = {}
     exec open(configPath) in configData
 

Removed: zorg/trunk/lnt/lnt/viewer/zorg.cgi
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/zorg.cgi?rev=99160&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/zorg.cgi (original)
+++ zorg/trunk/lnt/lnt/viewer/zorg.cgi (removed)
@@ -1,45 +0,0 @@
-#!/usr/bin/env python
-# -*- Python -*-
-
-import sys
-import os
-
-# These were just some local hacks I used at some point to enable testing with
-# MySQL. We were running afoul of cimport issues, I think. Revisit when we care
-# about MySQL.
-if 0:
-    os.environ['PATH'] += ':/usr/local/mysql/bin'
-
-    os.environ['PYTHON_EGG_CACHE'] = '/tmp'
-    import MySQLdb
-
-    import PerfDB
-    db = PerfDB.PerfDB("mysql://root:admin at localhost/nt_internal")
-    from PerfDB import Machine
-    q = db.session.query(Machine.name).distinct().order_by(Machine.name)
-    for i in q[:1]:
-        break
-
-def create_publisher():
-    import warnings
-    warnings.simplefilter("ignore", category=DeprecationWarning)
-
-    # We expect the config file to be adjacent to the absolute path of
-    # the cgi script.
-    configPath = os.path.join(os.path.dirname(os.path.realpath(__file__)),
-                          "zorg.cfg")
-    configData = {}
-    exec open(configPath) in configData
-
-    # Find the zorg installation dir.
-    zorgDir = os.path.join(os.path.dirname(configPath),
-                           configData.get('zorg', ''))
-    if zorgDir and zorgDir not in sys.path:
-        sys.path.append(zorgDir)
-
-    from viewer import publisher
-    return publisher.create_publisher(configPath, configData)
-
-if __name__ == '__main__':
-    from quixote.server import cgi_server
-    cgi_server.run(create_publisher)

Removed: zorg/trunk/lnt/lnt/viewer/zorg.wsgi
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/zorg.wsgi?rev=99160&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/zorg.wsgi (original)
+++ zorg/trunk/lnt/lnt/viewer/zorg.wsgi (removed)
@@ -1,13 +0,0 @@
-#!/usr/bin/env python2.6
-# -*- Python -*-
-
-import app
-
-application = app.create_app()
-
-if __name__ == '__main__':
-    from wsgiref.simple_server import make_server
-    print "Running test application."
-    print "  open http://localhost:8000/"
-    httpd = make_server('', 8000, application)
-    httpd.serve_forever()




From daniel at zuster.org  Mon Mar 22 02:18:19 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 07:18:19 -0000
Subject: [llvm-commits] [zorg] r99162 - in /zorg/trunk/lnt:
 lnt/import/ImportData lnt/import/ImportXCBTimes lnt/import/NTEmailReport.py
 lnt/viewer/app.py lnt/viewer/root.ptl lnt/viewer/zview/zviewui.ptl
 tests/Web/WebSubmit.py
Message-ID: <20100322071819.D17D12A6C12D@llvm.org>

Author: ddunbar
Date: Mon Mar 22 02:18:19 2010
New Revision: 99162

URL: http://llvm.org/viewvc/llvm-project?rev=99162&view=rev
Log:
LNT: Update imports and drop sys.path tricks now that we are building a proper package.

Modified:
    zorg/trunk/lnt/lnt/import/ImportData
    zorg/trunk/lnt/lnt/import/ImportXCBTimes
    zorg/trunk/lnt/lnt/import/NTEmailReport.py
    zorg/trunk/lnt/lnt/viewer/app.py
    zorg/trunk/lnt/lnt/viewer/root.ptl
    zorg/trunk/lnt/lnt/viewer/zview/zviewui.ptl
    zorg/trunk/lnt/tests/Web/WebSubmit.py

Modified: zorg/trunk/lnt/lnt/import/ImportData
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/ImportData?rev=99162&r1=99161&r2=99162&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/import/ImportData (original)
+++ zorg/trunk/lnt/lnt/import/ImportData Mon Mar 22 02:18:19 2010
@@ -10,11 +10,9 @@
 import plistlib
 import sys
 import time
-sys.path.append(os.path.join(os.path.dirname(__file__),'../'))
 
-import viewer
-from viewer import Util
-from viewer import PerfDB
+from lnt import viewer
+from lnt.viewer import Util, PerfDB
 import NightlytestReader
 import AppleOpenSSLReader
 

Modified: zorg/trunk/lnt/lnt/import/ImportXCBTimes
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/ImportXCBTimes?rev=99162&r1=99161&r2=99162&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/import/ImportXCBTimes (original)
+++ zorg/trunk/lnt/lnt/import/ImportXCBTimes Mon Mar 22 02:18:19 2010
@@ -3,10 +3,9 @@
 import os
 import time
 import sys
-sys.path.append(os.path.join(os.path.dirname(__file__),'../'))
-import viewer
-from viewer import Util
-from viewer import PerfDB
+
+from lnt import viewer
+from lnt.viewer import Util, PerfDB
 
 def main():
     global opts

Modified: zorg/trunk/lnt/lnt/import/NTEmailReport.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/NTEmailReport.py?rev=99162&r1=99161&r2=99162&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/import/NTEmailReport.py (original)
+++ zorg/trunk/lnt/lnt/import/NTEmailReport.py Mon Mar 22 02:18:19 2010
@@ -9,12 +9,11 @@
 import os
 import smtplib
 import sys
-sys.path.append(os.path.join(os.path.dirname(__file__),'../'))
 
 import StringIO
-import viewer
-from viewer import PerfDB
-from viewer.NTUtil import *
+from lnt import viewer
+from lnt.viewer import PerfDB
+from lnt.viewer.NTUtil import *
 
 def main():
     global opts

Modified: zorg/trunk/lnt/lnt/viewer/app.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/app.py?rev=99162&r1=99161&r2=99162&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/app.py (original)
+++ zorg/trunk/lnt/lnt/viewer/app.py Mon Mar 22 02:18:19 2010
@@ -16,11 +16,11 @@
 
     # Optionally enable auto-restart.
     if configData.get('wsgi_restart', False):
-        from viewer import wsgi_restart
+        from lnt.viewer import wsgi_restart
         wsgi_restart.track(configPath)
         wsgi_restart.start()
 
-    from viewer import publisher
+    from lnt.viewer import publisher
     return publisher.create_publisher(configPath, configData, threaded=True)
 
 def create_app(cfg_path=None):

Modified: zorg/trunk/lnt/lnt/viewer/root.ptl
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/root.ptl?rev=99162&r1=99161&r2=99162&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/root.ptl (original)
+++ zorg/trunk/lnt/lnt/viewer/root.ptl Mon Mar 22 02:18:19 2010
@@ -339,9 +339,9 @@
             # internally to fix the FIXME above and keep it more readable, we
             # want to serialize imports to keep SQLite happy and avoiding
             # dropping submissions.
-            import subprocess
-            p = subprocess.Popen([os.path.join(self.config.zorgDir,
-                                               "import/ImportData"),
+            import lnt, subprocess
+            lnt_dir = os.path.dirname(lnt.__file__)
+            p = subprocess.Popen([os.path.join(lnt_dir, "import/ImportData"),
                                   "--commit=%s" % form['commit'],
                                   "--email-on-import=%s" % int(self.config.ntEmailEnabled),
                                   "--email-base-url=%s/db_%s/nightlytest/" % (self.config.zorgURL,

Modified: zorg/trunk/lnt/lnt/viewer/zview/zviewui.ptl
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/zview/zviewui.ptl?rev=99162&r1=99161&r2=99162&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/zview/zviewui.ptl (original)
+++ zorg/trunk/lnt/lnt/viewer/zview/zviewui.ptl Mon Mar 22 02:18:19 2010
@@ -7,8 +7,8 @@
 from quixote.directory import Directory
 from quixote.html import htmltext
 
-from viewer.PerfDB import Machine, Run, Sample, Test
-from viewer import NTUtil
+from lnt.viewer.PerfDB import Machine, Run, Sample, Test
+from lnt.viewer import NTUtil
 
 from sqlalchemy import func
 

Modified: zorg/trunk/lnt/tests/Web/WebSubmit.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/Web/WebSubmit.py?rev=99162&r1=99161&r2=99162&view=diff
==============================================================================
--- zorg/trunk/lnt/tests/Web/WebSubmit.py (original)
+++ zorg/trunk/lnt/tests/Web/WebSubmit.py Mon Mar 22 02:18:19 2010
@@ -1,5 +1,5 @@
 # RUN: %src_root/lnt/import/SubmitData %base_url/submitRun \
-# RUN:   ../DB/Inputs/sample-a-small.plist > %t.log
+# RUN:   %S/../DB/Inputs/sample-a-small.plist > %t.log
 # RUN: FileCheck %s < %t.log
 
 # CHECK: STATUS: 0




From daniel at zuster.org  Mon Mar 22 02:18:23 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 07:18:23 -0000
Subject: [llvm-commits] [zorg] r99163 - in /zorg/trunk/lnt/lnt/lnttool:
	__init__.py create.py
Message-ID: <20100322071823.211502A6C12E@llvm.org>

Author: ddunbar
Date: Mon Mar 22 02:18:22 2010
New Revision: 99163

URL: http://llvm.org/viewvc/llvm-project?rev=99163&view=rev
Log:
'lnt': Factor out create tool, and move to OptionParser, its easier to document.

Added:
    zorg/trunk/lnt/lnt/lnttool/create.py
      - copied, changed from r99162, zorg/trunk/lnt/lnt/lnttool/__init__.py
Modified:
    zorg/trunk/lnt/lnt/lnttool/__init__.py

Modified: zorg/trunk/lnt/lnt/lnttool/__init__.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/__init__.py?rev=99163&r1=99162&r2=99163&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/lnttool/__init__.py (original)
+++ zorg/trunk/lnt/lnt/lnttool/__init__.py Mon Mar 22 02:18:22 2010
@@ -1,89 +1,33 @@
 """Implement the command line 'lnt' tool."""
 
-from werkzeug import script
-
-###
+import os
+import sys
 
-kConfigVersion = (0,1,0)
-kConfigTemplate = """\
-# LNT (aka Zorg) configuration file
-#
-# Paths are resolved relative to this file.
-
-# The configuration file version.
-config_version = %(cfg_version)r
-
-# Name to use for this installation. This appears in web page headers, for
-# example.
-name = %(name)r
-
-# Path to the LNT root.
-zorg = %(zorg_dir)r
-
-# Path to the LNT server.
-zorgURL = %(hosturl)r
-
-# Temporary directory, for use by the web app. This must be writable by the user
-# the web app runs as.
-tmp_dir = %(tmp_dir)r
-
-# Database directory, for easily rerooting the entire set of database. Database
-# paths are resolved relative to the config path + this path.
-db_dir = %(db_dir)r
-
-# The list of available databases, and their properties. At a minimum, there
-# should be a 'default' entry for the default database.
-databases = {
-    'default' : { 'path' : %(default_db)r,
-                  'showNightlytest' : 1 },
-    }
-
-# The LNT email configuration.
-#
-# The 'to' field can be either a single email address, or a list of
-# (regular-expression, address) pairs. In the latter form, the machine name of
-# the submitted results is matched against the regular expressions to determine
-# which email address to use for the results.
-nt_emailer = {
-    'enabled' : False,
-    'host' : None,
-    'from' : None,
-
-    # This is a list of (filter-regexp, address) pairs -- it is evaluated in
-    # order based on the machine name. This can be used to dispatch different
-    # reports to different email address.
-    'to' : [(".*", None)],
-    }
-
-# Enable automatic restart using the wsgi_restart module; this should be off in
-# a production environment.
-wsgi_restart = False
-"""
-
-kWSGITemplate = """\
-#!/usr/bin/env python2.6
-# -*- Python -*-
-
-from lnt.viewer import app
-
-application = app.create_app(%(cfg_path)r)
-
-if __name__ == "__main__":
-    import werkzeug
-    werkzeug.run_simple('localhost', 8000, application)
-"""
+def action_runserver(name, args):
+    """start a new development server."""
 
-###
+    from optparse import OptionParser, OptionGroup
+    parser = OptionParser("%%prog %s [options] [<path|config file>]" % name)
+    parser.add_option("", "--hostname", dest="hostname", type=str,
+                      help="host interface to use [%default]",
+                      default='localhost')
+    parser.add_option("", "--port", dest="port", type=int, metavar="N",
+                      help="local port to use [%default]", default=8000)
+    parser.add_option("", "--reloader", dest="reloader", default=False,
+                      action="store_true", help="use WSGI reload monitor")
+    parser.add_option("", "--debugger", dest="debugger", default=False,
+                      action="store_true", help="use WSGI debugger")
+    parser.add_option("", "--threaded", dest="threaded", default=False,
+                      action="store_true", help="use a threaded server")
+    parser.add_option("", "--processes", dest="processes", type=int,
+                      metavar="N", help="number of processes to use [%default]",
+                      default=1)
+
+    (opts, args) = parser.parse_args(args)
+    if len(args) != 1:
+        parser.error("invalid number of arguments")
 
-import os
-import platform
-from lnt.viewer import app
-
-def action_runserver(config='', hostname=('h','localhost'), port=('p',8000),
-                     reloader=False, debugger=False, evalex=False,
-                     threaded=False, processes=1):
-    """Start a new development server."""
-    from werkzeug import run_simple
+    config, = args
 
     # Accept paths to config files, or to directories containing 'lnt.cfg'.
     if os.path.isdir(config):
@@ -94,70 +38,32 @@
     if not config or not os.path.exists(config):
         raise SystemExit,"error: invalid config: %r" % config
 
-    run_simple(hostname, port, app.create_app(config), reloader, debugger,
-               evalex, None, 1, threaded, processes)
-
-
-def action_create(path='', name='LNT', config='lnt.cfg', wsgi='lnt.wsgi',
-                  tmp_dir='lnt_tmp', db_dir='data', default_db='lnt.db',
-                  hostname=platform.uname()[1], hostsuffix='perf'):
-    """Create an LLVM nightly test installation"""
-
-    if not path:
-        raise SystemExit,"error: invalid path: %r" % path
-
-    basepath = os.path.abspath(path)
-    if os.path.exists(basepath):
-        raise SystemExit,"error: invalid path: %r already exists" % path
-
-    hosturl = "http://%s/%s" % (hostname, hostsuffix)
-
-    # FIXME: Eliminate this variable and just require that LNT be installed.
-    import lnt
-    zorg_dir = os.path.dirname(lnt.__file__)
-
-    db_dir_path = os.path.join(basepath, db_dir)
-    cfg_path = os.path.join(basepath, config)
-    db_path = os.path.join(db_dir_path, default_db)
-    tmp_path = os.path.join(basepath, tmp_dir)
-    wsgi_path = os.path.join(basepath, wsgi)
-
-    os.mkdir(path)
-    os.mkdir(db_dir_path)
-    os.mkdir(tmp_path)
-
-    cfg_version = kConfigVersion
-    cfg_file = open(cfg_path, 'w')
-    cfg_file.write(kConfigTemplate % locals())
-    cfg_file.close()
-
-    wsgi_file = open(wsgi_path, 'w')
-    wsgi_file.write(kWSGITemplate % locals())
-    wsgi_file.close()
-
-    from lnt.viewer import PerfDB
-    db = PerfDB.PerfDB('sqlite:///' + db_path)
-    db.commit()
-
-    print 'created LNT configuration in %r' % basepath
-    print '  configuration file: %s' % cfg_path
-    print '  WSGI app          : %s' % wsgi_path
-    print '  database file     : %s' % db_path
-    print '  temporary dir     : %s' % tmp_path
-    print '  host URL          : %s' % hosturl
-    print
-    print 'You can execute:'
-    print '  python %s' % wsgi_path
-    print 'to test your installation with the builtin server.'
-    print
-    print 'For production use configure this application to run with any'
-    print 'WSGI capable web server. You may need to modify the permissions'
-    print 'on the database and temporary file directory to allow writing'
-    print 'by the web app.'
-    print
+    from werkzeug import run_simple
+    from lnt.viewer import app
+    run_simple(opts.hostname, opts.port, app.create_app(opts.config),
+               opts.reloader, opts.debugger,
+               False, None, 1, opts.threaded, opts.processes)
+
+from create import action_create
+
+commands = dict((name[7:], f) for name,f in locals().items()
+                if name.startswith('action_'))
+
+def usage():
+    print >>sys.stderr, "Usage: %s command [options]" % (
+        os.path.basename(sys.argv[0]))
+    print >>sys.stderr
+    print >>sys.stderr, "Available commands:"
+    cmds_width = max(map(len, commands))
+    for name,func in sorted(commands.items()):
+        print >>sys.stderr, "  %-*s - %s" % (cmds_width, name, func.__doc__)
+    sys.exit(1)
 
 def main():
-    script.run(globals())
+    import sys
+
+    if len(sys.argv) < 2 or sys.argv[1] not in commands:
+        usage()
 
-if __name__ == '__main__':
-    main()
+    cmd = sys.argv[1]
+    commands[cmd](cmd, sys.argv[2:])

Copied: zorg/trunk/lnt/lnt/lnttool/create.py (from r99162, zorg/trunk/lnt/lnt/lnttool/__init__.py)
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/create.py?p2=zorg/trunk/lnt/lnt/lnttool/create.py&p1=zorg/trunk/lnt/lnt/lnttool/__init__.py&r1=99162&r2=99163&rev=99163&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/lnttool/__init__.py (original)
+++ zorg/trunk/lnt/lnt/lnttool/create.py Mon Mar 22 02:18:22 2010
@@ -1,6 +1,5 @@
-"""Implement the command line 'lnt' tool."""
-
-from werkzeug import script
+import os
+import platform
 
 ###
 
@@ -17,9 +16,6 @@
 # example.
 name = %(name)r
 
-# Path to the LNT root.
-zorg = %(zorg_dir)r
-
 # Path to the LNT server.
 zorgURL = %(hosturl)r
 
@@ -75,36 +71,44 @@
 
 ###
 
-import os
-import platform
-from lnt.viewer import app
-
-def action_runserver(config='', hostname=('h','localhost'), port=('p',8000),
-                     reloader=False, debugger=False, evalex=False,
-                     threaded=False, processes=1):
-    """Start a new development server."""
-    from werkzeug import run_simple
-
-    # Accept paths to config files, or to directories containing 'lnt.cfg'.
-    if os.path.isdir(config):
-        tmp = os.path.join(config, 'lnt.cfg')
-        if os.path.exists(tmp):
-            config = tmp
-
-    if not config or not os.path.exists(config):
-        raise SystemExit,"error: invalid config: %r" % config
-
-    run_simple(hostname, port, app.create_app(config), reloader, debugger,
-               evalex, None, 1, threaded, processes)
-
-
-def action_create(path='', name='LNT', config='lnt.cfg', wsgi='lnt.wsgi',
-                  tmp_dir='lnt_tmp', db_dir='data', default_db='lnt.db',
-                  hostname=platform.uname()[1], hostsuffix='perf'):
-    """Create an LLVM nightly test installation"""
+def action_create(name, args):
+    """create an LLVM nightly test installation"""
 
-    if not path:
-        raise SystemExit,"error: invalid path: %r" % path
+    from optparse import OptionParser, OptionGroup
+    parser = OptionParser("%%prog %s [options] [<path|config file>]" % name)
+    parser.add_option("", "--name", dest="name", default="LNT",
+                      help="name to use for the installation [%default]")
+    parser.add_option("", "--config", dest="config", default="lnt.cfg",
+                      help="name of the LNT config file [%default]")
+    parser.add_option("", "--wsgi", dest="wsgi",  default="lnt.wsgi",
+                      help="name of the WSGI app  [%default]")
+    parser.add_option("", "--tmp-dir", dest="tmp_dir", default="lnt_tmp",
+                      help="name of the temp file directory [%default]")
+    parser.add_option("", "--db-dir", dest="db_dir", default="data",
+                      help="name of the directory to hold databases")
+    parser.add_option("", "--default-db", dest="default_db", default="lnt.db",
+                      help="name for the default db [%default]", metavar="NAME")
+    parser.add_option("", "--hostname", dest="hostname",
+                      default=platform.uname()[1],
+                      help="host name of the server [%default]", metavar="NAME")
+    parser.add_option("", "--hostsuffix", dest="hostsuffix", default="perf",
+                      help="suffix at which WSGI app lives [%default]",
+                      metavar="NAME")
+
+    (opts, args) = parser.parse_args(args)
+    if len(args) != 1:
+        parser.error("invalid number of arguments")
+
+    path, = args
+
+    name = opts.name
+    config = opts.config
+    wsgi = opts.wsgi
+    tmp_dir = opts.tmp_dir
+    db_dir = opts.db_dir
+    default_db = opts.default_db
+    hostname = opts.hostname
+    hostsuffix = opts.hostsuffix
 
     basepath = os.path.abspath(path)
     if os.path.exists(basepath):
@@ -112,10 +116,6 @@
 
     hosturl = "http://%s/%s" % (hostname, hostsuffix)
 
-    # FIXME: Eliminate this variable and just require that LNT be installed.
-    import lnt
-    zorg_dir = os.path.dirname(lnt.__file__)
-
     db_dir_path = os.path.join(basepath, db_dir)
     cfg_path = os.path.join(basepath, config)
     db_path = os.path.join(db_dir_path, default_db)
@@ -155,9 +155,3 @@
     print 'on the database and temporary file directory to allow writing'
     print 'by the web app.'
     print
-
-def main():
-    script.run(globals())
-
-if __name__ == '__main__':
-    main()




From daniel at zuster.org  Mon Mar 22 02:18:29 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 07:18:29 -0000
Subject: [llvm-commits] [zorg] r99164 - in /zorg/trunk/lnt: lnt/formats/
 lnt/import/ lnt/lnttool/ tests/Formats/ tests/Formats/Inputs/
Message-ID: <20100322071829.CAC9B2A6C12C@llvm.org>

Author: ddunbar
Date: Mon Mar 22 02:18:29 2010
New Revision: 99164

URL: http://llvm.org/viewvc/llvm-project?rev=99164&view=rev
Log:
LNT: Reimplement format handling.
 - Transparently convert between formats.

 - Change NTAuxSubmit to submit the data directly; this lets it be free-standing which is useful for automating submission scripts (one can just 'svn export' it). The server can handle the conversion.

 - Add support for JSON files.

Added:
    zorg/trunk/lnt/lnt/formats/
    zorg/trunk/lnt/lnt/formats/AppleOpenSSLReader.py
      - copied, changed from r99163, zorg/trunk/lnt/lnt/import/AppleOpenSSLReader.py
    zorg/trunk/lnt/lnt/formats/JSONFormat.py
    zorg/trunk/lnt/lnt/formats/NightlytestReader.py
      - copied, changed from r99163, zorg/trunk/lnt/lnt/import/NightlytestReader.py
    zorg/trunk/lnt/lnt/formats/PlistFormat.py
    zorg/trunk/lnt/lnt/formats/__init__.py
    zorg/trunk/lnt/lnt/lnttool/convert.py
    zorg/trunk/lnt/tests/Formats/
    zorg/trunk/lnt/tests/Formats/Inputs/
    zorg/trunk/lnt/tests/Formats/Inputs/test.json
    zorg/trunk/lnt/tests/Formats/Inputs/test.nightlytest
    zorg/trunk/lnt/tests/Formats/Inputs/test.plist
    zorg/trunk/lnt/tests/Formats/json.py
    zorg/trunk/lnt/tests/Formats/nightlytest.py
    zorg/trunk/lnt/tests/Formats/plist.py
Removed:
    zorg/trunk/lnt/lnt/import/AppleOpenSSLReader.py
    zorg/trunk/lnt/lnt/import/ImportXCBTimes
    zorg/trunk/lnt/lnt/import/NightlytestReader.py
Modified:
    zorg/trunk/lnt/lnt/import/ImportData
    zorg/trunk/lnt/lnt/import/NTAuxSubmit
    zorg/trunk/lnt/lnt/lnttool/__init__.py

Copied: zorg/trunk/lnt/lnt/formats/AppleOpenSSLReader.py (from r99163, zorg/trunk/lnt/lnt/import/AppleOpenSSLReader.py)
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/formats/AppleOpenSSLReader.py?p2=zorg/trunk/lnt/lnt/formats/AppleOpenSSLReader.py&p1=zorg/trunk/lnt/lnt/import/AppleOpenSSLReader.py&r1=99163&r2=99164&rev=99164&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/import/AppleOpenSSLReader.py (original)
+++ zorg/trunk/lnt/lnt/formats/AppleOpenSSLReader.py Mon Mar 22 02:18:29 2010
@@ -1,3 +1,7 @@
+"""
+Converter for a custom format with the output of OpenSSL test runs.
+"""
+
 import os
 
 def parseOpenSSLFile(path):
@@ -23,7 +27,17 @@
 
     return data
 
-def loadData(path):
+def _matches_format(path_or_file):
+    # If this is a file, we definitely can't load it.
+    if not isinstance(path_or_file,str):
+        return False
+
+    # Assume an input matches this format if any of the key files exists.
+    return (os.path.exists(os.path.join(path_or_file, 'svn-revision')) or
+            os.path.exists(os.path.join(path_or_file, 'start.timestamp')) or
+            os.path.exists(os.path.join(path_or_file, 'finished.timestamp')))
+                     
+def _load_data(path):
     # Look for svn-revision and timestamps.
 
     llvmRevision = ''
@@ -92,23 +106,6 @@
              'Tests' : tests,
              'Group Info' : groupInfo }
 
-def main():
-    import plistlib
-    import sys
-
-    global opts
-    from optparse import OptionParser
-    parser = OptionParser("usage: %prog raw-data-path output")
-    opts,args = parser.parse_args()
-
-    if len(args) != 2:
-        parser.error("incorrect number of argments")
-
-    file,output = args
-
-    data = loadData(file)
-
-    plistlib.writePlist(data, output)
-
-if __name__=='__main__':
-    main()
+format = { 'name' : 'apple_openssl',
+           'predicate' : _matches_format,
+           'read' : _load_data }

Added: zorg/trunk/lnt/lnt/formats/JSONFormat.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/formats/JSONFormat.py?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/formats/JSONFormat.py (added)
+++ zorg/trunk/lnt/lnt/formats/JSONFormat.py Mon Mar 22 02:18:29 2010
@@ -0,0 +1,22 @@
+import json
+
+def _matches_format(path_or_file):
+    if isinstance(path_or_file, str):
+        path_or_file = open(path_or_file)
+
+    try:
+        json.load(path_or_file)
+        return True
+    except:
+        return False
+
+def _load_format(path_or_file):
+    if isinstance(path_or_file, str):
+        path_or_file = open(path_or_file)
+    
+    return json.load(path_or_file)
+    
+format = { 'name' : 'json',
+           'predicate' : _matches_format,
+           'read' : _load_format,
+           'write' : json.dump }

Copied: zorg/trunk/lnt/lnt/formats/NightlytestReader.py (from r99163, zorg/trunk/lnt/lnt/import/NightlytestReader.py)
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/formats/NightlytestReader.py?p2=zorg/trunk/lnt/lnt/formats/NightlytestReader.py&p1=zorg/trunk/lnt/lnt/import/NightlytestReader.py&r1=99163&r2=99164&rev=99164&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/import/NightlytestReader.py (original)
+++ zorg/trunk/lnt/lnt/formats/NightlytestReader.py Mon Mar 22 02:18:29 2010
@@ -1,17 +1,26 @@
-#!/usr/bin/env python
-
 """
 Data converter from the llvm/utils/NewNightlyTest.pl report file format
 (*-sentdata.txt) to the LNT plist format.
 """
 
-# FIXME: Refactor data conversion code.
-
 import re
 
 kDataKeyStart = re.compile('(.*)  =>(.*)')
 
-def loadSentData(path):
+def _matches_format(path_or_file):
+    if isinstance(path_or_file, str):
+        path_or_file = open(path_or_file)
+
+    # Assume this is in nightlytes format if the first line matches the
+    # key-value format.
+    for ln in path_or_file:
+        m = kDataKeyStart.match(ln)
+        if m:
+            return True
+        return False
+
+        
+def _load_data(path_or_file):
     def parseDGResults(text):
         results = {}
         if 'Dejagnu skipped by user choice' in text:
@@ -22,13 +31,17 @@
             results[result].append(value)
         return results
 
+    if isinstance(path_or_file, str):
+        path_or_file = open(path_or_file)
+
     basename = 'nightlytest'
 
     # Guess the format (server side or client side) based on the first
     # character.
-    isServerSide = (open(path).read(1) == '\'')
+    f = path_or_file
+    isServerSide = (f.read(1) == '\'')
+    f.seek(0)
 
-    f = open(path)
     data = {}
 
     current = None
@@ -224,26 +237,6 @@
              'Tests' : tests,
              'Group Info' : groupInfo }
 
-def convertNTData(inputPath, outputPath):
-    """convertNTData - Convert a nightlytest "sentdata.txt" file into a zorg
-    plist file."""
-    import plistlib
-
-    data = loadSentData(inputPath)
-    plistlib.writePlist(data, outputPath)
-
-def main():
-    global opts
-    from optparse import OptionParser
-    parser = OptionParser("usage: %prog file output")
-    opts,args = parser.parse_args()
-
-    if len(args) != 2:
-        parser.error("incorrect number of argments")
-
-    file,output = args
-
-    convertNTData(file, output)
-
-if __name__=='__main__':
-    main()
+format = { 'name' : 'nightlytest',
+           'predicate' : _matches_format,
+           'read' : _load_data }

Added: zorg/trunk/lnt/lnt/formats/PlistFormat.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/formats/PlistFormat.py?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/formats/PlistFormat.py (added)
+++ zorg/trunk/lnt/lnt/formats/PlistFormat.py Mon Mar 22 02:18:29 2010
@@ -0,0 +1,13 @@
+import plistlib
+
+def _matches_format(path_or_file):
+    try:
+        plistlib.readPlist(path_or_file)
+        return True
+    except:
+        return False
+
+format = { 'name' : 'plist',
+           'predicate' : _matches_format,
+           'read' : plistlib.readPlist,
+           'write' : plistlib.writePlist }

Added: zorg/trunk/lnt/lnt/formats/__init__.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/formats/__init__.py?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/formats/__init__.py (added)
+++ zorg/trunk/lnt/lnt/formats/__init__.py Mon Mar 22 02:18:29 2010
@@ -0,0 +1,67 @@
+"""
+Utilities for converting to LNT's test format.
+"""
+
+from AppleOpenSSLReader import format as apple_openssl
+from NightlytestReader import format as nightlytest
+from PlistFormat import format as plist
+from JSONFormat import format as json
+
+# FIXME: Lazy loading would be nice.
+formats = [plist, json, nightlytest, apple_openssl]
+formats_by_name = dict((f['name'], f) for f in formats)
+format_names = formats_by_name.keys()
+
+def get_format(name):
+    return formats_by_name.get(name)
+    
+def guess_format(path_or_file):
+    """guess_format(path_or_file) -> [format]
+
+    Guess which format should be used to load the given file and return it, if
+    found.
+    """
+
+    # Check that files are seekable.
+    is_file = False
+    if not isinstance(path_or_file, str):
+        is_file = True
+        path_or_file.seek(0)
+
+    matches = None
+    for f in formats:
+        # Check if the path matches this format, ignoring exceptions.
+        try:
+            try:
+                if not f['predicate'](path_or_file):
+                    continue
+            except:
+                continue
+        finally:
+            if is_file:
+                # Reset seek.
+                path_or_file.seek(0)
+
+        # Reject anything which matches multiple formats.
+        if matches:
+            return None
+
+        matches = f
+
+    return matches
+
+def read_any(path_or_file, format_name):
+    # Figure out the input format.
+    if format_name == '<auto>':
+        f = guess_format(path_or_file)
+        if f is None:
+            if isinstance(path_or_file, str):
+                raise SystemExit("unable to guess input format for %r" % input)
+            else:
+                raise SystemExit("unable to guess input format for file")
+    else:
+        f = get_format(format_name)
+        if f is None or not f.get('read'):
+            raise SystemExit("unknown input format: %r" % inFormat)
+
+    return f['read'](path_or_file)

Removed: zorg/trunk/lnt/lnt/import/AppleOpenSSLReader.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/AppleOpenSSLReader.py?rev=99163&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/import/AppleOpenSSLReader.py (original)
+++ zorg/trunk/lnt/lnt/import/AppleOpenSSLReader.py (removed)
@@ -1,114 +0,0 @@
-import os
-
-def parseOpenSSLFile(path):
-    data = open(path).read()
-    lines = list(open(path))
-    lnfields = [ln.strip().split(':') for ln in lines]
-    assert(lnfields[0][0] == '+H')
-    header = lnfields[0]
-    blockSizes = map(int, header[1:])
-
-    # Cipher -> [(Block Size,Value)*]
-    data = {}
-    for fields in lnfields[1:]:
-        # Ignore other fields
-        if fields[0] != '+F':
-            continue
-
-        name = fields[2]
-        countsPerBlock = fields[3:]
-        assert len(countsPerBlock) == len(blockSizes)
-        data[name] = [(b,float(c))
-                      for b,c in zip(blockSizes,countsPerBlock)]
-
-    return data
-
-def loadData(path):
-    # Look for svn-revision and timestamps.
-
-    llvmRevision = ''
-    startTime = endTime = ''
-
-    f = os.path.join(path, 'svn-revision')
-    if os.path.exists(f):
-        svnRevisionData = open(f).read()
-        assert(svnRevisionData[0] == 'r')
-        llvmRevision = int(svnRevisionData[1:])
-
-    f = os.path.join(path, 'start.timestamp')
-    if os.path.exists(f):
-        startTime = open(f).read().strip()
-
-    f = os.path.join(path, 'finished.timestamp')
-    if os.path.exists(f):
-        endTime = open(f).read().strip()
-
-    # Look for sub directories
-    openSSLData = []
-    for file in os.listdir(path):
-        p = os.path.join(path, file)
-        if os.path.isdir(p):
-            # Look for Tests/Apple.OpenSSL.64/speed.txt
-            p = os.path.join(p, 'Tests/Apple.OpenSSL.64/speed.txt')
-            if os.path.exists(p):
-                openSSLData.append((file, parseOpenSSLFile(p)))
-
-    basename = 'apple_openssl'
-
-    machine = { 'Name' : 'dgohman.apple.com',
-                'Info' : {  } }
-
-    run = { 'Start Time' : startTime,
-            'End Time' : endTime,
-            'Info' : { 'llvm-revision' : llvmRevision,
-                       'tag' : 'apple_openssl' } }
-
-    tests = []
-    groupInfo = []
-
-    for dirName,dirData in openSSLData:
-        # Demangle compiler & flags
-        if dirName.startswith('gcc'):
-            compiler = 'gcc'
-        elif dirName.startswith('llvm-gcc'):
-            compiler = 'llvm-gcc'
-        else:
-            raise ValueError,compiler
-        assert dirName[len(compiler)] == '-'
-        flags = dirName[len(compiler)+1:]
-
-        for cipher,values in dirData.items():
-            testName = basename + '.' + cipher + '.ips'
-            for block,value in values:
-                parameters = { 'blockSize' : block,
-                               'compiler' : compiler,
-                               'compiler_flags' : flags }
-                tests.append( { 'Name' : testName,
-                                'Info' : parameters,
-                                'Data' : [value] } )
-
-    return { 'Machine' : machine,
-             'Run' : run,
-             'Tests' : tests,
-             'Group Info' : groupInfo }
-
-def main():
-    import plistlib
-    import sys
-
-    global opts
-    from optparse import OptionParser
-    parser = OptionParser("usage: %prog raw-data-path output")
-    opts,args = parser.parse_args()
-
-    if len(args) != 2:
-        parser.error("incorrect number of argments")
-
-    file,output = args
-
-    data = loadData(file)
-
-    plistlib.writePlist(data, output)
-
-if __name__=='__main__':
-    main()

Modified: zorg/trunk/lnt/lnt/import/ImportData
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/ImportData?rev=99164&r1=99163&r2=99164&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/import/ImportData (original)
+++ zorg/trunk/lnt/lnt/import/ImportData Mon Mar 22 02:18:29 2010
@@ -11,10 +11,8 @@
 import sys
 import time
 
-from lnt import viewer
+from lnt import formats, viewer
 from lnt.viewer import Util, PerfDB
-import NightlytestReader
-import AppleOpenSSLReader
 
 def main():
     global opts
@@ -31,8 +29,8 @@
     parser.add_option("", "--email-to", dest="emailReportTo", type=str,
                       default=None)
     parser.add_option("", "--format", dest="format",
-                      choices=('plist','nightlytest','apple_openssl'),
-                      default='plist')
+                      choices=formats.format_names + ['<auto>'],
+                      default='<auto>')
     parser.add_option("", "--commit", dest="commit", type=int,
                       default=True)
     parser.add_option("", "--show-sql", dest="showSQL", action="store_true",
@@ -62,13 +60,9 @@
     print 'TOTAL IMPORT TIME: %.2fs' % (time.time() - startTime,)
 
 def importFiles(db, files):
-    importer = { 'plist' : plistlib.readPlist,
-                 'nightlytest' : NightlytestReader.loadSentData,
-                 'apple_openssl' : AppleOpenSSLReader.loadData }[opts.format]
-
     def consumer(file):
         try:
-            return importer(file)
+            return formats.read_any(file, opts.format)
         except KeyboardInterrupt:
             raise
         except:

Removed: zorg/trunk/lnt/lnt/import/ImportXCBTimes
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/ImportXCBTimes?rev=99163&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/import/ImportXCBTimes (original)
+++ zorg/trunk/lnt/lnt/import/ImportXCBTimes (removed)
@@ -1,106 +0,0 @@
-#!/usr/bin/env python
-
-import os
-import time
-import sys
-
-from lnt import viewer
-from lnt.viewer import Util, PerfDB
-
-def main():
-    global opts
-    from optparse import OptionParser
-    parser = OptionParser("usage: %prog file dbpath")
-    parser.add_option("", "--test-prefix",
-                      action="store", dest="testPrefix", default=None)
-    opts,args = parser.parse_args()
-
-    if len(args) != 2:
-        parser.error("incorrect number of argments")
-    if not opts.testPrefix:
-        parser.error("must specify test prefix")
-
-    dbpath,file = args
-
-    globals = {}
-    exec open(file) in globals, globals
-
-    db = PerfDB.PerfDB(dbpath)
-
-    numMachines = db.getNumMachines()
-    numTests = db.getNumTests()
-    numSamples = db.getNumSamples()
-
-    # Hardcode some things that aren't in the file
-    machine = PerfDB.Machine(-1,
-                             name = 'lordcrumb.apple.com',
-                             arch = 'Intel i386',
-                             os = 'SnowLeopard',
-                             hwconfig = '<unknown>',
-                             compiler = '<unknown>')
-    machine = db.getOrCreateMachine(machine)
-    print "MACHINE: %r" % machine
-
-    # Treat as a single "run"; our DB format has no way to lock
-    # individual samples together. I recall now that this was the
-    # motivation in treating a sample as a group of numbers, not just
-    # one.
-
-    # Rough guess.
-    mtime = os.stat(file).st_mtime
-    timestamp = time.strftime('%Y-%m-%dT%H:%M:%Sz', time.localtime(mtime))
-
-    # FIXME: Need to extract revision. :(
-    run = db.createRun(machine, PerfDB.Run(-1, -1, timestamp=timestamp, svnRevision=None))
-    print "RUN: %r" % run
-
-    ####
-
-    runs = globals.get('runs')
-    for keys,data in runs:
-        # Mangle a test name
-        testName = '%s:threads=%s:pch=%s:mode=%s' % (opts.testPrefix,
-                                                     keys.get('threads'),
-                                                     int(keys.get('pch') == 'pch'),
-                                                     keys.get('script'))
-        compiler = keys.get('cc')
-        compiler = compiler.replace('clang_driver','clang')
-        compiler = compiler.replace('_','/')
-        compiler = compiler.replace('xcc','ccc')
-        compilerOpts = '-O0,-g'
-
-        userTest = db.getOrCreateTest(PerfDB.Test(-1,
-                                                  name = testName,
-                                                  subtest = 'user',
-                                                  kindID = None,
-                                                  groupID = None,
-                                                  compiler = compiler,
-                                                  compilerOpts = compilerOpts))
-        sysTest = db.getOrCreateTest(PerfDB.Test(-1,
-                                                  name = testName,
-                                                  subtest = 'sys',
-                                                  kindID = None,
-                                                  groupID = None,
-                                                  compiler = compiler,
-                                                  compilerOpts = compilerOpts))
-        wallTest = db.getOrCreateTest(PerfDB.Test(-1,
-                                                  name = testName,
-                                                  subtest = 'wall',
-                                                  kindID = None,
-                                                  groupID = None,
-                                                  compiler = compiler,
-                                                  compilerOpts = compilerOpts))
-        assert data['version'] == 0
-        for (mem,user,sys,wall) in data['samples']:
-            db.addSample(userTest, run, PerfDB.Sample(-1, -1, -1, '', user))
-            db.addSample(sysTest, run, PerfDB.Sample(-1, -1, -1, '', sys))
-            db.addSample(wallTest, run, PerfDB.Sample(-1, -1, -1, '', wall))
-
-    db.commit()
-
-    print "ADDED: %d machines, %d tests, and %d samples." % (db.getNumMachines() - numMachines,
-                                                             db.getNumTests() - numTests,
-                                                             db.getNumSamples() - numSamples)
-
-if __name__ == '__main__':
-    main()

Modified: zorg/trunk/lnt/lnt/import/NTAuxSubmit
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/NTAuxSubmit?rev=99164&r1=99163&r2=99164&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/import/NTAuxSubmit (original)
+++ zorg/trunk/lnt/lnt/import/NTAuxSubmit Mon Mar 22 02:18:29 2010
@@ -4,15 +4,17 @@
 Command line tool for submitting to a LNT server.
 
 This script is explicitly designed to work with llvm/utils/NewNightlyTest.pl's
--submit-aux argument. It simply converts the data and submits it to the llvm.org
-nightly test server.
-"""
+-submit-aux argument. It simply uploads the data to the server, and assumes the
+server will sort out any input conversion issues.
 
-# FIXME: Roll into lnttool and kill.
+This script should be totally free-standing; it is designed so users can svn
+export it directly from the LLVM repository as part of their submission scripts.
+"""
 
+import plistlib
 import sys
-import NightlytestReader
-import ServerUtil
+import urllib
+import urllib2
 
 def main():
     global opts
@@ -20,7 +22,6 @@
     parser = OptionParser("usage: %prog {nightlytest sentdata.txt}*")
     parser.add_option("", "--commit", dest="commit", type=int,
                       default=True)
-    parser.add_option("", "--no-convert", dest="noConvert")
 
     # FIXME: It would be nice to support an easy mechanism for localized
     # instances of the LNT infrastructure to default to the correct server for
@@ -36,17 +37,20 @@
     for inputFile in args:
         print '%s: note: submitting %s' % (sys.argv[0], inputFile)
 
-        if opts.noConvert:
-            plistPath = inputFile
-        else:
-            # Convert to the zorg format.
-            #
-            # FIXME: Avoid temp file.
-            plistPath = "/tmp/t.plist"
-            NightlytestReader.convertNTData(inputFile, plistPath)
+        # Encode the form data.
+        f = open(inputFile, 'rb')
+        values = { 'input_data' : f.read(),
+                   'commit' : ("0","1")[not not commit] }
+        f.close()
+        data = urllib.urlencode(values)
 
         # Send it off.
-        ServerUtil.submitFiles(opts.serverUrl, [plistPath], opts.commit)
+        response = urllib2.urlopen(urllib2.Request(url, data))
+        the_page = response.read()
+
+        # FIXME: Parse results and return proper error code.
+        print the_page
+
 
 if __name__ == '__main__':
     main()

Removed: zorg/trunk/lnt/lnt/import/NightlytestReader.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/NightlytestReader.py?rev=99163&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/import/NightlytestReader.py (original)
+++ zorg/trunk/lnt/lnt/import/NightlytestReader.py (removed)
@@ -1,249 +0,0 @@
-#!/usr/bin/env python
-
-"""
-Data converter from the llvm/utils/NewNightlyTest.pl report file format
-(*-sentdata.txt) to the LNT plist format.
-"""
-
-# FIXME: Refactor data conversion code.
-
-import re
-
-kDataKeyStart = re.compile('(.*)  =>(.*)')
-
-def loadSentData(path):
-    def parseDGResults(text):
-        results = {}
-        if 'Dejagnu skipped by user choice' in text:
-            return results
-        for ln in text.strip().split('\n'):
-            result,value = ln.split(':',1)
-            results[result] = results.get(result,[])
-            results[result].append(value)
-        return results
-
-    basename = 'nightlytest'
-
-    # Guess the format (server side or client side) based on the first
-    # character.
-    isServerSide = (open(path).read(1) == '\'')
-
-    f = open(path)
-    data = {}
-
-    current = None
-    inData = False
-    for ln in f:
-        if inData:
-            if ln == 'EOD\n':
-                inData = False
-            else:
-                data[current] += ln
-            continue
-
-        m = kDataKeyStart.match(ln)
-        if m:
-            current,value = m.groups()
-            if isServerSide:
-                assert current[0] == current[-1] == "'"
-                current = current[1:-1]
-                assert value[0] == value[1] == ' '
-                value = value[2:]
-                if value == '<<EOD':
-                    value = ''
-                    inData = True
-                else:
-                    assert value[0] == value[-2] == '"'
-                    assert value[-1] == ','
-                    value = value[1:-2]
-            data[current] = value
-        elif isServerSide:
-            assert ln == ',\n'
-        else:
-            assert current is not None
-            data[current] += ln
-
-    # Things we are ignoring for now
-    data.pop('a_file_sizes')
-    data.pop('all_tests')
-    data.pop('build_data')
-    data.pop('cvs_dir_count')
-    data.pop('cvs_file_count')
-    data.pop('cvsaddedfiles')
-    data.pop('cvsmodifiedfiles')
-    data.pop('cvsremovedfiles')
-    data.pop('cvsusercommitlist')
-    data.pop('cvsuserupdatelist')
-    data.pop('dejagnutests_log')
-    data.pop('expfail_tests')
-    data.pop('lines_of_code')
-    data.pop('llcbeta_options')
-    data.pop('new_tests')
-    data.pop('o_file_sizes')
-    data.pop('passing_tests')
-    data.pop('removed_tests')
-    data.pop('target_triple')
-    data.pop('unexpfail_tests')
-    data.pop('warnings')
-    data.pop('warnings_added')
-    data.pop('warnings_removed')
-
-    starttime = data.pop('starttime').strip()
-    endtime = data.pop('endtime').strip()
-
-    nickname = data.pop('nickname').strip()
-    machine_data = data.pop('machine_data').strip()
-    buildstatus = data.pop('buildstatus').strip()
-    configtime_user = data.pop('configtime_cpu')
-    configtime_wall = data.pop('configtime_wall')
-    checkouttime_user = data.pop('cvscheckouttime_cpu')
-    checkouttime_wall = data.pop('cvscheckouttime_wall')
-    dgtime_user = data.pop('dejagnutime_cpu')
-    dgtime_wall = data.pop('dejagnutime_wall')
-    buildtime_wall = float(data.pop('buildtime_wall').strip())
-    buildtime_user = float(data.pop('buildtime_cpu').strip())
-    gcc_version = data.pop('gcc_version')
-    dejagnutests_results = data.pop('dejagnutests_results')
-    multisource = data.pop('multisource_programstable')
-    singlesource = data.pop('singlesource_programstable')
-    externals = data.pop('externalsource_programstable')
-
-    assert not data.keys()
-
-    machine = { 'Name' : nickname,
-                'Info' : { 'gcc_version' : gcc_version } }
-    for ln in machine_data.split('\n'):
-        ln = ln.strip()
-        if not ln:
-            continue
-        assert ':' in ln
-        key,value = ln.split(':',1)
-        machine['Info'][key] = value
-
-    # We definitely don't want these in the machine data.
-    if 'time' in machine['Info']:
-        machine['Info'].pop('time')
-    if 'date' in machine['Info']:
-        machine['Info'].pop('date')
-
-    run = { 'Start Time' : starttime,
-            'End Time' : endtime,
-            'Info' : { 'tag' : 'nightlytest' } }
-
-    tests = []
-
-    groupInfo = []
-
-    # llvm-test doesn't provide this
-    infoData = {}
-
-    # Summary test information
-    tests.append( { 'Name' : basename + '.Summary.configtime.wall',
-                    'Info' : infoData,
-                    'Data' : [configtime_wall] } )
-    tests.append( { 'Name' : basename + '.Summary.configtime.user',
-                    'Info' : infoData,
-                    'Data' : [configtime_user] } )
-    tests.append( { 'Name' : basename + '.Summary.checkouttime.wall',
-                    'Info' : infoData,
-                    'Data' : [checkouttime_wall] } )
-    tests.append( { 'Name' : basename + '.Summary.checkouttime.user',
-                    'Info' : infoData,
-                    'Data' : [checkouttime_user] } )
-    tests.append( { 'Name' : basename + '.Summary.buildtime.wall',
-                    'Info' : infoData,
-                    'Data' : [buildtime_wall] } )
-    tests.append( { 'Name' : basename + '.Summary.buildtime.user',
-                    'Info' : infoData,
-                    'Data' : [buildtime_user] } )
-    tests.append( { 'Name' : basename + '.Summary.dgtime.wall',
-                    'Info' : infoData,
-                    'Data' : [dgtime_wall] } )
-    tests.append( { 'Name' : basename + '.Summary.dgtime.user',
-                    'Info' : infoData,
-                    'Data' : [dgtime_user] } )
-    tests.append( { 'Name' : basename + '.Summary.buildstatus',
-                    'Info' : infoData,
-                    'Data' : [buildstatus == 'OK'] } )
-
-    # DejaGNU Info
-    results = parseDGResults(dejagnutests_results)
-    for name in ('PASS', 'FAIL', 'XPASS', 'XFAIL'):
-        tests.append( { 'Name' : basename + '.DejaGNU.' + name,
-                        'Info' : infoData,
-                        'Data' : [len(results.get(name,[]))] } )
-
-    # llvm-test results
-    groupInfo.append( { 'Name' : basename,
-                        'Primary' : 1 } )
-    for groupname,data in (('SingleSource', singlesource),
-                           ('MultiSource', multisource),
-                           ('Externals', externals)):
-        groupInfo.append( { 'Name' : basename + '.' + groupname,
-                            'Primary' : 1 } )
-        lines = data.split('\n')
-        header = lines[0].strip().split(',')
-        for ln in lines[1:]:
-            ln = ln.strip()
-            if not ln:
-                continue
-            entry = dict([(k,v.strip())
-                           for k,v in zip(header, ln.split(','))])
-            testname = basename + '.%s/%s' % (groupname,
-                                              entry['Program'].replace('.','_'))
-            groupInfo.append( { 'Name' : testname,
-                                'Primary' : 1 } )
-
-            for name,key,tname in (('gcc.compile', 'GCCAS', 'time'),
-                                   ('bc.compile', 'Bytecode', 'size'),
-                                   ('llc.compile', 'LLC compile', 'time'),
-                                   ('llc-beta.compile', 'LLC-BETA compile', 'time'),
-                                   ('jit.compile', 'JIT codegen', 'time'),
-                                   ('gcc.exec', 'GCC', 'time'),
-                                   ('cbe.exec', 'CBE', 'time'),
-                                   ('llc.exec', 'LLC', 'time'),
-                                   ('llc-beta.exec', 'LLC-BETA', 'time'),
-                                   ('jit.exec', 'JIT', 'time'),
-                             ):
-                time = entry[key]
-                if time == '*':
-                    tests.append( { 'Name' : testname + '.%s.success' % name,
-                                    'Info' : infoData,
-                                    'Data' : [0] } )
-                else:
-                    tests.append( { 'Name' : testname + '.%s.success' % name,
-                                    'Info' : infoData,
-                                    'Data' : [1] } )
-                    tests.append( { 'Name' : testname + '.%s.%s' % (name, tname),
-                                    'Info' : infoData,
-                                    'Data' : [float(time)] } )
-        pass
-
-    return { 'Machine' : machine,
-             'Run' : run,
-             'Tests' : tests,
-             'Group Info' : groupInfo }
-
-def convertNTData(inputPath, outputPath):
-    """convertNTData - Convert a nightlytest "sentdata.txt" file into a zorg
-    plist file."""
-    import plistlib
-
-    data = loadSentData(inputPath)
-    plistlib.writePlist(data, outputPath)
-
-def main():
-    global opts
-    from optparse import OptionParser
-    parser = OptionParser("usage: %prog file output")
-    opts,args = parser.parse_args()
-
-    if len(args) != 2:
-        parser.error("incorrect number of argments")
-
-    file,output = args
-
-    convertNTData(file, output)
-
-if __name__=='__main__':
-    main()

Modified: zorg/trunk/lnt/lnt/lnttool/__init__.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/__init__.py?rev=99164&r1=99163&r2=99164&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/lnttool/__init__.py (original)
+++ zorg/trunk/lnt/lnt/lnttool/__init__.py Mon Mar 22 02:18:29 2010
@@ -45,6 +45,7 @@
                False, None, 1, opts.threaded, opts.processes)
 
 from create import action_create
+from convert import action_convert
 
 commands = dict((name[7:], f) for name,f in locals().items()
                 if name.startswith('action_'))

Added: zorg/trunk/lnt/lnt/lnttool/convert.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/convert.py?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/lnttool/convert.py (added)
+++ zorg/trunk/lnt/lnt/lnttool/convert.py Mon Mar 22 02:18:29 2010
@@ -0,0 +1,63 @@
+import os
+import sys
+
+def convert_data(input, output, inFormat, outFormat):
+    from lnt import formats
+
+    out = formats.get_format(outFormat)
+    if out is None or not out.get('write'):
+        raise SystemExit("unknown output format: %r" % outFormat)
+
+    data = formats.read_any(input, inFormat)
+
+    out['write'](data, output)
+    output.flush()
+
+def action_convert(name, args):
+    """convert between input formats"""
+
+    from optparse import OptionParser, OptionGroup
+    from lnt import formats
+    global parser
+    parser = OptionParser("%%prog %s [options] [<input>, [<output>]]" % name)
+    parser.add_option("", "--from", dest="inputFormat", metavar="NAME",
+                      help="input format name [%default]", default='<auto>',
+                      choices=formats.format_names + ['<auto>'])
+    parser.add_option("", "--to", dest="outputFormat", metavar="NAME",
+                      help="output format name [%default]", default='plist',
+                      choices=formats.format_names + ['<auto>'])
+    (opts, args) = parser.parse_args(args)
+
+    input = output = '-'
+    if len(args) == 0:
+        pass
+    elif len(args) == 1:
+        input, = args
+    elif len(args) == 2:
+        input,output = args
+    else:
+        parser.error("invalid number of arguments")
+
+    if input == '-':
+        # Guarantee that we can seek.
+        import StringIO
+        data = sys.stdin.read()
+        inf = StringIO.StringIO(data)
+    else:
+        inf = input
+
+    if output == '-':
+        outf = sys.stdout
+    else:
+        outf = open(output, 'wb')
+
+    try:
+        try:
+            convert_data(inf, outf, opts.inputFormat, opts.outputFormat)
+        finally:
+            if outf != sys.stdout:
+                outf.close()
+    except:
+        if outf != sys.stdout:
+            os.remove(output)
+        raise

Added: zorg/trunk/lnt/tests/Formats/Inputs/test.json
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/Formats/Inputs/test.json?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/tests/Formats/Inputs/test.json (added)
+++ zorg/trunk/lnt/tests/Formats/Inputs/test.json Mon Mar 22 02:18:29 2010
@@ -0,0 +1 @@
+{ "a" : 1 }

Added: zorg/trunk/lnt/tests/Formats/Inputs/test.nightlytest
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/Formats/Inputs/test.nightlytest?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/tests/Formats/Inputs/test.nightlytest (added)
+++ zorg/trunk/lnt/tests/Formats/Inputs/test.nightlytest Mon Mar 22 02:18:29 2010
@@ -0,0 +1,58 @@
+cvsaddedfiles  => 
+cvsuserupdatelist  => 
+all_tests  => TEST-PASS: compile /MultiSource/Applications/aha/aha
+TEST-PASS: compile /MultiSource/Applications/aha/aha
+
+llcbeta_options  => 
+
+cvsusercommitlist  => 
+warnings_added  => 
+new_tests  => 
+starttime  => 2010-03-20 05:23:59
+
+dejagnutests_log  => 
+buildstatus  => OK
+multisource_programstable  => Program,GCCAS,Bytecode,LLC compile,LLC-BETA compile,JIT codegen,GCC,CBE,LLC,LLC-BETA,JIT,GCC/CBE,GCC/LLC,GCC/LLC-BETA,LLC/LLC-BETA
+Applications/aha/aha,0.0326,9696,0.0448,*,*, 2.7800,*, 2.1700,*,*,n/a,1.28,n/a,n/a
+
+warnings  => 
+dejagnutime_cpu  => 0.0
+cvscheckouttime_wall  => 22.86
+cvsremovedfiles  => 
+cvscheckouttime_cpu  => 0
+unexpfail_tests  => 
+gcc_version  => i686-apple-darwin10-gcc-4.2.1 (GCC) 4.2.1 (Apple Inc. build 5659)
+buildtime_wall  => 229.26
+build_data  =>
+
+buildtime_cpu  => 1458.92
+removed_tests  => 
+dejagnutime_wall  => 0.0
+o_file_sizes  => 
+configtime_cpu  => 20.04
+target_triple  => x86_64-apple-darwin10
+warnings_removed  => 
+cvs_file_count  => 0
+machine_data  => uname: Darwin lordcrumb.apple.com 10.2.0 Darwin Kernel Version 10.2.0: Tue Nov  3 10:37:10 PST 2009; root:xnu-1486.2.11~1/RELEASE_I386 i386
+hardware: i386
+os: Darwin 10.2.0
+name: lordcrumb.apple.com
+date: 2010-03-20
+time: 06:41:16
+
+cvsmodifiedfiles  => 
+a_file_sizes  => 
+externalsource_programstable  =>
+
+dejagnutests_results  => Dejagnu skipped by user choice.
+configtime_wall  => 21.38
+endtime  => 2010-03-20 06:41:16
+
+nickname  => lc-01-clang-i386-apple-darwin10
+singlesource_programstable  =>
+
+passing_tests  => 
+expfail_tests  => 
+lines_of_code  => 
+cvs_dir_count  => 0
+

Added: zorg/trunk/lnt/tests/Formats/Inputs/test.plist
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/Formats/Inputs/test.plist?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/tests/Formats/Inputs/test.plist (added)
+++ zorg/trunk/lnt/tests/Formats/Inputs/test.plist Mon Mar 22 02:18:29 2010
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE plist PUBLIC "-//Apple Computer//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
+<plist version="1.0">
+<dict>
+	<key>a</key>
+	<integer>1</integer>
+</dict>
+</plist>

Added: zorg/trunk/lnt/tests/Formats/json.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/Formats/json.py?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/tests/Formats/json.py (added)
+++ zorg/trunk/lnt/tests/Formats/json.py Mon Mar 22 02:18:29 2010
@@ -0,0 +1,4 @@
+# RUN: lnt convert --to=json %S/Inputs/test.json | FileCheck %s
+# RUN: lnt convert --to=json < %S/Inputs/test.json | FileCheck %s
+
+# CHECK: {"a": 1}

Added: zorg/trunk/lnt/tests/Formats/nightlytest.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/Formats/nightlytest.py?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/tests/Formats/nightlytest.py (added)
+++ zorg/trunk/lnt/tests/Formats/nightlytest.py Mon Mar 22 02:18:29 2010
@@ -0,0 +1,6 @@
+# RUN: lnt convert --to=json %S/Inputs/test.nightlytest %t
+# RUN: FileCheck %s < %t
+
+# We are just checking the conversion, not validating the format.
+# CHECK: "Machine":
+# CHECK: "Tests": [

Added: zorg/trunk/lnt/tests/Formats/plist.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/Formats/plist.py?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/tests/Formats/plist.py (added)
+++ zorg/trunk/lnt/tests/Formats/plist.py Mon Mar 22 02:18:29 2010
@@ -0,0 +1,4 @@
+# RUN: lnt convert --to=json %S/Inputs/test.plist | FileCheck %s
+# RUN: lnt convert --to=json < %S/Inputs/test.plist | FileCheck %s
+
+# CHECK: {"a": 1}




From daniel at zuster.org  Mon Mar 22 02:18:34 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 07:18:34 -0000
Subject: [llvm-commits] [zorg] r99165 - in /zorg/trunk/lnt/lnt:
 import/ImportData import/NTAuxSubmit import/NTEmailReport.py
 import/ServerUtil.py import/SubmitData lnttool/__init__.py util/
 util/NTAuxSubmit util/NTEmailReport.py util/ServerUtil.py
Message-ID: <20100322071835.049CE2A6C12D@llvm.org>

Author: ddunbar
Date: Mon Mar 22 02:18:34 2010
New Revision: 99165

URL: http://llvm.org/viewvc/llvm-project?rev=99165&view=rev
Log:
LNT: Move some import tools to lnt.util, and move SubmitData to 'lnt submit'.

Added:
    zorg/trunk/lnt/lnt/util/
    zorg/trunk/lnt/lnt/util/NTAuxSubmit
      - copied, changed from r99164, zorg/trunk/lnt/lnt/import/NTAuxSubmit
    zorg/trunk/lnt/lnt/util/NTEmailReport.py
      - copied, changed from r99164, zorg/trunk/lnt/lnt/import/NTEmailReport.py
    zorg/trunk/lnt/lnt/util/ServerUtil.py
      - copied, changed from r99164, zorg/trunk/lnt/lnt/import/ServerUtil.py
Removed:
    zorg/trunk/lnt/lnt/import/NTAuxSubmit
    zorg/trunk/lnt/lnt/import/NTEmailReport.py
    zorg/trunk/lnt/lnt/import/ServerUtil.py
    zorg/trunk/lnt/lnt/import/SubmitData
Modified:
    zorg/trunk/lnt/lnt/import/ImportData
    zorg/trunk/lnt/lnt/lnttool/__init__.py

Modified: zorg/trunk/lnt/lnt/import/ImportData
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/ImportData?rev=99165&r1=99164&r2=99165&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/import/ImportData (original)
+++ zorg/trunk/lnt/lnt/import/ImportData Mon Mar 22 02:18:34 2010
@@ -13,6 +13,7 @@
 
 from lnt import formats, viewer
 from lnt.viewer import Util, PerfDB
+from lnt.util import NTEmailReport
 
 def main():
     global opts
@@ -99,7 +100,6 @@
                 print "    INFO   : %r = %r" % (ri.key, ri.value)
 
         if opts.emailOnImport and (success or opts.alwaysEmail):
-            import NTEmailReport
             print "\nMAILING RESULTS TO: %r\n" % opts.emailReportTo
             NTEmailReport.emailReport(db, run,
                                       opts.emailReportURL,

Removed: zorg/trunk/lnt/lnt/import/NTAuxSubmit
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/NTAuxSubmit?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/import/NTAuxSubmit (original)
+++ zorg/trunk/lnt/lnt/import/NTAuxSubmit (removed)
@@ -1,56 +0,0 @@
-#!/usr/bin/env python
-
-"""
-Command line tool for submitting to a LNT server.
-
-This script is explicitly designed to work with llvm/utils/NewNightlyTest.pl's
--submit-aux argument. It simply uploads the data to the server, and assumes the
-server will sort out any input conversion issues.
-
-This script should be totally free-standing; it is designed so users can svn
-export it directly from the LLVM repository as part of their submission scripts.
-"""
-
-import plistlib
-import sys
-import urllib
-import urllib2
-
-def main():
-    global opts
-    from optparse import OptionParser
-    parser = OptionParser("usage: %prog {nightlytest sentdata.txt}*")
-    parser.add_option("", "--commit", dest="commit", type=int,
-                      default=True)
-
-    # FIXME: It would be nice to support an easy mechanism for localized
-    # instances of the LNT infrastructure to default to the correct server for
-    # their installation.
-    parser.add_option("", "--server", dest="serverUrl", type=str,
-                      default="http://llvm.org/perf/db_default/submitRun")
-
-    opts,args = parser.parse_args()
-
-    if not args:
-        parser.error("no input files")
-
-    for inputFile in args:
-        print '%s: note: submitting %s' % (sys.argv[0], inputFile)
-
-        # Encode the form data.
-        f = open(inputFile, 'rb')
-        values = { 'input_data' : f.read(),
-                   'commit' : ("0","1")[not not commit] }
-        f.close()
-        data = urllib.urlencode(values)
-
-        # Send it off.
-        response = urllib2.urlopen(urllib2.Request(url, data))
-        the_page = response.read()
-
-        # FIXME: Parse results and return proper error code.
-        print the_page
-
-
-if __name__ == '__main__':
-    main()

Removed: zorg/trunk/lnt/lnt/import/NTEmailReport.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/NTEmailReport.py?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/import/NTEmailReport.py (original)
+++ zorg/trunk/lnt/lnt/import/NTEmailReport.py (removed)
@@ -1,235 +0,0 @@
-#!/usr/bin/python
-
-"""
-Command line tool for sending an LNT email report.
-"""
-
-# FIXME: Roll into lnttool or just kill?
-
-import os
-import smtplib
-import sys
-
-import StringIO
-from lnt import viewer
-from lnt.viewer import PerfDB
-from lnt.viewer.NTUtil import *
-
-def main():
-    global opts
-    from optparse import OptionParser
-    parser = OptionParser("usage: %prog database run-id baseurl sendmail-host from to")
-    opts,args = parser.parse_args()
-
-    if len(args) != 6:
-        parser.error("incorrect number of argments")
-
-    dbpath,runID,baseurl,host,from_,to = args
-
-    db = PerfDB.PerfDB(dbpath)
-    run = db.getRun(int(runID))
-
-    emailReport(db, run, baseurl, host, from_, to)
-
-def emailReport(db, run, baseurl, host, from_, to, was_added=True,
-                will_commit=True):
-    import email.mime.text
-
-    subject, report = getReport(db, run, baseurl, was_added, will_commit)
-
-    msg = email.mime.text.MIMEText(report)
-    msg['Subject'] = subject
-    msg['From'] = from_
-    msg['To'] = to
-
-    s = smtplib.SMTP(host)
-    s.sendmail(from_, [to], msg.as_string())
-    s.quit()
-
-def findPreceedingRun(query, run):
-    """findPreceedingRun - Find the most recent run in query which
-    preceeds run."""
-    best = None
-    for r in query:
-        # Restrict to nightlytest runs.
-        if 'tag' in r.info and r.info['tag'].value != 'nightlytest':
-            continue
-
-        # Select most recent run prior to the one we are reporting on.
-        if (r.start_time < run.start_time and
-            (best is None or r.start_time > best.start_time)):
-            best = r
-    return best
-
-def getReport(db, run, baseurl, was_added, will_commit):
-    report = StringIO.StringIO()
-
-    machine = run.machine
-    compareTo = None
-
-    # Find comparison run.
-    # FIXME: Share this code with similar stuff in the viewer.
-    # FIXME: Scalability.
-    compareCrossesMachine = False
-    compareTo = findPreceedingRun(db.runs(machine=machine), run)
-
-    # If we didn't find a comparison run against this machine, look
-    # for a comparison run against the same machine name, and warn the
-    # user we are crosses machines.
-    if compareTo is None:
-        compareCrossesMachine = True
-        q = db.session.query(PerfDB.Run).join(PerfDB.Machine)
-        q = q.filter_by(name=machine.name)
-        compareTo = findPreceedingRun(q, run)
-
-    summary = RunSummary()
-    summary.addRun(db, run)
-    if compareTo:
-        summary.addRun(db, compareTo)
-
-    def getTestValue(run, testname, keyname):
-        fullname = 'nightlytest.' + testname + '.' + keyname
-        t = summary.testMap.get(str(fullname))
-        if t is None:
-            return None
-        samples = summary.getRunSamples(run).get(t.id)
-        if not samples:
-            return None
-        return samples[0]
-    def getTestSuccess(run, testname, keyname):
-        res = getTestValue(run, testname, keyname + '.success')
-        if res is None:
-            return res
-        return not not res
-
-    newPasses = Util.multidict()
-    newFailures = Util.multidict()
-    addedTests = Util.multidict()
-    removedTests = Util.multidict()
-    allTests = set()
-    allFailures = set()
-    allFailuresByKey = Util.multidict()
-    for keyname,title in kTSKeys.items():
-        for testname in summary.testNames:
-            curResult = getTestSuccess(run, testname, keyname)
-            prevResult = getTestSuccess(compareTo, testname, keyname)
-
-            if curResult is not None:
-                allTests.add((testname,keyname))
-                if curResult is False:
-                    allFailures.add((testname,keyname))
-                    allFailuresByKey[title] = testname
-
-            # Count as new pass if it passed, and previous result was failure.
-            if curResult and prevResult == False:
-                newPasses[testname] = title
-
-            # Count as new failure if it failed, and previous result was not
-            # failure.
-            if curResult == False and prevResult != False:
-                newFailures[testname] = title
-
-            if curResult is not None and prevResult is None:
-                addedTests[testname] = title
-            if curResult is None and prevResult is not None:
-                removedTests[testname] = title
-
-    changes = Util.multidict()
-    for i,(name,key) in enumerate(kComparisonKinds):
-        if not key:
-            # FIXME: File Size
-            continue
-
-        for testname in summary.testNames:
-            curValue = getTestValue(run, testname, key)
-            prevValue = getTestValue(compareTo, testname, key)
-
-            # Skip missing tests.
-            if curValue is None or prevValue is None:
-                continue
-
-            pct = Util.safediv(curValue, prevValue)
-            if pct is None:
-                continue
-            pctDelta = pct - 1.
-            if abs(pctDelta) < .05:
-                continue
-            if min(prevValue, curValue) <= .2:
-                continue
-
-            changes[name] = (testname, curValue, prevValue, pctDelta)
-
-    if will_commit:
-        if not was_added:
-            print >>report, ("*** NOTE ***: This was a duplicate submission, "
-                             "and did not modify the database.\n")
-    else:
-        if was_added:
-            print >>report, ("*** NOTE ***: This is a test submission, "
-                             "it will not be committed to the database.\n")
-        else:
-            print >>report, ("*** NOTE ***: This is a test submission, "
-                             "and was a duplicate of an existing run.\n")
-
-    if baseurl[-1] == '/':
-        baseurl = baseurl[:-1]
-    print >>report, """%s/%d/""" % (baseurl, run.id)
-    print >>report, """Name: %s""" % (machine.info['name'].value,)
-    print >>report, """Nickname: %s:%d""" % (machine.name, machine.number)
-    print >>report
-    print >>report, """Run: %d, Start Time: %s, End Time: %s""" % (
-        run.id, run.start_time, run.end_time)
-    if compareTo:
-        print >>report, """Comparing To: %d, Start Time: %s, End Time: %s""" % (
-            compareTo.id, compareTo.start_time, compareTo.end_time)
-        if compareCrossesMachine:
-            print >>report, """*** WARNING ***:""",
-            print >>report, """comparison is against a different machine""",
-            print >>report, """(%s:%d)""" % (compareTo.machine.name,
-                                             compareTo.machine.number)
-    else:
-        print >>report, """Comparing To: (none)"""
-    print >>report
-
-    print >>report, """--- Changes Summary ---"""
-    for title,elts in (('New Test Passes', newPasses),
-                       ('New Test Failures', newFailures),
-                       ('Added Tests', addedTests),
-                       ('Removed Tests', removedTests)):
-        print >>report, """%s: %d""" % (title,
-                                        sum([len(values)
-                                             for key,values in elts.items()]))
-    numSignificantChanges = sum([len(changelist)
-                                 for name,changelist in changes.items()])
-    print >>report, """Significant Changes: %d""" % (numSignificantChanges,)
-    print >>report
-    print >>report, """--- Tests Summary ---"""
-    print >>report, """Total Tests: %d""" % (len(allTests),)
-    print >>report, """Total Test Failures: %d""" % (len(allFailures),)
-    print >>report
-    print >>report, """Total Test Failures By Type:"""
-    for name,items in Util.sorted(allFailuresByKey.items()):
-        print >>report, """  %s: %d""" % (name, len(set(items)))
-
-    print >>report
-    print >>report, """--- Changes Detail ---"""
-    for title,elts in (('New Test Passes', newPasses),
-                       ('New Test Failures', newFailures),
-                       ('Added Tests', addedTests),
-                       ('Removed Tests', removedTests)):
-        print >>report, """%s:""" % (title,)
-        print >>report, "".join("%s [%s]\n" % (key, ", ".join(values))
-                                for key,values in Util.sorted(elts.items()))
-    print >>report, """Significant Changes in Test Results:"""
-    for name,changelist in changes.items():
-        print >>report, """%s:""" % name
-        for name,curValue,prevValue,delta in Util.sorted(changelist):
-            print >>report, """ %s: %.2f%% (%.4f => %.4f)""" % (
-                name, delta*100, prevValue, curValue)
-
-    # FIXME: Where is the old mailer getting the arch from?
-    subject = """%s nightly tester results""" % machine.name
-    return subject,report.getvalue()
-
-if __name__ == '__main__':
-    main()

Removed: zorg/trunk/lnt/lnt/import/ServerUtil.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/ServerUtil.py?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/import/ServerUtil.py (original)
+++ zorg/trunk/lnt/lnt/import/ServerUtil.py (removed)
@@ -1,20 +0,0 @@
-"""
-Utility for submitting files to a web server over HTTP.
-"""
-
-import plistlib
-import urllib
-import urllib2
-
-def submitFiles(url, files, commit):
-    for file in files:
-        f = open(file, 'rb')
-        values = { 'input_data' : f.read(),
-                   'commit' : ("0","1")[not not commit] }
-        f.close()
-
-        data = urllib.urlencode(values)
-        response = urllib2.urlopen(urllib2.Request(url, data))
-        the_page = response.read()
-
-        print the_page

Removed: zorg/trunk/lnt/lnt/import/SubmitData
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/SubmitData?rev=99164&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/import/SubmitData (original)
+++ zorg/trunk/lnt/lnt/import/SubmitData (removed)
@@ -1,25 +0,0 @@
-#!/usr/bin/python
-
-"""
-Command line utility for submitting an LNT plist file to a LNT server.
-"""
-
-# FIXME: Roll into lnttool and kill. See also refactor conversion code.
-
-import ServerUtil
-
-def main():
-    global opts
-    from optparse import OptionParser
-    parser = OptionParser("usage: %prog serverUrl files+")
-    parser.add_option("", "--commit", dest="commit", type=int,
-                      default=False)
-    opts,args = parser.parse_args()
-
-    if len(args) < 2:
-        parser.error("incorrect number of argments")
-
-    ServerUtil.submitFiles(args[0], args[1:], opts.commit)
-
-if __name__ == '__main__':
-    main()

Modified: zorg/trunk/lnt/lnt/lnttool/__init__.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/__init__.py?rev=99165&r1=99164&r2=99165&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/lnttool/__init__.py (original)
+++ zorg/trunk/lnt/lnt/lnttool/__init__.py Mon Mar 22 02:18:34 2010
@@ -47,6 +47,23 @@
 from create import action_create
 from convert import action_convert
 
+def action_submit(name, args):
+    """submit a test report to the server."""
+
+    from optparse import OptionParser, OptionGroup
+    parser = OptionParser("%%prog %s [options] url files+" % name)
+    parser.add_option("", "--commit", dest="commit", type=int,
+                      default=False)
+
+    (opts, args) = parser.parse_args(args)
+    if len(args) < 2:
+        parser.error("incorrect number of argments")
+
+    from lnt.util import ServerUtil
+    ServerUtil.submitFiles(args[0], args[1:], opts.commit)
+
+###
+
 commands = dict((name[7:], f) for name,f in locals().items()
                 if name.startswith('action_'))
 

Copied: zorg/trunk/lnt/lnt/util/NTAuxSubmit (from r99164, zorg/trunk/lnt/lnt/import/NTAuxSubmit)
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/NTAuxSubmit?p2=zorg/trunk/lnt/lnt/util/NTAuxSubmit&p1=zorg/trunk/lnt/lnt/import/NTAuxSubmit&r1=99164&r2=99165&rev=99165&view=diff
==============================================================================
    (empty)

Copied: zorg/trunk/lnt/lnt/util/NTEmailReport.py (from r99164, zorg/trunk/lnt/lnt/import/NTEmailReport.py)
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/NTEmailReport.py?p2=zorg/trunk/lnt/lnt/util/NTEmailReport.py&p1=zorg/trunk/lnt/lnt/import/NTEmailReport.py&r1=99164&r2=99165&rev=99165&view=diff
==============================================================================
    (empty)

Copied: zorg/trunk/lnt/lnt/util/ServerUtil.py (from r99164, zorg/trunk/lnt/lnt/import/ServerUtil.py)
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/ServerUtil.py?p2=zorg/trunk/lnt/lnt/util/ServerUtil.py&p1=zorg/trunk/lnt/lnt/import/ServerUtil.py&r1=99164&r2=99165&rev=99165&view=diff
==============================================================================
    (empty)




From daniel at zuster.org  Mon Mar 22 02:18:48 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 07:18:48 -0000
Subject: [llvm-commits] [zorg] r99168 - in /zorg/trunk/lnt:
 lnt/viewer/Config.py lnt/viewer/app.py setup.py
Message-ID: <20100322071848.8AE6A2A6C12D@llvm.org>

Author: ddunbar
Date: Mon Mar 22 02:18:48 2010
New Revision: 99168

URL: http://llvm.org/viewvc/llvm-project?rev=99168&view=rev
Log:
LNT: Kill off zorgDir config variable (the last of the sys.path hacks), and finish off setup.py for real installs (install resource files).

Modified:
    zorg/trunk/lnt/lnt/viewer/Config.py
    zorg/trunk/lnt/lnt/viewer/app.py
    zorg/trunk/lnt/setup.py

Modified: zorg/trunk/lnt/lnt/viewer/Config.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/Config.py?rev=99168&r1=99167&r2=99168&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/Config.py (original)
+++ zorg/trunk/lnt/lnt/viewer/Config.py Mon Mar 22 02:18:48 2010
@@ -44,24 +44,21 @@
             ntEmailEnabled = False
             ntEmailHost = ntEmailFrom = ntEmailTo = ""
 
-        zorgDir = os.path.join(baseDir, data['zorg'])
-
         dbDir = data.get('db_dir', '.')
         dbDirPath = os.path.join(baseDir, dbDir)
 
         # FIXME: Remove this default.
         tempDir = data.get('tmp_dir', 'viewer/resources/graphs')
 
-        return Config(data.get('name', 'LNT'), zorgDir, data['zorgURL'],
+        return Config(data.get('name', 'LNT'), data['zorgURL'],
                       dbDir, os.path.join(baseDir, tempDir),
                       dict([(k,DBInfo.fromData(dbDirPath, v))
                                      for k,v in data['databases'].items()]),
                       ntEmailEnabled, ntEmailHost, ntEmailFrom, ntEmailTo)
 
-    def __init__(self, name, zorgDir, zorgURL, dbDir, tempDir, databases,
+    def __init__(self, name, zorgURL, dbDir, tempDir, databases,
                  ntEmailEnabled, ntEmailHost, ntEmailFrom, ntEmailTo):
         self.name = name
-        self.zorgDir = zorgDir
         self.zorgURL = zorgURL
         self.dbDir = dbDir
         self.tempDir = tempDir

Modified: zorg/trunk/lnt/lnt/viewer/app.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/app.py?rev=99168&r1=99167&r2=99168&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/app.py (original)
+++ zorg/trunk/lnt/lnt/viewer/app.py Mon Mar 22 02:18:48 2010
@@ -8,12 +8,6 @@
     configData = {}
     exec open(configPath) in configData
 
-    # Find the zorg installation dir.
-    zorgDir = os.path.join(os.path.dirname(configPath),
-                           configData.get('zorg', ''))
-    if zorgDir and zorgDir not in sys.path:
-        sys.path.append(zorgDir)
-
     # Optionally enable auto-restart.
     if configData.get('wsgi_restart', False):
         from lnt.viewer import wsgi_restart

Modified: zorg/trunk/lnt/setup.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/setup.py?rev=99168&r1=99167&r2=99168&view=diff
==============================================================================
--- zorg/trunk/lnt/setup.py (original)
+++ zorg/trunk/lnt/setup.py Mon Mar 22 02:18:48 2010
@@ -26,7 +26,23 @@
         ],
 
     zip_safe = False,
+
+    # Additional resource extensions we use.
+    #
+    # FIXME: Remove the .ptl entry once we move to Jinja. Note that the files
+    # most likely won't get byte compiled because of how permissions will be
+    # set, unless WSGI app has permissions to write to the install directory. I
+    # can't find a way to force setuptools to treat these as Python modules.
+    package_data = {'lnt.viewer': ['*.ptl',
+                                   'zview/*.ptl',
+                                   'js/*.js',
+                                   'resources/*.css',
+                                   'resources/*.js'],
+                    'lnt.util': ['NTAuxSubmit'],
+                    },
+
     packages = find_packages(),
+
     entry_points = {
         'console_scripts': [
             'lnt = lnt.lnttool:main',




From daniel at zuster.org  Mon Mar 22 02:18:40 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 07:18:40 -0000
Subject: [llvm-commits] [zorg] r99166 - in /zorg/trunk/lnt:
 lnt/import/ImportData lnt/lnttool/__init__.py lnt/lnttool/convert.py
 lnt/lnttool/import_data.py lnt/util/ImportData.py lnt/util/__init__.py
 lnt/viewer/PerfDB.py lnt/viewer/root.ptl
 tests/DB/Inputs/sample-a-small.plist tests/DB/Inputs/sample-b-small.plist
Message-ID: <20100322071840.CAAE02A6C12C@llvm.org>

Author: ddunbar
Date: Mon Mar 22 02:18:40 2010
New Revision: 99166

URL: http://llvm.org/viewvc/llvm-project?rev=99166&view=rev
Log:
LNT: Factor out lnt.util.ImportData, add 'lnt import' tool to replace ImportData script, and internalize import (instead of forking out). The server should accept any format we can auto-detect now.

Added:
    zorg/trunk/lnt/lnt/lnttool/import_data.py
    zorg/trunk/lnt/lnt/util/ImportData.py
    zorg/trunk/lnt/lnt/util/__init__.py
Removed:
    zorg/trunk/lnt/lnt/import/ImportData
Modified:
    zorg/trunk/lnt/lnt/lnttool/__init__.py
    zorg/trunk/lnt/lnt/lnttool/convert.py
    zorg/trunk/lnt/lnt/viewer/PerfDB.py
    zorg/trunk/lnt/lnt/viewer/root.ptl
    zorg/trunk/lnt/tests/DB/Inputs/sample-a-small.plist
    zorg/trunk/lnt/tests/DB/Inputs/sample-b-small.plist

Removed: zorg/trunk/lnt/lnt/import/ImportData
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/import/ImportData?rev=99165&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/import/ImportData (original)
+++ zorg/trunk/lnt/lnt/import/ImportData (removed)
@@ -1,119 +0,0 @@
-#!/usr/bin/env python
-
-"""
-Generic script for importing LNT test data into a database.
-"""
-
-# FIXME: Roll this into lnttool and kill.
-
-import os
-import plistlib
-import sys
-import time
-
-from lnt import formats, viewer
-from lnt.viewer import Util, PerfDB
-from lnt.util import NTEmailReport
-
-def main():
-    global opts
-    from optparse import OptionParser
-    parser = OptionParser("usage: %prog dbpath files+")
-    parser.add_option("", "--email-on-import", dest="emailOnImport", type=int,
-                      default=False)
-    parser.add_option("", "--email-base-url", dest="emailReportURL", type=str,
-                      default=None)
-    parser.add_option("", "--email-host", dest="emailReportHost", type=str,
-                      default=None)
-    parser.add_option("", "--email-from", dest="emailReportFrom", type=str,
-                      default=None)
-    parser.add_option("", "--email-to", dest="emailReportTo", type=str,
-                      default=None)
-    parser.add_option("", "--format", dest="format",
-                      choices=formats.format_names + ['<auto>'],
-                      default='<auto>')
-    parser.add_option("", "--commit", dest="commit", type=int,
-                      default=True)
-    parser.add_option("", "--show-sql", dest="showSQL", action="store_true",
-                      default=False)
-    parser.add_option("", "--show-sample-count", dest="showSampleCount",
-                      action="store_true", default=False)
-    parser.add_option("", "--always-email", dest="alwaysEmail",
-                      action="store_true", default=False)
-    opts,args = parser.parse_args()
-
-    if len(args) < 2:
-        parser.error("incorrect number of argments")
-
-    dbpath = args[0]
-
-    startTime = time.time()
-    db = PerfDB.PerfDB(dbpath, echo=opts.showSQL)
-    importFiles(db, args[1:])
-    if opts.commit:
-        print 'COMMITTING RESULT:',
-        db.commit()
-        print 'DONE'
-    else:
-        print 'DISCARDING RESULT:',
-        db.rollback()
-        print 'DONE'
-    print 'TOTAL IMPORT TIME: %.2fs' % (time.time() - startTime,)
-
-def importFiles(db, files):
-    def consumer(file):
-        try:
-            return formats.read_any(file, opts.format)
-        except KeyboardInterrupt:
-            raise
-        except:
-            print 'ERROR: %r: import failed' % file
-            import traceback
-            traceback.print_exc()
-            return None
-
-    numMachines = db.getNumMachines()
-    numRuns = db.getNumRuns()
-    numTests = db.getNumTests()
-
-    # If the database gets fragmented, count(*) in SQLite can get really slow!?!
-    if opts.showSampleCount:
-        numSamples = db.getNumSamples()
-
-    for file in files:
-        print 'IMPORT: %s' % file
-        startTime = time.time()
-        data = consumer(file)
-        print '  LOAD TIME: %.2fs' % (time.time() - startTime,)
-        if data is None:
-            continue
-
-        startTime = time.time()
-        success,(machine,run) = PerfDB.importDataFromDict(db, data)
-        print '  IMPORT TIME: %.2fs' % (time.time() - startTime,)
-        if not success:
-            print "  IGNORING DUPLICATE RUN"
-            print "    MACHINE: %d" % (run.machine_id, )
-            print "    START  : %s" % (run.start_time, )
-            print "    END    : %s" % (run.end_time, )
-            for ri in run.info.values():
-                print "    INFO   : %r = %r" % (ri.key, ri.value)
-
-        if opts.emailOnImport and (success or opts.alwaysEmail):
-            print "\nMAILING RESULTS TO: %r\n" % opts.emailReportTo
-            NTEmailReport.emailReport(db, run,
-                                      opts.emailReportURL,
-                                      opts.emailReportHost,
-                                      opts.emailReportFrom,
-                                      opts.emailReportTo,
-                                      success,
-                                      opts.commit)
-
-    print "ADDED: %d machines" % (db.getNumMachines() - numMachines,)
-    print "ADDED: %d runs" % (db.getNumRuns() - numRuns,)
-    print "ADDED: %d tests" % (db.getNumTests() - numTests,)
-    if opts.showSampleCount:
-        print "ADDED: %d samples" % (db.getNumSamples() - numSamples)
-
-if __name__ == '__main__':
-    main()

Modified: zorg/trunk/lnt/lnt/lnttool/__init__.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/__init__.py?rev=99166&r1=99165&r2=99166&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/lnttool/__init__.py (original)
+++ zorg/trunk/lnt/lnt/lnttool/__init__.py Mon Mar 22 02:18:40 2010
@@ -46,6 +46,7 @@
 
 from create import action_create
 from convert import action_convert
+from import_data import action_import
 
 def action_submit(name, args):
     """submit a test report to the server."""
@@ -81,6 +82,9 @@
     import sys
 
     if len(sys.argv) < 2 or sys.argv[1] not in commands:
+        if len(sys.argv) >= 2:
+            print >>sys.sterr,"error: invalid command %r\n" % sys.argv[1]
+
         usage()
 
     cmd = sys.argv[1]

Modified: zorg/trunk/lnt/lnt/lnttool/convert.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/convert.py?rev=99166&r1=99165&r2=99166&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/lnttool/convert.py (original)
+++ zorg/trunk/lnt/lnt/lnttool/convert.py Mon Mar 22 02:18:40 2010
@@ -18,7 +18,6 @@
 
     from optparse import OptionParser, OptionGroup
     from lnt import formats
-    global parser
     parser = OptionParser("%%prog %s [options] [<input>, [<output>]]" % name)
     parser.add_option("", "--from", dest="inputFormat", metavar="NAME",
                       help="input format name [%default]", default='<auto>',

Added: zorg/trunk/lnt/lnt/lnttool/import_data.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/import_data.py?rev=99166&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/lnttool/import_data.py (added)
+++ zorg/trunk/lnt/lnt/lnttool/import_data.py Mon Mar 22 02:18:40 2010
@@ -0,0 +1,52 @@
+import os, sys, time
+
+from lnt import formats
+from lnt.viewer import Config, PerfDB
+from lnt.util import ImportData
+
+def action_import(name, args):
+    """import test data into a database"""
+
+    from optparse import OptionParser, OptionGroup
+
+    parser = OptionParser("%%prog %s [options] <path|config-file> file+" %name)
+    parser.add_option("", "--database", dest="database", default="default",
+                      help="database to write to [%default]")
+    parser.add_option("", "--format", dest="format",
+                      choices=formats.format_names + ['<auto>'],
+                      default='<auto>')
+    parser.add_option("", "--commit", dest="commit", type=int,
+                      default=False)
+    parser.add_option("", "--show-sql", dest="showSQL", action="store_true",
+                      default=False)
+    parser.add_option("", "--show-sample-count", dest="showSampleCount",
+                      action="store_true", default=False)
+    (opts, args) = parser.parse_args(args)
+
+    if len(args) < 2:
+        parser.error("invalid number of arguments")
+
+    config = args.pop(0)
+
+    # Accept paths to config files, or to directories containing 'lnt.cfg'.
+    if os.path.isdir(config):
+        tmp = os.path.join(config, 'lnt.cfg')
+        if os.path.exists(tmp):
+            config = tmp
+
+    # Load the config file.
+    config_data = {}
+    exec open(config) in config_data
+    config = Config.Config.fromData(config, config_data)
+
+    # Get the database entry to use.
+    db_entry = config.databases.get(opts.database)
+    if db_entry is None:
+        parser.error("invalid database name")
+
+    # Load the database.
+    db = PerfDB.PerfDB(db_entry.path, echo=opts.showSQL)
+    for file in args:
+        success, run = ImportData.import_and_report(
+            config, opts.database, db, file, sys.stdout,
+            opts.format, opts.commit, opts.showSampleCount)

Added: zorg/trunk/lnt/lnt/util/ImportData.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/ImportData.py?rev=99166&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/util/ImportData.py (added)
+++ zorg/trunk/lnt/lnt/util/ImportData.py Mon Mar 22 02:18:40 2010
@@ -0,0 +1,89 @@
+import re, time
+
+from lnt import formats
+from lnt.viewer import PerfDB
+from lnt.util import NTEmailReport
+
+def import_and_report(config, db_name, db, file, log, format, commit=False,
+                      show_sample_count=False):
+    """
+    import_file(config, db_name, db, file) -> (success, run, log)
+
+    Import a test data file into the database. On success, run is the newly
+    imported run.
+    """
+    numMachines = db.getNumMachines()
+    numRuns = db.getNumRuns()
+    numTests = db.getNumTests()
+
+    # If the database gets fragmented, count(*) in SQLite can get really slow!?!
+    if show_sample_count:
+        numSamples = db.getNumSamples()
+
+    print >>log, 'IMPORT: %s' % file
+    startTime = time.time()
+    try:
+        data = formats.read_any(file, format)
+    except:
+        print >>log, 'ERROR: %r: load failed' % file
+        return (False, None)
+    print >>log, '  LOAD TIME: %.2fs' % (time.time() - startTime,)
+
+    # Find the email address for this machine's results.
+    toAddress = None
+    if isinstance(config.ntEmailTo, str):
+        toAddress = config.ntEmailTo
+    else:
+        # Find the machine name.
+        machineName = str(data.get('Machine',{}).get('Name'))
+        for pattern,addr in config.ntEmailTo:
+            if re.match(pattern, machineName):
+                toAddress = addr
+                break
+        else:
+            print >>log,("ERROR: unable to match machine name "
+                         "for test results email address!")
+            return (False, None)
+
+    importStartTime = time.time()
+    try:
+        success,run = PerfDB.importDataFromDict(db, data)
+    except:
+        print >>log, 'ERROR: %r: import failed' % file
+        return (False, None)
+
+    print >>log, '  IMPORT TIME: %.2fs' % (time.time() - importStartTime,)
+    if not success:
+        print >>log, "  IGNORING DUPLICATE RUN"
+        print >>log, "    MACHINE: %d" % (run.machine_id, )
+        print >>log, "    START  : %s" % (run.start_time, )
+        print >>log, "    END    : %s" % (run.end_time, )
+        for ri in run.info.values():
+            print >>log, "    INFO   : %r = %r" % (ri.key, ri.value)
+
+    if config.ntEmailEnabled:
+        print >>log, "\nMAILING RESULTS TO: %r\n" % toAddress
+        NTEmailReport.emailReport(db, run,
+                                  "%s/db_%s/nightlytest/" % (config.zorgURL,
+                                                             db_name),
+                                  config.ntEmailHost, config.ntEmailFrom,
+                                  toAddress, success, commit)
+
+    print >>log, "ADDED: %d machines" % (db.getNumMachines() - numMachines,)
+    print >>log, "ADDED: %d runs" % (db.getNumRuns() - numRuns,)
+    print >>log, "ADDED: %d tests" % (db.getNumTests() - numTests,)
+    if show_sample_count:
+        print >>log, "ADDED: %d samples" % (db.getNumSamples() - numSamples)
+
+    if commit:
+        print >>log, 'COMMITTING RESULT:',
+        db.commit()
+        print >>log, 'DONE'
+    else:
+        print >>log, 'DISCARDING RESULT:',
+        db.rollback()
+        print >>log, 'DONE'
+
+    print >>log, 'TOTAL IMPORT TIME: %.2fs' % (time.time() - startTime,)
+
+    return (success, run)

Added: zorg/trunk/lnt/lnt/util/__init__.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/__init__.py?rev=99166&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/util/__init__.py (added)
+++ zorg/trunk/lnt/lnt/util/__init__.py Mon Mar 22 02:18:40 2010
@@ -0,0 +1 @@
+__all__ = []

Modified: zorg/trunk/lnt/lnt/viewer/PerfDB.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/PerfDB.py?rev=99166&r1=99165&r2=99166&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/PerfDB.py (original)
+++ zorg/trunk/lnt/lnt/viewer/PerfDB.py Mon Mar 22 02:18:40 2010
@@ -313,7 +313,7 @@
                                      runData.get('End Time',''),
                                      runData.get('Info',{}).items())
     if not inserted:
-        return False,(machine,run)
+        return False,run
 
     # Batch load the set of tests instead of repeatedly querying to unique.
     #
@@ -355,8 +355,7 @@
     db.addSamples([(run.id, test_id, value)
                    for test_id,testData in zip(test_ids, testsData)
                    for value in testData['Data']])
-
-    return True,(machine,run)
+    return True,run
 
 def test_sa_db(dbpath):
     if not dbpath.startswith('mysql://'):

Modified: zorg/trunk/lnt/lnt/viewer/root.ptl
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/root.ptl?rev=99166&r1=99165&r2=99166&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/root.ptl (original)
+++ zorg/trunk/lnt/lnt/viewer/root.ptl Mon Mar 22 02:18:40 2010
@@ -285,92 +285,60 @@
             form.render()
             self.getFooter()
 
-        def process():
-            import plistlib
-            import tempfile
-
-            # Get the input data.
-            input_file = form.get_widget('file')
-            file_value = input_file.parse()
-
-            input_data = form.get_widget('input_data')
-            data_value = input_data.parse()
-
-            if ((file_value is None and data_value is None) or
-                (file_value is not None and data_value is not None)):
-                raise quixote.errors.QueryError(
-                       "Must supply either an input file or input text data")
-
-            if file_value is not None:
-                data_value = file_value.fp.read()
-                file_value.fp.close()
-
-            # Stash a copy of the submission.
-            prefix = time.strftime("data-%Y-%m-%d_%H-%M-%S")
-            fd,path = tempfile.mkstemp(prefix=prefix,
-                                       suffix='.plist',
-                                       dir=self.config.tempDir)
-            os.write(fd, data_value)
-            os.close(fd)
-
-            # Find the email address for this machine's results.
-            toAddress = None
-            if isinstance(self.config.ntEmailTo, str):
-                toAddress = self.config.ntEmailTo
-            else:
-                # Find the machine name.
-                #
-                # FIXME: This is really stupid, we shouldn't load the plist
-                # twice just for this.
-                import plistlib
-                data = plistlib.readPlist(path)
-                machineName = data.get('Machine',{}).get('Name')
-
-                for pattern,addr in self.config.ntEmailTo:
-                    if re.match(pattern, machineName):
-                        toAddress = addr
-                        break
-                else:
-                    return 1,"","error: unable to match machine name for test results email address!"
-
-            # Execute ImportData to actually do the import.
-            #
-            # FIXME: This is both broken and annoying. We want to do this
-            # internally to fix the FIXME above and keep it more readable, we
-            # want to serialize imports to keep SQLite happy and avoiding
-            # dropping submissions.
-            import lnt, subprocess
-            lnt_dir = os.path.dirname(lnt.__file__)
-            p = subprocess.Popen([os.path.join(lnt_dir, "import/ImportData"),
-                                  "--commit=%s" % form['commit'],
-                                  "--email-on-import=%s" % int(self.config.ntEmailEnabled),
-                                  "--email-base-url=%s/db_%s/nightlytest/" % (self.config.zorgURL,
-                                                                              self.dbName),
-                                  "--email-host=%s" % self.config.ntEmailHost,
-                                  "--email-from=%s" % self.config.ntEmailFrom,
-                                  "--email-to=%s" % toAddress,
-                                  "--always-email",
-                                  self.dbInfo.path,
-                                  path],
-                                 stdout=subprocess.PIPE,
-                                 stderr=subprocess.PIPE)
-            stdout,stderr = p.communicate(None)
-            res = p.wait()
-            return res,stdout,stderr
-
-        def result [plain] ():
-            res,stdout,stderr = process()
+        def result [plain] (success, run, log):
             """\
-STATUS: %s
+STATUS: %d
 
 OUTPUT:
 %s
-ERRORS:
-%s""" % (res, stdout, stderr)
+""" % (not run, log.getvalue())
 
         if not form.is_submitted() or form.has_errors():
             return render()
-        return result()
+
+        import plistlib
+        import tempfile
+        from lnt.util import ImportData
+        from StringIO import StringIO
+
+        commit = int(form.get_widget('commit').parse())
+
+        # Get the input data.
+        input_file = form.get_widget('file')
+        file_value = input_file.parse()
+
+        input_data = form.get_widget('input_data')
+        data_value = input_data.parse()
+
+        if ((file_value is None and data_value is None) or
+            (file_value is not None and data_value is not None)):
+            raise quixote.errors.QueryError(
+                   "Must supply either an input file or input text data")
+
+        if file_value is not None:
+            data_value = file_value.fp.read()
+            file_value.fp.close()
+
+        # Stash a copy of the raw submission.
+        prefix = time.strftime("data-%Y-%m-%d_%H-%M-%S")
+        fd,path = tempfile.mkstemp(prefix=prefix,
+                                   suffix='.plist',
+                                   dir=self.config.tempDir)
+        os.write(fd, data_value)
+        os.close(fd)
+
+        # Get a DB connection.
+        db = self.getDB()
+
+        # Import the data.
+        #
+        # FIXME: Gracefully handle formats failures and DOS attempts. We
+        # should at least reject overly large inputs.
+        log = StringIO()
+        success, run = ImportData.import_and_report(
+            self.config, self.dbName, db, path, log, '<auto>', commit)
+
+        return result(success, run, log)
 
     def favicon_ico(self):
         response = get_response()

Modified: zorg/trunk/lnt/tests/DB/Inputs/sample-a-small.plist
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/DB/Inputs/sample-a-small.plist?rev=99166&r1=99165&r2=99166&view=diff
==============================================================================
--- zorg/trunk/lnt/tests/DB/Inputs/sample-a-small.plist (original)
+++ zorg/trunk/lnt/tests/DB/Inputs/sample-a-small.plist Mon Mar 22 02:18:40 2010
@@ -2,1803 +2,6 @@
 <!DOCTYPE plist PUBLIC "-//Apple Computer//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
 <plist version="1.0">
 <dict>
-	<key>Group Info</key>
-	<array>
-		<dict>
-			<key>Name</key>
-			<string>nightlytest</string>
-			<key>Primary</key>
-			<integer>1</integer>
-		</dict>
-		<dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource</string>
-			<key>Primary</key>
-			<integer>1</integer>
-		</dict>
-		<dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch</string>
-			<key>Primary</key>
-			<integer>1</integer>
-		</dict>
-		<dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta</string>
-			<key>Primary</key>
-			<integer>1</integer>
-		</dict>
-		<dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body</string>
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-	</array>
 	<key>Machine</key>
 	<dict>
 		<key>Info</key>

Modified: zorg/trunk/lnt/tests/DB/Inputs/sample-b-small.plist
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/DB/Inputs/sample-b-small.plist?rev=99166&r1=99165&r2=99166&view=diff
==============================================================================
--- zorg/trunk/lnt/tests/DB/Inputs/sample-b-small.plist (original)
+++ zorg/trunk/lnt/tests/DB/Inputs/sample-b-small.plist Mon Mar 22 02:18:40 2010
@@ -2,1803 +2,6 @@
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-		<dict>
-			<key>Name</key>
-			<string>nightlytest.MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode</string>
-			<key>Primary</key>
-			<integer>1</integer>
-		</dict>
-		<dict>
-			<key>Name</key>
-			<string>nightlytest.MultiSource/Benchmarks/sim/sim</string>
-			<key>Primary</key>
-			<integer>1</integer>
-		</dict>
-		<dict>
-			<key>Name</key>
-			<string>nightlytest.Externals</string>
-			<key>Primary</key>
-			<integer>1</integer>
-		</dict>
-	</array>
 	<key>Machine</key>
 	<dict>
 		<key>Info</key>




From daniel at zuster.org  Mon Mar 22 02:18:45 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 07:18:45 -0000
Subject: [llvm-commits] [zorg] r99167 - in /zorg/trunk/lnt:
 lnt/formats/NightlytestReader.py tests/DB/Import.py
 tests/DB/Inputs/sample-a-small.plist tests/DB/Inputs/sample-b-small.plist
 tests/Misc/Inputs/sample-a-small.plist tests/Misc/SubmitAndEmail.py
 tests/Web/WebSubmit.py
Message-ID: <20100322071845.99FA52A6C12E@llvm.org>

Author: ddunbar
Date: Mon Mar 22 02:18:45 2010
New Revision: 99167

URL: http://llvm.org/viewvc/llvm-project?rev=99167&view=rev
Log:
LNT: Update tests, and also slim them down a bit.

Removed:
    zorg/trunk/lnt/tests/Misc/Inputs/sample-a-small.plist
    zorg/trunk/lnt/tests/Misc/SubmitAndEmail.py
Modified:
    zorg/trunk/lnt/lnt/formats/NightlytestReader.py
    zorg/trunk/lnt/tests/DB/Import.py
    zorg/trunk/lnt/tests/DB/Inputs/sample-a-small.plist
    zorg/trunk/lnt/tests/DB/Inputs/sample-b-small.plist
    zorg/trunk/lnt/tests/Web/WebSubmit.py

Modified: zorg/trunk/lnt/lnt/formats/NightlytestReader.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/formats/NightlytestReader.py?rev=99167&r1=99166&r2=99167&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/formats/NightlytestReader.py (original)
+++ zorg/trunk/lnt/lnt/formats/NightlytestReader.py Mon Mar 22 02:18:45 2010
@@ -145,8 +145,6 @@
 
     tests = []
 
-    groupInfo = []
-
     # llvm-test doesn't provide this
     infoData = {}
 
@@ -187,13 +185,9 @@
                         'Data' : [len(results.get(name,[]))] } )
 
     # llvm-test results
-    groupInfo.append( { 'Name' : basename,
-                        'Primary' : 1 } )
     for groupname,data in (('SingleSource', singlesource),
                            ('MultiSource', multisource),
                            ('Externals', externals)):
-        groupInfo.append( { 'Name' : basename + '.' + groupname,
-                            'Primary' : 1 } )
         lines = data.split('\n')
         header = lines[0].strip().split(',')
         for ln in lines[1:]:
@@ -204,8 +198,6 @@
                            for k,v in zip(header, ln.split(','))])
             testname = basename + '.%s/%s' % (groupname,
                                               entry['Program'].replace('.','_'))
-            groupInfo.append( { 'Name' : testname,
-                                'Primary' : 1 } )
 
             for name,key,tname in (('gcc.compile', 'GCCAS', 'time'),
                                    ('bc.compile', 'Bytecode', 'size'),
@@ -234,8 +226,7 @@
 
     return { 'Machine' : machine,
              'Run' : run,
-             'Tests' : tests,
-             'Group Info' : groupInfo }
+             'Tests' : tests }
 
 format = { 'name' : 'nightlytest',
            'predicate' : _matches_format,

Modified: zorg/trunk/lnt/tests/DB/Import.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/DB/Import.py?rev=99167&r1=99166&r2=99167&view=diff
==============================================================================
--- zorg/trunk/lnt/tests/DB/Import.py (original)
+++ zorg/trunk/lnt/tests/DB/Import.py Mon Mar 22 02:18:45 2010
@@ -1,26 +1,23 @@
-# RUN: rm -f %t.db
-# RUN: sqlite3 %t.db ".read %src_root/db/CreateTables.sql"
+# RUN: rm -rf %t.install
+# RUN: lnt create %t.install
 
-# RUN: %src_root/lnt/import/ImportData --show-sample-count \
-# RUN:     %t.db %S/Inputs/sample-a-small.plist |\
+# RUN: lnt import %t.install %S/Inputs/sample-a-small.plist --commit=1 --show-sample-count |\
 # RUN:   FileCheck -check-prefix=IMPORT-A-1 %s
 
 # IMPORT-A-1: ADDED: 1 machines
 # IMPORT-A-1: ADDED: 1 runs
-# IMPORT-A-1: ADDED: 90 tests
-# IMPORT-A-1: ADDED: 90 samples
+# IMPORT-A-1: ADDED: 8 tests
+# IMPORT-A-1: ADDED: 8 samples
 
-# RUN: %src_root/lnt/import/ImportData --show-sample-count \
-# RUN:     %t.db %S/Inputs/sample-b-small.plist |\
+# RUN: lnt import %t.install %S/Inputs/sample-b-small.plist --commit=1 --show-sample-count |\
 # RUN:   FileCheck -check-prefix=IMPORT-B %s
 
 # IMPORT-B: ADDED: 0 machines
 # IMPORT-B: ADDED: 1 runs
 # IMPORT-B: ADDED: 0 tests
-# IMPORT-B: ADDED: 90 samples
+# IMPORT-B: ADDED: 8 samples
 
-# RUN: %src_root/lnt/import/ImportData --show-sample-count \
-# RUN:     %t.db %S/Inputs/sample-a-small.plist |\
+# RUN: lnt import %t.install %S/Inputs/sample-a-small.plist --commit=1 --show-sample-count |\
 # RUN:   FileCheck -check-prefix=IMPORT-A-2 %s
 
 # IMPORT-A-2: IGNORING DUPLICATE RUN
@@ -29,7 +26,7 @@
 # IMPORT-A-2: ADDED: 0 tests
 # IMPORT-A-2: ADDED: 0 samples
 
-# RUN: python %s %t.db
+# RUN: python %s %t.install/data/lnt.db
 
 import datetime, sys
 from lnt.viewer.PerfDB import PerfDB, Run, Test
@@ -38,7 +35,7 @@
 
 m = db.machines().one()
 assert m.id == 1
-assert m.name == 'smoosh-01.apple.com'
+assert m.name == 'LNT SAMPLE MACHINE'
 
 info = dict((i.key,i.value) for i in m.info.values())
 assert 'os' in info
@@ -54,7 +51,7 @@
 assert rA.info['tag'].key == 'tag'
 assert rA.info['tag'].value == 'nightlytest'
 
-t = db.tests().order_by(Test.name)[20]
+t = db.tests().order_by(Test.name)[4]
 assert t.name == 'nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.llc.compile.success'
 assert t.info.values() == []
 

Modified: zorg/trunk/lnt/tests/DB/Inputs/sample-a-small.plist
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/DB/Inputs/sample-a-small.plist?rev=99167&r1=99166&r2=99167&view=diff
==============================================================================
--- zorg/trunk/lnt/tests/DB/Inputs/sample-a-small.plist (original)
+++ zorg/trunk/lnt/tests/DB/Inputs/sample-a-small.plist Mon Mar 22 02:18:45 2010
@@ -16,7 +16,7 @@
 			<string> Darwin smoosh-01 10.2.0 Darwin Kernel Version 10.2.0: Tue Nov  3 10:37:10 PST 2009; root:xnu-1486.2.11~1/RELEASE_I386 i386hardware: i386</string>
 		</dict>
 		<key>Name</key>
-		<string>smoosh-01.apple.com</string>
+		<string>LNT SAMPLE MACHINE</string>
 	</dict>
 	<key>Run</key>
 	<dict>
@@ -35,149 +35,6 @@
 		<dict>
 			<key>Data</key>
 			<array>
-				<string> 24.50</string>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.Summary.configtime.wall</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<string> 22.59</string>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.Summary.configtime.user</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<string> 168.04</string>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.Summary.checkouttime.wall</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<string> 0</string>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.Summary.checkouttime.user</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>209.99000000000001</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.Summary.buildtime.wall</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>2501.0</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.Summary.buildtime.user</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<string> 0.0</string>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.Summary.dgtime.wall</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<string> 0.0</string>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.Summary.dgtime.user</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<true/>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.Summary.buildstatus</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>0</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.DejaGNU.PASS</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>0</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.DejaGNU.FAIL</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>0</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.DejaGNU.XPASS</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>0</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.DejaGNU.XFAIL</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
 				<integer>1</integer>
 			</array>
 			<key>Info</key>
@@ -250,94 +107,6 @@
 			<dict>
 			</dict>
 			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.llc-beta.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.010800000000000001</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.llc-beta.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.jit.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.011299999999999999</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.jit.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.gcc.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>3.25</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.gcc.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.cbe.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>3.2200000000000002</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.cbe.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
 			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.llc.exec.success</string>
 		</dict>
 		<dict>
@@ -351,677 +120,6 @@
 			<key>Name</key>
 			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.llc.exec.time</string>
 		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.llc-beta.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>3.2200000000000002</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.llc-beta.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.jit.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>3.0899999999999999</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fannkuch.jit.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.gcc.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.0137</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.gcc.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.bc.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>2848.0</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.bc.compile.size</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.llc.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.013299999999999999</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.llc.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.llc-beta.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.0135</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.llc-beta.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.jit.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.0144</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.jit.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.gcc.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>1.1699999999999999</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.gcc.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.cbe.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>1.3400000000000001</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.cbe.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.llc.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>1.1499999999999999</real>
-			</array>
-			<key>Info</key>
-			<dict>
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-			<key>Name</key>
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 </plist>

Modified: zorg/trunk/lnt/tests/DB/Inputs/sample-b-small.plist
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/DB/Inputs/sample-b-small.plist?rev=99167&r1=99166&r2=99167&view=diff
==============================================================================
--- zorg/trunk/lnt/tests/DB/Inputs/sample-b-small.plist (original)
+++ zorg/trunk/lnt/tests/DB/Inputs/sample-b-small.plist Mon Mar 22 02:18:45 2010
@@ -16,7 +16,7 @@
 			<string> Darwin smoosh-01 10.2.0 Darwin Kernel Version 10.2.0: Tue Nov  3 10:37:10 PST 2009; root:xnu-1486.2.11~1/RELEASE_I386 i386hardware: i386</string>
 		</dict>
 		<key>Name</key>
-		<string>smoosh-01.apple.com</string>
+		<string>LNT SAMPLE MACHINE</string>
 	</dict>
 	<key>Run</key>
 	<dict>
@@ -35,149 +35,6 @@
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-			<string>nightlytest.Summary.configtime.wall</string>
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-				<string> 22.62</string>
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-			<key>Name</key>
-			<string>nightlytest.Summary.configtime.user</string>
-		</dict>
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-				<string> 146.27</string>
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-			<key>Name</key>
-			<string>nightlytest.Summary.checkouttime.wall</string>
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-			<string>nightlytest.Summary.buildtime.wall</string>
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-			<string>nightlytest.DejaGNU.PASS</string>
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-			<key>Name</key>
-			<string>nightlytest.DejaGNU.FAIL</string>
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-			<string>nightlytest.DejaGNU.XPASS</string>
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@@ -250,94 +107,6 @@
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Removed: zorg/trunk/lnt/tests/Misc/Inputs/sample-a-small.plist
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/Misc/Inputs/sample-a-small.plist?rev=99166&view=auto
==============================================================================
--- zorg/trunk/lnt/tests/Misc/Inputs/sample-a-small.plist (original)
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@@ -1,2824 +0,0 @@
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-			<array>
-				<real>1.1599999999999999</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.llc-beta.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.jit.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>1.1799999999999999</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/fasta.jit.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.gcc.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.013599999999999999</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.gcc.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.bc.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>3248.0</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.bc.compile.size</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.llc.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.012699999999999999</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.llc.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.llc-beta.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.012800000000000001</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.llc-beta.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.jit.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.0121</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.jit.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.gcc.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>1.3200000000000001</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.gcc.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.cbe.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>1.3500000000000001</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.cbe.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.llc.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>1.3999999999999999</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.llc.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.llc-beta.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>1.3999999999999999</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.llc-beta.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.jit.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>1.4299999999999999</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/n-body.jit.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.gcc.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.0058999999999999999</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.gcc.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.bc.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>1264.0</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.bc.compile.size</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.llc.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.0067000000000000002</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.llc.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.llc-beta.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.0067999999999999996</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.llc-beta.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.jit.compile.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.0071999999999999998</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.jit.compile.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.gcc.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.92000000000000004</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.gcc.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.cbe.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.93999999999999995</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.cbe.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.llc.exec.success</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<real>0.93999999999999995</real>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.llc.exec.time</string>
-		</dict>
-		<dict>
-			<key>Data</key>
-			<array>
-				<integer>1</integer>
-			</array>
-			<key>Info</key>
-			<dict>
-			</dict>
-			<key>Name</key>
-			<string>nightlytest.SingleSource/Benchmarks/BenchmarkGame/nsieve-bits.llc-beta.exec.success</string>
-		</dict>
-	</array>
-</dict>
-</plist>

Removed: zorg/trunk/lnt/tests/Misc/SubmitAndEmail.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/Misc/SubmitAndEmail.py?rev=99166&view=auto
==============================================================================
--- zorg/trunk/lnt/tests/Misc/SubmitAndEmail.py (original)
+++ zorg/trunk/lnt/tests/Misc/SubmitAndEmail.py (removed)
@@ -1,19 +0,0 @@
-# RUN: rm -f %t.db
-# RUN: sqlite3 %t.db ".read %src_root/db/CreateTables.sql"
-
-# FIXME: Find a way to test email works, without being annoying.
-# RUN: %src_root/lnt/import/ImportData \
-# RUN:  --show-sample-count \
-# RUN:  --commit=0 \
-# RUN:  --email-on-import=1 --email-host=%email_host \
-# RUN:  --email-from=lnt-test at llvm.org --email-to=%email_to \
-# RUN:  --email-base-url=ZORG_TEST %t.db %S/Inputs/sample-a-small.plist > %t
-# RUN: FileCheck %s < %t
-
-# CHECK: ADDED: 1 machines
-# CHECK: ADDED: 1 runs
-# CHECK: ADDED: 90 tests
-# CHECK: ADDED: 90 samples
-
-
-

Modified: zorg/trunk/lnt/tests/Web/WebSubmit.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/Web/WebSubmit.py?rev=99167&r1=99166&r2=99167&view=diff
==============================================================================
--- zorg/trunk/lnt/tests/Web/WebSubmit.py (original)
+++ zorg/trunk/lnt/tests/Web/WebSubmit.py Mon Mar 22 02:18:45 2010
@@ -1,14 +1,13 @@
-# RUN: %src_root/lnt/import/SubmitData %base_url/submitRun \
-# RUN:   %S/../DB/Inputs/sample-a-small.plist > %t.log
-# RUN: FileCheck %s < %t.log
+# RUN: lnt submit %base_url/submitRun %S/../DB/Inputs/sample-a-small.plist > %t
+# RUN: FileCheck %s < %t
 
 # CHECK: STATUS: 0
 
 # CHECK: OUTPUT:
 # CHECK: IMPORT: {{.*}}/lnt_tmp/{{.*}}.plist
-# CHECK: LOAD TIME: 0.03s
-# CHECK: IMPORT TIME: 0.03s
-# CHECK: MACHINE: 107
+# CHECK: LOAD TIME: {{.*}}
+# CHECK: IMPORT TIME: {{.*}}
+# CHECK: MACHINE: {{.*}}
 # CHECK: START  : {{.*}}
 # CHECK: END    : {{.*}}
 # CHECK: INFO   : u'tag' = u'nightlytest'




From daniel at zuster.org  Mon Mar 22 02:18:51 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 07:18:51 -0000
Subject: [llvm-commits] [zorg] r99169 - in /zorg/trunk/lnt/lnt:
 lnttool/import_data.py util/ImportData.py
Message-ID: <20100322071851.61D7C2A6C12C@llvm.org>

Author: ddunbar
Date: Mon Mar 22 02:18:51 2010
New Revision: 99169

URL: http://llvm.org/viewvc/llvm-project?rev=99169&view=rev
Log:
LNT: Add 'lnt import' option to disable email reports.

Modified:
    zorg/trunk/lnt/lnt/lnttool/import_data.py
    zorg/trunk/lnt/lnt/util/ImportData.py

Modified: zorg/trunk/lnt/lnt/lnttool/import_data.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/import_data.py?rev=99169&r1=99168&r2=99169&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/lnttool/import_data.py (original)
+++ zorg/trunk/lnt/lnt/lnttool/import_data.py Mon Mar 22 02:18:51 2010
@@ -21,6 +21,8 @@
                       default=False)
     parser.add_option("", "--show-sample-count", dest="showSampleCount",
                       action="store_true", default=False)
+    parser.add_option("", "--no-email", dest="noEmail",
+                      action="store_true", default=False)
     (opts, args) = parser.parse_args(args)
 
     if len(args) < 2:
@@ -49,4 +51,5 @@
     for file in args:
         success, run = ImportData.import_and_report(
             config, opts.database, db, file, sys.stdout,
-            opts.format, opts.commit, opts.showSampleCount)
+            opts.format, opts.commit, opts.showSampleCount,
+            opts.noEmail)

Modified: zorg/trunk/lnt/lnt/util/ImportData.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/ImportData.py?rev=99169&r1=99168&r2=99169&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/util/ImportData.py (original)
+++ zorg/trunk/lnt/lnt/util/ImportData.py Mon Mar 22 02:18:51 2010
@@ -5,7 +5,7 @@
 from lnt.util import NTEmailReport
 
 def import_and_report(config, db_name, db, file, log, format, commit=False,
-                      show_sample_count=False):
+                      show_sample_count=False, disable_email=False):
     """
     import_file(config, db_name, db, file) -> (success, run, log)
 
@@ -24,6 +24,8 @@
     startTime = time.time()
     try:
         data = formats.read_any(file, format)
+    except KeyboardInterrupt:
+        raise
     except:
         print >>log, 'ERROR: %r: load failed' % file
         return (False, None)
@@ -48,6 +50,8 @@
     importStartTime = time.time()
     try:
         success,run = PerfDB.importDataFromDict(db, data)
+    except KeyboardInterrupt:
+        raise
     except:
         print >>log, 'ERROR: %r: import failed' % file
         return (False, None)
@@ -61,7 +65,7 @@
         for ri in run.info.values():
             print >>log, "    INFO   : %r = %r" % (ri.key, ri.value)
 
-    if config.ntEmailEnabled:
+    if not disable_email and config.ntEmailEnabled:
         print >>log, "\nMAILING RESULTS TO: %r\n" % toAddress
         NTEmailReport.emailReport(db, run,
                                   "%s/db_%s/nightlytest/" % (config.zorgURL,




From ggreif at gmail.com  Mon Mar 22 03:28:00 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Mon, 22 Mar 2010 08:28:00 -0000
Subject: [llvm-commits] [llvm] r99170 - in /llvm/trunk: ./
 include/llvm/Instructions.h include/llvm/Support/CallSite.h
 lib/Analysis/IPA/GlobalsModRef.cpp lib/Bitcode/Writer/BitcodeWriter.cpp
 lib/Transforms/IPO/DeadArgumentElimination.cpp
 lib/Transforms/IPO/PruneEH.cpp lib/Transforms/Scalar/SimplifyCFGPass.cpp
 lib/Transforms/Utils/LowerInvoke.cpp lib/VMCore/AsmWriter.cpp
 lib/VMCore/Instructions.cpp lib/VMCore/Verifier.cpp
Message-ID: <20100322082800.EA99D2A6C12C@llvm.org>

Author: ggreif
Date: Mon Mar 22 03:28:00 2010
New Revision: 99170

URL: http://llvm.org/viewvc/llvm-project?rev=99170&view=rev
Log:
Now that hopefully all direct accesses to InvokeInst operands are fixed
we can reapply the InvokeInst operand reordering patch. (see r98957).


Modified:
    llvm/trunk/   (props changed)
    llvm/trunk/include/llvm/Instructions.h
    llvm/trunk/include/llvm/Support/CallSite.h
    llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp
    llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
    llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp
    llvm/trunk/lib/Transforms/IPO/PruneEH.cpp
    llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp
    llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp
    llvm/trunk/lib/VMCore/AsmWriter.cpp
    llvm/trunk/lib/VMCore/Instructions.cpp
    llvm/trunk/lib/VMCore/Verifier.cpp

Propchange: llvm/trunk/
------------------------------------------------------------------------------
    svn:mergeinfo = /llvm/branches/ggreif/InvokeInst-operands:98645-99138

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=99170&r1=99169&r2=99170&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Mon Mar 22 03:28:00 2010
@@ -2508,32 +2508,31 @@
   /// indirect function invocation.
   ///
   Function *getCalledFunction() const {
-    return dyn_cast<Function>(getOperand(0));
+    return dyn_cast<Function>(Op<-3>());
   }
 
   /// getCalledValue - Get a pointer to the function that is invoked by this
   /// instruction
-  const Value *getCalledValue() const { return getOperand(0); }
-        Value *getCalledValue()       { return getOperand(0); }
+  const Value *getCalledValue() const { return Op<-3>(); }
+        Value *getCalledValue()       { return Op<-3>(); }
 
   /// setCalledFunction - Set the function called.
   void setCalledFunction(Value* Fn) {
-    Op<0>() = Fn;
+    Op<-3>() = Fn;
   }
 
   // get*Dest - Return the destination basic blocks...
   BasicBlock *getNormalDest() const {
-    return cast<BasicBlock>(getOperand(1));
+    return cast<BasicBlock>(Op<-2>());
   }
   BasicBlock *getUnwindDest() const {
-    return cast<BasicBlock>(getOperand(2));
+    return cast<BasicBlock>(Op<-1>());
   }
   void setNormalDest(BasicBlock *B) {
-    setOperand(1, (Value*)B);
+    Op<-2>() = reinterpret_cast<Value*>(B);
   }
-
   void setUnwindDest(BasicBlock *B) {
-    setOperand(2, (Value*)B);
+    Op<-1>() = reinterpret_cast<Value*>(B);
   }
 
   BasicBlock *getSuccessor(unsigned i) const {
@@ -2543,7 +2542,7 @@
 
   void setSuccessor(unsigned idx, BasicBlock *NewSucc) {
     assert(idx < 2 && "Successor # out of range for invoke!");
-    setOperand(idx+1, (Value*)NewSucc);
+    *(&Op<-2>() + idx) = reinterpret_cast<Value*>(NewSucc);
   }
 
   unsigned getNumSuccessors() const { return 2; }
@@ -2556,6 +2555,7 @@
   static inline bool classof(const Value *V) {
     return isa<Instruction>(V) && classof(cast<Instruction>(V));
   }
+
 private:
   virtual BasicBlock *getSuccessorV(unsigned idx) const;
   virtual unsigned getNumSuccessorsV() const;

Modified: llvm/trunk/include/llvm/Support/CallSite.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=99170&r1=99169&r2=99170&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CallSite.h (original)
+++ llvm/trunk/include/llvm/Support/CallSite.h Mon Mar 22 03:28:00 2010
@@ -118,7 +118,7 @@
   ///
   Value *getCalledValue() const {
     assert(getInstruction() && "Not a call or invoke instruction!");
-    return getInstruction()->getOperand(0);
+    return *getCallee();
   }
 
   /// getCalledFunction - Return the function being called if this is a direct
@@ -132,7 +132,7 @@
   ///
   void setCalledFunction(Value *V) {
     assert(getInstruction() && "Not a call or invoke instruction!");
-    getInstruction()->setOperand(0, V);
+    *getCallee() = V;
   }
 
   Value *getArgument(unsigned ArgNo) const {
@@ -146,6 +146,16 @@
     getInstruction()->setOperand(getArgumentOffset() + ArgNo, newVal);
   }
 
+  /// Given a value use iterator, returns the argument that corresponds to it.
+  /// Iterator must actually correspond to an argument.
+  unsigned getArgumentNo(Value::use_iterator I) const {
+    assert(getInstruction() && "Not a call or invoke instruction!");
+    assert(arg_begin() <= &I.getUse() && &I.getUse() < arg_end()
+           && "Argument # out of range!");
+
+    return &I.getUse() - arg_begin();
+  }
+
   /// Given an operand number, returns the argument that corresponds to it.
   /// OperandNo must be a valid operand number that actually corresponds to an
   /// argument.
@@ -171,7 +181,7 @@
     return getInstruction()->op_begin() + getArgumentOffset();
   }
 
-  arg_iterator arg_end() const { return getInstruction()->op_end(); }
+  arg_iterator arg_end() const { return getInstruction()->op_end() - getArgumentEndOffset(); }
   bool arg_empty() const { return arg_end() == arg_begin(); }
   unsigned arg_size() const { return unsigned(arg_end() - arg_begin()); }
 
@@ -180,17 +190,25 @@
   }
 
   bool isCallee(Value::use_iterator UI) const {
-    return getInstruction()->op_begin() == &UI.getUse();
+    return getCallee() == &UI.getUse();
   }
-
 private:
   /// Returns the operand number of the first argument
   unsigned getArgumentOffset() const {
     if (isCall())
       return 1; // Skip Function
     else
-      return 3; // Skip Function, BB, BB
+      return 0; // Args are at the front
   }
+
+  unsigned getArgumentEndOffset() const {
+    if (isCall())
+      return 0; // Unchanged
+    else
+      return 3; // Skip BB, BB, Function
+  }
+
+  User::op_iterator getCallee() const;
 };
 
 } // End llvm namespace

Modified: llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp?rev=99170&r1=99169&r2=99170&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp (original)
+++ llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp Mon Mar 22 03:28:00 2010
@@ -257,7 +257,7 @@
     } else if (InvokeInst *II = dyn_cast<InvokeInst>(*UI)) {
       // Make sure that this is just the function being called, not that it is
       // passing into the function.
-      for (unsigned i = 3, e = II->getNumOperands(); i != e; ++i)
+      for (unsigned i = 0, e = II->getNumOperands() - 3; i != e; ++i)
         if (II->getOperand(i) == V) return true;
     } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(*UI)) {
       if (CE->getOpcode() == Instruction::GetElementPtr ||

Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=99170&r1=99169&r2=99170&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Mon Mar 22 03:28:00 2010
@@ -1090,11 +1090,11 @@
 
     // Emit value #'s for the fixed parameters.
     for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i)
-      Vals.push_back(VE.getValueID(I.getOperand(i+3)));  // fixed param.
+      Vals.push_back(VE.getValueID(I.getOperand(i)));  // fixed param.
 
     // Emit type/value pairs for varargs params.
     if (FTy->isVarArg()) {
-      for (unsigned i = 3+FTy->getNumParams(), e = I.getNumOperands();
+      for (unsigned i = FTy->getNumParams(), e = I.getNumOperands()-3;
            i != e; ++i)
         PushValueAndType(I.getOperand(i), InstID, Vals, VE); // vararg
     }

Modified: llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp?rev=99170&r1=99169&r2=99170&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp Mon Mar 22 03:28:00 2010
@@ -352,14 +352,14 @@
         // argument, since if it was the function argument this would be an
         // indirect call and the we know can't be looking at a value of the
         // label type (for the invoke instruction).
-        unsigned ArgNo = CS.getArgumentNo(U.getOperandNo());
+        unsigned ArgNo = CS.getArgumentNo(U);
 
         if (ArgNo >= F->getFunctionType()->getNumParams())
           // The value is passed in through a vararg! Must be live.
           return Live;
 
-        assert(CS.getArgument(ArgNo) 
-               == CS.getInstruction()->getOperand(U.getOperandNo()) 
+        assert(CS.getArgument(ArgNo)
+               == CS.getInstruction()->getOperand(U.getOperandNo())
                && "Argument is not where we expected it");
 
         // Value passed to a normal call. It's only live when the corresponding

Modified: llvm/trunk/lib/Transforms/IPO/PruneEH.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/PruneEH.cpp?rev=99170&r1=99169&r2=99170&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/PruneEH.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/PruneEH.cpp Mon Mar 22 03:28:00 2010
@@ -168,7 +168,7 @@
   for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
     if (InvokeInst *II = dyn_cast<InvokeInst>(BB->getTerminator()))
       if (II->doesNotThrow()) {
-        SmallVector<Value*, 8> Args(II->op_begin()+3, II->op_end());
+        SmallVector<Value*, 8> Args(II->op_begin(), II->op_end() - 3);
         // Insert a call instruction before the invoke.
         CallInst *Call = CallInst::Create(II->getCalledValue(),
                                           Args.begin(), Args.end(), "", II);

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp?rev=99170&r1=99169&r2=99170&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp Mon Mar 22 03:28:00 2010
@@ -79,7 +79,7 @@
 /// ChangeToCall - Convert the specified invoke into a normal call.
 static void ChangeToCall(InvokeInst *II) {
   BasicBlock *BB = II->getParent();
-  SmallVector<Value*, 8> Args(II->op_begin()+3, II->op_end());
+  SmallVector<Value*, 8> Args(II->op_begin(), II->op_end() - 3);
   CallInst *NewCall = CallInst::Create(II->getCalledValue(), Args.begin(),
                                        Args.end(), "", II);
   NewCall->takeName(II);

Modified: llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp?rev=99170&r1=99169&r2=99170&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp Mon Mar 22 03:28:00 2010
@@ -226,7 +226,7 @@
   bool Changed = false;
   for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
     if (InvokeInst *II = dyn_cast<InvokeInst>(BB->getTerminator())) {
-      std::vector<Value*> CallArgs(II->op_begin()+3, II->op_end());
+      std::vector<Value*> CallArgs(II->op_begin(), II->op_end() - 3);
       // Insert a normal call instruction...
       CallInst *NewCall = CallInst::Create(II->getCalledValue(),
                                            CallArgs.begin(), CallArgs.end(), "",II);
@@ -298,7 +298,7 @@
   CatchSwitch->addCase(InvokeNoC, II->getUnwindDest());
 
   // Insert a normal call instruction.
-  std::vector<Value*> CallArgs(II->op_begin()+3, II->op_end());
+  std::vector<Value*> CallArgs(II->op_begin(), II->op_end() - 3);
   CallInst *NewCall = CallInst::Create(II->getCalledValue(),
                                        CallArgs.begin(), CallArgs.end(), "",
                                        II);

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=99170&r1=99169&r2=99170&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Mar 22 03:28:00 2010
@@ -1875,6 +1875,7 @@
     if (PAL.getFnAttributes() != Attribute::None)
       Out << ' ' << Attribute::getAsString(PAL.getFnAttributes());
   } else if (const InvokeInst *II = dyn_cast<InvokeInst>(&I)) {
+    Operand = II->getCalledValue();
     const PointerType    *PTy = cast<PointerType>(Operand->getType());
     const FunctionType   *FTy = cast<FunctionType>(PTy->getElementType());
     const Type         *RetTy = FTy->getReturnType();
@@ -1912,10 +1913,10 @@
       writeOperand(Operand, true);
     }
     Out << '(';
-    for (unsigned op = 3, Eop = I.getNumOperands(); op < Eop; ++op) {
-      if (op > 3)
+    for (unsigned op = 0, Eop = I.getNumOperands() - 3; op < Eop; ++op) {
+      if (op)
         Out << ", ";
-      writeParamOperand(I.getOperand(op), PAL.getParamAttributes(op-2));
+      writeParamOperand(I.getOperand(op), PAL.getParamAttributes(op + 1));
     }
 
     Out << ')';

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=99170&r1=99169&r2=99170&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Mon Mar 22 03:28:00 2010
@@ -98,6 +98,13 @@
   return false;
 }
 
+User::op_iterator CallSite::getCallee() const {
+  Instruction *II(getInstruction());
+  return isCall()
+    ? cast<CallInst>(II)->op_begin()
+    : cast<InvokeInst>(II)->op_end() - 3; // Skip BB, BB, Function
+}
+
 #undef CALLSITE_DELEGATE_GETTER
 #undef CALLSITE_DELEGATE_SETTER
 
@@ -611,10 +618,9 @@
 void InvokeInst::init(Value *Fn, BasicBlock *IfNormal, BasicBlock *IfException,
                       Value* const *Args, unsigned NumArgs) {
   assert(NumOperands == 3+NumArgs && "NumOperands not set up?");
-  Use *OL = OperandList;
-  OL[0] = Fn;
-  OL[1] = IfNormal;
-  OL[2] = IfException;
+  Op<-3>() = Fn;
+  Op<-2>() = IfNormal;
+  Op<-1>() = IfException;
   const FunctionType *FTy =
     cast<FunctionType>(cast<PointerType>(Fn->getType())->getElementType());
   FTy = FTy;  // silence warning.
@@ -623,12 +629,13 @@
           (FTy->isVarArg() && NumArgs > FTy->getNumParams())) &&
          "Calling a function with bad signature");
 
+  Use *OL = OperandList;
   for (unsigned i = 0, e = NumArgs; i != e; i++) {
     assert((i >= FTy->getNumParams() || 
             FTy->getParamType(i) == Args[i]->getType()) &&
            "Invoking a function with a bad signature!");
     
-    OL[i+3] = Args[i];
+    OL[i] = Args[i];
   }
 }
 

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=99170&r1=99169&r2=99170&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Mar 22 03:28:00 2010
@@ -1483,7 +1483,7 @@
                 "Instruction does not dominate all uses!", Op, &I);
       }
     } else if (isa<InlineAsm>(I.getOperand(i))) {
-      Assert1(i == 0 && (isa<CallInst>(I) || isa<InvokeInst>(I)),
+      Assert1((i == 0 && isa<CallInst>(I)) || (i + 3 == e && isa<InvokeInst>(I)),
               "Cannot take the address of an inline asm!", &I);
     }
   }




From ggreif at gmail.com  Mon Mar 22 04:11:00 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Mon, 22 Mar 2010 09:11:00 -0000
Subject: [llvm-commits] [llvm] r99171 - in /llvm/trunk: ./
 include/llvm/Instructions.h include/llvm/Support/CallSite.h
 lib/Analysis/IPA/GlobalsModRef.cpp lib/Bitcode/Writer/BitcodeWriter.cpp
 lib/Transforms/IPO/DeadArgumentElimination.cpp
 lib/Transforms/IPO/PruneEH.cpp lib/Transforms/Scalar/SimplifyCFGPass.cpp
 lib/Transforms/Utils/LowerInvoke.cpp lib/VMCore/AsmWriter.cpp
 lib/VMCore/Instructions.cpp lib/VMCore/Verifier.cpp
Message-ID: <20100322091100.733152A6C12C@llvm.org>

Author: ggreif
Date: Mon Mar 22 04:11:00 2010
New Revision: 99171

URL: http://llvm.org/viewvc/llvm-project?rev=99171&view=rev
Log:
backing out r99170 because it still fails on clang-x86_64-darwin10-fnt

Modified:
    llvm/trunk/   (props changed)
    llvm/trunk/include/llvm/Instructions.h
    llvm/trunk/include/llvm/Support/CallSite.h
    llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp
    llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
    llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp
    llvm/trunk/lib/Transforms/IPO/PruneEH.cpp
    llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp
    llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp
    llvm/trunk/lib/VMCore/AsmWriter.cpp
    llvm/trunk/lib/VMCore/Instructions.cpp
    llvm/trunk/lib/VMCore/Verifier.cpp

Propchange: llvm/trunk/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo (removed)
@@ -1 +0,0 @@
-/llvm/branches/ggreif/InvokeInst-operands:98645-99138

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=99171&r1=99170&r2=99171&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Mon Mar 22 04:11:00 2010
@@ -2508,31 +2508,32 @@
   /// indirect function invocation.
   ///
   Function *getCalledFunction() const {
-    return dyn_cast<Function>(Op<-3>());
+    return dyn_cast<Function>(getOperand(0));
   }
 
   /// getCalledValue - Get a pointer to the function that is invoked by this
   /// instruction
-  const Value *getCalledValue() const { return Op<-3>(); }
-        Value *getCalledValue()       { return Op<-3>(); }
+  const Value *getCalledValue() const { return getOperand(0); }
+        Value *getCalledValue()       { return getOperand(0); }
 
   /// setCalledFunction - Set the function called.
   void setCalledFunction(Value* Fn) {
-    Op<-3>() = Fn;
+    Op<0>() = Fn;
   }
 
   // get*Dest - Return the destination basic blocks...
   BasicBlock *getNormalDest() const {
-    return cast<BasicBlock>(Op<-2>());
+    return cast<BasicBlock>(getOperand(1));
   }
   BasicBlock *getUnwindDest() const {
-    return cast<BasicBlock>(Op<-1>());
+    return cast<BasicBlock>(getOperand(2));
   }
   void setNormalDest(BasicBlock *B) {
-    Op<-2>() = reinterpret_cast<Value*>(B);
+    setOperand(1, (Value*)B);
   }
+
   void setUnwindDest(BasicBlock *B) {
-    Op<-1>() = reinterpret_cast<Value*>(B);
+    setOperand(2, (Value*)B);
   }
 
   BasicBlock *getSuccessor(unsigned i) const {
@@ -2542,7 +2543,7 @@
 
   void setSuccessor(unsigned idx, BasicBlock *NewSucc) {
     assert(idx < 2 && "Successor # out of range for invoke!");
-    *(&Op<-2>() + idx) = reinterpret_cast<Value*>(NewSucc);
+    setOperand(idx+1, (Value*)NewSucc);
   }
 
   unsigned getNumSuccessors() const { return 2; }
@@ -2555,7 +2556,6 @@
   static inline bool classof(const Value *V) {
     return isa<Instruction>(V) && classof(cast<Instruction>(V));
   }
-
 private:
   virtual BasicBlock *getSuccessorV(unsigned idx) const;
   virtual unsigned getNumSuccessorsV() const;

Modified: llvm/trunk/include/llvm/Support/CallSite.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=99171&r1=99170&r2=99171&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CallSite.h (original)
+++ llvm/trunk/include/llvm/Support/CallSite.h Mon Mar 22 04:11:00 2010
@@ -118,7 +118,7 @@
   ///
   Value *getCalledValue() const {
     assert(getInstruction() && "Not a call or invoke instruction!");
-    return *getCallee();
+    return getInstruction()->getOperand(0);
   }
 
   /// getCalledFunction - Return the function being called if this is a direct
@@ -132,7 +132,7 @@
   ///
   void setCalledFunction(Value *V) {
     assert(getInstruction() && "Not a call or invoke instruction!");
-    *getCallee() = V;
+    getInstruction()->setOperand(0, V);
   }
 
   Value *getArgument(unsigned ArgNo) const {
@@ -146,16 +146,6 @@
     getInstruction()->setOperand(getArgumentOffset() + ArgNo, newVal);
   }
 
-  /// Given a value use iterator, returns the argument that corresponds to it.
-  /// Iterator must actually correspond to an argument.
-  unsigned getArgumentNo(Value::use_iterator I) const {
-    assert(getInstruction() && "Not a call or invoke instruction!");
-    assert(arg_begin() <= &I.getUse() && &I.getUse() < arg_end()
-           && "Argument # out of range!");
-
-    return &I.getUse() - arg_begin();
-  }
-
   /// Given an operand number, returns the argument that corresponds to it.
   /// OperandNo must be a valid operand number that actually corresponds to an
   /// argument.
@@ -181,7 +171,7 @@
     return getInstruction()->op_begin() + getArgumentOffset();
   }
 
-  arg_iterator arg_end() const { return getInstruction()->op_end() - getArgumentEndOffset(); }
+  arg_iterator arg_end() const { return getInstruction()->op_end(); }
   bool arg_empty() const { return arg_end() == arg_begin(); }
   unsigned arg_size() const { return unsigned(arg_end() - arg_begin()); }
 
@@ -190,25 +180,17 @@
   }
 
   bool isCallee(Value::use_iterator UI) const {
-    return getCallee() == &UI.getUse();
+    return getInstruction()->op_begin() == &UI.getUse();
   }
+
 private:
   /// Returns the operand number of the first argument
   unsigned getArgumentOffset() const {
     if (isCall())
       return 1; // Skip Function
     else
-      return 0; // Args are at the front
+      return 3; // Skip Function, BB, BB
   }
-
-  unsigned getArgumentEndOffset() const {
-    if (isCall())
-      return 0; // Unchanged
-    else
-      return 3; // Skip BB, BB, Function
-  }
-
-  User::op_iterator getCallee() const;
 };
 
 } // End llvm namespace

Modified: llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp?rev=99171&r1=99170&r2=99171&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp (original)
+++ llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp Mon Mar 22 04:11:00 2010
@@ -257,7 +257,7 @@
     } else if (InvokeInst *II = dyn_cast<InvokeInst>(*UI)) {
       // Make sure that this is just the function being called, not that it is
       // passing into the function.
-      for (unsigned i = 0, e = II->getNumOperands() - 3; i != e; ++i)
+      for (unsigned i = 3, e = II->getNumOperands(); i != e; ++i)
         if (II->getOperand(i) == V) return true;
     } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(*UI)) {
       if (CE->getOpcode() == Instruction::GetElementPtr ||

Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=99171&r1=99170&r2=99171&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Mon Mar 22 04:11:00 2010
@@ -1090,11 +1090,11 @@
 
     // Emit value #'s for the fixed parameters.
     for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i)
-      Vals.push_back(VE.getValueID(I.getOperand(i)));  // fixed param.
+      Vals.push_back(VE.getValueID(I.getOperand(i+3)));  // fixed param.
 
     // Emit type/value pairs for varargs params.
     if (FTy->isVarArg()) {
-      for (unsigned i = FTy->getNumParams(), e = I.getNumOperands()-3;
+      for (unsigned i = 3+FTy->getNumParams(), e = I.getNumOperands();
            i != e; ++i)
         PushValueAndType(I.getOperand(i), InstID, Vals, VE); // vararg
     }

Modified: llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp?rev=99171&r1=99170&r2=99171&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp Mon Mar 22 04:11:00 2010
@@ -352,14 +352,14 @@
         // argument, since if it was the function argument this would be an
         // indirect call and the we know can't be looking at a value of the
         // label type (for the invoke instruction).
-        unsigned ArgNo = CS.getArgumentNo(U);
+        unsigned ArgNo = CS.getArgumentNo(U.getOperandNo());
 
         if (ArgNo >= F->getFunctionType()->getNumParams())
           // The value is passed in through a vararg! Must be live.
           return Live;
 
-        assert(CS.getArgument(ArgNo)
-               == CS.getInstruction()->getOperand(U.getOperandNo())
+        assert(CS.getArgument(ArgNo) 
+               == CS.getInstruction()->getOperand(U.getOperandNo()) 
                && "Argument is not where we expected it");
 
         // Value passed to a normal call. It's only live when the corresponding

Modified: llvm/trunk/lib/Transforms/IPO/PruneEH.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/PruneEH.cpp?rev=99171&r1=99170&r2=99171&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/PruneEH.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/PruneEH.cpp Mon Mar 22 04:11:00 2010
@@ -168,7 +168,7 @@
   for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
     if (InvokeInst *II = dyn_cast<InvokeInst>(BB->getTerminator()))
       if (II->doesNotThrow()) {
-        SmallVector<Value*, 8> Args(II->op_begin(), II->op_end() - 3);
+        SmallVector<Value*, 8> Args(II->op_begin()+3, II->op_end());
         // Insert a call instruction before the invoke.
         CallInst *Call = CallInst::Create(II->getCalledValue(),
                                           Args.begin(), Args.end(), "", II);

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp?rev=99171&r1=99170&r2=99171&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp Mon Mar 22 04:11:00 2010
@@ -79,7 +79,7 @@
 /// ChangeToCall - Convert the specified invoke into a normal call.
 static void ChangeToCall(InvokeInst *II) {
   BasicBlock *BB = II->getParent();
-  SmallVector<Value*, 8> Args(II->op_begin(), II->op_end() - 3);
+  SmallVector<Value*, 8> Args(II->op_begin()+3, II->op_end());
   CallInst *NewCall = CallInst::Create(II->getCalledValue(), Args.begin(),
                                        Args.end(), "", II);
   NewCall->takeName(II);

Modified: llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp?rev=99171&r1=99170&r2=99171&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp Mon Mar 22 04:11:00 2010
@@ -226,7 +226,7 @@
   bool Changed = false;
   for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
     if (InvokeInst *II = dyn_cast<InvokeInst>(BB->getTerminator())) {
-      std::vector<Value*> CallArgs(II->op_begin(), II->op_end() - 3);
+      std::vector<Value*> CallArgs(II->op_begin()+3, II->op_end());
       // Insert a normal call instruction...
       CallInst *NewCall = CallInst::Create(II->getCalledValue(),
                                            CallArgs.begin(), CallArgs.end(), "",II);
@@ -298,7 +298,7 @@
   CatchSwitch->addCase(InvokeNoC, II->getUnwindDest());
 
   // Insert a normal call instruction.
-  std::vector<Value*> CallArgs(II->op_begin(), II->op_end() - 3);
+  std::vector<Value*> CallArgs(II->op_begin()+3, II->op_end());
   CallInst *NewCall = CallInst::Create(II->getCalledValue(),
                                        CallArgs.begin(), CallArgs.end(), "",
                                        II);

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=99171&r1=99170&r2=99171&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Mar 22 04:11:00 2010
@@ -1875,7 +1875,6 @@
     if (PAL.getFnAttributes() != Attribute::None)
       Out << ' ' << Attribute::getAsString(PAL.getFnAttributes());
   } else if (const InvokeInst *II = dyn_cast<InvokeInst>(&I)) {
-    Operand = II->getCalledValue();
     const PointerType    *PTy = cast<PointerType>(Operand->getType());
     const FunctionType   *FTy = cast<FunctionType>(PTy->getElementType());
     const Type         *RetTy = FTy->getReturnType();
@@ -1913,10 +1912,10 @@
       writeOperand(Operand, true);
     }
     Out << '(';
-    for (unsigned op = 0, Eop = I.getNumOperands() - 3; op < Eop; ++op) {
-      if (op)
+    for (unsigned op = 3, Eop = I.getNumOperands(); op < Eop; ++op) {
+      if (op > 3)
         Out << ", ";
-      writeParamOperand(I.getOperand(op), PAL.getParamAttributes(op + 1));
+      writeParamOperand(I.getOperand(op), PAL.getParamAttributes(op-2));
     }
 
     Out << ')';

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=99171&r1=99170&r2=99171&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Mon Mar 22 04:11:00 2010
@@ -98,13 +98,6 @@
   return false;
 }
 
-User::op_iterator CallSite::getCallee() const {
-  Instruction *II(getInstruction());
-  return isCall()
-    ? cast<CallInst>(II)->op_begin()
-    : cast<InvokeInst>(II)->op_end() - 3; // Skip BB, BB, Function
-}
-
 #undef CALLSITE_DELEGATE_GETTER
 #undef CALLSITE_DELEGATE_SETTER
 
@@ -618,9 +611,10 @@
 void InvokeInst::init(Value *Fn, BasicBlock *IfNormal, BasicBlock *IfException,
                       Value* const *Args, unsigned NumArgs) {
   assert(NumOperands == 3+NumArgs && "NumOperands not set up?");
-  Op<-3>() = Fn;
-  Op<-2>() = IfNormal;
-  Op<-1>() = IfException;
+  Use *OL = OperandList;
+  OL[0] = Fn;
+  OL[1] = IfNormal;
+  OL[2] = IfException;
   const FunctionType *FTy =
     cast<FunctionType>(cast<PointerType>(Fn->getType())->getElementType());
   FTy = FTy;  // silence warning.
@@ -629,13 +623,12 @@
           (FTy->isVarArg() && NumArgs > FTy->getNumParams())) &&
          "Calling a function with bad signature");
 
-  Use *OL = OperandList;
   for (unsigned i = 0, e = NumArgs; i != e; i++) {
     assert((i >= FTy->getNumParams() || 
             FTy->getParamType(i) == Args[i]->getType()) &&
            "Invoking a function with a bad signature!");
     
-    OL[i] = Args[i];
+    OL[i+3] = Args[i];
   }
 }
 

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=99171&r1=99170&r2=99171&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Mar 22 04:11:00 2010
@@ -1483,7 +1483,7 @@
                 "Instruction does not dominate all uses!", Op, &I);
       }
     } else if (isa<InlineAsm>(I.getOperand(i))) {
-      Assert1((i == 0 && isa<CallInst>(I)) || (i + 3 == e && isa<InvokeInst>(I)),
+      Assert1(i == 0 && (isa<CallInst>(I) || isa<InvokeInst>(I)),
               "Cannot take the address of an inline asm!", &I);
     }
   }




From andrewl at lenharth.org  Mon Mar 22 09:42:05 2010
From: andrewl at lenharth.org (Andrew Lenharth)
Date: Mon, 22 Mar 2010 14:42:05 -0000
Subject: [llvm-commits] [poolalloc] r99173 - in /poolalloc/trunk:
 include/dsa/DSCallGraph.h include/dsa/DSGraphTraits.h include/dsa/DSNode.h
 include/dsa/DataStructure.h include/dsa/keyiterator.h
 lib/DSA/BottomUpClosure.cpp lib/DSA/Local.cpp lib/DSA/Printer.cpp
Message-ID: <20100322144205.7369F2A6C12C@llvm.org>

Author: alenhar2
Date: Mon Mar 22 09:42:05 2010
New Revision: 99173

URL: http://llvm.org/viewvc/llvm-project?rev=99173&view=rev
Log:
simplify and update callgraph after BU

Modified:
    poolalloc/trunk/include/dsa/DSCallGraph.h
    poolalloc/trunk/include/dsa/DSGraphTraits.h
    poolalloc/trunk/include/dsa/DSNode.h
    poolalloc/trunk/include/dsa/DataStructure.h
    poolalloc/trunk/include/dsa/keyiterator.h
    poolalloc/trunk/lib/DSA/BottomUpClosure.cpp
    poolalloc/trunk/lib/DSA/Local.cpp
    poolalloc/trunk/lib/DSA/Printer.cpp

Modified: poolalloc/trunk/include/dsa/DSCallGraph.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSCallGraph.h?rev=99173&r1=99172&r2=99173&view=diff
==============================================================================
--- poolalloc/trunk/include/dsa/DSCallGraph.h (original)
+++ poolalloc/trunk/include/dsa/DSCallGraph.h Mon Mar 22 09:42:05 2010
@@ -46,6 +46,8 @@
   //Functions we know about that aren't called
   svset<const llvm::Function*> knownRoots;
 
+  svset<llvm::CallSite> completeCS;
+
   //Types for SCC construction
   typedef std::map<const llvm::Function*, unsigned> TFMap;
   typedef std::vector<const llvm::Function*> TFStack;
@@ -147,6 +149,14 @@
     return ii->second.size();
   }
 
+  void callee_mark_complete(llvm::CallSite CS) {
+    completeCS.insert(CS);
+  }
+
+  bool callee_is_complete(llvm::CallSite CS) const {
+    return completeCS.find(CS) != completeCS.end();
+  }
+
   unsigned size() const {
     unsigned sum = 0;
     for (ActualCalleesTy::const_iterator ii = ActualCallees.begin(),

Modified: poolalloc/trunk/include/dsa/DSGraphTraits.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSGraphTraits.h?rev=99173&r1=99172&r2=99173&view=diff
==============================================================================
--- poolalloc/trunk/include/dsa/DSGraphTraits.h (original)
+++ poolalloc/trunk/include/dsa/DSGraphTraits.h Mon Mar 22 09:42:05 2010
@@ -27,57 +27,42 @@
 template<typename NodeTy>
 class DSNodeIterator : public std::iterator<std::forward_iterator_tag, const DSNode, ptrdiff_t> {
   friend class DSNode;
-  NodeTy * const Node;
-  unsigned Offset;
+
+  DSNode::const_edge_iterator NH;
 
   typedef DSNodeIterator<NodeTy> _Self;
 
-  DSNodeIterator(NodeTy *N) : Node(N), Offset(0) {}   // begin iterator
-  DSNodeIterator(NodeTy *N, bool) : Node(N) {         // Create end iterator
-    if (N != 0) {
-      Offset = N->getSize();
-      if (Offset == 0 && Node->isForwarding() &&
-          Node->isDeadNode())        // Model Forward link
-        Offset += 1;
-    } else {
-      Offset = 0;
-    }
-  }
+  DSNodeIterator(NodeTy *N) : NH(N->edge_begin()) {}   // begin iterator
+  DSNodeIterator(NodeTy *N, bool) : NH(N->edge_end()) {}  // Create end iterator
+
 public:
-  DSNodeIterator(const DSNodeHandle &NH)
-    : Node(NH.getNode()), Offset(NH.getOffset()) {}
+//  DSNodeIterator(const DSNodeHandle &NH)
+//    : Node(NH.getNode()), Offset(NH.getOffset()) {}
 
   bool operator==(const _Self& x) const {
-    return Offset == x.Offset;
+    return NH == x.NH;
   }
   bool operator!=(const _Self& x) const { return !operator==(x); }
 
   const _Self &operator=(const _Self &I) {
-    assert(I.Node == Node && "Cannot assign iterators to two different nodes!");
-    Offset = I.Offset;
+    NH = I.NH;
     return *this;
   }
 
   pointer operator*() const {
-    if (Node->isDeadNode())
-      return Node->getForwardNode();
-    else if (Node->hasLink(Offset))
-      return Node->getLink(Offset).getNode();
-    else
-      return 0;
+    return NH->second.getNode();
   }
   pointer operator->() const { return operator*(); }
 
   _Self& operator++() {                // Preincrement
-    Offset += 1;
+    ++NH;
     return *this;
   }
   _Self operator++(int) { // Postincrement
     _Self tmp = *this; ++*this; return tmp;
   }
 
-  unsigned getOffset() const { return Offset; }
-  const DSNode *getNode() const { return Node; }
+  unsigned getOffset() const { return NH->first; }
 };
 
 // Provide iterators for DSNode...

Modified: poolalloc/trunk/include/dsa/DSNode.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSNode.h?rev=99173&r1=99172&r2=99173&view=diff
==============================================================================
--- poolalloc/trunk/include/dsa/DSNode.h (original)
+++ poolalloc/trunk/include/dsa/DSNode.h Mon Mar 22 09:42:05 2010
@@ -22,7 +22,8 @@
 #include <set>
 #include "dsa/svset.h"
 #include "dsa/super_set.h"
-#include "DSGraph.h"
+#include "dsa/keyiterator.h"
+#include "dsa/DSGraph.h"
 
 namespace llvm {
 

Modified: poolalloc/trunk/include/dsa/DataStructure.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DataStructure.h?rev=99173&r1=99172&r2=99173&view=diff
==============================================================================
--- poolalloc/trunk/include/dsa/DataStructure.h (original)
+++ poolalloc/trunk/include/dsa/DataStructure.h Mon Mar 22 09:42:05 2010
@@ -202,12 +202,7 @@
 class BUDataStructures : public DataStructures {
 protected:
 
-  // This map is only maintained during construction of BU Graphs
-  std::map<std::vector<const Function*>,
-           std::pair<DSGraph*, std::vector<DSNodeHandle> > > IndCallGraphMap;
-
   const char* debugname;
-  bool useCallGraph;
 
   EntryPointAnalysis* EP;
 
@@ -215,11 +210,10 @@
   static char ID;
   //Child constructor (CBU)
   BUDataStructures(intptr_t CID, const char* name, const char* printname)
-    : DataStructures(CID, printname), debugname(name), useCallGraph(true) {}
+    : DataStructures(CID, printname), debugname(name) {}
   //main constructor
   BUDataStructures() 
-    : DataStructures((intptr_t)&ID, "bu."), debugname("dsa-bu"),
-      useCallGraph(false) {}
+    : DataStructures((intptr_t)&ID, "bu."), debugname("dsa-bu") {}
   ~BUDataStructures() { releaseMemory(); }
 
   virtual bool runOnModule(Module &M);

Modified: poolalloc/trunk/include/dsa/keyiterator.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/keyiterator.h?rev=99173&r1=99172&r2=99173&view=diff
==============================================================================
--- poolalloc/trunk/include/dsa/keyiterator.h (original)
+++ poolalloc/trunk/include/dsa/keyiterator.h Mon Mar 22 09:42:05 2010
@@ -14,6 +14,161 @@
 #ifndef LLVM_KEYITERATOR_H
 #define	LLVM_KEYITERATOR_H
 
+#include <functional>
+
+//From SGI's STL
+
+// select1st and select2nd are extensions: they are not part of the standard.
+
+template <class _Pair>
+class _Select1st : public std::unary_function<_Pair, typename _Pair::first_type> {
+public:
+
+  const typename _Pair::first_type & operator()(const _Pair& __x) const {
+    return __x.first;
+  }
+};
+
+template <class _Pair>
+class _Select2nd : public std::unary_function<_Pair, typename _Pair::second_type> {
+public:
+
+  const typename _Pair::second_type & operator()(const _Pair& __x) const {
+    return __x.second;
+  }
+};
+
+template <class _Pair> class select1st : public _Select1st<_Pair> {
+};
+
+template <class _Pair> class select2nd : public _Select2nd<_Pair> {
+};
+
+
+// ref_mapped_iterator - This is a simple iterator adapter that causes a
+// function to be dereferenced whenever operator* is invoked on the iterator.
+// It is assumed that the function returns a valid reference, which differs
+// from llvm::mapped_iterator from which this was derived (copied)
+
+template <class RootIt, class UnaryFunc>
+class ref_mapped_iterator {
+  RootIt current;
+  UnaryFunc Fn;
+public:
+  typedef typename std::iterator_traits<RootIt>::iterator_category
+  iterator_category;
+  typedef typename std::iterator_traits<RootIt>::difference_type
+  difference_type;
+  typedef typename UnaryFunc::result_type value_type;
+
+  typedef typename UnaryFunc::result_type *pointer;
+  typedef typename UnaryFunc::result_type& reference;
+
+  typedef RootIt iterator_type;
+  typedef ref_mapped_iterator<RootIt, UnaryFunc> _Self;
+
+  inline const RootIt &getCurrent() const {
+    return current;
+  }
+
+  inline const UnaryFunc &getFunc() const {
+    return Fn;
+  }
+
+  inline explicit ref_mapped_iterator(const RootIt &I, UnaryFunc F)
+  : current(I), Fn(F) { }
+
+  inline ref_mapped_iterator(const ref_mapped_iterator &It)
+  : current(It.current), Fn(It.Fn) { }
+
+  inline reference operator*() const { // All this work to do this
+    return Fn(*current); // little change
+  }
+
+  _Self & operator++() {
+    ++current;
+    return *this;
+  }
+
+  _Self & operator--() {
+    --current;
+    return *this;
+  }
+
+  _Self operator++(int) {
+    _Self __tmp = *this;
+    ++current;
+    return __tmp;
+  }
+
+  _Self operator--(int) {
+    _Self __tmp = *this;
+    --current;
+    return __tmp;
+  }
+
+  _Self operator+(difference_type n) const {
+    return _Self(current + n, Fn);
+  }
+
+  _Self & operator+=(difference_type n) {
+    current += n;
+    return *this;
+  }
+
+  _Self operator-(difference_type n) const {
+    return _Self(current - n, Fn);
+  }
+
+  _Self & operator-=(difference_type n) {
+    current -= n;
+    return *this;
+  }
+
+  reference operator[](difference_type n) const {
+    return *(*this +n);
+  }
+
+  inline bool operator!=(const _Self &X) const {
+    return !operator==(X);
+  }
+
+  inline bool operator==(const _Self &X) const {
+    return current == X.current;
+  }
+
+  inline bool operator<(const _Self &X) const {
+    return current < X.current;
+  }
+
+  inline difference_type operator-(const _Self &X) const {
+    return current - X.current;
+  }
+};
+
+template <class Iter>
+class KeyIterator
+: public ref_mapped_iterator<Iter, select1st<typename Iter::value_type> > {
+  typedef select1st<typename Iter::value_type> FunTy;
+public:
+
+  KeyIterator(const Iter I)
+  : ref_mapped_iterator<Iter, select1st<typename Iter::value_type> >(I, FunTy()) { }
+};
+
+template <class Iter>
+class ValueIterator
+: public ref_mapped_iterator<Iter, select2nd<typename Iter::value_type> > {
+  typedef select2nd<typename Iter::value_type> FunTy;
+public:
+
+  ValueIterator(const Iter I)
+  : ref_mapped_iterator<Iter, select2nd<typename Iter::value_type> >(I, FunTy()) { }
+};
+
+
+#if 0
+
 template<class Iter>
 class KeyIterator {
   Iter I;
@@ -87,6 +242,8 @@
     return I != RHS.I;
   }
 };
+#endif
+
 
 #endif	/* LLVM_KEYITERATOR_H */
 

Modified: poolalloc/trunk/lib/DSA/BottomUpClosure.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/BottomUpClosure.cpp?rev=99173&r1=99172&r2=99173&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/BottomUpClosure.cpp (original)
+++ poolalloc/trunk/lib/DSA/BottomUpClosure.cpp Mon Mar 22 09:42:05 2010
@@ -83,56 +83,10 @@
   }
 
 
-  return false;
-
-  std::vector<const Function*> EntryPoints;
-  EP = &getAnalysis<EntryPointAnalysis>();
-  EP->findEntryPoints(M, EntryPoints);
-
-  #if 0
-
-  std::vector<const Function*> Stack;
-  std::map<const Function*, unsigned> ValMap;
-  unsigned NextID = 1;
-
   std::vector<const Function*> EntryPoints;
   EP = &getAnalysis<EntryPointAnalysis>();
   EP->findEntryPoints(M, EntryPoints);
 
-  for (std::vector<const Function*>::iterator ii = EntryPoints.begin(),
-          ee = EntryPoints.end(); ii != ee; ++ii)
-    if (!hasDSGraph(**ii)) {
-      errs() << debugname << ": Main Function: " << (*ii)->getName() << "\n";
-      calculateGraphs(*ii, Stack, NextID, ValMap);
-      //CloneAuxIntoGlobal(getDSGraph(**ii));
-    }
-
-  errs() << "done main Funcs\n";
-
-  // Calculate the graphs for any functions that are unreachable from main...
-  for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
-    if (!I->isDeclaration() && !hasDSGraph(*I)) {
-      //DEBUG(
-            if (EntryPoints.size())
-            errs() << debugname << ": Function unreachable from main: "
-            << I->getName() << "\n";
-      //);
-      calculateGraphs(I, Stack, NextID, ValMap); // Calculate all graphs.
-      //CloneAuxIntoGlobal(getDSGraph(*I));
-    }
-
-  errs() << "done unreachable Funcs\n";
-  #endif
-
-  // If we computed any temporary indcallgraphs, free them now.
-  for (std::map<std::vector<const Function*>,
-         std::pair<DSGraph*, std::vector<DSNodeHandle> > >::iterator I =
-         IndCallGraphMap.begin(), E = IndCallGraphMap.end(); I != E; ++I) {
-    I->second.second.clear();  // Drop arg refs into the graph.
-    delete I->second.first;
-  }
-  IndCallGraphMap.clear();
-
   // At the end of the bottom-up pass, the globals graph becomes complete.
   // FIXME: This is not the right way to do this, but it is sorta better than
   // nothing!  In particular, externally visible globals and unresolvable call
@@ -216,6 +170,8 @@
 
   marked.insert(F);
   calculateGraph(G);
+  //once calculated, we can update the callgraph
+  G->buildCallGraph(callgraph);
   return G;
 }
 
@@ -278,25 +234,6 @@
 void BUDataStructures::calculateGraph(DSGraph* Graph) {
   DEBUG(Graph->AssertGraphOK(); Graph->getGlobalsGraph()->AssertGraphOK());
 
-  // If this graph contains the main function, clone the globals graph into this
-  // graph before we inline callees and other fun stuff.
-  bool ContainsMain = false;
-  DSGraph::ReturnNodesTy &ReturnNodes = Graph->getReturnNodes();
-
-  for (DSGraph::ReturnNodesTy::iterator I = ReturnNodes.begin(),
-       E = ReturnNodes.end(); I != E; ++I)
-    if (EP->isEntryPoint(I->first)) {
-      ContainsMain = true;
-      break;
-    }
-
-   // If this graph contains main, copy the contents of the globals graph over.
-   // Note that this is *required* for correctness.  If a callee contains a use
-   // of a global, we have to make sure to link up nodes due to global-argument
-   // bindings.
-   if (ContainsMain)
-    cloneGlobalsInto(Graph);
-
   // Move our call site list into TempFCs so that inline call sites go into the
   // new call site list and doesn't invalidate our iterators!
   std::list<DSCallSite> TempFCs;
@@ -410,8 +347,7 @@
   // Clone the global nodes into this graph.
   for (DSScalarMap::global_iterator I = Graph->getScalarMap().global_begin(),
        E = Graph->getScalarMap().global_end(); I != E; ++I)
-    if (isa<GlobalVariable > (*I))
-      RC.getClonedNH(GG->getNodeForValue(*I));
+    RC.getClonedNH(GG->getNodeForValue(*I));
 }
 
 //For all graphs

Modified: poolalloc/trunk/lib/DSA/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=99173&r1=99172&r2=99173&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/Local.cpp (original)
+++ poolalloc/trunk/lib/DSA/Local.cpp Mon Mar 22 09:42:05 2010
@@ -953,10 +953,12 @@
     // Add initializers for all of the globals to the globals graph.
     for (Module::global_iterator I = M.global_begin(), E = M.global_end();
          I != E; ++I)
-      if (I->isDeclaration())
-        GGB.mergeExternalGlobal(I);
-      else
-        GGB.mergeInGlobalInitializer(I);
+      if (!(I->hasSection() && I->getSection() == "llvm.metadata")) {
+        if (I->isDeclaration())
+          GGB.mergeExternalGlobal(I);
+        else
+          GGB.mergeInGlobalInitializer(I);
+      }
     // Add Functions to the globals graph.
     for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
       if (I->hasAddressTaken())

Modified: poolalloc/trunk/lib/DSA/Printer.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Printer.cpp?rev=99173&r1=99172&r2=99173&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/Printer.cpp (original)
+++ poolalloc/trunk/lib/DSA/Printer.cpp Mon Mar 22 09:42:05 2010
@@ -145,18 +145,21 @@
 
   static bool edgeTargetsEdgeSource(const void *Node,
                                     DSNode::const_iterator I) {
-    unsigned O = I.getNode()->getLink(I.getOffset()).getOffset();
+    unsigned O = I->getLink(I.getOffset()).getOffset();
     return O != 0;
   }
 
   static std::string getEdgeSourceLabel(const void* Node,
                                         DSNode::const_iterator I) {
-    return "*";
+    std::string S;
+    llvm::raw_string_ostream O(S);
+    O << I.getOffset();
+    return O.str();
   }
 
   static DSNode::const_iterator getEdgeTarget(const DSNode *Node,
                                               DSNode::const_iterator I) {
-    unsigned O = I.getNode()->getLink(I.getOffset()).getOffset();
+    unsigned O = I->getLink(I.getOffset()).getOffset();
     unsigned LinkNo = O;
     const DSNode *N = *I;
     DSNode::const_iterator R = N->begin();




From jyasskin at google.com  Mon Mar 22 10:56:04 2010
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Mon, 22 Mar 2010 15:56:04 -0000
Subject: [llvm-commits] [llvm] r99180 - /llvm/trunk/tools/opt/opt.cpp
Message-ID: <20100322155604.784612A6C12C@llvm.org>

Author: jyasskin
Date: Mon Mar 22 10:56:04 2010
New Revision: 99180

URL: http://llvm.org/viewvc/llvm-project?rev=99180&view=rev
Log:
Avoid leaking the FunctionPassManager from opt.

Modified:
    llvm/trunk/tools/opt/opt.cpp

Modified: llvm/trunk/tools/opt/opt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=99180&r1=99179&r2=99180&view=diff
==============================================================================
--- llvm/trunk/tools/opt/opt.cpp (original)
+++ llvm/trunk/tools/opt/opt.cpp Mon Mar 22 10:56:04 2010
@@ -424,9 +424,9 @@
   if (TD)
     Passes.add(TD);
 
-  FunctionPassManager *FPasses = NULL;
+  OwningPtr<FunctionPassManager> FPasses;
   if (OptLevelO1 || OptLevelO2 || OptLevelO3) {
-    FPasses = new FunctionPassManager(M.get());
+    FPasses.reset(new FunctionPassManager(M.get()));
     if (TD)
       FPasses->add(new TargetData(*TD));
   }




From jyasskin at google.com  Mon Mar 22 11:13:21 2010
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Mon, 22 Mar 2010 16:13:21 -0000
Subject: [llvm-commits] [llvm] r99182 -
	/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
Message-ID: <20100322161321.78A602A6C12C@llvm.org>

Author: jyasskin
Date: Mon Mar 22 11:13:21 2010
New Revision: 99182

URL: http://llvm.org/viewvc/llvm-project?rev=99182&view=rev
Log:
Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=99182&r1=99181&r2=99182&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Mon Mar 22 11:13:21 2010
@@ -200,6 +200,8 @@
   // It's illegal to emit pop instruction without operands.
   if (NumRegs)
     MBB.insert(MI, &*MIB);
+  else
+    MF.DeleteMachineInstr(MIB);
 
   return true;
 }




From stoklund at 2pi.dk  Mon Mar 22 11:30:04 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 22 Mar 2010 16:30:04 -0000
Subject: [llvm-commits] [llvm] r99183 -
	/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td
Message-ID: <20100322163004.AF8492A6C12C@llvm.org>

Author: stoklund
Date: Mon Mar 22 11:30:04 2010
New Revision: 99183

URL: http://llvm.org/viewvc/llvm-project?rev=99183&view=rev
Log:
Completely remove Blackfin patterns that thought JustCC was i1.

Thanks, Chris!

Modified:
    llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td?rev=99183&r1=99182&r2=99183&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td Mon Mar 22 11:30:04 2010
@@ -610,8 +610,7 @@
                     "cc = !cc;", []>;
 
 def MOVECC_zext : F1<(outs D:$dst), (ins JustCC:$cc),
-                      "$dst = $cc;",
-                     [/*(set D:$dst, (zext JustCC:$cc))*/]>;
+                      "$dst = $cc;", []>;
 
 def MOVENCC_z : F1<(outs D:$dst), (ins NotCC:$cc),
                    "$dst = cc;", []>;
@@ -859,17 +858,5 @@
           (CALLa tglobaladdr:$dst)>;
 def : Pat<(BfinCall (i32 texternalsym:$dst)),
           (CALLa texternalsym:$dst)>;
-
-//def : Pat<(sext JustCC:$cc),
-//          (NEG (MOVECC_zext JustCC:$cc))>;
-//def : Pat<(anyext JustCC:$cc),
-//          (MOVECC_zext JustCC:$cc)>;
-def : Pat<(i16 (zext JustCC:$cc)),
-          (EXTRACT_SUBREG (MOVECC_zext JustCC:$cc), bfin_subreg_lo16)>;
-def : Pat<(i16 (sext JustCC:$cc)),
-          (EXTRACT_SUBREG (NEG (MOVECC_zext JustCC:$cc)), bfin_subreg_lo16)>;
-def : Pat<(i16 (anyext JustCC:$cc)),
-          (EXTRACT_SUBREG (MOVECC_zext JustCC:$cc), bfin_subreg_lo16)>;
-
 def : Pat<(i16 (trunc D:$src)),
           (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS D:$src, D)), bfin_subreg_lo16)>;




From bob.wilson at apple.com  Mon Mar 22 11:43:11 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 22 Mar 2010 16:43:11 -0000
Subject: [llvm-commits] [llvm] r99185 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20100322164311.360132A6C12C@llvm.org>

Author: bwilson
Date: Mon Mar 22 11:43:10 2010
New Revision: 99185

URL: http://llvm.org/viewvc/llvm-project?rev=99185&view=rev
Log:
Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to
specify encoding bits in arguments instead of "let" expressions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99185&r1=99184&r2=99185&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Mar 22 11:43:10 2010
@@ -383,62 +383,62 @@
 //   FIXME: Not yet implemented.
 
 //   VLD2LN   : Vector Load (single 2-element structure to one lane)
-class VLD2LN<bits<4> op11_8, string Dt>
-  : NLdSt<1, 0b10, op11_8, {?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
+class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
+  : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
           (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
           IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
           "$src1 = $dst1, $src2 = $dst2", []>;
 
-def VLD2LNd8  : VLD2LN<0b0001, "8">;
-def VLD2LNd16 : VLD2LN<0b0101, "16"> { let Inst{5} = 0; }
-def VLD2LNd32 : VLD2LN<0b1001, "32"> { let Inst{6} = 0; }
+def VLD2LNd8  : VLD2LN<0b0001, {?,?,?,?}, "8">;
+def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">;
+def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">;
 
 // ...with double-spaced registers:
-def VLD2LNq16 : VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
-def VLD2LNq32 : VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
+def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">;
+def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">;
 
 // ...alternate versions to be allocated odd register numbers:
-def VLD2LNq16odd : VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
-def VLD2LNq32odd : VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
+def VLD2LNq16odd : VLD2LN<0b0101, {?,?,1,?}, "16">;
+def VLD2LNq32odd : VLD2LN<0b1001, {?,1,?,?}, "32">;
 
 // ...with address register writeback:
-class VLD2LNWB<bits<4> op11_8, string Dt>
-  : NLdSt<1, 0b10, op11_8, {?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
+class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
+  : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
           (ins addrmode6:$addr, am6offset:$offset,
            DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, "vld2", Dt,
           "\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset",
           "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>;
 
-def VLD2LNd8_UPD  : VLD2LNWB<0b0001, "8">;
-def VLD2LNd16_UPD : VLD2LNWB<0b0101, "16"> { let Inst{5} = 0; }
-def VLD2LNd32_UPD : VLD2LNWB<0b1001, "32"> { let Inst{6} = 0; }
+def VLD2LNd8_UPD  : VLD2LNWB<0b0001, {?,?,?,?}, "8">;
+def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">;
+def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">;
 
-def VLD2LNq16_UPD : VLD2LNWB<0b0101, "16"> { let Inst{5} = 1; }
-def VLD2LNq32_UPD : VLD2LNWB<0b1001, "32"> { let Inst{6} = 1; }
+def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">;
+def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">;
 
 //   VLD3LN   : Vector Load (single 3-element structure to one lane)
-class VLD3LN<bits<4> op11_8, string Dt>
-  : NLdSt<1, 0b10, op11_8, {?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
+class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
+  : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
           (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
           nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
           "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
           "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
 
-def VLD3LNd8  : VLD3LN<0b0010, "8"> { let Inst{4} = 0; }
-def VLD3LNd16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
-def VLD3LNd32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
+def VLD3LNd8  : VLD3LN<0b0010, {?,?,?,0}, "8">;
+def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">;
+def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">;
 
 // ...with double-spaced registers:
-def VLD3LNq16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
-def VLD3LNq32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
+def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">;
+def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">;
 
 // ...alternate versions to be allocated odd register numbers:
-def VLD3LNq16odd : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
-def VLD3LNq32odd : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
+def VLD3LNq16odd : VLD3LN<0b0110, {?,?,1,0}, "16">;
+def VLD3LNq32odd : VLD3LN<0b1010, {?,1,0,0}, "32">;
 
 // ...with address register writeback:
-class VLD3LNWB<bits<4> op11_8, string Dt>
-  : NLdSt<1, 0b10, op11_8, {?,?,?,?},
+class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
+  : NLdSt<1, 0b10, op11_8, op7_4,
           (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
           (ins addrmode6:$addr, am6offset:$offset,
            DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
@@ -447,37 +447,37 @@
           "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb",
           []>;
 
-def VLD3LNd8_UPD  : VLD3LNWB<0b0010, "8"> { let Inst{4} = 0; }
-def VLD3LNd16_UPD : VLD3LNWB<0b0110, "16"> { let Inst{5-4} = 0b00; }
-def VLD3LNd32_UPD : VLD3LNWB<0b1010, "32"> { let Inst{6-4} = 0b000; }
+def VLD3LNd8_UPD  : VLD3LNWB<0b0010, {?,?,?,0}, "8">;
+def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">;
+def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">;
 
-def VLD3LNq16_UPD : VLD3LNWB<0b0110, "16"> { let Inst{5-4} = 0b10; }
-def VLD3LNq32_UPD : VLD3LNWB<0b1010, "32"> { let Inst{6-4} = 0b100; }
+def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">;
+def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">;
 
 //   VLD4LN   : Vector Load (single 4-element structure to one lane)
-class VLD4LN<bits<4> op11_8, string Dt>
-  : NLdSt<1, 0b10, op11_8, {?,?,?,?},
+class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
+  : NLdSt<1, 0b10, op11_8, op7_4,
           (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
           (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
           nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
           "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
           "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
 
-def VLD4LNd8  : VLD4LN<0b0011, "8">;
-def VLD4LNd16 : VLD4LN<0b0111, "16"> { let Inst{5} = 0; }
-def VLD4LNd32 : VLD4LN<0b1011, "32"> { let Inst{6} = 0; }
+def VLD4LNd8  : VLD4LN<0b0011, {?,?,?,?}, "8">;
+def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16">;
+def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32">;
 
 // ...with double-spaced registers:
-def VLD4LNq16 : VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
-def VLD4LNq32 : VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
+def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16">;
+def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32">;
 
 // ...alternate versions to be allocated odd register numbers:
-def VLD4LNq16odd : VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
-def VLD4LNq32odd : VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
+def VLD4LNq16odd : VLD4LN<0b0111, {?,?,1,?}, "16">;
+def VLD4LNq32odd : VLD4LN<0b1011, {?,1,?,?}, "32">;
 
 // ...with address register writeback:
-class VLD4LNWB<bits<4> op11_8, string Dt>
-  : NLdSt<1, 0b10, op11_8, {?,?,?,?},
+class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
+  : NLdSt<1, 0b10, op11_8, op7_4,
           (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
           (ins addrmode6:$addr, am6offset:$offset,
            DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
@@ -486,12 +486,12 @@
 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb",
           []>;
 
-def VLD4LNd8_UPD  : VLD4LNWB<0b0011, "8">;
-def VLD4LNd16_UPD : VLD4LNWB<0b0111, "16"> { let Inst{5} = 0; }
-def VLD4LNd32_UPD : VLD4LNWB<0b1011, "32"> { let Inst{6} = 0; }
+def VLD4LNd8_UPD  : VLD4LNWB<0b0011, {?,?,?,?}, "8">;
+def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16">;
+def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32">;
 
-def VLD4LNq16_UPD : VLD4LNWB<0b0111, "16"> { let Inst{5} = 1; }
-def VLD4LNq32_UPD : VLD4LNWB<0b1011, "32"> { let Inst{6} = 1; }
+def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16">;
+def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
 
 //   VLD1DUP  : Vector Load (single element to all lanes)
 //   VLD2DUP  : Vector Load (single 2-element structure to all lanes)
@@ -745,109 +745,109 @@
 //   FIXME: Not yet implemented.
 
 //   VST2LN   : Vector Store (single 2-element structure from one lane)
-class VST2LN<bits<4> op11_8, string Dt>
-  : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
+class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
+  : NLdSt<1, 0b00, op11_8, op7_4, (outs),
           (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
           IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
           "", []>;
 
-def VST2LNd8  : VST2LN<0b0001, "8">;
-def VST2LNd16 : VST2LN<0b0101, "16"> { let Inst{5} = 0; }
-def VST2LNd32 : VST2LN<0b1001, "32"> { let Inst{6} = 0; }
+def VST2LNd8  : VST2LN<0b0001, {?,?,?,?}, "8">;
+def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16">;
+def VST2LNd32 : VST2LN<0b1001, {?,0,?,?}, "32">;
 
 // ...with double-spaced registers:
-def VST2LNq16 : VST2LN<0b0101, "16"> { let Inst{5} = 1; }
-def VST2LNq32 : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
+def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16">;
+def VST2LNq32 : VST2LN<0b1001, {?,1,?,?}, "32">;
 
 // ...alternate versions to be allocated odd register numbers:
-def VST2LNq16odd : VST2LN<0b0101, "16"> { let Inst{5} = 1; }
-def VST2LNq32odd : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
+def VST2LNq16odd : VST2LN<0b0101, {?,?,1,?}, "16">;
+def VST2LNq32odd : VST2LN<0b1001, {?,1,?,?}, "32">;
 
 // ...with address register writeback:
-class VST2LNWB<bits<4> op11_8, string Dt>
-  : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs GPR:$wb),
+class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
+  : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
           (ins addrmode6:$addr, am6offset:$offset,
            DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST, "vst2", Dt,
           "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
           "$addr.addr = $wb", []>;
 
-def VST2LNd8_UPD  : VST2LNWB<0b0001, "8">;
-def VST2LNd16_UPD : VST2LNWB<0b0101, "16"> { let Inst{5} = 0; }
-def VST2LNd32_UPD : VST2LNWB<0b1001, "32"> { let Inst{6} = 0; }
+def VST2LNd8_UPD  : VST2LNWB<0b0001, {?,?,?,?}, "8">;
+def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16">;
+def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,?,?}, "32">;
 
-def VST2LNq16_UPD : VST2LNWB<0b0101, "16"> { let Inst{5} = 1; }
-def VST2LNq32_UPD : VST2LNWB<0b1001, "32"> { let Inst{6} = 1; }
+def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16">;
+def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,?,?}, "32">;
 
 //   VST3LN   : Vector Store (single 3-element structure from one lane)
-class VST3LN<bits<4> op11_8, string Dt>
-  : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
+class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
+  : NLdSt<1, 0b00, op11_8, op7_4, (outs),
           (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
            nohash_imm:$lane), IIC_VST, "vst3", Dt,
           "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
 
-def VST3LNd8  : VST3LN<0b0010, "8"> { let Inst{4} = 0; }
-def VST3LNd16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
-def VST3LNd32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
+def VST3LNd8  : VST3LN<0b0010, {?,?,?,0}, "8">;
+def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16">;
+def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32">;
 
 // ...with double-spaced registers:
-def VST3LNq16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
-def VST3LNq32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
+def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16">;
+def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32">;
 
 // ...alternate versions to be allocated odd register numbers:
-def VST3LNq16odd : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
-def VST3LNq32odd : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
+def VST3LNq16odd : VST3LN<0b0110, {?,?,1,0}, "16">;
+def VST3LNq32odd : VST3LN<0b1010, {?,1,0,0}, "32">;
 
 // ...with address register writeback:
-class VST3LNWB<bits<4> op11_8, string Dt>
-  : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs GPR:$wb),
+class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
+  : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
           (ins addrmode6:$addr, am6offset:$offset,
            DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
           IIC_VST, "vst3", Dt,
           "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset",
           "$addr.addr = $wb", []>;
 
-def VST3LNd8_UPD  : VST3LNWB<0b0010, "8"> { let Inst{4} = 0; }
-def VST3LNd16_UPD : VST3LNWB<0b0110, "16"> { let Inst{5-4} = 0b00; }
-def VST3LNd32_UPD : VST3LNWB<0b1010, "32"> { let Inst{6-4} = 0b000; }
+def VST3LNd8_UPD  : VST3LNWB<0b0010, {?,?,?,0}, "8">;
+def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16">;
+def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32">;
 
-def VST3LNq16_UPD : VST3LNWB<0b0110, "16"> { let Inst{5-4} = 0b10; }
-def VST3LNq32_UPD : VST3LNWB<0b1010, "32"> { let Inst{6-4} = 0b100; }
+def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16">;
+def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32">;
 
 //   VST4LN   : Vector Store (single 4-element structure from one lane)
-class VST4LN<bits<4> op11_8, string Dt>
-  : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
+class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
+  : NLdSt<1, 0b00, op11_8, op7_4, (outs),
           (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
            nohash_imm:$lane), IIC_VST, "vst4", Dt,
           "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
           "", []>;
 
-def VST4LNd8  : VST4LN<0b0011, "8">;
-def VST4LNd16 : VST4LN<0b0111, "16"> { let Inst{5} = 0; }
-def VST4LNd32 : VST4LN<0b1011, "32"> { let Inst{6} = 0; }
+def VST4LNd8  : VST4LN<0b0011, {?,?,?,?}, "8">;
+def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16">;
+def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32">;
 
 // ...with double-spaced registers:
-def VST4LNq16 : VST4LN<0b0111, "16"> { let Inst{5} = 1; }
-def VST4LNq32 : VST4LN<0b1011, "32"> { let Inst{6} = 1; }
+def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16">;
+def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32">;
 
 // ...alternate versions to be allocated odd register numbers:
-def VST4LNq16odd : VST4LN<0b0111, "16"> { let Inst{5} = 1; }
-def VST4LNq32odd : VST4LN<0b1011, "32"> { let Inst{6} = 1; }
+def VST4LNq16odd : VST4LN<0b0111, {?,?,1,?}, "16">;
+def VST4LNq32odd : VST4LN<0b1011, {?,1,?,?}, "32">;
 
 // ...with address register writeback:
-class VST4LNWB<bits<4> op11_8, string Dt>
-  : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs GPR:$wb),
+class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
+  : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
           (ins addrmode6:$addr, am6offset:$offset,
            DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
           IIC_VST, "vst4", Dt,
   "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset",
           "$addr.addr = $wb", []>;
 
-def VST4LNd8_UPD  : VST4LNWB<0b0011, "8">;
-def VST4LNd16_UPD : VST4LNWB<0b0111, "16"> { let Inst{5} = 0; }
-def VST4LNd32_UPD : VST4LNWB<0b1011, "32"> { let Inst{6} = 0; }
+def VST4LNd8_UPD  : VST4LNWB<0b0011, {?,?,?,?}, "8">;
+def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16">;
+def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">;
 
-def VST4LNq16_UPD : VST4LNWB<0b0111, "16"> { let Inst{5} = 1; }
-def VST4LNq32_UPD : VST4LNWB<0b1011, "32"> { let Inst{6} = 1; }
+def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">;
+def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">;
 
 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
 




From gohman at apple.com  Mon Mar 22 11:59:44 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 22 Mar 2010 16:59:44 -0000
Subject: [llvm-commits] [llvm] r99186 - /llvm/trunk/tools/llc/llc.cpp
Message-ID: <20100322165944.B23572A6C12C@llvm.org>

Author: djg
Date: Mon Mar 22 11:59:44 2010
New Revision: 99186

URL: http://llvm.org/viewvc/llvm-project?rev=99186&view=rev
Log:
llc doesn't need LinkAllVMCore.

Modified:
    llvm/trunk/tools/llc/llc.cpp

Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=99186&r1=99185&r2=99186&view=diff
==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Mon Mar 22 11:59:44 2010
@@ -23,7 +23,6 @@
 #include "llvm/CodeGen/LinkAllAsmWriterComponents.h"
 #include "llvm/CodeGen/LinkAllCodegenComponents.h"
 #include "llvm/Config/config.h"
-#include "llvm/LinkAllVMCore.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/FileUtilities.h"




From evan.cheng at apple.com  Mon Mar 22 12:57:53 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 22 Mar 2010 10:57:53 -0700
Subject: [llvm-commits] [llvm] r98889 - in /llvm/trunk/lib/Target/ARM:
	ARMISelLowering.cpp ARMISelLowering.h
	ARMInstrFormats.td	ARMInstrInfo.td ARMInstrNEON.td ARMInstrVFP.td
In-Reply-To: <b087fca01003191517g2196797bj632be6b3fbe20fdf@mail.gmail.com>
References: <20100318223545.834B62A6C12C@llvm.org>
	<C52E9734-75A2-498A-9DD5-E4D81BD50D13@apple.com>
	<b087fca01003191517g2196797bj632be6b3fbe20fdf@mail.gmail.com>
Message-ID: <4794B6D7-F3D7-40FC-9DBE-3D43B508A88B@apple.com>


On Mar 19, 2010, at 3:17 PM, Anton Korobeynikov wrote:

> Hi, Bob
> 
>> This looks like a nice cleanup but it is causing performance regressions.  Since I don't get the impression from your commit message that this is critical to your work, I'm going to revert it for now.  If I can find a small testcase, I will certainly send it to you.  Otherwise, I may see if I can figure out what's going wrong.  Basically I'm seeing lots of things like:
>> 
>>        vmov    r2, s2
>>        vmov    s2, r2
> Hrm, maybe we need to teach cross-rc coalescer to remove these moves away?

Can't. Each of these moves by itself is not a nop.

Evan

> 
> -- 
> With best regards, Anton Korobeynikov
> Faculty of Mathematics and Mechanics, Saint Petersburg State University
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From bob.wilson at apple.com  Mon Mar 22 13:02:38 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 22 Mar 2010 18:02:38 -0000
Subject: [llvm-commits] [llvm] r99187 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20100322180238.95BEA2A6C12F@llvm.org>

Author: bwilson
Date: Mon Mar 22 13:02:38 2010
New Revision: 99187

URL: http://llvm.org/viewvc/llvm-project?rev=99187&view=rev
Log:
Remove some redundant instruction classes.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99187&r1=99186&r2=99187&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Mar 22 13:02:38 2010
@@ -190,46 +190,43 @@
 class VLD1D3<bits<4> op7_4, string Dt>
   : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
           (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
-          "\\{$dst1, $dst2, $dst3\\}, $addr", "",
-          [/* For disassembly only; pattern left blank */]>;
+          "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
 class VLD1D4<bits<4> op7_4, string Dt>
   : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
           (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
-          "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "",
-          [/* For disassembly only; pattern left blank */]>;
+          "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
 
 def  VLD1d8T  : VLD1D3<0b0000, "8">;
 def  VLD1d16T : VLD1D3<0b0100, "16">;
 def  VLD1d32T : VLD1D3<0b1000, "32">;
-//   VLD1d64T : implemented as VLD3d64
+def  VLD3d64  : VLD1D3<0b1100, "64">;
 
 def  VLD1d8Q  : VLD1D4<0b0000, "8">;
 def  VLD1d16Q : VLD1D4<0b0100, "16">;
 def  VLD1d32Q : VLD1D4<0b1000, "32">;
-//   VLD1d64Q : implemented as VLD4d64
+def  VLD4d64  : VLD1D4<0b1100, "64">;
 
 // ...with address register writeback:
 class VLD1D3WB<bits<4> op7_4, string Dt>
   : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
           (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
-          "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb",
-          [/* For disassembly only; pattern left blank */]>;
+          "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
 class VLD1D4WB<bits<4> op7_4, string Dt>
   : NLdSt<0,0b10,0b0010,op7_4,
           (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
           (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
           "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
-          [/* For disassembly only; pattern left blank */]>;
+          []>;
 
 def VLD1d8T_UPD  : VLD1D3WB<0b0000, "8">;
 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
-//  VLD1d64T_UPD : implemented as VLD3d64_UPD
+def VLD3d64_UPD  : VLD1D3WB<0b1100, "64">;
 
 def VLD1d8Q_UPD  : VLD1D4WB<0b0000, "8">;
 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
 def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
-//  VLD1d64Q_UPD : implemented as VLD4d64_UPD
+def VLD4d64_UPD  : VLD1D4WB<0b1100, "64">;
 
 //   VLD2     : Vector Load (multiple 2-element structures)
 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
@@ -296,10 +293,6 @@
 def  VLD3d8   : VLD3D<0b0100, 0b0000, "8">;
 def  VLD3d16  : VLD3D<0b0100, 0b0100, "16">;
 def  VLD3d32  : VLD3D<0b0100, 0b1000, "32">;
-def  VLD3d64  : NLdSt<0,0b10,0b0110,0b1100,
-                      (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
-                      (ins addrmode6:$addr), IIC_VLD1,
-                      "vld1", "64", "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
 
 // ...with address register writeback:
 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
@@ -312,11 +305,6 @@
 def VLD3d8_UPD  : VLD3DWB<0b0100, 0b0000, "8">;
 def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
 def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
-def VLD3d64_UPD : NLdSt<0,0b10,0b0110,0b1100,
-                        (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
-                        (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
-                        "vld1", "64", "\\{$dst1, $dst2, $dst3\\}, $addr$offset",
-                        "$addr.addr = $wb", []>;
 
 // ...with double-spaced registers (non-updating versions for disassembly only):
 def VLD3q8      : VLD3D<0b0101, 0b0000, "8">;
@@ -341,11 +329,6 @@
 def  VLD4d8   : VLD4D<0b0000, 0b0000, "8">;
 def  VLD4d16  : VLD4D<0b0000, 0b0100, "16">;
 def  VLD4d32  : VLD4D<0b0000, 0b1000, "32">;
-def  VLD4d64  : NLdSt<0,0b10,0b0010,0b1100,
-                      (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
-                      (ins addrmode6:$addr), IIC_VLD1,
-                      "vld1", "64", "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
-                      "", []>;
 
 // ...with address register writeback:
 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
@@ -358,13 +341,6 @@
 def VLD4d8_UPD  : VLD4DWB<0b0000, 0b0000, "8">;
 def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
 def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
-def VLD4d64_UPD : NLdSt<0,0b10,0b0010,0b1100,
-                        (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4,
-                         GPR:$wb),
-                        (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
-                        "vld1", "64",
-                        "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
-                        "$addr.addr = $wb", []>;
 
 // ...with double-spaced registers (non-updating versions for disassembly only):
 def VLD4q8      : VLD4D<0b0001, 0b0000, "8">;
@@ -550,23 +526,22 @@
 class VST1D3<bits<4> op7_4, string Dt>
   : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
           (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
-          IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "",
-          [/* For disassembly only; pattern left blank */]>;
+          IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
 class VST1D4<bits<4> op7_4, string Dt>
   : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
           (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
           IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
-          [/* For disassembly only; pattern left blank */]>;
+          []>;
 
 def  VST1d8T  : VST1D3<0b0000, "8">;
 def  VST1d16T : VST1D3<0b0100, "16">;
 def  VST1d32T : VST1D3<0b1000, "32">;
-//   VST1d64T : implemented as VST3d64
+def  VST3d64  : VST1D3<0b1100, "64">;
 
 def  VST1d8Q  : VST1D4<0b0000, "8">;
 def  VST1d16Q : VST1D4<0b0100, "16">;
 def  VST1d32Q : VST1D4<0b1000, "32">;
-//   VST1d64Q : implemented as VST4d64
+def  VST4d64  : VST1D4<0b1100, "64">;
 
 // ...with address register writeback:
 class VST1D3WB<bits<4> op7_4, string Dt>
@@ -574,25 +549,23 @@
           (ins addrmode6:$addr, am6offset:$offset,
            DPR:$src1, DPR:$src2, DPR:$src3),
           IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
-          "$addr.addr = $wb",
-          [/* For disassembly only; pattern left blank */]>;
+          "$addr.addr = $wb", []>;
 class VST1D4WB<bits<4> op7_4, string Dt>
   : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
           (ins addrmode6:$addr, am6offset:$offset,
            DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
           IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
-          "$addr.addr = $wb",
-          [/* For disassembly only; pattern left blank */]>;
+          "$addr.addr = $wb", []>;
 
 def VST1d8T_UPD  : VST1D3WB<0b0000, "8">;
 def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
 def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
-//  VST1d64T_UPD : implemented as VST3d64_UPD
+def VST3d64_UPD  : VST1D3WB<0b1100, "64">;
 
 def VST1d8Q_UPD  : VST1D4WB<0b0000, "8">;
 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
-//  VST1d64Q_UPD : implemented as VST4d64_UPD
+def VST4d64_UPD  : VST1D4WB<0b1100, "64">;
 
 //   VST2     : Vector Store (multiple 2-element structures)
 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
@@ -659,10 +632,6 @@
 def  VST3d8   : VST3D<0b0100, 0b0000, "8">;
 def  VST3d16  : VST3D<0b0100, 0b0100, "16">;
 def  VST3d32  : VST3D<0b0100, 0b1000, "32">;
-def  VST3d64  : NLdSt<0,0b00,0b0110,0b1100, (outs),
-                      (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
-                      IIC_VST,
-                      "vst1", "64", "\\{$src1, $src2, $src3\\}, $addr", "", []>;
 
 // ...with address register writeback:
 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
@@ -675,11 +644,6 @@
 def VST3d8_UPD  : VST3DWB<0b0100, 0b0000, "8">;
 def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
 def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
-def VST3d64_UPD : NLdSt<0,0b00,0b0110,0b1100, (outs GPR:$wb),
-                      (ins addrmode6:$addr, am6offset:$offset,
-                       DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
-                      "vst1", "64", "\\{$src1, $src2, $src3\\}, $addr$offset",
-                      "$addr.addr = $wb", []>;
 
 // ...with double-spaced registers (non-updating versions for disassembly only):
 def VST3q8      : VST3D<0b0101, 0b0000, "8">;
@@ -704,11 +668,6 @@
 def  VST4d8   : VST4D<0b0000, 0b0000, "8">;
 def  VST4d16  : VST4D<0b0000, 0b0100, "16">;
 def  VST4d32  : VST4D<0b0000, 0b1000, "32">;
-def  VST4d64  : NLdSt<0,0b00,0b0010,0b1100, (outs),
-                      (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
-                       DPR:$src4), IIC_VST,
-                      "vst1", "64", "\\{$src1, $src2, $src3, $src4\\}, $addr",
-                      "", []>;
 
 // ...with address register writeback:
 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
@@ -721,12 +680,6 @@
 def VST4d8_UPD  : VST4DWB<0b0000, 0b0000, "8">;
 def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
 def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
-def VST4d64_UPD : NLdSt<0,0b00,0b0010,0b1100, (outs GPR:$wb),
-                      (ins addrmode6:$addr, am6offset:$offset,
-                       DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
-                      "vst1", "64",
-                      "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
-                      "$addr.addr = $wb", []>;
 
 // ...with double-spaced registers (non-updating versions for disassembly only):
 def VST4q8      : VST4D<0b0001, 0b0000, "8">;




From bob.wilson at apple.com  Mon Mar 22 13:13:18 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 22 Mar 2010 18:13:18 -0000
Subject: [llvm-commits] [llvm] r99189 - in /llvm/trunk/lib/Target/ARM:
 ARMISelDAGToDAG.cpp ARMInstrNEON.td NEONPreAllocPass.cpp
Message-ID: <20100322181318.E13A42A6C12C@llvm.org>

Author: bwilson
Date: Mon Mar 22 13:13:18 2010
New Revision: 99189

URL: http://llvm.org/viewvc/llvm-project?rev=99189&view=rev
Log:
Rename some VLD1/VST1 instructions to match the implementation, i.e., the
corresponding NEON instructions, instead of operation they are currently
used for.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=99189&r1=99188&r2=99189&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Mar 22 13:13:18 2010
@@ -1840,7 +1840,7 @@
 
     case Intrinsic::arm_neon_vld3: {
       unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
-                              ARM::VLD3d32, ARM::VLD3d64 };
+                              ARM::VLD3d32, ARM::VLD1d64T };
       unsigned QOpcodes0[] = { ARM::VLD3q8_UPD,
                                ARM::VLD3q16_UPD,
                                ARM::VLD3q32_UPD };
@@ -1852,7 +1852,7 @@
 
     case Intrinsic::arm_neon_vld4: {
       unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
-                              ARM::VLD4d32, ARM::VLD4d64 };
+                              ARM::VLD4d32, ARM::VLD1d64Q };
       unsigned QOpcodes0[] = { ARM::VLD4q8_UPD,
                                ARM::VLD4q16_UPD,
                                ARM::VLD4q32_UPD };
@@ -1892,7 +1892,7 @@
 
     case Intrinsic::arm_neon_vst3: {
       unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16,
-                              ARM::VST3d32, ARM::VST3d64 };
+                              ARM::VST3d32, ARM::VST1d64T };
       unsigned QOpcodes0[] = { ARM::VST3q8_UPD,
                                ARM::VST3q16_UPD,
                                ARM::VST3q32_UPD };
@@ -1904,7 +1904,7 @@
 
     case Intrinsic::arm_neon_vst4: {
       unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
-                              ARM::VST4d32, ARM::VST4d64 };
+                              ARM::VST4d32, ARM::VST1d64Q };
       unsigned QOpcodes0[] = { ARM::VST4q8_UPD,
                                ARM::VST4q16_UPD,
                                ARM::VST4q32_UPD };

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99189&r1=99188&r2=99189&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Mar 22 13:13:18 2010
@@ -199,12 +199,12 @@
 def  VLD1d8T  : VLD1D3<0b0000, "8">;
 def  VLD1d16T : VLD1D3<0b0100, "16">;
 def  VLD1d32T : VLD1D3<0b1000, "32">;
-def  VLD3d64  : VLD1D3<0b1100, "64">;
+def  VLD1d64T : VLD1D3<0b1100, "64">;
 
 def  VLD1d8Q  : VLD1D4<0b0000, "8">;
 def  VLD1d16Q : VLD1D4<0b0100, "16">;
 def  VLD1d32Q : VLD1D4<0b1000, "32">;
-def  VLD4d64  : VLD1D4<0b1100, "64">;
+def  VLD1d64Q : VLD1D4<0b1100, "64">;
 
 // ...with address register writeback:
 class VLD1D3WB<bits<4> op7_4, string Dt>
@@ -221,12 +221,12 @@
 def VLD1d8T_UPD  : VLD1D3WB<0b0000, "8">;
 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
-def VLD3d64_UPD  : VLD1D3WB<0b1100, "64">;
+def VLD3d64T_UPD : VLD1D3WB<0b1100, "64">;
 
 def VLD1d8Q_UPD  : VLD1D4WB<0b0000, "8">;
 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
 def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
-def VLD4d64_UPD  : VLD1D4WB<0b1100, "64">;
+def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">;
 
 //   VLD2     : Vector Load (multiple 2-element structures)
 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
@@ -536,12 +536,12 @@
 def  VST1d8T  : VST1D3<0b0000, "8">;
 def  VST1d16T : VST1D3<0b0100, "16">;
 def  VST1d32T : VST1D3<0b1000, "32">;
-def  VST3d64  : VST1D3<0b1100, "64">;
+def  VST1d64T : VST1D3<0b1100, "64">;
 
 def  VST1d8Q  : VST1D4<0b0000, "8">;
 def  VST1d16Q : VST1D4<0b0100, "16">;
 def  VST1d32Q : VST1D4<0b1000, "32">;
-def  VST4d64  : VST1D4<0b1100, "64">;
+def  VST1d64Q : VST1D4<0b1100, "64">;
 
 // ...with address register writeback:
 class VST1D3WB<bits<4> op7_4, string Dt>
@@ -560,12 +560,12 @@
 def VST1d8T_UPD  : VST1D3WB<0b0000, "8">;
 def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
 def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
-def VST3d64_UPD  : VST1D3WB<0b1100, "64">;
+def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
 
 def VST1d8Q_UPD  : VST1D4WB<0b0000, "8">;
 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
-def VST4d64_UPD  : VST1D4WB<0b1100, "64">;
+def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
 
 //   VST2     : Vector Store (multiple 2-element structures)
 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>

Modified: llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp?rev=99189&r1=99188&r2=99189&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Mon Mar 22 13:13:18 2010
@@ -83,7 +83,7 @@
   case ARM::VLD3d8:
   case ARM::VLD3d16:
   case ARM::VLD3d32:
-  case ARM::VLD3d64:
+  case ARM::VLD1d64T:
   case ARM::VLD3LNd8:
   case ARM::VLD3LNd16:
   case ARM::VLD3LNd32:
@@ -128,7 +128,7 @@
   case ARM::VLD4d8:
   case ARM::VLD4d16:
   case ARM::VLD4d32:
-  case ARM::VLD4d64:
+  case ARM::VLD1d64Q:
   case ARM::VLD4LNd8:
   case ARM::VLD4LNd16:
   case ARM::VLD4LNd32:
@@ -207,7 +207,7 @@
   case ARM::VST3d8:
   case ARM::VST3d16:
   case ARM::VST3d32:
-  case ARM::VST3d64:
+  case ARM::VST1d64T:
   case ARM::VST3LNd8:
   case ARM::VST3LNd16:
   case ARM::VST3LNd32:
@@ -252,7 +252,7 @@
   case ARM::VST4d8:
   case ARM::VST4d16:
   case ARM::VST4d32:
-  case ARM::VST4d64:
+  case ARM::VST1d64Q:
   case ARM::VST4LNd8:
   case ARM::VST4LNd16:
   case ARM::VST4LNd32:




From asl at math.spbu.ru  Mon Mar 22 13:21:54 2010
From: asl at math.spbu.ru (Anton Korobeynikov)
Date: Mon, 22 Mar 2010 21:21:54 +0300
Subject: [llvm-commits] [llvm] r98889 - in /llvm/trunk/lib/Target/ARM:
	ARMISelLowering.cpp ARMISelLowering.h ARMInstrFormats.td
	ARMInstrInfo.td ARMInstrNEON.td ARMInstrVFP.td
In-Reply-To: <4794B6D7-F3D7-40FC-9DBE-3D43B508A88B@apple.com>
References: <20100318223545.834B62A6C12C@llvm.org>
	<C52E9734-75A2-498A-9DD5-E4D81BD50D13@apple.com>
	<b087fca01003191517g2196797bj632be6b3fbe20fdf@mail.gmail.com>
	<4794B6D7-F3D7-40FC-9DBE-3D43B508A88B@apple.com>
Message-ID: <b087fca01003221121i284935sd44972dc75898436@mail.gmail.com>

>
> Can't. Each of these moves by itself is not a nop.
Right, but the second move instruction is definitely redundant and
should be removed.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From bob.wilson at apple.com  Mon Mar 22 13:22:06 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 22 Mar 2010 18:22:06 -0000
Subject: [llvm-commits] [llvm] r99192 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20100322182206.A3FBE2A6C12C@llvm.org>

Author: bwilson
Date: Mon Mar 22 13:22:06 2010
New Revision: 99192

URL: http://llvm.org/viewvc/llvm-project?rev=99192&view=rev
Log:
Regroup some instructions.  No functional change.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99192&r1=99191&r2=99192&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Mar 22 13:22:06 2010
@@ -186,31 +186,31 @@
 
 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
 
-// These (dreg triple/quadruple) are for disassembly only.
+// ...with 3 registers (some of these are only for the disassembler):
 class VLD1D3<bits<4> op7_4, string Dt>
   : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
           (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
           "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
-class VLD1D4<bits<4> op7_4, string Dt>
-  : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
-          (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
-          "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
-
-def  VLD1d8T  : VLD1D3<0b0000, "8">;
-def  VLD1d16T : VLD1D3<0b0100, "16">;
-def  VLD1d32T : VLD1D3<0b1000, "32">;
-def  VLD1d64T : VLD1D3<0b1100, "64">;
-
-def  VLD1d8Q  : VLD1D4<0b0000, "8">;
-def  VLD1d16Q : VLD1D4<0b0100, "16">;
-def  VLD1d32Q : VLD1D4<0b1000, "32">;
-def  VLD1d64Q : VLD1D4<0b1100, "64">;
-
-// ...with address register writeback:
 class VLD1D3WB<bits<4> op7_4, string Dt>
   : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
           (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
           "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
+
+def VLD1d8T      : VLD1D3<0b0000, "8">;
+def VLD1d16T     : VLD1D3<0b0100, "16">;
+def VLD1d32T     : VLD1D3<0b1000, "32">;
+def VLD1d64T     : VLD1D3<0b1100, "64">;
+
+def VLD1d8T_UPD  : VLD1D3WB<0b0000, "8">;
+def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
+def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
+def VLD3d64T_UPD : VLD1D3WB<0b1100, "64">;
+
+// ...with 4 registers (some of these are only for the disassembler):
+class VLD1D4<bits<4> op7_4, string Dt>
+  : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
+          (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
+          "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
 class VLD1D4WB<bits<4> op7_4, string Dt>
   : NLdSt<0,0b10,0b0010,op7_4,
           (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
@@ -218,10 +218,10 @@
           "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
           []>;
 
-def VLD1d8T_UPD  : VLD1D3WB<0b0000, "8">;
-def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
-def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
-def VLD3d64T_UPD : VLD1D3WB<0b1100, "64">;
+def VLD1d8Q      : VLD1D4<0b0000, "8">;
+def VLD1d16Q     : VLD1D4<0b0100, "16">;
+def VLD1d32Q     : VLD1D4<0b1000, "32">;
+def VLD1d64Q     : VLD1D4<0b1100, "64">;
 
 def VLD1d8Q_UPD  : VLD1D4WB<0b0000, "8">;
 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
@@ -522,34 +522,34 @@
 def VST1q32_UPD : VST1QWB<0b1000, "32">;
 def VST1q64_UPD : VST1QWB<0b1100, "64">;
 
-// These (dreg triple/quadruple) are for disassembly only.
+// ...with 3 registers (some of these are only for the disassembler):
 class VST1D3<bits<4> op7_4, string Dt>
   : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
           (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
           IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
-class VST1D4<bits<4> op7_4, string Dt>
-  : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
-          (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
-          IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
-          []>;
-
-def  VST1d8T  : VST1D3<0b0000, "8">;
-def  VST1d16T : VST1D3<0b0100, "16">;
-def  VST1d32T : VST1D3<0b1000, "32">;
-def  VST1d64T : VST1D3<0b1100, "64">;
-
-def  VST1d8Q  : VST1D4<0b0000, "8">;
-def  VST1d16Q : VST1D4<0b0100, "16">;
-def  VST1d32Q : VST1D4<0b1000, "32">;
-def  VST1d64Q : VST1D4<0b1100, "64">;
-
-// ...with address register writeback:
 class VST1D3WB<bits<4> op7_4, string Dt>
   : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
           (ins addrmode6:$addr, am6offset:$offset,
            DPR:$src1, DPR:$src2, DPR:$src3),
           IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
           "$addr.addr = $wb", []>;
+
+def VST1d8T      : VST1D3<0b0000, "8">;
+def VST1d16T     : VST1D3<0b0100, "16">;
+def VST1d32T     : VST1D3<0b1000, "32">;
+def VST1d64T     : VST1D3<0b1100, "64">;
+
+def VST1d8T_UPD  : VST1D3WB<0b0000, "8">;
+def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
+def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
+def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
+
+// ...with 4 registers (some of these are only for the disassembler):
+class VST1D4<bits<4> op7_4, string Dt>
+  : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
+          (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
+          IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
+          []>;
 class VST1D4WB<bits<4> op7_4, string Dt>
   : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
           (ins addrmode6:$addr, am6offset:$offset,
@@ -557,10 +557,10 @@
           IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
           "$addr.addr = $wb", []>;
 
-def VST1d8T_UPD  : VST1D3WB<0b0000, "8">;
-def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
-def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
-def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
+def VST1d8Q      : VST1D4<0b0000, "8">;
+def VST1d16Q     : VST1D4<0b0100, "16">;
+def VST1d32Q     : VST1D4<0b1000, "32">;
+def VST1d64Q     : VST1D4<0b1100, "64">;
 
 def VST1d8Q_UPD  : VST1D4WB<0b0000, "8">;
 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;




From bob.wilson at apple.com  Mon Mar 22 13:25:59 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 22 Mar 2010 11:25:59 -0700
Subject: [llvm-commits] [llvm] r98889 - in /llvm/trunk/lib/Target/ARM:
	ARMISelLowering.cpp ARMISelLowering.h
	ARMInstrFormats.td	ARMInstrInfo.td ARMInstrNEON.td ARMInstrVFP.td
In-Reply-To: <b087fca01003221121i284935sd44972dc75898436@mail.gmail.com>
References: <20100318223545.834B62A6C12C@llvm.org>
	<C52E9734-75A2-498A-9DD5-E4D81BD50D13@apple.com>
	<b087fca01003191517g2196797bj632be6b3fbe20fdf@mail.gmail.com>
	<4794B6D7-F3D7-40FC-9DBE-3D43B508A88B@apple.com>
	<b087fca01003221121i284935sd44972dc75898436@mail.gmail.com>
Message-ID: <3C59017C-4096-403D-9C31-9EDA45F5270B@apple.com>


On Mar 22, 2010, at 11:21 AM, Anton Korobeynikov wrote:

>> 
>> Can't. Each of these moves by itself is not a nop.
> Right, but the second move instruction is definitely redundant and
> should be removed.

That's not good enough.  For the testcase that I sent you (off-list), we don't generate either of the VMOV instructions.  Removing one of them will only fix half the problem.


From evan.cheng at apple.com  Mon Mar 22 13:40:50 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 22 Mar 2010 18:40:50 -0000
Subject: [llvm-commits] [llvm] r99195 -
	/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
Message-ID: <20100322184050.8D96A2A6C12C@llvm.org>

Author: evancheng
Date: Mon Mar 22 13:40:50 2010
New Revision: 99195

URL: http://llvm.org/viewvc/llvm-project?rev=99195&view=rev
Log:
80 col violation.

Modified:
    llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=99195&r1=99194&r2=99195&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Mon Mar 22 13:40:50 2010
@@ -528,7 +528,8 @@
   MachineInstr *DefMI = Def->getInstr();
   int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
   if (DefIdx != -1) {
-    int DefCycle = InstrItins.getOperandCycle(DefMI->getDesc().getSchedClass(), DefIdx);
+    int DefCycle = InstrItins.getOperandCycle(DefMI->getDesc().getSchedClass(),
+                                              DefIdx);
     if (DefCycle >= 0) {
       MachineInstr *UseMI = Use->getInstr();
       const unsigned UseClass = UseMI->getDesc().getSchedClass();




From jyasskin at google.com  Mon Mar 22 13:47:14 2010
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Mon, 22 Mar 2010 18:47:14 -0000
Subject: [llvm-commits] [llvm] r99196 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DIE.cpp DIE.h DwarfDebug.cpp
Message-ID: <20100322184714.773AB2A6C12C@llvm.org>

Author: jyasskin
Date: Mon Mar 22 13:47:14 2010
New Revision: 99196

URL: http://llvm.org/viewvc/llvm-project?rev=99196&view=rev
Log:
Fix a memory leak from DIE::addSiblingOffset() by adding the DIEValue
it allocates to DwarfDebug::DIEValues.


Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp?rev=99196&r1=99195&r2=99196&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp Mon Mar 22 13:47:14 2010
@@ -114,10 +114,11 @@
 
 /// addSiblingOffset - Add a sibling offset field to the front of the DIE.
 ///
-void DIE::addSiblingOffset() {
+DIEValue *DIE::addSiblingOffset() {
   DIEInteger *DI = new DIEInteger(0);
   Values.insert(Values.begin(), DI);
   Abbrev.AddFirstAttribute(dwarf::DW_AT_sibling, dwarf::DW_FORM_ref4);
+  return DI;
 }
 
 #ifndef NDEBUG

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h?rev=99196&r1=99195&r2=99196&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h Mon Mar 22 13:47:14 2010
@@ -153,7 +153,7 @@
     unsigned getOffset() const { return Offset; }
     unsigned getSize() const { return Size; }
     const std::vector<DIE *> &getChildren() const { return Children; }
-    SmallVector<DIEValue*, 32> &getValues() { return Values; }
+    const SmallVector<DIEValue*, 32> &getValues() const { return Values; }
     DIE *getParent() const { return Parent; }
     void setTag(unsigned Tag) { Abbrev.setTag(Tag); }
     void setOffset(unsigned O) { Offset = O; }
@@ -171,8 +171,10 @@
     unsigned getSiblingOffset() const { return Offset + Size; }
 
     /// addSiblingOffset - Add a sibling offset field to the front of the DIE.
+    /// The caller is responsible for deleting the return value at or after the
+    /// same time it destroys this DIE.
     ///
-    void addSiblingOffset();
+    DIEValue *addSiblingOffset();
 
     /// addChild - Add a child to the DIE.
     ///

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=99196&r1=99195&r2=99196&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Mar 22 13:47:14 2010
@@ -2351,7 +2351,8 @@
   const std::vector<DIE *> &Children = Die->getChildren();
 
   // If not last sibling and has children then add sibling offset attribute.
-  if (!Last && !Children.empty()) Die->addSiblingOffset();
+  if (!Last && !Children.empty())
+    DIEValues.push_back(Die->addSiblingOffset());
 
   // Record the abbreviation.
   assignAbbrevNumber(Die->getAbbrev());
@@ -2465,7 +2466,7 @@
                                 dwarf::TagString(Abbrev->getTag()));
   EmitULEB128(AbbrevNumber);
 
-  SmallVector<DIEValue*, 32> &Values = Die->getValues();
+  const SmallVector<DIEValue*, 32> &Values = Die->getValues();
   const SmallVector<DIEAbbrevData, 8> &AbbrevData = Abbrev->getData();
 
   // Emit the DIE attribute values.




From bob.wilson at apple.com  Mon Mar 22 15:31:39 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 22 Mar 2010 20:31:39 -0000
Subject: [llvm-commits] [llvm] r99201 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20100322203139.8AD472A6C12C@llvm.org>

Author: bwilson
Date: Mon Mar 22 15:31:39 2010
New Revision: 99201

URL: http://llvm.org/viewvc/llvm-project?rev=99201&view=rev
Log:
Rename one more NEON instruction that I missed earlier.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99201&r1=99200&r2=99201&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Mar 22 15:31:39 2010
@@ -204,7 +204,7 @@
 def VLD1d8T_UPD  : VLD1D3WB<0b0000, "8">;
 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
-def VLD3d64T_UPD : VLD1D3WB<0b1100, "64">;
+def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">;
 
 // ...with 4 registers (some of these are only for the disassembler):
 class VLD1D4<bits<4> op7_4, string Dt>




From daniel at zuster.org  Mon Mar 22 15:35:35 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 20:35:35 -0000
Subject: [llvm-commits] [llvm] r99202 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp
Message-ID: <20100322203535.D26322A6C12C@llvm.org>

Author: ddunbar
Date: Mon Mar 22 15:35:35 2010
New Revision: 99202

URL: http://llvm.org/viewvc/llvm-project?rev=99202&view=rev
Log:
MC: Share the MCAsmLayout object, although its still not used for anything important.

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99202&r1=99201&r2=99202&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Mon Mar 22 15:35:35 2010
@@ -642,16 +642,17 @@
 
   /// Check whether a fixup can be satisfied, or whether it needs to be relaxed
   /// (increased in size, in order to hold its value correctly).
-  bool FixupNeedsRelaxation(MCAsmFixup &Fixup, MCDataFragment *DF);
+  bool FixupNeedsRelaxation(MCAsmFixup &Fixup, MCDataFragment *DF,
+                            const MCAsmLayout &Layout) const;
 
   /// LayoutSection - Assign offsets and sizes to the fragments in the section
   /// \arg SD, and update the section size. The section file offset should
   /// already have been computed.
-  void LayoutSection(MCSectionData &SD);
+  void LayoutSection(MCSectionData &SD, MCAsmLayout &Layout);
 
   /// LayoutOnce - Perform one layout iteration and return true if any offsets
   /// were adjusted.
-  bool LayoutOnce();
+  bool LayoutOnce(MCAsmLayout &Layout);
 
 public:
   /// Find the symbol which defines the atom containing given address, inside

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99202&r1=99201&r2=99202&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Mar 22 15:35:35 2010
@@ -297,8 +297,8 @@
   return IsResolved;
 }
 
-void MCAssembler::LayoutSection(MCSectionData &SD) {
-  MCAsmLayout Layout(*this);
+void MCAssembler::LayoutSection(MCSectionData &SD,
+                                MCAsmLayout &Layout) {
   uint64_t Address = SD.getAddress();
 
   for (MCSectionData::iterator it = SD.begin(), ie = SD.end(); it != ie; ++it) {
@@ -533,14 +533,14 @@
       dump(); });
 
   // Layout until everything fits.
-  while (LayoutOnce())
+  MCAsmLayout Layout(*this);
+  while (LayoutOnce(Layout))
     continue;
 
   DEBUG_WITH_TYPE("mc-dump", {
       llvm::errs() << "assembler backend - post-layout\n--\n";
       dump(); });
 
-  // FIXME: Factor out MCObjectWriter.
   llvm::OwningPtr<MCObjectWriter> Writer(getBackend().createObjectWriter(OS));
   if (!Writer)
     llvm_report_error("unable to create object writer!");
@@ -550,9 +550,6 @@
   Writer->ExecutePostLayoutBinding(*this);
 
   // Evaluate and apply the fixups, generating relocation entries as necessary.
-  //
-  // FIXME: Share layout object.
-  MCAsmLayout Layout(*this);
   for (MCAssembler::iterator it = begin(), ie = end(); it != ie; ++it) {
     for (MCSectionData::iterator it2 = it->begin(),
            ie2 = it->end(); it2 != ie2; ++it2) {
@@ -584,10 +581,8 @@
   OS.flush();
 }
 
-bool MCAssembler::FixupNeedsRelaxation(MCAsmFixup &Fixup, MCDataFragment *DF) {
-  // FIXME: Share layout object.
-  MCAsmLayout Layout(*this);
-
+bool MCAssembler::FixupNeedsRelaxation(MCAsmFixup &Fixup, MCDataFragment *DF,
+                                       const MCAsmLayout &Layout) const {
   // Currently we only need to relax X86::reloc_pcrel_1byte.
   if (unsigned(Fixup.Kind) != X86::reloc_pcrel_1byte)
     return false;
@@ -602,7 +597,7 @@
   return int64_t(Value) != int64_t(int8_t(Value));
 }
 
-bool MCAssembler::LayoutOnce() {
+bool MCAssembler::LayoutOnce(MCAsmLayout &Layout) {
   // Layout the concrete sections and fragments.
   uint64_t Address = 0;
   MCSectionData *Prev = 0;
@@ -623,7 +618,7 @@
 
     // Layout the section fragments and its size.
     SD.setAddress(Address);
-    LayoutSection(SD);
+    LayoutSection(SD, Layout);
     Address += SD.getFileSize();
 
     Prev = &SD;
@@ -642,7 +637,7 @@
       Address += Pad;
 
     SD.setAddress(Address);
-    LayoutSection(SD);
+    LayoutSection(SD, Layout);
     Address += SD.getSize();
   }
 
@@ -661,7 +656,7 @@
         MCAsmFixup &Fixup = *it3;
 
         // Check whether we need to relax this fixup.
-        if (!FixupNeedsRelaxation(Fixup, DF))
+        if (!FixupNeedsRelaxation(Fixup, DF, Layout))
           continue;
 
         // Relax the instruction.




From daniel at zuster.org  Mon Mar 22 15:35:43 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 20:35:43 -0000
Subject: [llvm-commits] [llvm] r99203 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp
Message-ID: <20100322203543.845E12A6C12C@llvm.org>

Author: ddunbar
Date: Mon Mar 22 15:35:43 2010
New Revision: 99203

URL: http://llvm.org/viewvc/llvm-project?rev=99203&view=rev
Log:
MC: Eliminate MCFragment::getMaxFileSize.

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99203&r1=99202&r2=99203&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Mon Mar 22 15:35:43 2010
@@ -99,12 +99,6 @@
   MCSectionData *getParent() const { return Parent; }
   void setParent(MCSectionData *Value) { Parent = Value; }
 
-  // FIXME: This should be abstract, fix sentinel.
-  virtual uint64_t getMaxFileSize() const {
-    assert(0 && "Invalid getMaxFileSize call!");
-    return 0;
-  }
-
   /// @name Assembler Backend Support
   /// @{
   //
@@ -116,10 +110,7 @@
     assert(FileSize != ~UINT64_C(0) && "File size not set!");
     return FileSize;
   }
-  void setFileSize(uint64_t Value) {
-    assert(Value <= getMaxFileSize() && "Invalid file size!");
-    FileSize = Value;
-  }
+  void setFileSize(uint64_t Value) { FileSize = Value; }
 
   uint64_t getOffset() const {
     assert(Offset != ~UINT64_C(0) && "File offset not set!");
@@ -150,10 +141,6 @@
   /// @name Accessors
   /// @{
 
-  uint64_t getMaxFileSize() const {
-    return Contents.size();
-  }
-
   SmallString<32> &getContents() { return Contents; }
   const SmallString<32> &getContents() const { return Contents; }
 
@@ -219,10 +206,6 @@
   /// @name Accessors
   /// @{
 
-  uint64_t getMaxFileSize() const {
-    return std::max(Alignment - 1, MaxBytesToEmit);
-  }
-
   unsigned getAlignment() const { return Alignment; }
 
   int64_t getValue() const { return Value; }
@@ -262,10 +245,6 @@
   /// @name Accessors
   /// @{
 
-  uint64_t getMaxFileSize() const {
-    return ValueSize * Count;
-  }
-
   int64_t getValue() const { return Value; }
 
   unsigned getValueSize() const { return ValueSize; }
@@ -297,11 +276,6 @@
   /// @name Accessors
   /// @{
 
-  uint64_t getMaxFileSize() const {
-    // FIXME: This doesn't make much sense.
-    return ~UINT64_C(0);
-  }
-
   const MCExpr &getOffset() const { return *Offset; }
 
   uint8_t getValue() const { return Value; }
@@ -333,11 +307,6 @@
   /// @name Accessors
   /// @{
 
-  uint64_t getMaxFileSize() const {
-    // FIXME: This also doesn't make much sense, this method is misnamed.
-    return ~UINT64_C(0);
-  }
-
   uint64_t getSize() const { return Size; }
 
   unsigned getAlignment() const { return Alignment; }

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99203&r1=99202&r2=99203&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Mar 22 15:35:43 2010
@@ -320,10 +320,15 @@
     }
 
     case MCFragment::FT_Data:
-    case MCFragment::FT_Fill:
-      F.setFileSize(F.getMaxFileSize());
+      F.setFileSize(cast<MCDataFragment>(F).getContents().size());
       break;
 
+    case MCFragment::FT_Fill: {
+      MCFillFragment &FF = cast<MCFillFragment>(F);
+      F.setFileSize(FF.getValueSize() * FF.getCount());
+      break;
+    }
+
     case MCFragment::FT_Org: {
       MCOrgFragment &OF = cast<MCOrgFragment>(F);
 




From daniel at zuster.org  Mon Mar 22 15:35:46 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 20:35:46 -0000
Subject: [llvm-commits] [llvm] r99204 -
	/llvm/trunk/lib/MC/MCMachOStreamer.cpp
Message-ID: <20100322203546.359652A6C12D@llvm.org>

Author: ddunbar
Date: Mon Mar 22 15:35:46 2010
New Revision: 99204

URL: http://llvm.org/viewvc/llvm-project?rev=99204&view=rev
Log:
MC/Mach-O: Factor out getOrCreateDataFragment().

Modified:
    llvm/trunk/lib/MC/MCMachOStreamer.cpp

Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=99204&r1=99203&r2=99204&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Mon Mar 22 15:35:46 2010
@@ -57,6 +57,15 @@
     return 0;
   }
 
+  /// Get a data fragment to write into, creating a new one if the current
+  /// fragment is not a data fragment.
+  MCDataFragment *getOrCreateDataFragment() const {
+    MCDataFragment *F = dyn_cast_or_null<MCDataFragment>(getCurrentFragment());
+    if (!F)
+      F = new MCDataFragment(CurSectionData);
+    return F;
+  }
+
 public:
   MCMachOStreamer(MCContext &Context, TargetAsmBackend &TAB,
                   raw_ostream &_OS, MCCodeEmitter *_Emitter)
@@ -150,11 +159,11 @@
 void MCMachOStreamer::EmitLabel(MCSymbol *Symbol) {
   assert(Symbol->isUndefined() && "Cannot define a symbol twice!");
 
-  // FIXME: We should also use offsets into Fill fragments.
-  MCDataFragment *F = dyn_cast_or_null<MCDataFragment>(getCurrentFragment());
-  if (!F)
-    F = new MCDataFragment(CurSectionData);
-
+  // FIXME: This is wasteful, we don't necessarily need to create a data
+  // fragment. Instead, we should mark the symbol as pointing into the data
+  // fragment if it exists, otherwise we should just queue the label and set its
+  // fragment pointer when we emit the next fragment.
+  MCDataFragment *F = getOrCreateDataFragment();
   MCSymbolData &SD = Assembler.getOrCreateSymbolData(*Symbol);
   assert(!SD.getFragment() && "Unexpected fragment on symbol data!");
   SD.setFragment(F);
@@ -307,17 +316,12 @@
 }
 
 void MCMachOStreamer::EmitBytes(StringRef Data, unsigned AddrSpace) {
-  MCDataFragment *DF = dyn_cast_or_null<MCDataFragment>(getCurrentFragment());
-  if (!DF)
-    DF = new MCDataFragment(CurSectionData);
-  DF->getContents().append(Data.begin(), Data.end());
+  getOrCreateDataFragment()->getContents().append(Data.begin(), Data.end());
 }
 
 void MCMachOStreamer::EmitValue(const MCExpr *Value, unsigned Size,
                                 unsigned AddrSpace) {
-  MCDataFragment *DF = dyn_cast_or_null<MCDataFragment>(getCurrentFragment());
-  if (!DF)
-    DF = new MCDataFragment(CurSectionData);
+  MCDataFragment *DF = getOrCreateDataFragment();
 
   // Avoid fixups when possible.
   int64_t AbsValue;
@@ -349,7 +353,7 @@
                                         unsigned MaxBytesToEmit) {
   if (MaxBytesToEmit == 0)
     MaxBytesToEmit = ByteAlignment;
-  // FIXME the 0x90 is the default x86 1 byte nop opcode.
+  // FIXME: The 0x90 is the default x86 1 byte nop opcode.
   new MCAlignFragment(ByteAlignment, 0x90, 1, MaxBytesToEmit,
                       true /* EmitNops */, CurSectionData);
 
@@ -378,9 +382,7 @@
   VecOS.flush();
 
   // Add the fixups and data.
-  MCDataFragment *DF = dyn_cast_or_null<MCDataFragment>(getCurrentFragment());
-  if (!DF)
-    DF = new MCDataFragment(CurSectionData);
+  MCDataFragment *DF = getOrCreateDataFragment();
   for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
     MCFixup &F = Fixups[i];
     DF->addFixup(MCAsmFixup(DF->getContents().size()+F.getOffset(),




From daniel at zuster.org  Mon Mar 22 15:35:50 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 20:35:50 -0000
Subject: [llvm-commits] [llvm] r99205 - in /llvm/trunk:
 include/llvm/MC/MCObjectWriter.h include/llvm/MC/MachObjectWriter.h
 lib/MC/MCAssembler.cpp lib/MC/MachObjectWriter.cpp
Message-ID: <20100322203550.6497E2A6C12E@llvm.org>

Author: ddunbar
Date: Mon Mar 22 15:35:50 2010
New Revision: 99205

URL: http://llvm.org/viewvc/llvm-project?rev=99205&view=rev
Log:
MC: Change MCObjectWriter::RecordRelocation to take an MCFragment (instead of a MCDataFragment). Object files should only need the generic MCFragment features.

Modified:
    llvm/trunk/include/llvm/MC/MCObjectWriter.h
    llvm/trunk/include/llvm/MC/MachObjectWriter.h
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/include/llvm/MC/MCObjectWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectWriter.h?rev=99205&r1=99204&r2=99205&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCObjectWriter.h (original)
+++ llvm/trunk/include/llvm/MC/MCObjectWriter.h Mon Mar 22 15:35:50 2010
@@ -17,7 +17,7 @@
 namespace llvm {
 class MCAsmFixup;
 class MCAssembler;
-class MCDataFragment;
+class MCFragment;
 class MCValue;
 class raw_ostream;
 
@@ -69,7 +69,7 @@
   /// information about the relocation so that it can be emitted during
   /// WriteObject().
   virtual void RecordRelocation(const MCAssembler &Asm,
-                                const MCDataFragment &Fragment,
+                                const MCFragment *Fragment,
                                 const MCAsmFixup &Fixup, MCValue Target,
                                 uint64_t &FixedValue) = 0;
 

Modified: llvm/trunk/include/llvm/MC/MachObjectWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MachObjectWriter.h?rev=99205&r1=99204&r2=99205&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MachObjectWriter.h (original)
+++ llvm/trunk/include/llvm/MC/MachObjectWriter.h Mon Mar 22 15:35:50 2010
@@ -17,7 +17,7 @@
 namespace llvm {
 class MCAsmFixup;
 class MCAssembler;
-class MCDataFragment;
+class MCFragment;
 class MCValue;
 class raw_ostream;
 
@@ -31,7 +31,7 @@
   virtual void ExecutePostLayoutBinding(MCAssembler &Asm);
 
   virtual void RecordRelocation(const MCAssembler &Asm,
-                                const MCDataFragment &Fragment,
+                                const MCFragment *Fragment,
                                 const MCAsmFixup &Fixup, MCValue Target,
                                 uint64_t &FixedValue);
 

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99205&r1=99204&r2=99205&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Mar 22 15:35:50 2010
@@ -573,7 +573,7 @@
           // The fixup was unresolved, we need a relocation. Inform the object
           // writer of the relocation, and give it an opportunity to adjust the
           // fixup value if need be.
-          Writer->RecordRelocation(*this, *DF, Fixup, Target, FixedValue);
+          Writer->RecordRelocation(*this, DF, Fixup, Target, FixedValue);
         }
 
         getBackend().ApplyFixup(Fixup, *DF, FixedValue);

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=99205&r1=99204&r2=99205&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Mon Mar 22 15:35:50 2010
@@ -438,7 +438,7 @@
   }
 
   void RecordX86_64Relocation(const MCAssembler &Asm,
-                              const MCDataFragment &Fragment,
+                              const MCFragment *Fragment,
                               const MCAsmFixup &Fixup, MCValue Target,
                               uint64_t &FixedValue) {
     unsigned IsPCRel = isFixupKindPCRel(Fixup.Kind);
@@ -446,7 +446,7 @@
     unsigned Log2Size = getFixupKindLog2Size(Fixup.Kind);
 
     // See <reloc.h>.
-    uint32_t Address = Fragment.getOffset() + Fixup.Offset;
+    uint32_t Address = Fragment->getOffset() + Fixup.Offset;
     int64_t Value = 0;
     unsigned Index = 0;
     unsigned IsExtern = 0;
@@ -521,7 +521,7 @@
                    (Log2Size  << 25) |
                    (IsExtern  << 27) |
                    (Type      << 28));
-      Relocations[Fragment.getParent()].push_back(MRE);
+      Relocations[Fragment->getParent()].push_back(MRE);
 
       Index = B_Base->getIndex();
       IsExtern = 1;
@@ -622,14 +622,14 @@
                  (Log2Size  << 25) |
                  (IsExtern  << 27) |
                  (Type      << 28));
-    Relocations[Fragment.getParent()].push_back(MRE);
+    Relocations[Fragment->getParent()].push_back(MRE);
   }
 
   void RecordScatteredRelocation(const MCAssembler &Asm,
-                                 const MCFragment &Fragment,
+                                 const MCFragment *Fragment,
                                  const MCAsmFixup &Fixup, MCValue Target,
                                  uint64_t &FixedValue) {
-    uint32_t Address = Fragment.getOffset() + Fixup.Offset;
+    uint32_t Address = Fragment->getOffset() + Fixup.Offset;
     unsigned IsPCRel = isFixupKindPCRel(Fixup.Kind);
     unsigned Log2Size = getFixupKindLog2Size(Fixup.Kind);
     unsigned Type = RIT_Vanilla;
@@ -670,7 +670,7 @@
                    (IsPCRel   << 30) |
                    RF_Scattered);
       MRE.Word1 = Value2;
-      Relocations[Fragment.getParent()].push_back(MRE);
+      Relocations[Fragment->getParent()].push_back(MRE);
     }
 
     MachRelocationEntry MRE;
@@ -680,10 +680,10 @@
                  (IsPCRel   << 30) |
                  RF_Scattered);
     MRE.Word1 = Value;
-    Relocations[Fragment.getParent()].push_back(MRE);
+    Relocations[Fragment->getParent()].push_back(MRE);
   }
 
-  void RecordRelocation(const MCAssembler &Asm, const MCDataFragment &Fragment,
+  void RecordRelocation(const MCAssembler &Asm, const MCFragment *Fragment,
                         const MCAsmFixup &Fixup, MCValue Target,
                         uint64_t &FixedValue) {
     if (Is64Bit) {
@@ -707,7 +707,7 @@
     }
 
     // See <reloc.h>.
-    uint32_t Address = Fragment.getOffset() + Fixup.Offset;
+    uint32_t Address = Fragment->getOffset() + Fixup.Offset;
     uint32_t Value = 0;
     unsigned Index = 0;
     unsigned IsExtern = 0;
@@ -752,7 +752,7 @@
                  (Log2Size  << 25) |
                  (IsExtern  << 27) |
                  (Type      << 28));
-    Relocations[Fragment.getParent()].push_back(MRE);
+    Relocations[Fragment->getParent()].push_back(MRE);
   }
 
   void BindIndirectSymbols(MCAssembler &Asm) {
@@ -1097,7 +1097,7 @@
 }
 
 void MachObjectWriter::RecordRelocation(const MCAssembler &Asm,
-                                        const MCDataFragment &Fragment,
+                                        const MCFragment *Fragment,
                                         const MCAsmFixup &Fixup, MCValue Target,
                                         uint64_t &FixedValue) {
   ((MachObjectWriterImpl*) Impl)->RecordRelocation(Asm, Fragment, Fixup,




From sabre at nondot.org  Mon Mar 22 15:56:37 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 22 Mar 2010 20:56:37 -0000
Subject: [llvm-commits] [llvm] r99206 - in /llvm/trunk:
 lib/VMCore/Verifier.cpp utils/TableGen/CodeGenDAGPatterns.cpp
 utils/TableGen/CodeGenTarget.cpp utils/TableGen/IntrinsicEmitter.cpp
Message-ID: <20100322205637.177632A6C12C@llvm.org>

Author: lattner
Date: Mon Mar 22 15:56:36 2010
New Revision: 99206

URL: http://llvm.org/viewvc/llvm-project?rev=99206&view=rev
Log:
Change intrinsic result type for void to store it as an empty list
instead of as a single element list with VoidTy.  Now with a fix
for the verifier.

Modified:
    llvm/trunk/lib/VMCore/Verifier.cpp
    llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
    llvm/trunk/utils/TableGen/CodeGenTarget.cpp
    llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=99206&r1=99205&r2=99206&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Mar 22 15:56:36 2010
@@ -1683,13 +1683,11 @@
 /// parameters beginning with NumRets.
 ///
 static std::string IntrinsicParam(unsigned ArgNo, unsigned NumRets) {
-  if (ArgNo < NumRets) {
-    if (NumRets == 1)
-      return "Intrinsic result type";
-    else
-      return "Intrinsic result type #" + utostr(ArgNo);
-  } else
+  if (ArgNo >= NumRets)
     return "Intrinsic parameter #" + utostr(ArgNo - NumRets);
+  if (NumRets == 1)
+    return "Intrinsic result type";
+  return "Intrinsic result type #" + utostr(ArgNo);
 }
 
 bool Verifier::PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty,
@@ -1706,9 +1704,13 @@
 
   const Type *RetTy = FTy->getReturnType();
   const StructType *ST = dyn_cast<StructType>(RetTy);
-  unsigned NumRets = 1;
-  if (ST)
-    NumRets = ST->getNumElements();
+  unsigned NumRetVals;
+  if (RetTy->isVoidTy())
+    NumRetVals = 0;
+  else if (ST)
+    NumRetVals = ST->getNumElements();
+  else
+    NumRetVals = 1;
 
   if (VT < 0) {
     int Match = ~VT;
@@ -1720,7 +1722,7 @@
                   TruncatedElementVectorType)) != 0) {
       const IntegerType *IEltTy = dyn_cast<IntegerType>(EltTy);
       if (!VTy || !IEltTy) {
-        CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not "
+        CheckFailed(IntrinsicParam(ArgNo, NumRetVals) + " is not "
                     "an integral vector type.", F);
         return false;
       }
@@ -1728,7 +1730,7 @@
       // the type being matched against.
       if ((Match & ExtendedElementVectorType) != 0) {
         if ((IEltTy->getBitWidth() & 1) != 0) {
-          CheckFailed(IntrinsicParam(ArgNo, NumRets) + " vector "
+          CheckFailed(IntrinsicParam(ArgNo, NumRetVals) + " vector "
                       "element bit-width is odd.", F);
           return false;
         }
@@ -1738,25 +1740,25 @@
       Match &= ~(ExtendedElementVectorType | TruncatedElementVectorType);
     }
 
-    if (Match <= static_cast<int>(NumRets - 1)) {
+    if (Match <= static_cast<int>(NumRetVals - 1)) {
       if (ST)
         RetTy = ST->getElementType(Match);
 
       if (Ty != RetTy) {
-        CheckFailed(IntrinsicParam(ArgNo, NumRets) + " does not "
+        CheckFailed(IntrinsicParam(ArgNo, NumRetVals) + " does not "
                     "match return type.", F);
         return false;
       }
     } else {
-      if (Ty != FTy->getParamType(Match - NumRets)) {
-        CheckFailed(IntrinsicParam(ArgNo, NumRets) + " does not "
-                    "match parameter %" + utostr(Match - NumRets) + ".", F);
+      if (Ty != FTy->getParamType(Match - NumRetVals)) {
+        CheckFailed(IntrinsicParam(ArgNo, NumRetVals) + " does not "
+                    "match parameter %" + utostr(Match - NumRetVals) + ".", F);
         return false;
       }
     }
   } else if (VT == MVT::iAny) {
     if (!EltTy->isIntegerTy()) {
-      CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not "
+      CheckFailed(IntrinsicParam(ArgNo, NumRetVals) + " is not "
                   "an integer type.", F);
       return false;
     }
@@ -1781,7 +1783,7 @@
     }
   } else if (VT == MVT::fAny) {
     if (!EltTy->isFloatingPointTy()) {
-      CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not "
+      CheckFailed(IntrinsicParam(ArgNo, NumRetVals) + " is not "
                   "a floating-point type.", F);
       return false;
     }
@@ -1794,13 +1796,14 @@
     Suffix += EVT::getEVT(EltTy).getEVTString();
   } else if (VT == MVT::vAny) {
     if (!VTy) {
-      CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not a vector type.", F);
+      CheckFailed(IntrinsicParam(ArgNo, NumRetVals) + " is not a vector type.",
+                  F);
       return false;
     }
     Suffix += ".v" + utostr(NumElts) + EVT::getEVT(EltTy).getEVTString();
   } else if (VT == MVT::iPTR) {
     if (!Ty->isPointerTy()) {
-      CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not a "
+      CheckFailed(IntrinsicParam(ArgNo, NumRetVals) + " is not a "
                   "pointer and a pointer is required.", F);
       return false;
     }
@@ -1812,7 +1815,7 @@
       Suffix += ".p" + utostr(PTyp->getAddressSpace()) + 
         EVT::getEVT(PTyp->getElementType()).getEVTString();
     } else {
-      CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not a "
+      CheckFailed(IntrinsicParam(ArgNo, NumRetVals) + " is not a "
                   "pointer and a pointer is required.", F);
       return false;
     }
@@ -1832,10 +1835,10 @@
     }
   } else if (EVT((MVT::SimpleValueType)VT).getTypeForEVT(Ty->getContext()) != 
              EltTy) {
-    CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is wrong!", F);
+    CheckFailed(IntrinsicParam(ArgNo, NumRetVals) + " is wrong!", F);
     return false;
   } else if (EltTy != Ty) {
-    CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is a vector "
+    CheckFailed(IntrinsicParam(ArgNo, NumRetVals) + " is a vector "
                 "and a scalar is required.", F);
     return false;
   }
@@ -1847,10 +1850,10 @@
 /// Intrinsics.gen.  This implements a little state machine that verifies the
 /// prototype of intrinsics.
 void Verifier::VerifyIntrinsicPrototype(Intrinsic::ID ID, Function *F,
-                                        unsigned RetNum,
-                                        unsigned ParamNum, ...) {
+                                        unsigned NumRetVals,
+                                        unsigned NumParams, ...) {
   va_list VA;
-  va_start(VA, ParamNum);
+  va_start(VA, NumParams);
   const FunctionType *FTy = F->getFunctionType();
 
   // For overloaded intrinsics, the Suffix of the function name must match the
@@ -1858,7 +1861,7 @@
   // suffix, to be checked at the end.
   std::string Suffix;
 
-  if (FTy->getNumParams() + FTy->isVarArg() != ParamNum) {
+  if (FTy->getNumParams() + FTy->isVarArg() != NumParams) {
     CheckFailed("Intrinsic prototype has incorrect number of arguments!", F);
     return;
   }
@@ -1866,23 +1869,27 @@
   const Type *Ty = FTy->getReturnType();
   const StructType *ST = dyn_cast<StructType>(Ty);
 
+  if (NumRetVals == 0 && !Ty->isVoidTy()) {
+    CheckFailed("Intrinsic should return void", F);
+    return;
+  }
+  
   // Verify the return types.
-  if (ST && ST->getNumElements() != RetNum) {
+  if (ST && ST->getNumElements() != NumRetVals) {
     CheckFailed("Intrinsic prototype has incorrect number of return types!", F);
     return;
   }
-
-  for (unsigned ArgNo = 0; ArgNo < RetNum; ++ArgNo) {
+  
+  for (unsigned ArgNo = 0; ArgNo != NumRetVals; ++ArgNo) {
     int VT = va_arg(VA, int); // An MVT::SimpleValueType when non-negative.
 
     if (ST) Ty = ST->getElementType(ArgNo);
-
     if (!PerformTypeCheck(ID, F, Ty, VT, ArgNo, Suffix))
       break;
   }
 
   // Verify the parameter types.
-  for (unsigned ArgNo = 0; ArgNo < ParamNum; ++ArgNo) {
+  for (unsigned ArgNo = 0; ArgNo != NumParams; ++ArgNo) {
     int VT = va_arg(VA, int); // An MVT::SimpleValueType when non-negative.
 
     if (VT == MVT::isVoid && ArgNo > 0) {
@@ -1891,8 +1898,8 @@
       break;
     }
 
-    if (!PerformTypeCheck(ID, F, FTy->getParamType(ArgNo), VT, ArgNo + RetNum,
-                          Suffix))
+    if (!PerformTypeCheck(ID, F, FTy->getParamType(ArgNo), VT,
+                          ArgNo + NumRetVals, Suffix))
       break;
   }
 

Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=99206&r1=99205&r2=99206&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Mon Mar 22 15:56:36 2010
@@ -754,12 +754,8 @@
       Operator->getName() == "parallel")
     return 0;  // All return nothing.
   
-  if (Operator->isSubClassOf("Intrinsic")) {
-    unsigned NumRes = CDP.getIntrinsic(Operator).IS.RetVTs.size();
-    if (NumRes == 1 && CDP.getIntrinsic(Operator).IS.RetVTs[0] == MVT::isVoid)
-      return 0;
-    return NumRes;
-  }
+  if (Operator->isSubClassOf("Intrinsic"))
+    return CDP.getIntrinsic(Operator).IS.RetVTs.size();
   
   if (Operator->isSubClassOf("SDNode"))
     return CDP.getSDNodeInfo(Operator).getNumResults();
@@ -1210,8 +1206,6 @@
     // Apply the result type to the node.
     unsigned NumRetVTs = Int->IS.RetVTs.size();
     unsigned NumParamVTs = Int->IS.ParamVTs.size();
-    if (NumRetVTs == 1 && Int->IS.RetVTs[0] == MVT::isVoid)
-      NumRetVTs = 0;
     
     for (unsigned i = 0, e = NumRetVTs; i != e; ++i)
       MadeChange |= UpdateNodeType(i, Int->IS.RetVTs[i], TP);
@@ -1591,7 +1585,7 @@
 
     // If this intrinsic returns void, it must have side-effects and thus a
     // chain.
-    if (Int.IS.RetVTs[0] == MVT::isVoid) {
+    if (Int.IS.RetVTs.empty()) {
       Operator = getDAGPatterns().get_intrinsic_void_sdnode();
     } else if (Int.ModRef != CodeGenIntrinsic::NoMem) {
       // Has side-effects, requires chain.

Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=99206&r1=99205&r2=99206&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Mar 22 15:56:36 2010
@@ -490,12 +490,15 @@
       OverloadedVTs.push_back(VT);
       isOverloaded |= true;
     }
+    
     IS.RetVTs.push_back(VT);
     IS.RetTypeDefs.push_back(TyEl);
   }
-
-  if (IS.RetVTs.size() == 0)
-    throw "Intrinsic '"+DefName+"' needs at least a type for the ret value!";
+  
+  if (IS.RetVTs.size() == 1 && IS.RetVTs[0] == MVT::isVoid) {
+    IS.RetVTs.pop_back();
+    IS.RetTypeDefs.pop_back();
+  }
 
   // Parse the list of parameter types.
   TypeList = R->getValueAsListInit("ParamTypes");

Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=99206&r1=99205&r2=99206&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Mon Mar 22 15:56:36 2010
@@ -172,10 +172,11 @@
 static void EmitTypeGenerate(raw_ostream &OS,
                              const std::vector<Record*> &ArgTypes,
                              unsigned &ArgNo) {
-  if (ArgTypes.size() == 1) {
-    EmitTypeGenerate(OS, ArgTypes.front(), ArgNo);
-    return;
-  }
+  if (ArgTypes.empty())
+    return EmitTypeForValueType(OS, MVT::isVoid);
+  
+  if (ArgTypes.size() == 1)
+    return EmitTypeGenerate(OS, ArgTypes.front(), ArgNo);
 
   OS << "StructType::get(Context, ";
 
@@ -251,11 +252,11 @@
       unsigned RHSSize = RHSVec->size();
       unsigned LHSSize = LHSVec->size();
 
-      do {
+      for (; i != LHSSize; ++i) {
         if (i == RHSSize) return false;  // RHS is shorter than LHS.
         if ((*LHSVec)[i] != (*RHSVec)[i])
           return (*LHSVec)[i]->getName() < (*RHSVec)[i]->getName();
-      } while (++i != LHSSize);
+      }
 
       if (i != RHSSize) return true;
 




From evan.cheng at apple.com  Mon Mar 22 16:24:33 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 22 Mar 2010 21:24:33 -0000
Subject: [llvm-commits] [llvm] r99214 -
	/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
Message-ID: <20100322212433.553E52A6C12C@llvm.org>

Author: evancheng
Date: Mon Mar 22 16:24:33 2010
New Revision: 99214

URL: http://llvm.org/viewvc/llvm-project?rev=99214&view=rev
Log:
Reduce indentation.

Modified:
    llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=99214&r1=99213&r2=99214&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Mon Mar 22 16:24:33 2010
@@ -248,48 +248,47 @@
         unsigned DataLatency = SU->Latency;
         for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
           SUnit *UseSU = UseList[i];
-          if (UseSU != SU) {
-            unsigned LDataLatency = DataLatency;
-            // Optionally add in a special extra latency for nodes that
-            // feed addresses.
-            // TODO: Do this for register aliases too.
-            // TODO: Perhaps we should get rid of
-            // SpecialAddressLatency and just move this into
-            // adjustSchedDependency for the targets that care about
-            // it.
-            if (SpecialAddressLatency != 0 && !UnitLatencies) {
-              MachineInstr *UseMI = UseSU->getInstr();
-              const TargetInstrDesc &UseTID = UseMI->getDesc();
-              int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
-              assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
-              if ((UseTID.mayLoad() || UseTID.mayStore()) &&
-                  (unsigned)RegUseIndex < UseTID.getNumOperands() &&
-                  UseTID.OpInfo[RegUseIndex].isLookupPtrRegClass())
-                LDataLatency += SpecialAddressLatency;
-            }
-            // Adjust the dependence latency using operand def/use
-            // information (if any), and then allow the target to
-            // perform its own adjustments.
-            const SDep& dep = SDep(SU, SDep::Data, LDataLatency, Reg);
-            if (!UnitLatencies) {
-              ComputeOperandLatency(SU, UseSU, (SDep &)dep);
-              ST.adjustSchedDependency(SU, UseSU, (SDep &)dep);
-            }
-            UseSU->addPred(dep);
+          if (UseSU == SU)
+            continue;
+          unsigned LDataLatency = DataLatency;
+          // Optionally add in a special extra latency for nodes that
+          // feed addresses.
+          // TODO: Do this for register aliases too.
+          // TODO: Perhaps we should get rid of
+          // SpecialAddressLatency and just move this into
+          // adjustSchedDependency for the targets that care about it.
+          if (SpecialAddressLatency != 0 && !UnitLatencies) {
+            MachineInstr *UseMI = UseSU->getInstr();
+            const TargetInstrDesc &UseTID = UseMI->getDesc();
+            int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
+            assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
+            if ((UseTID.mayLoad() || UseTID.mayStore()) &&
+                (unsigned)RegUseIndex < UseTID.getNumOperands() &&
+                UseTID.OpInfo[RegUseIndex].isLookupPtrRegClass())
+              LDataLatency += SpecialAddressLatency;
           }
+          // Adjust the dependence latency using operand def/use
+          // information (if any), and then allow the target to
+          // perform its own adjustments.
+          const SDep& dep = SDep(SU, SDep::Data, LDataLatency, Reg);
+          if (!UnitLatencies) {
+            ComputeOperandLatency(SU, UseSU, (SDep &)dep);
+            ST.adjustSchedDependency(SU, UseSU, (SDep &)dep);
+          }
+          UseSU->addPred(dep);
         }
         for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
           std::vector<SUnit *> &UseList = Uses[*Alias];
           for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
             SUnit *UseSU = UseList[i];
-            if (UseSU != SU) {
-              const SDep& dep = SDep(SU, SDep::Data, DataLatency, *Alias);
-              if (!UnitLatencies) {
-                ComputeOperandLatency(SU, UseSU, (SDep &)dep);
-                ST.adjustSchedDependency(SU, UseSU, (SDep &)dep);
-              }
-              UseSU->addPred(dep);
+            if (UseSU == SU)
+              continue;
+            const SDep& dep = SDep(SU, SDep::Data, DataLatency, *Alias);
+            if (!UnitLatencies) {
+              ComputeOperandLatency(SU, UseSU, (SDep &)dep);
+              ST.adjustSchedDependency(SU, UseSU, (SDep &)dep);
             }
+            UseSU->addPred(dep);
           }
         }
 




From daniel at zuster.org  Mon Mar 22 16:49:34 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 21:49:34 -0000
Subject: [llvm-commits] [llvm] r99216 - in /llvm/trunk:
 include/llvm/MC/MCInst.h lib/MC/MCAsmStreamer.cpp lib/MC/MCInst.cpp
Message-ID: <20100322214934.E829D2A6C12C@llvm.org>

Author: ddunbar
Date: Mon Mar 22 16:49:34 2010
New Revision: 99216

URL: http://llvm.org/viewvc/llvm-project?rev=99216&view=rev
Log:
MCInst: Add ::dump_pretty.

Modified:
    llvm/trunk/include/llvm/MC/MCInst.h
    llvm/trunk/lib/MC/MCAsmStreamer.cpp
    llvm/trunk/lib/MC/MCInst.cpp

Modified: llvm/trunk/include/llvm/MC/MCInst.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInst.h?rev=99216&r1=99215&r2=99216&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCInst.h (original)
+++ llvm/trunk/include/llvm/MC/MCInst.h Mon Mar 22 16:49:34 2010
@@ -17,11 +17,13 @@
 #define LLVM_MC_MCINST_H
 
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
 #include "llvm/System/DataTypes.h"
 
 namespace llvm {
 class raw_ostream;
 class MCAsmInfo;
+class MCInstPrinter;
 class MCExpr;
 
 /// MCOperand - Instances of this class represent operands of the MCInst class.
@@ -125,6 +127,13 @@
 
   void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
   void dump() const;
+
+  /// \brief Dump the MCInst as prettily as possible using the additional MC
+  /// structures, if given. Operators are separated by the \arg Separator
+  /// string.
+  void dump_pretty(raw_ostream &OS, const MCAsmInfo *MAI = 0,
+                   const MCInstPrinter *Printer = 0,
+                   StringRef Separator = " ") const;
 };
 
 

Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=99216&r1=99215&r2=99216&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Mon Mar 22 16:49:34 2010
@@ -623,24 +623,10 @@
     AddEncodingComment(Inst);
 
   // Show the MCInst if enabled.
-  if (ShowInst) {
-    raw_ostream &OS = GetCommentOS();
-    OS << "<MCInst #" << Inst.getOpcode();
-    
-    StringRef InstName;
-    if (InstPrinter)
-      InstName = InstPrinter->getOpcodeName(Inst.getOpcode());
-    if (!InstName.empty())
-      OS << ' ' << InstName;
-    
-    for (unsigned i = 0, e = Inst.getNumOperands(); i != e; ++i) {
-      OS << "\n  ";
-      Inst.getOperand(i).print(OS, &MAI);
-    }
-    OS << ">\n";
-  }
+  if (ShowInst)
+    Inst.dump_pretty(GetCommentOS(), &MAI, InstPrinter.get(), "\n ");
   
-  // If we have an AsmPrinter, use that to print, otherwise dump the MCInst.
+  // If we have an AsmPrinter, use that to print, otherwise print the MCInst.
   if (InstPrinter)
     InstPrinter->printInst(&Inst);
   else

Modified: llvm/trunk/lib/MC/MCInst.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCInst.cpp?rev=99216&r1=99215&r2=99216&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCInst.cpp (original)
+++ llvm/trunk/lib/MC/MCInst.cpp Mon Mar 22 16:49:34 2010
@@ -9,6 +9,7 @@
 
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInstPrinter.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
@@ -43,6 +44,22 @@
   OS << ">";
 }
 
+void MCInst::dump_pretty(raw_ostream &OS, const MCAsmInfo *MAI,
+                         const MCInstPrinter *Printer,
+                         StringRef Separator) const {
+  OS << "<MCInst #" << getOpcode();
+
+  // Show the instruction opcode name if we have access to a printer.
+  if (Printer)
+    OS << ' ' << Printer->getOpcodeName(getOpcode());
+
+  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
+    OS << Separator;
+    getOperand(i).print(OS, MAI);
+  }
+  OS << ">\n";
+}
+
 void MCInst::dump() const {
   print(dbgs(), 0);
   dbgs() << "\n";




From daniel at zuster.org  Mon Mar 22 16:49:38 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 21:49:38 -0000
Subject: [llvm-commits] [llvm] r99217 - /llvm/trunk/lib/MC/MCAssembler.cpp
Message-ID: <20100322214938.2F2E62A6C12D@llvm.org>

Author: ddunbar
Date: Mon Mar 22 16:49:38 2010
New Revision: 99217

URL: http://llvm.org/viewvc/llvm-project?rev=99217&view=rev
Log:
Simplify.

Modified:
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99217&r1=99216&r2=99217&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Mar 22 16:49:38 2010
@@ -104,7 +104,6 @@
 
 static bool isScatteredFixupFullyResolvedSimple(const MCAssembler &Asm,
                                                 const MCAsmFixup &Fixup,
-                                                const MCDataFragment *DF,
                                                 const MCValue Target,
                                                 const MCSection *BaseSection) {
   // The effective fixup address is
@@ -142,7 +141,6 @@
 
 static bool isScatteredFixupFullyResolved(const MCAssembler &Asm,
                                           const MCAsmFixup &Fixup,
-                                          const MCDataFragment *DF,
                                           const MCValue Target,
                                           const MCSymbolData *BaseSymbol) {
   // The effective fixup address is
@@ -279,14 +277,14 @@
       }
 
       if (IsResolved)
-        IsResolved = isScatteredFixupFullyResolved(*this, Fixup, DF, Target,
+        IsResolved = isScatteredFixupFullyResolved(*this, Fixup, Target,
                                                    BaseSymbol);
     } else {
       const MCSection *BaseSection = 0;
       if (IsPCRel)
         BaseSection = &DF->getParent()->getSection();
 
-      IsResolved = isScatteredFixupFullyResolvedSimple(*this, Fixup, DF, Target,
+      IsResolved = isScatteredFixupFullyResolvedSimple(*this, Fixup, Target,
                                                        BaseSection);
     }
   }




From daniel at zuster.org  Mon Mar 22 16:49:41 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 21:49:41 -0000
Subject: [llvm-commits] [llvm] r99218 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp
Message-ID: <20100322214941.B9D212A6C12E@llvm.org>

Author: ddunbar
Date: Mon Mar 22 16:49:41 2010
New Revision: 99218

URL: http://llvm.org/viewvc/llvm-project?rev=99218&view=rev
Log:
MC: Fix a few more cases we were passing an MCDataFragment when a MCFragment would do, and sprinkle in some const.

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99218&r1=99217&r2=99218&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Mon Mar 22 16:49:41 2010
@@ -606,12 +606,12 @@
   /// \arg Value result is fixed, otherwise the value may change due to
   /// relocation.
   bool EvaluateFixup(const MCAsmLayout &Layout,
-                     MCAsmFixup &Fixup, MCDataFragment *DF,
+                     const MCAsmFixup &Fixup, const MCFragment *DF,
                      MCValue &Target, uint64_t &Value) const;
 
   /// Check whether a fixup can be satisfied, or whether it needs to be relaxed
   /// (increased in size, in order to hold its value correctly).
-  bool FixupNeedsRelaxation(MCAsmFixup &Fixup, MCDataFragment *DF,
+  bool FixupNeedsRelaxation(const MCAsmFixup &Fixup, const MCFragment *DF,
                             const MCAsmLayout &Layout) const;
 
   /// LayoutSection - Assign offsets and sizes to the fragments in the section

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99218&r1=99217&r2=99218&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Mar 22 16:49:41 2010
@@ -234,8 +234,8 @@
   return getAtomForAddress(SD->getFragment()->getParent(), SD->getAddress());
 }
 
-bool MCAssembler::EvaluateFixup(const MCAsmLayout &Layout, MCAsmFixup &Fixup,
-                                MCDataFragment *DF,
+bool MCAssembler::EvaluateFixup(const MCAsmLayout &Layout,
+                                const MCAsmFixup &Fixup, const MCFragment *DF,
                                 MCValue &Target, uint64_t &Value) const {
   if (!Fixup.Value->EvaluateAsRelocatable(Target, &Layout))
     llvm_report_error("expected relocatable expression");
@@ -584,7 +584,8 @@
   OS.flush();
 }
 
-bool MCAssembler::FixupNeedsRelaxation(MCAsmFixup &Fixup, MCDataFragment *DF,
+bool MCAssembler::FixupNeedsRelaxation(const MCAsmFixup &Fixup,
+                                       const MCFragment *DF,
                                        const MCAsmLayout &Layout) const {
   // Currently we only need to relax X86::reloc_pcrel_1byte.
   if (unsigned(Fixup.Kind) != X86::reloc_pcrel_1byte)




From dpatel at apple.com  Mon Mar 22 17:38:48 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 22 Mar 2010 22:38:48 -0000
Subject: [llvm-commits] [llvm] r99223 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DIE.cpp DIE.h DwarfDebug.cpp
 DwarfDebug.h
Message-ID: <20100322223848.BC6C72A6C12C@llvm.org>

Author: dpatel
Date: Mon Mar 22 17:38:48 2010
New Revision: 99223

URL: http://llvm.org/viewvc/llvm-project?rev=99223&view=rev
Log:
DW_AT_stmt_list attribute attached with a compile unit encodes offset of line number information for this compile unit in debug_line section. This offset is always zero when only one compile unit is emitted in a object file. 


Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp?rev=99223&r1=99222&r2=99223&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp Mon Mar 22 17:38:48 2010
@@ -278,31 +278,6 @@
 #endif
 
 //===----------------------------------------------------------------------===//
-// DIESectionOffset Implementation
-//===----------------------------------------------------------------------===//
-
-/// EmitValue - Emit delta value.
-///
-void DIESectionOffset::EmitValue(DwarfPrinter *D, unsigned Form) const {
-  bool IsSmall = Form == dwarf::DW_FORM_data4;
-  D->EmitSectionOffset(Label, Section, IsSmall, IsEH);
-}
-
-/// SizeOf - Determine size of delta value in bytes.
-///
-unsigned DIESectionOffset::SizeOf(const TargetData *TD, unsigned Form) const {
-  if (Form == dwarf::DW_FORM_data4) return 4;
-  return TD->getPointerSize();
-}
-
-#ifndef NDEBUG
-void DIESectionOffset::print(raw_ostream &O) {
-  O << "Off: " << Label->getName() << "-" << Section->getName()
-    << "-" << IsEH;
-}
-#endif
-
-//===----------------------------------------------------------------------===//
 // DIEDelta Implementation
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h?rev=99223&r1=99222&r2=99223&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h Mon Mar 22 17:38:48 2010
@@ -330,38 +330,6 @@
   };
 
   //===--------------------------------------------------------------------===//
-  /// DIESectionOffset - A section offset DIE.
-  ///
-  class DIESectionOffset : public DIEValue {
-    const MCSymbol *Label;
-    const MCSymbol *Section;
-    bool IsEH : 1;
-  public:
-    DIESectionOffset(const MCSymbol *Lab, const MCSymbol *Sec,
-                     bool isEH = false)
-      : DIEValue(isSectionOffset), Label(Lab), Section(Sec),
-        IsEH(isEH) {}
-
-    /// EmitValue - Emit section offset.
-    ///
-    virtual void EmitValue(DwarfPrinter *D, unsigned Form) const;
-
-    /// SizeOf - Determine size of section offset value in bytes.
-    ///
-    virtual unsigned SizeOf(const TargetData *TD, unsigned Form) const;
-
-    // Implement isa/cast/dyncast.
-    static bool classof(const DIESectionOffset *)  { return true; }
-    static bool classof(const DIEValue *D) {
-      return D->getType() == isSectionOffset;
-    }
-
-#ifndef NDEBUG
-    virtual void print(raw_ostream &O);
-#endif
-  };
-
-  //===--------------------------------------------------------------------===//
   /// DIEDelta - A simple label difference DIE.
   ///
   class DIEDelta : public DIEValue {

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=99223&r1=99222&r2=99223&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Mar 22 17:38:48 2010
@@ -386,16 +386,6 @@
   Die->addValue(Attribute, Form, Value);
 }
 
-/// addSectionOffset - Add a section offset label attribute data and value.
-///
-void DwarfDebug::addSectionOffset(DIE *Die, unsigned Attribute, unsigned Form,
-                                  const MCSymbol *Label,const MCSymbol *Section,
-                                  bool isEH) {
-  DIEValue *Value = new DIESectionOffset(Label, Section, isEH);
-  DIEValues.push_back(Value);
-  Die->addValue(Attribute, Form, Value);
-}
-
 /// addDelta - Add a label delta attribute data and value.
 ///
 void DwarfDebug::addDelta(DIE *Die, unsigned Attribute, unsigned Form,
@@ -1666,10 +1656,10 @@
   unsigned ID = GetOrCreateSourceID(Dir, FN);
 
   DIE *Die = new DIE(dwarf::DW_TAG_compile_unit);
-  // FIXME: Why getting the delta between two identical labels??
-  addSectionOffset(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4,
-                   getTempLabel("section_line"), getTempLabel("section_line"),
-                   false);
+  // DW_AT_stmt_list is a offset of line number information for this
+  // compile unit in debug_line section. It is always zero when only one
+  // compile unit is emitted in one object file.
+  addUInt(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4, 0);
   addString(Die, dwarf::DW_AT_producer, dwarf::DW_FORM_string,
             DIUnit.getProducer());
   addUInt(Die, dwarf::DW_AT_language, dwarf::DW_FORM_data1,

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=99223&r1=99222&r2=99223&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Mar 22 17:38:48 2010
@@ -250,12 +250,6 @@
   void addLabel(DIE *Die, unsigned Attribute, unsigned Form,
                 const MCSymbol *Label);
 
-  /// addSectionOffset - Add a section offset label attribute data and value.
-  ///
-  void addSectionOffset(DIE *Die, unsigned Attribute, unsigned Form,
-                        const MCSymbol *Label, const MCSymbol *Section,
-                        bool isEH = false);
-
   /// addDelta - Add a label delta attribute data and value.
   ///
   void addDelta(DIE *Die, unsigned Attribute, unsigned Form,




From evan.cheng at apple.com  Mon Mar 22 17:44:32 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 22 Mar 2010 22:44:32 -0000
Subject: [llvm-commits] [llvm] r99224 -
	/llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp
Message-ID: <20100322224432.266E92A6C12C@llvm.org>

Author: evancheng
Date: Mon Mar 22 17:44:31 2010
New Revision: 99224

URL: http://llvm.org/viewvc/llvm-project?rev=99224&view=rev
Log:
Fix 80 col violation.

Modified:
    llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp

Modified: llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp?rev=99224&r1=99223&r2=99224&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp Mon Mar 22 17:44:31 2010
@@ -123,7 +123,7 @@
 /// EmitMemMove - Emit a call to the memmove function to the builder.  This
 /// always expects that the size has type 'intptr_t' and Dst/Src are pointers.
 Value *llvm::EmitMemMove(Value *Dst, Value *Src, Value *Len,
-					               unsigned Align, IRBuilder<> &B, const TargetData *TD) {
+                         unsigned Align, IRBuilder<> &B, const TargetData *TD) {
   Module *M = B.GetInsertBlock()->getParent()->getParent();
   LLVMContext &Context = B.GetInsertBlock()->getContext();
   const Type *Ty = TD->getIntPtrType(Context);




From dpatel at apple.com  Mon Mar 22 18:11:36 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 22 Mar 2010 23:11:36 -0000
Subject: [llvm-commits] [llvm] r99225 - in /llvm/trunk:
 lib/CodeGen/AsmPrinter/DwarfDebug.cpp
 test/DebugInfo/2010-03-22-CU-HighLow.ll
Message-ID: <20100322231136.511652A6C12C@llvm.org>

Author: dpatel
Date: Mon Mar 22 18:11:36 2010
New Revision: 99225

URL: http://llvm.org/viewvc/llvm-project?rev=99225&view=rev
Log:
Emit DW_AT_low_pc and DW_AT_high_pc attributes for TAG_compile_unit.

Added:
    llvm/trunk/test/DebugInfo/2010-03-22-CU-HighLow.ll
Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=99225&r1=99224&r2=99225&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Mar 22 18:11:36 2010
@@ -1656,15 +1656,19 @@
   unsigned ID = GetOrCreateSourceID(Dir, FN);
 
   DIE *Die = new DIE(dwarf::DW_TAG_compile_unit);
-  // DW_AT_stmt_list is a offset of line number information for this
-  // compile unit in debug_line section. It is always zero when only one
-  // compile unit is emitted in one object file.
-  addUInt(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4, 0);
   addString(Die, dwarf::DW_AT_producer, dwarf::DW_FORM_string,
             DIUnit.getProducer());
   addUInt(Die, dwarf::DW_AT_language, dwarf::DW_FORM_data1,
           DIUnit.getLanguage());
   addString(Die, dwarf::DW_AT_name, dwarf::DW_FORM_string, FN);
+  addLabel(Die, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr,
+           getTempLabel("text_begin"));
+  addLabel(Die, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr,
+           getTempLabel("text_end"));
+  // DW_AT_stmt_list is a offset of line number information for this
+  // compile unit in debug_line section. It is always zero when only one
+  // compile unit is emitted in one object file.
+  addUInt(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4, 0);
 
   if (!Dir.empty())
     addString(Die, dwarf::DW_AT_comp_dir, dwarf::DW_FORM_string, Dir);

Added: llvm/trunk/test/DebugInfo/2010-03-22-CU-HighLow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2010-03-22-CU-HighLow.ll?rev=99225&view=auto
==============================================================================
--- llvm/trunk/test/DebugInfo/2010-03-22-CU-HighLow.ll (added)
+++ llvm/trunk/test/DebugInfo/2010-03-22-CU-HighLow.ll Mon Mar 22 18:11:36 2010
@@ -0,0 +1,9 @@
+; RUN: llc < %s | grep low_pc | count 2
+ at i = global i32 1                                 ; <i32*> [#uses=0]
+
+!llvm.dbg.gv = !{!0}
+
+!0 = metadata !{i32 524340, i32 0, metadata !1, metadata !"i", metadata !"i", metadata !"", metadata !1, i32 1, metadata !3, i1 false, i1 true, i32* @i} ; [ DW_TAG_variable ]
+!1 = metadata !{i32 524329, metadata !"b.c", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 524305, i32 0, i32 1, metadata !"b.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]




From sabre at nondot.org  Mon Mar 22 18:15:57 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 22 Mar 2010 23:15:57 -0000
Subject: [llvm-commits] [llvm] r99227 - in /llvm/trunk:
 lib/CodeGen/MachineModuleInfo.cpp test/CodeGen/Generic/addr-label.ll
Message-ID: <20100322231557.BA57E2A6C12C@llvm.org>

Author: lattner
Date: Mon Mar 22 18:15:57 2010
New Revision: 99227

URL: http://llvm.org/viewvc/llvm-project?rev=99227&view=rev
Log:
Fix PR6673: updating the callback should not clear the map.

Modified:
    llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp
    llvm/trunk/test/CodeGen/Generic/addr-label.ll

Modified: llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp?rev=99227&r1=99226&r2=99227&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Mon Mar 22 18:15:57 2010
@@ -44,6 +44,10 @@
   MMIAddrLabelMapCallbackPtr() : Map(0) {}
   MMIAddrLabelMapCallbackPtr(Value *V) : CallbackVH(V), Map(0) {}
   
+  void setPtr(BasicBlock *BB) {
+    ValueHandleBase::operator=(BB);
+  }
+    
   void setMap(MMIAddrLabelMap *map) { Map = map; }
   
   virtual void deleted();
@@ -209,7 +213,7 @@
 
   // If New is not address taken, just move our symbol over to it.
   if (NewEntry.Symbols.isNull()) {
-    BBCallbacks[OldEntry.Index] = New;    // Update the callback.
+    BBCallbacks[OldEntry.Index].setPtr(New);    // Update the callback.
     NewEntry = OldEntry;     // Set New's entry.
     return;
   }

Modified: llvm/trunk/test/CodeGen/Generic/addr-label.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/addr-label.ll?rev=99227&r1=99226&r2=99227&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Generic/addr-label.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/addr-label.ll Mon Mar 22 18:15:57 2010
@@ -56,3 +56,26 @@
 	ret i32 -1
 }
 
+
+; PR6673
+
+define i64 @test4a() {
+	%target = bitcast i8* blockaddress(@test4b, %usermain) to i8*
+	%ret = call i64 @test4b(i8* %target)
+
+	ret i64 %ret
+}
+
+define i64 @test4b(i8* %Code) {
+entry:
+	indirectbr i8* %Code, [label %usermain]
+usermain:
+	br label %label_line_0
+
+label_line_0:
+	br label %label_line_1
+
+label_line_1:
+	%target = ptrtoint i8* blockaddress(@test4b, %label_line_0) to i64
+	ret i64 %target
+}




From daniel at zuster.org  Mon Mar 22 18:16:43 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 23:16:43 -0000
Subject: [llvm-commits] [llvm] r99228 -
	/llvm/trunk/lib/MC/MachObjectWriter.cpp
Message-ID: <20100322231643.775F52A6C12C@llvm.org>

Author: ddunbar
Date: Mon Mar 22 18:16:43 2010
New Revision: 99228

URL: http://llvm.org/viewvc/llvm-project?rev=99228&view=rev
Log:
Add a FIXME.

Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=99228&r1=99227&r2=99228&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Mon Mar 22 18:16:43 2010
@@ -437,6 +437,20 @@
       Write32(Address);
   }
 
+  // FIXME: We really need to improve the relocation validation. Basically, we
+  // want to implement a separate computation which evaluates the relocation
+  // entry as the linker would, and verifies that the resultant fixup value is
+  // exactly what the encoder wanted. This will catch several classes of
+  // problems:
+  //
+  //  - Relocation entry bugs, the two algorithms are unlikely to have the same
+  //    exact bug.
+  //
+  //  - Relaxation issues, where we forget to relax something.
+  //
+  //  - Input errors, where something cannot be correctly encoded. 'as' allows
+  //    these through in many cases.
+
   void RecordX86_64Relocation(const MCAssembler &Asm,
                               const MCFragment *Fragment,
                               const MCAsmFixup &Fixup, MCValue Target,




From daniel at zuster.org  Mon Mar 22 18:16:48 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 22 Mar 2010 23:16:48 -0000
Subject: [llvm-commits] [llvm] r99229 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp
 lib/MC/MCMachOStreamer.cpp
Message-ID: <20100322231648.D96C02A6C12D@llvm.org>

Author: ddunbar
Date: Mon Mar 22 18:16:48 2010
New Revision: 99229

URL: http://llvm.org/viewvc/llvm-project?rev=99229&view=rev
Log:
MC: Add MCInstFragment, not used yet.

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MCMachOStreamer.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99229&r1=99228&r2=99229&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Mon Mar 22 18:16:48 2010
@@ -16,6 +16,7 @@
 #include "llvm/ADT/ilist_node.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/MC/MCFixup.h"
+#include "llvm/MC/MCInst.h"
 #include "llvm/System/DataTypes.h"
 #include <vector> // FIXME: Shouldn't be needed.
 
@@ -37,6 +38,8 @@
 /// MCAsmFixup - Represent a fixed size region of bytes inside some fragment
 /// which needs to be rewritten. This region will either be rewritten by the
 /// assembler or cause a relocation entry to be generated.
+//
+// FIXME: This should probably just be merged with MCFixup.
 class MCAsmFixup {
 public:
   /// Offset - The offset inside the fragment which needs to be rewritten.
@@ -59,9 +62,10 @@
 
 public:
   enum FragmentType {
-    FT_Data,
     FT_Align,
+    FT_Data,
     FT_Fill,
+    FT_Inst,
     FT_Org,
     FT_ZeroFill
   };
@@ -145,7 +149,6 @@
   const SmallString<32> &getContents() const { return Contents; }
 
   /// @}
-
   /// @name Fixup Access
   /// @{
 
@@ -177,6 +180,39 @@
   virtual void dump();
 };
 
+class MCInstFragment : public MCFragment {
+  /// Inst - The instruction this is a fragment for.
+  MCInst Inst;
+
+  /// InstSize - The size of the currently encoded instruction.
+  unsigned InstSize;
+
+public:
+  MCInstFragment(MCInst _Inst, unsigned _InstSize, MCSectionData *SD = 0)
+    : MCFragment(FT_Inst, SD), Inst(_Inst), InstSize(_InstSize) {}
+
+  /// @name Accessors
+  /// @{
+
+  unsigned getInstSize() const { return InstSize; }
+
+  const MCInst &getInst() const { return Inst; }
+
+  void setInst(MCInst Inst, unsigned InstSize) {
+    this->Inst = Inst;
+    this->InstSize = InstSize;
+  }
+
+  /// @}
+
+  static bool classof(const MCFragment *F) {
+    return F->getKind() == MCFragment::FT_Inst;
+  }
+  static bool classof(const MCInstFragment *) { return true; }
+
+  virtual void dump();
+};
+
 class MCAlignFragment : public MCFragment {
   /// Alignment - The alignment to ensure, in bytes.
   unsigned Alignment;
@@ -623,6 +659,9 @@
   /// were adjusted.
   bool LayoutOnce(MCAsmLayout &Layout);
 
+  /// FinishLayout - Finalize a layout, including fragment lowering.
+  void FinishLayout(MCAsmLayout &Layout);
+
 public:
   /// Find the symbol which defines the atom containing given address, inside
   /// the given section, or null if there is no such symbol.

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99229&r1=99228&r2=99229&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Mar 22 18:16:48 2010
@@ -327,6 +327,10 @@
       break;
     }
 
+    case MCFragment::FT_Inst:
+      F.setFileSize(cast<MCInstFragment>(F).getInstSize());
+      break;
+
     case MCFragment::FT_Org: {
       MCOrgFragment &OF = cast<MCOrgFragment>(F);
 
@@ -471,7 +475,9 @@
   }
 
   case MCFragment::FT_Data: {
-    OW->WriteBytes(cast<MCDataFragment>(F).getContents().str());
+    MCDataFragment &DF = cast<MCDataFragment>(F);
+    assert(DF.getFileSize() == DF.getContents().size() && "Invalid size!");
+    OW->WriteBytes(DF.getContents().str());
     break;
   }
 
@@ -490,6 +496,10 @@
     break;
   }
 
+  case MCFragment::FT_Inst:
+    llvm_unreachable("unexpected inst fragment after lowering");
+    break;
+
   case MCFragment::FT_Org: {
     MCOrgFragment &OF = cast<MCOrgFragment>(F);
 
@@ -541,7 +551,14 @@
     continue;
 
   DEBUG_WITH_TYPE("mc-dump", {
-      llvm::errs() << "assembler backend - post-layout\n--\n";
+      llvm::errs() << "assembler backend - post-relaxation\n--\n";
+      dump(); });
+
+  // Finalize the layout, including fragment lowering.
+  FinishLayout(Layout);
+
+  DEBUG_WITH_TYPE("mc-dump", {
+      llvm::errs() << "assembler backend - final-layout\n--\n";
       dump(); });
 
   llvm::OwningPtr<MCObjectWriter> Writer(getBackend().createObjectWriter(OS));
@@ -722,8 +739,8 @@
 
         // Restart layout.
         //
-        // FIXME: This is O(N^2), but will be eliminated once we have a smart
-        // MCAsmLayout object.
+        // FIXME-PERF: This is O(N^2), but will be eliminated once we have a
+        // smart MCAsmLayout object.
         return true;
       }
     }
@@ -732,6 +749,54 @@
   return false;
 }
 
+void MCAssembler::FinishLayout(MCAsmLayout &Layout) {
+  // Lower out any instruction fragments, to simplify the fixup application and
+  // output.
+  //
+  // FIXME-PERF: We don't have to do this, but the assumption is that it is
+  // cheap (we will mostly end up eliminating fragments and appending on to data
+  // fragments), so the extra complexity downstream isn't worth it. Evaluate
+  // this assumption.
+  for (iterator it = begin(), ie = end(); it != ie; ++it) {
+    MCSectionData &SD = *it;
+
+    for (MCSectionData::iterator it2 = SD.begin(),
+           ie2 = SD.end(); it2 != ie2; ++it2) {
+      MCInstFragment *IF = dyn_cast<MCInstFragment>(it2);
+      if (!IF)
+        continue;
+
+      // Create a new data fragment for the instruction.
+      //
+      // FIXME: Reuse previous data fragment if possible.
+      MCDataFragment *DF = new MCDataFragment();
+      SD.getFragmentList().insert(it2, DF);
+
+      // Update the data fragments layout data.
+      DF->setOffset(IF->getOffset());
+      DF->setFileSize(IF->getInstSize());
+
+      // Encode the final instruction.
+      SmallVector<MCFixup, 4> Fixups;
+      raw_svector_ostream VecOS(DF->getContents());
+      getEmitter().EncodeInstruction(IF->getInst(), VecOS, Fixups);
+
+      // Copy over the fixups.
+      //
+      // FIXME-PERF: Encode fixups directly into the data fragment as well.
+      for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
+        MCFixup &F = Fixups[i];
+        DF->addFixup(MCAsmFixup(DF->getContents().size()+F.getOffset(),
+                                *F.getValue(), F.getKind()));
+      }
+
+      // Delete the instruction fragment and update the iterator.
+      SD.getFragmentList().erase(IF);
+      it2 = DF;
+    }
+  }
+}
+
 // Debugging methods
 
 namespace llvm {
@@ -800,6 +865,17 @@
      << " Count:" << getCount() << ">";
 }
 
+void MCInstFragment::dump() {
+  raw_ostream &OS = llvm::errs();
+
+  OS << "<MCInstFragment ";
+  this->MCFragment::dump();
+  OS << "\n       ";
+  OS << " Inst:";
+  getInst().dump_pretty(OS);
+  OS << ">";
+}
+
 void MCOrgFragment::dump() {
   raw_ostream &OS = llvm::errs();
 

Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=99229&r1=99228&r2=99229&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Mon Mar 22 18:16:48 2010
@@ -375,6 +375,9 @@
 
   CurSectionData->setHasInstructions(true);
 
+  // FIXME-PERF: Common case is that we don't need to relax, encode directly
+  // onto the data fragments buffers.
+
   SmallVector<MCFixup, 4> Fixups;
   SmallString<256> Code;
   raw_svector_ostream VecOS(Code);




From jyasskin at google.com  Mon Mar 22 18:26:13 2010
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Mon, 22 Mar 2010 23:26:13 -0000
Subject: [llvm-commits] [llvm] r99231 - in /llvm/trunk:
 include/llvm/MC/MCSection.h lib/MC/MCSection.cpp
Message-ID: <20100322232613.1B7532A6C12C@llvm.org>

Author: jyasskin
Date: Mon Mar 22 18:26:12 2010
New Revision: 99231

URL: http://llvm.org/viewvc/llvm-project?rev=99231&view=rev
Log:
Put MCSectionCOFF::Name into the MCContext instead of leaking it.

Modified:
    llvm/trunk/include/llvm/MC/MCSection.h
    llvm/trunk/lib/MC/MCSection.cpp

Modified: llvm/trunk/include/llvm/MC/MCSection.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSection.h?rev=99231&r1=99230&r2=99231&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCSection.h (original)
+++ llvm/trunk/include/llvm/MC/MCSection.h Mon Mar 22 18:26:12 2010
@@ -42,9 +42,8 @@
   };
 
   class MCSectionCOFF : public MCSection {
-    // FIXME: This memory is leaked because MCSectionCOFF is bump pointer
-    // allocated and this never gets freed.
-    std::string Name;
+    // The memory for this string is stored in the same MCContext as *this.
+    StringRef Name;
     
     /// IsDirective - This is true if the section name is a directive, not
     /// something that should be printed with ".section".
@@ -61,7 +60,7 @@
     static MCSectionCOFF *Create(StringRef Name, bool IsDirective, 
                                  SectionKind K, MCContext &Ctx);
 
-    const std::string &getName() const { return Name; }
+    StringRef getName() const { return Name; }
     bool isDirective() const { return IsDirective; }
     
     virtual void PrintSwitchToSection(const MCAsmInfo &MAI,

Modified: llvm/trunk/lib/MC/MCSection.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCSection.cpp?rev=99231&r1=99230&r2=99231&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCSection.cpp (original)
+++ llvm/trunk/lib/MC/MCSection.cpp Mon Mar 22 18:26:12 2010
@@ -26,7 +26,11 @@
 
 MCSectionCOFF *MCSectionCOFF::
 Create(StringRef Name, bool IsDirective, SectionKind K, MCContext &Ctx) {
-  return new (Ctx) MCSectionCOFF(Name, IsDirective, K);
+  char *NameCopy = static_cast<char*>(
+    Ctx.Allocate(Name.size(), /*Alignment=*/1));
+  memcpy(NameCopy, Name.data(), Name.size());
+  return new (Ctx) MCSectionCOFF(StringRef(NameCopy, Name.size()),
+                                 IsDirective, K);
 }
 
 void MCSectionCOFF::PrintSwitchToSection(const MCAsmInfo &MAI,




From sabre at nondot.org  Mon Mar 22 18:59:48 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 22 Mar 2010 23:59:48 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r99232 -
	/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Message-ID: <20100322235948.D02E22A6C12C@llvm.org>

Author: lattner
Date: Mon Mar 22 18:59:48 2010
New Revision: 99232

URL: http://llvm.org/viewvc/llvm-project?rev=99232&view=rev
Log:
"fix" PR6656: the passmanager needs to be destroyed before
the module is, in case immutable passes have asserting VH's
pointing into the IR.  Immutable passes apparently don't
get their doFinalization methods called, which seems like
a bug.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=99232&r1=99231&r2=99232&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Mon Mar 22 18:59:48 2010
@@ -975,6 +975,9 @@
 // llvm_call_llvm_shutdown - Release LLVM global state.
 void llvm_call_llvm_shutdown(void) {
 #ifndef NDEBUG
+  delete PerModulePasses;
+  delete PerFunctionPasses;
+  delete CodeGenPasses;
   delete TheModule;
   llvm_shutdown();
 #endif




From daniel at zuster.org  Mon Mar 22 20:39:05 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 23 Mar 2010 01:39:05 -0000
Subject: [llvm-commits] [llvm] r99244 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp
Message-ID: <20100323013905.7CCED2A6C12C@llvm.org>

Author: ddunbar
Date: Mon Mar 22 20:39:05 2010
New Revision: 99244

URL: http://llvm.org/viewvc/llvm-project?rev=99244&view=rev
Log:
MC: Tweak MCInstFragment to include the encoded data and fixups, so that we don't need to recompute them during relaxation. I will revisit this once all the other pieces of fast relaxation are in place.

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99244&r1=99243&r2=99244&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Mon Mar 22 20:39:05 2010
@@ -180,28 +180,57 @@
   virtual void dump();
 };
 
+// FIXME: This current incarnation of MCInstFragment doesn't make much sense, as
+// it is almost entirely a duplicate of MCDataFragment. If we decide to stick
+// with this approach (as opposed to making MCInstFragment a very light weight
+// object with just the MCInst and a code size, then we should just change
+// MCDataFragment to have an optional MCInst at its end.
 class MCInstFragment : public MCFragment {
   /// Inst - The instruction this is a fragment for.
   MCInst Inst;
 
   /// InstSize - The size of the currently encoded instruction.
-  unsigned InstSize;
+  SmallString<8> Code;
+
+  /// Fixups - The list of fixups in this fragment.
+  SmallVector<MCAsmFixup, 1> Fixups;
+
+public:
+  typedef SmallVectorImpl<MCAsmFixup>::const_iterator const_fixup_iterator;
+  typedef SmallVectorImpl<MCAsmFixup>::iterator fixup_iterator;
 
 public:
-  MCInstFragment(MCInst _Inst, unsigned _InstSize, MCSectionData *SD = 0)
-    : MCFragment(FT_Inst, SD), Inst(_Inst), InstSize(_InstSize) {}
+  MCInstFragment(MCInst _Inst, MCSectionData *SD = 0)
+    : MCFragment(FT_Inst, SD), Inst(_Inst) {
+  }
 
   /// @name Accessors
   /// @{
 
-  unsigned getInstSize() const { return InstSize; }
+  SmallVectorImpl<char> &getCode() { return Code; }
+  const SmallVectorImpl<char> &getCode() const { return Code; }
 
+  unsigned getInstSize() const { return Code.size(); }
+
+  MCInst &getInst() { return Inst; }
   const MCInst &getInst() const { return Inst; }
 
-  void setInst(MCInst Inst, unsigned InstSize) {
-    this->Inst = Inst;
-    this->InstSize = InstSize;
-  }
+  void setInst(MCInst Value) { Inst = Value; }
+
+  /// @}
+  /// @name Fixup Access
+  /// @{
+
+  SmallVectorImpl<MCAsmFixup> &getFixups() { return Fixups; }
+  const SmallVectorImpl<MCAsmFixup> &getFixups() const { return Fixups; }
+
+  fixup_iterator fixup_begin() { return Fixups.begin(); }
+  const_fixup_iterator fixup_begin() const { return Fixups.begin(); }
+
+  fixup_iterator fixup_end() {return Fixups.end();}
+  const_fixup_iterator fixup_end() const {return Fixups.end();}
+
+  size_t fixup_size() const { return Fixups.size(); }
 
   /// @}
 

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99244&r1=99243&r2=99244&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Mar 22 20:39:05 2010
@@ -773,22 +773,14 @@
       SD.getFragmentList().insert(it2, DF);
 
       // Update the data fragments layout data.
+      DF->setParent(IF->getParent());
       DF->setOffset(IF->getOffset());
       DF->setFileSize(IF->getInstSize());
 
-      // Encode the final instruction.
-      SmallVector<MCFixup, 4> Fixups;
-      raw_svector_ostream VecOS(DF->getContents());
-      getEmitter().EncodeInstruction(IF->getInst(), VecOS, Fixups);
-
-      // Copy over the fixups.
-      //
-      // FIXME-PERF: Encode fixups directly into the data fragment as well.
-      for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
-        MCFixup &F = Fixups[i];
-        DF->addFixup(MCAsmFixup(DF->getContents().size()+F.getOffset(),
-                                *F.getValue(), F.getKind()));
-      }
+      // Copy in the data and the fixups.
+      DF->getContents().append(IF->getCode().begin(), IF->getCode().end());
+      for (unsigned i = 0, e = IF->getFixups().size(); i != e; ++i)
+        DF->getFixups().push_back(IF->getFixups()[i]);
 
       // Delete the instruction fragment and update the iterator.
       SD.getFragmentList().erase(IF);




From daniel at zuster.org  Mon Mar 22 20:39:09 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 23 Mar 2010 01:39:09 -0000
Subject: [llvm-commits] [llvm] r99245 - in /llvm/trunk:
 include/llvm/Target/TargetAsmBackend.h lib/Target/X86/X86AsmBackend.cpp
Message-ID: <20100323013909.358EA2A6C12D@llvm.org>

Author: ddunbar
Date: Mon Mar 22 20:39:09 2010
New Revision: 99245

URL: http://llvm.org/viewvc/llvm-project?rev=99245&view=rev
Log:
MC: Add TargetAsmBackend::RelaxInstruction callback, and custom X86 implementation.

Modified:
    llvm/trunk/include/llvm/Target/TargetAsmBackend.h
    llvm/trunk/lib/Target/X86/X86AsmBackend.cpp

Modified: llvm/trunk/include/llvm/Target/TargetAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmBackend.h?rev=99245&r1=99244&r2=99245&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetAsmBackend.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmBackend.h Mon Mar 22 20:39:09 2010
@@ -15,6 +15,8 @@
 namespace llvm {
 class MCAsmFixup;
 class MCDataFragment;
+class MCInst;
+class MCInstFragment;
 class MCObjectWriter;
 class MCSection;
 class Target;
@@ -95,6 +97,11 @@
   /// fixup kind as appropriate.
   virtual void ApplyFixup(const MCAsmFixup &Fixup, MCDataFragment &Fragment,
                           uint64_t Value) const = 0;
+
+  /// RelaxInstruction - Relax the instruction in the given fragment to the next
+  /// wider instruction.
+  virtual void RelaxInstruction(const MCInstFragment *IF,
+                                MCInst &Res) const = 0;
 };
 
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=99245&r1=99244&r2=99245&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Mon Mar 22 20:39:09 2010
@@ -10,10 +10,13 @@
 #include "llvm/Target/TargetAsmBackend.h"
 #include "X86.h"
 #include "X86FixupKinds.h"
+#include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MachObjectWriter.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetRegistry.h"
 #include "llvm/Target/TargetAsmBackend.h"
 using namespace llvm;
@@ -48,8 +51,55 @@
     for (unsigned i = 0; i != Size; ++i)
       DF.getContents()[Fixup.Offset + i] = uint8_t(Value >> (i * 8));
   }
+
+  void RelaxInstruction(const MCInstFragment *IF, MCInst &Res) const;
 };
 
+static unsigned getRelaxedOpcode(unsigned Op) {
+  switch (Op) {
+  default:
+    return Op;
+
+  case X86::JAE_1: return X86::JAE_4;
+  case X86::JA_1:  return X86::JA_4;
+  case X86::JBE_1: return X86::JBE_4;
+  case X86::JB_1:  return X86::JB_4;
+  case X86::JE_1:  return X86::JE_4;
+  case X86::JGE_1: return X86::JGE_4;
+  case X86::JG_1:  return X86::JG_4;
+  case X86::JLE_1: return X86::JLE_4;
+  case X86::JL_1:  return X86::JL_4;
+  case X86::JMP_1: return X86::JMP_4;
+  case X86::JNE_1: return X86::JNE_4;
+  case X86::JNO_1: return X86::JNO_4;
+  case X86::JNP_1: return X86::JNP_4;
+  case X86::JNS_1: return X86::JNS_4;
+  case X86::JO_1:  return X86::JO_4;
+  case X86::JP_1:  return X86::JP_4;
+  case X86::JS_1:  return X86::JS_4;
+  }
+}
+
+// FIXME: Can tblgen help at all here to verify there aren't other instructions
+// we can relax?
+void X86AsmBackend::RelaxInstruction(const MCInstFragment *IF,
+                                     MCInst &Res) const {
+  // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
+  unsigned RelaxedOp = getRelaxedOpcode(IF->getInst().getOpcode());
+
+  if (RelaxedOp == IF->getInst().getOpcode()) {
+    SmallString<256> Tmp;
+    raw_svector_ostream OS(Tmp);
+    IF->getInst().dump_pretty(OS);
+    llvm_report_error("unexpected instruction to relax: " + OS.str());
+  }
+
+  Res = IF->getInst();
+  Res.setOpcode(RelaxedOp);
+}
+
+/* *** */
+
 class ELFX86AsmBackend : public X86AsmBackend {
 public:
   ELFX86AsmBackend(const Target &T)




From daniel at zuster.org  Mon Mar 22 21:36:58 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 23 Mar 2010 02:36:58 -0000
Subject: [llvm-commits] [llvm] r99248 - in /llvm/trunk:
 include/llvm/Target/TargetAsmBackend.h lib/MC/MCAssembler.cpp
 lib/MC/MCMachOStreamer.cpp lib/Target/X86/X86AsmBackend.cpp
Message-ID: <20100323023658.A8F682A6C12C@llvm.org>

Author: ddunbar
Date: Mon Mar 22 21:36:58 2010
New Revision: 99248

URL: http://llvm.org/viewvc/llvm-project?rev=99248&view=rev
Log:
MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler.

Modified:
    llvm/trunk/include/llvm/Target/TargetAsmBackend.h
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MCMachOStreamer.cpp
    llvm/trunk/lib/Target/X86/X86AsmBackend.cpp

Modified: llvm/trunk/include/llvm/Target/TargetAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmBackend.h?rev=99248&r1=99247&r2=99248&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetAsmBackend.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmBackend.h Mon Mar 22 21:36:58 2010
@@ -102,6 +102,13 @@
   /// wider instruction.
   virtual void RelaxInstruction(const MCInstFragment *IF,
                                 MCInst &Res) const = 0;
+
+  /// WriteNopData - Write an (optimal) nop sequence of Count bytes to the given
+  /// output. If the target cannot generate such a sequence, it should return an
+  /// error.
+  ///
+  /// \return - True on success.
+  virtual bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const = 0;
 };
 
 } // End llvm namespace

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99248&r1=99247&r2=99248&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Mar 22 21:36:58 2010
@@ -373,66 +373,9 @@
     SD.setFileSize(Address - SD.getAddress());
 }
 
-/// WriteNopData - Write optimal nops to the output file for the \arg Count
-/// bytes.  This returns the number of bytes written.  It may return 0 if
-/// the \arg Count is more than the maximum optimal nops.
-///
-/// FIXME this is X86 32-bit specific and should move to a better place.
-static uint64_t WriteNopData(uint64_t Count, MCObjectWriter *OW) {
-  static const uint8_t Nops[16][16] = {
-    // nop
-    {0x90},
-    // xchg %ax,%ax
-    {0x66, 0x90},
-    // nopl (%[re]ax)
-    {0x0f, 0x1f, 0x00},
-    // nopl 0(%[re]ax)
-    {0x0f, 0x1f, 0x40, 0x00},
-    // nopl 0(%[re]ax,%[re]ax,1)
-    {0x0f, 0x1f, 0x44, 0x00, 0x00},
-    // nopw 0(%[re]ax,%[re]ax,1)
-    {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
-    // nopl 0L(%[re]ax)
-    {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
-    // nopl 0L(%[re]ax,%[re]ax,1)
-    {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
-    // nopw 0L(%[re]ax,%[re]ax,1)
-    {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
-    // nopw %cs:0L(%[re]ax,%[re]ax,1)
-    {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
-    // nopl 0(%[re]ax,%[re]ax,1)
-    // nopw 0(%[re]ax,%[re]ax,1)
-    {0x0f, 0x1f, 0x44, 0x00, 0x00,
-     0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
-    // nopw 0(%[re]ax,%[re]ax,1)
-    // nopw 0(%[re]ax,%[re]ax,1)
-    {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
-     0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
-    // nopw 0(%[re]ax,%[re]ax,1)
-    // nopl 0L(%[re]ax) */
-    {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
-     0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
-    // nopl 0L(%[re]ax)
-    // nopl 0L(%[re]ax)
-    {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
-     0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
-    // nopl 0L(%[re]ax)
-    // nopl 0L(%[re]ax,%[re]ax,1)
-    {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
-     0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}
-  };
-
-  if (Count > 15)
-    return 0;
-
-  for (uint64_t i = 0; i < Count; i++)
-    OW->Write8(uint8_t(Nops[Count - 1][i]));
-
-  return Count;
-}
-
 /// WriteFragmentData - Write the \arg F data to the output file.
-static void WriteFragmentData(const MCFragment &F, MCObjectWriter *OW) {
+static void WriteFragmentData(const MCAssembler &Asm, const MCFragment &F,
+                              MCObjectWriter *OW) {
   uint64_t Start = OW->getStream().tell();
   (void) Start;
 
@@ -456,11 +399,15 @@
     // See if we are aligning with nops, and if so do that first to try to fill
     // the Count bytes.  Then if that did not fill any bytes or there are any
     // bytes left to fill use the the Value and ValueSize to fill the rest.
+    // If we are aligning with nops, ask that target to emit the right data.
     if (AF.getEmitNops()) {
-      uint64_t NopByteCount = WriteNopData(Count, OW);
-      Count -= NopByteCount;
+      if (!Asm.getBackend().WriteNopData(Count, OW))
+        llvm_report_error("unable to write nop sequence of " +
+                          Twine(Count) + " bytes");
+      break;
     }
 
+    // Otherwise, write out in multiples of the value size.
     for (uint64_t i = 0; i != Count; ++i) {
       switch (AF.getValueSize()) {
       default:
@@ -531,7 +478,7 @@
 
   for (MCSectionData::const_iterator it = SD->begin(),
          ie = SD->end(); it != ie; ++it)
-    WriteFragmentData(*it, OW);
+    WriteFragmentData(*this, *it, OW);
 
   // Add section padding.
   assert(SD->getFileSize() >= SD->getSize() && "Invalid section sizes!");

Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=99248&r1=99247&r2=99248&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Mon Mar 22 21:36:58 2010
@@ -353,8 +353,7 @@
                                         unsigned MaxBytesToEmit) {
   if (MaxBytesToEmit == 0)
     MaxBytesToEmit = ByteAlignment;
-  // FIXME: The 0x90 is the default x86 1 byte nop opcode.
-  new MCAlignFragment(ByteAlignment, 0x90, 1, MaxBytesToEmit,
+  new MCAlignFragment(ByteAlignment, 0, 1, MaxBytesToEmit,
                       true /* EmitNops */, CurSectionData);
 
   // Update the maximum alignment on the current section if necessary.

Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=99248&r1=99247&r2=99248&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Mon Mar 22 21:36:58 2010
@@ -53,6 +53,8 @@
   }
 
   void RelaxInstruction(const MCInstFragment *IF, MCInst &Res) const;
+
+  bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
 };
 
 static unsigned getRelaxedOpcode(unsigned Op) {
@@ -98,6 +100,67 @@
   Res.setOpcode(RelaxedOp);
 }
 
+/// WriteNopData - Write optimal nops to the output file for the \arg Count
+/// bytes.  This returns the number of bytes written.  It may return 0 if
+/// the \arg Count is more than the maximum optimal nops.
+///
+/// FIXME this is X86 32-bit specific and should move to a better place.
+bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
+  static const uint8_t Nops[16][16] = {
+    // nop
+    {0x90},
+    // xchg %ax,%ax
+    {0x66, 0x90},
+    // nopl (%[re]ax)
+    {0x0f, 0x1f, 0x00},
+    // nopl 0(%[re]ax)
+    {0x0f, 0x1f, 0x40, 0x00},
+    // nopl 0(%[re]ax,%[re]ax,1)
+    {0x0f, 0x1f, 0x44, 0x00, 0x00},
+    // nopw 0(%[re]ax,%[re]ax,1)
+    {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
+    // nopl 0L(%[re]ax)
+    {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
+    // nopl 0L(%[re]ax,%[re]ax,1)
+    {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
+    // nopw 0L(%[re]ax,%[re]ax,1)
+    {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
+    // nopw %cs:0L(%[re]ax,%[re]ax,1)
+    {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
+    // nopl 0(%[re]ax,%[re]ax,1)
+    // nopw 0(%[re]ax,%[re]ax,1)
+    {0x0f, 0x1f, 0x44, 0x00, 0x00,
+     0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
+    // nopw 0(%[re]ax,%[re]ax,1)
+    // nopw 0(%[re]ax,%[re]ax,1)
+    {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
+     0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
+    // nopw 0(%[re]ax,%[re]ax,1)
+    // nopl 0L(%[re]ax) */
+    {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
+     0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
+    // nopl 0L(%[re]ax)
+    // nopl 0L(%[re]ax)
+    {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
+     0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
+    // nopl 0L(%[re]ax)
+    // nopl 0L(%[re]ax,%[re]ax,1)
+    {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
+     0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}
+  };
+
+  // Write an optimal sequence for the first 15 bytes.
+  uint64_t OptimalCount = (Count < 16) ? Count : 15;
+  for (uint64_t i = 0, e = OptimalCount; i != e; i++)
+    OW->Write8(Nops[OptimalCount - 1][i]);
+
+  // Finish with single byte nops.
+  for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
+   OW->Write8(0x90);
+
+  return true;
+}
+
 /* *** */
 
 class ELFX86AsmBackend : public X86AsmBackend {




From daniel at zuster.org  Mon Mar 22 22:13:05 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 23 Mar 2010 03:13:05 -0000
Subject: [llvm-commits] [llvm] r99249 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h include/llvm/Target/TargetAsmBackend.h
 lib/MC/MCAssembler.cpp lib/MC/MCMachOStreamer.cpp
 lib/Target/X86/X86AsmBackend.cpp
Message-ID: <20100323031305.A3CE22A6C12C@llvm.org>

Author: ddunbar
Date: Mon Mar 22 22:13:05 2010
New Revision: 99249

URL: http://llvm.org/viewvc/llvm-project?rev=99249&view=rev
Log:
MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation.

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/include/llvm/Target/TargetAsmBackend.h
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MCMachOStreamer.cpp
    llvm/trunk/lib/Target/X86/X86AsmBackend.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99249&r1=99248&r2=99249&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Mon Mar 22 22:13:05 2010
@@ -679,6 +679,10 @@
   bool FixupNeedsRelaxation(const MCAsmFixup &Fixup, const MCFragment *DF,
                             const MCAsmLayout &Layout) const;
 
+  /// Check whether the given fragment needs relaxation.
+  bool FragmentNeedsRelaxation(const MCInstFragment *IF,
+                               const MCAsmLayout &Layout) const;
+
   /// LayoutSection - Assign offsets and sizes to the fragments in the section
   /// \arg SD, and update the section size. The section file offset should
   /// already have been computed.

Modified: llvm/trunk/include/llvm/Target/TargetAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmBackend.h?rev=99249&r1=99248&r2=99249&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetAsmBackend.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmBackend.h Mon Mar 22 22:13:05 2010
@@ -19,6 +19,8 @@
 class MCInstFragment;
 class MCObjectWriter;
 class MCSection;
+template<typename T>
+class SmallVectorImpl;
 class Target;
 class raw_ostream;
 
@@ -98,6 +100,15 @@
   virtual void ApplyFixup(const MCAsmFixup &Fixup, MCDataFragment &Fragment,
                           uint64_t Value) const = 0;
 
+  /// MayNeedRelaxation - Check whether the given instruction may need
+  /// relaxation.
+  ///
+  /// \arg Inst - The instruction to test.
+  /// \arg Fixups - The actual fixups this instruction encoded to, for potential
+  /// use by the target backend.
+  virtual bool MayNeedRelaxation(const MCInst &Inst,
+                           const SmallVectorImpl<MCAsmFixup> &Fixups) const = 0;
+
   /// RelaxInstruction - Relax the instruction in the given fragment to the next
   /// wider instruction.
   virtual void RelaxInstruction(const MCInstFragment *IF,

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99249&r1=99248&r2=99249&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Mar 22 22:13:05 2010
@@ -715,7 +715,7 @@
 
       // Create a new data fragment for the instruction.
       //
-      // FIXME: Reuse previous data fragment if possible.
+      // FIXME-PERF: Reuse previous data fragment if possible.
       MCDataFragment *DF = new MCDataFragment();
       SD.getFragmentList().insert(it2, DF);
 

Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=99249&r1=99248&r2=99249&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Mon Mar 22 22:13:05 2010
@@ -383,12 +383,19 @@
   Assembler.getEmitter().EncodeInstruction(Inst, VecOS, Fixups);
   VecOS.flush();
 
-  // Add the fixups and data.
-  MCDataFragment *DF = getOrCreateDataFragment();
+  // FIXME: Eliminate this copy.
+  SmallVector<MCAsmFixup, 4> AsmFixups;
   for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
     MCFixup &F = Fixups[i];
-    DF->addFixup(MCAsmFixup(DF->getContents().size()+F.getOffset(),
-                            *F.getValue(), F.getKind()));
+    AsmFixups.push_back(MCAsmFixup(F.getOffset(), *F.getValue(),
+                                   F.getKind()));
+  }
+
+  // Add the fixups and data.
+  MCDataFragment *DF = getOrCreateDataFragment();
+  for (unsigned i = 0, e = AsmFixups.size(); i != e; ++i) {
+    AsmFixups[i].Offset += DF->getContents().size();
+    DF->addFixup(AsmFixups[i]);
   }
   DF->getContents().append(Code.begin(), Code.end());
 }

Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=99249&r1=99248&r2=99249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Mon Mar 22 22:13:05 2010
@@ -12,6 +12,7 @@
 #include "X86FixupKinds.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MachObjectWriter.h"
@@ -52,6 +53,9 @@
       DF.getContents()[Fixup.Offset + i] = uint8_t(Value >> (i * 8));
   }
 
+  bool MayNeedRelaxation(const MCInst &Inst,
+                         const SmallVectorImpl<MCAsmFixup> &Fixups) const;
+
   void RelaxInstruction(const MCInstFragment *IF, MCInst &Res) const;
 
   bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
@@ -82,6 +86,20 @@
   }
 }
 
+bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst,
+                              const SmallVectorImpl<MCAsmFixup> &Fixups) const {
+  // Check for a 1byte pcrel fixup, and enforce that we would know how to relax
+  // this instruction.
+  for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
+    if (unsigned(Fixups[i].Kind) == X86::reloc_pcrel_1byte) {
+      assert(getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode());
+      return true;
+    }
+  }
+
+  return false;
+}
+
 // FIXME: Can tblgen help at all here to verify there aren't other instructions
 // we can relax?
 void X86AsmBackend::RelaxInstruction(const MCInstFragment *IF,




From daniel at zuster.org  Tue Mar 23 00:09:03 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 23 Mar 2010 05:09:03 -0000
Subject: [llvm-commits] [llvm] r99256 - in /llvm/trunk/lib/MC:
	MCAssembler.cpp MCMachOStreamer.cpp
Message-ID: <20100323050903.D38DF2A6C12C@llvm.org>

Author: ddunbar
Date: Tue Mar 23 00:09:03 2010
New Revision: 99256

URL: http://llvm.org/viewvc/llvm-project?rev=99256&view=rev
Log:
MC: Switch to using MCInst fragments to do relaxation.

Also, both MCMachOStreamer and MCAssembler are now target independent!

Modified:
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MCMachOStreamer.cpp

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99256&r1=99255&r2=99256&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Tue Mar 23 00:09:03 2010
@@ -25,9 +25,6 @@
 #include "llvm/Target/TargetRegistry.h"
 #include "llvm/Target/TargetAsmBackend.h"
 
-// FIXME: Gross.
-#include "../Target/X86/X86FixupKinds.h"
-
 #include <vector>
 using namespace llvm;
 
@@ -551,10 +548,6 @@
 bool MCAssembler::FixupNeedsRelaxation(const MCAsmFixup &Fixup,
                                        const MCFragment *DF,
                                        const MCAsmLayout &Layout) const {
-  // Currently we only need to relax X86::reloc_pcrel_1byte.
-  if (unsigned(Fixup.Kind) != X86::reloc_pcrel_1byte)
-    return false;
-
   // If we cannot resolve the fixup value, it requires relaxation.
   MCValue Target;
   uint64_t Value;
@@ -565,6 +558,22 @@
   return int64_t(Value) != int64_t(int8_t(Value));
 }
 
+bool MCAssembler::FragmentNeedsRelaxation(const MCInstFragment *IF,
+                                          const MCAsmLayout &Layout) const {
+  // If this inst doesn't ever need relaxation, ignore it. This occurs when we
+  // are intentionally pushing out inst fragments, or because we relaxed a
+  // previous instruction to one that doesn't need relaxation.
+  if (!getBackend().MayNeedRelaxation(IF->getInst(), IF->getFixups()))
+    return false;
+
+  for (MCInstFragment::const_fixup_iterator it = IF->fixup_begin(),
+         ie = IF->fixup_end(); it != ie; ++it)
+    if (FixupNeedsRelaxation(*it, IF, Layout))
+      return true;
+
+  return false;
+}
+
 bool MCAssembler::LayoutOnce(MCAsmLayout &Layout) {
   // Layout the concrete sections and fragments.
   uint64_t Address = 0;
@@ -609,87 +618,50 @@
     Address += SD.getSize();
   }
 
-  // Scan the fixups in order and relax any that don't fit.
+  // Scan for fragments that need relaxation.
   for (iterator it = begin(), ie = end(); it != ie; ++it) {
     MCSectionData &SD = *it;
 
     for (MCSectionData::iterator it2 = SD.begin(),
            ie2 = SD.end(); it2 != ie2; ++it2) {
-      MCDataFragment *DF = dyn_cast<MCDataFragment>(it2);
-      if (!DF)
+      // Check if this is an instruction fragment that needs relaxation.
+      MCInstFragment *IF = dyn_cast<MCInstFragment>(it2);
+      if (!IF || !FragmentNeedsRelaxation(IF, Layout))
         continue;
 
-      for (MCDataFragment::fixup_iterator it3 = DF->fixup_begin(),
-             ie3 = DF->fixup_end(); it3 != ie3; ++it3) {
-        MCAsmFixup &Fixup = *it3;
-
-        // Check whether we need to relax this fixup.
-        if (!FixupNeedsRelaxation(Fixup, DF, Layout))
-          continue;
-
-        // Relax the instruction.
-        //
-        // FIXME: This is a huge temporary hack which just looks for x86
-        // branches; the only thing we need to relax on x86 is
-        // 'X86::reloc_pcrel_1byte'. Once we have MCInst fragments, this will be
-        // replaced by a TargetAsmBackend hook (most likely tblgen'd) to relax
-        // an individual MCInst.
-        SmallVectorImpl<char> &C = DF->getContents();
-        uint64_t PrevOffset = Fixup.Offset;
-        unsigned Amt = 0;
-
-          // jcc instructions
-        if (unsigned(C[Fixup.Offset-1]) >= 0x70 &&
-            unsigned(C[Fixup.Offset-1]) <= 0x7f) {
-          C[Fixup.Offset] = C[Fixup.Offset-1] + 0x10;
-          C[Fixup.Offset-1] = char(0x0f);
-          ++Fixup.Offset;
-          Amt = 4;
-
-          // jmp rel8
-        } else if (C[Fixup.Offset-1] == char(0xeb)) {
-          C[Fixup.Offset-1] = char(0xe9);
-          Amt = 3;
-
-        } else
-          llvm_unreachable("unknown 1 byte pcrel instruction!");
-
-        Fixup.Value = MCBinaryExpr::Create(
-          MCBinaryExpr::Sub, Fixup.Value,
-          MCConstantExpr::Create(3, getContext()),
-          getContext());
-        C.insert(C.begin() + Fixup.Offset, Amt, char(0));
-        Fixup.Kind = MCFixupKind(X86::reloc_pcrel_4byte);
-
-        // Update the remaining fixups, which have slid.
-        //
-        // FIXME: This is bad for performance, but will be eliminated by the
-        // move to MCInst specific fragments.
-        ++it3;
-        for (; it3 != ie3; ++it3)
-          it3->Offset += Amt;
-
-        // Update all the symbols for this fragment, which may have slid.
-        //
-        // FIXME: This is really really bad for performance, but will be
-        // eliminated by the move to MCInst specific fragments.
-        for (MCAssembler::symbol_iterator it = symbol_begin(),
-               ie = symbol_end(); it != ie; ++it) {
-          MCSymbolData &SD = *it;
+      // FIXME-PERF: We could immediately lower out instructions if we can tell
+      // they are fully resolved, to avoid retesting on later passes.
 
-          if (it->getFragment() != DF)
-            continue;
+      // Relax the fragment.
 
-          if (SD.getOffset() > PrevOffset)
-            SD.setOffset(SD.getOffset() + Amt);
-        }
+      MCInst Relaxed;
+      getBackend().RelaxInstruction(IF, Relaxed);
 
-        // Restart layout.
-        //
-        // FIXME-PERF: This is O(N^2), but will be eliminated once we have a
-        // smart MCAsmLayout object.
-        return true;
+      // Encode the new instruction.
+      //
+      // FIXME-PERF: If it matters, we could let the target do this. It can
+      // probably do so more efficiently in many cases.
+      SmallVector<MCFixup, 4> Fixups;
+      SmallString<256> Code;
+      raw_svector_ostream VecOS(Code);
+      getEmitter().EncodeInstruction(Relaxed, VecOS, Fixups);
+      VecOS.flush();
+
+      // Update the instruction fragment.
+      IF->setInst(Relaxed);
+      IF->getCode() = Code;
+      IF->getFixups().clear();
+      for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
+        MCFixup &F = Fixups[i];
+        IF->getFixups().push_back(MCAsmFixup(F.getOffset(), *F.getValue(),
+                                             F.getKind()));
       }
+
+      // Restart layout.
+      //
+      // FIXME-PERF: This is O(N^2), but will be eliminated once we have a
+      // smart MCAsmLayout object.
+      return true;
     }
   }
 

Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=99256&r1=99255&r2=99256&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Tue Mar 23 00:09:03 2010
@@ -18,6 +18,8 @@
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetAsmBackend.h"
+
 using namespace llvm;
 
 namespace {
@@ -391,6 +393,32 @@
                                    F.getKind()));
   }
 
+  // See if we might need to relax this instruction, if so it needs its own
+  // fragment.
+  //
+  // FIXME-PERF: Support target hook to do a fast path that avoids the encoder,
+  // when we can immediately tell that we will get something which might need
+  // relaxation (and compute its size).
+  //
+  // FIXME-PERF: We should also be smart about immediately relaxing instructions
+  // which we can already show will never possibly fit (we can also do a very
+  // good job of this before we do the first relaxation pass, because we have
+  // total knowledge about undefined symbols at that point). Even now, though,
+  // we can do a decent job, especially on Darwin where scattering means that we
+  // are going to often know that we can never fully resolve a fixup.
+  if (Assembler.getBackend().MayNeedRelaxation(Inst, AsmFixups)) {
+    MCInstFragment *IF = new MCInstFragment(Inst, CurSectionData);
+
+    // Add the fixups and data.
+    //
+    // FIXME: Revisit this design decision when relaxation is done, we may be
+    // able to get away with not storing any extra data in the MCInst.
+    IF->getCode() = Code;
+    IF->getFixups() = AsmFixups;
+
+    return;
+  }
+
   // Add the fixups and data.
   MCDataFragment *DF = getOrCreateDataFragment();
   for (unsigned i = 0, e = AsmFixups.size(); i != e; ++i) {




From bob.wilson at apple.com  Tue Mar 23 00:25:43 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 23 Mar 2010 05:25:43 -0000
Subject: [llvm-commits] [llvm] r99261 - in /llvm/trunk/lib/Target/ARM:
 ARMBaseInstrInfo.cpp ARMISelDAGToDAG.cpp ARMInstrNEON.td
 NEONPreAllocPass.cpp
Message-ID: <20100323052543.77F932A6C12C@llvm.org>

Author: bwilson
Date: Tue Mar 23 00:25:43 2010
New Revision: 99261

URL: http://llvm.org/viewvc/llvm-project?rev=99261&view=rev
Log:
Change VLD1 instructions for loading Q register values to operate on pairs
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=99261&r1=99260&r2=99261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Mar 23 00:25:43 2010
@@ -788,7 +788,7 @@
             RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
     if (Align >= 16
         && (getRegisterInfo().canRealignStack(MF))) {
-      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
+      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
                      .addFrameIndex(FI).addImm(128)
                      .addMemOperand(MMO));
     } else {

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=99261&r1=99260&r2=99261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Mar 23 00:25:43 2010
@@ -124,10 +124,10 @@
   /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
   SDNode *SelectDYN_ALLOC(SDNode *N);
 
-  /// SelectVLD - Select NEON load intrinsics.  NumVecs should
-  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
+  /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
+  /// 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
   /// loads of D registers and even subregs and odd subregs of Q registers.
-  /// For NumVecs == 2, QOpcodes1 is not used.
+  /// For NumVecs <= 2, QOpcodes1 is not used.
   SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
                     unsigned *QOpcodes0, unsigned *QOpcodes1);
 
@@ -1022,7 +1022,7 @@
 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
                                    unsigned *DOpcodes, unsigned *QOpcodes0,
                                    unsigned *QOpcodes1) {
-  assert(NumVecs >=2 && NumVecs <= 4 && "VLD NumVecs out-of-range");
+  assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
   DebugLoc dl = N->getDebugLoc();
 
   SDValue MemAddr, Align;
@@ -1047,6 +1047,9 @@
   case MVT::v8i16: OpcodeIndex = 1; break;
   case MVT::v4f32:
   case MVT::v4i32: OpcodeIndex = 2; break;
+  case MVT::v2i64: OpcodeIndex = 3;
+    assert(NumVecs == 1 && "v2i64 type only supported for VLD1/VST1");
+    break;
   }
 
   SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
@@ -1060,15 +1063,15 @@
   }
 
   EVT RegVT = GetNEONSubregVT(VT);
-  if (NumVecs == 2) {
-    // Quad registers are directly supported for VLD2,
-    // loading 2 pairs of D regs.
+  if (NumVecs <= 2) {
+    // Quad registers are directly supported for VLD1 and VLD2,
+    // loading pairs of D regs.
     unsigned Opc = QOpcodes0[OpcodeIndex];
     const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
-    std::vector<EVT> ResTys(4, VT);
+    std::vector<EVT> ResTys(2 * NumVecs, RegVT);
     ResTys.push_back(MVT::Other);
     SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
-    Chain = SDValue(VLd, 4);
+    Chain = SDValue(VLd, 2 * NumVecs);
 
     // Combine the even and odd subregs to produce the result.
     for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
@@ -1831,9 +1834,17 @@
     default:
       break;
 
+    case Intrinsic::arm_neon_vld1: {
+      unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
+                              ARM::VLD1d32, ARM::VLD1d64 };
+      unsigned QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
+                              ARM::VLD1q32, ARM::VLD1q64 };
+      return SelectVLD(N, 1, DOpcodes, QOpcodes, 0);
+    }
+
     case Intrinsic::arm_neon_vld2: {
       unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
-                              ARM::VLD2d32, ARM::VLD2d64 };
+                              ARM::VLD2d32, ARM::VLD1q64 };
       unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 };
       return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
     }

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99261&r1=99260&r2=99261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 00:25:43 2010
@@ -116,6 +116,7 @@
 //===----------------------------------------------------------------------===//
 
 // Use vldmia to load a Q register as a D register pair.
+// This is equivalent to VLDMD except that it has a Q register operand.
 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoadm,
                 "vldmia", "$addr, ${dst:dregpair}",
                 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
@@ -126,6 +127,19 @@
   let Inst{11-8}  = 0b1011;
 }
 
+let mayLoad = 1 in {
+// Use vld1 to load a Q register as a D register pair.
+// This alternative to VLDRQ allows an alignment to be specified.
+// This is equivalent to VLD1q64 except that it has a Q register operand.
+def VLD1q
+  : NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst), (ins addrmode6:$addr),
+          IIC_VLD1, "vld1", "64", "${dst:dregpair}, $addr", "", []>;
+def VLD1q_UPD
+  : NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst, GPR:$wb),
+          (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", "64",
+          "${dst:dregpair}, $addr$offset", "$addr.addr = $wb", []>;
+} // mayLoad = 1
+
 // Use vstmia to store a Q register as a D register pair.
 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem,
                 "vstmia", "$addr, ${src:dregpair}",
@@ -137,29 +151,27 @@
   let Inst{11-8}  = 0b1011;
 }
 
-//   VLD1     : Vector Load (multiple single elements)
-class VLD1D<bits<4> op7_4, string Dt, ValueType Ty>
-  : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
-          "vld1", Dt, "\\{$dst\\}, $addr", "",
-          [(set DPR:$dst, (Ty (int_arm_neon_vld1 addrmode6:$addr)))]>;
-class VLD1Q<bits<4> op7_4, string Dt, ValueType Ty>
-  : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
-          "vld1", Dt, "${dst:dregpair}, $addr", "",
-          [(set QPR:$dst, (Ty (int_arm_neon_vld1 addrmode6:$addr)))]>;
-
-def  VLD1d8   : VLD1D<0b0000, "8",  v8i8>;
-def  VLD1d16  : VLD1D<0b0100, "16", v4i16>;
-def  VLD1d32  : VLD1D<0b1000, "32", v2i32>;
-def  VLD1df   : VLD1D<0b1000, "32", v2f32>;
-def  VLD1d64  : VLD1D<0b1100, "64", v1i64>;
-
-def  VLD1q8   : VLD1Q<0b0000, "8",  v16i8>;
-def  VLD1q16  : VLD1Q<0b0100, "16", v8i16>;
-def  VLD1q32  : VLD1Q<0b1000, "32", v4i32>;
-def  VLD1qf   : VLD1Q<0b1000, "32", v4f32>;
-def  VLD1q64  : VLD1Q<0b1100, "64", v2i64>;
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
 
-let mayLoad = 1 in {
+//   VLD1     : Vector Load (multiple single elements)
+class VLD1D<bits<4> op7_4, string Dt>
+  : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst),
+          (ins addrmode6:$addr), IIC_VLD1,
+          "vld1", Dt, "\\{$dst\\}, $addr", "", []>;
+class VLD1Q<bits<4> op7_4, string Dt>
+  : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2),
+          (ins addrmode6:$addr), IIC_VLD1,
+          "vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
+
+def  VLD1d8   : VLD1D<0b0000, "8">;
+def  VLD1d16  : VLD1D<0b0100, "16">;
+def  VLD1d32  : VLD1D<0b1000, "32">;
+def  VLD1d64  : VLD1D<0b1100, "64">;
+
+def  VLD1q8   : VLD1Q<0b0000, "8">;
+def  VLD1q16  : VLD1Q<0b0100, "16">;
+def  VLD1q32  : VLD1Q<0b1000, "32">;
+def  VLD1q64  : VLD1Q<0b1100, "64">;
 
 // ...with address register writeback:
 class VLD1DWB<bits<4> op7_4, string Dt>
@@ -182,9 +194,6 @@
 def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
 def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
 def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
-} // mayLoad = 1
-
-let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
 
 // ...with 3 registers (some of these are only for the disassembler):
 class VLD1D3<bits<4> op7_4, string Dt>
@@ -242,9 +251,6 @@
 def  VLD2d8   : VLD2D<0b1000, 0b0000, "8">;
 def  VLD2d16  : VLD2D<0b1000, 0b0100, "16">;
 def  VLD2d32  : VLD2D<0b1000, 0b1000, "32">;
-def  VLD2d64  : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
-                      (ins addrmode6:$addr), IIC_VLD1,
-                      "vld1", "64", "\\{$dst1, $dst2\\}, $addr", "", []>;
 
 def  VLD2q8   : VLD2Q<0b0000, "8">;
 def  VLD2q16  : VLD2Q<0b0100, "16">;
@@ -266,11 +272,6 @@
 def VLD2d8_UPD  : VLD2DWB<0b1000, 0b0000, "8">;
 def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">;
 def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">;
-def VLD2d64_UPD : NLdSt<0,0b10,0b1010,0b1100,
-                        (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
-                        (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
-                        "vld1", "64", "\\{$dst1, $dst2\\}, $addr$offset",
-                        "$addr.addr = $wb", []>;
 
 def VLD2q8_UPD  : VLD2QWB<0b0000, "8">;
 def VLD2q16_UPD : VLD2QWB<0b0100, "16">;

Modified: llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp?rev=99261&r1=99260&r2=99261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Tue Mar 23 00:25:43 2010
@@ -46,10 +46,17 @@
   default:
     break;
 
+  case ARM::VLD1q8:
+  case ARM::VLD1q16:
+  case ARM::VLD1q32:
+  case ARM::VLD1q64:
+    FirstOpnd = 0;
+    NumRegs = 2;
+    return true;
+
   case ARM::VLD2d8:
   case ARM::VLD2d16:
   case ARM::VLD2d32:
-  case ARM::VLD2d64:
   case ARM::VLD2LNd8:
   case ARM::VLD2LNd16:
   case ARM::VLD2LNd32:




From bob.wilson at apple.com  Tue Mar 23 00:50:14 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 23 Mar 2010 05:50:14 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r99262 -
	/llvm-gcc-4.2/trunk/libgomp/Makefile.in
Message-ID: <20100323055014.606F42A6C12C@llvm.org>

Author: bwilson
Date: Tue Mar 23 00:50:14 2010
New Revision: 99262

URL: http://llvm.org/viewvc/llvm-project?rev=99262&view=rev
Log:
Try again to fix the intermittent build failures that we've been seeing when
building libgomp.  Since the error occurs when invoking the recursive make for
the "all-multi" target, add a dependency to prevent this make from running at
the same time as the compilations for the non-multilib version of libgomp.

Modified:
    llvm-gcc-4.2/trunk/libgomp/Makefile.in

Modified: llvm-gcc-4.2/trunk/libgomp/Makefile.in
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/libgomp/Makefile.in?rev=99262&r1=99261&r2=99262&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/libgomp/Makefile.in (original)
+++ llvm-gcc-4.2/trunk/libgomp/Makefile.in Tue Mar 23 00:50:14 2010
@@ -457,6 +457,9 @@
 distclean-libtool:
 	-rm -f libtool
 
+# LLVM LOCAL: Try to avoid a mysterious race condition by adding a dependency.
+all-multi: $(LTLIBRARIES)
+
 # GNU Make needs to see an explicit $(MAKE) variable in the command it
 # runs to enable its job server during parallel builds.  Hence the
 # comments below.




From evan.cheng at apple.com  Tue Mar 23 01:06:10 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 23 Mar 2010 06:06:10 -0000
Subject: [llvm-commits] [llvm] r99263 - in /llvm/trunk:
 lib/Transforms/InstCombine/InstCombineCalls.cpp
 test/Transforms/InstCombine/objsize.ll
Message-ID: <20100323060610.115E62A6C12C@llvm.org>

Author: evancheng
Date: Tue Mar 23 01:06:09 2010
New Revision: 99263

URL: http://llvm.org/viewvc/llvm-project?rev=99263&view=rev
Log:
Fix an incorrect logic causing instcombine to miss some _chk -> non-chk transformations.

Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
    llvm/trunk/test/Transforms/InstCombine/objsize.ll

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=99263&r1=99262&r2=99263&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Tue Mar 23 01:06:09 2010
@@ -766,7 +766,7 @@
         return SizeCI->getZExtValue() >=
                GetStringLength(CI->getOperand(SizeArgOp));
       if (ConstantInt *Arg = dyn_cast<ConstantInt>(CI->getOperand(SizeArgOp)))
-        return SizeCI->getZExtValue() <= Arg->getZExtValue();
+        return SizeCI->getZExtValue() >= Arg->getZExtValue();
     }
     return false;
   }

Modified: llvm/trunk/test/Transforms/InstCombine/objsize.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/objsize.ll?rev=99263&r1=99262&r2=99263&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/objsize.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/objsize.ll Tue Mar 23 01:06:09 2010
@@ -118,6 +118,7 @@
   ret i32 0
 }
 
+; rdar://7782496
 @s = external global i8*
 
 define void @test5(i32 %n) nounwind ssp {
@@ -127,11 +128,23 @@
   %1 = tail call i32 @llvm.objectsize.i32(i8* %0, i1 false)
   %2 = load i8** @s, align 8
 ; CHECK-NOT: @llvm.objectsize
-; CHECK: @__memcpy_chk(i8* %0, i8* %1, i32 10, i32 20)
+; CHECK: @llvm.memcpy.i32(i8* %0, i8* %1, i32 10, i32 1)
   %3 = tail call i8* @__memcpy_chk(i8* %0, i8* %2, i32 10, i32 %1) nounwind
   ret void
 }
 
+define void @test6(i32 %n) nounwind ssp {
+; CHECK: @test6
+entry:
+  %0 = tail call noalias i8* @malloc(i32 20) nounwind
+  %1 = tail call i32 @llvm.objectsize.i32(i8* %0, i1 false)
+  %2 = load i8** @s, align 8
+; CHECK-NOT: @llvm.objectsize
+; CHECK: @__memcpy_chk(i8* %0, i8* %1, i32 30, i32 20)
+  %3 = tail call i8* @__memcpy_chk(i8* %0, i8* %2, i32 30, i32 %1) nounwind
+  ret void
+}
+
 declare i8* @__memset_chk(i8*, i32, i64, i64) nounwind
 
 declare noalias i8* @malloc(i32) nounwind




From bob.wilson at apple.com  Tue Mar 23 01:20:33 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 23 Mar 2010 06:20:33 -0000
Subject: [llvm-commits] [llvm] r99265 - in /llvm/trunk/lib/Target/ARM:
 ARMBaseInstrInfo.cpp ARMISelDAGToDAG.cpp ARMInstrNEON.td
 NEONPreAllocPass.cpp
Message-ID: <20100323062033.909262A6C12C@llvm.org>

Author: bwilson
Date: Tue Mar 23 01:20:33 2010
New Revision: 99265

URL: http://llvm.org/viewvc/llvm-project?rev=99265&view=rev
Log:
Change VST1 instructions for loading Q register values to operate on pairs
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.


Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=99265&r1=99264&r2=99265&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Mar 23 01:20:33 2010
@@ -738,7 +738,7 @@
             RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
     // FIXME: Neon instructions should support predicates
     if (Align >= 16 && (getRegisterInfo().canRealignStack(MF))) {
-      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
+      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
                      .addFrameIndex(FI).addImm(128)
                      .addMemOperand(MMO)
                      .addReg(SrcReg, getKillRegState(isKill)));

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=99265&r1=99264&r2=99265&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Mar 23 01:20:33 2010
@@ -132,9 +132,9 @@
                     unsigned *QOpcodes0, unsigned *QOpcodes1);
 
   /// SelectVST - Select NEON store intrinsics.  NumVecs should
-  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
+  /// be 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
   /// stores of D registers and even subregs and odd subregs of Q registers.
-  /// For NumVecs == 2, QOpcodes1 is not used.
+  /// For NumVecs <= 2, QOpcodes1 is not used.
   SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
                     unsigned *QOpcodes0, unsigned *QOpcodes1);
 
@@ -1048,7 +1048,7 @@
   case MVT::v4f32:
   case MVT::v4i32: OpcodeIndex = 2; break;
   case MVT::v2i64: OpcodeIndex = 3;
-    assert(NumVecs == 1 && "v2i64 type only supported for VLD1/VST1");
+    assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
     break;
   }
 
@@ -1112,7 +1112,7 @@
 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
                                    unsigned *DOpcodes, unsigned *QOpcodes0,
                                    unsigned *QOpcodes1) {
-  assert(NumVecs >=2 && NumVecs <= 4 && "VST NumVecs out-of-range");
+  assert(NumVecs >=1 && NumVecs <= 4 && "VST NumVecs out-of-range");
   DebugLoc dl = N->getDebugLoc();
 
   SDValue MemAddr, Align;
@@ -1137,6 +1137,9 @@
   case MVT::v8i16: OpcodeIndex = 1; break;
   case MVT::v4f32:
   case MVT::v4i32: OpcodeIndex = 2; break;
+  case MVT::v2i64: OpcodeIndex = 3;
+    assert(NumVecs == 1 && "v2i64 type only supported for VST1");
+    break;
   }
 
   SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
@@ -1157,9 +1160,9 @@
   }
 
   EVT RegVT = GetNEONSubregVT(VT);
-  if (NumVecs == 2) {
-    // Quad registers are directly supported for VST2,
-    // storing 2 pairs of D regs.
+  if (NumVecs <= 2) {
+    // Quad registers are directly supported for VST1 and VST2,
+    // storing pairs of D regs.
     unsigned Opc = QOpcodes0[OpcodeIndex];
     for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
       Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
@@ -1170,7 +1173,8 @@
     Ops.push_back(Pred);
     Ops.push_back(Reg0); // predicate register
     Ops.push_back(Chain);
-    return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 9);
+    return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(),
+                                  5 + 2 * NumVecs);
   }
 
   // Otherwise, quad registers are stored with two separate instructions,
@@ -1894,9 +1898,17 @@
       return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
     }
 
+    case Intrinsic::arm_neon_vst1: {
+      unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
+                              ARM::VST1d32, ARM::VST1d64 };
+      unsigned QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
+                              ARM::VST1q32, ARM::VST1q64 };
+      return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
+    }
+
     case Intrinsic::arm_neon_vst2: {
       unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
-                              ARM::VST2d32, ARM::VST2d64 };
+                              ARM::VST2d32, ARM::VST1q64 };
       unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
       return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
     }

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99265&r1=99264&r2=99265&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 01:20:33 2010
@@ -141,6 +141,7 @@
 } // mayLoad = 1
 
 // Use vstmia to store a Q register as a D register pair.
+// This is equivalent to VSTMD except that it has a Q register operand.
 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem,
                 "vstmia", "$addr, ${src:dregpair}",
                 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
@@ -151,6 +152,20 @@
   let Inst{11-8}  = 0b1011;
 }
 
+let mayStore = 1 in {
+// Use vst1 to store a Q register as a D register pair.
+// This alternative to VSTRQ allows an alignment to be specified.
+// This is equivalent to VST1q64 except that it has a Q register operand.
+def VST1q
+  : NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, QPR:$src),
+          IIC_VST, "vst1", "64", "${src:dregpair}, $addr", "", []>;
+def VST1q_UPD
+  : NLdSt<0,0b00,0b1010,0b1100, (outs GPR:$wb),
+          (ins addrmode6:$addr, am6offset:$offset, QPR:$src),
+          IIC_VST, "vst1", "64", "{$src:dregpair}, $addr$offset",
+          "$addr.addr = $wb", []>;
+} // mayStore = 1
+
 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
 
 //   VLD1     : Vector Load (multiple single elements)
@@ -477,31 +492,26 @@
 //   FIXME: Not yet implemented.
 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
 
+let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
+
 //   VST1     : Vector Store (multiple single elements)
-class VST1D<bits<4> op7_4, string Dt, ValueType Ty>
+class VST1D<bits<4> op7_4, string Dt>
   : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
-          "vst1", Dt, "\\{$src\\}, $addr", "",
-          [(int_arm_neon_vst1 addrmode6:$addr, (Ty DPR:$src))]>;
-class VST1Q<bits<4> op7_4, string Dt, ValueType Ty>
-  : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
-          "vst1", Dt, "${src:dregpair}, $addr", "",
-          [(int_arm_neon_vst1 addrmode6:$addr, (Ty QPR:$src))]>;
-
-let hasExtraSrcRegAllocReq = 1 in {
-def  VST1d8   : VST1D<0b0000, "8",  v8i8>;
-def  VST1d16  : VST1D<0b0100, "16", v4i16>;
-def  VST1d32  : VST1D<0b1000, "32", v2i32>;
-def  VST1df   : VST1D<0b1000, "32", v2f32>;
-def  VST1d64  : VST1D<0b1100, "64", v1i64>;
-
-def  VST1q8   : VST1Q<0b0000, "8",  v16i8>;
-def  VST1q16  : VST1Q<0b0100, "16", v8i16>;
-def  VST1q32  : VST1Q<0b1000, "32", v4i32>;
-def  VST1qf   : VST1Q<0b1000, "32", v4f32>;
-def  VST1q64  : VST1Q<0b1100, "64", v2i64>;
-} // hasExtraSrcRegAllocReq
-
-let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
+          "vst1", Dt, "\\{$src\\}, $addr", "", []>;
+class VST1Q<bits<4> op7_4, string Dt>
+  : NLdSt<0,0b00,0b1010,op7_4, (outs),
+          (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
+          "vst1", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
+
+def  VST1d8   : VST1D<0b0000, "8">;
+def  VST1d16  : VST1D<0b0100, "16">;
+def  VST1d32  : VST1D<0b1000, "32">;
+def  VST1d64  : VST1D<0b1100, "64">;
+
+def  VST1q8   : VST1Q<0b0000, "8">;
+def  VST1q16  : VST1Q<0b0100, "16">;
+def  VST1q32  : VST1Q<0b1000, "32">;
+def  VST1q64  : VST1Q<0b1100, "64">;
 
 // ...with address register writeback:
 class VST1DWB<bits<4> op7_4, string Dt>
@@ -582,9 +592,6 @@
 def  VST2d8   : VST2D<0b1000, 0b0000, "8">;
 def  VST2d16  : VST2D<0b1000, 0b0100, "16">;
 def  VST2d32  : VST2D<0b1000, 0b1000, "32">;
-def  VST2d64  : NLdSt<0,0b00,0b1010,0b1100, (outs),
-                      (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
-                      "vst1", "64", "\\{$src1, $src2\\}, $addr", "", []>;
 
 def  VST2q8   : VST2Q<0b0000, "8">;
 def  VST2q16  : VST2Q<0b0100, "16">;
@@ -606,11 +613,6 @@
 def VST2d8_UPD  : VST2DWB<0b1000, 0b0000, "8">;
 def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
 def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
-def VST2d64_UPD : NLdSt<0,0b00,0b1010,0b1100, (outs GPR:$wb),
-                        (ins addrmode6:$addr, am6offset:$offset,
-                         DPR:$src1, DPR:$src2), IIC_VST,
-                        "vst1", "64", "\\{$src1, $src2\\}, $addr$offset",
-                        "$addr.addr = $wb", []>;
 
 def VST2q8_UPD  : VST2QWB<0b0000, "8">;
 def VST2q16_UPD : VST2QWB<0b0100, "16">;

Modified: llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp?rev=99265&r1=99264&r2=99265&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Tue Mar 23 01:20:33 2010
@@ -50,10 +50,6 @@
   case ARM::VLD1q16:
   case ARM::VLD1q32:
   case ARM::VLD1q64:
-    FirstOpnd = 0;
-    NumRegs = 2;
-    return true;
-
   case ARM::VLD2d8:
   case ARM::VLD2d16:
   case ARM::VLD2d32:
@@ -177,10 +173,13 @@
     Stride = 2;
     return true;
 
+  case ARM::VST1q8:
+  case ARM::VST1q16:
+  case ARM::VST1q32:
+  case ARM::VST1q64:
   case ARM::VST2d8:
   case ARM::VST2d16:
   case ARM::VST2d32:
-  case ARM::VST2d64:
   case ARM::VST2LNd8:
   case ARM::VST2LNd16:
   case ARM::VST2LNd32:




From bob.wilson at apple.com  Tue Mar 23 01:26:18 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 23 Mar 2010 06:26:18 -0000
Subject: [llvm-commits] [llvm] r99266 - in /llvm/trunk/lib/Target/ARM:
 ARMBaseInstrInfo.cpp ARMInstrNEON.td
Message-ID: <20100323062618.536BA2A6C12C@llvm.org>

Author: bwilson
Date: Tue Mar 23 01:26:18 2010
New Revision: 99266

URL: http://llvm.org/viewvc/llvm-project?rev=99266&view=rev
Log:
Rename some instructions to match the corresponding NEON opcode.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=99266&r1=99265&r2=99266&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Mar 23 01:26:18 2010
@@ -743,7 +743,7 @@
                      .addMemOperand(MMO)
                      .addReg(SrcReg, getKillRegState(isKill)));
     } else {
-      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRQ)).
+      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)).
                      addReg(SrcReg, getKillRegState(isKill))
                      .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
     }
@@ -792,7 +792,7 @@
                      .addFrameIndex(FI).addImm(128)
                      .addMemOperand(MMO));
     } else {
-      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg)
+      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
                      .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
     }
   }

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99266&r1=99265&r2=99266&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 01:26:18 2010
@@ -117,7 +117,7 @@
 
 // Use vldmia to load a Q register as a D register pair.
 // This is equivalent to VLDMD except that it has a Q register operand.
-def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoadm,
+def VLDMQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoadm,
                 "vldmia", "$addr, ${dst:dregpair}",
                 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
   let Inst{27-25} = 0b110;
@@ -129,7 +129,7 @@
 
 let mayLoad = 1 in {
 // Use vld1 to load a Q register as a D register pair.
-// This alternative to VLDRQ allows an alignment to be specified.
+// This alternative to VLDMQ allows an alignment to be specified.
 // This is equivalent to VLD1q64 except that it has a Q register operand.
 def VLD1q
   : NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst), (ins addrmode6:$addr),
@@ -142,7 +142,7 @@
 
 // Use vstmia to store a Q register as a D register pair.
 // This is equivalent to VSTMD except that it has a Q register operand.
-def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem,
+def VSTMQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem,
                 "vstmia", "$addr, ${src:dregpair}",
                 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
   let Inst{27-25} = 0b110;
@@ -154,7 +154,7 @@
 
 let mayStore = 1 in {
 // Use vst1 to store a Q register as a D register pair.
-// This alternative to VSTRQ allows an alignment to be specified.
+// This alternative to VSTMQ allows an alignment to be specified.
 // This is equivalent to VST1q64 except that it has a Q register operand.
 def VST1q
   : NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, QPR:$src),




From baldrick at free.fr  Tue Mar 23 03:42:36 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 23 Mar 2010 08:42:36 -0000
Subject: [llvm-commits] [dragonegg] r99270 -
	/dragonegg/trunk/llvm-backend.cpp
Message-ID: <20100323084236.27B252A6C12C@llvm.org>

Author: baldrick
Date: Tue Mar 23 03:42:35 2010
New Revision: 99270

URL: http://llvm.org/viewvc/llvm-project?rev=99270&view=rev
Log:
Port commit 99232 (lattner) from llvm-gcc:
"fix" PR6656: the passmanager needs to be destroyed before
the module is, in case immutable passes have asserting VH's
pointing into the IR.  Immutable passes apparently don't
get their doFinalization methods called, which seems like
a bug.

Modified:
    dragonegg/trunk/llvm-backend.cpp

Modified: dragonegg/trunk/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-backend.cpp?rev=99270&r1=99269&r2=99270&view=diff
==============================================================================
--- dragonegg/trunk/llvm-backend.cpp (original)
+++ dragonegg/trunk/llvm-backend.cpp Tue Mar 23 03:42:35 2010
@@ -1470,6 +1470,9 @@
     return;
 
 #ifndef NDEBUG
+  delete PerModulePasses;
+  delete PerFunctionPasses;
+  delete CodeGenPasses;
   delete TheModule;
   llvm_shutdown();
 #endif




From daniel at zuster.org  Tue Mar 23 04:59:23 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 23 Mar 2010 09:59:23 -0000
Subject: [llvm-commits] [zorg] r99272 - in /zorg/trunk/lnt/lnt/viewer:
 NTStyleBrowser.ptl nightlytest.ptl
Message-ID: <20100323095923.227BD2A6C12C@llvm.org>

Author: ddunbar
Date: Tue Mar 23 04:59:22 2010
New Revision: 99272

URL: http://llvm.org/viewvc/llvm-project?rev=99272&view=rev
Log:
LNT: Move the machine view to common code.

Modified:
    zorg/trunk/lnt/lnt/viewer/NTStyleBrowser.ptl
    zorg/trunk/lnt/lnt/viewer/nightlytest.ptl

Modified: zorg/trunk/lnt/lnt/viewer/NTStyleBrowser.ptl
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/NTStyleBrowser.ptl?rev=99272&r1=99271&r2=99272&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/NTStyleBrowser.ptl (original)
+++ zorg/trunk/lnt/lnt/viewer/NTStyleBrowser.ptl Tue Mar 23 04:59:22 2010
@@ -227,7 +227,14 @@
                 <td> <b>Nickname</b> </td>
                 <td> %s </td>
               </tr>
-        """ %  (machine.name,)
+              <tr>
+                <td> <b>Machine ID</b> </td>
+                <td> %d </td>
+              </tr>
+              </table>
+              <p>
+              <table border=1>
+        """ %  (machine.name, machine.id)
         for mi in machine.info.values():
             """
               <tr>
@@ -236,12 +243,20 @@
               </tr>
             """ % (mi.key, mi.value)
         """
+              </table>
+              <p>
+              <table border=1>
+        """
+        for ri in run.info.values():
+            """
               <tr>
-                <td> <b>Machine ID</b> </td>
-                <td> %d </td>
+                <td> <b>%s</b> </td>
+                <td>%s</td>
               </tr>
+            """ % (ri.key, ri.value)
+        """
               </table>
-        """ % (machine.id,)
+        """
 
         if allResults:
             """<h4><a href="?full=">See Brief Test Results</a></h4>"""
@@ -280,6 +295,127 @@
     def renderCommonContents(self, db, run, compareTo, summary):
         abstract
 
+class MachineUI(Directory):
+    _q_exports = [""]
+
+    def __init__(self, root, idstr):
+        self.root = root
+        try:
+            self.id = int(idstr)
+        except ValueError, exc:
+            raise TraversalError(str(exc))
+
+    def _q_index [html] (self):
+        # Get a DB connection.
+        db = self.root.getDB()
+
+        machine = db.getMachine(self.id)
+
+        self.root.getHeader("Machine: %s:%d" % (machine.name,machine.number),
+                            "../../..",
+                            components=(('nightlytest','nightlytest'),),
+                            addPopupJS=True)
+
+        # Find all runs on this machine.
+        runs = db.runs(machine).order_by(Run.start_time.desc()).all()
+
+        # FIXME: List previous machines with the same nickname?
+        """
+        <table width="100%%" border=1>
+          <tr>
+            <td valign="top" width="200">
+              <a href="../..">Homepage</a>
+              <h4>Relatives:</h4>
+              <ul>
+        """
+        # List all machines with this name.
+        for m in db.machines(name=machine.name):
+            """<li><a href="../%d">%s:%d</a></li>""" % (m.id, m.name, m.number)
+        """
+              </ul>
+              <h4>Runs:</h4>
+              <ul>
+        """
+
+        # Show the most recent 10 runs.
+        for r in runs[:10]:
+            """ <li> <a href="../../%d/">%s</a> """ % (r.id, r.start_time)
+
+        # Full list of runs in a drop down.
+        #
+        # FIXME: Link to run correctly.
+        """
+        <p>
+        <form method="GET" action="../../1/">
+        <select name="run">
+        """
+        for r in runs:
+            """\
+        <option value="%d">%s""" % (r.id, r.start_time)
+
+        """
+        </select>
+        <input type="submit" value="Go to Run">
+        </form>
+        """
+
+        """
+              </ul>
+            </td>
+            <td valign="top">
+              <table border=1>
+              <tr>
+                <td> <b>Nickname</b> </td>
+                <td> %s </td>
+              </tr>
+              <tr>
+                <td> <b>Machine ID</b> </td>
+                <td> %d </td>
+              </tr>
+              </table>
+              <p>
+              <table border=1>
+              <tr>
+        """ % (machine.name, machine.id)
+        for mi in machine.info.values():
+            """
+              <tr>
+                <td> <b>%s</b> </td>
+                <td>%s</td>
+              </tr>
+            """ % (mi.key, mi.value)
+
+        # List associated runs.
+        """
+        </table>
+        <p>
+        <table class="sortable" border=1>
+        <thead>
+          <tr>
+            <th>Start Time</th>
+            <th>End Time</th>
+            <th>&nbsp;</th>
+        </thead>
+        """
+        for r in runs:
+            """
+          <tr>
+            <td>%s</td>
+            <td>%s</td>
+            <td><a href="../../%d">View Results</a></td>
+          </tr>""" % (r.start_time, r.end_time, r.id)
+        """
+        </table>
+        """
+
+        """
+            </td>
+          </tr>
+        </table>
+        """
+
+        self.root.getFooter()
+
 class MachinesDirectory(Directory):
     _q_exports = [""]
 
@@ -293,7 +429,7 @@
         """
 
     def _q_lookup(self, component):
-        return self.parent.getTestMachineUI(component)
+        return MachineUI(self.parent.root, component)
 
 class ProgramsDirectory(Directory):
     _q_exports = [""]
@@ -349,6 +485,15 @@
             # Get the most recent run for this machine name.
             q = db.session.query(Run).join(Machine).filter(Machine.name == name)
             r = q.order_by(Run.start_time.desc()).first()
+
+            # Limit by matching tags.
+            if 'tag' in r.info:
+                tag = r.info['tag'].value
+            else:
+                tag = None
+            if tag not in self.getTags():
+                continue
+
             """
               <tr>
                 <td>%s</td>
@@ -378,6 +523,14 @@
 
         # Show the 20 most recent submissions, ordered by time.
         for r in db.session.query(Run).order_by(Run.start_time.desc())[:20]:
+            # Limit by matching tags.
+            if 'tag' in r.info:
+                tag = r.info['tag'].value
+            else:
+                tag = None
+            if tag not in self.getTags():
+                continue
+
             m = r.machine
             """
               <tr>

Modified: zorg/trunk/lnt/lnt/viewer/nightlytest.ptl
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/nightlytest.ptl?rev=99272&r1=99271&r2=99272&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/nightlytest.ptl (original)
+++ zorg/trunk/lnt/lnt/viewer/nightlytest.ptl Tue Mar 23 04:59:22 2010
@@ -26,9 +26,6 @@
         NTStyleBrowser.TestRunUI.__init__(self, *args, **kwargs)
         self.popupDepth = 0
 
-    def getTags(self):
-        return (None, 'nightlytest')
-
     def getParameters(self):
         return ()
 
@@ -503,125 +500,6 @@
 
         self.root.getFooter()
 
-class NightlyTestMachineUI(Directory):
-    _q_exports = [""]
-
-    def __init__(self, root, idstr):
-        self.root = root
-        try:
-            self.id = int(idstr)
-        except ValueError, exc:
-            raise TraversalError(str(exc))
-
-    def _q_index [html] (self):
-        # Get a DB connection.
-        db = self.root.getDB()
-
-        machine = db.getMachine(self.id)
-
-        self.root.getHeader("Machine: %s:%d" % (machine.name,machine.number),
-                            "../../..",
-                            components=(('nightlytest','nightlytest'),),
-                            addPopupJS=True)
-
-        # Find all runs on this machine.
-        runs = db.runs(machine).order_by(Run.start_time.desc()).all()
-
-        # FIXME: List previous machines with the same nickname?
-        """
-        <table width="100%%" border=1>
-          <tr>
-            <td valign="top" width="200">
-              <a href="../..">Homepage</a>
-              <h4>Relatives:</h4>
-              <ul>
-        """
-        # List all machines with this name.
-        for m in db.machines(name=machine.name):
-            """<li><a href="../%d">%s:%d</a></li>""" % (m.id, m.name, m.number)
-        """
-              </ul>
-              <h4>Runs:</h4>
-              <ul>
-        """
-
-        # Show the most recent 10 runs.
-        for r in runs[:10]:
-            """ <li> <a href="../../%d/">%s</a> """ % (r.id, r.start_time)
-
-        # Full list of runs in a drop down.
-        #
-        # FIXME: Link to run correctly.
-        """
-        <p>
-        <form method="GET" action="../../1/">
-        <select name="run">
-        """
-        for r in runs:
-            """\
-        <option value="%d">%s""" % (r.id, r.start_time)
-
-        """
-        </select>
-        <input type="submit" value="Go to Run">
-        </form>
-        """
-
-        """
-              </ul>
-            </td>
-            <td valign="top">
-              <table border=1>
-              <tr>
-                <td> <b>Nickname</b> </td>
-                <td> %s </td>
-              </tr>
-        """ %  (machine.name,)
-        for mi in machine.info.values():
-            """
-              <tr>
-                <td> <b>%s</b> </td>
-                <td>%s</td>
-              </tr>
-            """ % (mi.key, mi.value)
-        """
-              <tr>
-                <td> <b>Machine ID</b> </td>
-                <td> %d </td>
-              </tr>
-              </table>
-              <p>
-        """ % (machine.id,)
-
-        # List associated runs.
-        """
-        <table class="sortable" border=1>
-        <thead>
-          <tr>
-            <th>Start Time</th>
-            <th>End Time</th>
-            <th>&nbsp;</th>
-        </thead>
-        """
-        for r in runs:
-            """
-          <tr>
-            <td>%s</td>
-            <td>%s</td>
-            <td><a href="../../%d">View Results</a></td>
-          </tr>""" % (r.start_time, r.end_time, r.id)
-        """
-        </table>
-        """
-
-        """
-            </td>
-          </tr>
-        </table>
-        """
-
-        self.root.getFooter()
-
 class NightlyTestProgramUI(Directory):
     _q_exports = [""]
 
@@ -768,8 +646,5 @@
     def getTestRunUI(self, component):
         return NightlyTestRunUI(self.root, component)
 
-    def getTestMachineUI(self, component):
-        return NightlyTestMachineUI(self.root, component)
-
     def getProgramUI(self, component):
         return NightlyTestProgramUI(self.root, component)




From daniel at zuster.org  Tue Mar 23 04:59:26 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 23 Mar 2010 09:59:26 -0000
Subject: [llvm-commits] [zorg] r99273 - in /zorg/trunk/lnt/lnt/util:
	ImportData.py NTEmailReport.py
Message-ID: <20100323095926.581F92A6C12D@llvm.org>

Author: ddunbar
Date: Tue Mar 23 04:59:26 2010
New Revision: 99273

URL: http://llvm.org/viewvc/llvm-project?rev=99273&view=rev
Log:
LNT: Don't send emails on non nightlytest tagged runs.

Modified:
    zorg/trunk/lnt/lnt/util/ImportData.py
    zorg/trunk/lnt/lnt/util/NTEmailReport.py

Modified: zorg/trunk/lnt/lnt/util/ImportData.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/ImportData.py?rev=99273&r1=99272&r2=99273&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/util/ImportData.py (original)
+++ zorg/trunk/lnt/lnt/util/ImportData.py Tue Mar 23 04:59:26 2010
@@ -27,25 +27,32 @@
     except KeyboardInterrupt:
         raise
     except:
+        import traceback
         print >>log, 'ERROR: %r: load failed' % file
+        print >>log, traceback.format_exc()
         return (False, None)
     print >>log, '  LOAD TIME: %.2fs' % (time.time() - startTime,)
 
+    # Check if this is a nightlytest run.
+    tag = data.get('Run',{}).get('Info',{}).get('tag',None)
+    is_nt = tag is None or tag == 'nightlytest'
+
     # Find the email address for this machine's results.
     toAddress = None
-    if isinstance(config.ntEmailTo, str):
-        toAddress = config.ntEmailTo
-    else:
-        # Find the machine name.
-        machineName = str(data.get('Machine',{}).get('Name'))
-        for pattern,addr in config.ntEmailTo:
-            if re.match(pattern, machineName):
-                toAddress = addr
-                break
+    if is_nt and config.ntEmailEnabled:
+        if isinstance(config.ntEmailTo, str):
+            toAddress = config.ntEmailTo
         else:
-            print >>log,("ERROR: unable to match machine name "
-                         "for test results email address!")
-            return (False, None)
+            # Find the machine name.
+            machineName = str(data.get('Machine',{}).get('Name'))
+            for pattern,addr in config.ntEmailTo:
+                if re.match(pattern, machineName):
+                    toAddress = addr
+                    break
+            else:
+                print >>log,("ERROR: unable to match machine name "
+                             "for test results email address!")
+                return (False, None)
 
     importStartTime = time.time()
     try:
@@ -53,7 +60,9 @@
     except KeyboardInterrupt:
         raise
     except:
+        import traceback
         print >>log, 'ERROR: %r: import failed' % file
+        print >>log, traceback.format_exc()
         return (False, None)
 
     print >>log, '  IMPORT TIME: %.2fs' % (time.time() - importStartTime,)
@@ -65,7 +74,7 @@
         for ri in run.info.values():
             print >>log, "    INFO   : %r = %r" % (ri.key, ri.value)
 
-    if not disable_email and config.ntEmailEnabled:
+    if not disable_email and toAddress is not None:
         print >>log, "\nMAILING RESULTS TO: %r\n" % toAddress
         NTEmailReport.emailReport(db, run,
                                   "%s/db_%s/nightlytest/" % (config.zorgURL,

Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/NTEmailReport.py?rev=99273&r1=99272&r2=99273&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/util/NTEmailReport.py (original)
+++ zorg/trunk/lnt/lnt/util/NTEmailReport.py Tue Mar 23 04:59:26 2010
@@ -174,8 +174,9 @@
     if baseurl[-1] == '/':
         baseurl = baseurl[:-1]
     print >>report, """%s/%d/""" % (baseurl, run.id)
-    print >>report, """Name: %s""" % (machine.info['name'].value,)
     print >>report, """Nickname: %s:%d""" % (machine.name, machine.number)
+    if 'name' in machine.info:
+        print >>report, """Name: %s""" % (machine.info['name'].value,)
     print >>report
     print >>report, """Run: %d, Start Time: %s, End Time: %s""" % (
         run.id, run.start_time, run.end_time)




From daniel at zuster.org  Tue Mar 23 04:59:31 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 23 Mar 2010 09:59:31 -0000
Subject: [llvm-commits] [zorg] r99274 - in /zorg/trunk/lnt: examples/
 examples/functions.py lnt/lnttool/__init__.py lnt/testing/
 lnt/testing/__init__.py lnt/viewer/Config.py lnt/viewer/PerfDB.py
 lnt/viewer/root.ptl lnt/viewer/simple.ptl
Message-ID: <20100323095931.771E12A6C12C@llvm.org>

Author: ddunbar
Date: Tue Mar 23 04:59:31 2010
New Revision: 99274

URL: http://llvm.org/viewvc/llvm-project?rev=99274&view=rev
Log:
LNT: Add a new 'simple' UI, which is an NT like viewer for generic data, and works with the full range of the database features (in particular, multiple samples per test, and test parameters).

Added:
    zorg/trunk/lnt/examples/
    zorg/trunk/lnt/examples/functions.py
    zorg/trunk/lnt/lnt/testing/
    zorg/trunk/lnt/lnt/testing/__init__.py
    zorg/trunk/lnt/lnt/viewer/simple.ptl
Modified:
    zorg/trunk/lnt/lnt/lnttool/__init__.py
    zorg/trunk/lnt/lnt/viewer/Config.py
    zorg/trunk/lnt/lnt/viewer/PerfDB.py
    zorg/trunk/lnt/lnt/viewer/root.ptl

Added: zorg/trunk/lnt/examples/functions.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/examples/functions.py?rev=99274&view=auto
==============================================================================
--- zorg/trunk/lnt/examples/functions.py (added)
+++ zorg/trunk/lnt/examples/functions.py Tue Mar 23 04:59:31 2010
@@ -0,0 +1,36 @@
+#!/usr/bin/env python
+
+"""
+Simple example of a test generator which just produces data on some mathematical
+functions, keyed off of the current time.
+"""
+
+import time
+import math, random
+
+from lnt.testing import *
+
+def main():
+    offset = math.pi/5
+    delay = 120.
+
+    machine = Machine('Mr. Sin Wave', info = { 'delay' : delay })
+
+    start = time.time()
+
+    run = Run(start, start, info = { 't' : start,
+                                     'tag' : 'simple' })
+    tests = [TestSamples('simple.%s' % name,
+                         [fn(start*2*math.pi / delay  + j * offset)],
+                         info = { 'offset' : j })
+             for j in range(5)
+             for name,fn in (('sin',math.sin),
+                             ('cos',math.cos),
+                             ('random',lambda x: random.random()))]
+
+    report = Report(machine, run, tests)
+
+    print report.render()
+
+if __name__ == '__main__':
+    main()

Modified: zorg/trunk/lnt/lnt/lnttool/__init__.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/__init__.py?rev=99274&r1=99273&r2=99274&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/lnttool/__init__.py (original)
+++ zorg/trunk/lnt/lnt/lnttool/__init__.py Tue Mar 23 04:59:31 2010
@@ -3,6 +3,8 @@
 import os
 import sys
 
+import StringIO
+
 def action_runserver(name, args):
     """start a new development server."""
 
@@ -48,6 +50,32 @@
 from convert import action_convert
 from import_data import action_import
 
+def action_checkformat(name, args):
+    """check the format of an LNT test report file."""
+
+    from optparse import OptionParser, OptionGroup
+    parser = OptionParser("%%prog %s [options] files" % name)
+
+    (opts, args) = parser.parse_args(args)
+    if len(args) > 1:
+        parser.error("incorrect number of argments")
+
+    if len(args) == 0:
+        input = '-'
+    else:
+        input, = args
+
+    if input == '-':
+        input = StringIO.StringIO(sys.stdin.read())
+
+    from lnt import formats
+    from lnt.viewer import PerfDB
+
+    db = PerfDB.PerfDB('sqlite:///:memory:')
+
+    data = formats.read_any(input, '<auto>')
+    PerfDB.importDataFromDict(db, data)
+
 def action_submit(name, args):
     """submit a test report to the server."""
 
@@ -83,7 +111,7 @@
 
     if len(sys.argv) < 2 or sys.argv[1] not in commands:
         if len(sys.argv) >= 2:
-            print >>sys.sterr,"error: invalid command %r\n" % sys.argv[1]
+            print >>sys.stderr,"error: invalid command %r\n" % sys.argv[1]
 
         usage()
 

Added: zorg/trunk/lnt/lnt/testing/__init__.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/testing/__init__.py?rev=99274&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/testing/__init__.py (added)
+++ zorg/trunk/lnt/lnt/testing/__init__.py Tue Mar 23 04:59:31 2010
@@ -0,0 +1,72 @@
+"""
+Utilities for working with the LNT test format.
+"""
+
+import time
+import datetime
+import json
+
+def normalize_time(t):
+    if isinstance(t,float):
+        t = datetime.datetime.utcfromtimestamp(t)
+    elif not isinstance(t, datatime.datetime):
+        t = time.strptime(start_time, '%Y-%m-%d %H:%M:%S')
+    return t.strftime('%Y-%m-%d %H:%M:%S')
+
+class Machine:
+    def __init__(self, name, info={}):
+        self.name = str(name)
+        self.info = dict((str(key),str(value))
+                         for key,value in info.items())
+
+    def render(self):
+        return { 'Name' : self.name,
+                 'Info' : self.info }
+
+class Run:
+    def __init__(self, start_time, end_time, info={}):
+        if start_time is None:
+            start_time = datetime.datetime.now()
+        if end_time is None:
+            end_time = datetime.datetime.now()
+
+        self.start_time = normalize_time(start_time)
+        self.end_time = normalize_time(end_time)
+        self.info = dict((str(key),str(value))
+                         for key,value in info.items())
+
+    def render(self):
+        return { 'Start Time' : self.start_time,
+                 'End Time' : self.end_time,
+                 'Info' : self.info }
+
+class TestSamples:
+    def __init__(self, name, data, info={}):
+        self.name = str(name)
+        self.info = dict((str(key),str(value))
+                         for key,value in info.items())
+        self.data = map(float, data)
+
+    def render(self):
+        return { 'Name' : self.name,
+                 'Info' : self.info,
+                 'Data' : self.data }
+
+class Report:
+    def __init__(self, machine, run, tests):
+        self.machine = machine
+        self.run = run
+        self.tests = list(tests)
+
+        assert isinstance(self.machine, Machine)
+        assert isinstance(self.run, Run)
+        for t in self.tests:
+            assert isinstance(t, TestSamples)
+
+    def render(self):
+        return json.dumps({ 'Machine' : self.machine.render(),
+                            'Run' : self.run.render(),
+                            'Tests' : [t.render() for t in self.tests] },
+                          sort_keys=True, indent=4)
+
+__all__ = ['Machine', 'Run', 'TestSamples', 'Report']

Modified: zorg/trunk/lnt/lnt/viewer/Config.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/Config.py?rev=99274&r1=99273&r2=99274&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/Config.py (original)
+++ zorg/trunk/lnt/lnt/viewer/Config.py Tue Mar 23 04:59:31 2010
@@ -12,12 +12,14 @@
             dbPath = os.path.join(baseDir, dbPath)
         return DBInfo(dbPath,
                       bool(dict.get('showNightlytest')),
-                      bool(dict.get('showGeneral')))
+                      bool(dict.get('showGeneral')),
+                      bool(dict.get('showSimple')))
 
-    def __init__(self, path, showNightlytest, showGeneral):
+    def __init__(self, path, showNightlytest, showGeneral, showSimple):
         self.path = path
-        self.showNightlytest = showNightlytest
         self.showGeneral = showGeneral
+        self.showNightlytest = showNightlytest
+        self.showSimple = showSimple
 
 class Config:
     @staticmethod

Modified: zorg/trunk/lnt/lnt/viewer/PerfDB.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/PerfDB.py?rev=99274&r1=99273&r2=99274&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/PerfDB.py (original)
+++ zorg/trunk/lnt/lnt/viewer/PerfDB.py Tue Mar 23 04:59:31 2010
@@ -321,11 +321,12 @@
     test_info = {}
     for id,k,v in db.session.query(TestInfo.test_id, TestInfo.key,
                                    TestInfo.value):
-        test_info[id] = (str(k),str(v))
+        info = test_info[id] = test_info.get(id,{})
+        info[str(k)] = str(v)
 
     testMap = {}
     for test_id,test_name in db.session.query(Test.id, Test.name):
-        info = test_info.get(test_id,[])
+        info = test_info.get(test_id,{}).items()
         info.sort()
         testMap[(str(test_name),tuple(info))] = test_id
 
@@ -338,7 +339,7 @@
         info.sort()
         test_id = testMap.get((name,tuple(info)))
         if test_id is None:
-            test,created = db.getOrCreateTest(testData['Name'],testData['Info'])
+            test,created = db.getOrCreateTest(testData['Name'],info)
             assert created
             late_ids.append((i,test))
         test_ids.append(test_id)

Modified: zorg/trunk/lnt/lnt/viewer/root.ptl
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/root.ptl?rev=99274&r1=99273&r2=99274&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/root.ptl (original)
+++ zorg/trunk/lnt/lnt/viewer/root.ptl Tue Mar 23 04:59:31 2010
@@ -21,7 +21,7 @@
 
 class RootDirectory(Resolving, Directory):
     _q_exports = ["", "resources", "js", "machines", "runs", "tests",
-                  "browse", "submitRun", "nightlytest", "zview",
+                  "browse", "submitRun", "nightlytest", "simple", "zview",
 
                   # Redirections.
                   "select_db",
@@ -172,6 +172,11 @@
 
         # Available UIs.
 
+        if self.dbInfo.showSimple:
+            """
+            <a href="simple/">Simple Test Viewer</a>
+            """
+
         if self.dbInfo.showNightlytest:
             """
             <h3>Nightly Test Results</h3>
@@ -359,6 +364,9 @@
         if component == 'nightlytest':
             import nightlytest
             return nightlytest.NightlyTestDirectory(self)
+        if component == 'simple':
+            import simple
+            return simple.RootDirectory(self)
         if component == 'zview':
             from zview import zviewui
             return zviewui.ZViewUI(self)

Added: zorg/trunk/lnt/lnt/viewer/simple.ptl
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/simple.ptl?rev=99274&view=auto
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/simple.ptl (added)
+++ zorg/trunk/lnt/lnt/viewer/simple.ptl Tue Mar 23 04:59:31 2010
@@ -0,0 +1,471 @@
+# -*- python -*-
+
+"""
+Nightly Test UI instance for actual nightly test data.
+"""
+
+# FIXME: The NTStyleBrowser abstraction is no longer useful. We should kill it.
+
+import sys
+import time
+
+import quixote
+from quixote.directory import Directory
+from quixote.errors import TraversalError
+
+import Util, NTStyleBrowser
+from Util import safediv
+from NTUtil import *
+
+from PerfDB import Machine, Run, Test
+
+class SimpleRunUI(Directory):
+    _q_exports = ["", "graph"]
+
+    def __init__(self, root, idstr):
+        self.root = root
+        try:
+            self.id = int(idstr)
+        except ValueError, exc:
+            raise TraversalError(str(exc))
+
+    def getInfo(self, db):
+        request = quixote.get_request()
+
+        compareToID = request.form.get('compare', '')
+        compareTo = None
+        if compareToID:
+            try:
+                compareTo = db.getRun(int(compareToID))
+            except:
+                pass
+
+        run = db.getRun(self.id)
+
+        # Find previous runs, ordered by time.
+        runs = db.runs(run.machine).order_by(Run.start_time.desc()).all()
+        runs = [r for r in runs
+                if 'tag' in r.info and r.info['tag'].value == 'simple']
+
+        # Find previous run to compare to.
+        if compareTo is None:
+            for r in runs:
+                # FIXME: Compare revisions, not times.
+                if r != run and r.start_time < run.start_time:
+                    compareTo = r
+                    break
+
+        return run, runs, compareTo
+
+    def show_run_page [html] (self, db, run, runs, compareTo, contents_fn):
+        machine = run.machine
+
+        """
+        <center>
+          <table>
+            <tr>
+              <td align=right>Machine:</td>
+              <td>%s:%d</td>
+            </tr>
+            <tr>
+              <td align=right>Run:</td>
+              <td>%s</td>
+            </tr>
+        """ % (machine.name, machine.number, run.start_time)
+        if compareTo:
+            """
+            <tr>
+              <td align=right>Compare To:</td>
+              <td>%s</td>
+            </tr>
+            """ % (compareTo.start_time,)
+        """
+          </table>
+        </center>
+        <p>
+        """
+
+        """
+        <table width="100%%" border=1>
+          <tr>
+            <td valign="top" width="200">
+              <a href="..">Homepage</a>
+              <h4>Machine:</h4>
+              <a href="../machines/%d/">%s:%d</a>
+              <h4>Runs:</h4>
+              <ul>
+        """ % (machine.id, machine.name, machine.number)
+
+        # Show a small number of neighboring runs.
+        runIndex = runs.index(run)
+        for r in runs[max(0,runIndex-3):runIndex+6]:
+            if r == run:
+                """ <li> <h3><a href="../%d/">%s</a></h3> """ % (r.id,
+                                                                 r.start_time)
+            else:
+                """ <li> <a href="../%d/">%s</a> """ % (r.id, r.start_time)
+        """
+              </ul>
+            </td>
+            <td valign="top">
+              <table border=1>
+              <tr>
+                <td> <b>Nickname</b> </td>
+                <td> %s </td>
+              </tr>
+              <tr>
+                <td> <b>Machine ID</b> </td>
+                <td> %d </td>
+              </tr>
+              </table>
+              <p>
+              <table border=1>
+        """ %  (machine.name, machine.id)
+        for mi in machine.info.values():
+            """
+              <tr>
+                <td> <b>%s</b> </td>
+                <td>%s</td>
+              </tr>
+            """ % (mi.key, mi.value)
+        """
+              </table>
+              <p>
+              <table border=1>
+        """
+        for ri in run.info.values():
+            """
+              <tr>
+                <td> <b>%s</b> </td>
+                <td>%s</td>
+              </tr>
+            """ % (ri.key, ri.value)
+        """
+              </table>
+        """
+
+        contents_fn(db, run, runs, compareTo)
+
+        """
+            </td>
+          </tr>
+        </table>
+        """
+
+        self.root.getFooter()
+
+    def _q_index [html] (self):
+        # Get a DB connection.
+        db = self.root.getDB()
+
+        run,runs,compareTo = self.getInfo(db)
+        machine = run.machine
+
+        self.root.getHeader('Run Results', "../..",
+                            components=(('simple','simple'),
+                                        ('machine',
+                                         'simple/machines/%d' % machine.id)),
+                            addPopupJS=True, addFormCSS=True)
+
+        self.show_run_page(db, run, runs, compareTo, self._q_index_body)
+
+    def graph [html] (self):
+        request = quixote.get_request()
+
+        # Get a DB connection.
+        db = self.root.getDB()
+
+        run,runs,compareTo = self.getInfo(db)
+        machine = run.machine
+
+        # Load the metadata.
+
+        test_names,test_map,parameter_keys,parameter_sets = self.\
+            get_simple_metadata(db)
+
+        # Load the form data.
+        graph_tests = []
+        graph_psets = []
+        for name,value in request.form.items():
+            if name.startswith(str('test.')):
+                graph_tests.append(name[5:])
+            elif name.startswith(str('pset.')):
+                graph_psets.append(parameter_sets[int(name[5:])])
+
+        # Get the test ids we want data for.
+        test_ids = [test_map[(name,pset)].id
+                     for name in graph_tests
+                     for pset in graph_psets]
+
+        # Load all the samples for those tests and this machine.
+        q = db.session.query(Sample.run_id,Sample.test_id,
+                             Sample.value).join(Run)
+        q = q.filter(Run.machine_id == machine.id)
+        q = q.filter(Sample.test_id.in_(test_ids))
+        samples = list(q)
+
+        # Aggregate by test id and then run id.
+        #
+        # FIXME: Pretty expensive.
+        samples_by_test_id = {}
+        for run_id,test_id,value in samples:
+            d = samples_by_test_id.get(test_id)
+            if d is None:
+                d = samples_by_test_id[test_id] = Util.multidict()
+            d[run_id] = value
+
+        # Build the graph data
+        run_id_map = dict([(r.id,r) for r in runs])
+        pset_id_map = dict([(pset,i) for i,pset in enumerate(parameter_sets)])
+        legend = []
+        plots = ""
+        num_plots = len(graph_tests) * len(graph_psets)
+        num_points = 0
+        index = 0
+        for name in graph_tests:
+            for pset in graph_psets:
+                test_id = test_map[(name,pset)].id
+
+                # Get the plot for this test.
+                #
+                # FIXME: Support order by something other than time.
+                data = []
+                for run_id,values in samples_by_test_id.get(test_id,{}).items():
+                    r = run_id_map.get(run_id)
+                    if not r:
+                        continue
+                    timeval = time.mktime(r.start_time.timetuple())
+                    data.append((timeval, min(values)))
+                data.sort()
+                num_points += len(data)
+
+                col = list(Util.makeDarkColor(float(index) / num_plots))
+                pts = ','.join(['[%f,%f]' % (t,v) for t,v in data])
+                style = "new Graph2D_LinePlotStyle(1, %r)" % col
+                plots += "    graph.addPlot([%s], %s);\n" % (pts,style)
+
+                legend.append(("%s : P%d" % (name, pset_id_map[pset]), col))
+                index += 1
+
+        def graph_body [html] (db, run, runs, compare_to):
+            """
+            <h3>Graph</h3>
+            <table>
+            <tr>
+            <td rowspan=2 valign="top">
+              <canvas id="graph" width="600" height="400"></canvas>
+            </td>
+            <td valign="top">
+            <table cellspacing=4 border=1>
+            <tr><th colspan=2>Test</th></tr>
+            """
+            for name,col in legend:
+                """
+                <tr><td bgcolor="%02x%02x%02x">&nbsp;</td>
+                <td>%s</td></tr>""" % (255*col[0], 255*col[1], 255*col[2], name)
+            """
+            </table>
+            </td></tr>
+            <tr><td align="right" valign="bottom">
+            <font size="-2">
+            Shift-Left Mouse: Pan<br>
+            Alt/Meta-Left Mouse: Zoom<br>
+            Wheel: Zoom (<i>Shift Slows</i>)<br>
+            </font>
+            </td></tr>
+            </table>
+            <p>
+            <b>Plots</b>: %d<br>
+            <b>Num Points<b>: %d<br>
+            """ % (num_plots, num_points)
+
+        graph_init = """\
+    function init() {
+        graph = new Graph2D("graph");
+        graph.clearColor = [1, 1, 1];
+    %s
+        graph.xAxis.format = graph.xAxis.formats.day;
+        graph.draw();
+    }
+    """ % (plots,)
+        self.root.getHeader('Run Results', "..",
+                            components=(('simple','simple'),
+                                        ('machine',
+                                         'simple/machines/%d' % machine.id),
+                                        ('run', 'simple/%d' % run.id)),
+                            addPopupJS=True, addGraphJS=True,
+                            addJSScript=graph_init,
+                            onload="init()")
+
+        self.show_run_page(db, run, runs, compareTo, graph_body)
+
+    def get_simple_metadata(self, db):
+        """Compute the metadata about tests, parameter sets, etc."""
+
+        # FIXME: We can cache this in a number of ways.
+
+        # Find all test names.
+        q = db.session.query(Test)
+        q = q.filter(Test.name.startswith(str('simple.')))
+        tests = list(q)
+
+        # Collect all the test data.
+        test_names = set()
+        parameter_sets = set()
+        test_map = {}
+        for t in tests:
+            name = t.name.split(str('.'),1)[1]
+            test_names.add(name)
+            
+            items = [(k,v.value) for k,v in t.info.items()]
+            items.sort()
+            key = tuple(items)
+
+            parameter_sets.add(key)
+            test_map[(name, key)] = t
+
+        # Order the test names.
+        test_names = list(test_names)
+        test_names.sort()
+
+        # Collect the set of all parameter keys.
+        parameter_keys = list(set([k for pset in parameter_sets
+                                   for k,v in pset]))
+        parameter_keys.sort()
+
+        # Order the parameter sets and convert to dictionaries.
+        parameter_sets = list(parameter_sets)
+        parameter_sets.sort()
+
+        return test_names,test_map,parameter_keys,parameter_sets
+
+    def _q_index_body [html] (self, db, run, runs, compare_to):
+        # Find the tests. The simple UI maps all tests that start with
+        # 'simple.'.
+        #
+        # One sensible addition would be to allow 'simple.foo.success' as a test
+        # to indicate the success or failure of the test. We would assume that
+        # the test succeeded if its .success test was missing, which leads to a
+        # nice compact format (failures are expected to be rare).
+
+        if compare_to:
+            prev_id = compare_to.id
+            interesting_runs = (run.id, prev_id)
+        else:
+            prev_id = None
+            interesting_runs = (run.id,)
+
+        # Load the metadata.
+
+        test_names,test_map,parameter_keys,parameter_sets = self.\
+            get_simple_metadata(db)
+
+        # Load the run sample data.
+
+        q = db.session.query(Sample.value, Sample.run_id, Sample.test_id)
+        q = q.filter(Sample.run_id.in_(interesting_runs))
+
+        sample_map = Util.multidict()
+        for value,run_id,test_id in q:
+            key = (run_id,test_id)
+            sample_map[key] = value
+
+        # Render the page.
+
+        def get_cell_value [html] (test, name, pset):
+            run_values = sample_map.get((run.id,test.id))
+            prev_values = sample_map.get((prev_id,test.id))
+
+            # FIXME: Check success
+            failed = not run_values
+                
+            run_cell_value = "-"
+            if run_values:
+                run_cell_value = "%.2f" % min(run_values)
+            
+            if failed:
+                """
+                <td bgcolor="#FF0000">%s</td""" % run_cell_value
+            else:
+                """
+                <td>%s</td""" % run_cell_value
+
+            if prev_values and run_values:
+                prev_value = min(prev_values)
+                pct = safediv(min(run_values), prev_value,
+                              '<center><font size=-2>nan</font></center>')
+                Util.PctCell(pct, delta=True).render()
+            else:
+                """<td>-</td>"""
+                
+
+        """
+        <h3>Parameter Sets</h3>
+        <table border=1>
+          <tr>
+            <th rowspan=2>Name</th>
+            <th colspan=%d>Parameters</th>
+          </tr><tr>""" % len(parameter_sets)
+        for key in parameter_keys:
+            """
+            <th>%s</th>""" % key
+        """
+          </tr>"""
+        for (i,pset) in enumerate(parameter_sets):
+            """
+          <tr>
+            <td>P%s</td>""" % (i,)
+            pmap = dict(pset)
+            for key in parameter_keys:
+                item = pmap.get(key)
+                if item is None:
+                    item = "-"
+                """
+            <td>%s</td>""" % item
+            """
+          </tr>"""
+        """
+        </table>"""
+
+        """
+        <h3>Tests</h3>"""
+
+        """
+        <form method="GET" action="graph">
+        <table border=1>
+          <tr>
+            <th></th><th>Name</th>"""
+        for i in range(len(parameter_sets)):
+            """
+            <th><input type="checkbox" name="pset.%d">P%d</th>
+            <th>%%</th>""" % (i, i)
+        """
+          </tr>"""
+        for name in test_names:
+            """
+          <tr>
+            <td><input type="checkbox" name="test.%s"></td>
+            <td>%s</td>""" % (name, name)
+            for pset in parameter_sets:
+                test = test_map.get((name,pset))
+                if test is None:
+                    """
+                <td></td><td></td>"""
+                    continue
+
+                get_cell_value(test, name, pset)
+            """
+          </tr>"""
+        """
+        </table>
+        <input type="submit" value="Graph">
+        </form>"""
+
+class RootDirectory(NTStyleBrowser.RecentMachineDirectory):
+    _q_exports = [""]
+
+    def getTags(self):
+        return ('simple',)
+
+    def getTestRunUI(self, component):
+        return SimpleRunUI(self.root, component)




From ggreif at gmail.com  Tue Mar 23 08:45:54 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 23 Mar 2010 13:45:54 -0000
Subject: [llvm-commits] [llvm] r99275 -
	/llvm/trunk/lib/VMCore/Instructions.cpp
Message-ID: <20100323134554.AB7E12A6C12C@llvm.org>

Author: ggreif
Date: Tue Mar 23 08:45:54 2010
New Revision: 99275

URL: http://llvm.org/viewvc/llvm-project?rev=99275&view=rev
Log:
word-o

Modified:
    llvm/trunk/lib/VMCore/Instructions.cpp

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=99275&r1=99274&r2=99275&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Tue Mar 23 08:45:54 2010
@@ -621,7 +621,7 @@
 
   assert(((NumArgs == FTy->getNumParams()) ||
           (FTy->isVarArg() && NumArgs > FTy->getNumParams())) &&
-         "Calling a function with bad signature");
+         "Invoking a function with bad signature");
 
   for (unsigned i = 0, e = NumArgs; i != e; i++) {
     assert((i >= FTy->getNumParams() || 




From ggreif at gmail.com  Tue Mar 23 09:40:20 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 23 Mar 2010 14:40:20 -0000
Subject: [llvm-commits] [llvm] r99276 - in /llvm/trunk/lib:
 Transforms/IPO/ArgumentPromotion.cpp VMCore/Function.cpp
Message-ID: <20100323144020.A92DF2A6C12C@llvm.org>

Author: ggreif
Date: Tue Mar 23 09:40:20 2010
New Revision: 99276

URL: http://llvm.org/viewvc/llvm-project?rev=99276&view=rev
Log:
add assert in argpromotion, which cannot trigger
if Function::hasAddressTaken works as advertised

also included some cosmetic cleanups

Modified:
    llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp
    llvm/trunk/lib/VMCore/Function.cpp

Modified: llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp?rev=99276&r1=99275&r2=99276&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp Tue Mar 23 09:40:20 2010
@@ -623,6 +623,7 @@
   SmallVector<Value*, 16> Args;
   while (!F->use_empty()) {
     CallSite CS = CallSite::get(F->use_back());
+    assert(CS.getCalledFunction() == F);
     Instruction *Call = CS.getInstruction();
     const AttrListPtr &CallPAL = CS.getAttributes();
 
@@ -660,7 +661,7 @@
         // Non-dead argument: insert GEPs and loads as appropriate.
         ScalarizeTable &ArgIndices = ScalarizedElements[I];
         // Store the Value* version of the indices in here, but declare it now
-        // for reuse
+        // for reuse.
         std::vector<Value*> Ops;
         for (ScalarizeTable::iterator SI = ArgIndices.begin(),
                E = ArgIndices.end(); SI != E; ++SI) {
@@ -677,10 +678,10 @@
                     Type::getInt32Ty(F->getContext()) : 
                     Type::getInt64Ty(F->getContext()));
               Ops.push_back(ConstantInt::get(IdxTy, *II));
-              // Keep track of the type we're currently indexing
+              // Keep track of the type we're currently indexing.
               ElTy = cast<CompositeType>(ElTy)->getTypeAtIndex(*II);
             }
-            // And create a GEP to extract those indices
+            // And create a GEP to extract those indices.
             V = GetElementPtrInst::Create(V, Ops.begin(), Ops.end(),
                                           V->getName()+".idx", Call);
             Ops.clear();
@@ -694,7 +695,7 @@
     if (ExtraArgHack)
       Args.push_back(Constant::getNullValue(Type::getInt32Ty(F->getContext())));
 
-    // Push any varargs arguments on the list
+    // Push any varargs arguments on the list.
     for (; AI != CS.arg_end(); ++AI, ++ArgIndex) {
       Args.push_back(*AI);
       if (Attributes Attrs = CallPAL.getParamAttributes(ArgIndex))

Modified: llvm/trunk/lib/VMCore/Function.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=99276&r1=99275&r2=99276&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Function.cpp (original)
+++ llvm/trunk/lib/VMCore/Function.cpp Tue Mar 23 09:40:20 2010
@@ -400,8 +400,8 @@
 #include "llvm/Intrinsics.gen"
 #undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN
 
-  /// hasAddressTaken - returns true if there are any uses of this function
-  /// other than direct calls or invokes to it.
+/// hasAddressTaken - returns true if there are any uses of this function
+/// other than direct calls or invokes to it.
 bool Function::hasAddressTaken() const {
   for (Value::use_const_iterator I = use_begin(), E = use_end(); I != E; ++I) {
     if (I.getOperandNo() != 0 ||




From evan.cheng at apple.com  Tue Mar 23 10:48:04 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 23 Mar 2010 15:48:04 -0000
Subject: [llvm-commits] [llvm] r99282 - in /llvm/trunk:
 lib/Transforms/Scalar/SimplifyLibCalls.cpp
 lib/Transforms/Utils/BuildLibCalls.cpp
 test/Transforms/SimplifyLibCalls/StrCpy.ll
Message-ID: <20100323154804.931872A6C12C@llvm.org>

Author: evancheng
Date: Tue Mar 23 10:48:04 2010
New Revision: 99282

URL: http://llvm.org/viewvc/llvm-project?rev=99282&view=rev
Log:
Teach simplify libcall to transform __strcpy_chk to __memcpy_chk to enable optimizations down stream.

Modified:
    llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
    llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp
    llvm/trunk/test/Transforms/SimplifyLibCalls/StrCpy.ll

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=99282&r1=99281&r2=99282&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Tue Mar 23 10:48:04 2010
@@ -49,10 +49,13 @@
   Function *Caller;
   const TargetData *TD;
   LLVMContext* Context;
+  bool OptChkCall;  // True if it's optimizing a *_chk libcall.
 public:
-  LibCallOptimization() { }
+  LibCallOptimization() : OptChkCall(false) { }
   virtual ~LibCallOptimization() {}
 
+  void setOptChkCall(bool c) { OptChkCall = c; }
+
   /// CallOptimizer - This pure virtual method is implemented by base classes to
   /// do various optimizations.  If this returns null then no transformation was
   /// performed.  If it returns CI, then it transformed the call and CI is to be
@@ -352,8 +355,10 @@
 struct StrCpyOpt : public LibCallOptimization {
   virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
     // Verify the "strcpy" function prototype.
+    unsigned NumParams = OptChkCall ? 3 : 2;
     const FunctionType *FT = Callee->getFunctionType();
-    if (FT->getNumParams() != 2 || FT->getReturnType() != FT->getParamType(0) ||
+    if (FT->getNumParams() != NumParams ||
+        FT->getReturnType() != FT->getParamType(0) ||
         FT->getParamType(0) != FT->getParamType(1) ||
         FT->getParamType(0) != Type::getInt8PtrTy(*Context))
       return 0;
@@ -371,8 +376,13 @@
 
     // We have enough information to now generate the memcpy call to do the
     // concatenation for us.  Make a memcpy to copy the nul byte with align = 1.
-    EmitMemCpy(Dst, Src,
-               ConstantInt::get(TD->getIntPtrType(*Context), Len), 1, B, TD);
+    if (OptChkCall)
+      EmitMemCpyChk(Dst, Src,
+                    ConstantInt::get(TD->getIntPtrType(*Context), Len),
+                    CI->getOperand(3), B, TD);
+    else
+      EmitMemCpy(Dst, Src,
+                 ConstantInt::get(TD->getIntPtrType(*Context), Len), 1, B, TD);
     return Dst;
   }
 };
@@ -1162,7 +1172,8 @@
     StringMap<LibCallOptimization*> Optimizations;
     // String and Memory LibCall Optimizations
     StrCatOpt StrCat; StrNCatOpt StrNCat; StrChrOpt StrChr; StrCmpOpt StrCmp;
-    StrNCmpOpt StrNCmp; StrCpyOpt StrCpy; StrNCpyOpt StrNCpy; StrLenOpt StrLen;
+    StrNCmpOpt StrNCmp; StrCpyOpt StrCpy; StrCpyOpt StrCpyChk;
+    StrNCpyOpt StrNCpy; StrLenOpt StrLen;
     StrToOpt StrTo; StrStrOpt StrStr;
     MemCmpOpt MemCmp; MemCpyOpt MemCpy; MemMoveOpt MemMove; MemSetOpt MemSet;
     // Math Library Optimizations
@@ -1228,6 +1239,10 @@
   Optimizations["memmove"] = &MemMove;
   Optimizations["memset"] = &MemSet;
 
+  // _chk variants of String and Memory LibCall Optimizations.
+  StrCpyChk.setOptChkCall(true);
+  Optimizations["__strcpy_chk"] = &StrCpyChk;
+
   // Math Library Optimizations
   Optimizations["powf"] = &Pow;
   Optimizations["pow"] = &Pow;

Modified: llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp?rev=99282&r1=99281&r2=99282&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp Tue Mar 23 10:48:04 2010
@@ -108,7 +108,7 @@
 
 
 /// EmitMemCpy - Emit a call to the memcpy function to the builder.  This always
-/// expects that the size has type 'intptr_t' and Dst/Src are pointers.
+/// expects that Len has type 'intptr_t' and Dst/Src are pointers.
 Value *llvm::EmitMemCpy(Value *Dst, Value *Src, Value *Len,
                         unsigned Align, IRBuilder<> &B, const TargetData *TD) {
   Module *M = B.GetInsertBlock()->getParent()->getParent();
@@ -120,6 +120,30 @@
                        ConstantInt::get(B.getInt32Ty(), Align));
 }
 
+/// EmitMemCpyChk - Emit a call to the __memcpy_chk function to the builder.
+/// This expects that the Len and ObjSize have type 'intptr_t' and Dst/Src
+/// are pointers.
+Value *llvm::EmitMemCpyChk(Value *Dst, Value *Src, Value *Len, Value *ObjSize,
+                           IRBuilder<> &B, const TargetData *TD) {
+  Module *M = B.GetInsertBlock()->getParent()->getParent();
+  AttributeWithIndex AWI;
+  AWI = AttributeWithIndex::get(~0u, Attribute::NoUnwind);
+  LLVMContext &Context = B.GetInsertBlock()->getContext();
+  Value *MemCpy = M->getOrInsertFunction("__memcpy_chk",
+                                         AttrListPtr::get(&AWI, 1),
+                                         B.getInt8PtrTy(),
+                                         B.getInt8PtrTy(),
+                                         B.getInt8PtrTy(),
+                                         TD->getIntPtrType(Context),
+                                         TD->getIntPtrType(Context), NULL);
+  Dst = CastToCStr(Dst, B);
+  Src = CastToCStr(Src, B);
+  CallInst *CI = B.CreateCall4(MemCpy, Dst, Src, Len, ObjSize);
+  if (const Function *F = dyn_cast<Function>(MemCpy->stripPointerCasts()))
+    CI->setCallingConv(F->getCallingConv());
+  return CI;
+}
+
 /// EmitMemMove - Emit a call to the memmove function to the builder.  This
 /// always expects that the size has type 'intptr_t' and Dst/Src are pointers.
 Value *llvm::EmitMemMove(Value *Dst, Value *Src, Value *Len,

Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/StrCpy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/StrCpy.ll?rev=99282&r1=99281&r2=99282&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyLibCalls/StrCpy.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyLibCalls/StrCpy.ll Tue Mar 23 10:48:04 2010
@@ -1,30 +1,37 @@
 ; Test that the StrCpyOptimizer works correctly
-; RUN: opt < %s -simplify-libcalls -S | \
-; RUN:   not grep {call.*strcpy}
+; RUN: opt < %s -simplify-libcalls -S | FileCheck %s
 
 ; This transformation requires the pointer size, as it assumes that size_t is
 ; the size of a pointer.
-target datalayout = "-p:64:64:64"
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
 
- at hello = constant [6 x i8] c"hello\00"		; <[6 x i8]*> [#uses=1]
- at null = constant [1 x i8] zeroinitializer		; <[1 x i8]*> [#uses=1]
- at null_hello = constant [7 x i8] c"\00hello\00"		; <[7 x i8]*> [#uses=1]
+ at hello = constant [6 x i8] c"hello\00"
 
 declare i8* @strcpy(i8*, i8*)
 
-declare i32 @puts(i8*)
+declare i8* @__strcpy_chk(i8*, i8*, i32) nounwind
 
-define i32 @main() {
-	%target = alloca [1024 x i8]		; <[1024 x i8]*> [#uses=1]
-	%arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0		; <i8*> [#uses=2]
-	store i8 0, i8* %arg1
-	%arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0		; <i8*> [#uses=1]
-	%rslt1 = call i8* @strcpy( i8* %arg1, i8* %arg2 )		; <i8*> [#uses=1]
-	%arg3 = getelementptr [1 x i8]* @null, i32 0, i32 0		; <i8*> [#uses=1]
-	%rslt2 = call i8* @strcpy( i8* %rslt1, i8* %arg3 )		; <i8*> [#uses=1]
-	%arg4 = getelementptr [7 x i8]* @null_hello, i32 0, i32 0		; <i8*> [#uses=1]
-	%rslt3 = call i8* @strcpy( i8* %rslt2, i8* %arg4 )		; <i8*> [#uses=1]
-	call i32 @puts( i8* %rslt3 )		; <i32>:1 [#uses=0]
-	ret i32 0
+declare i32 @llvm.objectsize.i32(i8*, i1) nounwind readonly
+
+; rdar://6839935
+
+define i32 @t1() {
+; CHECK: @t1
+  %target = alloca [1024 x i8]
+  %arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0
+  %arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %rslt1 = call i8* @strcpy( i8* %arg1, i8* %arg2 )
+; CHECK: @llvm.memcpy.i32
+  ret i32 0
 }
 
+define i32 @t2() {
+; CHECK: @t2
+  %target = alloca [1024 x i8]
+  %arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0
+  %arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0
+  %tmp1 = call i32 @llvm.objectsize.i32(i8* %arg1, i1 false)
+  %rslt1 = call i8* @__strcpy_chk(i8* %arg1, i8* %arg2, i32 %tmp1)
+; CHECK: @__memcpy_chk
+  ret i32 0
+}




From evan.cheng at apple.com  Tue Mar 23 10:49:37 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 23 Mar 2010 15:49:37 -0000
Subject: [llvm-commits] [llvm] r99283 -
	/llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h
Message-ID: <20100323154937.DF0A92A6C12C@llvm.org>

Author: evancheng
Date: Tue Mar 23 10:49:37 2010
New Revision: 99283

URL: http://llvm.org/viewvc/llvm-project?rev=99283&view=rev
Log:
Forgot this.

Modified:
    llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h

Modified: llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h?rev=99283&r1=99282&r2=99283&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h (original)
+++ llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h Tue Mar 23 10:49:37 2010
@@ -49,6 +49,9 @@
   Value *EmitMemCpy(Value *Dst, Value *Src, Value *Len,
                     unsigned Align, IRBuilder<> &B, const TargetData *TD);
 
+  Value *EmitMemCpyChk(Value *Dst, Value *Src, Value *Len, Value *ObjSize,
+                       IRBuilder<> &B, const TargetData *TD);
+
   /// EmitMemMove - Emit a call to the memmove function to the builder.  This
   /// always expects that the size has type 'intptr_t' and Dst/Src are pointers.
   Value *EmitMemMove(Value *Dst, Value *Src, Value *Len,




From evan.cheng at apple.com  Tue Mar 23 10:50:49 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 23 Mar 2010 15:50:49 -0000
Subject: [llvm-commits] [llvm] r99284 -
	/llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h
Message-ID: <20100323155049.5EDC02A6C12C@llvm.org>

Author: evancheng
Date: Tue Mar 23 10:50:49 2010
New Revision: 99284

URL: http://llvm.org/viewvc/llvm-project?rev=99284&view=rev
Log:
Add comment.

Modified:
    llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h

Modified: llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h?rev=99284&r1=99283&r2=99284&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h (original)
+++ llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h Tue Mar 23 10:50:49 2010
@@ -49,6 +49,9 @@
   Value *EmitMemCpy(Value *Dst, Value *Src, Value *Len,
                     unsigned Align, IRBuilder<> &B, const TargetData *TD);
 
+  /// EmitMemCpyChk - Emit a call to the __memcpy_chk function to the builder.
+  /// This expects that the Len and ObjSize have type 'intptr_t' and Dst/Src
+  /// are pointers.
   Value *EmitMemCpyChk(Value *Dst, Value *Src, Value *Len, Value *ObjSize,
                        IRBuilder<> &B, const TargetData *TD);
 




From tonic at nondot.org  Tue Mar 23 11:34:46 2010
From: tonic at nondot.org (Tanya Lattner)
Date: Tue, 23 Mar 2010 16:34:46 -0000
Subject: [llvm-commits] [www] r99286 - /www/trunk/index.html
Message-ID: <20100323163446.370BD2A6C12C@llvm.org>

Author: tbrethou
Date: Tue Mar 23 11:34:46 2010
New Revision: 99286

URL: http://llvm.org/viewvc/llvm-project?rev=99286&view=rev
Log:
Update release schedule.

Modified:
    www/trunk/index.html

Modified: www/trunk/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=99286&r1=99285&r2=99286&view=diff
==============================================================================
--- www/trunk/index.html (original)
+++ www/trunk/index.html Tue Mar 23 11:34:46 2010
@@ -107,10 +107,12 @@
 
 <li>Mar   7 - Code Freeze (9PM PST) </li>
 <li>Mar  13 - Pre-release1 testing begins</li>
-<li>Mar  20 - Pre-release1 testing ends</li>
-<li>Mar  27 - Pre-release2 testing begins</li>
-<li>Apr   3  - Pre-release2 testing ends</li>
-<li>Apr   5  - Release!</li>
+<li>Mar  24 - Pre-release1 testing ends</li>
+<li>Mar  24 - Regression fixing week.</li>
+<li>Mar  31 - Regression fixing week ends.</li>
+<li>Apr   4 - Pre-release2 testing begins</li>
+<li>Apr  11 - Pre-release2 testing ends</li>
+<li>Apr  12 - Release!</li>
 </div>
 
 <br>




From johnny.chen at apple.com  Tue Mar 23 11:43:47 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 23 Mar 2010 16:43:47 -0000
Subject: [llvm-commits] [llvm] r99288 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20100323164347.7D3D52A6C12C@llvm.org>

Author: johnny
Date: Tue Mar 23 11:43:47 2010
New Revision: 99288

URL: http://llvm.org/viewvc/llvm-project?rev=99288&view=rev
Log:
Add New NEON Format NVdImmFrm.
Ref: A7.4.6 One register and a modified immediate value.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99288&r1=99287&r2=99288&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 11:43:47 2010
@@ -60,6 +60,7 @@
 def ThumbMiscFrm  : Format<30>;
 
 def NLdStFrm      : Format<31>;
+def NVdImmFrm     : Format<32>;
 
 // Misc flags.
 
@@ -1514,10 +1515,10 @@
   let Inst{7-4} = op7_4;
 }
 
-class NDataI<dag oops, dag iops, InstrItinClass itin,
+class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
              string opc, string dt, string asm, string cstr, list<dag> pattern>
-  : NeonI<oops, iops, AddrModeNone, IndexModeNone, NEONFrm, itin, opc, dt, asm,
-         cstr, pattern> {
+  : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
+          pattern> {
   let Inst{31-25} = 0b1111001;
 }
 
@@ -1533,7 +1534,7 @@
                bit op5, bit op4,
                dag oops, dag iops, InstrItinClass itin,
                string opc, string dt, string asm, string cstr, list<dag> pattern>
-  : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
+  : NDataI<oops, iops, NVdImmFrm, itin, opc, dt, asm, cstr, pattern> {
   let Inst{23} = op23;
   let Inst{21-19} = op21_19;
   let Inst{11-8} = op11_8;
@@ -1548,7 +1549,7 @@
           bits<5> op11_7, bit op6, bit op4,
           dag oops, dag iops, InstrItinClass itin,
           string opc, string dt, string asm, string cstr, list<dag> pattern>
-  : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
+  : NDataI<oops, iops, NEONFrm, itin, opc, dt, asm, cstr, pattern> {
   let Inst{24-23} = op24_23;
   let Inst{21-20} = op21_20;
   let Inst{19-18} = op19_18;
@@ -1577,7 +1578,7 @@
 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
              dag oops, dag iops, InstrItinClass itin,
              string opc, string dt, string asm, string cstr, list<dag> pattern>
-  : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
+  : NDataI<oops, iops, NEONFrm, itin, opc, dt, asm, cstr, pattern> {
   let Inst{24} = op24;
   let Inst{23} = op23;
   let Inst{11-8} = op11_8;
@@ -1590,7 +1591,7 @@
 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
           dag oops, dag iops, InstrItinClass itin,
           string opc, string dt, string asm, string cstr, list<dag> pattern>
-  : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
+  : NDataI<oops, iops, NEONFrm, itin, opc, dt, asm, cstr, pattern> {
   let Inst{24} = op24;
   let Inst{23} = op23;
   let Inst{21-20} = op21_20;




From bob.wilson at apple.com  Tue Mar 23 12:23:59 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 23 Mar 2010 17:23:59 -0000
Subject: [llvm-commits] [llvm] r99295 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20100323172359.93C012A6C12C@llvm.org>

Author: bwilson
Date: Tue Mar 23 12:23:59 2010
New Revision: 99295

URL: http://llvm.org/viewvc/llvm-project?rev=99295&view=rev
Log:
Fix bad indentation, 80-column violations, and trailing whitespace.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99295&r1=99294&r2=99295&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 12:23:59 2010
@@ -1,10 +1,10 @@
 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
@@ -178,13 +178,13 @@
   // TSFlagsFields
   AddrMode AM = am;
   bits<4> AddrModeBits = AM.Value;
-  
+
   SizeFlagVal SZ = sz;
   bits<3> SizeFlag = SZ.Value;
 
   IndexMode IM = im;
   bits<2> IndexModeBits = IM.Value;
-  
+
   Format F = f;
   bits<6> Form = F.Value;
 
@@ -196,7 +196,7 @@
   //
   bit isUnaryDataProc = 0;
   bit canXformTo16Bit = 0;
-  
+
   let Constraints = cstr;
   let Itinerary = itin;
 }
@@ -215,9 +215,9 @@
                 Format f, Domain d, string cstr, InstrItinClass itin>
   : InstTemplate<am, sz, im, f, d, cstr, itin>;
 
-class PseudoInst<dag oops, dag iops, InstrItinClass itin, 
+class PseudoInst<dag oops, dag iops, InstrItinClass itin,
                  string asm, list<dag> pattern>
-  : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 
+  : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
             "", itin> {
   let OutOperandList = oops;
   let InOperandList = iops;
@@ -227,7 +227,7 @@
 
 // Almost all ARM instructions are predicable.
 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
-        IndexMode im, Format f, InstrItinClass itin, 
+        IndexMode im, Format f, InstrItinClass itin,
         string opc, string asm, string cstr,
         list<dag> pattern>
   : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
@@ -239,9 +239,9 @@
 }
 // A few are not predicable
 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
-        IndexMode im, Format f, InstrItinClass itin, 
-        string opc, string asm, string cstr,
-        list<dag> pattern>
+           IndexMode im, Format f, InstrItinClass itin,
+           string opc, string asm, string cstr,
+           list<dag> pattern>
   : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
   let OutOperandList = oops;
   let InOperandList = iops;
@@ -291,9 +291,9 @@
   : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
        asm, "", pattern>;
 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
-         string opc, string asm, list<dag> pattern>
+            string opc, string asm, list<dag> pattern>
   : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
-      opc, asm, "", pattern>;
+         opc, asm, "", pattern>;
 
 // Ctrl flow instructions
 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
@@ -363,7 +363,7 @@
   let Inst{24-21} = opcod;
   let Inst{27-26} = {0,0};
 }
-class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin, 
+class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
             string opc, string asm, list<dag> pattern>
   : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
       opc, asm, "", pattern>;
@@ -388,7 +388,7 @@
   let Inst{24}    = 1; // P bit
   let Inst{27-26} = {0,1};
 }
-class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 
+class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
               string asm, list<dag> pattern>
   : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
        asm, "", pattern> {
@@ -408,7 +408,7 @@
   let Inst{24}    = 1; // P bit
   let Inst{27-26} = {0,1};
 }
-class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 
+class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
               string asm, list<dag> pattern>
   : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
        asm, "", pattern> {
@@ -550,7 +550,7 @@
 }
 
 // addrmode3 instructions
-class AI3<dag oops, dag iops, Format f, InstrItinClass itin, 
+class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
           string opc, string asm, list<dag> pattern>
   : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
       opc, asm, "", pattern>;
@@ -854,7 +854,6 @@
   let Inst{27-25} = 0b000;
 }
 
-
 // addrmode4 instructions
 class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
              string asm, string cstr, list<dag> pattern>
@@ -962,20 +961,25 @@
   : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
 
 // Two-address instructions
-class TIt<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
-  : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", pattern>;
+class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
+          list<dag> pattern>
+  : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
+           pattern>;
 
 // tBL, tBX 32-bit instructions
 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
-    dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
-    : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, Encoding {
+           dag oops, dag iops, InstrItinClass itin, string asm,
+           list<dag> pattern>
+    : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
+      Encoding {
   let Inst{31-27} = opcod1;
   let Inst{15-14} = opcod2;
   let Inst{12} = opcod3;
 }
 
 // BR_JT instructions
-class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
+class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
+           list<dag> pattern>
   : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
 
 // Thumb1 only
@@ -1002,7 +1006,7 @@
 // Two-address instructions
 class T1It<dag oops, dag iops, InstrItinClass itin,
            string asm, string cstr, list<dag> pattern>
-  : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 
+  : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
             asm, cstr, pattern>;
 
 // Thumb1 instruction that can either be predicated or set CPSR.
@@ -1025,7 +1029,7 @@
 class T1sIt<dag oops, dag iops, InstrItinClass itin,
             string opc, string asm, list<dag> pattern>
   : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
-            "$lhs = $dst", pattern>;
+             "$lhs = $dst", pattern>;
 
 // Thumb1 instruction that can be predicated.
 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
@@ -1047,7 +1051,7 @@
 class T1pIt<dag oops, dag iops, InstrItinClass itin,
             string opc, string asm, list<dag> pattern>
   : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
-            "$lhs = $dst", pattern>;
+             "$lhs = $dst", pattern>;
 
 class T1pI1<dag oops, dag iops, InstrItinClass itin,
             string opc, string asm, list<dag> pattern>
@@ -1058,7 +1062,7 @@
 class T1pI4<dag oops, dag iops, InstrItinClass itin,
             string opc, string asm, list<dag> pattern>
   : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
-class T1pIs<dag oops, dag iops, 
+class T1pIs<dag oops, dag iops,
             InstrItinClass itin, string opc, string asm, list<dag> pattern>
   : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
 
@@ -1147,8 +1151,8 @@
 }
 
 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
-               InstrItinClass itin,
-               string asm, string cstr, list<dag> pattern>
+              InstrItinClass itin,
+              string asm, string cstr, list<dag> pattern>
   : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
   let OutOperandList = oops;
   let InOperandList = iops;
@@ -1162,7 +1166,7 @@
   : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
              string opc, string asm, list<dag> pattern>
-  : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "", pattern>;
+  : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
             string opc, string asm, list<dag> pattern>
   : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
@@ -1197,7 +1201,7 @@
   : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
 
 class T2Ix2<dag oops, dag iops, InstrItinClass itin,
-          string opc, string asm, list<dag> pattern>
+            string opc, string asm, list<dag> pattern>
   : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
 
 // Two-address instructions
@@ -1296,7 +1300,7 @@
            InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
-      VFPLdStFrm, itin, opc, asm, "", pattern> {
+         VFPLdStFrm, itin, opc, asm, "", pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
   let Inst{27-24} = opcod1;
   let Inst{21-20} = opcod2;
@@ -1310,7 +1314,7 @@
            InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
-      VFPLdStFrm, itin, opc, asm, "", pattern> {
+         VFPLdStFrm, itin, opc, asm, "", pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
   let Inst{27-24} = opcod1;
   let Inst{21-20} = opcod2;
@@ -1321,7 +1325,7 @@
 class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
             string asm, string cstr, list<dag> pattern>
   : VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
-       VFPLdStMulFrm, itin, asm, cstr, pattern> {
+          VFPLdStMulFrm, itin, asm, cstr, pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
   let Inst{27-25} = 0b110;
   let Inst{11-8}  = 0b1011;
@@ -1333,7 +1337,7 @@
 class AXSI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
             string asm, string cstr, list<dag> pattern>
   : VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
-       VFPLdStMulFrm, itin, asm, cstr, pattern> {
+          VFPLdStMulFrm, itin, asm, cstr, pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
   let Inst{27-25} = 0b110;
   let Inst{11-8}  = 0b1010;
@@ -1354,7 +1358,8 @@
 
 // Double precision, binary
 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
-       dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
+           dag iops, InstrItinClass itin, string opc, string asm,
+           list<dag> pattern>
   : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
   let Inst{27-23} = opcod1;
   let Inst{21-20} = opcod2;
@@ -1400,7 +1405,8 @@
 // Single precision binary, if no NEON
 // Same as ASbI except not available if NEON is enabled
 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
-       dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
+            dag iops, InstrItinClass itin, string opc, string asm,
+            list<dag> pattern>
   : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
   list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
 }
@@ -1420,8 +1426,8 @@
 
 // VFP conversion between floating-point and fixed-point
 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
-               dag oops, dag iops, InstrItinClass itin, string opc, string asm,
-               list<dag> pattern>
+                dag oops, dag iops, InstrItinClass itin, string opc, string asm,
+                list<dag> pattern>
   : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
   // size (fixed-point number): sx == 0 ? 16 : 32
   let Inst{7} = op5; // sx
@@ -1449,7 +1455,7 @@
                InstrItinClass itin, string opc, string asm, list<dag> pattern>
   : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
 
-class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 
+class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
                InstrItinClass itin, string opc, string asm, list<dag> pattern>
   : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
 
@@ -1482,7 +1488,7 @@
 
 // Same as NeonI except it does not have a "data type" specifier.
 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
-            string opc, string asm, string cstr, list<dag> pattern>
+             string opc, string asm, string cstr, list<dag> pattern>
   : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
   let OutOperandList = oops;
   let InOperandList = !con(iops, (ins pred:$p));
@@ -1494,7 +1500,7 @@
 class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm,
          list<dag> pattern>
   : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "",
-          pattern> {
+           pattern> {
 }
 
 class NI4<dag oops, dag iops, InstrItinClass itin, string opc,
@@ -1523,9 +1529,9 @@
 }
 
 class NDataXI<dag oops, dag iops, InstrItinClass itin,
-             string opc, string asm, string cstr, list<dag> pattern>
+              string opc, string asm, string cstr, list<dag> pattern>
   : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm,
-         cstr, pattern> {
+           cstr, pattern> {
   let Inst{31-25} = 0b1111001;
 }
 
@@ -1533,7 +1539,8 @@
 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
                bit op5, bit op4,
                dag oops, dag iops, InstrItinClass itin,
-               string opc, string dt, string asm, string cstr, list<dag> pattern>
+               string opc, string dt, string asm, string cstr,
+               list<dag> pattern>
   : NDataI<oops, iops, NVdImmFrm, itin, opc, dt, asm, cstr, pattern> {
   let Inst{23} = op23;
   let Inst{21-19} = op21_19;
@@ -1561,9 +1568,9 @@
 
 // Same as N2V except it doesn't have a datatype suffix.
 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
-          bits<5> op11_7, bit op6, bit op4,
-          dag oops, dag iops, InstrItinClass itin,
-          string opc, string asm, string cstr, list<dag> pattern>
+           bits<5> op11_7, bit op6, bit op4,
+           dag oops, dag iops, InstrItinClass itin,
+           string opc, string asm, string cstr, list<dag> pattern>
   : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
   let Inst{24-23} = op24_23;
   let Inst{21-20} = op21_20;
@@ -1601,9 +1608,10 @@
 }
 
 // Same as N3VX except it doesn't have a data type suffix.
-class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
-          dag oops, dag iops, InstrItinClass itin,
-          string opc, string asm, string cstr, list<dag> pattern>
+class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
+           bit op4,
+           dag oops, dag iops, InstrItinClass itin,
+           string opc, string asm, string cstr, list<dag> pattern>
   : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
   let Inst{24} = op24;
   let Inst{23} = op23;
@@ -1618,7 +1626,7 @@
                dag oops, dag iops, Format f, InstrItinClass itin,
                string opc, string dt, string asm, list<dag> pattern>
   : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain,
-    "", itin> {
+            "", itin> {
   let Inst{27-20} = opcod1;
   let Inst{11-8} = opcod2;
   let Inst{6-5} = opcod3;




From criswell at uiuc.edu  Tue Mar 23 12:49:57 2010
From: criswell at uiuc.edu (John Criswell)
Date: Tue, 23 Mar 2010 17:49:57 -0000
Subject: [llvm-commits] [poolalloc] r99297 -
	/poolalloc/trunk/include/poolalloc/PoolAllocate.h
Message-ID: <20100323174957.D01452A6C12C@llvm.org>

Author: criswell
Date: Tue Mar 23 12:49:57 2010
New Revision: 99297

URL: http://llvm.org/viewvc/llvm-project?rev=99297&view=rev
Log:
Modified the PoolAllocateGroup class to inherit from ModulePass, eliminating
multiple inheritance in the PoolAllocate pass.  This seems to fix a bizarre
error where calling the getGlobalsGraph() method invoked the releaseMemory()
method.

Modified:
    poolalloc/trunk/include/poolalloc/PoolAllocate.h

Modified: poolalloc/trunk/include/poolalloc/PoolAllocate.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/poolalloc/PoolAllocate.h?rev=99297&r1=99296&r2=99297&view=diff
==============================================================================
--- poolalloc/trunk/include/poolalloc/PoolAllocate.h (original)
+++ poolalloc/trunk/include/poolalloc/PoolAllocate.h Tue Mar 23 12:49:57 2010
@@ -107,7 +107,7 @@
 } // end PA namespace
 
 
-class PoolAllocateGroup {
+class PoolAllocateGroup : public ModulePass {
 protected:
   DataStructures *Graphs;
   const Type * VoidType;
@@ -125,7 +125,10 @@
   enum PASS_TYPE {PASS_EQTD, PASS_BUEQ, PASS_DEFAULT};
   PASS_TYPE dsa_pass_to_use;
 
+                
+  PoolAllocateGroup  (intptr_t IDp = (intptr_t) (&ID)) : ModulePass (IDp) { }
   virtual ~PoolAllocateGroup () {return;}
+
   virtual PA::FuncInfo *getFuncInfo(const Function &F) { return 0;}
   virtual PA::FuncInfo *getFuncInfoOrClone(const Function &F) {return 0;}
   virtual Function *getOrigFunctionFromClone(const Function *F) const {return 0;}
@@ -152,7 +155,7 @@
 
 /// PoolAllocate - The main pool allocation pass
 ///
-class PoolAllocate : public ModulePass , public PoolAllocateGroup {
+class PoolAllocate : public PoolAllocateGroup {
   /// PassAllArguments - If set to true, we should pass pool descriptor
   /// arguments into any function that loads or stores to a pool, in addition to
   /// those functions that allocate or deallocate.  See also the
@@ -188,7 +191,7 @@
   PoolAllocate (bool passAllArguments,
                 bool SAFECode = true,
                 intptr_t IDp = (intptr_t) (&ID))
-    : ModulePass((intptr_t)IDp),
+    : PoolAllocateGroup ((intptr_t)IDp),
       PassAllArguments(passAllArguments)
       {
 		  SAFECodeEnabled = BoundsChecksEnabled = SAFECode |  PA::PA_SAFECODE;
@@ -202,7 +205,7 @@
 				bool passAllArguments = false,
 				bool SAFECode = true,
                 intptr_t IDp = (intptr_t) (&ID))
-      : ModulePass((intptr_t)IDp),
+      : PoolAllocateGroup ((intptr_t)IDp),
         PassAllArguments(passAllArguments)
         {
   		  SAFECodeEnabled = BoundsChecksEnabled = SAFECode |  PA::PA_SAFECODE;




From stuart at apple.com  Tue Mar 23 13:37:18 2010
From: stuart at apple.com (Stuart Hastings)
Date: Tue, 23 Mar 2010 18:37:18 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r99305 - in /llvm-gcc-4.2/trunk/gcc:
 cp/cp-objcp-common.c cp/cp-objcp-common.h cp/cp-tree.h langhooks-def.h
 langhooks.c langhooks.h llvm-convert.cpp
Message-ID: <20100323183718.C43E42A6C12C@llvm.org>

Author: stuart
Date: Tue Mar 23 13:37:18 2010
New Revision: 99305

URL: http://llvm.org/viewvc/llvm-project?rev=99305&view=rev
Log:
Elide stores of empty structures for correct support of boost::compressed_pair.  Radar 7659636.

Modified:
    llvm-gcc-4.2/trunk/gcc/cp/cp-objcp-common.c
    llvm-gcc-4.2/trunk/gcc/cp/cp-objcp-common.h
    llvm-gcc-4.2/trunk/gcc/cp/cp-tree.h
    llvm-gcc-4.2/trunk/gcc/langhooks-def.h
    llvm-gcc-4.2/trunk/gcc/langhooks.c
    llvm-gcc-4.2/trunk/gcc/langhooks.h
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/cp/cp-objcp-common.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/cp/cp-objcp-common.c?rev=99305&r1=99304&r2=99305&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/cp/cp-objcp-common.c (original)
+++ llvm-gcc-4.2/trunk/gcc/cp/cp-objcp-common.c Tue Mar 23 13:37:18 2010
@@ -111,6 +111,30 @@
     return lhd_expr_size (exp);
 }
 
+/* LLVM LOCAL begin 7659636 */
+/* lang_hooks.empty_type_p: Return true if the given type has size
+   zero.  */
+
+int
+cp_empty_type_p (tree exp)
+{
+  gcc_assert(TYPE_P(exp));
+  if (VOID_TYPE_P(exp))
+    return 0;
+
+  /* C++ classes with non-trivial constructors or non-trivial
+     assignment operators are assumed non-empty, thus assignments of
+     these types can't be elided.  */
+  if (CLASS_TYPE_P(exp)
+      && (TYPE_HAS_COMPLEX_INIT_REF(exp)
+          || TYPE_HAS_COMPLEX_ASSIGN_REF(exp)))
+    return 0;
+
+  return is_empty_class(exp);
+}
+
+/* LLVM LOCAL end 7659636 */
+
 /* Langhook for tree_size: determine size of our 'x' and 'c' nodes.  */
 size_t
 cp_tree_size (enum tree_code code)

Modified: llvm-gcc-4.2/trunk/gcc/cp/cp-objcp-common.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/cp/cp-objcp-common.h?rev=99305&r1=99304&r2=99305&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/cp/cp-objcp-common.h (original)
+++ llvm-gcc-4.2/trunk/gcc/cp/cp-objcp-common.h Tue Mar 23 13:37:18 2010
@@ -33,6 +33,10 @@
 
 #undef LANG_HOOKS_TREE_SIZE
 #define LANG_HOOKS_TREE_SIZE cp_tree_size
+/* LLVM LOCAL begin 7659636 */
+#undef LANG_HOOKS_EMPTY_TYPE_P
+#define LANG_HOOKS_EMPTY_TYPE_P cp_empty_type_p
+/* LLVM LOCAL end 7659636 */
 #undef LANG_HOOKS_FINISH
 #define LANG_HOOKS_FINISH cxx_finish
 #undef LANG_HOOKS_CLEAR_BINDING_STACK

Modified: llvm-gcc-4.2/trunk/gcc/cp/cp-tree.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/cp/cp-tree.h?rev=99305&r1=99304&r2=99305&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/cp/cp-tree.h (original)
+++ llvm-gcc-4.2/trunk/gcc/cp/cp-tree.h Tue Mar 23 13:37:18 2010
@@ -4639,6 +4639,8 @@
 extern bool cxx_warn_unused_global_decl		(tree);
 extern tree cp_expr_size			(tree);
 extern size_t cp_tree_size			(enum tree_code);
+/* LLVM LOCAL 7659636 */
+extern int cp_empty_type_p                      (tree);
 extern bool cp_var_mod_type_p			(tree, tree);
 extern void cxx_initialize_diagnostics		(struct diagnostic_context *);
 extern int cxx_types_compatible_p		(tree, tree);

Modified: llvm-gcc-4.2/trunk/gcc/langhooks-def.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/langhooks-def.h?rev=99305&r1=99304&r2=99305&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/langhooks-def.h (original)
+++ llvm-gcc-4.2/trunk/gcc/langhooks-def.h Tue Mar 23 13:37:18 2010
@@ -70,6 +70,8 @@
 extern bool lhd_decl_ok_for_sibcall (tree);
 extern const char *lhd_comdat_group (tree);
 extern tree lhd_expr_size (tree);
+/* LLVM LOCAL 7659636 */
+extern int lhd_empty_type_p (tree);
 extern size_t lhd_tree_size (enum tree_code);
 extern HOST_WIDE_INT lhd_to_target_charset (HOST_WIDE_INT);
 extern tree lhd_expr_to_decl (tree, bool *, bool *, bool *);
@@ -139,6 +141,8 @@
 #define LANG_HOOKS_DWARF_NAME		lhd_dwarf_name
 #define LANG_HOOKS_GET_CALLEE_FNDECL	lhd_return_null_tree
 #define LANG_HOOKS_EXPR_SIZE		lhd_expr_size
+/* LLVM LOCAL 7659636 */
+#define LANG_HOOKS_EMPTY_TYPE_P		lhd_empty_type_p
 #define LANG_HOOKS_TREE_SIZE		lhd_tree_size
 #define LANG_HOOKS_TYPES_COMPATIBLE_P	lhd_types_compatible_p
 #define LANG_HOOKS_BUILTIN_FUNCTION	builtin_function
@@ -336,6 +340,8 @@
   LANG_HOOKS_GET_CALLEE_FNDECL, \
   LANG_HOOKS_PRINT_ERROR_FUNCTION, \
   LANG_HOOKS_EXPR_SIZE, \
+/* LLVM LOCAL 7659636 */ \
+  LANG_HOOKS_EMPTY_TYPE_P, \
   LANG_HOOKS_TO_TARGET_CHARSET, \
   LANG_HOOKS_ATTRIBUTE_TABLE, \
   LANG_HOOKS_COMMON_ATTRIBUTE_TABLE, \

Modified: llvm-gcc-4.2/trunk/gcc/langhooks.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/langhooks.c?rev=99305&r1=99304&r2=99305&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/langhooks.c (original)
+++ llvm-gcc-4.2/trunk/gcc/langhooks.c Tue Mar 23 13:37:18 2010
@@ -439,6 +439,21 @@
     return size_in_bytes (TREE_TYPE (exp));
 }
 
+/* LLVM LOCAL begin 7659636 */
+/* lang_hooks.empty_type_p: Return true if the given type has size
+   zero.  */
+
+int
+lhd_empty_type_p (tree exp)
+{
+  gcc_assert(TYPE_P(exp));
+  if (VOID_TYPE_P(exp))
+    return 0;
+  return size_in_bytes(exp) == 0;
+}
+
+/* LLVM LOCAL end 7659636 */
+
 /* lang_hooks.gimplify_expr re-writes *EXPR_P into GIMPLE form.  */
 
 int

Modified: llvm-gcc-4.2/trunk/gcc/langhooks.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/langhooks.h?rev=99305&r1=99304&r2=99305&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/langhooks.h (original)
+++ llvm-gcc-4.2/trunk/gcc/langhooks.h Tue Mar 23 13:37:18 2010
@@ -410,6 +410,11 @@
      semantics in cases that it doesn't want to handle specially.  */
   tree (*expr_size) (tree);
 
+/* LLVM LOCAL begin 7659636 */
+  /* Return true (non-zero) if the given RECORD_TYPE has size zero.  */
+  int (*empty_type_p) (tree);
+/* LLVM LOCAL end 7659636 */
+
   /* Convert a character from the host's to the target's character
      set.  The character should be in what C calls the "basic source
      character set" (roughly, the set of characters defined by plain

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=99305&r1=99304&r2=99305&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Mar 23 13:37:18 2010
@@ -3046,6 +3046,20 @@
   tree lhs = TREE_OPERAND (exp, 0);
   tree rhs = TREE_OPERAND (exp, 1);
 
+  // Avoid generating stores of empty types.  This is rare, but necessary
+  // to support the compressed_pair template.
+  if (lang_hooks.empty_type_p(TREE_TYPE(exp))) {
+    if (TREE_SIDE_EFFECTS(rhs)) {
+      // There's a side-effect; alloc a temporary to receive the
+      // value, if any.  Do not store into lhs; we must not
+      // reference it.
+      const Type *RHSTy = ConvertType(TREE_TYPE(rhs));
+      MemRef dest = CreateTempLoc(RHSTy);
+      return Emit(rhs, &dest);
+    } else
+      return (Value *)0;
+  }
+
   // If this is the definition of a gimple temporary, set its DECL_LLVM to the
   // RHS.
   bool LHSSigned = !TYPE_UNSIGNED(TREE_TYPE(lhs));




From stuart at apple.com  Tue Mar 23 13:39:23 2010
From: stuart at apple.com (Stuart Hastings)
Date: Tue, 23 Mar 2010 18:39:23 -0000
Subject: [llvm-commits] [llvm] r99306 -
	/llvm/trunk/test/FrontendC++/2010-03-22-empty-baseclass.cpp
Message-ID: <20100323183923.B50982A6C12C@llvm.org>

Author: stuart
Date: Tue Mar 23 13:39:23 2010
New Revision: 99306

URL: http://llvm.org/viewvc/llvm-project?rev=99306&view=rev
Log:
Test case for llvm-gcc r99305.  Radar 7659636.

Added:
    llvm/trunk/test/FrontendC++/2010-03-22-empty-baseclass.cpp

Added: llvm/trunk/test/FrontendC++/2010-03-22-empty-baseclass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-03-22-empty-baseclass.cpp?rev=99306&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC++/2010-03-22-empty-baseclass.cpp (added)
+++ llvm/trunk/test/FrontendC++/2010-03-22-empty-baseclass.cpp Tue Mar 23 13:39:23 2010
@@ -0,0 +1,134 @@
+// RUN: %llvmgxx -S -emit-llvm %s -o - -O2 | FileCheck %s
+namespace boost {
+  namespace detail {
+    template <typename T> struct cv_traits_imp {};
+    template <typename T> struct cv_traits_imp<T*> {typedef T unqualified_type;};
+  }
+}
+namespace mpl_ {}
+namespace boost {
+  namespace mpl {using namespace mpl_;}
+  template< typename T > struct remove_cv {typedef typename boost::detail::cv_traits_imp<T*>::unqualified_type type;};
+  namespace type_traits {
+    typedef char yes_type;
+    struct no_type {char padding[8];};
+  }
+}
+namespace mpl_ {
+  template< bool C_ > struct bool_;
+  typedef bool_<true> true_;
+  typedef bool_<false> false_;
+  template< bool C_ > struct bool_ {static const bool value = C_;};
+  template< typename T, T N > struct integral_c;
+}
+namespace boost{
+  template <class T, T val>   struct integral_constant :
+    public mpl::integral_c<T, val> {};
+  template<> struct integral_constant<bool,true> : public mpl::true_ {};
+  template<> struct integral_constant<bool,false> : public mpl::false_ {};
+  namespace type_traits {
+    template <bool b1, bool b2, bool b3 = false, bool b4 = false,
+              bool b5 = false, bool b6 = false, bool b7 = false> struct ice_or;
+    template <bool b1, bool b2, bool b3, bool b4, bool b5, bool b6, bool b7>
+    struct ice_or {static const bool value = true; };
+    template <> struct ice_or<false, false, false, false, false, false, false>
+    {static const bool value = false;};
+    template <bool b1, bool b2, bool b3 = true, bool b4 = true, bool b5 = true,
+              bool b6 = true, bool b7 = true> struct ice_and;
+    template <bool b1, bool b2, bool b3, bool b4, bool b5, bool b6, bool b7>
+    struct ice_and {static const bool value = false;};
+    template <> struct ice_and<true, true, true, true, true, true, true>
+    {static const bool value = true;};
+    template <bool b> struct ice_not {static const bool value = true;};
+  };
+  namespace detail {
+    template <typename T> struct is_union_impl {static const bool value = false;};
+  }
+  template< typename T > struct is_union :
+  ::boost::integral_constant<bool, ::boost::detail::is_union_impl<T>::value> {};
+  namespace detail {
+    template <class U> ::boost::type_traits::yes_type is_class_tester(void(U::*)(void));
+    template <class U> ::boost::type_traits::no_type is_class_tester(...);
+    template <typename T> struct is_class_impl {
+      static const bool value = (::boost::type_traits::ice_and< sizeof(is_class_tester<T>(0))
+                                 == sizeof(::boost::type_traits::yes_type),
+                                 ::boost::type_traits::ice_not< ::boost::is_union<T>::value >::value >::value);};
+}
+  template<typename T> struct is_class:
+  ::boost::integral_constant<bool,::boost::detail::is_class_impl<T>::value> {  };
+namespace detail {
+  template <typename T> struct empty_helper_t1: public T {int i[256];};
+  struct empty_helper_t2 {int i[256];};
+  template <typename T, bool is_a_class = false> struct empty_helper
+  {static const bool value = false;};
+  template <typename T> struct empty_helper<T, true>
+  {static const bool value = (sizeof(empty_helper_t1<T>) == sizeof(empty_helper_t2));};
+  template <typename T> struct is_empty_impl {
+    typedef typename remove_cv<T>::type cvt;
+    static const bool value = (::boost::type_traits::ice_or< ::boost::detail::empty_helper
+                               <cvt,::boost::is_class<T>::value>::value, false>::value);
+  };
+}
+template<typename T> struct is_empty:
+::boost::integral_constant<bool,::boost::detail::is_empty_impl<T>::value> {};
+template<typename T, typename U > struct is_same:
+::boost::integral_constant<bool,false> {};
+template<typename T> struct call_traits {typedef T& reference;};
+namespace details {
+  template <class T1, class T2, bool IsSame, bool FirstEmpty, bool SecondEmpty>
+  struct compressed_pair_switch;
+  template <class T1, class T2>
+  struct compressed_pair_switch<T1, T2, false, true, false>
+  {static const int value = 1;};
+  template <class T1, class T2, int Version> class compressed_pair_imp;
+  template <class T1, class T2> class compressed_pair_imp<T1, T2, 1>:
+  protected ::boost::remove_cv<T1>::type {
+  public:
+    typedef T1 first_type;
+    typedef T2 second_type;
+    typedef typename call_traits<first_type>::reference first_reference;
+    typedef typename call_traits<second_type>::reference second_reference;
+    first_reference first() {return *this;}
+    second_reference second() {return second_;}
+    second_type second_;
+  };
+}
+template <class T1, class T2> class compressed_pair:
+  private ::boost::details::compressed_pair_imp<T1, T2, ::boost::details::compressed_pair_switch<
+                                                          T1, T2, ::boost::is_same<typename remove_cv<T1>::type,
+                                                                                   typename remove_cv<T2>::type>::value,
+                                                          ::boost::is_empty<T1>::value, ::boost::is_empty<T2>::value>::value>
+  {
+  private:
+    typedef details::compressed_pair_imp<T1, T2, ::boost::details::compressed_pair_switch<
+                                                   T1, T2, ::boost::is_same<typename remove_cv<T1>::type,
+                                                                            typename remove_cv<T2>::type>::value,
+                                                                              ::boost::is_empty<T1>::value, ::boost::is_empty<T2>::value>::value> base;
+  public:
+    typedef T1 first_type;
+    typedef T2 second_type;
+    typedef typename call_traits<first_type>::reference first_reference;
+    typedef typename call_traits<second_type>::reference second_reference;
+    first_reference first() {return base::first();}
+    second_reference second() {return base::second();}
+  };
+}
+struct empty_base_t {};
+struct empty_t : empty_base_t {};
+typedef boost::compressed_pair<empty_t, int> data_t;
+extern "C" {int printf(const char * , ...);}
+extern "C" {void abort(void);}
+int main (int argc, char * const argv[]) {
+  data_t x;
+  x.second() = -3;
+  // This store should be elided:
+  x.first() = empty_t();
+  // If x.second() has been clobbered by the elided store, fail.
+  if (x.second() != -3) {
+    printf("x.second() was clobbered\n");
+    // CHECK-NOT: x.second() was clobbered
+    abort();
+  }
+  return 0;
+}
+// CHECK: ret i32




From isanbard at gmail.com  Tue Mar 23 13:48:56 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 23 Mar 2010 18:48:56 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r99308 -
	/llvm-gcc-4.2/trunk/gcc/stub-c.c
Message-ID: <20100323184856.B60192A6C12C@llvm.org>

Author: void
Date: Tue Mar 23 13:48:56 2010
New Revision: 99308

URL: http://llvm.org/viewvc/llvm-project?rev=99308&view=rev
Log:
Add stub for pushdecl_top_level.

Modified:
    llvm-gcc-4.2/trunk/gcc/stub-c.c

Modified: llvm-gcc-4.2/trunk/gcc/stub-c.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/stub-c.c?rev=99308&r1=99307&r2=99308&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/stub-c.c (original)
+++ llvm-gcc-4.2/trunk/gcc/stub-c.c Tue Mar 23 13:48:56 2010
@@ -191,3 +191,11 @@
   gcc_assert(0);
   return NULL;
 }
+
+tree pushdecl_top_level(tree) ATTRIBUTE_WEAK;
+
+tree
+pushdecl_top_level(tree x ATTRIBUTE_UNUSED) {
+  gcc_assert(0);
+  return NULL;
+}




From bob.wilson at apple.com  Tue Mar 23 13:54:46 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 23 Mar 2010 18:54:46 -0000
Subject: [llvm-commits] [llvm] r99309 - in /llvm/trunk/lib/Target/ARM:
 ARMBaseInstrInfo.cpp ARMISelDAGToDAG.cpp ARMInstrFormats.td ARMInstrNEON.td
Message-ID: <20100323185446.CD80F2A6C12C@llvm.org>

Author: bwilson
Date: Tue Mar 23 13:54:46 2010
New Revision: 99309

URL: http://llvm.org/viewvc/llvm-project?rev=99309&view=rev
Log:
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=99309&r1=99308&r2=99309&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Mar 23 13:54:46 2010
@@ -745,7 +745,9 @@
     } else {
       AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)).
                      addReg(SrcReg, getKillRegState(isKill))
-                     .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
+                     .addFrameIndex(FI)
+                     .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
+                     .addMemOperand(MMO));
     }
   }
 }
@@ -793,7 +795,9 @@
                      .addMemOperand(MMO));
     } else {
       AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
-                     .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
+                     .addFrameIndex(FI)
+                     .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
+                     .addMemOperand(MMO));
     }
   }
 }

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=99309&r1=99308&r2=99309&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Mar 23 13:54:46 2010
@@ -1701,6 +1701,35 @@
       ResNode = SelectARMIndexedLoad(N);
     if (ResNode)
       return ResNode;
+
+    // VLDMQ must be custom-selected for "v2f64 load" to set the AM5Opc value.
+    if (Subtarget->hasVFP2() &&
+        N->getValueType(0).getSimpleVT().SimpleTy == MVT::v2f64) {
+      SDValue Chain = N->getOperand(0);
+      SDValue AM5Opc =
+        CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32);
+      SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
+      SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
+      SDValue Ops[] = { N->getOperand(1), AM5Opc, Pred, PredReg, Chain };
+      return CurDAG->getMachineNode(ARM::VLDMQ, dl, MVT::v2f64, MVT::Other,
+                                    Ops, 5);
+    }
+    // Other cases are autogenerated.
+    break;
+  }
+  case ISD::STORE: {
+    // VSTMQ must be custom-selected for "v2f64 store" to set the AM5Opc value.
+    if (Subtarget->hasVFP2() &&
+        N->getOperand(1).getValueType().getSimpleVT().SimpleTy == MVT::v2f64) {
+      SDValue Chain = N->getOperand(0);
+      SDValue AM5Opc =
+        CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32);
+      SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
+      SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
+      SDValue Ops[] = { N->getOperand(1), N->getOperand(2),
+                        AM5Opc, Pred, PredReg, Chain };
+      return CurDAG->getMachineNode(ARM::VSTMQ, dl, MVT::Other, Ops, 6);
+    }
     // Other cases are autogenerated.
     break;
   }

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99309&r1=99308&r2=99309&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 13:54:46 2010
@@ -1503,12 +1503,6 @@
            pattern> {
 }
 
-class NI4<dag oops, dag iops, InstrItinClass itin, string opc,
-          string asm, list<dag> pattern>
-  : NeonXI<oops, iops, AddrMode4, IndexModeNone, itin, opc, asm, "",
-          pattern> {
-}
-
 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
             dag oops, dag iops, InstrItinClass itin,
             string opc, string dt, string asm, string cstr, list<dag> pattern>

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99309&r1=99308&r2=99309&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 13:54:46 2010
@@ -115,19 +115,20 @@
 // NEON load / store instructions
 //===----------------------------------------------------------------------===//
 
+let mayLoad = 1 in {
 // Use vldmia to load a Q register as a D register pair.
-// This is equivalent to VLDMD except that it has a Q register operand.
-def VLDMQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoadm,
-                "vldmia", "$addr, ${dst:dregpair}",
-                [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
-  let Inst{27-25} = 0b110;
-  let Inst{24}    = 0; // P bit
-  let Inst{23}    = 1; // U bit
-  let Inst{20}    = 1;
-  let Inst{11-8}  = 0b1011;
-}
+// This is equivalent to VLDMD except that it has a Q register operand
+// instead of a pair of D registers.
+def VLDMQ
+  : AXDI5<(outs QPR:$dst), (ins addrmode5:$addr, pred:$p),
+          IndexModeNone, IIC_fpLoadm,
+          "vldm${addr:submode}${p}\t${addr:base}, ${dst:dregpair}", "", []>;
+def VLDMQ_UPD
+  : AXDI5<(outs QPR:$dst, GPR:$wb), (ins addrmode5:$addr, pred:$p),
+          IndexModeUpd, IIC_fpLoadm,
+          "vldm${addr:submode}${p}\t${addr:base}!, ${dst:dregpair}",
+          "$addr.base = $wb", []>;
 
-let mayLoad = 1 in {
 // Use vld1 to load a Q register as a D register pair.
 // This alternative to VLDMQ allows an alignment to be specified.
 // This is equivalent to VLD1q64 except that it has a Q register operand.
@@ -140,19 +141,20 @@
           "${dst:dregpair}, $addr$offset", "$addr.addr = $wb", []>;
 } // mayLoad = 1
 
+let mayStore = 1 in {
 // Use vstmia to store a Q register as a D register pair.
-// This is equivalent to VSTMD except that it has a Q register operand.
-def VSTMQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem,
-                "vstmia", "$addr, ${src:dregpair}",
-                [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
-  let Inst{27-25} = 0b110;
-  let Inst{24}    = 0; // P bit
-  let Inst{23}    = 1; // U bit
-  let Inst{20}    = 0;
-  let Inst{11-8}  = 0b1011;
-}
+// This is equivalent to VSTMD except that it has a Q register operand
+// instead of a pair of D registers.
+def VSTMQ
+  : AXDI5<(outs), (ins QPR:$src, addrmode5:$addr, pred:$p),
+          IndexModeNone, IIC_fpStorem,
+          "vstm${addr:submode}${p}\t${addr:base}, ${src:dregpair}", "", []>;
+def VSTMQ_UPD
+  : AXDI5<(outs GPR:$wb), (ins QPR:$src, addrmode5:$addr, pred:$p),
+          IndexModeUpd, IIC_fpStorem,
+          "vstm${addr:submode}${p}\t${addr:base}!, ${src:dregpair}",
+          "$addr.base = $wb", []>;
 
-let mayStore = 1 in {
 // Use vst1 to store a Q register as a D register pair.
 // This alternative to VSTMQ allows an alignment to be specified.
 // This is equivalent to VST1q64 except that it has a Q register operand.




From ggreif at gmail.com  Tue Mar 23 14:08:19 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 23 Mar 2010 19:08:19 -0000
Subject: [llvm-commits] [test-suite] r99315 -
 /test-suite/trunk/MultiSource/Benchmarks/PAQ8p/paq8p.cpp
Message-ID: <20100323190820.033122A6C12C@llvm.org>

Author: ggreif
Date: Tue Mar 23 14:08:19 2010
New Revision: 99315

URL: http://llvm.org/viewvc/llvm-project?rev=99315&view=rev
Log:
fix two warnings (pointed out by clang)
there are others, but those probably should be
fixed by an upgrade, as they are semantically relevant

Modified:
    test-suite/trunk/MultiSource/Benchmarks/PAQ8p/paq8p.cpp

Modified: test-suite/trunk/MultiSource/Benchmarks/PAQ8p/paq8p.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/PAQ8p/paq8p.cpp?rev=99315&r1=99314&r2=99315&view=diff
==============================================================================
--- test-suite/trunk/MultiSource/Benchmarks/PAQ8p/paq8p.cpp (original)
+++ test-suite/trunk/MultiSource/Benchmarks/PAQ8p/paq8p.cpp Tue Mar 23 14:08:19 2010
@@ -605,7 +605,9 @@
 #include <time.h>
 #include <math.h>
 #include <ctype.h>
+#ifndef NDEBUG
 #define NDEBUG  // remove for debugging (turns on Array bound checks)
+#endif
 #include <assert.h>
 
 #ifdef UNIX
@@ -4389,7 +4391,7 @@
         while (*p && *p!='\t') ++p;
         fname[i]=p+1;
         while (*p && *p!='\r') ++p;
-        if (!*p) printf("%s: header corrupted at %d\n", archiveName.c_str(),
+        if (!*p) printf("%s: header corrupted at %ld\n", archiveName.c_str(),
           p-&filenames[0]), quit();
         assert(p-&filenames[0]<header_size);
         *p++=0;




From evan.cheng at apple.com  Tue Mar 23 15:33:48 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 23 Mar 2010 20:33:48 -0000
Subject: [llvm-commits] [llvm] r99319 -
	/llvm/trunk/lib/CodeGen/MachineCSE.cpp
Message-ID: <20100323203348.D4ED22A6C12C@llvm.org>

Author: evancheng
Date: Tue Mar 23 15:33:48 2010
New Revision: 99319

URL: http://llvm.org/viewvc/llvm-project?rev=99319&view=rev
Log:
Code clean up.

Modified:
    llvm/trunk/lib/CodeGen/MachineCSE.cpp

Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=99319&r1=99318&r2=99319&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Tue Mar 23 15:33:48 2010
@@ -117,17 +117,15 @@
                                         MachineBasicBlock::const_iterator I,
                                         MachineBasicBlock::const_iterator E) {
   unsigned LookAheadLeft = 5;
-  while (LookAheadLeft--) {
+  while (LookAheadLeft) {
     if (I == E)
       // Reached end of block, register is obviously dead.
       return true;
 
-    if (I->isDebugValue()) {
-      // These must not count against the limit.
-      ++LookAheadLeft;
+    // Skip over dbg_value's.
+    while (I->isDebugValue())
       ++I;
-      continue;
-    }
+
     bool SeenDef = false;
     for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
       const MachineOperand &MO = I->getOperand(i);
@@ -143,6 +141,8 @@
       // See a def of Reg (or an alias) before encountering any use, it's 
       // trivially dead.
       return true;
+
+    --LookAheadLeft;
     ++I;
   }
   return false;




From evan.cheng at apple.com  Tue Mar 23 15:35:45 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 23 Mar 2010 20:35:45 -0000
Subject: [llvm-commits] [llvm] r99320 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Message-ID: <20100323203545.6C2EF2A6C12C@llvm.org>

Author: evancheng
Date: Tue Mar 23 15:35:45 2010
New Revision: 99320

URL: http://llvm.org/viewvc/llvm-project?rev=99320&view=rev
Log:
Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically?

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=99320&r1=99319&r2=99320&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Mar 23 15:35:45 2010
@@ -992,8 +992,10 @@
 /// a few instructions in each direction it assumes it's not safe.
 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I) {
+  MachineBasicBlock::iterator E = MBB.end();
+
   // It's always safe to clobber EFLAGS at the end of a block.
-  if (I == MBB.end())
+  if (I == E)
     return true;
 
   // For compile time consideration, if we are not able to determine the
@@ -1017,20 +1019,28 @@
       // This instruction defines EFLAGS, no need to look any further.
       return true;
     ++Iter;
+    // Skip over DBG_VALUE.
+    while (Iter != E && Iter->isDebugValue())
+      ++Iter;
 
     // If we make it to the end of the block, it's safe to clobber EFLAGS.
-    if (Iter == MBB.end())
+    if (Iter == E)
       return true;
   }
 
+  MachineBasicBlock::iterator B = MBB.begin();
   Iter = I;
   for (unsigned i = 0; i < 4; ++i) {
     // If we make it to the beginning of the block, it's safe to clobber
     // EFLAGS iff EFLAGS is not live-in.
-    if (Iter == MBB.begin())
+    if (Iter == B)
       return !MBB.isLiveIn(X86::EFLAGS);
 
     --Iter;
+    // Skip over DBG_VALUE.
+    while (Iter != B && Iter->isDebugValue())
+      --Iter;
+
     bool SawKill = false;
     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
       MachineOperand &MO = Iter->getOperand(j);




From evan.cheng at apple.com  Tue Mar 23 15:36:12 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 23 Mar 2010 20:36:12 -0000
Subject: [llvm-commits] [llvm] r99321 -
	/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
Message-ID: <20100323203612.A637B2A6C12C@llvm.org>

Author: evancheng
Date: Tue Mar 23 15:36:12 2010
New Revision: 99321

URL: http://llvm.org/viewvc/llvm-project?rev=99321&view=rev
Log:
Ignore dbg_value's.

Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=99321&r1=99320&r2=99321&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Mar 23 15:36:12 2010
@@ -188,8 +188,9 @@
 
   // Find the instruction that kills SavedReg.
   MachineInstr *KillMI = NULL;
-  for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg),
-         UE = MRI->use_end(); UI != UE; ++UI) {
+  for (MachineRegisterInfo::use_nodbg_iterator
+         UI = MRI->use_nodbg_begin(SavedReg),
+         UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
     MachineOperand &UseMO = UI.getOperand();
     if (!UseMO.isKill())
       continue;
@@ -280,8 +281,8 @@
                                          MachineInstr *MI, MachineInstr *DefMI,
                                          MachineBasicBlock *MBB, unsigned Loc) {
   bool OtherUse = false;
-  for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
-         UE = MRI->use_end(); UI != UE; ++UI) {
+  for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg),
+         UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
     MachineOperand &UseMO = UI.getOperand();
     MachineInstr *UseMI = UseMO.getParent();
     MachineBasicBlock *UseMBB = UseMI->getParent();
@@ -927,6 +928,7 @@
         mi = nmi;
         continue;
       }
+
       const TargetInstrDesc &TID = mi->getDesc();
       bool FirstTied = true;
 
@@ -1101,7 +1103,7 @@
   // Some remat'ed instructions are dead.
   int VReg = ReMatRegs.find_first();
   while (VReg != -1) {
-    if (MRI->use_empty(VReg)) {
+    if (MRI->use_nodbg_empty(VReg)) {
       MachineInstr *DefMI = MRI->getVRegDef(VReg);
       DefMI->eraseFromParent();
     }




From johnny.chen at apple.com  Tue Mar 23 15:40:44 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 23 Mar 2010 20:40:44 -0000
Subject: [llvm-commits] [llvm] r99322 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20100323204044.72B102A6C12C@llvm.org>

Author: johnny
Date: Tue Mar 23 15:40:44 2010
New Revision: 99322

URL: http://llvm.org/viewvc/llvm-project?rev=99322&view=rev
Log:
Add New NEON Format NVdVmImmFrm.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99322&r1=99321&r2=99322&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 15:40:44 2010
@@ -59,8 +59,9 @@
 def MiscFrm       : Format<29>;
 def ThumbMiscFrm  : Format<30>;
 
-def NLdStFrm      : Format<31>;
-def NVdImmFrm     : Format<32>;
+def NLdStFrm                : Format<31>;
+def NVdImmFrm               : Format<32>;
+def NVdVmImmFrm             : Format<33>;
 
 // Misc flags.
 
@@ -1487,9 +1488,10 @@
 }
 
 // Same as NeonI except it does not have a "data type" specifier.
-class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
-             string opc, string asm, string cstr, list<dag> pattern>
-  : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
+class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
+             InstrItinClass itin, string opc, string asm, string cstr,
+             list<dag> pattern>
+  : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
   let OutOperandList = oops;
   let InOperandList = !con(iops, (ins pred:$p));
   let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm));
@@ -1499,7 +1501,7 @@
 
 class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm,
          list<dag> pattern>
-  : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "",
+  : NeonXI<oops, iops, AddrModeNone, IndexModeNone, NEONFrm, itin, opc, asm, "",
            pattern> {
 }
 
@@ -1522,9 +1524,9 @@
   let Inst{31-25} = 0b1111001;
 }
 
-class NDataXI<dag oops, dag iops, InstrItinClass itin,
+class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
               string opc, string asm, string cstr, list<dag> pattern>
-  : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm,
+  : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
            cstr, pattern> {
   let Inst{31-25} = 0b1111001;
 }
@@ -1550,7 +1552,7 @@
           bits<5> op11_7, bit op6, bit op4,
           dag oops, dag iops, InstrItinClass itin,
           string opc, string dt, string asm, string cstr, list<dag> pattern>
-  : NDataI<oops, iops, NEONFrm, itin, opc, dt, asm, cstr, pattern> {
+  : NDataI<oops, iops, NVdVmImmFrm, itin, opc, dt, asm, cstr, pattern> {
   let Inst{24-23} = op24_23;
   let Inst{21-20} = op21_20;
   let Inst{19-18} = op19_18;
@@ -1565,7 +1567,7 @@
            bits<5> op11_7, bit op6, bit op4,
            dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, string cstr, list<dag> pattern>
-  : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
+  : NDataXI<oops, iops, NVdVmImmFrm, itin, opc, asm, cstr, pattern> {
   let Inst{24-23} = op24_23;
   let Inst{21-20} = op21_20;
   let Inst{19-18} = op19_18;
@@ -1606,7 +1608,7 @@
            bit op4,
            dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, string cstr, list<dag> pattern>
-  : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
+  : NDataXI<oops, iops, NEONFrm, itin, opc, asm, cstr, pattern> {
   let Inst{24} = op24;
   let Inst{23} = op23;
   let Inst{21-20} = op21_20;




From isanbard at gmail.com  Tue Mar 23 16:15:59 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 23 Mar 2010 21:15:59 -0000
Subject: [llvm-commits] [llvm] r99324 -
	/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
Message-ID: <20100323211559.7174B2A6C12C@llvm.org>

Author: void
Date: Tue Mar 23 16:15:59 2010
New Revision: 99324

URL: http://llvm.org/viewvc/llvm-project?rev=99324&view=rev
Log:
Skip debugging intrinsics when sinking unused invariants.

Modified:
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=99324&r1=99323&r2=99324&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Mar 23 16:15:59 2010
@@ -553,22 +553,26 @@
     // New instructions were inserted at the end of the preheader.
     if (isa<PHINode>(I))
       break;
+
     // Don't move instructions which might have side effects, since the side
-    // effects need to complete before instructions inside the loop.  Also
-    // don't move instructions which might read memory, since the loop may
-    // modify memory. Note that it's okay if the instruction might have
-    // undefined behavior: LoopSimplify guarantees that the preheader
-    // dominates the exit block.
+    // effects need to complete before instructions inside the loop.  Also don't
+    // move instructions which might read memory, since the loop may modify
+    // memory. Note that it's okay if the instruction might have undefined
+    // behavior: LoopSimplify guarantees that the preheader dominates the exit
+    // block.
     if (I->mayHaveSideEffects() || I->mayReadFromMemory())
       continue;
+
     // Skip debug info intrinsics.
     if (isa<DbgInfoIntrinsic>(I))
       continue;
+
     // Don't sink static AllocaInsts out of the entry block, which would
     // turn them into dynamic allocas!
     if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
       if (AI->isStaticAlloca())
         continue;
+
     // Determine if there is a use in or before the loop (direct or
     // otherwise).
     bool UsedInLoop = false;
@@ -585,19 +589,29 @@
         break;
       }
     }
+
     // If there is, the def must remain in the preheader.
     if (UsedInLoop)
       continue;
+
     // Otherwise, sink it to the exit block.
     Instruction *ToMove = I;
     bool Done = false;
-    if (I != Preheader->begin())
-      --I;
-    else
+
+    if (I != Preheader->begin()) {
+      // Skip debug info intrinsics.
+      do {
+        --I;
+      } while (isa<DbgInfoIntrinsic>(I) && I != Preheader->begin());
+
+      if (isa<DbgInfoIntrinsic>(I) && I == Preheader->begin())
+        Done = true;
+    } else {
       Done = true;
+    }
+
     ToMove->moveBefore(InsertPt);
-    if (Done)
-      break;
+    if (Done) break;
     InsertPt = ToMove;
   }
 }




From bob.wilson at apple.com  Tue Mar 23 16:17:53 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 23 Mar 2010 14:17:53 -0700
Subject: [llvm-commits] [llvm] r99322 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
In-Reply-To: <20100323204044.72B102A6C12C@llvm.org>
References: <20100323204044.72B102A6C12C@llvm.org>
Message-ID: <C66E1E95-EC1B-4C26-AA8D-FDFE70C55025@apple.com>

See comments below:

On Mar 23, 2010, at 1:40 PM, Johnny Chen wrote:

> Author: johnny
> Date: Tue Mar 23 15:40:44 2010
> New Revision: 99322
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99322&view=rev
> Log:
> Add New NEON Format NVdVmImmFrm.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99322&r1=99321&r2=99322&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 15:40:44 2010
> @@ -59,8 +59,9 @@
> def MiscFrm       : Format<29>;
> def ThumbMiscFrm  : Format<30>;
> 
> -def NLdStFrm      : Format<31>;
> -def NVdImmFrm     : Format<32>;
> +def NLdStFrm                : Format<31>;
> +def NVdImmFrm               : Format<32>;
> +def NVdVmImmFrm             : Format<33>;

I'm not thrilled with these names.  How about "N2RegImmFrm" instead of "NVdVmImmFrm"?  For consistency, "NVdImmFrm" should then be something like "N1RegModImm".

The rest of the patch changes the N2V and N2VX classes to have the new "NVdVmImmFrm" format, but neither of those classes are used for instructions with immediate operands, are they?  You didn't change N2VImm, which _does_ have an immediate operand.

If you intended this new format to describe instructions with 2 registers and NO immediate operand, then it shouldn't have "Imm" in the name of the format.


From johnny.chen at apple.com  Tue Mar 23 16:25:38 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 23 Mar 2010 21:25:38 -0000
Subject: [llvm-commits] [llvm] r99326 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrNEON.td
Message-ID: <20100323212538.8E13F2A6C12C@llvm.org>

Author: johnny
Date: Tue Mar 23 16:25:38 2010
New Revision: 99326

URL: http://llvm.org/viewvc/llvm-project?rev=99326&view=rev
Log:
Add New NEON Format NVdVmVCVTFrm.
Converted some of the NEON vcvt instructions to this format.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99326&r1=99325&r2=99326&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 16:25:38 2010
@@ -62,6 +62,7 @@
 def NLdStFrm                : Format<31>;
 def NVdImmFrm               : Format<32>;
 def NVdVmImmFrm             : Format<33>;
+def NVdVmVCVTFrm            : Format<34>;
 
 // Misc flags.
 

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99326&r1=99325&r2=99326&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 16:25:38 2010
@@ -853,25 +853,40 @@
 // Instruction Classes
 //===----------------------------------------------------------------------===//
 
+// Same as N2V except that it doesn't pass a default NVdVmImmFrm to NDataI.
+class N2V2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
+          bits<5> op11_7, bit op6, bit op4,
+          dag oops, dag iops, Format f, InstrItinClass itin,
+          string opc, string dt, string asm, string cstr, list<dag> pattern>
+  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
+  let Inst{24-23} = op24_23;
+  let Inst{21-20} = op21_20;
+  let Inst{19-18} = op19_18;
+  let Inst{17-16} = op17_16;
+  let Inst{11-7} = op11_7;
+  let Inst{6} = op6;
+  let Inst{4} = op4;
+}
+
 // Basic 2-register operations: single-, double- and quad-register.
 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
-  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
-        (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
-        IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
+  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
+         (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NVdVmVCVTFrm,
+         IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
-  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
-        (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
-        [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
+  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
+         (ins DPR:$src), NVdVmVCVTFrm, IIC_VUNAD, OpcodeStr, Dt,"$dst, $src","",
+         [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
-  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
-        (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
-        [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
+  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
+         (ins QPR:$src), NVdVmVCVTFrm, IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src","",
+         [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
 
 // Basic 2-register intrinsics, both double- and quad-register.
 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,




From johnny.chen at apple.com  Tue Mar 23 16:30:12 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 23 Mar 2010 21:30:12 -0000
Subject: [llvm-commits] [llvm] r99327 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20100323213012.D4BCA2A6C12C@llvm.org>

Author: johnny
Date: Tue Mar 23 16:30:12 2010
New Revision: 99327

URL: http://llvm.org/viewvc/llvm-project?rev=99327&view=rev
Log:
Add comment.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99327&r1=99326&r2=99327&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 16:30:12 2010
@@ -869,6 +869,7 @@
 }
 
 // Basic 2-register operations: single-, double- and quad-register.
+// This is used for NVdVmVCVTFrm form.
 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>




From johnny.chen at apple.com  Tue Mar 23 16:35:03 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 23 Mar 2010 21:35:03 -0000
Subject: [llvm-commits] [llvm] r99328 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20100323213503.3AFAA2A6C12C@llvm.org>

Author: johnny
Date: Tue Mar 23 16:35:03 2010
New Revision: 99328

URL: http://llvm.org/viewvc/llvm-project?rev=99328&view=rev
Log:
Fix typo in the comment for N3VX class.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99328&r1=99327&r2=99328&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 16:35:03 2010
@@ -1604,7 +1604,7 @@
   let Inst{4} = op4;
 }
 
-// Same as N3VX except it doesn't have a data type suffix.
+// Same as N3V except it doesn't have a data type suffix.
 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
            bit op4,
            dag oops, dag iops, InstrItinClass itin,




From isanbard at gmail.com  Tue Mar 23 16:36:36 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 23 Mar 2010 21:36:36 -0000
Subject: [llvm-commits] [test-suite] r99329 -
	/test-suite/trunk/TEST.m2regllcdbg.Makefile
Message-ID: <20100323213636.66A6E2A6C12C@llvm.org>

Author: void
Date: Tue Mar 23 16:36:36 2010
New Revision: 99329

URL: http://llvm.org/viewvc/llvm-project?rev=99329&view=rev
Log:
Remove "crit_edge*" comments. These could change, but they don't effect code
generation.

Modified:
    test-suite/trunk/TEST.m2regllcdbg.Makefile

Modified: test-suite/trunk/TEST.m2regllcdbg.Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/TEST.m2regllcdbg.Makefile?rev=99329&r1=99328&r2=99329&view=diff
==============================================================================
--- test-suite/trunk/TEST.m2regllcdbg.Makefile (original)
+++ test-suite/trunk/TEST.m2regllcdbg.Makefile Tue Mar 23 16:36:36 2010
@@ -17,7 +17,7 @@
 TESTNAME = $*
 TARGET_FLAGS = -g -O0
 LLC_DEBUG_FLAGS = -O0 -regalloc=local
-.PRECIOUS: Output/%.first.s Output/%.second.s Output/%.t2c.s Output/%.t1c.s
+.PRECIOUS: Output/%.first.s Output/%.second.s Output/%.t2c.s Output/%.t1c.s Output/%.t2b.bc Output/%.t1b.bc
 
 $(PROGRAMS_TO_TEST:%=test.$(TEST).%): \
 test.$(TEST).%: Output/%.diff
@@ -32,7 +32,7 @@
 	$(LLC) $(LLC_DEBUG_FLAGS) $< -f -o $@
 
 Output/%.first.s: Output/%.t1c.s Output/.dir $(LLC)
-	grep -v '\.long' < $< | grep -v '\.byte' | grep -v '\.short' | grep -v '\.asci' | grep -v '\.quad' | grep -v '## DW_AT' | grep -v '## Abbrev' | grep -v '## End Of Children' | grep -v '## DIE' | grep -v '## $$' | grep -v '^$$' > $@
+	grep -v '\.long' < $< | grep -v '\.byte' | grep -v '\.short' | grep -v '\.asci' | grep -v '\.quad' | grep -v '## DW_AT' | grep -v '## Abbrev' | grep -v '## End Of Children' | grep -v '## DIE' | grep -v '## $$' | grep -v '^#.*' | grep -v '^$$' | sed -e 's,## %._crit_edge[0-9]*,##,' > $@
 
 Output/%.t2a.bc: Output/%.linked.rbc Output/.dir $(LOPT)
 	$(LOPT) -strip-nondebug $< -f -o $@
@@ -44,7 +44,7 @@
 	$(LLC) $(LLC_DEBUG_FLAGS) $< -f -o $@
 
 Output/%.second.s: Output/%.t2c.s Output/.dir
-	grep -v DEBUG_VALUE < $< | grep -v '\.long' | grep -v '\.byte' | grep -v '\.short' | grep -v '\.asci' | grep -v '## DW_AT' | grep -v '## Abbrev' |  grep -v '## End Of Children' | grep -v '## DIE' | grep -v '## $$' | grep -v '\.quad' | grep -v '^$$' > $@
+	grep -v DEBUG_VALUE < $< | grep -v '\.long' | grep -v '\.byte' | grep -v '\.short' | grep -v '\.asci' | grep -v '## DW_AT' | grep -v '## Abbrev' |  grep -v '## End Of Children' | grep -v '## DIE' | grep -v '## $$' | grep -v '\.quad' | grep -v '^#' | grep -v '^$$' | sed -e 's,## %._crit_edge[0-9]*,##,' > $@
 
 Output/%.diff: Output/%.first.s Output/%.second.s
 	@-if diff $^ > $@; then \




From clattner at apple.com  Tue Mar 23 16:41:28 2010
From: clattner at apple.com (Chris Lattner)
Date: Tue, 23 Mar 2010 14:41:28 -0700
Subject: [llvm-commits] [test-suite] r99329 -
	/test-suite/trunk/TEST.m2regllcdbg.Makefile
In-Reply-To: <20100323213636.66A6E2A6C12C@llvm.org>
References: <20100323213636.66A6E2A6C12C@llvm.org>
Message-ID: <56A8637E-2A14-40F7-933D-9F72495E2548@apple.com>


On Mar 23, 2010, at 2:36 PM, Bill Wendling wrote:

> Author: void
> Date: Tue Mar 23 16:36:36 2010
> New Revision: 99329
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99329&view=rev
> Log:
> Remove "crit_edge*" comments. These could change, but they don't effect code
> generation.

Are you checking the -fverbose-asm output or something or do these comments come out even when verbose-asm is disabled?  If they're coming out with verbose-asm off, we should fix that.

-Chris

> 
> Modified:
>    test-suite/trunk/TEST.m2regllcdbg.Makefile
> 
> Modified: test-suite/trunk/TEST.m2regllcdbg.Makefile
> URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/TEST.m2regllcdbg.Makefile?rev=99329&r1=99328&r2=99329&view=diff
> ==============================================================================
> --- test-suite/trunk/TEST.m2regllcdbg.Makefile (original)
> +++ test-suite/trunk/TEST.m2regllcdbg.Makefile Tue Mar 23 16:36:36 2010
> @@ -17,7 +17,7 @@
> TESTNAME = $*
> TARGET_FLAGS = -g -O0
> LLC_DEBUG_FLAGS = -O0 -regalloc=local
> -.PRECIOUS: Output/%.first.s Output/%.second.s Output/%.t2c.s Output/%.t1c.s
> +.PRECIOUS: Output/%.first.s Output/%.second.s Output/%.t2c.s Output/%.t1c.s Output/%.t2b.bc Output/%.t1b.bc
> 
> $(PROGRAMS_TO_TEST:%=test.$(TEST).%): \
> test.$(TEST).%: Output/%.diff
> @@ -32,7 +32,7 @@
> 	$(LLC) $(LLC_DEBUG_FLAGS) $< -f -o $@
> 
> Output/%.first.s: Output/%.t1c.s Output/.dir $(LLC)
> -	grep -v '\.long' < $< | grep -v '\.byte' | grep -v '\.short' | grep -v '\.asci' | grep -v '\.quad' | grep -v '## DW_AT' | grep -v '## Abbrev' | grep -v '## End Of Children' | grep -v '## DIE' | grep -v '## $$' | grep -v '^$$' > $@
> +	grep -v '\.long' < $< | grep -v '\.byte' | grep -v '\.short' | grep -v '\.asci' | grep -v '\.quad' | grep -v '## DW_AT' | grep -v '## Abbrev' | grep -v '## End Of Children' | grep -v '## DIE' | grep -v '## $$' | grep -v '^#.*' | grep -v '^$$' | sed -e 's,## %._crit_edge[0-9]*,##,' > $@
> 
> Output/%.t2a.bc: Output/%.linked.rbc Output/.dir $(LOPT)
> 	$(LOPT) -strip-nondebug $< -f -o $@
> @@ -44,7 +44,7 @@
> 	$(LLC) $(LLC_DEBUG_FLAGS) $< -f -o $@
> 
> Output/%.second.s: Output/%.t2c.s Output/.dir
> -	grep -v DEBUG_VALUE < $< | grep -v '\.long' | grep -v '\.byte' | grep -v '\.short' | grep -v '\.asci' | grep -v '## DW_AT' | grep -v '## Abbrev' |  grep -v '## End Of Children' | grep -v '## DIE' | grep -v '## $$' | grep -v '\.quad' | grep -v '^$$' > $@
> +	grep -v DEBUG_VALUE < $< | grep -v '\.long' | grep -v '\.byte' | grep -v '\.short' | grep -v '\.asci' | grep -v '## DW_AT' | grep -v '## Abbrev' |  grep -v '## End Of Children' | grep -v '## DIE' | grep -v '## $$' | grep -v '\.quad' | grep -v '^#' | grep -v '^$$' | sed -e 's,## %._crit_edge[0-9]*,##,' > $@
> 
> Output/%.diff: Output/%.first.s Output/%.second.s
> 	@-if diff $^ > $@; then \
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From clattner at apple.com  Tue Mar 23 16:42:40 2010
From: clattner at apple.com (Chris Lattner)
Date: Tue, 23 Mar 2010 14:42:40 -0700
Subject: [llvm-commits] [llvm] r99282 - in /llvm/trunk:
	lib/Transforms/Scalar/SimplifyLibCalls.cpp
	lib/Transforms/Utils/BuildLibCalls.cpp
	test/Transforms/SimplifyLibCalls/StrCpy.ll
In-Reply-To: <20100323154804.931872A6C12C@llvm.org>
References: <20100323154804.931872A6C12C@llvm.org>
Message-ID: <8BA006A9-CBB5-497A-BADA-D5B5B1A14F5F@apple.com>


On Mar 23, 2010, at 8:48 AM, Evan Cheng wrote:

> Author: evancheng
> Date: Tue Mar 23 10:48:04 2010
> New Revision: 99282
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99282&view=rev
> Log:
> Teach simplify libcall to transform __strcpy_chk to __memcpy_chk to enable optimizations down stream.

Hi Evan,

> +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Tue Mar 23 10:48:04 2010
> @@ -49,10 +49,13 @@
>   Function *Caller;
>   const TargetData *TD;
>   LLVMContext* Context;
> +  bool OptChkCall;  // True if it's optimizing a *_chk libcall.

This is state is not appropriate to add to LibCallOptimization.  If you want to do this, it should be added as a constructor option to StrCpyOpt.

-Chris

> public:
> -  LibCallOptimization() { }
> +  LibCallOptimization() : OptChkCall(false) { }
>   virtual ~LibCallOptimization() {}
> 
> +  void setOptChkCall(bool c) { OptChkCall = c; }
> +
>   /// CallOptimizer - This pure virtual method is implemented by base classes to
>   /// do various optimizations.  If this returns null then no transformation was
>   /// performed.  If it returns CI, then it transformed the call and CI is to be
> @@ -352,8 +355,10 @@
> struct StrCpyOpt : public LibCallOptimization {
>   virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
>     // Verify the "strcpy" function prototype.
> +    unsigned NumParams = OptChkCall ? 3 : 2;
>     const FunctionType *FT = Callee->getFunctionType();
> -    if (FT->getNumParams() != 2 || FT->getReturnType() != FT->getParamType(0) ||
> +    if (FT->getNumParams() != NumParams ||
> +        FT->getReturnType() != FT->getParamType(0) ||
>         FT->getParamType(0) != FT->getParamType(1) ||
>         FT->getParamType(0) != Type::getInt8PtrTy(*Context))
>       return 0;
> @@ -371,8 +376,13 @@
> 
>     // We have enough information to now generate the memcpy call to do the
>     // concatenation for us.  Make a memcpy to copy the nul byte with align = 1.
> -    EmitMemCpy(Dst, Src,
> -               ConstantInt::get(TD->getIntPtrType(*Context), Len), 1, B, TD);
> +    if (OptChkCall)
> +      EmitMemCpyChk(Dst, Src,
> +                    ConstantInt::get(TD->getIntPtrType(*Context), Len),
> +                    CI->getOperand(3), B, TD);
> +    else
> +      EmitMemCpy(Dst, Src,
> +                 ConstantInt::get(TD->getIntPtrType(*Context), Len), 1, B, TD);
>     return Dst;
>   }
> };
> @@ -1162,7 +1172,8 @@
>     StringMap<LibCallOptimization*> Optimizations;
>     // String and Memory LibCall Optimizations
>     StrCatOpt StrCat; StrNCatOpt StrNCat; StrChrOpt StrChr; StrCmpOpt StrCmp;
> -    StrNCmpOpt StrNCmp; StrCpyOpt StrCpy; StrNCpyOpt StrNCpy; StrLenOpt StrLen;
> +    StrNCmpOpt StrNCmp; StrCpyOpt StrCpy; StrCpyOpt StrCpyChk;
> +    StrNCpyOpt StrNCpy; StrLenOpt StrLen;
>     StrToOpt StrTo; StrStrOpt StrStr;
>     MemCmpOpt MemCmp; MemCpyOpt MemCpy; MemMoveOpt MemMove; MemSetOpt MemSet;
>     // Math Library Optimizations
> @@ -1228,6 +1239,10 @@
>   Optimizations["memmove"] = &MemMove;
>   Optimizations["memset"] = &MemSet;
> 
> +  // _chk variants of String and Memory LibCall Optimizations.
> +  StrCpyChk.setOptChkCall(true);
> +  Optimizations["__strcpy_chk"] = &StrCpyChk;
> +
>   // Math Library Optimizations
>   Optimizations["powf"] = &Pow;
>   Optimizations["pow"] = &Pow;
> 
> Modified: llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp?rev=99282&r1=99281&r2=99282&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp (original)
> +++ llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp Tue Mar 23 10:48:04 2010
> @@ -108,7 +108,7 @@
> 
> 
> /// EmitMemCpy - Emit a call to the memcpy function to the builder.  This always
> -/// expects that the size has type 'intptr_t' and Dst/Src are pointers.
> +/// expects that Len has type 'intptr_t' and Dst/Src are pointers.
> Value *llvm::EmitMemCpy(Value *Dst, Value *Src, Value *Len,
>                         unsigned Align, IRBuilder<> &B, const TargetData *TD) {
>   Module *M = B.GetInsertBlock()->getParent()->getParent();
> @@ -120,6 +120,30 @@
>                        ConstantInt::get(B.getInt32Ty(), Align));
> }
> 
> +/// EmitMemCpyChk - Emit a call to the __memcpy_chk function to the builder.
> +/// This expects that the Len and ObjSize have type 'intptr_t' and Dst/Src
> +/// are pointers.
> +Value *llvm::EmitMemCpyChk(Value *Dst, Value *Src, Value *Len, Value *ObjSize,
> +                           IRBuilder<> &B, const TargetData *TD) {
> +  Module *M = B.GetInsertBlock()->getParent()->getParent();
> +  AttributeWithIndex AWI;
> +  AWI = AttributeWithIndex::get(~0u, Attribute::NoUnwind);
> +  LLVMContext &Context = B.GetInsertBlock()->getContext();
> +  Value *MemCpy = M->getOrInsertFunction("__memcpy_chk",
> +                                         AttrListPtr::get(&AWI, 1),
> +                                         B.getInt8PtrTy(),
> +                                         B.getInt8PtrTy(),
> +                                         B.getInt8PtrTy(),
> +                                         TD->getIntPtrType(Context),
> +                                         TD->getIntPtrType(Context), NULL);
> +  Dst = CastToCStr(Dst, B);
> +  Src = CastToCStr(Src, B);
> +  CallInst *CI = B.CreateCall4(MemCpy, Dst, Src, Len, ObjSize);
> +  if (const Function *F = dyn_cast<Function>(MemCpy->stripPointerCasts()))
> +    CI->setCallingConv(F->getCallingConv());
> +  return CI;
> +}
> +
> /// EmitMemMove - Emit a call to the memmove function to the builder.  This
> /// always expects that the size has type 'intptr_t' and Dst/Src are pointers.
> Value *llvm::EmitMemMove(Value *Dst, Value *Src, Value *Len,
> 
> Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/StrCpy.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/StrCpy.ll?rev=99282&r1=99281&r2=99282&view=diff
> ==============================================================================
> --- llvm/trunk/test/Transforms/SimplifyLibCalls/StrCpy.ll (original)
> +++ llvm/trunk/test/Transforms/SimplifyLibCalls/StrCpy.ll Tue Mar 23 10:48:04 2010
> @@ -1,30 +1,37 @@
> ; Test that the StrCpyOptimizer works correctly
> -; RUN: opt < %s -simplify-libcalls -S | \
> -; RUN:   not grep {call.*strcpy}
> +; RUN: opt < %s -simplify-libcalls -S | FileCheck %s
> 
> ; This transformation requires the pointer size, as it assumes that size_t is
> ; the size of a pointer.
> -target datalayout = "-p:64:64:64"
> +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
> 
> - at hello = constant [6 x i8] c"hello\00"		; <[6 x i8]*> [#uses=1]
> - at null = constant [1 x i8] zeroinitializer		; <[1 x i8]*> [#uses=1]
> - at null_hello = constant [7 x i8] c"\00hello\00"		; <[7 x i8]*> [#uses=1]
> + at hello = constant [6 x i8] c"hello\00"
> 
> declare i8* @strcpy(i8*, i8*)
> 
> -declare i32 @puts(i8*)
> +declare i8* @__strcpy_chk(i8*, i8*, i32) nounwind
> 
> -define i32 @main() {
> -	%target = alloca [1024 x i8]		; <[1024 x i8]*> [#uses=1]
> -	%arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0		; <i8*> [#uses=2]
> -	store i8 0, i8* %arg1
> -	%arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0		; <i8*> [#uses=1]
> -	%rslt1 = call i8* @strcpy( i8* %arg1, i8* %arg2 )		; <i8*> [#uses=1]
> -	%arg3 = getelementptr [1 x i8]* @null, i32 0, i32 0		; <i8*> [#uses=1]
> -	%rslt2 = call i8* @strcpy( i8* %rslt1, i8* %arg3 )		; <i8*> [#uses=1]
> -	%arg4 = getelementptr [7 x i8]* @null_hello, i32 0, i32 0		; <i8*> [#uses=1]
> -	%rslt3 = call i8* @strcpy( i8* %rslt2, i8* %arg4 )		; <i8*> [#uses=1]
> -	call i32 @puts( i8* %rslt3 )		; <i32>:1 [#uses=0]
> -	ret i32 0
> +declare i32 @llvm.objectsize.i32(i8*, i1) nounwind readonly
> +
> +; rdar://6839935
> +
> +define i32 @t1() {
> +; CHECK: @t1
> +  %target = alloca [1024 x i8]
> +  %arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0
> +  %arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0
> +  %rslt1 = call i8* @strcpy( i8* %arg1, i8* %arg2 )
> +; CHECK: @llvm.memcpy.i32
> +  ret i32 0
> }
> 
> +define i32 @t2() {
> +; CHECK: @t2
> +  %target = alloca [1024 x i8]
> +  %arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0
> +  %arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0
> +  %tmp1 = call i32 @llvm.objectsize.i32(i8* %arg1, i1 false)
> +  %rslt1 = call i8* @__strcpy_chk(i8* %arg1, i8* %arg2, i32 %tmp1)
> +; CHECK: @__memcpy_chk
> +  ret i32 0
> +}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From clattner at apple.com  Tue Mar 23 16:43:15 2010
From: clattner at apple.com (Chris Lattner)
Date: Tue, 23 Mar 2010 14:43:15 -0700
Subject: [llvm-commits] [llvm] r99256 - in
	/llvm/trunk/lib/MC:	MCAssembler.cpp MCMachOStreamer.cpp
In-Reply-To: <20100323050903.D38DF2A6C12C@llvm.org>
References: <20100323050903.D38DF2A6C12C@llvm.org>
Message-ID: <B7430C8F-5AE6-4B47-8192-E8C009F85025@apple.com>


On Mar 22, 2010, at 10:09 PM, Daniel Dunbar wrote:

> Author: ddunbar
> Date: Tue Mar 23 00:09:03 2010
> New Revision: 99256
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99256&view=rev
> Log:
> MC: Switch to using MCInst fragments to do relaxation.
> 
> Also, both MCMachOStreamer and MCAssembler are now target independent!

nice!


From bob.wilson at apple.com  Tue Mar 23 16:45:31 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 23 Mar 2010 14:45:31 -0700
Subject: [llvm-commits] [llvm] r99326 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrNEON.td
In-Reply-To: <20100323212538.8E13F2A6C12C@llvm.org>
References: <20100323212538.8E13F2A6C12C@llvm.org>
Message-ID: <965001EB-F442-4602-86B2-90FE8620B3A2@apple.com>


On Mar 23, 2010, at 2:25 PM, Johnny Chen wrote:

> Author: johnny
> Date: Tue Mar 23 16:25:38 2010
> New Revision: 99326
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99326&view=rev
> Log:
> Add New NEON Format NVdVmVCVTFrm.
> Converted some of the NEON vcvt instructions to this format.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99326&r1=99325&r2=99326&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 16:25:38 2010
> @@ -62,6 +62,7 @@
> def NLdStFrm                : Format<31>;
> def NVdImmFrm               : Format<32>;
> def NVdVmImmFrm             : Format<33>;
> +def NVdVmVCVTFrm            : Format<34>;

How about "NVCVTFrm"?


> 
> // Misc flags.
> 
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99326&r1=99325&r2=99326&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 16:25:38 2010
> @@ -853,25 +853,40 @@
> // Instruction Classes
> //===----------------------------------------------------------------------===//
> 
> +// Same as N2V except that it doesn't pass a default NVdVmImmFrm to NDataI.
> +class N2V2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
> +          bits<5> op11_7, bit op6, bit op4,
> +          dag oops, dag iops, Format f, InstrItinClass itin,
> +          string opc, string dt, string asm, string cstr, list<dag> pattern>
> +  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
> +  let Inst{24-23} = op24_23;
> +  let Inst{21-20} = op21_20;
> +  let Inst{19-18} = op19_18;
> +  let Inst{17-16} = op17_16;
> +  let Inst{11-7} = op11_7;
> +  let Inst{6} = op6;
> +  let Inst{4} = op4;
> +}
> +

This should not be necessary.  You should not have added the NVdVmImmFrm for N2V to begin with (per my earlier comments).  Please remove this class.


> // Basic 2-register operations: single-, double- and quad-register.
> class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
> -        (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
> -        IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
> +         (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NVdVmVCVTFrm,
> +         IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
> class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
> -        (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
> -        [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
> +         (ins DPR:$src), NVdVmVCVTFrm, IIC_VUNAD, OpcodeStr, Dt,"$dst, $src","",
> +         [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
> class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
> -        (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
> -        [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
> +         (ins QPR:$src), NVdVmVCVTFrm, IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src","",
> +         [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
> 
> // Basic 2-register intrinsics, both double- and quad-register.
> class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From sabre at nondot.org  Tue Mar 23 16:48:41 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 23 Mar 2010 21:48:41 -0000
Subject: [llvm-commits] [llvm] r99330 - /llvm/trunk/lib/VMCore/Module.cpp
Message-ID: <20100323214841.583552A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 16:48:41 2010
New Revision: 99330

URL: http://llvm.org/viewvc/llvm-project?rev=99330&view=rev
Log:
fix an infinite loop in Module::getEndianness, PR6684
patch by Alex Mac!

Modified:
    llvm/trunk/lib/VMCore/Module.cpp

Modified: llvm/trunk/lib/VMCore/Module.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Module.cpp?rev=99330&r1=99329&r2=99330&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Module.cpp (original)
+++ llvm/trunk/lib/VMCore/Module.cpp Tue Mar 23 16:48:41 2010
@@ -82,7 +82,7 @@
   
   while (!temp.empty()) {
     StringRef token = DataLayout;
-    tie(token, temp) = getToken(DataLayout, "-");
+    tie(token, temp) = getToken(temp, "-");
     
     if (token[0] == 'e') {
       ret = LittleEndian;




From ggreif at gmail.com  Tue Mar 23 16:50:49 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 23 Mar 2010 21:50:49 -0000
Subject: [llvm-commits] [test-suite] r99331 -
	/test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile
Message-ID: <20100323215049.6B28F2A6C12C@llvm.org>

Author: ggreif
Date: Tue Mar 23 16:50:49 2010
New Revision: 99331

URL: http://llvm.org/viewvc/llvm-project?rev=99331&view=rev
Log:
support for running out-of-source tree

Modified:
    test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile

Modified: test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile?rev=99331&r1=99330&r2=99331&view=diff
==============================================================================
--- test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile (original)
+++ test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile Tue Mar 23 16:50:49 2010
@@ -4,8 +4,8 @@
 CPPFLAGS += -DNOASM -DLLVM
 LDFLAGS = -lstdc++ -lm
 ifdef SMALL_PROBLEM_SIZE
-RUN_OPTIONS = -1 file1.in
+RUN_OPTIONS = -1 $(PROJ_SRC_ROOT)/MultiSource/Benchmarks/PAQ8p/file1.in
 else
-RUN_OPTIONS = -4 file1.in
+RUN_OPTIONS = -4 $(PROJ_SRC_ROOT)/MultiSource/Benchmarks/PAQ8p/file1.in
 endif
 include $(LEVEL)/MultiSource/Makefile.multisrc




From gohman at apple.com  Tue Mar 23 16:53:22 2010
From: gohman at apple.com (Dan Gohman)
Date: Tue, 23 Mar 2010 21:53:22 -0000
Subject: [llvm-commits] [llvm] r99332 -
	/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
Message-ID: <20100323215322.9FB342A6C12C@llvm.org>

Author: djg
Date: Tue Mar 23 16:53:22 2010
New Revision: 99332

URL: http://llvm.org/viewvc/llvm-project?rev=99332&view=rev
Log:
Don't back past debug info intrinsics; SCEVExpander's strategy
for ignoring debug info intrinsics everywhere else is to advance
past them, and it needs to be consistent.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=99332&r1=99331&r2=99332&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Tue Mar 23 16:53:22 2010
@@ -1268,19 +1268,8 @@
        L = L->getParentLoop())
     if (S->isLoopInvariant(L)) {
       if (!L) break;
-      if (BasicBlock *Preheader = L->getLoopPreheader()) {
+      if (BasicBlock *Preheader = L->getLoopPreheader())
         InsertPt = Preheader->getTerminator();
-        BasicBlock::iterator IP = InsertPt;
-        // Back past any debug info instructions.  Sometimes we inserted
-        // something earlier before debug info but after any real instructions.
-        // This should behave the same as if debug info was not present.
-        while (IP != Preheader->begin()) {
-          --IP;
-          if (!isa<DbgInfoIntrinsic>(IP))
-            break;
-          InsertPt = IP;
-        }
-      }
     } else {
       // If the SCEV is computable at this level, insert it into the header
       // after the PHIs (and after any other instructions that we've inserted




From sabre at nondot.org  Tue Mar 23 16:59:43 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 23 Mar 2010 21:59:43 -0000
Subject: [llvm-commits] [llvm] r99334 - /llvm/trunk/tools/llvm-ld/llvm-ld.cpp
Message-ID: <20100323215943.457942A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 16:59:43 2010
New Revision: 99334

URL: http://llvm.org/viewvc/llvm-project?rev=99334&view=rev
Log:
make sure to delete the llvm module before calling llvm_shutdown,
this fixes crashes in error cases, PR6683

Modified:
    llvm/trunk/tools/llvm-ld/llvm-ld.cpp

Modified: llvm/trunk/tools/llvm-ld/llvm-ld.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ld/llvm-ld.cpp?rev=99334&r1=99333&r2=99334&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-ld/llvm-ld.cpp (original)
+++ llvm/trunk/tools/llvm-ld/llvm-ld.cpp Tue Mar 23 16:59:43 2010
@@ -130,8 +130,9 @@
 /// Inputs:
 ///  Message  - The message to print to standard error.
 ///
-static void PrintAndExit(const std::string &Message, int errcode = 1) {
+static void PrintAndExit(const std::string &Message, Module *M, int errcode = 1) {
   errs() << progname << ": " << Message << "\n";
+  delete M;
   llvm_shutdown();
   exit(errcode);
 }
@@ -234,7 +235,7 @@
   raw_fd_ostream Out(FileName.c_str(), ErrorInfo,
                      raw_fd_ostream::F_Binary);
   if (!ErrorInfo.empty())
-    PrintAndExit(ErrorInfo);
+    PrintAndExit(ErrorInfo, M);
 
   // Ensure that the bitcode file gets removed from the disk if we get a
   // terminating signal.
@@ -408,7 +409,7 @@
 
 /// EmitShellScript - Output the wrapper file that invokes the JIT on the LLVM
 /// bitcode file for the program.
-static void EmitShellScript(char **argv) {
+static void EmitShellScript(char **argv, Module *M) {
   if (Verbose)
     outs() << "Emitting Shell Script\n";
 #if defined(_WIN32) || defined(__CYGWIN__)
@@ -419,10 +420,10 @@
   sys::Path llvmstub = FindExecutable("llvm-stub.exe", argv[0],
                                       (void *)(intptr_t)&Optimize);
   if (llvmstub.isEmpty())
-    PrintAndExit("Could not find llvm-stub.exe executable!");
+    PrintAndExit("Could not find llvm-stub.exe executable!", M);
 
   if (0 != sys::CopyFile(sys::Path(OutputFilename), llvmstub, &ErrMsg))
-    PrintAndExit(ErrMsg);
+    PrintAndExit(ErrMsg, M);
 
   return;
 #endif
@@ -431,7 +432,7 @@
   std::string ErrorInfo;
   raw_fd_ostream Out2(OutputFilename.c_str(), ErrorInfo);
   if (!ErrorInfo.empty())
-    PrintAndExit(ErrorInfo);
+    PrintAndExit(ErrorInfo, M);
 
   Out2 << "#!/bin/sh\n";
   // Allow user to setenv LLVMINTERP if lli is not in their PATH.
@@ -601,13 +602,13 @@
           prog = sys::Program::FindProgramByName(*I);
           if (prog.isEmpty())
             PrintAndExit(std::string("Optimization program '") + *I +
-              "' is not found or not executable.");
+                         "' is not found or not executable.", Composite.get());
         }
         // Get the program arguments
         sys::Path tmp_output("opt_result");
         std::string ErrMsg;
         if (tmp_output.createTemporaryFileOnDisk(true, &ErrMsg))
-          PrintAndExit(ErrMsg);
+          PrintAndExit(ErrMsg, Composite.get());
 
         const char* args[4];
         args[0] = I->c_str();
@@ -619,11 +620,12 @@
             sys::Path target(BitcodeOutputFilename);
             target.eraseFromDisk();
             if (tmp_output.renamePathOnDisk(target, &ErrMsg))
-              PrintAndExit(ErrMsg, 2);
+              PrintAndExit(ErrMsg, Composite.get(), 2);
           } else
-            PrintAndExit("Post-link optimization output is not bitcode");
+            PrintAndExit("Post-link optimization output is not bitcode",
+                         Composite.get());
         } else {
-          PrintAndExit(ErrMsg);
+          PrintAndExit(ErrMsg, Composite.get());
         }
       }
     }
@@ -645,21 +647,21 @@
       sys::Path llc = FindExecutable("llc", argv[0],
                                      (void *)(intptr_t)&Optimize);
       if (llc.isEmpty())
-        PrintAndExit("Failed to find llc");
+        PrintAndExit("Failed to find llc", Composite.get());
 
       sys::Path gcc = sys::Program::FindProgramByName("gcc");
       if (gcc.isEmpty())
-        PrintAndExit("Failed to find gcc");
+        PrintAndExit("Failed to find gcc", Composite.get());
 
       // Generate an assembly language file for the bitcode.
       std::string ErrMsg;
       if (0 != GenerateAssembly(AssemblyFile.str(), BitcodeOutputFilename,
           llc, ErrMsg))
-        PrintAndExit(ErrMsg);
+        PrintAndExit(ErrMsg, Composite.get());
 
       if (0 != GenerateNative(OutputFilename, AssemblyFile.str(),
                               NativeLinkItems, gcc, envp, ErrMsg))
-        PrintAndExit(ErrMsg);
+        PrintAndExit(ErrMsg, Composite.get());
 
       // Remove the assembly language file.
       AssemblyFile.eraseFromDisk();
@@ -675,39 +677,39 @@
       sys::Path llc = FindExecutable("llc", argv[0],
                                      (void *)(intptr_t)&Optimize);
       if (llc.isEmpty())
-        PrintAndExit("Failed to find llc");
+        PrintAndExit("Failed to find llc", Composite.get());
 
       sys::Path gcc = sys::Program::FindProgramByName("gcc");
       if (gcc.isEmpty())
-        PrintAndExit("Failed to find gcc");
+        PrintAndExit("Failed to find gcc", Composite.get());
 
       // Generate an assembly language file for the bitcode.
       std::string ErrMsg;
       if (GenerateCFile(CFile.str(), BitcodeOutputFilename, llc, ErrMsg))
-        PrintAndExit(ErrMsg);
+        PrintAndExit(ErrMsg, Composite.get());
 
       if (GenerateNative(OutputFilename, CFile.str(), 
                          NativeLinkItems, gcc, envp, ErrMsg))
-        PrintAndExit(ErrMsg);
+        PrintAndExit(ErrMsg, Composite.get());
 
       // Remove the assembly language file.
       CFile.eraseFromDisk();
 
     } else {
-      EmitShellScript(argv);
+      EmitShellScript(argv, Composite.get());
     }
 
     // Make the script executable...
     std::string ErrMsg;
     if (sys::Path(OutputFilename).makeExecutableOnDisk(&ErrMsg))
-      PrintAndExit(ErrMsg);
+      PrintAndExit(ErrMsg, Composite.get());
 
     // Make the bitcode file readable and directly executable in LLEE as well
     if (sys::Path(BitcodeOutputFilename).makeExecutableOnDisk(&ErrMsg))
-      PrintAndExit(ErrMsg);
+      PrintAndExit(ErrMsg, Composite.get());
 
     if (sys::Path(BitcodeOutputFilename).makeReadableOnDisk(&ErrMsg))
-      PrintAndExit(ErrMsg);
+      PrintAndExit(ErrMsg, Composite.get());
   }
 
   // Graceful exit




From johnny.chen at apple.com  Tue Mar 23 17:00:30 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 23 Mar 2010 15:00:30 -0700
Subject: [llvm-commits] [llvm] r99322 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
In-Reply-To: <C66E1E95-EC1B-4C26-AA8D-FDFE70C55025@apple.com>
References: <20100323204044.72B102A6C12C@llvm.org>
	<C66E1E95-EC1B-4C26-AA8D-FDFE70C55025@apple.com>
Message-ID: <278517EB-716D-464E-8ADA-89DFA70289DE@apple.com>

Attending a meeting, will deal with it later....

On Mar 23, 2010, at 2:17 PM, Bob Wilson wrote:

> See comments below:
> 
> On Mar 23, 2010, at 1:40 PM, Johnny Chen wrote:
> 
>> Author: johnny
>> Date: Tue Mar 23 15:40:44 2010
>> New Revision: 99322
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99322&view=rev
>> Log:
>> Add New NEON Format NVdVmImmFrm.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99322&r1=99321&r2=99322&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 15:40:44 2010
>> @@ -59,8 +59,9 @@
>> def MiscFrm       : Format<29>;
>> def ThumbMiscFrm  : Format<30>;
>> 
>> -def NLdStFrm      : Format<31>;
>> -def NVdImmFrm     : Format<32>;
>> +def NLdStFrm                : Format<31>;
>> +def NVdImmFrm               : Format<32>;
>> +def NVdVmImmFrm             : Format<33>;
> 
> I'm not thrilled with these names.  How about "N2RegImmFrm" instead of "NVdVmImmFrm"?  For consistency, "NVdImmFrm" should then be something like "N1RegModImm".
> 
> The rest of the patch changes the N2V and N2VX classes to have the new "NVdVmImmFrm" format, but neither of those classes are used for instructions with immediate operands, are they?  You didn't change N2VImm, which _does_ have an immediate operand.
> 
> If you intended this new format to describe instructions with 2 registers and NO immediate operand, then it shouldn't have "Imm" in the name of the format.




From isanbard at gmail.com  Tue Mar 23 17:03:35 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 23 Mar 2010 15:03:35 -0700
Subject: [llvm-commits] [test-suite] r99329 -
	/test-suite/trunk/TEST.m2regllcdbg.Makefile
In-Reply-To: <56A8637E-2A14-40F7-933D-9F72495E2548@apple.com>
References: <20100323213636.66A6E2A6C12C@llvm.org>
	<56A8637E-2A14-40F7-933D-9F72495E2548@apple.com>
Message-ID: <CF5E4DD6-7B2F-4FC1-B397-0F536D29FB81@gmail.com>

On Mar 23, 2010, at 2:41 PM, Chris Lattner wrote:

> On Mar 23, 2010, at 2:36 PM, Bill Wendling wrote:
> 
>> Author: void
>> Date: Tue Mar 23 16:36:36 2010
>> New Revision: 99329
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99329&view=rev
>> Log:
>> Remove "crit_edge*" comments. These could change, but they don't effect code
>> generation.
> 
> Are you checking the -fverbose-asm output or something or do these comments come out even when verbose-asm is disabled?  If they're coming out with verbose-asm off, we should fix that.
> 
This is the result of "llc", which has verbose-asm on by default as far as I can tell. We aren't checking the output of the comments in general. We do check them for DWARF debugging info, which is really only readable in comments. (That's my understanding. Devang can correct me if I'm wrong.)

-bw




From gohman at apple.com  Tue Mar 23 17:15:32 2010
From: gohman at apple.com (Dan Gohman)
Date: Tue, 23 Mar 2010 22:15:32 -0000
Subject: [llvm-commits] [llvm] r99335 - in /llvm/trunk:
 include/llvm/Target/TargetLowering.h
 lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Message-ID: <20100323221532.1DF5D2A6C12C@llvm.org>

Author: djg
Date: Tue Mar 23 17:15:31 2010
New Revision: 99335

URL: http://llvm.org/viewvc/llvm-project?rev=99335&view=rev
Log:
Remove getTypeToExpandTo, since it isn't adding much value
beyond just calling getTypeToTransformTo.

Modified:
    llvm/trunk/include/llvm/Target/TargetLowering.h
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=99335&r1=99334&r2=99335&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Tue Mar 23 17:15:31 2010
@@ -268,27 +268,6 @@
     return MVT(MVT::Other); // Not reached
   }
 
-  /// getTypeToExpandTo - For types supported by the target, this is an
-  /// identity function.  For types that must be expanded (i.e. integer types
-  /// that are larger than the largest integer register or illegal floating
-  /// point types), this returns the largest legal type it will be expanded to.
-  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
-    assert(!VT.isVector());
-    while (true) {
-      switch (getTypeAction(Context, VT)) {
-      case Legal:
-        return VT;
-      case Expand:
-        VT = getTypeToTransformTo(Context, VT);
-        break;
-      default:
-        assert(false && "Type is not legal nor is it to be expanded!");
-        return VT;
-      }
-    }
-    return VT;
-  }
-
   /// getVectorTypeBreakdown - Vector types are broken down into some number of
   /// legal first class types.  For example, EVT::v8f32 maps to 2 EVT::v4f32
   /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=99335&r1=99334&r2=99335&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Mar 23 17:15:31 2010
@@ -1021,7 +1021,7 @@
       Hi = InL;
     } else if (Amt == 1 &&
                TLI.isOperationLegalOrCustom(ISD::ADDC,
-                                            TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
+                                            TLI.getTypeToTransformTo(*DAG.getContext(), NVT))) {
       // Emit this X << 1 as X+X.
       SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
       SDValue LoOps[2] = { InL, InL };
@@ -1263,7 +1263,8 @@
   bool hasCarry =
     TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
                                    ISD::ADDC : ISD::SUBC,
-                                 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
+                                 TLI.getTypeToTransformTo(*DAG.getContext(),
+                                                          NVT));
 
   if (hasCarry) {
     SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);




From isanbard at gmail.com  Tue Mar 23 17:15:33 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 23 Mar 2010 22:15:33 -0000
Subject: [llvm-commits] [llvm] r99336 - in /llvm/trunk: tools/Makefile
	utils/buildit/build_llvm
Message-ID: <20100323221533.E7AE42A6C12D@llvm.org>

Author: void
Date: Tue Mar 23 17:15:33 2010
New Revision: 99336

URL: http://llvm.org/viewvc/llvm-project?rev=99336&view=rev
Log:
Use "DISABLE_EDIS" to disable building "edis" explicitly. Don't build it for
Apple-style builds.

Modified:
    llvm/trunk/tools/Makefile
    llvm/trunk/utils/buildit/build_llvm

Modified: llvm/trunk/tools/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=99336&r1=99335&r2=99336&view=diff
==============================================================================
--- llvm/trunk/tools/Makefile (original)
+++ llvm/trunk/tools/Makefile Tue Mar 23 17:15:33 2010
@@ -22,7 +22,6 @@
                  lli llvm-extract \
                  bugpoint llvm-bcanalyzer llvm-stub \
                  llvm-mc llvmc
-                 
 
 # Let users override the set of tools to build from the command line.
 ifdef ONLY_TOOLS
@@ -38,7 +37,7 @@
   # No support for dynamic libraries on windows targets.
   ifneq ($(TARGET_OS), $(filter $(TARGET_OS), Cygwin MingW))
     PARALLEL_DIRS += edis
-    
+
     # gold only builds if binutils is around.  It requires "lto" to build before
     # it so it is added to DIRS.
     ifdef BINUTILS_INCDIR
@@ -54,4 +53,9 @@
   PARALLEL_DIRS := $(filter-out edis, $(PARALLEL_DIRS))
 endif
 
+# Don't build edis if we explicitly disabled it.
+ifneq ($(DISABLE_EDIS),1)
+  PARALLEL_DIRS := $(filter-out edis, $(PARALLEL_DIRS))
+endif
+
 include $(LEVEL)/Makefile.common

Modified: llvm/trunk/utils/buildit/build_llvm
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=99336&r1=99335&r2=99336&view=diff
==============================================================================
--- llvm/trunk/utils/buildit/build_llvm (original)
+++ llvm/trunk/utils/buildit/build_llvm Tue Mar 23 17:15:33 2010
@@ -203,6 +203,7 @@
 make $JOBS_FLAG $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \
     UNIVERSAL_SDK_PATH=$HOST_SDKROOT \
     NO_RUNTIME_LIBS=1 \
+    DISABLE_EDIS=1 \
     LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \
     LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \
     CXXFLAGS="-DLLVM_VERSION_INFO='\" Apple Build #$LLVM_VERSION\"'" \
@@ -227,6 +228,7 @@
 # Install the tree into the destination directory.
 make $LOCAL_MAKEFLAGS $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \
     NO_RUNTIME_LIBS=1 \
+    DISABLE_EDIS=1 \
     LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \
     LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \
     OPTIMIZE_OPTION='-O3' VERBOSE=1 install




From dalej at apple.com  Tue Mar 23 17:26:48 2010
From: dalej at apple.com (Dale Johannesen)
Date: Tue, 23 Mar 2010 15:26:48 -0700
Subject: [llvm-commits] [test-suite] r99329 -
	/test-suite/trunk/TEST.m2regllcdbg.Makefile
In-Reply-To: <20100323213636.66A6E2A6C12C@llvm.org>
References: <20100323213636.66A6E2A6C12C@llvm.org>
Message-ID: <0EDCC3DA-845C-4CEE-A40E-29CAB69783B7@apple.com>


On Mar 23, 2010, at 2:36 PMPDT, Bill Wendling wrote:

> Remove "crit_edge*" comments. These could change, but they don't effect code
> generation.

The comments don't affect codegen, but the reason they change is that additional tmp symbols (a duplicate of some value that is already available elsewhere) are generated in one case.  It is true that some later pass clears up these dupes in all the examples I've looked at, so the only difference is the comments, but I'm unpersuaded this is always true, and I don't think this patch is a good idea.

The debugging patch here will dump out tmp symbols as they are created; you'll see what I mean:
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From ggreif at gmail.com  Tue Mar 23 17:33:36 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 23 Mar 2010 22:33:36 -0000
Subject: [llvm-commits] [test-suite] r99338 -
	/test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile
Message-ID: <20100323223336.BD3612A6C12C@llvm.org>

Author: ggreif
Date: Tue Mar 23 17:33:36 2010
New Revision: 99338

URL: http://llvm.org/viewvc/llvm-project?rev=99338&view=rev
Log:
back out my last change, seems to break nightlybot

Modified:
    test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile

Modified: test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile?rev=99338&r1=99337&r2=99338&view=diff
==============================================================================
--- test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile (original)
+++ test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile Tue Mar 23 17:33:36 2010
@@ -4,8 +4,8 @@
 CPPFLAGS += -DNOASM -DLLVM
 LDFLAGS = -lstdc++ -lm
 ifdef SMALL_PROBLEM_SIZE
-RUN_OPTIONS = -1 $(PROJ_SRC_ROOT)/MultiSource/Benchmarks/PAQ8p/file1.in
+RUN_OPTIONS = -1 file1.in
 else
-RUN_OPTIONS = -4 $(PROJ_SRC_ROOT)/MultiSource/Benchmarks/PAQ8p/file1.in
+RUN_OPTIONS = -4 file1.in
 endif
 include $(LEVEL)/MultiSource/Makefile.multisrc




From gohman at apple.com  Tue Mar 23 17:44:42 2010
From: gohman at apple.com (Dan Gohman)
Date: Tue, 23 Mar 2010 22:44:42 -0000
Subject: [llvm-commits] [llvm] r99339 - in /llvm/trunk:
 include/llvm/Target/TargetLowering.h
 lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Message-ID: <20100323224442.EAC5D2A6C12C@llvm.org>

Author: djg
Date: Tue Mar 23 17:44:42 2010
New Revision: 99339

URL: http://llvm.org/viewvc/llvm-project?rev=99339&view=rev
Log:
Revert 99335. getTypeToExpandTo's iterative behavior is actually
needed here.

Modified:
    llvm/trunk/include/llvm/Target/TargetLowering.h
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=99339&r1=99338&r2=99339&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Tue Mar 23 17:44:42 2010
@@ -268,6 +268,27 @@
     return MVT(MVT::Other); // Not reached
   }
 
+  /// getTypeToExpandTo - For types supported by the target, this is an
+  /// identity function.  For types that must be expanded (i.e. integer types
+  /// that are larger than the largest integer register or illegal floating
+  /// point types), this returns the largest legal type it will be expanded to.
+  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
+    assert(!VT.isVector());
+    while (true) {
+      switch (getTypeAction(Context, VT)) {
+      case Legal:
+        return VT;
+      case Expand:
+        VT = getTypeToTransformTo(Context, VT);
+        break;
+      default:
+        assert(false && "Type is not legal nor is it to be expanded!");
+        return VT;
+      }
+    }
+    return VT;
+  }
+
   /// getVectorTypeBreakdown - Vector types are broken down into some number of
   /// legal first class types.  For example, EVT::v8f32 maps to 2 EVT::v4f32
   /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=99339&r1=99338&r2=99339&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Mar 23 17:44:42 2010
@@ -1021,7 +1021,7 @@
       Hi = InL;
     } else if (Amt == 1 &&
                TLI.isOperationLegalOrCustom(ISD::ADDC,
-                                            TLI.getTypeToTransformTo(*DAG.getContext(), NVT))) {
+                                            TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
       // Emit this X << 1 as X+X.
       SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
       SDValue LoOps[2] = { InL, InL };
@@ -1263,8 +1263,7 @@
   bool hasCarry =
     TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
                                    ISD::ADDC : ISD::SUBC,
-                                 TLI.getTypeToTransformTo(*DAG.getContext(),
-                                                          NVT));
+                                 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
 
   if (hasCarry) {
     SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);




From isanbard at gmail.com  Tue Mar 23 17:49:38 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 23 Mar 2010 22:49:38 -0000
Subject: [llvm-commits] [test-suite] r99340 -
	/test-suite/trunk/TEST.m2regllcdbg.Makefile
Message-ID: <20100323224938.231E12A6C12C@llvm.org>

Author: void
Date: Tue Mar 23 17:49:37 2010
New Revision: 99340

URL: http://llvm.org/viewvc/llvm-project?rev=99340&view=rev
Log:
Don't remove this comment. It could cover up a real bug.

Modified:
    test-suite/trunk/TEST.m2regllcdbg.Makefile

Modified: test-suite/trunk/TEST.m2regllcdbg.Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/TEST.m2regllcdbg.Makefile?rev=99340&r1=99339&r2=99340&view=diff
==============================================================================
--- test-suite/trunk/TEST.m2regllcdbg.Makefile (original)
+++ test-suite/trunk/TEST.m2regllcdbg.Makefile Tue Mar 23 17:49:37 2010
@@ -32,7 +32,7 @@
 	$(LLC) $(LLC_DEBUG_FLAGS) $< -f -o $@
 
 Output/%.first.s: Output/%.t1c.s Output/.dir $(LLC)
-	grep -v '\.long' < $< | grep -v '\.byte' | grep -v '\.short' | grep -v '\.asci' | grep -v '\.quad' | grep -v '## DW_AT' | grep -v '## Abbrev' | grep -v '## End Of Children' | grep -v '## DIE' | grep -v '## $$' | grep -v '^#.*' | grep -v '^$$' | sed -e 's,## %._crit_edge[0-9]*,##,' > $@
+	grep -v '\.long' < $< | grep -v '\.byte' | grep -v '\.short' | grep -v '\.asci' | grep -v '\.quad' | grep -v '## DW_AT' | grep -v '## Abbrev' | grep -v '## End Of Children' | grep -v '## DIE' | grep -v '## $$' | grep -v '^#.*' | grep -v '^$$' > $@
 
 Output/%.t2a.bc: Output/%.linked.rbc Output/.dir $(LOPT)
 	$(LOPT) -strip-nondebug $< -f -o $@
@@ -44,7 +44,7 @@
 	$(LLC) $(LLC_DEBUG_FLAGS) $< -f -o $@
 
 Output/%.second.s: Output/%.t2c.s Output/.dir
-	grep -v DEBUG_VALUE < $< | grep -v '\.long' | grep -v '\.byte' | grep -v '\.short' | grep -v '\.asci' | grep -v '## DW_AT' | grep -v '## Abbrev' |  grep -v '## End Of Children' | grep -v '## DIE' | grep -v '## $$' | grep -v '\.quad' | grep -v '^#' | grep -v '^$$' | sed -e 's,## %._crit_edge[0-9]*,##,' > $@
+	grep -v DEBUG_VALUE < $< | grep -v '\.long' | grep -v '\.byte' | grep -v '\.short' | grep -v '\.asci' | grep -v '## DW_AT' | grep -v '## Abbrev' |  grep -v '## End Of Children' | grep -v '## DIE' | grep -v '## $$' | grep -v '\.quad' | grep -v '^#' | grep -v '^$$' > $@
 
 Output/%.diff: Output/%.first.s Output/%.second.s
 	@-if diff $^ > $@; then \




From sabre at nondot.org  Tue Mar 23 17:59:07 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 23 Mar 2010 22:59:07 -0000
Subject: [llvm-commits] [llvm] r99341 - in /llvm/trunk:
 include/llvm/Instructions.h include/llvm/Support/CallSite.h
 lib/Transforms/Utils/InlineFunction.cpp lib/VMCore/Instructions.cpp
 test/Transforms/Inline/noinline.ll
Message-ID: <20100323225907.A1BAD2A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 17:59:07 2010
New Revision: 99341

URL: http://llvm.org/viewvc/llvm-project?rev=99341&view=rev
Log:
add some accessors to callsite/callinst/invokeinst to check
for the noinline attribute, and make the inliner refuse to
inline a call site when the call site is marked noinline even
if the callee isn't.  This fixes PR6682.

Added:
    llvm/trunk/test/Transforms/Inline/noinline.ll
Modified:
    llvm/trunk/include/llvm/Instructions.h
    llvm/trunk/include/llvm/Support/CallSite.h
    llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
    llvm/trunk/lib/VMCore/Instructions.cpp

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=99341&r1=99340&r2=99341&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Tue Mar 23 17:59:07 2010
@@ -971,6 +971,13 @@
   unsigned getParamAlignment(unsigned i) const {
     return AttributeList.getParamAlignment(i);
   }
+  
+  /// @brief Return true if the call should not be inlined.
+  bool isNoInline() const { return paramHasAttr(~0, Attribute::NoInline); }
+  void setIsNoInline(bool Value) {
+    if (Value) addAttribute(~0, Attribute::NoInline);
+    else removeAttribute(~0, Attribute::NoInline);
+  }
 
   /// @brief Determine if the call does not access memory.
   bool doesNotAccessMemory() const {
@@ -2456,6 +2463,13 @@
     return AttributeList.getParamAlignment(i);
   }
 
+  /// @brief Return true if the call should not be inlined.
+  bool isNoInline() const { return paramHasAttr(~0, Attribute::NoInline); }
+  void setIsNoInline(bool Value) {
+    if (Value) addAttribute(~0, Attribute::NoInline);
+    else removeAttribute(~0, Attribute::NoInline);
+  }
+  
   /// @brief Determine if the call does not access memory.
   bool doesNotAccessMemory() const {
     return paramHasAttr(~0, Attribute::ReadNone);

Modified: llvm/trunk/include/llvm/Support/CallSite.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=99341&r1=99340&r2=99341&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CallSite.h (original)
+++ llvm/trunk/include/llvm/Support/CallSite.h Tue Mar 23 17:59:07 2010
@@ -76,6 +76,10 @@
   /// @brief Extract the alignment for a call or parameter (0=unknown).
   uint16_t getParamAlignment(uint16_t i) const;
 
+  /// @brief Return true if the call should not be inlined.
+  bool isNoInline() const;
+  void setIsNoInline(bool Value = true);
+  
   /// @brief Determine if the call does not access memory.
   bool doesNotAccessMemory() const;
   void setDoesNotAccessMemory(bool doesNotAccessMemory = true);

Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=99341&r1=99340&r2=99341&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Tue Mar 23 17:59:07 2010
@@ -229,7 +229,9 @@
   const Function *CalledFunc = CS.getCalledFunction();
   if (CalledFunc == 0 ||          // Can't inline external function or indirect
       CalledFunc->isDeclaration() || // call, or call to a vararg function!
-      CalledFunc->getFunctionType()->isVarArg()) return false;
+      CalledFunc->getFunctionType()->isVarArg() ||
+      CS.isNoInline())            // Call site is marked noinline.
+    return false;
 
 
   // If the call to the callee is not a tail call, we must clear the 'tail'

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=99341&r1=99340&r2=99341&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Tue Mar 23 17:59:07 2010
@@ -31,13 +31,13 @@
 //===----------------------------------------------------------------------===//
 
 #define CALLSITE_DELEGATE_GETTER(METHOD) \
-  Instruction *II(getInstruction());     \
+  Instruction *II = getInstruction();    \
   return isCall()                        \
     ? cast<CallInst>(II)->METHOD         \
     : cast<InvokeInst>(II)->METHOD
 
 #define CALLSITE_DELEGATE_SETTER(METHOD) \
-  Instruction *II(getInstruction());     \
+  Instruction *II = getInstruction();    \
   if (isCall())                          \
     cast<CallInst>(II)->METHOD;          \
   else                                   \
@@ -66,6 +66,17 @@
 uint16_t CallSite::getParamAlignment(uint16_t i) const {
   CALLSITE_DELEGATE_GETTER(getParamAlignment(i));
 }
+
+/// @brief Return true if the call should not be inlined.
+bool CallSite::isNoInline() const {
+  CALLSITE_DELEGATE_GETTER(isNoInline());
+}
+
+void CallSite::setIsNoInline(bool Value) {
+  CALLSITE_DELEGATE_GETTER(setIsNoInline(Value));
+}
+
+
 bool CallSite::doesNotAccessMemory() const {
   CALLSITE_DELEGATE_GETTER(doesNotAccessMemory());
 }

Added: llvm/trunk/test/Transforms/Inline/noinline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/noinline.ll?rev=99341&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/Inline/noinline.ll (added)
+++ llvm/trunk/test/Transforms/Inline/noinline.ll Tue Mar 23 17:59:07 2010
@@ -0,0 +1,18 @@
+; RUN: opt %s -inline -S | FileCheck %s
+; PR6682
+declare void @foo() nounwind
+
+define void @bar() nounwind {
+entry:
+    tail call void @foo() nounwind
+    ret void
+}
+
+define void @bazz() nounwind {
+entry:
+    tail call void @bar() nounwind noinline
+    ret void
+}
+
+; CHECK: define void @bazz()
+; CHECK: call void @bar()




From clattner at apple.com  Tue Mar 23 18:01:36 2010
From: clattner at apple.com (Chris Lattner)
Date: Tue, 23 Mar 2010 16:01:36 -0700
Subject: [llvm-commits] [test-suite] r99329 -
	/test-suite/trunk/TEST.m2regllcdbg.Makefile
In-Reply-To: <CF5E4DD6-7B2F-4FC1-B397-0F536D29FB81@gmail.com>
References: <20100323213636.66A6E2A6C12C@llvm.org>
	<56A8637E-2A14-40F7-933D-9F72495E2548@apple.com>
	<CF5E4DD6-7B2F-4FC1-B397-0F536D29FB81@gmail.com>
Message-ID: <C87F8530-0CAF-4CA4-94C2-A8A1294F367F@apple.com>


On Mar 23, 2010, at 3:03 PM, Bill Wendling wrote:

> On Mar 23, 2010, at 2:41 PM, Chris Lattner wrote:
> 
>> On Mar 23, 2010, at 2:36 PM, Bill Wendling wrote:
>> 
>>> Author: void
>>> Date: Tue Mar 23 16:36:36 2010
>>> New Revision: 99329
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=99329&view=rev
>>> Log:
>>> Remove "crit_edge*" comments. These could change, but they don't effect code
>>> generation.
>> 
>> Are you checking the -fverbose-asm output or something or do these comments come out even when verbose-asm is disabled?  If they're coming out with verbose-asm off, we should fix that.
>> 
> This is the result of "llc", which has verbose-asm on by default as far as I can tell. We aren't checking the output of the comments in general. We do check them for DWARF debugging info, which is really only readable in comments. (That's my understanding. Devang can correct me if I'm wrong.)

Can you just disable verbose asm then?  Alternatively, just run through llvm-mc which will read the .s file then print it back out (without comments) to canonicalize it?

-Chris


From clattner at apple.com  Tue Mar 23 18:02:33 2010
From: clattner at apple.com (Chris Lattner)
Date: Tue, 23 Mar 2010 16:02:33 -0700
Subject: [llvm-commits] [test-suite] r99329 -
	/test-suite/trunk/TEST.m2regllcdbg.Makefile
In-Reply-To: <0EDCC3DA-845C-4CEE-A40E-29CAB69783B7@apple.com>
References: <20100323213636.66A6E2A6C12C@llvm.org>
	<0EDCC3DA-845C-4CEE-A40E-29CAB69783B7@apple.com>
Message-ID: <00117149-8412-405F-B6A7-840B77F01970@apple.com>


On Mar 23, 2010, at 3:26 PM, Dale Johannesen wrote:

> 
> On Mar 23, 2010, at 2:36 PMPDT, Bill Wendling wrote:
> 
>> Remove "crit_edge*" comments. These could change, but they don't effect code
>> generation.
> 
> The comments don't affect codegen, but the reason they change is that additional tmp symbols (a duplicate of some value that is already available elsewhere) are generated in one case.  It is true that some later pass clears up these dupes in all the examples I've looked at, so the only difference is the comments, but I'm unpersuaded this is always true, and I don't think this patch is a good idea.

Labels being different is different than comments being different.  I'd consider label differences, even if they are "L" labels to be a serious problem.

-Chris


From isanbard at gmail.com  Tue Mar 23 18:09:03 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 23 Mar 2010 23:09:03 -0000
Subject: [llvm-commits] [llvm] r99343 - /llvm/trunk/tools/Makefile
Message-ID: <20100323230904.045D72A6C12C@llvm.org>

Author: void
Date: Tue Mar 23 18:09:03 2010
New Revision: 99343

URL: http://llvm.org/viewvc/llvm-project?rev=99343&view=rev
Log:
Remove if DISABLED not if not DISABLED...

Modified:
    llvm/trunk/tools/Makefile

Modified: llvm/trunk/tools/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=99343&r1=99342&r2=99343&view=diff
==============================================================================
--- llvm/trunk/tools/Makefile (original)
+++ llvm/trunk/tools/Makefile Tue Mar 23 18:09:03 2010
@@ -54,7 +54,7 @@
 endif
 
 # Don't build edis if we explicitly disabled it.
-ifneq ($(DISABLE_EDIS),1)
+ifeq ($(DISABLE_EDIS),1)
   PARALLEL_DIRS := $(filter-out edis, $(PARALLEL_DIRS))
 endif
 




From johnny.chen at apple.com  Tue Mar 23 18:09:14 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 23 Mar 2010 23:09:14 -0000
Subject: [llvm-commits] [llvm] r99344 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20100323230914.E09F92A6C12C@llvm.org>

Author: johnny
Date: Tue Mar 23 18:09:14 2010
New Revision: 99344

URL: http://llvm.org/viewvc/llvm-project?rev=99344&view=rev
Log:
Renamed NVdImmFrm to N1RegModImmFrm.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99344&r1=99343&r2=99344&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 18:09:14 2010
@@ -60,7 +60,7 @@
 def ThumbMiscFrm  : Format<30>;
 
 def NLdStFrm                : Format<31>;
-def NVdImmFrm               : Format<32>;
+def N1RegModImmFrm          : Format<32>;
 def NVdVmImmFrm             : Format<33>;
 def NVdVmVCVTFrm            : Format<34>;
 
@@ -1538,7 +1538,7 @@
                dag oops, dag iops, InstrItinClass itin,
                string opc, string dt, string asm, string cstr,
                list<dag> pattern>
-  : NDataI<oops, iops, NVdImmFrm, itin, opc, dt, asm, cstr, pattern> {
+  : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
   let Inst{23} = op23;
   let Inst{21-19} = op21_19;
   let Inst{11-8} = op11_8;




From isanbard at gmail.com  Tue Mar 23 18:12:04 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 23 Mar 2010 16:12:04 -0700
Subject: [llvm-commits] [test-suite] r99329 -
	/test-suite/trunk/TEST.m2regllcdbg.Makefile
In-Reply-To: <0EDCC3DA-845C-4CEE-A40E-29CAB69783B7@apple.com>
References: <20100323213636.66A6E2A6C12C@llvm.org>
	<0EDCC3DA-845C-4CEE-A40E-29CAB69783B7@apple.com>
Message-ID: <61E4796F-82E3-44A2-AC34-24288C9DD4C3@gmail.com>

On Mar 23, 2010, at 3:26 PM, Dale Johannesen wrote:

> On Mar 23, 2010, at 2:36 PMPDT, Bill Wendling wrote:
> 
>> Remove "crit_edge*" comments. These could change, but they don't effect code
>> generation.
> 
> The comments don't affect codegen, but the reason they change is that additional tmp symbols (a duplicate of some value that is already available elsewhere) are generated in one case.  It is true that some later pass clears up these dupes in all the examples I've looked at, so the only difference is the comments, but I'm unpersuaded this is always true, and I don't think this patch is a good idea.
> 
Yeah. I agree. I went ahead and reverted the patch. I'll investigate why the extra temp is being created.

-bw





From isanbard at gmail.com  Tue Mar 23 18:14:03 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 23 Mar 2010 16:14:03 -0700
Subject: [llvm-commits] [test-suite] r99329 -
	/test-suite/trunk/TEST.m2regllcdbg.Makefile
In-Reply-To: <C87F8530-0CAF-4CA4-94C2-A8A1294F367F@apple.com>
References: <20100323213636.66A6E2A6C12C@llvm.org>
	<56A8637E-2A14-40F7-933D-9F72495E2548@apple.com>
	<CF5E4DD6-7B2F-4FC1-B397-0F536D29FB81@gmail.com>
	<C87F8530-0CAF-4CA4-94C2-A8A1294F367F@apple.com>
Message-ID: <EED9B41E-333F-4684-90AB-8AAC422D4C31@gmail.com>

On Mar 23, 2010, at 4:01 PM, Chris Lattner wrote:

> On Mar 23, 2010, at 3:03 PM, Bill Wendling wrote:
> 
>> On Mar 23, 2010, at 2:41 PM, Chris Lattner wrote:
>> 
>>> On Mar 23, 2010, at 2:36 PM, Bill Wendling wrote:
>>> 
>>>> Author: void
>>>> Date: Tue Mar 23 16:36:36 2010
>>>> New Revision: 99329
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=99329&view=rev
>>>> Log:
>>>> Remove "crit_edge*" comments. These could change, but they don't effect code
>>>> generation.
>>> 
>>> Are you checking the -fverbose-asm output or something or do these comments come out even when verbose-asm is disabled?  If they're coming out with verbose-asm off, we should fix that.
>>> 
>> This is the result of "llc", which has verbose-asm on by default as far as I can tell. We aren't checking the output of the comments in general. We do check them for DWARF debugging info, which is really only readable in comments. (That's my understanding. Devang can correct me if I'm wrong.)
> 
> Can you just disable verbose asm then?  Alternatively, just run through llvm-mc which will read the .s file then print it back out (without comments) to canonicalize it?
> 
As Dale mentioned, it could potentially hide code optimizations / generation that's behaving differently when debugging info is introduced. We don't need 100% compliance with comments, but there are some key things we should watch out for, it seems. And those are available only in comments (from what I understand).

-bw




From stoklund at 2pi.dk  Tue Mar 23 18:14:44 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 23 Mar 2010 23:14:44 -0000
Subject: [llvm-commits] [llvm] r99345 - in /llvm/trunk/lib/Target/X86:
 CMakeLists.txt SSEDomainFix.cpp X86.h X86InstrInfo.cpp X86InstrInfo.h
 X86TargetMachine.cpp X86TargetMachine.h
Message-ID: <20100323231444.97DDA2A6C12C@llvm.org>

Author: stoklund
Date: Tue Mar 23 18:14:44 2010
New Revision: 99345

URL: http://llvm.org/viewvc/llvm-project?rev=99345&view=rev
Log:
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.

This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.

Added:
    llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
Modified:
    llvm/trunk/lib/Target/X86/CMakeLists.txt
    llvm/trunk/lib/Target/X86/X86.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.h
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.h

Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=99345&r1=99344&r2=99345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/X86/CMakeLists.txt Tue Mar 23 18:14:44 2010
@@ -15,6 +15,7 @@
 tablegen(X86GenSubtarget.inc -gen-subtarget)
 
 set(sources
+  SSEDomainFix.cpp
   X86AsmBackend.cpp
   X86CodeEmitter.cpp
   X86COFFMachineModuleInfo.cpp

Added: llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/SSEDomainFix.cpp?rev=99345&view=auto
==============================================================================
--- llvm/trunk/lib/Target/X86/SSEDomainFix.cpp (added)
+++ llvm/trunk/lib/Target/X86/SSEDomainFix.cpp Tue Mar 23 18:14:44 2010
@@ -0,0 +1,536 @@
+//===- SSEDomainFix.cpp - Use proper int/float domain for SSE ---*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the SSEDomainFix pass.
+//
+// Some SSE instructions like mov, and, or, xor are available in different
+// variants for different operand types. These variant instructions are
+// equivalent, but on Nehalem and newer cpus there is extra latency
+// transferring data between integer and floating point domains.
+//
+// This pass changes the variant instructions to minimize domain crossings.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "sse-domain-fix"
+#include "X86InstrInfo.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/ADT/DepthFirstIterator.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+namespace {
+class SSEDomainFixPass : public MachineFunctionPass {
+  static char ID;
+  const X86InstrInfo *TII;
+
+  MachineFunction *MF;
+  MachineBasicBlock *MBB;
+public:
+  SSEDomainFixPass() : MachineFunctionPass(&ID) {}
+
+  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    AU.setPreservesAll();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  virtual bool runOnMachineFunction(MachineFunction &MF);
+
+  virtual const char *getPassName() const {
+    return "SSE execution domain fixup";
+  }
+
+private:
+  void enterBasicBlock(MachineBasicBlock *MBB);
+};
+}
+
+void SSEDomainFixPass::enterBasicBlock(MachineBasicBlock *mbb) {
+  MBB = mbb;
+  DEBUG(dbgs() << "Entering MBB " << MBB->getName() << "\n");
+}
+
+bool SSEDomainFixPass::runOnMachineFunction(MachineFunction &mf) {
+  MF = &mf;
+  TII = static_cast<const X86InstrInfo*>(MF->getTarget().getInstrInfo());
+
+  MachineBasicBlock *Entry = MF->begin();
+  SmallPtrSet<MachineBasicBlock*, 16> Visited;
+  for (df_ext_iterator<MachineBasicBlock*,
+         SmallPtrSet<MachineBasicBlock*, 16> >
+         DFI = df_ext_begin(Entry, Visited), DFE = df_ext_end(Entry, Visited);
+       DFI != DFE; ++DFI) {
+    enterBasicBlock(*DFI);
+    for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
+        ++I) {
+      MachineInstr *MI = I;
+      const unsigned *equiv = 0;
+      X86InstrInfo::SSEDomain domain = TII->GetSSEDomain(MI, equiv);
+      DEBUG(dbgs() << "isd-"[domain] << (equiv ? "* " : "  ") << *MI);
+    }
+  }
+  return false;
+}
+
+FunctionPass *llvm::createSSEDomainFixPass() {
+  return new SSEDomainFixPass();
+}
+
+// These are the replaceable instructions. Some of these have _Int variants
+// that we don't include here. We don't want to replace instructions selected
+// by intrinsics.
+static const unsigned ReplaceableInstrs[][3] = {
+  //PackedInt          PackedSingle     PackedDouble
+  { X86::MOVDQAmr,     X86::MOVAPSmr,   X86::MOVAPDmr   },
+  { X86::MOVDQArm,     X86::MOVAPSrm,   X86::MOVAPDrm   },
+  { X86::MOVDQArr,     X86::MOVAPSrr,   X86::MOVAPDrr   },
+  { X86::MOVDQUmr,     X86::MOVUPSmr,   X86::MOVUPDmr   },
+  { X86::MOVDQUrm,     X86::MOVUPSrm,   X86::MOVUPDrm   },
+  { X86::MOVNTDQmr,    X86::MOVNTPSmr,  X86::MOVNTPDmr  },
+  { X86::PANDNrm,      X86::ANDNPSrm,   X86::ANDNPDrm   },
+  { X86::PANDNrr,      X86::ANDNPSrr,   X86::ANDNPDrr   },
+  { X86::PANDrm,       X86::ANDPSrm,    X86::ANDPDrm    },
+  { X86::PANDrr,       X86::ANDPSrr,    X86::ANDPDrr    },
+  { X86::PORrm,        X86::ORPSrm,     X86::ORPDrm     },
+  { X86::PORrr,        X86::ORPSrr,     X86::ORPDrr     },
+  { X86::PUNPCKHQDQrm, X86::UNPCKHPSrm, X86::UNPCKHPDrm },
+  { X86::PUNPCKHQDQrr, X86::UNPCKHPSrr, X86::UNPCKHPDrr },
+  { X86::PUNPCKLQDQrm, X86::UNPCKLPSrm, X86::UNPCKLPDrm },
+  { X86::PUNPCKLQDQrr, X86::UNPCKLPSrr, X86::UNPCKLPDrr },
+  { X86::PXORrm,       X86::XORPSrm,    X86::XORPDrm    },
+  { X86::PXORrr,       X86::XORPSrr,    X86::XORPDrr    },
+};
+
+void X86InstrInfo::populateSSEInstrDomainTable() {
+  // Instructions that execute in the packed integer domain.
+  static const unsigned PackedIntInstrs[] = {
+    X86::LDDQUrm,
+    X86::MASKMOVDQU,
+    X86::MASKMOVDQU64,
+    X86::MOVDI2PDIrm,
+    X86::MOVDI2PDIrr,
+    X86::MOVDQUmr_Int,
+    X86::MOVDQUrm_Int,
+    X86::MOVLQ128mr,
+    X86::MOVNTDQArm,
+    X86::MOVNTDQmr_Int,
+    X86::MOVNTDQ_64mr,
+    X86::MOVPDI2DImr,
+    X86::MOVPDI2DIrr,
+    X86::MOVPQI2QImr,
+    X86::MOVPQIto64rr,
+    X86::MOVQI2PQIrm,
+    X86::MOVQxrxr,
+    X86::MOVZDI2PDIrm,
+    X86::MOVZDI2PDIrr,
+    X86::MOVZPQILo2PQIrm,
+    X86::MOVZPQILo2PQIrr,
+    X86::MOVZQI2PQIrm,
+    X86::MOVZQI2PQIrr,
+    X86::MPSADBWrmi,
+    X86::MPSADBWrri,
+    X86::PABSBrm128,
+    X86::PABSBrr128,
+    X86::PABSDrm128,
+    X86::PABSDrr128,
+    X86::PABSWrm128,
+    X86::PABSWrr128,
+    X86::PACKSSDWrm,
+    X86::PACKSSDWrr,
+    X86::PACKSSWBrm,
+    X86::PACKSSWBrr,
+    X86::PACKUSDWrm,
+    X86::PACKUSDWrr,
+    X86::PACKUSWBrm,
+    X86::PACKUSWBrr,
+    X86::PADDBrm,
+    X86::PADDBrr,
+    X86::PADDDrm,
+    X86::PADDDrr,
+    X86::PADDQrm,
+    X86::PADDQrr,
+    X86::PADDSBrm,
+    X86::PADDSBrr,
+    X86::PADDSWrm,
+    X86::PADDSWrr,
+    X86::PADDUSBrm,
+    X86::PADDUSBrr,
+    X86::PADDUSWrm,
+    X86::PADDUSWrr,
+    X86::PADDWrm,
+    X86::PADDWrr,
+    X86::PALIGNR128rm,
+    X86::PALIGNR128rr,
+    X86::PAVGBrm,
+    X86::PAVGBrr,
+    X86::PAVGWrm,
+    X86::PAVGWrr,
+    X86::PBLENDVBrm0,
+    X86::PBLENDVBrr0,
+    X86::PBLENDWrmi,
+    X86::PBLENDWrri,
+    X86::PCMPEQBrm,
+    X86::PCMPEQBrr,
+    X86::PCMPEQDrm,
+    X86::PCMPEQDrr,
+    X86::PCMPEQQrm,
+    X86::PCMPEQQrr,
+    X86::PCMPEQWrm,
+    X86::PCMPEQWrr,
+    X86::PCMPESTRIArm,
+    X86::PCMPESTRIArr,
+    X86::PCMPESTRICrm,
+    X86::PCMPESTRICrr,
+    X86::PCMPESTRIOrm,
+    X86::PCMPESTRIOrr,
+    X86::PCMPESTRIrm,
+    X86::PCMPESTRIrr,
+    X86::PCMPESTRISrm,
+    X86::PCMPESTRISrr,
+    X86::PCMPESTRIZrm,
+    X86::PCMPESTRIZrr,
+    X86::PCMPESTRM128MEM,
+    X86::PCMPESTRM128REG,
+    X86::PCMPESTRM128rm,
+    X86::PCMPESTRM128rr,
+    X86::PCMPGTBrm,
+    X86::PCMPGTBrr,
+    X86::PCMPGTDrm,
+    X86::PCMPGTDrr,
+    X86::PCMPGTQrm,
+    X86::PCMPGTQrr,
+    X86::PCMPGTWrm,
+    X86::PCMPGTWrr,
+    X86::PCMPISTRIArm,
+    X86::PCMPISTRIArr,
+    X86::PCMPISTRICrm,
+    X86::PCMPISTRICrr,
+    X86::PCMPISTRIOrm,
+    X86::PCMPISTRIOrr,
+    X86::PCMPISTRIrm,
+    X86::PCMPISTRIrr,
+    X86::PCMPISTRISrm,
+    X86::PCMPISTRISrr,
+    X86::PCMPISTRIZrm,
+    X86::PCMPISTRIZrr,
+    X86::PCMPISTRM128MEM,
+    X86::PCMPISTRM128REG,
+    X86::PCMPISTRM128rm,
+    X86::PCMPISTRM128rr,
+    X86::PEXTRBmr,
+    X86::PEXTRBrr,
+    X86::PEXTRDmr,
+    X86::PEXTRDrr,
+    X86::PEXTRQmr,
+    X86::PEXTRQrr,
+    X86::PEXTRWmr,
+    X86::PEXTRWri,
+    X86::PHADDDrm128,
+    X86::PHADDDrr128,
+    X86::PHADDSWrm128,
+    X86::PHADDSWrr128,
+    X86::PHADDWrm128,
+    X86::PHADDWrr128,
+    X86::PHMINPOSUWrm128,
+    X86::PHMINPOSUWrr128,
+    X86::PHSUBDrm128,
+    X86::PHSUBDrr128,
+    X86::PHSUBSWrm128,
+    X86::PHSUBSWrr128,
+    X86::PHSUBWrm128,
+    X86::PHSUBWrr128,
+    X86::PINSRBrm,
+    X86::PINSRBrr,
+    X86::PINSRDrm,
+    X86::PINSRDrr,
+    X86::PINSRQrm,
+    X86::PINSRQrr,
+    X86::PINSRWrmi,
+    X86::PINSRWrri,
+    X86::PMADDUBSWrm128,
+    X86::PMADDUBSWrr128,
+    X86::PMADDWDrm,
+    X86::PMADDWDrr,
+    X86::PMAXSBrm,
+    X86::PMAXSBrr,
+    X86::PMAXSDrm,
+    X86::PMAXSDrr,
+    X86::PMAXSWrm,
+    X86::PMAXSWrr,
+    X86::PMAXUBrm,
+    X86::PMAXUBrr,
+    X86::PMAXUDrm,
+    X86::PMAXUDrr,
+    X86::PMAXUWrm,
+    X86::PMAXUWrr,
+    X86::PMINSBrm,
+    X86::PMINSBrr,
+    X86::PMINSDrm,
+    X86::PMINSDrr,
+    X86::PMINSWrm,
+    X86::PMINSWrr,
+    X86::PMINUBrm,
+    X86::PMINUBrr,
+    X86::PMINUDrm,
+    X86::PMINUDrr,
+    X86::PMINUWrm,
+    X86::PMINUWrr,
+    X86::PMOVSXBDrm,
+    X86::PMOVSXBDrr,
+    X86::PMOVSXBQrm,
+    X86::PMOVSXBQrr,
+    X86::PMOVSXBWrm,
+    X86::PMOVSXBWrr,
+    X86::PMOVSXDQrm,
+    X86::PMOVSXDQrr,
+    X86::PMOVSXWDrm,
+    X86::PMOVSXWDrr,
+    X86::PMOVSXWQrm,
+    X86::PMOVSXWQrr,
+    X86::PMOVZXBDrm,
+    X86::PMOVZXBDrr,
+    X86::PMOVZXBQrm,
+    X86::PMOVZXBQrr,
+    X86::PMOVZXBWrm,
+    X86::PMOVZXBWrr,
+    X86::PMOVZXDQrm,
+    X86::PMOVZXDQrr,
+    X86::PMOVZXWDrm,
+    X86::PMOVZXWDrr,
+    X86::PMOVZXWQrm,
+    X86::PMOVZXWQrr,
+    X86::PMULDQrm,
+    X86::PMULDQrr,
+    X86::PMULHRSWrm128,
+    X86::PMULHRSWrr128,
+    X86::PMULHUWrm,
+    X86::PMULHUWrr,
+    X86::PMULHWrm,
+    X86::PMULHWrr,
+    X86::PMULLDrm,
+    X86::PMULLDrm_int,
+    X86::PMULLDrr,
+    X86::PMULLDrr_int,
+    X86::PMULLWrm,
+    X86::PMULLWrr,
+    X86::PMULUDQrm,
+    X86::PMULUDQrr,
+    X86::PSADBWrm,
+    X86::PSADBWrr,
+    X86::PSHUFBrm128,
+    X86::PSHUFBrr128,
+    X86::PSHUFHWmi,
+    X86::PSHUFHWri,
+    X86::PSHUFLWmi,
+    X86::PSHUFLWri,
+    X86::PSIGNBrm128,
+    X86::PSIGNBrr128,
+    X86::PSIGNDrm128,
+    X86::PSIGNDrr128,
+    X86::PSIGNWrm128,
+    X86::PSIGNWrr128,
+    X86::PSLLDQri,
+    X86::PSLLDri,
+    X86::PSLLDrm,
+    X86::PSLLDrr,
+    X86::PSLLQri,
+    X86::PSLLQrm,
+    X86::PSLLQrr,
+    X86::PSLLWri,
+    X86::PSLLWrm,
+    X86::PSLLWrr,
+    X86::PSRADri,
+    X86::PSRADrm,
+    X86::PSRADrr,
+    X86::PSRAWri,
+    X86::PSRAWrm,
+    X86::PSRAWrr,
+    X86::PSRLDQri,
+    X86::PSRLDri,
+    X86::PSRLDrm,
+    X86::PSRLDrr,
+    X86::PSRLQri,
+    X86::PSRLQrm,
+    X86::PSRLQrr,
+    X86::PSRLWri,
+    X86::PSRLWrm,
+    X86::PSRLWrr,
+    X86::PSUBBrm,
+    X86::PSUBBrr,
+    X86::PSUBDrm,
+    X86::PSUBDrr,
+    X86::PSUBQrm,
+    X86::PSUBQrr,
+    X86::PSUBSBrm,
+    X86::PSUBSBrr,
+    X86::PSUBSWrm,
+    X86::PSUBSWrr,
+    X86::PSUBUSBrm,
+    X86::PSUBUSBrr,
+    X86::PSUBUSWrm,
+    X86::PSUBUSWrr,
+    X86::PSUBWrm,
+    X86::PSUBWrr,
+    X86::PUNPCKHBWrm,
+    X86::PUNPCKHBWrr,
+    X86::PUNPCKHWDrm,
+    X86::PUNPCKHWDrr,
+    X86::PUNPCKLBWrm,
+    X86::PUNPCKLBWrr,
+    X86::PUNPCKLWDrm,
+    X86::PUNPCKLWDrr,
+  };
+
+  // Instructions that execute in the packed single domain.
+  static const unsigned PackedSingleInstrs[] = {
+    X86::ADDPSrm,
+    X86::ADDPSrr,
+    X86::ADDSUBPSrm,
+    X86::ADDSUBPSrr,
+    X86::BLENDPSrmi,
+    X86::BLENDPSrri,
+    X86::BLENDVPSrm0,
+    X86::BLENDVPSrr0,
+    X86::CMPPSrmi,
+    X86::CMPPSrri,
+    X86::DIVPSrm,
+    X86::DIVPSrr,
+    X86::DPPSrmi,
+    X86::DPPSrri,
+    X86::EXTRACTPSmr,
+    X86::EXTRACTPSrr,
+    X86::HADDPSrm,
+    X86::HADDPSrr,
+    X86::HSUBPSrm,
+    X86::HSUBPSrr,
+    X86::INSERTPSrm,
+    X86::INSERTPSrr,
+    X86::MAXPSrm,
+    X86::MAXPSrm_Int,
+    X86::MAXPSrr,
+    X86::MAXPSrr_Int,
+    X86::MINPSrm,
+    X86::MINPSrm_Int,
+    X86::MINPSrr,
+    X86::MINPSrr_Int,
+    X86::MOVHLPSrr,
+    X86::MOVHPSmr,
+    X86::MOVHPSrm,
+    X86::MOVLHPSrr,
+    X86::MOVLPSmr,
+    X86::MOVLPSrm,
+    X86::MOVMSKPSrr,
+    X86::MOVNTPSmr_Int,
+    X86::MOVSHDUPrm,
+    X86::MOVSHDUPrr,
+    X86::MOVSLDUPrm,
+    X86::MOVSLDUPrr,
+    X86::MOVUPSmr_Int,
+    X86::MOVUPSrm_Int,
+    X86::MULPSrm,
+    X86::MULPSrr,
+    X86::RCPPSm,
+    X86::RCPPSm_Int,
+    X86::RCPPSr,
+    X86::RCPPSr_Int,
+    X86::ROUNDPSm_Int,
+    X86::ROUNDPSr_Int,
+    X86::RSQRTPSm,
+    X86::RSQRTPSm_Int,
+    X86::RSQRTPSr,
+    X86::RSQRTPSr_Int,
+    X86::SQRTPSm,
+    X86::SQRTPSm_Int,
+    X86::SQRTPSr,
+    X86::SQRTPSr_Int,
+    X86::SUBPSrm,
+    X86::SUBPSrr,
+  };
+
+  // Instructions that execute in the packed double domain.
+  static const unsigned PackedDoubleInstrs[] = {
+    X86::ADDPDrm,
+    X86::ADDPDrr,
+    X86::ADDSUBPDrm,
+    X86::ADDSUBPDrr,
+    X86::BLENDPDrmi,
+    X86::BLENDPDrri,
+    X86::BLENDVPDrm0,
+    X86::BLENDVPDrr0,
+    X86::CMPPDrmi,
+    X86::CMPPDrri,
+    X86::DIVPDrm,
+    X86::DIVPDrr,
+    X86::DPPDrmi,
+    X86::DPPDrri,
+    X86::HADDPDrm,
+    X86::HADDPDrr,
+    X86::HSUBPDrm,
+    X86::HSUBPDrr,
+    X86::MAXPDrm,
+    X86::MAXPDrm_Int,
+    X86::MAXPDrr,
+    X86::MAXPDrr_Int,
+    X86::MINPDrm,
+    X86::MINPDrm_Int,
+    X86::MINPDrr,
+    X86::MINPDrr_Int,
+    X86::MOVHPDmr,
+    X86::MOVHPDrm,
+    X86::MOVLPDmr,
+    X86::MOVLPDrm,
+    X86::MOVMSKPDrr,
+    X86::MOVNTPDmr_Int,
+    X86::MOVUPDmr_Int,
+    X86::MOVUPDrm_Int,
+    X86::MULPDrm,
+    X86::MULPDrr,
+    X86::ROUNDPDm_Int,
+    X86::ROUNDPDr_Int,
+    X86::SQRTPDm,
+    X86::SQRTPDm_Int,
+    X86::SQRTPDr,
+    X86::SQRTPDr_Int,
+    X86::SUBPDrm,
+    X86::SUBPDrr,
+  };
+
+  // Add non-negative entries for forcing instructions.
+  for (unsigned i = 0, e = array_lengthof(PackedIntInstrs); i != e; ++i)
+    SSEInstrDomainTable.insert(std::make_pair(PackedIntInstrs[i],
+                                              PackedInt));
+  for (unsigned i = 0, e = array_lengthof(PackedSingleInstrs); i != e; ++i)
+    SSEInstrDomainTable.insert(std::make_pair(PackedSingleInstrs[i],
+                                              PackedSingle));
+  for (unsigned i = 0, e = array_lengthof(PackedDoubleInstrs); i != e; ++i)
+    SSEInstrDomainTable.insert(std::make_pair(PackedDoubleInstrs[i],
+                                              PackedDouble));
+
+  // Add row number + 1 for replaceable instructions.
+  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
+    for (unsigned c = 0; c != 3; ++c)
+    SSEInstrDomainTable.insert(std::make_pair(ReplaceableInstrs[i][c],
+                                              c + 4*(i+1)));
+}
+
+X86InstrInfo::SSEDomain X86InstrInfo::GetSSEDomain(const MachineInstr *MI,
+                                                 const unsigned *&equiv) const {
+  DenseMap<unsigned,unsigned>::const_iterator i =
+    SSEInstrDomainTable.find(MI->getOpcode());
+  if (i == SSEInstrDomainTable.end())
+    return NotSSEDomain;
+  unsigned value = i->second;
+  if (value/4)
+    equiv = ReplaceableInstrs[value/4 - 1];
+  else
+    equiv = 0;
+  return SSEDomain(value & 3);
+}

Modified: llvm/trunk/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=99345&r1=99344&r2=99345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.h (original)
+++ llvm/trunk/lib/Target/X86/X86.h Tue Mar 23 18:14:44 2010
@@ -41,6 +41,10 @@
 ///
 FunctionPass *createX86FloatingPointStackifierPass();
 
+/// createSSEDomainFixPass - This pass twiddles SSE opcodes to prevent domain
+/// crossings.
+FunctionPass *createSSEDomainFixPass();
+
 /// createX87FPRegKillInserterPass - This function returns a pass which
 /// inserts FP_REG_KILL instructions where needed.
 ///

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=99345&r1=99344&r2=99345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Mar 23 18:14:44 2010
@@ -665,6 +665,9 @@
 
   // Remove ambiguous entries.
   assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
+
+  if (TM.getSubtarget<X86Subtarget>().hasSSE2())
+    populateSSEInstrDomainTable();
 }
 
 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=99345&r1=99344&r2=99345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Tue Mar 23 18:14:44 2010
@@ -486,6 +486,9 @@
   /// MemOp2RegOpTable - Load / store unfolding opcode map.
   ///
   DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
+
+  /// SSEInstrDomainTable - Map SSE opcodes to execution domain info.
+  DenseMap<unsigned, unsigned> SSEInstrDomainTable;
   
 public:
   explicit X86InstrInfo(X86TargetMachine &tm);
@@ -716,6 +719,14 @@
   ///
   unsigned getGlobalBaseReg(MachineFunction *MF) const;
 
+  /// Some SSE instructions come in variants for three domains.
+  enum SSEDomain { PackedInt, PackedSingle, PackedDouble, NotSSEDomain };
+
+  /// GetSSEDomain - Return the SSE execution domain of MI, or NotSSEDomain for
+  /// unknown instructions. If the instruction has equivalents for other domain,
+  /// equiv points to a list of opcodes index by domain.
+  SSEDomain GetSSEDomain(const MachineInstr *MI, const unsigned *&equiv) const;
+
 private:
   MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
                                               MachineFunction::iterator &MFI,
@@ -732,6 +743,9 @@
   /// operand and follow operands form a reference to the stack frame.
   bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
                       int &FrameIndex) const;
+
+  // Implemented in SSEDomainFix.cpp
+  void populateSSEInstrDomainTable();
 };
 
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=99345&r1=99344&r2=99345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Tue Mar 23 18:14:44 2010
@@ -17,11 +17,17 @@
 #include "llvm/PassManager.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/Passes.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetRegistry.h"
 using namespace llvm;
 
+static cl::opt<bool>
+SSEDomainFix("sse-domain-fix",
+               cl::desc("Enable fixing of SSE execution domain"),
+               cl::init(false), cl::Hidden);
+
 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
   Triple TheTriple(TT);
   switch (TheTriple.getOS()) {
@@ -169,6 +175,15 @@
   return true;  // -print-machineinstr should print after this.
 }
 
+bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM,
+                                      CodeGenOpt::Level OptLevel) {
+  if (SSEDomainFix && OptLevel != CodeGenOpt::None && Subtarget.hasSSE2()) {
+    PM.add(createSSEDomainFixPass());
+    return true;
+  }
+  return false;
+}
+
 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
                                       CodeGenOpt::Level OptLevel,
                                       JITCodeEmitter &JCE) {

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=99345&r1=99344&r2=99345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Tue Mar 23 18:14:44 2010
@@ -66,6 +66,7 @@
   virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
   virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
   virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
                               JITCodeEmitter &JCE);
 };




From clattner at apple.com  Tue Mar 23 18:15:54 2010
From: clattner at apple.com (Chris Lattner)
Date: Tue, 23 Mar 2010 16:15:54 -0700
Subject: [llvm-commits] [test-suite] r99329 -
	/test-suite/trunk/TEST.m2regllcdbg.Makefile
In-Reply-To: <EED9B41E-333F-4684-90AB-8AAC422D4C31@gmail.com>
References: <20100323213636.66A6E2A6C12C@llvm.org>
	<56A8637E-2A14-40F7-933D-9F72495E2548@apple.com>
	<CF5E4DD6-7B2F-4FC1-B397-0F536D29FB81@gmail.com>
	<C87F8530-0CAF-4CA4-94C2-A8A1294F367F@apple.com>
	<EED9B41E-333F-4684-90AB-8AAC422D4C31@gmail.com>
Message-ID: <E0323660-7FA9-4CAD-9D7E-78EC0B1ABA2D@apple.com>


On Mar 23, 2010, at 4:14 PM, Bill Wendling wrote:

>>> 
>>> This is the result of "llc", which has verbose-asm on by default as far as I can tell. We aren't checking the output of the comments in general. We do check them for DWARF debugging info, which is really only readable in comments. (That's my understanding. Devang can correct me if I'm wrong.)
>> 
>> Can you just disable verbose asm then?  Alternatively, just run through llvm-mc which will read the .s file then print it back out (without comments) to canonicalize it?
>> 
> As Dale mentioned, it could potentially hide code optimizations / generation that's behaving differently when debugging info is introduced. We don't need 100% compliance with comments, but there are some key things we should watch out for, it seems. And those are available only in comments (from what I understand).

Your guys' call, do whichever you prefer.

-Chris


From clattner at apple.com  Tue Mar 23 18:17:07 2010
From: clattner at apple.com (Chris Lattner)
Date: Tue, 23 Mar 2010 16:17:07 -0700
Subject: [llvm-commits] [llvm] r99345 - in /llvm/trunk/lib/Target/X86:
	CMakeLists.txt SSEDomainFix.cpp X86.h X86InstrInfo.cpp
	X86InstrInfo.h X86TargetMachine.cpp X86TargetMachine.h
In-Reply-To: <20100323231444.97DDA2A6C12C@llvm.org>
References: <20100323231444.97DDA2A6C12C@llvm.org>
Message-ID: <36283ED3-8DD2-4EA4-9B68-B486BD42DD0F@apple.com>


On Mar 23, 2010, at 4:14 PM, Jakob Stoklund Olesen wrote:

> Author: stoklund
> Date: Tue Mar 23 18:14:44 2010
> New Revision: 99345
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99345&view=rev
> Log:
> Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.
> 
> This is work in progress. So far, SSE execution domain tables are added to
> X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.

Cool, but:

> 
> +  static const unsigned PackedIntInstrs[] = {
> +    X86::LDDQUrm,
> +    X86::MASKMOVDQU,

Ewww...!

Can you add a bit to TargetInstrDesc::TSFlags so that this lives in the .td files?

-Chris




From sabre at nondot.org  Tue Mar 23 18:46:07 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 23 Mar 2010 23:46:07 -0000
Subject: [llvm-commits] [llvm] r99346 - in /llvm/trunk:
 include/llvm/Intrinsics.td include/llvm/IntrinsicsARM.td
 include/llvm/IntrinsicsPowerPC.td include/llvm/IntrinsicsX86.td
 lib/Target/Blackfin/BlackfinIntrinsics.td
 lib/Target/MBlaze/MBlazeIntrinsics.td
Message-ID: <20100323234607.44C202A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 18:46:07 2010
New Revision: 99346

URL: http://llvm.org/viewvc/llvm-project?rev=99346&view=rev
Log:
[llvm_void_ty] is no longer needed for result types, 
just use an empty result list.

Modified:
    llvm/trunk/include/llvm/Intrinsics.td
    llvm/trunk/include/llvm/IntrinsicsARM.td
    llvm/trunk/include/llvm/IntrinsicsPowerPC.td
    llvm/trunk/include/llvm/IntrinsicsX86.td
    llvm/trunk/lib/Target/Blackfin/BlackfinIntrinsics.td
    llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsics.td

Modified: llvm/trunk/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=99346&r1=99345&r2=99346&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/Intrinsics.td Tue Mar 23 18:46:07 2010
@@ -176,19 +176,19 @@
 //===--------------- Variable Argument Handling Intrinsics ----------------===//
 //
 
-def int_vastart : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [], "llvm.va_start">;
-def int_vacopy  : Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_ptr_ty], [],
+def int_vastart : Intrinsic<[], [llvm_ptr_ty], [], "llvm.va_start">;
+def int_vacopy  : Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], [],
                             "llvm.va_copy">;
-def int_vaend   : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [], "llvm.va_end">;
+def int_vaend   : Intrinsic<[], [llvm_ptr_ty], [], "llvm.va_end">;
 
 //===------------------- Garbage Collection Intrinsics --------------------===//
 //
-def int_gcroot  : Intrinsic<[llvm_void_ty],
+def int_gcroot  : Intrinsic<[],
                             [llvm_ptrptr_ty, llvm_ptr_ty]>;
 def int_gcread  : Intrinsic<[llvm_ptr_ty],
                             [llvm_ptr_ty, llvm_ptrptr_ty],
                             [IntrReadArgMem]>;
-def int_gcwrite : Intrinsic<[llvm_void_ty],
+def int_gcwrite : Intrinsic<[],
                             [llvm_ptr_ty, llvm_ptr_ty, llvm_ptrptr_ty],
                             [IntrWriteArgMem, NoCapture<1>, NoCapture<2>]>;
 
@@ -201,37 +201,37 @@
 // model their dependencies on allocas.
 def int_stacksave     : Intrinsic<[llvm_ptr_ty]>,
                         GCCBuiltin<"__builtin_stack_save">;
-def int_stackrestore  : Intrinsic<[llvm_void_ty], [llvm_ptr_ty]>,
+def int_stackrestore  : Intrinsic<[], [llvm_ptr_ty]>,
                         GCCBuiltin<"__builtin_stack_restore">;
 
 // IntrWriteArgMem is more pessimistic than strictly necessary for prefetch,
 // however it does conveniently prevent the prefetch from being reordered
 // with respect to nearby accesses to the same memory.
-def int_prefetch      : Intrinsic<[llvm_void_ty],
+def int_prefetch      : Intrinsic<[],
                                   [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
                                   [IntrWriteArgMem, NoCapture<0>]>;
-def int_pcmarker      : Intrinsic<[llvm_void_ty], [llvm_i32_ty]>;
+def int_pcmarker      : Intrinsic<[], [llvm_i32_ty]>;
 
 def int_readcyclecounter : Intrinsic<[llvm_i64_ty]>;
 
 // Stack Protector Intrinsic - The stackprotector intrinsic writes the stack
 // guard to the correct place on the stack frame.
-def int_stackprotector : Intrinsic<[llvm_void_ty],
+def int_stackprotector : Intrinsic<[],
                                    [llvm_ptr_ty, llvm_ptrptr_ty],
                                    [IntrWriteMem]>;
 
 //===------------------- Standard C Library Intrinsics --------------------===//
 //
 
-def int_memcpy  : Intrinsic<[llvm_void_ty],
+def int_memcpy  : Intrinsic<[],
                              [llvm_ptr_ty, llvm_ptr_ty, llvm_anyint_ty,
                               llvm_i32_ty],
                             [IntrWriteArgMem, NoCapture<0>, NoCapture<1>]>;
-def int_memmove : Intrinsic<[llvm_void_ty],
+def int_memmove : Intrinsic<[],
                             [llvm_ptr_ty, llvm_ptr_ty, llvm_anyint_ty,
                              llvm_i32_ty],
                             [IntrWriteArgMem, NoCapture<0>, NoCapture<1>]>;
-def int_memset  : Intrinsic<[llvm_void_ty],
+def int_memset  : Intrinsic<[],
                             [llvm_ptr_ty, llvm_i8_ty, llvm_anyint_ty,
                              llvm_i32_ty],
                             [IntrWriteArgMem, NoCapture<0>]>;
@@ -255,9 +255,9 @@
 
 // NOTE: these are internal interfaces.
 def int_setjmp     : Intrinsic<[llvm_i32_ty],  [llvm_ptr_ty]>;
-def int_longjmp    : Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_i32_ty]>;
+def int_longjmp    : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty]>;
 def int_sigsetjmp  : Intrinsic<[llvm_i32_ty] , [llvm_ptr_ty, llvm_i32_ty]>;
-def int_siglongjmp : Intrinsic<[llvm_void_ty], [llvm_ptr_ty, llvm_i32_ty]>;
+def int_siglongjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty]>;
 
 // Internal interface for object size checking
 def int_objectsize : Intrinsic<[llvm_anyint_ty], [llvm_ptr_ty, llvm_i1_ty],
@@ -282,9 +282,9 @@
 // optimizers can change them aggressively.  Special handling needed in a few
 // places.
 let Properties = [IntrNoMem] in {
-  def int_dbg_declare      : Intrinsic<[llvm_void_ty],
+  def int_dbg_declare      : Intrinsic<[],
                                        [llvm_metadata_ty, llvm_metadata_ty]>;
-  def int_dbg_value  	   : Intrinsic<[llvm_void_ty],
+  def int_dbg_value  	   : Intrinsic<[],
                                        [llvm_metadata_ty, llvm_i64_ty,
                                         llvm_metadata_ty]>;
 }
@@ -297,24 +297,24 @@
 
 def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
 
-def int_eh_return_i32 : Intrinsic<[llvm_void_ty], [llvm_i32_ty, llvm_ptr_ty]>;
-def int_eh_return_i64 : Intrinsic<[llvm_void_ty], [llvm_i64_ty, llvm_ptr_ty]>;
+def int_eh_return_i32 : Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty]>;
+def int_eh_return_i64 : Intrinsic<[], [llvm_i64_ty, llvm_ptr_ty]>;
 
-def int_eh_unwind_init: Intrinsic<[llvm_void_ty]>,
+def int_eh_unwind_init: Intrinsic<[]>,
                         GCCBuiltin<"__builtin_unwind_init">;
 
 def int_eh_dwarf_cfa  : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>;
 
 let Properties = [IntrNoMem] in {
   def int_eh_sjlj_setjmp  : Intrinsic<[llvm_i32_ty],  [llvm_ptr_ty]>;
-  def int_eh_sjlj_longjmp : Intrinsic<[llvm_void_ty], [llvm_ptr_ty]>;
+  def int_eh_sjlj_longjmp : Intrinsic<[], [llvm_ptr_ty]>;
   def int_eh_sjlj_lsda    : Intrinsic<[llvm_ptr_ty]>;
-  def int_eh_sjlj_callsite: Intrinsic<[llvm_void_ty], [llvm_i32_ty]>;
+  def int_eh_sjlj_callsite: Intrinsic<[], [llvm_i32_ty]>;
 }
 
 //===---------------- Generic Variable Attribute Intrinsics----------------===//
 //
-def int_var_annotation : Intrinsic<[llvm_void_ty],
+def int_var_annotation : Intrinsic<[],
                                    [llvm_ptr_ty, llvm_ptr_ty,
                                     llvm_ptr_ty, llvm_i32_ty],
                                    [], "llvm.var.annotation">;
@@ -361,7 +361,7 @@
 
 //===------------------------- Atomic Intrinsics --------------------------===//
 //
-def int_memory_barrier : Intrinsic<[llvm_void_ty],
+def int_memory_barrier : Intrinsic<[],
                                    [llvm_i1_ty, llvm_i1_ty,
                                     llvm_i1_ty, llvm_i1_ty, llvm_i1_ty], []>,
                                     GCCBuiltin<"__builtin_llvm_memory_barrier">;
@@ -429,16 +429,16 @@
 
 //===------------------------- Memory Use Markers -------------------------===//
 //
-def int_lifetime_start  : Intrinsic<[llvm_void_ty],
+def int_lifetime_start  : Intrinsic<[],
                                     [llvm_i64_ty, llvm_ptr_ty],
                                     [IntrWriteArgMem, NoCapture<1>]>;
-def int_lifetime_end    : Intrinsic<[llvm_void_ty],
+def int_lifetime_end    : Intrinsic<[],
                                     [llvm_i64_ty, llvm_ptr_ty],
                                     [IntrWriteArgMem, NoCapture<1>]>;
 def int_invariant_start : Intrinsic<[llvm_descriptor_ty],
                                     [llvm_i64_ty, llvm_ptr_ty],
                                     [IntrReadArgMem, NoCapture<1>]>;
-def int_invariant_end   : Intrinsic<[llvm_void_ty],
+def int_invariant_end   : Intrinsic<[],
                                     [llvm_descriptor_ty, llvm_i64_ty,
                                      llvm_ptr_ty],
                                     [IntrWriteArgMem, NoCapture<2>]>;
@@ -447,7 +447,7 @@
 //
 def int_flt_rounds : Intrinsic<[llvm_i32_ty]>,
                      GCCBuiltin<"__builtin_flt_rounds">;
-def int_trap : Intrinsic<[llvm_void_ty]>,
+def int_trap : Intrinsic<[]>,
                GCCBuiltin<"__builtin_trap">;
 
 // Intrisics to support half precision floating point format

Modified: llvm/trunk/include/llvm/IntrinsicsARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsARM.td?rev=99346&r1=99345&r2=99346&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsARM.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsARM.td Tue Mar 23 18:46:07 2010
@@ -344,31 +344,31 @@
                                         [IntrReadArgMem]>;
 
   // Interleaving vector stores from N-element structures.
-  def int_arm_neon_vst1 : Intrinsic<[llvm_void_ty],
+  def int_arm_neon_vst1 : Intrinsic<[],
                                     [llvm_ptr_ty, llvm_anyvector_ty],
                                     [IntrWriteArgMem]>;
-  def int_arm_neon_vst2 : Intrinsic<[llvm_void_ty],
+  def int_arm_neon_vst2 : Intrinsic<[],
                                     [llvm_ptr_ty, llvm_anyvector_ty,
                                      LLVMMatchType<0>], [IntrWriteArgMem]>;
-  def int_arm_neon_vst3 : Intrinsic<[llvm_void_ty],
+  def int_arm_neon_vst3 : Intrinsic<[],
                                     [llvm_ptr_ty, llvm_anyvector_ty,
                                      LLVMMatchType<0>, LLVMMatchType<0>],
                                      [IntrWriteArgMem]>;
-  def int_arm_neon_vst4 : Intrinsic<[llvm_void_ty],
+  def int_arm_neon_vst4 : Intrinsic<[],
                                     [llvm_ptr_ty, llvm_anyvector_ty,
                                      LLVMMatchType<0>, LLVMMatchType<0>,
                                      LLVMMatchType<0>], [IntrWriteArgMem]>;
 
   // Vector store N-element structure from one lane.
-  def int_arm_neon_vst2lane : Intrinsic<[llvm_void_ty],
+  def int_arm_neon_vst2lane : Intrinsic<[],
                                         [llvm_ptr_ty, llvm_anyvector_ty,
                                          LLVMMatchType<0>, llvm_i32_ty],
                                         [IntrWriteArgMem]>;
-  def int_arm_neon_vst3lane : Intrinsic<[llvm_void_ty],
+  def int_arm_neon_vst3lane : Intrinsic<[],
                                         [llvm_ptr_ty, llvm_anyvector_ty,
                                          LLVMMatchType<0>, LLVMMatchType<0>,
                                          llvm_i32_ty], [IntrWriteArgMem]>;
-  def int_arm_neon_vst4lane : Intrinsic<[llvm_void_ty],
+  def int_arm_neon_vst4lane : Intrinsic<[],
                                         [llvm_ptr_ty, llvm_anyvector_ty,
                                          LLVMMatchType<0>, LLVMMatchType<0>,
                                          LLVMMatchType<0>, llvm_i32_ty],

Modified: llvm/trunk/include/llvm/IntrinsicsPowerPC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsPowerPC.td?rev=99346&r1=99345&r2=99346&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsPowerPC.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsPowerPC.td Tue Mar 23 18:46:07 2010
@@ -18,17 +18,17 @@
 // Non-altivec intrinsics.
 let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   // dcba/dcbf/dcbi/dcbst/dcbt/dcbz/dcbzl(PPC970) instructions.
-  def int_ppc_dcba  : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbf  : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbi  : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbst : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbt  : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbtst: Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbz  : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>;
-  def int_ppc_dcbzl : Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>;
+  def int_ppc_dcba  : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
+  def int_ppc_dcbf  : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
+  def int_ppc_dcbi  : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
+  def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
+  def int_ppc_dcbt  : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
+  def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
+  def int_ppc_dcbz  : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
+  def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
 
   // sync instruction
-  def int_ppc_sync : Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>;
+  def int_ppc_sync : Intrinsic<[], [], [IntrWriteMem]>;
 }
 
 
@@ -86,23 +86,23 @@
 let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   // Data Stream Control.
   def int_ppc_altivec_dss : GCCBuiltin<"__builtin_altivec_dss">,
-              Intrinsic<[llvm_void_ty], [llvm_i32_ty], [IntrWriteMem]>;
+              Intrinsic<[], [llvm_i32_ty], [IntrWriteMem]>;
   def int_ppc_altivec_dssall : GCCBuiltin<"__builtin_altivec_dssall">,
-              Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>;
+              Intrinsic<[], [], [IntrWriteMem]>;
   def int_ppc_altivec_dst : GCCBuiltin<"__builtin_altivec_dst">,
-              Intrinsic<[llvm_void_ty],
+              Intrinsic<[],
                         [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
                         [IntrWriteMem]>;
   def int_ppc_altivec_dstt : GCCBuiltin<"__builtin_altivec_dstt">,
-              Intrinsic<[llvm_void_ty],
+              Intrinsic<[],
                         [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
                         [IntrWriteMem]>;
   def int_ppc_altivec_dstst : GCCBuiltin<"__builtin_altivec_dstst">,
-              Intrinsic<[llvm_void_ty],
+              Intrinsic<[],
                         [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
                         [IntrWriteMem]>;
   def int_ppc_altivec_dststt : GCCBuiltin<"__builtin_altivec_dststt">,
-              Intrinsic<[llvm_void_ty],
+              Intrinsic<[],
                         [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
                         [IntrWriteMem]>;
 
@@ -110,7 +110,7 @@
   def int_ppc_altivec_mfvscr : GCCBuiltin<"__builtin_altivec_mfvscr">,
               Intrinsic<[llvm_v8i16_ty], [], [IntrReadMem]>;
   def int_ppc_altivec_mtvscr : GCCBuiltin<"__builtin_altivec_mtvscr">,
-              Intrinsic<[llvm_void_ty], [llvm_v4i32_ty], [IntrWriteMem]>;
+              Intrinsic<[], [llvm_v4i32_ty], [IntrWriteMem]>;
 
 
   // Loads.  These don't map directly to GCC builtins because they represent the
@@ -129,19 +129,19 @@
   // Stores.  These don't map directly to GCC builtins because they represent the
   // source address with a single pointer.
   def int_ppc_altivec_stvx :
-              Intrinsic<[llvm_void_ty], [llvm_v4i32_ty, llvm_ptr_ty],
+              Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
   def int_ppc_altivec_stvxl :
-              Intrinsic<[llvm_void_ty], [llvm_v4i32_ty, llvm_ptr_ty],
+              Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
   def int_ppc_altivec_stvebx :
-              Intrinsic<[llvm_void_ty], [llvm_v16i8_ty, llvm_ptr_ty],
+              Intrinsic<[], [llvm_v16i8_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
   def int_ppc_altivec_stvehx :
-              Intrinsic<[llvm_void_ty], [llvm_v8i16_ty, llvm_ptr_ty],
+              Intrinsic<[], [llvm_v8i16_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
   def int_ppc_altivec_stvewx :
-              Intrinsic<[llvm_void_ty], [llvm_v4i32_ty, llvm_ptr_ty],
+              Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
 
   // Comparisons setting a vector.

Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=99346&r1=99345&r2=99346&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsX86.td Tue Mar 23 18:46:07 2010
@@ -142,25 +142,25 @@
 // SIMD store ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">,
-              Intrinsic<[llvm_void_ty], [llvm_ptr_ty,
+              Intrinsic<[], [llvm_ptr_ty,
                          llvm_v4f32_ty], [IntrWriteMem]>;
 }
 
 // Cacheability support ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">,
-              Intrinsic<[llvm_void_ty], [llvm_ptr_ty,
+              Intrinsic<[], [llvm_ptr_ty,
                          llvm_v4f32_ty], [IntrWriteMem]>;
   def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">,
-              Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>;
+              Intrinsic<[], [], [IntrWriteMem]>;
 }
 
 // Control register.
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse_stmxcsr :
-              Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>;
+              Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
   def int_x86_sse_ldmxcsr :
-              Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>;
+              Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
 }
 
 // Misc.
@@ -458,26 +458,26 @@
 // SIMD store ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">,
-              Intrinsic<[llvm_void_ty], [llvm_ptr_ty,
+              Intrinsic<[], [llvm_ptr_ty,
                          llvm_v2f64_ty], [IntrWriteMem]>;
   def int_x86_sse2_storeu_dq : GCCBuiltin<"__builtin_ia32_storedqu">,
-              Intrinsic<[llvm_void_ty], [llvm_ptr_ty,
+              Intrinsic<[], [llvm_ptr_ty,
                          llvm_v16i8_ty], [IntrWriteMem]>;
   def int_x86_sse2_storel_dq : GCCBuiltin<"__builtin_ia32_storelv4si">,
-              Intrinsic<[llvm_void_ty], [llvm_ptr_ty,
+              Intrinsic<[], [llvm_ptr_ty,
                          llvm_v4i32_ty], [IntrWriteMem]>;
 }
 
 // Cacheability support ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse2_movnt_dq : GCCBuiltin<"__builtin_ia32_movntdq">,
-              Intrinsic<[llvm_void_ty], [llvm_ptr_ty,
+              Intrinsic<[], [llvm_ptr_ty,
                          llvm_v2i64_ty], [IntrWriteMem]>;
   def int_x86_sse2_movnt_pd : GCCBuiltin<"__builtin_ia32_movntpd">,
-              Intrinsic<[llvm_void_ty], [llvm_ptr_ty,
+              Intrinsic<[], [llvm_ptr_ty,
                          llvm_v2f64_ty], [IntrWriteMem]>;
   def int_x86_sse2_movnt_i : GCCBuiltin<"__builtin_ia32_movnti">,
-              Intrinsic<[llvm_void_ty], [llvm_ptr_ty,
+              Intrinsic<[], [llvm_ptr_ty,
                          llvm_i32_ty], [IntrWriteMem]>;
 }
 
@@ -497,14 +497,14 @@
   def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">,
               Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
   def int_x86_sse2_maskmov_dqu : GCCBuiltin<"__builtin_ia32_maskmovdqu">,
-              Intrinsic<[llvm_void_ty], [llvm_v16i8_ty,
+              Intrinsic<[], [llvm_v16i8_ty,
                          llvm_v16i8_ty, llvm_ptr_ty], [IntrWriteMem]>;
   def int_x86_sse2_clflush : GCCBuiltin<"__builtin_ia32_clflush">,
-              Intrinsic<[llvm_void_ty], [llvm_ptr_ty], [IntrWriteMem]>;
+              Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
   def int_x86_sse2_lfence : GCCBuiltin<"__builtin_ia32_lfence">,
-              Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>;
+              Intrinsic<[], [], [IntrWriteMem]>;
   def int_x86_sse2_mfence : GCCBuiltin<"__builtin_ia32_mfence">,
-              Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>;
+              Intrinsic<[], [], [IntrWriteMem]>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -545,10 +545,10 @@
 // Thread synchronization ops.
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse3_monitor : GCCBuiltin<"__builtin_ia32_monitor">,
-              Intrinsic<[llvm_void_ty], [llvm_ptr_ty,
+              Intrinsic<[], [llvm_ptr_ty,
                          llvm_i32_ty, llvm_i32_ty], [IntrWriteMem]>;
   def int_x86_sse3_mwait : GCCBuiltin<"__builtin_ia32_mwait">,
-              Intrinsic<[llvm_void_ty], [llvm_i32_ty,
+              Intrinsic<[], [llvm_i32_ty,
                          llvm_i32_ty], [IntrWriteMem]>;
 }
 
@@ -973,9 +973,9 @@
 // Empty MMX state op.
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_mmx_emms  : GCCBuiltin<"__builtin_ia32_emms">,
-              Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>;
+              Intrinsic<[], [], [IntrWriteMem]>;
   def int_x86_mmx_femms : GCCBuiltin<"__builtin_ia32_femms">,
-              Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>;
+              Intrinsic<[], [], [IntrWriteMem]>;
 }
 
 // Integer arithmetic ops.
@@ -1151,7 +1151,7 @@
 // Misc.
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_mmx_maskmovq : GCCBuiltin<"__builtin_ia32_maskmovq">,
-              Intrinsic<[llvm_void_ty],
+              Intrinsic<[],
                         [llvm_v8i8_ty, llvm_v8i8_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
 
@@ -1159,6 +1159,6 @@
               Intrinsic<[llvm_i32_ty], [llvm_v8i8_ty], [IntrNoMem]>;
 
   def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">,
-              Intrinsic<[llvm_void_ty], [llvm_ptr_ty,
+              Intrinsic<[], [llvm_ptr_ty,
                          llvm_v1i64_ty], [IntrWriteMem]>;
 }

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinIntrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinIntrinsics.td?rev=99346&r1=99345&r2=99346&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinIntrinsics.td (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinIntrinsics.td Tue Mar 23 18:46:07 2010
@@ -21,14 +21,14 @@
 
 // Execute csync instruction with workarounds
 def int_bfin_csync : GCCBuiltin<"__builtin_bfin_csync">,
-        Intrinsic<[llvm_void_ty]>;
+        Intrinsic<[]>;
 
 // Execute ssync instruction with workarounds
 def int_bfin_ssync : GCCBuiltin<"__builtin_bfin_ssync">,
-        Intrinsic<[llvm_void_ty]>;
+        Intrinsic<[]>;
 
 // Execute idle instruction with workarounds
 def int_bfin_idle : GCCBuiltin<"__builtin_bfin_idle">,
-        Intrinsic<[llvm_void_ty]>;
+        Intrinsic<[]>;
 
 }

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsics.td?rev=99346&r1=99345&r2=99346&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsics.td (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsics.td Tue Mar 23 18:46:07 2010
@@ -21,11 +21,11 @@
                                         [llvm_i32_ty],
                                         [IntrWriteMem]>;
 
-  class MBFSL_Put_Intrinsic : Intrinsic<[llvm_void_ty],
+  class MBFSL_Put_Intrinsic : Intrinsic<[],
                                         [llvm_i32_ty, llvm_i32_ty],
                                         [IntrWriteMem]>;
 
-  class MBFSL_PutT_Intrinsic : Intrinsic<[llvm_void_ty],
+  class MBFSL_PutT_Intrinsic : Intrinsic<[],
                                          [llvm_i32_ty],
                                          [IntrWriteMem]>;
 }




From sabre at nondot.org  Tue Mar 23 18:46:27 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 23 Mar 2010 23:46:27 -0000
Subject: [llvm-commits] [llvm] r99347 -
	/llvm/trunk/utils/TableGen/CodeGenTarget.cpp
Message-ID: <20100323234627.5FE7C2A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 18:46:27 2010
New Revision: 99347

URL: http://llvm.org/viewvc/llvm-project?rev=99347&view=rev
Log:
reject void in intrinsic type lists.

Modified:
    llvm/trunk/utils/TableGen/CodeGenTarget.cpp

Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=99347&r1=99346&r2=99347&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Tue Mar 23 18:46:27 2010
@@ -488,18 +488,17 @@
     }
     if (EVT(VT).isOverloaded()) {
       OverloadedVTs.push_back(VT);
-      isOverloaded |= true;
+      isOverloaded = true;
     }
+
+    // Reject invalid types.
+    if (VT == MVT::isVoid)
+      throw "Intrinsic '" + DefName + " has void in result type list!";
     
     IS.RetVTs.push_back(VT);
     IS.RetTypeDefs.push_back(TyEl);
   }
   
-  if (IS.RetVTs.size() == 1 && IS.RetVTs[0] == MVT::isVoid) {
-    IS.RetVTs.pop_back();
-    IS.RetTypeDefs.pop_back();
-  }
-
   // Parse the list of parameter types.
   TypeList = R->getValueAsListInit("ParamTypes");
   for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
@@ -520,10 +519,16 @@
              "Expected iAny or vAny type");
     } else
       VT = getValueType(TyEl->getValueAsDef("VT"));
+    
     if (EVT(VT).isOverloaded()) {
       OverloadedVTs.push_back(VT);
-      isOverloaded |= true;
+      isOverloaded = true;
     }
+    
+    // Reject invalid types.
+    if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
+      throw "Intrinsic '" + DefName + " has void in result type list!";
+    
     IS.ParamVTs.push_back(VT);
     IS.ParamTypeDefs.push_back(TyEl);
   }




From daniel at zuster.org  Tue Mar 23 18:47:07 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 23 Mar 2010 23:47:07 -0000
Subject: [llvm-commits] [llvm] r99348 - /llvm/trunk/lib/MC/MCExpr.cpp
Message-ID: <20100323234708.048272A6C12C@llvm.org>

Author: ddunbar
Date: Tue Mar 23 18:47:07 2010
New Revision: 99348

URL: http://llvm.org/viewvc/llvm-project?rev=99348&view=rev
Log:
llvm-mc: Fast path EvaluateAbsolute of constants.

Modified:
    llvm/trunk/lib/MC/MCExpr.cpp

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=99348&r1=99347&r2=99348&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Tue Mar 23 18:47:07 2010
@@ -194,6 +194,12 @@
 bool MCExpr::EvaluateAsAbsolute(int64_t &Res, const MCAsmLayout *Layout) const {
   MCValue Value;
 
+  // Fast path constants.
+  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(this)) {
+    Res = CE->getValue();
+    return true;
+  }
+
   if (!EvaluateAsRelocatable(Value, Layout) || !Value.isAbsolute())
     return false;
 




From daniel at zuster.org  Tue Mar 23 18:47:12 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 23 Mar 2010 23:47:12 -0000
Subject: [llvm-commits] [llvm] r99349 - /llvm/trunk/tools/llvm-mc/llvm-mc.cpp
Message-ID: <20100323234712.D43DE2A6C12D@llvm.org>

Author: ddunbar
Date: Tue Mar 23 18:47:12 2010
New Revision: 99349

URL: http://llvm.org/viewvc/llvm-project?rev=99349&view=rev
Log:
llvm-mc: Support -filetype=null, for timing purposes.

Modified:
    llvm/trunk/tools/llvm-mc/llvm-mc.cpp

Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=99349&r1=99348&r2=99349&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Tue Mar 23 18:47:12 2010
@@ -56,6 +56,7 @@
                  cl::desc("Syntax variant to use for output printing"));
 
 enum OutputFileType {
+  OFT_Null,
   OFT_AssemblyFile,
   OFT_ObjectFile
 };
@@ -65,6 +66,8 @@
   cl::values(
        clEnumValN(OFT_AssemblyFile, "asm",
                   "Emit an assembly ('.s') file"),
+       clEnumValN(OFT_Null, "null",
+                  "Don't emit anything (for timing purposes)"),
        clEnumValN(OFT_ObjectFile, "obj",
                   "Emit a native object ('.o') file"),
        clEnumValEnd));
@@ -289,6 +292,8 @@
       CE.reset(TheTarget->createCodeEmitter(*TM, Ctx));
     Str.reset(createAsmStreamer(Ctx, *Out,TM->getTargetData()->isLittleEndian(),
                                 /*asmverbose*/true, IP, CE.get(), ShowInst));
+  } else if (FileType == OFT_Null) {
+    Str.reset(createNullStreamer(Ctx));
   } else {
     assert(FileType == OFT_ObjectFile && "Invalid file type!");
     CE.reset(TheTarget->createCodeEmitter(*TM, Ctx));




From daniel at zuster.org  Tue Mar 23 18:47:15 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 23 Mar 2010 23:47:15 -0000
Subject: [llvm-commits] [llvm] r99350 - in /llvm/trunk/lib/MC:
	MCAssembler.cpp MCExpr.cpp
Message-ID: <20100323234715.1C52A2A6C12E@llvm.org>

Author: ddunbar
Date: Tue Mar 23 18:47:14 2010
New Revision: 99350

URL: http://llvm.org/viewvc/llvm-project?rev=99350&view=rev
Log:
MC: Sprinkle in some more interesting statistics.

Modified:
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MCExpr.cpp

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99350&r1=99349&r2=99350&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Tue Mar 23 18:47:14 2010
@@ -28,7 +28,15 @@
 #include <vector>
 using namespace llvm;
 
+namespace {
+namespace stats {
+STATISTIC(RelaxedInstructions, "Number of relaxed instructions");
+STATISTIC(RelaxationSteps, "Number of assembler layout and relaxation steps");
 STATISTIC(EmittedFragments, "Number of emitted assembler fragments");
+STATISTIC(EvaluateFixup, "Number of evaluated fixups");
+STATISTIC(ObjectBytes, "Number of emitted object file bytes");
+}
+}
 
 // FIXME FIXME FIXME: There are number of places in this file where we convert
 // what is a 64-bit assembler value used for computation into a value in the
@@ -234,6 +242,8 @@
 bool MCAssembler::EvaluateFixup(const MCAsmLayout &Layout,
                                 const MCAsmFixup &Fixup, const MCFragment *DF,
                                 MCValue &Target, uint64_t &Value) const {
+  ++stats::EvaluateFixup;
+
   if (!Fixup.Value->EvaluateAsRelocatable(Target, &Layout))
     llvm_report_error("expected relocatable expression");
 
@@ -376,7 +386,7 @@
   uint64_t Start = OW->getStream().tell();
   (void) Start;
 
-  ++EmittedFragments;
+  ++stats::EmittedFragments;
 
   // FIXME: Embed in fragments instead?
   switch (F.getKind()) {
@@ -505,6 +515,7 @@
       llvm::errs() << "assembler backend - final-layout\n--\n";
       dump(); });
 
+  uint64_t StartOffset = OS.tell();
   llvm::OwningPtr<MCObjectWriter> Writer(getBackend().createObjectWriter(OS));
   if (!Writer)
     llvm_report_error("unable to create object writer!");
@@ -543,6 +554,8 @@
   // Write the object file.
   Writer->WriteObject(*this);
   OS.flush();
+
+  stats::ObjectBytes += OS.tell() - StartOffset;
 }
 
 bool MCAssembler::FixupNeedsRelaxation(const MCAsmFixup &Fixup,
@@ -575,6 +588,8 @@
 }
 
 bool MCAssembler::LayoutOnce(MCAsmLayout &Layout) {
+  ++stats::RelaxationSteps;
+
   // Layout the concrete sections and fragments.
   uint64_t Address = 0;
   MCSectionData *Prev = 0;
@@ -629,6 +644,8 @@
       if (!IF || !FragmentNeedsRelaxation(IF, Layout))
         continue;
 
+      ++stats::RelaxedInstructions;
+
       // FIXME-PERF: We could immediately lower out instructions if we can tell
       // they are fully resolved, to avoid retesting on later passes.
 

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=99350&r1=99349&r2=99350&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Tue Mar 23 18:47:14 2010
@@ -7,7 +7,9 @@
 //
 //===----------------------------------------------------------------------===//
 
+#define DEBUG_TYPE "mcexpr"
 #include "llvm/MC/MCExpr.h"
+#include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCAsmLayout.h"
 #include "llvm/MC/MCAssembler.h"
@@ -19,6 +21,12 @@
 #include "llvm/Target/TargetAsmBackend.h"
 using namespace llvm;
 
+namespace {
+namespace stats {
+STATISTIC(MCExprEvaluate, "Number of MCExpr evaluations");
+}
+}
+
 void MCExpr::print(raw_ostream &OS) const {
   switch (getKind()) {
   case MCExpr::Target:
@@ -231,6 +239,8 @@
 
 bool MCExpr::EvaluateAsRelocatable(MCValue &Res,
                                    const MCAsmLayout *Layout) const {
+  ++stats::MCExprEvaluate;
+
   switch (getKind()) {
   case Target:
     return cast<MCTargetExpr>(this)->EvaluateAsRelocatableImpl(Res, Layout);




From stoklund at 2pi.dk  Tue Mar 23 18:48:51 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 23 Mar 2010 23:48:51 -0000
Subject: [llvm-commits] [llvm] r99352 - in /llvm/trunk/lib/Target/X86:
 CMakeLists.txt SSEDomainFix.cpp X86.h X86InstrInfo.cpp X86InstrInfo.h
 X86TargetMachine.cpp X86TargetMachine.h
Message-ID: <20100323234852.110712A6C12C@llvm.org>

Author: stoklund
Date: Tue Mar 23 18:48:51 2010
New Revision: 99352

URL: http://llvm.org/viewvc/llvm-project?rev=99352&view=rev
Log:
Revert "Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings."

This reverts commit 99345. It was breaking buildbots.

Removed:
    llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
Modified:
    llvm/trunk/lib/Target/X86/CMakeLists.txt
    llvm/trunk/lib/Target/X86/X86.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.h
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.h

Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=99352&r1=99351&r2=99352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/X86/CMakeLists.txt Tue Mar 23 18:48:51 2010
@@ -15,7 +15,6 @@
 tablegen(X86GenSubtarget.inc -gen-subtarget)
 
 set(sources
-  SSEDomainFix.cpp
   X86AsmBackend.cpp
   X86CodeEmitter.cpp
   X86COFFMachineModuleInfo.cpp

Removed: llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/SSEDomainFix.cpp?rev=99351&view=auto
==============================================================================
--- llvm/trunk/lib/Target/X86/SSEDomainFix.cpp (original)
+++ llvm/trunk/lib/Target/X86/SSEDomainFix.cpp (removed)
@@ -1,536 +0,0 @@
-//===- SSEDomainFix.cpp - Use proper int/float domain for SSE ---*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the SSEDomainFix pass.
-//
-// Some SSE instructions like mov, and, or, xor are available in different
-// variants for different operand types. These variant instructions are
-// equivalent, but on Nehalem and newer cpus there is extra latency
-// transferring data between integer and floating point domains.
-//
-// This pass changes the variant instructions to minimize domain crossings.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "sse-domain-fix"
-#include "X86InstrInfo.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/ADT/DepthFirstIterator.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/raw_ostream.h"
-
-using namespace llvm;
-
-namespace {
-class SSEDomainFixPass : public MachineFunctionPass {
-  static char ID;
-  const X86InstrInfo *TII;
-
-  MachineFunction *MF;
-  MachineBasicBlock *MBB;
-public:
-  SSEDomainFixPass() : MachineFunctionPass(&ID) {}
-
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
-    AU.setPreservesAll();
-    MachineFunctionPass::getAnalysisUsage(AU);
-  }
-
-  virtual bool runOnMachineFunction(MachineFunction &MF);
-
-  virtual const char *getPassName() const {
-    return "SSE execution domain fixup";
-  }
-
-private:
-  void enterBasicBlock(MachineBasicBlock *MBB);
-};
-}
-
-void SSEDomainFixPass::enterBasicBlock(MachineBasicBlock *mbb) {
-  MBB = mbb;
-  DEBUG(dbgs() << "Entering MBB " << MBB->getName() << "\n");
-}
-
-bool SSEDomainFixPass::runOnMachineFunction(MachineFunction &mf) {
-  MF = &mf;
-  TII = static_cast<const X86InstrInfo*>(MF->getTarget().getInstrInfo());
-
-  MachineBasicBlock *Entry = MF->begin();
-  SmallPtrSet<MachineBasicBlock*, 16> Visited;
-  for (df_ext_iterator<MachineBasicBlock*,
-         SmallPtrSet<MachineBasicBlock*, 16> >
-         DFI = df_ext_begin(Entry, Visited), DFE = df_ext_end(Entry, Visited);
-       DFI != DFE; ++DFI) {
-    enterBasicBlock(*DFI);
-    for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
-        ++I) {
-      MachineInstr *MI = I;
-      const unsigned *equiv = 0;
-      X86InstrInfo::SSEDomain domain = TII->GetSSEDomain(MI, equiv);
-      DEBUG(dbgs() << "isd-"[domain] << (equiv ? "* " : "  ") << *MI);
-    }
-  }
-  return false;
-}
-
-FunctionPass *llvm::createSSEDomainFixPass() {
-  return new SSEDomainFixPass();
-}
-
-// These are the replaceable instructions. Some of these have _Int variants
-// that we don't include here. We don't want to replace instructions selected
-// by intrinsics.
-static const unsigned ReplaceableInstrs[][3] = {
-  //PackedInt          PackedSingle     PackedDouble
-  { X86::MOVDQAmr,     X86::MOVAPSmr,   X86::MOVAPDmr   },
-  { X86::MOVDQArm,     X86::MOVAPSrm,   X86::MOVAPDrm   },
-  { X86::MOVDQArr,     X86::MOVAPSrr,   X86::MOVAPDrr   },
-  { X86::MOVDQUmr,     X86::MOVUPSmr,   X86::MOVUPDmr   },
-  { X86::MOVDQUrm,     X86::MOVUPSrm,   X86::MOVUPDrm   },
-  { X86::MOVNTDQmr,    X86::MOVNTPSmr,  X86::MOVNTPDmr  },
-  { X86::PANDNrm,      X86::ANDNPSrm,   X86::ANDNPDrm   },
-  { X86::PANDNrr,      X86::ANDNPSrr,   X86::ANDNPDrr   },
-  { X86::PANDrm,       X86::ANDPSrm,    X86::ANDPDrm    },
-  { X86::PANDrr,       X86::ANDPSrr,    X86::ANDPDrr    },
-  { X86::PORrm,        X86::ORPSrm,     X86::ORPDrm     },
-  { X86::PORrr,        X86::ORPSrr,     X86::ORPDrr     },
-  { X86::PUNPCKHQDQrm, X86::UNPCKHPSrm, X86::UNPCKHPDrm },
-  { X86::PUNPCKHQDQrr, X86::UNPCKHPSrr, X86::UNPCKHPDrr },
-  { X86::PUNPCKLQDQrm, X86::UNPCKLPSrm, X86::UNPCKLPDrm },
-  { X86::PUNPCKLQDQrr, X86::UNPCKLPSrr, X86::UNPCKLPDrr },
-  { X86::PXORrm,       X86::XORPSrm,    X86::XORPDrm    },
-  { X86::PXORrr,       X86::XORPSrr,    X86::XORPDrr    },
-};
-
-void X86InstrInfo::populateSSEInstrDomainTable() {
-  // Instructions that execute in the packed integer domain.
-  static const unsigned PackedIntInstrs[] = {
-    X86::LDDQUrm,
-    X86::MASKMOVDQU,
-    X86::MASKMOVDQU64,
-    X86::MOVDI2PDIrm,
-    X86::MOVDI2PDIrr,
-    X86::MOVDQUmr_Int,
-    X86::MOVDQUrm_Int,
-    X86::MOVLQ128mr,
-    X86::MOVNTDQArm,
-    X86::MOVNTDQmr_Int,
-    X86::MOVNTDQ_64mr,
-    X86::MOVPDI2DImr,
-    X86::MOVPDI2DIrr,
-    X86::MOVPQI2QImr,
-    X86::MOVPQIto64rr,
-    X86::MOVQI2PQIrm,
-    X86::MOVQxrxr,
-    X86::MOVZDI2PDIrm,
-    X86::MOVZDI2PDIrr,
-    X86::MOVZPQILo2PQIrm,
-    X86::MOVZPQILo2PQIrr,
-    X86::MOVZQI2PQIrm,
-    X86::MOVZQI2PQIrr,
-    X86::MPSADBWrmi,
-    X86::MPSADBWrri,
-    X86::PABSBrm128,
-    X86::PABSBrr128,
-    X86::PABSDrm128,
-    X86::PABSDrr128,
-    X86::PABSWrm128,
-    X86::PABSWrr128,
-    X86::PACKSSDWrm,
-    X86::PACKSSDWrr,
-    X86::PACKSSWBrm,
-    X86::PACKSSWBrr,
-    X86::PACKUSDWrm,
-    X86::PACKUSDWrr,
-    X86::PACKUSWBrm,
-    X86::PACKUSWBrr,
-    X86::PADDBrm,
-    X86::PADDBrr,
-    X86::PADDDrm,
-    X86::PADDDrr,
-    X86::PADDQrm,
-    X86::PADDQrr,
-    X86::PADDSBrm,
-    X86::PADDSBrr,
-    X86::PADDSWrm,
-    X86::PADDSWrr,
-    X86::PADDUSBrm,
-    X86::PADDUSBrr,
-    X86::PADDUSWrm,
-    X86::PADDUSWrr,
-    X86::PADDWrm,
-    X86::PADDWrr,
-    X86::PALIGNR128rm,
-    X86::PALIGNR128rr,
-    X86::PAVGBrm,
-    X86::PAVGBrr,
-    X86::PAVGWrm,
-    X86::PAVGWrr,
-    X86::PBLENDVBrm0,
-    X86::PBLENDVBrr0,
-    X86::PBLENDWrmi,
-    X86::PBLENDWrri,
-    X86::PCMPEQBrm,
-    X86::PCMPEQBrr,
-    X86::PCMPEQDrm,
-    X86::PCMPEQDrr,
-    X86::PCMPEQQrm,
-    X86::PCMPEQQrr,
-    X86::PCMPEQWrm,
-    X86::PCMPEQWrr,
-    X86::PCMPESTRIArm,
-    X86::PCMPESTRIArr,
-    X86::PCMPESTRICrm,
-    X86::PCMPESTRICrr,
-    X86::PCMPESTRIOrm,
-    X86::PCMPESTRIOrr,
-    X86::PCMPESTRIrm,
-    X86::PCMPESTRIrr,
-    X86::PCMPESTRISrm,
-    X86::PCMPESTRISrr,
-    X86::PCMPESTRIZrm,
-    X86::PCMPESTRIZrr,
-    X86::PCMPESTRM128MEM,
-    X86::PCMPESTRM128REG,
-    X86::PCMPESTRM128rm,
-    X86::PCMPESTRM128rr,
-    X86::PCMPGTBrm,
-    X86::PCMPGTBrr,
-    X86::PCMPGTDrm,
-    X86::PCMPGTDrr,
-    X86::PCMPGTQrm,
-    X86::PCMPGTQrr,
-    X86::PCMPGTWrm,
-    X86::PCMPGTWrr,
-    X86::PCMPISTRIArm,
-    X86::PCMPISTRIArr,
-    X86::PCMPISTRICrm,
-    X86::PCMPISTRICrr,
-    X86::PCMPISTRIOrm,
-    X86::PCMPISTRIOrr,
-    X86::PCMPISTRIrm,
-    X86::PCMPISTRIrr,
-    X86::PCMPISTRISrm,
-    X86::PCMPISTRISrr,
-    X86::PCMPISTRIZrm,
-    X86::PCMPISTRIZrr,
-    X86::PCMPISTRM128MEM,
-    X86::PCMPISTRM128REG,
-    X86::PCMPISTRM128rm,
-    X86::PCMPISTRM128rr,
-    X86::PEXTRBmr,
-    X86::PEXTRBrr,
-    X86::PEXTRDmr,
-    X86::PEXTRDrr,
-    X86::PEXTRQmr,
-    X86::PEXTRQrr,
-    X86::PEXTRWmr,
-    X86::PEXTRWri,
-    X86::PHADDDrm128,
-    X86::PHADDDrr128,
-    X86::PHADDSWrm128,
-    X86::PHADDSWrr128,
-    X86::PHADDWrm128,
-    X86::PHADDWrr128,
-    X86::PHMINPOSUWrm128,
-    X86::PHMINPOSUWrr128,
-    X86::PHSUBDrm128,
-    X86::PHSUBDrr128,
-    X86::PHSUBSWrm128,
-    X86::PHSUBSWrr128,
-    X86::PHSUBWrm128,
-    X86::PHSUBWrr128,
-    X86::PINSRBrm,
-    X86::PINSRBrr,
-    X86::PINSRDrm,
-    X86::PINSRDrr,
-    X86::PINSRQrm,
-    X86::PINSRQrr,
-    X86::PINSRWrmi,
-    X86::PINSRWrri,
-    X86::PMADDUBSWrm128,
-    X86::PMADDUBSWrr128,
-    X86::PMADDWDrm,
-    X86::PMADDWDrr,
-    X86::PMAXSBrm,
-    X86::PMAXSBrr,
-    X86::PMAXSDrm,
-    X86::PMAXSDrr,
-    X86::PMAXSWrm,
-    X86::PMAXSWrr,
-    X86::PMAXUBrm,
-    X86::PMAXUBrr,
-    X86::PMAXUDrm,
-    X86::PMAXUDrr,
-    X86::PMAXUWrm,
-    X86::PMAXUWrr,
-    X86::PMINSBrm,
-    X86::PMINSBrr,
-    X86::PMINSDrm,
-    X86::PMINSDrr,
-    X86::PMINSWrm,
-    X86::PMINSWrr,
-    X86::PMINUBrm,
-    X86::PMINUBrr,
-    X86::PMINUDrm,
-    X86::PMINUDrr,
-    X86::PMINUWrm,
-    X86::PMINUWrr,
-    X86::PMOVSXBDrm,
-    X86::PMOVSXBDrr,
-    X86::PMOVSXBQrm,
-    X86::PMOVSXBQrr,
-    X86::PMOVSXBWrm,
-    X86::PMOVSXBWrr,
-    X86::PMOVSXDQrm,
-    X86::PMOVSXDQrr,
-    X86::PMOVSXWDrm,
-    X86::PMOVSXWDrr,
-    X86::PMOVSXWQrm,
-    X86::PMOVSXWQrr,
-    X86::PMOVZXBDrm,
-    X86::PMOVZXBDrr,
-    X86::PMOVZXBQrm,
-    X86::PMOVZXBQrr,
-    X86::PMOVZXBWrm,
-    X86::PMOVZXBWrr,
-    X86::PMOVZXDQrm,
-    X86::PMOVZXDQrr,
-    X86::PMOVZXWDrm,
-    X86::PMOVZXWDrr,
-    X86::PMOVZXWQrm,
-    X86::PMOVZXWQrr,
-    X86::PMULDQrm,
-    X86::PMULDQrr,
-    X86::PMULHRSWrm128,
-    X86::PMULHRSWrr128,
-    X86::PMULHUWrm,
-    X86::PMULHUWrr,
-    X86::PMULHWrm,
-    X86::PMULHWrr,
-    X86::PMULLDrm,
-    X86::PMULLDrm_int,
-    X86::PMULLDrr,
-    X86::PMULLDrr_int,
-    X86::PMULLWrm,
-    X86::PMULLWrr,
-    X86::PMULUDQrm,
-    X86::PMULUDQrr,
-    X86::PSADBWrm,
-    X86::PSADBWrr,
-    X86::PSHUFBrm128,
-    X86::PSHUFBrr128,
-    X86::PSHUFHWmi,
-    X86::PSHUFHWri,
-    X86::PSHUFLWmi,
-    X86::PSHUFLWri,
-    X86::PSIGNBrm128,
-    X86::PSIGNBrr128,
-    X86::PSIGNDrm128,
-    X86::PSIGNDrr128,
-    X86::PSIGNWrm128,
-    X86::PSIGNWrr128,
-    X86::PSLLDQri,
-    X86::PSLLDri,
-    X86::PSLLDrm,
-    X86::PSLLDrr,
-    X86::PSLLQri,
-    X86::PSLLQrm,
-    X86::PSLLQrr,
-    X86::PSLLWri,
-    X86::PSLLWrm,
-    X86::PSLLWrr,
-    X86::PSRADri,
-    X86::PSRADrm,
-    X86::PSRADrr,
-    X86::PSRAWri,
-    X86::PSRAWrm,
-    X86::PSRAWrr,
-    X86::PSRLDQri,
-    X86::PSRLDri,
-    X86::PSRLDrm,
-    X86::PSRLDrr,
-    X86::PSRLQri,
-    X86::PSRLQrm,
-    X86::PSRLQrr,
-    X86::PSRLWri,
-    X86::PSRLWrm,
-    X86::PSRLWrr,
-    X86::PSUBBrm,
-    X86::PSUBBrr,
-    X86::PSUBDrm,
-    X86::PSUBDrr,
-    X86::PSUBQrm,
-    X86::PSUBQrr,
-    X86::PSUBSBrm,
-    X86::PSUBSBrr,
-    X86::PSUBSWrm,
-    X86::PSUBSWrr,
-    X86::PSUBUSBrm,
-    X86::PSUBUSBrr,
-    X86::PSUBUSWrm,
-    X86::PSUBUSWrr,
-    X86::PSUBWrm,
-    X86::PSUBWrr,
-    X86::PUNPCKHBWrm,
-    X86::PUNPCKHBWrr,
-    X86::PUNPCKHWDrm,
-    X86::PUNPCKHWDrr,
-    X86::PUNPCKLBWrm,
-    X86::PUNPCKLBWrr,
-    X86::PUNPCKLWDrm,
-    X86::PUNPCKLWDrr,
-  };
-
-  // Instructions that execute in the packed single domain.
-  static const unsigned PackedSingleInstrs[] = {
-    X86::ADDPSrm,
-    X86::ADDPSrr,
-    X86::ADDSUBPSrm,
-    X86::ADDSUBPSrr,
-    X86::BLENDPSrmi,
-    X86::BLENDPSrri,
-    X86::BLENDVPSrm0,
-    X86::BLENDVPSrr0,
-    X86::CMPPSrmi,
-    X86::CMPPSrri,
-    X86::DIVPSrm,
-    X86::DIVPSrr,
-    X86::DPPSrmi,
-    X86::DPPSrri,
-    X86::EXTRACTPSmr,
-    X86::EXTRACTPSrr,
-    X86::HADDPSrm,
-    X86::HADDPSrr,
-    X86::HSUBPSrm,
-    X86::HSUBPSrr,
-    X86::INSERTPSrm,
-    X86::INSERTPSrr,
-    X86::MAXPSrm,
-    X86::MAXPSrm_Int,
-    X86::MAXPSrr,
-    X86::MAXPSrr_Int,
-    X86::MINPSrm,
-    X86::MINPSrm_Int,
-    X86::MINPSrr,
-    X86::MINPSrr_Int,
-    X86::MOVHLPSrr,
-    X86::MOVHPSmr,
-    X86::MOVHPSrm,
-    X86::MOVLHPSrr,
-    X86::MOVLPSmr,
-    X86::MOVLPSrm,
-    X86::MOVMSKPSrr,
-    X86::MOVNTPSmr_Int,
-    X86::MOVSHDUPrm,
-    X86::MOVSHDUPrr,
-    X86::MOVSLDUPrm,
-    X86::MOVSLDUPrr,
-    X86::MOVUPSmr_Int,
-    X86::MOVUPSrm_Int,
-    X86::MULPSrm,
-    X86::MULPSrr,
-    X86::RCPPSm,
-    X86::RCPPSm_Int,
-    X86::RCPPSr,
-    X86::RCPPSr_Int,
-    X86::ROUNDPSm_Int,
-    X86::ROUNDPSr_Int,
-    X86::RSQRTPSm,
-    X86::RSQRTPSm_Int,
-    X86::RSQRTPSr,
-    X86::RSQRTPSr_Int,
-    X86::SQRTPSm,
-    X86::SQRTPSm_Int,
-    X86::SQRTPSr,
-    X86::SQRTPSr_Int,
-    X86::SUBPSrm,
-    X86::SUBPSrr,
-  };
-
-  // Instructions that execute in the packed double domain.
-  static const unsigned PackedDoubleInstrs[] = {
-    X86::ADDPDrm,
-    X86::ADDPDrr,
-    X86::ADDSUBPDrm,
-    X86::ADDSUBPDrr,
-    X86::BLENDPDrmi,
-    X86::BLENDPDrri,
-    X86::BLENDVPDrm0,
-    X86::BLENDVPDrr0,
-    X86::CMPPDrmi,
-    X86::CMPPDrri,
-    X86::DIVPDrm,
-    X86::DIVPDrr,
-    X86::DPPDrmi,
-    X86::DPPDrri,
-    X86::HADDPDrm,
-    X86::HADDPDrr,
-    X86::HSUBPDrm,
-    X86::HSUBPDrr,
-    X86::MAXPDrm,
-    X86::MAXPDrm_Int,
-    X86::MAXPDrr,
-    X86::MAXPDrr_Int,
-    X86::MINPDrm,
-    X86::MINPDrm_Int,
-    X86::MINPDrr,
-    X86::MINPDrr_Int,
-    X86::MOVHPDmr,
-    X86::MOVHPDrm,
-    X86::MOVLPDmr,
-    X86::MOVLPDrm,
-    X86::MOVMSKPDrr,
-    X86::MOVNTPDmr_Int,
-    X86::MOVUPDmr_Int,
-    X86::MOVUPDrm_Int,
-    X86::MULPDrm,
-    X86::MULPDrr,
-    X86::ROUNDPDm_Int,
-    X86::ROUNDPDr_Int,
-    X86::SQRTPDm,
-    X86::SQRTPDm_Int,
-    X86::SQRTPDr,
-    X86::SQRTPDr_Int,
-    X86::SUBPDrm,
-    X86::SUBPDrr,
-  };
-
-  // Add non-negative entries for forcing instructions.
-  for (unsigned i = 0, e = array_lengthof(PackedIntInstrs); i != e; ++i)
-    SSEInstrDomainTable.insert(std::make_pair(PackedIntInstrs[i],
-                                              PackedInt));
-  for (unsigned i = 0, e = array_lengthof(PackedSingleInstrs); i != e; ++i)
-    SSEInstrDomainTable.insert(std::make_pair(PackedSingleInstrs[i],
-                                              PackedSingle));
-  for (unsigned i = 0, e = array_lengthof(PackedDoubleInstrs); i != e; ++i)
-    SSEInstrDomainTable.insert(std::make_pair(PackedDoubleInstrs[i],
-                                              PackedDouble));
-
-  // Add row number + 1 for replaceable instructions.
-  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
-    for (unsigned c = 0; c != 3; ++c)
-    SSEInstrDomainTable.insert(std::make_pair(ReplaceableInstrs[i][c],
-                                              c + 4*(i+1)));
-}
-
-X86InstrInfo::SSEDomain X86InstrInfo::GetSSEDomain(const MachineInstr *MI,
-                                                 const unsigned *&equiv) const {
-  DenseMap<unsigned,unsigned>::const_iterator i =
-    SSEInstrDomainTable.find(MI->getOpcode());
-  if (i == SSEInstrDomainTable.end())
-    return NotSSEDomain;
-  unsigned value = i->second;
-  if (value/4)
-    equiv = ReplaceableInstrs[value/4 - 1];
-  else
-    equiv = 0;
-  return SSEDomain(value & 3);
-}

Modified: llvm/trunk/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=99352&r1=99351&r2=99352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.h (original)
+++ llvm/trunk/lib/Target/X86/X86.h Tue Mar 23 18:48:51 2010
@@ -41,10 +41,6 @@
 ///
 FunctionPass *createX86FloatingPointStackifierPass();
 
-/// createSSEDomainFixPass - This pass twiddles SSE opcodes to prevent domain
-/// crossings.
-FunctionPass *createSSEDomainFixPass();
-
 /// createX87FPRegKillInserterPass - This function returns a pass which
 /// inserts FP_REG_KILL instructions where needed.
 ///

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=99352&r1=99351&r2=99352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Mar 23 18:48:51 2010
@@ -665,9 +665,6 @@
 
   // Remove ambiguous entries.
   assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
-
-  if (TM.getSubtarget<X86Subtarget>().hasSSE2())
-    populateSSEInstrDomainTable();
 }
 
 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=99352&r1=99351&r2=99352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Tue Mar 23 18:48:51 2010
@@ -486,9 +486,6 @@
   /// MemOp2RegOpTable - Load / store unfolding opcode map.
   ///
   DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
-
-  /// SSEInstrDomainTable - Map SSE opcodes to execution domain info.
-  DenseMap<unsigned, unsigned> SSEInstrDomainTable;
   
 public:
   explicit X86InstrInfo(X86TargetMachine &tm);
@@ -719,14 +716,6 @@
   ///
   unsigned getGlobalBaseReg(MachineFunction *MF) const;
 
-  /// Some SSE instructions come in variants for three domains.
-  enum SSEDomain { PackedInt, PackedSingle, PackedDouble, NotSSEDomain };
-
-  /// GetSSEDomain - Return the SSE execution domain of MI, or NotSSEDomain for
-  /// unknown instructions. If the instruction has equivalents for other domain,
-  /// equiv points to a list of opcodes index by domain.
-  SSEDomain GetSSEDomain(const MachineInstr *MI, const unsigned *&equiv) const;
-
 private:
   MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
                                               MachineFunction::iterator &MFI,
@@ -743,9 +732,6 @@
   /// operand and follow operands form a reference to the stack frame.
   bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
                       int &FrameIndex) const;
-
-  // Implemented in SSEDomainFix.cpp
-  void populateSSEInstrDomainTable();
 };
 
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=99352&r1=99351&r2=99352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Tue Mar 23 18:48:51 2010
@@ -17,17 +17,11 @@
 #include "llvm/PassManager.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/Passes.h"
-#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetRegistry.h"
 using namespace llvm;
 
-static cl::opt<bool>
-SSEDomainFix("sse-domain-fix",
-               cl::desc("Enable fixing of SSE execution domain"),
-               cl::init(false), cl::Hidden);
-
 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
   Triple TheTriple(TT);
   switch (TheTriple.getOS()) {
@@ -175,15 +169,6 @@
   return true;  // -print-machineinstr should print after this.
 }
 
-bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM,
-                                      CodeGenOpt::Level OptLevel) {
-  if (SSEDomainFix && OptLevel != CodeGenOpt::None && Subtarget.hasSSE2()) {
-    PM.add(createSSEDomainFixPass());
-    return true;
-  }
-  return false;
-}
-
 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
                                       CodeGenOpt::Level OptLevel,
                                       JITCodeEmitter &JCE) {

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=99352&r1=99351&r2=99352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Tue Mar 23 18:48:51 2010
@@ -66,7 +66,6 @@
   virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
   virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
   virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
                               JITCodeEmitter &JCE);
 };




From sabre at nondot.org  Tue Mar 23 18:50:31 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 23 Mar 2010 23:50:31 -0000
Subject: [llvm-commits] [llvm] r99353 -
	/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
Message-ID: <20100323235031.6AC852A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 18:50:31 2010
New Revision: 99353

URL: http://llvm.org/viewvc/llvm-project?rev=99353&view=rev
Log:
Cleanup getImplicitType

Modified:
    llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp

Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=99353&r1=99352&r2=99353&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Tue Mar 23 18:50:31 2010
@@ -996,34 +996,49 @@
 ///
 static EEVT::TypeSet getImplicitType(Record *R, unsigned ResNo,
                                      bool NotRegisters, TreePattern &TP) {
-  assert(ResNo == 0 && "FIXME: Unhandled result number");
-  
   // Check to see if this is a register or a register class.
   if (R->isSubClassOf("RegisterClass")) {
+    assert(ResNo == 0 && "Regclass ref only has one result!");
     if (NotRegisters) 
       return EEVT::TypeSet(); // Unknown.
     const CodeGenTarget &T = TP.getDAGPatterns().getTargetInfo();
     return EEVT::TypeSet(T.getRegisterClass(R).getValueTypes());
-  } else if (R->isSubClassOf("PatFrag")) {
+  }
+  
+  if (R->isSubClassOf("PatFrag")) {
+    assert(ResNo == 0 && "FIXME: PatFrag with multiple results?");
     // Pattern fragment types will be resolved when they are inlined.
     return EEVT::TypeSet(); // Unknown.
-  } else if (R->isSubClassOf("Register")) {
+  }
+  
+  if (R->isSubClassOf("Register")) {
+    assert(ResNo == 0 && "Registers only produce one result!");
     if (NotRegisters) 
       return EEVT::TypeSet(); // Unknown.
     const CodeGenTarget &T = TP.getDAGPatterns().getTargetInfo();
     return EEVT::TypeSet(T.getRegisterVTs(R));
-  } else if (R->isSubClassOf("ValueType") || R->isSubClassOf("CondCode")) {
+  }
+  
+  if (R->isSubClassOf("ValueType") || R->isSubClassOf("CondCode")) {
+    assert(ResNo == 0 && "This node only has one result!");
     // Using a VTSDNode or CondCodeSDNode.
     return EEVT::TypeSet(MVT::Other, TP);
-  } else if (R->isSubClassOf("ComplexPattern")) {
+  }
+  
+  if (R->isSubClassOf("ComplexPattern")) {
+    assert(ResNo == 0 && "FIXME: ComplexPattern with multiple results?");
     if (NotRegisters) 
       return EEVT::TypeSet(); // Unknown.
    return EEVT::TypeSet(TP.getDAGPatterns().getComplexPattern(R).getValueType(),
                          TP);
-  } else if (R->isSubClassOf("PointerLikeRegClass")) {
+  }
+  if (R->isSubClassOf("PointerLikeRegClass")) {
+    assert(ResNo == 0 && "Regclass can only have one result!");
     return EEVT::TypeSet(MVT::iPTR, TP);
-  } else if (R->getName() == "node" || R->getName() == "srcvalue" ||
-             R->getName() == "zero_reg") {
+  }
+  
+  if (R->getName() == "node" || R->getName() == "srcvalue" ||
+      R->getName() == "zero_reg") {
     // Placeholder.
     return EEVT::TypeSet(); // Unknown.
   }




From stoklund at 2pi.dk  Tue Mar 23 18:53:41 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 23 Mar 2010 16:53:41 -0700
Subject: [llvm-commits] [llvm] r99345 - in /llvm/trunk/lib/Target/X86:
	CMakeLists.txt SSEDomainFix.cpp X86.h X86InstrInfo.cpp
	X86InstrInfo.h X86TargetMachine.cpp X86TargetMachine.h
In-Reply-To: <36283ED3-8DD2-4EA4-9B68-B486BD42DD0F@apple.com>
References: <20100323231444.97DDA2A6C12C@llvm.org>
	<36283ED3-8DD2-4EA4-9B68-B486BD42DD0F@apple.com>
Message-ID: <A8A52C33-3D35-4B61-89CF-DCFD2BBE4738@2pi.dk>


On Mar 23, 2010, at 4:17 PM, Chris Lattner wrote:

> 
> On Mar 23, 2010, at 4:14 PM, Jakob Stoklund Olesen wrote:
>> +  static const unsigned PackedIntInstrs[] = {
>> +    X86::LDDQUrm,
>> +    X86::MASKMOVDQU,
> 
> Ewww...!

Yeah, I agree.

> Can you add a bit to TargetInstrDesc::TSFlags so that this lives in the .td files?

Bits 22 and 23 are the last two bits in TSFlags. I would need to use both.




From sabre at nondot.org  Tue Mar 23 19:01:16 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 00:01:16 -0000
Subject: [llvm-commits] [llvm] r99354 - in /llvm/trunk/utils/TableGen:
 CodeGenDAGPatterns.cpp CodeGenDAGPatterns.h
Message-ID: <20100324000116.38CE32A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 19:01:16 2010
New Revision: 99354

URL: http://llvm.org/viewvc/llvm-project?rev=99354&view=rev
Log:
bring sanity to EnforceVectorEltType

Modified:
    llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
    llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h

Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=99354&r1=99353&r2=99354&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Tue Mar 23 19:01:16 2010
@@ -394,24 +394,39 @@
 }
 
 /// EnforceVectorEltTypeIs - 'this' is now constrainted to be a vector type
-/// whose element is VT.
-bool EEVT::TypeSet::EnforceVectorEltTypeIs(MVT::SimpleValueType VT,
+/// whose element is specified by VTOperand.
+bool EEVT::TypeSet::EnforceVectorEltTypeIs(EEVT::TypeSet &VTOperand,
                                            TreePattern &TP) {
-  TypeSet InputSet(*this);
+  // "This" must be a vector and "VTOperand" must be a scalar.
   bool MadeChange = false;
+  MadeChange |= EnforceVector(TP);
+  MadeChange |= VTOperand.EnforceScalar(TP);
+
+  // If we know the vector type, it forces the scalar to agree.
+  if (isConcrete()) {
+    EVT IVT = getConcrete();
+    IVT = IVT.getVectorElementType();
+    return MadeChange | 
+      VTOperand.MergeInTypeInfo(IVT.getSimpleVT().SimpleTy, TP);
+  }
+
+  // If the scalar type is known, filter out vector types whose element types
+  // disagree.
+  if (!VTOperand.isConcrete())
+    return MadeChange;
+  
+  MVT::SimpleValueType VT = VTOperand.getConcrete();
   
-  // If we know nothing, then get the full set.
-  if (TypeVec.empty())
-    MadeChange = FillWithPossibleTypes(TP, isVector, "vector");
-  
-  // Filter out all the non-vector types and types which don't have the right
-  // element type.
-  for (unsigned i = 0; i != TypeVec.size(); ++i)
-    if (!isVector(TypeVec[i]) ||
-        EVT(TypeVec[i]).getVectorElementType().getSimpleVT().SimpleTy != VT) {
+  TypeSet InputSet(*this);
+  
+  // Filter out all the types which don't have the right element type.
+  for (unsigned i = 0; i != TypeVec.size(); ++i) {
+    assert(isVector(TypeVec[i]) && "EnforceVector didn't work");
+    if (EVT(TypeVec[i]).getVectorElementType().getSimpleVT().SimpleTy != VT) {
       TypeVec.erase(TypeVec.begin()+i--);
       MadeChange = true;
     }
+  }
   
   if (TypeVec.empty())  // FIXME: Really want an SMLoc here!
     TP.error("Type inference contradiction found, forcing '" +
@@ -642,22 +657,11 @@
     TreePatternNode *VecOperand =
       getOperandNum(x.SDTCisEltOfVec_Info.OtherOperandNum, N, NodeInfo,
                     VResNo);
-    if (VecOperand->hasTypeSet(VResNo)) {
-      if (!isVector(VecOperand->getType(VResNo)))
-        TP.error(N->getOperator()->getName() + " VT operand must be a vector!");
-      EVT IVT = VecOperand->getType(VResNo);
-      IVT = IVT.getVectorElementType();
-      return NodeToApply->UpdateNodeType(ResNo, IVT.getSimpleVT().SimpleTy, TP);
-    }
     
-    if (NodeToApply->hasTypeSet(ResNo) &&
-        VecOperand->getExtType(VResNo).hasVectorTypes()){
-      // Filter vector types out of VecOperand that don't have the right element
-      // type.
-      return VecOperand->getExtType(VResNo).
-        EnforceVectorEltTypeIs(NodeToApply->getType(ResNo), TP);
-    }
-    return false;
+    // Filter vector types out of VecOperand that don't have the right element
+    // type.
+    return VecOperand->getExtType(VResNo).
+      EnforceVectorEltTypeIs(NodeToApply->getExtType(ResNo), TP);
   }
   }  
   return false;

Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=99354&r1=99353&r2=99354&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Tue Mar 23 19:01:16 2010
@@ -129,7 +129,7 @@
     
     /// EnforceVectorEltTypeIs - 'this' is now constrainted to be a vector type
     /// whose element is VT.
-    bool EnforceVectorEltTypeIs(MVT::SimpleValueType VT, TreePattern &TP);
+    bool EnforceVectorEltTypeIs(EEVT::TypeSet &VT, TreePattern &TP);
     
     bool operator!=(const TypeSet &RHS) const { return TypeVec != RHS.TypeVec; }
     bool operator==(const TypeSet &RHS) const { return TypeVec == RHS.TypeVec; }




From grosbach at apple.com  Tue Mar 23 19:03:13 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 24 Mar 2010 00:03:13 -0000
Subject: [llvm-commits] [llvm] r99355 -
	/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <20100324000313.C9EE02A6C12C@llvm.org>

Author: grosbach
Date: Tue Mar 23 19:03:13 2010
New Revision: 99355

URL: http://llvm.org/viewvc/llvm-project?rev=99355&view=rev
Log:
try being more permissive for if-conversion on ARM V7. see what the nightly
test run permformance numbers say as to whether it helps.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=99355&r1=99354&r2=99355&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Mar 23 19:03:13 2010
@@ -40,12 +40,18 @@
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/VectorExtras.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include <sstream>
 using namespace llvm;
 
+static cl::opt<bool>
+aggressiveV7IfConvert("arm-aggressive-v7-ifcvt", cl::Hidden,
+                      cl::desc("Enable more liberal if-converstion for v7"),
+                      cl::init(false));
+
 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
                                    CCValAssign::LocInfo &LocInfo,
                                    ISD::ArgFlagsTy &ArgFlags,
@@ -456,6 +462,9 @@
     // Generic (and overly aggressive) if-conversion limits.
     setIfCvtBlockSizeLimit(10);
     setIfCvtDupBlockSizeLimit(2);
+  } else if (aggressiveV7IfConvert && Subtarget->hasV7Ops()) {
+    setIfCvtBlockSizeLimit(3);
+    setIfCvtDupBlockSizeLimit(1);
   } else if (Subtarget->hasV6Ops()) {
     setIfCvtBlockSizeLimit(2);
     setIfCvtDupBlockSizeLimit(1);




From grosbach at apple.com  Tue Mar 23 19:04:56 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 24 Mar 2010 00:04:56 -0000
Subject: [llvm-commits] [test-suite] r99356 -
	/test-suite/trunk/Makefile.programs
Message-ID: <20100324000456.0CE122A6C12C@llvm.org>

Author: grosbach
Date: Tue Mar 23 19:04:55 2010
New Revision: 99356

URL: http://llvm.org/viewvc/llvm-project?rev=99356&view=rev
Log:
try being more permissive for if-conversion on ARM V7. see what the nightly
test run permformance numbers say as to whether it helps.

Modified:
    test-suite/trunk/Makefile.programs

Modified: test-suite/trunk/Makefile.programs
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=99356&r1=99355&r2=99356&view=diff
==============================================================================
--- test-suite/trunk/Makefile.programs (original)
+++ test-suite/trunk/Makefile.programs Tue Mar 23 19:04:55 2010
@@ -241,10 +241,10 @@
 LLCBETAOPTION := -enable-sparc-v9-insts
 endif
 ifeq ($(ARCH),ARM)
-LLCBETAOPTION :=
+LLCBETAOPTION := -arm-aggressive-v7-ifcvt
 endif
 ifeq ($(ARCH),THUMB)
-LLCBETAOPTION :=
+LLCBETAOPTION := -arm-aggressive-v7-ifcvt
 endif
 
 print-llcbeta-option:




From sabre at nondot.org  Tue Mar 23 19:06:46 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 00:06:46 -0000
Subject: [llvm-commits] [llvm] r99357 -
	/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
Message-ID: <20100324000646.E552D2A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 19:06:46 2010
New Revision: 99357

URL: http://llvm.org/viewvc/llvm-project?rev=99357&view=rev
Log:
implement SDTCisVTSmallerThanOp with EnforceSmallerThan
instead of reimplementing it wrong and poorly.

Modified:
    llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp

Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=99357&r1=99356&r2=99357&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Tue Mar 23 19:06:46 2010
@@ -627,22 +627,15 @@
       TP.error(N->getOperator()->getName() + " expects a VT operand!");
     MVT::SimpleValueType VT =
      getValueType(static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef());
-    if (!isInteger(VT))
-      TP.error(N->getOperator()->getName() + " VT operand must be integer!");
+    
+    EEVT::TypeSet TypeListTmp(VT, TP);
     
     unsigned OResNo = 0;
     TreePatternNode *OtherNode =
       getOperandNum(x.SDTCisVTSmallerThanOp_Info.OtherOperandNum, N, NodeInfo,
                     OResNo);
-    
-    // It must be integer.
-    bool MadeChange = OtherNode->getExtType(OResNo).EnforceInteger(TP);
 
-    // This doesn't try to enforce any information on the OtherNode, it just
-    // validates it when information is determined.
-    if (OtherNode->hasTypeSet(OResNo) && OtherNode->getType(OResNo) <= VT)
-      OtherNode->UpdateNodeType(OResNo, MVT::Other, TP);  // Throw an error.
-    return MadeChange;
+    return TypeListTmp.EnforceSmallerThan(OtherNode->getExtType(OResNo), TP);
   }
   case SDTCisOpSmallerThanOp: {
     unsigned BResNo = 0;




From sabre at nondot.org  Tue Mar 23 19:12:57 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 00:12:57 -0000
Subject: [llvm-commits] [llvm] r99358 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.td
Message-ID: <20100324001257.5FB7C2A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 19:12:57 2010
New Revision: 99358

URL: http://llvm.org/viewvc/llvm-project?rev=99358&view=rev
Log:
reduce nesting.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=99358&r1=99357&r2=99358&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Mar 23 19:12:57 2010
@@ -473,15 +473,14 @@
 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
     return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
-  else {
-    unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
-    APInt Mask = APInt::getAllOnesValue(BitWidth);
-    APInt KnownZero0, KnownOne0;
-    CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
-    APInt KnownZero1, KnownOne1;
-    CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
-    return (~KnownZero0 & ~KnownZero1) == 0;
-  }
+
+  unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
+  APInt Mask = APInt::getAllOnesValue(BitWidth);
+  APInt KnownZero0, KnownOne0;
+  CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
+  APInt KnownZero1, KnownOne1;
+  CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
+  return (~KnownZero0 & ~KnownZero1) == 0;
 }]>;
 
 // 'shld' and 'shrd' instruction patterns. Note that even though these have




From sabre at nondot.org  Tue Mar 23 19:15:23 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 00:15:23 -0000
Subject: [llvm-commits] [llvm] r99359 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.td
Message-ID: <20100324001523.88FFF2A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 19:15:23 2010
New Revision: 99359

URL: http://llvm.org/viewvc/llvm-project?rev=99359&view=rev
Log:
remove useless or_is_add parallel's.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=99359&r1=99358&r2=99359&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Mar 23 19:15:23 2010
@@ -4721,23 +4721,17 @@
 
 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
 let AddedComplexity = 5 in { // Try this before the selecting to OR
-def : Pat<(parallel (or_is_add GR16:$src1, imm:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(or_is_add GR16:$src1, imm:$src2),
           (ADD16ri GR16:$src1, imm:$src2)>;
-def : Pat<(parallel (or_is_add GR32:$src1, imm:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(or_is_add GR32:$src1, imm:$src2),
           (ADD32ri GR32:$src1, imm:$src2)>;
-def : Pat<(parallel (or_is_add GR16:$src1, i16immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
           (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
-def : Pat<(parallel (or_is_add GR32:$src1, i32immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
           (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
-def : Pat<(parallel (or_is_add GR16:$src1, GR16:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(or_is_add GR16:$src1, GR16:$src2),
           (ADD16rr GR16:$src1, GR16:$src2)>;
-def : Pat<(parallel (or_is_add GR32:$src1, GR32:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(or_is_add GR32:$src1, GR32:$src2),
           (ADD32rr GR32:$src1, GR32:$src2)>;
 } // AddedComplexity
 




From sabre at nondot.org  Tue Mar 23 19:16:52 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 00:16:52 -0000
Subject: [llvm-commits] [llvm] r99360 -
	/llvm/trunk/lib/Target/X86/X86Instr64bit.td
Message-ID: <20100324001652.A4CAE2A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 19:16:52 2010
New Revision: 99360

URL: http://llvm.org/viewvc/llvm-project?rev=99360&view=rev
Log:
remove 64-bit or_is_add parallels.

Modified:
    llvm/trunk/lib/Target/X86/X86Instr64bit.td

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=99360&r1=99359&r2=99360&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Mar 23 19:16:52 2010
@@ -2181,14 +2181,11 @@
 
 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
 let AddedComplexity = 5 in {  // Try this before the selecting to OR
-def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(or_is_add GR64:$src1, i64immSExt8:$src2),
           (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
-def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt32:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(or_is_add GR64:$src1, i64immSExt32:$src2),
           (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
-def : Pat<(parallel (or_is_add GR64:$src1, GR64:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(or_is_add GR64:$src1, GR64:$src2),
           (ADD64rr GR64:$src1, GR64:$src2)>;
 } // AddedComplexity
 




From clattner at apple.com  Tue Mar 23 19:19:03 2010
From: clattner at apple.com (Chris Lattner)
Date: Tue, 23 Mar 2010 17:19:03 -0700
Subject: [llvm-commits] [llvm] r99345 - in /llvm/trunk/lib/Target/X86:
	CMakeLists.txt SSEDomainFix.cpp X86.h X86InstrInfo.cpp
	X86InstrInfo.h X86TargetMachine.cpp X86TargetMachine.h
In-Reply-To: <A8A52C33-3D35-4B61-89CF-DCFD2BBE4738@2pi.dk>
References: <20100323231444.97DDA2A6C12C@llvm.org>
	<36283ED3-8DD2-4EA4-9B68-B486BD42DD0F@apple.com>
	<A8A52C33-3D35-4B61-89CF-DCFD2BBE4738@2pi.dk>
Message-ID: <99223259-C224-4A00-8953-5E541B80ABCB@apple.com>


On Mar 23, 2010, at 4:53 PM, Jakob Stoklund Olesen wrote:

> 
> On Mar 23, 2010, at 4:17 PM, Chris Lattner wrote:
> 
>> 
>> On Mar 23, 2010, at 4:14 PM, Jakob Stoklund Olesen wrote:
>>> +  static const unsigned PackedIntInstrs[] = {
>>> +    X86::LDDQUrm,
>>> +    X86::MASKMOVDQU,
>> 
>> Ewww...!
> 
> Yeah, I agree.
> 
>> Can you add a bit to TargetInstrDesc::TSFlags so that this lives in the .td files?
> 
> Bits 22 and 23 are the last two bits in TSFlags. I would need to use both

Go for it,

-Chris




From gohman at apple.com  Tue Mar 23 19:22:25 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 24 Mar 2010 00:22:25 -0000
Subject: [llvm-commits] [llvm] r99361 -
	/llvm/trunk/include/llvm/Analysis/Dominators.h
Message-ID: <20100324002225.18FAF2A6C12C@llvm.org>

Author: djg
Date: Tue Mar 23 19:22:24 2010
New Revision: 99361

URL: http://llvm.org/viewvc/llvm-project?rev=99361&view=rev
Log:
Generalize findNearestCommonDominator to work on post-dominators,
based on a suggestion by Jochen Wilhelmy.

Modified:
    llvm/trunk/include/llvm/Analysis/Dominators.h

Modified: llvm/trunk/include/llvm/Analysis/Dominators.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Dominators.h?rev=99361&r1=99360&r2=99361&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/Dominators.h (original)
+++ llvm/trunk/include/llvm/Analysis/Dominators.h Tue Mar 23 19:22:24 2010
@@ -431,15 +431,16 @@
   /// for basic block A and B. If there is no such block then return NULL.
   NodeT *findNearestCommonDominator(NodeT *A, NodeT *B) {
 
-    assert (!this->isPostDominator()
-            && "This is not implemented for post dominators");
     assert (A->getParent() == B->getParent()
             && "Two blocks are not in same function");
 
-    // If either A or B is a entry block then it is nearest common dominator.
-    NodeT &Entry  = A->getParent()->front();
-    if (A == &Entry || B == &Entry)
-      return &Entry;
+    // If either A or B is a entry block then it is nearest common dominator
+    // (for forward-dominators).
+    if (!this->isPostDominator()) {
+      NodeT &Entry  = A->getParent()->front();
+      if (A == &Entry || B == &Entry)
+        return &Entry;
+    }
 
     // If B dominates A then B is nearest common dominator.
     if (dominates(B, A))




From gohman at apple.com  Tue Mar 23 19:27:49 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 24 Mar 2010 00:27:49 -0000
Subject: [llvm-commits] [llvm] r99362 -
	/llvm/trunk/include/llvm/Analysis/Dominators.h
Message-ID: <20100324002749.DD40A2A6C12C@llvm.org>

Author: djg
Date: Tue Mar 23 19:27:49 2010
New Revision: 99362

URL: http://llvm.org/viewvc/llvm-project?rev=99362&view=rev
Log:
Fix coding style.

Modified:
    llvm/trunk/include/llvm/Analysis/Dominators.h

Modified: llvm/trunk/include/llvm/Analysis/Dominators.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Dominators.h?rev=99362&r1=99361&r2=99362&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/Dominators.h (original)
+++ llvm/trunk/include/llvm/Analysis/Dominators.h Tue Mar 23 19:27:49 2010
@@ -116,12 +116,12 @@
       return true;
 
     SmallPtrSet<NodeT *, 4> OtherChildren;
-    for(iterator I = Other->begin(), E = Other->end(); I != E; ++I) {
+    for (iterator I = Other->begin(), E = Other->end(); I != E; ++I) {
       NodeT *Nd = (*I)->getBlock();
       OtherChildren.insert(Nd);
     }
 
-    for(iterator I = begin(), E = end(); I != E; ++I) {
+    for (iterator I = begin(), E = end(); I != E; ++I) {
       NodeT *N = (*I)->getBlock();
       if (OtherChildren.count(N) == 0)
         return true;
@@ -240,8 +240,9 @@
   template<class N, class GraphT>
   void Split(DominatorTreeBase<typename GraphT::NodeType>& DT,
              typename GraphT::NodeType* NewBB) {
-    assert(std::distance(GraphT::child_begin(NewBB), GraphT::child_end(NewBB)) == 1
-           && "NewBB should have a single successor!");
+    assert(std::distance(GraphT::child_begin(NewBB),
+                         GraphT::child_end(NewBB)) == 1 &&
+           "NewBB should have a single successor!");
     typename GraphT::NodeType* NewBBSucc = *GraphT::child_begin(NewBB);
 
     std::vector<typename GraphT::NodeType*> PredBlocks;
@@ -374,8 +375,8 @@
   /// isReachableFromEntry - Return true if A is dominated by the entry
   /// block of the function containing it.
   bool isReachableFromEntry(NodeT* A) {
-    assert (!this->isPostDominator()
-            && "This is not implemented for post dominators");
+    assert(!this->isPostDominator() &&
+           "This is not implemented for post dominators");
     return dominates(&A->getParent()->front(), A);
   }
 
@@ -393,8 +394,9 @@
     // Compare the result of the tree walk and the dfs numbers, if expensive
     // checks are enabled.
 #ifdef XDEBUG
-    assert(!DFSInfoValid
-           || (dominatedBySlowTreeWalk(A, B) == B->DominatedBy(A)));
+    assert((!DFSInfoValid ||
+            (dominatedBySlowTreeWalk(A, B) == B->DominatedBy(A))) &&
+           "Tree walk disagrees with dfs numbers!");
 #endif
 
     if (DFSInfoValid)
@@ -430,14 +432,13 @@
   /// findNearestCommonDominator - Find nearest common dominator basic block
   /// for basic block A and B. If there is no such block then return NULL.
   NodeT *findNearestCommonDominator(NodeT *A, NodeT *B) {
-
-    assert (A->getParent() == B->getParent()
-            && "Two blocks are not in same function");
+    assert(A->getParent() == B->getParent() &&
+           "Two blocks are not in same function");
 
     // If either A or B is a entry block then it is nearest common dominator
     // (for forward-dominators).
     if (!this->isPostDominator()) {
-      NodeT &Entry  = A->getParent()->front();
+      NodeT &Entry = A->getParent()->front();
       if (A == &Entry || B == &Entry)
         return &Entry;
     }
@@ -464,7 +465,7 @@
 
     // Walk NodeB immediate dominators chain and find common dominator node.
     DomTreeNodeBase<NodeT> *IDomB = NodeB->getIDom();
-    while(IDomB) {
+    while (IDomB) {
       if (NodeADoms.count(IDomB) != 0)
         return IDomB->getBlock();
 
@@ -509,8 +510,8 @@
   /// children list. Deletes dominator node associated with basic block BB.
   void eraseNode(NodeT *BB) {
     DomTreeNodeBase<NodeT> *Node = getNode(BB);
-    assert (Node && "Removing node that isn't in dominator tree.");
-    assert (Node->getChildren().empty() && "Node is not a leaf node.");
+    assert(Node && "Removing node that isn't in dominator tree.");
+    assert(Node->getChildren().empty() && "Node is not a leaf node.");
 
       // Remove node from immediate dominator's children list.
     DomTreeNodeBase<NodeT> *IDom = Node->getIDom();
@@ -953,7 +954,7 @@
         return true;
     }
 
-    if(!tmpSet.empty())
+    if (!tmpSet.empty())
       // There are nodes that are in DS2 but not in DS1.
       return true;
 




From sabre at nondot.org  Tue Mar 23 19:41:19 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 00:41:19 -0000
Subject: [llvm-commits] [llvm] r99366 - in /llvm/trunk/utils/TableGen:
 CodeGenDAGPatterns.cpp CodeGenDAGPatterns.h DAGISelMatcher.cpp
 DAGISelMatcher.h DAGISelMatcherEmitter.cpp DAGISelMatcherGen.cpp
 DAGISelMatcherOpt.cpp FastISelEmitter.cpp
Message-ID: <20100324004119.5FA8C2A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 19:41:19 2010
New Revision: 99366

URL: http://llvm.org/viewvc/llvm-project?rev=99366&view=rev
Log:
add plumbing for handling multiple result nodes 
in some more places.

Modified:
    llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
    llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
    llvm/trunk/utils/TableGen/DAGISelMatcher.cpp
    llvm/trunk/utils/TableGen/DAGISelMatcher.h
    llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp
    llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp
    llvm/trunk/utils/TableGen/DAGISelMatcherOpt.cpp
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp

Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=99366&r1=99365&r2=99366&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Tue Mar 23 19:41:19 2010
@@ -713,10 +713,11 @@
 /// getKnownType - If the type constraints on this node imply a fixed type
 /// (e.g. all stores return void, etc), then return it as an
 /// MVT::SimpleValueType.  Otherwise, return EEVT::Other.
-MVT::SimpleValueType SDNodeInfo::getKnownType() const {
+MVT::SimpleValueType SDNodeInfo::getKnownType(unsigned ResNo) const {
   unsigned NumResults = getNumResults();
   assert(NumResults <= 1 &&
          "We only work with nodes with zero or one result so far!");
+  assert(ResNo == 0 && "Only handles single result nodes so far");
   
   for (unsigned i = 0, e = TypeConstraints.size(); i != e; ++i) {
     // Make sure that this applies to the correct node result.

Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=99366&r1=99365&r2=99366&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Tue Mar 23 19:41:19 2010
@@ -211,7 +211,7 @@
   /// getKnownType - If the type constraints on this node imply a fixed type
   /// (e.g. all stores return void, etc), then return it as an
   /// MVT::SimpleValueType.  Otherwise, return MVT::Other.
-  MVT::SimpleValueType getKnownType() const;
+  MVT::SimpleValueType getKnownType(unsigned ResNo) const;
   
   /// hasProperty - Return true if this node has the specified property.
   ///

Modified: llvm/trunk/utils/TableGen/DAGISelMatcher.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelMatcher.cpp?rev=99366&r1=99365&r2=99366&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelMatcher.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelMatcher.cpp Tue Mar 23 19:41:19 2010
@@ -147,7 +147,8 @@
 
 
 void CheckTypeMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
-  OS.indent(indent) << "CheckType " << getEnumName(Type) << '\n';
+  OS.indent(indent) << "CheckType " << getEnumName(Type) << ", ResNo="
+    << ResNo << '\n';
 }
 
 void SwitchTypeMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
@@ -356,12 +357,11 @@
   // different, then we know they contradict.  For example, a check for
   // ISD::STORE will never be true at the same time a check for Type i32 is.
   if (const CheckTypeMatcher *CT = dyn_cast<CheckTypeMatcher>(M)) {
-    // FIXME: What result is this referring to?
-    MVT::SimpleValueType NodeType;
-    if (getOpcode().getNumResults() == 0)
-      NodeType = MVT::isVoid;
-    else
-      NodeType = getOpcode().getKnownType();
+    // If checking for a result the opcode doesn't have, it can't match.
+    if (CT->getResNo() >= getOpcode().getNumResults())
+      return true;
+    
+    MVT::SimpleValueType NodeType = getOpcode().getKnownType(CT->getResNo());
     if (NodeType != MVT::Other)
       return TypesAreContradictory(NodeType, CT->getType());
   }

Modified: llvm/trunk/utils/TableGen/DAGISelMatcher.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelMatcher.h?rev=99366&r1=99365&r2=99366&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelMatcher.h (original)
+++ llvm/trunk/utils/TableGen/DAGISelMatcher.h Tue Mar 23 19:41:19 2010
@@ -492,14 +492,16 @@
 };
   
 /// CheckTypeMatcher - This checks to see if the current node has the
-/// specified type, if not it fails to match.
+/// specified type at the specified result, if not it fails to match.
 class CheckTypeMatcher : public Matcher {
   MVT::SimpleValueType Type;
+  unsigned ResNo;
 public:
-  CheckTypeMatcher(MVT::SimpleValueType type)
-    : Matcher(CheckType), Type(type) {}
+  CheckTypeMatcher(MVT::SimpleValueType type, unsigned resno)
+    : Matcher(CheckType), Type(type), ResNo(resno) {}
   
   MVT::SimpleValueType getType() const { return Type; }
+  unsigned getResNo() const { return ResNo; }
   
   static inline bool classof(const Matcher *N) {
     return N->getKind() == CheckType;

Modified: llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp?rev=99366&r1=99365&r2=99366&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp Tue Mar 23 19:41:19 2010
@@ -341,6 +341,8 @@
   }
 
  case Matcher::CheckType:
+    assert(cast<CheckTypeMatcher>(N)->getResNo() == 0 &&
+           "FIXME: Add support for CheckType of resno != 0");
     OS << "OPC_CheckType, "
        << getEnumName(cast<CheckTypeMatcher>(N)->getType()) << ",\n";
     return 2;

Modified: llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp?rev=99366&r1=99365&r2=99366&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp Tue Mar 23 19:41:19 2010
@@ -408,13 +408,13 @@
   // If N and NodeNoTypes don't agree on a type, then this is a case where we
   // need to do a type check.  Emit the check, apply the tyep to NodeNoTypes and
   // reinfer any correlated types.
-  bool DoTypeCheck = false;
-  if (NodeNoTypes->getNumTypes() != 0 &&
-      NodeNoTypes->getExtType(0) != N->getExtType(0)) {
-    assert(NodeNoTypes->getNumTypes() == 1 && "FIXME: Handle multiple results");
-    NodeNoTypes->setType(0, N->getExtType(0));
+  SmallVector<unsigned, 2> ResultsToTypeCheck;
+  
+  for (unsigned i = 0, e = NodeNoTypes->getNumTypes(); i != e; ++i) {
+    if (NodeNoTypes->getExtType(i) == N->getExtType(i)) continue;
+    NodeNoTypes->setType(i, N->getExtType(i));
     InferPossibleTypes();
-    DoTypeCheck = true;
+    ResultsToTypeCheck.push_back(i);
   }
   
   // If this node has a name associated with it, capture it in VariableMap. If
@@ -444,10 +444,9 @@
   for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i)
     AddMatcher(new CheckPredicateMatcher(N->getPredicateFns()[i]));
   
-  if (DoTypeCheck) {
-    assert(N->getNumTypes() == 1);
-    AddMatcher(new CheckTypeMatcher(N->getType(0)));
-  }
+  for (unsigned i = 0, e = ResultsToTypeCheck.size(); i != e; ++i)
+    AddMatcher(new CheckTypeMatcher(N->getType(ResultsToTypeCheck[i]),
+                                    ResultsToTypeCheck[i]));
 }
 
 /// EmitMatcherCode - Generate the code that matches the predicate of this

Modified: llvm/trunk/utils/TableGen/DAGISelMatcherOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelMatcherOpt.cpp?rev=99366&r1=99365&r2=99366&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelMatcherOpt.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelMatcherOpt.cpp Tue Mar 23 19:41:19 2010
@@ -48,8 +48,9 @@
         New = new RecordChildMatcher(MC->getChildNo(), RM->getWhatFor(),
                                      RM->getResultNo());
     
-    if (CheckTypeMatcher *CT= dyn_cast<CheckTypeMatcher>(MC->getNext()))
-      if (MC->getChildNo() < 8)  // Only have CheckChildType0...7
+    if (CheckTypeMatcher *CT = dyn_cast<CheckTypeMatcher>(MC->getNext()))
+      if (MC->getChildNo() < 8 &&  // Only have CheckChildType0...7
+          CT->getResNo() == 0)     // CheckChildType checks res #0
         New = new CheckChildTypeMatcher(MC->getChildNo(), CT->getType());
     
     if (New) {
@@ -420,10 +421,12 @@
       CheckTypeMatcher *CTM =
         cast_or_null<CheckTypeMatcher>(FindNodeWithKind(NewOptionsToMatch[i],
                                                         Matcher::CheckType));
-      if (CTM == 0 || 
+      if (CTM == 0 ||
           // iPTR checks could alias any other case without us knowing, don't
           // bother with them.
           CTM->getType() == MVT::iPTR ||
+          // SwitchType only works for result #0.
+          CTM->getResNo() != 0 ||
           // If the CheckType isn't at the start of the list, see if we can move
           // it there.
           !CTM->canMoveBefore(NewOptionsToMatch[i])) {
@@ -488,7 +491,7 @@
       MatcherPtr.reset(new SwitchTypeMatcher(&Cases[0], Cases.size()));
     } else {
       // If we factored and ended up with one case, create it now.
-      MatcherPtr.reset(new CheckTypeMatcher(Cases[0].first));
+      MatcherPtr.reset(new CheckTypeMatcher(Cases[0].first, 0));
       MatcherPtr->setNext(Cases[0].second);
     }
     return;

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=99366&r1=99365&r2=99366&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Tue Mar 23 19:41:19 2010
@@ -296,9 +296,11 @@
     if (!InstPatNode) continue;
     if (InstPatNode->isLeaf()) continue;
 
+    // Ignore multiple result nodes for now.
+    if (InstPatNode->getNumTypes() > 1) continue;
+    
     Record *InstPatOp = InstPatNode->getOperator();
     std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
-    assert(InstPatNode->getNumTypes() <= 1);
     MVT::SimpleValueType RetVT = MVT::isVoid;
     if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0);
     MVT::SimpleValueType VT = RetVT;




From sabre at nondot.org  Tue Mar 23 19:47:47 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 00:47:47 -0000
Subject: [llvm-commits] [llvm] r99369 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.td
Message-ID: <20100324004747.491EF2A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 19:47:47 2010
New Revision: 99369

URL: http://llvm.org/viewvc/llvm-project?rev=99369&view=rev
Log:
Switch SDTUnaryArithWithFlags to being modeled as a two-result
ISD node.  The only change in the generated isel code are comments
like:

<                 // Src: (X86dec_flag:i16 GR16:i16:$src)
---
>                 // Src: (X86dec_flag:i16:i32 GR16:i16:$src)

because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case.  Wewt.


Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=99369&r1=99368&r2=99369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Mar 23 19:47:47 2010
@@ -28,8 +28,9 @@
                                    SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
 
 // Unary and binary operator instructions that set EFLAGS as a side-effect.
-def SDTUnaryArithWithFlags  : SDTypeProfile<1, 1,
-                                            [SDTCisInt<0>]>;
+def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
+                                           [SDTCisInt<0>, SDTCisVT<1, i32>]>;
+
 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
                                             [SDTCisSameAs<0, 1>,
                                              SDTCisSameAs<0, 2>,
@@ -167,6 +168,7 @@
                           [SDNPCommutative]>;
 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
                           [SDNPCommutative]>;
+                          
 def X86inc_flag  : SDNode<"X86ISD::INC",  SDTUnaryArithWithFlags>;
 def X86dec_flag  : SDNode<"X86ISD::DEC",  SDTUnaryArithWithFlags>;
 def X86or_flag   : SDNode<"X86ISD::OR",   SDTBinaryArithWithFlags,




From sabre at nondot.org  Tue Mar 23 19:49:30 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 00:49:30 -0000
Subject: [llvm-commits] [llvm] r99370 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.td
Message-ID: <20100324004930.339662A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 19:49:29 2010
New Revision: 99370

URL: http://llvm.org/viewvc/llvm-project?rev=99370&view=rev
Log:
switch SDTBinaryArithWithFlags to be a multiple-result node as well.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=99370&r1=99369&r2=99370&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Mar 23 19:49:29 2010
@@ -31,10 +31,10 @@
 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
                                            [SDTCisInt<0>, SDTCisVT<1, i32>]>;
 
-def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
-                                            [SDTCisSameAs<0, 1>,
-                                             SDTCisSameAs<0, 2>,
-                                             SDTCisInt<0>]>;
+def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
+                                            [SDTCisSameAs<0, 2>,
+                                             SDTCisSameAs<0, 3>,
+                                             SDTCisInt<0>, SDTCisVT<1, i32>]>;
 def SDTX86BrCond  : SDTypeProfile<0, 3,
                                   [SDTCisVT<0, OtherVT>,
                                    SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;




From sabre at nondot.org  Tue Mar 23 19:53:27 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 00:53:27 -0000
Subject: [llvm-commits] [llvm] r99371 -
	/llvm/trunk/include/llvm/ADT/StringMap.h
Message-ID: <20100324005327.A9FAF2A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 19:53:27 2010
New Revision: 99371

URL: http://llvm.org/viewvc/llvm-project?rev=99371&view=rev
Log:
Add a method to get a StringMapEntry from a pointer to the string
data it contains (similar to GetStringMapEntryFromValue).  
Patch by Greg Clayton!

Modified:
    llvm/trunk/include/llvm/ADT/StringMap.h

Modified: llvm/trunk/include/llvm/ADT/StringMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringMap.h?rev=99371&r1=99370&r2=99371&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/StringMap.h (original)
+++ llvm/trunk/include/llvm/ADT/StringMap.h Tue Mar 23 19:53:27 2010
@@ -216,6 +216,14 @@
   static const StringMapEntry &GetStringMapEntryFromValue(const ValueTy &V) {
     return GetStringMapEntryFromValue(const_cast<ValueTy&>(V));
   }
+  
+  /// GetStringMapEntryFromKeyData - Given key data that is known to be embedded
+  /// into a StringMapEntry, return the StringMapEntry itself.
+  static StringMapEntry &GetStringMapEntryFromKeyData(const char *KeyData) {
+    char *Ptr = const_cast<char*>(KeyData) - sizeof(StringMapEntry<ValueTy>);
+    return *reinterpret_cast<StringMapEntry*>(Ptr);
+  }
+  
 
   /// Destroy - Destroy this StringMapEntry, releasing memory back to the
   /// specified allocator.




From johnny.chen at apple.com  Tue Mar 23 19:54:05 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 23 Mar 2010 17:54:05 -0700
Subject: [llvm-commits] [llvm] r99326 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrNEON.td
In-Reply-To: <965001EB-F442-4602-86B2-90FE8620B3A2@apple.com>
References: <20100323212538.8E13F2A6C12C@llvm.org>
	<965001EB-F442-4602-86B2-90FE8620B3A2@apple.com>
Message-ID: <23F4D5CA-FEE3-430B-BE39-D2B9C931B114@apple.com>

I will rename NVdVmImmFrm to the more proper N2RegFrm.
N2V2 is still necessary, though, because of N2VS, N2VD, N2VQ, which are for vcvt instructions.

On Mar 23, 2010, at 2:45 PM, Bob Wilson wrote:

> 
> On Mar 23, 2010, at 2:25 PM, Johnny Chen wrote:
> 
>> Author: johnny
>> Date: Tue Mar 23 16:25:38 2010
>> New Revision: 99326
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99326&view=rev
>> Log:
>> Add New NEON Format NVdVmVCVTFrm.
>> Converted some of the NEON vcvt instructions to this format.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>   llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99326&r1=99325&r2=99326&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 16:25:38 2010
>> @@ -62,6 +62,7 @@
>> def NLdStFrm                : Format<31>;
>> def NVdImmFrm               : Format<32>;
>> def NVdVmImmFrm             : Format<33>;
>> +def NVdVmVCVTFrm            : Format<34>;
> 
> How about "NVCVTFrm"?
> 
> 
>> 
>> // Misc flags.
>> 
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99326&r1=99325&r2=99326&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 16:25:38 2010
>> @@ -853,25 +853,40 @@
>> // Instruction Classes
>> //===----------------------------------------------------------------------===//
>> 
>> +// Same as N2V except that it doesn't pass a default NVdVmImmFrm to NDataI.
>> +class N2V2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
>> +          bits<5> op11_7, bit op6, bit op4,
>> +          dag oops, dag iops, Format f, InstrItinClass itin,
>> +          string opc, string dt, string asm, string cstr, list<dag> pattern>
>> +  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
>> +  let Inst{24-23} = op24_23;
>> +  let Inst{21-20} = op21_20;
>> +  let Inst{19-18} = op19_18;
>> +  let Inst{17-16} = op17_16;
>> +  let Inst{11-7} = op11_7;
>> +  let Inst{6} = op6;
>> +  let Inst{4} = op4;
>> +}
>> +
> 
> This should not be necessary.  You should not have added the NVdVmImmFrm for N2V to begin with (per my earlier comments).  Please remove this class.
> 
> 
>> // Basic 2-register operations: single-, double- and quad-register.
>> class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>           bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>           string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
>> -        (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
>> -        IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
>> +         (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NVdVmVCVTFrm,
>> +         IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
>> class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>           bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>           string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
>> -        (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
>> -        [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
>> +         (ins DPR:$src), NVdVmVCVTFrm, IIC_VUNAD, OpcodeStr, Dt,"$dst, $src","",
>> +         [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
>> class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>           bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>           string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
>> -        (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
>> -        [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
>> +         (ins QPR:$src), NVdVmVCVTFrm, IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src","",
>> +         [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
>> 
>> // Basic 2-register intrinsics, both double- and quad-register.
>> class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 




From gohman at apple.com  Tue Mar 23 19:53:39 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 24 Mar 2010 00:53:39 -0000
Subject: [llvm-commits] [llvm] r99372 - in /llvm/trunk:
 include/llvm/Target/TargetLowering.h
 lib/CodeGen/SelectionDAG/TargetLowering.cpp
Message-ID: <20100324005339.21DF72A6C12C@llvm.org>

Author: djg
Date: Tue Mar 23 19:53:38 2010
New Revision: 99372

URL: http://llvm.org/viewvc/llvm-project?rev=99372&view=rev
Log:
Remove the ConvertActions table and associated code, which is unused.

Modified:
    llvm/trunk/include/llvm/Target/TargetLowering.h
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=99372&r1=99371&r2=99372&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Tue Mar 23 19:53:38 2010
@@ -469,29 +469,6 @@
        getIndexedStoreAction(IdxMode, VT) == Custom);
   }
 
-  /// getConvertAction - Return how the conversion should be treated:
-  /// either it is legal, needs to be promoted to a larger size, needs to be
-  /// expanded to some other code sequence, or the target has a custom expander
-  /// for it.
-  LegalizeAction
-  getConvertAction(EVT FromVT, EVT ToVT) const {
-    assert((unsigned)FromVT.getSimpleVT().SimpleTy <
-              array_lengthof(ConvertActions) &&
-           (unsigned)ToVT.getSimpleVT().SimpleTy <
-              sizeof(ConvertActions[0])*4 &&
-           "Table isn't big enough!");
-    return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT().SimpleTy] >>
-                             (2*ToVT.getSimpleVT().SimpleTy)) & 3);
-  }
-
-  /// isConvertLegal - Return true if the specified conversion is legal
-  /// on this target.
-  bool isConvertLegal(EVT FromVT, EVT ToVT) const {
-    return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
-      (getConvertAction(FromVT, ToVT) == Legal ||
-       getConvertAction(FromVT, ToVT) == Custom);
-  }
-
   /// getCondCodeAction - Return how the condition code should be treated:
   /// either it is legal, needs to be expanded to some other code sequence,
   /// or the target has a custom expander for it.
@@ -1035,17 +1012,6 @@
     IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action;
   }
   
-  /// setConvertAction - Indicate that the specified conversion does or does
-  /// not work with the with specified type and indicate what to do about it.
-  void setConvertAction(MVT FromVT, MVT ToVT,
-                        LegalizeAction Action) {
-    assert((unsigned)FromVT.SimpleTy < array_lengthof(ConvertActions) &&
-           (unsigned)ToVT.SimpleTy < MVT::LAST_VALUETYPE &&
-           "Table isn't big enough!");
-    ConvertActions[FromVT.SimpleTy] &= ~(uint64_t(3UL)  << ToVT.SimpleTy*2);
-    ConvertActions[FromVT.SimpleTy] |= (uint64_t)Action << ToVT.SimpleTy*2;
-  }
-
   /// setCondCodeAction - Indicate that the specified condition code is or isn't
   /// supported on the target and indicate what to do about it.
   void setCondCodeAction(ISD::CondCode CC, MVT VT,
@@ -1674,13 +1640,6 @@
   /// represents the various modes for load store.
   uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
   
-  /// ConvertActions - For each conversion from source type to destination type,
-  /// keep a LegalizeAction that indicates how instruction selection should
-  /// deal with the conversion.
-  /// Currently, this is used only for floating->floating conversions
-  /// (FP_EXTEND and FP_ROUND).
-  uint64_t ConvertActions[MVT::LAST_VALUETYPE];
-
   /// CondCodeActions - For each condition code (ISD::CondCode) keep a
   /// LegalizeAction that indicates how instruction selection should
   /// deal with the condition code.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=99372&r1=99371&r2=99372&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Mar 23 19:53:38 2010
@@ -475,7 +475,6 @@
   memset(LoadExtActions, 0, sizeof(LoadExtActions));
   memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
   memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
-  memset(ConvertActions, 0, sizeof(ConvertActions));
   memset(CondCodeActions, 0, sizeof(CondCodeActions));
 
   // Set default actions for various operations.




From johnny.chen at apple.com  Tue Mar 23 19:57:50 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Wed, 24 Mar 2010 00:57:50 -0000
Subject: [llvm-commits] [llvm] r99373 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrNEON.td
Message-ID: <20100324005751.1184C2A6C12C@llvm.org>

Author: johnny
Date: Tue Mar 23 19:57:50 2010
New Revision: 99373

URL: http://llvm.org/viewvc/llvm-project?rev=99373&view=rev
Log:
Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
respectively, and add some more comment.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99373&r1=99372&r2=99373&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 19:57:50 2010
@@ -59,10 +59,10 @@
 def MiscFrm       : Format<29>;
 def ThumbMiscFrm  : Format<30>;
 
-def NLdStFrm                : Format<31>;
-def N1RegModImmFrm          : Format<32>;
-def NVdVmImmFrm             : Format<33>;
-def NVdVmVCVTFrm            : Format<34>;
+def NLdStFrm            : Format<31>;
+def N1RegModImmFrm      : Format<32>;
+def N2RegFrm            : Format<33>;
+def NVCVTFrm            : Format<34>;
 
 // Misc flags.
 
@@ -1553,7 +1553,7 @@
           bits<5> op11_7, bit op6, bit op4,
           dag oops, dag iops, InstrItinClass itin,
           string opc, string dt, string asm, string cstr, list<dag> pattern>
-  : NDataI<oops, iops, NVdVmImmFrm, itin, opc, dt, asm, cstr, pattern> {
+  : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
   let Inst{24-23} = op24_23;
   let Inst{21-20} = op21_20;
   let Inst{19-18} = op19_18;
@@ -1568,7 +1568,7 @@
            bits<5> op11_7, bit op6, bit op4,
            dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, string cstr, list<dag> pattern>
-  : NDataXI<oops, iops, NVdVmImmFrm, itin, opc, asm, cstr, pattern> {
+  : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
   let Inst{24-23} = op24_23;
   let Inst{21-20} = op21_20;
   let Inst{19-18} = op19_18;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99373&r1=99372&r2=99373&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 19:57:50 2010
@@ -853,7 +853,7 @@
 // Instruction Classes
 //===----------------------------------------------------------------------===//
 
-// Same as N2V except that it doesn't pass a default NVdVmImmFrm to NDataI.
+// Same as N2V except that it doesn't pass a default N2RegFrm to NDataI.
 class N2V2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
           bits<5> op11_7, bit op6, bit op4,
           dag oops, dag iops, Format f, InstrItinClass itin,
@@ -869,24 +869,24 @@
 }
 
 // Basic 2-register operations: single-, double- and quad-register.
-// This is used for NVdVmVCVTFrm form.
+// This is used for NVCVTFrm form.
 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
   : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
-         (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NVdVmVCVTFrm,
+         (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NVCVTFrm,
          IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
   : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
-         (ins DPR:$src), NVdVmVCVTFrm, IIC_VUNAD, OpcodeStr, Dt,"$dst, $src","",
+         (ins DPR:$src), NVCVTFrm, IIC_VUNAD, OpcodeStr, Dt,"$dst, $src","",
          [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
   : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
-         (ins QPR:$src), NVdVmVCVTFrm, IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src","",
+         (ins QPR:$src), NVCVTFrm, IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src","",
          [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
 
 // Basic 2-register intrinsics, both double- and quad-register.




From sabre at nondot.org  Tue Mar 23 20:02:12 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 01:02:12 -0000
Subject: [llvm-commits] [llvm] r99375 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.td
Message-ID: <20100324010212.6E3E12A6C12C@llvm.org>

Author: lattner
Date: Tue Mar 23 20:02:12 2010
New Revision: 99375

URL: http://llvm.org/viewvc/llvm-project?rev=99375&view=rev
Log:
Switch INC8r to defining its pattern in terms of X86inc_flag
and defining the add pattern with Pat<>, eliminating a use of
parallel.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=99375&r1=99374&r2=99375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Mar 23 20:02:12 2010
@@ -1698,8 +1698,8 @@
 let Defs = [EFLAGS] in {
 let CodeSize = 2 in
 def INC8r  : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
-               [(set GR8:$dst, (add GR8:$src, 1)),
-                (implicit EFLAGS)]>;
+               [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src))]>;
+
 let isConvertibleToThreeAddress = 1, CodeSize = 1 in {  // Can xform into LEA.
 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), 
                "inc{w}\t$dst",
@@ -4875,8 +4875,8 @@
 }
 
 // INC and DEC with EFLAGS result. Note that these do not set CF.
-def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
-          (INC8r GR8:$src)>;
+def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>;
+
 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
           (DEC8r GR8:$src)>;
 




From johnny.chen at apple.com  Tue Mar 23 20:29:25 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Wed, 24 Mar 2010 01:29:25 -0000
Subject: [llvm-commits] [llvm] r99376 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20100324012926.119612A6C12C@llvm.org>

Author: johnny
Date: Tue Mar 23 20:29:25 2010
New Revision: 99376

URL: http://llvm.org/viewvc/llvm-project?rev=99376&view=rev
Log:
Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99376&r1=99375&r2=99376&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 20:29:25 2010
@@ -2778,10 +2778,13 @@
 
 //   VMOV     : Vector Move (Register)
 
+// Mark these as 2-register instructions to help the disassembler.
+let F = N2RegFrm, Form = N2RegFrm.Value in {
 def  VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
-                    IIC_VMOVD, "vmov", "$dst, $src", "", []>;
+                     IIC_VMOVD, "vmov", "$dst, $src", "", []>;
 def  VMOVQ    : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
-                    IIC_VMOVD, "vmov", "$dst, $src", "", []>;
+                     IIC_VMOVD, "vmov", "$dst, $src", "", []>;
+}
 
 //   VMOV     : Vector Move (Immediate)
 




From evan.cheng at apple.com  Tue Mar 23 20:50:28 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 24 Mar 2010 01:50:28 -0000
Subject: [llvm-commits] [llvm] r99378 -
	/llvm/trunk/lib/CodeGen/MachineCSE.cpp
Message-ID: <20100324015028.ED7C02A6C12C@llvm.org>

Author: evancheng
Date: Tue Mar 23 20:50:28 2010
New Revision: 99378

URL: http://llvm.org/viewvc/llvm-project?rev=99378&view=rev
Log:
dbg_value may end a block.

Modified:
    llvm/trunk/lib/CodeGen/MachineCSE.cpp

Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=99378&r1=99377&r2=99378&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Tue Mar 23 20:50:28 2010
@@ -118,14 +118,14 @@
                                         MachineBasicBlock::const_iterator E) {
   unsigned LookAheadLeft = 5;
   while (LookAheadLeft) {
+    // Skip over dbg_value's.
+    while (I != E && I->isDebugValue())
+      ++I;
+
     if (I == E)
       // Reached end of block, register is obviously dead.
       return true;
 
-    // Skip over dbg_value's.
-    while (I->isDebugValue())
-      ++I;
-
     bool SeenDef = false;
     for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
       const MachineOperand &MO = I->getOperand(i);




From evan.cheng at apple.com  Tue Mar 23 22:10:08 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 23 Mar 2010 20:10:08 -0700
Subject: [llvm-commits] [llvm] r99282 - in /llvm/trunk:
	lib/Transforms/Scalar/SimplifyLibCalls.cpp
	lib/Transforms/Utils/BuildLibCalls.cpp
	test/Transforms/SimplifyLibCalls/StrCpy.ll
In-Reply-To: <8BA006A9-CBB5-497A-BADA-D5B5B1A14F5F@apple.com>
References: <20100323154804.931872A6C12C@llvm.org>
	<8BA006A9-CBB5-497A-BADA-D5B5B1A14F5F@apple.com>
Message-ID: <35161F28-7FBD-4144-BC41-BA40BE9F6618@apple.com>


On Mar 23, 2010, at 2:42 PM, Chris Lattner wrote:

> 
> On Mar 23, 2010, at 8:48 AM, Evan Cheng wrote:
> 
>> Author: evancheng
>> Date: Tue Mar 23 10:48:04 2010
>> New Revision: 99282
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99282&view=rev
>> Log:
>> Teach simplify libcall to transform __strcpy_chk to __memcpy_chk to enable optimizations down stream.
> 
> Hi Evan,
> 
>> +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Tue Mar 23 10:48:04 2010
>> @@ -49,10 +49,13 @@
>>  Function *Caller;
>>  const TargetData *TD;
>>  LLVMContext* Context;
>> +  bool OptChkCall;  // True if it's optimizing a *_chk libcall.
> 
> This is state is not appropriate to add to LibCallOptimization.  If you want to do this, it should be added as a constructor option to StrCpyOpt.

Why is it inappropriate? I can't add it to the constructor option because optimization objects are ivars. I can't construct it with "StrCpyOpt StrCpyChk(true);". And I don't want to heap allocate them.

Evan

> 
> -Chris
> 
>> public:
>> -  LibCallOptimization() { }
>> +  LibCallOptimization() : OptChkCall(false) { }
>>  virtual ~LibCallOptimization() {}
>> 
>> +  void setOptChkCall(bool c) { OptChkCall = c; }
>> +
>>  /// CallOptimizer - This pure virtual method is implemented by base classes to
>>  /// do various optimizations.  If this returns null then no transformation was
>>  /// performed.  If it returns CI, then it transformed the call and CI is to be
>> @@ -352,8 +355,10 @@
>> struct StrCpyOpt : public LibCallOptimization {
>>  virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
>>    // Verify the "strcpy" function prototype.
>> +    unsigned NumParams = OptChkCall ? 3 : 2;
>>    const FunctionType *FT = Callee->getFunctionType();
>> -    if (FT->getNumParams() != 2 || FT->getReturnType() != FT->getParamType(0) ||
>> +    if (FT->getNumParams() != NumParams ||
>> +        FT->getReturnType() != FT->getParamType(0) ||
>>        FT->getParamType(0) != FT->getParamType(1) ||
>>        FT->getParamType(0) != Type::getInt8PtrTy(*Context))
>>      return 0;
>> @@ -371,8 +376,13 @@
>> 
>>    // We have enough information to now generate the memcpy call to do the
>>    // concatenation for us.  Make a memcpy to copy the nul byte with align = 1.
>> -    EmitMemCpy(Dst, Src,
>> -               ConstantInt::get(TD->getIntPtrType(*Context), Len), 1, B, TD);
>> +    if (OptChkCall)
>> +      EmitMemCpyChk(Dst, Src,
>> +                    ConstantInt::get(TD->getIntPtrType(*Context), Len),
>> +                    CI->getOperand(3), B, TD);
>> +    else
>> +      EmitMemCpy(Dst, Src,
>> +                 ConstantInt::get(TD->getIntPtrType(*Context), Len), 1, B, TD);
>>    return Dst;
>>  }
>> };
>> @@ -1162,7 +1172,8 @@
>>    StringMap<LibCallOptimization*> Optimizations;
>>    // String and Memory LibCall Optimizations
>>    StrCatOpt StrCat; StrNCatOpt StrNCat; StrChrOpt StrChr; StrCmpOpt StrCmp;
>> -    StrNCmpOpt StrNCmp; StrCpyOpt StrCpy; StrNCpyOpt StrNCpy; StrLenOpt StrLen;
>> +    StrNCmpOpt StrNCmp; StrCpyOpt StrCpy; StrCpyOpt StrCpyChk;
>> +    StrNCpyOpt StrNCpy; StrLenOpt StrLen;
>>    StrToOpt StrTo; StrStrOpt StrStr;
>>    MemCmpOpt MemCmp; MemCpyOpt MemCpy; MemMoveOpt MemMove; MemSetOpt MemSet;
>>    // Math Library Optimizations
>> @@ -1228,6 +1239,10 @@
>>  Optimizations["memmove"] = &MemMove;
>>  Optimizations["memset"] = &MemSet;
>> 
>> +  // _chk variants of String and Memory LibCall Optimizations.
>> +  StrCpyChk.setOptChkCall(true);
>> +  Optimizations["__strcpy_chk"] = &StrCpyChk;
>> +
>>  // Math Library Optimizations
>>  Optimizations["powf"] = &Pow;
>>  Optimizations["pow"] = &Pow;
>> 
>> Modified: llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp?rev=99282&r1=99281&r2=99282&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp (original)
>> +++ llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp Tue Mar 23 10:48:04 2010
>> @@ -108,7 +108,7 @@
>> 
>> 
>> /// EmitMemCpy - Emit a call to the memcpy function to the builder.  This always
>> -/// expects that the size has type 'intptr_t' and Dst/Src are pointers.
>> +/// expects that Len has type 'intptr_t' and Dst/Src are pointers.
>> Value *llvm::EmitMemCpy(Value *Dst, Value *Src, Value *Len,
>>                        unsigned Align, IRBuilder<> &B, const TargetData *TD) {
>>  Module *M = B.GetInsertBlock()->getParent()->getParent();
>> @@ -120,6 +120,30 @@
>>                       ConstantInt::get(B.getInt32Ty(), Align));
>> }
>> 
>> +/// EmitMemCpyChk - Emit a call to the __memcpy_chk function to the builder.
>> +/// This expects that the Len and ObjSize have type 'intptr_t' and Dst/Src
>> +/// are pointers.
>> +Value *llvm::EmitMemCpyChk(Value *Dst, Value *Src, Value *Len, Value *ObjSize,
>> +                           IRBuilder<> &B, const TargetData *TD) {
>> +  Module *M = B.GetInsertBlock()->getParent()->getParent();
>> +  AttributeWithIndex AWI;
>> +  AWI = AttributeWithIndex::get(~0u, Attribute::NoUnwind);
>> +  LLVMContext &Context = B.GetInsertBlock()->getContext();
>> +  Value *MemCpy = M->getOrInsertFunction("__memcpy_chk",
>> +                                         AttrListPtr::get(&AWI, 1),
>> +                                         B.getInt8PtrTy(),
>> +                                         B.getInt8PtrTy(),
>> +                                         B.getInt8PtrTy(),
>> +                                         TD->getIntPtrType(Context),
>> +                                         TD->getIntPtrType(Context), NULL);
>> +  Dst = CastToCStr(Dst, B);
>> +  Src = CastToCStr(Src, B);
>> +  CallInst *CI = B.CreateCall4(MemCpy, Dst, Src, Len, ObjSize);
>> +  if (const Function *F = dyn_cast<Function>(MemCpy->stripPointerCasts()))
>> +    CI->setCallingConv(F->getCallingConv());
>> +  return CI;
>> +}
>> +
>> /// EmitMemMove - Emit a call to the memmove function to the builder.  This
>> /// always expects that the size has type 'intptr_t' and Dst/Src are pointers.
>> Value *llvm::EmitMemMove(Value *Dst, Value *Src, Value *Len,
>> 
>> Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/StrCpy.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/StrCpy.ll?rev=99282&r1=99281&r2=99282&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/Transforms/SimplifyLibCalls/StrCpy.ll (original)
>> +++ llvm/trunk/test/Transforms/SimplifyLibCalls/StrCpy.ll Tue Mar 23 10:48:04 2010
>> @@ -1,30 +1,37 @@
>> ; Test that the StrCpyOptimizer works correctly
>> -; RUN: opt < %s -simplify-libcalls -S | \
>> -; RUN:   not grep {call.*strcpy}
>> +; RUN: opt < %s -simplify-libcalls -S | FileCheck %s
>> 
>> ; This transformation requires the pointer size, as it assumes that size_t is
>> ; the size of a pointer.
>> -target datalayout = "-p:64:64:64"
>> +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
>> 
>> - at hello = constant [6 x i8] c"hello\00"		; <[6 x i8]*> [#uses=1]
>> - at null = constant [1 x i8] zeroinitializer		; <[1 x i8]*> [#uses=1]
>> - at null_hello = constant [7 x i8] c"\00hello\00"		; <[7 x i8]*> [#uses=1]
>> + at hello = constant [6 x i8] c"hello\00"
>> 
>> declare i8* @strcpy(i8*, i8*)
>> 
>> -declare i32 @puts(i8*)
>> +declare i8* @__strcpy_chk(i8*, i8*, i32) nounwind
>> 
>> -define i32 @main() {
>> -	%target = alloca [1024 x i8]		; <[1024 x i8]*> [#uses=1]
>> -	%arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0		; <i8*> [#uses=2]
>> -	store i8 0, i8* %arg1
>> -	%arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0		; <i8*> [#uses=1]
>> -	%rslt1 = call i8* @strcpy( i8* %arg1, i8* %arg2 )		; <i8*> [#uses=1]
>> -	%arg3 = getelementptr [1 x i8]* @null, i32 0, i32 0		; <i8*> [#uses=1]
>> -	%rslt2 = call i8* @strcpy( i8* %rslt1, i8* %arg3 )		; <i8*> [#uses=1]
>> -	%arg4 = getelementptr [7 x i8]* @null_hello, i32 0, i32 0		; <i8*> [#uses=1]
>> -	%rslt3 = call i8* @strcpy( i8* %rslt2, i8* %arg4 )		; <i8*> [#uses=1]
>> -	call i32 @puts( i8* %rslt3 )		; <i32>:1 [#uses=0]
>> -	ret i32 0
>> +declare i32 @llvm.objectsize.i32(i8*, i1) nounwind readonly
>> +
>> +; rdar://6839935
>> +
>> +define i32 @t1() {
>> +; CHECK: @t1
>> +  %target = alloca [1024 x i8]
>> +  %arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0
>> +  %arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0
>> +  %rslt1 = call i8* @strcpy( i8* %arg1, i8* %arg2 )
>> +; CHECK: @llvm.memcpy.i32
>> +  ret i32 0
>> }
>> 
>> +define i32 @t2() {
>> +; CHECK: @t2
>> +  %target = alloca [1024 x i8]
>> +  %arg1 = getelementptr [1024 x i8]* %target, i32 0, i32 0
>> +  %arg2 = getelementptr [6 x i8]* @hello, i32 0, i32 0
>> +  %tmp1 = call i32 @llvm.objectsize.i32(i8* %arg1, i1 false)
>> +  %rslt1 = call i8* @__strcpy_chk(i8* %arg1, i8* %arg2, i32 %tmp1)
>> +; CHECK: @__memcpy_chk
>> +  ret i32 0
>> +}
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 




From daniel at zuster.org  Tue Mar 23 22:43:40 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 24 Mar 2010 03:43:40 -0000
Subject: [llvm-commits] [llvm] r99380 - in /llvm/trunk:
 include/llvm/MC/MCAsmLayout.h include/llvm/MC/MCAssembler.h
 include/llvm/MC/MCObjectWriter.h include/llvm/MC/MachObjectWriter.h
 lib/MC/MCAssembler.cpp lib/MC/MCExpr.cpp lib/MC/MachObjectWriter.cpp
Message-ID: <20100324034340.B51E42A6C12C@llvm.org>

Author: ddunbar
Date: Tue Mar 23 22:43:40 2010
New Revision: 99380

URL: http://llvm.org/viewvc/llvm-project?rev=99380&view=rev
Log:
MC: Direct all {fragment,section,symbol} address access through the MCAsmLayout object.

Modified:
    llvm/trunk/include/llvm/MC/MCAsmLayout.h
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/include/llvm/MC/MCObjectWriter.h
    llvm/trunk/include/llvm/MC/MachObjectWriter.h
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MCExpr.cpp
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/include/llvm/MC/MCAsmLayout.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmLayout.h?rev=99380&r1=99379&r2=99380&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmLayout.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmLayout.h Tue Mar 23 22:43:40 2010
@@ -12,6 +12,9 @@
 
 namespace llvm {
 class MCAssembler;
+class MCFragment;
+class MCSectionData;
+class MCSymbolData;
 
 /// Encapsulates the layout of an assembly file at a particular point in time.
 ///
@@ -29,6 +32,14 @@
 
   /// Get the assembler object this is a layout for.
   MCAssembler &getAssembler() const { return Assembler; }
+
+  uint64_t getFragmentAddress(const MCFragment *F) const;
+
+  uint64_t getSectionAddress(const MCSectionData *SD) const;
+
+  uint64_t getSymbolAddress(const MCSymbolData *SD) const;
+
+  void setSectionAddress(MCSectionData *SD, uint64_t Value);
 };
 
 } // end namespace llvm

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99380&r1=99379&r2=99380&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Tue Mar 23 22:43:40 2010
@@ -699,15 +699,17 @@
   /// Find the symbol which defines the atom containing given address, inside
   /// the given section, or null if there is no such symbol.
   //
-  // FIXME: Eliminate this, it is very slow.
-  const MCSymbolData *getAtomForAddress(const MCSectionData *Section,
+  // FIXME-PERF: Eliminate this, it is very slow.
+  const MCSymbolData *getAtomForAddress(const MCAsmLayout &Layout,
+                                        const MCSectionData *Section,
                                         uint64_t Address) const;
 
   /// Find the symbol which defines the atom containing the given symbol, or
   /// null if there is no such symbol.
   //
-  // FIXME: Eliminate this, it is very slow.
-  const MCSymbolData *getAtom(const MCSymbolData *Symbol) const;
+  // FIXME-PERF: Eliminate this, it is very slow.
+  const MCSymbolData *getAtom(const MCAsmLayout &Layout,
+                              const MCSymbolData *Symbol) const;
 
   /// Check whether a particular symbol is visible to the linker and is required
   /// in the symbol table, or whether it can be discarded by the assembler. This

Modified: llvm/trunk/include/llvm/MC/MCObjectWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectWriter.h?rev=99380&r1=99379&r2=99380&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCObjectWriter.h (original)
+++ llvm/trunk/include/llvm/MC/MCObjectWriter.h Tue Mar 23 22:43:40 2010
@@ -16,6 +16,7 @@
 
 namespace llvm {
 class MCAsmFixup;
+class MCAsmLayout;
 class MCAssembler;
 class MCFragment;
 class MCValue;
@@ -69,6 +70,7 @@
   /// information about the relocation so that it can be emitted during
   /// WriteObject().
   virtual void RecordRelocation(const MCAssembler &Asm,
+                                const MCAsmLayout &Layout,
                                 const MCFragment *Fragment,
                                 const MCAsmFixup &Fixup, MCValue Target,
                                 uint64_t &FixedValue) = 0;
@@ -78,7 +80,8 @@
   /// This routine is called by the assembler after layout and relaxation is
   /// complete, fixups have been evaluate and applied, and relocations
   /// generated.
-  virtual void WriteObject(const MCAssembler &Asm) = 0;
+  virtual void WriteObject(const MCAssembler &Asm,
+                           const MCAsmLayout &Layout) = 0;
 
   /// @}
   /// @name Binary Output

Modified: llvm/trunk/include/llvm/MC/MachObjectWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MachObjectWriter.h?rev=99380&r1=99379&r2=99380&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MachObjectWriter.h (original)
+++ llvm/trunk/include/llvm/MC/MachObjectWriter.h Tue Mar 23 22:43:40 2010
@@ -31,11 +31,12 @@
   virtual void ExecutePostLayoutBinding(MCAssembler &Asm);
 
   virtual void RecordRelocation(const MCAssembler &Asm,
+                                const MCAsmLayout &Layout,
                                 const MCFragment *Fragment,
                                 const MCAsmFixup &Fixup, MCValue Target,
                                 uint64_t &FixedValue);
 
-  virtual void WriteObject(const MCAssembler &Asm);
+  virtual void WriteObject(const MCAssembler &Asm, const MCAsmLayout &Layout);
 };
 
 } // End llvm namespace

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99380&r1=99379&r2=99380&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Tue Mar 23 22:43:40 2010
@@ -45,6 +45,24 @@
 
 /* *** */
 
+uint64_t MCAsmLayout::getFragmentAddress(const MCFragment *F) const {
+  return F->getAddress();
+}
+
+uint64_t MCAsmLayout::getSymbolAddress(const MCSymbolData *SD) const {
+  return SD->getAddress();
+}
+
+uint64_t MCAsmLayout::getSectionAddress(const MCSectionData *SD) const {
+  return SD->getAddress();
+}
+
+void MCAsmLayout::setSectionAddress(MCSectionData *SD, uint64_t Value) {
+  SD->setAddress(Value);
+}
+
+/* *** */
+
 MCFragment::MCFragment() : Kind(FragmentType(~0)) {
 }
 
@@ -145,6 +163,7 @@
 }
 
 static bool isScatteredFixupFullyResolved(const MCAssembler &Asm,
+                                          const MCAsmLayout &Layout,
                                           const MCAsmFixup &Fixup,
                                           const MCValue Target,
                                           const MCSymbolData *BaseSymbol) {
@@ -165,7 +184,7 @@
     if (A->getKind() != MCSymbolRefExpr::VK_None)
       return false;
 
-    A_Base = Asm.getAtom(&Asm.getSymbolData(A->getSymbol()));
+    A_Base = Asm.getAtom(Layout, &Asm.getSymbolData(A->getSymbol()));
     if (!A_Base)
       return false;
   }
@@ -175,7 +194,7 @@
     if (B->getKind() != MCSymbolRefExpr::VK_None)
       return false;
 
-    B_Base = Asm.getAtom(&Asm.getSymbolData(B->getSymbol()));
+    B_Base = Asm.getAtom(Layout, &Asm.getSymbolData(B->getSymbol()));
     if (!B_Base)
       return false;
   }
@@ -203,9 +222,13 @@
     SD->getFragment()->getParent()->getSection());
 }
 
-const MCSymbolData *MCAssembler::getAtomForAddress(const MCSectionData *Section,
+// FIXME-PERF: This routine is really slow.
+const MCSymbolData *MCAssembler::getAtomForAddress(const MCAsmLayout &Layout,
+                                                   const MCSectionData *Section,
                                                    uint64_t Address) const {
   const MCSymbolData *Best = 0;
+  uint64_t BestAddress = 0;
+
   for (MCAssembler::const_symbol_iterator it = symbol_begin(),
          ie = symbol_end(); it != ie; ++it) {
     // Ignore non-linker visible symbols.
@@ -218,15 +241,19 @@
 
     // Otherwise, find the closest symbol preceding this address (ties are
     // resolved in favor of the last defined symbol).
-    if (it->getAddress() <= Address &&
-        (!Best || it->getAddress() >= Best->getAddress()))
+    uint64_t SymbolAddress = Layout.getSymbolAddress(it);
+    if (SymbolAddress <= Address && (!Best || SymbolAddress >= BestAddress)) {
       Best = it;
+      BestAddress = SymbolAddress;
+    }
   }
 
   return Best;
 }
 
-const MCSymbolData *MCAssembler::getAtom(const MCSymbolData *SD) const {
+// FIXME-PERF: This routine is really slow.
+const MCSymbolData *MCAssembler::getAtom(const MCAsmLayout &Layout,
+                                         const MCSymbolData *SD) const {
   // Linker visible symbols define atoms.
   if (isSymbolLinkerVisible(SD))
     return SD;
@@ -236,7 +263,8 @@
     return 0;
 
   // Otherwise, search by address.
-  return getAtomForAddress(SD->getFragment()->getParent(), SD->getAddress());
+  return getAtomForAddress(Layout, SD->getFragment()->getParent(),
+                           Layout.getSymbolAddress(SD));
 }
 
 bool MCAssembler::EvaluateFixup(const MCAsmLayout &Layout,
@@ -258,13 +286,13 @@
   bool IsResolved = true;
   if (const MCSymbolRefExpr *A = Target.getSymA()) {
     if (A->getSymbol().isDefined())
-      Value += getSymbolData(A->getSymbol()).getAddress();
+      Value += Layout.getSymbolAddress(&getSymbolData(A->getSymbol()));
     else
       IsResolved = false;
   }
   if (const MCSymbolRefExpr *B = Target.getSymB()) {
     if (B->getSymbol().isDefined())
-      Value -= getSymbolData(B->getSymbol()).getAddress();
+      Value -= Layout.getSymbolAddress(&getSymbolData(B->getSymbol()));
     else
       IsResolved = false;
   }
@@ -278,13 +306,13 @@
       const MCSymbolData *BaseSymbol = 0;
       if (IsPCRel) {
         BaseSymbol = getAtomForAddress(
-          DF->getParent(), DF->getAddress() + Fixup.Offset);
+          Layout, DF->getParent(), Layout.getFragmentAddress(DF)+Fixup.Offset);
         if (!BaseSymbol)
           IsResolved = false;
       }
 
       if (IsResolved)
-        IsResolved = isScatteredFixupFullyResolved(*this, Fixup, Target,
+        IsResolved = isScatteredFixupFullyResolved(*this, Layout, Fixup, Target,
                                                    BaseSymbol);
     } else {
       const MCSection *BaseSection = 0;
@@ -297,19 +325,19 @@
   }
 
   if (IsPCRel)
-    Value -= DF->getAddress() + Fixup.Offset;
+    Value -= Layout.getFragmentAddress(DF) + Fixup.Offset;
 
   return IsResolved;
 }
 
 void MCAssembler::LayoutSection(MCSectionData &SD,
                                 MCAsmLayout &Layout) {
-  uint64_t Address = SD.getAddress();
+  uint64_t Address, StartAddress = Address = Layout.getSectionAddress(&SD);
 
   for (MCSectionData::iterator it = SD.begin(), ie = SD.end(); it != ie; ++it) {
     MCFragment &F = *it;
 
-    F.setOffset(Address - SD.getAddress());
+    F.setOffset(Address - StartAddress);
 
     // Evaluate fragment size.
     switch (F.getKind()) {
@@ -361,7 +389,7 @@
       // Align the fragment offset; it is safe to adjust the offset freely since
       // this is only in virtual sections.
       Address = RoundUpToAlignment(Address, ZFF.getAlignment());
-      F.setOffset(Address - SD.getAddress());
+      F.setOffset(Address - StartAddress);
 
       // FIXME: This is misnamed.
       F.setFileSize(ZFF.getSize());
@@ -373,11 +401,11 @@
   }
 
   // Set the section sizes.
-  SD.setSize(Address - SD.getAddress());
+  SD.setSize(Address - StartAddress);
   if (getBackend().isVirtualSection(SD.getSection()))
     SD.setFileSize(0);
   else
-    SD.setFileSize(Address - SD.getAddress());
+    SD.setFileSize(Address - StartAddress);
 }
 
 /// WriteFragmentData - Write the \arg F data to the output file.
@@ -543,7 +571,7 @@
           // The fixup was unresolved, we need a relocation. Inform the object
           // writer of the relocation, and give it an opportunity to adjust the
           // fixup value if need be.
-          Writer->RecordRelocation(*this, DF, Fixup, Target, FixedValue);
+          Writer->RecordRelocation(*this, Layout, DF, Fixup, Target,FixedValue);
         }
 
         getBackend().ApplyFixup(Fixup, *DF, FixedValue);
@@ -552,7 +580,7 @@
   }
 
   // Write the object file.
-  Writer->WriteObject(*this);
+  Writer->WriteObject(*this, Layout);
   OS.flush();
 
   stats::ObjectBytes += OS.tell() - StartOffset;
@@ -609,7 +637,7 @@
     }
 
     // Layout the section fragments and its size.
-    SD.setAddress(Address);
+    Layout.setSectionAddress(&SD, Address);
     LayoutSection(SD, Layout);
     Address += SD.getFileSize();
 
@@ -628,7 +656,7 @@
     if (uint64_t Pad = OffsetToAlignment(Address, it->getAlignment()))
       Address += Pad;
 
-    SD.setAddress(Address);
+    Layout.setSectionAddress(&SD, Address);
     LayoutSection(SD, Layout);
     Address += SD.getSize();
   }

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=99380&r1=99379&r2=99380&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Tue Mar 23 22:43:40 2010
@@ -268,8 +268,8 @@
           Layout->getAssembler().getSymbolData(Res.getSymA()->getSymbol());
         MCSymbolData &B =
           Layout->getAssembler().getSymbolData(Res.getSymB()->getSymbol());
-        Res = MCValue::get(+ A.getFragment()->getAddress() + A.getOffset()
-                           - B.getFragment()->getAddress() - B.getOffset()
+        Res = MCValue::get(+ Layout->getSymbolAddress(&A) + A.getOffset()
+                           - Layout->getSymbolAddress(&B) - B.getOffset()
                            + Res.getConstant());
       }
 

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=99380&r1=99379&r2=99380&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Tue Mar 23 22:43:40 2010
@@ -11,6 +11,7 @@
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCAsmLayout.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSectionMachO.h"
@@ -271,9 +272,9 @@
     assert(OS.tell() - Start == SegmentLoadCommandSize);
   }
 
-  void WriteSection(const MCAssembler &Asm, const MCSectionData &SD,
-                    uint64_t FileOffset, uint64_t RelocationsStart,
-                    unsigned NumRelocations) {
+  void WriteSection(const MCAssembler &Asm, const MCAsmLayout &Layout,
+                    const MCSectionData &SD, uint64_t FileOffset,
+                    uint64_t RelocationsStart, unsigned NumRelocations) {
     // The offset is unused for virtual sections.
     if (Asm.getBackend().isVirtualSection(SD.getSection())) {
       assert(SD.getFileSize() == 0 && "Invalid file size!");
@@ -292,10 +293,10 @@
     WriteBytes(Section.getSectionName(), 16);
     WriteBytes(Section.getSegmentName(), 16);
     if (Is64Bit) {
-      Write64(SD.getAddress()); // address
+      Write64(Layout.getSectionAddress(&SD)); // address
       Write64(SD.getSize()); // size
     } else {
-      Write32(SD.getAddress()); // address
+      Write32(Layout.getSectionAddress(&SD)); // address
       Write32(SD.getSize()); // size
     }
     Write32(FileOffset);
@@ -372,7 +373,7 @@
     assert(OS.tell() - Start == DysymtabLoadCommandSize);
   }
 
-  void WriteNlist(MachSymbolData &MSD) {
+  void WriteNlist(MachSymbolData &MSD, const MCAsmLayout &Layout) {
     MCSymbolData &Data = *MSD.SymbolData;
     const MCSymbol &Symbol = Data.getSymbol();
     uint8_t Type = 0;
@@ -403,7 +404,7 @@
       if (Symbol.isAbsolute()) {
         llvm_unreachable("FIXME: Not yet implemented!");
       } else {
-        Address = Data.getAddress();
+        Address = Layout.getSymbolAddress(&Data);
       }
     } else if (Data.isCommon()) {
       // Common symbols are encoded with the size in the address
@@ -451,7 +452,7 @@
   //  - Input errors, where something cannot be correctly encoded. 'as' allows
   //    these through in many cases.
 
-  void RecordX86_64Relocation(const MCAssembler &Asm,
+  void RecordX86_64Relocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
                               const MCFragment *Fragment,
                               const MCAsmFixup &Fixup, MCValue Target,
                               uint64_t &FixedValue) {
@@ -494,11 +495,11 @@
     } else if (Target.getSymB()) { // A - B + constant
       const MCSymbol *A = &Target.getSymA()->getSymbol();
       MCSymbolData &A_SD = Asm.getSymbolData(*A);
-      const MCSymbolData *A_Base = Asm.getAtom(&A_SD);
+      const MCSymbolData *A_Base = Asm.getAtom(Layout, &A_SD);
 
       const MCSymbol *B = &Target.getSymB()->getSymbol();
       MCSymbolData &B_SD = Asm.getSymbolData(*B);
-      const MCSymbolData *B_Base = Asm.getAtom(&B_SD);
+      const MCSymbolData *B_Base = Asm.getAtom(Layout, &B_SD);
 
       // Neither symbol can be modified.
       if (Target.getSymA()->getKind() != MCSymbolRefExpr::VK_None ||
@@ -521,8 +522,8 @@
       if (A_Base == B_Base)
         llvm_report_error("unsupported relocation with identical base");
 
-      Value += A_SD.getAddress() - A_Base->getAddress();
-      Value -= B_SD.getAddress() - B_Base->getAddress();
+      Value += Layout.getSymbolAddress(&A_SD) - Layout.getSymbolAddress(A_Base);
+      Value -= Layout.getSymbolAddress(&B_SD) - Layout.getSymbolAddress(B_Base);
 
       Index = A_Base->getIndex();
       IsExtern = 1;
@@ -543,7 +544,7 @@
     } else {
       const MCSymbol *Symbol = &Target.getSymA()->getSymbol();
       MCSymbolData &SD = Asm.getSymbolData(*Symbol);
-      const MCSymbolData *Base = Asm.getAtom(&SD);
+      const MCSymbolData *Base = Asm.getAtom(Layout, &SD);
 
       // x86_64 almost always uses external relocations, except when there is no
       // symbol to use as a base address (a local symbol with no preceeding
@@ -554,7 +555,7 @@
 
         // Add the local offset, if needed.
         if (Base != &SD)
-          Value += SD.getAddress() - Base->getAddress();
+          Value += Layout.getSymbolAddress(&SD) - Layout.getSymbolAddress(Base);
       } else {
         // The index is the section ordinal.
         //
@@ -566,7 +567,7 @@
             break;
         assert(it != ie && "Unable to find section index!");
         IsExtern = 0;
-        Value += SD.getAddress();
+        Value += Layout.getSymbolAddress(&SD);
 
         if (IsPCRel)
           Value -= Address + (1 << Log2Size);
@@ -640,6 +641,7 @@
   }
 
   void RecordScatteredRelocation(const MCAssembler &Asm,
+                                 const MCAsmLayout &Layout,
                                  const MCFragment *Fragment,
                                  const MCAsmFixup &Fixup, MCValue Target,
                                  uint64_t &FixedValue) {
@@ -656,7 +658,7 @@
       llvm_report_error("symbol '" + A->getName() +
                         "' can not be undefined in a subtraction expression");
 
-    uint32_t Value = A_SD->getAddress();
+    uint32_t Value = Layout.getSymbolAddress(A_SD);
     uint32_t Value2 = 0;
 
     if (const MCSymbolRefExpr *B = Target.getSymB()) {
@@ -672,7 +674,7 @@
       // relocation types from the linkers point of view, this is done solely
       // for pedantic compatibility with 'as'.
       Type = A_SD->isExternal() ? RIT_Difference : RIT_LocalDifference;
-      Value2 = B_SD->getAddress();
+      Value2 = Layout.getSymbolAddress(B_SD);
     }
 
     // Relocations are written out in reverse order, so the PAIR comes first.
@@ -697,11 +699,11 @@
     Relocations[Fragment->getParent()].push_back(MRE);
   }
 
-  void RecordRelocation(const MCAssembler &Asm, const MCFragment *Fragment,
-                        const MCAsmFixup &Fixup, MCValue Target,
-                        uint64_t &FixedValue) {
+  void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
+                        const MCFragment *Fragment, const MCAsmFixup &Fixup,
+                        MCValue Target, uint64_t &FixedValue) {
     if (Is64Bit) {
-      RecordX86_64Relocation(Asm, Fragment, Fixup, Target, FixedValue);
+      RecordX86_64Relocation(Asm, Layout, Fragment, Fixup, Target, FixedValue);
       return;
     }
 
@@ -716,7 +718,7 @@
     if (Target.getSymB() ||
         (Target.getSymA() && !Target.getSymA()->getSymbol().isUndefined() &&
          Offset)) {
-      RecordScatteredRelocation(Asm, Fragment, Fixup, Target, FixedValue);
+      RecordScatteredRelocation(Asm, Layout, Fragment, Fixup,Target,FixedValue);
       return;
     }
 
@@ -752,7 +754,7 @@
           if (&*it == SD->getFragment()->getParent())
             break;
         assert(it != ie && "Unable to find section index!");
-        Value = SD->getAddress();
+        Value = Layout.getSymbolAddress(SD);
       }
 
       Type = RIT_Vanilla;
@@ -934,7 +936,7 @@
                        UndefinedSymbolData);
   }
 
-  void WriteObject(const MCAssembler &Asm) {
+  void WriteObject(const MCAssembler &Asm, const MCAsmLayout &Layout) {
     unsigned NumSections = Asm.size();
 
     // The section data starts after the header, the segment load command (and
@@ -962,16 +964,16 @@
     for (MCAssembler::const_iterator it = Asm.begin(),
            ie = Asm.end(); it != ie; ++it) {
       const MCSectionData &SD = *it;
+      uint64_t Address = Layout.getSectionAddress(&SD);
 
-      VMSize = std::max(VMSize, SD.getAddress() + SD.getSize());
+      VMSize = std::max(VMSize, Address + SD.getSize());
 
       if (Asm.getBackend().isVirtualSection(SD.getSection()))
         continue;
 
-      SectionDataSize = std::max(SectionDataSize,
-                                 SD.getAddress() + SD.getSize());
+      SectionDataSize = std::max(SectionDataSize, Address + SD.getSize());
       SectionDataFileSize = std::max(SectionDataFileSize,
-                                     SD.getAddress() + SD.getFileSize());
+                                     Address + SD.getFileSize());
     }
 
     // The section data is padded to 4 bytes.
@@ -992,8 +994,8 @@
            ie = Asm.end(); it != ie; ++it) {
       std::vector<MachRelocationEntry> &Relocs = Relocations[it];
       unsigned NumRelocs = Relocs.size();
-      uint64_t SectionStart = SectionDataStart + it->getAddress();
-      WriteSection(Asm, *it, SectionStart, RelocTableEnd, NumRelocs);
+      uint64_t SectionStart = SectionDataStart + Layout.getSectionAddress(it);
+      WriteSection(Asm, Layout, *it, SectionStart, RelocTableEnd, NumRelocs);
       RelocTableEnd += NumRelocs * RelocationInfoSize;
     }
 
@@ -1080,11 +1082,11 @@
 
       // Write the symbol table entries.
       for (unsigned i = 0, e = LocalSymbolData.size(); i != e; ++i)
-        WriteNlist(LocalSymbolData[i]);
+        WriteNlist(LocalSymbolData[i], Layout);
       for (unsigned i = 0, e = ExternalSymbolData.size(); i != e; ++i)
-        WriteNlist(ExternalSymbolData[i]);
+        WriteNlist(ExternalSymbolData[i], Layout);
       for (unsigned i = 0, e = UndefinedSymbolData.size(); i != e; ++i)
-        WriteNlist(UndefinedSymbolData[i]);
+        WriteNlist(UndefinedSymbolData[i], Layout);
 
       // Write the string table.
       OS << StringTable.str();
@@ -1111,13 +1113,15 @@
 }
 
 void MachObjectWriter::RecordRelocation(const MCAssembler &Asm,
+                                        const MCAsmLayout &Layout,
                                         const MCFragment *Fragment,
                                         const MCAsmFixup &Fixup, MCValue Target,
                                         uint64_t &FixedValue) {
-  ((MachObjectWriterImpl*) Impl)->RecordRelocation(Asm, Fragment, Fixup,
+  ((MachObjectWriterImpl*) Impl)->RecordRelocation(Asm, Layout, Fragment, Fixup,
                                                    Target, FixedValue);
 }
 
-void MachObjectWriter::WriteObject(const MCAssembler &Asm) {
-  ((MachObjectWriterImpl*) Impl)->WriteObject(Asm);
+void MachObjectWriter::WriteObject(const MCAssembler &Asm,
+                                   const MCAsmLayout &Layout) {
+  ((MachObjectWriterImpl*) Impl)->WriteObject(Asm, Layout);
 }




From baldrick at free.fr  Wed Mar 24 04:05:14 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 24 Mar 2010 09:05:14 -0000
Subject: [llvm-commits] [llvm] r99392 - /llvm/trunk/lib/Support/Triple.cpp
Message-ID: <20100324090514.C07C72A6C12C@llvm.org>

Author: baldrick
Date: Wed Mar 24 04:05:14 2010
New Revision: 99392

URL: http://llvm.org/viewvc/llvm-project?rev=99392&view=rev
Log:
Fix comment typo.

Modified:
    llvm/trunk/lib/Support/Triple.cpp

Modified: llvm/trunk/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=99392&r1=99391&r2=99392&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Triple.cpp (original)
+++ llvm/trunk/lib/Support/Triple.cpp Wed Mar 24 04:05:14 2010
@@ -189,7 +189,7 @@
   return Triple::UnknownArch;
 }
 
-// Returns architecture name that is unsderstood by the target assembler.
+// Returns architecture name that is understood by the target assembler.
 const char *Triple::getArchNameForAssembler() {
   if (getOS() != Triple::Darwin && getVendor() != Triple::Apple)
     return NULL;




From anton at korobeynikov.info  Wed Mar 24 04:15:58 2010
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Wed, 24 Mar 2010 12:15:58 +0300
Subject: [llvm-commits] [llvm] r99345 - in /llvm/trunk/lib/Target/X86:
	CMakeLists.txt SSEDomainFix.cpp X86.h X86InstrInfo.cpp
	X86InstrInfo.h X86TargetMachine.cpp X86TargetMachine.h
In-Reply-To: <20100323231444.97DDA2A6C12C@llvm.org>
References: <20100323231444.97DDA2A6C12C@llvm.org>
Message-ID: <b087fca01003240215t72b32009y963d7d8c336dda54@mail.gmail.com>

Hi, Jakob

> Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.
>
> This is work in progress. So far, SSE execution domain tables are added to
> X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.
We will need same for ARM: VFP vs NEON. Is it possible to generalize
this pass somehow?

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From baldrick at free.fr  Wed Mar 24 04:47:41 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 24 Mar 2010 09:47:41 -0000
Subject: [llvm-commits] [dragonegg] r99393 -
	/dragonegg/trunk/utils/target.cpp
Message-ID: <20100324094741.C0BB52A6C12C@llvm.org>

Author: baldrick
Date: Wed Mar 24 04:47:41 2010
New Revision: 99393

URL: http://llvm.org/viewvc/llvm-project?rev=99393&view=rev
Log:
Always used parsed values, rather than accessing triple components
directly.  Get rid of accessors for the environment, since they are
not used.

Modified:
    dragonegg/trunk/utils/target.cpp

Modified: dragonegg/trunk/utils/target.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/utils/target.cpp?rev=99393&r1=99392&r2=99393&view=diff
==============================================================================
--- dragonegg/trunk/utils/target.cpp (original)
+++ dragonegg/trunk/utils/target.cpp Wed Mar 24 04:47:41 2010
@@ -9,20 +9,14 @@
   std::cout << T.getTriple() << "\n";
 }
 static void PrintArchName(Triple &T) {
-  std::cout << T.getArchName().str() << "\n";
+  std::cout << T.getArchTypeName(T.getArch()) << "\n";
 }
 static void PrintVendorName(Triple &T) {
-  std::cout << T.getVendorName().str() << "\n";
+  std::cout << T.getVendorTypeName(T.getVendor()) << "\n";
 }
-static void PrintOSTypeName(Triple &T) {
+static void PrintOSName(Triple &T) {
   std::cout << T.getOSTypeName(T.getOS()) << "\n";
 }
-static void PrintEnvironmentName(Triple &T) {
-  std::cout << T.getEnvironmentName().str() << "\n";
-}
-static void PrintOSAndEnvironmentName(Triple &T) {
-  std::cout << T.getOSAndEnvironmentName().str() << "\n";
-}
 static void PrintArchTypePrefix(Triple &T) {
   std::cout << T.getArchTypePrefix(T.getArch()) << "\n";
 }
@@ -36,9 +30,7 @@
   { "-t", PrintTriple },
   { "-a", PrintArchName },
   { "-v", PrintVendorName },
-  { "-o", PrintOSTypeName },
-  { "-e", PrintEnvironmentName },
-  { "-oe", PrintOSAndEnvironmentName },
+  { "-o", PrintOSName },
   { "-p", PrintArchTypePrefix },
   { NULL, NULL }
 };




From ggreif at gmail.com  Wed Mar 24 05:12:54 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 24 Mar 2010 10:12:54 -0000
Subject: [llvm-commits] [llvm] r99394 -
	/llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp
Message-ID: <20100324101254.401A52A6C12C@llvm.org>

Author: ggreif
Date: Wed Mar 24 05:12:54 2010
New Revision: 99394

URL: http://llvm.org/viewvc/llvm-project?rev=99394&view=rev
Log:
cache result of UI.getOperandNo() instead of calling it twice, it is cheaper this way

Modified:
    llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp

Modified: llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp?rev=99394&r1=99393&r2=99394&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp Wed Mar 24 05:12:54 2010
@@ -440,8 +440,9 @@
     }
     
     if (StoreInst *SI = dyn_cast<StoreInst>(*UI)) {
-      if (UI.getOperandNo() == 0) return true; // Storing addr, not into addr.
-      MemoryUses.push_back(std::make_pair(SI, UI.getOperandNo()));
+      unsigned opNo = UI.getOperandNo();
+      if (opNo == 0) return true; // Storing addr, not into addr.
+      MemoryUses.push_back(std::make_pair(SI, opNo));
       continue;
     }
     




From ggreif at gmail.com  Wed Mar 24 05:29:52 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 24 Mar 2010 10:29:52 -0000
Subject: [llvm-commits] [llvm] r99395 -
	/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
Message-ID: <20100324102952.A01A42A6C12C@llvm.org>

Author: ggreif
Date: Wed Mar 24 05:29:52 2010
New Revision: 99395

URL: http://llvm.org/viewvc/llvm-project?rev=99395&view=rev
Log:
increase const goodness and remove pointless getUser() calls

Modified:
    llvm/trunk/lib/Transforms/Scalar/SCCP.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=99395&r1=99394&r2=99395&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Wed Mar 24 05:29:52 2010
@@ -1705,28 +1705,30 @@
 }
 
 
-static bool AddressIsTaken(GlobalValue *GV) {
+static bool AddressIsTaken(const GlobalValue *GV) {
   // Delete any dead constantexpr klingons.
   GV->removeDeadConstantUsers();
 
-  for (Value::use_iterator UI = GV->use_begin(), E = GV->use_end();
-       UI != E; ++UI)
-    if (StoreInst *SI = dyn_cast<StoreInst>(*UI)) {
+  for (Value::use_const_iterator UI = GV->use_begin(), E = GV->use_end();
+       UI != E; ++UI) {
+    const User *U = *UI;
+    if (const StoreInst *SI = dyn_cast<StoreInst>(U)) {
       if (SI->getOperand(0) == GV || SI->isVolatile())
         return true;  // Storing addr of GV.
-    } else if (isa<InvokeInst>(*UI) || isa<CallInst>(*UI)) {
+    } else if (isa<InvokeInst>(U) || isa<CallInst>(U)) {
       // Make sure we are calling the function, not passing the address.
       if (UI.getOperandNo() != 0)
         return true;
-    } else if (LoadInst *LI = dyn_cast<LoadInst>(*UI)) {
+    } else if (const LoadInst *LI = dyn_cast<LoadInst>(U)) {
       if (LI->isVolatile())
         return true;
-    } else if (isa<BlockAddress>(*UI)) {
+    } else if (isa<BlockAddress>(U)) {
       // blockaddress doesn't take the address of the function, it takes addr
       // of label.
     } else {
       return true;
     }
+  }
   return false;
 }
 




From ggreif at gmail.com  Wed Mar 24 06:58:07 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 24 Mar 2010 11:58:07 -0000
Subject: [llvm-commits] [llvm] r99398 -
	/llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp
Message-ID: <20100324115807.B8F772A6C12E@llvm.org>

Author: ggreif
Date: Wed Mar 24 06:58:07 2010
New Revision: 99398

URL: http://llvm.org/viewvc/llvm-project?rev=99398&view=rev
Log:
tighten a type and remove trailing whitespace, no functional changes

Modified:
    llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp

Modified: llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp?rev=99398&r1=99397&r2=99398&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp Wed Mar 24 06:58:07 2010
@@ -72,7 +72,7 @@
       }
 
       std::string getDescription() const {
-        return std::string((IsArg ? "Argument #" : "Return value #")) 
+        return std::string((IsArg ? "Argument #" : "Return value #"))
                + utostr(Idx) + " of function " + F->getNameStr();
       }
     };
@@ -196,7 +196,7 @@
   // Start by computing a new prototype for the function, which is the same as
   // the old function, but doesn't have isVarArg set.
   const FunctionType *FTy = Fn.getFunctionType();
-  
+
   std::vector<const Type*> Params(FTy->param_begin(), FTy->param_end());
   FunctionType *NFTy = FunctionType::get(FTy->getReturnType(),
                                                 Params, false);
@@ -225,7 +225,7 @@
       SmallVector<AttributeWithIndex, 8> AttributesVec;
       for (unsigned i = 0; PAL.getSlot(i).Index <= NumArgs; ++i)
         AttributesVec.push_back(PAL.getSlot(i));
-      if (Attributes FnAttrs = PAL.getFnAttributes()) 
+      if (Attributes FnAttrs = PAL.getFnAttributes())
         AttributesVec.push_back(AttributeWithIndex::get(~0, FnAttrs));
       PAL = AttrListPtr::get(AttributesVec.begin(), AttributesVec.end());
     }
@@ -312,7 +312,7 @@
 /// it at 0.
 DAE::Liveness DAE::SurveyUse(Value::use_iterator U, UseVector &MaybeLiveUses,
                              unsigned RetValNum) {
-    Value *V = *U;
+    User *V = *U;
     if (ReturnInst *RI = dyn_cast<ReturnInst>(V)) {
       // The value is returned from a function. It's only live when the
       // function's return value is live. We use RetValNum here, for the case
@@ -347,7 +347,7 @@
       Function *F = CS.getCalledFunction();
       if (F) {
         // Used in a direct call.
-  
+
         // Find the argument number. We know for sure that this use is an
         // argument, since if it was the function argument this would be an
         // indirect call and the we know can't be looking at a value of the
@@ -358,8 +358,8 @@
           // The value is passed in through a vararg! Must be live.
           return Live;
 
-        assert(CS.getArgument(ArgNo) 
-               == CS.getInstruction()->getOperand(U.getOperandNo()) 
+        assert(CS.getArgument(ArgNo)
+               == CS.getInstruction()->getOperand(U.getOperandNo())
                && "Argument is not where we expected it");
 
         // Value passed to a normal call. It's only live when the corresponding
@@ -599,7 +599,7 @@
   const Type *RetTy = FTy->getReturnType();
   const Type *NRetTy = NULL;
   unsigned RetCount = NumRetVals(F);
-  
+
   // -1 means unused, other numbers are the new index
   SmallVector<int, 5> NewRetIdxs(RetCount, -1);
   std::vector<const Type*> RetTypes;
@@ -656,7 +656,7 @@
   if (NRetTy == Type::getVoidTy(F->getContext()))
     RAttrs &= ~Attribute::typeIncompatible(NRetTy);
   else
-    assert((RAttrs & Attribute::typeIncompatible(NRetTy)) == 0 
+    assert((RAttrs & Attribute::typeIncompatible(NRetTy)) == 0
            && "Return attributes no longer compatible?");
 
   if (RAttrs)
@@ -686,7 +686,7 @@
     }
   }
 
-  if (FnAttrs != Attribute::None) 
+  if (FnAttrs != Attribute::None)
     AttributesVec.push_back(AttributeWithIndex::get(~0, FnAttrs));
 
   // Reconstruct the AttributesList based on the vector we constructed.
@@ -805,7 +805,7 @@
           while (isa<PHINode>(IP)) ++IP;
           InsertPt = IP;
         }
-          
+
         // We used to return a struct. Instead of doing smart stuff with all the
         // uses of this struct, we will just rebuild it using
         // extract/insertvalue chaining and let instcombine clean that up.
@@ -929,7 +929,7 @@
   DEBUG(dbgs() << "DAE - Determining liveness\n");
   for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
     SurveyFunction(*I);
-  
+
   // Now, remove all dead arguments and return values from each function in
   // turn
   for (Module::iterator I = M.begin(), E = M.end(); I != E; ) {




From ggreif at gmail.com  Wed Mar 24 08:21:49 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 24 Mar 2010 13:21:49 -0000
Subject: [llvm-commits] [llvm] r99399 - in /llvm/trunk: ./
 include/llvm/Function.h include/llvm/Instructions.h
 include/llvm/Support/CallSite.h lib/Analysis/IPA/GlobalsModRef.cpp
 lib/Bitcode/Writer/BitcodeWriter.cpp
 lib/Transforms/IPO/DeadArgumentElimination.cpp
 lib/Transforms/IPO/PruneEH.cpp lib/Transforms/Scalar/SCCP.cpp
 lib/Transforms/Scalar/SimplifyCFGPass.cpp
 lib/Transforms/Utils/LowerInvoke.cpp lib/VMCore/AsmWriter.cpp
 lib/VMCore/Function.cpp lib/VMCore/Instructions.cpp lib/VMCore/Verifier.cpp
Message-ID: <20100324132149.A8EC42A6C12C@llvm.org>

Author: ggreif
Date: Wed Mar 24 08:21:49 2010
New Revision: 99399

URL: http://llvm.org/viewvc/llvm-project?rev=99399&view=rev
Log:
Finally land the InvokeInst operand reordering.
I have audited all getOperandNo calls now, fixing
hidden assumptions. CallSite related uglyness will
be eliminated successively.

Note this patch has a long and griveous history,
for all the back-and-forths have a look at
CallSite.h's log.

Modified:
    llvm/trunk/   (props changed)
    llvm/trunk/include/llvm/Function.h
    llvm/trunk/include/llvm/Instructions.h
    llvm/trunk/include/llvm/Support/CallSite.h
    llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp
    llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
    llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp
    llvm/trunk/lib/Transforms/IPO/PruneEH.cpp
    llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
    llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp
    llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp
    llvm/trunk/lib/VMCore/AsmWriter.cpp
    llvm/trunk/lib/VMCore/Function.cpp
    llvm/trunk/lib/VMCore/Instructions.cpp
    llvm/trunk/lib/VMCore/Verifier.cpp

Propchange: llvm/trunk/
------------------------------------------------------------------------------
    svn:mergeinfo = /llvm/branches/ggreif/InvokeInst-operands:98645-99398

Modified: llvm/trunk/include/llvm/Function.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Function.h?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Function.h (original)
+++ llvm/trunk/include/llvm/Function.h Wed Mar 24 08:21:49 2010
@@ -409,8 +409,11 @@
   void dropAllReferences();
 
   /// hasAddressTaken - returns true if there are any uses of this function
-  /// other than direct calls or invokes to it.
-  bool hasAddressTaken() const;
+  /// other than direct calls or invokes to it. Optionally passes back the
+  /// offending user for diagnostic purposes.
+  ///
+  bool hasAddressTaken(const User** = 0) const;
+
 private:
   // Shadow Value::setValueSubclassData with a private forwarding method so that
   // subclasses cannot accidentally use it.

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Wed Mar 24 08:21:49 2010
@@ -2522,32 +2522,31 @@
   /// indirect function invocation.
   ///
   Function *getCalledFunction() const {
-    return dyn_cast<Function>(getOperand(0));
+    return dyn_cast<Function>(Op<-3>());
   }
 
   /// getCalledValue - Get a pointer to the function that is invoked by this
   /// instruction
-  const Value *getCalledValue() const { return getOperand(0); }
-        Value *getCalledValue()       { return getOperand(0); }
+  const Value *getCalledValue() const { return Op<-3>(); }
+        Value *getCalledValue()       { return Op<-3>(); }
 
   /// setCalledFunction - Set the function called.
   void setCalledFunction(Value* Fn) {
-    Op<0>() = Fn;
+    Op<-3>() = Fn;
   }
 
   // get*Dest - Return the destination basic blocks...
   BasicBlock *getNormalDest() const {
-    return cast<BasicBlock>(getOperand(1));
+    return cast<BasicBlock>(Op<-2>());
   }
   BasicBlock *getUnwindDest() const {
-    return cast<BasicBlock>(getOperand(2));
+    return cast<BasicBlock>(Op<-1>());
   }
   void setNormalDest(BasicBlock *B) {
-    setOperand(1, (Value*)B);
+    Op<-2>() = reinterpret_cast<Value*>(B);
   }
-
   void setUnwindDest(BasicBlock *B) {
-    setOperand(2, (Value*)B);
+    Op<-1>() = reinterpret_cast<Value*>(B);
   }
 
   BasicBlock *getSuccessor(unsigned i) const {
@@ -2557,7 +2556,7 @@
 
   void setSuccessor(unsigned idx, BasicBlock *NewSucc) {
     assert(idx < 2 && "Successor # out of range for invoke!");
-    setOperand(idx+1, (Value*)NewSucc);
+    *(&Op<-2>() + idx) = reinterpret_cast<Value*>(NewSucc);
   }
 
   unsigned getNumSuccessors() const { return 2; }
@@ -2570,6 +2569,7 @@
   static inline bool classof(const Value *V) {
     return isa<Instruction>(V) && classof(cast<Instruction>(V));
   }
+
 private:
   virtual BasicBlock *getSuccessorV(unsigned idx) const;
   virtual unsigned getNumSuccessorsV() const;

Modified: llvm/trunk/include/llvm/Support/CallSite.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CallSite.h (original)
+++ llvm/trunk/include/llvm/Support/CallSite.h Wed Mar 24 08:21:49 2010
@@ -122,7 +122,7 @@
   ///
   Value *getCalledValue() const {
     assert(getInstruction() && "Not a call or invoke instruction!");
-    return getInstruction()->getOperand(0);
+    return *getCallee();
   }
 
   /// getCalledFunction - Return the function being called if this is a direct
@@ -136,7 +136,7 @@
   ///
   void setCalledFunction(Value *V) {
     assert(getInstruction() && "Not a call or invoke instruction!");
-    getInstruction()->setOperand(0, V);
+    *getCallee() = V;
   }
 
   Value *getArgument(unsigned ArgNo) const {
@@ -150,6 +150,16 @@
     getInstruction()->setOperand(getArgumentOffset() + ArgNo, newVal);
   }
 
+  /// Given a value use iterator, returns the argument that corresponds to it.
+  /// Iterator must actually correspond to an argument.
+  unsigned getArgumentNo(Value::use_iterator I) const {
+    assert(getInstruction() && "Not a call or invoke instruction!");
+    assert(arg_begin() <= &I.getUse() && &I.getUse() < arg_end()
+           && "Argument # out of range!");
+
+    return &I.getUse() - arg_begin();
+  }
+
   /// Given an operand number, returns the argument that corresponds to it.
   /// OperandNo must be a valid operand number that actually corresponds to an
   /// argument.
@@ -175,7 +185,7 @@
     return getInstruction()->op_begin() + getArgumentOffset();
   }
 
-  arg_iterator arg_end() const { return getInstruction()->op_end(); }
+  arg_iterator arg_end() const { return getInstruction()->op_end() - getArgumentEndOffset(); }
   bool arg_empty() const { return arg_end() == arg_begin(); }
   unsigned arg_size() const { return unsigned(arg_end() - arg_begin()); }
 
@@ -184,17 +194,28 @@
   }
 
   bool isCallee(Value::use_iterator UI) const {
-    return getInstruction()->op_begin() == &UI.getUse();
+    return getCallee() == &UI.getUse();
+  }
+  bool isCallee(Value::use_const_iterator UI) const {
+    return getCallee() == &UI.getUse();
   }
-
 private:
   /// Returns the operand number of the first argument
   unsigned getArgumentOffset() const {
     if (isCall())
       return 1; // Skip Function
     else
-      return 3; // Skip Function, BB, BB
+      return 0; // Args are at the front
   }
+
+  unsigned getArgumentEndOffset() const {
+    if (isCall())
+      return 0; // Unchanged
+    else
+      return 3; // Skip BB, BB, Function
+  }
+
+  User::op_iterator getCallee() const;
 };
 
 } // End llvm namespace

Modified: llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp (original)
+++ llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp Wed Mar 24 08:21:49 2010
@@ -257,7 +257,7 @@
     } else if (InvokeInst *II = dyn_cast<InvokeInst>(*UI)) {
       // Make sure that this is just the function being called, not that it is
       // passing into the function.
-      for (unsigned i = 3, e = II->getNumOperands(); i != e; ++i)
+      for (unsigned i = 0, e = II->getNumOperands() - 3; i != e; ++i)
         if (II->getOperand(i) == V) return true;
     } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(*UI)) {
       if (CE->getOpcode() == Instruction::GetElementPtr ||

Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Wed Mar 24 08:21:49 2010
@@ -1090,11 +1090,11 @@
 
     // Emit value #'s for the fixed parameters.
     for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i)
-      Vals.push_back(VE.getValueID(I.getOperand(i+3)));  // fixed param.
+      Vals.push_back(VE.getValueID(I.getOperand(i)));  // fixed param.
 
     // Emit type/value pairs for varargs params.
     if (FTy->isVarArg()) {
-      for (unsigned i = 3+FTy->getNumParams(), e = I.getNumOperands();
+      for (unsigned i = FTy->getNumParams(), e = I.getNumOperands()-3;
            i != e; ++i)
         PushValueAndType(I.getOperand(i), InstID, Vals, VE); // vararg
     }

Modified: llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp Wed Mar 24 08:21:49 2010
@@ -352,7 +352,7 @@
         // argument, since if it was the function argument this would be an
         // indirect call and the we know can't be looking at a value of the
         // label type (for the invoke instruction).
-        unsigned ArgNo = CS.getArgumentNo(U.getOperandNo());
+        unsigned ArgNo = CS.getArgumentNo(U);
 
         if (ArgNo >= F->getFunctionType()->getNumParams())
           // The value is passed in through a vararg! Must be live.

Modified: llvm/trunk/lib/Transforms/IPO/PruneEH.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/PruneEH.cpp?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/PruneEH.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/PruneEH.cpp Wed Mar 24 08:21:49 2010
@@ -168,7 +168,7 @@
   for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
     if (InvokeInst *II = dyn_cast<InvokeInst>(BB->getTerminator()))
       if (II->doesNotThrow()) {
-        SmallVector<Value*, 8> Args(II->op_begin()+3, II->op_end());
+        SmallVector<Value*, 8> Args(II->op_begin(), II->op_end() - 3);
         // Insert a call instruction before the invoke.
         CallInst *Call = CallInst::Create(II->getCalledValue(),
                                           Args.begin(), Args.end(), "", II);

Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Wed Mar 24 08:21:49 2010
@@ -1717,7 +1717,8 @@
         return true;  // Storing addr of GV.
     } else if (isa<InvokeInst>(U) || isa<CallInst>(U)) {
       // Make sure we are calling the function, not passing the address.
-      if (UI.getOperandNo() != 0)
+      CallSite CS((Instruction*)U);
+      if (!CS.isCallee(UI))
         return true;
     } else if (const LoadInst *LI = dyn_cast<LoadInst>(U)) {
       if (LI->isVolatile())

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp Wed Mar 24 08:21:49 2010
@@ -79,7 +79,7 @@
 /// ChangeToCall - Convert the specified invoke into a normal call.
 static void ChangeToCall(InvokeInst *II) {
   BasicBlock *BB = II->getParent();
-  SmallVector<Value*, 8> Args(II->op_begin()+3, II->op_end());
+  SmallVector<Value*, 8> Args(II->op_begin(), II->op_end() - 3);
   CallInst *NewCall = CallInst::Create(II->getCalledValue(), Args.begin(),
                                        Args.end(), "", II);
   NewCall->takeName(II);

Modified: llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp Wed Mar 24 08:21:49 2010
@@ -226,7 +226,7 @@
   bool Changed = false;
   for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
     if (InvokeInst *II = dyn_cast<InvokeInst>(BB->getTerminator())) {
-      std::vector<Value*> CallArgs(II->op_begin()+3, II->op_end());
+      std::vector<Value*> CallArgs(II->op_begin(), II->op_end() - 3);
       // Insert a normal call instruction...
       CallInst *NewCall = CallInst::Create(II->getCalledValue(),
                                            CallArgs.begin(), CallArgs.end(), "",II);
@@ -298,7 +298,7 @@
   CatchSwitch->addCase(InvokeNoC, II->getUnwindDest());
 
   // Insert a normal call instruction.
-  std::vector<Value*> CallArgs(II->op_begin()+3, II->op_end());
+  std::vector<Value*> CallArgs(II->op_begin(), II->op_end() - 3);
   CallInst *NewCall = CallInst::Create(II->getCalledValue(),
                                        CallArgs.begin(), CallArgs.end(), "",
                                        II);

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Wed Mar 24 08:21:49 2010
@@ -1875,6 +1875,7 @@
     if (PAL.getFnAttributes() != Attribute::None)
       Out << ' ' << Attribute::getAsString(PAL.getFnAttributes());
   } else if (const InvokeInst *II = dyn_cast<InvokeInst>(&I)) {
+    Operand = II->getCalledValue();
     const PointerType    *PTy = cast<PointerType>(Operand->getType());
     const FunctionType   *FTy = cast<FunctionType>(PTy->getElementType());
     const Type         *RetTy = FTy->getReturnType();
@@ -1912,10 +1913,10 @@
       writeOperand(Operand, true);
     }
     Out << '(';
-    for (unsigned op = 3, Eop = I.getNumOperands(); op < Eop; ++op) {
-      if (op > 3)
+    for (unsigned op = 0, Eop = I.getNumOperands() - 3; op < Eop; ++op) {
+      if (op)
         Out << ", ";
-      writeParamOperand(I.getOperand(op), PAL.getParamAttributes(op-2));
+      writeParamOperand(I.getOperand(op), PAL.getParamAttributes(op + 1));
     }
 
     Out << ')';

Modified: llvm/trunk/lib/VMCore/Function.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Function.cpp (original)
+++ llvm/trunk/lib/VMCore/Function.cpp Wed Mar 24 08:21:49 2010
@@ -16,6 +16,7 @@
 #include "llvm/IntrinsicInst.h"
 #include "llvm/LLVMContext.h"
 #include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/Support/CallSite.h"
 #include "llvm/Support/LeakDetector.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/StringPool.h"
@@ -402,11 +403,14 @@
 
 /// hasAddressTaken - returns true if there are any uses of this function
 /// other than direct calls or invokes to it.
-bool Function::hasAddressTaken() const {
+bool Function::hasAddressTaken(const User* *PutOffender) const {
   for (Value::use_const_iterator I = use_begin(), E = use_end(); I != E; ++I) {
-    if (I.getOperandNo() != 0 ||
-        (!isa<CallInst>(*I) && !isa<InvokeInst>(*I)))
-      return true;
+    const User *U = *I;
+    if (!isa<CallInst>(U) && !isa<InvokeInst>(U))
+      return PutOffender ? (*PutOffender = U, true) : true;
+    CallSite CS(const_cast<Instruction*>(static_cast<const Instruction*>(U)));
+    if (!CS.isCallee(I))
+      return PutOffender ? (*PutOffender = U, true) : true;
   }
   return false;
 }

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Wed Mar 24 08:21:49 2010
@@ -109,6 +109,13 @@
   return false;
 }
 
+User::op_iterator CallSite::getCallee() const {
+  Instruction *II(getInstruction());
+  return isCall()
+    ? cast<CallInst>(II)->op_begin()
+    : cast<InvokeInst>(II)->op_end() - 3; // Skip BB, BB, Function
+}
+
 #undef CALLSITE_DELEGATE_GETTER
 #undef CALLSITE_DELEGATE_SETTER
 
@@ -622,10 +629,9 @@
 void InvokeInst::init(Value *Fn, BasicBlock *IfNormal, BasicBlock *IfException,
                       Value* const *Args, unsigned NumArgs) {
   assert(NumOperands == 3+NumArgs && "NumOperands not set up?");
-  Use *OL = OperandList;
-  OL[0] = Fn;
-  OL[1] = IfNormal;
-  OL[2] = IfException;
+  Op<-3>() = Fn;
+  Op<-2>() = IfNormal;
+  Op<-1>() = IfException;
   const FunctionType *FTy =
     cast<FunctionType>(cast<PointerType>(Fn->getType())->getElementType());
   FTy = FTy;  // silence warning.
@@ -634,12 +640,13 @@
           (FTy->isVarArg() && NumArgs > FTy->getNumParams())) &&
          "Invoking a function with bad signature");
 
+  Use *OL = OperandList;
   for (unsigned i = 0, e = NumArgs; i != e; i++) {
     assert((i >= FTy->getNumParams() || 
             FTy->getParamType(i) == Args[i]->getType()) &&
            "Invoking a function with a bad signature!");
     
-    OL[i+3] = Args[i];
+    OL[i] = Args[i];
   }
 }
 

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=99399&r1=99398&r2=99399&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Wed Mar 24 08:21:49 2010
@@ -676,17 +676,13 @@
               "blockaddress may not be used with the entry block!", Entry);
     }
   }
-  
+ 
   // If this function is actually an intrinsic, verify that it is only used in
   // direct call/invokes, never having its "address taken".
   if (F.getIntrinsicID()) {
-    for (Value::use_iterator UI = F.use_begin(), E = F.use_end(); UI != E;++UI){
-      User *U = cast<User>(UI);
-      if ((isa<CallInst>(U) || isa<InvokeInst>(U)) && UI.getOperandNo() == 0)
-        continue;  // Direct calls/invokes are ok.
-      
+    const User *U;
+    if (F.hasAddressTaken(&U))
       Assert1(0, "Invalid user of intrinsic instruction!", U); 
-    }
   }
 }
 
@@ -1483,7 +1479,7 @@
                 "Instruction does not dominate all uses!", Op, &I);
       }
     } else if (isa<InlineAsm>(I.getOperand(i))) {
-      Assert1(i == 0 && (isa<CallInst>(I) || isa<InvokeInst>(I)),
+      Assert1((i == 0 && isa<CallInst>(I)) || (i + 3 == e && isa<InvokeInst>(I)),
               "Cannot take the address of an inline asm!", &I);
     }
   }




From edwintorok at gmail.com  Wed Mar 24 08:50:36 2010
From: edwintorok at gmail.com (Torok Edwin)
Date: Wed, 24 Mar 2010 13:50:36 -0000
Subject: [llvm-commits] [llvm] r99400 - in /llvm/trunk:
 lib/CodeGen/LiveIntervalAnalysis.cpp
 test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
Message-ID: <20100324135036.CB2412A6C12C@llvm.org>

Author: edwin
Date: Wed Mar 24 08:50:36 2010
New Revision: 99400

URL: http://llvm.org/viewvc/llvm-project?rev=99400&view=rev
Log:
Fix memory leak in liveintervals: the destructor for VNInfos must be called,
otherwise the SmallVector it contains doesn't free its memory.
In most cases LiveIntervalAnalysis could get away by not calling the destructor,
because VNInfos are bumpptr-allocated, and smallvectors usually don't grow.
However when the SmallVector does grow it always leaks.

This is the valgrind shown leak from the original testcase:
==8206== 18,304 bytes in 151 blocks are definitely lost in loss record 164 of 164
==8206==    at 0x4A079C7: operator new(unsigned long) (vg_replace_malloc.c:220)
==8206==    by 0x4DB7A7E: llvm::SmallVectorBase::grow_pod(unsigned long, unsigned long) (in /home/edwin/clam/git/builds/defaul
t/libclamav/.libs/libclamav.so.6.1.0)
==8206==    by 0x4F90382: llvm::VNInfo::addKill(llvm::SlotIndex) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libcl
amav.so.6.1.0)
==8206==    by 0x5126B5C: llvm::LiveIntervals::handleVirtualRegisterDef(llvm::MachineBasicBlock*, llvm::ilist_iterator<llvm::M
achineInstr>, llvm::SlotIndex, llvm::MachineOperand&, unsigned int, llvm::LiveInterval&) (in /home/edwin/clam/git/builds/defau
lt/libclamav/.libs/libclamav.so.6.1.0)
==8206==    by 0x512725E: llvm::LiveIntervals::handleRegisterDef(llvm::MachineBasicBlock*, llvm::ilist_iterator<llvm::MachineI
nstr>, llvm::SlotIndex, llvm::MachineOperand&, unsigned int) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libclamav
.so.6.1.0)
==8206==    by 0x51278A8: llvm::LiveIntervals::computeIntervals() (in /home/edwin/clam/git/builds/default/libclamav/.libs/libc
lamav.so.6.1.0)
==8206==    by 0x5127CB4: llvm::LiveIntervals::runOnMachineFunction(llvm::MachineFunction&) (in /home/edwin/clam/git/builds/de
fault/libclamav/.libs/libclamav.so.6.1.0)
==8206==    by 0x4DAE935: llvm::FPPassManager::runOnFunction(llvm::Function&) (in /home/edwin/clam/git/builds/default/libclama
v/.libs/libclamav.so.6.1.0)
==8206==    by 0x4DAEB10: llvm::FunctionPassManagerImpl::run(llvm::Function&) (in /home/edwin/clam/git/builds/default/libclama
v/.libs/libclamav.so.6.1.0)
==8206==    by 0x4DAED3D: llvm::FunctionPassManager::run(llvm::Function&) (in /home/edwin/clam/git/builds/default/libclamav/.l
ibs/libclamav.so.6.1.0)
==8206==    by 0x4D8BE8E: llvm::JIT::runJITOnFunctionUnlocked(llvm::Function*, llvm::MutexGuard const&) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libclamav.so.6.1.0)
==8206==    by 0x4D8CA72: llvm::JIT::getPointerToFunction(llvm::Function*) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libclamav.so.6.1.0)

Added:
    llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=99400&r1=99399&r2=99400&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Mar 24 08:50:36 2010
@@ -85,8 +85,10 @@
 void LiveIntervals::releaseMemory() {
   // Free the live intervals themselves.
   for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
-       E = r2iMap_.end(); I != E; ++I)
+       E = r2iMap_.end(); I != E; ++I) {
+    I->second->clear();
     delete I->second;
+  }
   
   r2iMap_.clear();
 

Added: llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll?rev=99400&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll (added)
+++ llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll Wed Mar 24 08:50:36 2010
@@ -0,0 +1,114 @@
+; RUN: llc <%s
+%0 = type { i8, %1, i8, %1, i8, %1 }
+%1 = type { i32 }
+%2 = type { i16, i8, i8, i8, [3 x [10 x i8]], [29 x i8] }
+%3 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+%4 = type { i32, i32, i16, i16, %5, %6, i32, %8, [16 x %7], i32, i32, i32, i32 }
+%5 = type { i32, i16, i16, i32, i32, i32, i16, i16 }
+%6 = type { i16, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16, i16, i16, i16, i16, i32, i32, i32, i32, i16, i16, i32, i32, i32, i32, i32, i32, [16 x %7] }
+%7 = type { i32, i32 }
+%8 = type { i16, i8, i8, i32, i32, i32, i32, i32, i64, i32, i32, i16, i16, i16, i16, i16, i16, i32, i32, i32, i32, i16, i16, i64, i64, i64, i64, i32, i32, [16 x %7] }
+ at glob2 = internal constant [39 x i8] c"ClamAV-Test-File-detected-via-bytecode\00" ; <[39 x i8]*> [#uses=1]
+ at glob9 = internal constant [5 x i8] c"EP: \00"    ; <[5 x i8]*> [#uses=1]
+ at glob10 = internal constant [27 x i8] c"Couldn't read 5 bytes @EP\0A\00" ; <[27 x i8]*> [#uses=1]
+ at glob11 = internal constant [46 x i8] c"No 'mov ebx, cyphertext' found at entrypoint\0A\00" ; <[46 x i8]*> [#uses=1]
+ at glob12 = internal constant [21 x i8] c"VA of cyphertext is \00" ; <[21 x i8]*> [#uses=1]
+ at glob13 = internal constant [22 x i8] c"RVA of cyphertext is \00" ; <[22 x i8]*> [#uses=1]
+ at glob14 = internal constant [51 x i8] c"Can't locate the phisical offset of the cyphertext\00" ; <[51 x i8]*> [#uses=1]
+ at glob15 = internal constant [22 x i8] c"Cyphertext starts at \00" ; <[22 x i8]*> [#uses=1]
+ at glob16 = internal constant [35 x i8] c"Can't read 10 bytes of cyphertext\0A\00" ; <[35 x i8]*> [#uses=1]
+ at glob17 = internal constant [11 x i8] c"HELLO WORM\00" ; <[11 x i8]*> [#uses=1]
+declare i32 @llvm.bswap.i32(i32) nounwind readnone
+declare i32 @memcmp(i8*, i8*, i64)
+declare i32 @read([128 x i8]*, i8*, i32)
+declare i32 @seek([128 x i8]*, i32, i32)
+declare i32 @setvirusname([128 x i8]*, i8*, i32)
+declare i32 @debug_print_str([128 x i8]*, i8*, i32)
+declare i32 @debug_print_uint([128 x i8]*, i32)
+declare i32 @pe_rawaddr([128 x i8]*, i32)
+define internal fastcc i32 @bc0f0([128 x i8]*) nounwind ssp sspreq {
+  %2 = alloca [5 x i8]                            ; <[5 x i8]*> [#uses=3]
+  %3 = alloca [11 x i8]                           ; <[11 x i8]*> [#uses=5]
+  %4 = getelementptr inbounds [128 x i8]* %0, i32 0, i32 120 ; <i8*> [#uses=1]
+  %5 = bitcast i8* %4 to %4**                     ; <%4**> [#uses=1]
+  %6 = load %4** %5                               ; <%4*> [#uses=1]
+  %g3_1 = bitcast %4* %6 to i8*                   ; <i8*> [#uses=1]
+  %7 = getelementptr i8* %g3_1, i32 64            ; <i8*> [#uses=1]
+  %8 = bitcast i8* %7 to %4**                     ; <%4**> [#uses=1]
+  %9 = getelementptr inbounds [128 x i8]* %0, i32 0, i32 120 ; <i8*> [#uses=1]
+  %10 = bitcast i8* %9 to %4**                    ; <%4**> [#uses=1]
+  %11 = load %4** %10                             ; <%4*> [#uses=1]
+  %g3_2 = bitcast %4* %11 to i8*                  ; <i8*> [#uses=1]
+  %12 = getelementptr i8* %g3_2, i32 4            ; <i8*> [#uses=1]
+  %13 = bitcast i8* %12 to %4**                   ; <%4**> [#uses=1]
+  %14 = bitcast %4** %13 to i32*                  ; <i32*> [#uses=1]
+  %15 = load i32* %14                             ; <i32> [#uses=2]
+  %16 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([5 x i8]* @glob9, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
+  %17 = call i32 @debug_print_uint([128 x i8]* %0, i32 %15) ; <i32> [#uses=0]
+  %18 = call i32 @seek([128 x i8]* %0, i32 %15, i32 0) ; <i32> [#uses=0]
+  %19 = getelementptr [5 x i8]* %2, i32 0, i32 0  ; <i8*> [#uses=1]
+  %20 = call i32 @read([128 x i8]* %0, i8* %19, i32 5) ; <i32> [#uses=1]
+  %21 = icmp eq i32 %20, 5                        ; <i1> [#uses=1]
+  br i1 %21, label %24, label %22
+  %23 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([27 x i8]* @glob10, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
+  ret i32 0
+  %25 = getelementptr [5 x i8]* %2, i32 0, i32 0  ; <i8*> [#uses=1]
+  %26 = load i8* %25                              ; <i8> [#uses=1]
+  %27 = icmp eq i8 %26, -69                       ; <i1> [#uses=1]
+  br i1 %27, label %30, label %28
+  %29 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([46 x i8]* @glob11, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
+  ret i32 0
+  %31 = getelementptr [5 x i8]* %2, i32 0, i32 1  ; <i8*> [#uses=1]
+  %32 = bitcast i8* %31 to i32*                   ; <i32*> [#uses=1]
+  %33 = load i32* %32                             ; <i32> [#uses=2]
+  br i1 false, label %34, label %36
+  %35 = tail call i32 @llvm.bswap.i32(i32 %33) nounwind ; <i32> [#uses=1]
+  br label %36
+  %.06 = phi i32 [ %35, %34 ], [ %33, %30 ]       ; <i32> [#uses=2]
+  %37 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([21 x i8]* @glob12, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
+  %38 = call i32 @debug_print_uint([128 x i8]* %0, i32 %.06) ; <i32> [#uses=0]
+  %39 = bitcast %4** %8 to i32*                   ; <i32*> [#uses=1]
+  %40 = load i32* %39                             ; <i32> [#uses=1]
+  %41 = sub i32 %.06, %40                         ; <i32> [#uses=2]
+  %42 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([22 x i8]* @glob13, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
+  %43 = call i32 @debug_print_uint([128 x i8]* %0, i32 %41) ; <i32> [#uses=0]
+  %44 = call i32 @pe_rawaddr([128 x i8]* %0, i32 %41) ; <i32> [#uses=3]
+  %45 = icmp eq i32 %44, -1                       ; <i1> [#uses=1]
+  br i1 %45, label %46, label %48
+  %47 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([51 x i8]* @glob14, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
+  ret i32 0
+  %49 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([22 x i8]* @glob15, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
+  %50 = call i32 @debug_print_uint([128 x i8]* %0, i32 %44) ; <i32> [#uses=0]
+  %51 = call i32 @seek([128 x i8]* %0, i32 %44, i32 0) ; <i32> [#uses=0]
+  %52 = getelementptr [11 x i8]* %3, i32 0, i32 0 ; <i8*> [#uses=1]
+  %53 = call i32 @read([128 x i8]* %0, i8* %52, i32 10) ; <i32> [#uses=1]
+  %54 = icmp eq i32 %53, 10                       ; <i1> [#uses=1]
+  br i1 %54, label %57, label %55
+  %56 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([35 x i8]* @glob16, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
+  ret i32 0
+  %.05 = phi i32 [ 0, %48 ], [ %66, %65 ]         ; <i32> [#uses=4]
+  %.0 = phi i8 [ 41, %48 ], [ %63, %65 ]          ; <i8> [#uses=1]
+  %58 = getelementptr [11 x i8]* %3, i32 0, i32 %.05 ; <i8*> [#uses=2]
+  %59 = icmp ult i32 %.05, 11                     ; <i1> [#uses=1]
+  br i1 %59, label %60, label %79
+  %61 = add i8 %.0, 1                             ; <i8> [#uses=1]
+  %62 = load i8* %58                              ; <i8> [#uses=1]
+  %63 = xor i8 %62, %61                           ; <i8> [#uses=2]
+  %64 = icmp ult i32 %.05, 11                     ; <i1> [#uses=1]
+  br i1 %64, label %65, label %79
+  %66 = add i32 %.05, 1                           ; <i32> [#uses=2]
+  %67 = icmp eq i32 %66, 10                       ; <i1> [#uses=1]
+  br i1 %67, label %68, label %57
+  %69 = getelementptr [11 x i8]* %3, i32 0, i32 0 ; <i8*> [#uses=1]
+  %70 = tail call i32 @memcmp(i8* %69, i8* getelementptr inbounds ([11 x i8]* @glob17, i32 0, i32 0), i64 10) nounwind ; <i32> [#uses=1]
+  %71 = icmp eq i32 %70, 0                        ; <i1> [#uses=1]
+  br i1 %71, label %72, label %78
+  %73 = getelementptr [11 x i8]* %3, i32 0, i32 10 ; <i8*> [#uses=1]
+  %74 = bitcast i8* %73 to i1*                    ; <i1*> [#uses=1]
+  %75 = getelementptr [11 x i8]* %3, i32 0, i32 0 ; <i8*> [#uses=1]
+  %76 = call i32 @debug_print_str([128 x i8]* %0, i8* %75, i32 0) ; <i32> [#uses=0]
+  %77 = call i32 @setvirusname([128 x i8]* %0, i8* getelementptr inbounds ([39 x i8]* @glob2, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
+  ret i32 0
+  ret i32 0
+  unreachable
+}




From stoklund at 2pi.dk  Wed Mar 24 09:37:44 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 24 Mar 2010 07:37:44 -0700
Subject: [llvm-commits] [llvm] r99345 - in /llvm/trunk/lib/Target/X86:
	CMakeLists.txt SSEDomainFix.cpp X86.h X86InstrInfo.cpp
	X86InstrInfo.h X86TargetMachine.cpp X86TargetMachine.h
In-Reply-To: <b087fca01003240215t72b32009y963d7d8c336dda54@mail.gmail.com>
References: <20100323231444.97DDA2A6C12C@llvm.org>
	<b087fca01003240215t72b32009y963d7d8c336dda54@mail.gmail.com>
Message-ID: <F86B3E7A-76B9-47D8-A3A1-2C27049292B0@2pi.dk>


On Mar 24, 2010, at 2:15 AM, Anton Korobeynikov wrote:

> Hi, Jakob
> 
>> Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.
>> 
>> This is work in progress. So far, SSE execution domain tables are added to
>> X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.
> We will need same for ARM: VFP vs NEON. Is it possible to generalize
> this pass somehow?

Good point.

We already have the NEONMoveFix pass, but it may be possible to generalize.

I need something a bit more fancy for SSE since there are more polymorphic instructions than just a single move, and often it is necessary to twiddle the defining instruction to make a late user happy.

I'll write the SSE specific pass first so I can work out the requirements, but I'll keep this in mind, and generalize later, if possible.

Thanks,
/jakob




From anton at korobeynikov.info  Wed Mar 24 10:26:27 2010
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Wed, 24 Mar 2010 18:26:27 +0300
Subject: [llvm-commits] [llvm] r99345 - in /llvm/trunk/lib/Target/X86:
	CMakeLists.txt SSEDomainFix.cpp X86.h X86InstrInfo.cpp
	X86InstrInfo.h X86TargetMachine.cpp X86TargetMachine.h
In-Reply-To: <F86B3E7A-76B9-47D8-A3A1-2C27049292B0@2pi.dk>
References: <20100323231444.97DDA2A6C12C@llvm.org>
	<b087fca01003240215t72b32009y963d7d8c336dda54@mail.gmail.com>
	<F86B3E7A-76B9-47D8-A3A1-2C27049292B0@2pi.dk>
Message-ID: <b087fca01003240826x2f48f30cye0e3b1bb84923d8@mail.gmail.com>

Hi, Jakob

> We already have the NEONMoveFix pass, but it may be possible to generalize.
Right, but this pass is just a small and "easy" part.

> I need something a bit more fancy for SSE since there are more polymorphic instructions than just a single move, and often it is necessary to twiddle the defining instruction to make a late user happy.
I have crazy idea - maybe it will be possible to integrate such pass
into scheduler somehow? However, this means that we'll need to do
isel+scheduling at once, or something like this.

> I'll write the SSE specific pass first so I can work out the requirements, but I'll keep this in mind, and generalize later, if possible.
Thanks!

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From stoklund at 2pi.dk  Wed Mar 24 11:00:29 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 24 Mar 2010 09:00:29 -0700
Subject: [llvm-commits] [llvm] r99345 - in /llvm/trunk/lib/Target/X86:
	CMakeLists.txt SSEDomainFix.cpp X86.h X86InstrInfo.cpp
	X86InstrInfo.h X86TargetMachine.cpp X86TargetMachine.h
In-Reply-To: <b087fca01003240826x2f48f30cye0e3b1bb84923d8@mail.gmail.com>
References: <20100323231444.97DDA2A6C12C@llvm.org>
	<b087fca01003240215t72b32009y963d7d8c336dda54@mail.gmail.com>
	<F86B3E7A-76B9-47D8-A3A1-2C27049292B0@2pi.dk>
	<b087fca01003240826x2f48f30cye0e3b1bb84923d8@mail.gmail.com>
Message-ID: <61CEADB8-7A10-4BA5-A21C-9F978F7775B9@2pi.dk>


On Mar 24, 2010, at 8:26 AM, Anton Korobeynikov wrote:
>> I need something a bit more fancy for SSE since there are more polymorphic instructions than just a single move, and often it is necessary to twiddle the defining instruction to make a late user happy.
> I have crazy idea - maybe it will be possible to integrate such pass
> into scheduler somehow? However, this means that we'll need to do
> isel+scheduling at once, or something like this.

That is an interesting idea, it is essentially a scheduling problem. The isel during scheduling is not so bad - it is only a matter of switching between instructions with identical inputs and outputs.

But right now we are not scheduling for latency on X86, and we may not want to do that ever for out-of-order machines.

We would also have to make sure that later stages of codegen don't mess things up. CopyRegToReg would need to get more clever. TwoAddressInstrPass could also do bad stuff.

On Blackfin, the separate execution domains are explicit with disjoint register classes (D and P). That is not handled at all currently, and it needs to be taken care of before register allocation.

On the other hand, a late pass is really easy, and I can do a bit of inference across basic blocks too.

/jakob





From grosbach at apple.com  Wed Mar 24 11:07:37 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 24 Mar 2010 16:07:37 -0000
Subject: [llvm-commits] [test-suite] r99401 -
	/test-suite/trunk/Makefile.programs
Message-ID: <20100324160737.6F3A82A6C12C@llvm.org>

Author: grosbach
Date: Wed Mar 24 11:07:37 2010
New Revision: 99401

URL: http://llvm.org/viewvc/llvm-project?rev=99401&view=rev
Log:
clear ARM llcbeta option

Modified:
    test-suite/trunk/Makefile.programs

Modified: test-suite/trunk/Makefile.programs
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=99401&r1=99400&r2=99401&view=diff
==============================================================================
--- test-suite/trunk/Makefile.programs (original)
+++ test-suite/trunk/Makefile.programs Wed Mar 24 11:07:37 2010
@@ -241,10 +241,10 @@
 LLCBETAOPTION := -enable-sparc-v9-insts
 endif
 ifeq ($(ARCH),ARM)
-LLCBETAOPTION := -arm-aggressive-v7-ifcvt
+LLCBETAOPTION :=
 endif
 ifeq ($(ARCH),THUMB)
-LLCBETAOPTION := -arm-aggressive-v7-ifcvt
+LLCBETAOPTION :=
 endif
 
 print-llcbeta-option:




From grosbach at apple.com  Wed Mar 24 11:15:14 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 24 Mar 2010 16:15:14 -0000
Subject: [llvm-commits] [llvm] r99402 -
	/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <20100324161514.E0D5B2A6C12C@llvm.org>

Author: grosbach
Date: Wed Mar 24 11:15:14 2010
New Revision: 99402

URL: http://llvm.org/viewvc/llvm-project?rev=99402&view=rev
Log:
tweak the arm if conversion heuristic

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=99402&r1=99401&r2=99402&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Mar 24 11:15:14 2010
@@ -40,18 +40,12 @@
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/VectorExtras.h"
-#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include <sstream>
 using namespace llvm;
 
-static cl::opt<bool>
-aggressiveV7IfConvert("arm-aggressive-v7-ifcvt", cl::Hidden,
-                      cl::desc("Enable more liberal if-converstion for v7"),
-                      cl::init(false));
-
 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
                                    CCValAssign::LocInfo &LocInfo,
                                    ISD::ArgFlagsTy &ArgFlags,
@@ -462,7 +456,7 @@
     // Generic (and overly aggressive) if-conversion limits.
     setIfCvtBlockSizeLimit(10);
     setIfCvtDupBlockSizeLimit(2);
-  } else if (aggressiveV7IfConvert && Subtarget->hasV7Ops()) {
+  } else if (Subtarget->hasV7Ops()) {
     setIfCvtBlockSizeLimit(3);
     setIfCvtDupBlockSizeLimit(1);
   } else if (Subtarget->hasV6Ops()) {




From clattner at apple.com  Wed Mar 24 11:25:45 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 24 Mar 2010 09:25:45 -0700
Subject: [llvm-commits] [llvm] r99282 - in /llvm/trunk:
	lib/Transforms/Scalar/SimplifyLibCalls.cpp
	lib/Transforms/Utils/BuildLibCalls.cpp
	test/Transforms/SimplifyLibCalls/StrCpy.ll
In-Reply-To: <35161F28-7FBD-4144-BC41-BA40BE9F6618@apple.com>
References: <20100323154804.931872A6C12C@llvm.org>
	<8BA006A9-CBB5-497A-BADA-D5B5B1A14F5F@apple.com>
	<35161F28-7FBD-4144-BC41-BA40BE9F6618@apple.com>
Message-ID: <24A8CC5C-48BD-4C8D-BAF6-C80E635E18A1@apple.com>


On Mar 23, 2010, at 8:10 PM, Evan Cheng wrote:

> 
> On Mar 23, 2010, at 2:42 PM, Chris Lattner wrote:
> 
>> 
>> On Mar 23, 2010, at 8:48 AM, Evan Cheng wrote:
>> 
>>> Author: evancheng
>>> Date: Tue Mar 23 10:48:04 2010
>>> New Revision: 99282
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=99282&view=rev
>>> Log:
>>> Teach simplify libcall to transform __strcpy_chk to __memcpy_chk to enable optimizations down stream.
>> 
>> Hi Evan,
>> 
>>> +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Tue Mar 23 10:48:04 2010
>>> @@ -49,10 +49,13 @@
>>> Function *Caller;
>>> const TargetData *TD;
>>> LLVMContext* Context;
>>> +  bool OptChkCall;  // True if it's optimizing a *_chk libcall.
>> 
>> This is state is not appropriate to add to LibCallOptimization.  If you want to do this, it should be added as a constructor option to StrCpyOpt.
> 
> Why is it inappropriate?

It's inappropriate because you're adding state to LibCallOptimization that only makes sense for StrCpyOpt, please sink it into strcpyopt.

> I can't add it to the constructor option because optimization objects are ivars. I can't construct it with "StrCpyOpt StrCpyChk(true);". And I don't want to heap allocate them.

Just initialize it in the ctor, e.g.:

 SimplifyLibCalls() : FunctionPass(&ID), StrCpy(false), StrCpyChk(true) {}

-Chris




From clattner at apple.com  Wed Mar 24 11:27:05 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 24 Mar 2010 09:27:05 -0700
Subject: [llvm-commits] [llvm] r99345 - in /llvm/trunk/lib/Target/X86:
	CMakeLists.txt SSEDomainFix.cpp X86.h
	X86InstrInfo.cpp	X86InstrInfo.h X86TargetMachine.cpp
	X86TargetMachine.h
In-Reply-To: <61CEADB8-7A10-4BA5-A21C-9F978F7775B9@2pi.dk>
References: <20100323231444.97DDA2A6C12C@llvm.org>
	<b087fca01003240215t72b32009y963d7d8c336dda54@mail.gmail.com>
	<F86B3E7A-76B9-47D8-A3A1-2C27049292B0@2pi.dk>
	<b087fca01003240826x2f48f30cye0e3b1bb84923d8@mail.gmail.com>
	<61CEADB8-7A10-4BA5-A21C-9F978F7775B9@2pi.dk>
Message-ID: <40DEC157-00C7-4E14-B2EB-EAB06822D862@apple.com>


On Mar 24, 2010, at 9:00 AM, Jakob Stoklund Olesen wrote:

> 
> On Mar 24, 2010, at 8:26 AM, Anton Korobeynikov wrote:
>>> I need something a bit more fancy for SSE since there are more polymorphic instructions than just a single move, and often it is necessary to twiddle the defining instruction to make a late user happy.
>> I have crazy idea - maybe it will be possible to integrate such pass
>> into scheduler somehow? However, this means that we'll need to do
>> isel+scheduling at once, or something like this.
> 
> That is an interesting idea, it is essentially a scheduling problem. The isel during scheduling is not so bad - it is only a matter of switching between instructions with identical inputs and outputs.
> 
> But right now we are not scheduling for latency on X86, and we may not want to do that ever for out-of-order machines.
> 
> We would also have to make sure that later stages of codegen don't mess things up. CopyRegToReg would need to get more clever. TwoAddressInstrPass could also do bad stuff.
> 
> On Blackfin, the separate execution domains are explicit with disjoint register classes (D and P). That is not handled at all currently, and it needs to be taken care of before register allocation.
> 
> On the other hand, a late pass is really easy, and I can do a bit of inference across basic blocks too.

Both of these seem like instruction selections problems to me.  The problem is that after isel, we have MVT's on instruction sdnodes instead of register classes.  This problem seems exactly the same as selecting fpstack vs sse instructions for scalar floating point.

-Chris


From stoklund at 2pi.dk  Wed Mar 24 11:54:14 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 24 Mar 2010 09:54:14 -0700
Subject: [llvm-commits] [llvm] r99345 - in /llvm/trunk/lib/Target/X86:
	CMakeLists.txt SSEDomainFix.cpp X86.h
	X86InstrInfo.cpp	X86InstrInfo.h X86TargetMachine.cpp
	X86TargetMachine.h
In-Reply-To: <40DEC157-00C7-4E14-B2EB-EAB06822D862@apple.com>
References: <20100323231444.97DDA2A6C12C@llvm.org>
	<b087fca01003240215t72b32009y963d7d8c336dda54@mail.gmail.com>
	<F86B3E7A-76B9-47D8-A3A1-2C27049292B0@2pi.dk>
	<b087fca01003240826x2f48f30cye0e3b1bb84923d8@mail.gmail.com>
	<61CEADB8-7A10-4BA5-A21C-9F978F7775B9@2pi.dk>
	<40DEC157-00C7-4E14-B2EB-EAB06822D862@apple.com>
Message-ID: <9508C68D-99D0-4319-8ED8-92B90858FFC0@2pi.dk>


On Mar 24, 2010, at 9:27 AM, Chris Lattner wrote:

> 
> On Mar 24, 2010, at 9:00 AM, Jakob Stoklund Olesen wrote:
> 
>> 
>> On Mar 24, 2010, at 8:26 AM, Anton Korobeynikov wrote:
>>>> I need something a bit more fancy for SSE since there are more polymorphic instructions than just a single move, and often it is necessary to twiddle the defining instruction to make a late user happy.
>>> I have crazy idea - maybe it will be possible to integrate such pass
>>> into scheduler somehow? However, this means that we'll need to do
>>> isel+scheduling at once, or something like this.
>> 
>> That is an interesting idea, it is essentially a scheduling problem. The isel during scheduling is not so bad - it is only a matter of switching between instructions with identical inputs and outputs.
>> 
>> But right now we are not scheduling for latency on X86, and we may not want to do that ever for out-of-order machines.
>> 
>> We would also have to make sure that later stages of codegen don't mess things up. CopyRegToReg would need to get more clever. TwoAddressInstrPass could also do bad stuff.
>> 
>> On Blackfin, the separate execution domains are explicit with disjoint register classes (D and P). That is not handled at all currently, and it needs to be taken care of before register allocation.
>> 
>> On the other hand, a late pass is really easy, and I can do a bit of inference across basic blocks too.
> 
> Both of these seem like instruction selections problems to me.  The problem is that after isel, we have MVT's on instruction sdnodes instead of register classes.  This problem seems exactly the same as selecting fpstack vs sse instructions for scalar floating point.

Yep.

If it is handled at isel time we could also handle different instruction patterns in different domains. Right now, I can't even replace shufps with pshufd because one is two-address and one is three-address.

I think that cross-block inference is necessary to get good results. How are the plans for full-function isel? :-)

Note that the cost of crossing domains varies a lot.

On SSE/Nehalem it is a 2-cycle latency-only penalty on an out-of-order CPU.
On ARM it is a 20-cycle penalty on an in-order CPU.
On Blackfin a move instruction (or spill/restore) is required.

/jakob




From grosbach at apple.com  Wed Mar 24 12:07:16 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 24 Mar 2010 17:07:16 -0000
Subject: [llvm-commits] [test-suite] r99406 -
 /test-suite/trunk/MultiSource/Applications/lemon/Makefile
Message-ID: <20100324170716.733A62A6C12C@llvm.org>

Author: grosbach
Date: Wed Mar 24 12:07:16 2010
New Revision: 99406

URL: http://llvm.org/viewvc/llvm-project?rev=99406&view=rev
Log:
Support for builddir != srcdir

Modified:
    test-suite/trunk/MultiSource/Applications/lemon/Makefile

Modified: test-suite/trunk/MultiSource/Applications/lemon/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Applications/lemon/Makefile?rev=99406&r1=99405&r2=99406&view=diff
==============================================================================
--- test-suite/trunk/MultiSource/Applications/lemon/Makefile (original)
+++ test-suite/trunk/MultiSource/Applications/lemon/Makefile Wed Mar 24 12:07:16 2010
@@ -3,7 +3,7 @@
 Source = lemon.c
 
 PROG = lemon
-RUN_OPTIONS = parse.y example1.y example2.y example3.y example4.y example5.y lighttpd_configparser.y lighttpd_mod_ssi_exprparser.y wireshark_dtd_grammar.lemon wireshark_grammar.lemon wireshark_mate_grammar.lemon xapian_queryparser.lemony ecmascript.y
+RUN_OPTIONS = $(PROJ_SRC_DIR)/parse.y $(PROJ_SRC_DIR)/example1.y $(PROJ_SRC_DIR)/example2.y $(PROJ_SRC_DIR)/example3.y $(PROJ_SRC_DIR)/example4.y $(PROJ_SRC_DIR)/example5.y $(PROJ_SRC_DIR)/lighttpd_configparser.y $(PROJ_SRC_DIR)/lighttpd_mod_ssi_exprparser.y $(PROJ_SRC_DIR)/wireshark_dtd_grammar.lemon $(PROJ_SRC_DIR)/wireshark_grammar.lemon $(PROJ_SRC_DIR)/wireshark_mate_grammar.lemon $(PROJ_SRC_DIR)/xapian_queryparser.lemony $(PROJ_SRC_DIR)/ecmascript.y
 
 include $(LEVEL)/Makefile.config
 




From bob.wilson at apple.com  Wed Mar 24 12:27:14 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 24 Mar 2010 10:27:14 -0700
Subject: [llvm-commits] [llvm] r99326 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrNEON.td
In-Reply-To: <23F4D5CA-FEE3-430B-BE39-D2B9C931B114@apple.com>
References: <20100323212538.8E13F2A6C12C@llvm.org>
	<965001EB-F442-4602-86B2-90FE8620B3A2@apple.com>
	<23F4D5CA-FEE3-430B-BE39-D2B9C931B114@apple.com>
Message-ID: <6511590C-4358-4E5F-9C98-FF1A2A823863@apple.com>


On Mar 23, 2010, at 5:54 PM, Johnny Chen wrote:

> I will rename NVdVmImmFrm to the more proper N2RegFrm.

OK, thanks.  (It would be helpful to keep this discussion threaded so I can keep track of which patches have been reviewed.  You're replying here to my review of r99326 with a comment that responds to my feedback on r99322.)

> N2V2 is still necessary, though, because of N2VS, N2VD, N2VQ, which are for vcvt instructions.

The N2V2 class is identical to the existing N2V class except that you've added a Format argument.  Just add the Format argument to N2V and then you don't need to make a new class.

I have a further comment about adding a new format for VCVT.  This should not be necessary, since the VCVT instructions that you've changed here have the same basic 2-register encoding format as other instructions like VMVN, VNEG, etc.  If you still think it is needed, please explain.  Otherwise, please revert this patch (r99326).

> 
> On Mar 23, 2010, at 2:45 PM, Bob Wilson wrote:
> 
>> 
>> On Mar 23, 2010, at 2:25 PM, Johnny Chen wrote:
>> 
>>> Author: johnny
>>> Date: Tue Mar 23 16:25:38 2010
>>> New Revision: 99326
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=99326&view=rev
>>> Log:
>>> Add New NEON Format NVdVmVCVTFrm.
>>> Converted some of the NEON vcvt instructions to this format.
>>> 
>>> Modified:
>>>  llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>>  llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99326&r1=99325&r2=99326&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 16:25:38 2010
>>> @@ -62,6 +62,7 @@
>>> def NLdStFrm                : Format<31>;
>>> def NVdImmFrm               : Format<32>;
>>> def NVdVmImmFrm             : Format<33>;
>>> +def NVdVmVCVTFrm            : Format<34>;
>> 
>> How about "NVCVTFrm"?
>> 
>> 
>>> 
>>> // Misc flags.
>>> 
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99326&r1=99325&r2=99326&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 16:25:38 2010
>>> @@ -853,25 +853,40 @@
>>> // Instruction Classes
>>> //===----------------------------------------------------------------------===//
>>> 
>>> +// Same as N2V except that it doesn't pass a default NVdVmImmFrm to NDataI.
>>> +class N2V2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
>>> +          bits<5> op11_7, bit op6, bit op4,
>>> +          dag oops, dag iops, Format f, InstrItinClass itin,
>>> +          string opc, string dt, string asm, string cstr, list<dag> pattern>
>>> +  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
>>> +  let Inst{24-23} = op24_23;
>>> +  let Inst{21-20} = op21_20;
>>> +  let Inst{19-18} = op19_18;
>>> +  let Inst{17-16} = op17_16;
>>> +  let Inst{11-7} = op11_7;
>>> +  let Inst{6} = op6;
>>> +  let Inst{4} = op4;
>>> +}
>>> +
>> 
>> This should not be necessary.  You should not have added the NVdVmImmFrm for N2V to begin with (per my earlier comments).  Please remove this class.
>> 
>> 
>>> // Basic 2-register operations: single-, double- and quad-register.
>>> class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>          bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>>          string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
>>> -        (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
>>> -        IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
>>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
>>> +         (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NVdVmVCVTFrm,
>>> +         IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
>>> class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>          bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>>          string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
>>> -        (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
>>> -        [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
>>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
>>> +         (ins DPR:$src), NVdVmVCVTFrm, IIC_VUNAD, OpcodeStr, Dt,"$dst, $src","",
>>> +         [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
>>> class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>          bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>>          string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
>>> -        (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
>>> -        [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
>>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
>>> +         (ins QPR:$src), NVdVmVCVTFrm, IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src","",
>>> +         [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
>>> 
>>> // Basic 2-register intrinsics, both double- and quad-register.
>>> class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
> 




From bob.wilson at apple.com  Wed Mar 24 12:30:26 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 24 Mar 2010 10:30:26 -0700
Subject: [llvm-commits] [llvm] r99376 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
In-Reply-To: <20100324012926.119612A6C12C@llvm.org>
References: <20100324012926.119612A6C12C@llvm.org>
Message-ID: <8E871C06-D032-43A0-B038-216620C3A640@apple.com>

Please add a format argument to the N3VX class and use that here instead of this "let" assignment.

On Mar 23, 2010, at 6:29 PM, Johnny Chen wrote:

> Author: johnny
> Date: Tue Mar 23 20:29:25 2010
> New Revision: 99376
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99376&view=rev
> Log:
> Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99376&r1=99375&r2=99376&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 20:29:25 2010
> @@ -2778,10 +2778,13 @@
> 
> //   VMOV     : Vector Move (Register)
> 
> +// Mark these as 2-register instructions to help the disassembler.
> +let F = N2RegFrm, Form = N2RegFrm.Value in {
> def  VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
> -                    IIC_VMOVD, "vmov", "$dst, $src", "", []>;
> +                     IIC_VMOVD, "vmov", "$dst, $src", "", []>;
> def  VMOVQ    : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
> -                    IIC_VMOVD, "vmov", "$dst, $src", "", []>;
> +                     IIC_VMOVD, "vmov", "$dst, $src", "", []>;
> +}
> 
> //   VMOV     : Vector Move (Immediate)
> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From clattner at apple.com  Wed Mar 24 12:32:07 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 24 Mar 2010 10:32:07 -0700
Subject: [llvm-commits] [llvm] r99345 - in /llvm/trunk/lib/Target/X86:
	CMakeLists.txt SSEDomainFix.cpp X86.h
	X86InstrInfo.cpp	X86InstrInfo.h X86TargetMachine.cpp
	X86TargetMachine.h
In-Reply-To: <9508C68D-99D0-4319-8ED8-92B90858FFC0@2pi.dk>
References: <20100323231444.97DDA2A6C12C@llvm.org>
	<b087fca01003240215t72b32009y963d7d8c336dda54@mail.gmail.com>
	<F86B3E7A-76B9-47D8-A3A1-2C27049292B0@2pi.dk>
	<b087fca01003240826x2f48f30cye0e3b1bb84923d8@mail.gmail.com>
	<61CEADB8-7A10-4BA5-A21C-9F978F7775B9@2pi.dk>
	<40DEC157-00C7-4E14-B2EB-EAB06822D862@apple.com>
	<9508C68D-99D0-4319-8ED8-92B90858FFC0@2pi.dk>
Message-ID: <DB907D9C-5A5C-4E54-8037-38AB13645EE7@apple.com>


On Mar 24, 2010, at 9:54 AM, Jakob Stoklund Olesen wrote:

>>> On Blackfin, the separate execution domains are explicit with disjoint register classes (D and P). That is not handled at all currently, and it needs to be taken care of before register allocation.
>>> 
>>> On the other hand, a late pass is really easy, and I can do a bit of inference across basic blocks too.
>> 
>> Both of these seem like instruction selections problems to me.  The problem is that after isel, we have MVT's on instruction sdnodes instead of register classes.  This problem seems exactly the same as selecting fpstack vs sse instructions for scalar floating point.
> 
> Yep.
> 
> If it is handled at isel time we could also handle different instruction patterns in different domains. Right now, I can't even replace shufps with pshufd because one is two-address and one is three-address.

Right.

> I think that cross-block inference is necessary to get good results. How are the plans for full-function isel? :-)

Exactly :)

> Note that the cost of crossing domains varies a lot.
> 
> On SSE/Nehalem it is a 2-cycle latency-only penalty on an out-of-order CPU.
> On ARM it is a 20-cycle penalty on an in-order CPU.
> On Blackfin a move instruction (or spill/restore) is required.

To be clear, I'm not objecting to the current plan of doing this as a late pass.  Changing isel to model this is a big change (but would solve other problems as well), so handling this late seems fine in the intermediate.  I just don't think we should tackle this as a scheduling problem.

-Chris  




From bob.wilson at apple.com  Wed Mar 24 12:36:40 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 24 Mar 2010 10:36:40 -0700
Subject: [llvm-commits] [llvm] r99376 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
In-Reply-To: <8E871C06-D032-43A0-B038-216620C3A640@apple.com>
References: <20100324012926.119612A6C12C@llvm.org>
	<8E871C06-D032-43A0-B038-216620C3A640@apple.com>
Message-ID: <A8E78B44-1271-4404-83CC-2FA585F7DA9D@apple.com>


On Mar 24, 2010, at 10:30 AM, Bob Wilson wrote:

> Please add a format argument to the N3VX class and use that here instead of this "let" assignment.

Hold that thought.  VMOVDneon and VMOVQ are not standard 2-register format instructions.  The "M" and "Vm" encoding fields are duplicated and must be consistent.  From an encoding perspective, "VMOV Vd, Vm" is equivalent to "VORR Vd, Vm, Vn" where m == n.

How do you intend to handle these instructions?  I think they should have a 3-register format and then add a special case in the encoding/decoding functions to distinguish VMOV from VORR.

> 
> On Mar 23, 2010, at 6:29 PM, Johnny Chen wrote:
> 
>> Author: johnny
>> Date: Tue Mar 23 20:29:25 2010
>> New Revision: 99376
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99376&view=rev
>> Log:
>> Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99376&r1=99375&r2=99376&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 20:29:25 2010
>> @@ -2778,10 +2778,13 @@
>> 
>> //   VMOV     : Vector Move (Register)
>> 
>> +// Mark these as 2-register instructions to help the disassembler.
>> +let F = N2RegFrm, Form = N2RegFrm.Value in {
>> def  VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
>> -                    IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>> +                     IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>> def  VMOVQ    : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
>> -                    IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>> +                     IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>> +}
>> 
>> //   VMOV     : Vector Move (Immediate)
>> 
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From evan.cheng at apple.com  Wed Mar 24 12:41:17 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 24 Mar 2010 10:41:17 -0700
Subject: [llvm-commits] [llvm] r99282 - in /llvm/trunk:
	lib/Transforms/Scalar/SimplifyLibCalls.cpp
	lib/Transforms/Utils/BuildLibCalls.cpp
	test/Transforms/SimplifyLibCalls/StrCpy.ll
In-Reply-To: <24A8CC5C-48BD-4C8D-BAF6-C80E635E18A1@apple.com>
References: <20100323154804.931872A6C12C@llvm.org>
	<8BA006A9-CBB5-497A-BADA-D5B5B1A14F5F@apple.com>
	<35161F28-7FBD-4144-BC41-BA40BE9F6618@apple.com>
	<24A8CC5C-48BD-4C8D-BAF6-C80E635E18A1@apple.com>
Message-ID: <24FE6281-2894-41F4-87C1-8C61A3876409@apple.com>


On Mar 24, 2010, at 9:25 AM, Chris Lattner wrote:

> 
> On Mar 23, 2010, at 8:10 PM, Evan Cheng wrote:
> 
>> 
>> On Mar 23, 2010, at 2:42 PM, Chris Lattner wrote:
>> 
>>> 
>>> On Mar 23, 2010, at 8:48 AM, Evan Cheng wrote:
>>> 
>>>> Author: evancheng
>>>> Date: Tue Mar 23 10:48:04 2010
>>>> New Revision: 99282
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=99282&view=rev
>>>> Log:
>>>> Teach simplify libcall to transform __strcpy_chk to __memcpy_chk to enable optimizations down stream.
>>> 
>>> Hi Evan,
>>> 
>>>> +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Tue Mar 23 10:48:04 2010
>>>> @@ -49,10 +49,13 @@
>>>> Function *Caller;
>>>> const TargetData *TD;
>>>> LLVMContext* Context;
>>>> +  bool OptChkCall;  // True if it's optimizing a *_chk libcall.
>>> 
>>> This is state is not appropriate to add to LibCallOptimization.  If you want to do this, it should be added as a constructor option to StrCpyOpt.
>> 
>> Why is it inappropriate?
> 
> It's inappropriate because you're adding state to LibCallOptimization that only makes sense for StrCpyOpt, please sink it into strcpyopt.

We will be adding other _chk variants. It's common across a large number of string and memory libcalls.

> 
>> I can't add it to the constructor option because optimization objects are ivars. I can't construct it with "StrCpyOpt StrCpyChk(true);". And I don't want to heap allocate them.
> 
> Just initialize it in the ctor, e.g.:
> 
> SimplifyLibCalls() : FunctionPass(&ID), StrCpy(false), StrCpyChk(true) {}

Duh. Of course.

Evan
> 
> -Chris
> 




From johnny.chen at apple.com  Wed Mar 24 12:44:59 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Wed, 24 Mar 2010 10:44:59 -0700
Subject: [llvm-commits] [llvm] r99376 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
In-Reply-To: <A8E78B44-1271-4404-83CC-2FA585F7DA9D@apple.com>
References: <20100324012926.119612A6C12C@llvm.org>
	<8E871C06-D032-43A0-B038-216620C3A640@apple.com>
	<A8E78B44-1271-4404-83CC-2FA585F7DA9D@apple.com>
Message-ID: <5CE9E000-AF8E-4DCB-BCD6-C3A453634F47@apple.com>

I think they should have a 2-register format for semantic reason.
The decoder has already gone through the hassle of recognizing
that Vm == Vn and return an Opcode of VMOVDneon/VMOVQ.

There are 14 consumers of N3VX, only two of them have exceptional meanings.
I can change the disassembler code to special case VMOVDneon/VMOVQ when dealing
with 3-register format instructions if you insist thay both should be 3-register format instructions.

On Mar 24, 2010, at 10:36 AM, Bob Wilson wrote:

> 
> On Mar 24, 2010, at 10:30 AM, Bob Wilson wrote:
> 
>> Please add a format argument to the N3VX class and use that here instead of this "let" assignment.
> 
> Hold that thought.  VMOVDneon and VMOVQ are not standard 2-register format instructions.  The "M" and "Vm" encoding fields are duplicated and must be consistent.  From an encoding perspective, "VMOV Vd, Vm" is equivalent to "VORR Vd, Vm, Vn" where m == n.
> 
> How do you intend to handle these instructions?  I think they should have a 3-register format and then add a special case in the encoding/decoding functions to distinguish VMOV from VORR.
> 
>> 
>> On Mar 23, 2010, at 6:29 PM, Johnny Chen wrote:
>> 
>>> Author: johnny
>>> Date: Tue Mar 23 20:29:25 2010
>>> New Revision: 99376
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=99376&view=rev
>>> Log:
>>> Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
>>> 
>>> Modified:
>>>  llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99376&r1=99375&r2=99376&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 20:29:25 2010
>>> @@ -2778,10 +2778,13 @@
>>> 
>>> //   VMOV     : Vector Move (Register)
>>> 
>>> +// Mark these as 2-register instructions to help the disassembler.
>>> +let F = N2RegFrm, Form = N2RegFrm.Value in {
>>> def  VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
>>> -                    IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>>> +                     IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>>> def  VMOVQ    : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
>>> -                    IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>>> +                     IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>>> +}
>>> 
>>> //   VMOV     : Vector Move (Immediate)
>>> 
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 




From evan.cheng at apple.com  Wed Mar 24 12:45:29 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 24 Mar 2010 10:45:29 -0700
Subject: [llvm-commits] [llvm] r99345 - in /llvm/trunk/lib/Target/X86:
	CMakeLists.txt SSEDomainFix.cpp
	X86.h	X86InstrInfo.cpp	X86InstrInfo.h
	X86TargetMachine.cpp	X86TargetMachine.h
In-Reply-To: <DB907D9C-5A5C-4E54-8037-38AB13645EE7@apple.com>
References: <20100323231444.97DDA2A6C12C@llvm.org>
	<b087fca01003240215t72b32009y963d7d8c336dda54@mail.gmail.com>
	<F86B3E7A-76B9-47D8-A3A1-2C27049292B0@2pi.dk>
	<b087fca01003240826x2f48f30cye0e3b1bb84923d8@mail.gmail.com>
	<61CEADB8-7A10-4BA5-A21C-9F978F7775B9@2pi.dk>
	<40DEC157-00C7-4E14-B2EB-EAB06822D862@apple.com>
	<9508C68D-99D0-4319-8ED8-92B90858FFC0@2pi.dk>
	<DB907D9C-5A5C-4E54-8037-38AB13645EE7@apple.com>
Message-ID: <4DD1F058-8354-413A-A006-2CBC17500137@apple.com>


On Mar 24, 2010, at 10:32 AM, Chris Lattner wrote:

> 
> On Mar 24, 2010, at 9:54 AM, Jakob Stoklund Olesen wrote:
> 
>>>> On Blackfin, the separate execution domains are explicit with disjoint register classes (D and P). That is not handled at all currently, and it needs to be taken care of before register allocation.
>>>> 
>>>> On the other hand, a late pass is really easy, and I can do a bit of inference across basic blocks too.
>>> 
>>> Both of these seem like instruction selections problems to me.  The problem is that after isel, we have MVT's on instruction sdnodes instead of register classes.  This problem seems exactly the same as selecting fpstack vs sse instructions for scalar floating point.
>> 
>> Yep.
>> 
>> If it is handled at isel time we could also handle different instruction patterns in different domains. Right now, I can't even replace shufps with pshufd because one is two-address and one is three-address.
> 
> Right.
> 
>> I think that cross-block inference is necessary to get good results. How are the plans for full-function isel? :-)
> 
> Exactly :)
> 
>> Note that the cost of crossing domains varies a lot.
>> 
>> On SSE/Nehalem it is a 2-cycle latency-only penalty on an out-of-order CPU.
>> On ARM it is a 20-cycle penalty on an in-order CPU.
>> On Blackfin a move instruction (or spill/restore) is required.
> 
> To be clear, I'm not objecting to the current plan of doing this as a late pass.  Changing isel to model this is a big change (but would solve other problems as well), so handling this late seems fine in the intermediate.  I just don't think we should tackle this as a scheduling problem.
> 

I don't see this as a isel problem. 1. Changing isel will only fix part of the problem, it will miss copies, loads, and stores introduced later. 2. We don't particularly care about choosing instructions based on the type information coming into isel. After all, users can write code that introduce domain crossing. Eliminating domain crossing is purely an optimization.

Evan


> -Chris  
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From johnny.chen at apple.com  Wed Mar 24 12:49:48 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Wed, 24 Mar 2010 10:49:48 -0700
Subject: [llvm-commits] [llvm] r99326 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrNEON.td
In-Reply-To: <6511590C-4358-4E5F-9C98-FF1A2A823863@apple.com>
References: <20100323212538.8E13F2A6C12C@llvm.org>
	<965001EB-F442-4602-86B2-90FE8620B3A2@apple.com>
	<23F4D5CA-FEE3-430B-BE39-D2B9C931B114@apple.com>
	<6511590C-4358-4E5F-9C98-FF1A2A823863@apple.com>
Message-ID: <B9313494-3DCB-4004-B2DC-BB7AD12F3B4D@apple.com>

I originally meant NVCVTFrm to cover all NEON vcvt instructions, and the upcoming patch uses
NVCVTFrm for "Convert, with fractional bits immediate".

This patch is more complex and involves more new formats.  So I will keep the NVCVTFrm and
remove N2V2 so that NVCVTFrm only covers vcvt with fractional bits immediate.

How's that?

On Mar 24, 2010, at 10:27 AM, Bob Wilson wrote:

> 
> On Mar 23, 2010, at 5:54 PM, Johnny Chen wrote:
> 
>> I will rename NVdVmImmFrm to the more proper N2RegFrm.
> 
> OK, thanks.  (It would be helpful to keep this discussion threaded so I can keep track of which patches have been reviewed.  You're replying here to my review of r99326 with a comment that responds to my feedback on r99322.)
> 
>> N2V2 is still necessary, though, because of N2VS, N2VD, N2VQ, which are for vcvt instructions.
> 
> The N2V2 class is identical to the existing N2V class except that you've added a Format argument.  Just add the Format argument to N2V and then you don't need to make a new class.
> 
> I have a further comment about adding a new format for VCVT.  This should not be necessary, since the VCVT instructions that you've changed here have the same basic 2-register encoding format as other instructions like VMVN, VNEG, etc.  If you still think it is needed, please explain.  Otherwise, please revert this patch (r99326).
> 
>> 
>> On Mar 23, 2010, at 2:45 PM, Bob Wilson wrote:
>> 
>>> 
>>> On Mar 23, 2010, at 2:25 PM, Johnny Chen wrote:
>>> 
>>>> Author: johnny
>>>> Date: Tue Mar 23 16:25:38 2010
>>>> New Revision: 99326
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=99326&view=rev
>>>> Log:
>>>> Add New NEON Format NVdVmVCVTFrm.
>>>> Converted some of the NEON vcvt instructions to this format.
>>>> 
>>>> Modified:
>>>> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>>> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>>> 
>>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99326&r1=99325&r2=99326&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 16:25:38 2010
>>>> @@ -62,6 +62,7 @@
>>>> def NLdStFrm                : Format<31>;
>>>> def NVdImmFrm               : Format<32>;
>>>> def NVdVmImmFrm             : Format<33>;
>>>> +def NVdVmVCVTFrm            : Format<34>;
>>> 
>>> How about "NVCVTFrm"?
>>> 
>>> 
>>>> 
>>>> // Misc flags.
>>>> 
>>>> 
>>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99326&r1=99325&r2=99326&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 16:25:38 2010
>>>> @@ -853,25 +853,40 @@
>>>> // Instruction Classes
>>>> //===----------------------------------------------------------------------===//
>>>> 
>>>> +// Same as N2V except that it doesn't pass a default NVdVmImmFrm to NDataI.
>>>> +class N2V2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
>>>> +          bits<5> op11_7, bit op6, bit op4,
>>>> +          dag oops, dag iops, Format f, InstrItinClass itin,
>>>> +          string opc, string dt, string asm, string cstr, list<dag> pattern>
>>>> +  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
>>>> +  let Inst{24-23} = op24_23;
>>>> +  let Inst{21-20} = op21_20;
>>>> +  let Inst{19-18} = op19_18;
>>>> +  let Inst{17-16} = op17_16;
>>>> +  let Inst{11-7} = op11_7;
>>>> +  let Inst{6} = op6;
>>>> +  let Inst{4} = op4;
>>>> +}
>>>> +
>>> 
>>> This should not be necessary.  You should not have added the NVdVmImmFrm for N2V to begin with (per my earlier comments).  Please remove this class.
>>> 
>>> 
>>>> // Basic 2-register operations: single-, double- and quad-register.
>>>> class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>>         bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>>>         string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>>>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
>>>> -        (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
>>>> -        IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
>>>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
>>>> +         (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NVdVmVCVTFrm,
>>>> +         IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
>>>> class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>>         bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>>>         string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>>>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
>>>> -        (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
>>>> -        [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
>>>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
>>>> +         (ins DPR:$src), NVdVmVCVTFrm, IIC_VUNAD, OpcodeStr, Dt,"$dst, $src","",
>>>> +         [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
>>>> class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>>         bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>>>         string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>>>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
>>>> -        (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
>>>> -        [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
>>>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
>>>> +         (ins QPR:$src), NVdVmVCVTFrm, IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src","",
>>>> +         [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
>>>> 
>>>> // Basic 2-register intrinsics, both double- and quad-register.
>>>> class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>> 
>>>> 
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>> 
>> 
> 




From bob.wilson at apple.com  Wed Mar 24 12:51:02 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 24 Mar 2010 10:51:02 -0700
Subject: [llvm-commits] [llvm] r99376 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
In-Reply-To: <5CE9E000-AF8E-4DCB-BCD6-C3A453634F47@apple.com>
References: <20100324012926.119612A6C12C@llvm.org>
	<8E871C06-D032-43A0-B038-216620C3A640@apple.com>
	<A8E78B44-1271-4404-83CC-2FA585F7DA9D@apple.com>
	<5CE9E000-AF8E-4DCB-BCD6-C3A453634F47@apple.com>
Message-ID: <10A72CDE-ACFF-4600-A9DF-39912A714047@apple.com>


On Mar 24, 2010, at 10:44 AM, Johnny Chen wrote:

> I think they should have a 2-register format for semantic reason.

The instruction format is used to describe the encoding bits, not the semantics.

> The decoder has already gone through the hassle of recognizing
> that Vm == Vn and return an Opcode of VMOVDneon/VMOVQ.
> 
> There are 14 consumers of N3VX, only two of them have exceptional meanings.
> I can change the disassembler code to special case VMOVDneon/VMOVQ when dealing
> with 3-register format instructions if you insist thay both should be 3-register format instructions.

Yes, please change the disassembler.  Then you won't need this change at all.

> 
> On Mar 24, 2010, at 10:36 AM, Bob Wilson wrote:
> 
>> 
>> On Mar 24, 2010, at 10:30 AM, Bob Wilson wrote:
>> 
>>> Please add a format argument to the N3VX class and use that here instead of this "let" assignment.
>> 
>> Hold that thought.  VMOVDneon and VMOVQ are not standard 2-register format instructions.  The "M" and "Vm" encoding fields are duplicated and must be consistent.  From an encoding perspective, "VMOV Vd, Vm" is equivalent to "VORR Vd, Vm, Vn" where m == n.
>> 
>> How do you intend to handle these instructions?  I think they should have a 3-register format and then add a special case in the encoding/decoding functions to distinguish VMOV from VORR.
>> 
>>> 
>>> On Mar 23, 2010, at 6:29 PM, Johnny Chen wrote:
>>> 
>>>> Author: johnny
>>>> Date: Tue Mar 23 20:29:25 2010
>>>> New Revision: 99376
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=99376&view=rev
>>>> Log:
>>>> Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
>>>> 
>>>> Modified:
>>>> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>>> 
>>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99376&r1=99375&r2=99376&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 20:29:25 2010
>>>> @@ -2778,10 +2778,13 @@
>>>> 
>>>> //   VMOV     : Vector Move (Register)
>>>> 
>>>> +// Mark these as 2-register instructions to help the disassembler.
>>>> +let F = N2RegFrm, Form = N2RegFrm.Value in {
>>>> def  VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
>>>> -                    IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>>>> +                     IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>>>> def  VMOVQ    : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
>>>> -                    IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>>>> +                     IIC_VMOVD, "vmov", "$dst, $src", "", []>;
>>>> +}
>>>> 
>>>> //   VMOV     : Vector Move (Immediate)
>>>> 
>>>> 
>>>> 
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
> 




From bob.wilson at apple.com  Wed Mar 24 12:55:25 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 24 Mar 2010 10:55:25 -0700
Subject: [llvm-commits] [llvm] r99326 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrNEON.td
In-Reply-To: <B9313494-3DCB-4004-B2DC-BB7AD12F3B4D@apple.com>
References: <20100323212538.8E13F2A6C12C@llvm.org>
	<965001EB-F442-4602-86B2-90FE8620B3A2@apple.com>
	<23F4D5CA-FEE3-430B-BE39-D2B9C931B114@apple.com>
	<6511590C-4358-4E5F-9C98-FF1A2A823863@apple.com>
	<B9313494-3DCB-4004-B2DC-BB7AD12F3B4D@apple.com>
Message-ID: <D78DFFE0-582C-4E1E-B130-383D44C2121E@apple.com>


On Mar 24, 2010, at 10:49 AM, Johnny Chen wrote:

> I originally meant NVCVTFrm to cover all NEON vcvt instructions, and the upcoming patch uses
> NVCVTFrm for "Convert, with fractional bits immediate".

The "VCVT with immediate" format must be distinct.  The VCVT format you have now is used for the _other_ VCVT instructions (with no immediates).  There is no need for that.  Please revert this patch.

> 
> This patch is more complex and involves more new formats.  So I will keep the NVCVTFrm and
> remove N2V2 so that NVCVTFrm only covers vcvt with fractional bits immediate.
> 
> How's that?

No, we need to resolve the current set of changes before adding more on top.

> 
> On Mar 24, 2010, at 10:27 AM, Bob Wilson wrote:
> 
>> 
>> On Mar 23, 2010, at 5:54 PM, Johnny Chen wrote:
>> 
>>> I will rename NVdVmImmFrm to the more proper N2RegFrm.
>> 
>> OK, thanks.  (It would be helpful to keep this discussion threaded so I can keep track of which patches have been reviewed.  You're replying here to my review of r99326 with a comment that responds to my feedback on r99322.)
>> 
>>> N2V2 is still necessary, though, because of N2VS, N2VD, N2VQ, which are for vcvt instructions.
>> 
>> The N2V2 class is identical to the existing N2V class except that you've added a Format argument.  Just add the Format argument to N2V and then you don't need to make a new class.
>> 
>> I have a further comment about adding a new format for VCVT.  This should not be necessary, since the VCVT instructions that you've changed here have the same basic 2-register encoding format as other instructions like VMVN, VNEG, etc.  If you still think it is needed, please explain.  Otherwise, please revert this patch (r99326).
>> 
>>> 
>>> On Mar 23, 2010, at 2:45 PM, Bob Wilson wrote:
>>> 
>>>> 
>>>> On Mar 23, 2010, at 2:25 PM, Johnny Chen wrote:
>>>> 
>>>>> Author: johnny
>>>>> Date: Tue Mar 23 16:25:38 2010
>>>>> New Revision: 99326
>>>>> 
>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=99326&view=rev
>>>>> Log:
>>>>> Add New NEON Format NVdVmVCVTFrm.
>>>>> Converted some of the NEON vcvt instructions to this format.
>>>>> 
>>>>> Modified:
>>>>> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>>>> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>>>> 
>>>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99326&r1=99325&r2=99326&view=diff
>>>>> ==============================================================================
>>>>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>>>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 16:25:38 2010
>>>>> @@ -62,6 +62,7 @@
>>>>> def NLdStFrm                : Format<31>;
>>>>> def NVdImmFrm               : Format<32>;
>>>>> def NVdVmImmFrm             : Format<33>;
>>>>> +def NVdVmVCVTFrm            : Format<34>;
>>>> 
>>>> How about "NVCVTFrm"?
>>>> 
>>>> 
>>>>> 
>>>>> // Misc flags.
>>>>> 
>>>>> 
>>>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99326&r1=99325&r2=99326&view=diff
>>>>> ==============================================================================
>>>>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>>>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 16:25:38 2010
>>>>> @@ -853,25 +853,40 @@
>>>>> // Instruction Classes
>>>>> //===----------------------------------------------------------------------===//
>>>>> 
>>>>> +// Same as N2V except that it doesn't pass a default NVdVmImmFrm to NDataI.
>>>>> +class N2V2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
>>>>> +          bits<5> op11_7, bit op6, bit op4,
>>>>> +          dag oops, dag iops, Format f, InstrItinClass itin,
>>>>> +          string opc, string dt, string asm, string cstr, list<dag> pattern>
>>>>> +  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
>>>>> +  let Inst{24-23} = op24_23;
>>>>> +  let Inst{21-20} = op21_20;
>>>>> +  let Inst{19-18} = op19_18;
>>>>> +  let Inst{17-16} = op17_16;
>>>>> +  let Inst{11-7} = op11_7;
>>>>> +  let Inst{6} = op6;
>>>>> +  let Inst{4} = op4;
>>>>> +}
>>>>> +
>>>> 
>>>> This should not be necessary.  You should not have added the NVdVmImmFrm for N2V to begin with (per my earlier comments).  Please remove this class.
>>>> 
>>>> 
>>>>> // Basic 2-register operations: single-, double- and quad-register.
>>>>> class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>>>        bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>>>>        string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>>>>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
>>>>> -        (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
>>>>> -        IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
>>>>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
>>>>> +         (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NVdVmVCVTFrm,
>>>>> +         IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
>>>>> class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>>>        bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>>>>        string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>>>>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
>>>>> -        (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
>>>>> -        [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
>>>>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
>>>>> +         (ins DPR:$src), NVdVmVCVTFrm, IIC_VUNAD, OpcodeStr, Dt,"$dst, $src","",
>>>>> +         [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
>>>>> class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>>>        bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>>>>        string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>>>>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
>>>>> -        (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
>>>>> -        [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
>>>>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
>>>>> +         (ins QPR:$src), NVdVmVCVTFrm, IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src","",
>>>>> +         [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
>>>>> 
>>>>> // Basic 2-register intrinsics, both double- and quad-register.
>>>>> class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>>> 
>>>>> 
>>>>> _______________________________________________
>>>>> llvm-commits mailing list
>>>>> llvm-commits at cs.uiuc.edu
>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>> 
>>> 
>> 
> 




From clattner at apple.com  Wed Mar 24 13:07:51 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 24 Mar 2010 11:07:51 -0700
Subject: [llvm-commits] [llvm] r99282 - in /llvm/trunk:
	lib/Transforms/Scalar/SimplifyLibCalls.cpp
	lib/Transforms/Utils/BuildLibCalls.cpp
	test/Transforms/SimplifyLibCalls/StrCpy.ll
In-Reply-To: <24FE6281-2894-41F4-87C1-8C61A3876409@apple.com>
References: <20100323154804.931872A6C12C@llvm.org>
	<8BA006A9-CBB5-497A-BADA-D5B5B1A14F5F@apple.com>
	<35161F28-7FBD-4144-BC41-BA40BE9F6618@apple.com>
	<24A8CC5C-48BD-4C8D-BAF6-C80E635E18A1@apple.com>
	<24FE6281-2894-41F4-87C1-8C61A3876409@apple.com>
Message-ID: <5224EF3C-8D30-4159-8880-13D7702E6733@apple.com>


On Mar 24, 2010, at 10:41 AM, Evan Cheng wrote:

>> 
>> It's inappropriate because you're adding state to LibCallOptimization that only makes sense for StrCpyOpt, please sink it into strcpyopt.
> 
> We will be adding other _chk variants. It's common across a large number of string and memory libcalls.

Please add it to each relevant subclass,  pow_chk is hopefully never going to happen :)

-Chris
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From johnny.chen at apple.com  Wed Mar 24 13:15:52 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Wed, 24 Mar 2010 11:15:52 -0700
Subject: [llvm-commits] [llvm] r99326 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrNEON.td
In-Reply-To: <D78DFFE0-582C-4E1E-B130-383D44C2121E@apple.com>
References: <20100323212538.8E13F2A6C12C@llvm.org>
	<965001EB-F442-4602-86B2-90FE8620B3A2@apple.com>
	<23F4D5CA-FEE3-430B-BE39-D2B9C931B114@apple.com>
	<6511590C-4358-4E5F-9C98-FF1A2A823863@apple.com>
	<B9313494-3DCB-4004-B2DC-BB7AD12F3B4D@apple.com>
	<D78DFFE0-582C-4E1E-B130-383D44C2121E@apple.com>
Message-ID: <5762FEE2-FE31-43C1-801A-FD2BCFEDEAE3@apple.com>

OK.  I will revert the NVCVTFrm patch.

On Mar 24, 2010, at 10:55 AM, Bob Wilson wrote:

> 
> On Mar 24, 2010, at 10:49 AM, Johnny Chen wrote:
> 
>> I originally meant NVCVTFrm to cover all NEON vcvt instructions, and the upcoming patch uses
>> NVCVTFrm for "Convert, with fractional bits immediate".
> 
> The "VCVT with immediate" format must be distinct.  The VCVT format you have now is used for the _other_ VCVT instructions (with no immediates).  There is no need for that.  Please revert this patch.
> 
>> 
>> This patch is more complex and involves more new formats.  So I will keep the NVCVTFrm and
>> remove N2V2 so that NVCVTFrm only covers vcvt with fractional bits immediate.
>> 
>> How's that?
> 
> No, we need to resolve the current set of changes before adding more on top.
> 
>> 
>> On Mar 24, 2010, at 10:27 AM, Bob Wilson wrote:
>> 
>>> 
>>> On Mar 23, 2010, at 5:54 PM, Johnny Chen wrote:
>>> 
>>>> I will rename NVdVmImmFrm to the more proper N2RegFrm.
>>> 
>>> OK, thanks.  (It would be helpful to keep this discussion threaded so I can keep track of which patches have been reviewed.  You're replying here to my review of r99326 with a comment that responds to my feedback on r99322.)
>>> 
>>>> N2V2 is still necessary, though, because of N2VS, N2VD, N2VQ, which are for vcvt instructions.
>>> 
>>> The N2V2 class is identical to the existing N2V class except that you've added a Format argument.  Just add the Format argument to N2V and then you don't need to make a new class.
>>> 
>>> I have a further comment about adding a new format for VCVT.  This should not be necessary, since the VCVT instructions that you've changed here have the same basic 2-register encoding format as other instructions like VMVN, VNEG, etc.  If you still think it is needed, please explain.  Otherwise, please revert this patch (r99326).
>>> 
>>>> 
>>>> On Mar 23, 2010, at 2:45 PM, Bob Wilson wrote:
>>>> 
>>>>> 
>>>>> On Mar 23, 2010, at 2:25 PM, Johnny Chen wrote:
>>>>> 
>>>>>> Author: johnny
>>>>>> Date: Tue Mar 23 16:25:38 2010
>>>>>> New Revision: 99326
>>>>>> 
>>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=99326&view=rev
>>>>>> Log:
>>>>>> Add New NEON Format NVdVmVCVTFrm.
>>>>>> Converted some of the NEON vcvt instructions to this format.
>>>>>> 
>>>>>> Modified:
>>>>>> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>>>>> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>>>>> 
>>>>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99326&r1=99325&r2=99326&view=diff
>>>>>> ==============================================================================
>>>>>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>>>>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Mar 23 16:25:38 2010
>>>>>> @@ -62,6 +62,7 @@
>>>>>> def NLdStFrm                : Format<31>;
>>>>>> def NVdImmFrm               : Format<32>;
>>>>>> def NVdVmImmFrm             : Format<33>;
>>>>>> +def NVdVmVCVTFrm            : Format<34>;
>>>>> 
>>>>> How about "NVCVTFrm"?
>>>>> 
>>>>> 
>>>>>> 
>>>>>> // Misc flags.
>>>>>> 
>>>>>> 
>>>>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99326&r1=99325&r2=99326&view=diff
>>>>>> ==============================================================================
>>>>>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>>>>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 23 16:25:38 2010
>>>>>> @@ -853,25 +853,40 @@
>>>>>> // Instruction Classes
>>>>>> //===----------------------------------------------------------------------===//
>>>>>> 
>>>>>> +// Same as N2V except that it doesn't pass a default NVdVmImmFrm to NDataI.
>>>>>> +class N2V2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
>>>>>> +          bits<5> op11_7, bit op6, bit op4,
>>>>>> +          dag oops, dag iops, Format f, InstrItinClass itin,
>>>>>> +          string opc, string dt, string asm, string cstr, list<dag> pattern>
>>>>>> +  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
>>>>>> +  let Inst{24-23} = op24_23;
>>>>>> +  let Inst{21-20} = op21_20;
>>>>>> +  let Inst{19-18} = op19_18;
>>>>>> +  let Inst{17-16} = op17_16;
>>>>>> +  let Inst{11-7} = op11_7;
>>>>>> +  let Inst{6} = op6;
>>>>>> +  let Inst{4} = op4;
>>>>>> +}
>>>>>> +
>>>>> 
>>>>> This should not be necessary.  You should not have added the NVdVmImmFrm for N2V to begin with (per my earlier comments).  Please remove this class.
>>>>> 
>>>>> 
>>>>>> // Basic 2-register operations: single-, double- and quad-register.
>>>>>> class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>>>>       bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>>>>>       string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>>>>>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
>>>>>> -        (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
>>>>>> -        IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
>>>>>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
>>>>>> +         (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NVdVmVCVTFrm,
>>>>>> +         IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
>>>>>> class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>>>>       bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>>>>>       string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>>>>>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
>>>>>> -        (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
>>>>>> -        [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
>>>>>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
>>>>>> +         (ins DPR:$src), NVdVmVCVTFrm, IIC_VUNAD, OpcodeStr, Dt,"$dst, $src","",
>>>>>> +         [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
>>>>>> class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>>>>       bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
>>>>>>       string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
>>>>>> -  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
>>>>>> -        (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
>>>>>> -        [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
>>>>>> +  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
>>>>>> +         (ins QPR:$src), NVdVmVCVTFrm, IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src","",
>>>>>> +         [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
>>>>>> 
>>>>>> // Basic 2-register intrinsics, both double- and quad-register.
>>>>>> class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
>>>>>> 
>>>>>> 
>>>>>> _______________________________________________
>>>>>> llvm-commits mailing list
>>>>>> llvm-commits at cs.uiuc.edu
>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>> 
>>>> 
>>> 
>> 
> 




From daniel at zuster.org  Wed Mar 24 13:35:25 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 24 Mar 2010 11:35:25 -0700
Subject: [llvm-commits] [llvm] r98998 - in /llvm/trunk:
	autoconf/configure.ac configure
In-Reply-To: <20100319213139.60F362A6C12C@llvm.org>
References: <20100319213139.60F362A6C12C@llvm.org>
Message-ID: <6a8523d61003241135g76e355bcgc24b6f77dde1d867@mail.gmail.com>

Hi John,

This change is causing configure to emit
  configure: WARNING: Unknown project (test-suite) won't be configured
automatically

 - Daniel

On Fri, Mar 19, 2010 at 2:31 PM, John Criswell <criswell at uiuc.edu> wrote:
> Author: criswell
> Date: Fri Mar 19 16:31:39 2010
> New Revision: 98998
>
> URL: http://llvm.org/viewvc/llvm-project?rev=98998&view=rev
> Log:
> Force configuration of some projects before others. ?In particular, some
> projects rely upon llvm-gcc, the LLVM test suite, and poolalloc. ?This ensures
> that the aforementioned projects have their object trees created first so that
> other projects can find their object trees when they themselves are configured.
>
> Modified:
> ? ?llvm/trunk/autoconf/configure.ac
> ? ?llvm/trunk/configure
>
> Modified: llvm/trunk/autoconf/configure.ac
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=98998&r1=98997&r2=98998&view=diff
> ==============================================================================
> --- llvm/trunk/autoconf/configure.ac (original)
> +++ llvm/trunk/autoconf/configure.ac Fri Mar 19 16:31:39 2010
> @@ -62,6 +62,41 @@
> ?dnl just AC_CONFIG_SUBDIRS on the set of directories in projects that have a
> ?dnl configure script, that usage of the AC_CONFIG_SUBDIRS macro is deprecated.
> ?dnl Instead we match on the known projects.
> +
> +dnl
> +dnl One tricky part of doing this is that some projects depend upon other
> +dnl projects. ?For example, several projects rely upon the LLVM test suite.
> +dnl We want to configure those projects first so that their object trees are
> +dnl created before running the configure scripts of projects that depend upon
> +dnl them.
> +dnl
> +
> +dnl Several projects use llvm-gcc, so configure that first
> +if test -d ${srcdir}/projects/llvm-gcc ; then
> + ?AC_CONFIG_SUBDIRS([projects/llvm-gcc])
> +fi
> +
> +dnl Several projects use the LLVM test suite, so configure it next.
> +if test -d ${srcdir}/projects/test-suite ; then
> + ?AC_CONFIG_SUBDIRS([projects/test-suite])
> +fi
> +
> +dnl llvm-test is the old name of the test-suite, kept here for backwards
> +dnl compatibility
> +if test -d ${srcdir}/projects/llvm-test ; then
> + ?AC_CONFIG_SUBDIRS([projects/llvm-test])
> +fi
> +
> +dnl Some projects use poolalloc; configure that next
> +if test -d ${srcdir}/projects/poolalloc ; then
> + ?AC_CONFIG_SUBDIRS([projects/poolalloc])
> +fi
> +
> +if test -d ${srcdir}/projects/llvm-poolalloc ; then
> + ?AC_CONFIG_SUBDIRS([projects/llvm-poolalloc])
> +fi
> +
> +dnl Check for all other projects
> ?for i in `ls ${srcdir}/projects`
> ?do
> ? if test -d ${srcdir}/projects/${i} ; then
> @@ -70,16 +105,9 @@
> ? ? ? sample) ? ? ? AC_CONFIG_SUBDIRS([projects/sample]) ? ?;;
> ? ? ? privbracket) ?AC_CONFIG_SUBDIRS([projects/privbracket]) ;;
> ? ? ? llvm-stacker) AC_CONFIG_SUBDIRS([projects/llvm-stacker]) ;;
> - ? ? ?# llvm-test is the old name of the test-suite, kept here for backwards
> - ? ? ?# compatibility
> - ? ? ?llvm-test) ? ?AC_CONFIG_SUBDIRS([projects/llvm-test]) ;;
> - ? ? ?test-suite) ? AC_CONFIG_SUBDIRS([projects/test-suite]) ;;
> ? ? ? llvm-reopt) ? AC_CONFIG_SUBDIRS([projects/llvm-reopt]);;
> - ? ? ?llvm-gcc) ? ? AC_CONFIG_SUBDIRS([projects/llvm-gcc]) ?;;
> ? ? ? llvm-java) ? ?AC_CONFIG_SUBDIRS([projects/llvm-java]) ;;
> ? ? ? llvm-tv) ? ? ?AC_CONFIG_SUBDIRS([projects/llvm-tv]) ? ;;
> - ? ? ?llvm-poolalloc) AC_CONFIG_SUBDIRS([projects/llvm-poolalloc]) ;;
> - ? ? ?poolalloc) ? ?AC_CONFIG_SUBDIRS([projects/poolalloc]) ;;
> ? ? ? safecode) ? ? AC_CONFIG_SUBDIRS([projects/safecode]) ;;
> ? ? ? llvm-kernel) ?AC_CONFIG_SUBDIRS([projects/llvm-kernel]) ;;
> ? ? ? *)
>
> Modified: llvm/trunk/configure
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=98998&r1=98997&r2=98998&view=diff
> ==============================================================================
> --- llvm/trunk/configure (original)
> +++ llvm/trunk/configure Fri Mar 19 16:31:39 2010
> @@ -802,17 +802,17 @@
> ?CXX
> ?CXXFLAGS
> ?CCC'
> -ac_subdirs_all='projects/sample
> +ac_subdirs_all='projects/llvm-gcc
> +projects/test-suite
> +projects/llvm-test
> +projects/poolalloc
> +projects/llvm-poolalloc
> +projects/sample
> ?projects/privbracket
> ?projects/llvm-stacker
> -projects/llvm-test
> -projects/test-suite
> ?projects/llvm-reopt
> -projects/llvm-gcc
> ?projects/llvm-java
> ?projects/llvm-tv
> -projects/llvm-poolalloc
> -projects/poolalloc
> ?projects/safecode
> ?projects/llvm-kernel'
>
> @@ -1951,6 +1951,33 @@
> ? fi
> ?fi
>
> +
> +
> +if test -d ${srcdir}/projects/llvm-gcc ; then
> + ?subdirs="$subdirs projects/llvm-gcc"
> +
> +fi
> +
> +if test -d ${srcdir}/projects/test-suite ; then
> + ?subdirs="$subdirs projects/test-suite"
> +
> +fi
> +
> +if test -d ${srcdir}/projects/llvm-test ; then
> + ?subdirs="$subdirs projects/llvm-test"
> +
> +fi
> +
> +if test -d ${srcdir}/projects/poolalloc ; then
> + ?subdirs="$subdirs projects/poolalloc"
> +
> +fi
> +
> +if test -d ${srcdir}/projects/llvm-poolalloc ; then
> + ?subdirs="$subdirs projects/llvm-poolalloc"
> +
> +fi
> +
> ?for i in `ls ${srcdir}/projects`
> ?do
> ? if test -d ${srcdir}/projects/${i} ; then
> @@ -1962,24 +1989,12 @@
> ?;;
> ? ? ? llvm-stacker) subdirs="$subdirs projects/llvm-stacker"
> ?;;
> - ? ? ?# llvm-test is the old name of the test-suite, kept here for backwards
> - ? ? ?# compatibility
> - ? ? ?llvm-test) ? ?subdirs="$subdirs projects/llvm-test"
> - ;;
> - ? ? ?test-suite) ? subdirs="$subdirs projects/test-suite"
> - ;;
> ? ? ? llvm-reopt) ? subdirs="$subdirs projects/llvm-reopt"
> ?;;
> - ? ? ?llvm-gcc) ? ? subdirs="$subdirs projects/llvm-gcc"
> - ?;;
> ? ? ? llvm-java) ? ?subdirs="$subdirs projects/llvm-java"
> ?;;
> ? ? ? llvm-tv) ? ? ?subdirs="$subdirs projects/llvm-tv"
> ? ?;;
> - ? ? ?llvm-poolalloc) subdirs="$subdirs projects/llvm-poolalloc"
> - ;;
> - ? ? ?poolalloc) ? ?subdirs="$subdirs projects/poolalloc"
> - ;;
> ? ? ? safecode) ? ? subdirs="$subdirs projects/safecode"
> ?;;
> ? ? ? llvm-kernel) ?subdirs="$subdirs projects/llvm-kernel"
> @@ -11136,7 +11151,7 @@
> ? lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
> ? lt_status=$lt_dlunknown
> ? cat > conftest.$ac_ext <<EOF
> -#line 11139 "configure"
> +#line 11154 "configure"
> ?#include "confdefs.h"
>
> ?#if HAVE_DLFCN_H
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



From johnny.chen at apple.com  Wed Mar 24 13:46:34 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Wed, 24 Mar 2010 18:46:34 -0000
Subject: [llvm-commits] [llvm] r99409 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20100324184634.ADED62A6C12C@llvm.org>

Author: johnny
Date: Wed Mar 24 13:46:34 2010
New Revision: 99409

URL: http://llvm.org/viewvc/llvm-project?rev=99409&view=rev
Log:
Reverted r99376.  The disassembler will deal with the 2-reg format of these two
N3VX instructions using special case code.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99409&r1=99408&r2=99409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Mar 24 13:46:34 2010
@@ -2778,13 +2778,10 @@
 
 //   VMOV     : Vector Move (Register)
 
-// Mark these as 2-register instructions to help the disassembler.
-let F = N2RegFrm, Form = N2RegFrm.Value in {
 def  VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
                      IIC_VMOVD, "vmov", "$dst, $src", "", []>;
 def  VMOVQ    : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
                      IIC_VMOVD, "vmov", "$dst, $src", "", []>;
-}
 
 //   VMOV     : Vector Move (Immediate)
 




From dpatel at apple.com  Wed Mar 24 13:48:01 2010
From: dpatel at apple.com (Devang Patel)
Date: Wed, 24 Mar 2010 18:48:01 -0000
Subject: [llvm-commits] [llvm] r99410 - in /llvm/trunk:
 include/llvm/Analysis/DebugInfo.h test/DebugInfo/2010-03-24-MemberFn.ll
Message-ID: <20100324184801.228752A6C12C@llvm.org>

Author: dpatel
Date: Wed Mar 24 13:48:00 2010
New Revision: 99410

URL: http://llvm.org/viewvc/llvm-project?rev=99410&view=rev
Log:
Do not rely on getCompileUnit() to find source file information for a subprogram.

Added:
    llvm/trunk/test/DebugInfo/2010-03-24-MemberFn.ll
Modified:
    llvm/trunk/include/llvm/Analysis/DebugInfo.h

Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=99410&r1=99409&r2=99410&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Wed Mar 24 13:48:00 2010
@@ -395,8 +395,21 @@
     }
     unsigned isArtificial() const    { return getUnsignedField(14); }
 
-    StringRef getFilename() const    { return getCompileUnit().getFilename();}
-    StringRef getDirectory() const   { return getCompileUnit().getDirectory();}
+    StringRef getFilename() const    { 
+      if (getVersion() == llvm::LLVMDebugVersion7)
+        return getCompileUnit().getFilename();
+
+      DIFile F = getFieldAs<DIFile>(6); 
+      return F.getFilename();
+    }
+
+    StringRef getDirectory() const   { 
+      if (getVersion() == llvm::LLVMDebugVersion7)
+        return getCompileUnit().getFilename();
+
+      DIFile F = getFieldAs<DIFile>(6); 
+      return F.getDirectory();
+    }
 
     /// Verify - Verify that a subprogram descriptor is well formed.
     bool Verify() const;

Added: llvm/trunk/test/DebugInfo/2010-03-24-MemberFn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2010-03-24-MemberFn.ll?rev=99410&view=auto
==============================================================================
--- llvm/trunk/test/DebugInfo/2010-03-24-MemberFn.ll (added)
+++ llvm/trunk/test/DebugInfo/2010-03-24-MemberFn.ll Wed Mar 24 13:48:00 2010
@@ -0,0 +1,62 @@
+; RUN: llc -O0 < %s | grep AT_decl_file |  grep 2
+; Here _ZN1S3fooEv is defined in header file identified as AT_decl_file no. 2 in debug info.
+%struct.S = type <{ i8 }>
+
+define i32 @_Z3barv() nounwind ssp {
+entry:
+  %retval = alloca i32                            ; <i32*> [#uses=2]
+  %0 = alloca i32                                 ; <i32*> [#uses=2]
+  %s1 = alloca %struct.S                          ; <%struct.S*> [#uses=1]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  call void @llvm.dbg.declare(metadata !{%struct.S* %s1}, metadata !0), !dbg !16
+  %1 = call i32 @_ZN1S3fooEv(%struct.S* %s1) nounwind, !dbg !17 ; <i32> [#uses=1]
+  store i32 %1, i32* %0, align 4, !dbg !17
+  %2 = load i32* %0, align 4, !dbg !17            ; <i32> [#uses=1]
+  store i32 %2, i32* %retval, align 4, !dbg !17
+  br label %return, !dbg !17
+
+return:                                           ; preds = %entry
+  %retval1 = load i32* %retval, !dbg !17          ; <i32> [#uses=1]
+  ret i32 %retval1, !dbg !16
+}
+
+define linkonce_odr i32 @_ZN1S3fooEv(%struct.S* %this) nounwind ssp align 2 {
+entry:
+  %this_addr = alloca %struct.S*                  ; <%struct.S**> [#uses=1]
+  %retval = alloca i32                            ; <i32*> [#uses=1]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  call void @llvm.dbg.declare(metadata !{%struct.S** %this_addr}, metadata !18), !dbg !21
+  store %struct.S* %this, %struct.S** %this_addr
+  br label %return, !dbg !21
+
+return:                                           ; preds = %entry
+  %retval1 = load i32* %retval, !dbg !21          ; <i32> [#uses=1]
+  ret i32 %retval1, !dbg !22
+}
+
+declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
+
+!0 = metadata !{i32 524544, metadata !1, metadata !"s1", metadata !4, i32 3, metadata !9} ; [ DW_TAG_auto_variable ]
+!1 = metadata !{i32 524299, metadata !2, i32 3, i32 0} ; [ DW_TAG_lexical_block ]
+!2 = metadata !{i32 524299, metadata !3, i32 3, i32 0} ; [ DW_TAG_lexical_block ]
+!3 = metadata !{i32 524334, i32 0, metadata !4, metadata !"bar", metadata !"bar", metadata !"_Z3barv", metadata !4, i32 3, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
+!4 = metadata !{i32 524329, metadata !"one.cc", metadata !"/tmp/", metadata !5} ; [ DW_TAG_file_type ]
+!5 = metadata !{i32 524305, i32 0, i32 4, metadata !"one.cc", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
+!6 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!7 = metadata !{metadata !8}
+!8 = metadata !{i32 524324, metadata !4, metadata !"int", metadata !4, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 524307, metadata !4, metadata !"S", metadata !10, i32 2, i64 8, i64 8, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ]
+!10 = metadata !{i32 524329, metadata !"one.h", metadata !"/tmp/", metadata !5} ; [ DW_TAG_file_type ]
+!11 = metadata !{metadata !12}
+!12 = metadata !{i32 524334, i32 0, metadata !9, metadata !"foo", metadata !"foo", metadata !"_ZN1S3fooEv", metadata !10, i32 3, metadata !13, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
+!13 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !14, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!14 = metadata !{metadata !8, metadata !15}
+!15 = metadata !{i32 524303, metadata !4, metadata !"", metadata !4, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !9} ; [ DW_TAG_pointer_type ]
+!16 = metadata !{i32 3, i32 0, metadata !1, null}
+!17 = metadata !{i32 3, i32 0, metadata !3, null}
+!18 = metadata !{i32 524545, metadata !12, metadata !"this", metadata !10, i32 3, metadata !19} ; [ DW_TAG_arg_variable ]
+!19 = metadata !{i32 524326, metadata !4, metadata !"", metadata !4, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !20} ; [ DW_TAG_const_type ]
+!20 = metadata !{i32 524303, metadata !4, metadata !"", metadata !4, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ]
+!21 = metadata !{i32 3, i32 0, metadata !12, null}
+!22 = metadata !{i32 3, i32 0, metadata !23, null}
+!23 = metadata !{i32 524299, metadata !12, i32 3, i32 0} ; [ DW_TAG_lexical_block ]




From bob.wilson at apple.com  Wed Mar 24 13:59:49 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 24 Mar 2010 18:59:49 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r99412 -
	/llvm-gcc-4.2/trunk/libgomp/Makefile.in
Message-ID: <20100324185949.B07C62A6C12C@llvm.org>

Author: bwilson
Date: Wed Mar 24 13:59:49 2010
New Revision: 99412

URL: http://llvm.org/viewvc/llvm-project?rev=99412&view=rev
Log:
Add comments for race condition fix, now that I'm reasonably confident that I
understand the problem.  I had been assuming that "mv" was implemented with
rename(2) when not crossing file system boundaries.  It used to be so.  On
Darwin, at least, the man page says that it is implemented using "rm" and "cp".
That leaves a brief time when the files in $(DEPDIR) do not exist.

Modified:
    llvm-gcc-4.2/trunk/libgomp/Makefile.in

Modified: llvm-gcc-4.2/trunk/libgomp/Makefile.in
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/libgomp/Makefile.in?rev=99412&r1=99411&r2=99412&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/libgomp/Makefile.in (original)
+++ llvm-gcc-4.2/trunk/libgomp/Makefile.in Wed Mar 24 13:59:49 2010
@@ -457,8 +457,14 @@
 distclean-libtool:
 	-rm -f libtool
 
-# LLVM LOCAL: Try to avoid a mysterious race condition by adding a dependency.
+# LLVM LOCAL begin
+# Avoid a race condition: On systems where "mv" is implemented as "rm+cp",
+# even when not crossing a file system boundary, the files in $(DEPDIR) will
+# be momentarily absent when they are updated.  If the recursive make for
+# multilibs starts up when one of those files is missing, it will fail.
+# Add a dependency to prevent that.
 all-multi: $(LTLIBRARIES)
+# LLVM LOCAL end
 
 # GNU Make needs to see an explicit $(MAKE) variable in the command it
 # runs to enable its job server during parallel builds.  Hence the




From gohman at apple.com  Wed Mar 24 14:00:02 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 24 Mar 2010 19:00:02 -0000
Subject: [llvm-commits] [llvm] r99413 - /llvm/trunk/tools/llvm-ld/llvm-ld.cpp
Message-ID: <20100324190002.2DCDE2A6C12C@llvm.org>

Author: djg
Date: Wed Mar 24 14:00:02 2010
New Revision: 99413

URL: http://llvm.org/viewvc/llvm-project?rev=99413&view=rev
Log:
It's not necessary to call raw_ostream::close explicitly on automatic
raw_ostream variables immediately before they go out of scope.

Modified:
    llvm/trunk/tools/llvm-ld/llvm-ld.cpp

Modified: llvm/trunk/tools/llvm-ld/llvm-ld.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ld/llvm-ld.cpp?rev=99413&r1=99412&r2=99413&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-ld/llvm-ld.cpp (original)
+++ llvm/trunk/tools/llvm-ld/llvm-ld.cpp Wed Mar 24 14:00:02 2010
@@ -243,9 +243,6 @@
 
   // Write it out
   WriteBitcodeToFile(M, Out);
-
-  // Close the bitcode file.
-  Out.close();
 }
 
 /// GenerateAssembly - generates a native assembly language source file from the
@@ -471,7 +468,6 @@
       Out2 << "    -load=" << FullLibraryPath.str() << " \\\n";
   }
   Out2 << "    "  << BitcodeOutputFilename << " ${1+\"$@\"}\n";
-  Out2.close();
 }
 
 // BuildLinkItems -- This function generates a LinkItemList for the LinkItems




From echristo at apple.com  Wed Mar 24 14:01:40 2010
From: echristo at apple.com (Eric Christopher)
Date: Wed, 24 Mar 2010 12:01:40 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r99412 -
	/llvm-gcc-4.2/trunk/libgomp/Makefile.in
In-Reply-To: <20100324185949.B07C62A6C12C@llvm.org>
References: <20100324185949.B07C62A6C12C@llvm.org>
Message-ID: <CD9C828B-CFAE-49B1-9AE2-E180FDD69A0D@apple.com>


On Mar 24, 2010, at 11:59 AM, Bob Wilson wrote:

> Add comments for race condition fix, now that I'm reasonably confident that I
> understand the problem.  I had been assuming that "mv" was implemented with
> rename(2) when not crossing file system boundaries.  It used to be so.  On
> Darwin, at least, the man page says that it is implemented using "rm" and "cp".
> That leaves a brief time when the files in $(DEPDIR) do not exist.

... *boggle*

Thanks Bob!

-eric


From daniel at zuster.org  Wed Mar 24 14:36:30 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 24 Mar 2010 12:36:30 -0700
Subject: [llvm-commits] [llvm] r99336 - in /llvm/trunk: tools/Makefile
	utils/buildit/build_llvm
In-Reply-To: <20100323221533.E7AE42A6C12D@llvm.org>
References: <20100323221533.E7AE42A6C12D@llvm.org>
Message-ID: <6a8523d61003241236r3e73a51dvba4c2307e3b3d41@mail.gmail.com>

Hi Bill,

Why not change to using ONLY_TOOLS to handle this, instead of adding
yet another specialized Makefile variable?

 - Daniel

On Tue, Mar 23, 2010 at 3:15 PM, Bill Wendling <isanbard at gmail.com> wrote:
> Author: void
> Date: Tue Mar 23 17:15:33 2010
> New Revision: 99336
>
> URL: http://llvm.org/viewvc/llvm-project?rev=99336&view=rev
> Log:
> Use "DISABLE_EDIS" to disable building "edis" explicitly. Don't build it for
> Apple-style builds.
>
> Modified:
> ? ?llvm/trunk/tools/Makefile
> ? ?llvm/trunk/utils/buildit/build_llvm
>
> Modified: llvm/trunk/tools/Makefile
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=99336&r1=99335&r2=99336&view=diff
> ==============================================================================
> --- llvm/trunk/tools/Makefile (original)
> +++ llvm/trunk/tools/Makefile Tue Mar 23 17:15:33 2010
> @@ -22,7 +22,6 @@
> ? ? ? ? ? ? ? ? ?lli llvm-extract \
> ? ? ? ? ? ? ? ? ?bugpoint llvm-bcanalyzer llvm-stub \
> ? ? ? ? ? ? ? ? ?llvm-mc llvmc
> -
>
> ?# Let users override the set of tools to build from the command line.
> ?ifdef ONLY_TOOLS
> @@ -38,7 +37,7 @@
> ? # No support for dynamic libraries on windows targets.
> ? ifneq ($(TARGET_OS), $(filter $(TARGET_OS), Cygwin MingW))
> ? ? PARALLEL_DIRS += edis
> -
> +
> ? ? # gold only builds if binutils is around. ?It requires "lto" to build before
> ? ? # it so it is added to DIRS.
> ? ? ifdef BINUTILS_INCDIR
> @@ -54,4 +53,9 @@
> ? PARALLEL_DIRS := $(filter-out edis, $(PARALLEL_DIRS))
> ?endif
>
> +# Don't build edis if we explicitly disabled it.
> +ifneq ($(DISABLE_EDIS),1)
> + ?PARALLEL_DIRS := $(filter-out edis, $(PARALLEL_DIRS))
> +endif
> +
> ?include $(LEVEL)/Makefile.common
>
> Modified: llvm/trunk/utils/buildit/build_llvm
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=99336&r1=99335&r2=99336&view=diff
> ==============================================================================
> --- llvm/trunk/utils/buildit/build_llvm (original)
> +++ llvm/trunk/utils/buildit/build_llvm Tue Mar 23 17:15:33 2010
> @@ -203,6 +203,7 @@
> ?make $JOBS_FLAG $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \
> ? ? UNIVERSAL_SDK_PATH=$HOST_SDKROOT \
> ? ? NO_RUNTIME_LIBS=1 \
> + ? ?DISABLE_EDIS=1 \
> ? ? LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \
> ? ? LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \
> ? ? CXXFLAGS="-DLLVM_VERSION_INFO='\" Apple Build #$LLVM_VERSION\"'" \
> @@ -227,6 +228,7 @@
> ?# Install the tree into the destination directory.
> ?make $LOCAL_MAKEFLAGS $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \
> ? ? NO_RUNTIME_LIBS=1 \
> + ? ?DISABLE_EDIS=1 \
> ? ? LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \
> ? ? LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \
> ? ? OPTIMIZE_OPTION='-O3' VERBOSE=1 install
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



From daniel at zuster.org  Wed Mar 24 14:37:02 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 24 Mar 2010 12:37:02 -0700
Subject: [llvm-commits] [llvm] r99336 - in /llvm/trunk: tools/Makefile
	utils/buildit/build_llvm
In-Reply-To: <6a8523d61003241236r3e73a51dvba4c2307e3b3d41@mail.gmail.com>
References: <20100323221533.E7AE42A6C12D@llvm.org>
	<6a8523d61003241236r3e73a51dvba4c2307e3b3d41@mail.gmail.com>
Message-ID: <6a8523d61003241237n470b4fdcs6145dba3168aa63c@mail.gmail.com>

Note that ONLY_TOOLS is currently broken with edis, but I'm about to fix that.

 - Daniel

On Wed, Mar 24, 2010 at 12:36 PM, Daniel Dunbar <daniel at zuster.org> wrote:
> Hi Bill,
>
> Why not change to using ONLY_TOOLS to handle this, instead of adding
> yet another specialized Makefile variable?
>
> ?- Daniel
>
> On Tue, Mar 23, 2010 at 3:15 PM, Bill Wendling <isanbard at gmail.com> wrote:
>> Author: void
>> Date: Tue Mar 23 17:15:33 2010
>> New Revision: 99336
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=99336&view=rev
>> Log:
>> Use "DISABLE_EDIS" to disable building "edis" explicitly. Don't build it for
>> Apple-style builds.
>>
>> Modified:
>> ? ?llvm/trunk/tools/Makefile
>> ? ?llvm/trunk/utils/buildit/build_llvm
>>
>> Modified: llvm/trunk/tools/Makefile
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=99336&r1=99335&r2=99336&view=diff
>> ==============================================================================
>> --- llvm/trunk/tools/Makefile (original)
>> +++ llvm/trunk/tools/Makefile Tue Mar 23 17:15:33 2010
>> @@ -22,7 +22,6 @@
>> ? ? ? ? ? ? ? ? ?lli llvm-extract \
>> ? ? ? ? ? ? ? ? ?bugpoint llvm-bcanalyzer llvm-stub \
>> ? ? ? ? ? ? ? ? ?llvm-mc llvmc
>> -
>>
>> ?# Let users override the set of tools to build from the command line.
>> ?ifdef ONLY_TOOLS
>> @@ -38,7 +37,7 @@
>> ? # No support for dynamic libraries on windows targets.
>> ? ifneq ($(TARGET_OS), $(filter $(TARGET_OS), Cygwin MingW))
>> ? ? PARALLEL_DIRS += edis
>> -
>> +
>> ? ? # gold only builds if binutils is around. ?It requires "lto" to build before
>> ? ? # it so it is added to DIRS.
>> ? ? ifdef BINUTILS_INCDIR
>> @@ -54,4 +53,9 @@
>> ? PARALLEL_DIRS := $(filter-out edis, $(PARALLEL_DIRS))
>> ?endif
>>
>> +# Don't build edis if we explicitly disabled it.
>> +ifneq ($(DISABLE_EDIS),1)
>> + ?PARALLEL_DIRS := $(filter-out edis, $(PARALLEL_DIRS))
>> +endif
>> +
>> ?include $(LEVEL)/Makefile.common
>>
>> Modified: llvm/trunk/utils/buildit/build_llvm
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=99336&r1=99335&r2=99336&view=diff
>> ==============================================================================
>> --- llvm/trunk/utils/buildit/build_llvm (original)
>> +++ llvm/trunk/utils/buildit/build_llvm Tue Mar 23 17:15:33 2010
>> @@ -203,6 +203,7 @@
>> ?make $JOBS_FLAG $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \
>> ? ? UNIVERSAL_SDK_PATH=$HOST_SDKROOT \
>> ? ? NO_RUNTIME_LIBS=1 \
>> + ? ?DISABLE_EDIS=1 \
>> ? ? LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \
>> ? ? LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \
>> ? ? CXXFLAGS="-DLLVM_VERSION_INFO='\" Apple Build #$LLVM_VERSION\"'" \
>> @@ -227,6 +228,7 @@
>> ?# Install the tree into the destination directory.
>> ?make $LOCAL_MAKEFLAGS $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \
>> ? ? NO_RUNTIME_LIBS=1 \
>> + ? ?DISABLE_EDIS=1 \
>> ? ? LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \
>> ? ? LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \
>> ? ? OPTIMIZE_OPTION='-O3' VERBOSE=1 install
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>



From gohman at apple.com  Wed Mar 24 14:38:03 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 24 Mar 2010 19:38:03 -0000
Subject: [llvm-commits] [llvm] r99414 - in /llvm/trunk/lib/Support:
 APFloat.cpp APInt.cpp CommandLine.cpp Debug.cpp ErrorHandling.cpp
 raw_ostream.cpp
Message-ID: <20100324193803.316D92A6C12C@llvm.org>

Author: djg
Date: Wed Mar 24 14:38:02 2010
New Revision: 99414

URL: http://llvm.org/viewvc/llvm-project?rev=99414&view=rev
Log:
Fix minor style issues.

Modified:
    llvm/trunk/lib/Support/APFloat.cpp
    llvm/trunk/lib/Support/APInt.cpp
    llvm/trunk/lib/Support/CommandLine.cpp
    llvm/trunk/lib/Support/Debug.cpp
    llvm/trunk/lib/Support/ErrorHandling.cpp
    llvm/trunk/lib/Support/raw_ostream.cpp

Modified: llvm/trunk/lib/Support/APFloat.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/APFloat.cpp?rev=99414&r1=99413&r2=99414&view=diff
==============================================================================
--- llvm/trunk/lib/Support/APFloat.cpp (original)
+++ llvm/trunk/lib/Support/APFloat.cpp Wed Mar 24 14:38:02 2010
@@ -65,7 +65,7 @@
      pow(5, power) is
 
        power * 815 / (351 * integerPartWidth) + 1
-       
+
      However, whilst the result may require only this many parts,
      because we are multiplying two values to get it, the
      multiplication may require an extra part with the excess part
@@ -100,15 +100,15 @@
   unsigned int r;
 
   r = c - '0';
-  if(r <= 9)
+  if (r <= 9)
     return r;
 
   r = c - 'A';
-  if(r <= 5)
+  if (r <= 5)
     return r + 10;
 
   r = c - 'a';
-  if(r <= 5)
+  if (r <= 5)
     return r + 10;
 
   return -1U;
@@ -116,8 +116,8 @@
 
 static inline void
 assertArithmeticOK(const llvm::fltSemantics &semantics) {
-  assert(semantics.arithmeticOK
-         && "Compile-time arithmetic does not support these semantics");
+  assert(semantics.arithmeticOK &&
+         "Compile-time arithmetic does not support these semantics");
 }
 
 /* Return the value of a decimal exponent of the form
@@ -179,37 +179,37 @@
   assert(p != end && "Exponent has no digits");
 
   negative = *p == '-';
-  if(*p == '-' || *p == '+') {
+  if (*p == '-' || *p == '+') {
     p++;
     assert(p != end && "Exponent has no digits");
   }
 
   unsignedExponent = 0;
   overflow = false;
-  for(; p != end; ++p) {
+  for (; p != end; ++p) {
     unsigned int value;
 
     value = decDigitValue(*p);
     assert(value < 10U && "Invalid character in exponent");
 
     unsignedExponent = unsignedExponent * 10 + value;
-    if(unsignedExponent > 65535)
+    if (unsignedExponent > 65535)
       overflow = true;
   }
 
-  if(exponentAdjustment > 65535 || exponentAdjustment < -65536)
+  if (exponentAdjustment > 65535 || exponentAdjustment < -65536)
     overflow = true;
 
-  if(!overflow) {
+  if (!overflow) {
     exponent = unsignedExponent;
-    if(negative)
+    if (negative)
       exponent = -exponent;
     exponent += exponentAdjustment;
-    if(exponent > 65535 || exponent < -65536)
+    if (exponent > 65535 || exponent < -65536)
       overflow = true;
   }
 
-  if(overflow)
+  if (overflow)
     exponent = negative ? -65536: 65535;
 
   return exponent;
@@ -221,15 +221,15 @@
 {
   StringRef::iterator p = begin;
   *dot = end;
-  while(*p == '0' && p != end)
+  while (*p == '0' && p != end)
     p++;
 
-  if(*p == '.') {
+  if (*p == '.') {
     *dot = p++;
 
     assert(end - begin != 1 && "Significand has no digits");
 
-    while(*p == '0' && p != end)
+    while (*p == '0' && p != end)
       p++;
   }
 
@@ -323,13 +323,13 @@
 
   /* If the first trailing digit isn't 0 or 8 we can work out the
      fraction immediately.  */
-  if(digitValue > 8)
+  if (digitValue > 8)
     return lfMoreThanHalf;
-  else if(digitValue < 8 && digitValue > 0)
+  else if (digitValue < 8 && digitValue > 0)
     return lfLessThanHalf;
 
   /* Otherwise we need to find the first non-zero digit.  */
-  while(*p == '0')
+  while (*p == '0')
     p++;
 
   assert(p != end && "Invalid trailing hexadecimal fraction!");
@@ -338,7 +338,7 @@
 
   /* If we ran off the end it is exactly zero or one-half, otherwise
      a little more.  */
-  if(hexDigit == -1U)
+  if (hexDigit == -1U)
     return digitValue == 0 ? lfExactlyZero: lfExactlyHalf;
   else
     return digitValue == 0 ? lfLessThanHalf: lfMoreThanHalf;
@@ -356,12 +356,12 @@
   lsb = APInt::tcLSB(parts, partCount);
 
   /* Note this is guaranteed true if bits == 0, or LSB == -1U.  */
-  if(bits <= lsb)
+  if (bits <= lsb)
     return lfExactlyZero;
-  if(bits == lsb + 1)
+  if (bits == lsb + 1)
     return lfExactlyHalf;
-  if(bits <= partCount * integerPartWidth
-     && APInt::tcExtractBit(parts, bits - 1))
+  if (bits <= partCount * integerPartWidth &&
+      APInt::tcExtractBit(parts, bits - 1))
     return lfMoreThanHalf;
 
   return lfLessThanHalf;
@@ -385,10 +385,10 @@
 combineLostFractions(lostFraction moreSignificant,
                      lostFraction lessSignificant)
 {
-  if(lessSignificant != lfExactlyZero) {
-    if(moreSignificant == lfExactlyZero)
+  if (lessSignificant != lfExactlyZero) {
+    if (moreSignificant == lfExactlyZero)
       moreSignificant = lfLessThanHalf;
-    else if(moreSignificant == lfExactlyHalf)
+    else if (moreSignificant == lfExactlyHalf)
       moreSignificant = lfMoreThanHalf;
   }
 
@@ -468,7 +468,7 @@
                                                   15625, 78125 };
   integerPart pow5s[maxPowerOfFiveParts * 2 + 5];
   pow5s[0] = 78125 * 5;
-  
+
   unsigned int partsCount[16] = { 1 };
   integerPart scratch[maxPowerOfFiveParts], *p1, *p2, *pow5;
   unsigned int result;
@@ -588,14 +588,14 @@
 
   semantics = ourSemantics;
   count = partCount();
-  if(count > 1)
+  if (count > 1)
     significand.parts = new integerPart[count];
 }
 
 void
 APFloat::freeSignificand()
 {
-  if(partCount() > 1)
+  if (partCount() > 1)
     delete [] significand.parts;
 }
 
@@ -609,7 +609,7 @@
   exponent = rhs.exponent;
   sign2 = rhs.sign2;
   exponent2 = rhs.exponent2;
-  if(category == fcNormal || category == fcNaN)
+  if (category == fcNormal || category == fcNaN)
     copySignificand(rhs);
 }
 
@@ -683,8 +683,8 @@
 APFloat &
 APFloat::operator=(const APFloat &rhs)
 {
-  if(this != &rhs) {
-    if(semantics != rhs.semantics) {
+  if (this != &rhs) {
+    if (semantics != rhs.semantics) {
       freeSignificand();
       initialize(rhs.semantics);
     }
@@ -881,7 +881,7 @@
   precision = semantics->precision;
   newPartsCount = partCountForBits(precision * 2);
 
-  if(newPartsCount > 4)
+  if (newPartsCount > 4)
     fullSignificand = new integerPart[newPartsCount];
   else
     fullSignificand = scratch;
@@ -896,7 +896,7 @@
   omsb = APInt::tcMSB(fullSignificand, newPartsCount) + 1;
   exponent += rhs.exponent;
 
-  if(addend) {
+  if (addend) {
     Significand savedSignificand = significand;
     const fltSemantics *savedSemantics = semantics;
     fltSemantics extendedSemantics;
@@ -905,18 +905,17 @@
 
     /* Normalize our MSB.  */
     extendedPrecision = precision + precision - 1;
-    if(omsb != extendedPrecision)
-      {
-        APInt::tcShiftLeft(fullSignificand, newPartsCount,
-                           extendedPrecision - omsb);
-        exponent -= extendedPrecision - omsb;
-      }
+    if (omsb != extendedPrecision) {
+      APInt::tcShiftLeft(fullSignificand, newPartsCount,
+                         extendedPrecision - omsb);
+      exponent -= extendedPrecision - omsb;
+    }
 
     /* Create new semantics.  */
     extendedSemantics = *semantics;
     extendedSemantics.precision = extendedPrecision;
 
-    if(newPartsCount == 1)
+    if (newPartsCount == 1)
       significand.part = fullSignificand[0];
     else
       significand.parts = fullSignificand;
@@ -928,7 +927,7 @@
     lost_fraction = addOrSubtractSignificand(extendedAddend, false);
 
     /* Restore our state.  */
-    if(newPartsCount == 1)
+    if (newPartsCount == 1)
       fullSignificand[0] = significand.part;
     significand = savedSignificand;
     semantics = savedSemantics;
@@ -938,7 +937,7 @@
 
   exponent -= (precision - 1);
 
-  if(omsb > precision) {
+  if (omsb > precision) {
     unsigned int bits, significantParts;
     lostFraction lf;
 
@@ -951,7 +950,7 @@
 
   APInt::tcAssign(lhsSignificand, fullSignificand, partsCount);
 
-  if(newPartsCount > 4)
+  if (newPartsCount > 4)
     delete [] fullSignificand;
 
   return lost_fraction;
@@ -973,7 +972,7 @@
   rhsSignificand = rhs.significandParts();
   partsCount = partCount();
 
-  if(partsCount > 2)
+  if (partsCount > 2)
     dividend = new integerPart[partsCount * 2];
   else
     dividend = scratch;
@@ -981,7 +980,7 @@
   divisor = dividend + partsCount;
 
   /* Copy the dividend and divisor as they will be modified in-place.  */
-  for(i = 0; i < partsCount; i++) {
+  for (i = 0; i < partsCount; i++) {
     dividend[i] = lhsSignificand[i];
     divisor[i] = rhsSignificand[i];
     lhsSignificand[i] = 0;
@@ -993,14 +992,14 @@
 
   /* Normalize the divisor.  */
   bit = precision - APInt::tcMSB(divisor, partsCount) - 1;
-  if(bit) {
+  if (bit) {
     exponent += bit;
     APInt::tcShiftLeft(divisor, partsCount, bit);
   }
 
   /* Normalize the dividend.  */
   bit = precision - APInt::tcMSB(dividend, partsCount) - 1;
-  if(bit) {
+  if (bit) {
     exponent -= bit;
     APInt::tcShiftLeft(dividend, partsCount, bit);
   }
@@ -1008,15 +1007,15 @@
   /* Ensure the dividend >= divisor initially for the loop below.
      Incidentally, this means that the division loop below is
      guaranteed to set the integer bit to one.  */
-  if(APInt::tcCompare(dividend, divisor, partsCount) < 0) {
+  if (APInt::tcCompare(dividend, divisor, partsCount) < 0) {
     exponent--;
     APInt::tcShiftLeft(dividend, partsCount, 1);
     assert(APInt::tcCompare(dividend, divisor, partsCount) >= 0);
   }
 
   /* Long division.  */
-  for(bit = precision; bit; bit -= 1) {
-    if(APInt::tcCompare(dividend, divisor, partsCount) >= 0) {
+  for (bit = precision; bit; bit -= 1) {
+    if (APInt::tcCompare(dividend, divisor, partsCount) >= 0) {
       APInt::tcSubtract(dividend, divisor, 0, partsCount);
       APInt::tcSetBit(lhsSignificand, bit - 1);
     }
@@ -1027,16 +1026,16 @@
   /* Figure out the lost fraction.  */
   int cmp = APInt::tcCompare(dividend, divisor, partsCount);
 
-  if(cmp > 0)
+  if (cmp > 0)
     lost_fraction = lfMoreThanHalf;
-  else if(cmp == 0)
+  else if (cmp == 0)
     lost_fraction = lfExactlyHalf;
-  else if(APInt::tcIsZero(dividend, partsCount))
+  else if (APInt::tcIsZero(dividend, partsCount))
     lost_fraction = lfExactlyZero;
   else
     lost_fraction = lfLessThanHalf;
 
-  if(partsCount > 2)
+  if (partsCount > 2)
     delete [] dividend;
 
   return lost_fraction;
@@ -1072,7 +1071,7 @@
 {
   assert(bits < semantics->precision);
 
-  if(bits) {
+  if (bits) {
     unsigned int partsCount = partCount();
 
     APInt::tcShiftLeft(significandParts(), partsCount, bits);
@@ -1095,13 +1094,13 @@
 
   /* If exponents are equal, do an unsigned bignum comparison of the
      significands.  */
-  if(compare == 0)
+  if (compare == 0)
     compare = APInt::tcCompare(significandParts(), rhs.significandParts(),
                                partCount());
 
-  if(compare > 0)
+  if (compare > 0)
     return cmpGreaterThan;
-  else if(compare < 0)
+  else if (compare < 0)
     return cmpLessThan;
   else
     return cmpEqual;
@@ -1113,14 +1112,13 @@
 APFloat::handleOverflow(roundingMode rounding_mode)
 {
   /* Infinity?  */
-  if(rounding_mode == rmNearestTiesToEven
-     || rounding_mode == rmNearestTiesToAway
-     || (rounding_mode == rmTowardPositive && !sign)
-     || (rounding_mode == rmTowardNegative && sign))
-    {
-      category = fcInfinity;
-      return (opStatus) (opOverflow | opInexact);
-    }
+  if (rounding_mode == rmNearestTiesToEven ||
+      rounding_mode == rmNearestTiesToAway ||
+      (rounding_mode == rmTowardPositive && !sign) ||
+      (rounding_mode == rmTowardNegative && sign)) {
+    category = fcInfinity;
+    return (opStatus) (opOverflow | opInexact);
+  }
 
   /* Otherwise we become the largest finite number.  */
   category = fcNormal;
@@ -1155,11 +1153,11 @@
     return lost_fraction == lfExactlyHalf || lost_fraction == lfMoreThanHalf;
 
   case rmNearestTiesToEven:
-    if(lost_fraction == lfMoreThanHalf)
+    if (lost_fraction == lfMoreThanHalf)
       return true;
 
     /* Our zeroes don't have a significand to test.  */
-    if(lost_fraction == lfExactlyHalf && category != fcZero)
+    if (lost_fraction == lfExactlyHalf && category != fcZero)
       return APInt::tcExtractBit(significandParts(), bit);
 
     return false;
@@ -1182,13 +1180,13 @@
   unsigned int omsb;                /* One, not zero, based MSB.  */
   int exponentChange;
 
-  if(category != fcNormal)
+  if (category != fcNormal)
     return opOK;
 
   /* Before rounding normalize the exponent of fcNormal numbers.  */
   omsb = significandMSB() + 1;
 
-  if(omsb) {
+  if (omsb) {
     /* OMSB is numbered from 1.  We want to place it in the integer
        bit numbered PRECISON if possible, with a compensating change in
        the exponent.  */
@@ -1196,16 +1194,16 @@
 
     /* If the resulting exponent is too high, overflow according to
        the rounding mode.  */
-    if(exponent + exponentChange > semantics->maxExponent)
+    if (exponent + exponentChange > semantics->maxExponent)
       return handleOverflow(rounding_mode);
 
     /* Subnormal numbers have exponent minExponent, and their MSB
        is forced based on that.  */
-    if(exponent + exponentChange < semantics->minExponent)
+    if (exponent + exponentChange < semantics->minExponent)
       exponentChange = semantics->minExponent - exponent;
 
     /* Shifting left is easy as we don't lose precision.  */
-    if(exponentChange < 0) {
+    if (exponentChange < 0) {
       assert(lost_fraction == lfExactlyZero);
 
       shiftSignificandLeft(-exponentChange);
@@ -1213,7 +1211,7 @@
       return opOK;
     }
 
-    if(exponentChange > 0) {
+    if (exponentChange > 0) {
       lostFraction lf;
 
       /* Shift right and capture any new lost fraction.  */
@@ -1222,7 +1220,7 @@
       lost_fraction = combineLostFractions(lf, lost_fraction);
 
       /* Keep OMSB up-to-date.  */
-      if(omsb > (unsigned) exponentChange)
+      if (omsb > (unsigned) exponentChange)
         omsb -= exponentChange;
       else
         omsb = 0;
@@ -1234,28 +1232,28 @@
 
   /* As specified in IEEE 754, since we do not trap we do not report
      underflow for exact results.  */
-  if(lost_fraction == lfExactlyZero) {
+  if (lost_fraction == lfExactlyZero) {
     /* Canonicalize zeroes.  */
-    if(omsb == 0)
+    if (omsb == 0)
       category = fcZero;
 
     return opOK;
   }
 
   /* Increment the significand if we're rounding away from zero.  */
-  if(roundAwayFromZero(rounding_mode, lost_fraction, 0)) {
-    if(omsb == 0)
+  if (roundAwayFromZero(rounding_mode, lost_fraction, 0)) {
+    if (omsb == 0)
       exponent = semantics->minExponent;
 
     incrementSignificand();
     omsb = significandMSB() + 1;
 
     /* Did the significand increment overflow?  */
-    if(omsb == (unsigned) semantics->precision + 1) {
+    if (omsb == (unsigned) semantics->precision + 1) {
       /* Renormalize by incrementing the exponent and shifting our
          significand right one.  However if we already have the
          maximum exponent we overflow to infinity.  */
-      if(exponent == semantics->maxExponent) {
+      if (exponent == semantics->maxExponent) {
         category = fcInfinity;
 
         return (opStatus) (opOverflow | opInexact);
@@ -1269,14 +1267,14 @@
 
   /* The normal case - we were and are not denormal, and any
      significand increment above didn't overflow.  */
-  if(omsb == semantics->precision)
+  if (omsb == semantics->precision)
     return opInexact;
 
   /* We have a non-zero denormal.  */
   assert(omsb < semantics->precision);
 
   /* Canonicalize zeroes.  */
-  if(omsb == 0)
+  if (omsb == 0)
     category = fcZero;
 
   /* The fcZero case is a denormal that underflowed to zero.  */
@@ -1324,7 +1322,7 @@
   case convolve(fcInfinity, fcInfinity):
     /* Differently signed infinities can only be validly
        subtracted.  */
-    if(((sign ^ rhs.sign)!=0) != subtract) {
+    if (((sign ^ rhs.sign)!=0) != subtract) {
       makeNaN();
       return opInvalidOp;
     }
@@ -1352,7 +1350,7 @@
   bits = exponent - rhs.exponent;
 
   /* Subtraction is more subtle than one might naively expect.  */
-  if(subtract) {
+  if (subtract) {
     APFloat temp_rhs(rhs);
     bool reverse;
 
@@ -1381,16 +1379,16 @@
 
     /* Invert the lost fraction - it was on the RHS and
        subtracted.  */
-    if(lost_fraction == lfLessThanHalf)
+    if (lost_fraction == lfLessThanHalf)
       lost_fraction = lfMoreThanHalf;
-    else if(lost_fraction == lfMoreThanHalf)
+    else if (lost_fraction == lfMoreThanHalf)
       lost_fraction = lfLessThanHalf;
 
     /* The code above is intended to ensure that no borrow is
        necessary.  */
     assert(!carry);
   } else {
-    if(bits > 0) {
+    if (bits > 0) {
       APFloat temp_rhs(rhs);
 
       lost_fraction = temp_rhs.shiftSignificandRight(bits);
@@ -1561,7 +1559,7 @@
   fs = addOrSubtractSpecials(rhs, subtract);
 
   /* This return code means it was not a simple case.  */
-  if(fs == opDivByZero) {
+  if (fs == opDivByZero) {
     lostFraction lost_fraction;
 
     lost_fraction = addOrSubtractSignificand(rhs, subtract);
@@ -1574,8 +1572,8 @@
   /* If two numbers add (exactly) to zero, IEEE 754 decrees it is a
      positive zero unless rounding to minus infinity, except that
      adding two like-signed zeroes gives that zero.  */
-  if(category == fcZero) {
-    if(rhs.category != fcZero || (sign == rhs.sign) == subtract)
+  if (category == fcZero) {
+    if (rhs.category != fcZero || (sign == rhs.sign) == subtract)
       sign = (rounding_mode == rmTowardNegative);
   }
 
@@ -1606,10 +1604,10 @@
   sign ^= rhs.sign;
   fs = multiplySpecials(rhs);
 
-  if(category == fcNormal) {
+  if (category == fcNormal) {
     lostFraction lost_fraction = multiplySignificand(rhs, 0);
     fs = normalize(rounding_mode, lost_fraction);
-    if(lost_fraction != lfExactlyZero)
+    if (lost_fraction != lfExactlyZero)
       fs = (opStatus) (fs | opInexact);
   }
 
@@ -1626,10 +1624,10 @@
   sign ^= rhs.sign;
   fs = divideSpecials(rhs);
 
-  if(category == fcNormal) {
+  if (category == fcNormal) {
     lostFraction lost_fraction = divideSignificand(rhs);
     fs = normalize(rounding_mode, lost_fraction);
-    if(lost_fraction != lfExactlyZero)
+    if (lost_fraction != lfExactlyZero)
       fs = (opStatus) (fs | opInexact);
   }
 
@@ -1673,7 +1671,7 @@
   return fs;
 }
 
-/* Normalized llvm frem (C fmod).  
+/* Normalized llvm frem (C fmod).
    This is not currently correct in all cases.  */
 APFloat::opStatus
 APFloat::mod(const APFloat &rhs, roundingMode rounding_mode)
@@ -1730,20 +1728,20 @@
 
   /* If and only if all arguments are normal do we need to do an
      extended-precision calculation.  */
-  if(category == fcNormal
-     && multiplicand.category == fcNormal
-     && addend.category == fcNormal) {
+  if (category == fcNormal &&
+      multiplicand.category == fcNormal &&
+      addend.category == fcNormal) {
     lostFraction lost_fraction;
 
     lost_fraction = multiplySignificand(multiplicand, &addend);
     fs = normalize(rounding_mode, lost_fraction);
-    if(lost_fraction != lfExactlyZero)
+    if (lost_fraction != lfExactlyZero)
       fs = (opStatus) (fs | opInexact);
 
     /* If two numbers add (exactly) to zero, IEEE 754 decrees it is a
        positive zero unless rounding to minus infinity, except that
        adding two like-signed zeroes gives that zero.  */
-    if(category == fcZero && sign != addend.sign)
+    if (category == fcZero && sign != addend.sign)
       sign = (rounding_mode == rmTowardNegative);
   } else {
     fs = multiplySpecials(multiplicand);
@@ -1755,7 +1753,7 @@
 
        If we need to do the addition we can do so with normal
        precision.  */
-    if(fs == opOK)
+    if (fs == opOK)
       fs = addOrSubtract(addend, rounding_mode, false);
   }
 
@@ -1787,7 +1785,7 @@
   case convolve(fcInfinity, fcNormal):
   case convolve(fcInfinity, fcZero):
   case convolve(fcNormal, fcZero):
-    if(sign)
+    if (sign)
       return cmpLessThan;
     else
       return cmpGreaterThan;
@@ -1795,15 +1793,15 @@
   case convolve(fcNormal, fcInfinity):
   case convolve(fcZero, fcInfinity):
   case convolve(fcZero, fcNormal):
-    if(rhs.sign)
+    if (rhs.sign)
       return cmpGreaterThan;
     else
       return cmpLessThan;
 
   case convolve(fcInfinity, fcInfinity):
-    if(sign == rhs.sign)
+    if (sign == rhs.sign)
       return cmpEqual;
-    else if(sign)
+    else if (sign)
       return cmpLessThan;
     else
       return cmpGreaterThan;
@@ -1816,8 +1814,8 @@
   }
 
   /* Two normal numbers.  Do they have the same sign?  */
-  if(sign != rhs.sign) {
-    if(sign)
+  if (sign != rhs.sign) {
+    if (sign)
       result = cmpLessThan;
     else
       result = cmpGreaterThan;
@@ -1825,10 +1823,10 @@
     /* Compare absolute values; invert result if negative.  */
     result = compareAbsoluteValue(rhs);
 
-    if(sign) {
-      if(result == cmpLessThan)
+    if (sign) {
+      if (result == cmpLessThan)
         result = cmpGreaterThan;
-      else if(result == cmpGreaterThan)
+      else if (result == cmpGreaterThan)
         result = cmpLessThan;
     }
   }
@@ -1886,7 +1884,7 @@
     }
   }
 
-  if(category == fcNormal) {
+  if (category == fcNormal) {
     /* Re-interpret our bit-pattern.  */
     exponent += toSemantics.precision - semantics->precision;
     semantics = &toSemantics;
@@ -1911,7 +1909,7 @@
       // x87 long double).
       if (APInt::tcLSB(significandParts(), newPartCount) < ushift)
         *losesInfo = true;
-      if (oldSemantics == &APFloat::x87DoubleExtended && 
+      if (oldSemantics == &APFloat::x87DoubleExtended &&
           (!(*significandParts() & 0x8000000000000000ULL) ||
            !(*significandParts() & 0x4000000000000000ULL)))
         *losesInfo = true;
@@ -1956,12 +1954,12 @@
   *isExact = false;
 
   /* Handle the three special cases first.  */
-  if(category == fcInfinity || category == fcNaN)
+  if (category == fcInfinity || category == fcNaN)
     return opInvalidOp;
 
   dstPartsCount = partCountForBits(width);
 
-  if(category == fcZero) {
+  if (category == fcZero) {
     APInt::tcSet(parts, 0, dstPartsCount);
     // Negative zero can't be represented as an int.
     *isExact = !sign;
@@ -2004,8 +2002,8 @@
   if (truncatedBits) {
     lost_fraction = lostFractionThroughTruncation(src, partCount(),
                                                   truncatedBits);
-    if (lost_fraction != lfExactlyZero
-        && roundAwayFromZero(rounding_mode, lost_fraction, truncatedBits)) {
+    if (lost_fraction != lfExactlyZero &&
+        roundAwayFromZero(rounding_mode, lost_fraction, truncatedBits)) {
       if (APInt::tcIncrement(parts, dstPartsCount))
         return opInvalidOp;     /* Overflow.  */
     }
@@ -2062,7 +2060,7 @@
 {
   opStatus fs;
 
-  fs = convertToSignExtendedInteger(parts, width, isSigned, rounding_mode, 
+  fs = convertToSignExtendedInteger(parts, width, isSigned, rounding_mode,
                                     isExact);
 
   if (fs == opInvalidOp) {
@@ -2149,8 +2147,8 @@
   opStatus status;
 
   assertArithmeticOK(*semantics);
-  if (isSigned
-      && APInt::tcExtractBit(src, srcCount * integerPartWidth - 1)) {
+  if (isSigned &&
+      APInt::tcExtractBit(src, srcCount * integerPartWidth - 1)) {
     integerPart *copy;
 
     /* If we're signed and negative negate a copy.  */
@@ -2178,7 +2176,7 @@
   APInt api = APInt(width, partCount, parts);
 
   sign = false;
-  if(isSigned && APInt::tcExtractBit(parts, width - 1)) {
+  if (isSigned && APInt::tcExtractBit(parts, width - 1)) {
     sign = true;
     api = -api;
   }
@@ -2209,10 +2207,10 @@
   StringRef::iterator p = skipLeadingZeroesAndAnyDot(begin, end, &dot);
   firstSignificantDigit = p;
 
-  for(; p != end;) {
+  for (; p != end;) {
     integerPart hex_value;
 
-    if(*p == '.') {
+    if (*p == '.') {
       assert(dot == end && "String contains multiple dots");
       dot = p++;
       if (p == end) {
@@ -2221,7 +2219,7 @@
     }
 
     hex_value = hexDigitValue(*p);
-    if(hex_value == -1U) {
+    if (hex_value == -1U) {
       break;
     }
 
@@ -2231,13 +2229,13 @@
       break;
     } else {
       /* Store the number whilst 4-bit nibbles remain.  */
-      if(bitPos) {
+      if (bitPos) {
         bitPos -= 4;
         hex_value <<= bitPos % integerPartWidth;
         significand[bitPos / integerPartWidth] |= hex_value;
       } else {
         lost_fraction = trailingHexadecimalFraction(p, end, hex_value);
-        while(p != end && hexDigitValue(*p) != -1U)
+        while (p != end && hexDigitValue(*p) != -1U)
           p++;
         break;
       }
@@ -2251,7 +2249,7 @@
   assert((dot == end || p - begin != 1) && "Significand has no digits");
 
   /* Ignore the exponent if we are zero.  */
-  if(p != firstSignificantDigit) {
+  if (p != firstSignificantDigit) {
     int expAdjustment;
 
     /* Implicit hexadecimal point?  */
@@ -2261,7 +2259,7 @@
     /* Calculate the exponent adjustment implicit in the number of
        significant digits.  */
     expAdjustment = static_cast<int>(dot - firstSignificantDigit);
-    if(expAdjustment < 0)
+    if (expAdjustment < 0)
       expAdjustment++;
     expAdjustment = expAdjustment * 4 - 1;
 
@@ -2287,8 +2285,8 @@
   integerPart pow5Parts[maxPowerOfFiveParts];
   bool isNearest;
 
-  isNearest = (rounding_mode == rmNearestTiesToEven
-               || rounding_mode == rmNearestTiesToAway);
+  isNearest = (rounding_mode == rmNearestTiesToEven ||
+               rounding_mode == rmNearestTiesToAway);
 
   parts = partCountForBits(semantics->precision + 11);
 
@@ -2482,13 +2480,13 @@
   StringRef::iterator p = str.begin();
   size_t slen = str.size();
   sign = *p == '-' ? 1 : 0;
-  if(*p == '-' || *p == '+') {
+  if (*p == '-' || *p == '+') {
     p++;
     slen--;
     assert(slen && "String has no digits");
   }
 
-  if(slen >= 2 && p[0] == '0' && (p[1] == 'x' || p[1] == 'X')) {
+  if (slen >= 2 && p[0] == '0' && (p[1] == 'x' || p[1] == 'X')) {
     assert(slen - 2 && "Invalid string");
     return convertFromHexadecimalString(StringRef(p + 2, slen - 2),
                                         rounding_mode);
@@ -3013,7 +3011,7 @@
     // exponent2 and significand2 are required to be 0; we don't check
     category = fcInfinity;
   } else if (myexponent==0x7ff && mysignificand!=0) {
-    // exponent meaningless.  So is the whole second word, but keep it 
+    // exponent meaningless.  So is the whole second word, but keep it
     // for determinism.
     category = fcNaN;
     exponent2 = myexponent2;
@@ -3031,7 +3029,7 @@
       exponent = -1022;
     else
       significandParts()[0] |= 0x10000000000000LL;  // integer bit
-    if (myexponent2==0) 
+    if (myexponent2==0)
       exponent2 = -1022;
     else
       significandParts()[1] |= 0x10000000000000LL;  // integer bit
@@ -3217,8 +3215,8 @@
     significand[i] = ~((integerPart) 0);
 
   // ...and then clear the top bits for internal consistency.
-  significand[N-1]
-    &= (((integerPart) 1) << ((Sem.precision % integerPartWidth) - 1)) - 1;
+  significand[N-1] &=
+    (((integerPart) 1) << ((Sem.precision % integerPartWidth) - 1)) - 1;
 
   return Val;
 }
@@ -3247,8 +3245,8 @@
 
   Val.exponent = Sem.minExponent;
   Val.zeroSignificand();
-  Val.significandParts()[partCountForBits(Sem.precision)-1]
-    |= (((integerPart) 1) << ((Sem.precision % integerPartWidth) - 1));
+  Val.significandParts()[partCountForBits(Sem.precision)-1] |=
+    (((integerPart) 1) << ((Sem.precision % integerPartWidth) - 1));
 
   return Val;
 }
@@ -3433,7 +3431,7 @@
     //   log2(N * 5^e) == log2(N) + e * log2(5)
     //                 <= semantics->precision + e * 137 / 59
     //   (log_2(5) ~ 2.321928 < 2.322034 ~ 137/59)
-    
+
     unsigned precision = semantics->precision + 137 * texp / 59;
 
     // Multiply significand by 5^e.
@@ -3442,7 +3440,7 @@
     APInt five_to_the_i(precision, 5);
     while (true) {
       if (texp & 1) significand *= five_to_the_i;
-      
+
       texp >>= 1;
       if (!texp) break;
       five_to_the_i *= five_to_the_i;

Modified: llvm/trunk/lib/Support/APInt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/APInt.cpp?rev=99414&r1=99413&r2=99414&view=diff
==============================================================================
--- llvm/trunk/lib/Support/APInt.cpp (original)
+++ llvm/trunk/lib/Support/APInt.cpp Wed Mar 24 14:38:02 2010
@@ -702,15 +702,14 @@
   a = b = c = 0xdeadbeef + (((uint32_t)length)<<2);
 
   /*------------------------------------------------- handle most of the key */
-  while (length > 3)
-    {
-      a += k[0];
-      b += k[1];
-      c += k[2];
-      mix(a,b,c);
-      length -= 3;
-      k += 3;
-    }
+  while (length > 3) {
+    a += k[0];
+    b += k[1];
+    c += k[2];
+    mix(a,b,c);
+    length -= 3;
+    k += 3;
+  }
 
   /*------------------------------------------- handle the last 3 uint32_t's */
   switch (length) {                  /* all the case statements fall through */
@@ -2065,8 +2064,8 @@
   assert((slen <= numbits || radix != 2) && "Insufficient bit width");
   assert(((slen-1)*3 <= numbits || radix != 8) && "Insufficient bit width");
   assert(((slen-1)*4 <= numbits || radix != 16) && "Insufficient bit width");
-  assert((((slen-1)*64)/22 <= numbits || radix != 10)
-         && "Insufficient bit width");
+  assert((((slen-1)*64)/22 <= numbits || radix != 10) &&
+         "Insufficient bit width");
 
   // Allocate memory
   if (!isSingleWord())
@@ -2229,7 +2228,7 @@
   static inline integerPart
   lowBitMask(unsigned int bits)
   {
-    assert (bits != 0 && bits <= integerPartWidth);
+    assert(bits != 0 && bits <= integerPartWidth);
 
     return ~(integerPart) 0 >> (integerPartWidth - bits);
   }
@@ -2306,10 +2305,10 @@
 {
   unsigned int i;
 
-  assert (parts > 0);
+  assert(parts > 0);
 
   dst[0] = part;
-  for(i = 1; i < parts; i++)
+  for (i = 1; i < parts; i++)
     dst[i] = 0;
 }
 
@@ -2319,7 +2318,7 @@
 {
   unsigned int i;
 
-  for(i = 0; i < parts; i++)
+  for (i = 0; i < parts; i++)
     dst[i] = src[i];
 }
 
@@ -2329,7 +2328,7 @@
 {
   unsigned int i;
 
-  for(i = 0; i < parts; i++)
+  for (i = 0; i < parts; i++)
     if (src[i])
       return false;
 
@@ -2340,8 +2339,8 @@
 int
 APInt::tcExtractBit(const integerPart *parts, unsigned int bit)
 {
-  return(parts[bit / integerPartWidth]
-         & ((integerPart) 1 << bit % integerPartWidth)) != 0;
+  return (parts[bit / integerPartWidth] &
+          ((integerPart) 1 << bit % integerPartWidth)) != 0;
 }
 
 /* Set the given bit of a bignum. */
@@ -2366,7 +2365,7 @@
 {
   unsigned int i, lsb;
 
-  for(i = 0; i < n; i++) {
+  for (i = 0; i < n; i++) {
       if (parts[i] != 0) {
           lsb = partLSB(parts[i]);
 
@@ -2385,13 +2384,13 @@
   unsigned int msb;
 
   do {
-      --n;
+    --n;
 
-      if (parts[n] != 0) {
-          msb = partMSB(parts[n]);
+    if (parts[n] != 0) {
+      msb = partMSB(parts[n]);
 
-          return msb + n * integerPartWidth;
-      }
+      return msb + n * integerPartWidth;
+    }
   } while (n);
 
   return -1U;
@@ -2408,7 +2407,7 @@
   unsigned int firstSrcPart, dstParts, shift, n;
 
   dstParts = (srcBits + integerPartWidth - 1) / integerPartWidth;
-  assert (dstParts <= dstCount);
+  assert(dstParts <= dstCount);
 
   firstSrcPart = srcLSB / integerPartWidth;
   tcAssign (dst, src + firstSrcPart, dstParts);
@@ -2443,7 +2442,7 @@
 
   assert(c <= 1);
 
-  for(i = 0; i < parts; i++) {
+  for (i = 0; i < parts; i++) {
     integerPart l;
 
     l = dst[i];
@@ -2468,7 +2467,7 @@
 
   assert(c <= 1);
 
-  for(i = 0; i < parts; i++) {
+  for (i = 0; i < parts; i++) {
     integerPart l;
 
     l = dst[i];
@@ -2518,7 +2517,7 @@
   /* N loops; minimum of dstParts and srcParts.  */
   n = dstParts < srcParts ? dstParts: srcParts;
 
-  for(i = 0; i < n; i++) {
+  for (i = 0; i < n; i++) {
     integerPart low, mid, high, srcPart;
 
       /* [ LOW, HIGH ] = MULTIPLIER * SRC[i] + DST[i] + CARRY.
@@ -2583,7 +2582,7 @@
        non-zero.  This is true if any remaining src parts are non-zero
        and the multiplier is non-zero.  */
     if (multiplier)
-      for(; i < srcParts; i++)
+      for (; i < srcParts; i++)
         if (src[i])
           return 1;
 
@@ -2608,7 +2607,7 @@
   overflow = 0;
   tcSet(dst, 0, parts);
 
-  for(i = 0; i < parts; i++)
+  for (i = 0; i < parts; i++)
     overflow |= tcMultiplyPart(&dst[i], lhs, rhs[i], 0, parts,
                                parts - i, true);
 
@@ -2634,7 +2633,7 @@
 
     tcSet(dst, 0, rhsParts);
 
-    for(n = 0; n < lhsParts; n++)
+    for (n = 0; n < lhsParts; n++)
       tcMultiplyPart(&dst[n], rhs, lhs[n], 0, rhsParts, rhsParts + 1, true);
 
     n = lhsParts + rhsParts;
@@ -2678,7 +2677,7 @@
 
   /* Loop, subtracting SRHS if REMAINDER is greater and adding that to
      the total.  */
-  for(;;) {
+  for (;;) {
       int compare;
 
       compare = tcCompare(remainder, srhs, parts);
@@ -2746,7 +2745,7 @@
 
     /* Perform the shift.  This leaves the most significant COUNT bits
        of the result at zero.  */
-    for(i = 0; i < parts; i++) {
+    for (i = 0; i < parts; i++) {
       integerPart part;
 
       if (i + jump >= parts) {
@@ -2771,7 +2770,7 @@
 {
   unsigned int i;
 
-  for(i = 0; i < parts; i++)
+  for (i = 0; i < parts; i++)
     dst[i] &= rhs[i];
 }
 
@@ -2781,7 +2780,7 @@
 {
   unsigned int i;
 
-  for(i = 0; i < parts; i++)
+  for (i = 0; i < parts; i++)
     dst[i] |= rhs[i];
 }
 
@@ -2791,7 +2790,7 @@
 {
   unsigned int i;
 
-  for(i = 0; i < parts; i++)
+  for (i = 0; i < parts; i++)
     dst[i] ^= rhs[i];
 }
 
@@ -2801,7 +2800,7 @@
 {
   unsigned int i;
 
-  for(i = 0; i < parts; i++)
+  for (i = 0; i < parts; i++)
     dst[i] = ~dst[i];
 }
 
@@ -2830,7 +2829,7 @@
 {
   unsigned int i;
 
-  for(i = 0; i < parts; i++)
+  for (i = 0; i < parts; i++)
     if (++dst[i] != 0)
       break;
 

Modified: llvm/trunk/lib/Support/CommandLine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=99414&r1=99413&r2=99414&view=diff
==============================================================================
--- llvm/trunk/lib/Support/CommandLine.cpp (original)
+++ llvm/trunk/lib/Support/CommandLine.cpp Wed Mar 24 14:38:02 2010
@@ -676,8 +676,8 @@
          << " positional arguments: See: " << argv[0] << " -help\n";
 
     ErrorParsing = true;
-  } else if (!HasUnlimitedPositionals
-             && PositionalVals.size() > PositionalOpts.size()) {
+  } else if (!HasUnlimitedPositionals &&
+             PositionalVals.size() > PositionalOpts.size()) {
     errs() << ProgramName
          << ": Too many positional arguments specified!\n"
          << "Can specify at most " << PositionalOpts.size()

Modified: llvm/trunk/lib/Support/Debug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Debug.cpp?rev=99414&r1=99413&r2=99414&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Debug.cpp (original)
+++ llvm/trunk/lib/Support/Debug.cpp Wed Mar 24 14:38:02 2010
@@ -64,8 +64,7 @@
           cl::location(DebugOnlyOptLoc), cl::ValueRequired);
 
 // Signal handlers - dump debug output on termination.
-static void debug_user_sig_handler(void *Cookie)
-{
+static void debug_user_sig_handler(void *Cookie) {
   // This is a bit sneaky.  Since this is under #ifndef NDEBUG, we
   // know that debug mode is enabled and dbgs() really is a
   // circular_raw_ostream.  If NDEBUG is defined, then dbgs() ==

Modified: llvm/trunk/lib/Support/ErrorHandling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/ErrorHandling.cpp?rev=99414&r1=99413&r2=99414&view=diff
==============================================================================
--- llvm/trunk/lib/Support/ErrorHandling.cpp (original)
+++ llvm/trunk/lib/Support/ErrorHandling.cpp Wed Mar 24 14:38:02 2010
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file defines an API for error handling, it supersedes cerr+abort(), and 
+// This file defines an API for error handling, it supersedes cerr+abort(), and
 // cerr+exit() style error handling.
 // Callbacks can be registered for these errors through this API.
 //===----------------------------------------------------------------------===//
@@ -57,7 +57,7 @@
   exit(1);
 }
 
-void llvm_unreachable_internal(const char *msg, const char *file, 
+void llvm_unreachable_internal(const char *msg, const char *file,
                                unsigned line) {
   // This code intentionally doesn't call the ErrorHandler callback, because
   // llvm_unreachable is intended to be used to indicate "impossible"
@@ -71,4 +71,3 @@
   abort();
 }
 }
-

Modified: llvm/trunk/lib/Support/raw_ostream.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/raw_ostream.cpp?rev=99414&r1=99413&r2=99414&view=diff
==============================================================================
--- llvm/trunk/lib/Support/raw_ostream.cpp (original)
+++ llvm/trunk/lib/Support/raw_ostream.cpp Wed Mar 24 14:38:02 2010
@@ -81,9 +81,9 @@
     SetUnbuffered();
 }
 
-void raw_ostream::SetBufferAndMode(char *BufferStart, size_t Size, 
+void raw_ostream::SetBufferAndMode(char *BufferStart, size_t Size,
                                     BufferKind Mode) {
-  assert(((Mode == Unbuffered && BufferStart == 0 && Size == 0) || 
+  assert(((Mode == Unbuffered && BufferStart == 0 && Size == 0) ||
           (Mode != Unbuffered && BufferStart && Size)) &&
          "stream must be unbuffered or have at least one byte");
   // Make sure the current buffer is free of content (we can't flush here; the
@@ -104,11 +104,11 @@
   // Zero is a special case.
   if (N == 0)
     return *this << '0';
-  
+
   char NumberBuffer[20];
   char *EndPtr = NumberBuffer+sizeof(NumberBuffer);
   char *CurPtr = EndPtr;
-  
+
   while (N) {
     *--CurPtr = '0' + char(N % 10);
     N /= 10;
@@ -121,7 +121,7 @@
     *this << '-';
     N = -N;
   }
-  
+
   return this->operator<<(static_cast<unsigned long>(N));
 }
 
@@ -133,7 +133,7 @@
   char NumberBuffer[20];
   char *EndPtr = NumberBuffer+sizeof(NumberBuffer);
   char *CurPtr = EndPtr;
-  
+
   while (N) {
     *--CurPtr = '0' + char(N % 10);
     N /= 10;
@@ -146,7 +146,7 @@
     *this << '-';
     N = -N;
   }
-  
+
   return this->operator<<(static_cast<unsigned long long>(N));
 }
 
@@ -297,33 +297,33 @@
   size_t BufferBytesLeft = OutBufEnd - OutBufCur;
   if (BufferBytesLeft > 3) {
     size_t BytesUsed = Fmt.print(OutBufCur, BufferBytesLeft);
-    
+
     // Common case is that we have plenty of space.
     if (BytesUsed <= BufferBytesLeft) {
       OutBufCur += BytesUsed;
       return *this;
     }
-    
+
     // Otherwise, we overflowed and the return value tells us the size to try
     // again with.
     NextBufferSize = BytesUsed;
   }
-  
+
   // If we got here, we didn't have enough space in the output buffer for the
   // string.  Try printing into a SmallVector that is resized to have enough
   // space.  Iterate until we win.
   SmallVector<char, 128> V;
-  
+
   while (1) {
     V.resize(NextBufferSize);
-    
+
     // Try formatting into the SmallVector.
     size_t BytesUsed = Fmt.print(V.data(), NextBufferSize);
-    
+
     // If BytesUsed fit into the vector, we win.
     if (BytesUsed <= NextBufferSize)
       return write(V.data(), BytesUsed);
-    
+
     // Otherwise, try again with a new size.
     assert(BytesUsed > NextBufferSize && "Didn't grow buffer!?");
     NextBufferSize = BytesUsed;
@@ -339,7 +339,7 @@
   // Usually the indentation is small, handle it with a fastpath.
   if (NumSpaces < array_lengthof(Spaces))
     return write(Spaces, NumSpaces);
-  
+
   while (NumSpaces) {
     unsigned NumToWrite = std::min(NumSpaces,
                                    (unsigned)array_lengthof(Spaces)-1);
@@ -372,7 +372,7 @@
   // Verify that we don't have both "append" and "excl".
   assert((!(Flags & F_Excl) || !(Flags & F_Append)) &&
          "Cannot specify both 'excl' and 'append' file creation flags!");
-  
+
   ErrorInfo.clear();
 
   // Handle "-" as stdout.
@@ -385,20 +385,20 @@
     ShouldClose = false;
     return;
   }
-  
+
   int OpenFlags = O_WRONLY|O_CREAT;
 #ifdef O_BINARY
   if (Flags & F_Binary)
     OpenFlags |= O_BINARY;
 #endif
-  
+
   if (Flags & F_Append)
     OpenFlags |= O_APPEND;
   else
     OpenFlags |= O_TRUNC;
   if (Flags & F_Excl)
     OpenFlags |= O_EXCL;
-  
+
   FD = open(Filename, OpenFlags, 0664);
   if (FD < 0) {
     ErrorInfo = "Error opening output file '" + std::string(Filename) + "'";
@@ -418,14 +418,14 @@
 
 
 void raw_fd_ostream::write_impl(const char *Ptr, size_t Size) {
-  assert (FD >= 0 && "File already closed.");
+  assert(FD >= 0 && "File already closed.");
   pos += Size;
   if (::write(FD, Ptr, Size) != (ssize_t) Size)
     error_detected();
 }
 
 void raw_fd_ostream::close() {
-  assert (ShouldClose);
+  assert(ShouldClose);
   ShouldClose = false;
   flush();
   if (::close(FD) != 0)
@@ -438,7 +438,7 @@
   pos = ::lseek(FD, off, SEEK_SET);
   if (pos != off)
     error_detected();
-  return pos;  
+  return pos;
 }
 
 size_t raw_fd_ostream::preferred_buffer_size() const {
@@ -447,7 +447,7 @@
   struct stat statbuf;
   if (fstat(FD, &statbuf) != 0)
     return 0;
-  
+
   // If this is a terminal, don't use buffering. Line buffering
   // would be a more traditional thing to do, but it's not worth
   // the complexity.




From johnny.chen at apple.com  Wed Mar 24 14:47:14 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Wed, 24 Mar 2010 19:47:14 -0000
Subject: [llvm-commits] [llvm] r99415 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrNEON.td
Message-ID: <20100324194714.930952A6C12C@llvm.org>

Author: johnny
Date: Wed Mar 24 14:47:14 2010
New Revision: 99415

URL: http://llvm.org/viewvc/llvm-project?rev=99415&view=rev
Log:
Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
NVCVTFrm will later be used to describe "vcvt with fractional bits".

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99415&r1=99414&r2=99415&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Mar 24 14:47:14 2010
@@ -62,7 +62,6 @@
 def NLdStFrm            : Format<31>;
 def N1RegModImmFrm      : Format<32>;
 def N2RegFrm            : Format<33>;
-def NVCVTFrm            : Format<34>;
 
 // Misc flags.
 

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99415&r1=99414&r2=99415&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Mar 24 14:47:14 2010
@@ -853,41 +853,26 @@
 // Instruction Classes
 //===----------------------------------------------------------------------===//
 
-// Same as N2V except that it doesn't pass a default N2RegFrm to NDataI.
-class N2V2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
-          bits<5> op11_7, bit op6, bit op4,
-          dag oops, dag iops, Format f, InstrItinClass itin,
-          string opc, string dt, string asm, string cstr, list<dag> pattern>
-  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
-  let Inst{24-23} = op24_23;
-  let Inst{21-20} = op21_20;
-  let Inst{19-18} = op19_18;
-  let Inst{17-16} = op17_16;
-  let Inst{11-7} = op11_7;
-  let Inst{6} = op6;
-  let Inst{4} = op4;
-}
-
 // Basic 2-register operations: single-, double- and quad-register.
 // This is used for NVCVTFrm form.
 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
-  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
-         (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NVCVTFrm,
-         IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
+  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
+        (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
+        IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
-  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
-         (ins DPR:$src), NVCVTFrm, IIC_VUNAD, OpcodeStr, Dt,"$dst, $src","",
-         [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
+  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
+        (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "",
+        [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
-  : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
-         (ins QPR:$src), NVCVTFrm, IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src","",
-         [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
+  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
+        (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "",
+        [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
 
 // Basic 2-register intrinsics, both double- and quad-register.
 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,




From gohman at apple.com  Wed Mar 24 14:56:17 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 24 Mar 2010 19:56:17 -0000
Subject: [llvm-commits] [llvm] r99416 - in /llvm/trunk/tools:
 bugpoint/BugDriver.cpp llc/llc.cpp llvm-extract/llvm-extract.cpp
 llvm-ld/Optimize.cpp llvm-ld/llvm-ld.cpp llvm-link/llvm-link.cpp
 lto/LTOCodeGenerator.cpp opt/opt.cpp
Message-ID: <20100324195617.9FB582A6C12C@llvm.org>

Author: djg
Date: Wed Mar 24 14:56:17 2010
New Revision: 99416

URL: http://llvm.org/viewvc/llvm-project?rev=99416&view=rev
Log:
Trim #includes.

Modified:
    llvm/trunk/tools/bugpoint/BugDriver.cpp
    llvm/trunk/tools/llc/llc.cpp
    llvm/trunk/tools/llvm-extract/llvm-extract.cpp
    llvm/trunk/tools/llvm-ld/Optimize.cpp
    llvm/trunk/tools/llvm-ld/llvm-ld.cpp
    llvm/trunk/tools/llvm-link/llvm-link.cpp
    llvm/trunk/tools/lto/LTOCodeGenerator.cpp
    llvm/trunk/tools/opt/opt.cpp

Modified: llvm/trunk/tools/bugpoint/BugDriver.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/BugDriver.cpp?rev=99416&r1=99415&r2=99416&view=diff
==============================================================================
--- llvm/trunk/tools/bugpoint/BugDriver.cpp (original)
+++ llvm/trunk/tools/bugpoint/BugDriver.cpp Wed Mar 24 14:56:17 2010
@@ -21,7 +21,6 @@
 #include "llvm/Support/IRReader.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FileUtilities.h"
-#include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/System/Host.h"

Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=99416&r1=99415&r2=99416&view=diff
==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Wed Mar 24 14:56:17 2010
@@ -25,10 +25,8 @@
 #include "llvm/Config/config.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
-#include "llvm/Support/FileUtilities.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/ManagedStatic.h"
-#include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/PluginLoader.h"
 #include "llvm/Support/PrettyStackTrace.h"
 #include "llvm/System/Host.h"
@@ -38,7 +36,6 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetRegistry.h"
 #include "llvm/Target/TargetSelect.h"
-#include "llvm/Transforms/Scalar.h"
 #include <memory>
 using namespace llvm;
 

Modified: llvm/trunk/tools/llvm-extract/llvm-extract.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-extract/llvm-extract.cpp?rev=99416&r1=99415&r2=99416&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-extract/llvm-extract.cpp (original)
+++ llvm/trunk/tools/llvm-extract/llvm-extract.cpp Wed Mar 24 14:56:17 2010
@@ -22,7 +22,6 @@
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/IRReader.h"
 #include "llvm/Support/ManagedStatic.h"
-#include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/PrettyStackTrace.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Support/SystemUtils.h"

Modified: llvm/trunk/tools/llvm-ld/Optimize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ld/Optimize.cpp?rev=99416&r1=99415&r2=99416&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-ld/Optimize.cpp (original)
+++ llvm/trunk/tools/llvm-ld/Optimize.cpp Wed Mar 24 14:56:17 2010
@@ -13,17 +13,12 @@
 
 #include "llvm/Module.h"
 #include "llvm/PassManager.h"
-#include "llvm/Analysis/Passes.h"
-#include "llvm/Analysis/LoopPass.h"
-#include "llvm/Analysis/Verifier.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/StandardPasses.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/System/DynamicLibrary.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Transforms/IPO.h"
-#include "llvm/Transforms/Scalar.h"
 #include "llvm/Support/PassNameParser.h"
 #include "llvm/Support/PluginLoader.h"
 using namespace llvm;

Modified: llvm/trunk/tools/llvm-ld/llvm-ld.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ld/llvm-ld.cpp?rev=99416&r1=99415&r2=99416&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-ld/llvm-ld.cpp (original)
+++ llvm/trunk/tools/llvm-ld/llvm-ld.cpp Wed Mar 24 14:56:17 2010
@@ -30,7 +30,6 @@
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/CommandLine.h"
-#include "llvm/Support/FileUtilities.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/PrettyStackTrace.h"

Modified: llvm/trunk/tools/llvm-link/llvm-link.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-link/llvm-link.cpp?rev=99416&r1=99415&r2=99416&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-link/llvm-link.cpp (original)
+++ llvm/trunk/tools/llvm-link/llvm-link.cpp Wed Mar 24 14:56:17 2010
@@ -19,7 +19,6 @@
 #include "llvm/Bitcode/ReaderWriter.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ManagedStatic.h"
-#include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/PrettyStackTrace.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Support/SystemUtils.h"

Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=99416&r1=99415&r2=99416&view=diff
==============================================================================
--- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original)
+++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Mar 24 14:56:17 2010
@@ -24,8 +24,6 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/Analysis/Passes.h"
-#include "llvm/Analysis/LoopPass.h"
-#include "llvm/Analysis/Verifier.h"
 #include "llvm/Bitcode/ReaderWriter.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
@@ -36,8 +34,6 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetRegistry.h"
 #include "llvm/Target/TargetSelect.h"
-#include "llvm/Transforms/IPO.h"
-#include "llvm/Transforms/Scalar.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/MemoryBuffer.h"

Modified: llvm/trunk/tools/opt/opt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=99416&r1=99415&r2=99416&view=diff
==============================================================================
--- llvm/trunk/tools/opt/opt.cpp (original)
+++ llvm/trunk/tools/opt/opt.cpp Wed Mar 24 14:56:17 2010
@@ -28,7 +28,6 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/IRReader.h"
 #include "llvm/Support/ManagedStatic.h"
-#include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/PluginLoader.h"
 #include "llvm/Support/PrettyStackTrace.h"
 #include "llvm/Support/StandardPasses.h"




From evan.cheng at apple.com  Wed Mar 24 15:19:04 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 24 Mar 2010 20:19:04 -0000
Subject: [llvm-commits] [llvm] r99418 -
	/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
Message-ID: <20100324201904.980312A6C12C@llvm.org>

Author: evancheng
Date: Wed Mar 24 15:19:04 2010
New Revision: 99418

URL: http://llvm.org/viewvc/llvm-project?rev=99418&view=rev
Log:
Move OptChkCall off LibCallOptimization into StrCpyOpt.

Modified:
    llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=99418&r1=99417&r2=99418&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Wed Mar 24 15:19:04 2010
@@ -49,13 +49,10 @@
   Function *Caller;
   const TargetData *TD;
   LLVMContext* Context;
-  bool OptChkCall;  // True if it's optimizing a *_chk libcall.
 public:
-  LibCallOptimization() : OptChkCall(false) { }
+  LibCallOptimization() { }
   virtual ~LibCallOptimization() {}
 
-  void setOptChkCall(bool c) { OptChkCall = c; }
-
   /// CallOptimizer - This pure virtual method is implemented by base classes to
   /// do various optimizations.  If this returns null then no transformation was
   /// performed.  If it returns CI, then it transformed the call and CI is to be
@@ -353,6 +350,10 @@
 // 'strcpy' Optimizations
 
 struct StrCpyOpt : public LibCallOptimization {
+  bool OptChkCall;  // True if it's optimizing a __strcpy_chk libcall.
+
+  StrCpyOpt(bool c) : OptChkCall(c) {}
+
   virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
     // Verify the "strcpy" function prototype.
     unsigned NumParams = OptChkCall ? 3 : 2;
@@ -1188,8 +1189,7 @@
     bool Modified;  // This is only used by doInitialization.
   public:
     static char ID; // Pass identification
-    SimplifyLibCalls() : FunctionPass(&ID) {}
-
+    SimplifyLibCalls() : FunctionPass(&ID), StrCpy(false), StrCpyChk(true) {}
     void InitOptimizations();
     bool runOnFunction(Function &F);
 
@@ -1240,7 +1240,6 @@
   Optimizations["memset"] = &MemSet;
 
   // _chk variants of String and Memory LibCall Optimizations.
-  StrCpyChk.setOptChkCall(true);
   Optimizations["__strcpy_chk"] = &StrCpyChk;
 
   // Math Library Optimizations




From bob.wilson at apple.com  Wed Mar 24 15:24:06 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 24 Mar 2010 13:24:06 -0700
Subject: [llvm-commits] [llvm] r99400 - in /llvm/trunk:
	lib/CodeGen/LiveIntervalAnalysis.cpp
	test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
In-Reply-To: <20100324135036.CB2412A6C12C@llvm.org>
References: <20100324135036.CB2412A6C12C@llvm.org>
Message-ID: <2FB1B738-C12D-49DF-8678-79C0E20F46F4@apple.com>

This breaks MultiSource/Applications/ClamAV/clamscan.
I'm going to revert it for now.

On Mar 24, 2010, at 6:50 AM, Torok Edwin wrote:

> Author: edwin
> Date: Wed Mar 24 08:50:36 2010
> New Revision: 99400
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99400&view=rev
> Log:
> Fix memory leak in liveintervals: the destructor for VNInfos must be called,
> otherwise the SmallVector it contains doesn't free its memory.
> In most cases LiveIntervalAnalysis could get away by not calling the destructor,
> because VNInfos are bumpptr-allocated, and smallvectors usually don't grow.
> However when the SmallVector does grow it always leaks.
> 
> This is the valgrind shown leak from the original testcase:
> ==8206== 18,304 bytes in 151 blocks are definitely lost in loss record 164 of 164
> ==8206==    at 0x4A079C7: operator new(unsigned long) (vg_replace_malloc.c:220)
> ==8206==    by 0x4DB7A7E: llvm::SmallVectorBase::grow_pod(unsigned long, unsigned long) (in /home/edwin/clam/git/builds/defaul
> t/libclamav/.libs/libclamav.so.6.1.0)
> ==8206==    by 0x4F90382: llvm::VNInfo::addKill(llvm::SlotIndex) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libcl
> amav.so.6.1.0)
> ==8206==    by 0x5126B5C: llvm::LiveIntervals::handleVirtualRegisterDef(llvm::MachineBasicBlock*, llvm::ilist_iterator<llvm::M
> achineInstr>, llvm::SlotIndex, llvm::MachineOperand&, unsigned int, llvm::LiveInterval&) (in /home/edwin/clam/git/builds/defau
> lt/libclamav/.libs/libclamav.so.6.1.0)
> ==8206==    by 0x512725E: llvm::LiveIntervals::handleRegisterDef(llvm::MachineBasicBlock*, llvm::ilist_iterator<llvm::MachineI
> nstr>, llvm::SlotIndex, llvm::MachineOperand&, unsigned int) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libclamav
> .so.6.1.0)
> ==8206==    by 0x51278A8: llvm::LiveIntervals::computeIntervals() (in /home/edwin/clam/git/builds/default/libclamav/.libs/libc
> lamav.so.6.1.0)
> ==8206==    by 0x5127CB4: llvm::LiveIntervals::runOnMachineFunction(llvm::MachineFunction&) (in /home/edwin/clam/git/builds/de
> fault/libclamav/.libs/libclamav.so.6.1.0)
> ==8206==    by 0x4DAE935: llvm::FPPassManager::runOnFunction(llvm::Function&) (in /home/edwin/clam/git/builds/default/libclama
> v/.libs/libclamav.so.6.1.0)
> ==8206==    by 0x4DAEB10: llvm::FunctionPassManagerImpl::run(llvm::Function&) (in /home/edwin/clam/git/builds/default/libclama
> v/.libs/libclamav.so.6.1.0)
> ==8206==    by 0x4DAED3D: llvm::FunctionPassManager::run(llvm::Function&) (in /home/edwin/clam/git/builds/default/libclamav/.l
> ibs/libclamav.so.6.1.0)
> ==8206==    by 0x4D8BE8E: llvm::JIT::runJITOnFunctionUnlocked(llvm::Function*, llvm::MutexGuard const&) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libclamav.so.6.1.0)
> ==8206==    by 0x4D8CA72: llvm::JIT::getPointerToFunction(llvm::Function*) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libclamav.so.6.1.0)
> 
> Added:
>    llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
> Modified:
>    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=99400&r1=99399&r2=99400&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Mar 24 08:50:36 2010
> @@ -85,8 +85,10 @@
> void LiveIntervals::releaseMemory() {
>   // Free the live intervals themselves.
>   for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
> -       E = r2iMap_.end(); I != E; ++I)
> +       E = r2iMap_.end(); I != E; ++I) {
> +    I->second->clear();
>     delete I->second;
> +  }
> 
>   r2iMap_.clear();
> 
> 
> Added: llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll?rev=99400&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll (added)
> +++ llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll Wed Mar 24 08:50:36 2010
> @@ -0,0 +1,114 @@
> +; RUN: llc <%s
> +%0 = type { i8, %1, i8, %1, i8, %1 }
> +%1 = type { i32 }
> +%2 = type { i16, i8, i8, i8, [3 x [10 x i8]], [29 x i8] }
> +%3 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
> +%4 = type { i32, i32, i16, i16, %5, %6, i32, %8, [16 x %7], i32, i32, i32, i32 }
> +%5 = type { i32, i16, i16, i32, i32, i32, i16, i16 }
> +%6 = type { i16, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16, i16, i16, i16, i16, i32, i32, i32, i32, i16, i16, i32, i32, i32, i32, i32, i32, [16 x %7] }
> +%7 = type { i32, i32 }
> +%8 = type { i16, i8, i8, i32, i32, i32, i32, i32, i64, i32, i32, i16, i16, i16, i16, i16, i16, i32, i32, i32, i32, i16, i16, i64, i64, i64, i64, i32, i32, [16 x %7] }
> + at glob2 = internal constant [39 x i8] c"ClamAV-Test-File-detected-via-bytecode\00" ; <[39 x i8]*> [#uses=1]
> + at glob9 = internal constant [5 x i8] c"EP: \00"    ; <[5 x i8]*> [#uses=1]
> + at glob10 = internal constant [27 x i8] c"Couldn't read 5 bytes @EP\0A\00" ; <[27 x i8]*> [#uses=1]
> + at glob11 = internal constant [46 x i8] c"No 'mov ebx, cyphertext' found at entrypoint\0A\00" ; <[46 x i8]*> [#uses=1]
> + at glob12 = internal constant [21 x i8] c"VA of cyphertext is \00" ; <[21 x i8]*> [#uses=1]
> + at glob13 = internal constant [22 x i8] c"RVA of cyphertext is \00" ; <[22 x i8]*> [#uses=1]
> + at glob14 = internal constant [51 x i8] c"Can't locate the phisical offset of the cyphertext\00" ; <[51 x i8]*> [#uses=1]
> + at glob15 = internal constant [22 x i8] c"Cyphertext starts at \00" ; <[22 x i8]*> [#uses=1]
> + at glob16 = internal constant [35 x i8] c"Can't read 10 bytes of cyphertext\0A\00" ; <[35 x i8]*> [#uses=1]
> + at glob17 = internal constant [11 x i8] c"HELLO WORM\00" ; <[11 x i8]*> [#uses=1]
> +declare i32 @llvm.bswap.i32(i32) nounwind readnone
> +declare i32 @memcmp(i8*, i8*, i64)
> +declare i32 @read([128 x i8]*, i8*, i32)
> +declare i32 @seek([128 x i8]*, i32, i32)
> +declare i32 @setvirusname([128 x i8]*, i8*, i32)
> +declare i32 @debug_print_str([128 x i8]*, i8*, i32)
> +declare i32 @debug_print_uint([128 x i8]*, i32)
> +declare i32 @pe_rawaddr([128 x i8]*, i32)
> +define internal fastcc i32 @bc0f0([128 x i8]*) nounwind ssp sspreq {
> +  %2 = alloca [5 x i8]                            ; <[5 x i8]*> [#uses=3]
> +  %3 = alloca [11 x i8]                           ; <[11 x i8]*> [#uses=5]
> +  %4 = getelementptr inbounds [128 x i8]* %0, i32 0, i32 120 ; <i8*> [#uses=1]
> +  %5 = bitcast i8* %4 to %4**                     ; <%4**> [#uses=1]
> +  %6 = load %4** %5                               ; <%4*> [#uses=1]
> +  %g3_1 = bitcast %4* %6 to i8*                   ; <i8*> [#uses=1]
> +  %7 = getelementptr i8* %g3_1, i32 64            ; <i8*> [#uses=1]
> +  %8 = bitcast i8* %7 to %4**                     ; <%4**> [#uses=1]
> +  %9 = getelementptr inbounds [128 x i8]* %0, i32 0, i32 120 ; <i8*> [#uses=1]
> +  %10 = bitcast i8* %9 to %4**                    ; <%4**> [#uses=1]
> +  %11 = load %4** %10                             ; <%4*> [#uses=1]
> +  %g3_2 = bitcast %4* %11 to i8*                  ; <i8*> [#uses=1]
> +  %12 = getelementptr i8* %g3_2, i32 4            ; <i8*> [#uses=1]
> +  %13 = bitcast i8* %12 to %4**                   ; <%4**> [#uses=1]
> +  %14 = bitcast %4** %13 to i32*                  ; <i32*> [#uses=1]
> +  %15 = load i32* %14                             ; <i32> [#uses=2]
> +  %16 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([5 x i8]* @glob9, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
> +  %17 = call i32 @debug_print_uint([128 x i8]* %0, i32 %15) ; <i32> [#uses=0]
> +  %18 = call i32 @seek([128 x i8]* %0, i32 %15, i32 0) ; <i32> [#uses=0]
> +  %19 = getelementptr [5 x i8]* %2, i32 0, i32 0  ; <i8*> [#uses=1]
> +  %20 = call i32 @read([128 x i8]* %0, i8* %19, i32 5) ; <i32> [#uses=1]
> +  %21 = icmp eq i32 %20, 5                        ; <i1> [#uses=1]
> +  br i1 %21, label %24, label %22
> +  %23 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([27 x i8]* @glob10, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
> +  ret i32 0
> +  %25 = getelementptr [5 x i8]* %2, i32 0, i32 0  ; <i8*> [#uses=1]
> +  %26 = load i8* %25                              ; <i8> [#uses=1]
> +  %27 = icmp eq i8 %26, -69                       ; <i1> [#uses=1]
> +  br i1 %27, label %30, label %28
> +  %29 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([46 x i8]* @glob11, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
> +  ret i32 0
> +  %31 = getelementptr [5 x i8]* %2, i32 0, i32 1  ; <i8*> [#uses=1]
> +  %32 = bitcast i8* %31 to i32*                   ; <i32*> [#uses=1]
> +  %33 = load i32* %32                             ; <i32> [#uses=2]
> +  br i1 false, label %34, label %36
> +  %35 = tail call i32 @llvm.bswap.i32(i32 %33) nounwind ; <i32> [#uses=1]
> +  br label %36
> +  %.06 = phi i32 [ %35, %34 ], [ %33, %30 ]       ; <i32> [#uses=2]
> +  %37 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([21 x i8]* @glob12, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
> +  %38 = call i32 @debug_print_uint([128 x i8]* %0, i32 %.06) ; <i32> [#uses=0]
> +  %39 = bitcast %4** %8 to i32*                   ; <i32*> [#uses=1]
> +  %40 = load i32* %39                             ; <i32> [#uses=1]
> +  %41 = sub i32 %.06, %40                         ; <i32> [#uses=2]
> +  %42 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([22 x i8]* @glob13, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
> +  %43 = call i32 @debug_print_uint([128 x i8]* %0, i32 %41) ; <i32> [#uses=0]
> +  %44 = call i32 @pe_rawaddr([128 x i8]* %0, i32 %41) ; <i32> [#uses=3]
> +  %45 = icmp eq i32 %44, -1                       ; <i1> [#uses=1]
> +  br i1 %45, label %46, label %48
> +  %47 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([51 x i8]* @glob14, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
> +  ret i32 0
> +  %49 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([22 x i8]* @glob15, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
> +  %50 = call i32 @debug_print_uint([128 x i8]* %0, i32 %44) ; <i32> [#uses=0]
> +  %51 = call i32 @seek([128 x i8]* %0, i32 %44, i32 0) ; <i32> [#uses=0]
> +  %52 = getelementptr [11 x i8]* %3, i32 0, i32 0 ; <i8*> [#uses=1]
> +  %53 = call i32 @read([128 x i8]* %0, i8* %52, i32 10) ; <i32> [#uses=1]
> +  %54 = icmp eq i32 %53, 10                       ; <i1> [#uses=1]
> +  br i1 %54, label %57, label %55
> +  %56 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([35 x i8]* @glob16, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
> +  ret i32 0
> +  %.05 = phi i32 [ 0, %48 ], [ %66, %65 ]         ; <i32> [#uses=4]
> +  %.0 = phi i8 [ 41, %48 ], [ %63, %65 ]          ; <i8> [#uses=1]
> +  %58 = getelementptr [11 x i8]* %3, i32 0, i32 %.05 ; <i8*> [#uses=2]
> +  %59 = icmp ult i32 %.05, 11                     ; <i1> [#uses=1]
> +  br i1 %59, label %60, label %79
> +  %61 = add i8 %.0, 1                             ; <i8> [#uses=1]
> +  %62 = load i8* %58                              ; <i8> [#uses=1]
> +  %63 = xor i8 %62, %61                           ; <i8> [#uses=2]
> +  %64 = icmp ult i32 %.05, 11                     ; <i1> [#uses=1]
> +  br i1 %64, label %65, label %79
> +  %66 = add i32 %.05, 1                           ; <i32> [#uses=2]
> +  %67 = icmp eq i32 %66, 10                       ; <i1> [#uses=1]
> +  br i1 %67, label %68, label %57
> +  %69 = getelementptr [11 x i8]* %3, i32 0, i32 0 ; <i8*> [#uses=1]
> +  %70 = tail call i32 @memcmp(i8* %69, i8* getelementptr inbounds ([11 x i8]* @glob17, i32 0, i32 0), i64 10) nounwind ; <i32> [#uses=1]
> +  %71 = icmp eq i32 %70, 0                        ; <i1> [#uses=1]
> +  br i1 %71, label %72, label %78
> +  %73 = getelementptr [11 x i8]* %3, i32 0, i32 10 ; <i8*> [#uses=1]
> +  %74 = bitcast i8* %73 to i1*                    ; <i1*> [#uses=1]
> +  %75 = getelementptr [11 x i8]* %3, i32 0, i32 0 ; <i8*> [#uses=1]
> +  %76 = call i32 @debug_print_str([128 x i8]* %0, i8* %75, i32 0) ; <i32> [#uses=0]
> +  %77 = call i32 @setvirusname([128 x i8]* %0, i8* getelementptr inbounds ([39 x i8]* @glob2, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
> +  ret i32 0
> +  ret i32 0
> +  unreachable
> +}
> 
> 
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> llvm-commits at cs.uiuc.edu
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From bob.wilson at apple.com  Wed Mar 24 15:25:25 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 24 Mar 2010 20:25:25 -0000
Subject: [llvm-commits] [llvm] r99419 - in /llvm/trunk:
 lib/CodeGen/LiveIntervalAnalysis.cpp
 test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
Message-ID: <20100324202525.A49592A6C12C@llvm.org>

Author: bwilson
Date: Wed Mar 24 15:25:25 2010
New Revision: 99419

URL: http://llvm.org/viewvc/llvm-project?rev=99419&view=rev
Log:
Revert Edwin's change that is breaking MultiSource/Applications/ClamAV/clamscan.
--- Reverse-merging r99400 into '.':
D    test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
U    lib/CodeGen/LiveIntervalAnalysis.cpp

Removed:
    llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=99419&r1=99418&r2=99419&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Mar 24 15:25:25 2010
@@ -85,10 +85,8 @@
 void LiveIntervals::releaseMemory() {
   // Free the live intervals themselves.
   for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
-       E = r2iMap_.end(); I != E; ++I) {
-    I->second->clear();
+       E = r2iMap_.end(); I != E; ++I)
     delete I->second;
-  }
   
   r2iMap_.clear();
 

Removed: llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll?rev=99418&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2010-03-24-liveintervalleak.ll (removed)
@@ -1,114 +0,0 @@
-; RUN: llc <%s
-%0 = type { i8, %1, i8, %1, i8, %1 }
-%1 = type { i32 }
-%2 = type { i16, i8, i8, i8, [3 x [10 x i8]], [29 x i8] }
-%3 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
-%4 = type { i32, i32, i16, i16, %5, %6, i32, %8, [16 x %7], i32, i32, i32, i32 }
-%5 = type { i32, i16, i16, i32, i32, i32, i16, i16 }
-%6 = type { i16, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16, i16, i16, i16, i16, i32, i32, i32, i32, i16, i16, i32, i32, i32, i32, i32, i32, [16 x %7] }
-%7 = type { i32, i32 }
-%8 = type { i16, i8, i8, i32, i32, i32, i32, i32, i64, i32, i32, i16, i16, i16, i16, i16, i16, i32, i32, i32, i32, i16, i16, i64, i64, i64, i64, i32, i32, [16 x %7] }
- at glob2 = internal constant [39 x i8] c"ClamAV-Test-File-detected-via-bytecode\00" ; <[39 x i8]*> [#uses=1]
- at glob9 = internal constant [5 x i8] c"EP: \00"    ; <[5 x i8]*> [#uses=1]
- at glob10 = internal constant [27 x i8] c"Couldn't read 5 bytes @EP\0A\00" ; <[27 x i8]*> [#uses=1]
- at glob11 = internal constant [46 x i8] c"No 'mov ebx, cyphertext' found at entrypoint\0A\00" ; <[46 x i8]*> [#uses=1]
- at glob12 = internal constant [21 x i8] c"VA of cyphertext is \00" ; <[21 x i8]*> [#uses=1]
- at glob13 = internal constant [22 x i8] c"RVA of cyphertext is \00" ; <[22 x i8]*> [#uses=1]
- at glob14 = internal constant [51 x i8] c"Can't locate the phisical offset of the cyphertext\00" ; <[51 x i8]*> [#uses=1]
- at glob15 = internal constant [22 x i8] c"Cyphertext starts at \00" ; <[22 x i8]*> [#uses=1]
- at glob16 = internal constant [35 x i8] c"Can't read 10 bytes of cyphertext\0A\00" ; <[35 x i8]*> [#uses=1]
- at glob17 = internal constant [11 x i8] c"HELLO WORM\00" ; <[11 x i8]*> [#uses=1]
-declare i32 @llvm.bswap.i32(i32) nounwind readnone
-declare i32 @memcmp(i8*, i8*, i64)
-declare i32 @read([128 x i8]*, i8*, i32)
-declare i32 @seek([128 x i8]*, i32, i32)
-declare i32 @setvirusname([128 x i8]*, i8*, i32)
-declare i32 @debug_print_str([128 x i8]*, i8*, i32)
-declare i32 @debug_print_uint([128 x i8]*, i32)
-declare i32 @pe_rawaddr([128 x i8]*, i32)
-define internal fastcc i32 @bc0f0([128 x i8]*) nounwind ssp sspreq {
-  %2 = alloca [5 x i8]                            ; <[5 x i8]*> [#uses=3]
-  %3 = alloca [11 x i8]                           ; <[11 x i8]*> [#uses=5]
-  %4 = getelementptr inbounds [128 x i8]* %0, i32 0, i32 120 ; <i8*> [#uses=1]
-  %5 = bitcast i8* %4 to %4**                     ; <%4**> [#uses=1]
-  %6 = load %4** %5                               ; <%4*> [#uses=1]
-  %g3_1 = bitcast %4* %6 to i8*                   ; <i8*> [#uses=1]
-  %7 = getelementptr i8* %g3_1, i32 64            ; <i8*> [#uses=1]
-  %8 = bitcast i8* %7 to %4**                     ; <%4**> [#uses=1]
-  %9 = getelementptr inbounds [128 x i8]* %0, i32 0, i32 120 ; <i8*> [#uses=1]
-  %10 = bitcast i8* %9 to %4**                    ; <%4**> [#uses=1]
-  %11 = load %4** %10                             ; <%4*> [#uses=1]
-  %g3_2 = bitcast %4* %11 to i8*                  ; <i8*> [#uses=1]
-  %12 = getelementptr i8* %g3_2, i32 4            ; <i8*> [#uses=1]
-  %13 = bitcast i8* %12 to %4**                   ; <%4**> [#uses=1]
-  %14 = bitcast %4** %13 to i32*                  ; <i32*> [#uses=1]
-  %15 = load i32* %14                             ; <i32> [#uses=2]
-  %16 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([5 x i8]* @glob9, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
-  %17 = call i32 @debug_print_uint([128 x i8]* %0, i32 %15) ; <i32> [#uses=0]
-  %18 = call i32 @seek([128 x i8]* %0, i32 %15, i32 0) ; <i32> [#uses=0]
-  %19 = getelementptr [5 x i8]* %2, i32 0, i32 0  ; <i8*> [#uses=1]
-  %20 = call i32 @read([128 x i8]* %0, i8* %19, i32 5) ; <i32> [#uses=1]
-  %21 = icmp eq i32 %20, 5                        ; <i1> [#uses=1]
-  br i1 %21, label %24, label %22
-  %23 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([27 x i8]* @glob10, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
-  ret i32 0
-  %25 = getelementptr [5 x i8]* %2, i32 0, i32 0  ; <i8*> [#uses=1]
-  %26 = load i8* %25                              ; <i8> [#uses=1]
-  %27 = icmp eq i8 %26, -69                       ; <i1> [#uses=1]
-  br i1 %27, label %30, label %28
-  %29 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([46 x i8]* @glob11, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
-  ret i32 0
-  %31 = getelementptr [5 x i8]* %2, i32 0, i32 1  ; <i8*> [#uses=1]
-  %32 = bitcast i8* %31 to i32*                   ; <i32*> [#uses=1]
-  %33 = load i32* %32                             ; <i32> [#uses=2]
-  br i1 false, label %34, label %36
-  %35 = tail call i32 @llvm.bswap.i32(i32 %33) nounwind ; <i32> [#uses=1]
-  br label %36
-  %.06 = phi i32 [ %35, %34 ], [ %33, %30 ]       ; <i32> [#uses=2]
-  %37 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([21 x i8]* @glob12, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
-  %38 = call i32 @debug_print_uint([128 x i8]* %0, i32 %.06) ; <i32> [#uses=0]
-  %39 = bitcast %4** %8 to i32*                   ; <i32*> [#uses=1]
-  %40 = load i32* %39                             ; <i32> [#uses=1]
-  %41 = sub i32 %.06, %40                         ; <i32> [#uses=2]
-  %42 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([22 x i8]* @glob13, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
-  %43 = call i32 @debug_print_uint([128 x i8]* %0, i32 %41) ; <i32> [#uses=0]
-  %44 = call i32 @pe_rawaddr([128 x i8]* %0, i32 %41) ; <i32> [#uses=3]
-  %45 = icmp eq i32 %44, -1                       ; <i1> [#uses=1]
-  br i1 %45, label %46, label %48
-  %47 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([51 x i8]* @glob14, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
-  ret i32 0
-  %49 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([22 x i8]* @glob15, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
-  %50 = call i32 @debug_print_uint([128 x i8]* %0, i32 %44) ; <i32> [#uses=0]
-  %51 = call i32 @seek([128 x i8]* %0, i32 %44, i32 0) ; <i32> [#uses=0]
-  %52 = getelementptr [11 x i8]* %3, i32 0, i32 0 ; <i8*> [#uses=1]
-  %53 = call i32 @read([128 x i8]* %0, i8* %52, i32 10) ; <i32> [#uses=1]
-  %54 = icmp eq i32 %53, 10                       ; <i1> [#uses=1]
-  br i1 %54, label %57, label %55
-  %56 = call i32 @debug_print_str([128 x i8]* %0, i8* getelementptr inbounds ([35 x i8]* @glob16, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
-  ret i32 0
-  %.05 = phi i32 [ 0, %48 ], [ %66, %65 ]         ; <i32> [#uses=4]
-  %.0 = phi i8 [ 41, %48 ], [ %63, %65 ]          ; <i8> [#uses=1]
-  %58 = getelementptr [11 x i8]* %3, i32 0, i32 %.05 ; <i8*> [#uses=2]
-  %59 = icmp ult i32 %.05, 11                     ; <i1> [#uses=1]
-  br i1 %59, label %60, label %79
-  %61 = add i8 %.0, 1                             ; <i8> [#uses=1]
-  %62 = load i8* %58                              ; <i8> [#uses=1]
-  %63 = xor i8 %62, %61                           ; <i8> [#uses=2]
-  %64 = icmp ult i32 %.05, 11                     ; <i1> [#uses=1]
-  br i1 %64, label %65, label %79
-  %66 = add i32 %.05, 1                           ; <i32> [#uses=2]
-  %67 = icmp eq i32 %66, 10                       ; <i1> [#uses=1]
-  br i1 %67, label %68, label %57
-  %69 = getelementptr [11 x i8]* %3, i32 0, i32 0 ; <i8*> [#uses=1]
-  %70 = tail call i32 @memcmp(i8* %69, i8* getelementptr inbounds ([11 x i8]* @glob17, i32 0, i32 0), i64 10) nounwind ; <i32> [#uses=1]
-  %71 = icmp eq i32 %70, 0                        ; <i1> [#uses=1]
-  br i1 %71, label %72, label %78
-  %73 = getelementptr [11 x i8]* %3, i32 0, i32 10 ; <i8*> [#uses=1]
-  %74 = bitcast i8* %73 to i1*                    ; <i1*> [#uses=1]
-  %75 = getelementptr [11 x i8]* %3, i32 0, i32 0 ; <i8*> [#uses=1]
-  %76 = call i32 @debug_print_str([128 x i8]* %0, i8* %75, i32 0) ; <i32> [#uses=0]
-  %77 = call i32 @setvirusname([128 x i8]* %0, i8* getelementptr inbounds ([39 x i8]* @glob2, i32 0, i32 0), i32 0) ; <i32> [#uses=0]
-  ret i32 0
-  ret i32 0
-  unreachable
-}




From natebegeman at mac.com  Wed Mar 24 15:49:50 2010
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 24 Mar 2010 20:49:50 -0000
Subject: [llvm-commits] [llvm] r99423 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/vec_insert-4.ll
 test/CodeGen/X86/vec_insert-9.ll test/CodeGen/X86/vec_insert_4.ll
 test/CodeGen/X86/vec_set.ll test/CodeGen/X86/vec_shuffle.ll
Message-ID: <20100324204951.275D62A6C12C@llvm.org>

Author: sampo
Date: Wed Mar 24 15:49:50 2010
New Revision: 99423

URL: http://llvm.org/viewvc/llvm-project?rev=99423&view=rev
Log:
BUILD_VECTOR was missing out on some prime opportunities to use SSE 4.1 inserts.

Added:
    llvm/trunk/test/CodeGen/X86/vec_insert-4.ll
      - copied unchanged from r99402, llvm/trunk/test/CodeGen/X86/vec_insert_4.ll
    llvm/trunk/test/CodeGen/X86/vec_insert-9.ll
Removed:
    llvm/trunk/test/CodeGen/X86/vec_insert_4.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/vec_set.ll
    llvm/trunk/test/CodeGen/X86/vec_shuffle.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=99423&r1=99422&r2=99423&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Mar 24 15:49:50 2010
@@ -3613,6 +3613,54 @@
   return SDValue();
 }
 
+static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
+                                        DebugLoc &dl, SelectionDAG &DAG) {
+  EVT EltVT = VT.getVectorElementType();
+  unsigned NumElems = Elts.size();
+  
+  // FIXME: check for zeroes
+  LoadSDNode *LDBase = NULL;
+  unsigned LastLoadedElt = -1U;
+  for (unsigned i = 0; i < NumElems; ++i) {
+    SDValue Elt = Elts[i];
+    
+    if (!Elt.getNode() ||
+        (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
+      return SDValue();
+    if (!LDBase) {
+      if (Elt.getNode()->getOpcode() == ISD::UNDEF)
+        return SDValue();
+      LDBase = cast<LoadSDNode>(Elt.getNode());
+      LastLoadedElt = i;
+      continue;
+    }
+    if (Elt.getOpcode() == ISD::UNDEF)
+      continue;
+
+    LoadSDNode *LD = cast<LoadSDNode>(Elt);
+    if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
+      return SDValue();
+    LastLoadedElt = i;
+  }
+                                       
+  if (LastLoadedElt == NumElems - 1) {
+    if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
+      return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
+                         LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
+                         LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
+    return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
+                       LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
+                       LDBase->isVolatile(), LDBase->isNonTemporal(),
+                       LDBase->getAlignment());
+  } else if (NumElems == 4 && LastLoadedElt == 1) {
+    SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
+    SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
+    SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
+    return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
+  }
+  return SDValue();
+}
+
 SDValue
 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
   DebugLoc dl = Op.getDebugLoc();
@@ -3841,14 +3889,18 @@
     return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
   }
 
-  if (Values.size() > 2) {
-    // If we have SSE 4.1, Expand into a number of inserts unless the number of
-    // values to be inserted is equal to the number of elements, in which case
-    // use the unpack code below in the hopes of matching the consecutive elts
-    // load merge pattern for shuffles.
-    // FIXME: We could probably just check that here directly.
-    if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
-        getSubtarget()->hasSSE41()) {
+  if (Values.size() > 1 && VT.getSizeInBits() == 128) {
+    // Check for a build vector of consecutive loads.
+    for (unsigned i = 0; i < NumElems; ++i)
+      V[i] = Op.getOperand(i);
+    
+    // Check for elements which are consecutive loads.
+    SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
+    if (LD.getNode())
+      return LD;
+    
+    // For SSE 4.1, use inserts into undef.  
+    if (getSubtarget()->hasSSE41()) {
       V[0] = DAG.getUNDEF(VT);
       for (unsigned i = 0; i < NumElems; ++i)
         if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
@@ -3856,7 +3908,8 @@
                              Op.getOperand(i), DAG.getIntPtrConstant(i));
       return V[0];
     }
-    // Expand into a number of unpckl*.
+    
+    // Otherwise, expand into a number of unpckl*
     // e.g. for v4f32
     //   Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
     //         : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
@@ -3871,7 +3924,6 @@
     }
     return V[0];
   }
-
   return SDValue();
 }
 
@@ -8797,83 +8849,24 @@
   return TargetLowering::isGAPlusOffset(N, GA, Offset);
 }
 
-static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
-                                     EVT EltVT, LoadSDNode *&LDBase,
-                                     unsigned &LastLoadedElt,
-                                     SelectionDAG &DAG, MachineFrameInfo *MFI,
-                                     const TargetLowering &TLI) {
-  LDBase = NULL;
-  LastLoadedElt = -1U;
-  for (unsigned i = 0; i < NumElems; ++i) {
-    if (N->getMaskElt(i) < 0) {
-      if (!LDBase)
-        return false;
-      continue;
-    }
-
-    SDValue Elt = DAG.getShuffleScalarElt(N, i);
-    if (!Elt.getNode() ||
-        (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
-      return false;
-    if (!LDBase) {
-      if (Elt.getNode()->getOpcode() == ISD::UNDEF)
-        return false;
-      LDBase = cast<LoadSDNode>(Elt.getNode());
-      LastLoadedElt = i;
-      continue;
-    }
-    if (Elt.getOpcode() == ISD::UNDEF)
-      continue;
-
-    LoadSDNode *LD = cast<LoadSDNode>(Elt);
-    if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
-      return false;
-    LastLoadedElt = i;
-  }
-  return true;
-}
-
 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
 /// if the load addresses are consecutive, non-overlapping, and in the right
-/// order.  In the case of v2i64, it will see if it can rewrite the
-/// shuffle to be an appropriate build vector so it can take advantage of
-// performBuildVectorCombine.
+/// order.
 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
                                      const TargetLowering &TLI) {
   DebugLoc dl = N->getDebugLoc();
   EVT VT = N->getValueType(0);
-  EVT EltVT = VT.getVectorElementType();
   ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
-  unsigned NumElems = VT.getVectorNumElements();
 
   if (VT.getSizeInBits() != 128)
     return SDValue();
 
-  // Try to combine a vector_shuffle into a 128-bit load.
-  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
-  LoadSDNode *LD = NULL;
-  unsigned LastLoadedElt;
-  if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
-                                MFI, TLI))
-    return SDValue();
-
-  if (LastLoadedElt == NumElems - 1) {
-    if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
-      return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
-                         LD->getSrcValue(), LD->getSrcValueOffset(),
-                         LD->isVolatile(), LD->isNonTemporal(), 0);
-    return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
-                       LD->getSrcValue(), LD->getSrcValueOffset(),
-                       LD->isVolatile(), LD->isNonTemporal(),
-                       LD->getAlignment());
-  } else if (NumElems == 4 && LastLoadedElt == 1) {
-    SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
-    SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
-    SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
-    return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
-  }
-  return SDValue();
+  SmallVector<SDValue, 16> Elts;
+  for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
+    Elts.push_back(DAG.getShuffleScalarElt(SVN, i));
+  
+  return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
 }
 
 /// PerformShuffleCombine - Detect vector gather/scatter index generation

Added: llvm/trunk/test/CodeGen/X86/vec_insert-9.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_insert-9.ll?rev=99423&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_insert-9.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vec_insert-9.ll Wed Mar 24 15:49:50 2010
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 -mattr=+sse41 > %t
+; RUN: grep pinsrd %t | count 2
+
+define <4 x i32> @var_insert2(<4 x i32> %x, i32 %val, i32 %idx) nounwind  {
+entry:
+	%tmp3 = insertelement <4 x i32> undef, i32 %val, i32 0		; <<4 x i32>> [#uses=1]
+	%tmp4 = insertelement <4 x i32> %tmp3, i32 %idx, i32 3		; <<4 x i32>> [#uses=1]
+	ret <4 x i32> %tmp4
+}

Removed: llvm/trunk/test/CodeGen/X86/vec_insert_4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_insert_4.ll?rev=99422&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_insert_4.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_insert_4.ll (removed)
@@ -1,11 +0,0 @@
-; RUN: llc < %s -march=x86 -mcpu=yonah | grep 1084227584 | count 1
-
-; ModuleID = '<stdin>'
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
-target triple = "i686-apple-darwin9.2.2"
-
-define <8 x float> @f(<8 x float> %a, i32 %b) nounwind  {
-entry:
-	%vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b		; <<4 x float>> [#uses=1]
-	ret <8 x float> %vecins
-}

Modified: llvm/trunk/test/CodeGen/X86/vec_set.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set.ll?rev=99423&r1=99422&r2=99423&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set.ll Wed Mar 24 15:49:50 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | grep punpckl | count 7
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep punpckl | count 7
 
 define void @test(<8 x i16>* %b, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind {
         %tmp = insertelement <8 x i16> zeroinitializer, i16 %a0, i32 0          ; <<8 x i16>> [#uses=1]

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle.ll?rev=99423&r1=99422&r2=99423&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle.ll Wed Mar 24 15:49:50 2010
@@ -1,5 +1,6 @@
 ; RUN: llc < %s -march=x86 -mcpu=core2 -o %t
-; RUN: grep shufp   %t | count 1
+; RUN: grep movq    %t | count 1
+; RUN: grep pshufd  %t | count 1
 ; RUN: grep movupd  %t | count 1
 ; RUN: grep pshufhw %t | count 1
 




From edwintorok at gmail.com  Wed Mar 24 15:58:48 2010
From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=)
Date: Wed, 24 Mar 2010 22:58:48 +0200
Subject: [llvm-commits] [llvm] r99400 - in /llvm/trunk:
 lib/CodeGen/LiveIntervalAnalysis.cpp
 test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
In-Reply-To: <2FB1B738-C12D-49DF-8678-79C0E20F46F4@apple.com>
References: <20100324135036.CB2412A6C12C@llvm.org>
	<2FB1B738-C12D-49DF-8678-79C0E20F46F4@apple.com>
Message-ID: <4BAA7D08.4090703@gmail.com>

On 03/24/2010 10:24 PM, Bob Wilson wrote:
> This breaks MultiSource/Applications/ClamAV/clamscan.

I didn't think that my attempt to fix a bug in ClamAV would introduce a
bug in compiling ClamAV :)

> I'm going to revert it for now.

OK.

Could you give me some more details on which configuration this breaks?
Did it happen when running the test-suite with llvm-gcc or clang?
Did llc crash, or did valgrind show an error?

If I apply my patch on top of llvm 2.7 I only get these unrelated
invalid reads from valgrind (when running test-suite with clang)

==6908== Memcheck, a memory error detector

==6908== Copyright (C) 2002-2009, and GNU GPL'd, by Julian Seward et al.

==6908== Using Valgrind-3.5.0-Debian and LibVEX; rerun with -h for
copyright info
==6908== Command: /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc
-asm-verbose=false -O3 Output/clamscan.llvm.bc -o Output/clamscan.llc.s
-info-output-file=/home/edwin/llvm2.7/llvm-2.7/projects/llvm-test/MultiSource/Applications/ClamAV/Output/clamscan.llc.s.info
-stats -time-passes

==6908==

==6908== Invalid read of size 1

==6908==    at 0x7A7A54: void
std::__insertion_sort<llvm::StringRef*>(llvm::StringRef*,
llvm::StringRef*) (in /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)


==6908==    by 0x79225B:
llvm::X86TargetLowering::ExpandInlineAsm(llvm::CallInst*) const (in
/home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)


==6908==    by 0xA8BABD: (anonymous
namespace)::CodeGenPrepare::runOnFunction(llvm::Function&) (in
/home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)


==6908==    by 0xBFDBB5:
llvm::FPPassManager::runOnFunction(llvm::Function&) (in
/home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
==6908==    by 0xBFDD90:
llvm::FunctionPassManagerImpl::run(llvm::Function&) (in
/home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
==6908==    by 0xBFDFBD: llvm::FunctionPassManager::run(llvm::Function&)
(in /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
==6908==    by 0x52A113: main (in
/home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)

==6908==  Address 0x7954db8 is 24 bytes inside a block of size 58 free'd

==6908==    at 0x4A06ACE: operator delete(void*)
(vg_replace_malloc.c:346)

==6908==    by 0x3CD5AA8948: std::basic_string<char,
std::char_traits<char>, std::allocator<char> >::~basic_string() (in
/usr/lib/libstdc++.so.6.0.13)

==6908==    by 0x79286A:
llvm::X86TargetLowering::ExpandInlineAsm(llvm::CallInst*) const (in
/home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)


==6908==    by 0xA8BABD: (anonymous
namespace)::CodeGenPrepare::runOnFunction(llvm::Function&) (in
/home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)


==6908==    by 0xBFDBB5:
llvm::FPPassManager::runOnFunction(llvm::Function&) (in
/home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
==6908==    by 0xBFDD90:
llvm::FunctionPassManagerImpl::run(llvm::Function&) (in
/home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
==6908==    by 0xBFDFBD: llvm::FunctionPassManager::run(llvm::Function&)
(in /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
==6908==    by 0x52A113: main (in
/home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)

==6908==

> 
> On Mar 24, 2010, at 6:50 AM, Torok Edwin wrote:
> 
>> Author: edwin
>> Date: Wed Mar 24 08:50:36 2010
>> New Revision: 99400
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=99400&view=rev
>> Log:
>> Fix memory leak in liveintervals: the destructor for VNInfos must be called,
>> otherwise the SmallVector it contains doesn't free its memory.
>> In most cases LiveIntervalAnalysis could get away by not calling the destructor,
>> because VNInfos are bumpptr-allocated, and smallvectors usually don't grow.
>> However when the SmallVector does grow it always leaks.


Best regards,
--Edwin



From bob.wilson at apple.com  Wed Mar 24 16:22:23 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 24 Mar 2010 14:22:23 -0700
Subject: [llvm-commits] [llvm] r99400 - in /llvm/trunk:
	lib/CodeGen/LiveIntervalAnalysis.cpp
	test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
In-Reply-To: <4BAA7D08.4090703@gmail.com>
References: <20100324135036.CB2412A6C12C@llvm.org>
	<2FB1B738-C12D-49DF-8678-79C0E20F46F4@apple.com>
	<4BAA7D08.4090703@gmail.com>
Message-ID: <D8277F81-B5D1-4DA5-85F1-4C6984274357@apple.com>

On Mar 24, 2010, at 1:58 PM, T?r?k Edwin wrote:

> On 03/24/2010 10:24 PM, Bob Wilson wrote:
> 
> Could you give me some more details on which configuration this breaks?
> Did it happen when running the test-suite with llvm-gcc or clang?
> Did llc crash, or did valgrind show an error?

I was afraid you were going to ask that....  Oh well, it's good for me to figure out how these things work!  I poked around on the buildbot and found the error.  llc crashed with the following:

llc(1164) malloc: *** error for object 0x1041219c0: pointer being freed was not allocated
*** set a breakpoint in malloc_error_break to debug
0  llc               0x00000001008fd932 PrintStackTrace(void*) + 34
1  llc               0x00000001008fe11e SignalHandler(int) + 622
2  libSystem.B.dylib 0x00007fff82898eaa _sigtramp + 26
3  libSystem.B.dylib 0x00007fff5fbfea98 _sigtramp + 3711327240
4  libSystem.B.dylib 0x00007fff8283f155 free + 128
5  llc               0x00000001005a1301 llvm::LiveIntervals::releaseMemory() + 161
6  llc               0x0000000100886635 llvm::PMDataManager::freePass(llvm::Pass*, llvm::StringRef, llvm::PassDebuggingString) + 117
7  llc               0x0000000100886bdc llvm::PMDataManager::removeDeadPasses(llvm::Pass*, llvm::StringRef, llvm::PassDebuggingString) + 172
8  llc               0x00000001008873c8 llvm::FPPassManager::runOnFunction(llvm::Function&) + 280
9  llc               0x00000001008876db llvm::FunctionPassManagerImpl::run(llvm::Function&) + 139
10 llc               0x0000000100887916 llvm::FunctionPassManager::run(llvm::Function&) + 102
11 llc               0x0000000100039d38 main + 3672
12 llc               0x00000001000385a8 start + 52
13 llc               0x0000000000000009 start + 4294736533

This was running with llvm-gcc.  I'd send you the bitcode file except that it has already been overwritten.  Is that good enough to help you figure it out?

> 
> If I apply my patch on top of llvm 2.7 I only get these unrelated
> invalid reads from valgrind (when running test-suite with clang)
> 
> ==6908== Memcheck, a memory error detector
> 
> ==6908== Copyright (C) 2002-2009, and GNU GPL'd, by Julian Seward et al.
> 
> ==6908== Using Valgrind-3.5.0-Debian and LibVEX; rerun with -h for
> copyright info
> ==6908== Command: /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc
> -asm-verbose=false -O3 Output/clamscan.llvm.bc -o Output/clamscan.llc.s
> -info-output-file=/home/edwin/llvm2.7/llvm-2.7/projects/llvm-test/MultiSource/Applications/ClamAV/Output/clamscan.llc.s.info
> -stats -time-passes
> 
> ==6908==
> 
> ==6908== Invalid read of size 1
> 
> ==6908==    at 0x7A7A54: void
> std::__insertion_sort<llvm::StringRef*>(llvm::StringRef*,
> llvm::StringRef*) (in /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
> 
> 
> ==6908==    by 0x79225B:
> llvm::X86TargetLowering::ExpandInlineAsm(llvm::CallInst*) const (in
> /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
> 
> 
> ==6908==    by 0xA8BABD: (anonymous
> namespace)::CodeGenPrepare::runOnFunction(llvm::Function&) (in
> /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
> 
> 
> ==6908==    by 0xBFDBB5:
> llvm::FPPassManager::runOnFunction(llvm::Function&) (in
> /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
> ==6908==    by 0xBFDD90:
> llvm::FunctionPassManagerImpl::run(llvm::Function&) (in
> /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
> ==6908==    by 0xBFDFBD: llvm::FunctionPassManager::run(llvm::Function&)
> (in /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
> ==6908==    by 0x52A113: main (in
> /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
> 
> ==6908==  Address 0x7954db8 is 24 bytes inside a block of size 58 free'd
> 
> ==6908==    at 0x4A06ACE: operator delete(void*)
> (vg_replace_malloc.c:346)
> 
> ==6908==    by 0x3CD5AA8948: std::basic_string<char,
> std::char_traits<char>, std::allocator<char> >::~basic_string() (in
> /usr/lib/libstdc++.so.6.0.13)
> 
> ==6908==    by 0x79286A:
> llvm::X86TargetLowering::ExpandInlineAsm(llvm::CallInst*) const (in
> /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
> 
> 
> ==6908==    by 0xA8BABD: (anonymous
> namespace)::CodeGenPrepare::runOnFunction(llvm::Function&) (in
> /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
> 
> 
> ==6908==    by 0xBFDBB5:
> llvm::FPPassManager::runOnFunction(llvm::Function&) (in
> /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
> ==6908==    by 0xBFDD90:
> llvm::FunctionPassManagerImpl::run(llvm::Function&) (in
> /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
> ==6908==    by 0xBFDFBD: llvm::FunctionPassManager::run(llvm::Function&)
> (in /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
> ==6908==    by 0x52A113: main (in
> /home/edwin/llvm2.7/llvm-2.7/Release/bin/llc)
> 
> ==6908==
> 
>> 
>> On Mar 24, 2010, at 6:50 AM, Torok Edwin wrote:
>> 
>>> Author: edwin
>>> Date: Wed Mar 24 08:50:36 2010
>>> New Revision: 99400
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=99400&view=rev
>>> Log:
>>> Fix memory leak in liveintervals: the destructor for VNInfos must be called,
>>> otherwise the SmallVector it contains doesn't free its memory.
>>> In most cases LiveIntervalAnalysis could get away by not calling the destructor,
>>> because VNInfos are bumpptr-allocated, and smallvectors usually don't grow.
>>> However when the SmallVector does grow it always leaks.
> 
> 
> Best regards,
> --Edwin
> 

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From johnny.chen at apple.com  Wed Mar 24 16:25:07 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Wed, 24 Mar 2010 21:25:07 -0000
Subject: [llvm-commits] [llvm] r99428 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20100324212507.817702A6C12C@llvm.org>

Author: johnny
Date: Wed Mar 24 16:25:07 2010
New Revision: 99428

URL: http://llvm.org/viewvc/llvm-project?rev=99428&view=rev
Log:
Trivial formating change.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99428&r1=99427&r2=99428&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Mar 24 16:25:07 2010
@@ -2282,8 +2282,8 @@
                         IIC_VBINi4Q, "vcge", "s", NEONvcge, 0>;
 defm VCGEu    : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 
                         IIC_VBINi4Q, "vcge", "u", NEONvcgeu, 0>;
-def  VCGEfd   : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32",
-                     v2i32, v2f32, NEONvcge, 0>;
+def  VCGEfd   : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
+                     NEONvcge, 0>;
 def  VCGEfq   : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
                      NEONvcge, 0>;
 // For disassembly only.




From dpatel at apple.com  Wed Mar 24 16:30:35 2010
From: dpatel at apple.com (Devang Patel)
Date: Wed, 24 Mar 2010 21:30:35 -0000
Subject: [llvm-commits] [llvm] r99429 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Message-ID: <20100324213035.E6D7F2A6C12C@llvm.org>

Author: dpatel
Date: Wed Mar 24 16:30:35 2010
New Revision: 99429

URL: http://llvm.org/viewvc/llvm-project?rev=99429&view=rev
Log:
Use SP filename directly instead of SP's context's filename.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=99429&r1=99428&r2=99429&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Mar 24 16:30:35 2010
@@ -447,8 +447,8 @@
   unsigned Line = SP->getLineNumber();
   if (!SP->getContext().Verify())
     return;
-  unsigned FileID = GetOrCreateSourceID(SP->getContext().getDirectory(),
-                                        SP->getContext().getFilename());
+  unsigned FileID = GetOrCreateSourceID(SP->getDirectory(),
+                                        SP->getFilename());
   assert(FileID && "Invalid file id");
   addUInt(Die, dwarf::DW_AT_decl_file, 0, FileID);
   addUInt(Die, dwarf::DW_AT_decl_line, 0, Line);




From baldrick at free.fr  Wed Mar 24 16:33:18 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 24 Mar 2010 21:33:18 -0000
Subject: [llvm-commits] [dragonegg] r99430 - in /dragonegg/trunk:
	llvm-convert.cpp llvm-internal.h
Message-ID: <20100324213319.05BE92A6C12C@llvm.org>

Author: baldrick
Date: Wed Mar 24 16:33:18 2010
New Revision: 99430

URL: http://llvm.org/viewvc/llvm-project?rev=99430&view=rev
Log:
Start implementing exception handling: implement BUILT_IN_EH_POINTER.

Modified:
    dragonegg/trunk/llvm-convert.cpp
    dragonegg/trunk/llvm-internal.h

Modified: dragonegg/trunk/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-convert.cpp?rev=99430&r1=99429&r2=99430&view=diff
==============================================================================
--- dragonegg/trunk/llvm-convert.cpp (original)
+++ dragonegg/trunk/llvm-convert.cpp Wed Mar 24 16:33:18 2010
@@ -256,8 +256,6 @@
 
   AllocaInsertionPoint = 0;
 
-  ExceptionValue = 0;
-  ExceptionSelectorValue = 0;
   FuncEHException = 0;
   FuncEHSelector = 0;
   FuncEHGetTypeID = 0;
@@ -1292,14 +1290,6 @@
     LV = EmitLV_VIEW_CONVERT_EXPR(exp);
     break;
 
-  // Exception Handling.
-//FIXME  case EXC_PTR_EXPR:
-//FIXME    LV = EmitLV_EXC_PTR_EXPR(exp);
-//FIXME    break;
-//FIXME  case FILTER_EXPR:
-//FIXME    LV = EmitLV_FILTER_EXPR(exp);
-//FIXME    break;
-
   // Trivial Cases.
   case WITH_SIZE_EXPR:
     LV = EmitLV_WITH_SIZE_EXPR(exp);
@@ -1849,15 +1839,7 @@
 /// CreateExceptionValues - Create values used internally by exception handling.
 void TreeToLLVM::CreateExceptionValues() {
   // Check to see if the exception values have been constructed.
-  if (ExceptionValue) return;
-
-  const Type *IntTy = ConvertType(integer_type_node);
-
-  ExceptionValue = CreateTemporary(Type::getInt8PtrTy(Context));
-  ExceptionValue->setName("eh_exception");
-
-  ExceptionSelectorValue = CreateTemporary(IntTy);
-  ExceptionSelectorValue->setName("eh_selector");
+  if (FuncEHException) return;
 
   FuncEHException = Intrinsic::getDeclaration(TheModule,
                                               Intrinsic::eh_exception);
@@ -1867,6 +1849,19 @@
                                               Intrinsic::eh_typeid_for);
 }
 
+/// getLandingPad - Return the landing pad for the given exception handling
+/// region, creating it if necessary.
+BasicBlock *TreeToLLVM::getLandingPad(unsigned RegionNo) {
+  LandingPads.grow(RegionNo);
+  BasicBlock *&LandingPad = LandingPads[RegionNo];
+
+  if (!LandingPad)
+    LandingPad = BasicBlock::Create(Context, "lpad");
+
+  return LandingPad;
+}
+
+
 /// getPostPad - Return the post landing pad for the given exception handling
 /// region, creating it if necessary.
 BasicBlock *TreeToLLVM::getPostPad(unsigned RegionNo) {
@@ -1879,6 +1874,20 @@
   return PostPad;
 }
 
+/// getExceptionPtr - Return the local holding the exception pointer for the
+/// given exception handling region, creating it if necessary.
+AllocaInst *TreeToLLVM::getExceptionPtr(unsigned RegionNo) {
+  ExceptionPtrs.grow(RegionNo);
+  AllocaInst *&ExceptionPtr = ExceptionPtrs[RegionNo];
+
+  if (!ExceptionPtr) {
+    ExceptionPtr = CreateTemporary(Type::getInt8PtrTy(Context));
+    ExceptionPtr->setName("exc_ptr");
+  }
+
+  return ExceptionPtr;
+}
+
 /// AddHandler - Append the given region to a vector of exception handlers.
 /// A callback passed to foreach_reachable_handler.
 //FIXMEstatic void AddHandler (eh_region region, void *data) {
@@ -1901,13 +1910,13 @@
     BeginBlock(LandingPad);
 
     // Fetch and store the exception.
-    Value *Ex = Builder.CreateCall(FuncEHException, "eh_ptr");
-    Builder.CreateStore(Ex, ExceptionValue);
+    Value *ExcPtr = Builder.CreateCall(FuncEHException, "exc_ptr");
+    Builder.CreateStore(ExcPtr, getExceptionPtr(i));
 
     // Fetch and store the exception selector.
 
     // The exception and the personality function.
-    Args.push_back(Builder.CreateLoad(ExceptionValue, "eh_ptr"));
+    Args.push_back(ExcPtr);
 abort();//FIXME
 //FIXME    assert(llvm_eh_personality_libfunc
 //FIXME           && "no exception handling personality function!");
@@ -2637,20 +2646,12 @@
 //FIXME    // Is the call contained in an exception handling region?
 //FIXME    if (RegionNo > 0) {
 //FIXME      // Are there any exception handlers for this region?
-//FIXME      if (can_throw_internal_1(RegionNo, false, false)) {
+//FIXME      if (can_throw_internal_1(RegionNo, false, false))
 //FIXME        // There are - turn the call into an invoke.
-//FIXME        LandingPads.grow(RegionNo);
-//FIXME        BasicBlock *&ThisPad = LandingPads[RegionNo];
-//FIXME
-//FIXME        // Create a landing pad if one didn't exist already.
-//FIXME        if (!ThisPad)
-//FIXME          ThisPad = BasicBlock::Create(Context, "lpad");
-//FIXME
-//FIXME        LandingPad = ThisPad;
-//FIXME      } else {
+//FIXME        LandingPad = getLandingPad(RegionNo);
+//FIXME      else
 //FIXME        assert(can_throw_external_1(RegionNo, false, false) &&
 //FIXME               "Must-not-throw region handled by runtime?");
-//FIXME      }
 //FIXME    }
   }
 
@@ -2824,23 +2825,6 @@
   return 0;
 }
 
-/// EmitEXC_PTR_EXPR - Handle EXC_PTR_EXPR.
-Value *TreeToLLVM::EmitEXC_PTR_EXPR(tree exp) {
-abort();
-//TODO  CreateExceptionValues();
-//TODO  // Load exception address.
-//TODO  Value *V = Builder.CreateLoad(ExceptionValue, "eh_value");
-//TODO  // Cast the address to the right pointer type.
-//TODO  return Builder.CreateBitCast(V, ConvertType(TREE_TYPE(exp)));
-}
-
-/// EmitFILTER_EXPR - Handle FILTER_EXPR.
-Value *TreeToLLVM::EmitFILTER_EXPR(tree exp) {
-abort();
-//FIXME  CreateExceptionValues();
-//FIXME  // Load exception selector.
-//FIXME  return Builder.CreateLoad(ExceptionSelectorValue, "eh_select");
-}
 
 //===----------------------------------------------------------------------===//
 //               ... Inline Assembly and Register Variables ...
@@ -3576,6 +3560,10 @@
   case BUILT_IN_INIT_TRAMPOLINE:
     return EmitBuiltinInitTrampoline(stmt, Result);
 
+  // Exception handling builtins.
+  case BUILT_IN_EH_POINTER:
+    return EmitBuiltinEHPointer(stmt, Result);
+
   // Builtins used by the exception handling runtime.
   case BUILT_IN_DWARF_CFA:
     return EmitBuiltinDwarfCFA(stmt, Result);
@@ -4742,6 +4730,21 @@
 }
 
 
+// Exception handling builtins.
+
+bool TreeToLLVM::EmitBuiltinEHPointer(gimple stmt, Value *&Result) {
+  // Lookup the local that holds the exception pointer for this region.
+  unsigned RegionNo = tree_low_cst(gimple_call_arg(stmt, 0), 0);
+  AllocaInst *ExcPtr = getExceptionPtr(RegionNo);
+  // Load the exception pointer out.
+  Result = Builder.CreateLoad(ExcPtr);
+  // Ensure the returned value has the right pointer type.
+  tree type = gimple_call_return_type(stmt);
+  Result = Builder.CreateBitCast(Result, ConvertType(type));
+  return true;
+}
+
+
 // Builtins used by the exception handling runtime.
 
 // On most machines, the CFA coincides with the first incoming parm.
@@ -5505,24 +5508,6 @@
   return LValue(Builder.CreateBitCast(Decl, PTy), Alignment);
 }
 
-LValue TreeToLLVM::EmitLV_EXC_PTR_EXPR(tree exp) {
-  CreateExceptionValues();
-  // Cast the address pointer to the expected type.
-  unsigned Alignment = TD.getABITypeAlignment(cast<PointerType>(ExceptionValue->
-                                                  getType())->getElementType());
-  return LValue(Builder.CreateBitCast(ExceptionValue,
-                           PointerType::getUnqual(ConvertType(TREE_TYPE(exp)))),
-                Alignment);
-}
-
-LValue TreeToLLVM::EmitLV_FILTER_EXPR(tree exp) {
-  CreateExceptionValues();
-  unsigned Alignment =
-    TD.getABITypeAlignment(cast<PointerType>(ExceptionSelectorValue->
-                                             getType())->getElementType());
-  return LValue(ExceptionSelectorValue, Alignment);
-}
-
 LValue TreeToLLVM::EmitLV_INDIRECT_REF(tree exp) {
   // The lvalue is just the address.
   LValue LV = LValue(EmitRegister(TREE_OPERAND(exp, 0)), expr_align(exp) / 8);

Modified: dragonegg/trunk/llvm-internal.h
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-internal.h?rev=99430&r1=99429&r2=99430&view=diff
==============================================================================
--- dragonegg/trunk/llvm-internal.h (original)
+++ dragonegg/trunk/llvm-internal.h Wed Mar 24 16:33:18 2010
@@ -430,12 +430,8 @@
   /// PostPads - The post landing pad for a given EH region.
   IndexedMap<BasicBlock *> PostPads;
 
-  /// ExceptionValue - Is the local to receive the current exception.
-  Value *ExceptionValue;
-
-  /// ExceptionSelectorValue - Is the local to receive the current exception
-  /// selector.
-  Value *ExceptionSelectorValue;
+  /// ExceptionPtrs - The local holding the exception pointer for a EH region.
+  IndexedMap<AllocaInst *> ExceptionPtrs;
 
   /// FuncEHException - Function used to receive the exception.
   Function *FuncEHException;
@@ -574,10 +570,18 @@
   /// handling.
   void CreateExceptionValues();
 
+  /// getLandingPad - Return the landing pad for the given exception handling
+  /// region, creating it if necessary.
+  BasicBlock *getLandingPad(unsigned RegionNo);
+
   /// getPostPad - Return the post landing pad for the given exception handling
   /// region, creating it if necessary.
   BasicBlock *getPostPad(unsigned RegionNo);
 
+  /// getExceptionPtr - Return the local holding the exception pointer for the
+  /// given exception handling region, creating it if necessary.
+  AllocaInst *getExceptionPtr(unsigned RegionNo);
+
 private:
   void EmitAutomaticVariableDecl(tree_node *decl);
 
@@ -695,10 +699,6 @@
                     const AttrListPtr &PAL);
   Value *EmitFieldAnnotation(Value *FieldPtr, tree_node *FieldDecl);
 
-  // Exception Handling.
-  Value *EmitEXC_PTR_EXPR(tree_node *exp);
-  Value *EmitFILTER_EXPR(tree_node *exp);
-
   // Inline Assembly and Register Variables.
   Value *EmitReadOfRegisterVariable(tree_node *vardecl);
   void EmitModifyOfRegisterVariable(tree_node *vardecl, Value *RHS);
@@ -739,6 +739,7 @@
   bool EmitBuiltinFrobReturnAddr(gimple stmt, Value *&Result);
   bool EmitBuiltinStackSave(gimple stmt, Value *&Result);
   bool EmitBuiltinStackRestore(gimple stmt);
+  bool EmitBuiltinEHPointer(gimple stmt, Value *&Result);
   bool EmitBuiltinDwarfCFA(gimple stmt, Value *&Result);
   bool EmitBuiltinDwarfSPColumn(gimple stmt, Value *&Result);
   bool EmitBuiltinEHReturnDataRegno(gimple stmt, Value *&Result);
@@ -758,8 +759,6 @@
   LValue EmitLV_BIT_FIELD_REF(tree_node *exp);
   LValue EmitLV_COMPONENT_REF(tree_node *exp);
   LValue EmitLV_DECL(tree_node *exp);
-  LValue EmitLV_EXC_PTR_EXPR(tree_node *exp);
-  LValue EmitLV_FILTER_EXPR(tree_node *exp);
   LValue EmitLV_INDIRECT_REF(tree_node *exp);
   LValue EmitLV_VIEW_CONVERT_EXPR(tree_node *exp);
   LValue EmitLV_WITH_SIZE_EXPR(tree_node *exp);




From ggreif at gmail.com  Wed Mar 24 16:34:47 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 24 Mar 2010 21:34:47 -0000
Subject: [llvm-commits] [test-suite] r99432 -
	/test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile
Message-ID: <20100324213447.7B8CA2A6C12C@llvm.org>

Author: ggreif
Date: Wed Mar 24 16:34:47 2010
New Revision: 99432

URL: http://llvm.org/viewvc/llvm-project?rev=99432&view=rev
Log:
fix out-of-tree build (modelled after MultiSource/Applications/lemon)

Modified:
    test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile

Modified: test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile?rev=99432&r1=99431&r2=99432&view=diff
==============================================================================
--- test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile (original)
+++ test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile Wed Mar 24 16:34:47 2010
@@ -4,8 +4,8 @@
 CPPFLAGS += -DNOASM -DLLVM
 LDFLAGS = -lstdc++ -lm
 ifdef SMALL_PROBLEM_SIZE
-RUN_OPTIONS = -1 file1.in
+RUN_OPTIONS = -1 $(PROJ_SRC_DIR)/file1.in
 else
-RUN_OPTIONS = -4 file1.in
+RUN_OPTIONS = -4 $(PROJ_SRC_DIR)/file1.in
 endif
 include $(LEVEL)/MultiSource/Makefile.multisrc




From edwintorok at gmail.com  Wed Mar 24 17:00:44 2010
From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=)
Date: Thu, 25 Mar 2010 00:00:44 +0200
Subject: [llvm-commits] [llvm] r99400 - in /llvm/trunk:
 lib/CodeGen/LiveIntervalAnalysis.cpp
 test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
In-Reply-To: <D8277F81-B5D1-4DA5-85F1-4C6984274357@apple.com>
References: <20100324135036.CB2412A6C12C@llvm.org>
	<2FB1B738-C12D-49DF-8678-79C0E20F46F4@apple.com>
	<4BAA7D08.4090703@gmail.com>
	<D8277F81-B5D1-4DA5-85F1-4C6984274357@apple.com>
Message-ID: <4BAA8B8C.4070300@gmail.com>

On 03/24/2010 11:22 PM, Bob Wilson wrote:
> On Mar 24, 2010, at 1:58 PM, T?r?k Edwin wrote:
> 
>> On 03/24/2010 10:24 PM, Bob Wilson wrote:
>>
>> Could you give me some more details on which configuration this breaks?
>> Did it happen when running the test-suite with llvm-gcc or clang?
>> Did llc crash, or did valgrind show an error?
> 
> I was afraid you were going to ask that....  Oh well, it's good for me
> to figure out how these things work!  I poked around on the buildbot and
> found the error. 

Thanks!
BTW why didn't the buildbot email me? :)

> llc crashed with the following:
> 
> llc(1164) malloc: *** error for object 0x1041219c0: pointer being freed
> was not allocated
> *** set a breakpoint in malloc_error_break to debug
> 0  llc               0x00000001008fd932 PrintStackTrace(void*) + 34
> 1  llc               0x00000001008fe11e SignalHandler(int) + 622
> 2  libSystem.B.dylib 0x00007fff82898eaa _sigtramp + 26
> 3  libSystem.B.dylib 0x00007fff5fbfea98 _sigtramp + 3711327240
> 4  libSystem.B.dylib 0x00007fff8283f155 free + 128
> 5  llc               0x00000001005a1301
> llvm::LiveIntervals::releaseMemory() + 161

Ok that obviously matches what my patch did.

> 6  llc               0x0000000100886635
> llvm::PMDataManager::freePass(llvm::Pass*, llvm::StringRef,
> llvm::PassDebuggingString) + 117
> 7  llc               0x0000000100886bdc
> llvm::PMDataManager::removeDeadPasses(llvm::Pass*, llvm::StringRef,
> llvm::PassDebuggingString) + 172
> 8  llc               0x00000001008873c8
> llvm::FPPassManager::runOnFunction(llvm::Function&) + 280
> 9  llc               0x00000001008876db
> llvm::FunctionPassManagerImpl::run(llvm::Function&) + 139
> 10 llc               0x0000000100887916
> llvm::FunctionPassManager::run(llvm::Function&) + 102
> 11 llc               0x0000000100039d38 main + 3672
> 12 llc               0x00000001000385a8 start + 52
> 13 llc               0x0000000000000009 start + 4294736533
> 
> This was running with llvm-gcc.

I'll see if I can reproduce it tomorrow. Can you also tell me exactly
what revision the buildbot has built? (was it exactly mine or something
a bit later?)

>  I'd send you the bitcode file except
> that it has already been overwritten.  Is that good enough to help you
> figure it out?

Hope so, if I can't reproduce I'll let you know.

Best regards,
--Edwin


From natebegeman at mac.com  Wed Mar 24 17:19:06 2010
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 24 Mar 2010 22:19:06 -0000
Subject: [llvm-commits] [llvm] r99434 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20100324221907.27B602A6C12C@llvm.org>

Author: sampo
Date: Wed Mar 24 17:19:06 2010
New Revision: 99434

URL: http://llvm.org/viewvc/llvm-project?rev=99434&view=rev
Log:
Per chris's request, add some comments.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=99434&r1=99433&r2=99434&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Mar 24 17:19:06 2010
@@ -3613,14 +3613,26 @@
   return SDValue();
 }
 
+/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 
+/// vector of type 'VT', see if the elements can be replaced by a single large 
+/// load which has the same value as a build_vector whose operands are 'elts'.
+///
+/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
+/// 
+/// FIXME: we'd also like to handle the case where the last elements are zero
+/// rather than undef via VZEXT_LOAD, but we do not detect that case today.
+/// There's even a handy isZeroNode for that purpose.
 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
                                         DebugLoc &dl, SelectionDAG &DAG) {
   EVT EltVT = VT.getVectorElementType();
   unsigned NumElems = Elts.size();
   
-  // FIXME: check for zeroes
   LoadSDNode *LDBase = NULL;
   unsigned LastLoadedElt = -1U;
+  
+  // For each element in the initializer, see if we've found a load or an undef.
+  // If we don't find an initial load element, or later load elements are 
+  // non-consecutive, bail out.
   for (unsigned i = 0; i < NumElems; ++i) {
     SDValue Elt = Elts[i];
     
@@ -3642,7 +3654,10 @@
       return SDValue();
     LastLoadedElt = i;
   }
-                                       
+
+  // If we have found an entire vector of loads and undefs, then return a large
+  // load of the entire vector width starting at the base pointer.  If we found
+  // consecutive loads for the low half, generate a vzext_load node.
   if (LastLoadedElt == NumElems - 1) {
     if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
       return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),




From bob.wilson at apple.com  Wed Mar 24 17:23:26 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 24 Mar 2010 15:23:26 -0700
Subject: [llvm-commits] [llvm] r99400 - in /llvm/trunk:
	lib/CodeGen/LiveIntervalAnalysis.cpp
	test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
In-Reply-To: <4BAA8B8C.4070300@gmail.com>
References: <20100324135036.CB2412A6C12C@llvm.org>
	<2FB1B738-C12D-49DF-8678-79C0E20F46F4@apple.com>
	<4BAA7D08.4090703@gmail.com>
	<D8277F81-B5D1-4DA5-85F1-4C6984274357@apple.com>
	<4BAA8B8C.4070300@gmail.com>
Message-ID: <AD3BD336-7ED4-4CFA-943C-D2DE9683BAC5@apple.com>


On Mar 24, 2010, at 3:00 PM, T?r?k Edwin wrote:
> 
> I'll see if I can reproduce it tomorrow. Can you also tell me exactly
> what revision the buildbot has built? (was it exactly mine or something
> a bit later?)

It was exactly your change.  99400.
-------------- next part --------------
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From enderby at apple.com  Wed Mar 24 17:28:42 2010
From: enderby at apple.com (Kevin Enderby)
Date: Wed, 24 Mar 2010 22:28:42 -0000
Subject: [llvm-commits] [llvm] r99435 - in /llvm/trunk:
 lib/Target/X86/X86InstrFormats.td test/MC/AsmParser/X86/x86_32-encoding.s
Message-ID: <20100324222842.DC0422A6C12C@llvm.org>

Author: enderby
Date: Wed Mar 24 17:28:42 2010
New Revision: 99435

URL: http://llvm.org/viewvc/llvm-project?rev=99435&view=rev
Log:
Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it does
not get an "Unknown immediate size" assert failure when used.  All instructions 
of this form have an 8-bit immediate.  Also added a test case of an example
instruction that is of this form.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrFormats.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=99435&r1=99434&r2=99435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Wed Mar 24 17:28:42 2010
@@ -286,7 +286,7 @@
 //   SS42AI = SSE 4.2 instructions with TA prefix
 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
              list<dag> pattern>
-      : I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE42]>;
+      : Ii8<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE42]>;
 
 // X86-64 Instruction templates...
 //

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=99435&r1=99434&r2=99435&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Wed Mar 24 17:28:42 2010
@@ -9905,3 +9905,11 @@
 // CHECK: crc32l 	%ecx, %ecx
 // CHECK:  encoding: [0xf2,0x0f,0x38,0xf1,0xc9]
                 crc32l %ecx,%ecx
+
+// CHECK: pcmpistrm	$125, %xmm1, %xmm2
+// CHECK:  encoding: [0x66,0x0f,0x3a,0x62,0xd1,0x7d]
+                pcmpistrm $125, %xmm1, %xmm2
+
+// CHECK: pcmpistrm	$125, (%edx,%eax,4), %xmm2
+// CHECK:  encoding: [0x66,0x0f,0x3a,0x62,0x14,0x82,0x7d]
+                pcmpistrm $125, (%edx,%eax,4), %xmm2




From echristo at apple.com  Wed Mar 24 17:31:29 2010
From: echristo at apple.com (Eric Christopher)
Date: Wed, 24 Mar 2010 15:31:29 -0700
Subject: [llvm-commits] [llvm] r99435 - in /llvm/trunk:
	lib/Target/X86/X86InstrFormats.td
	test/MC/AsmParser/X86/x86_32-encoding.s
In-Reply-To: <20100324222842.DC0422A6C12C@llvm.org>
References: <20100324222842.DC0422A6C12C@llvm.org>
Message-ID: <78B2BD13-75BF-4799-B5F4-12DED8F79E37@apple.com>


On Mar 24, 2010, at 3:28 PM, Kevin Enderby wrote:

> Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it does
> not get an "Unknown immediate size" assert failure when used.  All instructions 
> of this form have an 8-bit immediate.  Also added a test case of an example
> instruction that is of this form.

Thanks Kevin!

-eric


From grosbach at apple.com  Wed Mar 24 17:31:46 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 24 Mar 2010 22:31:46 -0000
Subject: [llvm-commits] [llvm] r99436 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrInfo.td ARMInstrVFP.td ARMSubtarget.cpp
 ARMSubtarget.h
Message-ID: <20100324223146.6B1C42A6C12C@llvm.org>

Author: grosbach
Date: Wed Mar 24 17:31:46 2010
New Revision: 99436

URL: http://llvm.org/viewvc/llvm-project?rev=99436&view=rev
Log:
Make the use of the vmla and vmls VFP instructions controllable via cmd line.
Preliminary testing shows significant performance wins by not using these
instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
    llvm/trunk/lib/Target/ARM/ARMSubtarget.h

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99436&r1=99435&r2=99436&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Mar 24 17:31:46 2010
@@ -1369,6 +1369,20 @@
   let Inst{4} = op4;
 }
 
+// Double precision, binary, VML[AS] (for additional predicate)
+class ADbI_vmlX<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
+           dag iops, InstrItinClass itin, string opc, string asm,
+           list<dag> pattern>
+  : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
+  let Inst{27-23} = opcod1;
+  let Inst{21-20} = opcod2;
+  let Inst{11-8}  = 0b1011;
+  let Inst{6} = op6;
+  let Inst{4} = op4;
+  list<Predicate> Predicates = [HasVFP2, UseVMLx];
+}
+
+
 // Single precision, unary
 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
            bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=99436&r1=99435&r2=99436&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Mar 24 17:31:46 2010
@@ -140,6 +140,8 @@
 def UseMovt   : Predicate<"Subtarget->useMovt()">;
 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
 
+def UseVMLx   : Predicate<"Subtarget->useVMLx()">;
+
 //===----------------------------------------------------------------------===//
 // ARM Flag Definitions.
 

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=99436&r1=99435&r2=99436&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Wed Mar 24 17:31:46 2010
@@ -545,7 +545,7 @@
 // FP FMA Operations.
 //
 
-def VMLAD : ADbI<0b11100, 0b00, 0, 0,
+def VMLAD : ADbI_vmlX<0b11100, 0b00, 0, 0,
                 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
                 IIC_fpMAC64, "vmla", ".f64\t$dst, $a, $b",
                 [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b),
@@ -558,7 +558,7 @@
                  [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
                  RegConstraint<"$dstin = $dst">;
 
-def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
+def VNMLSD : ADbI_vmlX<0b11100, 0b01, 0, 0,
                 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
                 IIC_fpMAC64, "vnmls", ".f64\t$dst, $a, $b",
                 [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b),
@@ -571,7 +571,7 @@
                 [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
                 RegConstraint<"$dstin = $dst">;
 
-def VMLSD : ADbI<0b11100, 0b00, 1, 0,
+def VMLSD : ADbI_vmlX<0b11100, 0b00, 1, 0,
                  (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
                  IIC_fpMAC64, "vmls", ".f64\t$dst, $a, $b",
              [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)),
@@ -589,7 +589,7 @@
 def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
           (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
 
-def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
+def VNMLAD : ADbI_vmlX<0b11100, 0b01, 1, 0,
                  (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
                  IIC_fpMAC64, "vnmla", ".f64\t$dst, $a, $b",
              [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)),

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=99436&r1=99435&r2=99436&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Mar 24 17:31:46 2010
@@ -26,6 +26,10 @@
 UseNEONFP("arm-use-neon-fp",
           cl::desc("Use NEON for single-precision FP"),
           cl::init(false), cl::Hidden);
+static cl::opt<bool>
+UseVMLxInstructions("arm-use-vmlx",
+                    cl::desc("Use VFP vmla and vmls instructions"),
+                    cl::init(true), cl::Hidden);
 
 static cl::opt<bool>
 UseMOVT("arm-use-movt",
@@ -36,6 +40,7 @@
   : ARMArchVersion(V4)
   , ARMFPUType(None)
   , UseNEONForSinglePrecisionFP(UseNEONFP)
+  , UseVMLx(UseVMLxInstructions)
   , IsThumb(isT)
   , ThumbMode(Thumb1)
   , PostRAScheduler(false)

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=99436&r1=99435&r2=99436&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Mar 24 17:31:46 2010
@@ -50,6 +50,10 @@
   /// determine if NEON should actually be used.
   bool UseNEONForSinglePrecisionFP;
 
+  /// UseVMLx - If the VFP2 instructions are available, indicates whether
+  /// the VML[AS] instructions should be used.
+  bool UseVMLx;
+
   /// IsThumb - True if we are in thumb mode, false if in ARM mode.
   bool IsThumb;
 
@@ -119,6 +123,7 @@
   bool hasNEON() const { return ARMFPUType >= NEON;  }
   bool useNEONForSinglePrecisionFP() const {
     return hasNEON() && UseNEONForSinglePrecisionFP; }
+  bool useVMLx() const {return hasVFP2() && UseVMLx; }
 
   bool hasFP16() const { return HasFP16; }
 




From grosbach at apple.com  Wed Mar 24 17:32:19 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 24 Mar 2010 22:32:19 -0000
Subject: [llvm-commits] [test-suite] r99437 -
	/test-suite/trunk/Makefile.programs
Message-ID: <20100324223219.397452A6C12C@llvm.org>

Author: grosbach
Date: Wed Mar 24 17:32:19 2010
New Revision: 99437

URL: http://llvm.org/viewvc/llvm-project?rev=99437&view=rev
Log:
test ARM vmla/vmls performance

Modified:
    test-suite/trunk/Makefile.programs

Modified: test-suite/trunk/Makefile.programs
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=99437&r1=99436&r2=99437&view=diff
==============================================================================
--- test-suite/trunk/Makefile.programs (original)
+++ test-suite/trunk/Makefile.programs Wed Mar 24 17:32:19 2010
@@ -241,10 +241,10 @@
 LLCBETAOPTION := -enable-sparc-v9-insts
 endif
 ifeq ($(ARCH),ARM)
-LLCBETAOPTION :=
+LLCBETAOPTION := -arm-use-vmlx=false
 endif
 ifeq ($(ARCH),THUMB)
-LLCBETAOPTION :=
+LLCBETAOPTION := -arm-use-vmlx=false
 endif
 
 print-llcbeta-option:




From enderby at apple.com  Wed Mar 24 17:33:33 2010
From: enderby at apple.com (Kevin Enderby)
Date: Wed, 24 Mar 2010 22:33:33 -0000
Subject: [llvm-commits] [llvm] r99440 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGNodes.h include/llvm/IntrinsicsX86.td
 lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrSSE.td
 test/MC/AsmParser/X86/x86_32-bit_cat.s
 test/MC/AsmParser/X86/x86_32-encoding.s
Message-ID: <20100324223334.21E052A6C12C@llvm.org>

Author: enderby
Date: Wed Mar 24 17:33:33 2010
New Revision: 99440

URL: http://llvm.org/viewvc/llvm-project?rev=99440&view=rev
Log:
Added the Advanced Encryption Standard (AES) Instructions.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/include/llvm/IntrinsicsX86.td
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=99440&r1=99439&r2=99440&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Mar 24 17:33:33 2010
@@ -616,7 +616,7 @@
   /// which do not reference a specific memory location should be less than
   /// this value. Those that do must not be less than this value, and can
   /// be used with SelectionDAG::getMemIntrinsicNode.
-  static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+80;
+  static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+85;
 
   /// Node predicates
 

Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=99440&r1=99439&r2=99440&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsX86.td Wed Mar 24 17:33:33 2010
@@ -779,6 +779,25 @@
                         [IntrNoMem, Commutative]>;
 }
 
+// Advanced Encryption Standard (AES) Instructions
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_sse42_aesimc          :
+              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
+                        [IntrNoMem]>;
+  def int_x86_sse42_aesenc          :
+              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
+                        [IntrNoMem]>;
+  def int_x86_sse42_aesenclast      :
+              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
+                        [IntrNoMem]>;
+  def int_x86_sse42_aesdec          :
+              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
+                        [IntrNoMem]>;
+  def int_x86_sse42_aesdeclast      :
+              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
+                        [IntrNoMem]>;
+}
+
 // Vector pack
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse41_packusdw        : GCCBuiltin<"__builtin_ia32_packusdw128">,

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=99440&r1=99439&r2=99440&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Mar 24 17:33:33 2010
@@ -234,6 +234,9 @@
       PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
       PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
 
+      // Advanced Encryption Standard (AES) Instructions
+      AESIMC, AESENC, AESENCLAST, AESDEC, AESDECLAST,
+
       // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
       ADD, SUB, SMUL, UMUL,
       INC, DEC, OR, XOR, AND,

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=99440&r1=99439&r2=99440&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Mar 24 17:33:33 2010
@@ -69,6 +69,12 @@
 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
 
+def X86aesimc          : SDNode<"X86ISD::AESIMC",          SDTIntBinOp>;
+def X86aesenc          : SDNode<"X86ISD::AESENC",          SDTIntBinOp>;
+def X86aesenclast      : SDNode<"X86ISD::AESENCLAST",      SDTIntBinOp>;
+def X86aesdec          : SDNode<"X86ISD::AESDEC",          SDTIntBinOp>;
+def X86aesdeclast      : SDNode<"X86ISD::AESDECLAST",      SDTIntBinOp>;
+
 def SDTX86CmpPTest : SDTypeProfile<0, 2, [SDTCisVT<0, v4f32>,
                                           SDTCisVT<1, v4f32>]>;
 def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
@@ -3817,6 +3823,45 @@
 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
           (PCMPGTQrm VR128:$src1, addr:$src2)>;
 
+defm AESIMC          : SS42I_binop_rm_int<0xDB, "aesimc",
+                       int_x86_sse42_aesimc>;
+defm AESENC          : SS42I_binop_rm_int<0xDC, "aesenc",
+                       int_x86_sse42_aesenc>;
+defm AESENCLAST      : SS42I_binop_rm_int<0xDD, "aesenclast",
+                       int_x86_sse42_aesenclast>;
+defm AESDEC          : SS42I_binop_rm_int<0xDE, "aesdec",
+                       int_x86_sse42_aesdec>;
+defm AESDECLAST      : SS42I_binop_rm_int<0xDF, "aesdeclast",
+                       int_x86_sse42_aesdeclast>;
+
+def : Pat<(v2i64 (X86aesimc VR128:$src1, VR128:$src2)),
+          (AESIMCrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v2i64 (X86aesimc VR128:$src1, (memop addr:$src2))),
+          (AESIMCrm VR128:$src1, addr:$src2)>;
+def : Pat<(v2i64 (X86aesenc VR128:$src1, VR128:$src2)),
+          (AESENCrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v2i64 (X86aesenc VR128:$src1, (memop addr:$src2))),
+          (AESENCrm VR128:$src1, addr:$src2)>;
+def : Pat<(v2i64 (X86aesenclast VR128:$src1, VR128:$src2)),
+          (AESENCLASTrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v2i64 (X86aesenclast VR128:$src1, (memop addr:$src2))),
+          (AESENCLASTrm VR128:$src1, addr:$src2)>;
+def : Pat<(v2i64 (X86aesdec VR128:$src1, VR128:$src2)),
+          (AESDECrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v2i64 (X86aesdec VR128:$src1, (memop addr:$src2))),
+          (AESDECrm VR128:$src1, addr:$src2)>;
+def : Pat<(v2i64 (X86aesdeclast VR128:$src1, VR128:$src2)),
+          (AESDECLASTrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v2i64 (X86aesdeclast VR128:$src1, (memop addr:$src2))),
+          (AESDECLASTrm VR128:$src1, addr:$src2)>;
+
+def AESKEYGENASSIST128rr : SS42AI<0xDF, MRMSrcReg, (outs),
+  (ins VR128:$src1, VR128:$src2, i8imm:$src3),
+  "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
+def AESKEYGENASSIST128rm : SS42AI<0xDF, MRMSrcMem, (outs),
+  (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
+  "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
+
 // crc intrinsic instruction
 // This set of instructions are only rm, the only difference is the size
 // of r and m.

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s?rev=99440&r1=99439&r2=99440&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s Wed Mar 24 17:33:33 2010
@@ -7806,3 +7806,39 @@
 
 // CHECK: 	pcmpgtq	%xmm5, %xmm5
         	pcmpgtq	%xmm5,%xmm5
+
+// CHECK: 	aesimc	%xmm0, %xmm1
+                aesimc %xmm0,%xmm1
+
+// CHECK: 	aesimc	(%eax), %xmm1
+                aesimc (%eax),%xmm1
+
+// CHECK: 	aesenc	%xmm1, %xmm2
+                aesenc %xmm1,%xmm2
+
+// CHECK: 	aesenc	4(%ebx), %xmm2
+                aesenc 4(%ebx),%xmm2
+
+// CHECK: 	aesenclast	%xmm3, %xmm4
+                aesenclast %xmm3,%xmm4
+
+// CHECK: 	aesenclast	4(%edx,%edi), %xmm4
+                aesenclast 4(%edx,%edi),%xmm4
+
+// CHECK: 	aesdec	%xmm5, %xmm6
+                aesdec %xmm5,%xmm6
+
+// CHECK: 	aesdec	4(%ecx,%eax,8), %xmm6
+                aesdec 4(%ecx,%eax,8),%xmm6
+
+// CHECK: 	aesdeclast	%xmm7, %xmm0
+                aesdeclast %xmm7,%xmm0
+
+// CHECK: 	aesdeclast	3405691582, %xmm0
+                aesdeclast 0xcafebabe,%xmm0
+
+// CHECK: 	aeskeygenassist	$125, %xmm1, %xmm2
+                aeskeygenassist $125, %xmm1, %xmm2
+
+// CHECK: 	aeskeygenassist	$125, (%edx,%eax,4), %xmm2
+                aeskeygenassist $125, (%edx,%eax,4), %xmm2

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=99440&r1=99439&r2=99440&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Wed Mar 24 17:33:33 2010
@@ -9913,3 +9913,51 @@
 // CHECK: pcmpistrm	$125, (%edx,%eax,4), %xmm2
 // CHECK:  encoding: [0x66,0x0f,0x3a,0x62,0x14,0x82,0x7d]
                 pcmpistrm $125, (%edx,%eax,4), %xmm2
+
+// CHECK: aesimc	%xmm0, %xmm1
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdb,0xc8]
+                aesimc %xmm0,%xmm1
+
+// CHECK: aesimc	(%eax), %xmm1
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdb,0x08]
+                aesimc (%eax),%xmm1
+
+// CHECK: aesenc	%xmm1, %xmm2
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdc,0xd1]
+                aesenc %xmm1,%xmm2
+
+// CHECK: aesenc	4(%ebx), %xmm2
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdc,0x53,0x04]
+                aesenc 4(%ebx),%xmm2
+
+// CHECK: aesenclast	%xmm3, %xmm4
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdd,0xe3]
+                aesenclast %xmm3,%xmm4
+
+// CHECK: aesenclast	4(%edx,%edi), %xmm4
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdd,0x64,0x3a,0x04]
+                aesenclast 4(%edx,%edi),%xmm4
+
+// CHECK: aesdec	%xmm5, %xmm6
+// CHECK:  encoding: [0x66,0x0f,0x38,0xde,0xf5]
+                aesdec %xmm5,%xmm6
+
+// CHECK: aesdec	4(%ecx,%eax,8), %xmm6
+// CHECK:  encoding: [0x66,0x0f,0x38,0xde,0x74,0xc1,0x04]
+                aesdec 4(%ecx,%eax,8),%xmm6
+
+// CHECK: aesdeclast	%xmm7, %xmm0
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdf,0xc7]
+                aesdeclast %xmm7,%xmm0
+
+// CHECK: aesdeclast	3405691582, %xmm0
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdf,0x05,0xbe,0xba,0xfe,0xca]
+                aesdeclast 0xcafebabe,%xmm0
+
+// CHECK: aeskeygenassist	$125, %xmm1, %xmm2
+// CHECK:  encoding: [0x66,0x0f,0x3a,0xdf,0xd1,0x7d]
+                aeskeygenassist $125, %xmm1, %xmm2
+
+// CHECK: aeskeygenassist	$125, (%edx,%eax,4), %xmm2
+// CHECK:  encoding: [0x66,0x0f,0x3a,0xdf,0x14,0x82,0x7d]
+                aeskeygenassist $125, (%edx,%eax,4), %xmm2




From sabre at nondot.org  Wed Mar 24 17:45:47 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 22:45:47 -0000
Subject: [llvm-commits] [llvm] r99444 - in
 /llvm/trunk/lib/CodeGen/SelectionDAG: InstrEmitter.cpp InstrEmitter.h
Message-ID: <20100324224547.77A842A6C12C@llvm.org>

Author: lattner
Date: Wed Mar 24 17:45:47 2010
New Revision: 99444

URL: http://llvm.org/viewvc/llvm-project?rev=99444&view=rev
Log:
split EmitNode in half to reduce indentation.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=99444&r1=99443&r2=99444&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Wed Mar 24 17:45:47 2010
@@ -569,93 +569,99 @@
   MBB->insert(InsertPos, MI);
 }
 
-/// EmitNode - Generate machine code for a node and needed dependencies.
+/// EmitMachineNode - Generate machine code for a target-specific node and
+/// needed dependencies.
 ///
-void InstrEmitter::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
-                            DenseMap<SDValue, unsigned> &VRBaseMap,
-                         DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
-  // If machine instruction
-  if (Node->isMachineOpcode()) {
-    unsigned Opc = Node->getMachineOpcode();
-    
-    // Handle subreg insert/extract specially
-    if (Opc == TargetOpcode::EXTRACT_SUBREG || 
-        Opc == TargetOpcode::INSERT_SUBREG ||
-        Opc == TargetOpcode::SUBREG_TO_REG) {
-      EmitSubregNode(Node, VRBaseMap);
-      return;
-    }
+void InstrEmitter::
+EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
+                DenseMap<SDValue, unsigned> &VRBaseMap,
+                DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
+  unsigned Opc = Node->getMachineOpcode();
+  
+  // Handle subreg insert/extract specially
+  if (Opc == TargetOpcode::EXTRACT_SUBREG || 
+      Opc == TargetOpcode::INSERT_SUBREG ||
+      Opc == TargetOpcode::SUBREG_TO_REG) {
+    EmitSubregNode(Node, VRBaseMap);
+    return;
+  }
 
-    // Handle COPY_TO_REGCLASS specially.
-    if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
-      EmitCopyToRegClassNode(Node, VRBaseMap);
-      return;
-    }
+  // Handle COPY_TO_REGCLASS specially.
+  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
+    EmitCopyToRegClassNode(Node, VRBaseMap);
+    return;
+  }
 
-    if (Opc == TargetOpcode::IMPLICIT_DEF)
-      // We want a unique VR for each IMPLICIT_DEF use.
-      return;
-    
-    const TargetInstrDesc &II = TII->get(Opc);
-    unsigned NumResults = CountResults(Node);
-    unsigned NodeOperands = CountOperands(Node);
-    bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
-                          II.getImplicitDefs() != 0;
+  if (Opc == TargetOpcode::IMPLICIT_DEF)
+    // We want a unique VR for each IMPLICIT_DEF use.
+    return;
+  
+  const TargetInstrDesc &II = TII->get(Opc);
+  unsigned NumResults = CountResults(Node);
+  unsigned NodeOperands = CountOperands(Node);
+  bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
+                        II.getImplicitDefs() != 0;
 #ifndef NDEBUG
-    unsigned NumMIOperands = NodeOperands + NumResults;
-    assert((II.getNumOperands() == NumMIOperands ||
-            HasPhysRegOuts || II.isVariadic()) &&
-           "#operands for dag node doesn't match .td file!"); 
+  unsigned NumMIOperands = NodeOperands + NumResults;
+  assert((II.getNumOperands() == NumMIOperands ||
+          HasPhysRegOuts || II.isVariadic()) &&
+         "#operands for dag node doesn't match .td file!"); 
 #endif
 
-    // Create the new machine instruction.
-    MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
-    
-    // Add result register values for things that are defined by this
-    // instruction.
-    if (NumResults)
-      CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
-    
-    // Emit all of the actual operands of this instruction, adding them to the
-    // instruction as appropriate.
-    bool HasOptPRefs = II.getNumDefs() > NumResults;
-    assert((!HasOptPRefs || !HasPhysRegOuts) &&
-           "Unable to cope with optional defs and phys regs defs!");
-    unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
-    for (unsigned i = NumSkip; i != NodeOperands; ++i)
-      AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
-                 VRBaseMap);
-
-    // Transfer all of the memory reference descriptions of this instruction.
-    MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
-                   cast<MachineSDNode>(Node)->memoperands_end());
-
-    if (II.usesCustomInsertionHook()) {
-      // Insert this instruction into the basic block using a target
-      // specific inserter which may returns a new basic block.
-      MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
-      InsertPos = MBB->end();
-    } else {
-      MBB->insert(InsertPos, MI);
-    }
+  // Create the new machine instruction.
+  MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
+  
+  // Add result register values for things that are defined by this
+  // instruction.
+  if (NumResults)
+    CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
+  
+  // Emit all of the actual operands of this instruction, adding them to the
+  // instruction as appropriate.
+  bool HasOptPRefs = II.getNumDefs() > NumResults;
+  assert((!HasOptPRefs || !HasPhysRegOuts) &&
+         "Unable to cope with optional defs and phys regs defs!");
+  unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
+  for (unsigned i = NumSkip; i != NodeOperands; ++i)
+    AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
+               VRBaseMap);
+
+  // Transfer all of the memory reference descriptions of this instruction.
+  MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
+                 cast<MachineSDNode>(Node)->memoperands_end());
+
+  if (II.usesCustomInsertionHook()) {
+    // Insert this instruction into the basic block using a target
+    // specific inserter which may returns a new basic block.
+    MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
+    InsertPos = MBB->end();
+  } else {
+    MBB->insert(InsertPos, MI);
+  }
 
-    // Additional results must be an physical register def.
-    if (HasPhysRegOuts) {
-      for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
-        unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
-        if (Node->hasAnyUseOfValue(i))
-          EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
-        // If there are no uses, mark the register as dead now, so that
-        // MachineLICM/Sink can see that it's dead. Don't do this if the
-        // node has a Flag value, for the benefit of targets still using
-        // Flag for values in physregs.
-        else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
-          MI->addRegisterDead(Reg, TRI);
-      }
+  // Additional results must be an physical register def.
+  if (HasPhysRegOuts) {
+    for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
+      unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
+      if (Node->hasAnyUseOfValue(i))
+        EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
+      // If there are no uses, mark the register as dead now, so that
+      // MachineLICM/Sink can see that it's dead. Don't do this if the
+      // node has a Flag value, for the benefit of targets still using
+      // Flag for values in physregs.
+      else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
+        MI->addRegisterDead(Reg, TRI);
     }
-    return;
   }
+  return;
+}
 
+/// EmitSpecialNode - Generate machine code for a target-independent node and
+/// needed dependencies.
+void InstrEmitter::
+EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
+                DenseMap<SDValue, unsigned> &VRBaseMap,
+                DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
   switch (Node->getOpcode()) {
   default:
 #ifndef NDEBUG

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h?rev=99444&r1=99443&r2=99444&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h Wed Mar 24 17:45:47 2010
@@ -113,7 +113,12 @@
   ///
   void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
                 DenseMap<SDValue, unsigned> &VRBaseMap,
-                DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
+                DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
+    if (Node->isMachineOpcode())
+      EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap, EM);
+    else
+      EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap, EM);
+  }
 
   /// getBlock - Return the current basic block.
   MachineBasicBlock *getBlock() { return MBB; }
@@ -124,6 +129,14 @@
   /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
   /// at the given position in the given block.
   InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos);
+  
+private:
+  void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
+                       DenseMap<SDValue, unsigned> &VRBaseMap,
+                       DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
+  void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
+                       DenseMap<SDValue, unsigned> &VRBaseMap,
+                       DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
 };
 
 }




From sabre at nondot.org  Wed Mar 24 17:47:12 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 22:47:12 -0000
Subject: [llvm-commits] [llvm] r99445 - in
 /llvm/trunk/lib/CodeGen/SelectionDAG: InstrEmitter.cpp InstrEmitter.h
Message-ID: <20100324224713.093422A6C12C@llvm.org>

Author: lattner
Date: Wed Mar 24 17:47:12 2010
New Revision: 99445

URL: http://llvm.org/viewvc/llvm-project?rev=99445&view=rev
Log:
remove dead argument.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=99445&r1=99444&r2=99445&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Wed Mar 24 17:47:12 2010
@@ -660,8 +660,7 @@
 /// needed dependencies.
 void InstrEmitter::
 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
-                DenseMap<SDValue, unsigned> &VRBaseMap,
-                DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
+                DenseMap<SDValue, unsigned> &VRBaseMap) {
   switch (Node->getOpcode()) {
   default:
 #ifndef NDEBUG

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h?rev=99445&r1=99444&r2=99445&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h Wed Mar 24 17:47:12 2010
@@ -117,7 +117,7 @@
     if (Node->isMachineOpcode())
       EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap, EM);
     else
-      EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap, EM);
+      EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap);
   }
 
   /// getBlock - Return the current basic block.
@@ -135,8 +135,7 @@
                        DenseMap<SDValue, unsigned> &VRBaseMap,
                        DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
   void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
-                       DenseMap<SDValue, unsigned> &VRBaseMap,
-                       DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
+                       DenseMap<SDValue, unsigned> &VRBaseMap);
 };
 
 }




From wangmp at apple.com  Wed Mar 24 18:01:30 2010
From: wangmp at apple.com (Mon Ping Wang)
Date: Wed, 24 Mar 2010 16:01:30 -0700
Subject: [llvm-commits] Patch: address space support for
	memcpy/memmove/memset
Message-ID: <89548B9C-55E6-40DF-8E7D-9B1C30162EA4@apple.com>


This is a patch to add support for address spaces for memcpy, memmove, and memset.  I have changed the signature of these functions to be overloaded based on the pointer type.  I have included both the llvm changes and the llvm-gcc-4.2 changes need to support.  Please let me know if I miss something.  I'll check it in a few days.

Thanks,
  -- Mon Ping

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From sabre at nondot.org  Wed Mar 24 18:07:48 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 23:07:48 -0000
Subject: [llvm-commits] [llvm] r99446 -
	/llvm/trunk/include/llvm/Target/TargetInstrDesc.h
Message-ID: <20100324230748.1BD3D2A6C12C@llvm.org>

Author: lattner
Date: Wed Mar 24 18:07:47 2010
New Revision: 99446

URL: http://llvm.org/viewvc/llvm-project?rev=99446&view=rev
Log:
add a convenient TargetInstrDesc::getNumImplicitUses/Defs method.

Modified:
    llvm/trunk/include/llvm/Target/TargetInstrDesc.h

Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=99446&r1=99445&r2=99446&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Wed Mar 24 18:07:47 2010
@@ -204,6 +204,16 @@
     return ImplicitUses;
   }
   
+  /// getNumImplicitUses - Return the number of implicit uses this instruction
+  /// has.
+  unsigned getNumImplicitUses() const {
+    if (ImplicitUses == 0) return 0;
+    unsigned i = 0;
+    for (; ImplicitUses[i]; ++i) /*empty*/;
+    return i;
+  }
+  
+  
   /// getImplicitDefs - Return a list of registers that are potentially
   /// written by any instance of this machine instruction.  For example, on X86,
   /// many instructions implicitly set the flags register.  In this case, they
@@ -218,6 +228,15 @@
     return ImplicitDefs;
   }
   
+  /// getNumImplicitDefs - Return the number of implicit defs this instruction
+  /// has.
+  unsigned getNumImplicitDefs() const {
+    if (ImplicitDefs == 0) return 0;
+    unsigned i = 0;
+    for (; ImplicitDefs[i]; ++i) /*empty*/;
+    return i;
+  }
+  
   /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
   /// uses the specified physical register.
   bool hasImplicitUseOfPhysReg(unsigned Reg) const {




From bob.wilson at apple.com  Wed Mar 24 18:25:15 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 24 Mar 2010 16:25:15 -0700
Subject: [llvm-commits] [llvm] r99440 - in /llvm/trunk:
	include/llvm/CodeGen/SelectionDAGNodes.h
	include/llvm/IntrinsicsX86.td lib/Target/X86/X86ISelLowering.h
	lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-bit_cat.s
	test/MC/AsmParser/X86/x86_32-encoding.s
In-Reply-To: <20100324223334.21E052A6C12C@llvm.org>
References: <20100324223334.21E052A6C12C@llvm.org>
Message-ID: <652D2372-821A-4A4B-A8C5-DBAF70817FD1@apple.com>

Kevin, I think this might be causing the buildbot failures.  I'm going to try speculatively reverting it.  If that doesn't help, I'll reapply it later.

On Mar 24, 2010, at 3:33 PM, Kevin Enderby wrote:

> Author: enderby
> Date: Wed Mar 24 17:33:33 2010
> New Revision: 99440
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99440&view=rev
> Log:
> Added the Advanced Encryption Standard (AES) Instructions.
> 
> Modified:
>    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
>    llvm/trunk/include/llvm/IntrinsicsX86.td
>    llvm/trunk/lib/Target/X86/X86ISelLowering.h
>    llvm/trunk/lib/Target/X86/X86InstrSSE.td
>    llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s
>    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
> 
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=99440&r1=99439&r2=99440&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Mar 24 17:33:33 2010
> @@ -616,7 +616,7 @@
>   /// which do not reference a specific memory location should be less than
>   /// this value. Those that do must not be less than this value, and can
>   /// be used with SelectionDAG::getMemIntrinsicNode.
> -  static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+80;
> +  static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+85;
> 
>   /// Node predicates
> 
> 
> Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=99440&r1=99439&r2=99440&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
> +++ llvm/trunk/include/llvm/IntrinsicsX86.td Wed Mar 24 17:33:33 2010
> @@ -779,6 +779,25 @@
>                         [IntrNoMem, Commutative]>;
> }
> 
> +// Advanced Encryption Standard (AES) Instructions
> +let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
> +  def int_x86_sse42_aesimc          :
> +              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
> +                        [IntrNoMem]>;
> +  def int_x86_sse42_aesenc          :
> +              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
> +                        [IntrNoMem]>;
> +  def int_x86_sse42_aesenclast      :
> +              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
> +                        [IntrNoMem]>;
> +  def int_x86_sse42_aesdec          :
> +              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
> +                        [IntrNoMem]>;
> +  def int_x86_sse42_aesdeclast      :
> +              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
> +                        [IntrNoMem]>;
> +}
> +
> // Vector pack
> let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
>   def int_x86_sse41_packusdw        : GCCBuiltin<"__builtin_ia32_packusdw128">,
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=99440&r1=99439&r2=99440&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Mar 24 17:33:33 2010
> @@ -234,6 +234,9 @@
>       PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
>       PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
> 
> +      // Advanced Encryption Standard (AES) Instructions
> +      AESIMC, AESENC, AESENCLAST, AESDEC, AESDECLAST,
> +
>       // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
>       ADD, SUB, SMUL, UMUL,
>       INC, DEC, OR, XOR, AND,
> 
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=99440&r1=99439&r2=99440&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Mar 24 17:33:33 2010
> @@ -69,6 +69,12 @@
> def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
> def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
> 
> +def X86aesimc          : SDNode<"X86ISD::AESIMC",          SDTIntBinOp>;
> +def X86aesenc          : SDNode<"X86ISD::AESENC",          SDTIntBinOp>;
> +def X86aesenclast      : SDNode<"X86ISD::AESENCLAST",      SDTIntBinOp>;
> +def X86aesdec          : SDNode<"X86ISD::AESDEC",          SDTIntBinOp>;
> +def X86aesdeclast      : SDNode<"X86ISD::AESDECLAST",      SDTIntBinOp>;
> +
> def SDTX86CmpPTest : SDTypeProfile<0, 2, [SDTCisVT<0, v4f32>,
>                                           SDTCisVT<1, v4f32>]>;
> def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
> @@ -3817,6 +3823,45 @@
> def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
>           (PCMPGTQrm VR128:$src1, addr:$src2)>;
> 
> +defm AESIMC          : SS42I_binop_rm_int<0xDB, "aesimc",
> +                       int_x86_sse42_aesimc>;
> +defm AESENC          : SS42I_binop_rm_int<0xDC, "aesenc",
> +                       int_x86_sse42_aesenc>;
> +defm AESENCLAST      : SS42I_binop_rm_int<0xDD, "aesenclast",
> +                       int_x86_sse42_aesenclast>;
> +defm AESDEC          : SS42I_binop_rm_int<0xDE, "aesdec",
> +                       int_x86_sse42_aesdec>;
> +defm AESDECLAST      : SS42I_binop_rm_int<0xDF, "aesdeclast",
> +                       int_x86_sse42_aesdeclast>;
> +
> +def : Pat<(v2i64 (X86aesimc VR128:$src1, VR128:$src2)),
> +          (AESIMCrr VR128:$src1, VR128:$src2)>;
> +def : Pat<(v2i64 (X86aesimc VR128:$src1, (memop addr:$src2))),
> +          (AESIMCrm VR128:$src1, addr:$src2)>;
> +def : Pat<(v2i64 (X86aesenc VR128:$src1, VR128:$src2)),
> +          (AESENCrr VR128:$src1, VR128:$src2)>;
> +def : Pat<(v2i64 (X86aesenc VR128:$src1, (memop addr:$src2))),
> +          (AESENCrm VR128:$src1, addr:$src2)>;
> +def : Pat<(v2i64 (X86aesenclast VR128:$src1, VR128:$src2)),
> +          (AESENCLASTrr VR128:$src1, VR128:$src2)>;
> +def : Pat<(v2i64 (X86aesenclast VR128:$src1, (memop addr:$src2))),
> +          (AESENCLASTrm VR128:$src1, addr:$src2)>;
> +def : Pat<(v2i64 (X86aesdec VR128:$src1, VR128:$src2)),
> +          (AESDECrr VR128:$src1, VR128:$src2)>;
> +def : Pat<(v2i64 (X86aesdec VR128:$src1, (memop addr:$src2))),
> +          (AESDECrm VR128:$src1, addr:$src2)>;
> +def : Pat<(v2i64 (X86aesdeclast VR128:$src1, VR128:$src2)),
> +          (AESDECLASTrr VR128:$src1, VR128:$src2)>;
> +def : Pat<(v2i64 (X86aesdeclast VR128:$src1, (memop addr:$src2))),
> +          (AESDECLASTrm VR128:$src1, addr:$src2)>;
> +
> +def AESKEYGENASSIST128rr : SS42AI<0xDF, MRMSrcReg, (outs),
> +  (ins VR128:$src1, VR128:$src2, i8imm:$src3),
> +  "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
> +def AESKEYGENASSIST128rm : SS42AI<0xDF, MRMSrcMem, (outs),
> +  (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
> +  "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
> +
> // crc intrinsic instruction
> // This set of instructions are only rm, the only difference is the size
> // of r and m.
> 
> Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s?rev=99440&r1=99439&r2=99440&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s (original)
> +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s Wed Mar 24 17:33:33 2010
> @@ -7806,3 +7806,39 @@
> 
> // CHECK: 	pcmpgtq	%xmm5, %xmm5
>         	pcmpgtq	%xmm5,%xmm5
> +
> +// CHECK: 	aesimc	%xmm0, %xmm1
> +                aesimc %xmm0,%xmm1
> +
> +// CHECK: 	aesimc	(%eax), %xmm1
> +                aesimc (%eax),%xmm1
> +
> +// CHECK: 	aesenc	%xmm1, %xmm2
> +                aesenc %xmm1,%xmm2
> +
> +// CHECK: 	aesenc	4(%ebx), %xmm2
> +                aesenc 4(%ebx),%xmm2
> +
> +// CHECK: 	aesenclast	%xmm3, %xmm4
> +                aesenclast %xmm3,%xmm4
> +
> +// CHECK: 	aesenclast	4(%edx,%edi), %xmm4
> +                aesenclast 4(%edx,%edi),%xmm4
> +
> +// CHECK: 	aesdec	%xmm5, %xmm6
> +                aesdec %xmm5,%xmm6
> +
> +// CHECK: 	aesdec	4(%ecx,%eax,8), %xmm6
> +                aesdec 4(%ecx,%eax,8),%xmm6
> +
> +// CHECK: 	aesdeclast	%xmm7, %xmm0
> +                aesdeclast %xmm7,%xmm0
> +
> +// CHECK: 	aesdeclast	3405691582, %xmm0
> +                aesdeclast 0xcafebabe,%xmm0
> +
> +// CHECK: 	aeskeygenassist	$125, %xmm1, %xmm2
> +                aeskeygenassist $125, %xmm1, %xmm2
> +
> +// CHECK: 	aeskeygenassist	$125, (%edx,%eax,4), %xmm2
> +                aeskeygenassist $125, (%edx,%eax,4), %xmm2
> 
> Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=99440&r1=99439&r2=99440&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
> +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Wed Mar 24 17:33:33 2010
> @@ -9913,3 +9913,51 @@
> // CHECK: pcmpistrm	$125, (%edx,%eax,4), %xmm2
> // CHECK:  encoding: [0x66,0x0f,0x3a,0x62,0x14,0x82,0x7d]
>                 pcmpistrm $125, (%edx,%eax,4), %xmm2
> +
> +// CHECK: aesimc	%xmm0, %xmm1
> +// CHECK:  encoding: [0x66,0x0f,0x38,0xdb,0xc8]
> +                aesimc %xmm0,%xmm1
> +
> +// CHECK: aesimc	(%eax), %xmm1
> +// CHECK:  encoding: [0x66,0x0f,0x38,0xdb,0x08]
> +                aesimc (%eax),%xmm1
> +
> +// CHECK: aesenc	%xmm1, %xmm2
> +// CHECK:  encoding: [0x66,0x0f,0x38,0xdc,0xd1]
> +                aesenc %xmm1,%xmm2
> +
> +// CHECK: aesenc	4(%ebx), %xmm2
> +// CHECK:  encoding: [0x66,0x0f,0x38,0xdc,0x53,0x04]
> +                aesenc 4(%ebx),%xmm2
> +
> +// CHECK: aesenclast	%xmm3, %xmm4
> +// CHECK:  encoding: [0x66,0x0f,0x38,0xdd,0xe3]
> +                aesenclast %xmm3,%xmm4
> +
> +// CHECK: aesenclast	4(%edx,%edi), %xmm4
> +// CHECK:  encoding: [0x66,0x0f,0x38,0xdd,0x64,0x3a,0x04]
> +                aesenclast 4(%edx,%edi),%xmm4
> +
> +// CHECK: aesdec	%xmm5, %xmm6
> +// CHECK:  encoding: [0x66,0x0f,0x38,0xde,0xf5]
> +                aesdec %xmm5,%xmm6
> +
> +// CHECK: aesdec	4(%ecx,%eax,8), %xmm6
> +// CHECK:  encoding: [0x66,0x0f,0x38,0xde,0x74,0xc1,0x04]
> +                aesdec 4(%ecx,%eax,8),%xmm6
> +
> +// CHECK: aesdeclast	%xmm7, %xmm0
> +// CHECK:  encoding: [0x66,0x0f,0x38,0xdf,0xc7]
> +                aesdeclast %xmm7,%xmm0
> +
> +// CHECK: aesdeclast	3405691582, %xmm0
> +// CHECK:  encoding: [0x66,0x0f,0x38,0xdf,0x05,0xbe,0xba,0xfe,0xca]
> +                aesdeclast 0xcafebabe,%xmm0
> +
> +// CHECK: aeskeygenassist	$125, %xmm1, %xmm2
> +// CHECK:  encoding: [0x66,0x0f,0x3a,0xdf,0xd1,0x7d]
> +                aeskeygenassist $125, %xmm1, %xmm2
> +
> +// CHECK: aeskeygenassist	$125, (%edx,%eax,4), %xmm2
> +// CHECK:  encoding: [0x66,0x0f,0x3a,0xdf,0x14,0x82,0x7d]
> +                aeskeygenassist $125, (%edx,%eax,4), %xmm2
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From bob.wilson at apple.com  Wed Mar 24 18:26:29 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 24 Mar 2010 23:26:29 -0000
Subject: [llvm-commits] [llvm] r99450 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGNodes.h include/llvm/IntrinsicsX86.td
 lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrSSE.td
 test/MC/AsmParser/X86/x86_32-bit_cat.s
 test/MC/AsmParser/X86/x86_32-encoding.s
Message-ID: <20100324232629.86BD92A6C12C@llvm.org>

Author: bwilson
Date: Wed Mar 24 18:26:29 2010
New Revision: 99450

URL: http://llvm.org/viewvc/llvm-project?rev=99450&view=rev
Log:
Speculatively revert this to see if it fixes buildbot failures.
--- Reverse-merging r99440 into '.':
U    test/MC/AsmParser/X86/x86_32-bit_cat.s
U    test/MC/AsmParser/X86/x86_32-encoding.s
U    include/llvm/IntrinsicsX86.td
U    include/llvm/CodeGen/SelectionDAGNodes.h
U    lib/Target/X86/X86InstrSSE.td
U    lib/Target/X86/X86ISelLowering.h

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/include/llvm/IntrinsicsX86.td
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=99450&r1=99449&r2=99450&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Mar 24 18:26:29 2010
@@ -616,7 +616,7 @@
   /// which do not reference a specific memory location should be less than
   /// this value. Those that do must not be less than this value, and can
   /// be used with SelectionDAG::getMemIntrinsicNode.
-  static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+85;
+  static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+80;
 
   /// Node predicates
 

Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=99450&r1=99449&r2=99450&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsX86.td Wed Mar 24 18:26:29 2010
@@ -779,25 +779,6 @@
                         [IntrNoMem, Commutative]>;
 }
 
-// Advanced Encryption Standard (AES) Instructions
-let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
-  def int_x86_sse42_aesimc          :
-              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
-                        [IntrNoMem]>;
-  def int_x86_sse42_aesenc          :
-              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
-                        [IntrNoMem]>;
-  def int_x86_sse42_aesenclast      :
-              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
-                        [IntrNoMem]>;
-  def int_x86_sse42_aesdec          :
-              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
-                        [IntrNoMem]>;
-  def int_x86_sse42_aesdeclast      :
-              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
-                        [IntrNoMem]>;
-}
-
 // Vector pack
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse41_packusdw        : GCCBuiltin<"__builtin_ia32_packusdw128">,

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=99450&r1=99449&r2=99450&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Mar 24 18:26:29 2010
@@ -234,9 +234,6 @@
       PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
       PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
 
-      // Advanced Encryption Standard (AES) Instructions
-      AESIMC, AESENC, AESENCLAST, AESDEC, AESDECLAST,
-
       // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
       ADD, SUB, SMUL, UMUL,
       INC, DEC, OR, XOR, AND,

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=99450&r1=99449&r2=99450&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Mar 24 18:26:29 2010
@@ -69,12 +69,6 @@
 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
 
-def X86aesimc          : SDNode<"X86ISD::AESIMC",          SDTIntBinOp>;
-def X86aesenc          : SDNode<"X86ISD::AESENC",          SDTIntBinOp>;
-def X86aesenclast      : SDNode<"X86ISD::AESENCLAST",      SDTIntBinOp>;
-def X86aesdec          : SDNode<"X86ISD::AESDEC",          SDTIntBinOp>;
-def X86aesdeclast      : SDNode<"X86ISD::AESDECLAST",      SDTIntBinOp>;
-
 def SDTX86CmpPTest : SDTypeProfile<0, 2, [SDTCisVT<0, v4f32>,
                                           SDTCisVT<1, v4f32>]>;
 def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
@@ -3823,45 +3817,6 @@
 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
           (PCMPGTQrm VR128:$src1, addr:$src2)>;
 
-defm AESIMC          : SS42I_binop_rm_int<0xDB, "aesimc",
-                       int_x86_sse42_aesimc>;
-defm AESENC          : SS42I_binop_rm_int<0xDC, "aesenc",
-                       int_x86_sse42_aesenc>;
-defm AESENCLAST      : SS42I_binop_rm_int<0xDD, "aesenclast",
-                       int_x86_sse42_aesenclast>;
-defm AESDEC          : SS42I_binop_rm_int<0xDE, "aesdec",
-                       int_x86_sse42_aesdec>;
-defm AESDECLAST      : SS42I_binop_rm_int<0xDF, "aesdeclast",
-                       int_x86_sse42_aesdeclast>;
-
-def : Pat<(v2i64 (X86aesimc VR128:$src1, VR128:$src2)),
-          (AESIMCrr VR128:$src1, VR128:$src2)>;
-def : Pat<(v2i64 (X86aesimc VR128:$src1, (memop addr:$src2))),
-          (AESIMCrm VR128:$src1, addr:$src2)>;
-def : Pat<(v2i64 (X86aesenc VR128:$src1, VR128:$src2)),
-          (AESENCrr VR128:$src1, VR128:$src2)>;
-def : Pat<(v2i64 (X86aesenc VR128:$src1, (memop addr:$src2))),
-          (AESENCrm VR128:$src1, addr:$src2)>;
-def : Pat<(v2i64 (X86aesenclast VR128:$src1, VR128:$src2)),
-          (AESENCLASTrr VR128:$src1, VR128:$src2)>;
-def : Pat<(v2i64 (X86aesenclast VR128:$src1, (memop addr:$src2))),
-          (AESENCLASTrm VR128:$src1, addr:$src2)>;
-def : Pat<(v2i64 (X86aesdec VR128:$src1, VR128:$src2)),
-          (AESDECrr VR128:$src1, VR128:$src2)>;
-def : Pat<(v2i64 (X86aesdec VR128:$src1, (memop addr:$src2))),
-          (AESDECrm VR128:$src1, addr:$src2)>;
-def : Pat<(v2i64 (X86aesdeclast VR128:$src1, VR128:$src2)),
-          (AESDECLASTrr VR128:$src1, VR128:$src2)>;
-def : Pat<(v2i64 (X86aesdeclast VR128:$src1, (memop addr:$src2))),
-          (AESDECLASTrm VR128:$src1, addr:$src2)>;
-
-def AESKEYGENASSIST128rr : SS42AI<0xDF, MRMSrcReg, (outs),
-  (ins VR128:$src1, VR128:$src2, i8imm:$src3),
-  "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
-def AESKEYGENASSIST128rm : SS42AI<0xDF, MRMSrcMem, (outs),
-  (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
-  "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
-
 // crc intrinsic instruction
 // This set of instructions are only rm, the only difference is the size
 // of r and m.

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s?rev=99450&r1=99449&r2=99450&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s Wed Mar 24 18:26:29 2010
@@ -7806,39 +7806,3 @@
 
 // CHECK: 	pcmpgtq	%xmm5, %xmm5
         	pcmpgtq	%xmm5,%xmm5
-
-// CHECK: 	aesimc	%xmm0, %xmm1
-                aesimc %xmm0,%xmm1
-
-// CHECK: 	aesimc	(%eax), %xmm1
-                aesimc (%eax),%xmm1
-
-// CHECK: 	aesenc	%xmm1, %xmm2
-                aesenc %xmm1,%xmm2
-
-// CHECK: 	aesenc	4(%ebx), %xmm2
-                aesenc 4(%ebx),%xmm2
-
-// CHECK: 	aesenclast	%xmm3, %xmm4
-                aesenclast %xmm3,%xmm4
-
-// CHECK: 	aesenclast	4(%edx,%edi), %xmm4
-                aesenclast 4(%edx,%edi),%xmm4
-
-// CHECK: 	aesdec	%xmm5, %xmm6
-                aesdec %xmm5,%xmm6
-
-// CHECK: 	aesdec	4(%ecx,%eax,8), %xmm6
-                aesdec 4(%ecx,%eax,8),%xmm6
-
-// CHECK: 	aesdeclast	%xmm7, %xmm0
-                aesdeclast %xmm7,%xmm0
-
-// CHECK: 	aesdeclast	3405691582, %xmm0
-                aesdeclast 0xcafebabe,%xmm0
-
-// CHECK: 	aeskeygenassist	$125, %xmm1, %xmm2
-                aeskeygenassist $125, %xmm1, %xmm2
-
-// CHECK: 	aeskeygenassist	$125, (%edx,%eax,4), %xmm2
-                aeskeygenassist $125, (%edx,%eax,4), %xmm2

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=99450&r1=99449&r2=99450&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Wed Mar 24 18:26:29 2010
@@ -9913,51 +9913,3 @@
 // CHECK: pcmpistrm	$125, (%edx,%eax,4), %xmm2
 // CHECK:  encoding: [0x66,0x0f,0x3a,0x62,0x14,0x82,0x7d]
                 pcmpistrm $125, (%edx,%eax,4), %xmm2
-
-// CHECK: aesimc	%xmm0, %xmm1
-// CHECK:  encoding: [0x66,0x0f,0x38,0xdb,0xc8]
-                aesimc %xmm0,%xmm1
-
-// CHECK: aesimc	(%eax), %xmm1
-// CHECK:  encoding: [0x66,0x0f,0x38,0xdb,0x08]
-                aesimc (%eax),%xmm1
-
-// CHECK: aesenc	%xmm1, %xmm2
-// CHECK:  encoding: [0x66,0x0f,0x38,0xdc,0xd1]
-                aesenc %xmm1,%xmm2
-
-// CHECK: aesenc	4(%ebx), %xmm2
-// CHECK:  encoding: [0x66,0x0f,0x38,0xdc,0x53,0x04]
-                aesenc 4(%ebx),%xmm2
-
-// CHECK: aesenclast	%xmm3, %xmm4
-// CHECK:  encoding: [0x66,0x0f,0x38,0xdd,0xe3]
-                aesenclast %xmm3,%xmm4
-
-// CHECK: aesenclast	4(%edx,%edi), %xmm4
-// CHECK:  encoding: [0x66,0x0f,0x38,0xdd,0x64,0x3a,0x04]
-                aesenclast 4(%edx,%edi),%xmm4
-
-// CHECK: aesdec	%xmm5, %xmm6
-// CHECK:  encoding: [0x66,0x0f,0x38,0xde,0xf5]
-                aesdec %xmm5,%xmm6
-
-// CHECK: aesdec	4(%ecx,%eax,8), %xmm6
-// CHECK:  encoding: [0x66,0x0f,0x38,0xde,0x74,0xc1,0x04]
-                aesdec 4(%ecx,%eax,8),%xmm6
-
-// CHECK: aesdeclast	%xmm7, %xmm0
-// CHECK:  encoding: [0x66,0x0f,0x38,0xdf,0xc7]
-                aesdeclast %xmm7,%xmm0
-
-// CHECK: aesdeclast	3405691582, %xmm0
-// CHECK:  encoding: [0x66,0x0f,0x38,0xdf,0x05,0xbe,0xba,0xfe,0xca]
-                aesdeclast 0xcafebabe,%xmm0
-
-// CHECK: aeskeygenassist	$125, %xmm1, %xmm2
-// CHECK:  encoding: [0x66,0x0f,0x3a,0xdf,0xd1,0x7d]
-                aeskeygenassist $125, %xmm1, %xmm2
-
-// CHECK: aeskeygenassist	$125, (%edx,%eax,4), %xmm2
-// CHECK:  encoding: [0x66,0x0f,0x3a,0xdf,0x14,0x82,0x7d]
-                aeskeygenassist $125, (%edx,%eax,4), %xmm2




From echristo at apple.com  Wed Mar 24 18:35:22 2010
From: echristo at apple.com (Eric Christopher)
Date: Wed, 24 Mar 2010 23:35:22 -0000
Subject: [llvm-commits] [llvm] r99451 - in /llvm/trunk:
 include/llvm/Instructions.h include/llvm/Support/CallSite.h
 lib/Transforms/Utils/InlineFunction.cpp lib/VMCore/Instructions.cpp
 test/Transforms/Inline/noinline.ll
Message-ID: <20100324233522.3643A2A6C12C@llvm.org>

Author: echristo
Date: Wed Mar 24 18:35:21 2010
New Revision: 99451

URL: http://llvm.org/viewvc/llvm-project?rev=99451&view=rev
Log:
Temporarily revert this, it's causing an issue with an internal project.

Removed:
    llvm/trunk/test/Transforms/Inline/noinline.ll
Modified:
    llvm/trunk/include/llvm/Instructions.h
    llvm/trunk/include/llvm/Support/CallSite.h
    llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
    llvm/trunk/lib/VMCore/Instructions.cpp

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=99451&r1=99450&r2=99451&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Wed Mar 24 18:35:21 2010
@@ -971,13 +971,6 @@
   unsigned getParamAlignment(unsigned i) const {
     return AttributeList.getParamAlignment(i);
   }
-  
-  /// @brief Return true if the call should not be inlined.
-  bool isNoInline() const { return paramHasAttr(~0, Attribute::NoInline); }
-  void setIsNoInline(bool Value) {
-    if (Value) addAttribute(~0, Attribute::NoInline);
-    else removeAttribute(~0, Attribute::NoInline);
-  }
 
   /// @brief Determine if the call does not access memory.
   bool doesNotAccessMemory() const {
@@ -2463,13 +2456,6 @@
     return AttributeList.getParamAlignment(i);
   }
 
-  /// @brief Return true if the call should not be inlined.
-  bool isNoInline() const { return paramHasAttr(~0, Attribute::NoInline); }
-  void setIsNoInline(bool Value) {
-    if (Value) addAttribute(~0, Attribute::NoInline);
-    else removeAttribute(~0, Attribute::NoInline);
-  }
-  
   /// @brief Determine if the call does not access memory.
   bool doesNotAccessMemory() const {
     return paramHasAttr(~0, Attribute::ReadNone);

Modified: llvm/trunk/include/llvm/Support/CallSite.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=99451&r1=99450&r2=99451&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CallSite.h (original)
+++ llvm/trunk/include/llvm/Support/CallSite.h Wed Mar 24 18:35:21 2010
@@ -76,10 +76,6 @@
   /// @brief Extract the alignment for a call or parameter (0=unknown).
   uint16_t getParamAlignment(uint16_t i) const;
 
-  /// @brief Return true if the call should not be inlined.
-  bool isNoInline() const;
-  void setIsNoInline(bool Value = true);
-  
   /// @brief Determine if the call does not access memory.
   bool doesNotAccessMemory() const;
   void setDoesNotAccessMemory(bool doesNotAccessMemory = true);

Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=99451&r1=99450&r2=99451&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Wed Mar 24 18:35:21 2010
@@ -229,9 +229,7 @@
   const Function *CalledFunc = CS.getCalledFunction();
   if (CalledFunc == 0 ||          // Can't inline external function or indirect
       CalledFunc->isDeclaration() || // call, or call to a vararg function!
-      CalledFunc->getFunctionType()->isVarArg() ||
-      CS.isNoInline())            // Call site is marked noinline.
-    return false;
+      CalledFunc->getFunctionType()->isVarArg()) return false;
 
 
   // If the call to the callee is not a tail call, we must clear the 'tail'

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=99451&r1=99450&r2=99451&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Wed Mar 24 18:35:21 2010
@@ -31,13 +31,13 @@
 //===----------------------------------------------------------------------===//
 
 #define CALLSITE_DELEGATE_GETTER(METHOD) \
-  Instruction *II = getInstruction();    \
+  Instruction *II(getInstruction());     \
   return isCall()                        \
     ? cast<CallInst>(II)->METHOD         \
     : cast<InvokeInst>(II)->METHOD
 
 #define CALLSITE_DELEGATE_SETTER(METHOD) \
-  Instruction *II = getInstruction();    \
+  Instruction *II(getInstruction());     \
   if (isCall())                          \
     cast<CallInst>(II)->METHOD;          \
   else                                   \
@@ -66,17 +66,6 @@
 uint16_t CallSite::getParamAlignment(uint16_t i) const {
   CALLSITE_DELEGATE_GETTER(getParamAlignment(i));
 }
-
-/// @brief Return true if the call should not be inlined.
-bool CallSite::isNoInline() const {
-  CALLSITE_DELEGATE_GETTER(isNoInline());
-}
-
-void CallSite::setIsNoInline(bool Value) {
-  CALLSITE_DELEGATE_GETTER(setIsNoInline(Value));
-}
-
-
 bool CallSite::doesNotAccessMemory() const {
   CALLSITE_DELEGATE_GETTER(doesNotAccessMemory());
 }

Removed: llvm/trunk/test/Transforms/Inline/noinline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/noinline.ll?rev=99450&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/Inline/noinline.ll (original)
+++ llvm/trunk/test/Transforms/Inline/noinline.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: opt %s -inline -S | FileCheck %s
-; PR6682
-declare void @foo() nounwind
-
-define void @bar() nounwind {
-entry:
-    tail call void @foo() nounwind
-    ret void
-}
-
-define void @bazz() nounwind {
-entry:
-    tail call void @bar() nounwind noinline
-    ret void
-}
-
-; CHECK: define void @bazz()
-; CHECK: call void @bar()




From sabre at nondot.org  Wed Mar 24 18:41:19 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 24 Mar 2010 23:41:19 -0000
Subject: [llvm-commits] [llvm] r99453 - in
 /llvm/trunk/lib/CodeGen/SelectionDAG: InstrEmitter.cpp InstrEmitter.h
Message-ID: <20100324234119.CA8132A6C12C@llvm.org>

Author: lattner
Date: Wed Mar 24 18:41:19 2010
New Revision: 99453

URL: http://llvm.org/viewvc/llvm-project?rev=99453&view=rev
Log:
revert 99444/99445.  This doesn't cause the failure of 
2006-07-19-stwbrx-crash.ll for me, but it's the only likely
patch in the blame list of several bots.  Lets see if this
fixes it.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=99453&r1=99452&r2=99453&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Wed Mar 24 18:41:19 2010
@@ -569,98 +569,93 @@
   MBB->insert(InsertPos, MI);
 }
 
-/// EmitMachineNode - Generate machine code for a target-specific node and
-/// needed dependencies.
+/// EmitNode - Generate machine code for a node and needed dependencies.
 ///
-void InstrEmitter::
-EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
-                DenseMap<SDValue, unsigned> &VRBaseMap,
-                DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
-  unsigned Opc = Node->getMachineOpcode();
-  
-  // Handle subreg insert/extract specially
-  if (Opc == TargetOpcode::EXTRACT_SUBREG || 
-      Opc == TargetOpcode::INSERT_SUBREG ||
-      Opc == TargetOpcode::SUBREG_TO_REG) {
-    EmitSubregNode(Node, VRBaseMap);
-    return;
-  }
+void InstrEmitter::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
+                            DenseMap<SDValue, unsigned> &VRBaseMap,
+                         DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
+  // If machine instruction
+  if (Node->isMachineOpcode()) {
+    unsigned Opc = Node->getMachineOpcode();
+    
+    // Handle subreg insert/extract specially
+    if (Opc == TargetOpcode::EXTRACT_SUBREG || 
+        Opc == TargetOpcode::INSERT_SUBREG ||
+        Opc == TargetOpcode::SUBREG_TO_REG) {
+      EmitSubregNode(Node, VRBaseMap);
+      return;
+    }
 
-  // Handle COPY_TO_REGCLASS specially.
-  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
-    EmitCopyToRegClassNode(Node, VRBaseMap);
-    return;
-  }
+    // Handle COPY_TO_REGCLASS specially.
+    if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
+      EmitCopyToRegClassNode(Node, VRBaseMap);
+      return;
+    }
 
-  if (Opc == TargetOpcode::IMPLICIT_DEF)
-    // We want a unique VR for each IMPLICIT_DEF use.
-    return;
-  
-  const TargetInstrDesc &II = TII->get(Opc);
-  unsigned NumResults = CountResults(Node);
-  unsigned NodeOperands = CountOperands(Node);
-  bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
-                        II.getImplicitDefs() != 0;
+    if (Opc == TargetOpcode::IMPLICIT_DEF)
+      // We want a unique VR for each IMPLICIT_DEF use.
+      return;
+    
+    const TargetInstrDesc &II = TII->get(Opc);
+    unsigned NumResults = CountResults(Node);
+    unsigned NodeOperands = CountOperands(Node);
+    bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
+                          II.getImplicitDefs() != 0;
 #ifndef NDEBUG
-  unsigned NumMIOperands = NodeOperands + NumResults;
-  assert((II.getNumOperands() == NumMIOperands ||
-          HasPhysRegOuts || II.isVariadic()) &&
-         "#operands for dag node doesn't match .td file!"); 
+    unsigned NumMIOperands = NodeOperands + NumResults;
+    assert((II.getNumOperands() == NumMIOperands ||
+            HasPhysRegOuts || II.isVariadic()) &&
+           "#operands for dag node doesn't match .td file!"); 
 #endif
 
-  // Create the new machine instruction.
-  MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
-  
-  // Add result register values for things that are defined by this
-  // instruction.
-  if (NumResults)
-    CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
-  
-  // Emit all of the actual operands of this instruction, adding them to the
-  // instruction as appropriate.
-  bool HasOptPRefs = II.getNumDefs() > NumResults;
-  assert((!HasOptPRefs || !HasPhysRegOuts) &&
-         "Unable to cope with optional defs and phys regs defs!");
-  unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
-  for (unsigned i = NumSkip; i != NodeOperands; ++i)
-    AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
-               VRBaseMap);
-
-  // Transfer all of the memory reference descriptions of this instruction.
-  MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
-                 cast<MachineSDNode>(Node)->memoperands_end());
-
-  if (II.usesCustomInsertionHook()) {
-    // Insert this instruction into the basic block using a target
-    // specific inserter which may returns a new basic block.
-    MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
-    InsertPos = MBB->end();
-  } else {
-    MBB->insert(InsertPos, MI);
-  }
+    // Create the new machine instruction.
+    MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
+    
+    // Add result register values for things that are defined by this
+    // instruction.
+    if (NumResults)
+      CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
+    
+    // Emit all of the actual operands of this instruction, adding them to the
+    // instruction as appropriate.
+    bool HasOptPRefs = II.getNumDefs() > NumResults;
+    assert((!HasOptPRefs || !HasPhysRegOuts) &&
+           "Unable to cope with optional defs and phys regs defs!");
+    unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
+    for (unsigned i = NumSkip; i != NodeOperands; ++i)
+      AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
+                 VRBaseMap);
+
+    // Transfer all of the memory reference descriptions of this instruction.
+    MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
+                   cast<MachineSDNode>(Node)->memoperands_end());
+
+    if (II.usesCustomInsertionHook()) {
+      // Insert this instruction into the basic block using a target
+      // specific inserter which may returns a new basic block.
+      MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
+      InsertPos = MBB->end();
+    } else {
+      MBB->insert(InsertPos, MI);
+    }
 
-  // Additional results must be an physical register def.
-  if (HasPhysRegOuts) {
-    for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
-      unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
-      if (Node->hasAnyUseOfValue(i))
-        EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
-      // If there are no uses, mark the register as dead now, so that
-      // MachineLICM/Sink can see that it's dead. Don't do this if the
-      // node has a Flag value, for the benefit of targets still using
-      // Flag for values in physregs.
-      else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
-        MI->addRegisterDead(Reg, TRI);
+    // Additional results must be an physical register def.
+    if (HasPhysRegOuts) {
+      for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
+        unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
+        if (Node->hasAnyUseOfValue(i))
+          EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
+        // If there are no uses, mark the register as dead now, so that
+        // MachineLICM/Sink can see that it's dead. Don't do this if the
+        // node has a Flag value, for the benefit of targets still using
+        // Flag for values in physregs.
+        else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
+          MI->addRegisterDead(Reg, TRI);
+      }
     }
+    return;
   }
-  return;
-}
 
-/// EmitSpecialNode - Generate machine code for a target-independent node and
-/// needed dependencies.
-void InstrEmitter::
-EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
-                DenseMap<SDValue, unsigned> &VRBaseMap) {
   switch (Node->getOpcode()) {
   default:
 #ifndef NDEBUG

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h?rev=99453&r1=99452&r2=99453&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h Wed Mar 24 18:41:19 2010
@@ -113,12 +113,7 @@
   ///
   void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
                 DenseMap<SDValue, unsigned> &VRBaseMap,
-                DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
-    if (Node->isMachineOpcode())
-      EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap, EM);
-    else
-      EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap);
-  }
+                DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
 
   /// getBlock - Return the current basic block.
   MachineBasicBlock *getBlock() { return MBB; }
@@ -129,13 +124,6 @@
   /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
   /// at the given position in the given block.
   InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos);
-  
-private:
-  void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
-                       DenseMap<SDValue, unsigned> &VRBaseMap,
-                       DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
-  void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
-                       DenseMap<SDValue, unsigned> &VRBaseMap);
 };
 
 }




From gohman at apple.com  Wed Mar 24 19:03:05 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 25 Mar 2010 00:03:05 -0000
Subject: [llvm-commits] [llvm] r99454 - in /llvm/trunk:
 docs/CodeGenerator.html include/llvm/MC/MCStreamer.h
 include/llvm/Target/TargetLowering.h
Message-ID: <20100325000305.3B7DD2A6C12C@llvm.org>

Author: djg
Date: Wed Mar 24 19:03:04 2010
New Revision: 99454

URL: http://llvm.org/viewvc/llvm-project?rev=99454&view=rev
Log:
Docuemntation corrections from John Myers.

Modified:
    llvm/trunk/docs/CodeGenerator.html
    llvm/trunk/include/llvm/MC/MCStreamer.h
    llvm/trunk/include/llvm/Target/TargetLowering.h

Modified: llvm/trunk/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=99454&r1=99453&r2=99454&view=diff
==============================================================================
--- llvm/trunk/docs/CodeGenerator.html (original)
+++ llvm/trunk/docs/CodeGenerator.html Wed Mar 24 19:03:04 2010
@@ -1090,8 +1090,8 @@
 <p>The portion of the instruction definition in bold indicates the pattern used
    to match the instruction.  The DAG operators
    (like <tt>fmul</tt>/<tt>fadd</tt>) are defined in
-   the <tt>lib/Target/TargetSelectionDAG.td</tt> file.  "<tt>F4RC</tt>" is the
-   register class of the input and result values.</p>
+   the <tt>include/llvm/Target/TargetSelectionDAG.td</tt> file.  "
+   <tt>F4RC</tt>" is the register class of the input and result values.</p>
 
 <p>The TableGen DAG instruction selector generator reads the instruction
    patterns in the <tt>.td</tt> file and automatically builds parts of the

Modified: llvm/trunk/include/llvm/MC/MCStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=99454&r1=99453&r2=99454&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCStreamer.h (original)
+++ llvm/trunk/include/llvm/MC/MCStreamer.h Wed Mar 24 19:03:04 2010
@@ -88,7 +88,7 @@
     /// @name Symbol & Section Management
     /// @{
     
-    /// getCurrentSection - Return the current seciton that the streamer is
+    /// getCurrentSection - Return the current section that the streamer is
     /// emitting code to.
     const MCSection *getCurrentSection() const { return CurSection; }
 

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=99454&r1=99453&r2=99454&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Mar 24 19:03:04 2010
@@ -967,7 +967,7 @@
   }
   
   /// setLoadExtAction - Indicate that the specified load with extension does
-  /// not work with the with specified type and indicate what to do about it.
+  /// not work with the specified type and indicate what to do about it.
   void setLoadExtAction(unsigned ExtType, MVT VT,
                       LegalizeAction Action) {
     assert((unsigned)VT.SimpleTy*2 < 63 &&
@@ -978,7 +978,7 @@
   }
   
   /// setTruncStoreAction - Indicate that the specified truncating store does
-  /// not work with the with specified type and indicate what to do about it.
+  /// not work with the specified type and indicate what to do about it.
   void setTruncStoreAction(MVT ValVT, MVT MemVT,
                            LegalizeAction Action) {
     assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) &&
@@ -989,7 +989,7 @@
   }
 
   /// setIndexedLoadAction - Indicate that the specified indexed load does or
-  /// does not work with the with specified type and indicate what to do abort
+  /// does not work with the specified type and indicate what to do abort
   /// it. NOTE: All indexed mode loads are initialized to Expand in
   /// TargetLowering.cpp
   void setIndexedLoadAction(unsigned IdxMode, MVT VT,
@@ -1001,7 +1001,7 @@
   }
   
   /// setIndexedStoreAction - Indicate that the specified indexed store does or
-  /// does not work with the with specified type and indicate what to do about
+  /// does not work with the specified type and indicate what to do about
   /// it. NOTE: All indexed mode stores are initialized to Expand in
   /// TargetLowering.cpp
   void setIndexedStoreAction(unsigned IdxMode, MVT VT,




From evan.cheng at apple.com  Wed Mar 24 19:10:31 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 00:10:31 -0000
Subject: [llvm-commits] [llvm] r99455 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.td
Message-ID: <20100325001031.BA2472A6C12C@llvm.org>

Author: evancheng
Date: Wed Mar 24 19:10:31 2010
New Revision: 99455

URL: http://llvm.org/viewvc/llvm-project?rev=99455&view=rev
Log:
Disable folding loads into tail call in 32-bit PIC mode. It can introduce illegal code like this:

        addl    $12, %esp
        popl    %esi
        popl    %edi
        popl    %ebx
        popl    %ebp
        jmpl    *__Block_deallocator-L1$pb(%esi)  # TAILCALL

The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class.

The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=99455&r1=99454&r2=99455&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Mar 24 19:10:31 2010
@@ -325,6 +325,7 @@
 def NearData     : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
                              "TM.getCodeModel() == CodeModel::Kernel">;
 def IsStatic     : Predicate<"TM.getRelocationModel() == Reloc::Static">;
+def IsNotPIC     : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
 def OptForSize   : Predicate<"OptForSize">;
 def OptForSpeed  : Predicate<"!OptForSize">;
 def FastBTMem    : Predicate<"!Subtarget->isBTMemSlow()">;
@@ -4346,9 +4347,12 @@
           (TCRETURNri GR32_TC:$dst, imm:$off)>,
 	  Requires<[In32BitMode]>;
 
+// FIXME: This is disabled for 32-bit PIC mode because the global base
+// register which is part of the address mode may be assigned a 
+// callee-saved register.
 def : Pat<(X86tcret (load addr:$dst), imm:$off),
           (TCRETURNmi addr:$dst, imm:$off)>,
-	  Requires<[In32BitMode]>;
+	  Requires<[In32BitMode, IsNotPIC]>;
 
 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
           (TCRETURNdi texternalsym:$dst, imm:$off)>,




From ggreif at gmail.com  Wed Mar 24 19:33:57 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 25 Mar 2010 00:33:57 -0000
Subject: [llvm-commits] [test-suite] r99460 -
	/test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile
Message-ID: <20100325003357.782FA2A6C12C@llvm.org>

Author: ggreif
Date: Wed Mar 24 19:33:57 2010
New Revision: 99460

URL: http://llvm.org/viewvc/llvm-project?rev=99460&view=rev
Log:
backed out last change, broke nightlybot

Modified:
    test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile

Modified: test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile?rev=99460&r1=99459&r2=99460&view=diff
==============================================================================
--- test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile (original)
+++ test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile Wed Mar 24 19:33:57 2010
@@ -4,8 +4,8 @@
 CPPFLAGS += -DNOASM -DLLVM
 LDFLAGS = -lstdc++ -lm
 ifdef SMALL_PROBLEM_SIZE
-RUN_OPTIONS = -1 $(PROJ_SRC_DIR)/file1.in
+RUN_OPTIONS = -1 file1.in
 else
-RUN_OPTIONS = -4 $(PROJ_SRC_DIR)/file1.in
+RUN_OPTIONS = -4 file1.in
 endif
 include $(LEVEL)/MultiSource/Makefile.multisrc




From echristo at apple.com  Wed Mar 24 19:59:51 2010
From: echristo at apple.com (Eric Christopher)
Date: Thu, 25 Mar 2010 00:59:51 -0000
Subject: [llvm-commits] [llvm] r99463 -
	/llvm/trunk/include/llvm/Target/TargetMachine.h
Message-ID: <20100325005951.E11302A6C12C@llvm.org>

Author: echristo
Date: Wed Mar 24 19:59:51 2010
New Revision: 99463

URL: http://llvm.org/viewvc/llvm-project?rev=99463&view=rev
Log:
Fix unused parameter warning.

Modified:
    llvm/trunk/include/llvm/Target/TargetMachine.h

Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=99463&r1=99462&r2=99463&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
+++ llvm/trunk/include/llvm/Target/TargetMachine.h Wed Mar 24 19:59:51 2010
@@ -192,7 +192,7 @@
                                    formatted_raw_ostream &,
                                    CodeGenFileType,
                                    CodeGenOpt::Level,
-                                   bool DisableVerify = true) {
+                                   bool = true) {
     return true;
   }
 
@@ -205,7 +205,7 @@
   virtual bool addPassesToEmitMachineCode(PassManagerBase &,
                                           JITCodeEmitter &,
                                           CodeGenOpt::Level,
-                                          bool DisableVerify = true) {
+                                          bool = true) {
     return true;
   }
 
@@ -216,7 +216,7 @@
   virtual bool addPassesToEmitWholeFile(PassManager &, formatted_raw_ostream &,
                                         CodeGenFileType,
                                         CodeGenOpt::Level,
-                                        bool DisableVerify = true) {
+                                        bool = true) {
     return true;
   }
 };




From evan.cheng at apple.com  Wed Mar 24 20:01:37 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 01:01:37 -0000
Subject: [llvm-commits] [llvm] r99465 - in /llvm/trunk/lib/CodeGen:
 PHIElimination.cpp SimpleRegisterCoalescing.cpp
Message-ID: <20100325010137.90BBB2A6C12C@llvm.org>

Author: evancheng
Date: Wed Mar 24 20:01:37 2010
New Revision: 99465

URL: http://llvm.org/viewvc/llvm-project?rev=99465&view=rev
Log:
Avoid being influenced by dbg_value instructions.

Modified:
    llvm/trunk/lib/CodeGen/PHIElimination.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=99465&r1=99464&r2=99465&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original)
+++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Wed Mar 24 20:01:37 2010
@@ -74,7 +74,7 @@
          E = ImpDefs.end(); I != E; ++I) {
     MachineInstr *DefMI = *I;
     unsigned DefReg = DefMI->getOperand(0).getReg();
-    if (MRI->use_empty(DefReg))
+    if (MRI->use_nodbg_empty(DefReg))
       DefMI->eraseFromParent();
   }
 

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=99465&r1=99464&r2=99465&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Wed Mar 24 20:01:37 2010
@@ -2800,7 +2800,7 @@
           if (MO.isDead())
             continue;
           if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
-              !mri_->use_empty(Reg)) {
+              !mri_->use_nodbg_empty(Reg)) {
             isDead = false;
             break;
           }




From daniel at zuster.org  Wed Mar 24 20:03:24 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 01:03:24 -0000
Subject: [llvm-commits] [llvm] r99467 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp
Message-ID: <20100325010324.6B00F2A6C12D@llvm.org>

Author: ddunbar
Date: Wed Mar 24 20:03:24 2010
New Revision: 99467

URL: http://llvm.org/viewvc/llvm-project?rev=99467&view=rev
Log:
MC: Eliminate MC{Fragment,{Section,Symbol}Data}::getAddress.

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99467&r1=99466&r2=99467&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Wed Mar 24 20:03:24 2010
@@ -57,6 +57,8 @@
 };
 
 class MCFragment : public ilist_node<MCFragment> {
+  friend class MCAsmLayout;
+
   MCFragment(const MCFragment&);     // DO NOT IMPLEMENT
   void operator=(const MCFragment&); // DO NOT IMPLEMENT
 
@@ -108,8 +110,6 @@
   //
   // FIXME: This could all be kept private to the assembler implementation.
 
-  uint64_t getAddress() const;
-
   uint64_t getFileSize() const {
     assert(FileSize != ~UINT64_C(0) && "File size not set!");
     return FileSize;
@@ -390,6 +390,8 @@
 // we anticipate the fast path being through an MCAssembler, the only reason to
 // keep it out is for API abstraction.
 class MCSectionData : public ilist_node<MCSectionData> {
+  friend class MCAsmLayout;
+
   MCSectionData(const MCSectionData&);  // DO NOT IMPLEMENT
   void operator=(const MCSectionData&); // DO NOT IMPLEMENT
 
@@ -469,12 +471,6 @@
   //
   // FIXME: This could all be kept private to the assembler implementation.
 
-  uint64_t getAddress() const {
-    assert(Address != ~UINT64_C(0) && "Address not set!");
-    return Address;
-  }
-  void setAddress(uint64_t Value) { Address = Value; }
-
   uint64_t getSize() const {
     assert(Size != ~UINT64_C(0) && "File size not set!");
     return Size;
@@ -549,11 +545,6 @@
   uint64_t getOffset() const { return Offset; }
   void setOffset(uint64_t Value) { Offset = Value; }
 
-  uint64_t getAddress() const {
-    assert(getFragment() && "Invalid getAddress() on undefined symbol!");
-    return getFragment()->getAddress() + getOffset();
-  }
-
   /// @}
   /// @name Symbol Attributes
   /// @{

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99467&r1=99466&r2=99467&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Mar 24 20:03:24 2010
@@ -46,19 +46,22 @@
 /* *** */
 
 uint64_t MCAsmLayout::getFragmentAddress(const MCFragment *F) const {
-  return F->getAddress();
+  assert(F->getParent() && "Missing section()!");
+  return getSectionAddress(F->getParent()) + F->getOffset();
 }
 
 uint64_t MCAsmLayout::getSymbolAddress(const MCSymbolData *SD) const {
-  return SD->getAddress();
+  assert(SD->getFragment() && "Invalid getAddress() on undefined symbol!");
+  return getFragmentAddress(SD->getFragment()) + SD->getOffset();
 }
 
 uint64_t MCAsmLayout::getSectionAddress(const MCSectionData *SD) const {
-  return SD->getAddress();
+  assert(SD->Address != ~UINT64_C(0) && "Address not set!");
+  return SD->Address;
 }
 
 void MCAsmLayout::setSectionAddress(MCSectionData *SD, uint64_t Value) {
-  SD->setAddress(Value);
+  SD->Address = Value;
 }
 
 /* *** */
@@ -78,11 +81,6 @@
 MCFragment::~MCFragment() {
 }
 
-uint64_t MCFragment::getAddress() const {
-  assert(getParent() && "Missing Section!");
-  return getParent()->getAddress() + Offset;
-}
-
 /* *** */
 
 MCSectionData::MCSectionData() : Section(0) {}




From daniel at zuster.org  Wed Mar 24 20:03:18 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 01:03:18 -0000
Subject: [llvm-commits] [llvm] r99466 - in /llvm/trunk: lib/MC/MCExpr.cpp
	test/MC/MachO/absolutize.s
Message-ID: <20100325010318.12A332A6C12C@llvm.org>

Author: ddunbar
Date: Wed Mar 24 20:03:17 2010
New Revision: 99466

URL: http://llvm.org/viewvc/llvm-project?rev=99466&view=rev
Log:
MC: Fix refacto in MCExpr evaluation, I mistakenly replaced a fragment address with a symbol address.
 - This fixes the integrated-as nightly test regressions.

Modified:
    llvm/trunk/lib/MC/MCExpr.cpp
    llvm/trunk/test/MC/MachO/absolutize.s

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=99466&r1=99465&r2=99466&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Wed Mar 24 20:03:17 2010
@@ -268,8 +268,8 @@
           Layout->getAssembler().getSymbolData(Res.getSymA()->getSymbol());
         MCSymbolData &B =
           Layout->getAssembler().getSymbolData(Res.getSymB()->getSymbol());
-        Res = MCValue::get(+ Layout->getSymbolAddress(&A) + A.getOffset()
-                           - Layout->getSymbolAddress(&B) - B.getOffset()
+        Res = MCValue::get(+ Layout->getSymbolAddress(&A)
+                           - Layout->getSymbolAddress(&B)
                            + Res.getConstant());
       }
 

Modified: llvm/trunk/test/MC/MachO/absolutize.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/absolutize.s?rev=99466&r1=99465&r2=99466&view=diff
==============================================================================
--- llvm/trunk/test/MC/MachO/absolutize.s (original)
+++ llvm/trunk/test/MC/MachO/absolutize.s Wed Mar 24 20:03:17 2010
@@ -1,27 +1,4 @@
-// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump | FileCheck %s
-
-// CHECK: # Relocation 0
-// CHECK: (('word-0', 0xa0000028),
-// CHECK:  ('word-1', 0x2b)),
-// CHECK: # Relocation 1
-// CHECK: (('word-0', 0xa4000020),
-// CHECK:  ('word-1', 0x37)),
-// CHECK: # Relocation 2
-// CHECK: (('word-0', 0xa1000000),
-// CHECK:  ('word-1', 0x33)),
-// CHECK: # Relocation 3
-// CHECK: (('word-0', 0xa4000018),
-// CHECK:  ('word-1', 0x33)),
-// CHECK: # Relocation 4
-// CHECK: (('word-0', 0xa1000000),
-// CHECK:  ('word-1', 0x2f)),
-// CHECK: # Relocation 5
-// CHECK: (('word-0', 0xa4000010),
-// CHECK:  ('word-1', 0x2b)),
-// CHECK: # Relocation 6
-// CHECK: (('word-0', 0xa1000000),
-// CHECK:  ('word-1', 0x2f)),
-// CHECK-NEXT: ])
+// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s
 
 _text_a:
         xorl %eax,%eax
@@ -69,3 +46,168 @@
         .long Ldata_expr_2
 
         .long _data_a + Ldata_expr_0
+
+// CHECK: ('cputype', 7)
+// CHECK: ('cpusubtype', 3)
+// CHECK: ('filetype', 1)
+// CHECK: ('num_load_commands', 1)
+// CHECK: ('load_commands_size', 296)
+// CHECK: ('flag', 0)
+// CHECK: ('load_commands', [
+// CHECK:   # Load Command 0
+// CHECK:  (('command', 1)
+// CHECK:   ('size', 192)
+// CHECK:   ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+// CHECK:   ('vm_addr', 0)
+// CHECK:   ('vm_size', 87)
+// CHECK:   ('file_offset', 324)
+// CHECK:   ('file_size', 87)
+// CHECK:   ('maxprot', 7)
+// CHECK:   ('initprot', 7)
+// CHECK:   ('num_sections', 2)
+// CHECK:   ('flags', 0)
+// CHECK:   ('sections', [
+// CHECK:     # Section 0
+// CHECK:    (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+// CHECK:     ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+// CHECK:     ('address', 0)
+// CHECK:     ('size', 43)
+// CHECK:     ('offset', 324)
+// CHECK:     ('alignment', 0)
+// CHECK:     ('reloc_offset', 412)
+// CHECK:     ('num_reloc', 7)
+// CHECK:     ('flags', 0x80000400)
+// CHECK:     ('reserved1', 0)
+// CHECK:     ('reserved2', 0)
+// CHECK:    ),
+// CHECK:   ('_relocations', [
+// CHECK:     # Relocation 0
+// CHECK:     (('word-0', 0xa0000027),
+// CHECK:      ('word-1', 0x0)),
+// CHECK:     # Relocation 1
+// CHECK:     (('word-0', 0xa400001d),
+// CHECK:      ('word-1', 0x6)),
+// CHECK:     # Relocation 2
+// CHECK:     (('word-0', 0xa1000000),
+// CHECK:      ('word-1', 0x4)),
+// CHECK:     # Relocation 3
+// CHECK:     (('word-0', 0xa4000013),
+// CHECK:      ('word-1', 0x4)),
+// CHECK:     # Relocation 4
+// CHECK:     (('word-0', 0xa1000000),
+// CHECK:      ('word-1', 0x2)),
+// CHECK:     # Relocation 5
+// CHECK:     (('word-0', 0xa4000009),
+// CHECK:      ('word-1', 0x0)),
+// CHECK:     # Relocation 6
+// CHECK:     (('word-0', 0xa1000000),
+// CHECK:      ('word-1', 0x2)),
+// CHECK:   ])
+// CHECK:   ('_section_data', '1\xc01\xc01\xc01\xc0\xb8\xfe\xff\xff\xff\xb8\xfe\xff\xff\xff\xb8\x02\x00\x00\x00\xb8\x02\x00\x00\x00\xb8\x02\x00\x00\x00\xb8\x02\x00\x00\x00\xb8\xfe\xff\xff\xff')
+// CHECK:     # Section 1
+// CHECK:    (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+// CHECK:     ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+// CHECK:     ('address', 43)
+// CHECK:     ('size', 44)
+// CHECK:     ('offset', 367)
+// CHECK:     ('alignment', 0)
+// CHECK:     ('reloc_offset', 468)
+// CHECK:     ('num_reloc', 7)
+// CHECK:     ('flags', 0x0)
+// CHECK:     ('reserved1', 0)
+// CHECK:     ('reserved2', 0)
+// CHECK:    ),
+// CHECK:   ('_relocations', [
+// CHECK:     # Relocation 0
+// CHECK:     (('word-0', 0xa0000028),
+// CHECK:      ('word-1', 0x2b)),
+// CHECK:     # Relocation 1
+// CHECK:     (('word-0', 0xa4000020),
+// CHECK:      ('word-1', 0x37)),
+// CHECK:     # Relocation 2
+// CHECK:     (('word-0', 0xa1000000),
+// CHECK:      ('word-1', 0x33)),
+// CHECK:     # Relocation 3
+// CHECK:     (('word-0', 0xa4000018),
+// CHECK:      ('word-1', 0x33)),
+// CHECK:     # Relocation 4
+// CHECK:     (('word-0', 0xa1000000),
+// CHECK:      ('word-1', 0x2f)),
+// CHECK:     # Relocation 5
+// CHECK:     (('word-0', 0xa4000010),
+// CHECK:      ('word-1', 0x2b)),
+// CHECK:     # Relocation 6
+// CHECK:     (('word-0', 0xa1000000),
+// CHECK:      ('word-1', 0x2f)),
+// CHECK:   ])
+// CHECK:   ('_section_data', "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xfc\xff\xff\xff\xfc\xff\xff\xff\x04\x00\x00\x00\x04\x00\x00\x00\x04\x00\x00\x00\x04\x00\x00\x00'\x00\x00\x00")
+// CHECK:   ])
+// CHECK:  ),
+// CHECK:   # Load Command 1
+// CHECK:  (('command', 2)
+// CHECK:   ('size', 24)
+// CHECK:   ('symoff', 524)
+// CHECK:   ('nsyms', 4)
+// CHECK:   ('stroff', 572)
+// CHECK:   ('strsize', 36)
+// CHECK:   ('_string_data', '\x00_text_a\x00_text_b\x00_data_a\x00_data_b\x00\x00\x00\x00')
+// CHECK:   ('_symbols', [
+// CHECK:     # Symbol 0
+// CHECK:    (('n_strx', 1)
+// CHECK:     ('n_type', 0xe)
+// CHECK:     ('n_sect', 1)
+// CHECK:     ('n_desc', 0)
+// CHECK:     ('n_value', 0)
+// CHECK:     ('_string', '_text_a')
+// CHECK:    ),
+// CHECK:     # Symbol 1
+// CHECK:    (('n_strx', 9)
+// CHECK:     ('n_type', 0xe)
+// CHECK:     ('n_sect', 1)
+// CHECK:     ('n_desc', 0)
+// CHECK:     ('n_value', 2)
+// CHECK:     ('_string', '_text_b')
+// CHECK:    ),
+// CHECK:     # Symbol 2
+// CHECK:    (('n_strx', 17)
+// CHECK:     ('n_type', 0xe)
+// CHECK:     ('n_sect', 2)
+// CHECK:     ('n_desc', 0)
+// CHECK:     ('n_value', 43)
+// CHECK:     ('_string', '_data_a')
+// CHECK:    ),
+// CHECK:     # Symbol 3
+// CHECK:    (('n_strx', 25)
+// CHECK:     ('n_type', 0xe)
+// CHECK:     ('n_sect', 2)
+// CHECK:     ('n_desc', 0)
+// CHECK:     ('n_value', 47)
+// CHECK:     ('_string', '_data_b')
+// CHECK:    ),
+// CHECK:   ])
+// CHECK:  ),
+// CHECK:   # Load Command 2
+// CHECK:  (('command', 11)
+// CHECK:   ('size', 80)
+// CHECK:   ('ilocalsym', 0)
+// CHECK:   ('nlocalsym', 4)
+// CHECK:   ('iextdefsym', 4)
+// CHECK:   ('nextdefsym', 0)
+// CHECK:   ('iundefsym', 4)
+// CHECK:   ('nundefsym', 0)
+// CHECK:   ('tocoff', 0)
+// CHECK:   ('ntoc', 0)
+// CHECK:   ('modtaboff', 0)
+// CHECK:   ('nmodtab', 0)
+// CHECK:   ('extrefsymoff', 0)
+// CHECK:   ('nextrefsyms', 0)
+// CHECK:   ('indirectsymoff', 0)
+// CHECK:   ('nindirectsyms', 0)
+// CHECK:   ('extreloff', 0)
+// CHECK:   ('nextrel', 0)
+// CHECK:   ('locreloff', 0)
+// CHECK:   ('nlocrel', 0)
+// CHECK:   ('_indirect_symbols', [
+// CHECK:   ])
+// CHECK:  ),
+// CHECK: ])




From evan.cheng at apple.com  Wed Mar 24 20:38:16 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 01:38:16 -0000
Subject: [llvm-commits] [llvm] r99469 - in /llvm/trunk:
 include/llvm/CodeGen/MachineOperand.h include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/InstrEmitter.cpp
 lib/CodeGen/SelectionDAG/InstrEmitter.h
 lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
 lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20100325013817.0822C2A6C12C@llvm.org>

Author: evancheng
Date: Wed Mar 24 20:38:16 2010
New Revision: 99469

URL: http://llvm.org/viewvc/llvm-project?rev=99469&view=rev
Log:
Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers.

Here is a theoretical example that illustrates why the placement is important.

tmp1 = 
store tmp1 -> x
...
tmp2 = add ...
...
call
...
store tmp2 -> x

Now mem2reg comes along:

tmp1 = 
dbg_value (tmp1 -> x)
...
tmp2 = add ...
...
call
...
dbg_value (tmp2 -> x)

When the debugger examine the value of x after the add instruction but before the call, it should have the value of tmp1.

Furthermore, for dbg_value's that reference constants, they should not be emitted at the beginning of the block (since they do not have "producers").

This patch also cleans up how SDISel manages DbgValue nodes. It allow a SDNode to be referenced by multiple SDDbgValue nodes. When a SDNode is deleted, it uses the information to find the SDDbgValues and invalidate them. They are not deleted until the corresponding SelectionDAG is destroyed.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineOperand.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=99469&r1=99468&r2=99469&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Wed Mar 24 20:38:16 2010
@@ -285,6 +285,11 @@
     IsEarlyClobber = Val;
   }
 
+  void setIsDebug(bool Val = true) {
+    assert(isReg() && IsDef && "Wrong MachineOperand accessor");
+    IsDebug = Val;
+  }
+
   //===--------------------------------------------------------------------===//
   // Accessors for various operand types.
   //===--------------------------------------------------------------------===//

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=99469&r1=99468&r2=99469&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Mar 24 20:38:16 2010
@@ -60,42 +60,40 @@
 
 /// SDDbgInfo - Keeps track of dbg_value information through SDISel.  We do
 /// not build SDNodes for these so as not to perturb the generated code;
-/// instead the info is kept off to the side in this structure.  SDNodes may
-/// have an associated dbg_value entry in DbgValMap.  Debug info that is not
-/// associated with any SDNode is held in DbgConstMap.  It is possible for
-/// optimizations to change a variable to a constant, in which case the
-/// corresponding debug info is moved from the variable to the constant table
-/// (NYI).
+/// instead the info is kept off to the side in this structure. Each SDNode may
+/// have one or more associated dbg_value entries. This information is kept in
+/// DbgValMap.
 class SDDbgInfo {
-  DenseMap<const SDNode*, SDDbgValue*> DbgVblMap;
-  SmallVector<SDDbgValue*, 4> DbgConstMap;
+  SmallVector<SDDbgValue*, 32> DbgValues;
+  DenseMap<const SDNode*, SmallVector<SDDbgValue*, 2> > DbgVblMap;
 
   void operator=(const SDDbgInfo&);   // Do not implement.
   SDDbgInfo(const SDDbgInfo&);   // Do not implement.
 public:
   SDDbgInfo() {}
 
-  void add(const SDNode *Node, SDDbgValue *V) {
-    DbgVblMap[Node] = V;
+  void add(SDDbgValue *V, const SDNode *Node = 0) {
+    if (Node)
+      DbgVblMap[Node].push_back(V);
+    DbgValues.push_back(V);
   }
-  void add(SDDbgValue *V) { DbgConstMap.push_back(V); }
-  void remove(const SDNode *Node) {
-    DenseMap<const SDNode*, SDDbgValue*>::iterator Itr =
-                      DbgVblMap.find(Node);
-    if (Itr != DbgVblMap.end())
-      DbgVblMap.erase(Itr);
-  }
-  // No need to remove a constant.
+
   void clear() {
     DbgVblMap.clear();
-    DbgConstMap.clear();
+    DbgValues.clear();
+  }
+
+  bool empty() const {
+    return DbgValues.empty();
   }
-  SDDbgValue *getSDDbgValue(const SDNode *Node) {
+
+  SmallVector<SDDbgValue*,2> &getSDDbgValues(const SDNode *Node) {
     return DbgVblMap[Node];
   }
-  typedef SmallVector<SDDbgValue*, 4>::iterator ConstDbgIterator;
-  ConstDbgIterator DbgConstBegin() { return DbgConstMap.begin(); }
-  ConstDbgIterator DbgConstEnd() { return DbgConstMap.end(); }
+
+  typedef SmallVector<SDDbgValue*,32>::iterator DbgIterator;
+  DbgIterator DbgBegin() { return DbgValues.begin(); }
+  DbgIterator DbgEnd()   { return DbgValues.end(); }
 };
 
 enum CombineLevel {
@@ -871,19 +869,21 @@
   /// GetOrdering - Get the order for the SDNode.
   unsigned GetOrdering(const SDNode *SD) const;
 
-  /// AssignDbgInfo - Assign debug info to the SDNode.
-  void AssignDbgInfo(SDNode *SD, SDDbgValue *db);
+  /// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means the
+  /// value is produced by SD.
+  void AddDbgValue(SDDbgValue *DB, SDNode *SD = 0);
 
-  /// RememberDbgInfo - Remember debug info with no associated SDNode.
-  void RememberDbgInfo(SDDbgValue *db);
+  /// GetDbgValues - Get the debug values which reference the given SDNode.
+  SmallVector<SDDbgValue*,2> &GetDbgValues(const SDNode* SD) {
+    return DbgInfo->getSDDbgValues(SD);
+  }
 
-  /// GetDbgInfo - Get the debug info for the SDNode.
-  SDDbgValue *GetDbgInfo(const SDNode* SD);
+  /// hasDebugValues - Return true if there are any SDDbgValue nodes associated
+  /// with this SelectionDAG.
+  bool hasDebugValues() const { return !DbgInfo->empty(); }
 
-  SDDbgInfo::ConstDbgIterator DbgConstBegin() { 
-    return DbgInfo->DbgConstBegin(); 
-  }
-  SDDbgInfo::ConstDbgIterator DbgConstEnd() { return DbgInfo->DbgConstEnd(); }
+  SDDbgInfo::DbgIterator DbgBegin() { return DbgInfo->DbgBegin(); }
+  SDDbgInfo::DbgIterator DbgEnd()   { return DbgInfo->DbgEnd(); }
 
   void dump() const;
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=99469&r1=99468&r2=99469&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Wed Mar 24 20:38:16 2010
@@ -264,7 +264,8 @@
 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
                                  unsigned IIOpNum,
                                  const TargetInstrDesc *II,
-                                 DenseMap<SDValue, unsigned> &VRBaseMap) {
+                                 DenseMap<SDValue, unsigned> &VRBaseMap,
+                                 bool IsDebug) {
   assert(Op.getValueType() != MVT::Other &&
          Op.getValueType() != MVT::Flag &&
          "Chain and flag operands should occur at end of operand list!");
@@ -295,7 +296,11 @@
     }
   }
 
-  MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
+  MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
+                                           false/*isImp*/, false/*isKill*/,
+                                           false/*isDead*/, false/*isUndef*/,
+                                           false/*isEarlyClobber*/,
+                                           0/*SubReg*/, IsDebug));
 }
 
 /// AddOperand - Add the specified operand to the specified machine instr.  II
@@ -305,9 +310,10 @@
 void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
                               unsigned IIOpNum,
                               const TargetInstrDesc *II,
-                              DenseMap<SDValue, unsigned> &VRBaseMap) {
+                              DenseMap<SDValue, unsigned> &VRBaseMap,
+                              bool IsDebug) {
   if (Op.isMachineOpcode()) {
-    AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
+    AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug);
   } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
     MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
   } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
@@ -356,7 +362,7 @@
     assert(Op.getValueType() != MVT::Other &&
            Op.getValueType() != MVT::Flag &&
            "Chain and flag operands should occur at end of operand list!");
-    AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
+    AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug);
   }
 }
 
@@ -498,75 +504,48 @@
   assert(isNew && "Node emitted out of order - early");
 }
 
-/// EmitDbgValue - Generate any debug info that refers to this Node.  Constant
-/// dbg_value is not handled here.
-void
-InstrEmitter::EmitDbgValue(SDNode *Node,
-                           DenseMap<SDValue, unsigned> &VRBaseMap,
-                           SDDbgValue *sd) {
-  if (!Node->getHasDebugValue())
-    return;
-  if (!sd)
-    return;
-  assert(sd->getKind() == SDDbgValue::SDNODE);
-  unsigned VReg = getVR(SDValue(sd->getSDNode(), sd->getResNo()), VRBaseMap);
-  const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
-  DebugLoc DL = sd->getDebugLoc();
-  MachineInstr *MI;
-  if (VReg) {
-    MI = BuildMI(*MF, DL, II).addReg(VReg, RegState::Debug).
-                              addImm(sd->getOffset()).
-                              addMetadata(sd->getMDPtr());
-  } else {
-    // Insert an Undef so we can see what we dropped.
-    MI = BuildMI(*MF, DL, II).addReg(0U).addImm(sd->getOffset()).
-                                    addMetadata(sd->getMDPtr());
-  }
-  MBB->insert(InsertPos, MI);
-}
-
-/// EmitDbgValue - Generate debug info that does not refer to a SDNode.
-void
-InstrEmitter::EmitDbgValue(SDDbgValue *sd,
+/// EmitDbgValue - Generate machine instruction for a dbg_value node.
+///
+MachineInstr *InstrEmitter::EmitDbgValue(SDDbgValue *SD,
+                                         MachineBasicBlock *InsertBB,
+                                         DenseMap<SDValue, unsigned> &VRBaseMap,
                          DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
-  if (!sd)
-    return;
+  uint64_t Offset = SD->getOffset();
+  MDNode* MDPtr = SD->getMDPtr();
+  DebugLoc DL = SD->getDebugLoc();
+
   const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
-  uint64_t Offset = sd->getOffset();
-  MDNode* mdPtr = sd->getMDPtr();
-  SDDbgValue::DbgValueKind kind = sd->getKind();
-  DebugLoc DL = sd->getDebugLoc();
-  MachineInstr* MI;
-  if (kind == SDDbgValue::CONST) {
-    Value *V = sd->getConst();
+  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
+  if (SD->getKind() == SDDbgValue::SDNODE) {
+    AddOperand(&*MIB, SDValue(SD->getSDNode(), SD->getResNo()),
+               (*MIB).getNumOperands(), &II, VRBaseMap, true /*IsDebug*/);
+  } else if (SD->getKind() == SDDbgValue::CONST) {
+    Value *V = SD->getConst();
     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
-      MI = BuildMI(*MF, DL, II).addImm(CI->getZExtValue()).
-                                     addImm(Offset).addMetadata(mdPtr);
+      MIB.addImm(CI->getSExtValue());
     } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
-      MI = BuildMI(*MF, DL, II).addFPImm(CF).
-                                     addImm(Offset).addMetadata(mdPtr);
+      MIB.addFPImm(CF);
     } else {
       // Could be an Undef.  In any case insert an Undef so we can see what we
       // dropped.
-      MI = BuildMI(*MF, DL, II).addReg(0U).
-                                       addImm(Offset).addMetadata(mdPtr);
+      MIB.addReg(0U);
     }
-  } else if (kind == SDDbgValue::FRAMEIX) {
-    unsigned FrameIx = sd->getFrameIx();
+  } else if (SD->getKind() == SDDbgValue::FRAMEIX) {
+    unsigned FrameIx = SD->getFrameIx();
     // Stack address; this needs to be lowered in target-dependent fashion.
     // FIXME test that the target supports this somehow; if not emit Undef.
     // Create a pseudo for EmitInstrWithCustomInserter's consumption.
-    MI = BuildMI(*MF, DL, II).addImm(FrameIx).
-                                   addImm(Offset).addMetadata(mdPtr);
-    MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
-    InsertPos = MBB->end();
-    return;
+    MIB.addImm(FrameIx).addImm(Offset).addMetadata(MDPtr);
+    abort();
+    TLI->EmitInstrWithCustomInserter(&*MIB, InsertBB, EM);
+    return 0;
   } else {
     // Insert an Undef so we can see what we dropped.
-    MI = BuildMI(*MF, DL, II).addReg(0U).
-                                     addImm(Offset).addMetadata(mdPtr);
+    MIB.addReg(0U);
   }
-  MBB->insert(InsertPos, MI);
+
+  MIB.addImm(Offset).addMetadata(MDPtr);
+  return &*MIB;
 }
 
 /// EmitNode - Generate machine code for a node and needed dependencies.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h?rev=99469&r1=99468&r2=99469&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h Wed Mar 24 20:38:16 2010
@@ -64,7 +64,8 @@
   void AddRegisterOperand(MachineInstr *MI, SDValue Op,
                           unsigned IIOpNum,
                           const TargetInstrDesc *II,
-                          DenseMap<SDValue, unsigned> &VRBaseMap);
+                          DenseMap<SDValue, unsigned> &VRBaseMap,
+                          bool IsDebug = false);
 
   /// AddOperand - Add the specified operand to the specified machine instr.  II
   /// specifies the instruction information for the node, and IIOpNum is the
@@ -73,7 +74,8 @@
   void AddOperand(MachineInstr *MI, SDValue Op,
                   unsigned IIOpNum,
                   const TargetInstrDesc *II,
-                  DenseMap<SDValue, unsigned> &VRBaseMap);
+                  DenseMap<SDValue, unsigned> &VRBaseMap,
+                  bool IsDebug = false);
 
   /// EmitSubregNode - Generate machine code for subreg nodes.
   ///
@@ -98,16 +100,12 @@
   /// MachineInstr.
   static unsigned CountOperands(SDNode *Node);
 
-  /// EmitDbgValue - Generate any debug info that refers to this Node.  Constant
-  /// dbg_value is not handled here.
-  void EmitDbgValue(SDNode *Node,
-                    DenseMap<SDValue, unsigned> &VRBaseMap,
-                    SDDbgValue* sd);
-
-
-  /// EmitDbgValue - Generate a constant DBG_VALUE.  No node is involved.
-  void EmitDbgValue(SDDbgValue* sd,
-                DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
+  /// EmitDbgValue - Generate machine instruction for a dbg_value node.
+  ///
+  MachineInstr *EmitDbgValue(SDDbgValue *SD,
+                          MachineBasicBlock *InsertBB,
+                          DenseMap<SDValue, unsigned> &VRBaseMap,
+                          DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
 
   /// EmitNode - Generate machine code for a node and needed dependencies.
   ///

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h?rev=99469&r1=99468&r2=99469&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h Wed Mar 24 20:38:16 2010
@@ -47,10 +47,12 @@
   uint64_t Offset;
   DebugLoc DL;
   unsigned Order;
+  bool Invalid;
 public:
   // Constructor for non-constants.
   SDDbgValue(MDNode *mdP, SDNode *N, unsigned R, uint64_t off, DebugLoc dl,
-             unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O) {
+             unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
+                           Invalid(false) {
     kind = SDNODE;
     u.s.Node = N;
     u.s.ResNo = R;
@@ -97,6 +99,12 @@
   // Returns the SDNodeOrder.  This is the order of the preceding node in the
   // input.
   unsigned getOrder() { return Order; }
+
+  // setIsInvalidated / isInvalidated - Setter / getter of the "Invalidated"
+  // property. A SDDbgValue is invalid if the SDNode that produces the value is
+  // deleted.
+  void setIsInvalidated() { Invalid = true; }
+  bool isInvalidated() { return Invalid; }
 };
 
 } // end llvm namespace

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=99469&r1=99468&r2=99469&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Wed Mar 24 20:38:16 2010
@@ -23,6 +23,7 @@
 #include "llvm/Target/TargetSubtarget.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Support/Debug.h"
@@ -407,19 +408,67 @@
   }
 }
 
+namespace {
+  struct OrderSorter {
+    bool operator()(const std::pair<unsigned, MachineInstr*> &A,
+                    const std::pair<unsigned, MachineInstr*> &B) {
+      return A.first < B.first;
+    }
+  };
+}
+
+// ProcessSourceNode - Process nodes with source order numbers. These are added
+// to a vector which EmitSchedule use to determine how to insert dbg_value
+// instructions in the right order.
+static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
+                           InstrEmitter &Emitter,
+                           DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM,
+                           DenseMap<SDValue, unsigned> &VRBaseMap,
+                    SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
+                           SmallSet<unsigned, 8> &Seen) {
+  unsigned Order = DAG->GetOrdering(N);
+  if (!Order || !Seen.insert(Order))
+    return;
+
+  MachineBasicBlock *BB = Emitter.getBlock();
+  if (BB->empty() || BB->back().isPHI()) {
+    // Did not insert any instruction.
+    Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
+    return;
+  }
+
+  Orders.push_back(std::make_pair(Order, &BB->back()));
+  if (!N->getHasDebugValue())
+    return;
+  // Opportunistically insert immediate dbg_value uses, i.e. those with source
+  // order number right after the N.
+  MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
+  SmallVector<SDDbgValue*,2> &DVs = DAG->GetDbgValues(N);
+  for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
+    if (DVs[i]->isInvalidated())
+      continue;
+    unsigned DVOrder = DVs[i]->getOrder();
+    if (DVOrder == ++Order) {
+      // FIXME: If the source node with next higher order is scheduled before
+      // this could end up generating funky debug info.
+      MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], BB, VRBaseMap, EM);
+      Orders.push_back(std::make_pair(DVOrder, DbgMI));
+      BB->insert(InsertPos, DbgMI);
+      DVs[i]->setIsInvalidated();
+    }
+  }
+}
+
+
 /// EmitSchedule - Emit the machine code in scheduled order.
 MachineBasicBlock *ScheduleDAGSDNodes::
 EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
   InstrEmitter Emitter(BB, InsertPos);
   DenseMap<SDValue, unsigned> VRBaseMap;
   DenseMap<SUnit*, unsigned> CopyVRBaseMap;
-
-  // For now, any constant debug info nodes go at the beginning.
-  for (SDDbgInfo::ConstDbgIterator I = DAG->DbgConstBegin(),
-       E = DAG->DbgConstEnd(); I!=E; I++) {
-    Emitter.EmitDbgValue(*I, EM);
-    delete *I;
-  }
+  SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
+  SmallSet<unsigned, 8> Seen;
+  bool HasDbg = DAG->hasDebugValues();
 
   for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
     SUnit *SU = Sequence[i];
@@ -442,22 +491,72 @@
          N = N->getFlaggedNode())
       FlaggedNodes.push_back(N);
     while (!FlaggedNodes.empty()) {
+      SDNode *N = FlaggedNodes.back();
       Emitter.EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,
                        VRBaseMap, EM);
-      if (FlaggedNodes.back()->getHasDebugValue())
-        if (SDDbgValue *sd = DAG->GetDbgInfo(FlaggedNodes.back())) {
-          Emitter.EmitDbgValue(FlaggedNodes.back(), VRBaseMap, sd);
-          delete sd;
-        }
+      // Remember the the source order of the inserted instruction.
+      if (HasDbg)
+        ProcessSourceNode(N, DAG, Emitter, EM, VRBaseMap, Orders, Seen);
       FlaggedNodes.pop_back();
     }
     Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
                      VRBaseMap, EM);
-    if (SU->getNode()->getHasDebugValue())
-      if (SDDbgValue *sd = DAG->GetDbgInfo(SU->getNode())) {
-        Emitter.EmitDbgValue(SU->getNode(), VRBaseMap, sd);
-        delete sd;
+    // Remember the the source order of the inserted instruction.
+    if (HasDbg)
+      ProcessSourceNode(SU->getNode(), DAG, Emitter, EM, VRBaseMap, Orders,
+                        Seen);
+  }
+
+  // Insert all the dbg_value which have not already been inserted in source
+  // order sequence.
+  if (HasDbg) {
+    MachineBasicBlock::iterator BBBegin = BB->empty() ? BB->end() : BB->begin();
+    while (BBBegin != BB->end() && BBBegin->isPHI())
+      ++BBBegin;
+
+    // Sort the source order instructions and use the order to insert debug
+    // values.
+    std::sort(Orders.begin(), Orders.end(), OrderSorter());
+
+    SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
+    SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
+    // Now emit the rest according to source order.
+    unsigned LastOrder = 0;
+    MachineInstr *LastMI = 0;
+    for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
+      unsigned Order = Orders[i].first;
+      MachineInstr *MI = Orders[i].second;
+      // Insert all SDDbgValue's whose order(s) are before "Order".
+      if (!MI)
+        continue;
+      MachineBasicBlock *MIBB = MI->getParent();
+      for (; DI != DE &&
+             (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
+        if ((*DI)->isInvalidated())
+          continue;
+        MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, MIBB, VRBaseMap, EM);
+        if (!LastOrder)
+          // Insert to start of the BB (after PHIs).
+          BB->insert(BBBegin, DbgMI);
+        else {
+          MachineBasicBlock::iterator Pos = MI;
+          MIBB->insert(llvm::next(Pos), DbgMI);
+        }
       }
+      LastOrder = Order;
+      LastMI = MI;
+    }
+    // Add trailing DbgValue's before the terminator. FIXME: May want to add
+    // some of them before one or more conditional branches?
+    while (DI != DE) {
+      MachineBasicBlock *InsertBB = Emitter.getBlock();
+      MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator();
+      if (!(*DI)->isInvalidated()) {
+        MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, InsertBB, VRBaseMap, EM);
+        InsertBB->insert(Pos, DbgMI);
+      }
+      ++DI;
+    }
   }
 
   BB = Emitter.getBlock();

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=99469&r1=99468&r2=99469&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Mar 24 20:38:16 2010
@@ -598,8 +598,10 @@
   // Remove the ordering of this node.
   Ordering->remove(N);
 
-  // And its entry in the debug info table, if any.
-  DbgInfo->remove(N);
+  // If any of the SDDbgValue nodes refer to this SDNode, invalidate them.
+  SmallVector<SDDbgValue*, 2> &DbgVals = DbgInfo->getSDDbgValues(N);
+  for (unsigned i = 0, e = DbgVals.size(); i != e; ++i)
+    DbgVals[i]->setIsInvalidated();
 }
 
 /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
@@ -811,6 +813,7 @@
 SelectionDAG::~SelectionDAG() {
   allnodes_clear();
   delete Ordering;
+  DbgInfo->clear();
   delete DbgInfo;
 }
 
@@ -5241,24 +5244,12 @@
   return Ordering->getOrder(SD);
 }
 
-/// AssignDbgInfo - Assign debug info to the SDNode.
-void SelectionDAG::AssignDbgInfo(SDNode* SD, SDDbgValue* db) {
-  assert(SD && "Trying to assign dbg info to a null node!");
-  DbgInfo->add(SD, db);
-  SD->setHasDebugValue(true);
-}
-
-/// RememberDbgInfo - Remember debug info which is not assigned to an SDNode.
-void SelectionDAG::RememberDbgInfo(SDDbgValue* db) {
-  DbgInfo->add(db);
-}
-
-/// GetDbgInfo - Get the debug info, if any, for the SDNode.
-SDDbgValue* SelectionDAG::GetDbgInfo(const SDNode *SD) {
-  assert(SD && "Trying to get the order of a null node!");
-  if (SD->getHasDebugValue())
-    return DbgInfo->getSDDbgValue(SD);
-  return 0;
+/// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means the
+/// value is produced by SD.
+void SelectionDAG::AddDbgValue(SDDbgValue *DB, SDNode *SD) {
+  DbgInfo->add(DB, SD);
+  if (SD)
+    SD->setHasDebugValue(true);
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=99469&r1=99468&r2=99469&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Mar 24 20:38:16 2010
@@ -3825,20 +3825,20 @@
     ++SDNodeOrder;
     if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
       SDDbgValue* dv = new SDDbgValue(Variable, V, Offset, dl, SDNodeOrder);
-      DAG.RememberDbgInfo(dv);
+      DAG.AddDbgValue(dv);
     } else {
       SDValue &N = NodeMap[V];
       if (N.getNode()) {
         SDDbgValue *dv = new SDDbgValue(Variable, N.getNode(),
                                         N.getResNo(), Offset, dl, SDNodeOrder);
-        DAG.AssignDbgInfo(N.getNode(), dv);
+        DAG.AddDbgValue(dv, N.getNode());
       } else {
         // We may expand this to cover more cases.  One case where we have no
         // data available is an unreferenced parameter; we need this fallback.
         SDDbgValue* dv = new SDDbgValue(Variable, 
                                         UndefValue::get(V->getType()),
                                         Offset, dl, SDNodeOrder);
-        DAG.RememberDbgInfo(dv);
+        DAG.AddDbgValue(dv);
       }
     }
 




From echristo at apple.com  Wed Mar 24 20:46:07 2010
From: echristo at apple.com (Eric Christopher)
Date: Thu, 25 Mar 2010 01:46:07 -0000
Subject: [llvm-commits] [llvm] r99472 -
	/llvm/trunk/test/FrontendObjC/2010-03-17-StructRef.m
Message-ID: <20100325014607.9702F2A6C12C@llvm.org>

Author: echristo
Date: Wed Mar 24 20:46:07 2010
New Revision: 99472

URL: http://llvm.org/viewvc/llvm-project?rev=99472&view=rev
Log:
Make sure this runs in 64-bit only, 32-bit won't produce the correct stores.

Fariborz please review and make sure this is what you meant.

Modified:
    llvm/trunk/test/FrontendObjC/2010-03-17-StructRef.m

Modified: llvm/trunk/test/FrontendObjC/2010-03-17-StructRef.m
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendObjC/2010-03-17-StructRef.m?rev=99472&r1=99471&r2=99472&view=diff
==============================================================================
--- llvm/trunk/test/FrontendObjC/2010-03-17-StructRef.m (original)
+++ llvm/trunk/test/FrontendObjC/2010-03-17-StructRef.m Wed Mar 24 20:46:07 2010
@@ -1,4 +1,4 @@
-// RUN: %llvmgcc %s -S -o - | FileCheck %s
+// RUN: %llvmgcc %s -m64 -S -o - | FileCheck %s
 // Bitfield references must not touch memory outside of the enclosing
 // struct.   Radar 7639995
 typedef signed char BOOL;




From daniel at zuster.org  Wed Mar 24 21:00:02 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 02:00:02 -0000
Subject: [llvm-commits] [llvm] r99473 - in /llvm/trunk:
 include/llvm/MC/MCAsmLayout.h include/llvm/MC/MCAssembler.h
 lib/MC/MCAssembler.cpp lib/MC/MachObjectWriter.cpp
Message-ID: <20100325020002.A1C442A6C12C@llvm.org>

Author: ddunbar
Date: Wed Mar 24 21:00:02 2010
New Revision: 99473

URL: http://llvm.org/viewvc/llvm-project?rev=99473&view=rev
Log:
MC: Route access to Fragment offset and effective size through MCAsmLayout.

Modified:
    llvm/trunk/include/llvm/MC/MCAsmLayout.h
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/include/llvm/MC/MCAsmLayout.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmLayout.h?rev=99473&r1=99472&r2=99473&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmLayout.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmLayout.h Wed Mar 24 21:00:02 2010
@@ -35,6 +35,12 @@
 
   uint64_t getFragmentAddress(const MCFragment *F) const;
 
+  uint64_t getFragmentEffectiveSize(const MCFragment *F) const;
+  void setFragmentEffectiveSize(MCFragment *F, uint64_t Value);
+
+  uint64_t getFragmentOffset(const MCFragment *F) const;
+  void setFragmentOffset(MCFragment *F, uint64_t Value);
+
   uint64_t getSectionAddress(const MCSectionData *SD) const;
 
   uint64_t getSymbolAddress(const MCSymbolData *SD) const;

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99473&r1=99472&r2=99473&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Wed Mar 24 21:00:02 2010
@@ -87,8 +87,9 @@
   /// initialized.
   uint64_t Offset;
 
-  /// FileSize - The file size of this section. This is ~0 until initialized.
-  uint64_t FileSize;
+  /// EffectiveSize - The compute size of this section. This is ~0 until
+  /// initialized.
+  uint64_t EffectiveSize;
 
   /// @}
 
@@ -105,25 +106,6 @@
   MCSectionData *getParent() const { return Parent; }
   void setParent(MCSectionData *Value) { Parent = Value; }
 
-  /// @name Assembler Backend Support
-  /// @{
-  //
-  // FIXME: This could all be kept private to the assembler implementation.
-
-  uint64_t getFileSize() const {
-    assert(FileSize != ~UINT64_C(0) && "File size not set!");
-    return FileSize;
-  }
-  void setFileSize(uint64_t Value) { FileSize = Value; }
-
-  uint64_t getOffset() const {
-    assert(Offset != ~UINT64_C(0) && "File offset not set!");
-    return Offset;
-  }
-  void setOffset(uint64_t Value) { Offset = Value; }
-
-  /// @}
-
   static bool classof(const MCFragment *O) { return true; }
 
   virtual void dump();
@@ -711,7 +693,8 @@
   /// Emit the section contents using the given object writer.
   //
   // FIXME: Should MCAssembler always have a reference to the object writer?
-  void WriteSectionData(const MCSectionData *Section, MCObjectWriter *OW) const;
+  void WriteSectionData(const MCSectionData *Section, const MCAsmLayout &Layout,
+                        MCObjectWriter *OW) const;
 
 public:
   /// Construct a new assembler instance.

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99473&r1=99472&r2=99473&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Mar 24 21:00:02 2010
@@ -47,7 +47,25 @@
 
 uint64_t MCAsmLayout::getFragmentAddress(const MCFragment *F) const {
   assert(F->getParent() && "Missing section()!");
-  return getSectionAddress(F->getParent()) + F->getOffset();
+  return getSectionAddress(F->getParent()) + getFragmentOffset(F);
+}
+
+uint64_t MCAsmLayout::getFragmentEffectiveSize(const MCFragment *F) const {
+  assert(F->EffectiveSize != ~UINT64_C(0) && "Address not set!");
+  return F->EffectiveSize;
+}
+
+void MCAsmLayout::setFragmentEffectiveSize(MCFragment *F, uint64_t Value) {
+  F->EffectiveSize = Value;
+}
+
+uint64_t MCAsmLayout::getFragmentOffset(const MCFragment *F) const {
+  assert(F->Offset != ~UINT64_C(0) && "Address not set!");
+  return F->Offset;
+}
+
+void MCAsmLayout::setFragmentOffset(MCFragment *F, uint64_t Value) {
+  F->Offset = Value;
 }
 
 uint64_t MCAsmLayout::getSymbolAddress(const MCSymbolData *SD) const {
@@ -72,7 +90,7 @@
 MCFragment::MCFragment(FragmentType _Kind, MCSectionData *_Parent)
   : Kind(_Kind),
     Parent(_Parent),
-    FileSize(~UINT64_C(0))
+    EffectiveSize(~UINT64_C(0))
 {
   if (Parent)
     Parent->getFragmentList().push_back(this);
@@ -335,33 +353,33 @@
   for (MCSectionData::iterator it = SD.begin(), ie = SD.end(); it != ie; ++it) {
     MCFragment &F = *it;
 
-    F.setOffset(Address - StartAddress);
+    uint64_t FragmentOffset = Address - StartAddress;
+    Layout.setFragmentOffset(&F, FragmentOffset);
 
     // Evaluate fragment size.
+    uint64_t EffectiveSize = 0;
     switch (F.getKind()) {
     case MCFragment::FT_Align: {
       MCAlignFragment &AF = cast<MCAlignFragment>(F);
 
-      uint64_t Size = OffsetToAlignment(Address, AF.getAlignment());
-      if (Size > AF.getMaxBytesToEmit())
-        AF.setFileSize(0);
-      else
-        AF.setFileSize(Size);
+      EffectiveSize = OffsetToAlignment(Address, AF.getAlignment());
+      if (EffectiveSize > AF.getMaxBytesToEmit())
+        EffectiveSize = 0;
       break;
     }
 
     case MCFragment::FT_Data:
-      F.setFileSize(cast<MCDataFragment>(F).getContents().size());
+      EffectiveSize = cast<MCDataFragment>(F).getContents().size();
       break;
 
     case MCFragment::FT_Fill: {
       MCFillFragment &FF = cast<MCFillFragment>(F);
-      F.setFileSize(FF.getValueSize() * FF.getCount());
+      EffectiveSize = FF.getValueSize() * FF.getCount();
       break;
     }
 
     case MCFragment::FT_Inst:
-      F.setFileSize(cast<MCInstFragment>(F).getInstSize());
+      EffectiveSize = cast<MCInstFragment>(F).getInstSize();
       break;
 
     case MCFragment::FT_Org: {
@@ -372,12 +390,12 @@
         llvm_report_error("expected assembly-time absolute expression");
 
       // FIXME: We need a way to communicate this error.
-      int64_t Offset = TargetLocation - F.getOffset();
+      int64_t Offset = TargetLocation - FragmentOffset;
       if (Offset < 0)
         llvm_report_error("invalid .org offset '" + Twine(TargetLocation) +
-                          "' (at offset '" + Twine(F.getOffset()) + "'");
+                          "' (at offset '" + Twine(FragmentOffset) + "'");
 
-      F.setFileSize(Offset);
+      EffectiveSize = Offset;
       break;
     }
 
@@ -386,16 +404,18 @@
 
       // Align the fragment offset; it is safe to adjust the offset freely since
       // this is only in virtual sections.
+      //
+      // FIXME: We shouldn't be doing this here.
       Address = RoundUpToAlignment(Address, ZFF.getAlignment());
-      F.setOffset(Address - StartAddress);
+      Layout.setFragmentOffset(&F, Address - StartAddress);
 
-      // FIXME: This is misnamed.
-      F.setFileSize(ZFF.getSize());
+      EffectiveSize = ZFF.getSize();
       break;
     }
     }
 
-    Address += F.getFileSize();
+    Layout.setFragmentEffectiveSize(&F, EffectiveSize);
+    Address += EffectiveSize;
   }
 
   // Set the section sizes.
@@ -407,27 +427,28 @@
 }
 
 /// WriteFragmentData - Write the \arg F data to the output file.
-static void WriteFragmentData(const MCAssembler &Asm, const MCFragment &F,
-                              MCObjectWriter *OW) {
+static void WriteFragmentData(const MCAssembler &Asm, const MCAsmLayout &Layout,
+                              const MCFragment &F, MCObjectWriter *OW) {
   uint64_t Start = OW->getStream().tell();
   (void) Start;
 
   ++stats::EmittedFragments;
 
   // FIXME: Embed in fragments instead?
+  uint64_t FragmentSize = Layout.getFragmentEffectiveSize(&F);
   switch (F.getKind()) {
   case MCFragment::FT_Align: {
     MCAlignFragment &AF = cast<MCAlignFragment>(F);
-    uint64_t Count = AF.getFileSize() / AF.getValueSize();
+    uint64_t Count = FragmentSize / AF.getValueSize();
 
     // FIXME: This error shouldn't actually occur (the front end should emit
     // multiple .align directives to enforce the semantics it wants), but is
     // severe enough that we want to report it. How to handle this?
-    if (Count * AF.getValueSize() != AF.getFileSize())
+    if (Count * AF.getValueSize() != FragmentSize)
       llvm_report_error("undefined .align directive, value size '" +
                         Twine(AF.getValueSize()) +
                         "' is not a divisor of padding size '" +
-                        Twine(AF.getFileSize()) + "'");
+                        Twine(FragmentSize) + "'");
 
     // See if we are aligning with nops, and if so do that first to try to fill
     // the Count bytes.  Then if that did not fill any bytes or there are any
@@ -456,7 +477,7 @@
 
   case MCFragment::FT_Data: {
     MCDataFragment &DF = cast<MCDataFragment>(F);
-    assert(DF.getFileSize() == DF.getContents().size() && "Invalid size!");
+    assert(FragmentSize == DF.getContents().size() && "Invalid size!");
     OW->WriteBytes(DF.getContents().str());
     break;
   }
@@ -483,7 +504,7 @@
   case MCFragment::FT_Org: {
     MCOrgFragment &OF = cast<MCOrgFragment>(F);
 
-    for (uint64_t i = 0, e = OF.getFileSize(); i != e; ++i)
+    for (uint64_t i = 0, e = FragmentSize; i != e; ++i)
       OW->Write8(uint8_t(OF.getValue()));
 
     break;
@@ -495,10 +516,11 @@
   }
   }
 
-  assert(OW->getStream().tell() - Start == F.getFileSize());
+  assert(OW->getStream().tell() - Start == FragmentSize);
 }
 
 void MCAssembler::WriteSectionData(const MCSectionData *SD,
+                                   const MCAsmLayout &Layout,
                                    MCObjectWriter *OW) const {
   // Ignore virtual sections.
   if (getBackend().isVirtualSection(SD->getSection())) {
@@ -511,7 +533,7 @@
 
   for (MCSectionData::const_iterator it = SD->begin(),
          ie = SD->end(); it != ie; ++it)
-    WriteFragmentData(*this, *it, OW);
+    WriteFragmentData(*this, Layout, *it, OW);
 
   // Add section padding.
   assert(SD->getFileSize() >= SD->getSize() && "Invalid section sizes!");
@@ -735,9 +757,11 @@
       SD.getFragmentList().insert(it2, DF);
 
       // Update the data fragments layout data.
+      //
+      // FIXME: Add MCAsmLayout utility for this.
       DF->setParent(IF->getParent());
-      DF->setOffset(IF->getOffset());
-      DF->setFileSize(IF->getInstSize());
+      Layout.setFragmentOffset(DF, Layout.getFragmentOffset(IF));
+      Layout.setFragmentEffectiveSize(DF, Layout.getFragmentEffectiveSize(IF));
 
       // Copy in the data and the fixups.
       DF->getContents().append(IF->getCode().begin(), IF->getCode().end());
@@ -767,7 +791,7 @@
   raw_ostream &OS = llvm::errs();
 
   OS << "<MCFragment " << (void*) this << " Offset:" << Offset
-     << " FileSize:" << FileSize;
+     << " EffectiveSize:" << EffectiveSize;
 
   OS << ">";
 }

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=99473&r1=99472&r2=99473&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Wed Mar 24 21:00:02 2010
@@ -461,7 +461,7 @@
     unsigned Log2Size = getFixupKindLog2Size(Fixup.Kind);
 
     // See <reloc.h>.
-    uint32_t Address = Fragment->getOffset() + Fixup.Offset;
+    uint32_t Address = Layout.getFragmentOffset(Fragment) + Fixup.Offset;
     int64_t Value = 0;
     unsigned Index = 0;
     unsigned IsExtern = 0;
@@ -645,7 +645,7 @@
                                  const MCFragment *Fragment,
                                  const MCAsmFixup &Fixup, MCValue Target,
                                  uint64_t &FixedValue) {
-    uint32_t Address = Fragment->getOffset() + Fixup.Offset;
+    uint32_t Address = Layout.getFragmentOffset(Fragment) + Fixup.Offset;
     unsigned IsPCRel = isFixupKindPCRel(Fixup.Kind);
     unsigned Log2Size = getFixupKindLog2Size(Fixup.Kind);
     unsigned Type = RIT_Vanilla;
@@ -723,7 +723,7 @@
     }
 
     // See <reloc.h>.
-    uint32_t Address = Fragment->getOffset() + Fixup.Offset;
+    uint32_t Address = Layout.getFragmentOffset(Fragment) + Fixup.Offset;
     uint32_t Value = 0;
     unsigned Index = 0;
     unsigned IsExtern = 0;
@@ -1036,7 +1036,7 @@
     // Write the actual section data.
     for (MCAssembler::const_iterator it = Asm.begin(),
            ie = Asm.end(); it != ie; ++it)
-      Asm.WriteSectionData(it, Writer);
+      Asm.WriteSectionData(it, Layout, Writer);
 
     // Write the extra padding.
     WriteZeros(SectionDataPadding);




From daniel at zuster.org  Wed Mar 24 21:00:07 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 02:00:07 -0000
Subject: [llvm-commits] [llvm] r99474 - in /llvm/trunk:
 include/llvm/MC/MCAsmLayout.h include/llvm/MC/MCAssembler.h
 lib/MC/MCAssembler.cpp lib/MC/MachObjectWriter.cpp
Message-ID: <20100325020007.417492A6C12D@llvm.org>

Author: ddunbar
Date: Wed Mar 24 21:00:07 2010
New Revision: 99474

URL: http://llvm.org/viewvc/llvm-project?rev=99474&view=rev
Log:
MC: Route access to SectionData offset and file size through MCAsmLayout.

Modified:
    llvm/trunk/include/llvm/MC/MCAsmLayout.h
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/include/llvm/MC/MCAsmLayout.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmLayout.h?rev=99474&r1=99473&r2=99474&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmLayout.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmLayout.h Wed Mar 24 21:00:07 2010
@@ -33,19 +33,58 @@
   /// Get the assembler object this is a layout for.
   MCAssembler &getAssembler() const { return Assembler; }
 
-  uint64_t getFragmentAddress(const MCFragment *F) const;
+  /// @name Fragment Layout Data
+  /// @{
 
+  /// \brief Get the effective size of the given fragment, as computed in the
+  /// current layout.
   uint64_t getFragmentEffectiveSize(const MCFragment *F) const;
+
+  /// \brief Set the effective size of the given fragment.
   void setFragmentEffectiveSize(MCFragment *F, uint64_t Value);
 
+  /// \brief Get the offset of the given fragment inside its containing section.
   uint64_t getFragmentOffset(const MCFragment *F) const;
+
+  /// \brief Set the offset of the given fragment inside its containing section.
   void setFragmentOffset(MCFragment *F, uint64_t Value);
 
+  /// @}
+  /// @name Section Layout Data
+  /// @{
+
+  /// \brief Get the computed address of the given section.
   uint64_t getSectionAddress(const MCSectionData *SD) const;
 
+  /// \brief Set the computed address of the given section.
+  void setSectionAddress(MCSectionData *SD, uint64_t Value);
+
+  /// \brief Get the data size of the given section, as emitted to the object
+  /// file. This may include additional padding, or be 0 for virtual sections.
+  uint64_t getSectionFileSize(const MCSectionData *SD) const;
+
+  /// \brief Set the data size of the given section.
+  void setSectionFileSize(MCSectionData *SD, uint64_t Value);
+
+  /// \brief Get the actual data size of the given section.
+  uint64_t getSectionSize(const MCSectionData *SD) const;
+
+  /// \brief Set the actual data size of the given section.
+  void setSectionSize(MCSectionData *SD, uint64_t Value);
+
+  /// @}
+  /// @name Utility Functions
+  /// @{
+
+  /// \brief Get the address of the given fragment, as computed in the current
+  /// layout.
+  uint64_t getFragmentAddress(const MCFragment *F) const;
+
+  /// \brief Get the address of the given symbol, as computed in the current
+  /// layout.
   uint64_t getSymbolAddress(const MCSymbolData *SD) const;
 
-  void setSectionAddress(MCSectionData *SD, uint64_t Value);
+  /// @}
 };
 
 } // end namespace llvm

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99474&r1=99473&r2=99474&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Wed Mar 24 21:00:07 2010
@@ -425,6 +425,9 @@
   unsigned getAlignment() const { return Alignment; }
   void setAlignment(unsigned Value) { Alignment = Value; }
 
+  bool hasInstructions() const { return HasInstructions; }
+  void setHasInstructions(bool Value) { HasInstructions = Value; }
+
   /// @name Fragment Access
   /// @{
 
@@ -447,29 +450,6 @@
 
   bool empty() const { return Fragments.empty(); }
 
-  /// @}
-  /// @name Assembler Backend Support
-  /// @{
-  //
-  // FIXME: This could all be kept private to the assembler implementation.
-
-  uint64_t getSize() const {
-    assert(Size != ~UINT64_C(0) && "File size not set!");
-    return Size;
-  }
-  void setSize(uint64_t Value) { Size = Value; }
-
-  uint64_t getFileSize() const {
-    assert(FileSize != ~UINT64_C(0) && "File size not set!");
-    return FileSize;
-  }
-  void setFileSize(uint64_t Value) { FileSize = Value; }
-
-  bool hasInstructions() const { return HasInstructions; }
-  void setHasInstructions(bool Value) { HasInstructions = Value; }
-
-  /// @}
-
   void dump();
 };
 

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99474&r1=99473&r2=99474&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Mar 24 21:00:07 2010
@@ -82,6 +82,24 @@
   SD->Address = Value;
 }
 
+uint64_t MCAsmLayout::getSectionSize(const MCSectionData *SD) const {
+  assert(SD->Size != ~UINT64_C(0) && "File size not set!");
+  return SD->Size;
+}
+void MCAsmLayout::setSectionSize(MCSectionData *SD, uint64_t Value) {
+  SD->Size = Value;
+}
+
+uint64_t MCAsmLayout::getSectionFileSize(const MCSectionData *SD) const {
+  assert(SD->FileSize != ~UINT64_C(0) && "File size not set!");
+  return SD->FileSize;
+}
+void MCAsmLayout::setSectionFileSize(MCSectionData *SD, uint64_t Value) {
+  SD->FileSize = Value;
+}
+
+  /// @}
+
 /* *** */
 
 MCFragment::MCFragment() : Kind(FragmentType(~0)) {
@@ -419,11 +437,11 @@
   }
 
   // Set the section sizes.
-  SD.setSize(Address - StartAddress);
+  Layout.setSectionSize(&SD, Address - StartAddress);
   if (getBackend().isVirtualSection(SD.getSection()))
-    SD.setFileSize(0);
+    Layout.setSectionFileSize(&SD, 0);
   else
-    SD.setFileSize(Address - StartAddress);
+    Layout.setSectionFileSize(&SD, Address - StartAddress);
 }
 
 /// WriteFragmentData - Write the \arg F data to the output file.
@@ -522,9 +540,12 @@
 void MCAssembler::WriteSectionData(const MCSectionData *SD,
                                    const MCAsmLayout &Layout,
                                    MCObjectWriter *OW) const {
+  uint64_t SectionSize = Layout.getSectionSize(SD);
+  uint64_t SectionFileSize = Layout.getSectionFileSize(SD);
+
   // Ignore virtual sections.
   if (getBackend().isVirtualSection(SD->getSection())) {
-    assert(SD->getFileSize() == 0);
+    assert(SectionFileSize == 0 && "Invalid size for section!");
     return;
   }
 
@@ -536,10 +557,10 @@
     WriteFragmentData(*this, Layout, *it, OW);
 
   // Add section padding.
-  assert(SD->getFileSize() >= SD->getSize() && "Invalid section sizes!");
-  OW->WriteZeros(SD->getFileSize() - SD->getSize());
+  assert(SectionFileSize >= SectionSize && "Invalid section sizes!");
+  OW->WriteZeros(SectionFileSize - SectionSize);
 
-  assert(OW->getStream().tell() - Start == SD->getFileSize());
+  assert(OW->getStream().tell() - Start == SectionFileSize);
 }
 
 void MCAssembler::Finish() {
@@ -652,14 +673,14 @@
     // section.
     if (uint64_t Pad = OffsetToAlignment(Address, it->getAlignment())) {
       assert(Prev && "Missing prev section!");
-      Prev->setFileSize(Prev->getFileSize() + Pad);
+      Layout.setSectionFileSize(Prev, Layout.getSectionFileSize(Prev) + Pad);
       Address += Pad;
     }
 
     // Layout the section fragments and its size.
     Layout.setSectionAddress(&SD, Address);
     LayoutSection(SD, Layout);
-    Address += SD.getFileSize();
+    Address += Layout.getSectionFileSize(&SD);
 
     Prev = &SD;
   }
@@ -678,7 +699,7 @@
 
     Layout.setSectionAddress(&SD, Address);
     LayoutSection(SD, Layout);
-    Address += SD.getSize();
+    Address += Layout.getSectionSize(&SD);
   }
 
   // Scan for fragments that need relaxation.

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=99474&r1=99473&r2=99474&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Wed Mar 24 21:00:07 2010
@@ -275,9 +275,12 @@
   void WriteSection(const MCAssembler &Asm, const MCAsmLayout &Layout,
                     const MCSectionData &SD, uint64_t FileOffset,
                     uint64_t RelocationsStart, unsigned NumRelocations) {
+    uint64_t SectionSize = Layout.getSectionSize(&SD);
+    uint64_t SectionFileSize = Layout.getSectionFileSize(&SD);
+
     // The offset is unused for virtual sections.
     if (Asm.getBackend().isVirtualSection(SD.getSection())) {
-      assert(SD.getFileSize() == 0 && "Invalid file size!");
+      assert(SectionFileSize == 0 && "Invalid file size!");
       FileOffset = 0;
     }
 
@@ -294,10 +297,10 @@
     WriteBytes(Section.getSegmentName(), 16);
     if (Is64Bit) {
       Write64(Layout.getSectionAddress(&SD)); // address
-      Write64(SD.getSize()); // size
+      Write64(SectionSize); // size
     } else {
       Write32(Layout.getSectionAddress(&SD)); // address
-      Write32(SD.getSize()); // size
+      Write32(SectionSize); // size
     }
     Write32(FileOffset);
 
@@ -965,15 +968,16 @@
            ie = Asm.end(); it != ie; ++it) {
       const MCSectionData &SD = *it;
       uint64_t Address = Layout.getSectionAddress(&SD);
+      uint64_t Size = Layout.getSectionSize(&SD);
+      uint64_t FileSize = Layout.getSectionFileSize(&SD);
 
-      VMSize = std::max(VMSize, Address + SD.getSize());
+      VMSize = std::max(VMSize, Address + Size);
 
       if (Asm.getBackend().isVirtualSection(SD.getSection()))
         continue;
 
-      SectionDataSize = std::max(SectionDataSize, Address + SD.getSize());
-      SectionDataFileSize = std::max(SectionDataFileSize,
-                                     Address + SD.getFileSize());
+      SectionDataSize = std::max(SectionDataSize, Address + Size);
+      SectionDataFileSize = std::max(SectionDataFileSize, Address + FileSize);
     }
 
     // The section data is padded to 4 bytes.




From sabre at nondot.org  Wed Mar 24 23:41:17 2010
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 25 Mar 2010 04:41:17 -0000
Subject: [llvm-commits] [llvm] r99482 - in
 /llvm/trunk/lib/CodeGen/SelectionDAG: InstrEmitter.cpp InstrEmitter.h
Message-ID: <20100325044117.15F512A6C12C@llvm.org>

Author: lattner
Date: Wed Mar 24 23:41:16 2010
New Revision: 99482

URL: http://llvm.org/viewvc/llvm-project?rev=99482&view=rev
Log:
reapply 99444/99445, which I speculatively reverted in
r99453.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=99482&r1=99481&r2=99482&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Wed Mar 24 23:41:16 2010
@@ -548,93 +548,98 @@
   return &*MIB;
 }
 
-/// EmitNode - Generate machine code for a node and needed dependencies.
+/// EmitMachineNode - Generate machine code for a target-specific node and
+/// needed dependencies.
 ///
-void InstrEmitter::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
-                            DenseMap<SDValue, unsigned> &VRBaseMap,
-                         DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
-  // If machine instruction
-  if (Node->isMachineOpcode()) {
-    unsigned Opc = Node->getMachineOpcode();
-    
-    // Handle subreg insert/extract specially
-    if (Opc == TargetOpcode::EXTRACT_SUBREG || 
-        Opc == TargetOpcode::INSERT_SUBREG ||
-        Opc == TargetOpcode::SUBREG_TO_REG) {
-      EmitSubregNode(Node, VRBaseMap);
-      return;
-    }
+void InstrEmitter::
+EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
+                DenseMap<SDValue, unsigned> &VRBaseMap,
+                DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
+  unsigned Opc = Node->getMachineOpcode();
+  
+  // Handle subreg insert/extract specially
+  if (Opc == TargetOpcode::EXTRACT_SUBREG || 
+      Opc == TargetOpcode::INSERT_SUBREG ||
+      Opc == TargetOpcode::SUBREG_TO_REG) {
+    EmitSubregNode(Node, VRBaseMap);
+    return;
+  }
 
-    // Handle COPY_TO_REGCLASS specially.
-    if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
-      EmitCopyToRegClassNode(Node, VRBaseMap);
-      return;
-    }
+  // Handle COPY_TO_REGCLASS specially.
+  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
+    EmitCopyToRegClassNode(Node, VRBaseMap);
+    return;
+  }
 
-    if (Opc == TargetOpcode::IMPLICIT_DEF)
-      // We want a unique VR for each IMPLICIT_DEF use.
-      return;
-    
-    const TargetInstrDesc &II = TII->get(Opc);
-    unsigned NumResults = CountResults(Node);
-    unsigned NodeOperands = CountOperands(Node);
-    bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
-                          II.getImplicitDefs() != 0;
+  if (Opc == TargetOpcode::IMPLICIT_DEF)
+    // We want a unique VR for each IMPLICIT_DEF use.
+    return;
+  
+  const TargetInstrDesc &II = TII->get(Opc);
+  unsigned NumResults = CountResults(Node);
+  unsigned NodeOperands = CountOperands(Node);
+  bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
+                        II.getImplicitDefs() != 0;
 #ifndef NDEBUG
-    unsigned NumMIOperands = NodeOperands + NumResults;
-    assert((II.getNumOperands() == NumMIOperands ||
-            HasPhysRegOuts || II.isVariadic()) &&
-           "#operands for dag node doesn't match .td file!"); 
+  unsigned NumMIOperands = NodeOperands + NumResults;
+  assert((II.getNumOperands() == NumMIOperands ||
+          HasPhysRegOuts || II.isVariadic()) &&
+         "#operands for dag node doesn't match .td file!"); 
 #endif
 
-    // Create the new machine instruction.
-    MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
-    
-    // Add result register values for things that are defined by this
-    // instruction.
-    if (NumResults)
-      CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
-    
-    // Emit all of the actual operands of this instruction, adding them to the
-    // instruction as appropriate.
-    bool HasOptPRefs = II.getNumDefs() > NumResults;
-    assert((!HasOptPRefs || !HasPhysRegOuts) &&
-           "Unable to cope with optional defs and phys regs defs!");
-    unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
-    for (unsigned i = NumSkip; i != NodeOperands; ++i)
-      AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
-                 VRBaseMap);
-
-    // Transfer all of the memory reference descriptions of this instruction.
-    MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
-                   cast<MachineSDNode>(Node)->memoperands_end());
-
-    if (II.usesCustomInsertionHook()) {
-      // Insert this instruction into the basic block using a target
-      // specific inserter which may returns a new basic block.
-      MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
-      InsertPos = MBB->end();
-    } else {
-      MBB->insert(InsertPos, MI);
-    }
+  // Create the new machine instruction.
+  MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
+  
+  // Add result register values for things that are defined by this
+  // instruction.
+  if (NumResults)
+    CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
+  
+  // Emit all of the actual operands of this instruction, adding them to the
+  // instruction as appropriate.
+  bool HasOptPRefs = II.getNumDefs() > NumResults;
+  assert((!HasOptPRefs || !HasPhysRegOuts) &&
+         "Unable to cope with optional defs and phys regs defs!");
+  unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
+  for (unsigned i = NumSkip; i != NodeOperands; ++i)
+    AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
+               VRBaseMap);
+
+  // Transfer all of the memory reference descriptions of this instruction.
+  MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
+                 cast<MachineSDNode>(Node)->memoperands_end());
+
+  if (II.usesCustomInsertionHook()) {
+    // Insert this instruction into the basic block using a target
+    // specific inserter which may returns a new basic block.
+    MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
+    InsertPos = MBB->end();
+  } else {
+    MBB->insert(InsertPos, MI);
+  }
 
-    // Additional results must be an physical register def.
-    if (HasPhysRegOuts) {
-      for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
-        unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
-        if (Node->hasAnyUseOfValue(i))
-          EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
-        // If there are no uses, mark the register as dead now, so that
-        // MachineLICM/Sink can see that it's dead. Don't do this if the
-        // node has a Flag value, for the benefit of targets still using
-        // Flag for values in physregs.
-        else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
-          MI->addRegisterDead(Reg, TRI);
-      }
+  // Additional results must be an physical register def.
+  if (HasPhysRegOuts) {
+    for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
+      unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
+      if (Node->hasAnyUseOfValue(i))
+        EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
+      // If there are no uses, mark the register as dead now, so that
+      // MachineLICM/Sink can see that it's dead. Don't do this if the
+      // node has a Flag value, for the benefit of targets still using
+      // Flag for values in physregs.
+      else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
+        MI->addRegisterDead(Reg, TRI);
     }
-    return;
   }
+  return;
+}
 
+/// EmitSpecialNode - Generate machine code for a target-independent node and
+/// needed dependencies.
+void InstrEmitter::
+EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
+                DenseMap<SDValue, unsigned> &VRBaseMap) {
   switch (Node->getOpcode()) {
   default:
 #ifndef NDEBUG

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h?rev=99482&r1=99481&r2=99482&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h Wed Mar 24 23:41:16 2010
@@ -111,7 +111,12 @@
   ///
   void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
                 DenseMap<SDValue, unsigned> &VRBaseMap,
-                DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
+                DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
+    if (Node->isMachineOpcode())
+      EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap, EM);
+    else
+      EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap);
+  }
 
   /// getBlock - Return the current basic block.
   MachineBasicBlock *getBlock() { return MBB; }
@@ -122,6 +127,13 @@
   /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
   /// at the given position in the given block.
   InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos);
+  
+private:
+  void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
+                       DenseMap<SDValue, unsigned> &VRBaseMap,
+                       DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
+  void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
+                       DenseMap<SDValue, unsigned> &VRBaseMap);
 };
 
 }




From echristo at apple.com  Wed Mar 24 23:49:11 2010
From: echristo at apple.com (Eric Christopher)
Date: Thu, 25 Mar 2010 04:49:11 -0000
Subject: [llvm-commits] [llvm] r99483 - in /llvm/trunk:
 include/llvm/Instructions.h include/llvm/Support/CallSite.h
 lib/Analysis/InlineCost.cpp lib/VMCore/Instructions.cpp
 test/Transforms/Inline/noinline.ll
Message-ID: <20100325044911.29E682A6C12D@llvm.org>

Author: echristo
Date: Wed Mar 24 23:49:10 2010
New Revision: 99483

URL: http://llvm.org/viewvc/llvm-project?rev=99483&view=rev
Log:
Reapply r99451 with a fix to move the NoInline check to the cost functions
instead of InlineFunction.

Added:
    llvm/trunk/test/Transforms/Inline/noinline.ll
      - copied unchanged from r99450, llvm/trunk/test/Transforms/Inline/noinline.ll
Modified:
    llvm/trunk/include/llvm/Instructions.h
    llvm/trunk/include/llvm/Support/CallSite.h
    llvm/trunk/lib/Analysis/InlineCost.cpp
    llvm/trunk/lib/VMCore/Instructions.cpp

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=99483&r1=99482&r2=99483&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Wed Mar 24 23:49:10 2010
@@ -971,6 +971,13 @@
   unsigned getParamAlignment(unsigned i) const {
     return AttributeList.getParamAlignment(i);
   }
+  
+  /// @brief Return true if the call should not be inlined.
+  bool isNoInline() const { return paramHasAttr(~0, Attribute::NoInline); }
+  void setIsNoInline(bool Value) {
+    if (Value) addAttribute(~0, Attribute::NoInline);
+    else removeAttribute(~0, Attribute::NoInline);
+  }
 
   /// @brief Determine if the call does not access memory.
   bool doesNotAccessMemory() const {
@@ -2456,6 +2463,13 @@
     return AttributeList.getParamAlignment(i);
   }
 
+  /// @brief Return true if the call should not be inlined.
+  bool isNoInline() const { return paramHasAttr(~0, Attribute::NoInline); }
+  void setIsNoInline(bool Value) {
+    if (Value) addAttribute(~0, Attribute::NoInline);
+    else removeAttribute(~0, Attribute::NoInline);
+  }
+  
   /// @brief Determine if the call does not access memory.
   bool doesNotAccessMemory() const {
     return paramHasAttr(~0, Attribute::ReadNone);

Modified: llvm/trunk/include/llvm/Support/CallSite.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=99483&r1=99482&r2=99483&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CallSite.h (original)
+++ llvm/trunk/include/llvm/Support/CallSite.h Wed Mar 24 23:49:10 2010
@@ -76,6 +76,10 @@
   /// @brief Extract the alignment for a call or parameter (0=unknown).
   uint16_t getParamAlignment(uint16_t i) const;
 
+  /// @brief Return true if the call should not be inlined.
+  bool isNoInline() const;
+  void setIsNoInline(bool Value = true);
+  
   /// @brief Determine if the call does not access memory.
   bool doesNotAccessMemory() const;
   void setDoesNotAccessMemory(bool doesNotAccessMemory = true);

Modified: llvm/trunk/lib/Analysis/InlineCost.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=99483&r1=99482&r2=99483&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InlineCost.cpp (original)
+++ llvm/trunk/lib/Analysis/InlineCost.cpp Wed Mar 24 23:49:10 2010
@@ -255,9 +255,11 @@
   Function *Caller = TheCall->getParent()->getParent();
 
   // Don't inline functions which can be redefined at link-time to mean
-  // something else.  Don't inline functions marked noinline.
+  // something else.  Don't inline functions marked noinline or call sites
+  // marked noinline.
   if (Callee->mayBeOverridden() ||
-      Callee->hasFnAttr(Attribute::NoInline) || NeverInline.count(Callee))
+      Callee->hasFnAttr(Attribute::NoInline) || NeverInline.count(Callee) ||
+      CS.isNoInline())
     return llvm::InlineCost::getNever();
 
   // InlineCost - This value measures how good of an inline candidate this call

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=99483&r1=99482&r2=99483&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Wed Mar 24 23:49:10 2010
@@ -31,13 +31,13 @@
 //===----------------------------------------------------------------------===//
 
 #define CALLSITE_DELEGATE_GETTER(METHOD) \
-  Instruction *II(getInstruction());     \
+  Instruction *II = getInstruction();    \
   return isCall()                        \
     ? cast<CallInst>(II)->METHOD         \
     : cast<InvokeInst>(II)->METHOD
 
 #define CALLSITE_DELEGATE_SETTER(METHOD) \
-  Instruction *II(getInstruction());     \
+  Instruction *II = getInstruction();    \
   if (isCall())                          \
     cast<CallInst>(II)->METHOD;          \
   else                                   \
@@ -66,6 +66,17 @@
 uint16_t CallSite::getParamAlignment(uint16_t i) const {
   CALLSITE_DELEGATE_GETTER(getParamAlignment(i));
 }
+
+/// @brief Return true if the call should not be inlined.
+bool CallSite::isNoInline() const {
+  CALLSITE_DELEGATE_GETTER(isNoInline());
+}
+
+void CallSite::setIsNoInline(bool Value) {
+  CALLSITE_DELEGATE_GETTER(setIsNoInline(Value));
+}
+
+
 bool CallSite::doesNotAccessMemory() const {
   CALLSITE_DELEGATE_GETTER(doesNotAccessMemory());
 }




From clattner at apple.com  Wed Mar 24 23:57:50 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 24 Mar 2010 21:57:50 -0700
Subject: [llvm-commits] [llvm] r99483 - in /llvm/trunk:
	include/llvm/Instructions.h include/llvm/Support/CallSite.h
	lib/Analysis/InlineCost.cpp lib/VMCore/Instructions.cpp
	test/Transforms/Inline/noinline.ll
In-Reply-To: <20100325044911.29E682A6C12D@llvm.org>
References: <20100325044911.29E682A6C12D@llvm.org>
Message-ID: <68335DD1-36B6-4A26-AD1A-8FE2F7490399@apple.com>


On Mar 24, 2010, at 9:49 PM, Eric Christopher wrote:

> Author: echristo
> Date: Wed Mar 24 23:49:10 2010
> New Revision: 99483
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99483&view=rev
> Log:
> Reapply r99451 with a fix to move the NoInline check to the cost functions
> instead of InlineFunction.

Cool thanks... but what's the difference?

-Chris


From echristo at apple.com  Thu Mar 25 00:05:30 2010
From: echristo at apple.com (Eric Christopher)
Date: Wed, 24 Mar 2010 22:05:30 -0700
Subject: [llvm-commits] [llvm] r99483 - in /llvm/trunk:
	include/llvm/Instructions.h include/llvm/Support/CallSite.h
	lib/Analysis/InlineCost.cpp lib/VMCore/Instructions.cpp
	test/Transforms/Inline/noinline.ll
In-Reply-To: <68335DD1-36B6-4A26-AD1A-8FE2F7490399@apple.com>
References: <20100325044911.29E682A6C12D@llvm.org>
	<68335DD1-36B6-4A26-AD1A-8FE2F7490399@apple.com>
Message-ID: <F3CAEC09-004F-4A44-B3AF-1EDFD1D8ED26@apple.com>


On Mar 24, 2010, at 9:57 PM, Chris Lattner wrote:

> 
> On Mar 24, 2010, at 9:49 PM, Eric Christopher wrote:
> 
>> Author: echristo
>> Date: Wed Mar 24 23:49:10 2010
>> New Revision: 99483
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99483&view=rev
>> Log:
>> Reapply r99451 with a fix to move the NoInline check to the cost functions
>> instead of InlineFunction.
> 
> Cool thanks... but what's the difference?

It allows someone to call InlineFunction if they decide they really want to inline something and the inliner pass will use the costs - including NeverInline from the CallSite.

-eric


From clattner at apple.com  Thu Mar 25 00:33:46 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 24 Mar 2010 22:33:46 -0700
Subject: [llvm-commits] [llvm] r99483 - in /llvm/trunk:
	include/llvm/Instructions.h include/llvm/Support/CallSite.h
	lib/Analysis/InlineCost.cpp lib/VMCore/Instructions.cpp
	test/Transforms/Inline/noinline.ll
In-Reply-To: <F3CAEC09-004F-4A44-B3AF-1EDFD1D8ED26@apple.com>
References: <20100325044911.29E682A6C12D@llvm.org>
	<68335DD1-36B6-4A26-AD1A-8FE2F7490399@apple.com>
	<F3CAEC09-004F-4A44-B3AF-1EDFD1D8ED26@apple.com>
Message-ID: <6153B5DA-993B-4F80-9569-CFA3A99A0231@apple.com>


On Mar 24, 2010, at 10:05 PM, Eric Christopher wrote:

>>> URL: http://llvm.org/viewvc/llvm-project?rev=99483&view=rev
>>> Log:
>>> Reapply r99451 with a fix to move the NoInline check to the cost functions
>>> instead of InlineFunction.
>> 
>> Cool thanks... but what's the difference?
> 
> It allows someone to call InlineFunction if they decide they really want to inline something and the inliner pass will use the costs - including NeverInline from the CallSite.

Very weird, but ok.

-Chris


From dpatel at apple.com  Thu Mar 25 00:36:13 2010
From: dpatel at apple.com (Devang Patel)
Date: Thu, 25 Mar 2010 05:36:13 -0000
Subject: [llvm-commits] [llvm] r99484 - /llvm/trunk/lib/VMCore/Metadata.cpp
Message-ID: <20100325053613.C5D3B2A6C12C@llvm.org>

Author: dpatel
Date: Thu Mar 25 00:36:13 2010
New Revision: 99484

URL: http://llvm.org/viewvc/llvm-project?rev=99484&view=rev
Log:
Include isFunctionLocal while calculating folding node set provide for a MDNode.

Modified:
    llvm/trunk/lib/VMCore/Metadata.cpp

Modified: llvm/trunk/lib/VMCore/Metadata.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=99484&r1=99483&r2=99484&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Metadata.cpp (original)
+++ llvm/trunk/lib/VMCore/Metadata.cpp Thu Mar 25 00:36:13 2010
@@ -248,6 +248,7 @@
 void MDNode::Profile(FoldingSetNodeID &ID) const {
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
     ID.AddPointer(getOperand(i));
+  ID.AddBoolean(isFunctionLocal());
 }
 
 void MDNode::setIsNotUniqued() {




From anton at korobeynikov.info  Thu Mar 25 00:38:04 2010
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Thu, 25 Mar 2010 08:38:04 +0300
Subject: [llvm-commits] [llvm] r99436 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrInfo.td ARMInstrVFP.td
	ARMSubtarget.cpp ARMSubtarget.h
In-Reply-To: <20100324223146.6B1C42A6C12C@llvm.org>
References: <20100324223146.6B1C42A6C12C@llvm.org>
Message-ID: <b087fca01003242238s24d448c4m188564c3a1985887@mail.gmail.com>

Hi, Jim

> Make the use of the vmla and vmls VFP instructions controllable via cmd line.
> Preliminary testing shows significant performance wins by not using these
> instructions.
not using where? I believe this should be made conditional on A8 only.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From sabre at nondot.org  Thu Mar 25 00:40:48 2010
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 25 Mar 2010 05:40:48 -0000
Subject: [llvm-commits] [llvm] r99485 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/InstrEmitter.cpp
 test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
 test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
 test/CodeGen/X86/coalesce-esp.ll test/CodeGen/X86/licm-symbol.ll
 test/CodeGen/X86/phys_subreg_coalesce-2.ll test/CodeGen/X86/pr2659.ll
Message-ID: <20100325054048.CDB172A6C12C@llvm.org>

Author: lattner
Date: Thu Mar 25 00:40:48 2010
New Revision: 99485

URL: http://llvm.org/viewvc/llvm-project?rev=99485&view=rev
Log:
Make the NDEBUG assertion stronger and more clear what is 
happening.

Enhance scheduling to set the DEAD flag on implicit defs
more aggressively.  Before, we'd set an implicit def operand
to dead if it were present in the SDNode corresponding to
the machineinstr but had no use.  Now we do it in this case
AND if the implicit def does not exist in the SDNode at all.

This exposes a couple of problems: one is the FIXME, which
causes a live intervals crash on CodeGen/X86/sibcall.ll.
The second is that it makes machinecse and licm more 
aggressive (which is a good thing) but also exposes a case
where licm hoists a set0 and then it doesn't get resunk.

Talking to codegen folks about both these issues, but I need
this patch in in the meantime.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    llvm/trunk/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
    llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
    llvm/trunk/test/CodeGen/X86/coalesce-esp.ll
    llvm/trunk/test/CodeGen/X86/licm-symbol.ll
    llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll
    llvm/trunk/test/CodeGen/X86/pr2659.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=99485&r1=99484&r2=99485&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Thu Mar 25 00:40:48 2010
@@ -578,13 +578,16 @@
   const TargetInstrDesc &II = TII->get(Opc);
   unsigned NumResults = CountResults(Node);
   unsigned NodeOperands = CountOperands(Node);
-  bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
-                        II.getImplicitDefs() != 0;
+  bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
 #ifndef NDEBUG
   unsigned NumMIOperands = NodeOperands + NumResults;
-  assert((II.getNumOperands() == NumMIOperands ||
-          HasPhysRegOuts || II.isVariadic()) &&
-         "#operands for dag node doesn't match .td file!"); 
+  if (II.isVariadic())
+    assert(NumMIOperands >= II.getNumOperands() &&
+           "Too few operands for a variadic node!");
+  else
+    assert(NumMIOperands >= II.getNumOperands() &&
+           NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() &&
+           "#operands for dag node doesn't match .td file!");
 #endif
 
   // Create the new machine instruction.
@@ -632,6 +635,18 @@
         MI->addRegisterDead(Reg, TRI);
     }
   }
+  
+  // If the instruction has implicit defs and the node doesn't, mark the
+  // implicit def as dead.  If the node has any flag outputs, we don't do this
+  // because we don't know what implicit defs are being used by flagged nodes.
+  if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag &&
+      // FIXME: This is a terrible hackaround for a liveintervals bug.
+      II.getNumImplicitDefs() < 8)
+    if (const unsigned *IDList = II.getImplicitDefs()) {
+      for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs();
+           i != e; ++i)
+        MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI);
+    }
   return;
 }
 

Modified: llvm/trunk/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll?rev=99485&r1=99484&r2=99485&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll Thu Mar 25 00:40:48 2010
@@ -1,5 +1,4 @@
 ; RUN: llc < %s -march=x86-64 > %t
-; RUN: grep leaq %t
 ; RUN: not grep {,%rsp)} %t
 ; PR1103
 

Modified: llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll?rev=99485&r1=99484&r2=99485&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll Thu Mar 25 00:40:48 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& not grep {machine-licm}
+; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& grep {2 machine-licm}
 ; rdar://6627786
 
 target triple = "x86_64-apple-darwin10.0"

Modified: llvm/trunk/test/CodeGen/X86/coalesce-esp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/coalesce-esp.ll?rev=99485&r1=99484&r2=99485&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/coalesce-esp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/coalesce-esp.ll Thu Mar 25 00:40:48 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s | grep {movl	%esp, %eax}
+; RUN: llc < %s | grep {movl	%esp, %ecx}
 ; PR4572
 
 ; Don't coalesce with %esp if it would end up putting %esp in

Modified: llvm/trunk/test/CodeGen/X86/licm-symbol.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/licm-symbol.ll?rev=99485&r1=99484&r2=99485&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/licm-symbol.ll (original)
+++ llvm/trunk/test/CodeGen/X86/licm-symbol.ll Thu Mar 25 00:40:48 2010
@@ -3,7 +3,7 @@
 ; MachineLICM should be able to hoist the sF reference out of the loop.
 
 ; CHECK: pushl %esi
-; CHECK: subl  $8, %esp
+; CHECK: subl  $4, %esp
 ; CHECK: movl  $176, %esi
 ; CHECK: addl  L___sF$non_lazy_ptr, %esi
 ; CHECK: .align  4, 0x90

Modified: llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll?rev=99485&r1=99484&r2=99485&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll Thu Mar 25 00:40:48 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | grep mov | count 5
+; RUN: llc < %s -march=x86 | grep mov | count 6
 ; PR2659
 
 define i32 @binomial(i32 %n, i32 %k) nounwind {

Modified: llvm/trunk/test/CodeGen/X86/pr2659.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr2659.ll?rev=99485&r1=99484&r2=99485&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr2659.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr2659.ll Thu Mar 25 00:40:48 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 5
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 6
 ; PR2659
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"




From sabre at nondot.org  Thu Mar 25 00:44:01 2010
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 25 Mar 2010 05:44:01 -0000
Subject: [llvm-commits] [llvm] r99486 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.td
Message-ID: <20100325054401.3D92F2A6C12C@llvm.org>

Author: lattner
Date: Thu Mar 25 00:44:01 2010
New Revision: 99486

URL: http://llvm.org/viewvc/llvm-project?rev=99486&view=rev
Log:
eliminate a bunch more parallels now that scheduling
handles dead implicit results more aggressively.  More
to come, I think this is now just a data entry problem.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=99486&r1=99485&r2=99486&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Mar 25 00:44:01 2010
@@ -1,4 +1,4 @@
-
+//===----------------------------------------------------------------------===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
@@ -1704,13 +1704,12 @@
 let isConvertibleToThreeAddress = 1, CodeSize = 1 in {  // Can xform into LEA.
 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), 
                "inc{w}\t$dst",
-               [(set GR16:$dst, (add GR16:$src, 1)),
-                (implicit EFLAGS)]>,
+               [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src))]>,
              OpSize, Requires<[In32BitMode]>;
 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), 
                "inc{l}\t$dst",
-               [(set GR32:$dst, (add GR32:$src, 1)),
-                (implicit EFLAGS)]>, Requires<[In32BitMode]>;
+               [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src))]>,
+             Requires<[In32BitMode]>;
 }
 let isTwoAddress = 0, CodeSize = 2 in {
   def INC8m  : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
@@ -1728,18 +1727,16 @@
 
 let CodeSize = 2 in
 def DEC8r  : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
-               [(set GR8:$dst, (add GR8:$src, -1)),
-                (implicit EFLAGS)]>;
+               [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src))]>;
 let isConvertibleToThreeAddress = 1, CodeSize = 1 in {   // Can xform into LEA.
 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), 
                "dec{w}\t$dst",
-               [(set GR16:$dst, (add GR16:$src, -1)),
-                (implicit EFLAGS)]>,
+               [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src))]>,
              OpSize, Requires<[In32BitMode]>;
 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), 
                "dec{l}\t$dst",
-               [(set GR32:$dst, (add GR32:$src, -1)),
-                (implicit EFLAGS)]>, Requires<[In32BitMode]>;
+               [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>,
+             Requires<[In32BitMode]>;
 }
 
 let isTwoAddress = 0, CodeSize = 2 in {
@@ -1760,21 +1757,20 @@
 // Logical operators...
 let Defs = [EFLAGS] in {
 let isCommutable = 1 in {   // X = AND Y, Z   --> X = AND Z, Y
-def AND8rr   : I<0x20, MRMDestReg,
-                (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
-                "and{b}\t{$src2, $dst|$dst, $src2}",
-                [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
-                 (implicit EFLAGS)]>;
-def AND16rr  : I<0x21, MRMDestReg,
-                 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
-                 "and{w}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
-                  (implicit EFLAGS)]>, OpSize;
-def AND32rr  : I<0x21, MRMDestReg, 
-                 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
-                 "and{l}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
-                  (implicit EFLAGS)]>;
+def AND8rr  : I<0x20, MRMDestReg,
+               (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
+               "and{b}\t{$src2, $dst|$dst, $src2}",
+               [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
+def AND16rr : I<0x21, MRMDestReg,
+                (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+                "and{w}\t{$src2, $dst|$dst, $src2}",
+                [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
+                                                      GR16:$src2))]>, OpSize;
+def AND32rr : I<0x21, MRMDestReg, 
+                (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+                "and{l}\t{$src2, $dst|$dst, $src2}",
+                [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
+                                                      GR32:$src2))]>;
 }
 
 // AND instructions with the destination register in REG and the source register
@@ -1791,45 +1787,46 @@
 def AND8rm   : I<0x22, MRMSrcMem, 
                  (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
                  "and{b}\t{$src2, $dst|$dst, $src2}",
-                [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
-                 (implicit EFLAGS)]>;
+                [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
+                                                     (loadi8 addr:$src2)))]>;
 def AND16rm  : I<0x23, MRMSrcMem, 
                  (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
                  "and{w}\t{$src2, $dst|$dst, $src2}",
-                [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
-                 (implicit EFLAGS)]>, OpSize;
+                [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
+                                                      (loadi16 addr:$src2)))]>,
+               OpSize;
 def AND32rm  : I<0x23, MRMSrcMem,
                  (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
                  "and{l}\t{$src2, $dst|$dst, $src2}",
-                [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
-                 (implicit EFLAGS)]>;
+                [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
+                                                      (loadi32 addr:$src2)))]>;
 
 def AND8ri   : Ii8<0x80, MRM4r, 
                    (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
                    "and{b}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
-                    (implicit EFLAGS)]>;
+                   [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
+                                                        imm:$src2))]>;
 def AND16ri  : Ii16<0x81, MRM4r, 
                     (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                     "and{w}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
-                     (implicit EFLAGS)]>, OpSize;
+                    [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
+                                                          imm:$src2))]>, OpSize;
 def AND32ri  : Ii32<0x81, MRM4r, 
                     (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
                     "and{l}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
-                     (implicit EFLAGS)]>;
+                    [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
+                                                          imm:$src2))]>;
 def AND16ri8 : Ii8<0x83, MRM4r, 
                    (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
                    "and{w}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
-                    (implicit EFLAGS)]>,
+                   [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
+                                                         i16immSExt8:$src2))]>,
                    OpSize;
 def AND32ri8 : Ii8<0x83, MRM4r, 
                    (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
                    "and{l}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
-                    (implicit EFLAGS)]>;
+                   [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
+                                                         i32immSExt8:$src2))]>;
 
 let isTwoAddress = 0 in {
   def AND8mr   : I<0x20, MRMDestMem,
@@ -1890,18 +1887,16 @@
 def OR8rr    : I<0x08, MRMDestReg, (outs GR8 :$dst), 
                  (ins GR8 :$src1, GR8 :$src2),
                  "or{b}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
-                  (implicit EFLAGS)]>;
+                 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
 def OR16rr   : I<0x09, MRMDestReg, (outs GR16:$dst), 
                  (ins GR16:$src1, GR16:$src2),
                  "or{w}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
-                  (implicit EFLAGS)]>, OpSize;
+                 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
+               OpSize;
 def OR32rr   : I<0x09, MRMDestReg, (outs GR32:$dst), 
                  (ins GR32:$src1, GR32:$src2),
                  "or{l}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
-                  (implicit EFLAGS)]>;
+                 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
 }
 
 // OR instructions with the destination register in REG and the source register
@@ -1915,48 +1910,48 @@
                    (ins GR32:$src1, GR32:$src2),
                    "or{l}\t{$src2, $dst|$dst, $src2}", []>;
                   
-def OR8rm    : I<0x0A, MRMSrcMem , (outs GR8 :$dst), 
+def OR8rm    : I<0x0A, MRMSrcMem, (outs GR8 :$dst), 
                  (ins GR8 :$src1, i8mem :$src2),
                  "or{b}\t{$src2, $dst|$dst, $src2}",
-                [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
-                 (implicit EFLAGS)]>;
-def OR16rm   : I<0x0B, MRMSrcMem , (outs GR16:$dst), 
+                [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
+                                                    (load addr:$src2)))]>;
+def OR16rm   : I<0x0B, MRMSrcMem, (outs GR16:$dst), 
                  (ins GR16:$src1, i16mem:$src2),
                  "or{w}\t{$src2, $dst|$dst, $src2}",
-                [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
-                 (implicit EFLAGS)]>, OpSize;
-def OR32rm   : I<0x0B, MRMSrcMem , (outs GR32:$dst), 
+                [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
+                                                     (load addr:$src2)))]>,
+               OpSize;
+def OR32rm   : I<0x0B, MRMSrcMem, (outs GR32:$dst), 
                  (ins GR32:$src1, i32mem:$src2),
                  "or{l}\t{$src2, $dst|$dst, $src2}",
-                [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
-                 (implicit EFLAGS)]>;
+                [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
+                                                     (load addr:$src2)))]>;
 
 def OR8ri    : Ii8 <0x80, MRM1r, (outs GR8 :$dst), 
                     (ins GR8 :$src1, i8imm:$src2),
                     "or{b}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
-                     (implicit EFLAGS)]>;
+                    [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
 def OR16ri   : Ii16<0x81, MRM1r, (outs GR16:$dst), 
                     (ins GR16:$src1, i16imm:$src2),
                     "or{w}\t{$src2, $dst|$dst, $src2}", 
-                    [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
-                     (implicit EFLAGS)]>, OpSize;
+                    [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
+                                                        imm:$src2))]>, OpSize;
 def OR32ri   : Ii32<0x81, MRM1r, (outs GR32:$dst), 
                     (ins GR32:$src1, i32imm:$src2),
                     "or{l}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
-                     (implicit EFLAGS)]>;
+                    [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
+                                                         imm:$src2))]>;
 
 def OR16ri8  : Ii8<0x83, MRM1r, (outs GR16:$dst), 
                    (ins GR16:$src1, i16i8imm:$src2),
                    "or{w}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
-                    (implicit EFLAGS)]>, OpSize;
+                   [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
+                                                i16immSExt8:$src2))]>, OpSize;
 def OR32ri8  : Ii8<0x83, MRM1r, (outs GR32:$dst), 
                    (ins GR32:$src1, i32i8imm:$src2),
                    "or{l}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
-                    (implicit EFLAGS)]>;
+                   [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
+                                                        i32immSExt8:$src2))]>;
 let isTwoAddress = 0 in {
   def OR8mr  : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
                  "or{b}\t{$src, $dst|$dst, $src}",
@@ -2006,18 +2001,18 @@
   def XOR8rr   : I<0x30, MRMDestReg,
                    (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
                    "xor{b}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
-                    (implicit EFLAGS)]>;
+                   [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
+                                                        GR8:$src2))]>;
   def XOR16rr  : I<0x31, MRMDestReg, 
                    (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 
                    "xor{w}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
-                    (implicit EFLAGS)]>, OpSize;
+                   [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
+                                                         GR16:$src2))]>, OpSize;
   def XOR32rr  : I<0x31, MRMDestReg, 
                    (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 
                    "xor{l}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
-                    (implicit EFLAGS)]>;
+                   [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
+                                                         GR32:$src2))]>;
 } // isCommutable = 1
 
 // XOR instructions with the destination register in REG and the source register
@@ -2031,49 +2026,48 @@
                     (ins GR32:$src1, GR32:$src2),
                    "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
 
-def XOR8rm   : I<0x32, MRMSrcMem , 
+def XOR8rm   : I<0x32, MRMSrcMem, 
                  (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2), 
                  "xor{b}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
-                  (implicit EFLAGS)]>;
-def XOR16rm  : I<0x33, MRMSrcMem , 
+                 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
+                                                      (load addr:$src2)))]>;
+def XOR16rm  : I<0x33, MRMSrcMem, 
                  (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), 
                  "xor{w}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
-                  (implicit EFLAGS)]>,
+                 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
+                                                       (load addr:$src2)))]>,
                  OpSize;
-def XOR32rm  : I<0x33, MRMSrcMem , 
+def XOR32rm  : I<0x33, MRMSrcMem, 
                  (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), 
                  "xor{l}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
-                  (implicit EFLAGS)]>;
+                 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
+                                                       (load addr:$src2)))]>;
 
-def XOR8ri   : Ii8<0x80, MRM6r, 
-                   (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), 
-                   "xor{b}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
-                    (implicit EFLAGS)]>;
-def XOR16ri  : Ii16<0x81, MRM6r, 
-                    (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 
-                    "xor{w}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
-                     (implicit EFLAGS)]>, OpSize;
+def XOR8ri  : Ii8<0x80, MRM6r, 
+                  (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), 
+                  "xor{b}\t{$src2, $dst|$dst, $src2}",
+                  [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
+def XOR16ri : Ii16<0x81, MRM6r, 
+                   (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 
+                   "xor{w}\t{$src2, $dst|$dst, $src2}",
+                   [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
+                                                         imm:$src2))]>, OpSize;
 def XOR32ri  : Ii32<0x81, MRM6r, 
                     (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 
                     "xor{l}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
-                     (implicit EFLAGS)]>;
+                    [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
+                                                          imm:$src2))]>;
 def XOR16ri8 : Ii8<0x83, MRM6r, 
                    (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
                    "xor{w}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
-                    (implicit EFLAGS)]>,
+                   [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
+                                                         i16immSExt8:$src2))]>,
                    OpSize;
 def XOR32ri8 : Ii8<0x83, MRM6r, 
                    (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
                    "xor{l}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
-                    (implicit EFLAGS)]>;
+                   [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
+                                                         i32immSExt8:$src2))]>;
 
 let isTwoAddress = 0 in {
   def XOR8mr   : I<0x30, MRMDestMem,
@@ -2120,12 +2114,12 @@
                  [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
                   (implicit EFLAGS)]>;
                   
-  def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
-                   "xor{b}\t{$src, %al|%al, $src}", []>;
-  def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
-                        "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
-  def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
-                        "xor{l}\t{$src, %eax|%eax, $src}", []>;
+  def XOR8i8   : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
+                      "xor{b}\t{$src, %al|%al, $src}", []>;
+  def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
+                      "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
+  def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
+                      "xor{l}\t{$src, %eax|%eax, $src}", []>;
 } // isTwoAddress = 0
 } // Defs = [EFLAGS]
 
@@ -4878,137 +4872,88 @@
           (ADD32rr GR32:$src1, GR32:$src1)>;
 }
 
-// INC and DEC with EFLAGS result. Note that these do not set CF.
-def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>;
+// Patterns for nodes that do not produce flags, for instructions that do.
 
-def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
-          (DEC8r GR8:$src)>;
-
-def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
-          (INC16r GR16:$src)>, Requires<[In32BitMode]>;
-def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
-          (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
-
-def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
-          (INC32r GR32:$src)>, Requires<[In32BitMode]>;
-def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
-          (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
-
-// Register-Register Or with EFLAGS result
-def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
-                    (implicit EFLAGS)),
-          (OR8rr GR8:$src1, GR8:$src2)>;
-def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2),
-                    (implicit EFLAGS)),
-          (OR16rr GR16:$src1, GR16:$src2)>;
-def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2),
-                    (implicit EFLAGS)),
-          (OR32rr GR32:$src1, GR32:$src2)>;
+// Increment reg.
+def : Pat<(add GR8:$src ,  1), (INC8r  GR8:$src)>;
+def : Pat<(add GR16:$src,  1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
+def : Pat<(add GR32:$src,  1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
+
+// Decrement reg.
+def : Pat<(add GR8:$src , -1), (DEC8r  GR8:$src)>;
+def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
+def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
+
+// or reg/reg.
+def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr  GR8 :$src1, GR8 :$src2)>;
+def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
+def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
 
-// Register-Memory Or with EFLAGS result
-def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)),
-                    (implicit EFLAGS)),
+// or reg/mem
+def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
           (OR8rm GR8:$src1, addr:$src2)>;
-def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
           (OR16rm GR16:$src1, addr:$src2)>;
-def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
           (OR32rm GR32:$src1, addr:$src2)>;
 
-// Register-Integer Or with EFLAGS result
-def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2),
-                    (implicit EFLAGS)),
-          (OR8ri GR8:$src1, imm:$src2)>;
-def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2),
-                    (implicit EFLAGS)),
-          (OR16ri GR16:$src1, imm:$src2)>;
-def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2),
-                    (implicit EFLAGS)),
-          (OR32ri GR32:$src1, imm:$src2)>;
-def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
-                    (implicit EFLAGS)),
+// or reg/imm
+def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri  GR8 :$src1, imm:$src2)>;
+def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
+def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
+def : Pat<(or GR16:$src1, i16immSExt8:$src2),
           (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
-def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(or GR32:$src1, i32immSExt8:$src2),
           (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
 
-// Register-Register XOr with EFLAGS result
-def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
-                    (implicit EFLAGS)),
-          (XOR8rr GR8:$src1, GR8:$src2)>;
-def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2),
-                    (implicit EFLAGS)),
-          (XOR16rr GR16:$src1, GR16:$src2)>;
-def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2),
-                    (implicit EFLAGS)),
-          (XOR32rr GR32:$src1, GR32:$src2)>;
+// xor reg/reg
+def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr  GR8 :$src1, GR8 :$src2)>;
+def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
+def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
 
-// Register-Memory XOr with EFLAGS result
-def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)),
-                    (implicit EFLAGS)),
+// xor reg/mem
+def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
           (XOR8rm GR8:$src1, addr:$src2)>;
-def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
           (XOR16rm GR16:$src1, addr:$src2)>;
-def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
           (XOR32rm GR32:$src1, addr:$src2)>;
 
-// Register-Integer XOr with EFLAGS result
-def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2),
-                    (implicit EFLAGS)),
+// xor reg/imm
+def : Pat<(xor GR8:$src1, imm:$src2),
           (XOR8ri GR8:$src1, imm:$src2)>;
-def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(xor GR16:$src1, imm:$src2),
           (XOR16ri GR16:$src1, imm:$src2)>;
-def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(xor GR32:$src1, imm:$src2),
           (XOR32ri GR32:$src1, imm:$src2)>;
-def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
           (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
-def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
           (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
 
-// Register-Register And with EFLAGS result
-def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
-                    (implicit EFLAGS)),
-          (AND8rr GR8:$src1, GR8:$src2)>;
-def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2),
-                    (implicit EFLAGS)),
-          (AND16rr GR16:$src1, GR16:$src2)>;
-def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2),
-                    (implicit EFLAGS)),
-          (AND32rr GR32:$src1, GR32:$src2)>;
+// and reg/reg
+def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr  GR8 :$src1, GR8 :$src2)>;
+def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
+def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
 
-// Register-Memory And with EFLAGS result
-def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)),
-                    (implicit EFLAGS)),
+// and reg/mem
+def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
           (AND8rm GR8:$src1, addr:$src2)>;
-def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
           (AND16rm GR16:$src1, addr:$src2)>;
-def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
           (AND32rm GR32:$src1, addr:$src2)>;
 
-// Register-Integer And with EFLAGS result
-def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2),
-                    (implicit EFLAGS)),
+// and reg/imm
+def : Pat<(and GR8:$src1, imm:$src2),
           (AND8ri GR8:$src1, imm:$src2)>;
-def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(and GR16:$src1, imm:$src2),
           (AND16ri GR16:$src1, imm:$src2)>;
-def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(and GR32:$src1, imm:$src2),
           (AND32ri GR32:$src1, imm:$src2)>;
-def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(and GR16:$src1, i16immSExt8:$src2),
           (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
-def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(and GR32:$src1, i32immSExt8:$src2),
           (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
 
 // -disable-16bit support.




From evan.cheng at apple.com  Thu Mar 25 00:50:26 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 05:50:26 -0000
Subject: [llvm-commits] [llvm] r99487 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
Message-ID: <20100325055026.E61962A6C12C@llvm.org>

Author: evancheng
Date: Thu Mar 25 00:50:26 2010
New Revision: 99487

URL: http://llvm.org/viewvc/llvm-project?rev=99487&view=rev
Log:
Make sure SDDbgValue.Invalid is initialized to false by all the constructors.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h?rev=99487&r1=99486&r2=99487&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h Thu Mar 25 00:50:26 2010
@@ -60,14 +60,14 @@
 
   // Constructor for constants.
   SDDbgValue(MDNode *mdP, Value *C, uint64_t off, DebugLoc dl, unsigned O) : 
-    mdPtr(mdP), Offset(off), DL(dl), Order(O) {
+    mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
     kind = CONST;
     u.Const = C;
   }
 
   // Constructor for frame indices.
   SDDbgValue(MDNode *mdP, unsigned FI, uint64_t off, DebugLoc dl, unsigned O) : 
-    mdPtr(mdP), Offset(off), DL(dl), Order(O) {
+    mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
     kind = FRAMEIX;
     u.FrameIx = FI;
   }




From sabre at nondot.org  Thu Mar 25 00:58:19 2010
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 25 Mar 2010 05:58:19 -0000
Subject: [llvm-commits] [llvm] r99488 - in /llvm/trunk:
 lib/Transforms/Scalar/GVN.cpp test/Transforms/GVN/rle.ll
Message-ID: <20100325055819.5408F2A6C12C@llvm.org>

Author: lattner
Date: Thu Mar 25 00:58:19 2010
New Revision: 99488

URL: http://llvm.org/viewvc/llvm-project?rev=99488&view=rev
Log:
fix PR6642, GVN forwarding from memset to load of the base of the memset.

Modified:
    llvm/trunk/lib/Transforms/Scalar/GVN.cpp
    llvm/trunk/test/Transforms/GVN/rle.ll

Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=99488&r1=99487&r2=99488&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Thu Mar 25 00:58:19 2010
@@ -1004,18 +1004,18 @@
   
   // If the load and store are to the exact same address, they should have been
   // a must alias.  AA must have gotten confused.
-  // FIXME: Study to see if/when this happens.
-  if (LoadOffset == StoreOffset) {
+  // FIXME: Study to see if/when this happens.  One case is forwarding a memset
+  // to a load from the base of the memset.
 #if 0
+  if (LoadOffset == StoreOffset) {
     dbgs() << "STORE/LOAD DEP WITH COMMON POINTER MISSED:\n"
     << "Base       = " << *StoreBase << "\n"
     << "Store Ptr  = " << *WritePtr << "\n"
     << "Store Offs = " << StoreOffset << "\n"
     << "Load Ptr   = " << *LoadPtr << "\n";
     abort();
-#endif
-    return -1;
   }
+#endif
   
   // If the load and store don't overlap at all, the store doesn't provide
   // anything to the load.  In this case, they really don't alias at all, AA
@@ -1031,11 +1031,11 @@
   
   
   bool isAAFailure = false;
-  if (StoreOffset < LoadOffset) {
+  if (StoreOffset < LoadOffset)
     isAAFailure = StoreOffset+int64_t(StoreSize) <= LoadOffset;
-  } else {
+  else
     isAAFailure = LoadOffset+int64_t(LoadSize) <= StoreOffset;
-  }
+
   if (isAAFailure) {
 #if 0
     dbgs() << "STORE LOAD DEP WITH COMMON BASE:\n"

Modified: llvm/trunk/test/Transforms/GVN/rle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/rle.ll?rev=99488&r1=99487&r2=99488&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/GVN/rle.ll (original)
+++ llvm/trunk/test/Transforms/GVN/rle.ll Thu Mar 25 00:58:19 2010
@@ -531,4 +531,16 @@
 }
 
 
+; PR6642
+define i32 @memset_to_load() nounwind readnone {
+entry:
+  %x = alloca [256 x i32], align 4                ; <[256 x i32]*> [#uses=2]
+  %tmp = bitcast [256 x i32]* %x to i8*           ; <i8*> [#uses=1]
+  call void @llvm.memset.i64(i8* %tmp, i8 0, i64 1024, i32 4)
+  %arraydecay = getelementptr inbounds [256 x i32]* %x, i32 0, i32 0 ; <i32*>
+  %tmp1 = load i32* %arraydecay                   ; <i32> [#uses=1]
+  ret i32 %tmp1
+; CHECK: @memset_to_load
+; CHECK: ret i32 0
+}
 




From evan.cheng at apple.com  Thu Mar 25 01:02:54 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 06:02:54 -0000
Subject: [llvm-commits] [llvm] r99489 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
Message-ID: <20100325060254.267AE2A6C12D@llvm.org>

Author: evancheng
Date: Thu Mar 25 01:02:53 2010
New Revision: 99489

URL: http://llvm.org/viewvc/llvm-project?rev=99489&view=rev
Log:
Remove a fixme that doesn't make sense any more.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=99489&r1=99488&r2=99489&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Thu Mar 25 01:02:53 2010
@@ -449,8 +449,6 @@
       continue;
     unsigned DVOrder = DVs[i]->getOrder();
     if (DVOrder == ++Order) {
-      // FIXME: If the source node with next higher order is scheduled before
-      // this could end up generating funky debug info.
       MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], BB, VRBaseMap, EM);
       Orders.push_back(std::make_pair(DVOrder, DbgMI));
       BB->insert(InsertPos, DbgMI);




From dpatel at apple.com  Thu Mar 25 01:04:47 2010
From: dpatel at apple.com (Devang Patel)
Date: Thu, 25 Mar 2010 06:04:47 -0000
Subject: [llvm-commits] [llvm] r99490 - /llvm/trunk/lib/VMCore/Metadata.cpp
Message-ID: <20100325060447.DC6CB2A6C12D@llvm.org>

Author: dpatel
Date: Thu Mar 25 01:04:47 2010
New Revision: 99490

URL: http://llvm.org/viewvc/llvm-project?rev=99490&view=rev
Log:
Include isFunctionLocal while calculating folding node set profile for a MDNode.


Modified:
    llvm/trunk/lib/VMCore/Metadata.cpp

Modified: llvm/trunk/lib/VMCore/Metadata.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=99490&r1=99489&r2=99490&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Metadata.cpp (original)
+++ llvm/trunk/lib/VMCore/Metadata.cpp Thu Mar 25 01:04:47 2010
@@ -182,19 +182,6 @@
                           unsigned NumVals, FunctionLocalness FL,
                           bool Insert) {
   LLVMContextImpl *pImpl = Context.pImpl;
-  FoldingSetNodeID ID;
-  for (unsigned i = 0; i != NumVals; ++i)
-    ID.AddPointer(Vals[i]);
-
-  void *InsertPoint;
-  MDNode *N = NULL;
-  
-  if ((N = pImpl->MDNodeSet.FindNodeOrInsertPos(ID, InsertPoint)))
-    return N;
-    
-  if (!Insert)
-    return NULL;
-    
   bool isFunctionLocal = false;
   switch (FL) {
   case FL_Unknown:
@@ -216,6 +203,20 @@
     break;
   }
 
+  FoldingSetNodeID ID;
+  for (unsigned i = 0; i != NumVals; ++i)
+    ID.AddPointer(Vals[i]);
+  ID.AddBoolean(isFunctionLocal);
+
+  void *InsertPoint;
+  MDNode *N = NULL;
+  
+  if ((N = pImpl->MDNodeSet.FindNodeOrInsertPos(ID, InsertPoint)))
+    return N;
+    
+  if (!Insert)
+    return NULL;
+    
   // Coallocate space for the node and Operands together, then placement new.
   void *Ptr = malloc(sizeof(MDNode)+NumVals*sizeof(MDNodeOperand));
   N = new (Ptr) MDNode(Context, Vals, NumVals, isFunctionLocal);




From clattner at apple.com  Thu Mar 25 01:06:05 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 24 Mar 2010 23:06:05 -0700
Subject: [llvm-commits] [llvm] r99490 -
	/llvm/trunk/lib/VMCore/Metadata.cpp
In-Reply-To: <20100325060447.DC6CB2A6C12D@llvm.org>
References: <20100325060447.DC6CB2A6C12D@llvm.org>
Message-ID: <60B2579A-3A15-4F22-A350-04889AF72646@apple.com>


On Mar 24, 2010, at 11:04 PM, Devang Patel wrote:

> Author: dpatel
> Date: Thu Mar 25 01:04:47 2010
> New Revision: 99490
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99490&view=rev
> Log:
> Include isFunctionLocal while calculating folding node set profile for a MDNode.

Can this code call MDNode::Profile instead of duplicating it?

-Chris

> 
> 
> Modified:
>    llvm/trunk/lib/VMCore/Metadata.cpp
> 
> Modified: llvm/trunk/lib/VMCore/Metadata.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=99490&r1=99489&r2=99490&view=diff
> ==============================================================================
> --- llvm/trunk/lib/VMCore/Metadata.cpp (original)
> +++ llvm/trunk/lib/VMCore/Metadata.cpp Thu Mar 25 01:04:47 2010
> @@ -182,19 +182,6 @@
>                           unsigned NumVals, FunctionLocalness FL,
>                           bool Insert) {
>   LLVMContextImpl *pImpl = Context.pImpl;
> -  FoldingSetNodeID ID;
> -  for (unsigned i = 0; i != NumVals; ++i)
> -    ID.AddPointer(Vals[i]);
> -
> -  void *InsertPoint;
> -  MDNode *N = NULL;
> -  
> -  if ((N = pImpl->MDNodeSet.FindNodeOrInsertPos(ID, InsertPoint)))
> -    return N;
> -    
> -  if (!Insert)
> -    return NULL;
> -    
>   bool isFunctionLocal = false;
>   switch (FL) {
>   case FL_Unknown:
> @@ -216,6 +203,20 @@
>     break;
>   }
> 
> +  FoldingSetNodeID ID;
> +  for (unsigned i = 0; i != NumVals; ++i)
> +    ID.AddPointer(Vals[i]);
> +  ID.AddBoolean(isFunctionLocal);
> +
> +  void *InsertPoint;
> +  MDNode *N = NULL;
> +  
> +  if ((N = pImpl->MDNodeSet.FindNodeOrInsertPos(ID, InsertPoint)))
> +    return N;
> +    
> +  if (!Insert)
> +    return NULL;
> +    
>   // Coallocate space for the node and Operands together, then placement new.
>   void *Ptr = malloc(sizeof(MDNode)+NumVals*sizeof(MDNodeOperand));
>   N = new (Ptr) MDNode(Context, Vals, NumVals, isFunctionLocal);
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From dpatel at apple.com  Thu Mar 25 01:15:33 2010
From: dpatel at apple.com (Devang Patel)
Date: Wed, 24 Mar 2010 23:15:33 -0700
Subject: [llvm-commits] [llvm] r99490 -
	/llvm/trunk/lib/VMCore/Metadata.cpp
In-Reply-To: <60B2579A-3A15-4F22-A350-04889AF72646@apple.com>
References: <20100325060447.DC6CB2A6C12D@llvm.org>
	<60B2579A-3A15-4F22-A350-04889AF72646@apple.com>
Message-ID: <4994F60D-90B1-4093-8690-9AEC1C4D6AFE@apple.com>


On Mar 24, 2010, at 11:06 PM, Chris Lattner wrote:

> 
> On Mar 24, 2010, at 11:04 PM, Devang Patel wrote:
> 
>> Author: dpatel
>> Date: Thu Mar 25 01:04:47 2010
>> New Revision: 99490
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99490&view=rev
>> Log:
>> Include isFunctionLocal while calculating folding node set profile for a MDNode.
> 
> Can this code call MDNode::Profile instead of duplicating it?

MDNode::getMDNode() calculates profile based on incoming value list before creating MDNode. 
-
Devang
> 
> -Chris
> 
>> 
>> 
>> Modified:
>>   llvm/trunk/lib/VMCore/Metadata.cpp
>> 
>> Modified: llvm/trunk/lib/VMCore/Metadata.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=99490&r1=99489&r2=99490&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/VMCore/Metadata.cpp (original)
>> +++ llvm/trunk/lib/VMCore/Metadata.cpp Thu Mar 25 01:04:47 2010
>> @@ -182,19 +182,6 @@
>>                          unsigned NumVals, FunctionLocalness FL,
>>                          bool Insert) {
>>  LLVMContextImpl *pImpl = Context.pImpl;
>> -  FoldingSetNodeID ID;
>> -  for (unsigned i = 0; i != NumVals; ++i)
>> -    ID.AddPointer(Vals[i]);
>> -
>> -  void *InsertPoint;
>> -  MDNode *N = NULL;
>> -  
>> -  if ((N = pImpl->MDNodeSet.FindNodeOrInsertPos(ID, InsertPoint)))
>> -    return N;
>> -    
>> -  if (!Insert)
>> -    return NULL;
>> -    
>>  bool isFunctionLocal = false;
>>  switch (FL) {
>>  case FL_Unknown:
>> @@ -216,6 +203,20 @@
>>    break;
>>  }
>> 
>> +  FoldingSetNodeID ID;
>> +  for (unsigned i = 0; i != NumVals; ++i)
>> +    ID.AddPointer(Vals[i]);
>> +  ID.AddBoolean(isFunctionLocal);
>> +
>> +  void *InsertPoint;
>> +  MDNode *N = NULL;
>> +  
>> +  if ((N = pImpl->MDNodeSet.FindNodeOrInsertPos(ID, InsertPoint)))
>> +    return N;
>> +    
>> +  if (!Insert)
>> +    return NULL;
>> +    
>>  // Coallocate space for the node and Operands together, then placement new.
>>  void *Ptr = malloc(sizeof(MDNode)+NumVals*sizeof(MDNodeOperand));
>>  N = new (Ptr) MDNode(Context, Vals, NumVals, isFunctionLocal);
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 




From stoklund at 2pi.dk  Thu Mar 25 01:23:35 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 25 Mar 2010 06:23:35 -0000
Subject: [llvm-commits] [llvm] r99492 - in /llvm/trunk:
 test/TableGen/2010-03-24-PrematureDefaults.td utils/TableGen/Record.cpp
 utils/TableGen/Record.h
Message-ID: <20100325062335.201872A6C12C@llvm.org>

Author: stoklund
Date: Thu Mar 25 01:23:34 2010
New Revision: 99492

URL: http://llvm.org/viewvc/llvm-project?rev=99492&view=rev
Log:
Fix evil TableGen bug in template parameters with defaults.

If a TableGen class has an initializer expression containing an X.Y subexpression,
AND X depends on template parameters,
AND those template parameters have defaults,
AND some parameters with defaults are beyond position 1,
THEN parts of the initializer expression are evaluated prematurely with the default values when the first explicit template parameter is substituted, before the remaining explicit template parameters have been substituted.

Added:
    llvm/trunk/test/TableGen/2010-03-24-PrematureDefaults.td
Modified:
    llvm/trunk/utils/TableGen/Record.cpp
    llvm/trunk/utils/TableGen/Record.h

Added: llvm/trunk/test/TableGen/2010-03-24-PrematureDefaults.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/2010-03-24-PrematureDefaults.td?rev=99492&view=auto
==============================================================================
--- llvm/trunk/test/TableGen/2010-03-24-PrematureDefaults.td (added)
+++ llvm/trunk/test/TableGen/2010-03-24-PrematureDefaults.td Thu Mar 25 01:23:34 2010
@@ -0,0 +1,43 @@
+// RUN: tblgen %s | FileCheck %s
+
+class A<int k, bits<2> x = 1> {
+  int K = k;
+  bits<2> Bits = x;
+}
+
+// CHECK: def a1
+// CHECK: Bits = { 0, 1 }
+def a1 : A<12>;
+
+// CHECK: def a2
+// CHECK: Bits = { 1, 0 }
+def a2 : A<13, 2>;
+
+// Here was the bug: X.Bits would get resolved to the default a1.Bits while
+// resolving the first template argument. When the second template argument
+// was processed, X would be set correctly, but Bits retained the default
+// value.
+class B<int k, A x = a1> {
+  A X = x;
+  bits<2> Bits = X.Bits;
+}
+
+// CHECK: def b1
+// CHECK: Bits = { 0, 1 }
+def b1 : B<27>;
+
+// CHECK: def b2
+// CHECK: Bits = { 1, 0 }
+def b2 : B<28, a2>;
+
+class C<A x = a1> {
+  bits<2> Bits = x.Bits;
+}
+
+// CHECK: def c1
+// CHECK: Bits = { 0, 1 }
+def c1 : C;
+
+// CHECK: def c2
+// CHECK: Bits = { 1, 0 }
+def c2 : C<a2>;

Modified: llvm/trunk/utils/TableGen/Record.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=99492&r1=99491&r2=99492&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/Record.cpp (original)
+++ llvm/trunk/utils/TableGen/Record.cpp Thu Mar 25 01:23:34 2010
@@ -1108,12 +1108,15 @@
   return 0;
 }
 
-Init *VarInit::getFieldInit(Record &R, const std::string &FieldName) const {
+Init *VarInit::getFieldInit(Record &R, const RecordVal *RV,
+                            const std::string &FieldName) const {
   if (dynamic_cast<RecordRecTy*>(getType()))
-    if (const RecordVal *RV = R.getValue(VarName)) {
-      Init *TheInit = RV->getValue();
+    if (const RecordVal *Val = R.getValue(VarName)) {
+      if (RV != Val && (RV || dynamic_cast<UnsetInit*>(Val->getValue())))
+        return 0;
+      Init *TheInit = Val->getValue();
       assert(TheInit != this && "Infinite loop detected!");
-      if (Init *I = TheInit->getFieldInit(R, FieldName))
+      if (Init *I = TheInit->getFieldInit(R, RV, FieldName))
         return I;
       else
         return 0;
@@ -1174,7 +1177,8 @@
   return 0;
 }
 
-Init *DefInit::getFieldInit(Record &R, const std::string &FieldName) const {
+Init *DefInit::getFieldInit(Record &R, const RecordVal *RV,
+                            const std::string &FieldName) const {
   return Def->getValue(FieldName)->getValue();
 }
 
@@ -1185,7 +1189,7 @@
 
 Init *FieldInit::resolveBitReference(Record &R, const RecordVal *RV,
                                      unsigned Bit) {
-  if (Init *BitsVal = Rec->getFieldInit(R, FieldName))
+  if (Init *BitsVal = Rec->getFieldInit(R, RV, FieldName))
     if (BitsInit *BI = dynamic_cast<BitsInit*>(BitsVal)) {
       assert(Bit < BI->getNumBits() && "Bit reference out of range!");
       Init *B = BI->getBit(Bit);
@@ -1198,7 +1202,7 @@
 
 Init *FieldInit::resolveListElementReference(Record &R, const RecordVal *RV,
                                              unsigned Elt) {
-  if (Init *ListVal = Rec->getFieldInit(R, FieldName))
+  if (Init *ListVal = Rec->getFieldInit(R, RV, FieldName))
     if (ListInit *LI = dynamic_cast<ListInit*>(ListVal)) {
       if (Elt >= LI->getSize()) return 0;
       Init *E = LI->getElement(Elt);
@@ -1215,7 +1219,7 @@
 Init *FieldInit::resolveReferences(Record &R, const RecordVal *RV) {
   Init *NewRec = RV ? Rec->resolveReferences(R, RV) : Rec;
 
-  Init *BitsVal = NewRec->getFieldInit(R, FieldName);
+  Init *BitsVal = NewRec->getFieldInit(R, RV, FieldName);
   if (BitsVal) {
     Init *BVR = BitsVal->resolveReferences(R, RV);
     return BVR->isComplete() ? BVR : this;

Modified: llvm/trunk/utils/TableGen/Record.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.h?rev=99492&r1=99491&r2=99492&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/Record.h (original)
+++ llvm/trunk/utils/TableGen/Record.h Thu Mar 25 01:23:34 2010
@@ -503,7 +503,8 @@
   /// initializer for the specified field.  If getFieldType returns non-null
   /// this method should return non-null, otherwise it returns null.
   ///
-  virtual Init *getFieldInit(Record &R, const std::string &FieldName) const {
+  virtual Init *getFieldInit(Record &R, const RecordVal *RV,
+                             const std::string &FieldName) const {
     return 0;
   }
 
@@ -950,7 +951,8 @@
                                             unsigned Elt);
 
   virtual RecTy *getFieldType(const std::string &FieldName) const;
-  virtual Init *getFieldInit(Record &R, const std::string &FieldName) const;
+  virtual Init *getFieldInit(Record &R, const RecordVal *RV,
+                             const std::string &FieldName) const;
 
   /// resolveReferences - This method is used by classes that refer to other
   /// variables which may not be defined at the time they expression is formed.
@@ -1035,7 +1037,8 @@
   //virtual Init *convertInitializerBitRange(const std::vector<unsigned> &Bits);
 
   virtual RecTy *getFieldType(const std::string &FieldName) const;
-  virtual Init *getFieldInit(Record &R, const std::string &FieldName) const;
+  virtual Init *getFieldInit(Record &R, const RecordVal *RV,
+                             const std::string &FieldName) const;
 
   virtual std::string getAsString() const;
 




From dpatel at apple.com  Thu Mar 25 01:26:14 2010
From: dpatel at apple.com (Devang Patel)
Date: Thu, 25 Mar 2010 06:26:14 -0000
Subject: [llvm-commits] [llvm] r99493 -
	/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
Message-ID: <20100325062614.3C9AF2A6C12C@llvm.org>

Author: dpatel
Date: Thu Mar 25 01:26:14 2010
New Revision: 99493

URL: http://llvm.org/viewvc/llvm-project?rev=99493&view=rev
Log:
Fix typo.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=99493&r1=99492&r2=99493&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Thu Mar 25 01:26:14 2010
@@ -65,7 +65,7 @@
 /// DbgValMap.
 class SDDbgInfo {
   SmallVector<SDDbgValue*, 32> DbgValues;
-  DenseMap<const SDNode*, SmallVector<SDDbgValue*, 2> > DbgVblMap;
+  DenseMap<const SDNode*, SmallVector<SDDbgValue*, 2> > DbgValMap;
 
   void operator=(const SDDbgInfo&);   // Do not implement.
   SDDbgInfo(const SDDbgInfo&);   // Do not implement.
@@ -74,12 +74,12 @@
 
   void add(SDDbgValue *V, const SDNode *Node = 0) {
     if (Node)
-      DbgVblMap[Node].push_back(V);
+      DbgValMap[Node].push_back(V);
     DbgValues.push_back(V);
   }
 
   void clear() {
-    DbgVblMap.clear();
+    DbgValMap.clear();
     DbgValues.clear();
   }
 
@@ -88,7 +88,7 @@
   }
 
   SmallVector<SDDbgValue*,2> &getSDDbgValues(const SDNode *Node) {
-    return DbgVblMap[Node];
+    return DbgValMap[Node];
   }
 
   typedef SmallVector<SDDbgValue*,32>::iterator DbgIterator;




From sabre at nondot.org  Thu Mar 25 01:33:05 2010
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 25 Mar 2010 06:33:05 -0000
Subject: [llvm-commits] [llvm] r99494 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
 utils/TableGen/DAGISelMatcherEmitter.cpp
Message-ID: <20100325063305.33A742A6C12C@llvm.org>

Author: lattner
Date: Thu Mar 25 01:33:05 2010
New Revision: 99494

URL: http://llvm.org/viewvc/llvm-project?rev=99494&view=rev
Log:
Change tblgen to emit FOOISD opcode names as two
bytes instead of one byte.  This is important because
we're running up to too many opcodes to fit in a byte
and it is aggrevated by FIRST_TARGET_MEMORY_OPCODE
making the numbering sparse.  This just bites the
bullet and bloats out the table.  In practice, this
increases the size of the x86 isel table from 74.5K
to 76K.  I think we'll cope :)

This fixes rdar://7791648

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=99494&r1=99493&r2=99494&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 25 01:33:05 2010
@@ -1888,7 +1888,9 @@
 ALWAYS_INLINE static bool
 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
             SDNode *N) {
-  return N->getOpcode() == MatcherTable[MatcherIndex++];
+  uint16_t Opc = MatcherTable[MatcherIndex++];
+  Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
+  return N->getOpcode() == Opc;
 }
 
 ALWAYS_INLINE static bool
@@ -2142,7 +2144,8 @@
       if (CaseSize == 0) break;
 
       // Get the opcode, add the index to the table.
-      unsigned Opc = MatcherTable[Idx++];
+      uint16_t Opc = MatcherTable[Idx++];
+      Opc |= (unsigned short)MatcherTable[Idx++] << 8;
       if (Opc >= OpcodeOffset.size())
         OpcodeOffset.resize((Opc+1)*2);
       OpcodeOffset[Opc] = Idx;
@@ -2298,8 +2301,11 @@
           CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
         if (CaseSize == 0) break;
 
+        uint16_t Opc = MatcherTable[MatcherIndex++];
+        Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
+
         // If the opcode matches, then we will execute this case.
-        if (CurNodeOpcode == MatcherTable[MatcherIndex++])
+        if (CurNodeOpcode == Opc)
           break;
       
         // Otherwise, skip over this case.

Modified: llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp?rev=99494&r1=99493&r2=99494&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp Thu Mar 25 01:33:05 2010
@@ -255,9 +255,9 @@
   }
 
   case Matcher::CheckOpcode:
-    OS << "OPC_CheckOpcode, "
-       << cast<CheckOpcodeMatcher>(N)->getOpcode().getEnumName() << ",\n";
-    return 2;
+    OS << "OPC_CheckOpcode, TARGET_OPCODE("
+       << cast<CheckOpcodeMatcher>(N)->getOpcode().getEnumName() << "),\n";
+    return 3;
       
   case Matcher::SwitchOpcode:
   case Matcher::SwitchType: {
@@ -315,16 +315,17 @@
       CurrentIdx += EmitVBRValue(ChildSize, OS);
       
       OS << ' ';
-      if (const SwitchOpcodeMatcher *SOM = dyn_cast<SwitchOpcodeMatcher>(N))
-        OS << SOM->getCaseOpcode(i).getEnumName();
-      else
-        OS << getEnumName(cast<SwitchTypeMatcher>(N)->getCaseType(i));
-      OS << ',';
+      if (const SwitchOpcodeMatcher *SOM = dyn_cast<SwitchOpcodeMatcher>(N)) {
+        OS << "TARGET_OPCODE(" << SOM->getCaseOpcode(i).getEnumName() << "),";
+        CurrentIdx += 2;
+      } else {
+        OS << getEnumName(cast<SwitchTypeMatcher>(N)->getCaseType(i)) << ',';
+        ++CurrentIdx;
+      }
       
       if (!OmitComments)
-        OS << "// ->" << CurrentIdx+ChildSize+1;
+        OS << "// ->" << CurrentIdx+ChildSize;
       OS << '\n';
-      ++CurrentIdx;
       OS << TmpBuf.str();
       CurrentIdx += ChildSize;
     }




From daniel at zuster.org  Thu Mar 25 02:10:01 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 07:10:01 -0000
Subject: [llvm-commits] [llvm] r99498 - in /llvm/trunk/utils/lit/lit:
 LitTestCase.py TestFormats.py lit.py
Message-ID: <20100325071001.C5E2B2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Mar 25 02:10:01 2010
New Revision: 99498

URL: http://llvm.org/viewvc/llvm-project?rev=99498&view=rev
Log:
lit: Add LitTestCase and lit.load_test_suite, for adapting lit based suites for
use with Python's unittest.

Added:
    llvm/trunk/utils/lit/lit/LitTestCase.py
Modified:
    llvm/trunk/utils/lit/lit/TestFormats.py
    llvm/trunk/utils/lit/lit/lit.py

Added: llvm/trunk/utils/lit/lit/LitTestCase.py
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/LitTestCase.py?rev=99498&view=auto
==============================================================================
--- llvm/trunk/utils/lit/lit/LitTestCase.py (added)
+++ llvm/trunk/utils/lit/lit/LitTestCase.py Thu Mar 25 02:10:01 2010
@@ -0,0 +1,30 @@
+import unittest
+import Test
+
+"""
+TestCase adaptor for providing a 'unittest' compatible interface to 'lit' tests.
+"""
+
+class UnresolvedError(RuntimeError):
+    pass
+        
+class LitTestCase(unittest.TestCase):
+    def __init__(self, test, lit_config):
+        unittest.TestCase.__init__(self)
+        self._test = test
+        self._lit_config = lit_config
+
+    def id(self):
+        return self._test.getFullName()
+
+    def shortDescription(self):
+        return self._test.getFullName()
+
+    def runTest(self):
+        tr, output = self._test.config.test_format.execute(
+            self._test, self._lit_config)
+
+        if tr is Test.UNRESOLVED:
+            raise UnresolvedError(output)
+        elif tr.isFailure:
+            self.fail(output)

Modified: llvm/trunk/utils/lit/lit/TestFormats.py
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestFormats.py?rev=99498&r1=99497&r2=99498&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/TestFormats.py (original)
+++ llvm/trunk/utils/lit/lit/TestFormats.py Thu Mar 25 02:10:01 2010
@@ -90,8 +90,9 @@
                             litConfig, localConfig):
         source_path = testSuite.getSourcePath(path_in_suite)
         for filename in os.listdir(source_path):
-            # Ignore dot files.
-            if filename.startswith('.'):
+            # Ignore dot files and excluded tests.
+            if (filename.startswith('.') or
+                filename in localConfig.excludes):
                 continue
 
             filepath = os.path.join(source_path, filename)

Modified: llvm/trunk/utils/lit/lit/lit.py
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/lit.py?rev=99498&r1=99497&r2=99498&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/lit.py (original)
+++ llvm/trunk/utils/lit/lit/lit.py Thu Mar 25 02:10:01 2010
@@ -315,6 +315,48 @@
     except KeyboardInterrupt:
         sys.exit(2)
 
+def load_test_suite(inputs):
+    import unittest
+
+    # Create the global config object.
+    litConfig = LitConfig.LitConfig(progname = 'lit',
+                                    path = [],
+                                    quiet = False,
+                                    useValgrind = False,
+                                    valgrindLeakCheck = False,
+                                    valgrindArgs = [],
+                                    useTclAsSh = False,
+                                    noExecute = False,
+                                    debug = False,
+                                    isWindows = (platform.system()=='Windows'),
+                                    params = {})
+
+    # Load the tests from the inputs.
+    tests = []
+    testSuiteCache = {}
+    localConfigCache = {}
+    for input in inputs:
+        prev = len(tests)
+        tests.extend(getTests(input, litConfig,
+                              testSuiteCache, localConfigCache)[1])
+        if prev == len(tests):
+            litConfig.warning('input %r contained no tests' % input)
+
+    # If there were any errors during test discovery, exit now.
+    if litConfig.numErrors:
+        print >>sys.stderr, '%d errors, exiting.' % litConfig.numErrors
+        sys.exit(2)
+
+    # Return a unittest test suite which just runs the tests in order.
+    def get_test_fn(test):
+        return unittest.FunctionTestCase(
+            lambda: test.config.test_format.execute(
+                test, litConfig),
+            description = test.getFullName())
+
+    from LitTestCase import LitTestCase
+    return unittest.TestSuite([LitTestCase(test, litConfig) for test in tests])
+
 def main():
     # Bump the GIL check interval, its more important to get any one thread to a
     # blocking operation (hopefully exec) than to try and unblock other threads.




From daniel at zuster.org  Thu Mar 25 02:10:06 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 07:10:06 -0000
Subject: [llvm-commits] [llvm] r99499 -
	/llvm/trunk/lib/MC/MachObjectWriter.cpp
Message-ID: <20100325071006.17CF92A6C12D@llvm.org>

Author: ddunbar
Date: Thu Mar 25 02:10:05 2010
New Revision: 99499

URL: http://llvm.org/viewvc/llvm-project?rev=99499&view=rev
Log:
Fix -Asserts warning.

Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=99499&r1=99498&r2=99499&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Mar 25 02:10:05 2010
@@ -276,11 +276,10 @@
                     const MCSectionData &SD, uint64_t FileOffset,
                     uint64_t RelocationsStart, unsigned NumRelocations) {
     uint64_t SectionSize = Layout.getSectionSize(&SD);
-    uint64_t SectionFileSize = Layout.getSectionFileSize(&SD);
 
     // The offset is unused for virtual sections.
     if (Asm.getBackend().isVirtualSection(SD.getSection())) {
-      assert(SectionFileSize == 0 && "Invalid file size!");
+      assert(Layout.getSectionFileSize(&SD) == 0 && "Invalid file size!");
       FileOffset = 0;
     }
 




From daniel at zuster.org  Thu Mar 25 02:10:12 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 07:10:12 -0000
Subject: [llvm-commits] [llvm] r99500 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp
Message-ID: <20100325071012.1CC262A6C12C@llvm.org>

Author: ddunbar
Date: Thu Mar 25 02:10:11 2010
New Revision: 99500

URL: http://llvm.org/viewvc/llvm-project?rev=99500&view=rev
Log:
MC: Explicity track section and fragment ordinals.

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99500&r1=99499&r2=99500&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Thu Mar 25 02:10:11 2010
@@ -91,6 +91,10 @@
   /// initialized.
   uint64_t EffectiveSize;
 
+  /// Ordinal - The global index of this fragment. This is the index across all
+  /// sections, not just the parent section.
+  unsigned Ordinal;
+
   /// @}
 
 protected:
@@ -106,6 +110,9 @@
   MCSectionData *getParent() const { return Parent; }
   void setParent(MCSectionData *Value) { Parent = Value; }
 
+  unsigned getOrdinal() const { return Ordinal; }
+  void setOrdinal(unsigned Value) { Ordinal = Value; }
+
   static bool classof(const MCFragment *O) { return true; }
 
   virtual void dump();
@@ -390,6 +397,9 @@
   iplist<MCFragment> Fragments;
   const MCSection *Section;
 
+  /// Ordinal - The section index in the assemblers section list.
+  unsigned Ordinal;
+
   /// Alignment - The maximum alignment seen in this section.
   unsigned Alignment;
 
@@ -428,6 +438,9 @@
   bool hasInstructions() const { return HasInstructions; }
   void setHasInstructions(bool Value) { HasInstructions = Value; }
 
+  unsigned getOrdinal() const { return Ordinal; }
+  void setOrdinal(unsigned Value) { Ordinal = Value; }
+
   /// @name Fragment Access
   /// @{
 
@@ -451,6 +464,8 @@
   bool empty() const { return Fragments.empty(); }
 
   void dump();
+
+  /// @}
 };
 
 // FIXME: Same concerns as with SectionData.

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99500&r1=99499&r2=99500&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Thu Mar 25 02:10:11 2010
@@ -568,6 +568,18 @@
       llvm::errs() << "assembler backend - pre-layout\n--\n";
       dump(); });
 
+  // Assign section and fragment ordinals, all subsequent backend code is
+  // responsible for updating these in place.
+  unsigned SectionIndex = 0;
+  unsigned FragmentIndex = 0;
+  for (MCAssembler::iterator it = begin(), ie = end(); it != ie; ++it) {
+    it->setOrdinal(SectionIndex++);
+
+    for (MCSectionData::iterator it2 = it->begin(),
+           ie2 = it->end(); it2 != ie2; ++it2)
+      it2->setOrdinal(FragmentIndex++);
+  }
+
   // Layout until everything fits.
   MCAsmLayout Layout(*this);
   while (LayoutOnce(Layout))
@@ -781,6 +793,7 @@
       //
       // FIXME: Add MCAsmLayout utility for this.
       DF->setParent(IF->getParent());
+      DF->setOrdinal(IF->getOrdinal());
       Layout.setFragmentOffset(DF, Layout.getFragmentOffset(IF));
       Layout.setFragmentEffectiveSize(DF, Layout.getFragmentEffectiveSize(IF));
 




From evan.cheng at apple.com  Thu Mar 25 02:16:57 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 07:16:57 -0000
Subject: [llvm-commits] [llvm] r99501 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
Message-ID: <20100325071657.469C42A6C12C@llvm.org>

Author: evancheng
Date: Thu Mar 25 02:16:57 2010
New Revision: 99501

URL: http://llvm.org/viewvc/llvm-project?rev=99501&view=rev
Log:
Scheduler assumes SDDbgValue nodes are in source order. That's true currently. But add an assertion to verify it.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=99501&r1=99500&r2=99501&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Thu Mar 25 02:16:57 2010
@@ -528,8 +528,16 @@
       if (!MI)
         continue;
       MachineBasicBlock *MIBB = MI->getParent();
+#ifndef NDEBUG
+      unsigned LastDIOrder = 0;
+#endif
       for (; DI != DE &&
              (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
+#ifndef NDEBUG
+        assert((*DI)->getOrder() >= LastDIOrder &&
+               "SDDbgValue nodes must be in source order!");
+        LastDIOrder = (*DI)->getOrder();
+#endif
         if ((*DI)->isInvalidated())
           continue;
         MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, MIBB, VRBaseMap, EM);




From isanbard at gmail.com  Thu Mar 25 02:47:17 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 25 Mar 2010 00:47:17 -0700
Subject: [llvm-commits] [llvm] r99336 - in /llvm/trunk: tools/Makefile
	utils/buildit/build_llvm
In-Reply-To: <6a8523d61003241236r3e73a51dvba4c2307e3b3d41@mail.gmail.com>
References: <20100323221533.E7AE42A6C12D@llvm.org>
	<6a8523d61003241236r3e73a51dvba4c2307e3b3d41@mail.gmail.com>
Message-ID: <FC9846E6-1B32-447A-B98A-549B5247E0F0@gmail.com>

I didn't know about that variable. :-) I'll give it a shot tomorrow. Thx.

-bw

On Mar 24, 2010, at 12:36 PM, Daniel Dunbar wrote:

> Hi Bill,
> 
> Why not change to using ONLY_TOOLS to handle this, instead of adding
> yet another specialized Makefile variable?
> 
> - Daniel
> 
> On Tue, Mar 23, 2010 at 3:15 PM, Bill Wendling <isanbard at gmail.com> wrote:
>> Author: void
>> Date: Tue Mar 23 17:15:33 2010
>> New Revision: 99336
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99336&view=rev
>> Log:
>> Use "DISABLE_EDIS" to disable building "edis" explicitly. Don't build it for
>> Apple-style builds.
>> 
>> Modified:
>>    llvm/trunk/tools/Makefile
>>    llvm/trunk/utils/buildit/build_llvm
>> 
>> Modified: llvm/trunk/tools/Makefile
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=99336&r1=99335&r2=99336&view=diff
>> ==============================================================================
>> --- llvm/trunk/tools/Makefile (original)
>> +++ llvm/trunk/tools/Makefile Tue Mar 23 17:15:33 2010
>> @@ -22,7 +22,6 @@
>>                  lli llvm-extract \
>>                  bugpoint llvm-bcanalyzer llvm-stub \
>>                  llvm-mc llvmc
>> -
>> 
>>  # Let users override the set of tools to build from the command line.
>>  ifdef ONLY_TOOLS
>> @@ -38,7 +37,7 @@
>>   # No support for dynamic libraries on windows targets.
>>   ifneq ($(TARGET_OS), $(filter $(TARGET_OS), Cygwin MingW))
>>     PARALLEL_DIRS += edis
>> -
>> +
>>     # gold only builds if binutils is around.  It requires "lto" to build before
>>     # it so it is added to DIRS.
>>     ifdef BINUTILS_INCDIR
>> @@ -54,4 +53,9 @@
>>   PARALLEL_DIRS := $(filter-out edis, $(PARALLEL_DIRS))
>>  endif
>> 
>> +# Don't build edis if we explicitly disabled it.
>> +ifneq ($(DISABLE_EDIS),1)
>> +  PARALLEL_DIRS := $(filter-out edis, $(PARALLEL_DIRS))
>> +endif
>> +
>>  include $(LEVEL)/Makefile.common
>> 
>> Modified: llvm/trunk/utils/buildit/build_llvm
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=99336&r1=99335&r2=99336&view=diff
>> ==============================================================================
>> --- llvm/trunk/utils/buildit/build_llvm (original)
>> +++ llvm/trunk/utils/buildit/build_llvm Tue Mar 23 17:15:33 2010
>> @@ -203,6 +203,7 @@
>>  make $JOBS_FLAG $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \
>>     UNIVERSAL_SDK_PATH=$HOST_SDKROOT \
>>     NO_RUNTIME_LIBS=1 \
>> +    DISABLE_EDIS=1 \
>>     LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \
>>     LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \
>>     CXXFLAGS="-DLLVM_VERSION_INFO='\" Apple Build #$LLVM_VERSION\"'" \
>> @@ -227,6 +228,7 @@
>>  # Install the tree into the destination directory.
>>  make $LOCAL_MAKEFLAGS $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \
>>     NO_RUNTIME_LIBS=1 \
>> +    DISABLE_EDIS=1 \
>>     LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \
>>     LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \
>>     OPTIMIZE_OPTION='-O3' VERBOSE=1 install
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 




From daniel at zuster.org  Thu Mar 25 02:59:33 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 07:59:33 -0000
Subject: [llvm-commits] [zorg] r99502 - in /zorg/trunk/lnt: setup.py
	tests/__init__.py tests/lit.cfg
Message-ID: <20100325075933.4863D2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Mar 25 02:59:33 2010
New Revision: 99502

URL: http://llvm.org/viewvc/llvm-project?rev=99502&view=rev
Log:
LNT: Add 'setup.py test' support.

Added:
    zorg/trunk/lnt/tests/__init__.py
Modified:
    zorg/trunk/lnt/setup.py
    zorg/trunk/lnt/tests/lit.cfg

Modified: zorg/trunk/lnt/setup.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/setup.py?rev=99502&r1=99501&r2=99502&view=diff
==============================================================================
--- zorg/trunk/lnt/setup.py (original)
+++ zorg/trunk/lnt/setup.py Thu Mar 25 02:59:33 2010
@@ -43,6 +43,8 @@
 
     packages = find_packages(),
 
+    test_suite = 'tests.test_all',
+
     entry_points = {
         'console_scripts': [
             'lnt = lnt.lnttool:main',

Added: zorg/trunk/lnt/tests/__init__.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/__init__.py?rev=99502&view=auto
==============================================================================
--- zorg/trunk/lnt/tests/__init__.py (added)
+++ zorg/trunk/lnt/tests/__init__.py Thu Mar 25 02:59:33 2010
@@ -0,0 +1,5 @@
+import os
+from lit import lit
+
+def test_all():
+    return lit.load_test_suite([os.path.dirname(__file__)])

Modified: zorg/trunk/lnt/tests/lit.cfg
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/tests/lit.cfg?rev=99502&r1=99501&r2=99502&view=diff
==============================================================================
--- zorg/trunk/lnt/tests/lit.cfg (original)
+++ zorg/trunk/lnt/tests/lit.cfg Thu Mar 25 02:59:33 2010
@@ -15,6 +15,9 @@
 # suffixes: A list of file extensions to treat as test files.
 config.suffixes = ['.py']
 
+# excludes: A list of individual files to exclude.
+config.excludes = ['__init__.py']
+
 # test_source_root: The root path where tests are located.
 config.test_source_root = os.path.dirname(__file__)
 config.test_exec_root = config.test_source_root




From daniel at zuster.org  Thu Mar 25 02:59:41 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 07:59:41 -0000
Subject: [llvm-commits] [zorg] r99503 - in /zorg/trunk/lnt: CHANGELOG.txt
 README.txt docs/ docs/Makefile docs/README.txt docs/_templates/
 docs/_templates/index.html docs/_templates/indexsidebar.html
 docs/_templates/layout.html docs/changes.rst docs/conf.py docs/contents.rst
 docs/intro.rst docs/make.bat docs/modules/ docs/modules/testing.rst
 docs/tools.rst lnt/__init__.py lnt/formats/__init__.py
 lnt/lnttool/__init__.py lnt/lnttool/create.py lnt/lnttool/import_data.py
 lnt/testing/__init__.py lnt/util/ImportData.py
Message-ID: <20100325075941.8D4102A6C12C@llvm.org>

Author: ddunbar
Date: Thu Mar 25 02:59:41 2010
New Revision: 99503

URL: http://llvm.org/viewvc/llvm-project?rev=99503&view=rev
Log:
LNT: Add/update docs.

Added:
    zorg/trunk/lnt/CHANGELOG.txt
    zorg/trunk/lnt/docs/
    zorg/trunk/lnt/docs/Makefile
    zorg/trunk/lnt/docs/README.txt
    zorg/trunk/lnt/docs/_templates/
    zorg/trunk/lnt/docs/_templates/index.html
    zorg/trunk/lnt/docs/_templates/indexsidebar.html
    zorg/trunk/lnt/docs/_templates/layout.html
    zorg/trunk/lnt/docs/changes.rst
    zorg/trunk/lnt/docs/conf.py
    zorg/trunk/lnt/docs/contents.rst
    zorg/trunk/lnt/docs/intro.rst
    zorg/trunk/lnt/docs/make.bat
    zorg/trunk/lnt/docs/modules/
    zorg/trunk/lnt/docs/modules/testing.rst
    zorg/trunk/lnt/docs/tools.rst
Modified:
    zorg/trunk/lnt/README.txt
    zorg/trunk/lnt/lnt/__init__.py
    zorg/trunk/lnt/lnt/formats/__init__.py
    zorg/trunk/lnt/lnt/lnttool/__init__.py
    zorg/trunk/lnt/lnt/lnttool/create.py
    zorg/trunk/lnt/lnt/lnttool/import_data.py
    zorg/trunk/lnt/lnt/testing/__init__.py
    zorg/trunk/lnt/lnt/util/ImportData.py

Added: zorg/trunk/lnt/CHANGELOG.txt
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/CHANGELOG.txt?rev=99503&view=auto
==============================================================================
--- zorg/trunk/lnt/CHANGELOG.txt (added)
+++ zorg/trunk/lnt/CHANGELOG.txt Thu Mar 25 02:59:41 2010
@@ -0,0 +1,4 @@
+0.3.0 (not yet released)
+========================
+
+* Initial release.

Modified: zorg/trunk/lnt/README.txt
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/README.txt?rev=99503&r1=99502&r2=99503&view=diff
==============================================================================
--- zorg/trunk/lnt/README.txt (original)
+++ zorg/trunk/lnt/README.txt Thu Mar 25 02:59:41 2010
@@ -5,87 +5,16 @@
 infrastructure. This is technically version "3.0" of the LLVM nightly test
 architecture.
 
-LNT is written in Python and implements a WSGI web app on top of Quixote, along
-with utilities for submitting data via LLVM's NewNightlyTest.pl in conjunction
-with LLVM's test-suite repository.
-
 The infrastructure has the following layout:
 
- $ROOT/lnt - Top-level source module
-
- $ROOT/lnt/import - Utilities for converting to the LNT plist format for test
-                    data, and for submitting plists to the server.
-
- $ROOT/lnt/viewer - The LNT web-app itself.
+ $ROOT/lnt - Top-level Python 'lnt' module
 
  $ROOT/db - Database schema, utilities, and examples of the LNT plist format.
 
+ $ROOT/docs - Sphinx documentation for LNT.
+
  $ROOT/tests - Tests for the infrastructure; they currently assume they are
                   running on a system with a live instance available at
                   'http://localhost/zorg/'.
 
-
-Installation Instructions
--------------------------
-
-External Dependencies: SQLAlchemy, Quixote, mod_wsgi, SQLite, MySQL (optional)
-
-Internal Dependencies: MooTools
-
-These are the rough steps to get a working LNT installation:
-
- 1. Install LNT:
-
-      python setup.py install
-
-    It is recommended that you install LNT into a virtualenv.
-
- 2. Create a new LNT installation:
-
-      lnt create path/to/install-dir
-
-    This will create the LNT configuration file, the default database, and a
-    .wsgi wrapper to create the application. You can execute the generated app
-    directly to run with the builtin web server, or use 'lnt runserver' with the
-    path the config file.
-
- 3. Edit the generated 'lnt.cfg' file if necessary, for example to:
-
-    a. Update the databases list.
-
-    b. Update the zorgURL.
-
-    c. Update the nt_emailer configuration.
-
- 4. Add the zorg.wsgi app to your Apache configuration. You should set also
-    configure the WSGIDaemonProcess and WSGIProcessGroup variables if not
-    already done.
-
-    If running in a virtualenv you will need to configure that as well; see the
-    `modwsgi wiki <http://code.google.com/p/modwsgi/wiki/VirtualEnvironments>`_.
-
-
-Development Instructions
-------------------------
-
-Developing LNT should be done under a virtualenv (most likely in 'develop'
-mode). Currently, the tests require:
-
- 1. 'lit', the LLVM test runner, is available.
-
- 2. The hosted application is live at http://localhost/perf/.
-
- 3. lnt/tests/lit.cfg should be modified to have the correct '%email_host' and
-    '%email_to' substitutions.
-
-To run the tests, use, e.g.,
-
-  lit -sv $ROOT/lnt/tests
-
-or
-
-  lit -sv $ZORG_ROOT/test
-
-to run the zorg and LNT tests all at once.
-
-Note that currently the email test will actually send you email.
+For more information, see the web documentation, or docs/.

Added: zorg/trunk/lnt/docs/Makefile
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/Makefile?rev=99503&view=auto
==============================================================================
--- zorg/trunk/lnt/docs/Makefile (added)
+++ zorg/trunk/lnt/docs/Makefile Thu Mar 25 02:59:41 2010
@@ -0,0 +1,120 @@
+# Makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line.
+SPHINXOPTS    =
+SPHINXBUILD   = sphinx-build
+PAPER         =
+BUILDDIR      = _build
+
+# Internal variables.
+PAPEROPT_a4     = -D latex_paper_size=a4
+PAPEROPT_letter = -D latex_paper_size=letter
+ALLSPHINXOPTS   = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .
+
+.PHONY: help clean html dirhtml singlehtml pickle json htmlhelp qthelp epub latex changes linkcheck doctest
+
+all:	html
+
+help:
+	@echo "Please use \`make <target>' where <target> is one of"
+	@echo "  html       to make standalone HTML files"
+	@echo "  dirhtml    to make HTML files named index.html in directories"
+	@echo "  singlehtml to make a single large HTML file"
+	@echo "  pickle     to make pickle files"
+	@echo "  json       to make JSON files"
+	@echo "  htmlhelp   to make HTML files and a HTML help project"
+	@echo "  qthelp     to make HTML files and a qthelp project"
+	@echo "  devhelp    to make HTML files and a Devhelp project"
+	@echo "  epub       to make an epub"
+	@echo "  latex      to make LaTeX files, you can set PAPER=a4 or PAPER=letter"
+	@echo "  latexpdf   to make LaTeX files and run them through pdflatex"
+	@echo "  changes    to make an overview of all changed/added/deprecated items"
+	@echo "  linkcheck  to check all external links for integrity"
+	@echo "  doctest    to run all doctests embedded in the documentation (if enabled)"
+
+clean:
+	-rm -rf $(BUILDDIR)/*
+
+html:
+	$(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
+	@echo
+	@echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
+
+dirhtml:
+	$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml
+	@echo
+	@echo "Build finished. The HTML pages are in $(BUILDDIR)/dirhtml."
+
+singlehtml:
+	$(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(BUILDDIR)/singlehtml
+	@echo
+	@echo "Build finished. The HTML page is in $(BUILDDIR)/singlehtml."
+
+pickle:
+	$(SPHINXBUILD) -b pickle $(ALLSPHINXOPTS) $(BUILDDIR)/pickle
+	@echo
+	@echo "Build finished; now you can process the pickle files."
+
+json:
+	$(SPHINXBUILD) -b json $(ALLSPHINXOPTS) $(BUILDDIR)/json
+	@echo
+	@echo "Build finished; now you can process the JSON files."
+
+htmlhelp:
+	$(SPHINXBUILD) -b htmlhelp $(ALLSPHINXOPTS) $(BUILDDIR)/htmlhelp
+	@echo
+	@echo "Build finished; now you can run HTML Help Workshop with the" \
+	      ".hhp project file in $(BUILDDIR)/htmlhelp."
+
+qthelp:
+	$(SPHINXBUILD) -b qthelp $(ALLSPHINXOPTS) $(BUILDDIR)/qthelp
+	@echo
+	@echo "Build finished; now you can run "qcollectiongenerator" with the" \
+	      ".qhcp project file in $(BUILDDIR)/qthelp, like this:"
+	@echo "# qcollectiongenerator $(BUILDDIR)/qthelp/LNT.qhcp"
+	@echo "To view the help file:"
+	@echo "# assistant -collectionFile $(BUILDDIR)/qthelp/LNT.qhc"
+
+devhelp:
+	$(SPHINXBUILD) -b devhelp $(ALLSPHINXOPTS) _build/devhelp
+	@echo
+	@echo "Build finished."
+	@echo "To view the help file:"
+	@echo "# mkdir -p $$HOME/.local/share/devhelp/LNT"
+	@echo "# ln -s _build/devhelp $$HOME/.local/share/devhelp/LNT"
+	@echo "# devhelp"
+
+epub:
+	$(SPHINXBUILD) -b epub $(ALLSPHINXOPTS) $(BUILDDIR)/epub
+	@echo
+	@echo "Build finished. The epub file is in $(BUILDDIR)/epub."
+
+latex:
+	$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
+	@echo
+	@echo "Build finished; the LaTeX files are in $(BUILDDIR)/latex."
+	@echo "Run \`make all-pdf' or \`make all-ps' in that directory to" \
+	      "run these through (pdf)latex."
+
+latexpdf: latex
+	$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) _build/latex
+	@echo "Running LaTeX files through pdflatex..."
+	make -C _build/latex all-pdf
+	@echo "pdflatex finished; the PDF files are in _build/latex."
+
+changes:
+	$(SPHINXBUILD) -b changes $(ALLSPHINXOPTS) $(BUILDDIR)/changes
+	@echo
+	@echo "The overview file is in $(BUILDDIR)/changes."
+
+linkcheck:
+	$(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck
+	@echo
+	@echo "Link check complete; look for any errors in the above output " \
+	      "or in $(BUILDDIR)/linkcheck/output.txt."
+
+doctest:
+	$(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest
+	@echo "Testing of doctests in the sources finished, look at the " \
+	      "results in $(BUILDDIR)/doctest/output.txt."

Added: zorg/trunk/lnt/docs/README.txt
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/README.txt?rev=99503&view=auto
==============================================================================
--- zorg/trunk/lnt/docs/README.txt (added)
+++ zorg/trunk/lnt/docs/README.txt Thu Mar 25 02:59:41 2010
@@ -0,0 +1,7 @@
+ LNT Documentation
+==================
+
+The LNT documentation is written using the Sphinx documentation generator. It is
+currently tested with Sphinx 1.0dev.
+
+We currently use the 'nature' theme and a Beaker inspired structure.

Added: zorg/trunk/lnt/docs/_templates/index.html
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/_templates/index.html?rev=99503&view=auto
==============================================================================
--- zorg/trunk/lnt/docs/_templates/index.html (added)
+++ zorg/trunk/lnt/docs/_templates/index.html Thu Mar 25 02:59:41 2010
@@ -0,0 +1,38 @@
+{% extends "layout.html" %}
+{% set title = 'LNT' %}
+{% block body %}
+<h1>LNT - LLVM Performance Tracking Software</h1>
+
+<p>
+  LNT is LLVM's performance tracking software. This is the web page for the LNT
+  software itself, the current online version of the server is available
+  at <a href="http://llvm.org/perf/">http://llvm.org/perf/</a>.
+</p>
+
+<h2>Documentation</h2>
+<table class="contentstable" align="center" style="margin-left: 30px">
+  <tr>
+    <td width="50%">
+      <p class="biglink"><a class="biglink" href="{{ pathto("contents") }}">
+          Contents</a><br/>
+        <span class="linkdescr">for a complete overview</span></p>
+      <p class="biglink"><a class="biglink" href="{{ pathto("search") }}">
+          Search page</a><br/>
+        <span class="linkdescr">search the documentation</span></p>
+    </td><td width="50%">
+      <p class="biglink"><a class="biglink" href="{{ pathto("genindex") }}">
+          General Index</a><br/>
+        <span class="linkdescr">all functions, classes, terms</span></p>
+      <p class="biglink"><a class="biglink" href="{{ pathto("modindex") }}">
+          Module Index</a><br/>
+        <span class="linkdescr">quick access to all documented modules</span></p>
+  </td></tr>
+</table>
+
+<h2>Source</h2>
+<p>LNT is available in the LLVM "zorg" SVN repository:
+  <tt>svn co
+    <a href="http://llvm.org/svn/llvm-project/zorg/trunk/lnt">
+      http://llvm.org/svn/llvm-project/zorg/trunk/lnt</a></tt>.</p>
+
+{% endblock %}

Added: zorg/trunk/lnt/docs/_templates/indexsidebar.html
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/_templates/indexsidebar.html?rev=99503&view=auto
==============================================================================
--- zorg/trunk/lnt/docs/_templates/indexsidebar.html (added)
+++ zorg/trunk/lnt/docs/_templates/indexsidebar.html Thu Mar 25 02:59:41 2010
@@ -0,0 +1,18 @@
+<h3>Download</h3>
+<ul>
+  <li><a href="lnt-{{ version }}.tar.gz">
+      Current version: {{ version }}</a>.</li>
+</ul>
+
+<h3>Install</h3>
+<ul>
+  <li>Current release:<br>
+    <tt>easy_install lnt=={{ version }}</tt></li>
+  <li>Development release:<br>
+    <tt>easy_install lnt==dev</tt></li>
+</ul>
+
+<h3>Bugs</h3>
+
+<p>LNT bugs should be reported at the
+  LLVM <a href="http://llvm.org/bugs">Bugzilla</a>.</p>

Added: zorg/trunk/lnt/docs/_templates/layout.html
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/_templates/layout.html?rev=99503&view=auto
==============================================================================
--- zorg/trunk/lnt/docs/_templates/layout.html (added)
+++ zorg/trunk/lnt/docs/_templates/layout.html Thu Mar 25 02:59:41 2010
@@ -0,0 +1,13 @@
+{% extends "!layout.html" %}
+
+{% block extrahead %}
+<style type="text/css">
+  table.right { float: right; margin-left: 20px; }
+  table.right td { border: 1px solid #ccc; }
+</style>
+{% endblock %}
+
+{% block rootrellink %}
+  <li><a href="{{ pathto('index') }}">LNT Home</a>&nbsp;|&nbsp;</li>
+  <li><a href="{{ pathto('contents') }}">Documentation</a>&raquo;</li>
+{% endblock %}

Added: zorg/trunk/lnt/docs/changes.rst
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/changes.rst?rev=99503&view=auto
==============================================================================
--- zorg/trunk/lnt/docs/changes.rst (added)
+++ zorg/trunk/lnt/docs/changes.rst Thu Mar 25 02:59:41 2010
@@ -0,0 +1,8 @@
+:tocdepth: 2
+
+.. _changes:
+
+Changelog
+*********
+
+.. include:: ../CHANGELOG.txt

Added: zorg/trunk/lnt/docs/conf.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/conf.py?rev=99503&view=auto
==============================================================================
--- zorg/trunk/lnt/docs/conf.py (added)
+++ zorg/trunk/lnt/docs/conf.py Thu Mar 25 02:59:41 2010
@@ -0,0 +1,242 @@
+# -*- coding: utf-8 -*-
+#
+# LNT documentation build configuration file, created by
+# sphinx-quickstart on Fri Dec 25 10:01:58 2009.
+#
+# This file is execfile()d with the current directory set to its containing dir.
+#
+# Note that not all possible configuration values are present in this
+# autogenerated file.
+#
+# All configuration values have a default; values that are commented out
+# serve to show the default.
+
+import datetime, sys, os
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+sys.path.append(os.path.abspath('..'))
+
+import lnt
+
+project = "LNT"
+project_module = lnt
+
+# -- General configuration -----------------------------------------------------
+
+# If your documentation needs a minimal Sphinx version, state it here.
+#needs_sphinx = '1.0'
+
+# Add any Sphinx extension module names here, as strings. They can be extensions
+# coming with Sphinx (named 'sphinx.ext.*') or your custom ones.
+extensions = ['sphinx.ext.autodoc', 'sphinx.ext.doctest', 'sphinx.ext.coverage']
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# The suffix of source filenames.
+source_suffix = '.rst'
+
+# The encoding of source files.
+#source_encoding = 'utf-8-sig'
+
+# The master toctree document.
+master_doc = 'contents'
+
+# General information about the project.
+copyright = u'%s, %s' % (datetime.datetime.now().year,
+                         project_module.__author__)
+
+# The version info for the project you're documenting, acts as replacement for
+# |version| and |release|, also used in various other places throughout the
+# built documents.
+#
+# The short X.Y version.
+version = project_module.__version__
+# The full version, including alpha/beta/rc tags.
+release = project_module.__version__
+
+# The language for content autogenerated by Sphinx. Refer to documentation
+# for a list of supported languages.
+#language = None
+
+# There are two options for replacing |today|: either, you set today to some
+# non-false value, then it is used:
+#today = ''
+# Else, today_fmt is used as the format for a strftime call.
+today_fmt = '%Y-%m-%d'
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+exclude_patterns = ['_build']
+
+# The reST default role (used for this markup: `text`) to use for all documents.
+#default_role = None
+
+# If true, '()' will be appended to :func: etc. cross-reference text.
+#add_function_parentheses = True
+
+# If true, the current module name will be prepended to all description
+# unit titles (such as .. function::).
+#add_module_names = True
+
+# If true, sectionauthor and moduleauthor directives will be shown in the
+# output. They are ignored by default.
+show_authors = True
+
+# The name of the Pygments (syntax highlighting) style to use.
+pygments_style = 'sphinx'
+
+# A list of ignored prefixes for module index sorting.
+#modindex_common_prefix = []
+
+
+# -- Options for HTML output ---------------------------------------------------
+
+# The theme to use for HTML and HTML Help pages.  Major themes that come with
+# Sphinx are currently 'default' and 'sphinxdoc'.
+html_theme = 'nature'
+
+# Theme options are theme-specific and customize the look and feel of a theme
+# further.  For a list of options available for each theme, see the
+# documentation.
+#html_theme_options = {}
+
+# Add any paths that contain custom themes here, relative to this directory.
+#html_theme_path = []
+
+# The name for this set of Sphinx documents.  If None, it defaults to
+# "<project> v<release> documentation".
+#html_title = None
+
+# A shorter title for the navigation bar.  Default is the same as html_title.
+#html_short_title = None
+
+# The name of an image file (relative to this directory) to place at the top
+# of the sidebar.
+#html_logo = None
+
+# The name of an image file (within the static path) to use as favicon of the
+# docs.  This file should be a Windows icon file (.ico) being 16x16 or 32x32
+# pixels large.
+#html_favicon = None
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+#html_static_path = ['_static']
+
+# If not '', a 'Last updated on:' timestamp is inserted at every page bottom,
+# using the given strftime format.
+html_last_updated_fmt = '%Y-%m-%d'
+
+# If true, SmartyPants will be used to convert quotes and dashes to
+# typographically correct entities.
+#html_use_smartypants = True
+
+# Custom sidebar templates, maps document names to template names.
+html_sidebars = {'index': 'indexsidebar.html'}
+
+# Additional templates that should be rendered to pages, maps page names to
+# template names.
+html_additional_pages = {'index': 'index.html'}
+
+# If false, no module index is generated.
+#html_use_modindex = True
+
+# If false, no index is generated.
+#html_use_index = True
+
+# If true, the index is split into individual pages for each letter.
+#html_split_index = False
+
+# If true, links to the reST sources are added to the pages.
+html_show_sourcelink = False
+
+# If true, "Created using Sphinx" is shown in the HTML footer. Default is True.
+#html_show_sphinx = True
+
+# If true, "(C) Copyright ..." is shown in the HTML footer. Default is True.
+#html_show_copyright = True
+
+# If true, an OpenSearch description file will be output, and all pages will
+# contain a <link> tag referring to it.  The value of this option must be the
+# base URL from which the finished HTML is served.
+#html_use_opensearch = ''
+
+# If nonempty, this is the file name suffix for HTML files (e.g. ".xhtml").
+#html_file_suffix = ''
+
+# Output file base name for HTML help builder.
+htmlhelp_basename = '%sdoc' % project
+
+
+# -- Options for LaTeX output --------------------------------------------------
+
+# The paper size ('letter' or 'a4').
+#latex_paper_size = 'letter'
+
+# The font size ('10pt', '11pt' or '12pt').
+#latex_font_size = '10pt'
+
+# Grouping the document tree into LaTeX files. List of tuples
+# (source start file, target name, title, author, documentclass [howto/manual]).
+latex_documents = [
+  ('contents', '%s.tex' % project, u'%s Documentation' % project,
+   project_module.__author__, 'manual'),
+]
+
+# The name of an image file (relative to this directory) to place at the top of
+# the title page.
+#latex_logo = None
+
+# For "manual" documents, if this is true, then toplevel headings are parts,
+# not chapters.
+#latex_use_parts = False
+
+# Additional stuff for the LaTeX preamble.
+#latex_preamble = ''
+
+# Documents to append as an appendix to all manuals.
+#latex_appendices = []
+
+# If false, no module index is generated.
+#latex_use_modindex = True
+
+
+# -- Options for Epub output ---------------------------------------------------
+
+# Bibliographic Dublin Core info.
+#epub_title = ''
+#epub_author = ''
+#epub_publisher = ''
+#epub_copyright = ''
+
+# The language of the text. It defaults to the language option
+# or en if the language is not set.
+#epub_language = ''
+
+# The scheme of the identifier. Typical schemes are ISBN or URL.
+#epub_scheme = ''
+
+# The unique identifier of the text. This can be a ISBN number
+# or the project homepage.
+#epub_identifier = ''
+
+# A unique identification for the text.
+#epub_uid = ''
+
+# HTML files that should be inserted before the pages created by sphinx.
+# The format is a list of tuples containing the path and title.
+#epub_pre_files = []
+
+# HTML files shat should be inserted after the pages created by sphinx.
+# The format is a list of tuples containing the path and title.
+#epub_post_files = []
+
+# A list of files that should not be packed into the epub file.
+#epub_exclude_files = []
+
+# The depth of the table of contents in toc.ncx.
+#epub_tocdepth = 3

Added: zorg/trunk/lnt/docs/contents.rst
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/contents.rst?rev=99503&view=auto
==============================================================================
--- zorg/trunk/lnt/docs/contents.rst (added)
+++ zorg/trunk/lnt/docs/contents.rst Thu Mar 25 02:59:41 2010
@@ -0,0 +1,30 @@
+.. _contents:
+
+Contents
+========
+
+.. toctree::
+   :maxdepth: 2
+
+   intro
+
+   tools
+
+   changes
+
+
+Indices and tables
+==================
+
+* :ref:`genindex`
+* :ref:`modindex`
+* :ref:`search`
+
+
+Module Listing
+--------------
+
+.. toctree::
+   :maxdepth: 2
+
+   modules/testing

Added: zorg/trunk/lnt/docs/intro.rst
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/intro.rst?rev=99503&view=auto
==============================================================================
--- zorg/trunk/lnt/docs/intro.rst (added)
+++ zorg/trunk/lnt/docs/intro.rst Thu Mar 25 02:59:41 2010
@@ -0,0 +1,105 @@
+Introduction
+============
+
+LNT consists of two main parts, a server side web application for accessing and
+visualizing performance data, and client side utilities for easily generating
+and submitting data.
+
+LNT uses a simple and extensible format for interchanging data between the
+clients and the server; this allows the LNT server to receive and store data for
+a wide variety of applications. The web app currently contains a specialized
+viewer for LLVM nightly test data, and a generic viewer for visualizing
+arbitrary test reports.
+
+Both the LNT client and server are written in Python, however the test data
+itself can be passed in one of several formats, including property lists and
+JSON. This makes it easy to produce test results from almost any language.
+
+
+Installation
+------------
+
+These are the (current) rough steps to get a working LNT client:
+
+ 1. Install LNT:
+
+      python setup.py install
+
+    It is recommended that you install LNT into a virtualenv.
+
+If you want to run an LNT server, you will need to perform the following
+additional steps:
+
+ 2. Create a new LNT installation:
+
+      lnt create path/to/install-dir
+
+    This will create the LNT configuration file, the default database, and a
+    .wsgi wrapper to create the application. You can execute the generated app
+    directly to run with the builtin web server, or use 
+
+      lnt runserver path/to/install-dir
+
+    which provides additional command line options. Neither of these servers is
+    recommended for production use.
+
+ 3. Edit the generated 'lnt.cfg' file if necessary, for example to:
+
+    a. Update the databases list.
+
+    b. Update the zorgURL.
+
+    c. Update the nt_emailer configuration.
+
+ 4. Add the 'zorg.wsgi' app to your Apache configuration. You should set also
+    configure the WSGIDaemonProcess and WSGIProcessGroup variables if not
+    already done.
+
+    If running in a virtualenv you will need to configure that as well; see the
+    `modwsgi wiki <http://code.google.com/p/modwsgi/wiki/VirtualEnvironments>`_.
+
+
+Development
+-----------
+
+Developing LNT should be done under a virtualenv (most likely in 'develop'
+mode). Currently, the tests require:
+
+ 1. 'lit', the LLVM test runner, is available.
+
+ 2. The hosted application is live at http://localhost/perf/.
+
+ 3. lnt/tests/lit.cfg should be modified to have the correct '%email_host' and
+    '%email_to' substitutions.
+
+To run the tests, use, e.g.,
+
+  lit -sv $ROOT/lnt/tests
+
+or
+
+  lit -sv $ZORG_ROOT/test
+
+to run the zorg and LNT tests all at once. You can use
+
+  python setup.py test
+
+if you prefer 'unittest' style output (this still requires that 'lit' be
+installed).
+
+Note that currently the email test will actually send you email.
+
+
+Architecture
+------------
+
+The LNT web app is currently implemented as a WSGI web app on top of Quixote,
+along with some facilities from Werkzeug. My tentative plan is to move to Jinja
+for templating, and to move to a more AJAXy web interface.
+
+The database layer uses SQLAlchemy for its ORM, and is typically backed by
+SQLite, although I have tested on MySQL on the past, and supporting other
+databases should be trivial. My plan is to always support SQLite as this allows
+the possibility of developers easily running their own LNT installation for
+viewing nightly test results, and to run with whatever DB makes the most sense
+on the server.

Added: zorg/trunk/lnt/docs/make.bat
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/make.bat?rev=99503&view=auto
==============================================================================
--- zorg/trunk/lnt/docs/make.bat (added)
+++ zorg/trunk/lnt/docs/make.bat Thu Mar 25 02:59:41 2010
@@ -0,0 +1,113 @@
+ at ECHO OFF
+
+REM Command file for Sphinx documentation
+
+set SPHINXBUILD=sphinx-build
+set BUILDDIR=_build
+set ALLSPHINXOPTS=-d %BUILDDIR%/doctrees %SPHINXOPTS% .
+if NOT "%PAPER%" == "" (
+	set ALLSPHINXOPTS=-D latex_paper_size=%PAPER% %ALLSPHINXOPTS%
+)
+
+if "%1" == "" goto help
+
+if "%1" == "help" (
+	:help
+	echo.Please use `make ^<target^>` where ^<target^> is one of
+	echo.  html      to make standalone HTML files
+	echo.  dirhtml   to make HTML files named index.html in directories
+	echo.  pickle    to make pickle files
+	echo.  json      to make JSON files
+	echo.  htmlhelp  to make HTML files and a HTML help project
+	echo.  qthelp    to make HTML files and a qthelp project
+	echo.  latex     to make LaTeX files, you can set PAPER=a4 or PAPER=letter
+	echo.  changes   to make an overview over all changed/added/deprecated items
+	echo.  linkcheck to check all external links for integrity
+	echo.  doctest   to run all doctests embedded in the documentation if enabled
+	goto end
+)
+
+if "%1" == "clean" (
+	for /d %%i in (%BUILDDIR%\*) do rmdir /q /s %%i
+	del /q /s %BUILDDIR%\*
+	goto end
+)
+
+if "%1" == "html" (
+	%SPHINXBUILD% -b html %ALLSPHINXOPTS% %BUILDDIR%/html
+	echo.
+	echo.Build finished. The HTML pages are in %BUILDDIR%/html.
+	goto end
+)
+
+if "%1" == "dirhtml" (
+	%SPHINXBUILD% -b dirhtml %ALLSPHINXOPTS% %BUILDDIR%/dirhtml
+	echo.
+	echo.Build finished. The HTML pages are in %BUILDDIR%/dirhtml.
+	goto end
+)
+
+if "%1" == "pickle" (
+	%SPHINXBUILD% -b pickle %ALLSPHINXOPTS% %BUILDDIR%/pickle
+	echo.
+	echo.Build finished; now you can process the pickle files.
+	goto end
+)
+
+if "%1" == "json" (
+	%SPHINXBUILD% -b json %ALLSPHINXOPTS% %BUILDDIR%/json
+	echo.
+	echo.Build finished; now you can process the JSON files.
+	goto end
+)
+
+if "%1" == "htmlhelp" (
+	%SPHINXBUILD% -b htmlhelp %ALLSPHINXOPTS% %BUILDDIR%/htmlhelp
+	echo.
+	echo.Build finished; now you can run HTML Help Workshop with the ^
+.hhp project file in %BUILDDIR%/htmlhelp.
+	goto end
+)
+
+if "%1" == "qthelp" (
+	%SPHINXBUILD% -b qthelp %ALLSPHINXOPTS% %BUILDDIR%/qthelp
+	echo.
+	echo.Build finished; now you can run "qcollectiongenerator" with the ^
+.qhcp project file in %BUILDDIR%/qthelp, like this:
+	echo.^> qcollectiongenerator %BUILDDIR%\qthelp\LNT.qhcp
+	echo.To view the help file:
+	echo.^> assistant -collectionFile %BUILDDIR%\qthelp\LNT.ghc
+	goto end
+)
+
+if "%1" == "latex" (
+	%SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex
+	echo.
+	echo.Build finished; the LaTeX files are in %BUILDDIR%/latex.
+	goto end
+)
+
+if "%1" == "changes" (
+	%SPHINXBUILD% -b changes %ALLSPHINXOPTS% %BUILDDIR%/changes
+	echo.
+	echo.The overview file is in %BUILDDIR%/changes.
+	goto end
+)
+
+if "%1" == "linkcheck" (
+	%SPHINXBUILD% -b linkcheck %ALLSPHINXOPTS% %BUILDDIR%/linkcheck
+	echo.
+	echo.Link check complete; look for any errors in the above output ^
+or in %BUILDDIR%/linkcheck/output.txt.
+	goto end
+)
+
+if "%1" == "doctest" (
+	%SPHINXBUILD% -b doctest %ALLSPHINXOPTS% %BUILDDIR%/doctest
+	echo.
+	echo.Testing of doctests in the sources finished, look at the ^
+results in %BUILDDIR%/doctest/output.txt.
+	goto end
+)
+
+:end

Added: zorg/trunk/lnt/docs/modules/testing.rst
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/modules/testing.rst?rev=99503&view=auto
==============================================================================
--- zorg/trunk/lnt/docs/modules/testing.rst (added)
+++ zorg/trunk/lnt/docs/modules/testing.rst Thu Mar 25 02:59:41 2010
@@ -0,0 +1,5 @@
+:mod:`lnt.testing` -- Test Data Creation
+========================================
+
+.. automodule:: lnt.testing
+   :members:

Added: zorg/trunk/lnt/docs/tools.rst
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/tools.rst?rev=99503&view=auto
==============================================================================
--- zorg/trunk/lnt/docs/tools.rst (added)
+++ zorg/trunk/lnt/docs/tools.rst Thu Mar 25 02:59:41 2010
@@ -0,0 +1,56 @@
+The ``lnt`` Tool
+================
+
+The ``lnt`` command line utility provides the following commands for client-side
+use and server-side use. The following is a list of commands and the most
+importat options, use ``lnt <toolname> --help`` for more information on any
+particular tool.
+
+Client-Side Tools
+-----------------
+
+  ``lnt checkformat [<file>]``
+    Checks the syntax of an LNT test report file. In addition to verifying that
+    LNT can read the raw format (e.g., JSON or property list), this also creates
+    a temporary in-memory database instance and insures that the test report
+    file can be imported correctly.
+
+    If run without arguments, this expects to read the input file from ``stdin``.
+
+  ``lnt convert <input path> [<output path>]``
+    Convert between LNT test report formats. By default, this will convert to
+    the property list format. You can use ``-`` for either the input (to read
+    from ``stdin) or the output (to write to ``stdout``).
+
+  ``lnt submit [--commit=1] <server url> <file>+``
+    Submits one or more files to the given server. The ``<server url>`` should
+    be the url to the actual ``submitRun`` page on the server; the database
+    being submitted to is effectively a part of this URL.
+
+    By default, this only submits the report to the server but does not actually
+    commit the data. When testing, you should verify that the server returns an
+    acceptable response before committing runs.
+
+
+Server-Side Tools
+-----------------
+
+The following tools are used to interact with an LNT server:
+
+  ``lnt create <path>``
+    Creates a new LNT server instance. This command has a number of parameters
+    to tweak the generated server, but they can all be modified after the fact
+    in the LNT configuration file.
+
+    The default server will have one database named *default*.
+
+  ``lnt import <path | config file> <file>+``
+    Import an LNT data file into a database. You can use ``--database`` to
+    select the database to write to. Note that by default this will also
+    generate report emails if enabled in the configuration, you can use
+    ``--no-email`` to disable this.
+
+  ``lnt runserver <path | config file>``
+    Start the LNT server using a development WSGI server. Additional options can
+    be used to control the server host and port, as well as useful development
+    features such as automatic reloading.

Modified: zorg/trunk/lnt/lnt/__init__.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/__init__.py?rev=99503&r1=99502&r2=99503&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/__init__.py (original)
+++ zorg/trunk/lnt/lnt/__init__.py Thu Mar 25 02:59:41 2010
@@ -1,6 +1,6 @@
 __author__ = 'Daniel Dunbar'
 __email__ = 'daniel at zuster.org'
 __versioninfo__ = (0, 3, 0)
-__version__ = '.'.join(map(str, __versioninfo__))
+__version__ = '.'.join(map(str, __versioninfo__)) + 'dev'
 
 __all__ = []

Modified: zorg/trunk/lnt/lnt/formats/__init__.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/formats/__init__.py?rev=99503&r1=99502&r2=99503&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/formats/__init__.py (original)
+++ zorg/trunk/lnt/lnt/formats/__init__.py Thu Mar 25 02:59:41 2010
@@ -1,5 +1,10 @@
 """
 Utilities for converting to LNT's test format.
+
+LNT formats are described by dictionaries with 'name', 'read', and 'write'
+fields. Only the 'name' field is required. The 'read' field should be a callable
+taking a path_or_file object, the 'write' function should be a callable taking a
+Python object to write, and the path_or_file to write to.
 """
 
 from AppleOpenSSLReader import format as apple_openssl
@@ -13,6 +18,11 @@
 format_names = formats_by_name.keys()
 
 def get_format(name):
+    """get_format(name) -> [format]
+
+    Loookup a format object by name.
+    """
+
     return formats_by_name.get(name)
     
 def guess_format(path_or_file):
@@ -51,6 +61,11 @@
     return matches
 
 def read_any(path_or_file, format_name):
+    """read_any(path_or_file, format_name) -> [format]
+
+    Attempt to read any compatible LNT test format file. The format_name can be
+    an actual format name, or "<auto>".
+    """
     # Figure out the input format.
     if format_name == '<auto>':
         f = guess_format(path_or_file)
@@ -65,3 +80,5 @@
             raise SystemExit("unknown input format: %r" % inFormat)
 
     return f['read'](path_or_file)
+
+__all__ = ['get_format', 'guess_format', 'read_any'] + format_names

Modified: zorg/trunk/lnt/lnt/lnttool/__init__.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/__init__.py?rev=99503&r1=99502&r2=99503&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/lnttool/__init__.py (original)
+++ zorg/trunk/lnt/lnt/lnttool/__init__.py Thu Mar 25 02:59:41 2010
@@ -80,7 +80,7 @@
     """submit a test report to the server."""
 
     from optparse import OptionParser, OptionGroup
-    parser = OptionParser("%%prog %s [options] url files+" % name)
+    parser = OptionParser("%%prog %s [options] <url> <file>+" % name)
     parser.add_option("", "--commit", dest="commit", type=int,
                       default=False)
 

Modified: zorg/trunk/lnt/lnt/lnttool/create.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/create.py?rev=99503&r1=99502&r2=99503&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/lnttool/create.py (original)
+++ zorg/trunk/lnt/lnt/lnttool/create.py Thu Mar 25 02:59:41 2010
@@ -75,7 +75,7 @@
     """create an LLVM nightly test installation"""
 
     from optparse import OptionParser, OptionGroup
-    parser = OptionParser("%%prog %s [options] [<path|config file>]" % name)
+    parser = OptionParser("%%prog %s [options] <path>" % name)
     parser.add_option("", "--name", dest="name", default="LNT",
                       help="name to use for the installation [%default]")
     parser.add_option("", "--config", dest="config", default="lnt.cfg",

Modified: zorg/trunk/lnt/lnt/lnttool/import_data.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/import_data.py?rev=99503&r1=99502&r2=99503&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/lnttool/import_data.py (original)
+++ zorg/trunk/lnt/lnt/lnttool/import_data.py Thu Mar 25 02:59:41 2010
@@ -9,7 +9,7 @@
 
     from optparse import OptionParser, OptionGroup
 
-    parser = OptionParser("%%prog %s [options] <path|config-file> file+" %name)
+    parser = OptionParser("%%prog %s [options] <path|config-file> <file>+"%name)
     parser.add_option("", "--database", dest="database", default="default",
                       help="database to write to [%default]")
     parser.add_option("", "--format", dest="format",

Modified: zorg/trunk/lnt/lnt/testing/__init__.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/testing/__init__.py?rev=99503&r1=99502&r2=99503&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/testing/__init__.py (original)
+++ zorg/trunk/lnt/lnt/testing/__init__.py Thu Mar 25 02:59:41 2010
@@ -1,5 +1,9 @@
 """
 Utilities for working with the LNT test format.
+
+Clients can easily generate LNT test format data by creating Report objects for
+the runs they wish to submit, and using Report.render to convert them to JSON
+data suitable for submitting to the server.
 """
 
 import time
@@ -13,7 +17,37 @@
         t = time.strptime(start_time, '%Y-%m-%d %H:%M:%S')
     return t.strftime('%Y-%m-%d %H:%M:%S')
 
+class Report:
+    """Information on a single testing run.
+
+    In the LNT test model, every test run should define exactly one machine and
+    run, and any number of test samples.
+    """
+    def __init__(self, machine, run, tests):
+        self.machine = machine
+        self.run = run
+        self.tests = list(tests)
+
+        assert isinstance(self.machine, Machine)
+        assert isinstance(self.run, Run)
+        for t in self.tests:
+            assert isinstance(t, TestSamples)
+
+    def render(self):
+        return json.dumps({ 'Machine' : self.machine.render(),
+                            'Run' : self.run.render(),
+                            'Tests' : [t.render() for t in self.tests] },
+                          sort_keys=True, indent=4)
+
 class Machine:
+    """Information on the machine the test was run on.
+
+    The info dictionary can be used to describe additional information about the
+    machine, for example the hardware resources or the operating environment.
+
+    Machines entries in the database are uniqued by their name and the entire
+    contents of the info dictionary.
+    """
     def __init__(self, name, info={}):
         self.name = str(name)
         self.info = dict((str(key),str(value))
@@ -24,6 +58,19 @@
                  'Info' : self.info }
 
 class Run:
+    """Information on the particular test run.
+
+    The start and end time should always be supplied with the run. Currently,
+    the server uses these to order runs. In the future we will support
+    additional ways to order runs (for example, by a source revision).
+
+    As with Machine, the info dictionary can be used to describe additional
+    information on the run. This dictionary should be used to describe
+    information on the software-under-test that is constant across the test run,
+    for example the revision number being tested. It can also be used to
+    describe information about the current state which could be useful in
+    analysis, for example the current machine load.
+    """
     def __init__(self, start_time, end_time, info={}):
         if start_time is None:
             start_time = datetime.datetime.now()
@@ -41,6 +88,33 @@
                  'Info' : self.info }
 
 class TestSamples:
+    """Test sample data.
+
+    The test sample data defines both the tests that were run and their
+    values. The server automatically creates test database objects whenever a
+    new test name is seen.
+
+    Test names are intended to be a persistent, recognizable identifier for what
+    is being executed. Currently, most formats use some form of dotted notation
+    for the test name, and this may become enshrined in the format in the
+    future. In general, the test names should be independent of the
+    software-under-test and refer to some known quantity, for example the
+    software under test. For example, 'CINT2006.403_gcc' is a meaningful test
+    name.
+
+    The test info dictionary is intended to hold information on the particular
+    permutation of the test that was run. This might include variables specific
+    to the software-under-test . This could include, for example, the compile
+    flags the test was built with, or the runtime parameters that were used. As
+    a general rule, if two test samples are meaningfully and directly
+    comparable, then the should have the same test name but different info
+    paramaters.
+
+    The report may include an arbitrary number of samples for each test for
+    situations where the same test is run multiple times to gather statistical
+    data.
+    """
+
     def __init__(self, name, data, info={}):
         self.name = str(name)
         self.info = dict((str(key),str(value))
@@ -52,21 +126,4 @@
                  'Info' : self.info,
                  'Data' : self.data }
 
-class Report:
-    def __init__(self, machine, run, tests):
-        self.machine = machine
-        self.run = run
-        self.tests = list(tests)
-
-        assert isinstance(self.machine, Machine)
-        assert isinstance(self.run, Run)
-        for t in self.tests:
-            assert isinstance(t, TestSamples)
-
-    def render(self):
-        return json.dumps({ 'Machine' : self.machine.render(),
-                            'Run' : self.run.render(),
-                            'Tests' : [t.render() for t in self.tests] },
-                          sort_keys=True, indent=4)
-
-__all__ = ['Machine', 'Run', 'TestSamples', 'Report']
+__all__ = ['Report', 'Machine', 'Run', 'TestSamples']

Modified: zorg/trunk/lnt/lnt/util/ImportData.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/ImportData.py?rev=99503&r1=99502&r2=99503&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/util/ImportData.py (original)
+++ zorg/trunk/lnt/lnt/util/ImportData.py Thu Mar 25 02:59:41 2010
@@ -7,10 +7,14 @@
 def import_and_report(config, db_name, db, file, log, format, commit=False,
                       show_sample_count=False, disable_email=False):
     """
-    import_file(config, db_name, db, file) -> (success, run, log)
-
-    Import a test data file into the database. On success, run is the newly
-    imported run.
+    import_and_report(config, db_name, db, file, log, format,
+                      [commit], [show_sample_count],
+                      [disable_email]) -> (success, run)
+
+    Import a test data file into an LNT server and generate a test report. On
+    success, run is the newly imported run. Note that success is uneffected by
+    the value of commit, this merely changes whether the run (on success) is
+    committed to the database.
     """
     numMachines = db.getNumMachines()
     numRuns = db.getNumRuns()




From daniel at zuster.org  Thu Mar 25 03:08:54 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 08:08:54 -0000
Subject: [llvm-commits] [llvm] r99504 -
	/llvm/trunk/lib/MC/MachObjectWriter.cpp
Message-ID: <20100325080854.BC7822A6C12C@llvm.org>

Author: ddunbar
Date: Thu Mar 25 03:08:54 2010
New Revision: 99504

URL: http://llvm.org/viewvc/llvm-project?rev=99504&view=rev
Log:
MC/Mach-O: Switch to MCSectionData::getOrdinal.

Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=99504&r1=99503&r2=99504&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Mar 25 03:08:54 2010
@@ -559,15 +559,8 @@
         if (Base != &SD)
           Value += Layout.getSymbolAddress(&SD) - Layout.getSymbolAddress(Base);
       } else {
-        // The index is the section ordinal.
-        //
-        // FIXME: O(N)
-        Index = 1;
-        MCAssembler::const_iterator it = Asm.begin(), ie = Asm.end();
-        for (; it != ie; ++it, ++Index)
-          if (&*it == SD.getFragment()->getParent())
-            break;
-        assert(it != ie && "Unable to find section index!");
+        // The index is the section ordinal (1-based).
+        Index = SD.getFragment()->getParent()->getOrdinal() + 1;
         IsExtern = 0;
         Value += Layout.getSymbolAddress(&SD);
 
@@ -747,15 +740,8 @@
         Index = SD->getIndex();
         Value = 0;
       } else {
-        // The index is the section ordinal.
-        //
-        // FIXME: O(N)
-        Index = 1;
-        MCAssembler::const_iterator it = Asm.begin(), ie = Asm.end();
-        for (; it != ie; ++it, ++Index)
-          if (&*it == SD->getFragment()->getParent())
-            break;
-        assert(it != ie && "Unable to find section index!");
+        // The index is the section ordinal (1-based).
+        Index = SD->getFragment()->getParent()->getOrdinal() + 1;
         Value = Layout.getSymbolAddress(SD);
       }
 




From criswell at uiuc.edu  Thu Mar 25 08:59:09 2010
From: criswell at uiuc.edu (John Criswell)
Date: Thu, 25 Mar 2010 13:59:09 -0000
Subject: [llvm-commits] [llvm] r99506 - in /llvm/trunk:
	autoconf/configure.ac configure
Message-ID: <20100325135909.43B592A6C12C@llvm.org>

Author: criswell
Date: Thu Mar 25 08:59:09 2010
New Revision: 99506

URL: http://llvm.org/viewvc/llvm-project?rev=99506&view=rev
Log:
Fixed spurious warning problem noticed by Daniel Dunbar.  The configure script
now configures prerequisite projects individually but also ignores them in the
big project switch statement to avoid the incorrect warning.

Modified:
    llvm/trunk/autoconf/configure.ac
    llvm/trunk/configure

Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=99506&r1=99505&r2=99506&view=diff
==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Thu Mar 25 08:59:09 2010
@@ -110,6 +110,11 @@
       llvm-tv)      AC_CONFIG_SUBDIRS([projects/llvm-tv])   ;;
       safecode)     AC_CONFIG_SUBDIRS([projects/safecode]) ;;
       llvm-kernel)  AC_CONFIG_SUBDIRS([projects/llvm-kernel]) ;;
+      llvm-gcc)       ;;
+      test-suite)     ;;
+      llvm-test)      ;;
+      poolalloc)      ;;
+      llvm-poolalloc) ;;
       *)
         AC_MSG_WARN([Unknown project (${i}) won't be configured automatically])
         ;;

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=99506&r1=99505&r2=99506&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Thu Mar 25 08:59:09 2010
@@ -1999,6 +1999,11 @@
  ;;
       llvm-kernel)  subdirs="$subdirs projects/llvm-kernel"
  ;;
+      llvm-gcc)       ;;
+      test-suite)     ;;
+      llvm-test)      ;;
+      poolalloc)      ;;
+      llvm-poolalloc) ;;
       *)
         { echo "$as_me:$LINENO: WARNING: Unknown project (${i}) won't be configured automatically" >&5
 echo "$as_me: WARNING: Unknown project (${i}) won't be configured automatically" >&2;}
@@ -11151,7 +11156,7 @@
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<EOF
-#line 11154 "configure"
+#line 11159 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H




From grosbach at apple.com  Thu Mar 25 10:05:10 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 25 Mar 2010 08:05:10 -0700
Subject: [llvm-commits] [llvm] r99436 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrInfo.td ARMInstrVFP.td
	ARMSubtarget.cpp ARMSubtarget.h
In-Reply-To: <b087fca01003242238s24d448c4m188564c3a1985887@mail.gmail.com>
References: <20100324223146.6B1C42A6C12C@llvm.org>
	<b087fca01003242238s24d448c4m188564c3a1985887@mail.gmail.com>
Message-ID: <9C55B026-52A6-4AC5-B149-FA116AFBA054@apple.com>


On Mar 24, 2010, at 10:38 PM, Anton Korobeynikov wrote:

> Hi, Jim
> 
>> Make the use of the vmla and vmls VFP instructions controllable via cmd line.
>> Preliminary testing shows significant performance wins by not using these
>> instructions.
> not using where? I believe this should be made conditional on A8 only.
> 

Have you run benchmarks on other variants showing the instructions to be a win? This looks to be a pretty fundamental flaw in the VFP unit.

-Jim


From stoklund at 2pi.dk  Thu Mar 25 10:05:31 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 25 Mar 2010 08:05:31 -0700
Subject: [llvm-commits] [llvm] r99485 - in /llvm/trunk:
	lib/CodeGen/SelectionDAG/InstrEmitter.cpp
	test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
	test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
	test/CodeGen/X86/coalesce-esp.ll test/CodeGen/X86/licm-symbol.ll
	test/CodeGen/X86/phys_subreg_coalesce-2.ll
	test/CodeGen/X86/pr2659.ll
In-Reply-To: <20100325054048.CDB172A6C12C@llvm.org>
References: <20100325054048.CDB172A6C12C@llvm.org>
Message-ID: <8981340B-A968-4A2C-B144-A43C509B08C7@2pi.dk>


On Mar 24, 2010, at 10:40 PM, Chris Lattner wrote:

> Author: lattner
> Date: Thu Mar 25 00:40:48 2010
> New Revision: 99485
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99485&view=rev
> Log:
> Make the NDEBUG assertion stronger and more clear what is 
> happening.
> 
> Enhance scheduling to set the DEAD flag on implicit defs
> more aggressively.  Before, we'd set an implicit def operand
> to dead if it were present in the SDNode corresponding to
> the machineinstr but had no use.  Now we do it in this case
> AND if the implicit def does not exist in the SDNode at all.

This patch seems to be upsetting the valgrind testers:

==1772== Invalid read of size 1
==1772==    at 0x85C9B7C: llvm::MachineOperand::isReg() const (MachineOperand.h:152)
==1772==    by 0x8A32FBD: llvm::MachineInstr::addRegisterDead(unsigned int, llvm::TargetRegisterInfo const*, bool) (MachineInstr.cpp:1307)
==1772==    by 0x896459E: llvm::InstrEmitter::EmitMachineNode(llvm::SDNode*, bool, bool, llvm::DenseMap<llvm::SDValue, unsigned int, llvm::DenseMapInfo<llvm::SDValue>, llvm::DenseMapInfo<unsigned int> >&, llvm::DenseMap<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DenseMapInfo<llvm::MachineBasicBlock*>, llvm::DenseMapInfo<llvm::MachineBasicBlock*> >*) (InstrEmitter.cpp:648)
==1772==    by 0x88C8AD2: llvm::InstrEmitter::EmitNode(llvm::SDNode*, bool, bool, llvm::DenseMap<llvm::SDValue, unsigned int, llvm::DenseMapInfo<llvm::SDValue>, llvm::DenseMapInfo<unsigned int> >&, llvm::DenseMap<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DenseMapInfo<llvm::MachineBasicBlock*>, llvm::DenseMapInfo<llvm::MachineBasicBlock*> >*) (InstrEmitter.h:116)
==1772==    by 0x88C7743: llvm::ScheduleDAGSDNodes::EmitSchedule(llvm::DenseMap<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DenseMapInfo<llvm::MachineBasicBlock*>, llvm::DenseMapInfo<llvm::MachineBasicBlock*> >*) (ScheduleDAGSDNodes.cpp:501)
==1772==    by 0x893ACF2: llvm::SelectionDAGISel::CodeGenAndEmitDAG() (SelectionDAGISel.cpp:776)
==1772==    by 0x8938D04: llvm::SelectionDAGISel::SelectBasicBlock(llvm::BasicBlock*, llvm::ilist_iterator<llvm::Instruction>, llvm::ilist_iterator<llvm::Instruction>, bool&) (SelectionDAGISel.cpp:437)
==1772==    by 0x893BA65: llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function&, llvm::MachineFunction&, llvm::MachineModuleInfo*, llvm::DwarfWriter*, llvm::TargetInstrInfo const&) (SelectionDAGISel.cpp:1030)
==1772==    by 0x89387E9: llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) (SelectionDAGISel.cpp:344)
==1772==    by 0x8A2D58A: llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (MachineFunctionPass.cpp:27)
==1772==    by 0x8D30AD0: llvm::FPPassManager::runOnFunction(llvm::Function&) (PassManager.cpp:1350)
==1772==    by 0x8D3080F: llvm::FunctionPassManagerImpl::run(llvm::Function&) (PassManager.cpp:1301)
==1772==  Address 0x7aeeb38 is 0 bytes inside a block of size 120 free'd
==1772==    at 0x779F57D: operator delete(void*) (vg_replace_malloc.c:346)
==1772==    by 0x87136C8: __gnu_cxx::new_allocator<llvm::MachineOperand>::deallocate(llvm::MachineOperand*, unsigned int) (new_allocator.h:95)
==1772==    by 0x871339E: std::_Vector_base<llvm::MachineOperand, std::allocator<llvm::MachineOperand> >::_M_deallocate(llvm::MachineOperand*, unsigned int) (stl_vector.h:146)
==1772==    by 0x8A04AD3: std::_Vector_base<llvm::MachineOperand, std::allocator<llvm::MachineOperand> >::~_Vector_base() (stl_vector.h:132)
==1772==    by 0x8A04272: std::vector<llvm::MachineOperand, std::allocator<llvm::MachineOperand> >::~vector() (stl_vector.h:313)
==1772==    by 0x8A305B9: llvm::MachineInstr::~MachineInstr() (MachineInstr.cpp:521)
==1772==    by 0x8A26296: llvm::MachineFunction::DeleteMachineInstr(llvm::MachineInstr*) (MachineFunction.cpp:203)
==1772==    by 0x8818DC7: llvm::X86TargetLowering::EmitLoweredSelect(llvm::MachineInstr*, llvm::MachineBasicBlock*, llvm::DenseMap<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DenseMapInfo<llvm::MachineBasicBlock*>, llvm::DenseMapInfo<llvm::MachineBasicBlock*> >*) const (X86ISelLowering.cpp:8490)
==1772==    by 0x881923B: llvm::X86TargetLowering::EmitInstrWithCustomInserter(llvm::MachineInstr*, llvm::MachineBasicBlock*, llvm::DenseMap<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DenseMapInfo<llvm::MachineBasicBlock*>, llvm::DenseMapInfo<llvm::MachineBasicBlock*> >*) const (X86ISelLowering.cpp:8538)
==1772==    by 0x896432C: llvm::InstrEmitter::EmitMachineNode(llvm::SDNode*, bool, bool, llvm::DenseMap<llvm::SDValue, unsigned int, llvm::DenseMapInfo<llvm::SDValue>, llvm::DenseMapInfo<unsigned int> >&, llvm::DenseMap<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DenseMapInfo<llvm::MachineBasicBlock*>, llvm::DenseMapInfo<llvm::MachineBasicBlock*> >*) (InstrEmitter.cpp:618)
==1772==    by 0x88C8AD2: llvm::InstrEmitter::EmitNode(llvm::SDNode*, bool, bool, llvm::DenseMap<llvm::SDValue, unsigned int, llvm::DenseMapInfo<llvm::SDValue>, llvm::DenseMapInfo<unsigned int> >&, llvm::DenseMap<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DenseMapInfo<llvm::MachineBasicBlock*>, llvm::DenseMapInfo<llvm::MachineBasicBlock*> >*) (InstrEmitter.h:116)
==1772==    by 0x88C7743: llvm::ScheduleDAGSDNodes::EmitSchedule(llvm::DenseMap<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::DenseMapInfo<llvm::MachineBasicBlock*>, llvm::DenseMapInfo<llvm::MachineBasicBlock*> >*) (ScheduleDAGSDNodes.cpp:501)






From dpatel at apple.com  Thu Mar 25 10:09:44 2010
From: dpatel at apple.com (Devang Patel)
Date: Thu, 25 Mar 2010 15:09:44 -0000
Subject: [llvm-commits] [llvm] r99507 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
Message-ID: <20100325150944.DC76C2A6C12C@llvm.org>

Author: dpatel
Date: Thu Mar 25 10:09:44 2010
New Revision: 99507

URL: http://llvm.org/viewvc/llvm-project?rev=99507&view=rev
Log:
Add comment.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=99507&r1=99506&r2=99507&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Thu Mar 25 10:09:44 2010
@@ -141,6 +141,9 @@
   /// AbstractScopes - Tracks the abstract scopes a module. These scopes are
   /// not included DbgScopeMap.  AbstractScopes owns its DbgScope*s.
   DenseMap<MDNode *, DbgScope *> AbstractScopes;
+
+  /// AbstractScopesList - Tracks abstract scopes constructed while processing
+  /// a function. This list is cleared during endFunction().
   SmallVector<DbgScope *, 4>AbstractScopesList;
 
   /// AbstractVariables - Collection on abstract variables.  Owned by the




From anton at korobeynikov.info  Thu Mar 25 10:42:37 2010
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Thu, 25 Mar 2010 18:42:37 +0300
Subject: [llvm-commits] [llvm] r99436 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrInfo.td ARMInstrVFP.td
	ARMSubtarget.cpp ARMSubtarget.h
In-Reply-To: <9C55B026-52A6-4AC5-B149-FA116AFBA054@apple.com>
References: <20100324223146.6B1C42A6C12C@llvm.org>
	<b087fca01003242238s24d448c4m188564c3a1985887@mail.gmail.com>
	<9C55B026-52A6-4AC5-B149-FA116AFBA054@apple.com>
Message-ID: <b087fca01003250842h5f0e8364x60ff2d268e73495c@mail.gmail.com>

Hello, Jim

> Have you run benchmarks on other variants showing the instructions to be a win? This looks to be a pretty fundamental flaw in the VFP unit.
This is pretty expected on A8, where VFP unit is not pipelined at all
(aka "VFP-lite").
However, for example, on A9 VFP is pipelined and these instructions
should behave properly.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From daniel at zuster.org  Thu Mar 25 11:01:55 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 16:01:55 -0000
Subject: [llvm-commits] [test-suite] r99511 -
 /test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-2.m
Message-ID: <20100325160155.EBD0E2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Mar 25 11:01:55 2010
New Revision: 99511

URL: http://llvm.org/viewvc/llvm-project?rev=99511&view=rev
Log:
Add note on why Clang diverges from GCC on this test.

Modified:
    test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-2.m

Modified: test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-2.m
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-2.m?rev=99511&r1=99510&r2=99511&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-2.m (original)
+++ test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-2.m Thu Mar 25 11:01:55 2010
@@ -11,7 +11,7 @@
 @end
 
 @implementation A
--(int) x { 
+-(int) x {
   return x + 2;
 }
 
@@ -27,6 +27,9 @@
   int res = (a.x += 1);
   printf("res: %d\n", res);
 
+  // This is a case where clang diverges from gcc in Objective-C code
+  // generation. Clang correctly truncates the value in the this assignment to
+  // char, and extends, which is consistent with C semantics.
   res = (a.y = 0xFFFF);
   printf("res: %d\n", res);
 




From grosbach at apple.com  Thu Mar 25 11:03:39 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 25 Mar 2010 09:03:39 -0700
Subject: [llvm-commits] [llvm] r99436 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrInfo.td ARMInstrVFP.td
	ARMSubtarget.cpp ARMSubtarget.h
In-Reply-To: <b087fca01003250842h5f0e8364x60ff2d268e73495c@mail.gmail.com>
References: <20100324223146.6B1C42A6C12C@llvm.org>
	<b087fca01003242238s24d448c4m188564c3a1985887@mail.gmail.com>
	<9C55B026-52A6-4AC5-B149-FA116AFBA054@apple.com>
	<b087fca01003250842h5f0e8364x60ff2d268e73495c@mail.gmail.com>
Message-ID: <D55642FF-7685-4AA7-8FD4-123DFEE1BEE5@apple.com>


On Mar 25, 2010, at 8:42 AM, Anton Korobeynikov wrote:

> Hello, Jim
> 
>> Have you run benchmarks on other variants showing the instructions to be a win? This looks to be a pretty fundamental flaw in the VFP unit.
> This is pretty expected on A8, where VFP unit is not pipelined at all
> (aka "VFP-lite").
> However, for example, on A9 VFP is pipelined and these instructions
> should behave properly.


This isn't expected behaviour on A8 at all. There are additional stalls beyond what can be explained by not being pipelined.




From daniel at zuster.org  Thu Mar 25 11:09:18 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 16:09:18 -0000
Subject: [llvm-commits] [llvm] r99512 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20100325160918.BAC942A6C12C@llvm.org>

Author: ddunbar
Date: Thu Mar 25 11:09:18 2010
New Revision: 99512

URL: http://llvm.org/viewvc/llvm-project?rev=99512&view=rev
Log:
Sketch a few Clang release notes.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=99512&r1=99511&r2=99512&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Thu Mar 25 11:09:18 2010
@@ -127,8 +127,21 @@
 <p>In the LLVM 2.7 time-frame, the Clang team has made many improvements:</p>
 
 <ul>
-<li>...</li>
-include a link to cxx_compatibility.html
+<li>FIXME: C++! Include a link to cxx_compatibility.html</li>
+
+<li>FIXME: Static Analyzer improvements?</li>
+
+<li>CIndex API and Python bindings: Clang now includes a C API as part of the
+CIndex library. Although we make make some changes to the API in the future, it
+is intended to be stable and has been designed for use by external projects. See
+the Clang
+doxygen <a href="http://clang.llvm.org/doxygen/group__CINDEX.html">CIndex</a>
+documentation for more details. The CIndex API also includings an preliminary
+set of Python bindings.</li>
+
+<li>ARM Support: Clang now has ABI support for both the Darwin and Linux ARM
+ABIs. Coupled with many improvements to the LLVM ARM backend, Clang is now
+suitable for use as a a beta quality ARM compiler.</li>
 </ul>
 </div>
 




From bob.wilson at apple.com  Thu Mar 25 11:36:14 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 25 Mar 2010 16:36:14 -0000
Subject: [llvm-commits] [llvm] r99514 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGNodes.h include/llvm/IntrinsicsX86.td
 lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrSSE.td
 test/MC/AsmParser/X86/x86_32-bit_cat.s
 test/MC/AsmParser/X86/x86_32-encoding.s
Message-ID: <20100325163614.6BEDF2A6C12C@llvm.org>

Author: bwilson
Date: Thu Mar 25 11:36:14 2010
New Revision: 99514

URL: http://llvm.org/viewvc/llvm-project?rev=99514&view=rev
Log:
Reapply Kevin's change 94440, now that Chris has fixed the limitation on
opcode values fitting in one byte (svn r99494).

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/include/llvm/IntrinsicsX86.td
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=99514&r1=99513&r2=99514&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Mar 25 11:36:14 2010
@@ -616,7 +616,7 @@
   /// which do not reference a specific memory location should be less than
   /// this value. Those that do must not be less than this value, and can
   /// be used with SelectionDAG::getMemIntrinsicNode.
-  static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+80;
+  static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+85;
 
   /// Node predicates
 

Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=99514&r1=99513&r2=99514&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsX86.td Thu Mar 25 11:36:14 2010
@@ -779,6 +779,25 @@
                         [IntrNoMem, Commutative]>;
 }
 
+// Advanced Encryption Standard (AES) Instructions
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_sse42_aesimc          :
+              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
+                        [IntrNoMem]>;
+  def int_x86_sse42_aesenc          :
+              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
+                        [IntrNoMem]>;
+  def int_x86_sse42_aesenclast      :
+              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
+                        [IntrNoMem]>;
+  def int_x86_sse42_aesdec          :
+              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
+                        [IntrNoMem]>;
+  def int_x86_sse42_aesdeclast      :
+              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
+                        [IntrNoMem]>;
+}
+
 // Vector pack
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse41_packusdw        : GCCBuiltin<"__builtin_ia32_packusdw128">,

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=99514&r1=99513&r2=99514&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Mar 25 11:36:14 2010
@@ -234,6 +234,9 @@
       PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
       PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
 
+      // Advanced Encryption Standard (AES) Instructions
+      AESIMC, AESENC, AESENCLAST, AESDEC, AESDECLAST,
+
       // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
       ADD, SUB, SMUL, UMUL,
       INC, DEC, OR, XOR, AND,

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=99514&r1=99513&r2=99514&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Mar 25 11:36:14 2010
@@ -69,6 +69,12 @@
 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
 
+def X86aesimc          : SDNode<"X86ISD::AESIMC",          SDTIntBinOp>;
+def X86aesenc          : SDNode<"X86ISD::AESENC",          SDTIntBinOp>;
+def X86aesenclast      : SDNode<"X86ISD::AESENCLAST",      SDTIntBinOp>;
+def X86aesdec          : SDNode<"X86ISD::AESDEC",          SDTIntBinOp>;
+def X86aesdeclast      : SDNode<"X86ISD::AESDECLAST",      SDTIntBinOp>;
+
 def SDTX86CmpPTest : SDTypeProfile<0, 2, [SDTCisVT<0, v4f32>,
                                           SDTCisVT<1, v4f32>]>;
 def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
@@ -3817,6 +3823,45 @@
 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
           (PCMPGTQrm VR128:$src1, addr:$src2)>;
 
+defm AESIMC          : SS42I_binop_rm_int<0xDB, "aesimc",
+                       int_x86_sse42_aesimc>;
+defm AESENC          : SS42I_binop_rm_int<0xDC, "aesenc",
+                       int_x86_sse42_aesenc>;
+defm AESENCLAST      : SS42I_binop_rm_int<0xDD, "aesenclast",
+                       int_x86_sse42_aesenclast>;
+defm AESDEC          : SS42I_binop_rm_int<0xDE, "aesdec",
+                       int_x86_sse42_aesdec>;
+defm AESDECLAST      : SS42I_binop_rm_int<0xDF, "aesdeclast",
+                       int_x86_sse42_aesdeclast>;
+
+def : Pat<(v2i64 (X86aesimc VR128:$src1, VR128:$src2)),
+          (AESIMCrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v2i64 (X86aesimc VR128:$src1, (memop addr:$src2))),
+          (AESIMCrm VR128:$src1, addr:$src2)>;
+def : Pat<(v2i64 (X86aesenc VR128:$src1, VR128:$src2)),
+          (AESENCrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v2i64 (X86aesenc VR128:$src1, (memop addr:$src2))),
+          (AESENCrm VR128:$src1, addr:$src2)>;
+def : Pat<(v2i64 (X86aesenclast VR128:$src1, VR128:$src2)),
+          (AESENCLASTrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v2i64 (X86aesenclast VR128:$src1, (memop addr:$src2))),
+          (AESENCLASTrm VR128:$src1, addr:$src2)>;
+def : Pat<(v2i64 (X86aesdec VR128:$src1, VR128:$src2)),
+          (AESDECrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v2i64 (X86aesdec VR128:$src1, (memop addr:$src2))),
+          (AESDECrm VR128:$src1, addr:$src2)>;
+def : Pat<(v2i64 (X86aesdeclast VR128:$src1, VR128:$src2)),
+          (AESDECLASTrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v2i64 (X86aesdeclast VR128:$src1, (memop addr:$src2))),
+          (AESDECLASTrm VR128:$src1, addr:$src2)>;
+
+def AESKEYGENASSIST128rr : SS42AI<0xDF, MRMSrcReg, (outs),
+  (ins VR128:$src1, VR128:$src2, i8imm:$src3),
+  "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
+def AESKEYGENASSIST128rm : SS42AI<0xDF, MRMSrcMem, (outs),
+  (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
+  "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
+
 // crc intrinsic instruction
 // This set of instructions are only rm, the only difference is the size
 // of r and m.

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s?rev=99514&r1=99513&r2=99514&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-bit_cat.s Thu Mar 25 11:36:14 2010
@@ -7806,3 +7806,39 @@
 
 // CHECK: 	pcmpgtq	%xmm5, %xmm5
         	pcmpgtq	%xmm5,%xmm5
+
+// CHECK: 	aesimc	%xmm0, %xmm1
+                aesimc %xmm0,%xmm1
+
+// CHECK: 	aesimc	(%eax), %xmm1
+                aesimc (%eax),%xmm1
+
+// CHECK: 	aesenc	%xmm1, %xmm2
+                aesenc %xmm1,%xmm2
+
+// CHECK: 	aesenc	4(%ebx), %xmm2
+                aesenc 4(%ebx),%xmm2
+
+// CHECK: 	aesenclast	%xmm3, %xmm4
+                aesenclast %xmm3,%xmm4
+
+// CHECK: 	aesenclast	4(%edx,%edi), %xmm4
+                aesenclast 4(%edx,%edi),%xmm4
+
+// CHECK: 	aesdec	%xmm5, %xmm6
+                aesdec %xmm5,%xmm6
+
+// CHECK: 	aesdec	4(%ecx,%eax,8), %xmm6
+                aesdec 4(%ecx,%eax,8),%xmm6
+
+// CHECK: 	aesdeclast	%xmm7, %xmm0
+                aesdeclast %xmm7,%xmm0
+
+// CHECK: 	aesdeclast	3405691582, %xmm0
+                aesdeclast 0xcafebabe,%xmm0
+
+// CHECK: 	aeskeygenassist	$125, %xmm1, %xmm2
+                aeskeygenassist $125, %xmm1, %xmm2
+
+// CHECK: 	aeskeygenassist	$125, (%edx,%eax,4), %xmm2
+                aeskeygenassist $125, (%edx,%eax,4), %xmm2

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=99514&r1=99513&r2=99514&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Thu Mar 25 11:36:14 2010
@@ -9913,3 +9913,51 @@
 // CHECK: pcmpistrm	$125, (%edx,%eax,4), %xmm2
 // CHECK:  encoding: [0x66,0x0f,0x3a,0x62,0x14,0x82,0x7d]
                 pcmpistrm $125, (%edx,%eax,4), %xmm2
+
+// CHECK: aesimc	%xmm0, %xmm1
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdb,0xc8]
+                aesimc %xmm0,%xmm1
+
+// CHECK: aesimc	(%eax), %xmm1
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdb,0x08]
+                aesimc (%eax),%xmm1
+
+// CHECK: aesenc	%xmm1, %xmm2
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdc,0xd1]
+                aesenc %xmm1,%xmm2
+
+// CHECK: aesenc	4(%ebx), %xmm2
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdc,0x53,0x04]
+                aesenc 4(%ebx),%xmm2
+
+// CHECK: aesenclast	%xmm3, %xmm4
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdd,0xe3]
+                aesenclast %xmm3,%xmm4
+
+// CHECK: aesenclast	4(%edx,%edi), %xmm4
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdd,0x64,0x3a,0x04]
+                aesenclast 4(%edx,%edi),%xmm4
+
+// CHECK: aesdec	%xmm5, %xmm6
+// CHECK:  encoding: [0x66,0x0f,0x38,0xde,0xf5]
+                aesdec %xmm5,%xmm6
+
+// CHECK: aesdec	4(%ecx,%eax,8), %xmm6
+// CHECK:  encoding: [0x66,0x0f,0x38,0xde,0x74,0xc1,0x04]
+                aesdec 4(%ecx,%eax,8),%xmm6
+
+// CHECK: aesdeclast	%xmm7, %xmm0
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdf,0xc7]
+                aesdeclast %xmm7,%xmm0
+
+// CHECK: aesdeclast	3405691582, %xmm0
+// CHECK:  encoding: [0x66,0x0f,0x38,0xdf,0x05,0xbe,0xba,0xfe,0xca]
+                aesdeclast 0xcafebabe,%xmm0
+
+// CHECK: aeskeygenassist	$125, %xmm1, %xmm2
+// CHECK:  encoding: [0x66,0x0f,0x3a,0xdf,0xd1,0x7d]
+                aeskeygenassist $125, %xmm1, %xmm2
+
+// CHECK: aeskeygenassist	$125, (%edx,%eax,4), %xmm2
+// CHECK:  encoding: [0x66,0x0f,0x3a,0xdf,0x14,0x82,0x7d]
+                aeskeygenassist $125, (%edx,%eax,4), %xmm2




From johnny.chen at apple.com  Thu Mar 25 12:01:28 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Thu, 25 Mar 2010 17:01:28 -0000
Subject: [llvm-commits] [llvm] r99518 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrNEON.td
Message-ID: <20100325170128.2B6C02A6C12D@llvm.org>

Author: johnny
Date: Thu Mar 25 12:01:27 2010
New Revision: 99518

URL: http://llvm.org/viewvc/llvm-project?rev=99518&view=rev
Log:
Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,
instead of the current N2V.  Format of NVDupLane instances are set to NEONFrm
currently.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99518&r1=99517&r2=99518&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Mar 25 12:01:27 2010
@@ -1666,6 +1666,19 @@
   : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin,
              opc, dt, asm, pattern>;
 
+// Vector Duplicate Lane (from scalar to all elements)
+class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
+                InstrItinClass itin, string opc, string dt, string asm,
+                list<dag> pattern>
+  : NDataI<oops, iops, NEONFrm, itin, opc, dt, asm, "", pattern> {
+  let Inst{24-23} = 0b11;
+  let Inst{21-20} = 0b11;
+  let Inst{19-16} = op19_16;
+  let Inst{11-7} = 0b11000;
+  let Inst{6} = op6;
+  let Inst{4} = 0;
+}
+
 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
 // for single-precision FP.
 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99518&r1=99517&r2=99518&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Mar 25 12:01:27 2010
@@ -854,7 +854,6 @@
 //===----------------------------------------------------------------------===//
 
 // Basic 2-register operations: single-, double- and quad-register.
-// This is used for NVCVTFrm form.
 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
@@ -3007,30 +3006,29 @@
 
 //   VDUP     : Vector Duplicate Lane (from scalar to all elements)
 
-class VDUPLND<bits<2> op19_18, bits<2> op17_16,
-              string OpcodeStr, string Dt, ValueType Ty>
-  : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
-        (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
-        OpcodeStr, Dt, "$dst, $src[$lane]", "",
-        [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
+class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
+              ValueType Ty>
+  : NVDupLane<op19_16, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane),
+              IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
+              [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
 
-class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, string Dt,
+class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
               ValueType ResTy, ValueType OpTy>
-  : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
-        (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
-        OpcodeStr, Dt, "$dst, $src[$lane]", "",
-        [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
+  : NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
+              IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
+              [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
+                                      imm:$lane)))]>;
 
 // Inst{19-16} is partially specified depending on the element size.
 
-def VDUPLN8d  : VDUPLND<{?,?}, {?,1}, "vdup", "8", v8i8>;
-def VDUPLN16d : VDUPLND<{?,?}, {1,0}, "vdup", "16", v4i16>;
-def VDUPLN32d : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2i32>;
-def VDUPLNfd  : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2f32>;
-def VDUPLN8q  : VDUPLNQ<{?,?}, {?,1}, "vdup", "8", v16i8, v8i8>;
-def VDUPLN16q : VDUPLNQ<{?,?}, {1,0}, "vdup", "16", v8i16, v4i16>;
-def VDUPLN32q : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4i32, v2i32>;
-def VDUPLNfq  : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4f32, v2f32>;
+def VDUPLN8d  : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8>;
+def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16>;
+def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32>;
+def VDUPLNfd  : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32>;
+def VDUPLN8q  : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8>;
+def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16>;
+def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32>;
+def VDUPLNfq  : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32>;
 
 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
           (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,




From stoklund at 2pi.dk  Thu Mar 25 12:25:01 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 25 Mar 2010 17:25:01 -0000
Subject: [llvm-commits] [llvm] r99524 - in /llvm/trunk/lib/Target/X86:
 CMakeLists.txt SSEDomainFix.cpp X86.h X86.td X86InstrFormats.td
 X86InstrInfo.cpp X86InstrInfo.h X86TargetMachine.cpp X86TargetMachine.h
Message-ID: <20100325172501.2A0B02A6C12C@llvm.org>

Author: stoklund
Date: Thu Mar 25 12:25:00 2010
New Revision: 99524

URL: http://llvm.org/viewvc/llvm-project?rev=99524&view=rev
Log:
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.

On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register
in a different domain than where it was defined. Some instructions have
equvivalents for different domains, like por/orps/orpd.

The SSEDomainFix pass tries to minimize the number of domain crossings by
changing between equvivalent opcodes where possible.

This is a work in progress, in particular the pass doesn't do anything yet. SSE
instructions are tagged with their execution domain in TableGen using the last
two bits of TSFlags. Note that not all instructions are tagged correctly. Life
just isn't that simple.

The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline
issue handled by NEONMoveFixPass. This pass may become target independent to
handle both.

Added:
    llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
Modified:
    llvm/trunk/lib/Target/X86/CMakeLists.txt
    llvm/trunk/lib/Target/X86/X86.h
    llvm/trunk/lib/Target/X86/X86.td
    llvm/trunk/lib/Target/X86/X86InstrFormats.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.h
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.h

Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=99524&r1=99523&r2=99524&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/X86/CMakeLists.txt Thu Mar 25 12:25:00 2010
@@ -15,6 +15,7 @@
 tablegen(X86GenSubtarget.inc -gen-subtarget)
 
 set(sources
+  SSEDomainFix.cpp
   X86AsmBackend.cpp
   X86CodeEmitter.cpp
   X86COFFMachineModuleInfo.cpp

Added: llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/SSEDomainFix.cpp?rev=99524&view=auto
==============================================================================
--- llvm/trunk/lib/Target/X86/SSEDomainFix.cpp (added)
+++ llvm/trunk/lib/Target/X86/SSEDomainFix.cpp Thu Mar 25 12:25:00 2010
@@ -0,0 +1,98 @@
+//===- SSEDomainFix.cpp - Use proper int/float domain for SSE ---*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the SSEDomainFix pass.
+//
+// Some SSE instructions like mov, and, or, xor are available in different
+// variants for different operand types. These variant instructions are
+// equivalent, but on Nehalem and newer cpus there is extra latency
+// transferring data between integer and floating point domains.
+//
+// This pass changes the variant instructions to minimize domain crossings.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "sse-domain-fix"
+#include "X86InstrInfo.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/ADT/DepthFirstIterator.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+namespace {
+class SSEDomainFixPass : public MachineFunctionPass {
+  static char ID;
+  const X86InstrInfo *TII;
+
+  MachineFunction *MF;
+  MachineBasicBlock *MBB;
+public:
+  SSEDomainFixPass() : MachineFunctionPass(&ID) {}
+
+  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    AU.setPreservesAll();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  virtual bool runOnMachineFunction(MachineFunction &MF);
+
+  virtual const char *getPassName() const {
+    return "SSE execution domain fixup";
+  }
+
+private:
+  void enterBasicBlock(MachineBasicBlock *MBB);
+};
+}
+
+char SSEDomainFixPass::ID = 0;
+
+void SSEDomainFixPass::enterBasicBlock(MachineBasicBlock *mbb) {
+  MBB = mbb;
+  DEBUG(dbgs() << "Entering MBB " << MBB->getName() << "\n");
+}
+
+bool SSEDomainFixPass::runOnMachineFunction(MachineFunction &mf) {
+  MF = &mf;
+  TII = static_cast<const X86InstrInfo*>(MF->getTarget().getInstrInfo());
+
+  // If no XMM registers are used in the function, we can skip it completely.
+  bool XMMIsUsed = false;
+  for (TargetRegisterClass::const_iterator I = X86::VR128RegClass.begin(),
+         E = X86::VR128RegClass.end(); I != E; ++I)
+    if (MF->getRegInfo().isPhysRegUsed(*I)) {
+      XMMIsUsed = true;
+      break;
+    }
+  if (!XMMIsUsed) return false;
+
+  MachineBasicBlock *Entry = MF->begin();
+  SmallPtrSet<MachineBasicBlock*, 16> Visited;
+  for (df_ext_iterator<MachineBasicBlock*,
+         SmallPtrSet<MachineBasicBlock*, 16> >
+         DFI = df_ext_begin(Entry, Visited), DFE = df_ext_end(Entry, Visited);
+       DFI != DFE; ++DFI) {
+    enterBasicBlock(*DFI);
+    for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
+        ++I) {
+      MachineInstr *MI = I;
+      const unsigned *equiv = 0;
+      X86InstrInfo::SSEDomain domain = TII->GetSSEDomain(MI, equiv);
+      DEBUG(dbgs() << "-isd"[domain] << (equiv ? "* " : "  ") << *MI);
+    }
+  }
+  return false;
+}
+
+FunctionPass *llvm::createSSEDomainFixPass() {
+  return new SSEDomainFixPass();
+}

Modified: llvm/trunk/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=99524&r1=99523&r2=99524&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.h (original)
+++ llvm/trunk/lib/Target/X86/X86.h Thu Mar 25 12:25:00 2010
@@ -41,6 +41,10 @@
 ///
 FunctionPass *createX86FloatingPointStackifierPass();
 
+/// createSSEDomainFixPass - This pass twiddles SSE opcodes to prevent domain
+/// crossings.
+FunctionPass *createSSEDomainFixPass();
+
 /// createX87FPRegKillInserterPass - This function returns a pass which
 /// inserts FP_REG_KILL instructions where needed.
 ///

Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=99524&r1=99523&r2=99524&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Thu Mar 25 12:25:00 2010
@@ -164,6 +164,7 @@
                        "FPFormBits",
                        "hasLockPrefix",
                        "SegOvrBits",
+                       "DomainBits",
                        "Opcode"];
   let TSFlagsShifts = [0,
                        6,
@@ -174,6 +175,7 @@
                        16,
                        19,
                        20,
+                       22,
                        24];
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=99524&r1=99523&r2=99524&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Thu Mar 25 12:25:00 2010
@@ -68,6 +68,16 @@
 def CondMovFP  : FPFormat<6>;
 def SpecialFP  : FPFormat<7>;
 
+// Class specifying the SSE execution domain, used by the SSEDomainFix pass.
+// Instruction execution domain.
+class Domain<bits<2> val> {
+  bits<2> Value = val;
+}
+def GenericDomain   : Domain<0>;
+def SSEPackedInt    : Domain<1>;
+def SSEPackedSingle : Domain<2>;
+def SSEPackedDouble : Domain<3>;
+
 // Prefix byte classes which are used to indicate to the ad-hoc machine code
 // emitter that various prefix bytes are required.
 class OpSize { bit hasOpSizePrefix = 1; }
@@ -93,7 +103,7 @@
 class TF     { bits<4> Prefix = 15; }
 
 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
-              string AsmStr>
+              string AsmStr, Domain d = GenericDomain>
   : Instruction {
   let Namespace = "X86";
 
@@ -119,16 +129,19 @@
   bits<3> FPFormBits = 0;
   bit hasLockPrefix = 0;    // Does this inst have a 0xF0 prefix?
   bits<2> SegOvrBits = 0;   // Segment override prefix.
+  Domain Dom = d;
+  bits<2> DomainBits = Dom.Value;
 }
 
-class I<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
-  : X86Inst<o, f, NoImm, outs, ins, asm> {
+class I<bits<8> o, Format f, dag outs, dag ins, string asm,
+        list<dag> pattern, Domain d = GenericDomain>
+  : X86Inst<o, f, NoImm, outs, ins, asm, d> {
   let Pattern = pattern;
   let CodeSize = 3;
 }
 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm, 
-           list<dag> pattern>
-  : X86Inst<o, f, Imm8 , outs, ins, asm> {
+           list<dag> pattern, Domain d = GenericDomain>
+  : X86Inst<o, f, Imm8, outs, ins, asm, d> {
   let Pattern = pattern;
   let CodeSize = 3;
 }
@@ -196,14 +209,16 @@
 
 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
       : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
-class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 
+class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
             list<dag> pattern>
       : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
-      : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>;
+      : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
+        Requires<[HasSSE1]>;
 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
             list<dag> pattern>
-      : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>;
+      : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
+        Requires<[HasSSE1]>;
 
 // SSE2 Instruction Templates:
 // 
@@ -222,10 +237,12 @@
              list<dag> pattern>
       : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
-      : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
+      : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
+        Requires<[HasSSE2]>;
 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
             list<dag> pattern>
-      : Ii8<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
+      : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
+        Requires<[HasSSE2]>;
 
 // SSE3 Instruction Templates:
 // 
@@ -235,12 +252,15 @@
 
 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, 
            list<dag> pattern>
-      : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE3]>;
+      : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, XS,
+        Requires<[HasSSE3]>;
 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, 
            list<dag> pattern>
-      : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE3]>;
+      : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, XD,
+        Requires<[HasSSE3]>;
 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
-      : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
+      : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
+        Requires<[HasSSE3]>;
 
 
 // SSSE3 Instruction Templates:
@@ -254,10 +274,12 @@
 
 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
             list<dag> pattern>
-      : Ii8<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSSE3]>;
+      : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
+        Requires<[HasSSSE3]>;
 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
             list<dag> pattern>
-      : Ii8<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSSE3]>;
+      : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
+        Requires<[HasSSSE3]>;
 
 // SSE4.1 Instruction Templates:
 // 
@@ -266,17 +288,20 @@
 //
 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
             list<dag> pattern>
-      : I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSE41]>;
+      : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
+        Requires<[HasSSE41]>;
 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
             list<dag> pattern>
-      : Ii8<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE41]>;
+      : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
+        Requires<[HasSSE41]>;
 
 // SSE4.2 Instruction Templates:
 // 
 //   SS428I - SSE 4.2 instructions with T8 prefix.
 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
              list<dag> pattern>
-      : I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSE42]>;
+      : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
+        Requires<[HasSSE42]>;
 
 //   SS42FI - SSE 4.2 instructions with TF prefix.
 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
@@ -286,7 +311,8 @@
 //   SS42AI = SSE 4.2 instructions with TA prefix
 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
              list<dag> pattern>
-      : Ii8<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE42]>;
+      : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
+        Requires<[HasSSE42]>;
 
 // X86-64 Instruction templates...
 //

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=99524&r1=99523&r2=99524&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Mar 25 12:25:00 2010
@@ -3658,3 +3658,46 @@
   X86FI->setGlobalBaseReg(GlobalBaseReg);
   return GlobalBaseReg;
 }
+
+X86InstrInfo::SSEDomain X86InstrInfo::GetSSEDomain(const MachineInstr *MI,
+                                                 const unsigned *&equiv) const {
+  // These are the replaceable SSE instructions. Some of these have Int variants
+  // that we don't include here. We don't want to replace instructions selected
+  // by intrinsics.
+  static const unsigned ReplaceableInstrs[][3] = {
+    //PackedInt          PackedSingle     PackedDouble
+    { X86::MOVDQAmr,     X86::MOVAPSmr,   X86::MOVAPDmr   },
+    { X86::MOVDQArm,     X86::MOVAPSrm,   X86::MOVAPDrm   },
+    { X86::MOVDQArr,     X86::MOVAPSrr,   X86::MOVAPDrr   },
+    { X86::MOVDQUmr,     X86::MOVUPSmr,   X86::MOVUPDmr   },
+    { X86::MOVDQUrm,     X86::MOVUPSrm,   X86::MOVUPDrm   },
+    { X86::MOVNTDQmr,    X86::MOVNTPSmr,  X86::MOVNTPDmr  },
+    { X86::PANDNrm,      X86::ANDNPSrm,   X86::ANDNPDrm   },
+    { X86::PANDNrr,      X86::ANDNPSrr,   X86::ANDNPDrr   },
+    { X86::PANDrm,       X86::ANDPSrm,    X86::ANDPDrm    },
+    { X86::PANDrr,       X86::ANDPSrr,    X86::ANDPDrr    },
+    { X86::PORrm,        X86::ORPSrm,     X86::ORPDrm     },
+    { X86::PORrr,        X86::ORPSrr,     X86::ORPDrr     },
+    { X86::PUNPCKHQDQrm, X86::UNPCKHPSrm, X86::UNPCKHPDrm },
+    { X86::PUNPCKHQDQrr, X86::UNPCKHPSrr, X86::UNPCKHPDrr },
+    { X86::PUNPCKLQDQrm, X86::UNPCKLPSrm, X86::UNPCKLPDrm },
+    { X86::PUNPCKLQDQrr, X86::UNPCKLPSrr, X86::UNPCKLPDrr },
+    { X86::PXORrm,       X86::XORPSrm,    X86::XORPDrm    },
+    { X86::PXORrr,       X86::XORPSrr,    X86::XORPDrr    },
+  };
+
+  const SSEDomain domain =
+    SSEDomain((MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3);
+  if (domain == NotSSEDomain)
+    return domain;
+
+  // Linear search FTW!
+  const unsigned opc = MI->getOpcode();
+  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
+    if (ReplaceableInstrs[i][domain-1] == opc) {
+      equiv = ReplaceableInstrs[i];
+      return domain;
+    }
+  equiv = 0;
+  return domain;
+}

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=99524&r1=99523&r2=99524&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Thu Mar 25 12:25:00 2010
@@ -398,7 +398,10 @@
     FS          = 1 << SegOvrShift,
     GS          = 2 << SegOvrShift,
 
-    // Bits 22 -> 23 are unused
+    // Execution domain for SSE instructions in bits 22, 23.
+    // 0 in bits 22-23 means normal, non-SSE instruction. See SSEDomain below.
+    SSEDomainShift = 22,
+
     OpcodeShift   = 24,
     OpcodeMask    = 0xFF << OpcodeShift
   };
@@ -486,7 +489,7 @@
   /// MemOp2RegOpTable - Load / store unfolding opcode map.
   ///
   DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
-  
+
 public:
   explicit X86InstrInfo(X86TargetMachine &tm);
 
@@ -716,6 +719,15 @@
   ///
   unsigned getGlobalBaseReg(MachineFunction *MF) const;
 
+  /// Some SSE instructions come in variants for three domains.
+  enum SSEDomain { NotSSEDomain, PackedInt, PackedSingle, PackedDouble };
+
+  /// GetSSEDomain - Return the SSE execution domain of MI, or NotSSEDomain for
+  /// unknown instructions. If the instruction has equivalents for other
+  /// domains, equiv points to a list of opcodes for [PackedInt, PackedSingle,
+  /// PackedDouble].
+  SSEDomain GetSSEDomain(const MachineInstr *MI, const unsigned *&equiv) const;
+
 private:
   MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
                                               MachineFunction::iterator &MFI,

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=99524&r1=99523&r2=99524&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Mar 25 12:25:00 2010
@@ -17,11 +17,17 @@
 #include "llvm/PassManager.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/Passes.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetRegistry.h"
 using namespace llvm;
 
+static cl::opt<bool>
+SSEDomainFix("sse-domain-fix",
+               cl::desc("Enable fixing of SSE execution domain"),
+               cl::init(false), cl::Hidden);
+
 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
   Triple TheTriple(TT);
   switch (TheTriple.getOS()) {
@@ -169,6 +175,15 @@
   return true;  // -print-machineinstr should print after this.
 }
 
+bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM,
+                                      CodeGenOpt::Level OptLevel) {
+  if (SSEDomainFix && OptLevel != CodeGenOpt::None && Subtarget.hasSSE2()) {
+    PM.add(createSSEDomainFixPass());
+    return true;
+  }
+  return false;
+}
+
 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
                                       CodeGenOpt::Level OptLevel,
                                       JITCodeEmitter &JCE) {

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=99524&r1=99523&r2=99524&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Thu Mar 25 12:25:00 2010
@@ -66,6 +66,7 @@
   virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
   virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
   virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
                               JITCodeEmitter &JCE);
 };




From daniel at zuster.org  Thu Mar 25 13:16:38 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 18:16:38 -0000
Subject: [llvm-commits] [llvm] r99528 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp
Message-ID: <20100325181638.DB4892A6C12C@llvm.org>

Author: ddunbar
Date: Thu Mar 25 13:16:38 2010
New Revision: 99528

URL: http://llvm.org/viewvc/llvm-project?rev=99528&view=rev
Log:
MC: Sink Section address assignment into LayoutSection.

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99528&r1=99527&r2=99528&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Thu Mar 25 13:16:38 2010
@@ -651,10 +651,11 @@
   bool FragmentNeedsRelaxation(const MCInstFragment *IF,
                                const MCAsmLayout &Layout) const;
 
-  /// LayoutSection - Assign offsets and sizes to the fragments in the section
-  /// \arg SD, and update the section size. The section file offset should
-  /// already have been computed.
-  void LayoutSection(MCSectionData &SD, MCAsmLayout &Layout);
+  /// LayoutSection - Assign the section the given \arg StartAddress, and then
+  /// assign offsets and sizes to the fragments in the section \arg SD, and
+  /// update the section size.
+  void LayoutSection(MCSectionData &SD, MCAsmLayout &Layout,
+                     uint64_t StartAddress);
 
   /// LayoutOnce - Perform one layout iteration and return true if any offsets
   /// were adjusted.

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99528&r1=99527&r2=99528&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Thu Mar 25 13:16:38 2010
@@ -365,9 +365,11 @@
 }
 
 void MCAssembler::LayoutSection(MCSectionData &SD,
-                                MCAsmLayout &Layout) {
-  uint64_t Address, StartAddress = Address = Layout.getSectionAddress(&SD);
+                                MCAsmLayout &Layout,
+                                uint64_t StartAddress) {
+  Layout.setSectionAddress(&SD, StartAddress);
 
+  uint64_t Address = StartAddress;
   for (MCSectionData::iterator it = SD.begin(), ie = SD.end(); it != ie; ++it) {
     MCFragment &F = *it;
 
@@ -690,8 +692,7 @@
     }
 
     // Layout the section fragments and its size.
-    Layout.setSectionAddress(&SD, Address);
-    LayoutSection(SD, Layout);
+    LayoutSection(SD, Layout, Address);
     Address += Layout.getSectionFileSize(&SD);
 
     Prev = &SD;
@@ -709,8 +710,7 @@
     if (uint64_t Pad = OffsetToAlignment(Address, it->getAlignment()))
       Address += Pad;
 
-    Layout.setSectionAddress(&SD, Address);
-    LayoutSection(SD, Layout);
+    LayoutSection(SD, Layout, Address);
     Address += Layout.getSectionSize(&SD);
   }
 




From daniel at zuster.org  Thu Mar 25 13:16:42 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 18:16:42 -0000
Subject: [llvm-commits] [llvm] r99529 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp
Message-ID: <20100325181642.36F0A2A6C12D@llvm.org>

Author: ddunbar
Date: Thu Mar 25 13:16:42 2010
New Revision: 99529

URL: http://llvm.org/viewvc/llvm-project?rev=99529&view=rev
Log:
MC: Simplify main section layout process by moving alignment into LayoutSection.

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99529&r1=99528&r2=99529&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Thu Mar 25 13:16:42 2010
@@ -654,8 +654,11 @@
   /// LayoutSection - Assign the section the given \arg StartAddress, and then
   /// assign offsets and sizes to the fragments in the section \arg SD, and
   /// update the section size.
-  void LayoutSection(MCSectionData &SD, MCAsmLayout &Layout,
-                     uint64_t StartAddress);
+  ///
+  /// \return The address at the end of the section, for use in laying out the
+  /// succeeding section.
+  uint64_t LayoutSection(MCSectionData &SD, MCAsmLayout &Layout,
+                         uint64_t StartAddress);
 
   /// LayoutOnce - Perform one layout iteration and return true if any offsets
   /// were adjusted.

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99529&r1=99528&r2=99529&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Thu Mar 25 13:16:42 2010
@@ -364,9 +364,29 @@
   return IsResolved;
 }
 
-void MCAssembler::LayoutSection(MCSectionData &SD,
-                                MCAsmLayout &Layout,
-                                uint64_t StartAddress) {
+uint64_t MCAssembler::LayoutSection(MCSectionData &SD,
+                                    MCAsmLayout &Layout,
+                                    uint64_t StartAddress) {
+  bool IsVirtual = getBackend().isVirtualSection(SD.getSection());
+
+  // Align this section if necessary by adding padding bytes to the previous
+  // section. It is safe to adjust this out-of-band, because no symbol or
+  // fragment is allowed to point past the end of the section at any time.
+  if (uint64_t Pad = OffsetToAlignment(StartAddress, SD.getAlignment())) {
+    // Unless this section is virtual (where we are allowed to adjust the offset
+    // freely), the padding goes in the previous section.
+    if (!IsVirtual) {
+      // Find the previous non-virtual section.
+      iterator it = &SD;
+      assert(it != begin() && "Invalid initial section address!");
+      for (--it; getBackend().isVirtualSection(it->getSection()); --it) ;
+      Layout.setSectionFileSize(&*it, Layout.getSectionFileSize(&*it) + Pad);
+    }
+
+    StartAddress += Pad;
+  }
+
+  // Set the aligned section address.
   Layout.setSectionAddress(&SD, StartAddress);
 
   uint64_t Address = StartAddress;
@@ -440,10 +460,12 @@
 
   // Set the section sizes.
   Layout.setSectionSize(&SD, Address - StartAddress);
-  if (getBackend().isVirtualSection(SD.getSection()))
+  if (IsVirtual)
     Layout.setSectionFileSize(&SD, 0);
   else
     Layout.setSectionFileSize(&SD, Address - StartAddress);
+
+  return Address;
 }
 
 /// WriteFragmentData - Write the \arg F data to the output file.
@@ -675,43 +697,22 @@
 
   // Layout the concrete sections and fragments.
   uint64_t Address = 0;
-  MCSectionData *Prev = 0;
   for (iterator it = begin(), ie = end(); it != ie; ++it) {
-    MCSectionData &SD = *it;
-
     // Skip virtual sections.
-    if (getBackend().isVirtualSection(SD.getSection()))
+    if (getBackend().isVirtualSection(it->getSection()))
       continue;
 
-    // Align this section if necessary by adding padding bytes to the previous
-    // section.
-    if (uint64_t Pad = OffsetToAlignment(Address, it->getAlignment())) {
-      assert(Prev && "Missing prev section!");
-      Layout.setSectionFileSize(Prev, Layout.getSectionFileSize(Prev) + Pad);
-      Address += Pad;
-    }
-
     // Layout the section fragments and its size.
-    LayoutSection(SD, Layout, Address);
-    Address += Layout.getSectionFileSize(&SD);
-
-    Prev = &SD;
+    Address = LayoutSection(*it, Layout, Address);
   }
 
   // Layout the virtual sections.
   for (iterator it = begin(), ie = end(); it != ie; ++it) {
-    MCSectionData &SD = *it;
-
-    if (!getBackend().isVirtualSection(SD.getSection()))
+    if (!getBackend().isVirtualSection(it->getSection()))
       continue;
 
-    // Align this section if necessary by adding padding bytes to the previous
-    // section.
-    if (uint64_t Pad = OffsetToAlignment(Address, it->getAlignment()))
-      Address += Pad;
-
-    LayoutSection(SD, Layout, Address);
-    Address += Layout.getSectionSize(&SD);
+    // Layout the section fragments and its size.
+    Address = LayoutSection(*it, Layout, Address);
   }
 
   // Scan for fragments that need relaxation.




From stuart at apple.com  Thu Mar 25 13:31:51 2010
From: stuart at apple.com (Stuart Hastings)
Date: Thu, 25 Mar 2010 18:31:51 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r99536 -
	/llvm-gcc-4.2/trunk/gcc/cp/pt.c
Message-ID: <20100325183151.C58B82A6C12C@llvm.org>

Author: stuart
Date: Thu Mar 25 13:31:51 2010
New Revision: 99536

URL: http://llvm.org/viewvc/llvm-project?rev=99536&view=rev
Log:
Use accurate location for instantiated FUNCTION_DECL.  Radar 7514620.

Modified:
    llvm-gcc-4.2/trunk/gcc/cp/pt.c

Modified: llvm-gcc-4.2/trunk/gcc/cp/pt.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/cp/pt.c?rev=99536&r1=99535&r2=99536&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/cp/pt.c (original)
+++ llvm-gcc-4.2/trunk/gcc/cp/pt.c Thu Mar 25 13:31:51 2010
@@ -6696,6 +6696,8 @@
 	   template, and in any case are considered separate under the
 	   discrete model.  */
 	r = copy_decl (t);
+        /* LLVM LOCAL 7514620 */
+        DECL_SOURCE_LOCATION(r) = saved_loc;
 	DECL_USE_TEMPLATE (r) = 0;
 	TREE_TYPE (r) = type;
 	/* Clear out the mangled name and RTL for the instantiation.  */




From evan.cheng at apple.com  Thu Mar 25 13:37:23 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 18:37:23 -0000
Subject: [llvm-commits] [llvm] r99537 -
	/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
Message-ID: <20100325183723.B41F02A6C12F@llvm.org>

Author: evancheng
Date: Thu Mar 25 13:37:23 2010
New Revision: 99537

URL: http://llvm.org/viewvc/llvm-project?rev=99537&view=rev
Log:
Remove an unused option.

Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=99537&r1=99536&r2=99537&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Mar 25 13:37:23 2010
@@ -59,11 +59,6 @@
                cl::desc("Avoid coalescing cross register class copies"),
                cl::init(false), cl::Hidden);
 
-static cl::opt<bool>
-PhysJoinTweak("tweak-phys-join-heuristics",
-               cl::desc("Tweak heuristics for joining phys reg with vr"),
-               cl::init(false), cl::Hidden);
-
 static RegisterPass<SimpleRegisterCoalescing>
 X("simple-register-coalescing", "Simple Register Coalescing");
 
@@ -1445,7 +1440,6 @@
   const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
   const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
   const TargetRegisterClass *NewRC = NULL;
-  MachineBasicBlock *CopyMBB = CopyMI->getParent();
   unsigned RealDstReg = 0;
   unsigned RealSrcReg = 0;
   if (isExtSubReg || isInsSubReg || isSubRegToReg) {
@@ -1656,60 +1650,36 @@
     // these are not spillable! If the destination interval uses are far away,
     // think twice about coalescing them!
     if (!isDead && (SrcIsPhys || DstIsPhys)) {
-      // If the copy is in a loop, take care not to coalesce aggressively if the
-      // src is coming in from outside the loop (or the dst is out of the loop).
-      // If it's not in a loop, then determine whether to join them base purely
-      // by the length of the interval.
-      if (PhysJoinTweak) {
-        if (SrcIsPhys) {
-          if (!isWinToJoinVRWithSrcPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
-            mri_->setRegAllocationHint(DstInt.reg, 0, SrcReg);
-            ++numAborts;
-            DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
-            Again = true;  // May be possible to coalesce later.
-            return false;
-          }
-        } else {
-          if (!isWinToJoinVRWithDstPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
-            mri_->setRegAllocationHint(SrcInt.reg, 0, DstReg);
-            ++numAborts;
-            DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
-            Again = true;  // May be possible to coalesce later.
-            return false;
-          }
-        }
-      } else {
-        // If the virtual register live interval is long but it has low use
-        // density, do not join them, instead mark the physical register as its
-        // allocation preference.
-        LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
-        LiveInterval &JoinPInt = SrcIsPhys ? SrcInt : DstInt;
-        unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
-        unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
-
-        // Don't join with physregs that have a ridiculous number of live
-        // ranges. The data structure performance is really bad when that
-        // happens.
-        if (JoinPInt.ranges.size() > 1000) {
-          mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
-          ++numAborts;
-          DEBUG(dbgs() << "\tPhysical register too complicated, abort!\n");
-          return false;
-        }
+      // If the virtual register live interval is long but it has low use
+      // density, do not join them, instead mark the physical register as its
+      // allocation preference.
+      LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
+      LiveInterval &JoinPInt = SrcIsPhys ? SrcInt : DstInt;
+      unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
+      unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
+
+      // Don't join with physregs that have a ridiculous number of live
+      // ranges. The data structure performance is really bad when that
+      // happens.
+      if (JoinPInt.ranges.size() > 1000) {
+        mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
+        ++numAborts;
+        DEBUG(dbgs() << "\tPhysical register too complicated, abort!\n");
+        return false;
+      }
 
-        const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
-        unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
-        unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
-        float Ratio = 1.0 / Threshold;
-        if (Length > Threshold &&
-            (((float)std::distance(mri_->use_nodbg_begin(JoinVReg),
-                                   mri_->use_nodbg_end()) / Length) < Ratio)) {
-          mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
-          ++numAborts;
-          DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
-          Again = true;  // May be possible to coalesce later.
-          return false;
-        }
+      const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
+      unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
+      unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
+      float Ratio = 1.0 / Threshold;
+      if (Length > Threshold &&
+          (((float)std::distance(mri_->use_nodbg_begin(JoinVReg),
+                                 mri_->use_nodbg_end()) / Length) < Ratio)) {
+        mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
+        ++numAborts;
+        DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
+        Again = true;  // May be possible to coalesce later.
+        return false;
       }
     }
   }




From sabre at nondot.org  Thu Mar 25 13:49:10 2010
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 25 Mar 2010 18:49:10 -0000
Subject: [llvm-commits] [llvm] r99538 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
Message-ID: <20100325184910.488E12A6C12C@llvm.org>

Author: lattner
Date: Thu Mar 25 13:49:10 2010
New Revision: 99538

URL: http://llvm.org/viewvc/llvm-project?rev=99538&view=rev
Log:
fix a valgrind error on copy-constructor-synthesis.cpp, which is caused when
the custom insertion hook deletes the instruction, then we try to set dead
flags on it.  Neither the code that I added nor the code that was there 
before was safe.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=99538&r1=99537&r2=99538&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Thu Mar 25 13:49:10 2010
@@ -617,9 +617,10 @@
     // specific inserter which may returns a new basic block.
     MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
     InsertPos = MBB->end();
-  } else {
-    MBB->insert(InsertPos, MI);
+    return;
   }
+  
+  MBB->insert(InsertPos, MI);
 
   // Additional results must be an physical register def.
   if (HasPhysRegOuts) {




From stoklund at 2pi.dk  Thu Mar 25 13:52:01 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 25 Mar 2010 18:52:01 -0000
Subject: [llvm-commits] [llvm] r99539 - in /llvm/trunk:
 lib/Target/X86/X86.td lib/Target/X86/X86InstrFormats.td
 lib/Target/X86/X86InstrInfo.td utils/TableGen/InstrInfoEmitter.cpp
 utils/TableGen/Record.cpp utils/TableGen/Record.h
Message-ID: <20100325185201.5F77F2A6C12C@llvm.org>

Author: stoklund
Date: Thu Mar 25 13:52:01 2010
New Revision: 99539

URL: http://llvm.org/viewvc/llvm-project?rev=99539&view=rev
Log:
Teach TableGen to understand X.Y notation in the TSFlagsFields strings.

Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.

Modified:
    llvm/trunk/lib/Target/X86/X86.td
    llvm/trunk/lib/Target/X86/X86InstrFormats.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
    llvm/trunk/utils/TableGen/Record.cpp
    llvm/trunk/utils/TableGen/Record.h

Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=99539&r1=99538&r2=99539&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Thu Mar 25 13:52:01 2010
@@ -160,11 +160,11 @@
                        "hasAdSizePrefix",
                        "Prefix",
                        "hasREX_WPrefix",
-                       "ImmTypeBits",
-                       "FPFormBits",
+                       "ImmT.Value",
+                       "FPForm.Value",
                        "hasLockPrefix",
                        "SegOvrBits",
-                       "DomainBits",
+                       "ExeDomain.Value",
                        "Opcode"];
   let TSFlagsShifts = [0,
                        6,

Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=99539&r1=99538&r2=99539&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Thu Mar 25 13:52:01 2010
@@ -111,7 +111,6 @@
   Format Form = f;
   bits<6> FormBits = Form.Value;
   ImmType ImmT = i;
-  bits<3> ImmTypeBits = ImmT.Value;
 
   dag OutOperandList = outs;
   dag InOperandList = ins;
@@ -125,12 +124,10 @@
 
   bits<4> Prefix = 0;       // Which prefix byte does this inst have?
   bit hasREX_WPrefix  = 0;  // Does this inst requires the REX.W prefix?
-  FPFormat FPForm;          // What flavor of FP instruction is this?
-  bits<3> FPFormBits = 0;
+  FPFormat FPForm = NotFP;  // What flavor of FP instruction is this?
   bit hasLockPrefix = 0;    // Does this inst have a 0xF0 prefix?
   bits<2> SegOvrBits = 0;   // Segment override prefix.
-  Domain Dom = d;
-  bits<2> DomainBits = Dom.Value;
+  Domain ExeDomain = d;
 }
 
 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
@@ -179,7 +176,7 @@
 // FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
   : X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
-  let FPForm = fp; let FPFormBits = FPForm.Value;
+  let FPForm = fp;
   let Pattern = pattern;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=99539&r1=99538&r2=99539&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Mar 25 13:52:01 2010
@@ -587,7 +587,7 @@
 
 // Return instructions.
 let isTerminator = 1, isReturn = 1, isBarrier = 1,
-    hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
+    hasCtrlDep = 1, FPForm = SpecialFP in {
   def RET    : I   <0xC3, RawFrm, (outs), (ins variable_ops),
                     "ret",
                     [(X86retflag 0)]>;

Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=99539&r1=99538&r2=99539&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Thu Mar 25 13:52:01 2010
@@ -337,7 +337,7 @@
                                         IntInit *ShiftInt, raw_ostream &OS) {
   if (Val == 0 || ShiftInt == 0)
     throw std::string("Illegal value or shift amount in TargetInfo*!");
-  RecordVal *RV = R->getValue(Val->getValue());
+  RecordVal *RV = R->getDottedValue(Val->getValue());
   int Shift = ShiftInt->getValue();
 
   if (RV == 0 || RV->getValue() == 0) {

Modified: llvm/trunk/utils/TableGen/Record.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=99539&r1=99538&r2=99539&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/Record.cpp (original)
+++ llvm/trunk/utils/TableGen/Record.cpp Thu Mar 25 13:52:01 2010
@@ -1307,6 +1307,16 @@
   }
 }
 
+RecordVal *Record::getDottedValue(StringRef Name) {
+  size_t pos = Name.find('.');
+  if (pos == StringRef::npos)
+    return getValue(Name);
+  RecordVal *RV = getValue(Name.substr(0, pos));
+  if (!RV) return 0;
+  DefInit *DI = dynamic_cast<DefInit*>(RV->getValue());
+  if (!DI) return 0;
+  return DI->getDef()->getDottedValue(Name.substr(pos+1));
+}
 
 void Record::dump() const { errs() << *this; }
 

Modified: llvm/trunk/utils/TableGen/Record.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.h?rev=99539&r1=99538&r2=99539&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/Record.h (original)
+++ llvm/trunk/utils/TableGen/Record.h Thu Mar 25 13:52:01 2010
@@ -1262,6 +1262,9 @@
     return 0;
   }
 
+  // Like getValue, but allow dotting into members: X.Y
+  RecordVal *getDottedValue(StringRef Name);
+
   void addTemplateArg(StringRef Name) {
     assert(!isTemplateArg(Name) && "Template arg already defined!");
     TemplateArgs.push_back(Name);




From stoklund at 2pi.dk  Thu Mar 25 13:52:04 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 25 Mar 2010 18:52:04 -0000
Subject: [llvm-commits] [llvm] r99540 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100325185204.947012A6C12D@llvm.org>

Author: stoklund
Date: Thu Mar 25 13:52:04 2010
New Revision: 99540

URL: http://llvm.org/viewvc/llvm-project?rev=99540&view=rev
Log:
Tag SSE2 integer instructions as SSEPackedInt.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=99540&r1=99539&r2=99540&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Mar 25 13:52:04 2010
@@ -1941,6 +1941,7 @@
 
 //===---------------------------------------------------------------------===//
 // SSE integer instructions
+let ExeDomain = SSEPackedInt in {
 
 // Move Instructions
 let neverHasSideEffects = 1 in
@@ -2049,6 +2050,7 @@
 }
 
 } // Constraints = "$src1 = $dst"
+} // ExeDomain = SSEPackedInt
 
 // 128-bit Integer Arithmetic
 
@@ -2111,7 +2113,8 @@
                                int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
 
 // 128-bit logical shifts.
-let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
+let Constraints = "$src1 = $dst", neverHasSideEffects = 1,
+    ExeDomain = SSEPackedInt in {
   def PSLLDQri : PDIi8<0x73, MRM7r,
                        (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
                        "pslldq\t{$src2, $dst|$dst, $src2}", []>;
@@ -2145,7 +2148,7 @@
 defm POR  : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
 
-let Constraints = "$src1 = $dst" in {
+let Constraints = "$src1 = $dst", ExeDomain = SSEPackedInt in {
   def PANDNrr : PDI<0xDF, MRMSrcReg,
                     (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
                     "pandn\t{$src2, $dst|$dst, $src2}",
@@ -2199,6 +2202,8 @@
 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
 
+let ExeDomain = SSEPackedInt in {
+
 // Shuffle and unpack instructions
 let AddedComplexity = 5 in {
 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
@@ -2375,10 +2380,13 @@
                      "maskmovdqu\t{$mask, $src|$src, $mask}",
                      [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
 
+} // ExeDomain = SSEPackedInt
+
 // Non-temporal stores
 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
                         "movntpd\t{$src, $dst|$dst, $src}",
                         [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
+let ExeDomain = SSEPackedInt in
 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
                         "movntdq\t{$src, $dst|$dst, $src}",
                         [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
@@ -2392,6 +2400,7 @@
                     "movntpd\t{$src, $dst|$dst, $src}",
                     [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
 
+let ExeDomain = SSEPackedInt in
 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
                     "movntdq\t{$src, $dst|$dst, $src}",
                     [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;




From daniel at zuster.org  Thu Mar 25 14:35:53 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 19:35:53 -0000
Subject: [llvm-commits] [llvm] r99542 -
	/llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
Message-ID: <20100325193553.2EB542A6C12C@llvm.org>

Author: ddunbar
Date: Thu Mar 25 14:35:53 2010
New Revision: 99542

URL: http://llvm.org/viewvc/llvm-project?rev=99542&view=rev
Log:
Fix -Asserts warning, again.

Modified:
    llvm/trunk/lib/Target/X86/SSEDomainFix.cpp

Modified: llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/SSEDomainFix.cpp?rev=99542&r1=99541&r2=99542&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/SSEDomainFix.cpp (original)
+++ llvm/trunk/lib/Target/X86/SSEDomainFix.cpp Thu Mar 25 14:35:53 2010
@@ -87,6 +87,7 @@
       MachineInstr *MI = I;
       const unsigned *equiv = 0;
       X86InstrInfo::SSEDomain domain = TII->GetSSEDomain(MI, equiv);
+      (void) domain;
       DEBUG(dbgs() << "-isd"[domain] << (equiv ? "* " : "  ") << *MI);
     }
   }




From daniel at zuster.org  Thu Mar 25 14:35:56 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 19:35:56 -0000
Subject: [llvm-commits] [llvm] r99543 - in /llvm/trunk:
 include/llvm/MC/MCAsmLayout.h include/llvm/MC/MCAssembler.h
 lib/MC/MCAssembler.cpp
Message-ID: <20100325193556.B8DE42A6C12D@llvm.org>

Author: ddunbar
Date: Thu Mar 25 14:35:56 2010
New Revision: 99543

URL: http://llvm.org/viewvc/llvm-project?rev=99543&view=rev
Log:
MC: Stop restarting layout on every relaxation.
 - Still O(N^2), just a faster form, and now its the MCAsmLayout's fault.

On the .s I am tuning against (combine.s from 403.gcc):
--
ddunbar at lordcrumb:MC$ diff stats-before.txt stats-after.txt
5,10c5,10
<    1728 assembler - Number of assembler layout and relaxation steps
<    7707 assembler - Number of emitted assembler fragments
<  120588 assembler - Number of emitted object file bytes
< 2233448 assembler - Number of evaluated fixups
<    1727 assembler - Number of relaxed instructions
< 6723845 mcexpr    - Number of MCExpr evaluations
---
>      3 assembler - Number of assembler layout and relaxation steps
>   7707 assembler - Number of emitted assembler fragments
> 120588 assembler - Number of emitted object file bytes
>  14796 assembler - Number of evaluated fixups
>   1727 assembler - Number of relaxed instructions
>  67889 mcexpr    - Number of MCExpr evaluations
--
Feel free to LOL at the -before numbers, if you like.

I am a little surprised we make more than 2 relaxation passes. It's pretty
trivial for us to do relaxation out-of-order if that would give a speedup.

Modified:
    llvm/trunk/include/llvm/MC/MCAsmLayout.h
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/include/llvm/MC/MCAsmLayout.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmLayout.h?rev=99543&r1=99542&r2=99543&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmLayout.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmLayout.h Thu Mar 25 14:35:56 2010
@@ -33,6 +33,11 @@
   /// Get the assembler object this is a layout for.
   MCAssembler &getAssembler() const { return Assembler; }
 
+  /// \brief Update the layout because a fragment has been resized. The
+  /// fragments size should have already been updated, the \arg SlideAmount is
+  /// the delta from the old size.
+  void UpdateForSlide(MCFragment *F, int SlideAmount);
+
   /// @name Fragment Layout Data
   /// @{
 

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99543&r1=99542&r2=99543&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Thu Mar 25 14:35:56 2010
@@ -580,6 +580,8 @@
 };
 
 class MCAssembler {
+  friend class MCAsmLayout;
+
 public:
   typedef iplist<MCSectionData> SectionDataListType;
   typedef iplist<MCSymbolData> SymbolDataListType;

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99543&r1=99542&r2=99543&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Thu Mar 25 14:35:56 2010
@@ -45,6 +45,39 @@
 
 /* *** */
 
+void MCAsmLayout::UpdateForSlide(MCFragment *F, int SlideAmount) {
+  // We shouldn't have to do anything special to support negative slides, and it
+  // is a perfectly valid thing to do as long as other parts of the system are
+  // can guarantee convergence.
+  assert(SlideAmount >= 0 && "Negative slides not yet supported");
+
+  // Update the layout by simply recomputing the layout for the entire
+  // file. This is trivially correct, but very slow.
+  //
+  // FIXME-PERF: This is O(N^2), but will be eliminated once we get smarter.
+
+  // Layout the concrete sections and fragments.
+  MCAssembler &Asm = getAssembler();
+  uint64_t Address = 0;
+  for (MCAssembler::iterator it = Asm.begin(), ie = Asm.end(); it != ie; ++it) {
+    // Skip virtual sections.
+    if (Asm.getBackend().isVirtualSection(it->getSection()))
+      continue;
+
+    // Layout the section fragments and its size.
+    Address = Asm.LayoutSection(*it, *this, Address);
+  }
+
+  // Layout the virtual sections.
+  for (MCAssembler::iterator it = Asm.begin(), ie = Asm.end(); it != ie; ++it) {
+    if (!Asm.getBackend().isVirtualSection(it->getSection()))
+      continue;
+
+    // Layout the section fragments and its size.
+    Address = Asm.LayoutSection(*it, *this, Address);
+  }
+}
+
 uint64_t MCAsmLayout::getFragmentAddress(const MCFragment *F) const {
   assert(F->getParent() && "Missing section()!");
   return getSectionAddress(F->getParent()) + getFragmentOffset(F);
@@ -716,6 +749,7 @@
   }
 
   // Scan for fragments that need relaxation.
+  bool WasRelaxed = false;
   for (iterator it = begin(), ie = end(); it != ie; ++it) {
     MCSectionData &SD = *it;
 
@@ -747,6 +781,7 @@
       VecOS.flush();
 
       // Update the instruction fragment.
+      int SlideAmount = Code.size() - IF->getInstSize();
       IF->setInst(Relaxed);
       IF->getCode() = Code;
       IF->getFixups().clear();
@@ -756,15 +791,13 @@
                                              F.getKind()));
       }
 
-      // Restart layout.
-      //
-      // FIXME-PERF: This is O(N^2), but will be eliminated once we have a
-      // smart MCAsmLayout object.
-      return true;
+      // Update the layout, and remember that we relaxed.
+      Layout.UpdateForSlide(IF, SlideAmount);
+      WasRelaxed = true;
     }
   }
 
-  return false;
+  return WasRelaxed;
 }
 
 void MCAssembler::FinishLayout(MCAsmLayout &Layout) {




From evan.cheng at apple.com  Thu Mar 25 14:46:11 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 19:46:11 -0000
Subject: [llvm-commits] [llvm] r99544 -
	/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
Message-ID: <20100325194611.D9DAE2A6C12C@llvm.org>

Author: evancheng
Date: Thu Mar 25 14:46:11 2010
New Revision: 99544

URL: http://llvm.org/viewvc/llvm-project?rev=99544&view=rev
Log:
Code clean up.

Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=99544&r1=99543&r2=99544&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Mar 25 14:46:11 2010
@@ -1640,8 +1640,8 @@
   else if (RealSrcReg)
     SavedLI.reset(li_->dupInterval(&DstInt));
 
-  // Check if it is necessary to propagate "isDead" property.
   if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
+    // Check if it is necessary to propagate "isDead" property.
     MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
     bool isDead = mopd->isDead();
 
@@ -1690,16 +1690,15 @@
   // been modified, so we can use this information below to update aliases.
   bool Swapped = false;
   // If SrcInt is implicitly defined, it's safe to coalesce.
-  bool isEmpty = SrcInt.empty();
-  if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
-    // Only coalesce an empty interval (defined by implicit_def) with
-    // another interval which has a valno defined by the CopyMI and the CopyMI
-    // is a kill of the implicit def.
-    DEBUG(dbgs() << "Not profitable!\n");
-    return false;
-  }
-
-  if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
+  if (SrcInt.empty()) {
+    if (!CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
+      // Only coalesce an empty interval (defined by implicit_def) with
+      // another interval which has a valno defined by the CopyMI and the CopyMI
+      // is a kill of the implicit def.
+      DEBUG(dbgs() << "Not profitable!\n");
+      return false;
+    }
+  } else if (!JoinIntervals(DstInt, SrcInt, Swapped)) {
     // Coalescing failed.
 
     // If definition of source is defined by trivial computation, try




From evan.cheng at apple.com  Thu Mar 25 15:01:07 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 20:01:07 -0000
Subject: [llvm-commits] [llvm] r99546 -
	/llvm/trunk/test/CodeGen/X86/postalloc-coalescing.ll
Message-ID: <20100325200107.622212A6C12C@llvm.org>

Author: evancheng
Date: Thu Mar 25 15:01:07 2010
New Revision: 99546

URL: http://llvm.org/viewvc/llvm-project?rev=99546&view=rev
Log:
Add nounwind.

Modified:
    llvm/trunk/test/CodeGen/X86/postalloc-coalescing.ll

Modified: llvm/trunk/test/CodeGen/X86/postalloc-coalescing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/postalloc-coalescing.ll?rev=99546&r1=99545&r2=99546&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/postalloc-coalescing.ll (original)
+++ llvm/trunk/test/CodeGen/X86/postalloc-coalescing.ll Thu Mar 25 15:01:07 2010
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 | grep mov | count 3
 
-define fastcc i32 @_Z18yy_get_next_bufferv() {
+define fastcc i32 @_Z18yy_get_next_bufferv() nounwind {
 entry:
 	br label %bb131
 




From wendling at apple.com  Thu Mar 25 15:11:10 2010
From: wendling at apple.com (Bill Wendling)
Date: Thu, 25 Mar 2010 13:11:10 -0700
Subject: [llvm-commits] [llvm] r99542 -
	/llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
In-Reply-To: <20100325193553.2EB542A6C12C@llvm.org>
References: <20100325193553.2EB542A6C12C@llvm.org>
Message-ID: <FDC10415-9ECA-4A57-8A9E-507887BEDCF6@apple.com>

On Mar 25, 2010, at 12:35 PM, Daniel Dunbar wrote:

> Author: ddunbar
> Date: Thu Mar 25 14:35:53 2010
> New Revision: 99542
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99542&view=rev
> Log:
> Fix -Asserts warning, again.
> 
> Modified:
>    llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
> 
> Modified: llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/SSEDomainFix.cpp?rev=99542&r1=99541&r2=99542&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/SSEDomainFix.cpp (original)
> +++ llvm/trunk/lib/Target/X86/SSEDomainFix.cpp Thu Mar 25 14:35:53 2010
> @@ -87,6 +87,7 @@
>       MachineInstr *MI = I;
>       const unsigned *equiv = 0;
>       X86InstrInfo::SSEDomain domain = TII->GetSSEDomain(MI, equiv);
> +      (void) domain;
>       DEBUG(dbgs() << "-isd"[domain] << (equiv ? "* " : "  ") << *MI);

Why not put the "domain" definition inside of the DEBUG macro? Comme ?a:

  DEBUG({
    X86InstrInfo::SSEDomain domain = TII->GetSSEDomain(MI, equiv);
    dbgs() << "-isd"[domain] << (equiv ? "* " : "  ") << *MI;
  });

-bw




From stoklund at 2pi.dk  Thu Mar 25 15:17:06 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 25 Mar 2010 13:17:06 -0700
Subject: [llvm-commits] [llvm] r99542 -
	/llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
In-Reply-To: <FDC10415-9ECA-4A57-8A9E-507887BEDCF6@apple.com>
References: <20100325193553.2EB542A6C12C@llvm.org>
	<FDC10415-9ECA-4A57-8A9E-507887BEDCF6@apple.com>
Message-ID: <77D7A197-78AE-4601-9250-ADB6EAC1EE76@2pi.dk>


On Mar 25, 2010, at 1:11 PM, Bill Wendling wrote:

> On Mar 25, 2010, at 12:35 PM, Daniel Dunbar wrote:
> 
>> Author: ddunbar
>> Date: Thu Mar 25 14:35:53 2010
>> New Revision: 99542
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99542&view=rev
>> Log:
>> Fix -Asserts warning, again.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
>> 
>> Modified: llvm/trunk/lib/Target/X86/SSEDomainFix.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/SSEDomainFix.cpp?rev=99542&r1=99541&r2=99542&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/SSEDomainFix.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/SSEDomainFix.cpp Thu Mar 25 14:35:53 2010
>> @@ -87,6 +87,7 @@
>>      MachineInstr *MI = I;
>>      const unsigned *equiv = 0;
>>      X86InstrInfo::SSEDomain domain = TII->GetSSEDomain(MI, equiv);
>> +      (void) domain;
>>      DEBUG(dbgs() << "-isd"[domain] << (equiv ? "* " : "  ") << *MI);
> 
> Why not put the "domain" definition inside of the DEBUG macro? Comme ?a:
> 
>  DEBUG({
>    X86InstrInfo::SSEDomain domain = TII->GetSSEDomain(MI, equiv);
>    dbgs() << "-isd"[domain] << (equiv ? "* " : "  ") << *MI;
>  });

That would work too.

This is just skeleton code that is going away immediately, so anything that keeps the compiler quiet is fine by me.

/jakob




From johnny.chen at apple.com  Thu Mar 25 15:39:04 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Thu, 25 Mar 2010 20:39:04 -0000
Subject: [llvm-commits] [llvm] r99548 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrNEON.td
Message-ID: <20100325203904.957472A6C12C@llvm.org>

Author: johnny
Date: Thu Mar 25 15:39:04 2010
New Revision: 99548

URL: http://llvm.org/viewvc/llvm-project?rev=99548&view=rev
Log:
Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to
expect a Format arg.  N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99548&r1=99547&r2=99548&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Mar 25 15:39:04 2010
@@ -59,9 +59,10 @@
 def MiscFrm       : Format<29>;
 def ThumbMiscFrm  : Format<30>;
 
-def NLdStFrm            : Format<31>;
-def N1RegModImmFrm      : Format<32>;
-def N2RegFrm            : Format<33>;
+def NLdStFrm       : Format<31>;
+def N1RegModImmFrm : Format<32>;
+def N2RegFrm       : Format<33>;
+def NVCVTFrm       : Format<34>;
 
 // Misc flags.
 
@@ -1593,9 +1594,9 @@
 
 // NEON 2 vector register with immediate.
 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
-             dag oops, dag iops, InstrItinClass itin,
+             dag oops, dag iops, Format f, InstrItinClass itin,
              string opc, string dt, string asm, string cstr, list<dag> pattern>
-  : NDataI<oops, iops, NEONFrm, itin, opc, dt, asm, cstr, pattern> {
+  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
   let Inst{24} = op24;
   let Inst{23} = op23;
   let Inst{11-8} = op11_8;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99548&r1=99547&r2=99548&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Mar 25 15:39:04 2010
@@ -875,7 +875,7 @@
 
 // Basic 2-register intrinsics, both double- and quad-register.
 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
-              bits<2> op17_16, bits<5> op11_7, bit op4, 
+              bits<2> op17_16, bits<5> op11_7, bit op4,
               InstrItinClass itin, string OpcodeStr, string Dt,
               ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
   : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
@@ -1305,14 +1305,14 @@
              InstrItinClass itin, string OpcodeStr, string Dt,
              ValueType Ty, SDNode OpNode>
   : N2VImm<op24, op23, op11_8, op7, 0, op4,
-           (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
+           (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegFrm, itin,
            OpcodeStr, Dt, "$dst, $src, $SIMM", "",
            [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
              InstrItinClass itin, string OpcodeStr, string Dt,
              ValueType Ty, SDNode OpNode>
   : N2VImm<op24, op23, op11_8, op7, 1, op4,
-           (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
+           (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegFrm, itin,
            OpcodeStr, Dt, "$dst, $src, $SIMM", "",
            [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
 
@@ -1321,8 +1321,8 @@
              string OpcodeStr, string Dt,
              ValueType ResTy, ValueType OpTy, SDNode OpNode>
   : N2VImm<op24, op23, op11_8, op7, op6, op4,
-           (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
-           OpcodeStr, Dt, "$dst, $src, $SIMM", "",
+           (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegFrm,
+           IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
            [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
                                           (i32 imm:$SIMM))))]>;
 
@@ -1331,7 +1331,7 @@
              InstrItinClass itin, string OpcodeStr, string Dt,
              ValueType ResTy, ValueType OpTy, SDNode OpNode>
   : N2VImm<op24, op23, op11_8, op7, op6, op4,
-           (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
+           (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegFrm, itin,
            OpcodeStr, Dt, "$dst, $src, $SIMM", "",
            [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
                                           (i32 imm:$SIMM))))]>;
@@ -1341,14 +1341,14 @@
 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
                 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
   : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
-           (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD, 
+           (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegFrm, IIC_VPALiD,
            OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
            [(set DPR:$dst, (Ty (add DPR:$src1,
                                 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
                 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
   : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
-           (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD, 
+           (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegFrm, IIC_VPALiD,
            OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
            [(set QPR:$dst, (Ty (add QPR:$src1,
                                 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
@@ -1358,13 +1358,13 @@
 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
                 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
   : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
-           (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD, 
+           (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegFrm, IIC_VSHLiD,
            OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
            [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
                 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
   : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
-           (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ, 
+           (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegFrm, IIC_VSHLiQ,
            OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
            [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
 
@@ -1374,15 +1374,15 @@
               string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
               Intrinsic IntOp>
   : N2VImm<op24, op23, op11_8, op7, 0, op4,
-           (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD, 
-           OpcodeStr, Dt, "$dst, $src, $SIMM", "",
+           (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NVCVTFrm,
+           IIC_VUNAD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
            [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
               string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
               Intrinsic IntOp>
   : N2VImm<op24, op23, op11_8, op7, 1, op4,
-           (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ, 
-           OpcodeStr, Dt, "$dst, $src, $SIMM", "",
+           (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NVCVTFrm,
+           IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
            [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
 
 //===----------------------------------------------------------------------===//




From grosbach at apple.com  Thu Mar 25 15:48:50 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 25 Mar 2010 20:48:50 -0000
Subject: [llvm-commits] [llvm] r99549 -
	/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
Message-ID: <20100325204850.67EC12A6C12C@llvm.org>

Author: grosbach
Date: Thu Mar 25 15:48:50 2010
New Revision: 99549

URL: http://llvm.org/viewvc/llvm-project?rev=99549&view=rev
Log:
ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu

Modified:
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=99549&r1=99548&r2=99549&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Mar 25 15:48:50 2010
@@ -127,6 +127,12 @@
     // operations with NEON instructions.
     if (UseNEONFP.getPosition() == 0)
       UseNEONForSinglePrecisionFP = true;
+    // The VFP vlma and vlms instructions don't play nicely with others;
+    // disable them.
+    // FIXME: This may be true for other variants as well. Get benchmark
+    // numbers and add them if determined that's the case.
+    if (UseVMLxInstructions.getPosition() == 0)
+      UseVMLx = false;
   }
 }
 




From evan.cheng at apple.com  Thu Mar 25 15:54:01 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 13:54:01 -0700
Subject: [llvm-commits] [llvm] r99549 -
	/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
In-Reply-To: <20100325204850.67EC12A6C12C@llvm.org>
References: <20100325204850.67EC12A6C12C@llvm.org>
Message-ID: <F96FCB46-CF02-4369-8B01-84CED349E913@apple.com>

Thanks Jim. But perhaps this can be a subtarget feature specified in ARM.td? For example, x86 has FeatureSlowBTMem which disables uses of certain instructions for specific variants.

Evan

On Mar 25, 2010, at 1:48 PM, Jim Grosbach wrote:

> Author: grosbach
> Date: Thu Mar 25 15:48:50 2010
> New Revision: 99549
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99549&view=rev
> Log:
> ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=99549&r1=99548&r2=99549&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Mar 25 15:48:50 2010
> @@ -127,6 +127,12 @@
>     // operations with NEON instructions.
>     if (UseNEONFP.getPosition() == 0)
>       UseNEONForSinglePrecisionFP = true;
> +    // The VFP vlma and vlms instructions don't play nicely with others;
> +    // disable them.
> +    // FIXME: This may be true for other variants as well. Get benchmark
> +    // numbers and add them if determined that's the case.
> +    if (UseVMLxInstructions.getPosition() == 0)
> +      UseVMLx = false;
>   }
> }
> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From grosbach at apple.com  Thu Mar 25 15:57:43 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 25 Mar 2010 13:57:43 -0700
Subject: [llvm-commits] [llvm] r99549 -
	/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
In-Reply-To: <F96FCB46-CF02-4369-8B01-84CED349E913@apple.com>
References: <20100325204850.67EC12A6C12C@llvm.org>
	<F96FCB46-CF02-4369-8B01-84CED349E913@apple.com>
Message-ID: <2AC1E04B-5548-42B3-9B56-5300FA1630C7@apple.com>

I'll look at the x86 stuff and see if there's a better approach that'll work here. Thanks for the pointer. I agree having the conditional like this is a bit "eww."

That said, I went with this for two reasons: it's consistent with what we already do for the NEON-for-scalar-math flag, and we only want to disable the instructions for specific CPUs (cortex-a8 for now), not whole architecture variants, and as far as I know, the CPUString flag is the only place we have that information.


On Mar 25, 2010, at 1:54 PM, Evan Cheng wrote:

> Thanks Jim. But perhaps this can be a subtarget feature specified in ARM.td? For example, x86 has FeatureSlowBTMem which disables uses of certain instructions for specific variants.
> 
> Evan
> 
> On Mar 25, 2010, at 1:48 PM, Jim Grosbach wrote:
> 
>> Author: grosbach
>> Date: Thu Mar 25 15:48:50 2010
>> New Revision: 99549
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99549&view=rev
>> Log:
>> ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=99549&r1=99548&r2=99549&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Mar 25 15:48:50 2010
>> @@ -127,6 +127,12 @@
>>    // operations with NEON instructions.
>>    if (UseNEONFP.getPosition() == 0)
>>      UseNEONForSinglePrecisionFP = true;
>> +    // The VFP vlma and vlms instructions don't play nicely with others;
>> +    // disable them.
>> +    // FIXME: This may be true for other variants as well. Get benchmark
>> +    // numbers and add them if determined that's the case.
>> +    if (UseVMLxInstructions.getPosition() == 0)
>> +      UseVMLx = false;
>>  }
>> }
>> 
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 




From isanbard at gmail.com  Thu Mar 25 15:57:55 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 25 Mar 2010 13:57:55 -0700
Subject: [llvm-commits] [llvm] r99336 - in /llvm/trunk: tools/Makefile
	utils/buildit/build_llvm
In-Reply-To: <6a8523d61003241237n470b4fdcs6145dba3168aa63c@mail.gmail.com>
References: <20100323221533.E7AE42A6C12D@llvm.org>
	<6a8523d61003241236r3e73a51dvba4c2307e3b3d41@mail.gmail.com>
	<6a8523d61003241237n470b4fdcs6145dba3168aa63c@mail.gmail.com>
Message-ID: <DC3CF990-84AF-43EB-8E39-8063F5640BF1@gmail.com>

The thing with ONLY_TOOLS is that I'd have to specify all but one tool. And then I'd have to keep up-to-date with new tools. Not exactly ideal. How about another option "WITHOUT_TOOLS" that removes said tools?

-bw

On Mar 24, 2010, at 12:37 PM, Daniel Dunbar wrote:

> Note that ONLY_TOOLS is currently broken with edis, but I'm about to fix that.
> 
> - Daniel
> 
> On Wed, Mar 24, 2010 at 12:36 PM, Daniel Dunbar <daniel at zuster.org> wrote:
>> Hi Bill,
>> 
>> Why not change to using ONLY_TOOLS to handle this, instead of adding
>> yet another specialized Makefile variable?
>> 
>>  - Daniel
>> 
>> On Tue, Mar 23, 2010 at 3:15 PM, Bill Wendling <isanbard at gmail.com> wrote:
>>> Author: void
>>> Date: Tue Mar 23 17:15:33 2010
>>> New Revision: 99336
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=99336&view=rev
>>> Log:
>>> Use "DISABLE_EDIS" to disable building "edis" explicitly. Don't build it for
>>> Apple-style builds.
>>> 
>>> Modified:
>>>    llvm/trunk/tools/Makefile
>>>    llvm/trunk/utils/buildit/build_llvm
>>> 
>>> Modified: llvm/trunk/tools/Makefile
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=99336&r1=99335&r2=99336&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/tools/Makefile (original)
>>> +++ llvm/trunk/tools/Makefile Tue Mar 23 17:15:33 2010
>>> @@ -22,7 +22,6 @@
>>>                  lli llvm-extract \
>>>                  bugpoint llvm-bcanalyzer llvm-stub \
>>>                  llvm-mc llvmc
>>> -
>>> 
>>>  # Let users override the set of tools to build from the command line.
>>>  ifdef ONLY_TOOLS
>>> @@ -38,7 +37,7 @@
>>>   # No support for dynamic libraries on windows targets.
>>>   ifneq ($(TARGET_OS), $(filter $(TARGET_OS), Cygwin MingW))
>>>     PARALLEL_DIRS += edis
>>> -
>>> +
>>>     # gold only builds if binutils is around.  It requires "lto" to build before
>>>     # it so it is added to DIRS.
>>>     ifdef BINUTILS_INCDIR
>>> @@ -54,4 +53,9 @@
>>>   PARALLEL_DIRS := $(filter-out edis, $(PARALLEL_DIRS))
>>>  endif
>>> 
>>> +# Don't build edis if we explicitly disabled it.
>>> +ifneq ($(DISABLE_EDIS),1)
>>> +  PARALLEL_DIRS := $(filter-out edis, $(PARALLEL_DIRS))
>>> +endif
>>> +
>>>  include $(LEVEL)/Makefile.common
>>> 
>>> Modified: llvm/trunk/utils/buildit/build_llvm
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=99336&r1=99335&r2=99336&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/utils/buildit/build_llvm (original)
>>> +++ llvm/trunk/utils/buildit/build_llvm Tue Mar 23 17:15:33 2010
>>> @@ -203,6 +203,7 @@
>>>  make $JOBS_FLAG $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \
>>>     UNIVERSAL_SDK_PATH=$HOST_SDKROOT \
>>>     NO_RUNTIME_LIBS=1 \
>>> +    DISABLE_EDIS=1 \
>>>     LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \
>>>     LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \
>>>     CXXFLAGS="-DLLVM_VERSION_INFO='\" Apple Build #$LLVM_VERSION\"'" \
>>> @@ -227,6 +228,7 @@
>>>  # Install the tree into the destination directory.
>>>  make $LOCAL_MAKEFLAGS $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \
>>>     NO_RUNTIME_LIBS=1 \
>>> +    DISABLE_EDIS=1 \
>>>     LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \
>>>     LLVM_SUBMIT_SUBVERSION=$LLVM_SUBMIT_SUBVERSION \
>>>     OPTIMIZE_OPTION='-O3' VERBOSE=1 install
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>> 
>> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From johnny.chen at apple.com  Thu Mar 25 16:49:12 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Thu, 25 Mar 2010 21:49:12 -0000
Subject: [llvm-commits] [llvm] r99557 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20100325214912.C3A332A6C12C@llvm.org>

Author: johnny
Date: Thu Mar 25 16:49:12 2010
New Revision: 99557

URL: http://llvm.org/viewvc/llvm-project?rev=99557&view=rev
Log:
Add NVDupLnFrm and change NVDupLane class to use that format.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99557&r1=99556&r2=99557&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Mar 25 16:49:12 2010
@@ -63,6 +63,7 @@
 def N1RegModImmFrm : Format<32>;
 def N2RegFrm       : Format<33>;
 def NVCVTFrm       : Format<34>;
+def NVDupLnFrm     : Format<35>;
 
 // Misc flags.
 
@@ -1671,7 +1672,7 @@
 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
                 InstrItinClass itin, string opc, string dt, string asm,
                 list<dag> pattern>
-  : NDataI<oops, iops, NEONFrm, itin, opc, dt, asm, "", pattern> {
+  : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
   let Inst{24-23} = 0b11;
   let Inst{21-20} = 0b11;
   let Inst{19-16} = op19_16;




From evan.cheng at apple.com  Thu Mar 25 17:43:34 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 15:43:34 -0700
Subject: [llvm-commits] [llvm] r99549 -
	/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
In-Reply-To: <2AC1E04B-5548-42B3-9B56-5300FA1630C7@apple.com>
References: <20100325204850.67EC12A6C12C@llvm.org>
	<F96FCB46-CF02-4369-8B01-84CED349E913@apple.com>
	<2AC1E04B-5548-42B3-9B56-5300FA1630C7@apple.com>
Message-ID: <D7EBFA92-E862-419A-802C-D18AFCC53A31@apple.com>


On Mar 25, 2010, at 1:57 PM, Jim Grosbach wrote:

> I'll look at the x86 stuff and see if there's a better approach that'll work here. Thanks for the pointer. I agree having the conditional like this is a bit "eww."
> 
> That said, I went with this for two reasons: it's consistent with what we already do for the NEON-for-scalar-math flag, and we only want to disable the instructions for specific CPUs (cortex-a8 for now), not whole architecture variants, and as far as I know, the CPUString flag is the only place we have that information.

You can specify features for individual cpu's. I think that's a cleaner way to go about it.

Evan

> 
> 
> On Mar 25, 2010, at 1:54 PM, Evan Cheng wrote:
> 
>> Thanks Jim. But perhaps this can be a subtarget feature specified in ARM.td? For example, x86 has FeatureSlowBTMem which disables uses of certain instructions for specific variants.
>> 
>> Evan
>> 
>> On Mar 25, 2010, at 1:48 PM, Jim Grosbach wrote:
>> 
>>> Author: grosbach
>>> Date: Thu Mar 25 15:48:50 2010
>>> New Revision: 99549
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=99549&view=rev
>>> Log:
>>> ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu
>>> 
>>> Modified:
>>>  llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=99549&r1=99548&r2=99549&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Mar 25 15:48:50 2010
>>> @@ -127,6 +127,12 @@
>>>   // operations with NEON instructions.
>>>   if (UseNEONFP.getPosition() == 0)
>>>     UseNEONForSinglePrecisionFP = true;
>>> +    // The VFP vlma and vlms instructions don't play nicely with others;
>>> +    // disable them.
>>> +    // FIXME: This may be true for other variants as well. Get benchmark
>>> +    // numbers and add them if determined that's the case.
>>> +    if (UseVMLxInstructions.getPosition() == 0)
>>> +      UseVMLx = false;
>>> }
>>> }
>>> 
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
> 




From daniel at zuster.org  Thu Mar 25 17:49:09 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 25 Mar 2010 22:49:09 -0000
Subject: [llvm-commits] [llvm] r99563 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h include/llvm/MC/MCStreamer.h
 lib/MC/MCAssembler.cpp lib/MC/MCMachOStreamer.cpp tools/llvm-mc/llvm-mc.cpp
Message-ID: <20100325224909.74CC62A6C12C@llvm.org>

Author: ddunbar
Date: Thu Mar 25 17:49:09 2010
New Revision: 99563

URL: http://llvm.org/viewvc/llvm-project?rev=99563&view=rev
Log:
llvm-mc: Add a -mc-relax-all option, which relaxes every fixup. We always need
exactly two passes in that case, and don't ever need to recompute any layout,
so this is a nice baseline for relaxation performance.

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/include/llvm/MC/MCStreamer.h
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MCMachOStreamer.cpp
    llvm/trunk/tools/llvm-mc/llvm-mc.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=99563&r1=99562&r2=99563&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Thu Mar 25 17:49:09 2010
@@ -624,6 +624,7 @@
 
   std::vector<IndirectSymbolData> IndirectSymbols;
 
+  unsigned RelaxAll : 1;
   unsigned SubsectionsViaSymbols : 1;
 
 private:
@@ -727,6 +728,9 @@
     SubsectionsViaSymbols = Value;
   }
 
+  bool getRelaxAll() const { return RelaxAll; }
+  void setRelaxAll(bool Value) { RelaxAll = Value; }
+
   /// @name Section List Access
   /// @{
 

Modified: llvm/trunk/include/llvm/MC/MCStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=99563&r1=99562&r2=99563&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCStreamer.h (original)
+++ llvm/trunk/include/llvm/MC/MCStreamer.h Thu Mar 25 17:49:09 2010
@@ -308,7 +308,8 @@
   /// createMachOStream - Create a machine code streamer which will generative
   /// Mach-O format object files.
   MCStreamer *createMachOStreamer(MCContext &Ctx, TargetAsmBackend &TAB,
-                                  raw_ostream &OS, MCCodeEmitter *CE);
+                                  raw_ostream &OS, MCCodeEmitter *CE,
+                                  bool RelaxAll = false);
 
 } // end namespace llvm
 

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=99563&r1=99562&r2=99563&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Thu Mar 25 17:49:09 2010
@@ -19,9 +19,9 @@
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Twine.h"
+#include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Support/Debug.h"
 #include "llvm/Target/TargetRegistry.h"
 #include "llvm/Target/TargetAsmBackend.h"
 
@@ -30,11 +30,13 @@
 
 namespace {
 namespace stats {
-STATISTIC(RelaxedInstructions, "Number of relaxed instructions");
-STATISTIC(RelaxationSteps, "Number of assembler layout and relaxation steps");
 STATISTIC(EmittedFragments, "Number of emitted assembler fragments");
 STATISTIC(EvaluateFixup, "Number of evaluated fixups");
+STATISTIC(FragmentLayouts, "Number of fragment layouts");
 STATISTIC(ObjectBytes, "Number of emitted object file bytes");
+STATISTIC(RelaxationSteps, "Number of assembler layout and relaxation steps");
+STATISTIC(RelaxedInstructions, "Number of relaxed instructions");
+STATISTIC(SectionLayouts, "Number of section layouts");
 }
 }
 
@@ -185,7 +187,7 @@
 MCAssembler::MCAssembler(MCContext &_Context, TargetAsmBackend &_Backend,
                          MCCodeEmitter &_Emitter, raw_ostream &_OS)
   : Context(_Context), Backend(_Backend), Emitter(_Emitter),
-    OS(_OS), SubsectionsViaSymbols(false)
+    OS(_OS), RelaxAll(false), SubsectionsViaSymbols(false)
 {
 }
 
@@ -402,6 +404,8 @@
                                     uint64_t StartAddress) {
   bool IsVirtual = getBackend().isVirtualSection(SD.getSection());
 
+  ++stats::SectionLayouts;
+
   // Align this section if necessary by adding padding bytes to the previous
   // section. It is safe to adjust this out-of-band, because no symbol or
   // fragment is allowed to point past the end of the section at any time.
@@ -426,6 +430,8 @@
   for (MCSectionData::iterator it = SD.begin(), ie = SD.end(); it != ie; ++it) {
     MCFragment &F = *it;
 
+    ++stats::FragmentLayouts;
+
     uint64_t FragmentOffset = Address - StartAddress;
     Layout.setFragmentOffset(&F, FragmentOffset);
 
@@ -699,6 +705,9 @@
 bool MCAssembler::FixupNeedsRelaxation(const MCAsmFixup &Fixup,
                                        const MCFragment *DF,
                                        const MCAsmLayout &Layout) const {
+  if (getRelaxAll())
+    return true;
+
   // If we cannot resolve the fixup value, it requires relaxation.
   MCValue Target;
   uint64_t Value;
@@ -791,8 +800,11 @@
                                              F.getKind()));
       }
 
-      // Update the layout, and remember that we relaxed.
-      Layout.UpdateForSlide(IF, SlideAmount);
+      // Update the layout, and remember that we relaxed. If we are relaxing
+      // everything, we can skip this step since nothing will depend on updating
+      // the values.
+      if (!getRelaxAll())
+        Layout.UpdateForSlide(IF, SlideAmount);
       WasRelaxed = true;
     }
   }

Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=99563&r1=99562&r2=99563&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Thu Mar 25 17:49:09 2010
@@ -75,6 +75,8 @@
       CurSectionData(0) {}
   ~MCMachOStreamer() {}
 
+  MCAssembler &getAssembler() { return Assembler; }
+
   const MCExpr *AddValueSymbols(const MCExpr *Value) {
     switch (Value->getKind()) {
     case MCExpr::Target: assert(0 && "Can't handle target exprs yet!");
@@ -433,6 +435,10 @@
 }
 
 MCStreamer *llvm::createMachOStreamer(MCContext &Context, TargetAsmBackend &TAB,
-                                      raw_ostream &OS, MCCodeEmitter *CE) {
-  return new MCMachOStreamer(Context, TAB, OS, CE);
+                                      raw_ostream &OS, MCCodeEmitter *CE,
+                                      bool RelaxAll) {
+  MCMachOStreamer *S = new MCMachOStreamer(Context, TAB, OS, CE);
+  if (RelaxAll)
+    S->getAssembler().setRelaxAll(true);
+  return S;
 }

Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=99563&r1=99562&r2=99563&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Thu Mar 25 17:49:09 2010
@@ -55,6 +55,9 @@
 OutputAsmVariant("output-asm-variant",
                  cl::desc("Syntax variant to use for output printing"));
 
+static cl::opt<bool>
+RelaxAll("mc-relax-all", cl::desc("Relax all fixups"));
+
 enum OutputFileType {
   OFT_Null,
   OFT_AssemblyFile,
@@ -298,7 +301,7 @@
     assert(FileType == OFT_ObjectFile && "Invalid file type!");
     CE.reset(TheTarget->createCodeEmitter(*TM, Ctx));
     TAB.reset(TheTarget->createAsmBackend(TripleName));
-    Str.reset(createMachOStreamer(Ctx, *TAB, *Out, CE.get()));
+    Str.reset(createMachOStreamer(Ctx, *TAB, *Out, CE.get(), RelaxAll));
   }
 
   AsmParser Parser(SrcMgr, Ctx, *Str.get(), *MAI);




From ggreif at gmail.com  Thu Mar 25 18:06:16 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 25 Mar 2010 23:06:16 -0000
Subject: [llvm-commits] [llvm] r99564 - in /llvm/trunk: include/llvm/
 include/llvm/Support/ lib/Analysis/ lib/Transforms/Scalar/
 lib/Transforms/Utils/ lib/VMCore/
Message-ID: <20100325230616.6E7392A6C12C@llvm.org>

Author: ggreif
Date: Thu Mar 25 18:06:16 2010
New Revision: 99564

URL: http://llvm.org/viewvc/llvm-project?rev=99564&view=rev
Log:
rename use_const_iterator to const_use_iterator for consistency's sake

Modified:
    llvm/trunk/include/llvm/Support/CFG.h
    llvm/trunk/include/llvm/Support/CallSite.h
    llvm/trunk/include/llvm/Value.h
    llvm/trunk/lib/Analysis/CaptureTracking.cpp
    llvm/trunk/lib/Analysis/LiveValues.cpp
    llvm/trunk/lib/Analysis/MemoryBuiltins.cpp
    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
    llvm/trunk/lib/Transforms/Scalar/Reg2Mem.cpp
    llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
    llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
    llvm/trunk/lib/VMCore/Constants.cpp
    llvm/trunk/lib/VMCore/Function.cpp
    llvm/trunk/lib/VMCore/Globals.cpp
    llvm/trunk/lib/VMCore/Instruction.cpp
    llvm/trunk/lib/VMCore/Value.cpp

Modified: llvm/trunk/include/llvm/Support/CFG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CFG.h?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CFG.h (original)
+++ llvm/trunk/include/llvm/Support/CFG.h Thu Mar 25 18:06:16 2010
@@ -67,7 +67,7 @@
 
 typedef PredIterator<BasicBlock, Value::use_iterator> pred_iterator;
 typedef PredIterator<const BasicBlock,
-                     Value::use_const_iterator> pred_const_iterator;
+                     Value::const_use_iterator> pred_const_iterator;
 
 inline pred_iterator pred_begin(BasicBlock *BB) { return pred_iterator(BB); }
 inline pred_const_iterator pred_begin(const BasicBlock *BB) {

Modified: llvm/trunk/include/llvm/Support/CallSite.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CallSite.h (original)
+++ llvm/trunk/include/llvm/Support/CallSite.h Thu Mar 25 18:06:16 2010
@@ -196,7 +196,7 @@
   bool isCallee(Value::use_iterator UI) const {
     return getCallee() == &UI.getUse();
   }
-  bool isCallee(Value::use_const_iterator UI) const {
+  bool isCallee(Value::const_use_iterator UI) const {
     return getCallee() == &UI.getUse();
   }
 private:

Modified: llvm/trunk/include/llvm/Value.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Value.h?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Value.h (original)
+++ llvm/trunk/include/llvm/Value.h Thu Mar 25 18:06:16 2010
@@ -157,13 +157,13 @@
   // Methods for handling the chain of uses of this Value.
   //
   typedef value_use_iterator<User>       use_iterator;
-  typedef value_use_iterator<const User> use_const_iterator;
+  typedef value_use_iterator<const User> const_use_iterator;
 
   bool               use_empty() const { return UseList == 0; }
   use_iterator       use_begin()       { return use_iterator(UseList); }
-  use_const_iterator use_begin() const { return use_const_iterator(UseList); }
+  const_use_iterator use_begin() const { return const_use_iterator(UseList); }
   use_iterator       use_end()         { return use_iterator(0);   }
-  use_const_iterator use_end()   const { return use_const_iterator(0);   }
+  const_use_iterator use_end()   const { return const_use_iterator(0);   }
   User              *use_back()        { return *use_begin(); }
   const User        *use_back()  const { return *use_begin(); }
 
@@ -172,7 +172,7 @@
   /// traversing the whole use list.
   ///
   bool hasOneUse() const {
-    use_const_iterator I = use_begin(), E = use_end();
+    const_use_iterator I = use_begin(), E = use_end();
     if (I == E) return false;
     return ++I == E;
   }

Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CaptureTracking.cpp?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/CaptureTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/CaptureTracking.cpp Thu Mar 25 18:06:16 2010
@@ -49,7 +49,7 @@
   SmallSet<Use*, Threshold> Visited;
   int Count = 0;
 
-  for (Value::use_const_iterator UI = V->use_begin(), UE = V->use_end();
+  for (Value::const_use_iterator UI = V->use_begin(), UE = V->use_end();
        UI != UE; ++UI) {
     // If there are lots of uses, conservatively say that the value
     // is captured to avoid taking too much compile time.

Modified: llvm/trunk/lib/Analysis/LiveValues.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LiveValues.cpp?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/LiveValues.cpp (original)
+++ llvm/trunk/lib/Analysis/LiveValues.cpp Thu Mar 25 18:06:16 2010
@@ -125,7 +125,7 @@
   bool LiveOutOfDefBB = false;
 
   // Examine each use of the value.
-  for (Value::use_const_iterator I = V->use_begin(), E = V->use_end();
+  for (Value::const_use_iterator I = V->use_begin(), E = V->use_end();
        I != E; ++I) {
     const User *U = *I;
     const BasicBlock *UseBB = cast<Instruction>(U)->getParent();

Modified: llvm/trunk/lib/Analysis/MemoryBuiltins.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryBuiltins.cpp?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/MemoryBuiltins.cpp (original)
+++ llvm/trunk/lib/Analysis/MemoryBuiltins.cpp Thu Mar 25 18:06:16 2010
@@ -139,7 +139,7 @@
   unsigned NumOfBitCastUses = 0;
 
   // Determine if CallInst has a bitcast use.
-  for (Value::use_const_iterator UI = CI->use_begin(), E = CI->use_end();
+  for (Value::const_use_iterator UI = CI->use_begin(), E = CI->use_end();
        UI != E; )
     if (const BitCastInst *BCI = dyn_cast<BitCastInst>(*UI++)) {
       MallocType = cast<PointerType>(BCI->getDestTy());

Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Thu Mar 25 18:06:16 2010
@@ -174,7 +174,7 @@
   // don't mess around with them.
   BasicBlock::const_iterator BBI = BB->begin();
   while (const PHINode *PN = dyn_cast<PHINode>(BBI++)) {
-    for (Value::use_const_iterator UI = PN->use_begin(), E = PN->use_end();
+    for (Value::const_use_iterator UI = PN->use_begin(), E = PN->use_end();
          UI != E; ++UI) {
       const Instruction *User = cast<Instruction>(*UI);
       if (User->getParent() != DestBB || !isa<PHINode>(User))

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Thu Mar 25 18:06:16 2010
@@ -1899,7 +1899,7 @@
       const Value *V = U->getValue();
       if (const Instruction *Inst = dyn_cast<Instruction>(V))
         if (L->contains(Inst)) continue;
-      for (Value::use_const_iterator UI = V->use_begin(), UE = V->use_end();
+      for (Value::const_use_iterator UI = V->use_begin(), UE = V->use_end();
            UI != UE; ++UI) {
         const Instruction *UserInst = dyn_cast<Instruction>(*UI);
         // Ignore non-instructions.

Modified: llvm/trunk/lib/Transforms/Scalar/Reg2Mem.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/Reg2Mem.cpp?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/Reg2Mem.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/Reg2Mem.cpp Thu Mar 25 18:06:16 2010
@@ -45,7 +45,7 @@
 
    bool valueEscapes(const Instruction *Inst) const {
      const BasicBlock *BB = Inst->getParent();
-      for (Value::use_const_iterator UI = Inst->use_begin(),E = Inst->use_end();
+      for (Value::const_use_iterator UI = Inst->use_begin(),E = Inst->use_end();
            UI != E; ++UI)
         if (cast<Instruction>(*UI)->getParent() != BB ||
             isa<PHINode>(*UI))

Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Thu Mar 25 18:06:16 2010
@@ -1709,7 +1709,7 @@
   // Delete any dead constantexpr klingons.
   GV->removeDeadConstantUsers();
 
-  for (Value::use_const_iterator UI = GV->use_begin(), E = GV->use_end();
+  for (Value::const_use_iterator UI = GV->use_begin(), E = GV->use_end();
        UI != E; ++UI) {
     const User *U = *UI;
     if (const StoreInst *SI = dyn_cast<StoreInst>(U)) {

Modified: llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp Thu Mar 25 18:06:16 2010
@@ -68,7 +68,7 @@
   // assignments to subsections of the memory unit.
 
   // Only allow direct and non-volatile loads and stores...
-  for (Value::use_const_iterator UI = AI->use_begin(), UE = AI->use_end();
+  for (Value::const_use_iterator UI = AI->use_begin(), UE = AI->use_end();
        UI != UE; ++UI)     // Loop over all of the uses of the alloca
     if (const LoadInst *LI = dyn_cast<LoadInst>(*UI)) {
       if (LI->isVolatile())

Modified: llvm/trunk/lib/VMCore/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Constants.cpp (original)
+++ llvm/trunk/lib/VMCore/Constants.cpp Thu Mar 25 18:06:16 2010
@@ -160,7 +160,7 @@
 /// isConstantUsed - Return true if the constant has users other than constant
 /// exprs and other dangling things.
 bool Constant::isConstantUsed() const {
-  for (use_const_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) {
+  for (const_use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) {
     const Constant *UC = dyn_cast<Constant>(*UI);
     if (UC == 0 || isa<GlobalValue>(UC))
       return true;

Modified: llvm/trunk/lib/VMCore/Function.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Function.cpp (original)
+++ llvm/trunk/lib/VMCore/Function.cpp Thu Mar 25 18:06:16 2010
@@ -404,7 +404,7 @@
 /// hasAddressTaken - returns true if there are any uses of this function
 /// other than direct calls or invokes to it.
 bool Function::hasAddressTaken(const User* *PutOffender) const {
-  for (Value::use_const_iterator I = use_begin(), E = use_end(); I != E; ++I) {
+  for (Value::const_use_iterator I = use_begin(), E = use_end(); I != E; ++I) {
     const User *U = *I;
     if (!isa<CallInst>(U) && !isa<InvokeInst>(U))
       return PutOffender ? (*PutOffender = U, true) : true;

Modified: llvm/trunk/lib/VMCore/Globals.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Globals.cpp?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Globals.cpp (original)
+++ llvm/trunk/lib/VMCore/Globals.cpp Thu Mar 25 18:06:16 2010
@@ -61,8 +61,8 @@
 /// that want to check to see if a global is unused, but don't want to deal
 /// with potentially dead constants hanging off of the globals.
 void GlobalValue::removeDeadConstantUsers() const {
-  Value::use_const_iterator I = use_begin(), E = use_end();
-  Value::use_const_iterator LastNonDeadUser = E;
+  Value::const_use_iterator I = use_begin(), E = use_end();
+  Value::const_use_iterator LastNonDeadUser = E;
   while (I != E) {
     if (const Constant *User = dyn_cast<Constant>(*I)) {
       if (!removeDeadUsersOfConstant(User)) {

Modified: llvm/trunk/lib/VMCore/Instruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instruction.cpp (original)
+++ llvm/trunk/lib/VMCore/Instruction.cpp Thu Mar 25 18:06:16 2010
@@ -283,7 +283,7 @@
 /// specified block.  Note that PHI nodes are considered to evaluate their
 /// operands in the corresponding predecessor block.
 bool Instruction::isUsedOutsideOfBlock(const BasicBlock *BB) const {
-  for (use_const_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) {
+  for (const_use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) {
     // PHI nodes uses values in the corresponding predecessor block.  For other
     // instructions, just check to see whether the parent of the use matches up.
     const PHINode *PN = dyn_cast<PHINode>(*UI);

Modified: llvm/trunk/lib/VMCore/Value.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Value.cpp?rev=99564&r1=99563&r2=99564&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Value.cpp (original)
+++ llvm/trunk/lib/VMCore/Value.cpp Thu Mar 25 18:06:16 2010
@@ -86,7 +86,7 @@
 /// hasNUses - Return true if this Value has exactly N users.
 ///
 bool Value::hasNUses(unsigned N) const {
-  use_const_iterator UI = use_begin(), E = use_end();
+  const_use_iterator UI = use_begin(), E = use_end();
 
   for (; N; --N, ++UI)
     if (UI == E) return false;  // Too few.
@@ -97,7 +97,7 @@
 /// logically equivalent to getNumUses() >= N.
 ///
 bool Value::hasNUsesOrMore(unsigned N) const {
-  use_const_iterator UI = use_begin(), E = use_end();
+  const_use_iterator UI = use_begin(), E = use_end();
 
   for (; N; --N, ++UI)
     if (UI == E) return false;  // Too few.
@@ -108,7 +108,7 @@
 /// isUsedInBasicBlock - Return true if this value is used in the specified
 /// basic block.
 bool Value::isUsedInBasicBlock(const BasicBlock *BB) const {
-  for (use_const_iterator I = use_begin(), E = use_end(); I != E; ++I) {
+  for (const_use_iterator I = use_begin(), E = use_end(); I != E; ++I) {
     const Instruction *User = dyn_cast<Instruction>(*I);
     if (User && User->getParent() == BB)
       return true;




From grosbach at apple.com  Thu Mar 25 18:11:16 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 25 Mar 2010 23:11:16 -0000
Subject: [llvm-commits] [llvm] r99565 - in /llvm/trunk/lib/Target/ARM:
 ARM.td ARMSubtarget.cpp ARMSubtarget.h
Message-ID: <20100325231116.45EB82A6C12C@llvm.org>

Author: grosbach
Date: Thu Mar 25 18:11:16 2010
New Revision: 99565

URL: http://llvm.org/viewvc/llvm-project?rev=99565&view=rev
Log:
switch the use-vml[as] instructions flag to a subtarget 'feature'

Modified:
    llvm/trunk/lib/Target/ARM/ARM.td
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
    llvm/trunk/lib/Target/ARM/ARMSubtarget.h

Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=99565&r1=99564&r2=99565&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Thu Mar 25 18:11:16 2010
@@ -43,6 +43,15 @@
 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
                                      "Enable half-precision floating point">;
 
+// Some processors have multiply-accumulate instructions that don't
+// play nicely with other VFP instructions, and it's generally better
+// to just not use them.
+// FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
+// others as well. We should do more benchmarking and confirm one way or
+// the other.
+def HasSlowVMLx   : SubtargetFeature<"vmlx", "SlowVMLx", "true",
+                                     "Disable VFP MAC instructions">;
+
 //===----------------------------------------------------------------------===//
 // ARM Processors supported.
 //
@@ -106,7 +115,7 @@
 
 // V7 Processors.
 def : Processor<"cortex-a8",        CortexA8Itineraries,
-                [ArchV7A, FeatureThumb2, FeatureNEON]>;
+                [ArchV7A, FeatureThumb2, FeatureNEON, HasSlowVMLx]>;
 def : ProcNoItin<"cortex-a9",       [ArchV7A, FeatureThumb2, FeatureNEON]>;
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=99565&r1=99564&r2=99565&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Mar 25 18:11:16 2010
@@ -26,10 +26,6 @@
 UseNEONFP("arm-use-neon-fp",
           cl::desc("Use NEON for single-precision FP"),
           cl::init(false), cl::Hidden);
-static cl::opt<bool>
-UseVMLxInstructions("arm-use-vmlx",
-                    cl::desc("Use VFP vmla and vmls instructions"),
-                    cl::init(true), cl::Hidden);
 
 static cl::opt<bool>
 UseMOVT("arm-use-movt",
@@ -40,7 +36,7 @@
   : ARMArchVersion(V4)
   , ARMFPUType(None)
   , UseNEONForSinglePrecisionFP(UseNEONFP)
-  , UseVMLx(UseVMLxInstructions)
+  , SlowVMLx(false)
   , IsThumb(isT)
   , ThumbMode(Thumb1)
   , PostRAScheduler(false)
@@ -127,12 +123,6 @@
     // operations with NEON instructions.
     if (UseNEONFP.getPosition() == 0)
       UseNEONForSinglePrecisionFP = true;
-    // The VFP vlma and vlms instructions don't play nicely with others;
-    // disable them.
-    // FIXME: This may be true for other variants as well. Get benchmark
-    // numbers and add them if determined that's the case.
-    if (UseVMLxInstructions.getPosition() == 0)
-      UseVMLx = false;
   }
 }
 

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=99565&r1=99564&r2=99565&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Mar 25 18:11:16 2010
@@ -50,9 +50,9 @@
   /// determine if NEON should actually be used.
   bool UseNEONForSinglePrecisionFP;
 
-  /// UseVMLx - If the VFP2 instructions are available, indicates whether
-  /// the VML[AS] instructions should be used.
-  bool UseVMLx;
+  /// SlowVMLx - If the VFP2 instructions are available, indicates whether
+  /// the VML[AS] instructions are slow (if so, don't use them).
+  bool SlowVMLx;
 
   /// IsThumb - True if we are in thumb mode, false if in ARM mode.
   bool IsThumb;
@@ -123,7 +123,7 @@
   bool hasNEON() const { return ARMFPUType >= NEON;  }
   bool useNEONForSinglePrecisionFP() const {
     return hasNEON() && UseNEONForSinglePrecisionFP; }
-  bool useVMLx() const {return hasVFP2() && UseVMLx; }
+  bool useVMLx() const {return hasVFP2() && !SlowVMLx; }
 
   bool hasFP16() const { return HasFP16; }
 




From johnny.chen at apple.com  Thu Mar 25 18:11:56 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Thu, 25 Mar 2010 23:11:56 -0000
Subject: [llvm-commits] [llvm] r99566 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20100325231156.A6AFA2A6C12C@llvm.org>

Author: johnny
Date: Thu Mar 25 18:11:56 2010
New Revision: 99566

URL: http://llvm.org/viewvc/llvm-project?rev=99566&view=rev
Log:
Removed instruction class NI from ARMInstrFormats.td.
It doesn't seem to be used anywhere.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99566&r1=99565&r2=99566&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Mar 25 18:11:56 2010
@@ -1515,12 +1515,6 @@
   list<Predicate> Predicates = [HasNEON];
 }
 
-class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm,
-         list<dag> pattern>
-  : NeonXI<oops, iops, AddrModeNone, IndexModeNone, NEONFrm, itin, opc, asm, "",
-           pattern> {
-}
-
 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
             dag oops, dag iops, InstrItinClass itin,
             string opc, string dt, string asm, string cstr, list<dag> pattern>




From grosbach at apple.com  Thu Mar 25 18:13:00 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 25 Mar 2010 16:13:00 -0700
Subject: [llvm-commits] [llvm] r99549 -
	/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
In-Reply-To: <D7EBFA92-E862-419A-802C-D18AFCC53A31@apple.com>
References: <20100325204850.67EC12A6C12C@llvm.org>
	<F96FCB46-CF02-4369-8B01-84CED349E913@apple.com>
	<2AC1E04B-5548-42B3-9B56-5300FA1630C7@apple.com>
	<D7EBFA92-E862-419A-802C-D18AFCC53A31@apple.com>
Message-ID: <07095A46-8225-4A34-8578-9B3051E3B366@apple.com>


On Mar 25, 2010, at 3:43 PM, Evan Cheng wrote:

> 
> On Mar 25, 2010, at 1:57 PM, Jim Grosbach wrote:
> 
>> I'll look at the x86 stuff and see if there's a better approach that'll work here. Thanks for the pointer. I agree having the conditional like this is a bit "eww."
>> 
>> That said, I went with this for two reasons: it's consistent with what we already do for the NEON-for-scalar-math flag, and we only want to disable the instructions for specific CPUs (cortex-a8 for now), not whole architecture variants, and as far as I know, the CPUString flag is the only place we have that information.
> 
> You can specify features for individual cpu's. I think that's a cleaner way to go about it.
> 

Done in r99565. Great suggestion. I like that a lot better.

Should we do the same for the UseNEONForSinglePrecisionFP flag, do you think?

> Evan
> 
>> 
>> 
>> On Mar 25, 2010, at 1:54 PM, Evan Cheng wrote:
>> 
>>> Thanks Jim. But perhaps this can be a subtarget feature specified in ARM.td? For example, x86 has FeatureSlowBTMem which disables uses of certain instructions for specific variants.
>>> 
>>> Evan
>>> 
>>> On Mar 25, 2010, at 1:48 PM, Jim Grosbach wrote:
>>> 
>>>> Author: grosbach
>>>> Date: Thu Mar 25 15:48:50 2010
>>>> New Revision: 99549
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=99549&view=rev
>>>> Log:
>>>> ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu
>>>> 
>>>> Modified:
>>>> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>>>> 
>>>> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=99549&r1=99548&r2=99549&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
>>>> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Mar 25 15:48:50 2010
>>>> @@ -127,6 +127,12 @@
>>>>  // operations with NEON instructions.
>>>>  if (UseNEONFP.getPosition() == 0)
>>>>    UseNEONForSinglePrecisionFP = true;
>>>> +    // The VFP vlma and vlms instructions don't play nicely with others;
>>>> +    // disable them.
>>>> +    // FIXME: This may be true for other variants as well. Get benchmark
>>>> +    // numbers and add them if determined that's the case.
>>>> +    if (UseVMLxInstructions.getPosition() == 0)
>>>> +      UseVMLx = false;
>>>> }
>>>> }
>>>> 
>>>> 
>>>> 
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>> 
>> 
> 




From evan.cheng at apple.com  Thu Mar 25 18:20:21 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 16:20:21 -0700
Subject: [llvm-commits] [llvm] r99549 -
	/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
In-Reply-To: <07095A46-8225-4A34-8578-9B3051E3B366@apple.com>
References: <20100325204850.67EC12A6C12C@llvm.org>
	<F96FCB46-CF02-4369-8B01-84CED349E913@apple.com>
	<2AC1E04B-5548-42B3-9B56-5300FA1630C7@apple.com>
	<D7EBFA92-E862-419A-802C-D18AFCC53A31@apple.com>
	<07095A46-8225-4A34-8578-9B3051E3B366@apple.com>
Message-ID: <D40B996F-DED0-4E53-83A4-0AD2DA41D8E7@apple.com>


On Mar 25, 2010, at 4:13 PM, Jim Grosbach wrote:

> 
> On Mar 25, 2010, at 3:43 PM, Evan Cheng wrote:
> 
>> 
>> On Mar 25, 2010, at 1:57 PM, Jim Grosbach wrote:
>> 
>>> I'll look at the x86 stuff and see if there's a better approach that'll work here. Thanks for the pointer. I agree having the conditional like this is a bit "eww."
>>> 
>>> That said, I went with this for two reasons: it's consistent with what we already do for the NEON-for-scalar-math flag, and we only want to disable the instructions for specific CPUs (cortex-a8 for now), not whole architecture variants, and as far as I know, the CPUString flag is the only place we have that information.
>> 
>> You can specify features for individual cpu's. I think that's a cleaner way to go about it.
>> 
> 
> Done in r99565. Great suggestion. I like that a lot better.
> 
> Should we do the same for the UseNEONForSinglePrecisionFP flag, do you think?

Yes, I think so. Thanks.

Evan

> 
>> Evan
>> 
>>> 
>>> 
>>> On Mar 25, 2010, at 1:54 PM, Evan Cheng wrote:
>>> 
>>>> Thanks Jim. But perhaps this can be a subtarget feature specified in ARM.td? For example, x86 has FeatureSlowBTMem which disables uses of certain instructions for specific variants.
>>>> 
>>>> Evan
>>>> 
>>>> On Mar 25, 2010, at 1:48 PM, Jim Grosbach wrote:
>>>> 
>>>>> Author: grosbach
>>>>> Date: Thu Mar 25 15:48:50 2010
>>>>> New Revision: 99549
>>>>> 
>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=99549&view=rev
>>>>> Log:
>>>>> ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu
>>>>> 
>>>>> Modified:
>>>>> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>>>>> 
>>>>> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=99549&r1=99548&r2=99549&view=diff
>>>>> ==============================================================================
>>>>> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
>>>>> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Mar 25 15:48:50 2010
>>>>> @@ -127,6 +127,12 @@
>>>>> // operations with NEON instructions.
>>>>> if (UseNEONFP.getPosition() == 0)
>>>>>   UseNEONForSinglePrecisionFP = true;
>>>>> +    // The VFP vlma and vlms instructions don't play nicely with others;
>>>>> +    // disable them.
>>>>> +    // FIXME: This may be true for other variants as well. Get benchmark
>>>>> +    // numbers and add them if determined that's the case.
>>>>> +    if (UseVMLxInstructions.getPosition() == 0)
>>>>> +      UseVMLx = false;
>>>>> }
>>>>> }
>>>>> 
>>>>> 
>>>>> 
>>>>> _______________________________________________
>>>>> llvm-commits mailing list
>>>>> llvm-commits at cs.uiuc.edu
>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>> 
>>> 
>> 
> 




From ggreif at gmail.com  Thu Mar 25 18:25:29 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 25 Mar 2010 23:25:29 -0000
Subject: [llvm-commits] [llvm] r99567 - in /llvm/trunk:
 include/llvm/Support/CFG.h lib/Analysis/ProfileEstimatorPass.cpp
 lib/Analysis/ProfileInfo.cpp lib/Analysis/ProfileInfoLoaderPass.cpp
 lib/Analysis/ProfileVerifierPass.cpp
 lib/Transforms/Utils/BreakCriticalEdges.cpp lib/VMCore/AsmWriter.cpp
Message-ID: <20100325232529.203C82A6C12C@llvm.org>

Author: ggreif
Date: Thu Mar 25 18:25:28 2010
New Revision: 99567

URL: http://llvm.org/viewvc/llvm-project?rev=99567&view=rev
Log:
rename pred_const_iterator to const_pred_iterator for consistency's sake

Modified:
    llvm/trunk/include/llvm/Support/CFG.h
    llvm/trunk/lib/Analysis/ProfileEstimatorPass.cpp
    llvm/trunk/lib/Analysis/ProfileInfo.cpp
    llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp
    llvm/trunk/lib/Analysis/ProfileVerifierPass.cpp
    llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
    llvm/trunk/lib/VMCore/AsmWriter.cpp

Modified: llvm/trunk/include/llvm/Support/CFG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CFG.h?rev=99567&r1=99566&r2=99567&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CFG.h (original)
+++ llvm/trunk/include/llvm/Support/CFG.h Thu Mar 25 18:25:28 2010
@@ -67,15 +67,15 @@
 
 typedef PredIterator<BasicBlock, Value::use_iterator> pred_iterator;
 typedef PredIterator<const BasicBlock,
-                     Value::const_use_iterator> pred_const_iterator;
+                     Value::const_use_iterator> const_pred_iterator;
 
 inline pred_iterator pred_begin(BasicBlock *BB) { return pred_iterator(BB); }
-inline pred_const_iterator pred_begin(const BasicBlock *BB) {
-  return pred_const_iterator(BB);
+inline const_pred_iterator pred_begin(const BasicBlock *BB) {
+  return const_pred_iterator(BB);
 }
 inline pred_iterator pred_end(BasicBlock *BB) { return pred_iterator(BB, true);}
-inline pred_const_iterator pred_end(const BasicBlock *BB) {
-  return pred_const_iterator(BB, true);
+inline const_pred_iterator pred_end(const BasicBlock *BB) {
+  return const_pred_iterator(BB, true);
 }
 
 
@@ -268,7 +268,7 @@
 
 template <> struct GraphTraits<Inverse<const BasicBlock*> > {
   typedef const BasicBlock NodeType;
-  typedef pred_const_iterator ChildIteratorType;
+  typedef const_pred_iterator ChildIteratorType;
   static NodeType *getEntryNode(Inverse<const BasicBlock*> G) {
     return G.Graph;
   }

Modified: llvm/trunk/lib/Analysis/ProfileEstimatorPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ProfileEstimatorPass.cpp?rev=99567&r1=99566&r2=99567&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ProfileEstimatorPass.cpp (original)
+++ llvm/trunk/lib/Analysis/ProfileEstimatorPass.cpp Thu Mar 25 18:25:28 2010
@@ -398,7 +398,7 @@
     for (Function::const_iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) {
       const BasicBlock *BB = &(*FI);
       BlockInformation[&F][BB] = 0;
-      pred_const_iterator predi = pred_begin(BB), prede = pred_end(BB);
+      const_pred_iterator predi = pred_begin(BB), prede = pred_end(BB);
       if (predi == prede) {
         Edge e = getEdge(0,BB);
         setEdgeWeight(e,0);

Modified: llvm/trunk/lib/Analysis/ProfileInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ProfileInfo.cpp?rev=99567&r1=99566&r2=99567&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ProfileInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/ProfileInfo.cpp Thu Mar 25 18:25:28 2010
@@ -67,7 +67,7 @@
 
   double Count = MissingValue;
 
-  pred_const_iterator PI = pred_begin(BB), PE = pred_end(BB);
+  const_pred_iterator PI = pred_begin(BB), PE = pred_end(BB);
 
   // Are there zero predecessors of this block?
   if (PI == PE) {
@@ -508,7 +508,7 @@
   // have no value
   double incount = 0;
   SmallSet<const BasicBlock*,8> pred_visited;
-  pred_const_iterator bbi = pred_begin(BB), bbe = pred_end(BB);
+  const_pred_iterator bbi = pred_begin(BB), bbe = pred_end(BB);
   if (bbi==bbe) {
     Edge e = getEdge(0,BB);
     incount += readEdgeOrRemember(e, getEdgeWeight(e) ,edgetocalc,uncalculated);
@@ -582,7 +582,7 @@
   double inWeight = 0;
   std::set<Edge> inMissing;
   std::set<const BasicBlock*> ProcessedPreds;
-  pred_const_iterator bbi = pred_begin(BB), bbe = pred_end(BB);
+  const_pred_iterator bbi = pred_begin(BB), bbe = pred_end(BB);
   if (bbi == bbe) {
     readEdge(this,getEdge(0,BB),inWeight,inMissing);
   }
@@ -639,7 +639,7 @@
 //         FI != FE; ++FI) {
 //      const BasicBlock* BB = &(*FI);
 //      {
-//        pred_const_iterator NBB = pred_begin(BB), End = pred_end(BB);
+//        const_pred_iterator NBB = pred_begin(BB), End = pred_end(BB);
 //        if (NBB == End) {
 //          setEdgeWeight(getEdge(0,BB),0);
 //        }
@@ -779,7 +779,7 @@
       // Calculate incoming flow.
       double iw = 0; unsigned inmissing = 0; unsigned incount = 0; unsigned invalid = 0;
       std::set<const BasicBlock *> Processed;
-      for (pred_const_iterator NBB = pred_begin(BB), End = pred_end(BB);
+      for (const_pred_iterator NBB = pred_begin(BB), End = pred_end(BB);
            NBB != End; ++NBB) {
         if (Processed.insert(*NBB).second) {
           Edge e = getEdge(*NBB, BB);
@@ -869,7 +869,7 @@
         if (getEdgeWeight(e) == MissingValue) {
           double iw = 0;
           std::set<const BasicBlock *> Processed;
-          for (pred_const_iterator NBB = pred_begin(BB), End = pred_end(BB);
+          for (const_pred_iterator NBB = pred_begin(BB), End = pred_end(BB);
                NBB != End; ++NBB) {
             if (Processed.insert(*NBB).second) {
               Edge e = getEdge(*NBB, BB);
@@ -893,7 +893,7 @@
       const BasicBlock *Dest;
       Path P;
       bool BackEdgeFound = false;
-      for (pred_const_iterator NBB = pred_begin(BB), End = pred_end(BB);
+      for (const_pred_iterator NBB = pred_begin(BB), End = pred_end(BB);
            NBB != End; ++NBB) {
         Dest = GetPath(BB, *NBB, P, GetPathToDest | GetPathWithNewEdges);
         if (Dest == *NBB) {
@@ -935,7 +935,7 @@
         // Calculate incoming flow.
         double iw = 0;
         std::set<const BasicBlock *> Processed;
-        for (pred_const_iterator NBB = pred_begin(BB), End = pred_end(BB);
+        for (const_pred_iterator NBB = pred_begin(BB), End = pred_end(BB);
              NBB != End; ++NBB) {
           if (Processed.insert(*NBB).second) {
             Edge e = getEdge(*NBB, BB);
@@ -965,7 +965,7 @@
     while(FI != FE && !FoundPath) {
       const BasicBlock *BB = *FI; ++FI;
 
-      for (pred_const_iterator NBB = pred_begin(BB), End = pred_end(BB);
+      for (const_pred_iterator NBB = pred_begin(BB), End = pred_end(BB);
            NBB != End; ++NBB) {
         Edge e = getEdge(*NBB,BB);
         double w = getEdgeWeight(e);

Modified: llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp?rev=99567&r1=99566&r2=99567&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp (original)
+++ llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp Thu Mar 25 18:25:28 2010
@@ -119,7 +119,7 @@
        bbi != bbe; ++bbi) {
     recurseBasicBlock(*bbi);
   }
-  for (pred_const_iterator bbi = pred_begin(BB), bbe = pred_end(BB);
+  for (const_pred_iterator bbi = pred_begin(BB), bbe = pred_end(BB);
        bbi != bbe; ++bbi) {
     recurseBasicBlock(*bbi);
   }

Modified: llvm/trunk/lib/Analysis/ProfileVerifierPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ProfileVerifierPass.cpp?rev=99567&r1=99566&r2=99567&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ProfileVerifierPass.cpp (original)
+++ llvm/trunk/lib/Analysis/ProfileVerifierPass.cpp Thu Mar 25 18:25:28 2010
@@ -96,8 +96,8 @@
     double inWeight = 0;
     int inCount = 0;
     std::set<const BType*> ProcessedPreds;
-    for ( pred_const_iterator bbi = pred_begin(BB), bbe = pred_end(BB);
-          bbi != bbe; ++bbi ) {
+    for (const_pred_iterator bbi = pred_begin(BB), bbe = pred_end(BB);
+         bbi != bbe; ++bbi ) {
       if (ProcessedPreds.insert(*bbi).second) {
         typename ProfileInfoT<FType, BType>::Edge E = PI->getEdge(*bbi,BB);
         double EdgeWeight = PI->getEdgeWeight(E);
@@ -242,7 +242,7 @@
 
     // Read predecessors.
     std::set<const BType*> ProcessedPreds;
-    pred_const_iterator bpi = pred_begin(BB), bpe = pred_end(BB);
+    const_pred_iterator bpi = pred_begin(BB), bpe = pred_end(BB);
     // If there are none, check for (0,BB) edge.
     if (bpi == bpe) {
       DI.inWeight += ReadOrAssert(PI->getEdge(0,BB));

Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=99567&r1=99566&r2=99567&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Thu Mar 25 18:25:28 2010
@@ -94,7 +94,7 @@
   if (TI->getNumSuccessors() == 1) return false;
 
   const BasicBlock *Dest = TI->getSuccessor(SuccNum);
-  pred_const_iterator I = pred_begin(Dest), E = pred_end(Dest);
+  const_pred_iterator I = pred_begin(Dest), E = pred_end(Dest);
 
   // If there is more than one predecessor, this is a critical edge...
   assert(I != E && "No preds, but we have an edge to the block?");

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=99567&r1=99566&r2=99567&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Thu Mar 25 18:25:28 2010
@@ -1681,7 +1681,7 @@
     // Output predecessors for the block...
     Out.PadToColumn(50);
     Out << ";";
-    pred_const_iterator PI = pred_begin(BB), PE = pred_end(BB);
+    const_pred_iterator PI = pred_begin(BB), PE = pred_end(BB);
 
     if (PI == PE) {
       Out << " No predecessors!";




From stoklund at 2pi.dk  Thu Mar 25 18:30:41 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 25 Mar 2010 16:30:41 -0700
Subject: [llvm-commits] [llvm] r99400 - in /llvm/trunk:
	lib/CodeGen/LiveIntervalAnalysis.cpp
	test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
In-Reply-To: <20100324135036.CB2412A6C12C@llvm.org>
References: <20100324135036.CB2412A6C12C@llvm.org>
Message-ID: <2004E368-7E33-4932-8135-48B6F6F610A8@2pi.dk>


On Mar 24, 2010, at 6:50 AM, Torok Edwin wrote:

> Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=99400&r1=99399&r2=99400&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Mar 24 08:50:36 2010
> @@ -85,8 +85,10 @@
> void LiveIntervals::releaseMemory() {
>   // Free the live intervals themselves.
>   for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
> -       E = r2iMap_.end(); I != E; ++I)
> +       E = r2iMap_.end(); I != E; ++I) {
> +    I->second->clear();
>     delete I->second;
> +  }
> 
>   r2iMap_.clear();

I think LiveInterval::clear is broken. I calls VNI->~VNInfo(), but those VNIs can be referenced from multiple intervals.

/jakob




From evan.cheng at apple.com  Thu Mar 25 18:32:02 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 16:32:02 -0700
Subject: [llvm-commits] [llvm] r99400 - in /llvm/trunk:
	lib/CodeGen/LiveIntervalAnalysis.cpp
	test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
In-Reply-To: <2004E368-7E33-4932-8135-48B6F6F610A8@2pi.dk>
References: <20100324135036.CB2412A6C12C@llvm.org>
	<2004E368-7E33-4932-8135-48B6F6F610A8@2pi.dk>
Message-ID: <FE5825EE-C18B-495A-A638-7BCC6BE0A49A@apple.com>


On Mar 25, 2010, at 4:30 PM, Jakob Stoklund Olesen wrote:

> 
> On Mar 24, 2010, at 6:50 AM, Torok Edwin wrote:
> 
>> Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=99400&r1=99399&r2=99400&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Mar 24 08:50:36 2010
>> @@ -85,8 +85,10 @@
>> void LiveIntervals::releaseMemory() {
>>  // Free the live intervals themselves.
>>  for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
>> -       E = r2iMap_.end(); I != E; ++I)
>> +       E = r2iMap_.end(); I != E; ++I) {
>> +    I->second->clear();
>>    delete I->second;
>> +  }
>> 
>>  r2iMap_.clear();
> 
> I think LiveInterval::clear is broken. I calls VNI->~VNInfo(), but those VNIs can be referenced from multiple intervals.

Really? Multiple liveinterval's or liverange's?

Evan

> 
> /jakob
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From grosbach at apple.com  Thu Mar 25 18:32:19 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 25 Mar 2010 23:32:19 -0000
Subject: [llvm-commits] [llvm] r99568 - in /llvm/trunk/lib/Target/ARM:
	ARM.td ARMSubtarget.cpp
Message-ID: <20100325233219.6EC262A6C12C@llvm.org>

Author: grosbach
Date: Thu Mar 25 18:32:19 2010
New Revision: 99568

URL: http://llvm.org/viewvc/llvm-project?rev=99568&view=rev
Log:
switch the flag for using NEON for SP floating point to a subtarget 'feature'

Modified:
    llvm/trunk/lib/Target/ARM/ARM.td
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=99568&r1=99567&r2=99568&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Thu Mar 25 18:32:19 2010
@@ -49,8 +49,14 @@
 // FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
 // others as well. We should do more benchmarking and confirm one way or
 // the other.
-def HasSlowVMLx   : SubtargetFeature<"vmlx", "SlowVMLx", "true",
-                                     "Disable VFP MAC instructions">;
+def FeatureHasSlowVMLx   : SubtargetFeature<"vmlx", "SlowVMLx", "true",
+                                            "Disable VFP MAC instructions">;
+// Some processors benefit from using NEON instructions for scalar
+// single-precision FP operations.
+def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
+                                        "true",
+                                        "Use NEON for single precision FP">;
+
 
 //===----------------------------------------------------------------------===//
 // ARM Processors supported.
@@ -115,7 +121,8 @@
 
 // V7 Processors.
 def : Processor<"cortex-a8",        CortexA8Itineraries,
-                [ArchV7A, FeatureThumb2, FeatureNEON, HasSlowVMLx]>;
+                [ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx,
+                 FeatureNEONForFP]>;
 def : ProcNoItin<"cortex-a9",       [ArchV7A, FeatureThumb2, FeatureNEON]>;
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=99568&r1=99567&r2=99568&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Mar 25 18:32:19 2010
@@ -22,10 +22,6 @@
 static cl::opt<bool>
 ReserveR9("arm-reserve-r9", cl::Hidden,
           cl::desc("Reserve R9, making it unavailable as GPR"));
-static cl::opt<bool>
-UseNEONFP("arm-use-neon-fp",
-          cl::desc("Use NEON for single-precision FP"),
-          cl::init(false), cl::Hidden);
 
 static cl::opt<bool>
 UseMOVT("arm-use-movt",
@@ -35,7 +31,7 @@
                            bool isT)
   : ARMArchVersion(V4)
   , ARMFPUType(None)
-  , UseNEONForSinglePrecisionFP(UseNEONFP)
+  , UseNEONForSinglePrecisionFP(false)
   , SlowVMLx(false)
   , IsThumb(isT)
   , ThumbMode(Thumb1)
@@ -116,14 +112,6 @@
 
   if (!isThumb() || hasThumb2())
     PostRAScheduler = true;
-
-  // Set CPU specific features.
-  if (CPUString == "cortex-a8") {
-    // On Cortex-a8, it's faster to perform some single-precision FP
-    // operations with NEON instructions.
-    if (UseNEONFP.getPosition() == 0)
-      UseNEONForSinglePrecisionFP = true;
-  }
 }
 
 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.




From grosbach at apple.com  Thu Mar 25 18:34:05 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 25 Mar 2010 23:34:05 -0000
Subject: [llvm-commits] [llvm] r99569 - in /llvm/trunk/lib/Target/ARM:
	ARM.td ARMSubtarget.cpp
Message-ID: <20100325233405.B1F982A6C12C@llvm.org>

Author: grosbach
Date: Thu Mar 25 18:34:05 2010
New Revision: 99569

URL: http://llvm.org/viewvc/llvm-project?rev=99569&view=rev
Log:
need to fix 'make check' tests first. revert for a moment.

Modified:
    llvm/trunk/lib/Target/ARM/ARM.td
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=99569&r1=99568&r2=99569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Thu Mar 25 18:34:05 2010
@@ -49,14 +49,8 @@
 // FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
 // others as well. We should do more benchmarking and confirm one way or
 // the other.
-def FeatureHasSlowVMLx   : SubtargetFeature<"vmlx", "SlowVMLx", "true",
-                                            "Disable VFP MAC instructions">;
-// Some processors benefit from using NEON instructions for scalar
-// single-precision FP operations.
-def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
-                                        "true",
-                                        "Use NEON for single precision FP">;
-
+def HasSlowVMLx   : SubtargetFeature<"vmlx", "SlowVMLx", "true",
+                                     "Disable VFP MAC instructions">;
 
 //===----------------------------------------------------------------------===//
 // ARM Processors supported.
@@ -121,8 +115,7 @@
 
 // V7 Processors.
 def : Processor<"cortex-a8",        CortexA8Itineraries,
-                [ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx,
-                 FeatureNEONForFP]>;
+                [ArchV7A, FeatureThumb2, FeatureNEON, HasSlowVMLx]>;
 def : ProcNoItin<"cortex-a9",       [ArchV7A, FeatureThumb2, FeatureNEON]>;
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=99569&r1=99568&r2=99569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Mar 25 18:34:05 2010
@@ -22,6 +22,10 @@
 static cl::opt<bool>
 ReserveR9("arm-reserve-r9", cl::Hidden,
           cl::desc("Reserve R9, making it unavailable as GPR"));
+static cl::opt<bool>
+UseNEONFP("arm-use-neon-fp",
+          cl::desc("Use NEON for single-precision FP"),
+          cl::init(false), cl::Hidden);
 
 static cl::opt<bool>
 UseMOVT("arm-use-movt",
@@ -31,7 +35,7 @@
                            bool isT)
   : ARMArchVersion(V4)
   , ARMFPUType(None)
-  , UseNEONForSinglePrecisionFP(false)
+  , UseNEONForSinglePrecisionFP(UseNEONFP)
   , SlowVMLx(false)
   , IsThumb(isT)
   , ThumbMode(Thumb1)
@@ -112,6 +116,14 @@
 
   if (!isThumb() || hasThumb2())
     PostRAScheduler = true;
+
+  // Set CPU specific features.
+  if (CPUString == "cortex-a8") {
+    // On Cortex-a8, it's faster to perform some single-precision FP
+    // operations with NEON instructions.
+    if (UseNEONFP.getPosition() == 0)
+      UseNEONForSinglePrecisionFP = true;
+  }
 }
 
 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.




From stoklund at 2pi.dk  Thu Mar 25 18:39:37 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 25 Mar 2010 16:39:37 -0700
Subject: [llvm-commits] [llvm] r99400 - in /llvm/trunk:
	lib/CodeGen/LiveIntervalAnalysis.cpp
	test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
In-Reply-To: <FE5825EE-C18B-495A-A638-7BCC6BE0A49A@apple.com>
References: <20100324135036.CB2412A6C12C@llvm.org>
	<2004E368-7E33-4932-8135-48B6F6F610A8@2pi.dk>
	<FE5825EE-C18B-495A-A638-7BCC6BE0A49A@apple.com>
Message-ID: <0BB4DEE1-61E1-4B17-AA3E-2AA9255990F0@2pi.dk>


On Mar 25, 2010, at 4:32 PM, Evan Cheng wrote:

> 
> On Mar 25, 2010, at 4:30 PM, Jakob Stoklund Olesen wrote:
> 
>> 
>> On Mar 24, 2010, at 6:50 AM, Torok Edwin wrote:
>> 
>>> Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=99400&r1=99399&r2=99400&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Mar 24 08:50:36 2010
>>> @@ -85,8 +85,10 @@
>>> void LiveIntervals::releaseMemory() {
>>> // Free the live intervals themselves.
>>> for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
>>> -       E = r2iMap_.end(); I != E; ++I)
>>> +       E = r2iMap_.end(); I != E; ++I) {
>>> +    I->second->clear();
>>>   delete I->second;
>>> +  }
>>> 
>>> r2iMap_.clear();
>> 
>> I think LiveInterval::clear is broken. I calls VNI->~VNInfo(), but those VNIs can be referenced from multiple intervals.
> 
> Really? Multiple liveinterval's or liverange's?

LiveIntervals.

Is a VNI supposed to belong to only one LiveInterval? I don't know any concrete examples where that is not the case, but a lot of funny stuff is going on when coalescing.

/jakob




From grosbach at apple.com  Thu Mar 25 18:47:35 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 25 Mar 2010 23:47:35 -0000
Subject: [llvm-commits] [llvm] r99570 - in /llvm/trunk: lib/Target/ARM/
 test/CodeGen/ARM/ test/CodeGen/Thumb2/
Message-ID: <20100325234735.2ED642A6C12C@llvm.org>

Author: grosbach
Date: Thu Mar 25 18:47:34 2010
New Revision: 99570

URL: http://llvm.org/viewvc/llvm-project?rev=99570&view=rev
Log:
switch the flag for using NEON for SP floating point to a subtarget 'feature'.

Re-commit. This time complete with testsuite updates.

Modified:
    llvm/trunk/lib/Target/ARM/ARM.td
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
    llvm/trunk/test/CodeGen/ARM/fabss.ll
    llvm/trunk/test/CodeGen/ARM/fadds.ll
    llvm/trunk/test/CodeGen/ARM/fdivs.ll
    llvm/trunk/test/CodeGen/ARM/fmacs.ll
    llvm/trunk/test/CodeGen/ARM/fmscs.ll
    llvm/trunk/test/CodeGen/ARM/fmuls.ll
    llvm/trunk/test/CodeGen/ARM/fnegs.ll
    llvm/trunk/test/CodeGen/ARM/fnmacs.ll
    llvm/trunk/test/CodeGen/ARM/fnmscs.ll
    llvm/trunk/test/CodeGen/ARM/fp_convert.ll
    llvm/trunk/test/CodeGen/ARM/fsubs.ll
    llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll
    llvm/trunk/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll
    llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll
    llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll
    llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll
    llvm/trunk/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll

Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Thu Mar 25 18:47:34 2010
@@ -49,8 +49,14 @@
 // FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
 // others as well. We should do more benchmarking and confirm one way or
 // the other.
-def HasSlowVMLx   : SubtargetFeature<"vmlx", "SlowVMLx", "true",
-                                     "Disable VFP MAC instructions">;
+def FeatureHasSlowVMLx   : SubtargetFeature<"vmlx", "SlowVMLx", "true",
+                                            "Disable VFP MAC instructions">;
+// Some processors benefit from using NEON instructions for scalar
+// single-precision FP operations.
+def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
+                                        "true",
+                                        "Use NEON for single precision FP">;
+
 
 //===----------------------------------------------------------------------===//
 // ARM Processors supported.
@@ -115,7 +121,8 @@
 
 // V7 Processors.
 def : Processor<"cortex-a8",        CortexA8Itineraries,
-                [ArchV7A, FeatureThumb2, FeatureNEON, HasSlowVMLx]>;
+                [ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx,
+                 FeatureNEONForFP]>;
 def : ProcNoItin<"cortex-a9",       [ArchV7A, FeatureThumb2, FeatureNEON]>;
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Mar 25 18:47:34 2010
@@ -22,10 +22,6 @@
 static cl::opt<bool>
 ReserveR9("arm-reserve-r9", cl::Hidden,
           cl::desc("Reserve R9, making it unavailable as GPR"));
-static cl::opt<bool>
-UseNEONFP("arm-use-neon-fp",
-          cl::desc("Use NEON for single-precision FP"),
-          cl::init(false), cl::Hidden);
 
 static cl::opt<bool>
 UseMOVT("arm-use-movt",
@@ -35,7 +31,7 @@
                            bool isT)
   : ARMArchVersion(V4)
   , ARMFPUType(None)
-  , UseNEONForSinglePrecisionFP(UseNEONFP)
+  , UseNEONForSinglePrecisionFP(false)
   , SlowVMLx(false)
   , IsThumb(isT)
   , ThumbMode(Thumb1)
@@ -116,14 +112,6 @@
 
   if (!isThumb() || hasThumb2())
     PostRAScheduler = true;
-
-  // Set CPU specific features.
-  if (CPUString == "cortex-a8") {
-    // On Cortex-a8, it's faster to perform some single-precision FP
-    // operations with NEON instructions.
-    if (UseNEONFP.getPosition() == 0)
-      UseNEONForSinglePrecisionFP = true;
-  }
 }
 
 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.

Modified: llvm/trunk/test/CodeGen/ARM/fabss.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fabss.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fabss.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fabss.ll Thu Mar 25 18:47:34 2010
@@ -1,6 +1,5 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
 

Modified: llvm/trunk/test/CodeGen/ARM/fadds.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fadds.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fadds.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fadds.ll Thu Mar 25 18:47:34 2010
@@ -1,6 +1,5 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
 

Modified: llvm/trunk/test/CodeGen/ARM/fdivs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fdivs.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fdivs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fdivs.ll Thu Mar 25 18:47:34 2010
@@ -1,6 +1,5 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
 

Modified: llvm/trunk/test/CodeGen/ARM/fmacs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fmacs.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fmacs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fmacs.ll Thu Mar 25 18:47:34 2010
@@ -1,6 +1,5 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
 

Modified: llvm/trunk/test/CodeGen/ARM/fmscs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fmscs.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fmscs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fmscs.ll Thu Mar 25 18:47:34 2010
@@ -1,6 +1,5 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
 

Modified: llvm/trunk/test/CodeGen/ARM/fmuls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fmuls.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fmuls.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fmuls.ll Thu Mar 25 18:47:34 2010
@@ -1,6 +1,5 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
 

Modified: llvm/trunk/test/CodeGen/ARM/fnegs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fnegs.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fnegs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fnegs.ll Thu Mar 25 18:47:34 2010
@@ -1,6 +1,5 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
 

Modified: llvm/trunk/test/CodeGen/ARM/fnmacs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fnmacs.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fnmacs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fnmacs.ll Thu Mar 25 18:47:34 2010
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NEON
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NEONFP
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEONFP
 
 define float @test(float %acc, float %a, float %b) {
 entry:

Modified: llvm/trunk/test/CodeGen/ARM/fnmscs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fnmscs.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fnmscs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fnmscs.ll Thu Mar 25 18:47:34 2010
@@ -1,6 +1,5 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
 

Modified: llvm/trunk/test/CodeGen/ARM/fp_convert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp_convert.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp_convert.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fp_convert.ll Thu Mar 25 18:47:34 2010
@@ -1,6 +1,5 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NEON
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=VFP2
 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON
 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2
 

Modified: llvm/trunk/test/CodeGen/ARM/fsubs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fsubs.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fsubs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fsubs.ll Thu Mar 25 18:47:34 2010
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NFP1
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
 
 define float @test(float %a, float %b) {
 entry:

Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll Thu Mar 25 18:47:34 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+neon -arm-use-neon-fp -relocation-model=pic -disable-fp-elim
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim
 
 	type { %struct.GAP }		; type %0
 	type { i16, i8, i8 }		; type %1

Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll Thu Mar 25 18:47:34 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+neon -arm-use-neon-fp -relocation-model=pic -disable-fp-elim -O3
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim -O3
 
 	type { i16, i8, i8 }		; type %0
 	type { [2 x i32], [2 x i32] }		; type %1

Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll Thu Mar 25 18:47:34 2010
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp 
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp | not grep fcpys
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | not grep fcpys
 ; rdar://7117307
 
 	%struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }

Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll Thu Mar 25 18:47:34 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8
 ; rdar://7117307
 
 	%struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }

Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll Thu Mar 25 18:47:34 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8
 ; rdar://7117307
 
 	%struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }

Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll?rev=99570&r1=99569&r2=99570&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll Thu Mar 25 18:47:34 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 -arm-use-neon-fp
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8
 
 	%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
 	%struct.JHUFF_TBL = type { [17 x i8], [256 x i8], i32 }




From evan.cheng at apple.com  Thu Mar 25 18:48:32 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 16:48:32 -0700
Subject: [llvm-commits] [llvm] r99400 - in /llvm/trunk:
	lib/CodeGen/LiveIntervalAnalysis.cpp
	test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
In-Reply-To: <0BB4DEE1-61E1-4B17-AA3E-2AA9255990F0@2pi.dk>
References: <20100324135036.CB2412A6C12C@llvm.org>
	<2004E368-7E33-4932-8135-48B6F6F610A8@2pi.dk>
	<FE5825EE-C18B-495A-A638-7BCC6BE0A49A@apple.com>
	<0BB4DEE1-61E1-4B17-AA3E-2AA9255990F0@2pi.dk>
Message-ID: <02E03C07-91C5-42C0-9A14-BCAAF154F997@apple.com>


On Mar 25, 2010, at 4:39 PM, Jakob Stoklund Olesen wrote:

> 
> On Mar 25, 2010, at 4:32 PM, Evan Cheng wrote:
> 
>> 
>> On Mar 25, 2010, at 4:30 PM, Jakob Stoklund Olesen wrote:
>> 
>>> 
>>> On Mar 24, 2010, at 6:50 AM, Torok Edwin wrote:
>>> 
>>>> Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=99400&r1=99399&r2=99400&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
>>>> +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Mar 24 08:50:36 2010
>>>> @@ -85,8 +85,10 @@
>>>> void LiveIntervals::releaseMemory() {
>>>> // Free the live intervals themselves.
>>>> for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
>>>> -       E = r2iMap_.end(); I != E; ++I)
>>>> +       E = r2iMap_.end(); I != E; ++I) {
>>>> +    I->second->clear();
>>>>  delete I->second;
>>>> +  }
>>>> 
>>>> r2iMap_.clear();
>>> 
>>> I think LiveInterval::clear is broken. I calls VNI->~VNInfo(), but those VNIs can be referenced from multiple intervals.
>> 
>> Really? Multiple liveinterval's or liverange's?
> 
> LiveIntervals.
> 
> Is a VNI supposed to belong to only one LiveInterval? I don't know any concrete examples where that is not the case, but a lot of funny stuff is going on when coalescing.

I don't think VNI should be shared between liveinterval's. It may be shared temporarily during coalescing though. Either way, VNI are all bump allocated so the dtor should not be called?

Evan

> 
> /jakob
> 




From grosbach at apple.com  Thu Mar 25 18:51:29 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 25 Mar 2010 16:51:29 -0700
Subject: [llvm-commits] [llvm] r99549 -
	/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
In-Reply-To: <D40B996F-DED0-4E53-83A4-0AD2DA41D8E7@apple.com>
References: <20100325204850.67EC12A6C12C@llvm.org>
	<F96FCB46-CF02-4369-8B01-84CED349E913@apple.com>
	<2AC1E04B-5548-42B3-9B56-5300FA1630C7@apple.com>
	<D7EBFA92-E862-419A-802C-D18AFCC53A31@apple.com>
	<07095A46-8225-4A34-8578-9B3051E3B366@apple.com>
	<D40B996F-DED0-4E53-83A4-0AD2DA41D8E7@apple.com>
Message-ID: <F2E0546F-2BA5-4101-8EA8-22075437980B@apple.com>


On Mar 25, 2010, at 4:20 PM, Evan Cheng wrote:

> 
> On Mar 25, 2010, at 4:13 PM, Jim Grosbach wrote:
> 
>> 
>> On Mar 25, 2010, at 3:43 PM, Evan Cheng wrote:
>> 
>>> 
>>> On Mar 25, 2010, at 1:57 PM, Jim Grosbach wrote:
>>> 
>>>> I'll look at the x86 stuff and see if there's a better approach that'll work here. Thanks for the pointer. I agree having the conditional like this is a bit "eww."
>>>> 
>>>> That said, I went with this for two reasons: it's consistent with what we already do for the NEON-for-scalar-math flag, and we only want to disable the instructions for specific CPUs (cortex-a8 for now), not whole architecture variants, and as far as I know, the CPUString flag is the only place we have that information.
>>> 
>>> You can specify features for individual cpu's. I think that's a cleaner way to go about it.
>>> 
>> 
>> Done in r99565. Great suggestion. I like that a lot better.
>> 
>> Should we do the same for the UseNEONForSinglePrecisionFP flag, do you think?
> 
> Yes, I think so. Thanks.

Sounds good. Done in 99570.



>>>> 
>>>> On Mar 25, 2010, at 1:54 PM, Evan Cheng wrote:
>>>> 
>>>>> Thanks Jim. But perhaps this can be a subtarget feature specified in ARM.td? For example, x86 has FeatureSlowBTMem which disables uses of certain instructions for specific variants.
>>>>> 
>>>>> Evan
>>>>> 
>>>>> On Mar 25, 2010, at 1:48 PM, Jim Grosbach wrote:
>>>>> 
>>>>>> Author: grosbach
>>>>>> Date: Thu Mar 25 15:48:50 2010
>>>>>> New Revision: 99549
>>>>>> 
>>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=99549&view=rev
>>>>>> Log:
>>>>>> ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu
>>>>>> 
>>>>>> Modified:
>>>>>> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>>>>>> 
>>>>>> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=99549&r1=99548&r2=99549&view=diff
>>>>>> ==============================================================================
>>>>>> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
>>>>>> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Mar 25 15:48:50 2010
>>>>>> @@ -127,6 +127,12 @@
>>>>>> // operations with NEON instructions.
>>>>>> if (UseNEONFP.getPosition() == 0)
>>>>>>  UseNEONForSinglePrecisionFP = true;
>>>>>> +    // The VFP vlma and vlms instructions don't play nicely with others;
>>>>>> +    // disable them.
>>>>>> +    // FIXME: This may be true for other variants as well. Get benchmark
>>>>>> +    // numbers and add them if determined that's the case.
>>>>>> +    if (UseVMLxInstructions.getPosition() == 0)
>>>>>> +      UseVMLx = false;
>>>>>> }
>>>>>> }
>>>>>> 
>>>>>> 
>>>>>> 
>>>>>> _______________________________________________
>>>>>> llvm-commits mailing list
>>>>>> llvm-commits at cs.uiuc.edu
>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>> 
>>>> 
>>> 
>> 
> 




From dalej at apple.com  Thu Mar 25 19:02:44 2010
From: dalej at apple.com (Dale Johannesen)
Date: Fri, 26 Mar 2010 00:02:44 -0000
Subject: [llvm-commits] [llvm] r99573 -
	/llvm/trunk/lib/CodeGen/OptimizeExts.cpp
Message-ID: <20100326000244.451342A6C12C@llvm.org>

Author: johannes
Date: Thu Mar 25 19:02:44 2010
New Revision: 99573

URL: http://llvm.org/viewvc/llvm-project?rev=99573&view=rev
Log:
Handle DEBUG_VALUE in this pass.


Modified:
    llvm/trunk/lib/CodeGen/OptimizeExts.cpp

Modified: llvm/trunk/lib/CodeGen/OptimizeExts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/OptimizeExts.cpp?rev=99573&r1=99572&r2=99573&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/OptimizeExts.cpp (original)
+++ llvm/trunk/lib/CodeGen/OptimizeExts.cpp Thu Mar 25 19:02:44 2010
@@ -73,6 +73,9 @@
 /// the source, and if the source value is preserved as a sub-register of
 /// the result, then replace all reachable uses of the source with the subreg
 /// of the result.
+/// Do not generate an EXTRACT that is used only in a debug use, as this
+/// changes the code.  Since this code does not currently share EXTRACTs, just
+/// ignore all debug uses.
 bool OptimizeExts::OptimizeInstr(MachineInstr *MI, MachineBasicBlock *MBB,
                                  SmallPtrSet<MachineInstr*, 8> &LocalMIs) {
   bool Changed = false;
@@ -84,17 +87,17 @@
         TargetRegisterInfo::isPhysicalRegister(SrcReg))
       return false;
 
-    MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg);
-    if (++UI == MRI->use_end())
+    MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(SrcReg);
+    if (++UI == MRI->use_nodbg_end())
       // No other uses.
       return false;
 
     // Ok, the source has other uses. See if we can replace the other uses
     // with use of the result of the extension.
     SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
-    UI = MRI->use_begin(DstReg);
-    for (MachineRegisterInfo::use_iterator UE = MRI->use_end(); UI != UE;
-         ++UI)
+    UI = MRI->use_nodbg_begin(DstReg);
+    for (MachineRegisterInfo::use_nodbg_iterator UE = MRI->use_nodbg_end();
+         UI != UE; ++UI)
       ReachedBBs.insert(UI->getParent());
 
     bool ExtendLife = true;
@@ -103,9 +106,9 @@
     // Uses that the result of the instruction can reach.
     SmallVector<MachineOperand*, 8> ExtendedUses;
 
-    UI = MRI->use_begin(SrcReg);
-    for (MachineRegisterInfo::use_iterator UE = MRI->use_end(); UI != UE;
-         ++UI) {
+    UI = MRI->use_nodbg_begin(SrcReg);
+    for (MachineRegisterInfo::use_nodbg_iterator UE = MRI->use_nodbg_end();
+         UI != UE; ++UI) {
       MachineOperand &UseMO = UI.getOperand();
       MachineInstr *UseMI = &*UI;
       if (UseMI == MI)
@@ -147,9 +150,9 @@
       // Look for PHI uses of the extended result, we don't want to extend the
       // liveness of a PHI input. It breaks all kinds of assumptions down
       // stream. A PHI use is expected to be the kill of its source values.
-      UI = MRI->use_begin(DstReg);
-      for (MachineRegisterInfo::use_iterator UE = MRI->use_end(); UI != UE;
-           ++UI)
+      UI = MRI->use_nodbg_begin(DstReg);
+      for (MachineRegisterInfo::use_nodbg_iterator UE = MRI->use_nodbg_end();
+           UI != UE; ++UI)
         if (UI->isPHI())
           PHIBBs.insert(UI->getParent());
 




From evan.cheng at apple.com  Thu Mar 25 19:07:26 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 26 Mar 2010 00:07:26 -0000
Subject: [llvm-commits] [llvm] r99575 - in /llvm/trunk:
 lib/CodeGen/SimpleRegisterCoalescing.cpp
 test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
 test/CodeGen/X86/phys_subreg_coalesce-2.ll test/CodeGen/X86/pr2659.ll
Message-ID: <20100326000726.10DA02A6C12C@llvm.org>

Author: evancheng
Date: Thu Mar 25 19:07:25 2010
New Revision: 99575

URL: http://llvm.org/viewvc/llvm-project?rev=99575&view=rev
Log:
Try trivial remat before the coalescer gives up on a vr / physreg coalescing for fear of tying up a physical register.

Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
    llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
    llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll
    llvm/trunk/test/CodeGen/X86/pr2659.ll

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=99575&r1=99574&r2=99575&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Mar 25 19:07:25 2010
@@ -1664,7 +1664,8 @@
       if (JoinPInt.ranges.size() > 1000) {
         mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
         ++numAborts;
-        DEBUG(dbgs() << "\tPhysical register too complicated, abort!\n");
+        DEBUG(dbgs()
+              << "\tPhysical register live interval too complicated, abort!\n");
         return false;
       }
 
@@ -1675,6 +1676,11 @@
       if (Length > Threshold &&
           (((float)std::distance(mri_->use_nodbg_begin(JoinVReg),
                                  mri_->use_nodbg_end()) / Length) < Ratio)) {
+        // Before giving up coalescing, if definition of source is defined by
+        // trivial computation, try rematerializing it.
+        if (ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
+          return true;
+
         mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
         ++numAborts;
         DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");

Modified: llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll?rev=99575&r1=99574&r2=99575&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll Thu Mar 25 19:07:25 2010
@@ -1,5 +1,7 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& grep {2 machine-licm}
+; RUN: llc < %s -march=x86-64 -mattr=+sse3 | FileCheck %s
 ; rdar://6627786
+; rdar://7792037
 
 target triple = "x86_64-apple-darwin10.0"
 	%struct.Key = type { i64 }
@@ -11,6 +13,13 @@
 	br label %bb4
 
 bb4:		; preds = %bb.i, %bb26, %bb4, %entry
+; CHECK: %bb4
+; CHECK: xorb
+; CHECK: callq
+; CHECK: movq
+; CHECK: xorl
+; CHECK: xorb
+
 	%0 = call i32 (...)* @xxGetOffsetForCode(i32 undef) nounwind		; <i32> [#uses=0]
 	%ins = or i64 %p, 2097152		; <i64> [#uses=1]
 	%1 = call i32 (...)* @xxCalculateMidType(%struct.Key* %desc, i32 0) nounwind		; <i32> [#uses=1]

Modified: llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll?rev=99575&r1=99574&r2=99575&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll Thu Mar 25 19:07:25 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | grep mov | count 6
+; RUN: llc < %s -march=x86 | grep mov | count 5
 ; PR2659
 
 define i32 @binomial(i32 %n, i32 %k) nounwind {

Modified: llvm/trunk/test/CodeGen/X86/pr2659.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr2659.ll?rev=99575&r1=99574&r2=99575&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr2659.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr2659.ll Thu Mar 25 19:07:25 2010
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 6
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 5
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | FileCheck %s
 ; PR2659
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
@@ -13,6 +14,11 @@
   %cmp44 = icmp eq i32 %k, 0            ; <i1> [#uses=1]
   br i1 %cmp44, label %afterfor, label %forbody
 
+; CHECK: %forcond.preheader.forbody_crit_edge
+; CHECK: movl $1
+; CHECK-NOT: xorl
+; CHECK-NEXT: movl $1
+
 ifthen:         ; preds = %entry
   ret i32 0
 




From stoklund at 2pi.dk  Thu Mar 25 19:29:54 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 25 Mar 2010 17:29:54 -0700
Subject: [llvm-commits] [llvm] r99400 - in /llvm/trunk:
	lib/CodeGen/LiveIntervalAnalysis.cpp
	test/CodeGen/Generic/2010-03-24-liveintervalleak.ll
In-Reply-To: <02E03C07-91C5-42C0-9A14-BCAAF154F997@apple.com>
References: <20100324135036.CB2412A6C12C@llvm.org>
	<2004E368-7E33-4932-8135-48B6F6F610A8@2pi.dk>
	<FE5825EE-C18B-495A-A638-7BCC6BE0A49A@apple.com>
	<0BB4DEE1-61E1-4B17-AA3E-2AA9255990F0@2pi.dk>
	<02E03C07-91C5-42C0-9A14-BCAAF154F997@apple.com>
Message-ID: <DE870BBD-C192-42BC-AAB5-BFB2A0775E6B@2pi.dk>


On Mar 25, 2010, at 4:48 PM, Evan Cheng wrote:

> 
> On Mar 25, 2010, at 4:39 PM, Jakob Stoklund Olesen wrote:
> 
>> 
>> On Mar 25, 2010, at 4:32 PM, Evan Cheng wrote:
>> 
>>> 
>>> On Mar 25, 2010, at 4:30 PM, Jakob Stoklund Olesen wrote:
>>> 
>>>> 
>>>> On Mar 24, 2010, at 6:50 AM, Torok Edwin wrote:
>>>> 
>>>>> Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=99400&r1=99399&r2=99400&view=diff
>>>>> ==============================================================================
>>>>> --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
>>>>> +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Mar 24 08:50:36 2010
>>>>> @@ -85,8 +85,10 @@
>>>>> void LiveIntervals::releaseMemory() {
>>>>> // Free the live intervals themselves.
>>>>> for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
>>>>> -       E = r2iMap_.end(); I != E; ++I)
>>>>> +       E = r2iMap_.end(); I != E; ++I) {
>>>>> +    I->second->clear();
>>>>> delete I->second;
>>>>> +  }
>>>>> 
>>>>> r2iMap_.clear();
>>>> 
>>>> I think LiveInterval::clear is broken. I calls VNI->~VNInfo(), but those VNIs can be referenced from multiple intervals.
>>> 
>>> Really? Multiple liveinterval's or liverange's?
>> 
>> LiveIntervals.
>> 
>> Is a VNI supposed to belong to only one LiveInterval? I don't know any concrete examples where that is not the case, but a lot of funny stuff is going on when coalescing.
> 
> I don't think VNI should be shared between liveinterval's. It may be shared temporarily during coalescing though.

Let's call it a bug. In that case, clear() is fine, but a VNI is accidentally shared somewhere.

>  Either way, VNI are all bump allocated so the dtor should not be called?

Yeah, but they contain a SmallVector that leaks if it is not destroyed.

/jakob




From gohman at apple.com  Thu Mar 25 19:33:27 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 26 Mar 2010 00:33:27 -0000
Subject: [llvm-commits] [llvm] r99580 -
	/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Message-ID: <20100326003327.D40F22A6C12C@llvm.org>

Author: djg
Date: Thu Mar 25 19:33:27 2010
New Revision: 99580

URL: http://llvm.org/viewvc/llvm-project?rev=99580&view=rev
Log:
Ignore debug intrinsics in yet more places.

Modified:
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=99580&r1=99579&r2=99580&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Thu Mar 25 19:33:27 2010
@@ -2827,6 +2827,7 @@
       IP = Tentative;
   }
   while (isa<PHINode>(IP)) ++IP;
+  while (isa<DbgInfoIntrinsic>(IP)) ++IP;
 
   // Inform the Rewriter if we have a post-increment use, so that it can
   // perform an advantageous expansion.
@@ -2864,8 +2865,10 @@
         // so that it is dominated by its operand. If the original insert point
         // was already dominated by the increment, keep it, because there may
         // be loop-variant operands that need to be respected also.
-        if (L->contains(LF.UserInst) && !DT.dominates(IVIncInsertPos, IP))
+        if (L->contains(LF.UserInst) && !DT.dominates(IVIncInsertPos, IP)) {
           IP = IVIncInsertPos;
+          while (isa<DbgInfoIntrinsic>(IP)) ++IP;
+        }
         break;
       }
       Start = AR->getStart();




From jyasskin at google.com  Thu Mar 25 19:59:12 2010
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Fri, 26 Mar 2010 00:59:12 -0000
Subject: [llvm-commits] [llvm] r99589 -
	/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
Message-ID: <20100326005912.E2E832A6C12C@llvm.org>

Author: jyasskin
Date: Thu Mar 25 19:59:12 2010
New Revision: 99589

URL: http://llvm.org/viewvc/llvm-project?rev=99589&view=rev
Log:
Avoid leaking argv and env arrays from lli.

Modified:
    llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp

Modified: llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp?rev=99589&r1=99588&r2=99589&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/ExecutionEngine.cpp Thu Mar 25 19:59:12 2010
@@ -221,35 +221,55 @@
   return I != EEState.getGlobalAddressReverseMap(locked).end() ? I->second : 0;
 }
 
-// CreateArgv - Turn a vector of strings into a nice argv style array of
-// pointers to null terminated strings.
-//
-static void *CreateArgv(LLVMContext &C, ExecutionEngine *EE,
-                        const std::vector<std::string> &InputArgv) {
+namespace {
+class ArgvArray {
+  char *Array;
+  std::vector<char*> Values;
+public:
+  ArgvArray() : Array(NULL) {}
+  ~ArgvArray() { clear(); }
+  void clear() {
+    delete[] Array;
+    Array = NULL;
+    for (size_t I = 0, E = Values.size(); I != E; ++I) {
+      delete[] Values[I];
+    }
+    Values.clear();
+  }
+  /// Turn a vector of strings into a nice argv style array of pointers to null
+  /// terminated strings.
+  void *reset(LLVMContext &C, ExecutionEngine *EE,
+              const std::vector<std::string> &InputArgv);
+};
+}  // anonymous namespace
+void *ArgvArray::reset(LLVMContext &C, ExecutionEngine *EE,
+                       const std::vector<std::string> &InputArgv) {
+  clear();  // Free the old contents.
   unsigned PtrSize = EE->getTargetData()->getPointerSize();
-  char *Result = new char[(InputArgv.size()+1)*PtrSize];
+  Array = new char[(InputArgv.size()+1)*PtrSize];
 
-  DEBUG(dbgs() << "JIT: ARGV = " << (void*)Result << "\n");
+  DEBUG(dbgs() << "JIT: ARGV = " << (void*)Array << "\n");
   const Type *SBytePtr = Type::getInt8PtrTy(C);
 
   for (unsigned i = 0; i != InputArgv.size(); ++i) {
     unsigned Size = InputArgv[i].size()+1;
     char *Dest = new char[Size];
+    Values.push_back(Dest);
     DEBUG(dbgs() << "JIT: ARGV[" << i << "] = " << (void*)Dest << "\n");
 
     std::copy(InputArgv[i].begin(), InputArgv[i].end(), Dest);
     Dest[Size-1] = 0;
 
-    // Endian safe: Result[i] = (PointerTy)Dest;
-    EE->StoreValueToMemory(PTOGV(Dest), (GenericValue*)(Result+i*PtrSize),
+    // Endian safe: Array[i] = (PointerTy)Dest;
+    EE->StoreValueToMemory(PTOGV(Dest), (GenericValue*)(Array+i*PtrSize),
                            SBytePtr);
   }
 
   // Null terminate it
   EE->StoreValueToMemory(PTOGV(0),
-                         (GenericValue*)(Result+InputArgv.size()*PtrSize),
+                         (GenericValue*)(Array+InputArgv.size()*PtrSize),
                          SBytePtr);
-  return Result;
+  return Array;
 }
 
 
@@ -353,11 +373,13 @@
    llvm_report_error("Invalid number of arguments of main() supplied");
   }
   
+  ArgvArray CArgv;
+  ArgvArray CEnv;
   if (NumArgs) {
     GVArgs.push_back(GVArgc); // Arg #0 = argc.
     if (NumArgs > 1) {
       // Arg #1 = argv.
-      GVArgs.push_back(PTOGV(CreateArgv(Fn->getContext(), this, argv))); 
+      GVArgs.push_back(PTOGV(CArgv.reset(Fn->getContext(), this, argv)));
       assert(!isTargetNullPtr(this, GVTOP(GVArgs[1])) &&
              "argv[0] was null after CreateArgv");
       if (NumArgs > 2) {
@@ -365,7 +387,7 @@
         for (unsigned i = 0; envp[i]; ++i)
           EnvVars.push_back(envp[i]);
         // Arg #2 = envp.
-        GVArgs.push_back(PTOGV(CreateArgv(Fn->getContext(), this, EnvVars)));
+        GVArgs.push_back(PTOGV(CEnv.reset(Fn->getContext(), this, EnvVars)));
       }
     }
   }




From johnny.chen at apple.com  Thu Mar 25 20:07:59 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Fri, 26 Mar 2010 01:07:59 -0000
Subject: [llvm-commits] [llvm] r99590 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrNEON.td
Message-ID: <20100326010759.49EA52A6C12C@llvm.org>

Author: johnny
Date: Thu Mar 25 20:07:59 2010
New Revision: 99590

URL: http://llvm.org/viewvc/llvm-project?rev=99590&view=rev
Log:
Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field.  The Vd, Vm fields are interpreted
the same between the two, though.

See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99590&r1=99589&r2=99590&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Mar 25 20:07:59 2010
@@ -64,6 +64,8 @@
 def N2RegFrm       : Format<33>;
 def NVCVTFrm       : Format<34>;
 def NVDupLnFrm     : Format<35>;
+def N2RegVShLFrm   : Format<36>;
+def N2RegVShRFrm   : Format<37>;
 
 // Misc flags.
 

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99590&r1=99589&r2=99590&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Mar 25 20:07:59 2010
@@ -1302,17 +1302,17 @@
 // Shift by immediate,
 // both double- and quad-register.
 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
-             InstrItinClass itin, string OpcodeStr, string Dt,
+             Format f, InstrItinClass itin, string OpcodeStr, string Dt,
              ValueType Ty, SDNode OpNode>
   : N2VImm<op24, op23, op11_8, op7, 0, op4,
-           (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegFrm, itin,
+           (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
            OpcodeStr, Dt, "$dst, $src, $SIMM", "",
            [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
-             InstrItinClass itin, string OpcodeStr, string Dt,
+             Format f, InstrItinClass itin, string OpcodeStr, string Dt,
              ValueType Ty, SDNode OpNode>
   : N2VImm<op24, op23, op11_8, op7, 1, op4,
-           (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegFrm, itin,
+           (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
            OpcodeStr, Dt, "$dst, $src, $SIMM", "",
            [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
 
@@ -1321,7 +1321,7 @@
              string OpcodeStr, string Dt,
              ValueType ResTy, ValueType OpTy, SDNode OpNode>
   : N2VImm<op24, op23, op11_8, op7, op6, op4,
-           (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegFrm,
+           (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
            IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
            [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
                                           (i32 imm:$SIMM))))]>;
@@ -1331,7 +1331,7 @@
              InstrItinClass itin, string OpcodeStr, string Dt,
              ValueType ResTy, ValueType OpTy, SDNode OpNode>
   : N2VImm<op24, op23, op11_8, op7, op6, op4,
-           (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegFrm, itin,
+           (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
            OpcodeStr, Dt, "$dst, $src, $SIMM", "",
            [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
                                           (i32 imm:$SIMM))))]>;
@@ -1341,14 +1341,14 @@
 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
                 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
   : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
-           (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegFrm, IIC_VPALiD,
+           (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
            OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
            [(set DPR:$dst, (Ty (add DPR:$src1,
                                 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
                 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
   : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
-           (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegFrm, IIC_VPALiD,
+           (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
            OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
            [(set QPR:$dst, (Ty (add QPR:$src1,
                                 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
@@ -1356,15 +1356,15 @@
 // Shift by immediate and insert,
 // both double- and quad-register.
 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
-                string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
+                Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
   : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
-           (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegFrm, IIC_VSHLiD,
+           (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), f, IIC_VSHLiD,
            OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
            [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
-                string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
+                Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
   : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
-           (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegFrm, IIC_VSHLiQ,
+           (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), f, IIC_VSHLiQ,
            OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
            [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
 
@@ -1824,46 +1824,46 @@
 
 
 // Neon 2-register vector shift by immediate,
+//   with f of either N2RegVShLFrm or N2RegVShRFrm
 //   element sizes of 8, 16, 32 and 64 bits:
 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
-                      InstrItinClass itin, string OpcodeStr, string Dt,
-                      SDNode OpNode> {
+                     InstrItinClass itin, string OpcodeStr, string Dt,
+                     SDNode OpNode, Format f> {
   // 64-bit vector types.
-  def v8i8  : N2VDSh<op24, op23, op11_8, 0, op4, itin,
+  def v8i8  : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
                      OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
     let Inst{21-19} = 0b001; // imm6 = 001xxx
   }
-  def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
+  def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
                      OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
     let Inst{21-20} = 0b01;  // imm6 = 01xxxx
   }
-  def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
+  def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
                      OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
     let Inst{21} = 0b1;      // imm6 = 1xxxxx
   }
-  def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin,
+  def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
                      OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
                              // imm6 = xxxxxx
 
   // 128-bit vector types.
-  def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
+  def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
                      OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
     let Inst{21-19} = 0b001; // imm6 = 001xxx
   }
-  def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
+  def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
                      OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
     let Inst{21-20} = 0b01;  // imm6 = 01xxxx
   }
-  def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
+  def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
                      OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
     let Inst{21} = 0b1;      // imm6 = 1xxxxx
   }
-  def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin,
+  def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
                      OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
                              // imm6 = xxxxxx
 }
 
-
 // Neon Shift-Accumulate vector operations,
 //   element sizes of 8, 16, 32 and 64 bits:
 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
@@ -1905,41 +1905,43 @@
 
 
 // Neon Shift-Insert vector operations,
+//   with f of either N2RegVShLFrm or N2RegVShRFrm
 //   element sizes of 8, 16, 32 and 64 bits:
 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
-                         string OpcodeStr, SDNode ShOp> {
+                         string OpcodeStr, SDNode ShOp,
+                         Format f> {
   // 64-bit vector types.
   def v8i8  : N2VDShIns<op24, op23, op11_8, 0, op4,
-                        OpcodeStr, "8", v8i8, ShOp> {
+                        f, OpcodeStr, "8", v8i8, ShOp> {
     let Inst{21-19} = 0b001; // imm6 = 001xxx
   }
   def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
-                        OpcodeStr, "16", v4i16, ShOp> {
+                        f, OpcodeStr, "16", v4i16, ShOp> {
     let Inst{21-20} = 0b01;  // imm6 = 01xxxx
   }
   def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
-                        OpcodeStr, "32", v2i32, ShOp> {
+                        f, OpcodeStr, "32", v2i32, ShOp> {
     let Inst{21} = 0b1;      // imm6 = 1xxxxx
   }
   def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
-                        OpcodeStr, "64", v1i64, ShOp>;
+                        f, OpcodeStr, "64", v1i64, ShOp>;
                              // imm6 = xxxxxx
 
   // 128-bit vector types.
   def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
-                        OpcodeStr, "8", v16i8, ShOp> {
+                        f, OpcodeStr, "8", v16i8, ShOp> {
     let Inst{21-19} = 0b001; // imm6 = 001xxx
   }
   def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
-                        OpcodeStr, "16", v8i16, ShOp> {
+                        f, OpcodeStr, "16", v8i16, ShOp> {
     let Inst{21-20} = 0b01;  // imm6 = 01xxxx
   }
   def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
-                        OpcodeStr, "32", v4i32, ShOp> {
+                        f, OpcodeStr, "32", v4i32, ShOp> {
     let Inst{21} = 0b1;      // imm6 = 1xxxxx
   }
   def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
-                        OpcodeStr, "64", v2i64, ShOp>;
+                        f, OpcodeStr, "64", v2i64, ShOp>;
                              // imm6 = xxxxxx
 }
 
@@ -2578,10 +2580,13 @@
 defm VSHLu    : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
                             IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
 //   VSHL     : Vector Shift Left (Immediate)
-defm VSHLi    : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
+defm VSHLi    : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
+                           N2RegVShLFrm>;
 //   VSHR     : Vector Shift Right (Immediate)
-defm VSHRs    : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs>;
-defm VSHRu    : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru>;
+defm VSHRs    : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
+                           N2RegVShRFrm>;
+defm VSHRu    : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
+                           N2RegVShRFrm>;
 
 //   VSHLL    : Vector Shift Left Long
 defm VSHLLs   : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
@@ -2612,8 +2617,10 @@
 defm VRSHLu   : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
                             IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
 //   VRSHR    : Vector Rounding Shift Right
-defm VRSHRs   : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs>;
-defm VRSHRu   : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru>;
+defm VRSHRs   : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
+                           N2RegVShRFrm>;
+defm VRSHRu   : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
+                           N2RegVShRFrm>;
 
 //   VRSHRN   : Vector Rounding Shift Right and Narrow
 defm VRSHRN   : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
@@ -2625,10 +2632,13 @@
 defm VQSHLu   : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
                             IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
 //   VQSHL    : Vector Saturating Shift Left (Immediate)
-defm VQSHLsi  : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s", NEONvqshls>;
-defm VQSHLui  : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u", NEONvqshlu>;
+defm VQSHLsi  : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
+                           N2RegVShLFrm>;
+defm VQSHLui  : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
+                           N2RegVShLFrm>;
 //   VQSHLU   : Vector Saturating Shift Left (Immediate, Unsigned)
-defm VQSHLsu  : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D, "vqshlu","s",NEONvqshlsu>;
+defm VQSHLsu  : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
+                           N2RegVShLFrm>;
 
 //   VQSHRN   : Vector Saturating Shift Right and Narrow
 defm VQSHRNs  : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
@@ -2666,9 +2676,9 @@
 defm VRSRAu   : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
 
 //   VSLI     : Vector Shift Left and Insert
-defm VSLI     : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli>;
+defm VSLI     : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
 //   VSRI     : Vector Shift Right and Insert
-defm VSRI     : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri>;
+defm VSRI     : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
 
 // Vector Absolute and Saturating Absolute.
 




From echristo at apple.com  Thu Mar 25 20:22:34 2010
From: echristo at apple.com (Eric Christopher)
Date: Fri, 26 Mar 2010 01:22:34 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r99592 -
	/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp
Message-ID: <20100326012234.3B4812A6C12C@llvm.org>

Author: echristo
Date: Thu Mar 25 20:22:34 2010
New Revision: 99592

URL: http://llvm.org/viewvc/llvm-project?rev=99592&view=rev
Log:
Lower IX86_BUILTIN_PMULLD128 in the x86 backend to the simple multiplication
it is.

Modified:
    llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp

Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=99592&r1=99591&r2=99592&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Thu Mar 25 20:22:34 2010
@@ -80,6 +80,7 @@
   case IX86_BUILTIN_MULPD:
   case IX86_BUILTIN_PMULLW:
   case IX86_BUILTIN_PMULLW128:
+  case IX86_BUILTIN_PMULLD128:
     Result = Builder.CreateMul(Ops[0], Ops[1]);
     return true;
   case IX86_BUILTIN_DIVPS:




From echristo at apple.com  Thu Mar 25 20:28:01 2010
From: echristo at apple.com (Eric Christopher)
Date: Fri, 26 Mar 2010 01:28:01 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r99593 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <20100326012801.6BF3D2A6C12C@llvm.org>

Author: echristo
Date: Thu Mar 25 20:28:01 2010
New Revision: 99593

URL: http://llvm.org/viewvc/llvm-project?rev=99593&view=rev
Log:
Try to lower in the backend first, it may know what to do better for the
target.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=99593&r1=99592&r2=99593&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Mar 25 20:28:01 2010
@@ -4955,8 +4955,7 @@
 //                     ... Builtin Function Expansion ...
 //===----------------------------------------------------------------------===//
 
-/// EmitFrontendExpandedBuiltinCall - For MD builtins that do not have a
-/// directly corresponding LLVM intrinsic, we allow the target to do some amount
+/// EmitFrontendExpandedBuiltinCall - We allow the target to do some amount
 /// of lowering.  This allows us to avoid having intrinsics for operations that
 /// directly correspond to LLVM constructs.
 ///
@@ -5112,14 +5111,17 @@
 #ifdef LLVM_TARGET_INTRINSIC_PREFIX
       TargetPrefix = LLVM_TARGET_INTRINSIC_PREFIX;
 #endif
+      // If the backend has some special code to lower, go ahead and try to
+      // do that first.
+      if (EmitFrontendExpandedBuiltinCall(exp, fndecl, DestLoc, Result))
+        return true;
+      
       // If this builtin directly corresponds to an LLVM intrinsic, get the
       // IntrinsicID now.
       const char *BuiltinName = IDENTIFIER_POINTER(DECL_NAME(fndecl));
       Intrinsic::ID IntrinsicID =
         Intrinsic::getIntrinsicForGCCBuiltin(TargetPrefix, BuiltinName);
       if (IntrinsicID == Intrinsic::not_intrinsic) {
-        if (EmitFrontendExpandedBuiltinCall(exp, fndecl, DestLoc, Result))
-          return true;
 
         error("%Hunsupported target builtin %<%s%> used", &EXPR_LOCATION(exp),
               BuiltinName);




From evan.cheng at apple.com  Thu Mar 25 21:12:25 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 26 Mar 2010 02:12:25 -0000
Subject: [llvm-commits] [llvm] r99597 - in /llvm/trunk/lib/CodeGen:
 LiveVariables.cpp SelectionDAG/InstrEmitter.cpp
Message-ID: <20100326021225.1B8642A6C12C@llvm.org>

Author: evancheng
Date: Thu Mar 25 21:12:24 2010
New Revision: 99597

URL: http://llvm.org/viewvc/llvm-project?rev=99597&view=rev
Log:
LiveVariables should clear kill / dead markers first. This allows us to remove a hack in the scheduler.

Modified:
    llvm/trunk/lib/CodeGen/LiveVariables.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=99597&r1=99596&r2=99597&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Thu Mar 25 21:12:24 2010
@@ -556,17 +556,21 @@
       if (MI->isPHI())
         NumOperandsToProcess = 1;
 
+      // Clear kill and dead markers. LV will recompute them.
       SmallVector<unsigned, 4> UseRegs;
       SmallVector<unsigned, 4> DefRegs;
       for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
-        const MachineOperand &MO = MI->getOperand(i);
+        MachineOperand &MO = MI->getOperand(i);
         if (!MO.isReg() || MO.getReg() == 0)
           continue;
         unsigned MOReg = MO.getReg();
-        if (MO.isUse())
+        if (MO.isUse()) {
+          MO.setIsKill(false);
           UseRegs.push_back(MOReg);
-        if (MO.isDef())
+        } else /*MO.isDef()*/ {
+          MO.setIsDead(false);
           DefRegs.push_back(MOReg);
+        }
       }
 
       // Process all uses.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=99597&r1=99596&r2=99597&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Thu Mar 25 21:12:24 2010
@@ -640,9 +640,7 @@
   // If the instruction has implicit defs and the node doesn't, mark the
   // implicit def as dead.  If the node has any flag outputs, we don't do this
   // because we don't know what implicit defs are being used by flagged nodes.
-  if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag &&
-      // FIXME: This is a terrible hackaround for a liveintervals bug.
-      II.getNumImplicitDefs() < 8)
+  if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
     if (const unsigned *IDList = II.getImplicitDefs()) {
       for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs();
            i != e; ++i)




From evan.cheng at apple.com  Thu Mar 25 21:13:13 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 26 Mar 2010 02:13:13 -0000
Subject: [llvm-commits] [llvm] r99598 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/pic.ll
 test/CodeGen/X86/sibcall.ll test/CodeGen/X86/xor-icmp.ll
Message-ID: <20100326021313.E02D42A6C12C@llvm.org>

Author: evancheng
Date: Thu Mar 25 21:13:13 2010
New Revision: 99598

URL: http://llvm.org/viewvc/llvm-project?rev=99598&view=rev
Log:
Allow trivial sibcall of vararg callee when no arguments are being passed.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/pic.ll
    llvm/trunk/test/CodeGen/X86/sibcall.ll
    llvm/trunk/test/CodeGen/X86/xor-icmp.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=99598&r1=99597&r2=99598&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Mar 25 21:13:13 2010
@@ -2301,8 +2301,9 @@
   // Look for obvious safe cases to perform tail call optimization that does not
   // requite ABI changes. This is what gcc calls sibcall.
 
-  // Do not sibcall optimize vararg calls for now.
-  if (isVarArg)
+  // Do not sibcall optimize vararg calls unless the call site is not passing any
+  // arguments.
+  if (isVarArg && !Outs.empty())
     return false;
 
   // Also avoid sibcall optimization if either caller or callee uses struct

Modified: llvm/trunk/test/CodeGen/X86/pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pic.ll?rev=99598&r1=99597&r2=99598&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pic.ll Thu Mar 25 21:13:13 2010
@@ -194,10 +194,10 @@
 
 ; LINUX: .LJTI8_0:
 ; LINUX:   .long	 .LBB8_2 at GOTOFF
-; LINUX:   .long	 .LBB8_2 at GOTOFF
-; LINUX:   .long	 .LBB8_7 at GOTOFF
-; LINUX:   .long	 .LBB8_3 at GOTOFF
-; LINUX:   .long	 .LBB8_7 at GOTOFF
+; LINUX:   .long	 .LBB8_8 at GOTOFF
+; LINUX:   .long	 .LBB8_14 at GOTOFF
+; LINUX:   .long	 .LBB8_9 at GOTOFF
+; LINUX:   .long	 .LBB8_10 at GOTOFF
 }
 
 declare void @foo1(...)

Modified: llvm/trunk/test/CodeGen/X86/sibcall.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sibcall.ll?rev=99598&r1=99597&r2=99598&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sibcall.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sibcall.ll Thu Mar 25 21:13:13 2010
@@ -271,3 +271,34 @@
 }
 
 declare double @bar4()
+
+; rdar://6283267
+define void @t17() nounwind ssp {
+entry:
+; 32: t17:
+; 32: jmp {{_?}}bar5
+
+; 64: t17:
+; 64: xorb %al, %al
+; 64: jmp {{_?}}bar5
+  tail call void (...)* @bar5() nounwind
+  ret void
+}
+
+declare void @bar5(...)
+
+; rdar://7774847
+define void @t18() nounwind ssp {
+entry:
+; 32: t18:
+; 32: call {{_?}}bar6
+; 32: fstp %st(0)
+
+; 64: t18:
+; 64: xorb %al, %al
+; 64: jmp {{_?}}bar6
+  %0 = tail call double (...)* @bar6() nounwind
+  ret void
+}
+
+declare double @bar6(...)

Modified: llvm/trunk/test/CodeGen/X86/xor-icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor-icmp.ll?rev=99598&r1=99597&r2=99598&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/xor-icmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/xor-icmp.ll Thu Mar 25 21:13:13 2010
@@ -43,7 +43,7 @@
 ; X32: cmpl
 ; X32: sete
 ; X32-NOT: xor
-; X32: je
+; X32: jne
 
 ; X64: t2:
 ; X64: testl
@@ -51,7 +51,7 @@
 ; X64: testl
 ; X64: sete
 ; X64-NOT: xor
-; X64: je
+; X64: jne
 entry:
   %0 = icmp eq i32 %x, 0                          ; <i1> [#uses=1]
   %1 = icmp eq i32 %y, 0                          ; <i1> [#uses=1]




From grosbach at apple.com  Thu Mar 25 21:27:33 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 25 Mar 2010 19:27:33 -0700
Subject: [llvm-commits] [llvm] r99598 - in /llvm/trunk:
	lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/pic.ll
	test/CodeGen/X86/sibcall.ll test/CodeGen/X86/xor-icmp.ll
In-Reply-To: <20100326021313.E02D42A6C12C@llvm.org>
References: <20100326021313.E02D42A6C12C@llvm.org>
Message-ID: <29096CFD-D9CF-42B3-94C3-077C3E5D2503@apple.com>

Is Outs only the variable portion of the argument list? If it includes the fixed portion, it'll never be empty for a varargs function, right?

On Mar 25, 2010, at 7:13 PM, Evan Cheng wrote:

> Author: evancheng
> Date: Thu Mar 25 21:13:13 2010
> New Revision: 99598
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99598&view=rev
> Log:
> Allow trivial sibcall of vararg callee when no arguments are being passed.
> 
> Modified:
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>    llvm/trunk/test/CodeGen/X86/pic.ll
>    llvm/trunk/test/CodeGen/X86/sibcall.ll
>    llvm/trunk/test/CodeGen/X86/xor-icmp.ll
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=99598&r1=99597&r2=99598&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Mar 25 21:13:13 2010
> @@ -2301,8 +2301,9 @@
>   // Look for obvious safe cases to perform tail call optimization that does not
>   // requite ABI changes. This is what gcc calls sibcall.
> 
> -  // Do not sibcall optimize vararg calls for now.
> -  if (isVarArg)
> +  // Do not sibcall optimize vararg calls unless the call site is not passing any
> +  // arguments.
> +  if (isVarArg && !Outs.empty())
>     return false;
> 
>   // Also avoid sibcall optimization if either caller or callee uses struct
> 
> Modified: llvm/trunk/test/CodeGen/X86/pic.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pic.ll?rev=99598&r1=99597&r2=99598&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/pic.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/pic.ll Thu Mar 25 21:13:13 2010
> @@ -194,10 +194,10 @@
> 
> ; LINUX: .LJTI8_0:
> ; LINUX:   .long	 .LBB8_2 at GOTOFF
> -; LINUX:   .long	 .LBB8_2 at GOTOFF
> -; LINUX:   .long	 .LBB8_7 at GOTOFF
> -; LINUX:   .long	 .LBB8_3 at GOTOFF
> -; LINUX:   .long	 .LBB8_7 at GOTOFF
> +; LINUX:   .long	 .LBB8_8 at GOTOFF
> +; LINUX:   .long	 .LBB8_14 at GOTOFF
> +; LINUX:   .long	 .LBB8_9 at GOTOFF
> +; LINUX:   .long	 .LBB8_10 at GOTOFF
> }
> 
> declare void @foo1(...)
> 
> Modified: llvm/trunk/test/CodeGen/X86/sibcall.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sibcall.ll?rev=99598&r1=99597&r2=99598&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/sibcall.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/sibcall.ll Thu Mar 25 21:13:13 2010
> @@ -271,3 +271,34 @@
> }
> 
> declare double @bar4()
> +
> +; rdar://6283267
> +define void @t17() nounwind ssp {
> +entry:
> +; 32: t17:
> +; 32: jmp {{_?}}bar5
> +
> +; 64: t17:
> +; 64: xorb %al, %al
> +; 64: jmp {{_?}}bar5
> +  tail call void (...)* @bar5() nounwind
> +  ret void
> +}
> +
> +declare void @bar5(...)
> +
> +; rdar://7774847
> +define void @t18() nounwind ssp {
> +entry:
> +; 32: t18:
> +; 32: call {{_?}}bar6
> +; 32: fstp %st(0)
> +
> +; 64: t18:
> +; 64: xorb %al, %al
> +; 64: jmp {{_?}}bar6
> +  %0 = tail call double (...)* @bar6() nounwind
> +  ret void
> +}
> +
> +declare double @bar6(...)
> 
> Modified: llvm/trunk/test/CodeGen/X86/xor-icmp.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor-icmp.ll?rev=99598&r1=99597&r2=99598&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/xor-icmp.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/xor-icmp.ll Thu Mar 25 21:13:13 2010
> @@ -43,7 +43,7 @@
> ; X32: cmpl
> ; X32: sete
> ; X32-NOT: xor
> -; X32: je
> +; X32: jne
> 
> ; X64: t2:
> ; X64: testl
> @@ -51,7 +51,7 @@
> ; X64: testl
> ; X64: sete
> ; X64-NOT: xor
> -; X64: je
> +; X64: jne
> entry:
>   %0 = icmp eq i32 %x, 0                          ; <i1> [#uses=1]
>   %1 = icmp eq i32 %y, 0                          ; <i1> [#uses=1]
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From stoklund at 2pi.dk  Thu Mar 25 22:34:25 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 25 Mar 2010 20:34:25 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r99593 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
In-Reply-To: <20100326012801.6BF3D2A6C12C@llvm.org>
References: <20100326012801.6BF3D2A6C12C@llvm.org>
Message-ID: <02F676DD-4720-4736-9818-26B4B5421CC6@2pi.dk>


On Mar 25, 2010, at 6:28 PM, Eric Christopher wrote:

> Author: echristo
> Date: Thu Mar 25 20:28:01 2010
> New Revision: 99593
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99593&view=rev
> Log:
> Try to lower in the backend first, it may know what to do better for the
> target.

Thanks, Eric!

When I tried this earlier on _mm_loadu_si128(), it got lowered as an IR load instead of an intrinsic as I wanted, but the 'align 1' was lost somehow. IIRC, it was correct at -O0, but wrong with optimization on.

I'll test it in the morning, I don't have an i7 to build llvm-gcc at home :-(


> 
> Modified:
>    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
> 
> Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=99593&r1=99592&r2=99593&view=diff
> ==============================================================================
> --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
> +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Mar 25 20:28:01 2010
> @@ -4955,8 +4955,7 @@
> //                     ... Builtin Function Expansion ...
> //===----------------------------------------------------------------------===//
> 
> -/// EmitFrontendExpandedBuiltinCall - For MD builtins that do not have a
> -/// directly corresponding LLVM intrinsic, we allow the target to do some amount
> +/// EmitFrontendExpandedBuiltinCall - We allow the target to do some amount
> /// of lowering.  This allows us to avoid having intrinsics for operations that
> /// directly correspond to LLVM constructs.
> ///
> @@ -5112,14 +5111,17 @@
> #ifdef LLVM_TARGET_INTRINSIC_PREFIX
>       TargetPrefix = LLVM_TARGET_INTRINSIC_PREFIX;
> #endif
> +      // If the backend has some special code to lower, go ahead and try to
> +      // do that first.
> +      if (EmitFrontendExpandedBuiltinCall(exp, fndecl, DestLoc, Result))
> +        return true;
> +      
>       // If this builtin directly corresponds to an LLVM intrinsic, get the
>       // IntrinsicID now.
>       const char *BuiltinName = IDENTIFIER_POINTER(DECL_NAME(fndecl));
>       Intrinsic::ID IntrinsicID =
>         Intrinsic::getIntrinsicForGCCBuiltin(TargetPrefix, BuiltinName);
>       if (IntrinsicID == Intrinsic::not_intrinsic) {
> -        if (EmitFrontendExpandedBuiltinCall(exp, fndecl, DestLoc, Result))
> -          return true;
> 
>         error("%Hunsupported target builtin %<%s%> used", &EXPR_LOCATION(exp),
>               BuiltinName);
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From evan.cheng at apple.com  Fri Mar 26 00:15:45 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 25 Mar 2010 22:15:45 -0700
Subject: [llvm-commits] [llvm] r99598 - in /llvm/trunk:
	lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/pic.ll
	test/CodeGen/X86/sibcall.ll test/CodeGen/X86/xor-icmp.ll
In-Reply-To: <29096CFD-D9CF-42B3-94C3-077C3E5D2503@apple.com>
References: <20100326021313.E02D42A6C12C@llvm.org>
	<29096CFD-D9CF-42B3-94C3-077C3E5D2503@apple.com>
Message-ID: <3DFD29C3-18E5-4C1B-9E1B-B6198B38DBC0@apple.com>


On Mar 25, 2010, at 7:27 PM, Jim Grosbach wrote:

> Is Outs only the variable portion of the argument list? If it includes the fixed portion, it'll never be empty for a varargs function, right?

Outs are all the arguments including the fixed portion. It can be empty. In fact it's very common because C is so awesome.

extern void bar();
void foo() {
  bar();
}

bar is a vararg function.

Evan

> 
> On Mar 25, 2010, at 7:13 PM, Evan Cheng wrote:
> 
>> Author: evancheng
>> Date: Thu Mar 25 21:13:13 2010
>> New Revision: 99598
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99598&view=rev
>> Log:
>> Allow trivial sibcall of vararg callee when no arguments are being passed.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>   llvm/trunk/test/CodeGen/X86/pic.ll
>>   llvm/trunk/test/CodeGen/X86/sibcall.ll
>>   llvm/trunk/test/CodeGen/X86/xor-icmp.ll
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=99598&r1=99597&r2=99598&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Mar 25 21:13:13 2010
>> @@ -2301,8 +2301,9 @@
>>  // Look for obvious safe cases to perform tail call optimization that does not
>>  // requite ABI changes. This is what gcc calls sibcall.
>> 
>> -  // Do not sibcall optimize vararg calls for now.
>> -  if (isVarArg)
>> +  // Do not sibcall optimize vararg calls unless the call site is not passing any
>> +  // arguments.
>> +  if (isVarArg && !Outs.empty())
>>    return false;
>> 
>>  // Also avoid sibcall optimization if either caller or callee uses struct
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/pic.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pic.ll?rev=99598&r1=99597&r2=99598&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/pic.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/pic.ll Thu Mar 25 21:13:13 2010
>> @@ -194,10 +194,10 @@
>> 
>> ; LINUX: .LJTI8_0:
>> ; LINUX:   .long	 .LBB8_2 at GOTOFF
>> -; LINUX:   .long	 .LBB8_2 at GOTOFF
>> -; LINUX:   .long	 .LBB8_7 at GOTOFF
>> -; LINUX:   .long	 .LBB8_3 at GOTOFF
>> -; LINUX:   .long	 .LBB8_7 at GOTOFF
>> +; LINUX:   .long	 .LBB8_8 at GOTOFF
>> +; LINUX:   .long	 .LBB8_14 at GOTOFF
>> +; LINUX:   .long	 .LBB8_9 at GOTOFF
>> +; LINUX:   .long	 .LBB8_10 at GOTOFF
>> }
>> 
>> declare void @foo1(...)
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/sibcall.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sibcall.ll?rev=99598&r1=99597&r2=99598&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/sibcall.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/sibcall.ll Thu Mar 25 21:13:13 2010
>> @@ -271,3 +271,34 @@
>> }
>> 
>> declare double @bar4()
>> +
>> +; rdar://6283267
>> +define void @t17() nounwind ssp {
>> +entry:
>> +; 32: t17:
>> +; 32: jmp {{_?}}bar5
>> +
>> +; 64: t17:
>> +; 64: xorb %al, %al
>> +; 64: jmp {{_?}}bar5
>> +  tail call void (...)* @bar5() nounwind
>> +  ret void
>> +}
>> +
>> +declare void @bar5(...)
>> +
>> +; rdar://7774847
>> +define void @t18() nounwind ssp {
>> +entry:
>> +; 32: t18:
>> +; 32: call {{_?}}bar6
>> +; 32: fstp %st(0)
>> +
>> +; 64: t18:
>> +; 64: xorb %al, %al
>> +; 64: jmp {{_?}}bar6
>> +  %0 = tail call double (...)* @bar6() nounwind
>> +  ret void
>> +}
>> +
>> +declare double @bar6(...)
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/xor-icmp.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor-icmp.ll?rev=99598&r1=99597&r2=99598&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/xor-icmp.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/xor-icmp.ll Thu Mar 25 21:13:13 2010
>> @@ -43,7 +43,7 @@
>> ; X32: cmpl
>> ; X32: sete
>> ; X32-NOT: xor
>> -; X32: je
>> +; X32: jne
>> 
>> ; X64: t2:
>> ; X64: testl
>> @@ -51,7 +51,7 @@
>> ; X64: testl
>> ; X64: sete
>> ; X64-NOT: xor
>> -; X64: je
>> +; X64: jne
>> entry:
>>  %0 = icmp eq i32 %x, 0                          ; <i1> [#uses=1]
>>  %1 = icmp eq i32 %y, 0                          ; <i1> [#uses=1]
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 




From grosbach at apple.com  Fri Mar 26 09:58:57 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 26 Mar 2010 07:58:57 -0700
Subject: [llvm-commits] [llvm] r99598 - in /llvm/trunk:
	lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/pic.ll
	test/CodeGen/X86/sibcall.ll test/CodeGen/X86/xor-icmp.ll
In-Reply-To: <3DFD29C3-18E5-4C1B-9E1B-B6198B38DBC0@apple.com>
References: <20100326021313.E02D42A6C12C@llvm.org>
	<29096CFD-D9CF-42B3-94C3-077C3E5D2503@apple.com>
	<3DFD29C3-18E5-4C1B-9E1B-B6198B38DBC0@apple.com>
Message-ID: <843B7DE9-4587-478E-BC9F-06ED1ED047DF@apple.com>

Ah, I see. We consider any C function call w/o a prototype to be a call to a vararg function? That makes sense, and does indeed make this an (unfortunately) common case. Not one of my favorite features of the C language, to be sure.

Thanks,
   Jim

On Mar 25, 2010, at 10:15 PM, Evan Cheng wrote:

> 
> On Mar 25, 2010, at 7:27 PM, Jim Grosbach wrote:
> 
>> Is Outs only the variable portion of the argument list? If it includes the fixed portion, it'll never be empty for a varargs function, right?
> 
> Outs are all the arguments including the fixed portion. It can be empty. In fact it's very common because C is so awesome.
> 
> extern void bar();
> void foo() {
>  bar();
> }
> 
> bar is a vararg function.
> 
> Evan
> 
>> 
>> On Mar 25, 2010, at 7:13 PM, Evan Cheng wrote:
>> 
>>> Author: evancheng
>>> Date: Thu Mar 25 21:13:13 2010
>>> New Revision: 99598
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=99598&view=rev
>>> Log:
>>> Allow trivial sibcall of vararg callee when no arguments are being passed.
>>> 
>>> Modified:
>>>  llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>>  llvm/trunk/test/CodeGen/X86/pic.ll
>>>  llvm/trunk/test/CodeGen/X86/sibcall.ll
>>>  llvm/trunk/test/CodeGen/X86/xor-icmp.ll
>>> 
>>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=99598&r1=99597&r2=99598&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Mar 25 21:13:13 2010
>>> @@ -2301,8 +2301,9 @@
>>> // Look for obvious safe cases to perform tail call optimization that does not
>>> // requite ABI changes. This is what gcc calls sibcall.
>>> 
>>> -  // Do not sibcall optimize vararg calls for now.
>>> -  if (isVarArg)
>>> +  // Do not sibcall optimize vararg calls unless the call site is not passing any
>>> +  // arguments.
>>> +  if (isVarArg && !Outs.empty())
>>>   return false;
>>> 
>>> // Also avoid sibcall optimization if either caller or callee uses struct
>>> 
>>> Modified: llvm/trunk/test/CodeGen/X86/pic.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pic.ll?rev=99598&r1=99597&r2=99598&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/X86/pic.ll (original)
>>> +++ llvm/trunk/test/CodeGen/X86/pic.ll Thu Mar 25 21:13:13 2010
>>> @@ -194,10 +194,10 @@
>>> 
>>> ; LINUX: .LJTI8_0:
>>> ; LINUX:   .long	 .LBB8_2 at GOTOFF
>>> -; LINUX:   .long	 .LBB8_2 at GOTOFF
>>> -; LINUX:   .long	 .LBB8_7 at GOTOFF
>>> -; LINUX:   .long	 .LBB8_3 at GOTOFF
>>> -; LINUX:   .long	 .LBB8_7 at GOTOFF
>>> +; LINUX:   .long	 .LBB8_8 at GOTOFF
>>> +; LINUX:   .long	 .LBB8_14 at GOTOFF
>>> +; LINUX:   .long	 .LBB8_9 at GOTOFF
>>> +; LINUX:   .long	 .LBB8_10 at GOTOFF
>>> }
>>> 
>>> declare void @foo1(...)
>>> 
>>> Modified: llvm/trunk/test/CodeGen/X86/sibcall.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sibcall.ll?rev=99598&r1=99597&r2=99598&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/X86/sibcall.ll (original)
>>> +++ llvm/trunk/test/CodeGen/X86/sibcall.ll Thu Mar 25 21:13:13 2010
>>> @@ -271,3 +271,34 @@
>>> }
>>> 
>>> declare double @bar4()
>>> +
>>> +; rdar://6283267
>>> +define void @t17() nounwind ssp {
>>> +entry:
>>> +; 32: t17:
>>> +; 32: jmp {{_?}}bar5
>>> +
>>> +; 64: t17:
>>> +; 64: xorb %al, %al
>>> +; 64: jmp {{_?}}bar5
>>> +  tail call void (...)* @bar5() nounwind
>>> +  ret void
>>> +}
>>> +
>>> +declare void @bar5(...)
>>> +
>>> +; rdar://7774847
>>> +define void @t18() nounwind ssp {
>>> +entry:
>>> +; 32: t18:
>>> +; 32: call {{_?}}bar6
>>> +; 32: fstp %st(0)
>>> +
>>> +; 64: t18:
>>> +; 64: xorb %al, %al
>>> +; 64: jmp {{_?}}bar6
>>> +  %0 = tail call double (...)* @bar6() nounwind
>>> +  ret void
>>> +}
>>> +
>>> +declare double @bar6(...)
>>> 
>>> Modified: llvm/trunk/test/CodeGen/X86/xor-icmp.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor-icmp.ll?rev=99598&r1=99597&r2=99598&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/X86/xor-icmp.ll (original)
>>> +++ llvm/trunk/test/CodeGen/X86/xor-icmp.ll Thu Mar 25 21:13:13 2010
>>> @@ -43,7 +43,7 @@
>>> ; X32: cmpl
>>> ; X32: sete
>>> ; X32-NOT: xor
>>> -; X32: je
>>> +; X32: jne
>>> 
>>> ; X64: t2:
>>> ; X64: testl
>>> @@ -51,7 +51,7 @@
>>> ; X64: testl
>>> ; X64: sete
>>> ; X64-NOT: xor
>>> -; X64: je
>>> +; X64: jne
>>> entry:
>>> %0 = icmp eq i32 %x, 0                          ; <i1> [#uses=1]
>>> %1 = icmp eq i32 %y, 0                          ; <i1> [#uses=1]
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
> 




From grosbach at apple.com  Fri Mar 26 10:17:13 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 26 Mar 2010 15:17:13 -0000
Subject: [llvm-commits] [test-suite] r99618 -
	/test-suite/trunk/Makefile.programs
Message-ID: <20100326151713.0D5A52A6C12C@llvm.org>

Author: grosbach
Date: Fri Mar 26 10:17:12 2010
New Revision: 99618

URL: http://llvm.org/viewvc/llvm-project?rev=99618&view=rev
Log:
clear ARM and THUMB llcbeta options

Modified:
    test-suite/trunk/Makefile.programs

Modified: test-suite/trunk/Makefile.programs
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=99618&r1=99617&r2=99618&view=diff
==============================================================================
--- test-suite/trunk/Makefile.programs (original)
+++ test-suite/trunk/Makefile.programs Fri Mar 26 10:17:12 2010
@@ -241,10 +241,10 @@
 LLCBETAOPTION := -enable-sparc-v9-insts
 endif
 ifeq ($(ARCH),ARM)
-LLCBETAOPTION := -arm-use-vmlx=false
+LLCBETAOPTION :=
 endif
 ifeq ($(ARCH),THUMB)
-LLCBETAOPTION := -arm-use-vmlx=false
+LLCBETAOPTION :=
 endif
 
 print-llcbeta-option:




From evan.cheng at apple.com  Fri Mar 26 11:26:04 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 26 Mar 2010 16:26:04 -0000
Subject: [llvm-commits] [llvm] r99620 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/sibcall.ll
Message-ID: <20100326162604.4EA972A6C12C@llvm.org>

Author: evancheng
Date: Fri Mar 26 11:26:03 2010
New Revision: 99620

URL: http://llvm.org/viewvc/llvm-project?rev=99620&view=rev
Log:
Do not sibcall if stack needs to be dynamically aligned.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/sibcall.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=99620&r1=99619&r2=99620&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Mar 26 11:26:03 2010
@@ -2290,6 +2290,7 @@
     return false;
 
   // If -tailcallopt is specified, make fastcc functions tail-callable.
+  const MachineFunction &MF = DAG.getMachineFunction();
   const Function *CallerF = DAG.getMachineFunction().getFunction();
   if (GuaranteedTailCallOpt) {
     if (IsTailCallConvention(CalleeCC) &&
@@ -2301,6 +2302,11 @@
   // Look for obvious safe cases to perform tail call optimization that does not
   // requite ABI changes. This is what gcc calls sibcall.
 
+  // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
+  // emit a special epilogue.
+  if (RegInfo->needsStackRealignment(MF))
+    return false;
+
   // Do not sibcall optimize vararg calls unless the call site is not passing any
   // arguments.
   if (isVarArg && !Outs.empty())

Modified: llvm/trunk/test/CodeGen/X86/sibcall.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sibcall.ll?rev=99620&r1=99619&r2=99620&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sibcall.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sibcall.ll Fri Mar 26 11:26:03 2010
@@ -302,3 +302,14 @@
 }
 
 declare double @bar6(...)
+
+define void @t19() alignstack(32) nounwind {
+entry:
+; CHECK: t19:
+; CHECK: andl $-32
+; CHECK: call {{_?}}foo
+  tail call void @foo() nounwind
+  ret void
+}
+
+declare void @foo()




From johnny.chen at apple.com  Fri Mar 26 13:32:20 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Fri, 26 Mar 2010 18:32:20 -0000
Subject: [llvm-commits] [llvm] r99628 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20100326183220.8E1102A6C12C@llvm.org>

Author: johnny
Date: Fri Mar 26 13:32:20 2010
New Revision: 99628

URL: http://llvm.org/viewvc/llvm-project?rev=99628&view=rev
Log:
Add N3RegFrm to represent "NEON 3 vector register format" instructions.
Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99628&r1=99627&r2=99628&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Mar 26 13:32:20 2010
@@ -66,6 +66,7 @@
 def NVDupLnFrm     : Format<35>;
 def N2RegVShLFrm   : Format<36>;
 def N2RegVShRFrm   : Format<37>;
+def N3RegFrm       : Format<38>;
 
 // Misc flags.
 
@@ -1606,7 +1607,7 @@
 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
           dag oops, dag iops, InstrItinClass itin,
           string opc, string dt, string asm, string cstr, list<dag> pattern>
-  : NDataI<oops, iops, NEONFrm, itin, opc, dt, asm, cstr, pattern> {
+  : NDataI<oops, iops, N3RegFrm, itin, opc, dt, asm, cstr, pattern> {
   let Inst{24} = op24;
   let Inst{23} = op23;
   let Inst{21-20} = op21_20;
@@ -1620,7 +1621,7 @@
            bit op4,
            dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, string cstr, list<dag> pattern>
-  : NDataXI<oops, iops, NEONFrm, itin, opc, asm, cstr, pattern> {
+  : NDataXI<oops, iops, N3RegFrm, itin, opc, asm, cstr, pattern> {
   let Inst{24} = op24;
   let Inst{23} = op23;
   let Inst{21-20} = op21_20;




From sabre at nondot.org  Fri Mar 26 13:41:06 2010
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 26 Mar 2010 18:41:06 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r99629 -
	/llvm-gcc-4.2/trunk/gcc/gimplify.c
Message-ID: <20100326184106.E6B7E2A6C12C@llvm.org>

Author: lattner
Date: Fri Mar 26 13:41:06 2010
New Revision: 99629

URL: http://llvm.org/viewvc/llvm-project?rev=99629&view=rev
Log:
disable a minor optimization on darwin.  For code like this:

extern int a, b, c, d;
void foo() {
  int *Arr[] = {&a, &b, &c, &d, &a, &b, &c, &d, &a, &b, &c, &d, &a, &b, &c, &d,
    &a, &b, &c, &d, &a, &b, &c, &d, &a, &b, &c, &d, &a, &b, &c, &d };
  bar(Arr);
}

the compiler synthesizes a global variable for the temporary array and then
memcpy's from it to Arr.  This is all great, but emitting the temporary global
with an L label on darwin fouls up atomization and can thus break dead code
stripping.

The right answer is to use an 'l' label without .globl, but this will require
introducing a yet-another new linkage type to llvm, which I'll do later.

This fixes rdar://7233622


Modified:
    llvm-gcc-4.2/trunk/gcc/gimplify.c

Modified: llvm-gcc-4.2/trunk/gcc/gimplify.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gimplify.c?rev=99629&r1=99628&r2=99629&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/gimplify.c (original)
+++ llvm-gcc-4.2/trunk/gcc/gimplify.c Fri Mar 26 13:41:06 2010
@@ -3097,9 +3097,16 @@
 		TREE_STATIC (new) = 1;
 		TREE_READONLY (new) = 1;
                 /* LLVM LOCAL begin */
+                /* On Darwin, we can't emit temporaries like this with private
+                 * linkage, because it breaks 'atomization' of stuff in the
+                 * object file by the linker.  We need to emit this as a l label
+                 * without .globl.
+                 */
+#ifndef CONFIG_DARWIN_H
 #ifdef ENABLE_LLVM
 		DECL_LLVM_PRIVATE (new) = 1;
 #endif
+#endif
                 /* LLVM LOCAL end */
 		DECL_INITIAL (new) = ctor;
 		if (align > DECL_ALIGN (new))




From grosbach at apple.com  Fri Mar 26 13:41:09 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 26 Mar 2010 18:41:09 -0000
Subject: [llvm-commits] [llvm] r99630 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Message-ID: <20100326184109.9984E2A6C12D@llvm.org>

Author: grosbach
Date: Fri Mar 26 13:41:09 2010
New Revision: 99630

URL: http://llvm.org/viewvc/llvm-project?rev=99630&view=rev
Log:
vldm/vstm can only do up to 16 double-word registers at a time.
Radar 7797856

Modified:
    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=99630&r1=99629&r2=99630&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Fri Mar 26 13:41:09 2010
@@ -341,6 +341,7 @@
   unsigned PReg = PMO.getReg();
   unsigned PRegNum = PMO.isUndef() ? UINT_MAX
     : ARMRegisterInfo::getRegisterNumbering(PReg);
+  unsigned Count = 1;
 
   for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) {
     int NewOffset = MemOps[i].Offset;
@@ -350,11 +351,14 @@
       : ARMRegisterInfo::getRegisterNumbering(Reg);
     // AM4 - register numbers in ascending order.
     // AM5 - consecutive register numbers in ascending order.
+    //       Can only do up to 16 double-word registers per insn.
     if (Reg != ARM::SP &&
         NewOffset == Offset + (int)Size &&
-        ((isAM4 && RegNum > PRegNum) || RegNum == PRegNum+1)) {
+        ((isAM4 && RegNum > PRegNum)
+         || ((Size < 8 || Count < 16) && RegNum == PRegNum+1))) {
       Offset += Size;
       PRegNum = RegNum;
+      ++Count;
     } else {
       // Can't merge this in. Try merge the earlier ones first.
       MergeOpsUpdate(MBB, MemOps, SIndex, i, insertAfter, SOffset,




From daniel at zuster.org  Fri Mar 26 13:52:46 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 26 Mar 2010 18:52:46 -0000
Subject: [llvm-commits] [compiler-rt] r99632 -
	/compiler-rt/trunk/make/platform/clang_darwin.mk
Message-ID: <20100326185246.191512A6C12C@llvm.org>

Author: ddunbar
Date: Fri Mar 26 13:52:45 2010
New Revision: 99632

URL: http://llvm.org/viewvc/llvm-project?rev=99632&view=rev
Log:
Clang/Darwin: Add definition for files to put in cc_kext.a.

Modified:
    compiler-rt/trunk/make/platform/clang_darwin.mk

Modified: compiler-rt/trunk/make/platform/clang_darwin.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin.mk?rev=99632&r1=99631&r2=99632&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/clang_darwin.mk (original)
+++ compiler-rt/trunk/make/platform/clang_darwin.mk Fri Mar 26 13:52:45 2010
@@ -20,6 +20,12 @@
 Configs += armv6
 UniversalArchs.armv6 := armv6
 
+# Configuration for use with kernel/kexts.
+Configs += cc_kext
+UniversalArchs.cc_kext := armv6 armv7 i386 x86_64
+
+###
+
 CC := gcc
 
 # Forcibly strip off any -arch, as that totally breaks our universal support.
@@ -32,4 +38,204 @@
 FUNCTIONS.armv6 := switch16 switch32 switch8 switchu8 \
                    save_vfp_d8_d15_regs restore_vfp_d8_d15_regs
 
+CCKEXT_COMMON_FUNCTIONS := \
+	absvdi2 \
+	absvsi2 \
+	addvdi3 \
+	addvsi3 \
+	ashldi3 \
+	ashrdi3 \
+	bswapdi2 \
+	bswapsi2 \
+	clear_cache \
+	clzdi2 \
+	clzsi2 \
+	cmpdi2 \
+	ctzdi2 \
+	ctzsi2 \
+	divdc3 \
+	divdi3 \
+	divsc3 \
+	do_global_dtors \
+	enable_execute_stack \
+	eprintf \
+	ffsdi2 \
+	fixdfdi \
+	fixsfdi \
+	fixunsdfdi \
+	fixunsdfsi \
+	fixunssfdi \
+	fixunssfsi \
+	floatdidf \
+	floatdisf \
+	floatundidf \
+	floatundisf \
+	gcc_bcmp \
+	lshrdi3 \
+	moddi3 \
+	muldc3 \
+	muldi3 \
+	mulsc3 \
+	mulvdi3 \
+	mulvsi3 \
+	negdi2 \
+	negvdi2 \
+	negvsi2 \
+	paritydi2 \
+	paritysi2 \
+	popcountdi2 \
+	popcountsi2 \
+	powidf2 \
+	powisf2 \
+	subvdi3 \
+	subvsi3 \
+	ucmpdi2 \
+	udiv_w_sdiv \
+	udivdi3 \
+	udivmoddi4 \
+	umoddi3
+
+CCKEXT_ARM_FUNCTIONS := $(CCKEXT_COMMON_FUNCTONS) \
+	adddf3 \
+	addsf3 \
+	aeabi_cdcmpeq \
+	aeabi_cdrcmple \
+	aeabi_cfcmpeq \
+	aeabi_cfrcmple \
+	aeabi_dcmpeq \
+	aeabi_dcmpge \
+	aeabi_dcmpgt \
+	aeabi_dcmple \
+	aeabi_dcmplt \
+	aeabi_drsub \
+	aeabi_fcmpeq \
+	aeabi_fcmpge \
+	aeabi_fcmpgt \
+	aeabi_fcmple \
+	aeabi_fcmplt \
+	aeabi_frsub \
+	aeabi_idivmod \
+	aeabi_uidivmod \
+	cmpdf2 \
+	cmpsf2 \
+	div0 \
+	divdf3 \
+	divsf3 \
+	divsi3 \
+	extendsfdf2 \
+	ffssi2 \
+	fixdfsi \
+	fixsfsi \
+	floatsidf \
+	floatsisf \
+	floatunsidf \
+	floatunsisf \
+	gtdf2 \
+	gtsf2 \
+	ltdf2 \
+	ltsf2 \
+	modsi3 \
+	muldf3 \
+	mulsf3 \
+	negdf2 \
+	negsf2 \
+	subdf3 \
+	subsf3 \
+	switch16 \
+	switch32 \
+	switch8 \
+	switchu8 \
+	truncdfsf2 \
+	udivsi3 \
+	umodsi3 \
+	unorddf2 \
+	unordsf2
+
+FUNCTIONS.cc_kext.armv6 := $(CCKEXT_ARM_FUNCTIONS)
+FUNCTIONS.cc_kext.armv7 := $(CCKEXT_ARM_FUNCTIONS)
+
+CCKEXT_X86_FUNCTIONS := $(CCKEXT_COMMON_FUNCTIONS) \
+	divxc3 \
+	fixunsxfdi \
+	fixunsxfsi \
+	fixxfdi \
+	floatdixf \
+	floatundixf \
+	mulxc3 \
+	powixf2
+
+FUNCTIONS.cc_kext.i386 := $(CCKEXT_X86_FUNCTIONS) \
+	ffssi2 \
+	i686.get_pc_thunk.eax \
+	i686.get_pc_thunk.ebp \
+	i686.get_pc_thunk.ebx \
+	i686.get_pc_thunk.ecx \
+	i686.get_pc_thunk.edi \
+	i686.get_pc_thunk.edx \
+	i686.get_pc_thunk.esi
+
+FUNCTIONS.cc_kext.x86_64 := $(CCKEXT_X86_FUNCTIONS) \
+	absvti2 \
+	addvti3 \
+	ashlti3 \
+	ashrti3 \
+	clzti2 \
+	cmpti2 \
+	ctzti2 \
+	divti3 \
+	ffsti2 \
+	fixdfti \
+	fixsfti \
+	fixunsdfti \
+	fixunssfti \
+	fixunsxfti \
+	fixxfti \
+	floattidf \
+	floattisf \
+	floattixf \
+	floatuntidf \
+	floatuntisf \
+	floatuntixf \
+	lshrti3 \
+	modti3 \
+	multi3 \
+	mulvti3 \
+	negti2 \
+	negvti2 \
+	parityti2 \
+	popcountti2 \
+	subvti3 \
+	ucmpti2 \
+	udivmodti4 \
+	udivti3 \
+	umodti3
+
+# FIXME: Currently, compiler-rt is missing implementations for a number of the
+# functions that need to go into libcc_kext.a. Filter them out for now.
+CCKEXT_MISSING_FUNCTIONS := \
+	adddf3 addsf3 cmpdf2 cmpsf2 div0 divdf3 divsf3 \
+	extendsfdf2 ffssi2 fixdfsi fixsfsi floatsidf floatsisf \
+	floatunsidf floatunsisf gtdf2 gtsf2 ltdf2 ltsf2 \
+	muldf3 mulsf3 negdf2 negsf2 subdf3 subsf3 \
+	truncdfsf2 udiv_w_sdiv unorddf2 unordsf2 bswapdi2 \
+	bswapsi2 \
+	gcc_bcmp \
+	do_global_dtors \
+	i686.get_pc_thunk.eax i686.get_pc_thunk.ebp i686.get_pc_thunk.ebx \
+	i686.get_pc_thunk.ecx i686.get_pc_thunk.edi i686.get_pc_thunk.edx \
+	i686.get_pc_thunk.esi \
+	aeabi_cdcmpeq aeabi_cdrcmple aeabi_cfcmpeq aeabi_cfrcmple aeabi_dcmpeq \
+	aeabi_dcmpge aeabi_dcmpgt aeabi_dcmple aeabi_dcmplt aeabi_drsub aeabi_fcmpeq \
+	aeabi_fcmpge aeabi_fcmpgt aeabi_fcmple aeabi_fcmplt aeabi_frsub aeabi_idivmod \
+	aeabi_uidivmod
+
+FUNCTIONS.cc_kext.armv6 := \
+	$(filter-out $(CCKEXT_MISSING_FUNCTIONS),$(FUNCTIONS.cc_kext.armv6))
+FUNCTIONS.cc_kext.armv7 := \
+	$(filter-out $(CCKEXT_MISSING_FUNCTIONS),$(FUNCTIONS.cc_kext.armv7))
+FUNCTIONS.cc_kext.i386 := \
+	$(filter-out $(CCKEXT_MISSING_FUNCTIONS),$(FUNCTIONS.cc_kext.i386))
+FUNCTIONS.cc_kext.x86_64 := \
+	$(filter-out $(CCKEXT_MISSING_FUNCTIONS),$(FUNCTIONS.cc_kext.x86_64))
+
 VISIBILITY_HIDDEN := 1




From gohman at apple.com  Fri Mar 26 13:53:37 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 26 Mar 2010 18:53:37 -0000
Subject: [llvm-commits] [llvm] r99633 - in /llvm/trunk:
 include/llvm/ADT/SmallVector.h unittests/ADT/SmallVectorTest.cpp
Message-ID: <20100326185337.978542A6C12C@llvm.org>

Author: djg
Date: Fri Mar 26 13:53:37 2010
New Revision: 99633

URL: http://llvm.org/viewvc/llvm-project?rev=99633&view=rev
Log:
Fix SmallVector's insert to handle non-random-access iterators.

Modified:
    llvm/trunk/include/llvm/ADT/SmallVector.h
    llvm/trunk/unittests/ADT/SmallVectorTest.cpp

Modified: llvm/trunk/include/llvm/ADT/SmallVector.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallVector.h?rev=99633&r1=99632&r2=99633&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/SmallVector.h (original)
+++ llvm/trunk/include/llvm/ADT/SmallVector.h Fri Mar 26 13:53:37 2010
@@ -239,11 +239,20 @@
   /// starting with "Dest", constructing elements into it as needed.
   template<typename It1, typename It2>
   static void uninitialized_copy(It1 I, It1 E, It2 Dest) {
-    // Use memcpy for PODs: std::uninitialized_copy optimizes to memmove, memcpy
-    // is better.
-    memcpy(&*Dest, &*I, (E-I)*sizeof(T));
+    // Arbitrary iterator types; just use the basic implementation.
+    std::uninitialized_copy(I, E, Dest);
   }
-  
+
+  /// uninitialized_copy - Copy the range [I, E) onto the uninitialized memory
+  /// starting with "Dest", constructing elements into it as needed.
+  template<typename T1, typename T2>
+  static void uninitialized_copy(T1 *I, T1 *E, T2 *Dest) {
+    // Use memcpy for PODs iterated by pointers (which includes SmallVector
+    // iterators): std::uninitialized_copy optimizes to memmove, but we can
+    // use memcpy here.
+    memcpy(Dest, I, (E-I)*sizeof(T));
+  }
+
   /// grow - double the size of the allocated memory, guaranteeing space for at
   /// least one more element or MinSize if specified.
   void grow(size_t MinSize = 0) {
@@ -501,10 +510,13 @@
     this->uninitialized_copy(I, OldEnd, this->end()-NumOverwritten);
     
     // Replace the overwritten part.
-    std::copy(From, From+NumOverwritten, I);
+    for (; NumOverwritten > 0; --NumOverwritten) {
+      *I = *From;
+      ++I; ++From;
+    }
     
     // Insert the non-overwritten middle part.
-    this->uninitialized_copy(From+NumOverwritten, To, OldEnd);
+    this->uninitialized_copy(From, To, OldEnd);
     return I;
   }
   

Modified: llvm/trunk/unittests/ADT/SmallVectorTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/SmallVectorTest.cpp?rev=99633&r1=99632&r2=99633&view=diff
==============================================================================
--- llvm/trunk/unittests/ADT/SmallVectorTest.cpp (original)
+++ llvm/trunk/unittests/ADT/SmallVectorTest.cpp Fri Mar 26 13:53:37 2010
@@ -14,6 +14,7 @@
 #include "gtest/gtest.h"
 #include "llvm/ADT/SmallVector.h"
 #include <stdarg.h>
+#include <list>
 
 using namespace llvm;
 
@@ -399,4 +400,9 @@
   EXPECT_EQ(4, theVector[3].getValue());
 }
 
+TEST_F(SmallVectorTest, IteratorTest) {
+  std::list<int> L;
+  theVector.insert(theVector.end(), L.begin(), L.end());
+}
+
 }




From ggreif at gmail.com  Fri Mar 26 14:04:42 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Fri, 26 Mar 2010 19:04:42 -0000
Subject: [llvm-commits] [llvm] r99635 -
	/llvm/trunk/docs/ProgrammersManual.html
Message-ID: <20100326190442.9F8B22A6C12C@llvm.org>

Author: ggreif
Date: Fri Mar 26 14:04:42 2010
New Revision: 99635

URL: http://llvm.org/viewvc/llvm-project?rev=99635&view=rev
Log:
http://englishplus.com/grammar/00000296.htm

Modified:
    llvm/trunk/docs/ProgrammersManual.html

Modified: llvm/trunk/docs/ProgrammersManual.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=99635&r1=99634&r2=99635&view=diff
==============================================================================
--- llvm/trunk/docs/ProgrammersManual.html (original)
+++ llvm/trunk/docs/ProgrammersManual.html Fri Mar 26 14:04:42 2010
@@ -1962,7 +1962,7 @@
 </pre>
 </div>
 
-<p>Alternately, it's common to have an instance of the <a
+<p>Alternatively, it's common to have an instance of the <a
 href="/doxygen/classllvm_1_1User.html">User Class</a> and need to know what
 <tt>Value</tt>s are used by it.  The list of all <tt>Value</tt>s used by a
 <tt>User</tt> is known as a <i>use-def</i> chain.  Instances of class




From dpatel at apple.com  Fri Mar 26 14:08:36 2010
From: dpatel at apple.com (Devang Patel)
Date: Fri, 26 Mar 2010 19:08:36 -0000
Subject: [llvm-commits] [llvm] r99636 -
	/llvm/trunk/docs/SourceLevelDebugging.html
Message-ID: <20100326190836.B44DA2A6C12C@llvm.org>

Author: dpatel
Date: Fri Mar 26 14:08:36 2010
New Revision: 99636

URL: http://llvm.org/viewvc/llvm-project?rev=99636&view=rev
Log:
Add a paragram describing how to extract line number information.

Modified:
    llvm/trunk/docs/SourceLevelDebugging.html

Modified: llvm/trunk/docs/SourceLevelDebugging.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=99636&r1=99635&r2=99636&view=diff
==============================================================================
--- llvm/trunk/docs/SourceLevelDebugging.html (original)
+++ llvm/trunk/docs/SourceLevelDebugging.html Fri Mar 26 14:08:36 2010
@@ -1069,6 +1069,18 @@
 </pre>
 </div>
 
+<p>llvm::Instruction provides easy access to metadata attached with an 
+instruction. One can extract line number information encoded in LLVM IR
+using <tt>Instruction::getMetadata()</tt> and 
+<tt>DILocation::getLineNumber()</tt>.
+<pre>
+ if (MDNode *N = I->getMetadata("dbg")) {  // Here I is an LLVM instruction
+   DILocation Loc(N);                      // DILocation is in DebugInfo.h
+   unsigned Line = Loc.getLineNumber();
+   StringRef File = Loc.getFilename();
+   StringRef Dir = Loc.getDirectory();
+ }
+</pre>
 </div>
 
 <!-- ======================================================================= -->




From dalej at apple.com  Fri Mar 26 14:21:26 2010
From: dalej at apple.com (Dale Johannesen)
Date: Fri, 26 Mar 2010 19:21:26 -0000
Subject: [llvm-commits] [llvm] r99637 -
	/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp
Message-ID: <20100326192126.493E62A6C12C@llvm.org>

Author: johannes
Date: Fri Mar 26 14:21:26 2010
New Revision: 99637

URL: http://llvm.org/viewvc/llvm-project?rev=99637&view=rev
Log:
Debug info shouldn't affect kills.


Modified:
    llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp

Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=99637&r1=99636&r2=99637&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Fri Mar 26 14:21:26 2010
@@ -572,6 +572,9 @@
 static void UpdateKills(MachineInstr &MI, const TargetRegisterInfo* TRI,
                         BitVector &RegKills,
                         std::vector<MachineOperand*> &KillOps) {
+  // These do not affect kill info at all.
+  if (MI.isDebugValue())
+    return;
   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI.getOperand(i);
     if (!MO.isReg() || !MO.isUse() || MO.isUndef())




From ggreif at gmail.com  Fri Mar 26 14:30:48 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Fri, 26 Mar 2010 19:30:48 -0000
Subject: [llvm-commits] [llvm] r99638 -
	/llvm/trunk/docs/ProgrammersManual.html
Message-ID: <20100326193048.49CC92A6C12C@llvm.org>

Author: ggreif
Date: Fri Mar 26 14:30:47 2010
New Revision: 99638

URL: http://llvm.org/viewvc/llvm-project?rev=99638&view=rev
Log:
add a blurb on const versions of chain traversals and a word of caution

Modified:
    llvm/trunk/docs/ProgrammersManual.html

Modified: llvm/trunk/docs/ProgrammersManual.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=99638&r1=99637&r2=99638&view=diff
==============================================================================
--- llvm/trunk/docs/ProgrammersManual.html (original)
+++ llvm/trunk/docs/ProgrammersManual.html Fri Mar 26 14:30:47 2010
@@ -1211,14 +1211,14 @@
 
 <div class="doc_text">
 
-<p>SmallPtrSet has all the advantages of SmallSet (and a SmallSet of pointers is 
-transparently implemented with a SmallPtrSet), but also supports iterators.  If
+<p>SmallPtrSet has all the advantages of <tt>SmallSet</tt> (and a <tt>SmallSet</tt> of pointers is 
+transparently implemented with a <tt>SmallPtrSet</tt>), but also supports iterators.  If
 more than 'N' insertions are performed, a single quadratically
 probed hash table is allocated and grows as needed, providing extremely
 efficient access (constant time insertion/deleting/queries with low constant
 factors) and is very stingy with malloc traffic.</p>
 
-<p>Note that, unlike std::set, the iterators of SmallPtrSet are invalidated
+<p>Note that, unlike <tt>std::set</tt>, the iterators of <tt>SmallPtrSet</tt> are invalidated
 whenever an insertion occurs.  Also, the values visited by the iterators are not
 visited in sorted order.</p>
 
@@ -1960,6 +1960,10 @@
     errs() &lt;&lt; *Inst &lt;&lt; "\n";
   }
 </pre>
+Note that dereferencing a <tt>Value::use_iterator</tt is not a very cheap
+operation. Instead of performing <tt>*i</tt> above several times, consider
+doing it only once in the loop body and reusing its result.
+
 </div>
 
 <p>Alternatively, it's common to have an instance of the <a
@@ -1981,11 +1985,13 @@
 </pre>
 </div>
 
-<!--
-  def-use chains ("finding all users of"): Value::use_begin/use_end
-  use-def chains ("finding all values used"): User::op_begin/op_end [op=operand]
--->
-
+<p>Declaring objects as <tt>const</tt> is an important tool of enforcing
+mutation free algorithms (such as analyses etc.). For this purpose above
+iterators come in constant flavors as <tt>Value::const_use_iterator</tt>
+and <tt>Value::const_op_iterator</tt>.  They automatically arise when
+calling <tt>use/op_begin()</tt> on <tt>const Value*</tt>s or
+<tt>const User*</tt>s respectively.  Upon dereferencing, they return
+<tt>const Use*</tt>s. Otherwise the above patterns remain unchanged.
 </div>
 
 <!--_______________________________________________________________________-->




From ggreif at gmail.com  Fri Mar 26 14:35:48 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Fri, 26 Mar 2010 19:35:48 -0000
Subject: [llvm-commits] [llvm] r99640 -
	/llvm/trunk/docs/ProgrammersManual.html
Message-ID: <20100326193548.89F682A6C12C@llvm.org>

Author: ggreif
Date: Fri Mar 26 14:35:48 2010
New Revision: 99640

URL: http://llvm.org/viewvc/llvm-project?rev=99640&view=rev
Log:
fix formatting and a validation fail

Modified:
    llvm/trunk/docs/ProgrammersManual.html

Modified: llvm/trunk/docs/ProgrammersManual.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=99640&r1=99639&r2=99640&view=diff
==============================================================================
--- llvm/trunk/docs/ProgrammersManual.html (original)
+++ llvm/trunk/docs/ProgrammersManual.html Fri Mar 26 14:35:48 2010
@@ -1960,12 +1960,12 @@
     errs() &lt;&lt; *Inst &lt;&lt; "\n";
   }
 </pre>
-Note that dereferencing a <tt>Value::use_iterator</tt is not a very cheap
+</div>
+
+Note that dereferencing a <tt>Value::use_iterator</tt> is not a very cheap
 operation. Instead of performing <tt>*i</tt> above several times, consider
 doing it only once in the loop body and reusing its result.
 
-</div>
-
 <p>Alternatively, it's common to have an instance of the <a
 href="/doxygen/classllvm_1_1User.html">User Class</a> and need to know what
 <tt>Value</tt>s are used by it.  The list of all <tt>Value</tt>s used by a




From gohman at apple.com  Fri Mar 26 14:39:05 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 26 Mar 2010 19:39:05 -0000
Subject: [llvm-commits] [llvm] r99642 -
	/llvm/trunk/docs/ProgrammersManual.html
Message-ID: <20100326193905.A9FD52A6C12C@llvm.org>

Author: djg
Date: Fri Mar 26 14:39:05 2010
New Revision: 99642

URL: http://llvm.org/viewvc/llvm-project?rev=99642&view=rev
Log:
Tell "the rest of the story" about LLVM's iterators' implicit conversions.

Modified:
    llvm/trunk/docs/ProgrammersManual.html

Modified: llvm/trunk/docs/ProgrammersManual.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=99642&r1=99641&r2=99642&view=diff
==============================================================================
--- llvm/trunk/docs/ProgrammersManual.html (original)
+++ llvm/trunk/docs/ProgrammersManual.html Fri Mar 26 14:39:05 2010
@@ -1843,6 +1843,21 @@
 </pre>
 </div>
 
+<p>Unfortunately, these implicit conversions come at a cost; they prevent
+these iterators from conforming to standard iterator conventions, and thus
+from being usable with standard algorithms and containers. For example, it
+prevents the following code, where <tt>B</tt> is a <tt>BasicBlock</tt>,
+from compiling:</p>
+
+<div class="doc_code">
+<pre>
+  llvm::SmallVector&lt;llvm::Instruction *, 16&gt;(B-&gt;begin(), B-&gt;end());
+</pre>
+</div>
+
+<p>Because of this, these implicit conversions may be removed some day,
+and <tt>operator*</tt> changed to return a pointer instead of a reference.
+
 </div>
 
 <!--_______________________________________________________________________-->




From ggreif at gmail.com  Fri Mar 26 14:40:38 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Fri, 26 Mar 2010 19:40:38 -0000
Subject: [llvm-commits] [llvm] r99643 -
	/llvm/trunk/docs/ProgrammersManual.html
Message-ID: <20100326194038.E0EAE2A6C12C@llvm.org>

Author: ggreif
Date: Fri Mar 26 14:40:38 2010
New Revision: 99643

URL: http://llvm.org/viewvc/llvm-project?rev=99643&view=rev
Log:
some more tweaks

Modified:
    llvm/trunk/docs/ProgrammersManual.html

Modified: llvm/trunk/docs/ProgrammersManual.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=99643&r1=99642&r2=99643&view=diff
==============================================================================
--- llvm/trunk/docs/ProgrammersManual.html (original)
+++ llvm/trunk/docs/ProgrammersManual.html Fri Mar 26 14:40:38 2010
@@ -1977,9 +1977,9 @@
 </pre>
 </div>
 
-Note that dereferencing a <tt>Value::use_iterator</tt> is not a very cheap
+<p>Note that dereferencing a <tt>Value::use_iterator</tt> is not a very cheap
 operation. Instead of performing <tt>*i</tt> above several times, consider
-doing it only once in the loop body and reusing its result.
+doing it only once in the loop body and reusing its result.</p>
 
 <p>Alternatively, it's common to have an instance of the <a
 href="/doxygen/classllvm_1_1User.html">User Class</a> and need to know what
@@ -2001,12 +2001,13 @@
 </div>
 
 <p>Declaring objects as <tt>const</tt> is an important tool of enforcing
-mutation free algorithms (such as analyses etc.). For this purpose above
+mutation free algorithms (such as analyses, etc.). For this purpose above
 iterators come in constant flavors as <tt>Value::const_use_iterator</tt>
 and <tt>Value::const_op_iterator</tt>.  They automatically arise when
 calling <tt>use/op_begin()</tt> on <tt>const Value*</tt>s or
 <tt>const User*</tt>s respectively.  Upon dereferencing, they return
-<tt>const Use*</tt>s. Otherwise the above patterns remain unchanged.
+<tt>const Use*</tt>s. Otherwise the above patterns remain unchanged.</p>
+
 </div>
 
 <!--_______________________________________________________________________-->




From gohman at apple.com  Fri Mar 26 14:51:14 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 26 Mar 2010 19:51:14 -0000
Subject: [llvm-commits] [llvm] r99644 -
	/llvm/trunk/docs/ProgrammersManual.html
Message-ID: <20100326195114.E3AE32A6C12C@llvm.org>

Author: djg
Date: Fri Mar 26 14:51:14 2010
New Revision: 99644

URL: http://llvm.org/viewvc/llvm-project?rev=99644&view=rev
Log:
Minor grammar and html fixes.

Modified:
    llvm/trunk/docs/ProgrammersManual.html

Modified: llvm/trunk/docs/ProgrammersManual.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=99644&r1=99643&r2=99644&view=diff
==============================================================================
--- llvm/trunk/docs/ProgrammersManual.html (original)
+++ llvm/trunk/docs/ProgrammersManual.html Fri Mar 26 14:51:14 2010
@@ -1845,8 +1845,8 @@
 
 <p>Unfortunately, these implicit conversions come at a cost; they prevent
 these iterators from conforming to standard iterator conventions, and thus
-from being usable with standard algorithms and containers. For example, it
-prevents the following code, where <tt>B</tt> is a <tt>BasicBlock</tt>,
+from being usable with standard algorithms and containers. For example, they
+prevent the following code, where <tt>B</tt> is a <tt>BasicBlock</tt>,
 from compiling:</p>
 
 <div class="doc_code">
@@ -1856,7 +1856,7 @@
 </div>
 
 <p>Because of this, these implicit conversions may be removed some day,
-and <tt>operator*</tt> changed to return a pointer instead of a reference.
+and <tt>operator*</tt> changed to return a pointer instead of a reference.</p>
 
 </div>
 




From ggreif at gmail.com  Fri Mar 26 14:59:25 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Fri, 26 Mar 2010 19:59:25 -0000
Subject: [llvm-commits] [llvm] r99646 -
	/llvm/trunk/docs/ProgrammersManual.html
Message-ID: <20100326195925.DE1B62A6C12C@llvm.org>

Author: ggreif
Date: Fri Mar 26 14:59:25 2010
New Revision: 99646

URL: http://llvm.org/viewvc/llvm-project?rev=99646&view=rev
Log:
fix iterator name

Modified:
    llvm/trunk/docs/ProgrammersManual.html

Modified: llvm/trunk/docs/ProgrammersManual.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=99646&r1=99645&r2=99646&view=diff
==============================================================================
--- llvm/trunk/docs/ProgrammersManual.html (original)
+++ llvm/trunk/docs/ProgrammersManual.html Fri Mar 26 14:59:25 2010
@@ -3298,7 +3298,7 @@
 <ul>
   <li><tt>Value::use_iterator</tt> - Typedef for iterator over the
 use-list<br>
-    <tt>Value::use_const_iterator</tt> - Typedef for const_iterator over
+    <tt>Value::const_use_iterator</tt> - Typedef for const_iterator over
 the use-list<br>
     <tt>unsigned use_size()</tt> - Returns the number of users of the
 value.<br>




From daniel at zuster.org  Fri Mar 26 16:07:05 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 26 Mar 2010 21:07:05 -0000
Subject: [llvm-commits] [compiler-rt] r99654 -
	/compiler-rt/trunk/make/platform/clang_darwin.mk
Message-ID: <20100326210705.C72862A6C12C@llvm.org>

Author: ddunbar
Date: Fri Mar 26 16:07:05 2010
New Revision: 99654

URL: http://llvm.org/viewvc/llvm-project?rev=99654&view=rev
Log:
Don't build an armv7 slice for now, it has the same stuff as on armv6.

Modified:
    compiler-rt/trunk/make/platform/clang_darwin.mk

Modified: compiler-rt/trunk/make/platform/clang_darwin.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin.mk?rev=99654&r1=99653&r2=99654&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/clang_darwin.mk (original)
+++ compiler-rt/trunk/make/platform/clang_darwin.mk Fri Mar 26 16:07:05 2010
@@ -22,7 +22,11 @@
 
 # Configuration for use with kernel/kexts.
 Configs += cc_kext
-UniversalArchs.cc_kext := armv6 armv7 i386 x86_64
+UniversalArchs.cc_kext := armv6 i386 x86_64
+
+# FIXME: Don't build an armv7 slice currently, they have the same functions.
+#
+#UniversalArchs.cc_kext := armv6 armv7 i386 x86_64
 
 ###
 




From johnny.chen at apple.com  Fri Mar 26 16:26:28 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Fri, 26 Mar 2010 21:26:28 -0000
Subject: [llvm-commits] [llvm] r99655 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrNEON.td
Message-ID: <20100326212628.CF81F2A6C12C@llvm.org>

Author: johnny
Date: Fri Mar 26 16:26:28 2010
New Revision: 99655

URL: http://llvm.org/viewvc/llvm-project?rev=99655&view=rev
Log:
Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).

Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from.  N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.

Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99655&r1=99654&r2=99655&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Mar 26 16:26:28 2010
@@ -67,6 +67,7 @@
 def N2RegVShLFrm   : Format<36>;
 def N2RegVShRFrm   : Format<37>;
 def N3RegFrm       : Format<38>;
+def N3RegVShFrm    : Format<39>;
 
 // Misc flags.
 
@@ -1603,11 +1604,11 @@
   let Inst{4} = op4;
 }
 
-// NEON 3 vector register format.
-class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
-          dag oops, dag iops, InstrItinClass itin,
-          string opc, string dt, string asm, string cstr, list<dag> pattern>
-  : NDataI<oops, iops, N3RegFrm, itin, opc, dt, asm, cstr, pattern> {
+// NEON 3 vector register template, which requires a Format argument.
+class N3Vf<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,bit op4,
+           dag oops, dag iops, Format f, InstrItinClass itin,
+           string opc, string dt, string asm, string cstr, list<dag> pattern>
+  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
   let Inst{24} = op24;
   let Inst{23} = op23;
   let Inst{21-20} = op21_20;
@@ -1616,6 +1617,13 @@
   let Inst{4} = op4;
 }
 
+// NEON 3 vector register format.
+class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
+          dag oops, dag iops, InstrItinClass itin,
+          string opc, string dt, string asm, string cstr, list<dag> pattern>
+  : N3Vf<op24, op23, op21_20, op11_8, op6, op4, oops, iops, N3RegFrm, itin,
+         opc, dt, asm, cstr, pattern>;
+
 // Same as N3V except it doesn't have a data type suffix.
 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
            bit op4,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99655&r1=99654&r2=99655&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Mar 26 16:26:28 2010
@@ -1594,6 +1594,60 @@
                       v2i64, v2i64, IntOp, Commutable>;
 }
 
+// N3VSh_QHSD is similar to N3VInt_QHSD, except that it is for 3-Register Vector
+// Shift Instructions (N3RegVShFrm), which do not follow the N3RegFrm's operand
+// order of D:Vd N:Vn M:Vm.
+//
+// The operand order of N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the
+// first src operand).
+class N3VDSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
+             InstrItinClass itin, string OpcodeStr, string Dt,
+             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
+  : N3Vf<op24, op23, op21_20, op11_8, 0, op4,
+         (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegVShFrm,
+         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
+         [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
+  let isCommutable = Commutable;
+}
+class N3VQSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
+             InstrItinClass itin, string OpcodeStr, string Dt,
+             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
+  : N3Vf<op24, op23, op21_20, op11_8, 1, op4,
+         (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegVShFrm,
+         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
+         [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
+  let isCommutable = Commutable;
+}
+multiclass N3VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
+                      InstrItinClass itinD16, InstrItinClass itinD32,
+                      InstrItinClass itinQ16, InstrItinClass itinQ32,
+                      string OpcodeStr, string Dt,
+                      Intrinsic IntOp, bit Commutable> {
+  def v4i16 : N3VDSh<op24, op23, 0b01, op11_8, op4, itinD16,
+                     OpcodeStr, !strconcat(Dt, "16"),
+                     v4i16, v4i16, IntOp, Commutable>;
+  def v2i32 : N3VDSh<op24, op23, 0b10, op11_8, op4, itinD32,
+                     OpcodeStr, !strconcat(Dt, "32"),
+                     v2i32, v2i32, IntOp, Commutable>;
+  def v8i16 : N3VQSh<op24, op23, 0b01, op11_8, op4, itinQ16,
+                     OpcodeStr, !strconcat(Dt, "16"),
+                     v8i16, v8i16, IntOp, Commutable>;
+  def v4i32 : N3VQSh<op24, op23, 0b10, op11_8, op4, itinQ32,
+                     OpcodeStr, !strconcat(Dt, "32"),
+                     v4i32, v4i32, IntOp, Commutable>;
+  def v8i8  : N3VDSh<op24, op23, 0b00, op11_8, op4, itinD16,
+                     OpcodeStr, !strconcat(Dt, "8"),
+                     v8i8, v8i8, IntOp, Commutable>;
+  def v16i8 : N3VQSh<op24, op23, 0b00, op11_8, op4, itinQ16,
+                     OpcodeStr, !strconcat(Dt, "8"),
+                     v16i8, v16i8, IntOp, Commutable>;
+  def v1i64 : N3VDSh<op24, op23, 0b11, op11_8, op4,
+                     itinD32, OpcodeStr, !strconcat(Dt, "64"),
+                     v1i64, v1i64, IntOp, Commutable>;
+  def v2i64 : N3VQSh<op24, op23, 0b11, op11_8, op4,
+                     itinQ32, OpcodeStr, !strconcat(Dt, "64"),
+                     v2i64, v2i64, IntOp, Commutable>;
+}
 
 // Neon Narrowing 3-register vector intrinsics,
 //   source operand element sizes of 16, 32 and 64 bits:
@@ -2575,10 +2629,10 @@
 // Vector Shifts.
 
 //   VSHL     : Vector Shift
-defm VSHLs    : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
-                            IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
-defm VSHLu    : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
-                            IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
+defm VSHLs    : N3VSh_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
+                           IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
+defm VSHLu    : N3VSh_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
+                           IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
 //   VSHL     : Vector Shift Left (Immediate)
 defm VSHLi    : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
                            N2RegVShLFrm>;
@@ -2612,10 +2666,10 @@
                            NEONvshrn>;
 
 //   VRSHL    : Vector Rounding Shift
-defm VRSHLs   : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
-                            IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
-defm VRSHLu   : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
-                            IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
+defm VRSHLs   : N3VSh_QHSD<0,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
+                           IIC_VSHLi4Q,"vrshl", "s", int_arm_neon_vrshifts,0>;
+defm VRSHLu   : N3VSh_QHSD<1,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
+                           IIC_VSHLi4Q,"vrshl", "u", int_arm_neon_vrshiftu,0>;
 //   VRSHR    : Vector Rounding Shift Right
 defm VRSHRs   : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
                            N2RegVShRFrm>;
@@ -2627,10 +2681,10 @@
                            NEONvrshrn>;
 
 //   VQSHL    : Vector Saturating Shift
-defm VQSHLs   : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
-                            IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
-defm VQSHLu   : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
-                            IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
+defm VQSHLs   : N3VSh_QHSD<0,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
+                           IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
+defm VQSHLu   : N3VSh_QHSD<1,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
+                           IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
 //   VQSHL    : Vector Saturating Shift Left (Immediate)
 defm VQSHLsi  : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
                            N2RegVShLFrm>;
@@ -2651,12 +2705,12 @@
                            NEONvqshrnsu>;
 
 //   VQRSHL   : Vector Saturating Rounding Shift
-defm VQRSHLs  : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
-                            IIC_VSHLi4Q, "vqrshl", "s",
-                            int_arm_neon_vqrshifts, 0>;
-defm VQRSHLu  : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
-                            IIC_VSHLi4Q, "vqrshl", "u",
-                            int_arm_neon_vqrshiftu, 0>;
+defm VQRSHLs  : N3VSh_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
+                           IIC_VSHLi4Q, "vqrshl", "s",
+                           int_arm_neon_vqrshifts, 0>;
+defm VQRSHLu  : N3VSh_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
+                           IIC_VSHLi4Q, "vqrshl", "u",
+                           int_arm_neon_vqrshiftu, 0>;
 
 //   VQRSHRN  : Vector Saturating Rounding Shift Right and Narrow
 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",




From asl at math.spbu.ru  Fri Mar 26 16:32:15 2010
From: asl at math.spbu.ru (Anton Korobeynikov)
Date: Fri, 26 Mar 2010 21:32:15 -0000
Subject: [llvm-commits] [llvm] r99656 - in /llvm/trunk:
 include/llvm/CodeGen/RuntimeLibcalls.h
 lib/CodeGen/SelectionDAG/TargetLowering.cpp
Message-ID: <20100326213215.1DF8E2A6C12C@llvm.org>

Author: asl
Date: Fri Mar 26 16:32:14 2010
New Revision: 99656

URL: http://llvm.org/viewvc/llvm-project?rev=99656&view=rev
Log:
Add few missed libcalls and correct names for others.

Modified:
    llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Modified: llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h?rev=99656&r1=99655&r2=99656&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h Fri Mar 26 16:32:14 2010
@@ -169,6 +169,8 @@
     FPTOSINT_F32_I32,
     FPTOSINT_F32_I64,
     FPTOSINT_F32_I128,
+    FPTOSINT_F64_I8,
+    FPTOSINT_F64_I16,
     FPTOSINT_F64_I32,
     FPTOSINT_F64_I64,
     FPTOSINT_F64_I128,
@@ -183,6 +185,8 @@
     FPTOUINT_F32_I32,
     FPTOUINT_F32_I64,
     FPTOUINT_F32_I128,
+    FPTOUINT_F64_I8,
+    FPTOUINT_F64_I16,
     FPTOUINT_F64_I32,
     FPTOUINT_F64_I64,
     FPTOUINT_F64_I128,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=99656&r1=99655&r2=99656&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Mar 26 16:32:14 2010
@@ -186,11 +186,13 @@
   Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
   Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
   Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
-  Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8";
-  Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16";
+  Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
+  Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
   Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
   Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
   Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
+  Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
+  Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
   Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
   Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
   Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
@@ -200,11 +202,13 @@
   Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
   Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
   Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
-  Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8";
-  Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16";
+  Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
+  Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
   Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
   Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
   Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
+  Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
+  Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
   Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
   Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
   Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
@@ -314,6 +318,10 @@
     if (RetVT == MVT::i128)
       return FPTOSINT_F32_I128;
   } else if (OpVT == MVT::f64) {
+    if (RetVT == MVT::i8)
+      return FPTOSINT_F64_I8;
+    if (RetVT == MVT::i16)
+      return FPTOSINT_F64_I16;
     if (RetVT == MVT::i32)
       return FPTOSINT_F64_I32;
     if (RetVT == MVT::i64)
@@ -353,6 +361,10 @@
     if (RetVT == MVT::i128)
       return FPTOUINT_F32_I128;
   } else if (OpVT == MVT::f64) {
+    if (RetVT == MVT::i8)
+      return FPTOUINT_F64_I8;
+    if (RetVT == MVT::i16)
+      return FPTOUINT_F64_I16;
     if (RetVT == MVT::i32)
       return FPTOUINT_F64_I32;
     if (RetVT == MVT::i64)




From bob.wilson at apple.com  Fri Mar 26 17:02:11 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Fri, 26 Mar 2010 15:02:11 -0700
Subject: [llvm-commits] [llvm] r99655 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrNEON.td
In-Reply-To: <20100326212628.CF81F2A6C12C@llvm.org>
References: <20100326212628.CF81F2A6C12C@llvm.org>
Message-ID: <7C09000F-9EC9-4AF0-8D70-DAD80F89229A@apple.com>

I would rather push the format argument into all the N3VInt instructions.  We already have too many classes and multiclasses for Neon, so I really don't want to create any more.  Can you do that or do you want me to do it?

On Mar 26, 2010, at 2:26 PM, Johnny Chen wrote:

> Author: johnny
> Date: Fri Mar 26 16:26:28 2010
> New Revision: 99655
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99655&view=rev
> Log:
> Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
> follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
> N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
> 
> Add a parent class N3Vf which requires passing a Format argument and which the
> N3V class is modified to inherit from.  N3V class represents the "normal"
> 3-Register NEON Instructions with N3RegFrm.
> 
> Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
> Instructions and replace 8 invocations with it.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99655&r1=99654&r2=99655&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Mar 26 16:26:28 2010
> @@ -67,6 +67,7 @@
> def N2RegVShLFrm   : Format<36>;
> def N2RegVShRFrm   : Format<37>;
> def N3RegFrm       : Format<38>;
> +def N3RegVShFrm    : Format<39>;
> 
> // Misc flags.
> 
> @@ -1603,11 +1604,11 @@
>   let Inst{4} = op4;
> }
> 
> -// NEON 3 vector register format.
> -class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
> -          dag oops, dag iops, InstrItinClass itin,
> -          string opc, string dt, string asm, string cstr, list<dag> pattern>
> -  : NDataI<oops, iops, N3RegFrm, itin, opc, dt, asm, cstr, pattern> {
> +// NEON 3 vector register template, which requires a Format argument.
> +class N3Vf<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,bit op4,
> +           dag oops, dag iops, Format f, InstrItinClass itin,
> +           string opc, string dt, string asm, string cstr, list<dag> pattern>
> +  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
>   let Inst{24} = op24;
>   let Inst{23} = op23;
>   let Inst{21-20} = op21_20;
> @@ -1616,6 +1617,13 @@
>   let Inst{4} = op4;
> }
> 
> +// NEON 3 vector register format.
> +class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
> +          dag oops, dag iops, InstrItinClass itin,
> +          string opc, string dt, string asm, string cstr, list<dag> pattern>
> +  : N3Vf<op24, op23, op21_20, op11_8, op6, op4, oops, iops, N3RegFrm, itin,
> +         opc, dt, asm, cstr, pattern>;
> +
> // Same as N3V except it doesn't have a data type suffix.
> class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
>            bit op4,
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99655&r1=99654&r2=99655&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Mar 26 16:26:28 2010
> @@ -1594,6 +1594,60 @@
>                       v2i64, v2i64, IntOp, Commutable>;
> }
> 
> +// N3VSh_QHSD is similar to N3VInt_QHSD, except that it is for 3-Register Vector
> +// Shift Instructions (N3RegVShFrm), which do not follow the N3RegFrm's operand
> +// order of D:Vd N:Vn M:Vm.
> +//
> +// The operand order of N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the
> +// first src operand).
> +class N3VDSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
> +             InstrItinClass itin, string OpcodeStr, string Dt,
> +             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
> +  : N3Vf<op24, op23, op21_20, op11_8, 0, op4,
> +         (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegVShFrm,
> +         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
> +         [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
> +  let isCommutable = Commutable;
> +}
> +class N3VQSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
> +             InstrItinClass itin, string OpcodeStr, string Dt,
> +             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
> +  : N3Vf<op24, op23, op21_20, op11_8, 1, op4,
> +         (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegVShFrm,
> +         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
> +         [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
> +  let isCommutable = Commutable;
> +}
> +multiclass N3VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
> +                      InstrItinClass itinD16, InstrItinClass itinD32,
> +                      InstrItinClass itinQ16, InstrItinClass itinQ32,
> +                      string OpcodeStr, string Dt,
> +                      Intrinsic IntOp, bit Commutable> {
> +  def v4i16 : N3VDSh<op24, op23, 0b01, op11_8, op4, itinD16,
> +                     OpcodeStr, !strconcat(Dt, "16"),
> +                     v4i16, v4i16, IntOp, Commutable>;
> +  def v2i32 : N3VDSh<op24, op23, 0b10, op11_8, op4, itinD32,
> +                     OpcodeStr, !strconcat(Dt, "32"),
> +                     v2i32, v2i32, IntOp, Commutable>;
> +  def v8i16 : N3VQSh<op24, op23, 0b01, op11_8, op4, itinQ16,
> +                     OpcodeStr, !strconcat(Dt, "16"),
> +                     v8i16, v8i16, IntOp, Commutable>;
> +  def v4i32 : N3VQSh<op24, op23, 0b10, op11_8, op4, itinQ32,
> +                     OpcodeStr, !strconcat(Dt, "32"),
> +                     v4i32, v4i32, IntOp, Commutable>;
> +  def v8i8  : N3VDSh<op24, op23, 0b00, op11_8, op4, itinD16,
> +                     OpcodeStr, !strconcat(Dt, "8"),
> +                     v8i8, v8i8, IntOp, Commutable>;
> +  def v16i8 : N3VQSh<op24, op23, 0b00, op11_8, op4, itinQ16,
> +                     OpcodeStr, !strconcat(Dt, "8"),
> +                     v16i8, v16i8, IntOp, Commutable>;
> +  def v1i64 : N3VDSh<op24, op23, 0b11, op11_8, op4,
> +                     itinD32, OpcodeStr, !strconcat(Dt, "64"),
> +                     v1i64, v1i64, IntOp, Commutable>;
> +  def v2i64 : N3VQSh<op24, op23, 0b11, op11_8, op4,
> +                     itinQ32, OpcodeStr, !strconcat(Dt, "64"),
> +                     v2i64, v2i64, IntOp, Commutable>;
> +}
> 
> // Neon Narrowing 3-register vector intrinsics,
> //   source operand element sizes of 16, 32 and 64 bits:
> @@ -2575,10 +2629,10 @@
> // Vector Shifts.
> 
> //   VSHL     : Vector Shift
> -defm VSHLs    : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
> -                            IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
> -defm VSHLu    : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
> -                            IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
> +defm VSHLs    : N3VSh_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
> +                           IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
> +defm VSHLu    : N3VSh_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
> +                           IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
> //   VSHL     : Vector Shift Left (Immediate)
> defm VSHLi    : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
>                            N2RegVShLFrm>;
> @@ -2612,10 +2666,10 @@
>                            NEONvshrn>;
> 
> //   VRSHL    : Vector Rounding Shift
> -defm VRSHLs   : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
> -                            IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
> -defm VRSHLu   : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
> -                            IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
> +defm VRSHLs   : N3VSh_QHSD<0,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
> +                           IIC_VSHLi4Q,"vrshl", "s", int_arm_neon_vrshifts,0>;
> +defm VRSHLu   : N3VSh_QHSD<1,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
> +                           IIC_VSHLi4Q,"vrshl", "u", int_arm_neon_vrshiftu,0>;
> //   VRSHR    : Vector Rounding Shift Right
> defm VRSHRs   : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
>                            N2RegVShRFrm>;
> @@ -2627,10 +2681,10 @@
>                            NEONvrshrn>;
> 
> //   VQSHL    : Vector Saturating Shift
> -defm VQSHLs   : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
> -                            IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
> -defm VQSHLu   : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
> -                            IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
> +defm VQSHLs   : N3VSh_QHSD<0,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
> +                           IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
> +defm VQSHLu   : N3VSh_QHSD<1,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
> +                           IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
> //   VQSHL    : Vector Saturating Shift Left (Immediate)
> defm VQSHLsi  : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
>                            N2RegVShLFrm>;
> @@ -2651,12 +2705,12 @@
>                            NEONvqshrnsu>;
> 
> //   VQRSHL   : Vector Saturating Rounding Shift
> -defm VQRSHLs  : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
> -                            IIC_VSHLi4Q, "vqrshl", "s",
> -                            int_arm_neon_vqrshifts, 0>;
> -defm VQRSHLu  : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
> -                            IIC_VSHLi4Q, "vqrshl", "u",
> -                            int_arm_neon_vqrshiftu, 0>;
> +defm VQRSHLs  : N3VSh_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
> +                           IIC_VSHLi4Q, "vqrshl", "s",
> +                           int_arm_neon_vqrshifts, 0>;
> +defm VQRSHLu  : N3VSh_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
> +                           IIC_VSHLi4Q, "vqrshl", "u",
> +                           int_arm_neon_vqrshiftu, 0>;
> 
> //   VQRSHRN  : Vector Saturating Rounding Shift Right and Narrow
> defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From johnny.chen at apple.com  Fri Mar 26 17:10:49 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Fri, 26 Mar 2010 15:10:49 -0700
Subject: [llvm-commits] [llvm] r99655 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrNEON.td
In-Reply-To: <7C09000F-9EC9-4AF0-8D70-DAD80F89229A@apple.com>
References: <20100326212628.CF81F2A6C12C@llvm.org>
	<7C09000F-9EC9-4AF0-8D70-DAD80F89229A@apple.com>
Message-ID: <62BA517B-BA50-4764-BFFC-7C695B78C0DD@apple.com>

There are 18 invocations of the N3VInt_* multiclasses, which means 18 places to push the format arguments.
Do you still think this is the way to go than invoking 8 N3VSh_QHSD for 3-register vector shift clusters?

There will be 24 places where we need to pass in the format argument.

If you still think so, I will do the modification, since I'm the one who caused it in the first place. :-)

On Mar 26, 2010, at 3:02 PM, Bob Wilson wrote:

> I would rather push the format argument into all the N3VInt instructions.  We already have too many classes and multiclasses for Neon, so I really don't want to create any more.  Can you do that or do you want me to do it?
> 
> On Mar 26, 2010, at 2:26 PM, Johnny Chen wrote:
> 
>> Author: johnny
>> Date: Fri Mar 26 16:26:28 2010
>> New Revision: 99655
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99655&view=rev
>> Log:
>> Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
>> follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
>> N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
>> 
>> Add a parent class N3Vf which requires passing a Format argument and which the
>> N3V class is modified to inherit from.  N3V class represents the "normal"
>> 3-Register NEON Instructions with N3RegFrm.
>> 
>> Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
>> Instructions and replace 8 invocations with it.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>   llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99655&r1=99654&r2=99655&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Mar 26 16:26:28 2010
>> @@ -67,6 +67,7 @@
>> def N2RegVShLFrm   : Format<36>;
>> def N2RegVShRFrm   : Format<37>;
>> def N3RegFrm       : Format<38>;
>> +def N3RegVShFrm    : Format<39>;
>> 
>> // Misc flags.
>> 
>> @@ -1603,11 +1604,11 @@
>>  let Inst{4} = op4;
>> }
>> 
>> -// NEON 3 vector register format.
>> -class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
>> -          dag oops, dag iops, InstrItinClass itin,
>> -          string opc, string dt, string asm, string cstr, list<dag> pattern>
>> -  : NDataI<oops, iops, N3RegFrm, itin, opc, dt, asm, cstr, pattern> {
>> +// NEON 3 vector register template, which requires a Format argument.
>> +class N3Vf<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,bit op4,
>> +           dag oops, dag iops, Format f, InstrItinClass itin,
>> +           string opc, string dt, string asm, string cstr, list<dag> pattern>
>> +  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
>>  let Inst{24} = op24;
>>  let Inst{23} = op23;
>>  let Inst{21-20} = op21_20;
>> @@ -1616,6 +1617,13 @@
>>  let Inst{4} = op4;
>> }
>> 
>> +// NEON 3 vector register format.
>> +class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
>> +          dag oops, dag iops, InstrItinClass itin,
>> +          string opc, string dt, string asm, string cstr, list<dag> pattern>
>> +  : N3Vf<op24, op23, op21_20, op11_8, op6, op4, oops, iops, N3RegFrm, itin,
>> +         opc, dt, asm, cstr, pattern>;
>> +
>> // Same as N3V except it doesn't have a data type suffix.
>> class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
>>           bit op4,
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99655&r1=99654&r2=99655&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Mar 26 16:26:28 2010
>> @@ -1594,6 +1594,60 @@
>>                      v2i64, v2i64, IntOp, Commutable>;
>> }
>> 
>> +// N3VSh_QHSD is similar to N3VInt_QHSD, except that it is for 3-Register Vector
>> +// Shift Instructions (N3RegVShFrm), which do not follow the N3RegFrm's operand
>> +// order of D:Vd N:Vn M:Vm.
>> +//
>> +// The operand order of N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the
>> +// first src operand).
>> +class N3VDSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
>> +             InstrItinClass itin, string OpcodeStr, string Dt,
>> +             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
>> +  : N3Vf<op24, op23, op21_20, op11_8, 0, op4,
>> +         (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegVShFrm,
>> +         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
>> +         [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
>> +  let isCommutable = Commutable;
>> +}
>> +class N3VQSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
>> +             InstrItinClass itin, string OpcodeStr, string Dt,
>> +             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
>> +  : N3Vf<op24, op23, op21_20, op11_8, 1, op4,
>> +         (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegVShFrm,
>> +         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
>> +         [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
>> +  let isCommutable = Commutable;
>> +}
>> +multiclass N3VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
>> +                      InstrItinClass itinD16, InstrItinClass itinD32,
>> +                      InstrItinClass itinQ16, InstrItinClass itinQ32,
>> +                      string OpcodeStr, string Dt,
>> +                      Intrinsic IntOp, bit Commutable> {
>> +  def v4i16 : N3VDSh<op24, op23, 0b01, op11_8, op4, itinD16,
>> +                     OpcodeStr, !strconcat(Dt, "16"),
>> +                     v4i16, v4i16, IntOp, Commutable>;
>> +  def v2i32 : N3VDSh<op24, op23, 0b10, op11_8, op4, itinD32,
>> +                     OpcodeStr, !strconcat(Dt, "32"),
>> +                     v2i32, v2i32, IntOp, Commutable>;
>> +  def v8i16 : N3VQSh<op24, op23, 0b01, op11_8, op4, itinQ16,
>> +                     OpcodeStr, !strconcat(Dt, "16"),
>> +                     v8i16, v8i16, IntOp, Commutable>;
>> +  def v4i32 : N3VQSh<op24, op23, 0b10, op11_8, op4, itinQ32,
>> +                     OpcodeStr, !strconcat(Dt, "32"),
>> +                     v4i32, v4i32, IntOp, Commutable>;
>> +  def v8i8  : N3VDSh<op24, op23, 0b00, op11_8, op4, itinD16,
>> +                     OpcodeStr, !strconcat(Dt, "8"),
>> +                     v8i8, v8i8, IntOp, Commutable>;
>> +  def v16i8 : N3VQSh<op24, op23, 0b00, op11_8, op4, itinQ16,
>> +                     OpcodeStr, !strconcat(Dt, "8"),
>> +                     v16i8, v16i8, IntOp, Commutable>;
>> +  def v1i64 : N3VDSh<op24, op23, 0b11, op11_8, op4,
>> +                     itinD32, OpcodeStr, !strconcat(Dt, "64"),
>> +                     v1i64, v1i64, IntOp, Commutable>;
>> +  def v2i64 : N3VQSh<op24, op23, 0b11, op11_8, op4,
>> +                     itinQ32, OpcodeStr, !strconcat(Dt, "64"),
>> +                     v2i64, v2i64, IntOp, Commutable>;
>> +}
>> 
>> // Neon Narrowing 3-register vector intrinsics,
>> //   source operand element sizes of 16, 32 and 64 bits:
>> @@ -2575,10 +2629,10 @@
>> // Vector Shifts.
>> 
>> //   VSHL     : Vector Shift
>> -defm VSHLs    : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>> -                            IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
>> -defm VSHLu    : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>> -                            IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
>> +defm VSHLs    : N3VSh_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>> +                           IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
>> +defm VSHLu    : N3VSh_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>> +                           IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
>> //   VSHL     : Vector Shift Left (Immediate)
>> defm VSHLi    : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
>>                           N2RegVShLFrm>;
>> @@ -2612,10 +2666,10 @@
>>                           NEONvshrn>;
>> 
>> //   VRSHL    : Vector Rounding Shift
>> -defm VRSHLs   : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>> -                            IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
>> -defm VRSHLu   : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>> -                            IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
>> +defm VRSHLs   : N3VSh_QHSD<0,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>> +                           IIC_VSHLi4Q,"vrshl", "s", int_arm_neon_vrshifts,0>;
>> +defm VRSHLu   : N3VSh_QHSD<1,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>> +                           IIC_VSHLi4Q,"vrshl", "u", int_arm_neon_vrshiftu,0>;
>> //   VRSHR    : Vector Rounding Shift Right
>> defm VRSHRs   : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
>>                           N2RegVShRFrm>;
>> @@ -2627,10 +2681,10 @@
>>                           NEONvrshrn>;
>> 
>> //   VQSHL    : Vector Saturating Shift
>> -defm VQSHLs   : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>> -                            IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
>> -defm VQSHLu   : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>> -                            IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
>> +defm VQSHLs   : N3VSh_QHSD<0,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>> +                           IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
>> +defm VQSHLu   : N3VSh_QHSD<1,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>> +                           IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
>> //   VQSHL    : Vector Saturating Shift Left (Immediate)
>> defm VQSHLsi  : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
>>                           N2RegVShLFrm>;
>> @@ -2651,12 +2705,12 @@
>>                           NEONvqshrnsu>;
>> 
>> //   VQRSHL   : Vector Saturating Rounding Shift
>> -defm VQRSHLs  : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>> -                            IIC_VSHLi4Q, "vqrshl", "s",
>> -                            int_arm_neon_vqrshifts, 0>;
>> -defm VQRSHLu  : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>> -                            IIC_VSHLi4Q, "vqrshl", "u",
>> -                            int_arm_neon_vqrshiftu, 0>;
>> +defm VQRSHLs  : N3VSh_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>> +                           IIC_VSHLi4Q, "vqrshl", "s",
>> +                           int_arm_neon_vqrshifts, 0>;
>> +defm VQRSHLu  : N3VSh_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>> +                           IIC_VSHLi4Q, "vqrshl", "u",
>> +                           int_arm_neon_vqrshiftu, 0>;
>> 
>> //   VQRSHRN  : Vector Saturating Rounding Shift Right and Narrow
>> defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 




From jiahong.chen at me.com  Fri Mar 26 17:12:59 2010
From: jiahong.chen at me.com (Johnny Chen)
Date: Fri, 26 Mar 2010 15:12:59 -0700
Subject: [llvm-commits] [llvm] r99655 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrNEON.td
In-Reply-To: <62BA517B-BA50-4764-BFFC-7C695B78C0DD@apple.com>
References: <20100326212628.CF81F2A6C12C@llvm.org>
	<7C09000F-9EC9-4AF0-8D70-DAD80F89229A@apple.com>
	<62BA517B-BA50-4764-BFFC-7C695B78C0DD@apple.com>
Message-ID: <004F58DA-946E-454C-A26E-A368749BB54F@me.com>

Wrong math, 26 places.

On Mar 26, 2010, at 3:10 PM, Johnny Chen wrote:

> There are 18 invocations of the N3VInt_* multiclasses, which means 18 places to push the format arguments.
> Do you still think this is the way to go than invoking 8 N3VSh_QHSD for 3-register vector shift clusters?
> 
> There will be 24 places where we need to pass in the format argument.
> 
> If you still think so, I will do the modification, since I'm the one who caused it in the first place. :-)
> 
> On Mar 26, 2010, at 3:02 PM, Bob Wilson wrote:
> 
>> I would rather push the format argument into all the N3VInt instructions.  We already have too many classes and multiclasses for Neon, so I really don't want to create any more.  Can you do that or do you want me to do it?
>> 
>> On Mar 26, 2010, at 2:26 PM, Johnny Chen wrote:
>> 
>>> Author: johnny
>>> Date: Fri Mar 26 16:26:28 2010
>>> New Revision: 99655
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=99655&view=rev
>>> Log:
>>> Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
>>> follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
>>> N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
>>> 
>>> Add a parent class N3Vf which requires passing a Format argument and which the
>>> N3V class is modified to inherit from.  N3V class represents the "normal"
>>> 3-Register NEON Instructions with N3RegFrm.
>>> 
>>> Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
>>> Instructions and replace 8 invocations with it.
>>> 
>>> Modified:
>>>  llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>>  llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99655&r1=99654&r2=99655&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Mar 26 16:26:28 2010
>>> @@ -67,6 +67,7 @@
>>> def N2RegVShLFrm   : Format<36>;
>>> def N2RegVShRFrm   : Format<37>;
>>> def N3RegFrm       : Format<38>;
>>> +def N3RegVShFrm    : Format<39>;
>>> 
>>> // Misc flags.
>>> 
>>> @@ -1603,11 +1604,11 @@
>>> let Inst{4} = op4;
>>> }
>>> 
>>> -// NEON 3 vector register format.
>>> -class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
>>> -          dag oops, dag iops, InstrItinClass itin,
>>> -          string opc, string dt, string asm, string cstr, list<dag> pattern>
>>> -  : NDataI<oops, iops, N3RegFrm, itin, opc, dt, asm, cstr, pattern> {
>>> +// NEON 3 vector register template, which requires a Format argument.
>>> +class N3Vf<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,bit op4,
>>> +           dag oops, dag iops, Format f, InstrItinClass itin,
>>> +           string opc, string dt, string asm, string cstr, list<dag> pattern>
>>> +  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
>>> let Inst{24} = op24;
>>> let Inst{23} = op23;
>>> let Inst{21-20} = op21_20;
>>> @@ -1616,6 +1617,13 @@
>>> let Inst{4} = op4;
>>> }
>>> 
>>> +// NEON 3 vector register format.
>>> +class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
>>> +          dag oops, dag iops, InstrItinClass itin,
>>> +          string opc, string dt, string asm, string cstr, list<dag> pattern>
>>> +  : N3Vf<op24, op23, op21_20, op11_8, op6, op4, oops, iops, N3RegFrm, itin,
>>> +         opc, dt, asm, cstr, pattern>;
>>> +
>>> // Same as N3V except it doesn't have a data type suffix.
>>> class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
>>>          bit op4,
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99655&r1=99654&r2=99655&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Mar 26 16:26:28 2010
>>> @@ -1594,6 +1594,60 @@
>>>                     v2i64, v2i64, IntOp, Commutable>;
>>> }
>>> 
>>> +// N3VSh_QHSD is similar to N3VInt_QHSD, except that it is for 3-Register Vector
>>> +// Shift Instructions (N3RegVShFrm), which do not follow the N3RegFrm's operand
>>> +// order of D:Vd N:Vn M:Vm.
>>> +//
>>> +// The operand order of N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the
>>> +// first src operand).
>>> +class N3VDSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
>>> +             InstrItinClass itin, string OpcodeStr, string Dt,
>>> +             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
>>> +  : N3Vf<op24, op23, op21_20, op11_8, 0, op4,
>>> +         (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegVShFrm,
>>> +         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
>>> +         [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
>>> +  let isCommutable = Commutable;
>>> +}
>>> +class N3VQSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
>>> +             InstrItinClass itin, string OpcodeStr, string Dt,
>>> +             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
>>> +  : N3Vf<op24, op23, op21_20, op11_8, 1, op4,
>>> +         (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegVShFrm,
>>> +         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
>>> +         [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
>>> +  let isCommutable = Commutable;
>>> +}
>>> +multiclass N3VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
>>> +                      InstrItinClass itinD16, InstrItinClass itinD32,
>>> +                      InstrItinClass itinQ16, InstrItinClass itinQ32,
>>> +                      string OpcodeStr, string Dt,
>>> +                      Intrinsic IntOp, bit Commutable> {
>>> +  def v4i16 : N3VDSh<op24, op23, 0b01, op11_8, op4, itinD16,
>>> +                     OpcodeStr, !strconcat(Dt, "16"),
>>> +                     v4i16, v4i16, IntOp, Commutable>;
>>> +  def v2i32 : N3VDSh<op24, op23, 0b10, op11_8, op4, itinD32,
>>> +                     OpcodeStr, !strconcat(Dt, "32"),
>>> +                     v2i32, v2i32, IntOp, Commutable>;
>>> +  def v8i16 : N3VQSh<op24, op23, 0b01, op11_8, op4, itinQ16,
>>> +                     OpcodeStr, !strconcat(Dt, "16"),
>>> +                     v8i16, v8i16, IntOp, Commutable>;
>>> +  def v4i32 : N3VQSh<op24, op23, 0b10, op11_8, op4, itinQ32,
>>> +                     OpcodeStr, !strconcat(Dt, "32"),
>>> +                     v4i32, v4i32, IntOp, Commutable>;
>>> +  def v8i8  : N3VDSh<op24, op23, 0b00, op11_8, op4, itinD16,
>>> +                     OpcodeStr, !strconcat(Dt, "8"),
>>> +                     v8i8, v8i8, IntOp, Commutable>;
>>> +  def v16i8 : N3VQSh<op24, op23, 0b00, op11_8, op4, itinQ16,
>>> +                     OpcodeStr, !strconcat(Dt, "8"),
>>> +                     v16i8, v16i8, IntOp, Commutable>;
>>> +  def v1i64 : N3VDSh<op24, op23, 0b11, op11_8, op4,
>>> +                     itinD32, OpcodeStr, !strconcat(Dt, "64"),
>>> +                     v1i64, v1i64, IntOp, Commutable>;
>>> +  def v2i64 : N3VQSh<op24, op23, 0b11, op11_8, op4,
>>> +                     itinQ32, OpcodeStr, !strconcat(Dt, "64"),
>>> +                     v2i64, v2i64, IntOp, Commutable>;
>>> +}
>>> 
>>> // Neon Narrowing 3-register vector intrinsics,
>>> //   source operand element sizes of 16, 32 and 64 bits:
>>> @@ -2575,10 +2629,10 @@
>>> // Vector Shifts.
>>> 
>>> //   VSHL     : Vector Shift
>>> -defm VSHLs    : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>> -                            IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
>>> -defm VSHLu    : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>> -                            IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
>>> +defm VSHLs    : N3VSh_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>> +                           IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
>>> +defm VSHLu    : N3VSh_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>> +                           IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
>>> //   VSHL     : Vector Shift Left (Immediate)
>>> defm VSHLi    : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
>>>                          N2RegVShLFrm>;
>>> @@ -2612,10 +2666,10 @@
>>>                          NEONvshrn>;
>>> 
>>> //   VRSHL    : Vector Rounding Shift
>>> -defm VRSHLs   : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> -                            IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
>>> -defm VRSHLu   : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> -                            IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
>>> +defm VRSHLs   : N3VSh_QHSD<0,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> +                           IIC_VSHLi4Q,"vrshl", "s", int_arm_neon_vrshifts,0>;
>>> +defm VRSHLu   : N3VSh_QHSD<1,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> +                           IIC_VSHLi4Q,"vrshl", "u", int_arm_neon_vrshiftu,0>;
>>> //   VRSHR    : Vector Rounding Shift Right
>>> defm VRSHRs   : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
>>>                          N2RegVShRFrm>;
>>> @@ -2627,10 +2681,10 @@
>>>                          NEONvrshrn>;
>>> 
>>> //   VQSHL    : Vector Saturating Shift
>>> -defm VQSHLs   : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> -                            IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
>>> -defm VQSHLu   : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> -                            IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
>>> +defm VQSHLs   : N3VSh_QHSD<0,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> +                           IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
>>> +defm VQSHLu   : N3VSh_QHSD<1,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> +                           IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
>>> //   VQSHL    : Vector Saturating Shift Left (Immediate)
>>> defm VQSHLsi  : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
>>>                          N2RegVShLFrm>;
>>> @@ -2651,12 +2705,12 @@
>>>                          NEONvqshrnsu>;
>>> 
>>> //   VQRSHL   : Vector Saturating Rounding Shift
>>> -defm VQRSHLs  : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> -                            IIC_VSHLi4Q, "vqrshl", "s",
>>> -                            int_arm_neon_vqrshifts, 0>;
>>> -defm VQRSHLu  : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> -                            IIC_VSHLi4Q, "vqrshl", "u",
>>> -                            int_arm_neon_vqrshiftu, 0>;
>>> +defm VQRSHLs  : N3VSh_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> +                           IIC_VSHLi4Q, "vqrshl", "s",
>>> +                           int_arm_neon_vqrshifts, 0>;
>>> +defm VQRSHLu  : N3VSh_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> +                           IIC_VSHLi4Q, "vqrshl", "u",
>>> +                           int_arm_neon_vqrshiftu, 0>;
>>> 
>>> //   VQRSHRN  : Vector Saturating Rounding Shift Right and Narrow
>>> defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
> 



From sabre at nondot.org  Fri Mar 26 17:17:24 2010
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 26 Mar 2010 22:17:24 -0000
Subject: [llvm-commits] [llvm] r99658 - /llvm/trunk/lib/System/Unix/Mutex.inc
Message-ID: <20100326221724.3B6052A6C12C@llvm.org>

Author: lattner
Date: Fri Mar 26 17:17:24 2010
New Revision: 99658

URL: http://llvm.org/viewvc/llvm-project?rev=99658&view=rev
Log:
remove a constructor implementation that isn't declared
in the header.  How can both clang and gcc accept this?

PR6703

Modified:
    llvm/trunk/lib/System/Unix/Mutex.inc

Modified: llvm/trunk/lib/System/Unix/Mutex.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Mutex.inc?rev=99658&r1=99657&r2=99658&view=diff
==============================================================================
--- llvm/trunk/lib/System/Unix/Mutex.inc (original)
+++ llvm/trunk/lib/System/Unix/Mutex.inc Fri Mar 26 17:17:24 2010
@@ -29,12 +29,6 @@
 }
 
 bool 
-MutexImpl::MutexImpl()
-{
-  return true;
-}
-
-bool 
 MutexImpl::release()
 {
   return true;




From johnny.chen at apple.com  Fri Mar 26 17:28:56 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Fri, 26 Mar 2010 22:28:56 -0000
Subject: [llvm-commits] [llvm] r99659 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrNEON.td
Message-ID: <20100326222856.70D012A6C12C@llvm.org>

Author: johnny
Date: Fri Mar 26 17:28:56 2010
New Revision: 99659

URL: http://llvm.org/viewvc/llvm-project?rev=99659&view=rev
Log:
Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8}
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.

Modify VEXTd and VEXTq classes to use the format.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99659&r1=99658&r2=99659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Mar 26 17:28:56 2010
@@ -68,6 +68,7 @@
 def N2RegVShRFrm   : Format<37>;
 def N3RegFrm       : Format<38>;
 def N3RegVShFrm    : Format<39>;
+def NVExtFrm       : Format<40>;
 
 // Misc flags.
 

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99659&r1=99658&r2=99659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Mar 26 17:28:56 2010
@@ -3253,18 +3253,18 @@
 //   VEXT     : Vector Extract
 
 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
-  : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
-        (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
-        OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
-        [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
-                                      (Ty DPR:$rhs), imm:$index)))]>;
+  : N3Vf<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
+         (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NVExtFrm,
+         IIC_VEXTD, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
+         [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
+                                       (Ty DPR:$rhs), imm:$index)))]>;
 
 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
-  : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
-        (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
-        OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
-        [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
-                                      (Ty QPR:$rhs), imm:$index)))]>;
+  : N3Vf<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
+         (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NVExtFrm,
+         IIC_VEXTQ, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
+         [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
+                                       (Ty QPR:$rhs), imm:$index)))]>;
 
 def VEXTd8  : VEXTd<"vext", "8",  v8i8>;
 def VEXTd16 : VEXTd<"vext", "16", v4i16>;




From bob.wilson at apple.com  Fri Mar 26 17:34:05 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Fri, 26 Mar 2010 15:34:05 -0700
Subject: [llvm-commits] [llvm] r99655 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrNEON.td
In-Reply-To: <62BA517B-BA50-4764-BFFC-7C695B78C0DD@apple.com>
References: <20100326212628.CF81F2A6C12C@llvm.org>
	<7C09000F-9EC9-4AF0-8D70-DAD80F89229A@apple.com>
	<62BA517B-BA50-4764-BFFC-7C695B78C0DD@apple.com>
Message-ID: <D6E7BD16-777C-4F3D-805C-17F287A9BB13@apple.com>


On Mar 26, 2010, at 3:10 PM, Johnny Chen wrote:

> There are 18 invocations of the N3VInt_* multiclasses, which means 18 places to push the format arguments.
> Do you still think this is the way to go than invoking 8 N3VSh_QHSD for 3-register vector shift clusters?
> 
> There will be 24 places where we need to pass in the format argument.

Yes (even if it is 26 places).  I generally prefer to keep the instructions as succinct as  possible, but not at the cost of duplicating all those classes and multiclasses.


> 
> If you still think so, I will do the modification, since I'm the one who caused it in the first place. :-)

Great.  Please do then.  Thanks!

> 
> On Mar 26, 2010, at 3:02 PM, Bob Wilson wrote:
> 
>> I would rather push the format argument into all the N3VInt instructions.  We already have too many classes and multiclasses for Neon, so I really don't want to create any more.  Can you do that or do you want me to do it?
>> 
>> On Mar 26, 2010, at 2:26 PM, Johnny Chen wrote:
>> 
>>> Author: johnny
>>> Date: Fri Mar 26 16:26:28 2010
>>> New Revision: 99655
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=99655&view=rev
>>> Log:
>>> Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
>>> follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
>>> N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
>>> 
>>> Add a parent class N3Vf which requires passing a Format argument and which the
>>> N3V class is modified to inherit from.  N3V class represents the "normal"
>>> 3-Register NEON Instructions with N3RegFrm.
>>> 
>>> Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
>>> Instructions and replace 8 invocations with it.
>>> 
>>> Modified:
>>>  llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>>  llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99655&r1=99654&r2=99655&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Mar 26 16:26:28 2010
>>> @@ -67,6 +67,7 @@
>>> def N2RegVShLFrm   : Format<36>;
>>> def N2RegVShRFrm   : Format<37>;
>>> def N3RegFrm       : Format<38>;
>>> +def N3RegVShFrm    : Format<39>;
>>> 
>>> // Misc flags.
>>> 
>>> @@ -1603,11 +1604,11 @@
>>> let Inst{4} = op4;
>>> }
>>> 
>>> -// NEON 3 vector register format.
>>> -class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
>>> -          dag oops, dag iops, InstrItinClass itin,
>>> -          string opc, string dt, string asm, string cstr, list<dag> pattern>
>>> -  : NDataI<oops, iops, N3RegFrm, itin, opc, dt, asm, cstr, pattern> {
>>> +// NEON 3 vector register template, which requires a Format argument.
>>> +class N3Vf<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,bit op4,
>>> +           dag oops, dag iops, Format f, InstrItinClass itin,
>>> +           string opc, string dt, string asm, string cstr, list<dag> pattern>
>>> +  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
>>> let Inst{24} = op24;
>>> let Inst{23} = op23;
>>> let Inst{21-20} = op21_20;
>>> @@ -1616,6 +1617,13 @@
>>> let Inst{4} = op4;
>>> }
>>> 
>>> +// NEON 3 vector register format.
>>> +class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
>>> +          dag oops, dag iops, InstrItinClass itin,
>>> +          string opc, string dt, string asm, string cstr, list<dag> pattern>
>>> +  : N3Vf<op24, op23, op21_20, op11_8, op6, op4, oops, iops, N3RegFrm, itin,
>>> +         opc, dt, asm, cstr, pattern>;
>>> +
>>> // Same as N3V except it doesn't have a data type suffix.
>>> class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
>>>          bit op4,
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99655&r1=99654&r2=99655&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Mar 26 16:26:28 2010
>>> @@ -1594,6 +1594,60 @@
>>>                     v2i64, v2i64, IntOp, Commutable>;
>>> }
>>> 
>>> +// N3VSh_QHSD is similar to N3VInt_QHSD, except that it is for 3-Register Vector
>>> +// Shift Instructions (N3RegVShFrm), which do not follow the N3RegFrm's operand
>>> +// order of D:Vd N:Vn M:Vm.
>>> +//
>>> +// The operand order of N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the
>>> +// first src operand).
>>> +class N3VDSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
>>> +             InstrItinClass itin, string OpcodeStr, string Dt,
>>> +             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
>>> +  : N3Vf<op24, op23, op21_20, op11_8, 0, op4,
>>> +         (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegVShFrm,
>>> +         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
>>> +         [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
>>> +  let isCommutable = Commutable;
>>> +}
>>> +class N3VQSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
>>> +             InstrItinClass itin, string OpcodeStr, string Dt,
>>> +             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
>>> +  : N3Vf<op24, op23, op21_20, op11_8, 1, op4,
>>> +         (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegVShFrm,
>>> +         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
>>> +         [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
>>> +  let isCommutable = Commutable;
>>> +}
>>> +multiclass N3VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
>>> +                      InstrItinClass itinD16, InstrItinClass itinD32,
>>> +                      InstrItinClass itinQ16, InstrItinClass itinQ32,
>>> +                      string OpcodeStr, string Dt,
>>> +                      Intrinsic IntOp, bit Commutable> {
>>> +  def v4i16 : N3VDSh<op24, op23, 0b01, op11_8, op4, itinD16,
>>> +                     OpcodeStr, !strconcat(Dt, "16"),
>>> +                     v4i16, v4i16, IntOp, Commutable>;
>>> +  def v2i32 : N3VDSh<op24, op23, 0b10, op11_8, op4, itinD32,
>>> +                     OpcodeStr, !strconcat(Dt, "32"),
>>> +                     v2i32, v2i32, IntOp, Commutable>;
>>> +  def v8i16 : N3VQSh<op24, op23, 0b01, op11_8, op4, itinQ16,
>>> +                     OpcodeStr, !strconcat(Dt, "16"),
>>> +                     v8i16, v8i16, IntOp, Commutable>;
>>> +  def v4i32 : N3VQSh<op24, op23, 0b10, op11_8, op4, itinQ32,
>>> +                     OpcodeStr, !strconcat(Dt, "32"),
>>> +                     v4i32, v4i32, IntOp, Commutable>;
>>> +  def v8i8  : N3VDSh<op24, op23, 0b00, op11_8, op4, itinD16,
>>> +                     OpcodeStr, !strconcat(Dt, "8"),
>>> +                     v8i8, v8i8, IntOp, Commutable>;
>>> +  def v16i8 : N3VQSh<op24, op23, 0b00, op11_8, op4, itinQ16,
>>> +                     OpcodeStr, !strconcat(Dt, "8"),
>>> +                     v16i8, v16i8, IntOp, Commutable>;
>>> +  def v1i64 : N3VDSh<op24, op23, 0b11, op11_8, op4,
>>> +                     itinD32, OpcodeStr, !strconcat(Dt, "64"),
>>> +                     v1i64, v1i64, IntOp, Commutable>;
>>> +  def v2i64 : N3VQSh<op24, op23, 0b11, op11_8, op4,
>>> +                     itinQ32, OpcodeStr, !strconcat(Dt, "64"),
>>> +                     v2i64, v2i64, IntOp, Commutable>;
>>> +}
>>> 
>>> // Neon Narrowing 3-register vector intrinsics,
>>> //   source operand element sizes of 16, 32 and 64 bits:
>>> @@ -2575,10 +2629,10 @@
>>> // Vector Shifts.
>>> 
>>> //   VSHL     : Vector Shift
>>> -defm VSHLs    : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>> -                            IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
>>> -defm VSHLu    : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>> -                            IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
>>> +defm VSHLs    : N3VSh_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>> +                           IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
>>> +defm VSHLu    : N3VSh_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>> +                           IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
>>> //   VSHL     : Vector Shift Left (Immediate)
>>> defm VSHLi    : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
>>>                          N2RegVShLFrm>;
>>> @@ -2612,10 +2666,10 @@
>>>                          NEONvshrn>;
>>> 
>>> //   VRSHL    : Vector Rounding Shift
>>> -defm VRSHLs   : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> -                            IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
>>> -defm VRSHLu   : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> -                            IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
>>> +defm VRSHLs   : N3VSh_QHSD<0,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> +                           IIC_VSHLi4Q,"vrshl", "s", int_arm_neon_vrshifts,0>;
>>> +defm VRSHLu   : N3VSh_QHSD<1,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> +                           IIC_VSHLi4Q,"vrshl", "u", int_arm_neon_vrshiftu,0>;
>>> //   VRSHR    : Vector Rounding Shift Right
>>> defm VRSHRs   : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
>>>                          N2RegVShRFrm>;
>>> @@ -2627,10 +2681,10 @@
>>>                          NEONvrshrn>;
>>> 
>>> //   VQSHL    : Vector Saturating Shift
>>> -defm VQSHLs   : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> -                            IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
>>> -defm VQSHLu   : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> -                            IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
>>> +defm VQSHLs   : N3VSh_QHSD<0,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> +                           IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
>>> +defm VQSHLu   : N3VSh_QHSD<1,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> +                           IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
>>> //   VQSHL    : Vector Saturating Shift Left (Immediate)
>>> defm VQSHLsi  : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
>>>                          N2RegVShLFrm>;
>>> @@ -2651,12 +2705,12 @@
>>>                          NEONvqshrnsu>;
>>> 
>>> //   VQRSHL   : Vector Saturating Rounding Shift
>>> -defm VQRSHLs  : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> -                            IIC_VSHLi4Q, "vqrshl", "s",
>>> -                            int_arm_neon_vqrshifts, 0>;
>>> -defm VQRSHLu  : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> -                            IIC_VSHLi4Q, "vqrshl", "u",
>>> -                            int_arm_neon_vqrshiftu, 0>;
>>> +defm VQRSHLs  : N3VSh_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> +                           IIC_VSHLi4Q, "vqrshl", "s",
>>> +                           int_arm_neon_vqrshifts, 0>;
>>> +defm VQRSHLu  : N3VSh_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>> +                           IIC_VSHLi4Q, "vqrshl", "u",
>>> +                           int_arm_neon_vqrshiftu, 0>;
>>> 
>>> //   VQRSHRN  : Vector Saturating Rounding Shift Right and Narrow
>>> defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
> 




From johnny.chen at apple.com  Fri Mar 26 17:46:36 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Fri, 26 Mar 2010 15:46:36 -0700
Subject: [llvm-commits] [llvm] r99655 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrNEON.td
In-Reply-To: <D6E7BD16-777C-4F3D-805C-17F287A9BB13@apple.com>
References: <20100326212628.CF81F2A6C12C@llvm.org>
	<7C09000F-9EC9-4AF0-8D70-DAD80F89229A@apple.com>
	<62BA517B-BA50-4764-BFFC-7C695B78C0DD@apple.com>
	<D6E7BD16-777C-4F3D-805C-17F287A9BB13@apple.com>
Message-ID: <73E97949-CF5E-4CE3-B9E0-FD2F40FC7128@apple.com>

This also means that the 26 invocations of N3VDInt<> and 8 invocations of N3VQInt<> will be
modified to pass in N3RegFrm.  Do you STILL think it is better that way?

On Mar 26, 2010, at 3:34 PM, Bob Wilson wrote:

> 
> On Mar 26, 2010, at 3:10 PM, Johnny Chen wrote:
> 
>> There are 18 invocations of the N3VInt_* multiclasses, which means 18 places to push the format arguments.
>> Do you still think this is the way to go than invoking 8 N3VSh_QHSD for 3-register vector shift clusters?
>> 
>> There will be 24 places where we need to pass in the format argument.
> 
> Yes (even if it is 26 places).  I generally prefer to keep the instructions as succinct as  possible, but not at the cost of duplicating all those classes and multiclasses.
> 
> 
>> 
>> If you still think so, I will do the modification, since I'm the one who caused it in the first place. :-)
> 
> Great.  Please do then.  Thanks!
> 
>> 
>> On Mar 26, 2010, at 3:02 PM, Bob Wilson wrote:
>> 
>>> I would rather push the format argument into all the N3VInt instructions.  We already have too many classes and multiclasses for Neon, so I really don't want to create any more.  Can you do that or do you want me to do it?
>>> 
>>> On Mar 26, 2010, at 2:26 PM, Johnny Chen wrote:
>>> 
>>>> Author: johnny
>>>> Date: Fri Mar 26 16:26:28 2010
>>>> New Revision: 99655
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=99655&view=rev
>>>> Log:
>>>> Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
>>>> follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
>>>> N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
>>>> 
>>>> Add a parent class N3Vf which requires passing a Format argument and which the
>>>> N3V class is modified to inherit from.  N3V class represents the "normal"
>>>> 3-Register NEON Instructions with N3RegFrm.
>>>> 
>>>> Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
>>>> Instructions and replace 8 invocations with it.
>>>> 
>>>> Modified:
>>>> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>>> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>>> 
>>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99655&r1=99654&r2=99655&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Mar 26 16:26:28 2010
>>>> @@ -67,6 +67,7 @@
>>>> def N2RegVShLFrm   : Format<36>;
>>>> def N2RegVShRFrm   : Format<37>;
>>>> def N3RegFrm       : Format<38>;
>>>> +def N3RegVShFrm    : Format<39>;
>>>> 
>>>> // Misc flags.
>>>> 
>>>> @@ -1603,11 +1604,11 @@
>>>> let Inst{4} = op4;
>>>> }
>>>> 
>>>> -// NEON 3 vector register format.
>>>> -class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
>>>> -          dag oops, dag iops, InstrItinClass itin,
>>>> -          string opc, string dt, string asm, string cstr, list<dag> pattern>
>>>> -  : NDataI<oops, iops, N3RegFrm, itin, opc, dt, asm, cstr, pattern> {
>>>> +// NEON 3 vector register template, which requires a Format argument.
>>>> +class N3Vf<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,bit op4,
>>>> +           dag oops, dag iops, Format f, InstrItinClass itin,
>>>> +           string opc, string dt, string asm, string cstr, list<dag> pattern>
>>>> +  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
>>>> let Inst{24} = op24;
>>>> let Inst{23} = op23;
>>>> let Inst{21-20} = op21_20;
>>>> @@ -1616,6 +1617,13 @@
>>>> let Inst{4} = op4;
>>>> }
>>>> 
>>>> +// NEON 3 vector register format.
>>>> +class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
>>>> +          dag oops, dag iops, InstrItinClass itin,
>>>> +          string opc, string dt, string asm, string cstr, list<dag> pattern>
>>>> +  : N3Vf<op24, op23, op21_20, op11_8, op6, op4, oops, iops, N3RegFrm, itin,
>>>> +         opc, dt, asm, cstr, pattern>;
>>>> +
>>>> // Same as N3V except it doesn't have a data type suffix.
>>>> class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
>>>>         bit op4,
>>>> 
>>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99655&r1=99654&r2=99655&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Mar 26 16:26:28 2010
>>>> @@ -1594,6 +1594,60 @@
>>>>                    v2i64, v2i64, IntOp, Commutable>;
>>>> }
>>>> 
>>>> +// N3VSh_QHSD is similar to N3VInt_QHSD, except that it is for 3-Register Vector
>>>> +// Shift Instructions (N3RegVShFrm), which do not follow the N3RegFrm's operand
>>>> +// order of D:Vd N:Vn M:Vm.
>>>> +//
>>>> +// The operand order of N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the
>>>> +// first src operand).
>>>> +class N3VDSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
>>>> +             InstrItinClass itin, string OpcodeStr, string Dt,
>>>> +             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
>>>> +  : N3Vf<op24, op23, op21_20, op11_8, 0, op4,
>>>> +         (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegVShFrm,
>>>> +         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
>>>> +         [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
>>>> +  let isCommutable = Commutable;
>>>> +}
>>>> +class N3VQSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
>>>> +             InstrItinClass itin, string OpcodeStr, string Dt,
>>>> +             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
>>>> +  : N3Vf<op24, op23, op21_20, op11_8, 1, op4,
>>>> +         (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegVShFrm,
>>>> +         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
>>>> +         [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
>>>> +  let isCommutable = Commutable;
>>>> +}
>>>> +multiclass N3VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
>>>> +                      InstrItinClass itinD16, InstrItinClass itinD32,
>>>> +                      InstrItinClass itinQ16, InstrItinClass itinQ32,
>>>> +                      string OpcodeStr, string Dt,
>>>> +                      Intrinsic IntOp, bit Commutable> {
>>>> +  def v4i16 : N3VDSh<op24, op23, 0b01, op11_8, op4, itinD16,
>>>> +                     OpcodeStr, !strconcat(Dt, "16"),
>>>> +                     v4i16, v4i16, IntOp, Commutable>;
>>>> +  def v2i32 : N3VDSh<op24, op23, 0b10, op11_8, op4, itinD32,
>>>> +                     OpcodeStr, !strconcat(Dt, "32"),
>>>> +                     v2i32, v2i32, IntOp, Commutable>;
>>>> +  def v8i16 : N3VQSh<op24, op23, 0b01, op11_8, op4, itinQ16,
>>>> +                     OpcodeStr, !strconcat(Dt, "16"),
>>>> +                     v8i16, v8i16, IntOp, Commutable>;
>>>> +  def v4i32 : N3VQSh<op24, op23, 0b10, op11_8, op4, itinQ32,
>>>> +                     OpcodeStr, !strconcat(Dt, "32"),
>>>> +                     v4i32, v4i32, IntOp, Commutable>;
>>>> +  def v8i8  : N3VDSh<op24, op23, 0b00, op11_8, op4, itinD16,
>>>> +                     OpcodeStr, !strconcat(Dt, "8"),
>>>> +                     v8i8, v8i8, IntOp, Commutable>;
>>>> +  def v16i8 : N3VQSh<op24, op23, 0b00, op11_8, op4, itinQ16,
>>>> +                     OpcodeStr, !strconcat(Dt, "8"),
>>>> +                     v16i8, v16i8, IntOp, Commutable>;
>>>> +  def v1i64 : N3VDSh<op24, op23, 0b11, op11_8, op4,
>>>> +                     itinD32, OpcodeStr, !strconcat(Dt, "64"),
>>>> +                     v1i64, v1i64, IntOp, Commutable>;
>>>> +  def v2i64 : N3VQSh<op24, op23, 0b11, op11_8, op4,
>>>> +                     itinQ32, OpcodeStr, !strconcat(Dt, "64"),
>>>> +                     v2i64, v2i64, IntOp, Commutable>;
>>>> +}
>>>> 
>>>> // Neon Narrowing 3-register vector intrinsics,
>>>> //   source operand element sizes of 16, 32 and 64 bits:
>>>> @@ -2575,10 +2629,10 @@
>>>> // Vector Shifts.
>>>> 
>>>> //   VSHL     : Vector Shift
>>>> -defm VSHLs    : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>>> -                            IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
>>>> -defm VSHLu    : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>>> -                            IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
>>>> +defm VSHLs    : N3VSh_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>>> +                           IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
>>>> +defm VSHLu    : N3VSh_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>>> +                           IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
>>>> //   VSHL     : Vector Shift Left (Immediate)
>>>> defm VSHLi    : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
>>>>                         N2RegVShLFrm>;
>>>> @@ -2612,10 +2666,10 @@
>>>>                         NEONvshrn>;
>>>> 
>>>> //   VRSHL    : Vector Rounding Shift
>>>> -defm VRSHLs   : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>> -                            IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
>>>> -defm VRSHLu   : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>> -                            IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
>>>> +defm VRSHLs   : N3VSh_QHSD<0,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>> +                           IIC_VSHLi4Q,"vrshl", "s", int_arm_neon_vrshifts,0>;
>>>> +defm VRSHLu   : N3VSh_QHSD<1,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>> +                           IIC_VSHLi4Q,"vrshl", "u", int_arm_neon_vrshiftu,0>;
>>>> //   VRSHR    : Vector Rounding Shift Right
>>>> defm VRSHRs   : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
>>>>                         N2RegVShRFrm>;
>>>> @@ -2627,10 +2681,10 @@
>>>>                         NEONvrshrn>;
>>>> 
>>>> //   VQSHL    : Vector Saturating Shift
>>>> -defm VQSHLs   : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>> -                            IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
>>>> -defm VQSHLu   : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>> -                            IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
>>>> +defm VQSHLs   : N3VSh_QHSD<0,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>> +                           IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
>>>> +defm VQSHLu   : N3VSh_QHSD<1,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>> +                           IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
>>>> //   VQSHL    : Vector Saturating Shift Left (Immediate)
>>>> defm VQSHLsi  : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
>>>>                         N2RegVShLFrm>;
>>>> @@ -2651,12 +2705,12 @@
>>>>                         NEONvqshrnsu>;
>>>> 
>>>> //   VQRSHL   : Vector Saturating Rounding Shift
>>>> -defm VQRSHLs  : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>> -                            IIC_VSHLi4Q, "vqrshl", "s",
>>>> -                            int_arm_neon_vqrshifts, 0>;
>>>> -defm VQRSHLu  : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>> -                            IIC_VSHLi4Q, "vqrshl", "u",
>>>> -                            int_arm_neon_vqrshiftu, 0>;
>>>> +defm VQRSHLs  : N3VSh_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>> +                           IIC_VSHLi4Q, "vqrshl", "s",
>>>> +                           int_arm_neon_vqrshifts, 0>;
>>>> +defm VQRSHLu  : N3VSh_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>> +                           IIC_VSHLi4Q, "vqrshl", "u",
>>>> +                           int_arm_neon_vqrshiftu, 0>;
>>>> 
>>>> //   VQRSHRN  : Vector Saturating Rounding Shift Right and Narrow
>>>> defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
>>>> 
>>>> 
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>> 
>> 
> 




From bob.wilson at apple.com  Fri Mar 26 17:50:48 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Fri, 26 Mar 2010 15:50:48 -0700
Subject: [llvm-commits] [llvm] r99655 - in /llvm/trunk/lib/Target/ARM:
	ARMInstrFormats.td ARMInstrNEON.td
In-Reply-To: <73E97949-CF5E-4CE3-B9E0-FD2F40FC7128@apple.com>
References: <20100326212628.CF81F2A6C12C@llvm.org>
	<7C09000F-9EC9-4AF0-8D70-DAD80F89229A@apple.com>
	<62BA517B-BA50-4764-BFFC-7C695B78C0DD@apple.com>
	<D6E7BD16-777C-4F3D-805C-17F287A9BB13@apple.com>
	<73E97949-CF5E-4CE3-B9E0-FD2F40FC7128@apple.com>
Message-ID: <EEC28001-6017-454E-8129-3C29377D8EAD@apple.com>

It is OK.  Compare it to the way that instruction itineraries are specified in most instructions.  If it works out to specify a format in the class, that's great, but I don't (generally) want to add new classes just because of differing format values.

On Mar 26, 2010, at 3:46 PM, Johnny Chen wrote:

> This also means that the 26 invocations of N3VDInt<> and 8 invocations of N3VQInt<> will be
> modified to pass in N3RegFrm.  Do you STILL think it is better that way?
> 
> On Mar 26, 2010, at 3:34 PM, Bob Wilson wrote:
> 
>> 
>> On Mar 26, 2010, at 3:10 PM, Johnny Chen wrote:
>> 
>>> There are 18 invocations of the N3VInt_* multiclasses, which means 18 places to push the format arguments.
>>> Do you still think this is the way to go than invoking 8 N3VSh_QHSD for 3-register vector shift clusters?
>>> 
>>> There will be 24 places where we need to pass in the format argument.
>> 
>> Yes (even if it is 26 places).  I generally prefer to keep the instructions as succinct as  possible, but not at the cost of duplicating all those classes and multiclasses.
>> 
>> 
>>> 
>>> If you still think so, I will do the modification, since I'm the one who caused it in the first place. :-)
>> 
>> Great.  Please do then.  Thanks!
>> 
>>> 
>>> On Mar 26, 2010, at 3:02 PM, Bob Wilson wrote:
>>> 
>>>> I would rather push the format argument into all the N3VInt instructions.  We already have too many classes and multiclasses for Neon, so I really don't want to create any more.  Can you do that or do you want me to do it?
>>>> 
>>>> On Mar 26, 2010, at 2:26 PM, Johnny Chen wrote:
>>>> 
>>>>> Author: johnny
>>>>> Date: Fri Mar 26 16:26:28 2010
>>>>> New Revision: 99655
>>>>> 
>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=99655&view=rev
>>>>> Log:
>>>>> Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
>>>>> follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
>>>>> N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
>>>>> 
>>>>> Add a parent class N3Vf which requires passing a Format argument and which the
>>>>> N3V class is modified to inherit from.  N3V class represents the "normal"
>>>>> 3-Register NEON Instructions with N3RegFrm.
>>>>> 
>>>>> Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
>>>>> Instructions and replace 8 invocations with it.
>>>>> 
>>>>> Modified:
>>>>> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>>>> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>>>> 
>>>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99655&r1=99654&r2=99655&view=diff
>>>>> ==============================================================================
>>>>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>>>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Mar 26 16:26:28 2010
>>>>> @@ -67,6 +67,7 @@
>>>>> def N2RegVShLFrm   : Format<36>;
>>>>> def N2RegVShRFrm   : Format<37>;
>>>>> def N3RegFrm       : Format<38>;
>>>>> +def N3RegVShFrm    : Format<39>;
>>>>> 
>>>>> // Misc flags.
>>>>> 
>>>>> @@ -1603,11 +1604,11 @@
>>>>> let Inst{4} = op4;
>>>>> }
>>>>> 
>>>>> -// NEON 3 vector register format.
>>>>> -class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
>>>>> -          dag oops, dag iops, InstrItinClass itin,
>>>>> -          string opc, string dt, string asm, string cstr, list<dag> pattern>
>>>>> -  : NDataI<oops, iops, N3RegFrm, itin, opc, dt, asm, cstr, pattern> {
>>>>> +// NEON 3 vector register template, which requires a Format argument.
>>>>> +class N3Vf<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,bit op4,
>>>>> +           dag oops, dag iops, Format f, InstrItinClass itin,
>>>>> +           string opc, string dt, string asm, string cstr, list<dag> pattern>
>>>>> +  : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
>>>>> let Inst{24} = op24;
>>>>> let Inst{23} = op23;
>>>>> let Inst{21-20} = op21_20;
>>>>> @@ -1616,6 +1617,13 @@
>>>>> let Inst{4} = op4;
>>>>> }
>>>>> 
>>>>> +// NEON 3 vector register format.
>>>>> +class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
>>>>> +          dag oops, dag iops, InstrItinClass itin,
>>>>> +          string opc, string dt, string asm, string cstr, list<dag> pattern>
>>>>> +  : N3Vf<op24, op23, op21_20, op11_8, op6, op4, oops, iops, N3RegFrm, itin,
>>>>> +         opc, dt, asm, cstr, pattern>;
>>>>> +
>>>>> // Same as N3V except it doesn't have a data type suffix.
>>>>> class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
>>>>>        bit op4,
>>>>> 
>>>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99655&r1=99654&r2=99655&view=diff
>>>>> ==============================================================================
>>>>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>>>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Mar 26 16:26:28 2010
>>>>> @@ -1594,6 +1594,60 @@
>>>>>                   v2i64, v2i64, IntOp, Commutable>;
>>>>> }
>>>>> 
>>>>> +// N3VSh_QHSD is similar to N3VInt_QHSD, except that it is for 3-Register Vector
>>>>> +// Shift Instructions (N3RegVShFrm), which do not follow the N3RegFrm's operand
>>>>> +// order of D:Vd N:Vn M:Vm.
>>>>> +//
>>>>> +// The operand order of N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the
>>>>> +// first src operand).
>>>>> +class N3VDSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
>>>>> +             InstrItinClass itin, string OpcodeStr, string Dt,
>>>>> +             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
>>>>> +  : N3Vf<op24, op23, op21_20, op11_8, 0, op4,
>>>>> +         (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegVShFrm,
>>>>> +         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
>>>>> +         [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
>>>>> +  let isCommutable = Commutable;
>>>>> +}
>>>>> +class N3VQSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
>>>>> +             InstrItinClass itin, string OpcodeStr, string Dt,
>>>>> +             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
>>>>> +  : N3Vf<op24, op23, op21_20, op11_8, 1, op4,
>>>>> +         (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegVShFrm,
>>>>> +         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
>>>>> +         [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
>>>>> +  let isCommutable = Commutable;
>>>>> +}
>>>>> +multiclass N3VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
>>>>> +                      InstrItinClass itinD16, InstrItinClass itinD32,
>>>>> +                      InstrItinClass itinQ16, InstrItinClass itinQ32,
>>>>> +                      string OpcodeStr, string Dt,
>>>>> +                      Intrinsic IntOp, bit Commutable> {
>>>>> +  def v4i16 : N3VDSh<op24, op23, 0b01, op11_8, op4, itinD16,
>>>>> +                     OpcodeStr, !strconcat(Dt, "16"),
>>>>> +                     v4i16, v4i16, IntOp, Commutable>;
>>>>> +  def v2i32 : N3VDSh<op24, op23, 0b10, op11_8, op4, itinD32,
>>>>> +                     OpcodeStr, !strconcat(Dt, "32"),
>>>>> +                     v2i32, v2i32, IntOp, Commutable>;
>>>>> +  def v8i16 : N3VQSh<op24, op23, 0b01, op11_8, op4, itinQ16,
>>>>> +                     OpcodeStr, !strconcat(Dt, "16"),
>>>>> +                     v8i16, v8i16, IntOp, Commutable>;
>>>>> +  def v4i32 : N3VQSh<op24, op23, 0b10, op11_8, op4, itinQ32,
>>>>> +                     OpcodeStr, !strconcat(Dt, "32"),
>>>>> +                     v4i32, v4i32, IntOp, Commutable>;
>>>>> +  def v8i8  : N3VDSh<op24, op23, 0b00, op11_8, op4, itinD16,
>>>>> +                     OpcodeStr, !strconcat(Dt, "8"),
>>>>> +                     v8i8, v8i8, IntOp, Commutable>;
>>>>> +  def v16i8 : N3VQSh<op24, op23, 0b00, op11_8, op4, itinQ16,
>>>>> +                     OpcodeStr, !strconcat(Dt, "8"),
>>>>> +                     v16i8, v16i8, IntOp, Commutable>;
>>>>> +  def v1i64 : N3VDSh<op24, op23, 0b11, op11_8, op4,
>>>>> +                     itinD32, OpcodeStr, !strconcat(Dt, "64"),
>>>>> +                     v1i64, v1i64, IntOp, Commutable>;
>>>>> +  def v2i64 : N3VQSh<op24, op23, 0b11, op11_8, op4,
>>>>> +                     itinQ32, OpcodeStr, !strconcat(Dt, "64"),
>>>>> +                     v2i64, v2i64, IntOp, Commutable>;
>>>>> +}
>>>>> 
>>>>> // Neon Narrowing 3-register vector intrinsics,
>>>>> //   source operand element sizes of 16, 32 and 64 bits:
>>>>> @@ -2575,10 +2629,10 @@
>>>>> // Vector Shifts.
>>>>> 
>>>>> //   VSHL     : Vector Shift
>>>>> -defm VSHLs    : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>>>> -                            IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
>>>>> -defm VSHLu    : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>>>> -                            IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
>>>>> +defm VSHLs    : N3VSh_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>>>> +                           IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
>>>>> +defm VSHLu    : N3VSh_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
>>>>> +                           IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
>>>>> //   VSHL     : Vector Shift Left (Immediate)
>>>>> defm VSHLi    : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
>>>>>                        N2RegVShLFrm>;
>>>>> @@ -2612,10 +2666,10 @@
>>>>>                        NEONvshrn>;
>>>>> 
>>>>> //   VRSHL    : Vector Rounding Shift
>>>>> -defm VRSHLs   : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>>> -                            IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
>>>>> -defm VRSHLu   : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>>> -                            IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
>>>>> +defm VRSHLs   : N3VSh_QHSD<0,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>>> +                           IIC_VSHLi4Q,"vrshl", "s", int_arm_neon_vrshifts,0>;
>>>>> +defm VRSHLu   : N3VSh_QHSD<1,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>>> +                           IIC_VSHLi4Q,"vrshl", "u", int_arm_neon_vrshiftu,0>;
>>>>> //   VRSHR    : Vector Rounding Shift Right
>>>>> defm VRSHRs   : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
>>>>>                        N2RegVShRFrm>;
>>>>> @@ -2627,10 +2681,10 @@
>>>>>                        NEONvrshrn>;
>>>>> 
>>>>> //   VQSHL    : Vector Saturating Shift
>>>>> -defm VQSHLs   : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>>> -                            IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
>>>>> -defm VQSHLu   : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>>> -                            IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
>>>>> +defm VQSHLs   : N3VSh_QHSD<0,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>>> +                           IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
>>>>> +defm VQSHLu   : N3VSh_QHSD<1,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>>> +                           IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
>>>>> //   VQSHL    : Vector Saturating Shift Left (Immediate)
>>>>> defm VQSHLsi  : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
>>>>>                        N2RegVShLFrm>;
>>>>> @@ -2651,12 +2705,12 @@
>>>>>                        NEONvqshrnsu>;
>>>>> 
>>>>> //   VQRSHL   : Vector Saturating Rounding Shift
>>>>> -defm VQRSHLs  : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>>> -                            IIC_VSHLi4Q, "vqrshl", "s",
>>>>> -                            int_arm_neon_vqrshifts, 0>;
>>>>> -defm VQRSHLu  : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>>> -                            IIC_VSHLi4Q, "vqrshl", "u",
>>>>> -                            int_arm_neon_vqrshiftu, 0>;
>>>>> +defm VQRSHLs  : N3VSh_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>>> +                           IIC_VSHLi4Q, "vqrshl", "s",
>>>>> +                           int_arm_neon_vqrshifts, 0>;
>>>>> +defm VQRSHLu  : N3VSh_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
>>>>> +                           IIC_VSHLi4Q, "vqrshl", "u",
>>>>> +                           int_arm_neon_vqrshiftu, 0>;
>>>>> 
>>>>> //   VQRSHRN  : Vector Saturating Rounding Shift Right and Narrow
>>>>> defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
>>>>> 
>>>>> 
>>>>> _______________________________________________
>>>>> llvm-commits mailing list
>>>>> llvm-commits at cs.uiuc.edu
>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>> 
>>> 
>> 
> 




From isanbard at gmail.com  Fri Mar 26 18:40:55 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 26 Mar 2010 23:40:55 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r99670 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <20100326234055.845232A6C12D@llvm.org>

Author: void
Date: Fri Mar 26 18:40:55 2010
New Revision: 99670

URL: http://llvm.org/viewvc/llvm-project?rev=99670&view=rev
Log:
A clean-up needs to be marked as a clean-up. It could cause problems in the
libunwind library otherwise. Take this program for an example:

int main() {
    try {
        throw new std::exception();
    } catch (std::exception *e) {
        throw e;
    }
}

At the re-throw, the libunwind expects the state to be in a clean-up
state. However, because we generate catch-alls in our code, the personality
returns the wrong state the libunwind, which then barfs.

Marking that re-throw as a clean-up puts libunwind into the correct state.

There is other code here, though. If we mark clean-ups as clean-ups, then it
could break when inlining through an 'invoke' instruction. You will get a
situation like this:

bb:
  %ehptr = eh.exception()
  %sel = eh.selector(%ehptr, @per, 0);

...

bb2:
  invoke _Unwind_Resume_or_Rethrow(%ehptr) %normal unwind to %lpad

lpad:
  ...

The unwinder will see the %sel call as a clean-up and, if it doesn't have a
catch further up the call stack, it will skip running it. But there *is* another
catch up the stack -- the catch for the %lpad. However, we can't see that. This
is fixed in code-gen, where we detect this situation, and convert the "clean-up"
selector call into a "catch-all" selector call. This gives us the correct
semantics.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=99670&r1=99669&r2=99670&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Fri Mar 26 18:40:55 2010
@@ -2089,6 +2089,9 @@
     // Add selections for each handler.
     foreach_reachable_handler(i, false, AddHandler, &Handlers);
 
+    bool HasCleanup = false;
+    static Value *CatchAll = 0;
+
     for (std::vector<struct eh_region *>::iterator I = Handlers.begin(),
          E = Handlers.end(); I != E; ++I) {
       struct eh_region *region = *I;
@@ -2115,9 +2118,16 @@
 
         if (!TypeList) {
           // Catch-all - push a null pointer.
-          Args.push_back(
-            Constant::getNullValue(Type::getInt8PtrTy(Context))
-          );
+          if (!CatchAll) {
+            Constant *Init =
+              Constant::getNullValue(Type::getInt8PtrTy(Context));
+
+            CatchAll = new GlobalVariable(*TheModule, Init->getType(), true,
+                                          GlobalVariable::LinkOnceAnyLinkage,
+                                          Init, ".llvm.eh.catch.all.value");
+          }
+
+          Args.push_back(CatchAll);
         } else {
           // Add the type infos.
           for (; TypeList; TypeList = TREE_CHAIN(TypeList)) {
@@ -2125,30 +2135,43 @@
             Args.push_back(Emit(TType, 0));
           }
         }
+      } else {
+        // Cleanup.
+        HasCleanup = true;
       }
     }
 
     if (can_throw_external_1(i, false)) {
-      // Some exceptions from this region may not be caught by any handler.
-      // Since invokes are required to branch to the unwind label no matter
-      // what exception is being unwound, append a catch-all.
-
-      // The representation of a catch-all is language specific.
-      Value *CatchAll;
-      if (USING_SJLJ_EXCEPTIONS || !lang_eh_catch_all) {
-        // Use a "cleanup" - this should be good enough for most languages.
-        CatchAll = ConstantInt::get(Type::getInt32Ty(Context), 0);
+      if (HasCleanup && Args.size() == 2) {
+        Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), 0));
       } else {
-        tree catch_all_type = lang_eh_catch_all();
-        if (catch_all_type == NULL_TREE)
-          // Use a C++ style null catch-all object.
-          CatchAll = Constant::getNullValue(
-                                    Type::getInt8PtrTy(Context));
-        else
-          // This language has a type that catches all others.
-          CatchAll = Emit(catch_all_type, 0);
+        // Some exceptions from this region may not be caught by any handler.
+        // Since invokes are required to branch to the unwind label no matter
+        // what exception is being unwound, append a catch-all.
+
+        // The representation of a catch-all is language specific.
+        if (USING_SJLJ_EXCEPTIONS || !lang_eh_catch_all) {
+          // Use a "cleanup" - this should be good enough for most languages.
+          Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), 0));
+        } else {
+          if (!CatchAll) {
+            Constant *Init = 0;
+            tree catch_all_type = lang_eh_catch_all();
+            if (catch_all_type == NULL_TREE)
+              // Use a C++ style null catch-all object.
+              Init = Constant::getNullValue(Type::getInt8PtrTy(Context));
+            else
+              // This language has a type that catches all others.
+              Init = cast<Constant>(Emit(catch_all_type, 0));
+
+            CatchAll = new GlobalVariable(*TheModule, Init->getType(), true,
+                                          GlobalVariable::PrivateLinkage,
+                                          Init, ".llvm.eh.catch.all.value");
+          }
+
+          Args.push_back(CatchAll);
+        }
       }
-      Args.push_back(CatchAll);
     }
 
     // Emit the selector call.




From isanbard at gmail.com  Fri Mar 26 18:41:30 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 26 Mar 2010 23:41:30 -0000
Subject: [llvm-commits] [llvm] r99671 -
	/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
Message-ID: <20100326234130.CE57C2A6C12D@llvm.org>

Author: void
Date: Fri Mar 26 18:41:30 2010
New Revision: 99671

URL: http://llvm.org/viewvc/llvm-project?rev=99671&view=rev
Log:
If we mark clean-ups as clean-ups, then it could break when inlining through an
'invoke' instruction. You will get a situation like this:

bb:
  %ehptr = eh.exception()
  %sel = eh.selector(%ehptr, @per, 0);

...

bb2:
  invoke _Unwind_Resume_or_Rethrow(%ehptr) %normal unwind to %lpad

lpad:
  ...

The unwinder will see the %sel call as a clean-up and, if it doesn't have a
catch further up the call stack, it will skip running it. But there *is* another
catch up the stack -- the catch for the %lpad. However, we can't see that. This
is fixed in code-gen, where we detect this situation, and convert the "clean-up"
selector call into a "catch-all" selector call. This gives us the correct
semantics.

Modified:
    llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp

Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=99671&r1=99670&r2=99671&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Fri Mar 26 18:41:30 2010
@@ -8,19 +8,19 @@
 //===----------------------------------------------------------------------===//
 //
 // This pass mulches exception handling code into a form adapted to code
-// generation.  Required if using dwarf exception handling.
+// generation. Required if using dwarf exception handling.
 //
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "dwarfehprepare"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/Analysis/Dominators.h"
-#include "llvm/CodeGen/Passes.h"
 #include "llvm/Function.h"
 #include "llvm/Instructions.h"
 #include "llvm/IntrinsicInst.h"
 #include "llvm/Module.h"
 #include "llvm/Pass.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/Analysis/Dominators.h"
+#include "llvm/CodeGen/Passes.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
@@ -40,6 +40,15 @@
     // The eh.exception intrinsic.
     Function *ExceptionValueIntrinsic;
 
+    // The eh.selector intrinsic.
+    Function *SelectorIntrinsic;
+
+    // _Unwind_Resume_or_Rethrow call.
+    Constant *URoR;
+
+    // The EH language-specific catch-all type.
+    GlobalVariable *EHCatchAllValue;
+
     // _Unwind_Resume or the target equivalent.
     Constant *RewindFunction;
 
@@ -67,18 +76,77 @@
     Instruction *CreateValueLoad(BasicBlock *BB);
 
     /// CreateReadOfExceptionValue - Return the result of the eh.exception
-    /// intrinsic by calling the intrinsic if in a landing pad, or loading
-    /// it from the exception value variable otherwise.
+    /// intrinsic by calling the intrinsic if in a landing pad, or loading it
+    /// from the exception value variable otherwise.
     Instruction *CreateReadOfExceptionValue(BasicBlock *BB) {
       return LandingPads.count(BB) ?
         CreateExceptionValueCall(BB) : CreateValueLoad(BB);
     }
 
+    /// HandleURoRInvokes - Handle invokes of "_Unwind_Resume_or_Rethrow"
+    /// calls. The "unwind" part of these invokes jump to a landing pad within
+    /// the current function. This is a candidate to merge the selector
+    /// associated with the URoR invoke with the one from the URoR's landing
+    /// pad.
+    bool HandleURoRInvokes();
+
+    /// FindSelectorAndURoR - Find the eh.selector call and URoR call associated
+    /// with the eh.exception call. This recursively looks past instructions
+    /// which don't change the EH pointer value, like casts or PHI nodes.
+    bool FindSelectorAndURoR(Instruction *Inst, bool &URoRInvoke,
+                             SmallPtrSet<IntrinsicInst*, 8> &SelCalls);
+      
+    /// DoMem2RegPromotion - Take an alloca call and promote it from memory to a
+    /// register.
+    bool DoMem2RegPromotion(Value *V) {
+      AllocaInst *AI = dyn_cast<AllocaInst>(V);
+      if (!AI || !isAllocaPromotable(AI)) return false;
+
+      // Turn the alloca into a register.
+      std::vector<AllocaInst*> Allocas(1, AI);
+      PromoteMemToReg(Allocas, *DT, *DF);
+      return true;
+    }
+
+    /// PromoteStoreInst - Perform Mem2Reg on a StoreInst.
+    bool PromoteStoreInst(StoreInst *SI) {
+      if (!SI || !DT || !DF) return false;
+      if (DoMem2RegPromotion(SI->getOperand(1)))
+        return true;
+      return false;
+    }
+
+    /// PromoteEHPtrStore - Promote the storing of an EH pointer into a
+    /// register. This should get rid of the store and subsequent loads.
+    bool PromoteEHPtrStore(IntrinsicInst *II) {
+      if (!DT || !DF) return false;
+
+      bool Changed = false;
+      StoreInst *SI;
+
+      while (1) {
+        SI = 0;
+        for (Value::use_iterator
+               I = II->use_begin(), E = II->use_end(); I != E; ++I) {
+          SI = dyn_cast<StoreInst>(I);
+          if (SI) break;
+        }
+
+        if (!PromoteStoreInst(SI))
+          break;
+
+        Changed = true;
+      }
+
+      return false;
+    }
+
   public:
     static char ID; // Pass identification, replacement for typeid.
     DwarfEHPrepare(const TargetLowering *tli, bool fast) :
       FunctionPass(&ID), TLI(tli), CompileFast(fast),
-      ExceptionValueIntrinsic(0), RewindFunction(0) {}
+      ExceptionValueIntrinsic(0), SelectorIntrinsic(0),
+      URoR(0), EHCatchAllValue(0), RewindFunction(0) {}
 
     virtual bool runOnFunction(Function &Fn);
 
@@ -105,6 +173,144 @@
   return new DwarfEHPrepare(tli, fast);
 }
 
+/// FindSelectorAndURoR - Find the eh.selector call associated with the
+/// eh.exception call. And indicate if there is a URoR "invoke" associated with
+/// the eh.exception call. This recursively looks past instructions which don't
+/// change the EH pointer value, like casts or PHI nodes.
+bool
+DwarfEHPrepare::FindSelectorAndURoR(Instruction *Inst, bool &URoRInvoke,
+                                    SmallPtrSet<IntrinsicInst*, 8> &SelCalls) {
+  SmallPtrSet<PHINode*, 32> SeenPHIs;
+  bool Changed = false;
+
+ restart:
+  for (Value::use_iterator
+         I = Inst->use_begin(), E = Inst->use_end(); I != E; ++I) {
+    Instruction *II = dyn_cast<Instruction>(I);
+    if (!II || II->getParent()->getParent() != F) continue;
+    
+    if (IntrinsicInst *Sel = dyn_cast<IntrinsicInst>(II)) {
+      if (Sel->getIntrinsicID() == Intrinsic::eh_selector)
+        SelCalls.insert(Sel);
+    } else if (InvokeInst *Invoke = dyn_cast<InvokeInst>(II)) {
+      if (Invoke->getCalledFunction() == URoR)
+        URoRInvoke = true;
+    } else if (CastInst *CI = dyn_cast<CastInst>(II)) {
+      Changed |= FindSelectorAndURoR(CI, URoRInvoke, SelCalls);
+    } else if (StoreInst *SI = dyn_cast<StoreInst>(II)) {
+      if (!PromoteStoreInst(SI)) continue;
+      Changed = true;
+      SeenPHIs.clear();
+      goto restart;             // Uses may have changed, restart loop.
+    } else if (PHINode *PN = dyn_cast<PHINode>(II)) {
+      if (SeenPHIs.insert(PN))
+        // Don't process a PHI node more than once.
+        Changed |= FindSelectorAndURoR(PN, URoRInvoke, SelCalls);
+    }
+  }
+
+  return Changed;
+}
+
+/// HandleURoRInvokes - Handle invokes of "_Unwind_Resume_or_Rethrow" calls. The
+/// "unwind" part of these invokes jump to a landing pad within the current
+/// function. This is a candidate to merge the selector associated with the URoR
+/// invoke with the one from the URoR's landing pad.
+bool DwarfEHPrepare::HandleURoRInvokes() {
+  if (!EHCatchAllValue) {
+    EHCatchAllValue =
+      F->getParent()->getNamedGlobal(".llvm.eh.catch.all.value");
+    if (!EHCatchAllValue) return false;
+  }
+
+  if (!URoR) {
+    URoR = F->getParent()->getFunction("_Unwind_Resume_or_Rethrow");
+    if (!URoR) return false;
+  }
+
+  if (!ExceptionValueIntrinsic) {
+    ExceptionValueIntrinsic =
+      Intrinsic::getDeclaration(F->getParent(), Intrinsic::eh_exception);
+    if (!ExceptionValueIntrinsic) return false;
+  }
+
+  if (!SelectorIntrinsic) {
+    SelectorIntrinsic =
+      Intrinsic::getDeclaration(F->getParent(), Intrinsic::eh_selector);
+    if (!SelectorIntrinsic) return false;
+  }
+
+  bool Changed = false;
+  SmallPtrSet<IntrinsicInst*, 32> SelsToConvert;
+
+  for (Value::use_iterator
+         I = ExceptionValueIntrinsic->use_begin(),
+         E = ExceptionValueIntrinsic->use_end(); I != E; ++I) {
+    IntrinsicInst *EHPtr = dyn_cast<IntrinsicInst>(I);
+    if (!EHPtr || EHPtr->getParent()->getParent() != F) continue;
+
+    Changed |= PromoteEHPtrStore(EHPtr);
+
+    bool URoRInvoke = false;
+    SmallPtrSet<IntrinsicInst*, 8> SelCalls;
+    Changed |= FindSelectorAndURoR(EHPtr, URoRInvoke, SelCalls);
+
+    if (URoRInvoke) {
+      // This EH pointer is being used by an invoke of an URoR instruction and
+      // an eh.selector intrinsic call. If the eh.selector is a 'clean-up', we
+      // need to convert it to a 'catch-all'.
+      for (SmallPtrSet<IntrinsicInst*, 8>::iterator
+             SI = SelCalls.begin(), SE = SelCalls.end(); SI != SE; ++SI) {
+        IntrinsicInst *II = *SI;
+        unsigned NumOps = II->getNumOperands();
+
+        if (NumOps <= 4) {
+          bool IsCleanUp = (NumOps == 3);
+
+          if (!IsCleanUp)
+            if (ConstantInt *CI = dyn_cast<ConstantInt>(II->getOperand(3)))
+              IsCleanUp = (CI->getZExtValue() == 0);
+
+          if (IsCleanUp)
+            SelsToConvert.insert(II);
+        }
+      }
+    }
+  }
+
+  if (!SelsToConvert.empty()) {
+    // Convert all clean-up eh.selectors, which are associated with "invokes" of
+    // URoR calls, into catch-all eh.selectors.
+    Changed = true;
+
+    for (SmallPtrSet<IntrinsicInst*, 8>::iterator
+           SI = SelsToConvert.begin(), SE = SelsToConvert.end();
+         SI != SE; ++SI) {
+      IntrinsicInst *II = *SI;
+      SmallVector<Value*, 8> Args;
+
+      // Use the exception object pointer and the personality function
+      // from the original selector.
+      Args.push_back(II->getOperand(1)); // Exception object pointer.
+      Args.push_back(II->getOperand(2)); // Personality function.
+      Args.push_back(EHCatchAllValue->getInitializer()); // Catch-all indicator.
+
+      CallInst *NewSelector =
+        CallInst::Create(SelectorIntrinsic, Args.begin(), Args.end(),
+                         "eh.sel.catch.all", II);
+
+      NewSelector->setTailCall(II->isTailCall());
+      NewSelector->setAttributes(II->getAttributes());
+      NewSelector->setCallingConv(II->getCallingConv());
+
+      II->replaceAllUsesWith(NewSelector);
+      II->eraseFromParent();
+    }
+  }
+
+  return Changed;
+}
+
 /// NormalizeLandingPads - Normalize and discover landing pads, noting them
 /// in the LandingPads set.  A landing pad is normal if the only CFG edges
 /// that end at it are unwind edges from invoke instructions. If we inlined
@@ -422,6 +628,8 @@
   if (!CompileFast)
     Changed |= PromoteStackTemporaries();
 
+  Changed |= HandleURoRInvokes();
+
   LandingPads.clear();
 
   return Changed;




From daniel at zuster.org  Fri Mar 26 18:42:12 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 26 Mar 2010 23:42:12 -0000
Subject: [llvm-commits] [test-suite] r99672 - /test-suite/trunk/RunSafely.sh
Message-ID: <20100326234212.8433F2A6C12D@llvm.org>

Author: ddunbar
Date: Fri Mar 26 18:42:12 2010
New Revision: 99672

URL: http://llvm.org/viewvc/llvm-project?rev=99672&view=rev
Log:
RunSafely: Add RUNSAFELY_UTIME_ONLY variable, which stops RunSafely from adding
in the system time to the values it reports.

Modified:
    test-suite/trunk/RunSafely.sh

Modified: test-suite/trunk/RunSafely.sh
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/RunSafely.sh?rev=99672&r1=99671&r2=99672&view=diff
==============================================================================
--- test-suite/trunk/RunSafely.sh (original)
+++ test-suite/trunk/RunSafely.sh Fri Mar 26 18:42:12 2010
@@ -136,7 +136,7 @@
     | awk -- '\
 BEGIN     { cpu = 0.0; }
 /^user/   { cpu += $2; print; }
-/^sys/    { cpu += $2; print; }
+/^sys/    { if (!ENVIRON["RUNSAFELY_UTIME_ONLY"]) { cpu += $2; }; print; }
 !/^user/ && !/^sys/  { print; }
 END       { printf("program %f\n", cpu); }' > $OUTFILE.time
 else
@@ -151,7 +151,7 @@
   cat $PWD/${OUTFILE}.remote.time | awk -- '\
 BEGIN     { cpu = 0.0; }
 /^user/   { cpu += $2; print; }
-/^sys/    { cpu += $2; print; }
+/^sys/    { if (!ENVIRON["RUNSAFELY_UTIME_ONLY"]) { cpu += $2; }; print; }
 !/^user/ && !/^sys/  { print; }
 END       { printf("program %f\n", cpu); }' > $OUTFILE.time
 sleep 1




From clattner at apple.com  Fri Mar 26 18:44:23 2010
From: clattner at apple.com (Chris Lattner)
Date: Fri, 26 Mar 2010 16:44:23 -0700
Subject: [llvm-commits] Patch: address space support
	for	memcpy/memmove/memset
In-Reply-To: <89548B9C-55E6-40DF-8E7D-9B1C30162EA4@apple.com>
References: <89548B9C-55E6-40DF-8E7D-9B1C30162EA4@apple.com>
Message-ID: <9E5E9EA6-0ECE-4678-A92B-083C78D8776B@apple.com>


On Mar 24, 2010, at 4:01 PM, Mon Ping Wang wrote:

> 
> This is a patch to add support for address spaces for memcpy, memmove, and memset.  I have changed the signature of these functions to be overloaded based on the pointer type.  I have included both the llvm changes and the llvm-gcc-4.2 changes need to support.  Please let me know if I miss something.  I'll check it in a few days.

Should the source and destination pointers be required to be in the same address space?  I can see it either way (f.e. on x86 a copy from DS -> GS segment address space makes sense), but it would be nice to reduce noisiness in the function name if a copy from one addr space to another isn't useful.

Other than that, this patch looks great to me, but "while you're at it" can you add an "i1 isVolatile" parameter to llvm.memcpy and friends?

-Chris


From johnny.chen at apple.com  Fri Mar 26 18:49:07 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Fri, 26 Mar 2010 23:49:07 -0000
Subject: [llvm-commits] [llvm] r99676 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20100326234907.CD5F82A6C12C@llvm.org>

Author: johnny
Date: Fri Mar 26 18:49:07 2010
New Revision: 99676

URL: http://llvm.org/viewvc/llvm-project?rev=99676&view=rev
Log:
Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified
to now take a format argument.  N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99676&r1=99675&r2=99676&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Mar 26 18:49:07 2010
@@ -1015,12 +1015,12 @@
 
 // Basic 3-register intrinsics, both double- and quad-register.
 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
-              InstrItinClass itin, string OpcodeStr, string Dt,
+              Format f, InstrItinClass itin, string OpcodeStr, string Dt,
               ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
-  : N3V<op24, op23, op21_20, op11_8, 0, op4,
-        (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin, 
-        OpcodeStr, Dt, "$dst, $src1, $src2", "",
-        [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
+  : N3Vf<op24, op23, op21_20, op11_8, 0, op4,
+         (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), f, itin,
+         OpcodeStr, Dt, "$dst, $src1, $src2", "",
+         [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
   let isCommutable = Commutable;
 }
 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 
@@ -1047,12 +1047,12 @@
 }
 
 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
-              InstrItinClass itin, string OpcodeStr, string Dt,
+              Format f, InstrItinClass itin, string OpcodeStr, string Dt,
               ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
-  : N3V<op24, op23, op21_20, op11_8, 1, op4,
-        (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin, 
-        OpcodeStr, Dt, "$dst, $src1, $src2", "",
-        [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
+  : N3Vf<op24, op23, op21_20, op11_8, 1, op4,
+         (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), f, itin,
+         OpcodeStr, Dt, "$dst, $src1, $src2", "",
+         [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
   let isCommutable = Commutable;
 }
 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 
@@ -1526,24 +1526,24 @@
 // Neon 3-register vector intrinsics.
 
 // First with only element sizes of 16 and 32 bits:
-multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
+multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
                      InstrItinClass itinD16, InstrItinClass itinD32,
                      InstrItinClass itinQ16, InstrItinClass itinQ32,
                      string OpcodeStr, string Dt,
                      Intrinsic IntOp, bit Commutable = 0> {
   // 64-bit vector types.
-  def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16,
+  def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
                       OpcodeStr, !strconcat(Dt, "16"),
                       v4i16, v4i16, IntOp, Commutable>;
-  def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32,
+  def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
                       OpcodeStr, !strconcat(Dt, "32"),
                       v2i32, v2i32, IntOp, Commutable>;
 
   // 128-bit vector types.
-  def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16,
+  def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
                       OpcodeStr, !strconcat(Dt, "16"),
                       v8i16, v8i16, IntOp, Commutable>;
-  def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32,
+  def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
                       OpcodeStr, !strconcat(Dt, "32"),
                       v4i32, v4i32, IntOp, Commutable>;
 }
@@ -1563,92 +1563,37 @@
 }
 
 // ....then also with element size of 8 bits:
-multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
+multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
                       InstrItinClass itinD16, InstrItinClass itinD32,
                       InstrItinClass itinQ16, InstrItinClass itinQ32,
                       string OpcodeStr, string Dt,
                       Intrinsic IntOp, bit Commutable = 0>
-  : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
+  : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
               OpcodeStr, Dt, IntOp, Commutable> {
-  def v8i8  : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
+  def v8i8  : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
                       OpcodeStr, !strconcat(Dt, "8"),
                       v8i8, v8i8, IntOp, Commutable>;
-  def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
+  def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
                       OpcodeStr, !strconcat(Dt, "8"),
                       v16i8, v16i8, IntOp, Commutable>;
 }
 
 // ....then also with element size of 64 bits:
-multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
+multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
                        InstrItinClass itinD16, InstrItinClass itinD32,
                        InstrItinClass itinQ16, InstrItinClass itinQ32,
                        string OpcodeStr, string Dt,
                        Intrinsic IntOp, bit Commutable = 0>
-  : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
+  : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
                OpcodeStr, Dt, IntOp, Commutable> {
-  def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
+  def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
                       OpcodeStr, !strconcat(Dt, "64"),
                       v1i64, v1i64, IntOp, Commutable>;
-  def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
+  def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
                       OpcodeStr, !strconcat(Dt, "64"),
                       v2i64, v2i64, IntOp, Commutable>;
 }
 
-// N3VSh_QHSD is similar to N3VInt_QHSD, except that it is for 3-Register Vector
-// Shift Instructions (N3RegVShFrm), which do not follow the N3RegFrm's operand
-// order of D:Vd N:Vn M:Vm.
-//
-// The operand order of N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the
-// first src operand).
-class N3VDSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
-             InstrItinClass itin, string OpcodeStr, string Dt,
-             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
-  : N3Vf<op24, op23, op21_20, op11_8, 0, op4,
-         (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegVShFrm,
-         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
-         [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
-  let isCommutable = Commutable;
-}
-class N3VQSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
-             InstrItinClass itin, string OpcodeStr, string Dt,
-             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
-  : N3Vf<op24, op23, op21_20, op11_8, 1, op4,
-         (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegVShFrm,
-         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
-         [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
-  let isCommutable = Commutable;
-}
-multiclass N3VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
-                      InstrItinClass itinD16, InstrItinClass itinD32,
-                      InstrItinClass itinQ16, InstrItinClass itinQ32,
-                      string OpcodeStr, string Dt,
-                      Intrinsic IntOp, bit Commutable> {
-  def v4i16 : N3VDSh<op24, op23, 0b01, op11_8, op4, itinD16,
-                     OpcodeStr, !strconcat(Dt, "16"),
-                     v4i16, v4i16, IntOp, Commutable>;
-  def v2i32 : N3VDSh<op24, op23, 0b10, op11_8, op4, itinD32,
-                     OpcodeStr, !strconcat(Dt, "32"),
-                     v2i32, v2i32, IntOp, Commutable>;
-  def v8i16 : N3VQSh<op24, op23, 0b01, op11_8, op4, itinQ16,
-                     OpcodeStr, !strconcat(Dt, "16"),
-                     v8i16, v8i16, IntOp, Commutable>;
-  def v4i32 : N3VQSh<op24, op23, 0b10, op11_8, op4, itinQ32,
-                     OpcodeStr, !strconcat(Dt, "32"),
-                     v4i32, v4i32, IntOp, Commutable>;
-  def v8i8  : N3VDSh<op24, op23, 0b00, op11_8, op4, itinD16,
-                     OpcodeStr, !strconcat(Dt, "8"),
-                     v8i8, v8i8, IntOp, Commutable>;
-  def v16i8 : N3VQSh<op24, op23, 0b00, op11_8, op4, itinQ16,
-                     OpcodeStr, !strconcat(Dt, "8"),
-                     v16i8, v16i8, IntOp, Commutable>;
-  def v1i64 : N3VDSh<op24, op23, 0b11, op11_8, op4,
-                     itinD32, OpcodeStr, !strconcat(Dt, "64"),
-                     v1i64, v1i64, IntOp, Commutable>;
-  def v2i64 : N3VQSh<op24, op23, 0b11, op11_8, op4,
-                     itinQ32, OpcodeStr, !strconcat(Dt, "64"),
-                     v2i64, v2i64, IntOp, Commutable>;
-}
-
 // Neon Narrowing 3-register vector intrinsics,
 //   source operand element sizes of 16, 32 and 64 bits:
 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
@@ -2058,20 +2003,26 @@
 defm VADDWs   : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
 defm VADDWu   : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
 //   VHADD    : Vector Halving Add
-defm VHADDs   : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
-                           IIC_VBINi4Q, "vhadd", "s", int_arm_neon_vhadds, 1>;
-defm VHADDu   : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
-                           IIC_VBINi4Q, "vhadd", "u", int_arm_neon_vhaddu, 1>;
+defm VHADDs   : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
+                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
+                           "vhadd", "s", int_arm_neon_vhadds, 1>;
+defm VHADDu   : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
+                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
+                           "vhadd", "u", int_arm_neon_vhaddu, 1>;
 //   VRHADD   : Vector Rounding Halving Add
-defm VRHADDs  : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
-                           IIC_VBINi4Q, "vrhadd", "s", int_arm_neon_vrhadds, 1>;
-defm VRHADDu  : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
-                           IIC_VBINi4Q, "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
+defm VRHADDs  : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
+                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
+                           "vrhadd", "s", int_arm_neon_vrhadds, 1>;
+defm VRHADDu  : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
+                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
+                           "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
 //   VQADD    : Vector Saturating Add
-defm VQADDs   : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
-                            IIC_VBINi4Q, "vqadd", "s", int_arm_neon_vqadds, 1>;
-defm VQADDu   : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
-                            IIC_VBINi4Q, "vqadd", "u", int_arm_neon_vqaddu, 1>;
+defm VQADDs   : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
+                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
+                            "vqadd", "s", int_arm_neon_vqadds, 1>;
+defm VQADDu   : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
+                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
+                            "vqadd", "u", int_arm_neon_vqaddu, 1>;
 //   VADDHN   : Vector Add and Narrow Returning High Half (D = Q + Q)
 defm VADDHN   : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
                             int_arm_neon_vaddhn, 1>;
@@ -2084,10 +2035,10 @@
 //   VMUL     : Vector Multiply (integer, polynomial and floating-point)
 defm VMUL     : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
                         IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
-def  VMULpd   : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul", "p8",
-                        v8i8, v8i8, int_arm_neon_vmulp, 1>;
-def  VMULpq   : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul", "p8",
-                        v16i8, v16i8, int_arm_neon_vmulp, 1>;
+def  VMULpd   : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
+                        "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
+def  VMULpq   : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
+                        "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
 def  VMULfd   : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
                      v2f32, v2f32, fmul, 1>;
 def  VMULfq   : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
@@ -2117,7 +2068,7 @@
                            (SubReg_i32_lane imm:$lane)))>;
 
 //   VQDMULH  : Vector Saturating Doubling Multiply Returning High Half
-defm VQDMULH  : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
+defm VQDMULH  : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
                           IIC_VMULi16Q, IIC_VMULi32Q, 
                           "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
@@ -2139,8 +2090,8 @@
                                  (SubReg_i32_lane imm:$lane)))>;
 
 //   VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
-defm VQRDMULH   : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
-                            IIC_VMULi16Q, IIC_VMULi32Q,
+defm VQRDMULH   : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
+                            IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
                             "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
                               IIC_VMULi16Q, IIC_VMULi32Q,
@@ -2299,18 +2250,18 @@
 defm VSUBWs   : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
 defm VSUBWu   : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
 //   VHSUB    : Vector Halving Subtract
-defm VHSUBs   : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
-                           IIC_VBINi4Q, IIC_VBINi4Q,
+defm VHSUBs   : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
+                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
                            "vhsub", "s", int_arm_neon_vhsubs, 0>;
-defm VHSUBu   : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
-                           IIC_VBINi4Q, IIC_VBINi4Q,
+defm VHSUBu   : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
+                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
                            "vhsub", "u", int_arm_neon_vhsubu, 0>;
 //   VQSUB    : Vector Saturing Subtract
-defm VQSUBs   : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
-                            IIC_VBINi4Q, IIC_VBINi4Q,
+defm VQSUBs   : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
+                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
                             "vqsub", "s", int_arm_neon_vqsubs, 0>;
-defm VQSUBu   : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
-                            IIC_VBINi4Q, IIC_VBINi4Q,
+defm VQSUBu   : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
+                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
                             "vqsub", "u", int_arm_neon_vqsubu, 0>;
 //   VSUBHN   : Vector Subtract and Narrow Returning High Half (D = Q - Q)
 defm VSUBHN   : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
@@ -2365,15 +2316,15 @@
                             "$dst, $src, #0">;
 
 //   VACGE    : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
-def  VACGEd   : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge", "f32",
-                        v2i32, v2f32, int_arm_neon_vacged, 0>;
-def  VACGEq   : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge", "f32",
-                        v4i32, v4f32, int_arm_neon_vacgeq, 0>;
+def  VACGEd   : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
+                        "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
+def  VACGEq   : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
+                        "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
 //   VACGT    : Vector Absolute Compare Greater Than (aka VCAGT)
-def  VACGTd   : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt", "f32",
-                        v2i32, v2f32, int_arm_neon_vacgtd, 0>;
-def  VACGTq   : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt", "f32",
-                        v4i32, v4f32, int_arm_neon_vacgtq, 0>;
+def  VACGTd   : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
+                        "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
+def  VACGTq   : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
+                        "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
 //   VTST     : Vector Test Bits
 defm VTST     : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 
                         IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
@@ -2477,15 +2428,15 @@
 // Vector Absolute Differences.
 
 //   VABD     : Vector Absolute Difference
-defm VABDs    : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
-                           IIC_VBINi4Q, IIC_VBINi4Q,
+defm VABDs    : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
+                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
                            "vabd", "s", int_arm_neon_vabds, 0>;
-defm VABDu    : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
-                           IIC_VBINi4Q, IIC_VBINi4Q,
+defm VABDu    : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
+                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
                            "vabd", "u", int_arm_neon_vabdu, 0>;
-def  VABDfd   : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND,
+def  VABDfd   : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
                         "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
-def  VABDfq   : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ,
+def  VABDfq   : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
                         "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
 
 //   VABDL    : Vector Absolute Difference Long (Q = | D - D |)
@@ -2505,36 +2456,40 @@
 // Vector Maximum and Minimum.
 
 //   VMAX     : Vector Maximum
-defm VMAXs    : N3VInt_QHS<0,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
-                           IIC_VBINi4Q, "vmax", "s", int_arm_neon_vmaxs, 1>;
-defm VMAXu    : N3VInt_QHS<1,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
-                           IIC_VBINi4Q, "vmax", "u", int_arm_neon_vmaxu, 1>;
-def  VMAXfd   : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax", "f32",
-                        v2f32, v2f32, int_arm_neon_vmaxs, 1>;
-def  VMAXfq   : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax", "f32",
-                        v4f32, v4f32, int_arm_neon_vmaxs, 1>;
+defm VMAXs    : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
+                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
+                           "vmax", "s", int_arm_neon_vmaxs, 1>;
+defm VMAXu    : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
+                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
+                           "vmax", "u", int_arm_neon_vmaxu, 1>;
+def  VMAXfd   : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND, "vmax",
+                        "f32", v2f32, v2f32, int_arm_neon_vmaxs, 1>;
+def  VMAXfq   : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ, "vmax",
+                        "f32", v4f32, v4f32, int_arm_neon_vmaxs, 1>;
 
 //   VMIN     : Vector Minimum
-defm VMINs    : N3VInt_QHS<0,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
-                           IIC_VBINi4Q, "vmin", "s", int_arm_neon_vmins, 1>;
-defm VMINu    : N3VInt_QHS<1,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
-                           IIC_VBINi4Q, "vmin", "u", int_arm_neon_vminu, 1>;
-def  VMINfd   : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin", "f32",
-                        v2f32, v2f32, int_arm_neon_vmins, 1>;
-def  VMINfq   : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin", "f32",
-                        v4f32, v4f32, int_arm_neon_vmins, 1>;
+defm VMINs    : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
+                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
+                           "vmin", "s", int_arm_neon_vmins, 1>;
+defm VMINu    : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
+                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
+                           "vmin", "u", int_arm_neon_vminu, 1>;
+def  VMINfd   : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND, "vmin",
+                        "f32", v2f32, v2f32, int_arm_neon_vmins, 1>;
+def  VMINfq   : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ, "vmin",
+                        "f32", v4f32, v4f32, int_arm_neon_vmins, 1>;
 
 // Vector Pairwise Operations.
 
 //   VPADD    : Vector Pairwise Add
-def  VPADDi8  : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd", "i8",
-                        v8i8, v8i8, int_arm_neon_vpadd, 0>;
-def  VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd", "i16",
-                        v4i16, v4i16, int_arm_neon_vpadd, 0>;
-def  VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd", "i32",
-                        v2i32, v2i32, int_arm_neon_vpadd, 0>;
-def  VPADDf   : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd", "f32",
-                        v2f32, v2f32, int_arm_neon_vpadd, 0>;
+def  VPADDi8  : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VBINiD, "vpadd",
+                        "i8", v8i8, v8i8, int_arm_neon_vpadd, 0>;
+def  VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VBINiD, "vpadd",
+                        "i16", v4i16, v4i16, int_arm_neon_vpadd, 0>;
+def  VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VBINiD, "vpadd",
+                        "i32", v2i32, v2i32, int_arm_neon_vpadd, 0>;
+def  VPADDf   : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm, IIC_VBIND, "vpadd",
+                        "f32", v2f32, v2f32, int_arm_neon_vpadd, 0>;
 
 //   VPADDL   : Vector Pairwise Add Long
 defm VPADDLs  : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
@@ -2549,36 +2504,36 @@
                               int_arm_neon_vpadalu>;
 
 //   VPMAX    : Vector Pairwise Maximum
-def  VPMAXs8  : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "s8",
-                        v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
-def  VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "s16",
-                        v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
-def  VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "s32",
-                        v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
-def  VPMAXu8  : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "u8",
-                        v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
-def  VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "u16",
-                        v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
-def  VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "u32",
-                        v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
-def  VPMAXf   : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax", "f32",
-                        v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
+def  VPMAXs8  : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VBINi4D, "vpmax",
+                        "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
+def  VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VBINi4D, "vpmax",
+                        "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
+def  VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VBINi4D, "vpmax",
+                        "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
+def  VPMAXu8  : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VBINi4D, "vpmax",
+                        "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
+def  VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VBINi4D, "vpmax",
+                        "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
+def  VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VBINi4D, "vpmax",
+                        "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
+def  VPMAXf   : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINi4D, "vpmax",
+                        "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
 
 //   VPMIN    : Vector Pairwise Minimum
-def  VPMINs8  : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "s8",
-                        v8i8, v8i8, int_arm_neon_vpmins, 0>;
-def  VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "s16",
-                        v4i16, v4i16, int_arm_neon_vpmins, 0>;
-def  VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "s32",
-                        v2i32, v2i32, int_arm_neon_vpmins, 0>;
-def  VPMINu8  : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "u8",
-                        v8i8, v8i8, int_arm_neon_vpminu, 0>;
-def  VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "u16",
-                        v4i16, v4i16, int_arm_neon_vpminu, 0>;
-def  VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "u32",
-                        v2i32, v2i32, int_arm_neon_vpminu, 0>;
-def  VPMINf   : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin", "f32",
-                        v2f32, v2f32, int_arm_neon_vpmins, 0>;
+def  VPMINs8  : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VBINi4D, "vpmin",
+                        "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
+def  VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VBINi4D, "vpmin",
+                        "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
+def  VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VBINi4D, "vpmin",
+                        "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
+def  VPMINu8  : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VBINi4D, "vpmin",
+                        "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
+def  VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VBINi4D, "vpmin",
+                        "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
+def  VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VBINi4D, "vpmin",
+                        "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
+def  VPMINf   : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINi4D, "vpmin",
+                        "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
 
 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
 
@@ -2597,10 +2552,10 @@
                         v4f32, v4f32, int_arm_neon_vrecpe>;
 
 //   VRECPS   : Vector Reciprocal Step
-def  VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1,
+def  VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
                         IIC_VRECSD, "vrecps", "f32",
                         v2f32, v2f32, int_arm_neon_vrecps, 1>;
-def  VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1,
+def  VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
                         IIC_VRECSQ, "vrecps", "f32",
                         v4f32, v4f32, int_arm_neon_vrecps, 1>;
 
@@ -2619,20 +2574,22 @@
                          v4f32, v4f32, int_arm_neon_vrsqrte>;
 
 //   VRSQRTS  : Vector Reciprocal Square Root Step
-def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1,
+def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
                         IIC_VRECSD, "vrsqrts", "f32",
                         v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
-def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1,
+def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
                         IIC_VRECSQ, "vrsqrts", "f32",
                         v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
 
 // Vector Shifts.
 
 //   VSHL     : Vector Shift
-defm VSHLs    : N3VSh_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
-                           IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
-defm VSHLu    : N3VSh_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
-                           IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
+defm VSHLs    : N3VInt_QHSD<0, 0, 0b0100, 0, N3RegVShFrm,
+                            IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
+                            "vshl", "s", int_arm_neon_vshifts, 0>;
+defm VSHLu    : N3VInt_QHSD<1, 0, 0b0100, 0, N3RegVShFrm,
+                            IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
+                            "vshl", "u", int_arm_neon_vshiftu, 0>;
 //   VSHL     : Vector Shift Left (Immediate)
 defm VSHLi    : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
                            N2RegVShLFrm>;
@@ -2666,10 +2623,12 @@
                            NEONvshrn>;
 
 //   VRSHL    : Vector Rounding Shift
-defm VRSHLs   : N3VSh_QHSD<0,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
-                           IIC_VSHLi4Q,"vrshl", "s", int_arm_neon_vrshifts,0>;
-defm VRSHLu   : N3VSh_QHSD<1,0,0b0101,0,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
-                           IIC_VSHLi4Q,"vrshl", "u", int_arm_neon_vrshiftu,0>;
+defm VRSHLs   : N3VInt_QHSD<0, 0, 0b0101, 0, N3RegVShFrm,
+                            IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
+                            "vrshl", "s", int_arm_neon_vrshifts, 0>;
+defm VRSHLu   : N3VInt_QHSD<1, 0, 0b0101, 0, N3RegVShFrm,
+                            IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
+                            "vrshl", "u", int_arm_neon_vrshiftu, 0>;
 //   VRSHR    : Vector Rounding Shift Right
 defm VRSHRs   : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
                            N2RegVShRFrm>;
@@ -2681,10 +2640,12 @@
                            NEONvrshrn>;
 
 //   VQSHL    : Vector Saturating Shift
-defm VQSHLs   : N3VSh_QHSD<0,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
-                           IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
-defm VQSHLu   : N3VSh_QHSD<1,0,0b0100,1,IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
-                           IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
+defm VQSHLs   : N3VInt_QHSD<0, 0, 0b0100, 1, N3RegVShFrm,
+                            IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
+                            "vqshl", "s", int_arm_neon_vqshifts, 0>;
+defm VQSHLu   : N3VInt_QHSD<1, 0, 0b0100, 1, N3RegVShFrm,
+                            IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
+                            "vqshl", "u", int_arm_neon_vqshiftu, 0>;
 //   VQSHL    : Vector Saturating Shift Left (Immediate)
 defm VQSHLsi  : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
                            N2RegVShLFrm>;
@@ -2705,12 +2666,12 @@
                            NEONvqshrnsu>;
 
 //   VQRSHL   : Vector Saturating Rounding Shift
-defm VQRSHLs  : N3VSh_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
-                           IIC_VSHLi4Q, "vqrshl", "s",
-                           int_arm_neon_vqrshifts, 0>;
-defm VQRSHLu  : N3VSh_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
-                           IIC_VSHLi4Q, "vqrshl", "u",
-                           int_arm_neon_vqrshiftu, 0>;
+defm VQRSHLs  : N3VInt_QHSD<0, 0, 0b0101, 1, N3RegVShFrm,
+                            IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
+                            "vqrshl", "s", int_arm_neon_vqrshifts, 0>;
+defm VQRSHLu  : N3VInt_QHSD<1, 0, 0b0101, 1, N3RegVShFrm,
+                            IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
+                            "vqrshl", "u", int_arm_neon_vqrshiftu, 0>;
 
 //   VQRSHRN  : Vector Saturating Rounding Shift Right and Narrow
 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",




From dpatel at apple.com  Fri Mar 26 18:54:01 2010
From: dpatel at apple.com (Devang Patel)
Date: Fri, 26 Mar 2010 16:54:01 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r99629 -
	/llvm-gcc-4.2/trunk/gcc/gimplify.c
In-Reply-To: <20100326184106.E6B7E2A6C12C@llvm.org>
References: <20100326184106.E6B7E2A6C12C@llvm.org>
Message-ID: <7F9A50BE-9874-4FC1-8649-B79BC895FA3A@apple.com>

Chris,

	This patch causes regressions in gdb test suite.
-
Devang
On Mar 26, 2010, at 11:41 AM, Chris Lattner wrote:

> Author: lattner
> Date: Fri Mar 26 13:41:06 2010
> New Revision: 99629
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99629&view=rev
> Log:
> disable a minor optimization on darwin.  For code like this:
> 
> extern int a, b, c, d;
> void foo() {
>  int *Arr[] = {&a, &b, &c, &d, &a, &b, &c, &d, &a, &b, &c, &d, &a, &b, &c, &d,
>    &a, &b, &c, &d, &a, &b, &c, &d, &a, &b, &c, &d, &a, &b, &c, &d };
>  bar(Arr);
> }
> 
> the compiler synthesizes a global variable for the temporary array and then
> memcpy's from it to Arr.  This is all great, but emitting the temporary global
> with an L label on darwin fouls up atomization and can thus break dead code
> stripping.
> 
> The right answer is to use an 'l' label without .globl, but this will require
> introducing a yet-another new linkage type to llvm, which I'll do later.
> 
> This fixes rdar://7233622
> 
> 
> Modified:
>    llvm-gcc-4.2/trunk/gcc/gimplify.c
> 
> Modified: llvm-gcc-4.2/trunk/gcc/gimplify.c
> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gimplify.c?rev=99629&r1=99628&r2=99629&view=diff
> ==============================================================================
> --- llvm-gcc-4.2/trunk/gcc/gimplify.c (original)
> +++ llvm-gcc-4.2/trunk/gcc/gimplify.c Fri Mar 26 13:41:06 2010
> @@ -3097,9 +3097,16 @@
> 		TREE_STATIC (new) = 1;
> 		TREE_READONLY (new) = 1;
>                 /* LLVM LOCAL begin */
> +                /* On Darwin, we can't emit temporaries like this with private
> +                 * linkage, because it breaks 'atomization' of stuff in the
> +                 * object file by the linker.  We need to emit this as a l label
> +                 * without .globl.
> +                 */
> +#ifndef CONFIG_DARWIN_H
> #ifdef ENABLE_LLVM
> 		DECL_LLVM_PRIVATE (new) = 1;
> #endif
> +#endif
>                 /* LLVM LOCAL end */
> 		DECL_INITIAL (new) = ctor;
> 		if (align > DECL_ALIGN (new))
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From sabre at nondot.org  Fri Mar 26 18:54:15 2010
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 26 Mar 2010 23:54:15 -0000
Subject: [llvm-commits] [llvm] r99677 - /llvm/trunk/lib/Support/APInt.cpp
Message-ID: <20100326235415.BEB7B2A6C12C@llvm.org>

Author: lattner
Date: Fri Mar 26 18:54:15 2010
New Revision: 99677

URL: http://llvm.org/viewvc/llvm-project?rev=99677&view=rev
Log:
improve portability to minix, patch by 
Kees van Reeuwijk for PR6704

Modified:
    llvm/trunk/lib/Support/APInt.cpp

Modified: llvm/trunk/lib/Support/APInt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/APInt.cpp?rev=99677&r1=99676&r2=99677&view=diff
==============================================================================
--- llvm/trunk/lib/Support/APInt.cpp (original)
+++ llvm/trunk/lib/Support/APInt.cpp Fri Mar 26 18:54:15 2010
@@ -1382,8 +1382,8 @@
   // libc sqrt function which will probably use a hardware sqrt computation.
   // This should be faster than the algorithm below.
   if (magnitude < 52) {
-#ifdef _MSC_VER
-    // Amazingly, VC++ doesn't have round().
+#if defined( _MSC_VER ) || defined(_MINIX)
+    // Amazingly, VC++ and Minix don't have round().
     return APInt(BitWidth,
                  uint64_t(::sqrt(double(isSingleWord()?VAL:pVal[0]))) + 0.5);
 #else




From clattner at apple.com  Fri Mar 26 19:06:16 2010
From: clattner at apple.com (Chris Lattner)
Date: Fri, 26 Mar 2010 17:06:16 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r99629 -
	/llvm-gcc-4.2/trunk/gcc/gimplify.c
In-Reply-To: <7F9A50BE-9874-4FC1-8649-B79BC895FA3A@apple.com>
References: <20100326184106.E6B7E2A6C12C@llvm.org>
	<7F9A50BE-9874-4FC1-8649-B79BC895FA3A@apple.com>
Message-ID: <842654B2-6005-430E-8FBF-7463E36DD2D2@apple.com>


On Mar 26, 2010, at 4:54 PM, Devang Patel wrote:

> Chris,
> 
> 	This patch causes regressions in gdb test suite.

that is bad, can you give me any more detail? :)

-Chris

> -
> Devang
> On Mar 26, 2010, at 11:41 AM, Chris Lattner wrote:
> 
>> Author: lattner
>> Date: Fri Mar 26 13:41:06 2010
>> New Revision: 99629
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=99629&view=rev
>> Log:
>> disable a minor optimization on darwin.  For code like this:
>> 
>> extern int a, b, c, d;
>> void foo() {
>> int *Arr[] = {&a, &b, &c, &d, &a, &b, &c, &d, &a, &b, &c, &d, &a, &b, &c, &d,
>>   &a, &b, &c, &d, &a, &b, &c, &d, &a, &b, &c, &d, &a, &b, &c, &d };
>> bar(Arr);
>> }
>> 
>> the compiler synthesizes a global variable for the temporary array and then
>> memcpy's from it to Arr.  This is all great, but emitting the temporary global
>> with an L label on darwin fouls up atomization and can thus break dead code
>> stripping.
>> 
>> The right answer is to use an 'l' label without .globl, but this will require
>> introducing a yet-another new linkage type to llvm, which I'll do later.
>> 
>> This fixes rdar://7233622
>> 
>> 
>> Modified:
>>   llvm-gcc-4.2/trunk/gcc/gimplify.c
>> 
>> Modified: llvm-gcc-4.2/trunk/gcc/gimplify.c
>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gimplify.c?rev=99629&r1=99628&r2=99629&view=diff
>> ==============================================================================
>> --- llvm-gcc-4.2/trunk/gcc/gimplify.c (original)
>> +++ llvm-gcc-4.2/trunk/gcc/gimplify.c Fri Mar 26 13:41:06 2010
>> @@ -3097,9 +3097,16 @@
>> 		TREE_STATIC (new) = 1;
>> 		TREE_READONLY (new) = 1;
>>                /* LLVM LOCAL begin */
>> +                /* On Darwin, we can't emit temporaries like this with private
>> +                 * linkage, because it breaks 'atomization' of stuff in the
>> +                 * object file by the linker.  We need to emit this as a l label
>> +                 * without .globl.
>> +                 */
>> +#ifndef CONFIG_DARWIN_H
>> #ifdef ENABLE_LLVM
>> 		DECL_LLVM_PRIVATE (new) = 1;
>> #endif
>> +#endif
>>                /* LLVM LOCAL end */
>> 		DECL_INITIAL (new) = ctor;
>> 		if (align > DECL_ALIGN (new))
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From grosbach at apple.com  Fri Mar 26 19:09:12 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Sat, 27 Mar 2010 00:09:12 -0000
Subject: [llvm-commits] [llvm] r99678 -
	/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
Message-ID: <20100327000912.C42DA2A6C12C@llvm.org>

Author: grosbach
Date: Fri Mar 26 19:09:12 2010
New Revision: 99678

URL: http://llvm.org/viewvc/llvm-project?rev=99678&view=rev
Log:
Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not pass
through to the generic version. The generic functions use STR/LDR, but T2
needs the t2STR/t2LDR instead so we get the addressing mode correct.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=99678&r1=99677&r2=99678&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Fri Mar 26 19:09:12 2010
@@ -69,7 +69,7 @@
   DebugLoc DL = DebugLoc::getUnknownLoc();
   if (I != MBB.end()) DL = I->getDebugLoc();
 
-  if (RC == ARM::GPRRegisterClass) {
+  if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) {
     MachineFunction &MF = *MBB.getParent();
     MachineFrameInfo &MFI = *MF.getFrameInfo();
     MachineMemOperand *MMO =
@@ -93,7 +93,7 @@
   DebugLoc DL = DebugLoc::getUnknownLoc();
   if (I != MBB.end()) DL = I->getDebugLoc();
 
-  if (RC == ARM::GPRRegisterClass) {
+  if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) {
     MachineFunction &MF = *MBB.getParent();
     MachineFrameInfo &MFI = *MF.getFrameInfo();
     MachineMemOperand *MMO =




From clattner at apple.com  Fri Mar 26 19:11:46 2010
From: clattner at apple.com (Chris Lattner)
Date: Fri, 26 Mar 2010 17:11:46 -0700
Subject: [llvm-commits] [llvm] r99490 -
	/llvm/trunk/lib/VMCore/Metadata.cpp
In-Reply-To: <4994F60D-90B1-4093-8690-9AEC1C4D6AFE@apple.com>
References: <20100325060447.DC6CB2A6C12D@llvm.org>
	<60B2579A-3A15-4F22-A350-04889AF72646@apple.com>
	<4994F60D-90B1-4093-8690-9AEC1C4D6AFE@apple.com>
Message-ID: <9E4734D6-C735-42E1-A478-E2F106707321@apple.com>


On Mar 24, 2010, at 11:15 PM, Devang Patel wrote:

> 
> On Mar 24, 2010, at 11:06 PM, Chris Lattner wrote:
> 
>> 
>> On Mar 24, 2010, at 11:04 PM, Devang Patel wrote:
>> 
>>> Author: dpatel
>>> Date: Thu Mar 25 01:04:47 2010
>>> New Revision: 99490
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=99490&view=rev
>>> Log:
>>> Include isFunctionLocal while calculating folding node set profile for a MDNode.
>> 
>> Can this code call MDNode::Profile instead of duplicating it?
> 
> MDNode::getMDNode() calculates profile based on incoming value list before creating MDNode.

Please define the code in the class as a static method.  For example, check out how the AttributeListImpl::Profile methods work.  This keeps the code close together so they don't start to drift.  Thanks!

-Chris


From sabre at nondot.org  Fri Mar 26 19:29:41 2010
From: sabre at nondot.org (Chris Lattner)
Date: Sat, 27 Mar 2010 00:29:41 -0000
Subject: [llvm-commits] [llvm] r99685 -
	/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
Message-ID: <20100327002941.37DE62A6C12C@llvm.org>

Author: lattner
Date: Fri Mar 26 19:29:41 2010
New Revision: 99685

URL: http://llvm.org/viewvc/llvm-project?rev=99685&view=rev
Log:
bump FIRST_TARGET_MEMORY_OPCODE back up, there is no reason to make it a tight bound anymore.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=99685&r1=99684&r2=99685&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Fri Mar 26 19:29:41 2010
@@ -616,7 +616,7 @@
   /// which do not reference a specific memory location should be less than
   /// this value. Those that do must not be less than this value, and can
   /// be used with SelectionDAG::getMemIntrinsicNode.
-  static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+85;
+  static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+100;
 
   /// Node predicates
 




From sabre at nondot.org  Fri Mar 26 19:45:04 2010
From: sabre at nondot.org (Chris Lattner)
Date: Sat, 27 Mar 2010 00:45:04 -0000
Subject: [llvm-commits] [llvm] r99686 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.td
Message-ID: <20100327004504.7D1002A6C12C@llvm.org>

Author: lattner
Date: Fri Mar 26 19:45:04 2010
New Revision: 99686

URL: http://llvm.org/viewvc/llvm-project?rev=99686&view=rev
Log:
eliminate almost all the rest of the x86-32 parallels.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=99686&r1=99685&r2=99686&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Mar 26 19:45:04 2010
@@ -2686,21 +2686,20 @@
 def ADD8rr    : I<0x00, MRMDestReg, (outs GR8 :$dst),
                                     (ins GR8 :$src1, GR8 :$src2),
                   "add{b}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
-                   (implicit EFLAGS)]>;
+                  [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
 
 let isConvertibleToThreeAddress = 1 in {   // Can transform into LEA.
 // Register-Register Addition
 def ADD16rr  : I<0x01, MRMDestReg, (outs GR16:$dst),
                                    (ins GR16:$src1, GR16:$src2),
                  "add{w}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
-                  (implicit EFLAGS)]>, OpSize;
+                 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
+                                                       GR16:$src2))]>, OpSize;
 def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst),
                                    (ins GR32:$src1, GR32:$src2),
                  "add{l}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
-                  (implicit EFLAGS)]>;
+                 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
+                                                       GR32:$src2))]>;
 } // end isConvertibleToThreeAddress
 } // end isCommutable
 
@@ -2719,47 +2718,47 @@
 def ADD8rm   : I<0x02, MRMSrcMem, (outs GR8 :$dst),
                                   (ins GR8 :$src1, i8mem :$src2),
                  "add{b}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
-                  (implicit EFLAGS)]>;
+                 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
+                                                      (load addr:$src2)))]>;
 def ADD16rm  : I<0x03, MRMSrcMem, (outs GR16:$dst),
                                   (ins GR16:$src1, i16mem:$src2),
                  "add{w}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
-                  (implicit EFLAGS)]>, OpSize;
+                 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
+                                                  (load addr:$src2)))]>, OpSize;
 def ADD32rm  : I<0x03, MRMSrcMem, (outs GR32:$dst),
                                   (ins GR32:$src1, i32mem:$src2),
                  "add{l}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
-                  (implicit EFLAGS)]>;
+                 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
+                                                       (load addr:$src2)))]>;
                   
 // Register-Integer Addition
 def ADD8ri    : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
                     "add{b}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
-                     (implicit EFLAGS)]>;
+                    [(set GR8:$dst, EFLAGS,
+                          (X86add_flag GR8:$src1, imm:$src2))]>;
 
 let isConvertibleToThreeAddress = 1 in {   // Can transform into LEA.
 // Register-Integer Addition
 def ADD16ri  : Ii16<0x81, MRM0r, (outs GR16:$dst),
                                  (ins GR16:$src1, i16imm:$src2),
                     "add{w}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
-                     (implicit EFLAGS)]>, OpSize;
+                    [(set GR16:$dst, EFLAGS,
+                          (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
 def ADD32ri  : Ii32<0x81, MRM0r, (outs GR32:$dst),
                                  (ins GR32:$src1, i32imm:$src2),
                     "add{l}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
-                     (implicit EFLAGS)]>;
+                    [(set GR32:$dst, EFLAGS, 
+                          (X86add_flag GR32:$src1, imm:$src2))]>;
 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
                                 (ins GR16:$src1, i16i8imm:$src2),
                    "add{w}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
-                    (implicit EFLAGS)]>, OpSize;
+                   [(set GR16:$dst, EFLAGS,
+                         (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
                                 (ins GR32:$src1, i32i8imm:$src2),
                    "add{l}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
-                    (implicit EFLAGS)]>;
+                   [(set GR32:$dst, EFLAGS,
+                         (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
 }
 
 let isTwoAddress = 0 in {
@@ -2907,16 +2906,16 @@
 // Register-Register Subtraction
 def SUB8rr  : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
                 "sub{b}\t{$src2, $dst|$dst, $src2}",
-                [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
-                 (implicit EFLAGS)]>;
+                [(set GR8:$dst, EFLAGS,
+                      (X86sub_flag GR8:$src1, GR8:$src2))]>;
 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
                 "sub{w}\t{$src2, $dst|$dst, $src2}",
-                [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
-                 (implicit EFLAGS)]>, OpSize;
+                [(set GR16:$dst, EFLAGS,
+                      (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
                 "sub{l}\t{$src2, $dst|$dst, $src2}",
-                [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
-                 (implicit EFLAGS)]>;
+                [(set GR32:$dst, EFLAGS,
+                      (X86sub_flag GR32:$src1, GR32:$src2))]>;
 
 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
                    "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
@@ -2931,45 +2930,45 @@
 def SUB8rm  : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
                                  (ins GR8 :$src1, i8mem :$src2),
                 "sub{b}\t{$src2, $dst|$dst, $src2}",
-                [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
-                 (implicit EFLAGS)]>;
+                [(set GR8:$dst, EFLAGS,
+                      (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
                                  (ins GR16:$src1, i16mem:$src2),
                 "sub{w}\t{$src2, $dst|$dst, $src2}",
-                [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
-                 (implicit EFLAGS)]>, OpSize;
+                [(set GR16:$dst, EFLAGS,
+                      (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
                                  (ins GR32:$src1, i32mem:$src2),
                 "sub{l}\t{$src2, $dst|$dst, $src2}",
-                [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
-                 (implicit EFLAGS)]>;
+                [(set GR32:$dst, EFLAGS,
+                      (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
 
 // Register-Integer Subtraction
 def SUB8ri   : Ii8 <0x80, MRM5r, (outs GR8:$dst),
                                  (ins GR8:$src1, i8imm:$src2),
                     "sub{b}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
-                     (implicit EFLAGS)]>;
+                    [(set GR8:$dst, EFLAGS,
+                          (X86sub_flag GR8:$src1, imm:$src2))]>;
 def SUB16ri  : Ii16<0x81, MRM5r, (outs GR16:$dst),
                                  (ins GR16:$src1, i16imm:$src2),
                     "sub{w}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
-                     (implicit EFLAGS)]>, OpSize;
+                    [(set GR16:$dst, EFLAGS,
+                          (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
 def SUB32ri  : Ii32<0x81, MRM5r, (outs GR32:$dst),
                                  (ins GR32:$src1, i32imm:$src2),
                     "sub{l}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
-                     (implicit EFLAGS)]>;
+                    [(set GR32:$dst, EFLAGS,
+                          (X86sub_flag GR32:$src1, imm:$src2))]>;
 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
                                 (ins GR16:$src1, i16i8imm:$src2),
                    "sub{w}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
-                    (implicit EFLAGS)]>, OpSize;
+                   [(set GR16:$dst, EFLAGS,
+                         (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
                                 (ins GR32:$src1, i32i8imm:$src2),
                    "sub{l}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
-                    (implicit EFLAGS)]>;
+                   [(set GR32:$dst, EFLAGS,
+                         (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
 
 let isTwoAddress = 0 in {
   // Memory-Register Subtraction
@@ -3118,25 +3117,26 @@
 // Register-Register Signed Integer Multiply
 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
                  "imul{w}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
-                  (implicit EFLAGS)]>, TB, OpSize;
+                 [(set GR16:$dst, EFLAGS,
+                       (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
                  "imul{l}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
-                  (implicit EFLAGS)]>, TB;
+                 [(set GR32:$dst, EFLAGS,
+                       (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
 }
 
 // Register-Memory Signed Integer Multiply
 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
                                   (ins GR16:$src1, i16mem:$src2),
                  "imul{w}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
-                  (implicit EFLAGS)]>, TB, OpSize;
+                 [(set GR16:$dst, EFLAGS,
+                       (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
+               TB, OpSize;
 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), 
                  (ins GR32:$src1, i32mem:$src2),
                  "imul{l}\t{$src2, $dst|$dst, $src2}",
-                 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
-                  (implicit EFLAGS)]>, TB;
+                 [(set GR32:$dst, EFLAGS,
+                       (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
 } // Defs = [EFLAGS]
 } // end Two Address instructions
 
@@ -3146,47 +3146,49 @@
 def IMUL16rri  : Ii16<0x69, MRMSrcReg,                      // GR16 = GR16*I16
                       (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                       "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                      [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
-                       (implicit EFLAGS)]>, OpSize;
+                      [(set GR16:$dst, EFLAGS, 
+                            (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
 def IMUL32rri  : Ii32<0x69, MRMSrcReg,                      // GR32 = GR32*I32
                       (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
                       "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                      [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
-                       (implicit EFLAGS)]>;
+                      [(set GR32:$dst, EFLAGS,
+                            (X86smul_flag GR32:$src1, imm:$src2))]>;
 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg,                       // GR16 = GR16*I8
                      (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
                      "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                     [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
-                      (implicit EFLAGS)]>, OpSize;
+                     [(set GR16:$dst, EFLAGS,
+                           (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
+                 OpSize;
 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg,                       // GR32 = GR32*I8
                      (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
                      "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                     [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
-                      (implicit EFLAGS)]>;
+                     [(set GR32:$dst, EFLAGS,
+                           (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
 
 // Memory-Integer Signed Integer Multiply
 def IMUL16rmi  : Ii16<0x69, MRMSrcMem,                     // GR16 = [mem16]*I16
                       (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
                       "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                      [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
-                       (implicit EFLAGS)]>, OpSize;
+                      [(set GR16:$dst, EFLAGS,
+                            (X86smul_flag (load addr:$src1), imm:$src2))]>,
+                 OpSize;
 def IMUL32rmi  : Ii32<0x69, MRMSrcMem,                     // GR32 = [mem32]*I32
                       (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
                       "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                      [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
-                       (implicit EFLAGS)]>;
+                      [(set GR32:$dst, EFLAGS,
+                            (X86smul_flag (load addr:$src1), imm:$src2))]>;
 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem,                       // GR16 = [mem16]*I8
                      (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
                      "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                     [(set GR16:$dst, (mul (load addr:$src1),
-                                       i16immSExt8:$src2)),
-                      (implicit EFLAGS)]>, OpSize;
+                     [(set GR16:$dst, EFLAGS,
+                           (X86smul_flag (load addr:$src1),
+                                         i16immSExt8:$src2))]>, OpSize;
 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem,                       // GR32 = [mem32]*I8
                      (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
                      "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                     [(set GR32:$dst, (mul (load addr:$src1),
-                                           i32immSExt8:$src2)),
-                      (implicit EFLAGS)]>;
+                     [(set GR32:$dst, EFLAGS,
+                           (X86smul_flag (load addr:$src1),
+                                         i32immSExt8:$src2))]>;
 } // Defs = [EFLAGS]
 
 //===----------------------------------------------------------------------===//
@@ -4739,126 +4741,83 @@
 // EFLAGS-defining Patterns
 //===----------------------------------------------------------------------===//
 
-// Register-Register Addition with EFLAGS result
-def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
-                    (implicit EFLAGS)),
-          (ADD8rr GR8:$src1, GR8:$src2)>;
-def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
-                    (implicit EFLAGS)),
-          (ADD16rr GR16:$src1, GR16:$src2)>;
-def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
-                    (implicit EFLAGS)),
-          (ADD32rr GR32:$src1, GR32:$src2)>;
+// add reg, reg
+def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr  GR8 :$src1, GR8 :$src2)>;
+def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
+def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
 
-// Register-Memory Addition with EFLAGS result
-def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
-                    (implicit EFLAGS)),
+// add reg, mem
+def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
           (ADD8rm GR8:$src1, addr:$src2)>;
-def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
           (ADD16rm GR16:$src1, addr:$src2)>;
-def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
           (ADD32rm GR32:$src1, addr:$src2)>;
 
-// Register-Integer Addition with EFLAGS result
-def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
-                    (implicit EFLAGS)),
-          (ADD8ri GR8:$src1, imm:$src2)>;
-def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
-                    (implicit EFLAGS)),
-          (ADD16ri GR16:$src1, imm:$src2)>;
-def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
-                    (implicit EFLAGS)),
-          (ADD32ri GR32:$src1, imm:$src2)>;
-def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
-                    (implicit EFLAGS)),
+// add reg, imm
+def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri  GR8:$src1 , imm:$src2)>;
+def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
+def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
+def : Pat<(add GR16:$src1, i16immSExt8:$src2),
           (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
-def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(add GR32:$src1, i32immSExt8:$src2),
           (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
 
-// Register-Register Subtraction with EFLAGS result
-def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
-                    (implicit EFLAGS)),
-          (SUB8rr GR8:$src1, GR8:$src2)>;
-def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
-                    (implicit EFLAGS)),
-          (SUB16rr GR16:$src1, GR16:$src2)>;
-def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
-                    (implicit EFLAGS)),
-          (SUB32rr GR32:$src1, GR32:$src2)>;
+// sub reg, reg
+def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr  GR8 :$src1, GR8 :$src2)>;
+def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
+def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
 
-// Register-Memory Subtraction with EFLAGS result
-def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
-                    (implicit EFLAGS)),
+// sub reg, mem
+def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
           (SUB8rm GR8:$src1, addr:$src2)>;
-def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
           (SUB16rm GR16:$src1, addr:$src2)>;
-def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
           (SUB32rm GR32:$src1, addr:$src2)>;
 
-// Register-Integer Subtraction with EFLAGS result
-def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
-                    (implicit EFLAGS)),
+// sub reg, imm
+def : Pat<(sub GR8:$src1, imm:$src2),
           (SUB8ri GR8:$src1, imm:$src2)>;
-def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(sub GR16:$src1, imm:$src2),
           (SUB16ri GR16:$src1, imm:$src2)>;
-def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(sub GR32:$src1, imm:$src2),
           (SUB32ri GR32:$src1, imm:$src2)>;
-def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
           (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
-def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
           (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
 
-// Register-Register Signed Integer Multiply with EFLAGS result
-def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
-                    (implicit EFLAGS)),
+// mul reg, reg
+def : Pat<(mul GR16:$src1, GR16:$src2),
           (IMUL16rr GR16:$src1, GR16:$src2)>;
-def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(mul GR32:$src1, GR32:$src2),
           (IMUL32rr GR32:$src1, GR32:$src2)>;
 
-// Register-Memory Signed Integer Multiply with EFLAGS result
-def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
-                    (implicit EFLAGS)),
+// mul reg, mem
+def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
           (IMUL16rm GR16:$src1, addr:$src2)>;
-def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
           (IMUL32rm GR32:$src1, addr:$src2)>;
 
-// Register-Integer Signed Integer Multiply with EFLAGS result
-def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
-                    (implicit EFLAGS)),
+// mul reg, imm
+def : Pat<(mul GR16:$src1, imm:$src2),
           (IMUL16rri GR16:$src1, imm:$src2)>;
-def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(mul GR32:$src1, imm:$src2),
           (IMUL32rri GR32:$src1, imm:$src2)>;
-def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
           (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
-def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
           (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
 
-// Memory-Integer Signed Integer Multiply with EFLAGS result
-def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
-                    (implicit EFLAGS)),
+// reg = mul mem, imm
+def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
           (IMUL16rmi addr:$src1, imm:$src2)>;
-def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
           (IMUL32rmi addr:$src1, imm:$src2)>;
-def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
           (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
-def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
           (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
 
 // Optimize multiply by 2 with EFLAGS result.




From isanbard at gmail.com  Fri Mar 26 19:48:51 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Sat, 27 Mar 2010 00:48:51 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r99689 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <20100327004851.6CCD72A6C12C@llvm.org>

Author: void
Date: Fri Mar 26 19:48:51 2010
New Revision: 99689

URL: http://llvm.org/viewvc/llvm-project?rev=99689&view=rev
Log:
Revert r99670. It was causing bugpoint to fail.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=99689&r1=99688&r2=99689&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Fri Mar 26 19:48:51 2010
@@ -2089,9 +2089,6 @@
     // Add selections for each handler.
     foreach_reachable_handler(i, false, AddHandler, &Handlers);
 
-    bool HasCleanup = false;
-    static Value *CatchAll = 0;
-
     for (std::vector<struct eh_region *>::iterator I = Handlers.begin(),
          E = Handlers.end(); I != E; ++I) {
       struct eh_region *region = *I;
@@ -2118,16 +2115,9 @@
 
         if (!TypeList) {
           // Catch-all - push a null pointer.
-          if (!CatchAll) {
-            Constant *Init =
-              Constant::getNullValue(Type::getInt8PtrTy(Context));
-
-            CatchAll = new GlobalVariable(*TheModule, Init->getType(), true,
-                                          GlobalVariable::LinkOnceAnyLinkage,
-                                          Init, ".llvm.eh.catch.all.value");
-          }
-
-          Args.push_back(CatchAll);
+          Args.push_back(
+            Constant::getNullValue(Type::getInt8PtrTy(Context))
+          );
         } else {
           // Add the type infos.
           for (; TypeList; TypeList = TREE_CHAIN(TypeList)) {
@@ -2135,43 +2125,30 @@
             Args.push_back(Emit(TType, 0));
           }
         }
-      } else {
-        // Cleanup.
-        HasCleanup = true;
       }
     }
 
     if (can_throw_external_1(i, false)) {
-      if (HasCleanup && Args.size() == 2) {
-        Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), 0));
+      // Some exceptions from this region may not be caught by any handler.
+      // Since invokes are required to branch to the unwind label no matter
+      // what exception is being unwound, append a catch-all.
+
+      // The representation of a catch-all is language specific.
+      Value *CatchAll;
+      if (USING_SJLJ_EXCEPTIONS || !lang_eh_catch_all) {
+        // Use a "cleanup" - this should be good enough for most languages.
+        CatchAll = ConstantInt::get(Type::getInt32Ty(Context), 0);
       } else {
-        // Some exceptions from this region may not be caught by any handler.
-        // Since invokes are required to branch to the unwind label no matter
-        // what exception is being unwound, append a catch-all.
-
-        // The representation of a catch-all is language specific.
-        if (USING_SJLJ_EXCEPTIONS || !lang_eh_catch_all) {
-          // Use a "cleanup" - this should be good enough for most languages.
-          Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), 0));
-        } else {
-          if (!CatchAll) {
-            Constant *Init = 0;
-            tree catch_all_type = lang_eh_catch_all();
-            if (catch_all_type == NULL_TREE)
-              // Use a C++ style null catch-all object.
-              Init = Constant::getNullValue(Type::getInt8PtrTy(Context));
-            else
-              // This language has a type that catches all others.
-              Init = cast<Constant>(Emit(catch_all_type, 0));
-
-            CatchAll = new GlobalVariable(*TheModule, Init->getType(), true,
-                                          GlobalVariable::PrivateLinkage,
-                                          Init, ".llvm.eh.catch.all.value");
-          }
-
-          Args.push_back(CatchAll);
-        }
+        tree catch_all_type = lang_eh_catch_all();
+        if (catch_all_type == NULL_TREE)
+          // Use a C++ style null catch-all object.
+          CatchAll = Constant::getNullValue(
+                                    Type::getInt8PtrTy(Context));
+        else
+          // This language has a type that catches all others.
+          CatchAll = Emit(catch_all_type, 0);
       }
+      Args.push_back(CatchAll);
     }
 
     // Emit the selector call.




From johnny.chen at apple.com  Fri Mar 26 20:03:13 2010
From: johnny.chen at apple.com (Johnny Chen)
Date: Sat, 27 Mar 2010 01:03:13 -0000
Subject: [llvm-commits] [llvm] r99690 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrNEON.td
Message-ID: <20100327010314.0EF112A6C12C@llvm.org>

Author: johnny
Date: Fri Mar 26 20:03:13 2010
New Revision: 99690

URL: http://llvm.org/viewvc/llvm-project?rev=99690&view=rev
Log:
Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set
it as the format for the appropriate N3V*SL*<> classes.  These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.

Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):

	vmlal.s32	q3, d2, d10[0]

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=99690&r1=99689&r2=99690&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Mar 26 20:03:13 2010
@@ -69,6 +69,7 @@
 def N3RegFrm       : Format<38>;
 def N3RegVShFrm    : Format<39>;
 def NVExtFrm       : Format<40>;
+def NVMulSLFrm     : Format<41>;
 
 // Misc flags.
 

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99690&r1=99689&r2=99690&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Mar 26 20:03:13 2010
@@ -949,25 +949,26 @@
          [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
   let isCommutable = Commutable;
 }
+
 class N3VDSL<bits<2> op21_20, bits<4> op11_8, 
              InstrItinClass itin, string OpcodeStr, string Dt,
              ValueType Ty, SDNode ShOp>
-  : N3V<0, 1, op21_20, op11_8, 1, 0,
-        (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
-        itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
-        [(set (Ty DPR:$dst),
-              (Ty (ShOp (Ty DPR:$src1),
-                        (Ty (NEONvduplane (Ty DPR_VFP2:$src2), imm:$lane)))))]>{
+  : N3Vf<0, 1, op21_20, op11_8, 1, 0,
+         (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
+         NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
+         [(set (Ty DPR:$dst),
+               (Ty (ShOp (Ty DPR:$src1),
+                         (Ty (NEONvduplane (Ty DPR_VFP2:$src2),imm:$lane)))))]>{
   let isCommutable = 0;
 }
 class N3VDSL16<bits<2> op21_20, bits<4> op11_8, 
                string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
-  : N3V<0, 1, op21_20, op11_8, 1, 0,
-        (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
-        IIC_VMULi16D, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
-        [(set (Ty DPR:$dst),
-              (Ty (ShOp (Ty DPR:$src1),
-                        (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
+  : N3Vf<0, 1, op21_20, op11_8, 1, 0,
+         (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
+         NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
+         [(set (Ty DPR:$dst),
+               (Ty (ShOp (Ty DPR:$src1),
+                         (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
   let isCommutable = 0;
 }
 
@@ -992,24 +993,24 @@
 class N3VQSL<bits<2> op21_20, bits<4> op11_8, 
              InstrItinClass itin, string OpcodeStr, string Dt,
              ValueType ResTy, ValueType OpTy, SDNode ShOp>
-  : N3V<1, 1, op21_20, op11_8, 1, 0,
-        (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
-        itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
-        [(set (ResTy QPR:$dst),
-              (ResTy (ShOp (ResTy QPR:$src1),
-                           (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
-                                                imm:$lane)))))]> {
+  : N3Vf<1, 1, op21_20, op11_8, 1, 0,
+         (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
+         NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
+         [(set (ResTy QPR:$dst),
+               (ResTy (ShOp (ResTy QPR:$src1),
+                            (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
+                                                 imm:$lane)))))]> {
   let isCommutable = 0;
 }
 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
                ValueType ResTy, ValueType OpTy, SDNode ShOp>
-  : N3V<1, 1, op21_20, op11_8, 1, 0,
-        (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
-        IIC_VMULi16Q, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
-        [(set (ResTy QPR:$dst),
-              (ResTy (ShOp (ResTy QPR:$src1),
-                           (ResTy (NEONvduplane (OpTy DPR_8:$src2),
-                                                imm:$lane)))))]> {
+  : N3Vf<1, 1, op21_20, op11_8, 1, 0,
+         (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
+         NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
+         [(set (ResTy QPR:$dst),
+               (ResTy (ShOp (ResTy QPR:$src1),
+                            (ResTy (NEONvduplane (OpTy DPR_8:$src2),
+                                                 imm:$lane)))))]> {
   let isCommutable = 0;
 }
 
@@ -1025,24 +1026,24 @@
 }
 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 
                 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
-  : N3V<0, 1, op21_20, op11_8, 1, 0,
-        (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
-        itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
-        [(set (Ty DPR:$dst),
-              (Ty (IntOp (Ty DPR:$src1),
-                         (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
-                                           imm:$lane)))))]> {
+  : N3Vf<0, 1, op21_20, op11_8, 1, 0,
+         (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
+         NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
+         [(set (Ty DPR:$dst),
+               (Ty (IntOp (Ty DPR:$src1),
+                          (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
+                                            imm:$lane)))))]> {
   let isCommutable = 0;
 }
 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
                   string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
-  : N3V<0, 1, op21_20, op11_8, 1, 0,
-        (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
-        itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
-        [(set (Ty DPR:$dst),
-              (Ty (IntOp (Ty DPR:$src1),
-                         (Ty (NEONvduplane (Ty DPR_8:$src2),
-                                           imm:$lane)))))]> {
+  : N3Vf<0, 1, op21_20, op11_8, 1, 0,
+         (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
+         NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
+         [(set (Ty DPR:$dst),
+               (Ty (IntOp (Ty DPR:$src1),
+                          (Ty (NEONvduplane (Ty DPR_8:$src2),
+                                            imm:$lane)))))]> {
   let isCommutable = 0;
 }
 
@@ -1058,25 +1059,25 @@
 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 
                 string OpcodeStr, string Dt,
                 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
-  : N3V<1, 1, op21_20, op11_8, 1, 0,
-        (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
-        itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
-        [(set (ResTy QPR:$dst),
-              (ResTy (IntOp (ResTy QPR:$src1),
-                            (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
-                                                 imm:$lane)))))]> {
+  : N3Vf<1, 1, op21_20, op11_8, 1, 0,
+         (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
+         NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
+         [(set (ResTy QPR:$dst),
+               (ResTy (IntOp (ResTy QPR:$src1),
+                             (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
+                                                  imm:$lane)))))]> {
   let isCommutable = 0;
 }
 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
                   string OpcodeStr, string Dt,
                   ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
-  : N3V<1, 1, op21_20, op11_8, 1, 0,
-        (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
-        itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
-        [(set (ResTy QPR:$dst),
-              (ResTy (IntOp (ResTy QPR:$src1),
-                            (ResTy (NEONvduplane (OpTy DPR_8:$src2),
-                                                 imm:$lane)))))]> {
+  : N3Vf<1, 1, op21_20, op11_8, 1, 0,
+         (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
+         NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
+         [(set (ResTy QPR:$dst),
+               (ResTy (IntOp (ResTy QPR:$src1),
+                             (ResTy (NEONvduplane (OpTy DPR_8:$src2),
+                                                  imm:$lane)))))]> {
   let isCommutable = 0;
 }
 
@@ -1100,27 +1101,29 @@
 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
                   string OpcodeStr, string Dt,
                   ValueType Ty, SDNode MulOp, SDNode ShOp>
-  : N3V<0, 1, op21_20, op11_8, 1, 0,
-        (outs DPR:$dst),
-        (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
-        OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
-        [(set (Ty DPR:$dst),
-              (Ty (ShOp (Ty DPR:$src1),
-                        (Ty (MulOp DPR:$src2,
-                                   (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
-                                                     imm:$lane)))))))]>;
+  : N3Vf<0, 1, op21_20, op11_8, 1, 0,
+         (outs DPR:$dst),
+         (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
+         NVMulSLFrm, itin,
+         OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
+         [(set (Ty DPR:$dst),
+               (Ty (ShOp (Ty DPR:$src1),
+                         (Ty (MulOp DPR:$src2,
+                                    (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
+                                                      imm:$lane)))))))]>;
 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
                     string OpcodeStr, string Dt,
                     ValueType Ty, SDNode MulOp, SDNode ShOp>
-  : N3V<0, 1, op21_20, op11_8, 1, 0,
-        (outs DPR:$dst),
-        (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
-        OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
-        [(set (Ty DPR:$dst),
-              (Ty (ShOp (Ty DPR:$src1),
-                        (Ty (MulOp DPR:$src2,
-                                   (Ty (NEONvduplane (Ty DPR_8:$src3),
-                                                     imm:$lane)))))))]>;
+  : N3Vf<0, 1, op21_20, op11_8, 1, 0,
+         (outs DPR:$dst),
+         (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
+         NVMulSLFrm, itin,
+         OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
+         [(set (Ty DPR:$dst),
+               (Ty (ShOp (Ty DPR:$src1),
+                         (Ty (MulOp DPR:$src2,
+                                    (Ty (NEONvduplane (Ty DPR_8:$src3),
+                                                      imm:$lane)))))))]>;
 
 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
                 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
@@ -1133,28 +1136,30 @@
 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
                   string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
                   SDNode MulOp, SDNode ShOp>
-  : N3V<1, 1, op21_20, op11_8, 1, 0,
-        (outs QPR:$dst),
-        (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
-        OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
-        [(set (ResTy QPR:$dst),
-              (ResTy (ShOp (ResTy QPR:$src1),
-                           (ResTy (MulOp QPR:$src2,
-                                   (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
-                                                        imm:$lane)))))))]>;
+  : N3Vf<1, 1, op21_20, op11_8, 1, 0,
+         (outs QPR:$dst),
+         (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
+         NVMulSLFrm, itin,
+         OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
+         [(set (ResTy QPR:$dst),
+               (ResTy (ShOp (ResTy QPR:$src1),
+                            (ResTy (MulOp QPR:$src2,
+                                    (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
+                                                         imm:$lane)))))))]>;
 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
                     string OpcodeStr, string Dt,
                     ValueType ResTy, ValueType OpTy,
                     SDNode MulOp, SDNode ShOp>
-  : N3V<1, 1, op21_20, op11_8, 1, 0,
-        (outs QPR:$dst),
-        (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
-        OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
-        [(set (ResTy QPR:$dst),
-              (ResTy (ShOp (ResTy QPR:$src1),
-                           (ResTy (MulOp QPR:$src2,
-                                   (ResTy (NEONvduplane (OpTy DPR_8:$src3),
-                                                        imm:$lane)))))))]>;
+  : N3Vf<1, 1, op21_20, op11_8, 1, 0,
+         (outs QPR:$dst),
+         (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane),
+         NVMulSLFrm, itin,
+         OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
+         [(set (ResTy QPR:$dst),
+               (ResTy (ShOp (ResTy QPR:$src1),
+                            (ResTy (MulOp QPR:$src2,
+                                    (ResTy (NEONvduplane (OpTy DPR_8:$src3),
+                                                         imm:$lane)))))))]>;
 
 // Neon 3-argument intrinsics, both double- and quad-register.
 // The destination register is also used as the first source operand register.
@@ -1188,27 +1193,29 @@
 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
                  string OpcodeStr, string Dt,
                  ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
-  : N3V<op24, 1, op21_20, op11_8, 1, 0,
-        (outs QPR:$dst),
-        (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
-        OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
-        [(set (ResTy QPR:$dst),
-              (ResTy (IntOp (ResTy QPR:$src1),
-                            (OpTy DPR:$src2),
-                            (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
-                                                imm:$lane)))))]>;
+  : N3Vf<op24, 1, op21_20, op11_8, 1, 0,
+         (outs QPR:$dst),
+         (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
+         NVMulSLFrm, itin,
+         OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
+         [(set (ResTy QPR:$dst),
+               (ResTy (IntOp (ResTy QPR:$src1),
+                             (OpTy DPR:$src2),
+                             (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
+                                                 imm:$lane)))))]>;
 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
                    InstrItinClass itin, string OpcodeStr, string Dt,
                    ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
-  : N3V<op24, 1, op21_20, op11_8, 1, 0,
-        (outs QPR:$dst),
-        (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
-        OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
-        [(set (ResTy QPR:$dst),
-              (ResTy (IntOp (ResTy QPR:$src1),
-                            (OpTy DPR:$src2),
-                            (OpTy (NEONvduplane (OpTy DPR_8:$src3),
-                                                imm:$lane)))))]>;
+  : N3Vf<op24, 1, op21_20, op11_8, 1, 0,
+         (outs QPR:$dst),
+         (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
+         NVMulSLFrm, itin,
+         OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
+         [(set (ResTy QPR:$dst),
+               (ResTy (IntOp (ResTy QPR:$src1),
+                             (OpTy DPR:$src2),
+                             (OpTy (NEONvduplane (OpTy DPR_8:$src3),
+                                                 imm:$lane)))))]>;
 
 // Narrowing 3-register intrinsics.
 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
@@ -1234,23 +1241,23 @@
 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
                 string OpcodeStr, string Dt,
                 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
-  : N3V<op24, 1, op21_20, op11_8, 1, 0,
-        (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane), 
-        itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
-        [(set (ResTy QPR:$dst),
-              (ResTy (IntOp (OpTy DPR:$src1),
-                            (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
-                                                imm:$lane)))))]>;
+  : N3Vf<op24, 1, op21_20, op11_8, 1, 0,
+         (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
+         NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
+         [(set (ResTy QPR:$dst),
+               (ResTy (IntOp (OpTy DPR:$src1),
+                             (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
+                                                 imm:$lane)))))]>;
 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
                   InstrItinClass itin, string OpcodeStr, string Dt,
                   ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
-  : N3V<op24, 1, op21_20, op11_8, 1, 0,
-        (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane), 
-        itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
-        [(set (ResTy QPR:$dst),
-              (ResTy (IntOp (OpTy DPR:$src1),
-                            (OpTy (NEONvduplane (OpTy DPR_8:$src2),
-                                                imm:$lane)))))]>;
+  : N3Vf<op24, 1, op21_20, op11_8, 1, 0,
+         (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane), 
+         NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
+         [(set (ResTy QPR:$dst),
+               (ResTy (IntOp (OpTy DPR:$src1),
+                             (OpTy (NEONvduplane (OpTy DPR_8:$src2),
+                                                 imm:$lane)))))]>;
 
 // Wide 3-register intrinsics.
 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,




From isanbard at gmail.com  Fri Mar 26 20:19:12 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Sat, 27 Mar 2010 01:19:12 -0000
Subject: [llvm-commits] [llvm] r99692 -
	/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
Message-ID: <20100327011912.2B8132A6C12C@llvm.org>

Author: void
Date: Fri Mar 26 20:19:12 2010
New Revision: 99692

URL: http://llvm.org/viewvc/llvm-project?rev=99692&view=rev
Log:
If a selector has a call to ".llvm.eh.catch.all.value" that we haven't
converted, then use the initializer, since using the name itself won't work.

Modified:
    llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp

Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=99692&r1=99691&r2=99692&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Fri Mar 26 20:19:12 2010
@@ -83,6 +83,11 @@
         CreateExceptionValueCall(BB) : CreateValueLoad(BB);
     }
 
+    /// CleanupSelectors - Any remaining eh.selector intrinsic calls which still
+    /// use the ".llvm.eh.catch.all.value" call need to convert to using it's
+    /// initializer instead.
+    void CleanupSelectors();
+
     /// HandleURoRInvokes - Handle invokes of "_Unwind_Resume_or_Rethrow"
     /// calls. The "unwind" part of these invokes jump to a landing pad within
     /// the current function. This is a candidate to merge the selector
@@ -212,6 +217,24 @@
   return Changed;
 }
 
+/// CleanupSelectors - Any remaining eh.selector intrinsic calls which still use
+/// the ".llvm.eh.catch.all.value" call need to convert to using it's
+/// initializer instead.
+void DwarfEHPrepare::CleanupSelectors() {
+  for (Value::use_iterator
+         I = SelectorIntrinsic->use_begin(),
+         E = SelectorIntrinsic->use_end(); I != E; ++I) {
+    IntrinsicInst *Sel = dyn_cast<IntrinsicInst>(I);
+    if (!Sel || Sel->getParent()->getParent() != F) continue;
+
+    // Index of the ".llvm.eh.catch.all.value" variable.
+    unsigned OpIdx = Sel->getNumOperands() - 1;
+    GlobalVariable *GV = dyn_cast<GlobalVariable>(Sel->getOperand(OpIdx));
+    if (GV != EHCatchAllValue) continue;
+    Sel->setOperand(OpIdx, EHCatchAllValue->getInitializer());
+  }
+}
+
 /// HandleURoRInvokes - Handle invokes of "_Unwind_Resume_or_Rethrow" calls. The
 /// "unwind" part of these invokes jump to a landing pad within the current
 /// function. This is a candidate to merge the selector associated with the URoR
@@ -223,21 +246,27 @@
     if (!EHCatchAllValue) return false;
   }
 
+  if (!SelectorIntrinsic) {
+    SelectorIntrinsic =
+      Intrinsic::getDeclaration(F->getParent(), Intrinsic::eh_selector);
+    if (!SelectorIntrinsic) return false;
+  }
+
   if (!URoR) {
     URoR = F->getParent()->getFunction("_Unwind_Resume_or_Rethrow");
-    if (!URoR) return false;
+    if (!URoR) {
+      CleanupSelectors();
+      return false;
+    }
   }
 
   if (!ExceptionValueIntrinsic) {
     ExceptionValueIntrinsic =
       Intrinsic::getDeclaration(F->getParent(), Intrinsic::eh_exception);
-    if (!ExceptionValueIntrinsic) return false;
-  }
-
-  if (!SelectorIntrinsic) {
-    SelectorIntrinsic =
-      Intrinsic::getDeclaration(F->getParent(), Intrinsic::eh_selector);
-    if (!SelectorIntrinsic) return false;
+    if (!ExceptionValueIntrinsic) {
+      CleanupSelectors();
+      return false;
+    }
   }
 
   bool Changed = false;
@@ -308,6 +337,7 @@
     }
   }
 
+  CleanupSelectors();
   return Changed;
 }
 




From isanbard at gmail.com  Fri Mar 26 20:19:48 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Sat, 27 Mar 2010 01:19:48 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r99693 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <20100327011948.8E0BE2A6C12C@llvm.org>

Author: void
Date: Fri Mar 26 20:19:48 2010
New Revision: 99693

URL: http://llvm.org/viewvc/llvm-project?rev=99693&view=rev
Log:
Recommit r99670 now that r99692 fixes it.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=99693&r1=99692&r2=99693&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Fri Mar 26 20:19:48 2010
@@ -2089,6 +2089,9 @@
     // Add selections for each handler.
     foreach_reachable_handler(i, false, AddHandler, &Handlers);
 
+    bool HasCleanup = false;
+    static Value *CatchAll = 0;
+
     for (std::vector<struct eh_region *>::iterator I = Handlers.begin(),
          E = Handlers.end(); I != E; ++I) {
       struct eh_region *region = *I;
@@ -2115,9 +2118,16 @@
 
         if (!TypeList) {
           // Catch-all - push a null pointer.
-          Args.push_back(
-            Constant::getNullValue(Type::getInt8PtrTy(Context))
-          );
+          if (!CatchAll) {
+            Constant *Init =
+              Constant::getNullValue(Type::getInt8PtrTy(Context));
+
+            CatchAll = new GlobalVariable(*TheModule, Init->getType(), true,
+                                          GlobalVariable::LinkOnceAnyLinkage,
+                                          Init, ".llvm.eh.catch.all.value");
+          }
+
+          Args.push_back(CatchAll);
         } else {
           // Add the type infos.
           for (; TypeList; TypeList = TREE_CHAIN(TypeList)) {
@@ -2125,30 +2135,43 @@
             Args.push_back(Emit(TType, 0));
           }
         }
+      } else {
+        // Cleanup.
+        HasCleanup = true;
       }
     }
 
     if (can_throw_external_1(i, false)) {
-      // Some exceptions from this region may not be caught by any handler.
-      // Since invokes are required to branch to the unwind label no matter
-      // what exception is being unwound, append a catch-all.
-
-      // The representation of a catch-all is language specific.
-      Value *CatchAll;
-      if (USING_SJLJ_EXCEPTIONS || !lang_eh_catch_all) {
-        // Use a "cleanup" - this should be good enough for most languages.
-        CatchAll = ConstantInt::get(Type::getInt32Ty(Context), 0);
+      if (HasCleanup && Args.size() == 2) {
+        Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), 0));
       } else {
-        tree catch_all_type = lang_eh_catch_all();
-        if (catch_all_type == NULL_TREE)
-          // Use a C++ style null catch-all object.
-          CatchAll = Constant::getNullValue(
-                                    Type::getInt8PtrTy(Context));
-        else
-          // This language has a type that catches all others.
-          CatchAll = Emit(catch_all_type, 0);
+        // Some exceptions from this region may not be caught by any handler.
+        // Since invokes are required to branch to the unwind label no matter
+        // what exception is being unwound, append a catch-all.
+
+        // The representation of a catch-all is language specific.
+        if (USING_SJLJ_EXCEPTIONS || !lang_eh_catch_all) {
+          // Use a "cleanup" - this should be good enough for most languages.
+          Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), 0));
+        } else {
+          if (!CatchAll) {
+            Constant *Init = 0;
+            tree catch_all_type = lang_eh_catch_all();
+            if (catch_all_type == NULL_TREE)
+              // Use a C++ style null catch-all object.
+              Init = Constant::getNullValue(Type::getInt8PtrTy(Context));
+            else
+              // This language has a type that catches all others.
+              Init = cast<Constant>(Emit(catch_all_type, 0));
+
+            CatchAll = new GlobalVariable(*TheModule, Init->getType(), true,
+                                          GlobalVariable::PrivateLinkage,
+                                          Init, ".llvm.eh.catch.all.value");
+          }
+
+          Args.push_back(CatchAll);
+        }
       }
-      Args.push_back(CatchAll);
     }
 
     // Emit the selector call.




From isanbard at gmail.com  Fri Mar 26 20:22:38 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Sat, 27 Mar 2010 01:22:38 -0000
Subject: [llvm-commits] [llvm] r99695 -
	/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
Message-ID: <20100327012238.3DF692A6C12C@llvm.org>

Author: void
Date: Fri Mar 26 20:22:38 2010
New Revision: 99695

URL: http://llvm.org/viewvc/llvm-project?rev=99695&view=rev
Log:
Return if we changed anything or not.

Modified:
    llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp

Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=99695&r1=99694&r2=99695&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Fri Mar 26 20:22:38 2010
@@ -86,7 +86,7 @@
     /// CleanupSelectors - Any remaining eh.selector intrinsic calls which still
     /// use the ".llvm.eh.catch.all.value" call need to convert to using it's
     /// initializer instead.
-    void CleanupSelectors();
+    bool CleanupSelectors();
 
     /// HandleURoRInvokes - Handle invokes of "_Unwind_Resume_or_Rethrow"
     /// calls. The "unwind" part of these invokes jump to a landing pad within
@@ -220,7 +220,8 @@
 /// CleanupSelectors - Any remaining eh.selector intrinsic calls which still use
 /// the ".llvm.eh.catch.all.value" call need to convert to using it's
 /// initializer instead.
-void DwarfEHPrepare::CleanupSelectors() {
+bool DwarfEHPrepare::CleanupSelectors() {
+  bool Changed = false;
   for (Value::use_iterator
          I = SelectorIntrinsic->use_begin(),
          E = SelectorIntrinsic->use_end(); I != E; ++I) {
@@ -232,7 +233,10 @@
     GlobalVariable *GV = dyn_cast<GlobalVariable>(Sel->getOperand(OpIdx));
     if (GV != EHCatchAllValue) continue;
     Sel->setOperand(OpIdx, EHCatchAllValue->getInitializer());
+    Changed = true;
   }
+
+  return Changed;
 }
 
 /// HandleURoRInvokes - Handle invokes of "_Unwind_Resume_or_Rethrow" calls. The
@@ -254,19 +258,13 @@
 
   if (!URoR) {
     URoR = F->getParent()->getFunction("_Unwind_Resume_or_Rethrow");
-    if (!URoR) {
-      CleanupSelectors();
-      return false;
-    }
+    if (!URoR) return CleanupSelectors();
   }
 
   if (!ExceptionValueIntrinsic) {
     ExceptionValueIntrinsic =
       Intrinsic::getDeclaration(F->getParent(), Intrinsic::eh_exception);
-    if (!ExceptionValueIntrinsic) {
-      CleanupSelectors();
-      return false;
-    }
+    if (!ExceptionValueIntrinsic) return CleanupSelectors();
   }
 
   bool Changed = false;
@@ -337,7 +335,7 @@
     }
   }
 
-  CleanupSelectors();
+  Changed |= CleanupSelectors();
   return Changed;
 }
 




From isanbard at gmail.com  Fri Mar 26 20:24:30 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Sat, 27 Mar 2010 01:24:30 -0000
Subject: [llvm-commits] [llvm] r99697 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
Message-ID: <20100327012430.A4E6F2A6C12C@llvm.org>

Author: void
Date: Fri Mar 26 20:24:30 2010
New Revision: 99697

URL: http://llvm.org/viewvc/llvm-project?rev=99697&view=rev
Log:
Forgot the part where we handle the ".llvm.eh.catch.all.value".

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=99697&r1=99696&r2=99697&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Fri Mar 26 20:24:30 2010
@@ -281,8 +281,17 @@
 GlobalVariable *llvm::ExtractTypeInfo(Value *V) {
   V = V->stripPointerCasts();
   GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
-  assert ((GV || isa<ConstantPointerNull>(V)) &&
-          "TypeInfo must be a global variable or NULL");
+
+  if (GV && GV->getName() == ".llvm.eh.catch.all.value") {
+    assert(GV->hasInitializer() &&
+           "The EH catch-all value must have an initializer");
+    Value *Init = GV->getInitializer();
+    GV = dyn_cast<GlobalVariable>(Init);
+    if (!GV) V = cast<ConstantPointerNull>(Init);
+  }
+
+  assert((GV || isa<ConstantPointerNull>(V)) &&
+         "TypeInfo must be a global variable or NULL");
   return GV;
 }
 




From echristo at apple.com  Fri Mar 26 20:54:01 2010
From: echristo at apple.com (Eric Christopher)
Date: Sat, 27 Mar 2010 01:54:01 -0000
Subject: [llvm-commits] [llvm] r99699 -
	/llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp
Message-ID: <20100327015401.1885A2A6C12C@llvm.org>

Author: echristo
Date: Fri Mar 26 20:54:00 2010
New Revision: 99699

URL: http://llvm.org/viewvc/llvm-project?rev=99699&view=rev
Log:
When we promote a load of an argument make sure to take the alignment
of the previous load - it's usually important.  For example, we don't want
to blindly turn an unaligned load into an aligned one.

Modified:
    llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp

Modified: llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp?rev=99699&r1=99698&r2=99699&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp Fri Mar 26 20:54:00 2010
@@ -687,7 +687,11 @@
             Ops.clear();
             AA.copyValue(OrigLoad->getOperand(0), V);
           }
-          Args.push_back(new LoadInst(V, V->getName()+".val", Call));
+          // Since we're replacing a load make sure we take the alignment
+          // of the previous load.
+          LoadInst *newLoad = new LoadInst(V, V->getName()+".val", Call);
+          newLoad->setAlignment(OrigLoad->getAlignment());
+          Args.push_back(newLoad);
           AA.copyValue(OrigLoad, Args.back());
         }
       }




From sabre at nondot.org  Fri Mar 26 21:47:14 2010
From: sabre at nondot.org (Chris Lattner)
Date: Sat, 27 Mar 2010 02:47:14 -0000
Subject: [llvm-commits] [llvm] r99700 - in /llvm/trunk/lib/Target/X86:
 X86Instr64bit.td X86InstrInfo.td
Message-ID: <20100327024714.A6AB52A6C12C@llvm.org>

Author: lattner
Date: Fri Mar 26 21:47:14 2010
New Revision: 99700

URL: http://llvm.org/viewvc/llvm-project?rev=99700&view=rev
Log:
eliminate the last of the parallel's!

Modified:
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=99700&r1=99699&r2=99700&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Fri Mar 26 21:47:14 2010
@@ -508,8 +508,8 @@
 def ADD64rr    : RI<0x01, MRMDestReg, (outs GR64:$dst), 
                     (ins GR64:$src1, GR64:$src2),
                     "add{q}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
-                     (implicit EFLAGS)]>;
+                    [(set GR64:$dst, EFLAGS,
+                          (X86add_flag GR64:$src1, GR64:$src2))]>;
 
 // These are alternate spellings for use by the disassembler, we mark them as
 // code gen only to ensure they aren't matched by the assembler.
@@ -523,21 +523,21 @@
 def ADD64ri8  : RIi8<0x83, MRM0r, (outs GR64:$dst), 
                      (ins GR64:$src1, i64i8imm:$src2),
                      "add{q}\t{$src2, $dst|$dst, $src2}",
-                     [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
-                      (implicit EFLAGS)]>;
+                     [(set GR64:$dst, EFLAGS,
+                           (X86add_flag GR64:$src1, i64immSExt8:$src2))]>;
 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), 
                       (ins GR64:$src1, i64i32imm:$src2),
                       "add{q}\t{$src2, $dst|$dst, $src2}",
-                      [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
-                       (implicit EFLAGS)]>;
+                      [(set GR64:$dst, EFLAGS,
+                            (X86add_flag GR64:$src1, i64immSExt32:$src2))]>;
 } // isConvertibleToThreeAddress
 
 // Register-Memory Addition
 def ADD64rm     : RI<0x03, MRMSrcMem, (outs GR64:$dst), 
                      (ins GR64:$src1, i64mem:$src2),
                      "add{q}\t{$src2, $dst|$dst, $src2}",
-                     [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
-                      (implicit EFLAGS)]>;
+                     [(set GR64:$dst, EFLAGS,
+                           (X86add_flag GR64:$src1, (load addr:$src2)))]>;
 
 } // isTwoAddress
 
@@ -604,8 +604,8 @@
 def SUB64rr  : RI<0x29, MRMDestReg, (outs GR64:$dst), 
                   (ins GR64:$src1, GR64:$src2),
                   "sub{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
-                   (implicit EFLAGS)]>;
+                  [(set GR64:$dst, EFLAGS,
+                        (X86sub_flag GR64:$src1, GR64:$src2))]>;
 
 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst), 
                      (ins GR64:$src1, GR64:$src2),
@@ -615,20 +615,20 @@
 def SUB64rm  : RI<0x2B, MRMSrcMem, (outs GR64:$dst), 
                   (ins GR64:$src1, i64mem:$src2),
                   "sub{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
-                   (implicit EFLAGS)]>;
+                  [(set GR64:$dst, EFLAGS, 
+                        (X86sub_flag GR64:$src1, (load addr:$src2)))]>;
 
 // Register-Integer Subtraction
 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
                                  (ins GR64:$src1, i64i8imm:$src2),
                     "sub{q}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
-                     (implicit EFLAGS)]>;
+                    [(set GR64:$dst, EFLAGS,
+                          (X86sub_flag GR64:$src1, i64immSExt8:$src2))]>;
 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
                                    (ins GR64:$src1, i64i32imm:$src2),
                       "sub{q}\t{$src2, $dst|$dst, $src2}",
-                      [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
-                       (implicit EFLAGS)]>;
+                      [(set GR64:$dst, EFLAGS,
+                            (X86sub_flag GR64:$src1, i64immSExt32:$src2))]>;
 } // isTwoAddress
 
 def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i32imm:$src),
@@ -716,15 +716,15 @@
 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
                                    (ins GR64:$src1, GR64:$src2),
                   "imul{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
-                   (implicit EFLAGS)]>, TB;
+                  [(set GR64:$dst, EFLAGS,
+                        (X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
 
 // Register-Memory Signed Integer Multiplication
 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
                                    (ins GR64:$src1, i64mem:$src2),
                   "imul{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
-                   (implicit EFLAGS)]>, TB;
+                  [(set GR64:$dst, EFLAGS,
+                        (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
 } // isTwoAddress
 
 // Suprisingly enough, these are not two address instructions!
@@ -733,27 +733,27 @@
 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg,                      // GR64 = GR64*I8
                       (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
                       "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                      [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
-                       (implicit EFLAGS)]>;
+                      [(set GR64:$dst, EFLAGS,
+                            (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
 def IMUL64rri32 : RIi32<0x69, MRMSrcReg,                    // GR64 = GR64*I32
                         (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
                         "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                       [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
-                        (implicit EFLAGS)]>;
+                       [(set GR64:$dst, EFLAGS,
+                             (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
 
 // Memory-Integer Signed Integer Multiplication
 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem,                      // GR64 = [mem64]*I8
                       (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
                       "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                      [(set GR64:$dst, (mul (load addr:$src1),
-                                            i64immSExt8:$src2)),
-                       (implicit EFLAGS)]>;
+                      [(set GR64:$dst, EFLAGS,
+                            (X86smul_flag (load addr:$src1),
+                                          i64immSExt8:$src2))]>;
 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem,                   // GR64 = [mem64]*I32
                         (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
                         "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                        [(set GR64:$dst, (mul (load addr:$src1),
-                                              i64immSExt32:$src2)),
-                         (implicit EFLAGS)]>;
+                        [(set GR64:$dst, EFLAGS,
+                              (X86smul_flag (load addr:$src1),
+                                            i64immSExt32:$src2))]>;
 } // Defs = [EFLAGS]
 
 // Unsigned division / remainder
@@ -787,16 +787,14 @@
 
 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
-                [(set GR64:$dst, (add GR64:$src, 1)),
-                 (implicit EFLAGS)]>;
+                [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src))]>;
 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
                 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
                  (implicit EFLAGS)]>;
 
 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
-                [(set GR64:$dst, (add GR64:$src, -1)),
-                 (implicit EFLAGS)]>;
+                [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src))]>;
 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
                 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
                  (implicit EFLAGS)]>;
@@ -806,23 +804,19 @@
 // Can transform into LEA.
 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), 
                   "inc{w}\t$dst",
-                  [(set GR16:$dst, (add GR16:$src, 1)),
-                   (implicit EFLAGS)]>,
+                  [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src))]>,
                 OpSize, Requires<[In64BitMode]>;
 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), 
                   "inc{l}\t$dst",
-                  [(set GR32:$dst, (add GR32:$src, 1)),
-                   (implicit EFLAGS)]>,
+                  [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src))]>,
                 Requires<[In64BitMode]>;
 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), 
                   "dec{w}\t$dst",
-                  [(set GR16:$dst, (add GR16:$src, -1)),
-                   (implicit EFLAGS)]>,
+                  [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src))]>,
                 OpSize, Requires<[In64BitMode]>;
 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), 
                   "dec{l}\t$dst",
-                  [(set GR32:$dst, (add GR32:$src, -1)),
-                   (implicit EFLAGS)]>,
+                  [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>,
                 Requires<[In64BitMode]>;
 } // isConvertibleToThreeAddress
 
@@ -1092,26 +1086,26 @@
 def AND64rr  : RI<0x21, MRMDestReg, 
                   (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
                   "and{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
-                   (implicit EFLAGS)]>;
+                  [(set GR64:$dst, EFLAGS,
+                        (X86and_flag GR64:$src1, GR64:$src2))]>;
 def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst), 
                      (ins GR64:$src1, GR64:$src2),
                      "and{q}\t{$src2, $dst|$dst, $src2}", []>;
 def AND64rm  : RI<0x23, MRMSrcMem,
                   (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
                   "and{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
-                   (implicit EFLAGS)]>;
+                  [(set GR64:$dst, EFLAGS,
+                        (X86and_flag GR64:$src1, (load addr:$src2)))]>;
 def AND64ri8 : RIi8<0x83, MRM4r, 
                     (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
                     "and{q}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
-                     (implicit EFLAGS)]>;
+                    [(set GR64:$dst, EFLAGS,
+                          (X86and_flag GR64:$src1, i64immSExt8:$src2))]>;
 def AND64ri32  : RIi32<0x81, MRM4r, 
                        (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
                        "and{q}\t{$src2, $dst|$dst, $src2}",
-                       [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
-                        (implicit EFLAGS)]>;
+                       [(set GR64:$dst, EFLAGS,
+                             (X86and_flag GR64:$src1, i64immSExt32:$src2))]>;
 } // isTwoAddress
 
 def AND64mr  : RI<0x21, MRMDestMem,
@@ -1135,26 +1129,26 @@
 def OR64rr   : RI<0x09, MRMDestReg, (outs GR64:$dst), 
                   (ins GR64:$src1, GR64:$src2),
                   "or{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
-                   (implicit EFLAGS)]>;
+                  [(set GR64:$dst, EFLAGS,
+                        (X86or_flag GR64:$src1, GR64:$src2))]>;
 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst), 
                     (ins GR64:$src1, GR64:$src2),
                     "or{q}\t{$src2, $dst|$dst, $src2}", []>;
 def OR64rm   : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
                   (ins GR64:$src1, i64mem:$src2),
                   "or{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
-                   (implicit EFLAGS)]>;
+                  [(set GR64:$dst, EFLAGS,
+                        (X86or_flag GR64:$src1, (load addr:$src2)))]>;
 def OR64ri8  : RIi8<0x83, MRM1r, (outs GR64:$dst),
                     (ins GR64:$src1, i64i8imm:$src2),
                     "or{q}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
-                    (implicit EFLAGS)]>;
+                   [(set GR64:$dst, EFLAGS,
+                         (X86or_flag GR64:$src1, i64immSExt8:$src2))]>;
 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
                      (ins GR64:$src1, i64i32imm:$src2),
                      "or{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
-                    (implicit EFLAGS)]>;
+                  [(set GR64:$dst, EFLAGS,
+                        (X86or_flag GR64:$src1, i64immSExt32:$src2))]>;
 } // isTwoAddress
 
 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
@@ -1178,26 +1172,26 @@
 def XOR64rr  : RI<0x31, MRMDestReg,  (outs GR64:$dst), 
                   (ins GR64:$src1, GR64:$src2), 
                   "xor{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
-                   (implicit EFLAGS)]>;
+                  [(set GR64:$dst, EFLAGS,
+                        (X86xor_flag GR64:$src1, GR64:$src2))]>;
 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst), 
                      (ins GR64:$src1, GR64:$src2),
                     "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
 def XOR64rm  : RI<0x33, MRMSrcMem, (outs GR64:$dst), 
                   (ins GR64:$src1, i64mem:$src2), 
                   "xor{q}\t{$src2, $dst|$dst, $src2}",
-                  [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
-                   (implicit EFLAGS)]>;
+                  [(set GR64:$dst, EFLAGS,
+                        (X86xor_flag GR64:$src1, (load addr:$src2)))]>;
 def XOR64ri8 : RIi8<0x83, MRM6r,  (outs GR64:$dst), 
                     (ins GR64:$src1, i64i8imm:$src2),
                     "xor{q}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
-                     (implicit EFLAGS)]>;
+                    [(set GR64:$dst, EFLAGS,
+                          (X86xor_flag GR64:$src1, i64immSExt8:$src2))]>;
 def XOR64ri32 : RIi32<0x81, MRM6r, 
                       (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 
                       "xor{q}\t{$src2, $dst|$dst, $src2}",
-                      [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
-                       (implicit EFLAGS)]>;
+                      [(set GR64:$dst, EFLAGS,
+                            (X86xor_flag GR64:$src1, i64immSExt32:$src2))]>;
 } // isTwoAddress
 
 def XOR64mr  : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
@@ -2212,136 +2206,76 @@
 // EFLAGS-defining Patterns
 //===----------------------------------------------------------------------===//
 
-// Register-Register Addition with EFLAGS result
-def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
-                    (implicit EFLAGS)),
+// addition
+def : Pat<(add GR64:$src1, GR64:$src2),
           (ADD64rr GR64:$src1, GR64:$src2)>;
-
-// Register-Integer Addition with EFLAGS result
-def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(add GR64:$src1, i64immSExt8:$src2),
           (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
-def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(add GR64:$src1, i64immSExt32:$src2),
           (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
-
-// Register-Memory Addition with EFLAGS result
-def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
           (ADD64rm GR64:$src1, addr:$src2)>;
 
-// Register-Register Subtraction with EFLAGS result
-def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
-                    (implicit EFLAGS)),
+// subtraction
+def : Pat<(sub GR64:$src1, GR64:$src2),
           (SUB64rr GR64:$src1, GR64:$src2)>;
-
-// Register-Memory Subtraction with EFLAGS result
-def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
           (SUB64rm GR64:$src1, addr:$src2)>;
-
-// Register-Integer Subtraction with EFLAGS result
-def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
           (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
-def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
           (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
 
-// Register-Register Signed Integer Multiplication with EFLAGS result
-def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
-                    (implicit EFLAGS)),
+// Multiply
+def : Pat<(mul GR64:$src1, GR64:$src2),
           (IMUL64rr GR64:$src1, GR64:$src2)>;
-
-// Register-Memory Signed Integer Multiplication with EFLAGS result
-def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
           (IMUL64rm GR64:$src1, addr:$src2)>;
-
-// Register-Integer Signed Integer Multiplication with EFLAGS result
-def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
           (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
-def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
           (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
-
-// Memory-Integer Signed Integer Multiplication with EFLAGS result
-def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
           (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
-def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
           (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
 
-// INC and DEC with EFLAGS result. Note that these do not set CF.
-def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
-          (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
-def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
-          (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
-
-def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
-          (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
-def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
-          (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
-
-def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
-          (INC64r GR64:$src)>;
-def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
-          (DEC64r GR64:$src)>;
-
-// Register-Register Logical Or with EFLAGS result
-def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
-                    (implicit EFLAGS)),
-          (OR64rr GR64:$src1, GR64:$src2)>;
+// inc/dec
+def : Pat<(add GR16:$src, 1),  (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
+def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
+def : Pat<(add GR32:$src, 1),  (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
+def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
+def : Pat<(add GR64:$src, 1),  (INC64r GR64:$src)>;
+def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
 
-// Register-Integer Logical Or with EFLAGS result
-def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt8:$src2),
-                    (implicit EFLAGS)),
+// or
+def : Pat<(or GR64:$src1, GR64:$src2),
+          (OR64rr GR64:$src1, GR64:$src2)>;
+def : Pat<(or GR64:$src1, i64immSExt8:$src2),
           (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
-def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt32:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(or GR64:$src1, i64immSExt32:$src2),
           (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
-
-// Register-Memory Logical Or with EFLAGS result
-def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
           (OR64rm GR64:$src1, addr:$src2)>;
 
-// Register-Register Logical XOr with EFLAGS result
-def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
-                    (implicit EFLAGS)),
+// xor
+def : Pat<(xor GR64:$src1, GR64:$src2),
           (XOR64rr GR64:$src1, GR64:$src2)>;
-
-// Register-Integer Logical XOr with EFLAGS result
-def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
           (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
-def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt32:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
           (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
-
-// Register-Memory Logical XOr with EFLAGS result
-def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
           (XOR64rm GR64:$src1, addr:$src2)>;
 
-// Register-Register Logical And with EFLAGS result
-def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
-                    (implicit EFLAGS)),
+// and
+def : Pat<(and GR64:$src1, GR64:$src2),
           (AND64rr GR64:$src1, GR64:$src2)>;
-
-// Register-Integer Logical And with EFLAGS result
-def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt8:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(and GR64:$src1, i64immSExt8:$src2),
           (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
-def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt32:$src2),
-                    (implicit EFLAGS)),
+def : Pat<(and GR64:$src1, i64immSExt32:$src2),
           (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
-
-// Register-Memory Logical And with EFLAGS result
-def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
-                    (implicit EFLAGS)),
+def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
           (AND64rm GR64:$src1, addr:$src2)>;
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=99700&r1=99699&r2=99700&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Mar 26 21:47:14 2010
@@ -4822,13 +4822,8 @@
 
 // Optimize multiply by 2 with EFLAGS result.
 let AddedComplexity = 2 in {
-def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
-                    (implicit EFLAGS)),
-          (ADD16rr GR16:$src1, GR16:$src1)>;
-
-def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
-                    (implicit EFLAGS)),
-          (ADD32rr GR32:$src1, GR32:$src1)>;
+def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
+def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
 }
 
 // Patterns for nodes that do not produce flags, for instructions that do.




From pwalton at mozilla.com  Fri Mar 26 21:35:17 2010
From: pwalton at mozilla.com (Patrick Walton)
Date: Fri, 26 Mar 2010 19:35:17 -0700
Subject: [llvm-commits] [PATCH] Use the ocamlfind module system
Message-ID: <4BAD6EE5.80505@mozilla.com>

Hi LLVM developers,

Here's a patch to use the ocamlfind package system for the OCaml 
bindings instead of manually installing the libraries into the OCaml 
libdir. ocamlfind is the standard package management system for OCaml - 
it provides a way for OCaml users of LLVM to figure out where the 
libraries are, much like llvm-config does for C++.

If anyone could review, it would be much appreciated!

Thanks,
Patrick
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From sabre at nondot.org  Fri Mar 26 21:53:28 2010
From: sabre at nondot.org (Chris Lattner)
Date: Sat, 27 Mar 2010 02:53:28 -0000
Subject: [llvm-commits] [llvm] r99703 - in /llvm/trunk:
 docs/TableGenFundamentals.html include/llvm/Target/TargetSelectionDAG.td
 utils/TableGen/CodeGenDAGPatterns.cpp
Message-ID: <20100327025328.557FE2A6C12C@llvm.org>

Author: lattner
Date: Fri Mar 26 21:53:27 2010
New Revision: 99703

URL: http://llvm.org/viewvc/llvm-project?rev=99703&view=rev
Log:
remove parallel support.

Modified:
    llvm/trunk/docs/TableGenFundamentals.html
    llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
    llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp

Modified: llvm/trunk/docs/TableGenFundamentals.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/TableGenFundamentals.html?rev=99703&r1=99702&r2=99703&view=diff
==============================================================================
--- llvm/trunk/docs/TableGenFundamentals.html (original)
+++ llvm/trunk/docs/TableGenFundamentals.html Fri Mar 26 21:53:27 2010
@@ -768,9 +768,6 @@
   <dd>an implicitly defined physical register.  This tells the dag instruction
   selection emitter the input pattern's extra definitions matches implicit
   physical register definitions.</dd>
-<dt><tt>(parallel (a), (b))</tt></dt>
-  <dd>a list of dags specifying parallel operations which map to the same
-  instruction.</dd>
 
 </div>
 

Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=99703&r1=99702&r2=99703&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Fri Mar 26 21:53:27 2010
@@ -235,7 +235,6 @@
 // Special TableGen-recognized dag nodes
 def set;
 def implicit;
-def parallel;
 def node;
 def srcvalue;
 

Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=99703&r1=99702&r2=99703&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Fri Mar 26 21:53:27 2010
@@ -748,8 +748,7 @@
 
 static unsigned GetNumNodeResults(Record *Operator, CodeGenDAGPatterns &CDP) {
   if (Operator->getName() == "set" ||
-      Operator->getName() == "implicit" ||
-      Operator->getName() == "parallel")
+      Operator->getName() == "implicit")
     return 0;  // All return nothing.
   
   if (Operator->isSubClassOf("Intrinsic"))
@@ -1184,8 +1183,7 @@
     return MadeChange;
   }
   
-  if (getOperator()->getName() == "implicit" ||
-      getOperator()->getName() == "parallel") {
+  if (getOperator()->getName() == "implicit") {
     assert(getNumTypes() == 0 && "Node doesn't produce a value");
 
     bool MadeChange = false;
@@ -1529,8 +1527,7 @@
       !Operator->isSubClassOf("SDNodeXForm") &&
       !Operator->isSubClassOf("Intrinsic") &&
       Operator->getName() != "set" &&
-      Operator->getName() != "implicit" &&
-      Operator->getName() != "parallel")
+      Operator->getName() != "implicit")
     error("Unrecognized node '" + Operator->getName() + "'!");
   
   //  Check to see if this is something that is illegal in an input pattern.
@@ -2549,37 +2546,7 @@
   for (unsigned i = 0, e = Patterns.size(); i != e; ++i) {
     Record *CurPattern = Patterns[i];
     DagInit *Tree = CurPattern->getValueAsDag("PatternToMatch");
-    DefInit *OpDef = dynamic_cast<DefInit*>(Tree->getOperator());
-    Record *Operator = OpDef->getDef();
-    TreePattern *Pattern;
-    if (Operator->getName() != "parallel")
-      Pattern = new TreePattern(CurPattern, Tree, true, *this);
-    else {
-      std::vector<Init*> Values;
-      RecTy *ListTy = 0;
-      for (unsigned j = 0, ee = Tree->getNumArgs(); j != ee; ++j) {
-        Values.push_back(Tree->getArg(j));
-        TypedInit *TArg = dynamic_cast<TypedInit*>(Tree->getArg(j));
-        if (TArg == 0) {
-          errs() << "In dag: " << Tree->getAsString();
-          errs() << " --  Untyped argument in pattern\n";
-          assert(0 && "Untyped argument in pattern");
-        }
-        if (ListTy != 0) {
-          ListTy = resolveTypes(ListTy, TArg->getType());
-          if (ListTy == 0) {
-            errs() << "In dag: " << Tree->getAsString();
-            errs() << " --  Incompatible types in pattern arguments\n";
-            assert(0 && "Incompatible types in pattern arguments");
-          }
-        }
-        else {
-          ListTy = TArg->getType();
-        }
-      }
-      ListInit *LI = new ListInit(Values, new ListRecTy(ListTy));
-      Pattern = new TreePattern(CurPattern, LI, true, *this);
-    }
+    TreePattern *Pattern = new TreePattern(CurPattern, Tree, true, *this);
 
     // Inline pattern fragments into it.
     Pattern->InlinePatternFragments();




From bob.wilson at apple.com  Fri Mar 26 22:56:59 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Fri, 26 Mar 2010 20:56:59 -0700
Subject: [llvm-commits] [llvm] r99676 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
In-Reply-To: <20100326234907.CD5F82A6C12C@llvm.org>
References: <20100326234907.CD5F82A6C12C@llvm.org>
Message-ID: <56537201-34D7-4B60-8519-1BB1B786E3F3@apple.com>

Thanks!  That looks good.

I'm going to take it one step further and add a format argument to both N3V and N3VX classes, getting rid of N3Vf.

On Mar 26, 2010, at 4:49 PM, Johnny Chen wrote:

> Author: johnny
> Date: Fri Mar 26 18:49:07 2010
> New Revision: 99676
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=99676&view=rev
> Log:
> Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified
> to now take a format argument.  N3VDInt<> and N3VQInt<> are modified to take a
> format argument as well.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=99676&r1=99675&r2=99676&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Mar 26 18:49:07 2010
> @@ -1015,12 +1015,12 @@
> 
> // Basic 3-register intrinsics, both double- and quad-register.
> class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
> -              InstrItinClass itin, string OpcodeStr, string Dt,
> +              Format f, InstrItinClass itin, string OpcodeStr, string Dt,
>               ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
> -  : N3V<op24, op23, op21_20, op11_8, 0, op4,
> -        (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin, 
> -        OpcodeStr, Dt, "$dst, $src1, $src2", "",
> -        [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
> +  : N3Vf<op24, op23, op21_20, op11_8, 0, op4,
> +         (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), f, itin,
> +         OpcodeStr, Dt, "$dst, $src1, $src2", "",
> +         [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
>   let isCommutable = Commutable;
> }
> class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 
> @@ -1047,12 +1047,12 @@
> }
> 
> class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
> -              InstrItinClass itin, string OpcodeStr, string Dt,
> +              Format f, InstrItinClass itin, string OpcodeStr, string Dt,
>               ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
> -  : N3V<op24, op23, op21_20, op11_8, 1, op4,
> -        (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin, 
> -        OpcodeStr, Dt, "$dst, $src1, $src2", "",
> -        [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
> +  : N3Vf<op24, op23, op21_20, op11_8, 1, op4,
> +         (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), f, itin,
> +         OpcodeStr, Dt, "$dst, $src1, $src2", "",
> +         [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
>   let isCommutable = Commutable;
> }
> class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 
> @@ -1526,24 +1526,24 @@
> // Neon 3-register vector intrinsics.
> 
> // First with only element sizes of 16 and 32 bits:
> -multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
> +multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
>                      InstrItinClass itinD16, InstrItinClass itinD32,
>                      InstrItinClass itinQ16, InstrItinClass itinQ32,
>                      string OpcodeStr, string Dt,
>                      Intrinsic IntOp, bit Commutable = 0> {
>   // 64-bit vector types.
> -  def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16,
> +  def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
>                       OpcodeStr, !strconcat(Dt, "16"),
>                       v4i16, v4i16, IntOp, Commutable>;
> -  def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32,
> +  def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
>                       OpcodeStr, !strconcat(Dt, "32"),
>                       v2i32, v2i32, IntOp, Commutable>;
> 
>   // 128-bit vector types.
> -  def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16,
> +  def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
>                       OpcodeStr, !strconcat(Dt, "16"),
>                       v8i16, v8i16, IntOp, Commutable>;
> -  def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32,
> +  def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
>                       OpcodeStr, !strconcat(Dt, "32"),
>                       v4i32, v4i32, IntOp, Commutable>;
> }
> @@ -1563,92 +1563,37 @@
> }
> 
> // ....then also with element size of 8 bits:
> -multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
> +multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
>                       InstrItinClass itinD16, InstrItinClass itinD32,
>                       InstrItinClass itinQ16, InstrItinClass itinQ32,
>                       string OpcodeStr, string Dt,
>                       Intrinsic IntOp, bit Commutable = 0>
> -  : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
> +  : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
>               OpcodeStr, Dt, IntOp, Commutable> {
> -  def v8i8  : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
> +  def v8i8  : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
>                       OpcodeStr, !strconcat(Dt, "8"),
>                       v8i8, v8i8, IntOp, Commutable>;
> -  def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
> +  def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
>                       OpcodeStr, !strconcat(Dt, "8"),
>                       v16i8, v16i8, IntOp, Commutable>;
> }
> 
> // ....then also with element size of 64 bits:
> -multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
> +multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
>                        InstrItinClass itinD16, InstrItinClass itinD32,
>                        InstrItinClass itinQ16, InstrItinClass itinQ32,
>                        string OpcodeStr, string Dt,
>                        Intrinsic IntOp, bit Commutable = 0>
> -  : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
> +  : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
>                OpcodeStr, Dt, IntOp, Commutable> {
> -  def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
> +  def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
>                       OpcodeStr, !strconcat(Dt, "64"),
>                       v1i64, v1i64, IntOp, Commutable>;
> -  def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
> +  def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
>                       OpcodeStr, !strconcat(Dt, "64"),
>                       v2i64, v2i64, IntOp, Commutable>;
> }
> 
> -// N3VSh_QHSD is similar to N3VInt_QHSD, except that it is for 3-Register Vector
> -// Shift Instructions (N3RegVShFrm), which do not follow the N3RegFrm's operand
> -// order of D:Vd N:Vn M:Vm.
> -//
> -// The operand order of N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the
> -// first src operand).
> -class N3VDSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
> -             InstrItinClass itin, string OpcodeStr, string Dt,
> -             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
> -  : N3Vf<op24, op23, op21_20, op11_8, 0, op4,
> -         (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegVShFrm,
> -         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
> -         [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
> -  let isCommutable = Commutable;
> -}
> -class N3VQSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
> -             InstrItinClass itin, string OpcodeStr, string Dt,
> -             ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
> -  : N3Vf<op24, op23, op21_20, op11_8, 1, op4,
> -         (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegVShFrm,
> -         itin, OpcodeStr, Dt, "$dst, $src1, $src2", "",
> -         [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
> -  let isCommutable = Commutable;
> -}
> -multiclass N3VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
> -                      InstrItinClass itinD16, InstrItinClass itinD32,
> -                      InstrItinClass itinQ16, InstrItinClass itinQ32,
> -                      string OpcodeStr, string Dt,
> -                      Intrinsic IntOp, bit Commutable> {
> -  def v4i16 : N3VDSh<op24, op23, 0b01, op11_8, op4, itinD16,
> -                     OpcodeStr, !strconcat(Dt, "16"),
> -                     v4i16, v4i16, IntOp, Commutable>;
> -  def v2i32 : N3VDSh<op24, op23, 0b10, op11_8, op4, itinD32,
> -                     OpcodeStr, !strconcat(Dt, "32"),
> -                     v2i32, v2i32, IntOp, Commutable>;
> -  def v8i16 : N3VQSh<op24, op23, 0b01, op11_8, op4, itinQ16,
> -                     OpcodeStr, !strconcat(Dt, "16"),
> -                     v8i16, v8i16, IntOp, Commutable>;
> -  def v4i32 : N3VQSh<op24, op23, 0b10, op11_8, op4, itinQ32,
> -                     OpcodeStr, !strconcat(Dt, "32"),
> -                     v4i32, v4i32, IntOp, Commutable>;
> -  def v8i8  : N3VDSh<op24, op23, 0b00, op11_8, op4, itinD16,
> -                     OpcodeStr, !strconcat(Dt, "8"),
> -                     v8i8, v8i8, IntOp, Commutable>;
> -  def v16i8 : N3VQSh<op24, op23, 0b00, op11_8, op4, itinQ16,
> -                     OpcodeStr, !strconcat(Dt, "8"),
> -                     v16i8, v16i8, IntOp, Commutable>;
> -  def v1i64 : N3VDSh<op24, op23, 0b11, op11_8, op4,
> -                     itinD32, OpcodeStr, !strconcat(Dt, "64"),
> -                     v1i64, v1i64, IntOp, Commutable>;
> -  def v2i64 : N3VQSh<op24, op23, 0b11, op11_8, op4,
> -                     itinQ32, OpcodeStr, !strconcat(Dt, "64"),
> -                     v2i64, v2i64, IntOp, Commutable>;
> -}
> -
> // Neon Narrowing 3-register vector intrinsics,
> //   source operand element sizes of 16, 32 and 64 bits:
> multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
> @@ -2058,20 +2003,26 @@
> defm VADDWs   : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
> defm VADDWu   : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
> //   VHADD    : Vector Halving Add
> -defm VHADDs   : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
> -                           IIC_VBINi4Q, "vhadd", "s", int_arm_neon_vhadds, 1>;
> -defm VHADDu   : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
> -                           IIC_VBINi4Q, "vhadd", "u", int_arm_neon_vhaddu, 1>;
> +defm VHADDs   : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
> +                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
> +                           "vhadd", "s", int_arm_neon_vhadds, 1>;
> +defm VHADDu   : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
> +                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
> +                           "vhadd", "u", int_arm_neon_vhaddu, 1>;
> //   VRHADD   : Vector Rounding Halving Add
> -defm VRHADDs  : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
> -                           IIC_VBINi4Q, "vrhadd", "s", int_arm_neon_vrhadds, 1>;
> -defm VRHADDu  : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
> -                           IIC_VBINi4Q, "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
> +defm VRHADDs  : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
> +                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
> +                           "vrhadd", "s", int_arm_neon_vrhadds, 1>;
> +defm VRHADDu  : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
> +                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
> +                           "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
> //   VQADD    : Vector Saturating Add
> -defm VQADDs   : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
> -                            IIC_VBINi4Q, "vqadd", "s", int_arm_neon_vqadds, 1>;
> -defm VQADDu   : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
> -                            IIC_VBINi4Q, "vqadd", "u", int_arm_neon_vqaddu, 1>;
> +defm VQADDs   : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
> +                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
> +                            "vqadd", "s", int_arm_neon_vqadds, 1>;
> +defm VQADDu   : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
> +                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
> +                            "vqadd", "u", int_arm_neon_vqaddu, 1>;
> //   VADDHN   : Vector Add and Narrow Returning High Half (D = Q + Q)
> defm VADDHN   : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
>                             int_arm_neon_vaddhn, 1>;
> @@ -2084,10 +2035,10 @@
> //   VMUL     : Vector Multiply (integer, polynomial and floating-point)
> defm VMUL     : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
>                         IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
> -def  VMULpd   : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul", "p8",
> -                        v8i8, v8i8, int_arm_neon_vmulp, 1>;
> -def  VMULpq   : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul", "p8",
> -                        v16i8, v16i8, int_arm_neon_vmulp, 1>;
> +def  VMULpd   : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
> +                        "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
> +def  VMULpq   : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
> +                        "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
> def  VMULfd   : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
>                      v2f32, v2f32, fmul, 1>;
> def  VMULfq   : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
> @@ -2117,7 +2068,7 @@
>                            (SubReg_i32_lane imm:$lane)))>;
> 
> //   VQDMULH  : Vector Saturating Doubling Multiply Returning High Half
> -defm VQDMULH  : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
> +defm VQDMULH  : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
>                           IIC_VMULi16Q, IIC_VMULi32Q, 
>                           "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
> defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
> @@ -2139,8 +2090,8 @@
>                                  (SubReg_i32_lane imm:$lane)))>;
> 
> //   VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
> -defm VQRDMULH   : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
> -                            IIC_VMULi16Q, IIC_VMULi32Q,
> +defm VQRDMULH   : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
> +                            IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
>                             "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
> defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
>                               IIC_VMULi16Q, IIC_VMULi32Q,
> @@ -2299,18 +2250,18 @@
> defm VSUBWs   : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
> defm VSUBWu   : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
> //   VHSUB    : Vector Halving Subtract
> -defm VHSUBs   : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
> -                           IIC_VBINi4Q, IIC_VBINi4Q,
> +defm VHSUBs   : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
> +                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
>                            "vhsub", "s", int_arm_neon_vhsubs, 0>;
> -defm VHSUBu   : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
> -                           IIC_VBINi4Q, IIC_VBINi4Q,
> +defm VHSUBu   : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
> +                           IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
>                            "vhsub", "u", int_arm_neon_vhsubu, 0>;
> //   VQSUB    : Vector Saturing Subtract
> -defm VQSUBs   : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
> -                            IIC_VBINi4Q, IIC_VBINi4Q,
> +defm VQSUBs   : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
> +                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
>                             "vqsub", "s", int_arm_neon_vqsubs, 0>;
> -defm VQSUBu   : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
> -                            IIC_VBINi4Q, IIC_VBINi4Q,
> +defm VQSUBu   : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
> +                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
>                             "vqsub", "u", int_arm_neon_vqsubu, 0>;
> //   VSUBHN   : Vector Subtract and Narrow Returning High Half (D = Q - Q)
> defm VSUBHN   : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
> @@ -2365,15 +2316,15 @@
>                             "$dst, $src, #0">;
> 
> //   VACGE    : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
> -def  VACGEd   : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge", "f32",
> -                        v2i32, v2f32, int_arm_neon_vacged, 0>;
> -def  VACGEq   : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge", "f32",
> -                        v4i32, v4f32, int_arm_neon_vacgeq, 0>;
> +def  VACGEd   : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
> +                        "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
> +def  VACGEq   : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
> +                        "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
> //   VACGT    : Vector Absolute Compare Greater Than (aka VCAGT)
> -def  VACGTd   : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt", "f32",
> -                        v2i32, v2f32, int_arm_neon_vacgtd, 0>;
> -def  VACGTq   : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt", "f32",
> -                        v4i32, v4f32, int_arm_neon_vacgtq, 0>;
> +def  VACGTd   : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
> +                        "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
> +def  VACGTq   : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
> +                        "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
> //   VTST     : Vector Test Bits
> defm VTST     : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 
>                         IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
> @@ -2477,15 +2428,15 @@
> // Vector Absolute Differences.
> 
> //   VABD     : Vector Absolute Difference
> -defm VABDs    : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
> -                           IIC_VBINi4Q, IIC_VBINi4Q,
> +defm VABDs    : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
> +                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
>                            "vabd", "s", int_arm_neon_vabds, 0>;
> -defm VABDu    : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
> -                           IIC_VBINi4Q, IIC_VBINi4Q,
> +defm VABDu    : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
> +                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
>                            "vabd", "u", int_arm_neon_vabdu, 0>;
> -def  VABDfd   : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND,
> +def  VABDfd   : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
>                         "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
> -def  VABDfq   : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ,
> +def  VABDfq   : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
>                         "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
> 
> //   VABDL    : Vecto