From daniel at zuster.org Mon Mar 29 03:25:08 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 29 Mar 2010 08:25:08 -0000
Subject: [llvm-commits] [zorg] r99808 -
/zorg/trunk/lnt/lnt/viewer/js/View2D.js
Message-ID: <20100329082508.79F712A6C12C@llvm.org>
Author: ddunbar
Date: Mon Mar 29 03:25:08 2010
New Revision: 99808
URL: http://llvm.org/viewvc/llvm-project?rev=99808&view=rev
Log:
Graph2D: Add two new graph styles, points and simple error bars (lines).
Modified:
zorg/trunk/lnt/lnt/viewer/js/View2D.js
Modified: zorg/trunk/lnt/lnt/viewer/js/View2D.js
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/js/View2D.js?rev=99808&r1=99807&r2=99808&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/js/View2D.js (original)
+++ zorg/trunk/lnt/lnt/viewer/js/View2D.js Mon Mar 29 03:25:08 2010
@@ -532,6 +532,67 @@
},
});
+var Graph2D_PointPlotStyle = new Class ({
+ Extends: Graph2D_PlotStyle,
+
+ initialize: function(width, color) {
+ if (!width)
+ width = 1;
+ if (!color)
+ color = [0,0,0];
+
+ this.parent();
+ this.width = width;
+ this.color = color;
+ },
+
+ plot: function(graph, ctx, data) {
+ if (data.length === 0)
+ return;
+
+ ctx.beginPath();
+ var radius = this.width * (graph.getPixelSize()[0] + graph.getPixelSize()[1]) * .5;
+ for (var i = 0, e = data.length; i != e; ++i) {
+ var co = graph.graphInfo.toNDC(data[i]);
+ ctx.moveTo(co[0], co[1]);
+ ctx.arc(co[0], co[1], radius, 0, Math.PI * 2, /*anticlockwise=*/false);
+ }
+ ctx.fillStyle = col3_to_rgb(this.color);
+ ctx.fill();
+ },
+});
+
+var Graph2D_ErrorBarPlotStyle = new Class ({
+ Extends: Graph2D_PlotStyle,
+
+ initialize: function(width, color) {
+ if (!width)
+ width = 1;
+ if (!color)
+ color = [0,0,0];
+
+ this.parent();
+ this.width = width;
+ this.color = color;
+ },
+
+ plot: function(graph, ctx, data) {
+ if (data.length === 0)
+ return;
+
+ ctx.beginPath();
+ for (var i = 0, e = data.length; i != e; ++i) {
+ var co_min = graph.graphInfo.toNDC([data[i][0], data[i][1]]);
+ var co_max = graph.graphInfo.toNDC([data[i][0], data[i][2]]);
+ ctx.moveTo(co_min[0], co_min[1]);
+ ctx.lineTo(co_max[0], co_max[1]);
+ }
+ ctx.lineWidth = this.width * (graph.getPixelSize()[0] + graph.getPixelSize()[1]) * .5;
+ ctx.strokeStyle = col3_to_rgb(this.color);
+ ctx.stroke();
+ },
+});
+
var Graph2D_Axis = new Class ({
// Static Methods
formats: {
From daniel at zuster.org Mon Mar 29 03:25:11 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 29 Mar 2010 08:25:11 -0000
Subject: [llvm-commits] [zorg] r99809 - in /zorg/trunk/lnt/lnt/viewer:
NTStyleBrowser.ptl simple.ptl
Message-ID: <20100329082511.2E0472A6C12D@llvm.org>
Author: ddunbar
Date: Mon Mar 29 03:25:11 2010
New Revision: 99809
URL: http://llvm.org/viewvc/llvm-project?rev=99809&view=rev
Log:
LNT: Add very basic 'simple' viewer support for the 'run_order' key.
Modified:
zorg/trunk/lnt/lnt/viewer/NTStyleBrowser.ptl
zorg/trunk/lnt/lnt/viewer/simple.ptl
Modified: zorg/trunk/lnt/lnt/viewer/NTStyleBrowser.ptl
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/NTStyleBrowser.ptl?rev=99809&r1=99808&r2=99809&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/NTStyleBrowser.ptl (original)
+++ zorg/trunk/lnt/lnt/viewer/NTStyleBrowser.ptl Mon Mar 29 03:25:11 2010
@@ -55,6 +55,18 @@
# Find previous runs, ordered by time.
runs = db.runs(run.machine).order_by(Run.start_time.desc()).all()
+ # Order by run_order info key, if given.
+ for r in runs:
+ if 'run_order' in r.info:
+ has_order = True
+ break
+ else:
+ has_order = False
+ if has_order:
+ runs.sort(key = lambda r: ('run_order' in r.info and
+ r.info['run_order'].value))
+ runs.reverse()
+
# Find previous run to compare to.
if compareTo is None:
for r in runs:
@@ -304,6 +316,21 @@
self.id = int(idstr)
except ValueError, exc:
raise TraversalError(str(exc))
+ self.popupDepth = 0
+
+ def renderPopupBegin [html] (self, id, title, hidden):
+ self.popupDepth += 1
+ """\
+
+ (%s) %s
+
+ """ % (id, id, ("+","-")[hidden], title, id, ("","none")[hidden],
+ self.popupDepth)
+
+ def renderPopupEnd [html] (self):
+ """
+
"""
+ self.popupDepth -= 1
def _q_index [html] (self):
# Get a DB connection.
@@ -319,6 +346,18 @@
# Find all runs on this machine.
runs = db.runs(machine).order_by(Run.start_time.desc()).all()
+ # Order by run_order info key, if given.
+ for r in runs:
+ if 'run_order' in r.info:
+ has_order = True
+ break
+ else:
+ has_order = False
+ if has_order:
+ runs.sort(key = lambda r: ('run_order' in r.info and
+ r.info['run_order'].value))
+ runs.reverse()
+
# FIXME: List previous machines with the same nickname?
"""
@@ -372,26 +411,31 @@
| Machine ID |
%d |
-
-
-
-
- """ % (machine.name, machine.id)
+
""" % (machine.name, machine.id)
+ self.renderPopupBegin('machine_info', 'Machine Info', True)
+ """
+ """
for mi in machine.info.values():
"""
| %s |
%s |
-
- """ % (mi.key, mi.value)
+ """ % (mi.key, mi.value)
+ """
+
"""
+ self.renderPopupEnd()
# List associated runs.
+
"""
-
-
+
"""
+ if has_order:
+ """
+ | Run Order | """
+ """
Start Time |
End Time |
|
@@ -399,7 +443,15 @@
"""
for r in runs:
"""
-
+
"""
+ if has_order:
+ if 'run_order' in r.info:
+ order_value = r.info['run_order'].value
+ else:
+ order_value = str(' ')
+ """
+ | %s | """ % order_value
+ """
%s |
%s |
View Results |
Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/simple.ptl?rev=99809&r1=99808&r2=99809&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/simple.ptl (original)
+++ zorg/trunk/lnt/lnt/viewer/simple.ptl Mon Mar 29 03:25:11 2010
@@ -19,6 +19,17 @@
from PerfDB import Machine, Run, Test
+def median(l):
+ l = list(l)
+ l.sort()
+ N = len(l)
+ return (l[(N-1)//2] + l[N//2])*.5
+
+def median_absolute_deviation(l, med = None):
+ if med is None:
+ med = median(l)
+ return median([abs(x - med) for x in l])
+
class SimpleRunUI(Directory):
_q_exports = ["", "graph"]
@@ -62,15 +73,25 @@
runs = [r for r in runs
if 'tag' in r.info and r.info['tag'].value == 'simple']
+ # Order by run_order info key, if given.
+ for r in runs:
+ if 'run_order' in r.info:
+ has_order = True
+ break
+ else:
+ has_order = False
+ if has_order:
+ runs.sort(key = lambda r: ('run_order' in r.info and
+ r.info['run_order'].value))
+ runs.reverse()
+
# Find previous run to compare to.
if compareTo is None:
- for r in runs:
- # FIXME: Compare revisions, not times.
- if r != run and r.start_time < run.start_time:
- compareTo = r
- break
+ run_index = runs.index(run)
+ if run_index < len(runs) - 1:
+ compareTo = runs[run_index + 1]
- return run, runs, compareTo
+ return run, runs, has_order, compareTo
def show_run_page [html] (self, db, run, runs, compareTo, contents_fn):
machine = run.machine
@@ -180,7 +201,7 @@
# Get a DB connection.
db = self.root.getDB()
- run,runs,compareTo = self.getInfo(db)
+ run,runs,has_order,compareTo = self.getInfo(db)
machine = run.machine
self.root.getHeader('Run Results', "../..",
@@ -197,7 +218,7 @@
# Get a DB connection.
db = self.root.getDB()
- run,runs,compareTo = self.getInfo(db)
+ run,runs,has_order,compareTo = self.getInfo(db)
machine = run.machine
# Load the metadata.
@@ -226,24 +247,36 @@
q = q.filter(Sample.test_id.in_(test_ids))
samples = list(q)
- # Aggregate by test id and then run id.
+ # Aggregate by test id and then run key.
#
# FIXME: Pretty expensive.
+ run_id_map = dict([(r.id,r) for r in runs])
samples_by_test_id = {}
for run_id,test_id,value in samples:
d = samples_by_test_id.get(test_id)
if d is None:
d = samples_by_test_id[test_id] = Util.multidict()
- d[run_id] = value
+ r = run_id_map.get(run_id)
+ if r is None:
+ continue
+
+ if has_order:
+ # FIXME: What to do on failure?
+ run_key = int(r.info.get('run_order').value)
+ else:
+ run_key = time.mktime(r.start_time.timetuple())
+ d[run_key] = value
# Build the graph data
- run_id_map = dict([(r.id,r) for r in runs])
pset_id_map = dict([(pset,i) for i,pset in enumerate(parameter_sets)])
legend = []
plots = ""
num_plots = len(graph_tests) * len(graph_psets)
num_points = 0
index = 0
+ show_mad_error = has_order
+ show_points = has_order
+ show_all_points = False
for name in graph_tests:
for pset in graph_psets:
test_id = test_map[(name,pset)].id
@@ -251,21 +284,45 @@
# Get the plot for this test.
#
# FIXME: Support order by something other than time.
+ errorbar_data = []
+ points_data = []
data = []
- for run_id,values in samples_by_test_id.get(test_id,{}).items():
- r = run_id_map.get(run_id)
- if not r:
- continue
- timeval = time.mktime(r.start_time.timetuple())
- data.append((timeval, min(values)))
+ for x,values in samples_by_test_id.get(test_id,{}).items():
+ min_value = min(values)
+ data.append((x, min_value))
+ if show_points:
+ if show_all_points:
+ for v in values:
+ points_data.append((x, v))
+ else:
+ points_data.append((x, min_value))
+ if show_mad_error:
+ med = median(values)
+ mad = median_absolute_deviation(values, med)
+ errorbar_data.append((x, med - mad, med + mad))
data.sort()
num_points += len(data)
col = list(Util.makeDarkColor(float(index) / num_plots))
- pts = ','.join(['[%f,%f]' % (t,v) for t,v in data])
+ pts = ','.join(['[%.3f,%.3f]' % (t,v)
+ for t,v in data])
style = "new Graph2D_LinePlotStyle(1, %r)" % col
plots += " graph.addPlot([%s], %s);\n" % (pts,style)
+ if points_data:
+ pts_col = (0,0,0)
+ pts = ','.join(['[%.3f,%.3f]' % (t,v)
+ for t,v in points_data])
+ style = "new Graph2D_PointPlotStyle(1, %r)" % (pts_col,)
+ plots += " graph.addPlot([%s], %s);\n" % (pts,style)
+
+ if errorbar_data:
+ bar_col = [c*.7 for c in col]
+ pts = ','.join(['[%.3f,%.3f,%.3f]' % (x,y_min,y_max)
+ for x,y_min,y_max in errorbar_data])
+ style = "new Graph2D_ErrorBarPlotStyle(1, %r)" % (bar_col,)
+ plots += " graph.addPlot([%s], %s);\n" % (pts,style)
+
legend.append(("%s : P%d" % (name, pset_id_map[pset]), col))
index += 1
@@ -301,15 +358,19 @@
Num Points: %d
""" % (num_plots, num_points)
+ if has_order:
+ xAxis_format = 'graph.xAxis.formats.normal'
+ else:
+ xAxis_format = 'graph.xAxis.formats.day'
graph_init = """\
function init() {
graph = new Graph2D("graph");
graph.clearColor = [1, 1, 1];
%s
- graph.xAxis.format = graph.xAxis.formats.day;
+ graph.xAxis.format = %s;
graph.draw();
}
- """ % (plots,)
+ """ % (plots,xAxis_format)
self.root.getHeader('Run Results', "..",
components=(('simple','simple'),
('machine',
From criswell at uiuc.edu Mon Mar 29 10:47:51 2010
From: criswell at uiuc.edu (John Criswell)
Date: Mon, 29 Mar 2010 15:47:51 -0000
Subject: [llvm-commits] [poolalloc] r99813 -
/poolalloc/trunk/lib/DSA/Local.cpp
Message-ID: <20100329154752.056CA2A6C12C@llvm.org>
Author: criswell
Date: Mon Mar 29 10:47:51 2010
New Revision: 99813
URL: http://llvm.org/viewvc/llvm-project?rev=99813&view=rev
Log:
Taught DSA about the llvm.objectsize() intrinsic.
Modified:
poolalloc/trunk/lib/DSA/Local.cpp
Modified: poolalloc/trunk/lib/DSA/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=99813&r1=99812&r2=99813&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/Local.cpp (original)
+++ poolalloc/trunk/lib/DSA/Local.cpp Mon Mar 29 10:47:51 2010
@@ -717,6 +717,9 @@
case Intrinsic::prefetch:
return true;
+ case Intrinsic::objectsize:
+ return true;
+
//
// The return address aliases with the stack, is type-unknown, and should
// have the unknown flag set since we don't know where it goes.
From sabre at nondot.org Mon Mar 29 12:02:02 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 29 Mar 2010 17:02:02 -0000
Subject: [llvm-commits] [llvm] r99815 - /llvm/trunk/lib/Target/ARM/README.txt
Message-ID: <20100329170202.49D952A6C12C@llvm.org>
Author: lattner
Date: Mon Mar 29 12:02:02 2010
New Revision: 99815
URL: http://llvm.org/viewvc/llvm-project?rev=99815&view=rev
Log:
add a note.
Modified:
llvm/trunk/lib/Target/ARM/README.txt
Modified: llvm/trunk/lib/Target/ARM/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README.txt?rev=99815&r1=99814&r2=99815&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/README.txt (original)
+++ llvm/trunk/lib/Target/ARM/README.txt Mon Mar 29 12:02:02 2010
@@ -12,6 +12,9 @@
A few ARMv6T2 ops should be pattern matched: BFI, SBFX, and UBFX
+Interesting optimization for PIC codegen on arm-linux:
+http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43129
+
//===---------------------------------------------------------------------===//
Crazy idea: Consider code that uses lots of 8-bit or 16-bit values. By the
From dpatel at apple.com Mon Mar 29 12:20:31 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 29 Mar 2010 17:20:31 -0000
Subject: [llvm-commits] [llvm] r99816 - in /llvm/trunk:
include/llvm/CodeGen/AsmPrinter.h include/llvm/CodeGen/DwarfWriter.h
lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/CodeGen/AsmPrinter/DwarfDebug.cpp
lib/CodeGen/AsmPrinter/DwarfDebug.h lib/CodeGen/AsmPrinter/DwarfWriter.cpp
Message-ID: <20100329172031.493E82A6C131@llvm.org>
Author: dpatel
Date: Mon Mar 29 12:20:31 2010
New Revision: 99816
URL: http://llvm.org/viewvc/llvm-project?rev=99816&view=rev
Log:
Refactor code to push DILocation prcessing into DwarfDebug.cpp from AsmPrinter.cpp.
This is same as r99772 (which was reverted) with just one meaningful difference where two source lines exchanged their positions.
Modified:
llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=99816&r1=99815&r2=99816&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Mon Mar 29 12:20:31 2010
@@ -47,7 +47,6 @@
class MCSection;
class MCStreamer;
class MCSymbol;
- class MDNode;
class DwarfWriter;
class Mangler;
class MCAsmInfo;
@@ -138,9 +137,6 @@
mutable unsigned Counter;
mutable unsigned SetCounter;
- // Private state for processDebugLoc()
- mutable const MDNode *PrevDLT;
-
protected:
explicit AsmPrinter(formatted_raw_ostream &o, TargetMachine &TM,
MCStreamer &Streamer);
Modified: llvm/trunk/include/llvm/CodeGen/DwarfWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DwarfWriter.h?rev=99816&r1=99815&r2=99816&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DwarfWriter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DwarfWriter.h Mon Mar 29 12:20:31 2010
@@ -83,19 +83,11 @@
///
void EndFunction(const MachineFunction *MF);
- /// RecordSourceLine - Register a source line with debug info. Returns the
- /// unique label that was emitted and which provides correspondence to
- /// the source line list.
- MCSymbol *RecordSourceLine(unsigned Line, unsigned Col, MDNode *Scope);
-
- /// getRecordSourceLineCount - Count source lines.
- unsigned getRecordSourceLineCount();
-
/// ShouldEmitDwarfDebug - Returns true if Dwarf debugging declarations should
/// be emitted.
bool ShouldEmitDwarfDebug() const;
- void BeginScope(const MachineInstr *MI, MCSymbol *Label);
+ void BeginScope(const MachineInstr *MI);
void EndScope(const MachineInstr *MI);
};
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=99816&r1=99815&r2=99816&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon Mar 29 12:20:31 2010
@@ -62,7 +62,7 @@
TM(tm), MAI(tm.getMCAsmInfo()), TRI(tm.getRegisterInfo()),
OutContext(Streamer.getContext()),
OutStreamer(Streamer),
- LastMI(0), LastFn(0), Counter(~0U), SetCounter(0), PrevDLT(NULL) {
+ LastMI(0), LastFn(0), Counter(~0U), SetCounter(0) {
DW = 0; MMI = 0;
VerboseAsm = Streamer.isVerboseAsm();
}
@@ -1337,25 +1337,12 @@
if (!MAI || !DW || !MAI->doesSupportDebugInformation()
|| !DW->ShouldEmitDwarfDebug())
return;
- if (MI->getOpcode() == TargetOpcode::DBG_VALUE)
- return;
- DebugLoc DL = MI->getDebugLoc();
- if (DL.isUnknown())
- return;
- DILocation CurDLT = MF->getDILocation(DL);
- if (!CurDLT.getScope().Verify())
- return;
- if (!BeforePrintingInsn) {
+ if (!BeforePrintingInsn)
// After printing instruction
DW->EndScope(MI);
- } else if (CurDLT.getNode() != PrevDLT) {
- MCSymbol *L = DW->RecordSourceLine(CurDLT.getLineNumber(),
- CurDLT.getColumnNumber(),
- CurDLT.getScope().getNode());
- DW->BeginScope(MI, L);
- PrevDLT = CurDLT.getNode();
- }
+ else
+ DW->BeginScope(MI);
}
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=99816&r1=99815&r2=99816&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Mar 29 12:20:31 2010
@@ -296,7 +296,7 @@
: DwarfPrinter(OS, A, T), ModuleCU(0),
AbbreviationsSet(InitAbbreviationsSetSize), Abbreviations(),
DIEValues(), SectionSourceLines(), didInitial(false), shouldEmit(false),
- CurrentFnDbgScope(0), DebugTimer(0) {
+ CurrentFnDbgScope(0), PrevDILoc(0), DebugTimer(0) {
NextStringPoolNumber = 0;
if (TimePassesIsEnabled)
DebugTimer = new Timer("Dwarf Debug Writer");
@@ -2036,19 +2036,58 @@
}
}
-/// beginScope - Process beginning of a scope starting at Label.
-void DwarfDebug::beginScope(const MachineInstr *MI, MCSymbol *Label) {
+/// beginScope - Process beginning of a scope.
+void DwarfDebug::beginScope(const MachineInstr *MI) {
+ // Ignore DBG_VALUE instructions.
+ if (MI->getOpcode() == TargetOpcode::DBG_VALUE)
+ return;
+
+ // Check location.
+ DebugLoc DL = MI->getDebugLoc();
+ if (DL.isUnknown())
+ return;
+ DILocation DILoc = MF->getDILocation(DL);
+ if (!DILoc.getScope().Verify())
+ return;
+
+ // Check and update last known location info.
+ if(DILoc.getNode() == PrevDILoc)
+ return;
+ PrevDILoc = DILoc.getNode();
+
+ // Emit a label to indicate location change. This is used for line
+ // table even if this instruction does start a new scope.
+ MCSymbol *Label = recordSourceLine(DILoc.getLineNumber(),
+ DILoc.getColumnNumber(),
+ DILoc.getScope().getNode());
+
+ // update DbgScope if this instruction starts a new scope.
InsnToDbgScopeMapTy::iterator I = DbgScopeBeginMap.find(MI);
if (I == DbgScopeBeginMap.end())
return;
+
ScopeVector &SD = I->second;
for (ScopeVector::iterator SDI = SD.begin(), SDE = SD.end();
SDI != SDE; ++SDI)
(*SDI)->setStartLabel(Label);
+
}
/// endScope - Process end of a scope.
void DwarfDebug::endScope(const MachineInstr *MI) {
+ // Ignore DBG_VALUE instruction.
+ if (MI->getOpcode() == TargetOpcode::DBG_VALUE)
+ return;
+
+ // Check location.
+ DebugLoc DL = MI->getDebugLoc();
+ if (DL.isUnknown())
+ return;
+ DILocation DILoc = MF->getDILocation(DL);
+ if (!DILoc.getScope().Verify())
+ return;
+
+ // Emit a label and update DbgScope if this instruction ends a scope.
InsnToDbgScopeMapTy::iterator I = DbgScopeEndMap.find(MI);
if (I == DbgScopeEndMap.end())
return;
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=99816&r1=99815&r2=99816&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Mar 29 12:20:31 2010
@@ -184,6 +184,10 @@
/// function.
DenseMap CompileUnitOffsets;
+ /// Previous instruction's location information. This is used to determine
+ /// label location to indicate scope boundries in dwarf debug info.
+ mutable const MDNode *PrevDILoc;
+
/// DebugTimer - Timer for the Dwarf debug writer.
Timer *DebugTimer;
@@ -542,8 +546,8 @@
/// collectVariableInfo - Populate DbgScope entries with variables' info.
void collectVariableInfo();
- /// beginScope - Process beginning of a scope starting at Label.
- void beginScope(const MachineInstr *MI, MCSymbol *Label);
+ /// beginScope - Process beginning of a scope.
+ void beginScope(const MachineInstr *MI);
/// endScope - Prcess end of a scope.
void endScope(const MachineInstr *MI);
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=99816&r1=99815&r2=99816&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Mon Mar 29 12:20:31 2010
@@ -73,27 +73,14 @@
MMI->EndFunction();
}
-/// RecordSourceLine - Register a source line with debug info. Returns the
-/// unique label that was emitted and which provides correspondence to
-/// the source line list.
-MCSymbol *DwarfWriter::RecordSourceLine(unsigned Line, unsigned Col,
- MDNode *Scope) {
- return DD->recordSourceLine(Line, Col, Scope);
-}
-
-/// getRecordSourceLineCount - Count source lines.
-unsigned DwarfWriter::getRecordSourceLineCount() {
- return DD->getSourceLineCount();
-}
-
/// ShouldEmitDwarfDebug - Returns true if Dwarf debugging declarations should
/// be emitted.
bool DwarfWriter::ShouldEmitDwarfDebug() const {
return DD && DD->ShouldEmitDwarfDebug();
}
-void DwarfWriter::BeginScope(const MachineInstr *MI, MCSymbol *L) {
- DD->beginScope(MI, L);
+void DwarfWriter::BeginScope(const MachineInstr *MI) {
+ DD->beginScope(MI);
}
void DwarfWriter::EndScope(const MachineInstr *MI) {
DD->endScope(MI);
From sabre at nondot.org Mon Mar 29 12:36:02 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 29 Mar 2010 17:36:02 -0000
Subject: [llvm-commits] [llvm] r99818 - in /llvm/trunk:
lib/VMCore/Constants.cpp test/Feature/unions.ll
Message-ID: <20100329173602.5A10C2A6C132@llvm.org>
Author: lattner
Date: Mon Mar 29 12:36:02 2010
New Revision: 99818
URL: http://llvm.org/viewvc/llvm-project?rev=99818&view=rev
Log:
add support for zero initialized unions, patch by Tim Northover!
Modified:
llvm/trunk/lib/VMCore/Constants.cpp
llvm/trunk/test/Feature/unions.ll
Modified: llvm/trunk/lib/VMCore/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=99818&r1=99817&r2=99818&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Constants.cpp (original)
+++ llvm/trunk/lib/VMCore/Constants.cpp Mon Mar 29 12:36:02 2010
@@ -59,6 +59,7 @@
case Type::PointerTyID:
return ConstantPointerNull::get(cast(Ty));
case Type::StructTyID:
+ case Type::UnionTyID:
case Type::ArrayTyID:
case Type::VectorTyID:
return ConstantAggregateZero::get(Ty);
@@ -944,7 +945,8 @@
// Factory Function Implementation
ConstantAggregateZero* ConstantAggregateZero::get(const Type* Ty) {
- assert((Ty->isStructTy() || Ty->isArrayTy() || Ty->isVectorTy()) &&
+ assert((Ty->isStructTy() || Ty->isUnionTy()
+ || Ty->isArrayTy() || Ty->isVectorTy()) &&
"Cannot create an aggregate zero of non-aggregate type!");
LLVMContextImpl *pImpl = Ty->getContext().pImpl;
Modified: llvm/trunk/test/Feature/unions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/unions.ll?rev=99818&r1=99817&r2=99818&view=diff
==============================================================================
--- llvm/trunk/test/Feature/unions.ll (original)
+++ llvm/trunk/test/Feature/unions.ll Mon Mar 29 12:36:02 2010
@@ -6,7 +6,9 @@
@union1 = constant union { i32, i8 } { i32 4 }
@union2 = constant union { i32, i8 } insertvalue(union { i32, i8 } undef, i32 4, 0)
+ at union3 = common global %union.anon zeroinitializer, align 8
define void @"Unions" () {
ret void
}
+
From sabre at nondot.org Mon Mar 29 12:38:47 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 29 Mar 2010 17:38:47 -0000
Subject: [llvm-commits] [llvm] r99819 - in /llvm/trunk:
lib/Target/CellSPU/SPU.h lib/Target/CellSPU/SPUISelLowering.cpp
lib/Target/CellSPU/SPURegisterInfo.cpp lib/Target/CellSPU/SPURegisterInfo.h
test/CodeGen/CellSPU/bigstack.ll
Message-ID: <20100329173847.EDD972A6C132@llvm.org>
Author: lattner
Date: Mon Mar 29 12:38:47 2010
New Revision: 99819
URL: http://llvm.org/viewvc/llvm-project?rev=99819&view=rev
Log:
>From Kalle Raiskila:
"the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions:
-in vararg handling, registers are marked to be live, to not confuse the register scavenger
-function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack."
Added:
llvm/trunk/test/CodeGen/CellSPU/bigstack.ll
Modified:
llvm/trunk/lib/Target/CellSPU/SPU.h
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h
Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=99819&r1=99818&r2=99819&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPU.h Mon Mar 29 12:38:47 2010
@@ -66,9 +66,6 @@
//! Predicate test for an unsigned 10-bit value
/*!
\param Value The input value to be tested
-
- This predicate tests for an unsigned 10-bit value, returning the 10-bit value
- as a short if true.
*/
inline bool isU10Constant(short Value) {
return (Value == (Value & 0x3ff));
@@ -90,6 +87,70 @@
return (Value == (Value & 0x3ff));
}
+ //! Predicate test for a signed 14-bit value
+ /*!
+ \param Value The input value to be tested
+ */
+ template
+ inline bool isS14Constant(T Value);
+
+ template<>
+ inline bool isS14Constant(short Value) {
+ return (Value >= -(1 << 13) && Value <= (1 << 13) - 1);
+ }
+
+ template<>
+ inline bool isS14Constant(int Value) {
+ return (Value >= -(1 << 13) && Value <= (1 << 13) - 1);
+ }
+
+ template<>
+ inline bool isS14Constant(uint32_t Value) {
+ return (Value <= ((1 << 13) - 1));
+ }
+
+ template<>
+ inline bool isS14Constant(int64_t Value) {
+ return (Value >= -(1 << 13) && Value <= (1 << 13) - 1);
+ }
+
+ template<>
+ inline bool isS14Constant(uint64_t Value) {
+ return (Value <= ((1 << 13) - 1));
+ }
+
+ //! Predicate test for a signed 16-bit value
+ /*!
+ \param Value The input value to be tested
+ */
+ template
+ inline bool isS16Constant(T Value);
+
+ template<>
+ inline bool isS16Constant(short Value) {
+ return true;
+ }
+
+ template<>
+ inline bool isS16Constant(int Value) {
+ return (Value >= -(1 << 15) && Value <= (1 << 15) - 1);
+ }
+
+ template<>
+ inline bool isS16Constant(uint32_t Value) {
+ return (Value <= ((1 << 15) - 1));
+ }
+
+ template<>
+ inline bool isS16Constant(int64_t Value) {
+ return (Value >= -(1 << 15) && Value <= (1 << 15) - 1);
+ }
+
+ template<>
+ inline bool isS16Constant(uint64_t Value) {
+ return (Value <= ((1 << 15) - 1));
+ }
+
extern Target TheCellSPUTarget;
}
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=99819&r1=99818&r2=99819&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Mon Mar 29 12:38:47 2010
@@ -1107,7 +1107,8 @@
VarArgsFrameIndex = MFI->CreateFixedObject(StackSlotSize, ArgOffset,
true, false);
SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
- SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], MVT::v16i8);
+ unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass);
+ SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8);
SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, NULL, 0,
false, false, 0);
Chain = Store.getOperand(0);
Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=99819&r1=99818&r2=99819&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Mon Mar 29 12:38:47 2010
@@ -28,6 +28,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
@@ -336,6 +337,7 @@
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo *MFI = MF.getFrameInfo();
+ DebugLoc dl = II->getDebugLoc();
while (!MI.getOperand(i).isFI()) {
++i;
@@ -364,11 +366,22 @@
// Replace the FrameIndex with base register with $sp (aka $r1)
SPOp.ChangeToRegister(SPU::R1, false);
- if (Offset > SPUFrameInfo::maxFrameOffset()
- || Offset < SPUFrameInfo::minFrameOffset()) {
- errs() << "Large stack adjustment ("
- << Offset
- << ") in SPURegisterInfo::eliminateFrameIndex.";
+
+ // if 'Offset' doesn't fit to the D-form instruction's
+ // immediate, convert the instruction to X-form
+ // if the instruction is not an AI (which takes a s10 immediate), assume
+ // it is a load/store that can take a s14 immediate
+ if ( (MI.getOpcode() == SPU::AIr32 && !isS10Constant(Offset))
+ || !isS14Constant(Offset) ) {
+ int newOpcode = convertDFormToXForm(MI.getOpcode());
+ unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj);
+ BuildMI(MBB, II, dl, TII.get(SPU::ILr32), tmpReg )
+ .addImm(Offset);
+ BuildMI(MBB, II, dl, TII.get(newOpcode), MI.getOperand(0).getReg())
+ .addReg(tmpReg, RegState::Kill)
+ .addReg(SPU::R1);
+ // remove the replaced D-form instruction
+ MBB.erase(II);
} else {
MO.ChangeToImmediate(Offset);
}
@@ -423,6 +436,14 @@
MF.getRegInfo().setPhysRegUnused(SPU::R0);
MF.getRegInfo().setPhysRegUnused(SPU::R1);
MF.getRegInfo().setPhysRegUnused(SPU::R2);
+
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ const TargetRegisterClass *RC = &SPU::R32CRegClass;
+ RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
+ RC->getAlignment(),
+ false));
+
+
}
void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
@@ -448,7 +469,8 @@
assert((FrameSize & 0xf) == 0
&& "SPURegisterInfo::emitPrologue: FrameSize not aligned");
- if (FrameSize > 0 || MFI->hasCalls()) {
+ // the "empty" frame size is 16 - just the register scavenger spill slot
+ if (FrameSize > 16 || MFI->hasCalls()) {
FrameSize = -(FrameSize + SPUFrameInfo::minStackSize());
if (hasDebugInfo) {
// Mark effective beginning of when frame pointer becomes valid.
@@ -467,7 +489,7 @@
// Adjust $sp by required amout
BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
.addImm(FrameSize);
- } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
+ } else if (isS16Constant(FrameSize)) {
// Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
// $r2 to adjust $sp:
BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
@@ -475,7 +497,7 @@
.addReg(SPU::R1);
BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
.addImm(FrameSize);
- BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1)
.addReg(SPU::R2)
.addReg(SPU::R1);
BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
@@ -549,7 +571,9 @@
"Can only insert epilog into returning blocks");
assert((FrameSize & 0xf) == 0
&& "SPURegisterInfo::emitEpilogue: FrameSize not aligned");
- if (FrameSize > 0 || MFI->hasCalls()) {
+
+ // the "empty" frame size is 16 - just the register scavenger spill slot
+ if (FrameSize > 16 || MFI->hasCalls()) {
FrameSize = FrameSize + SPUFrameInfo::minStackSize();
if (isS10Constant(FrameSize + LinkSlotOffset)) {
// Reload $lr, adjust $sp by required amount
@@ -574,7 +598,7 @@
.addReg(SPU::R2);
BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
.addImm(16)
- .addReg(SPU::R2);
+ .addReg(SPU::R1);
BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2).
addReg(SPU::R2)
.addImm(16);
@@ -618,4 +642,43 @@
return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
+int
+SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
+{
+ switch(dFormOpcode)
+ {
+ case SPU::AIr32: return SPU::Ar32;
+ case SPU::LQDr32: return SPU::LQXr32;
+ case SPU::LQDr128: return SPU::LQXr128;
+ case SPU::LQDv16i8: return SPU::LQXv16i8;
+ case SPU::LQDv4f32: return SPU::LQXv4f32;
+ case SPU::STQDr32: return SPU::STQXr32;
+ case SPU::STQDr128: return SPU::STQXr128;
+ case SPU::STQDv16i8: return SPU::STQXv16i8;
+ case SPU::STQDv4i32: return SPU::STQXv4i32;
+ case SPU::STQDv4f32: return SPU::STQXv4f32;
+
+ default: assert( false && "Unhandled D to X-form conversion");
+ }
+ // default will assert, but need to return something to keep the
+ // compiler happy.
+ return dFormOpcode;
+}
+
+// TODO this is already copied from PPC. Could this convenience function
+// be moved to the RegScavenger class?
+unsigned
+SPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II,
+ RegScavenger *RS,
+ const TargetRegisterClass *RC,
+ int SPAdj) const
+{
+ assert(RS && "Register scavenging must be on");
+ unsigned Reg = RS->FindUnusedReg(RC);
+ if (Reg == 0)
+ Reg = RS->scavengeRegister(RC, II, SPAdj);
+ assert( Reg && "Register scavenger failed");
+ return Reg;
+}
+
#include "SPUGenRegisterInfo.inc"
Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h?rev=99819&r1=99818&r2=99819&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h Mon Mar 29 12:38:47 2010
@@ -53,6 +53,10 @@
virtual const TargetRegisterClass* const *
getCalleeSavedRegClasses(const MachineFunction *MF) const;
+ //! Allow for scavenging, so we can get scratch registers when needed.
+ virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
+ { return true; }
+
//! Return the reserved registers
BitVector getReservedRegs(const MachineFunction &MF) const;
@@ -97,6 +101,21 @@
//! Get DWARF debugging register number
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
+
+ //! Convert D-form load/store to X-form load/store
+ /*!
+ Converts a regiser displacement load/store into a register-indexed
+ load/store for large stack frames, when the stack frame exceeds the
+ range of a s10 displacement.
+ */
+ int convertDFormToXForm(int dFormOpcode) const;
+
+ //! Acquire an unused register in an emergency.
+ unsigned findScratchRegister(MachineBasicBlock::iterator II,
+ RegScavenger *RS,
+ const TargetRegisterClass *RC,
+ int SPAdj) const;
+
};
} // end namespace llvm
Added: llvm/trunk/test/CodeGen/CellSPU/bigstack.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/bigstack.ll?rev=99819&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/bigstack.ll (added)
+++ llvm/trunk/test/CodeGen/CellSPU/bigstack.ll Mon Mar 29 12:38:47 2010
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=cellspu -o %t1.s
+; RUN: grep lqx %t1.s | count 4
+; RUN: grep il %t1.s | grep -v file | count 7
+; RUN: grep stqx %t1.s | count 2
+
+define i32 @bigstack() nounwind {
+entry:
+ %avar = alloca i32
+ %big_data = alloca [2048 x i32]
+ store i32 3840, i32* %avar, align 4
+ br label %return
+
+return:
+ %retval = load i32* %avar
+ ret i32 %retval
+}
+
From sabre at nondot.org Mon Mar 29 12:50:39 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 29 Mar 2010 17:50:39 -0000
Subject: [llvm-commits] [llvm] r99820 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20100329175039.7F1902A6C132@llvm.org>
Author: lattner
Date: Mon Mar 29 12:50:39 2010
New Revision: 99820
URL: http://llvm.org/viewvc/llvm-project?rev=99820&view=rev
Log:
add tce
Modified:
llvm/trunk/docs/ReleaseNotes.html
Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=99820&r1=99819&r2=99820&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Mon Mar 29 12:50:39 2010
@@ -404,6 +404,27 @@
+
+
+
+
+
+TCE is a toolset for designing
+application-specific processors (ASP) based on the Transport triggered
+architecture (TTA). The toolset provides a complete co-design flow from C/C++
+programs down to synthesizable VHDL and parallel program binaries. Processor
+customization points include the register files, function units, supported
+operations, and the interconnection network.
+
+
TCE uses llvm-gcc/Clang and LLVM for C/C++ language support, target
+independent optimizations and also for parts of code generation. It generates
+new LLVM-based code generators "on the fly" for the designed TTA processors and
+loads them in to the compiler backend as runtime libraries to avoid per-target
+recompilation of larger parts of the compiler chain.
+
+
From criswell at uiuc.edu Mon Mar 29 12:59:31 2010
From: criswell at uiuc.edu (John Criswell)
Date: Mon, 29 Mar 2010 17:59:31 -0000
Subject: [llvm-commits] [poolalloc] r99822 -
/poolalloc/trunk/lib/PoolAllocate/PASimple.cpp
Message-ID: <20100329175931.B570C2A6C12C@llvm.org>
Author: criswell
Date: Mon Mar 29 12:59:31 2010
New Revision: 99822
URL: http://llvm.org/viewvc/llvm-project?rev=99822&view=rev
Log:
Reenabled and updated the code for simple pool allocation to handle the fact
that LLVM 2.7 no longer has malloc and free instructions.
Modified:
poolalloc/trunk/lib/PoolAllocate/PASimple.cpp
Modified: poolalloc/trunk/lib/PoolAllocate/PASimple.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PASimple.cpp?rev=99822&r1=99821&r2=99822&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/PASimple.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/PASimple.cpp Mon Mar 29 12:59:31 2010
@@ -156,9 +156,10 @@
void
PoolAllocateSimple::ProcessFunctionBodySimple (Function& F, TargetData & TD) {
+ // Set of instructions to delete because they have been replaced. We record
+ // all instructions to delete first and then delete them later to avoid
+ // invalidating the iterators over the instruction list.
std::vector
toDelete;
- std::vector Returns;
- std::vector ToFree;
//
// Create a silly Function Info structure for this function.
@@ -171,48 +172,67 @@
//
DSGraph* ECG = Graphs->getDSGraph(F);
- for (Function::iterator i = F.begin(), e = F.end(); i != e; ++i)
+ for (Function::iterator i = F.begin(), e = F.end(); i != e; ++i) {
for (BasicBlock::iterator ii = i->begin(), ee = i->end(); ii != ee; ++ii) {
- if (false) {
- //FIXME: malloc
-#if 0
- if (MallocInst * MI = dyn_cast(ii)) {
- // Associate the global pool decriptor with the DSNode
- DSNode * Node = ECG->getNodeForValue(MI).getNode();
- FInfo.PoolDescriptors.insert(std::make_pair(Node,TheGlobalPool));
-
- // Mark the malloc as an instruction to delete
- toDelete.push_back(ii);
-
- // Create instructions to calculate the size of the allocation in
- // bytes
- Value * AllocSize;
- if (MI->isArrayAllocation()) {
- Value * NumElements = MI->getArraySize();
- Value * ElementSize = ConstantInt::get(Int32Type,
- TD.getTypeAllocSize(MI->getAllocatedType()));
- AllocSize = BinaryOperator::Create (Instruction::Mul,
- ElementSize,
- NumElements,
- "sizetmp",
- MI);
- } else {
- AllocSize = ConstantInt::get(Int32Type,
- TD.getTypeAllocSize(MI->getAllocatedType()));
- }
-
- Value* args[] = {TheGlobalPool, AllocSize};
- Instruction* x = CallInst::Create(PoolAlloc, &args[0], &args[2], MI->getName(), ii);
- ii->replaceAllUsesWith(CastInst::CreatePointerCast(x, ii->getType(), "", ii));
- #endif
- } else if (CallInst * CI = dyn_cast(ii)) {
+ if (CallInst * CI = dyn_cast(ii)) {
+ //
+ // Get the name of the called function.
+ //
CallSite CS(CI);
Function *CF = CS.getCalledFunction();
- if (ConstantExpr *CE = dyn_cast(CS.getCalledValue()))
+ if (ConstantExpr *CE = dyn_cast(CS.getCalledValue())) {
if (CE->getOpcode() == Instruction::BitCast &&
- isa(CE->getOperand(0)))
+ isa(CE->getOperand(0))) {
CF = cast(CE->getOperand(0));
- if (CF && (CF->isDeclaration()) && (CF->getName() == "realloc")) {
+ }
+ }
+
+ //
+ // Process functions that we recognize as allocators.
+ //
+ if (CF && (CF->isDeclaration()) && (CF->getName() == "malloc")) {
+ // Associate the global pool decriptor with the DSNode
+ DSNode * Node = ECG->getNodeForValue(CI).getNode();
+ FInfo.PoolDescriptors.insert(std::make_pair(Node,TheGlobalPool));
+
+ // Mark the call to malloc as an instruction to delete
+ toDelete.push_back(CI);
+
+ // Insertion point - Instruction before which all our instructions go
+ Instruction *InsertPt = CI;
+ Value *Size = CS.getArgument(0);
+
+ // Ensure the size and pointer arguments are of the correct type
+ if (Size->getType() != Int32Type)
+ Size = CastInst::CreateIntegerCast (Size,
+ Int32Type,
+ false,
+ Size->getName(),
+ InsertPt);
+
+ //
+ // Remember the name of the old instruction and then clear it. This
+ // allows us to give the name to the new call to poolalloc().
+ //
+ std::string Name = CI->getName(); CI->setName("");
+
+ //
+ // Insert the call to poolalloc()
+ //
+ Value* Opts[3] = {TheGlobalPool, Size};
+ Instruction *V = CallInst::Create (PoolAlloc,
+ Opts,
+ Opts + 2,
+ Name,
+ InsertPt);
+
+ Instruction *Casted = V;
+ if (V->getType() != CI->getType())
+ Casted = CastInst::CreatePointerCast (V, CI->getType(), V->getName(), InsertPt);
+
+ // Update def-use info
+ CI->replaceAllUsesWith(Casted);
+ } else if (CF && (CF->isDeclaration()) && (CF->getName() == "realloc")) {
// Associate the global pool decriptor with the DSNode
DSNode * Node = ECG->getNodeForValue(CI).getNode();
FInfo.PoolDescriptors.insert(std::make_pair(Node,TheGlobalPool));
@@ -328,33 +348,20 @@
// Update def-use info
CI->replaceAllUsesWith(Casted);
+ } else if (CF && (CF->isDeclaration()) && (CF->getName() == "free")) {
+ Type * VoidPtrTy = PointerType::getUnqual(Int8Type);
+ Value * FreedNode = castTo (CI->getOperand(1), VoidPtrTy, "cast", ii);
+ toDelete.push_back(ii);
+ Value* args[] = {TheGlobalPool, FreedNode};
+ CallInst::Create(PoolFree, &args[0], &args[2], "", ii);
}
- //FIXME: free
- #if 0
- } else if (FreeInst * FI = dyn_cast(ii)) {
- Type * VoidPtrTy = PointerType::getUnqual(Int8Type);
- Value * FreedNode = castTo (FI->getPointerOperand(), VoidPtrTy, "cast", ii);
- toDelete.push_back(ii);
- Value* args[] = {TheGlobalPool, FreedNode};
- CallInst::Create(PoolFree, &args[0], &args[2], "", ii);
- #endif
- } else if (isa(ii)) {
- Returns.push_back(cast(ii));
}
}
+ }
- //add frees at each return for the allocas
- for (std::vector::iterator i = Returns.begin(), e = Returns.end();
- i != e; ++i)
- for (std::vector::iterator ii = ToFree.begin(), ee = ToFree.end();
- ii != ee; ++ii) {
- std::vector args;
- args.push_back (TheGlobalPool);
- args.push_back (*ii);
- CallInst::Create(PoolFree, args.begin(), args.end(), "", *i);
- }
-
- //delete malloc and alloca insts
+ //
+ // Delete all instructions that were previously scheduled for deletion.
+ //
for (unsigned x = 0; x < toDelete.size(); ++x)
toDelete[x]->eraseFromParent();
}
From sabre at nondot.org Mon Mar 29 13:34:13 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 29 Mar 2010 18:34:13 -0000
Subject: [llvm-commits] [llvm] r99824 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20100329183413.624F32A6C12C@llvm.org>
Author: lattner
Date: Mon Mar 29 13:34:13 2010
New Revision: 99824
URL: http://llvm.org/viewvc/llvm-project?rev=99824&view=rev
Log:
update the vmkit blurb
Modified:
llvm/trunk/docs/ReleaseNotes.html
Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=99824&r1=99823&r2=99824&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Mon Mar 29 13:34:13 2010
@@ -175,13 +175,23 @@
compilation.
-VMKit version ?? builds with LLVM 2.7 and you can find it on its
-web page. The release includes
-bug fixes, cleanup and new features. The major changes are:
+With the release of LLVM 2.7, VMKit has shifted to a great framework for writing
+virtual machines. VMKit now offers precise and efficient garbage collection with
+multi-threading support, thanks to the MMTk memory management toolkit, as well
+as just in time and ahead of time compilation with LLVM. The major changes in
+VMKit 0.27 are:
-- ...
+- Garbage collection: VMKit now uses the MMTk toolkit for garbage collectors.
+ The first collector to be ported is the MarkSweep collector, which is precise,
+ and drastically improves the performance of VMKit.
+- Line number information in the JVM: by using the debug metadata of LLVM, the
+ JVM now supports precise line number information, useful when printing a stack
+ trace.
+- Interface calls in the JVM: we implemented a variant of the Interface Method
+ Table technique for interface calls in the JVM.
+
From evan.cheng at apple.com Mon Mar 29 13:38:28 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 29 Mar 2010 11:38:28 -0700
Subject: [llvm-commits] [llvm] r99469 - in /llvm/trunk:
include/llvm/CodeGen/MachineOperand.h
include/llvm/CodeGen/SelectionDAG.h
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
lib/CodeGen/SelectionDAG/InstrEmitter.h
lib/CodeGen/SelectionDAG/SDNodeDbgValue.h l
In-Reply-To:
References:
Message-ID: <37F7E1A8-9AB0-4736-9C59-7C304AA2BB3A@apple.com>
Looking.
Evan
On Mar 26, 2010, at 10:16 PM, Jeffrey Yasskin wrote:
> Hey Evan, this change may have introduced the new memory leak in
> DebugInfo/2010-02-01-DbgValueCrash.ll
> (http://google1.osuosl.org:8011/builders/llvm-x86_64-linux-vg_leak/builds/7/steps/test-llvm/logs/stdio).
> The whole valgrind error (run at r99590) is:
>
> ==8278== 56 bytes in 1 blocks are definitely lost in loss record 130 of 135
> ==8278== at 0x4C229C7: operator new(unsigned long) (vg_replace_malloc.c:220)
> ==8278== by 0xD809F6:
> llvm::SelectionDAGBuilder::visitIntrinsicCall(llvm::CallInst&,
> unsigned int) (SelectionDAGBuilder.cpp:3840)
> ==8278== by 0xD87327:
> llvm::SelectionDAGBuilder::visitCall(llvm::CallInst&)
> (SelectionDAGBuilder.cpp:4662)
> ==8278== by 0xD62E31: llvm::SelectionDAGBuilder::visit(unsigned
> int, llvm::User&) (Instruction.def:161)
> ==8278== by 0xD6293D:
> llvm::SelectionDAGBuilder::visit(llvm::Instruction&)
> (SelectionDAGBuilder.cpp:617)
> ==8278== by 0xDA455C:
> llvm::SelectionDAGISel::SelectBasicBlock(llvm::BasicBlock*,
> llvm::ilist_iterator,
> llvm::ilist_iterator, bool&)
> (SelectionDAGISel.cpp:407)
> ==8278== by 0xDA7952:
> llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function&,
> llvm::MachineFunction&, llvm::MachineModuleInfo*, llvm::DwarfWriter*,
> llvm::TargetInstrInfo const&) (SelectionDAGISel.cpp:1030)
> ==8278== by 0xDA41E6:
> llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&)
> (SelectionDAGISel.cpp:344)
> ==8278== by 0xEBE6B6:
> llvm::MachineFunctionPass::runOnFunction(llvm::Function&)
> (MachineFunctionPass.cpp:27)
> ==8278== by 0x11E2A5C:
> llvm::FPPassManager::runOnFunction(llvm::Function&)
> (PassManager.cpp:1350)
> ==8278== by 0x11E2734:
> llvm::FunctionPassManagerImpl::run(llvm::Function&)
> (PassManager.cpp:1301)
> ==8278== by 0x11E23E4:
> llvm::FunctionPassManager::run(llvm::Function&) (PassManager.cpp:1231)
> ==8278==
>
> Could you take a look? Sorry if you've already fixed this.
>
> On Wed, Mar 24, 2010 at 6:38 PM, Evan Cheng wrote:
>> Author: evancheng
>> Date: Wed Mar 24 20:38:16 2010
>> New Revision: 99469
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=99469&view=rev
>> Log:
>> Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers.
>>
>> Here is a theoretical example that illustrates why the placement is important.
>>
>> tmp1 =
>> store tmp1 -> x
>> ...
>> tmp2 = add ...
>> ...
>> call
>> ...
>> store tmp2 -> x
>>
>> Now mem2reg comes along:
>>
>> tmp1 =
>> dbg_value (tmp1 -> x)
>> ...
>> tmp2 = add ...
>> ...
>> call
>> ...
>> dbg_value (tmp2 -> x)
>>
>> When the debugger examine the value of x after the add instruction but before the call, it should have the value of tmp1.
>>
>> Furthermore, for dbg_value's that reference constants, they should not be emitted at the beginning of the block (since they do not have "producers").
>>
>> This patch also cleans up how SDISel manages DbgValue nodes. It allow a SDNode to be referenced by multiple SDDbgValue nodes. When a SDNode is deleted, it uses the information to find the SDDbgValues and invalidate them. They are not deleted until the corresponding SelectionDAG is destroyed.
>>
>> Modified:
>> llvm/trunk/include/llvm/CodeGen/MachineOperand.h
>> llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>> llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
>> llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
>> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=99469&r1=99468&r2=99469&view=diff
>> ==============================================================================
>> --- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Wed Mar 24 20:38:16 2010
>> @@ -285,6 +285,11 @@
>> IsEarlyClobber = Val;
>> }
>>
>> + void setIsDebug(bool Val = true) {
>> + assert(isReg() && IsDef && "Wrong MachineOperand accessor");
>> + IsDebug = Val;
>> + }
>> +
>> //===--------------------------------------------------------------------===//
>> // Accessors for various operand types.
>> //===--------------------------------------------------------------------===//
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=99469&r1=99468&r2=99469&view=diff
>> ==============================================================================
>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Mar 24 20:38:16 2010
>> @@ -60,42 +60,40 @@
>>
>> /// SDDbgInfo - Keeps track of dbg_value information through SDISel. We do
>> /// not build SDNodes for these so as not to perturb the generated code;
>> -/// instead the info is kept off to the side in this structure. SDNodes may
>> -/// have an associated dbg_value entry in DbgValMap. Debug info that is not
>> -/// associated with any SDNode is held in DbgConstMap. It is possible for
>> -/// optimizations to change a variable to a constant, in which case the
>> -/// corresponding debug info is moved from the variable to the constant table
>> -/// (NYI).
>> +/// instead the info is kept off to the side in this structure. Each SDNode may
>> +/// have one or more associated dbg_value entries. This information is kept in
>> +/// DbgValMap.
>> class SDDbgInfo {
>> - DenseMap DbgVblMap;
>> - SmallVector DbgConstMap;
>> + SmallVector DbgValues;
>> + DenseMap > DbgVblMap;
>>
>> void operator=(const SDDbgInfo&); // Do not implement.
>> SDDbgInfo(const SDDbgInfo&); // Do not implement.
>> public:
>> SDDbgInfo() {}
>>
>> - void add(const SDNode *Node, SDDbgValue *V) {
>> - DbgVblMap[Node] = V;
>> + void add(SDDbgValue *V, const SDNode *Node = 0) {
>> + if (Node)
>> + DbgVblMap[Node].push_back(V);
>> + DbgValues.push_back(V);
>> }
>> - void add(SDDbgValue *V) { DbgConstMap.push_back(V); }
>> - void remove(const SDNode *Node) {
>> - DenseMap::iterator Itr =
>> - DbgVblMap.find(Node);
>> - if (Itr != DbgVblMap.end())
>> - DbgVblMap.erase(Itr);
>> - }
>> - // No need to remove a constant.
>> +
>> void clear() {
>> DbgVblMap.clear();
>> - DbgConstMap.clear();
>> + DbgValues.clear();
>> + }
>> +
>> + bool empty() const {
>> + return DbgValues.empty();
>> }
>> - SDDbgValue *getSDDbgValue(const SDNode *Node) {
>> +
>> + SmallVector &getSDDbgValues(const SDNode *Node) {
>> return DbgVblMap[Node];
>> }
>> - typedef SmallVector::iterator ConstDbgIterator;
>> - ConstDbgIterator DbgConstBegin() { return DbgConstMap.begin(); }
>> - ConstDbgIterator DbgConstEnd() { return DbgConstMap.end(); }
>> +
>> + typedef SmallVector::iterator DbgIterator;
>> + DbgIterator DbgBegin() { return DbgValues.begin(); }
>> + DbgIterator DbgEnd() { return DbgValues.end(); }
>> };
>>
>> enum CombineLevel {
>> @@ -871,19 +869,21 @@
>> /// GetOrdering - Get the order for the SDNode.
>> unsigned GetOrdering(const SDNode *SD) const;
>>
>> - /// AssignDbgInfo - Assign debug info to the SDNode.
>> - void AssignDbgInfo(SDNode *SD, SDDbgValue *db);
>> + /// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means the
>> + /// value is produced by SD.
>> + void AddDbgValue(SDDbgValue *DB, SDNode *SD = 0);
>>
>> - /// RememberDbgInfo - Remember debug info with no associated SDNode.
>> - void RememberDbgInfo(SDDbgValue *db);
>> + /// GetDbgValues - Get the debug values which reference the given SDNode.
>> + SmallVector &GetDbgValues(const SDNode* SD) {
>> + return DbgInfo->getSDDbgValues(SD);
>> + }
>>
>> - /// GetDbgInfo - Get the debug info for the SDNode.
>> - SDDbgValue *GetDbgInfo(const SDNode* SD);
>> + /// hasDebugValues - Return true if there are any SDDbgValue nodes associated
>> + /// with this SelectionDAG.
>> + bool hasDebugValues() const { return !DbgInfo->empty(); }
>>
>> - SDDbgInfo::ConstDbgIterator DbgConstBegin() {
>> - return DbgInfo->DbgConstBegin();
>> - }
>> - SDDbgInfo::ConstDbgIterator DbgConstEnd() { return DbgInfo->DbgConstEnd(); }
>> + SDDbgInfo::DbgIterator DbgBegin() { return DbgInfo->DbgBegin(); }
>> + SDDbgInfo::DbgIterator DbgEnd() { return DbgInfo->DbgEnd(); }
>>
>> void dump() const;
>>
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=99469&r1=99468&r2=99469&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Wed Mar 24 20:38:16 2010
>> @@ -264,7 +264,8 @@
>> InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
>> unsigned IIOpNum,
>> const TargetInstrDesc *II,
>> - DenseMap &VRBaseMap) {
>> + DenseMap &VRBaseMap,
>> + bool IsDebug) {
>> assert(Op.getValueType() != MVT::Other &&
>> Op.getValueType() != MVT::Flag &&
>> "Chain and flag operands should occur at end of operand list!");
>> @@ -295,7 +296,11 @@
>> }
>> }
>>
>> - MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
>> + MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
>> + false/*isImp*/, false/*isKill*/,
>> + false/*isDead*/, false/*isUndef*/,
>> + false/*isEarlyClobber*/,
>> + 0/*SubReg*/, IsDebug));
>> }
>>
>> /// AddOperand - Add the specified operand to the specified machine instr. II
>> @@ -305,9 +310,10 @@
>> void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
>> unsigned IIOpNum,
>> const TargetInstrDesc *II,
>> - DenseMap &VRBaseMap) {
>> + DenseMap &VRBaseMap,
>> + bool IsDebug) {
>> if (Op.isMachineOpcode()) {
>> - AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
>> + AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug);
>> } else if (ConstantSDNode *C = dyn_cast(Op)) {
>> MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
>> } else if (ConstantFPSDNode *F = dyn_cast(Op)) {
>> @@ -356,7 +362,7 @@
>> assert(Op.getValueType() != MVT::Other &&
>> Op.getValueType() != MVT::Flag &&
>> "Chain and flag operands should occur at end of operand list!");
>> - AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
>> + AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug);
>> }
>> }
>>
>> @@ -498,75 +504,48 @@
>> assert(isNew && "Node emitted out of order - early");
>> }
>>
>> -/// EmitDbgValue - Generate any debug info that refers to this Node. Constant
>> -/// dbg_value is not handled here.
>> -void
>> -InstrEmitter::EmitDbgValue(SDNode *Node,
>> - DenseMap &VRBaseMap,
>> - SDDbgValue *sd) {
>> - if (!Node->getHasDebugValue())
>> - return;
>> - if (!sd)
>> - return;
>> - assert(sd->getKind() == SDDbgValue::SDNODE);
>> - unsigned VReg = getVR(SDValue(sd->getSDNode(), sd->getResNo()), VRBaseMap);
>> - const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
>> - DebugLoc DL = sd->getDebugLoc();
>> - MachineInstr *MI;
>> - if (VReg) {
>> - MI = BuildMI(*MF, DL, II).addReg(VReg, RegState::Debug).
>> - addImm(sd->getOffset()).
>> - addMetadata(sd->getMDPtr());
>> - } else {
>> - // Insert an Undef so we can see what we dropped.
>> - MI = BuildMI(*MF, DL, II).addReg(0U).addImm(sd->getOffset()).
>> - addMetadata(sd->getMDPtr());
>> - }
>> - MBB->insert(InsertPos, MI);
>> -}
>> -
>> -/// EmitDbgValue - Generate debug info that does not refer to a SDNode.
>> -void
>> -InstrEmitter::EmitDbgValue(SDDbgValue *sd,
>> +/// EmitDbgValue - Generate machine instruction for a dbg_value node.
>> +///
>> +MachineInstr *InstrEmitter::EmitDbgValue(SDDbgValue *SD,
>> + MachineBasicBlock *InsertBB,
>> + DenseMap &VRBaseMap,
>> DenseMap *EM) {
>> - if (!sd)
>> - return;
>> + uint64_t Offset = SD->getOffset();
>> + MDNode* MDPtr = SD->getMDPtr();
>> + DebugLoc DL = SD->getDebugLoc();
>> +
>> const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
>> - uint64_t Offset = sd->getOffset();
>> - MDNode* mdPtr = sd->getMDPtr();
>> - SDDbgValue::DbgValueKind kind = sd->getKind();
>> - DebugLoc DL = sd->getDebugLoc();
>> - MachineInstr* MI;
>> - if (kind == SDDbgValue::CONST) {
>> - Value *V = sd->getConst();
>> + MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
>> + if (SD->getKind() == SDDbgValue::SDNODE) {
>> + AddOperand(&*MIB, SDValue(SD->getSDNode(), SD->getResNo()),
>> + (*MIB).getNumOperands(), &II, VRBaseMap, true /*IsDebug*/);
>> + } else if (SD->getKind() == SDDbgValue::CONST) {
>> + Value *V = SD->getConst();
>> if (ConstantInt *CI = dyn_cast(V)) {
>> - MI = BuildMI(*MF, DL, II).addImm(CI->getZExtValue()).
>> - addImm(Offset).addMetadata(mdPtr);
>> + MIB.addImm(CI->getSExtValue());
>> } else if (ConstantFP *CF = dyn_cast(V)) {
>> - MI = BuildMI(*MF, DL, II).addFPImm(CF).
>> - addImm(Offset).addMetadata(mdPtr);
>> + MIB.addFPImm(CF);
>> } else {
>> // Could be an Undef. In any case insert an Undef so we can see what we
>> // dropped.
>> - MI = BuildMI(*MF, DL, II).addReg(0U).
>> - addImm(Offset).addMetadata(mdPtr);
>> + MIB.addReg(0U);
>> }
>> - } else if (kind == SDDbgValue::FRAMEIX) {
>> - unsigned FrameIx = sd->getFrameIx();
>> + } else if (SD->getKind() == SDDbgValue::FRAMEIX) {
>> + unsigned FrameIx = SD->getFrameIx();
>> // Stack address; this needs to be lowered in target-dependent fashion.
>> // FIXME test that the target supports this somehow; if not emit Undef.
>> // Create a pseudo for EmitInstrWithCustomInserter's consumption.
>> - MI = BuildMI(*MF, DL, II).addImm(FrameIx).
>> - addImm(Offset).addMetadata(mdPtr);
>> - MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
>> - InsertPos = MBB->end();
>> - return;
>> + MIB.addImm(FrameIx).addImm(Offset).addMetadata(MDPtr);
>> + abort();
>> + TLI->EmitInstrWithCustomInserter(&*MIB, InsertBB, EM);
>> + return 0;
>> } else {
>> // Insert an Undef so we can see what we dropped.
>> - MI = BuildMI(*MF, DL, II).addReg(0U).
>> - addImm(Offset).addMetadata(mdPtr);
>> + MIB.addReg(0U);
>> }
>> - MBB->insert(InsertPos, MI);
>> +
>> + MIB.addImm(Offset).addMetadata(MDPtr);
>> + return &*MIB;
>> }
>>
>> /// EmitNode - Generate machine code for a node and needed dependencies.
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h?rev=99469&r1=99468&r2=99469&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h Wed Mar 24 20:38:16 2010
>> @@ -64,7 +64,8 @@
>> void AddRegisterOperand(MachineInstr *MI, SDValue Op,
>> unsigned IIOpNum,
>> const TargetInstrDesc *II,
>> - DenseMap &VRBaseMap);
>> + DenseMap &VRBaseMap,
>> + bool IsDebug = false);
>>
>> /// AddOperand - Add the specified operand to the specified machine instr. II
>> /// specifies the instruction information for the node, and IIOpNum is the
>> @@ -73,7 +74,8 @@
>> void AddOperand(MachineInstr *MI, SDValue Op,
>> unsigned IIOpNum,
>> const TargetInstrDesc *II,
>> - DenseMap &VRBaseMap);
>> + DenseMap &VRBaseMap,
>> + bool IsDebug = false);
>>
>> /// EmitSubregNode - Generate machine code for subreg nodes.
>> ///
>> @@ -98,16 +100,12 @@
>> /// MachineInstr.
>> static unsigned CountOperands(SDNode *Node);
>>
>> - /// EmitDbgValue - Generate any debug info that refers to this Node. Constant
>> - /// dbg_value is not handled here.
>> - void EmitDbgValue(SDNode *Node,
>> - DenseMap &VRBaseMap,
>> - SDDbgValue* sd);
>> -
>> -
>> - /// EmitDbgValue - Generate a constant DBG_VALUE. No node is involved.
>> - void EmitDbgValue(SDDbgValue* sd,
>> - DenseMap *EM);
>> + /// EmitDbgValue - Generate machine instruction for a dbg_value node.
>> + ///
>> + MachineInstr *EmitDbgValue(SDDbgValue *SD,
>> + MachineBasicBlock *InsertBB,
>> + DenseMap &VRBaseMap,
>> + DenseMap *EM);
>>
>> /// EmitNode - Generate machine code for a node and needed dependencies.
>> ///
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h?rev=99469&r1=99468&r2=99469&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h Wed Mar 24 20:38:16 2010
>> @@ -47,10 +47,12 @@
>> uint64_t Offset;
>> DebugLoc DL;
>> unsigned Order;
>> + bool Invalid;
>> public:
>> // Constructor for non-constants.
>> SDDbgValue(MDNode *mdP, SDNode *N, unsigned R, uint64_t off, DebugLoc dl,
>> - unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O) {
>> + unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
>> + Invalid(false) {
>> kind = SDNODE;
>> u.s.Node = N;
>> u.s.ResNo = R;
>> @@ -97,6 +99,12 @@
>> // Returns the SDNodeOrder. This is the order of the preceding node in the
>> // input.
>> unsigned getOrder() { return Order; }
>> +
>> + // setIsInvalidated / isInvalidated - Setter / getter of the "Invalidated"
>> + // property. A SDDbgValue is invalid if the SDNode that produces the value is
>> + // deleted.
>> + void setIsInvalidated() { Invalid = true; }
>> + bool isInvalidated() { return Invalid; }
>> };
>>
>> } // end llvm namespace
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=99469&r1=99468&r2=99469&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Wed Mar 24 20:38:16 2010
>> @@ -23,6 +23,7 @@
>> #include "llvm/Target/TargetSubtarget.h"
>> #include "llvm/ADT/DenseMap.h"
>> #include "llvm/ADT/SmallPtrSet.h"
>> +#include "llvm/ADT/SmallSet.h"
>> #include "llvm/ADT/SmallVector.h"
>> #include "llvm/ADT/Statistic.h"
>> #include "llvm/Support/Debug.h"
>> @@ -407,19 +408,67 @@
>> }
>> }
>>
>> +namespace {
>> + struct OrderSorter {
>> + bool operator()(const std::pair &A,
>> + const std::pair &B) {
>> + return A.first < B.first;
>> + }
>> + };
>> +}
>> +
>> +// ProcessSourceNode - Process nodes with source order numbers. These are added
>> +// to a vector which EmitSchedule use to determine how to insert dbg_value
>> +// instructions in the right order.
>> +static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
>> + InstrEmitter &Emitter,
>> + DenseMap *EM,
>> + DenseMap &VRBaseMap,
>> + SmallVector, 32> &Orders,
>> + SmallSet &Seen) {
>> + unsigned Order = DAG->GetOrdering(N);
>> + if (!Order || !Seen.insert(Order))
>> + return;
>> +
>> + MachineBasicBlock *BB = Emitter.getBlock();
>> + if (BB->empty() || BB->back().isPHI()) {
>> + // Did not insert any instruction.
>> + Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
>> + return;
>> + }
>> +
>> + Orders.push_back(std::make_pair(Order, &BB->back()));
>> + if (!N->getHasDebugValue())
>> + return;
>> + // Opportunistically insert immediate dbg_value uses, i.e. those with source
>> + // order number right after the N.
>> + MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
>> + SmallVector &DVs = DAG->GetDbgValues(N);
>> + for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
>> + if (DVs[i]->isInvalidated())
>> + continue;
>> + unsigned DVOrder = DVs[i]->getOrder();
>> + if (DVOrder == ++Order) {
>> + // FIXME: If the source node with next higher order is scheduled before
>> + // this could end up generating funky debug info.
>> + MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], BB, VRBaseMap, EM);
>> + Orders.push_back(std::make_pair(DVOrder, DbgMI));
>> + BB->insert(InsertPos, DbgMI);
>> + DVs[i]->setIsInvalidated();
>> + }
>> + }
>> +}
>> +
>> +
>> /// EmitSchedule - Emit the machine code in scheduled order.
>> MachineBasicBlock *ScheduleDAGSDNodes::
>> EmitSchedule(DenseMap *EM) {
>> InstrEmitter Emitter(BB, InsertPos);
>> DenseMap VRBaseMap;
>> DenseMap CopyVRBaseMap;
>> -
>> - // For now, any constant debug info nodes go at the beginning.
>> - for (SDDbgInfo::ConstDbgIterator I = DAG->DbgConstBegin(),
>> - E = DAG->DbgConstEnd(); I!=E; I++) {
>> - Emitter.EmitDbgValue(*I, EM);
>> - delete *I;
>> - }
>> + SmallVector, 32> Orders;
>> + SmallSet Seen;
>> + bool HasDbg = DAG->hasDebugValues();
>>
>> for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
>> SUnit *SU = Sequence[i];
>> @@ -442,22 +491,72 @@
>> N = N->getFlaggedNode())
>> FlaggedNodes.push_back(N);
>> while (!FlaggedNodes.empty()) {
>> + SDNode *N = FlaggedNodes.back();
>> Emitter.EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,
>> VRBaseMap, EM);
>> - if (FlaggedNodes.back()->getHasDebugValue())
>> - if (SDDbgValue *sd = DAG->GetDbgInfo(FlaggedNodes.back())) {
>> - Emitter.EmitDbgValue(FlaggedNodes.back(), VRBaseMap, sd);
>> - delete sd;
>> - }
>> + // Remember the the source order of the inserted instruction.
>> + if (HasDbg)
>> + ProcessSourceNode(N, DAG, Emitter, EM, VRBaseMap, Orders, Seen);
>> FlaggedNodes.pop_back();
>> }
>> Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
>> VRBaseMap, EM);
>> - if (SU->getNode()->getHasDebugValue())
>> - if (SDDbgValue *sd = DAG->GetDbgInfo(SU->getNode())) {
>> - Emitter.EmitDbgValue(SU->getNode(), VRBaseMap, sd);
>> - delete sd;
>> + // Remember the the source order of the inserted instruction.
>> + if (HasDbg)
>> + ProcessSourceNode(SU->getNode(), DAG, Emitter, EM, VRBaseMap, Orders,
>> + Seen);
>> + }
>> +
>> + // Insert all the dbg_value which have not already been inserted in source
>> + // order sequence.
>> + if (HasDbg) {
>> + MachineBasicBlock::iterator BBBegin = BB->empty() ? BB->end() : BB->begin();
>> + while (BBBegin != BB->end() && BBBegin->isPHI())
>> + ++BBBegin;
>> +
>> + // Sort the source order instructions and use the order to insert debug
>> + // values.
>> + std::sort(Orders.begin(), Orders.end(), OrderSorter());
>> +
>> + SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
>> + SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
>> + // Now emit the rest according to source order.
>> + unsigned LastOrder = 0;
>> + MachineInstr *LastMI = 0;
>> + for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
>> + unsigned Order = Orders[i].first;
>> + MachineInstr *MI = Orders[i].second;
>> + // Insert all SDDbgValue's whose order(s) are before "Order".
>> + if (!MI)
>> + continue;
>> + MachineBasicBlock *MIBB = MI->getParent();
>> + for (; DI != DE &&
>> + (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
>> + if ((*DI)->isInvalidated())
>> + continue;
>> + MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, MIBB, VRBaseMap, EM);
>> + if (!LastOrder)
>> + // Insert to start of the BB (after PHIs).
>> + BB->insert(BBBegin, DbgMI);
>> + else {
>> + MachineBasicBlock::iterator Pos = MI;
>> + MIBB->insert(llvm::next(Pos), DbgMI);
>> + }
>> }
>> + LastOrder = Order;
>> + LastMI = MI;
>> + }
>> + // Add trailing DbgValue's before the terminator. FIXME: May want to add
>> + // some of them before one or more conditional branches?
>> + while (DI != DE) {
>> + MachineBasicBlock *InsertBB = Emitter.getBlock();
>> + MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator();
>> + if (!(*DI)->isInvalidated()) {
>> + MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, InsertBB, VRBaseMap, EM);
>> + InsertBB->insert(Pos, DbgMI);
>> + }
>> + ++DI;
>> + }
>> }
>>
>> BB = Emitter.getBlock();
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=99469&r1=99468&r2=99469&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Mar 24 20:38:16 2010
>> @@ -598,8 +598,10 @@
>> // Remove the ordering of this node.
>> Ordering->remove(N);
>>
>> - // And its entry in the debug info table, if any.
>> - DbgInfo->remove(N);
>> + // If any of the SDDbgValue nodes refer to this SDNode, invalidate them.
>> + SmallVector &DbgVals = DbgInfo->getSDDbgValues(N);
>> + for (unsigned i = 0, e = DbgVals.size(); i != e; ++i)
>> + DbgVals[i]->setIsInvalidated();
>> }
>>
>> /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
>> @@ -811,6 +813,7 @@
>> SelectionDAG::~SelectionDAG() {
>> allnodes_clear();
>> delete Ordering;
>> + DbgInfo->clear();
>> delete DbgInfo;
>> }
>>
>> @@ -5241,24 +5244,12 @@
>> return Ordering->getOrder(SD);
>> }
>>
>> -/// AssignDbgInfo - Assign debug info to the SDNode.
>> -void SelectionDAG::AssignDbgInfo(SDNode* SD, SDDbgValue* db) {
>> - assert(SD && "Trying to assign dbg info to a null node!");
>> - DbgInfo->add(SD, db);
>> - SD->setHasDebugValue(true);
>> -}
>> -
>> -/// RememberDbgInfo - Remember debug info which is not assigned to an SDNode.
>> -void SelectionDAG::RememberDbgInfo(SDDbgValue* db) {
>> - DbgInfo->add(db);
>> -}
>> -
>> -/// GetDbgInfo - Get the debug info, if any, for the SDNode.
>> -SDDbgValue* SelectionDAG::GetDbgInfo(const SDNode *SD) {
>> - assert(SD && "Trying to get the order of a null node!");
>> - if (SD->getHasDebugValue())
>> - return DbgInfo->getSDDbgValue(SD);
>> - return 0;
>> +/// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means the
>> +/// value is produced by SD.
>> +void SelectionDAG::AddDbgValue(SDDbgValue *DB, SDNode *SD) {
>> + DbgInfo->add(DB, SD);
>> + if (SD)
>> + SD->setHasDebugValue(true);
>> }
>>
>> //===----------------------------------------------------------------------===//
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=99469&r1=99468&r2=99469&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Mar 24 20:38:16 2010
>> @@ -3825,20 +3825,20 @@
>> ++SDNodeOrder;
>> if (isa(V) || isa(V)) {
>> SDDbgValue* dv = new SDDbgValue(Variable, V, Offset, dl, SDNodeOrder);
>> - DAG.RememberDbgInfo(dv);
>> + DAG.AddDbgValue(dv);
>> } else {
>> SDValue &N = NodeMap[V];
>> if (N.getNode()) {
>> SDDbgValue *dv = new SDDbgValue(Variable, N.getNode(),
>> N.getResNo(), Offset, dl, SDNodeOrder);
>> - DAG.AssignDbgInfo(N.getNode(), dv);
>> + DAG.AddDbgValue(dv, N.getNode());
>> } else {
>> // We may expand this to cover more cases. One case where we have no
>> // data available is an unreferenced parameter; we need this fallback.
>> SDDbgValue* dv = new SDDbgValue(Variable,
>> UndefValue::get(V->getType()),
>> Offset, dl, SDNodeOrder);
>> - DAG.RememberDbgInfo(dv);
>> + DAG.AddDbgValue(dv);
>> }
>> }
>>
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
From sabre at nondot.org Mon Mar 29 13:39:28 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 29 Mar 2010 18:39:28 -0000
Subject: [llvm-commits] [llvm] r99825 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20100329183928.BD9B92A6C12C@llvm.org>
Author: lattner
Date: Mon Mar 29 13:39:28 2010
New Revision: 99825
URL: http://llvm.org/viewvc/llvm-project?rev=99825&view=rev
Log:
apparently llvm 2.7 now has great armv4 support, from
John Tytgat
Modified:
llvm/trunk/docs/ReleaseNotes.html
Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=99825&r1=99824&r2=99825&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Mon Mar 29 13:39:28 2010
@@ -500,6 +500,9 @@
New LSR with full strength reduction mode
The most awesome sext / zext optimization pass. ?
+The ARM backend now has good support for ARMv4 backend (tested on StrongARM
+ hardware), previously only supported ARMv4T and newer.
+
CondProp pass removed (functionality merged into jump threading).
From sabre at nondot.org Mon Mar 29 13:42:42 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 29 Mar 2010 18:42:42 -0000
Subject: [llvm-commits] [llvm] r99826 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20100329184242.D13B52A6C12C@llvm.org>
Author: lattner
Date: Mon Mar 29 13:42:42 2010
New Revision: 99826
URL: http://llvm.org/viewvc/llvm-project?rev=99826&view=rev
Log:
some other notes.
Modified:
llvm/trunk/docs/ReleaseNotes.html
Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=99826&r1=99825&r2=99826&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Mon Mar 29 13:42:42 2010
@@ -483,7 +483,7 @@
Many subtle pointer invalidation bugs in Callgraph have been fixed and it now uses asserting value handles.
MC Disassembler (with blog post), MCInstPrinter. Many X86 backend and AsmPrinter simplifications
Various tools like llc and opt now read either .ll or .bc files as input.
-Malloc and free instructions got removed.
+Malloc and free instructions got removed, along with LowerAllocations pass.
compiler-rt support for ARM.
completely llvm-gcc NEON support.
Can transcode from GAS to intel syntax with "llvm-mc foo.s -output-asm-variant=1"
@@ -505,6 +505,7 @@
+Defaults to RTTI off, packagers should build with make REQUIRE_RTTI=1.
CondProp pass removed (functionality merged into jump threading).
AndersAA got removed (from 2.7 or mainline?)
PredSimplify, LoopVR, GVNPRE got removed.
From benny.kra at googlemail.com Mon Mar 29 14:07:58 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Mon, 29 Mar 2010 19:07:58 -0000
Subject: [llvm-commits] [llvm] r99827 - in /llvm/trunk/lib/Target/CellSPU:
SPU.h SPUISelDAGToDAG.cpp SPUISelLowering.cpp SPURegisterInfo.cpp
Message-ID: <20100329190758.3B47B2A6C12C@llvm.org>
Author: d0k
Date: Mon Mar 29 14:07:58 2010
New Revision: 99827
URL: http://llvm.org/viewvc/llvm-project?rev=99827&view=rev
Log:
Remove a bunch of integer width predicate functions in favor of MathExtras.
Most of these were unused, some of them were wrong and unused (isS16Constant,
isS10Constant).
Modified:
llvm/trunk/lib/Target/CellSPU/SPU.h
llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=99827&r1=99826&r2=99827&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPU.h Mon Mar 29 14:07:58 2010
@@ -15,7 +15,6 @@
#ifndef LLVM_TARGET_IBMCELLSPU_H
#define LLVM_TARGET_IBMCELLSPU_H
-#include "llvm/System/DataTypes.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
@@ -25,134 +24,7 @@
FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
- /*--== Utility functions/predicates/etc used all over the place: --==*/
- //! Predicate test for a signed 10-bit value
- /*!
- \param Value The input value to be tested
-
- This predicate tests for a signed 10-bit value, returning the 10-bit value
- as a short if true.
- */
- template
- inline bool isS10Constant(T Value);
-
- template<>
- inline bool isS10Constant(short Value) {
- int SExtValue = ((int) Value << (32 - 10)) >> (32 - 10);
- return ((Value > 0 && Value <= (1 << 9) - 1)
- || (Value < 0 && (short) SExtValue == Value));
- }
-
- template<>
- inline bool isS10Constant(int Value) {
- return (Value >= -(1 << 9) && Value <= (1 << 9) - 1);
- }
-
- template<>
- inline bool isS10Constant(uint32_t Value) {
- return (Value <= ((1 << 9) - 1));
- }
-
- template<>
- inline bool isS10Constant(int64_t Value) {
- return (Value >= -(1 << 9) && Value <= (1 << 9) - 1);
- }
-
- template<>
- inline bool isS10Constant(uint64_t Value) {
- return (Value <= ((1 << 9) - 1));
- }
-
- //! Predicate test for an unsigned 10-bit value
- /*!
- \param Value The input value to be tested
- */
- inline bool isU10Constant(short Value) {
- return (Value == (Value & 0x3ff));
- }
-
- inline bool isU10Constant(int Value) {
- return (Value == (Value & 0x3ff));
- }
-
- inline bool isU10Constant(uint32_t Value) {
- return (Value == (Value & 0x3ff));
- }
-
- inline bool isU10Constant(int64_t Value) {
- return (Value == (Value & 0x3ff));
- }
-
- inline bool isU10Constant(uint64_t Value) {
- return (Value == (Value & 0x3ff));
- }
-
- //! Predicate test for a signed 14-bit value
- /*!
- \param Value The input value to be tested
- */
- template
- inline bool isS14Constant(T Value);
-
- template<>
- inline bool isS14Constant(short Value) {
- return (Value >= -(1 << 13) && Value <= (1 << 13) - 1);
- }
-
- template<>
- inline bool isS14Constant(int Value) {
- return (Value >= -(1 << 13) && Value <= (1 << 13) - 1);
- }
-
- template<>
- inline bool isS14Constant(uint32_t Value) {
- return (Value <= ((1 << 13) - 1));
- }
-
- template<>
- inline bool isS14Constant(int64_t Value) {
- return (Value >= -(1 << 13) && Value <= (1 << 13) - 1);
- }
-
- template<>
- inline bool isS14Constant(uint64_t Value) {
- return (Value <= ((1 << 13) - 1));
- }
-
- //! Predicate test for a signed 16-bit value
- /*!
- \param Value The input value to be tested
- */
- template
- inline bool isS16Constant(T Value);
-
- template<>
- inline bool isS16Constant(short Value) {
- return true;
- }
-
- template<>
- inline bool isS16Constant(int Value) {
- return (Value >= -(1 << 15) && Value <= (1 << 15) - 1);
- }
-
- template<>
- inline bool isS16Constant(uint32_t Value) {
- return (Value <= ((1 << 15) - 1));
- }
-
- template<>
- inline bool isS16Constant(int64_t Value) {
- return (Value >= -(1 << 15) && Value <= (1 << 15) - 1);
- }
-
- template<>
- inline bool isS16Constant(uint64_t Value) {
- return (Value <= ((1 << 15) - 1));
- }
-
extern Target TheCellSPUTarget;
-
}
// Defines symbolic names for the SPU instructions.
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=99827&r1=99826&r2=99827&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Mon Mar 29 14:07:58 2010
@@ -44,28 +44,28 @@
bool
isI64IntS10Immediate(ConstantSDNode *CN)
{
- return isS10Constant(CN->getSExtValue());
+ return isInt<10>(CN->getSExtValue());
}
//! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
bool
isI32IntS10Immediate(ConstantSDNode *CN)
{
- return isS10Constant(CN->getSExtValue());
+ return isInt<10>(CN->getSExtValue());
}
//! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
bool
isI32IntU10Immediate(ConstantSDNode *CN)
{
- return isU10Constant(CN->getSExtValue());
+ return isUint<10>(CN->getSExtValue());
}
//! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
bool
isI16IntS10Immediate(ConstantSDNode *CN)
{
- return isS10Constant(CN->getSExtValue());
+ return isInt<10>(CN->getSExtValue());
}
//! SDNode predicate for i16 sign-extended, 10-bit immediate values
@@ -80,7 +80,7 @@
bool
isI16IntU10Immediate(ConstantSDNode *CN)
{
- return isU10Constant((short) CN->getZExtValue());
+ return isUint<10>((short) CN->getZExtValue());
}
//! SDNode predicate for i16 sign-extended, 10-bit immediate values
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=99827&r1=99826&r2=99827&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Mon Mar 29 14:07:58 2010
@@ -1492,7 +1492,7 @@
return SDValue();
Value = Value >> 32;
}
- if (isS10Constant(Value))
+ if (isInt<10>(Value))
return DAG.getTargetConstant(Value, ValueType);
}
Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=99827&r1=99826&r2=99827&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Mon Mar 29 14:07:58 2010
@@ -371,8 +371,8 @@
// immediate, convert the instruction to X-form
// if the instruction is not an AI (which takes a s10 immediate), assume
// it is a load/store that can take a s14 immediate
- if ( (MI.getOpcode() == SPU::AIr32 && !isS10Constant(Offset))
- || !isS14Constant(Offset) ) {
+ if ((MI.getOpcode() == SPU::AIr32 && !isInt<10>(Offset))
+ || !isInt<14>(Offset)) {
int newOpcode = convertDFormToXForm(MI.getOpcode());
unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj);
BuildMI(MBB, II, dl, TII.get(SPU::ILr32), tmpReg )
@@ -482,14 +482,14 @@
// for the ABI
BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
.addReg(SPU::R1);
- if (isS10Constant(FrameSize)) {
+ if (isInt<10>(FrameSize)) {
// Spill $sp to adjusted $sp
BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
.addReg(SPU::R1);
// Adjust $sp by required amout
BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
.addImm(FrameSize);
- } else if (isS16Constant(FrameSize)) {
+ } else if (isInt<16>(FrameSize)) {
// Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
// $r2 to adjust $sp:
BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
@@ -575,7 +575,7 @@
// the "empty" frame size is 16 - just the register scavenger spill slot
if (FrameSize > 16 || MFI->hasCalls()) {
FrameSize = FrameSize + SPUFrameInfo::minStackSize();
- if (isS10Constant(FrameSize + LinkSlotOffset)) {
+ if (isInt<10>(FrameSize + LinkSlotOffset)) {
// Reload $lr, adjust $sp by required amount
// Note: We do this to slightly improve dual issue -- not by much, but it
// is an opportunity for dual issue.
From sabre at nondot.org Mon Mar 29 15:35:01 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 29 Mar 2010 20:35:01 -0000
Subject: [llvm-commits] [llvm] r99831 - /llvm/trunk/lib/Support/Timer.cpp
Message-ID: <20100329203501.9CC302A6C12C@llvm.org>
Author: lattner
Date: Mon Mar 29 15:35:01 2010
New Revision: 99831
URL: http://llvm.org/viewvc/llvm-project?rev=99831&view=rev
Log:
move code around and improve indentation, no functionality change.
Modified:
llvm/trunk/lib/Support/Timer.cpp
Modified: llvm/trunk/lib/Support/Timer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=99831&r1=99830&r2=99831&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Timer.cpp (original)
+++ llvm/trunk/lib/Support/Timer.cpp Mon Mar 29 15:35:01 2010
@@ -55,22 +55,26 @@
static TimerGroup *DefaultTimerGroup = 0;
static TimerGroup *getDefaultTimerGroup() {
- TimerGroup* tmp = DefaultTimerGroup;
+ TimerGroup *tmp = DefaultTimerGroup;
sys::MemoryFence();
+ if (tmp) return tmp;
+
+ llvm_acquire_global_lock();
+ tmp = DefaultTimerGroup;
if (!tmp) {
- llvm_acquire_global_lock();
- tmp = DefaultTimerGroup;
- if (!tmp) {
- tmp = new TimerGroup("Miscellaneous Ungrouped Timers");
- sys::MemoryFence();
- DefaultTimerGroup = tmp;
- }
- llvm_release_global_lock();
+ tmp = new TimerGroup("Miscellaneous Ungrouped Timers");
+ sys::MemoryFence();
+ DefaultTimerGroup = tmp;
}
+ llvm_release_global_lock();
return tmp;
}
+//===----------------------------------------------------------------------===//
+// Timer Implementation
+//===----------------------------------------------------------------------===//
+
Timer::Timer(const std::string &N)
: Elapsed(0), UserTime(0), SystemTime(0), MemUsed(0), PeakMem(0), Name(N),
Started(false), TG(getDefaultTimerGroup()) {
@@ -89,7 +93,6 @@
operator=(T);
}
-
// Copy ctor, initialize with no TG member.
Timer::Timer(bool, const Timer &T) {
TG = T.TG; // Avoid assertion in operator=
@@ -97,15 +100,14 @@
TG = 0;
}
-
Timer::~Timer() {
- if (TG) {
- if (Started) {
- Started = false;
- TG->addTimerToPrint(*this);
- }
- TG->removeTimer();
+ if (!TG) return;
+
+ if (Started) {
+ Started = false;
+ TG->addTimerToPrint(*this);
}
+ TG->removeTimer();
}
static inline size_t getMemUsage() {
@@ -129,17 +131,16 @@
ssize_t MemUsed = 0;
if (Start) {
MemUsed = getMemUsage();
- sys::Process::GetTimeUsage(now,user,sys);
+ sys::Process::GetTimeUsage(now, user, sys);
} else {
- sys::Process::GetTimeUsage(now,user,sys);
+ sys::Process::GetTimeUsage(now, user, sys);
MemUsed = getMemUsage();
}
- Result.Elapsed = now.seconds() + now.microseconds() / 1000000.0;
- Result.UserTime = user.seconds() + user.microseconds() / 1000000.0;
- Result.SystemTime = sys.seconds() + sys.microseconds() / 1000000.0;
- Result.MemUsed = MemUsed;
-
+ Result.Elapsed = now.seconds() + now.microseconds() / 1000000.0;
+ Result.UserTime = user.seconds() + user.microseconds() / 1000000.0;
+ Result.SystemTime = sys.seconds() + sys.microseconds() / 1000000.0;
+ Result.MemUsed = MemUsed;
return Result;
}
@@ -196,19 +197,51 @@
(*I)->PeakMem = std::max((*I)->PeakMem, MemUsed-(*I)->PeakMemBase);
}
+
+static void printVal(double Val, double Total, raw_ostream &OS) {
+ if (Total < 1e-7) // Avoid dividing by zero...
+ OS << " ----- ";
+ else {
+ OS << " " << format("%7.4f", Val) << " (";
+ OS << format("%5.1f", Val*100/Total) << "%)";
+ }
+}
+
+void Timer::print(const Timer &Total, raw_ostream &OS) {
+ sys::SmartScopedLock L(*TimerLock);
+ if (Total.UserTime)
+ printVal(UserTime, Total.UserTime, OS);
+ if (Total.SystemTime)
+ printVal(SystemTime, Total.SystemTime, OS);
+ if (Total.getProcessTime())
+ printVal(getProcessTime(), Total.getProcessTime(), OS);
+ printVal(Elapsed, Total.Elapsed, OS);
+
+ OS << " ";
+
+ if (Total.MemUsed) {
+ OS << format("%9lld", (long long)MemUsed) << " ";
+ }
+ if (Total.PeakMem) {
+ if (PeakMem) {
+ OS << format("%9lld", (long long)PeakMem) << " ";
+ } else
+ OS << " ";
+ }
+ OS << Name << "\n";
+
+ Started = false; // Once printed, don't print again
+}
+
+
//===----------------------------------------------------------------------===//
// NamedRegionTimer Implementation
//===----------------------------------------------------------------------===//
-namespace {
-
typedef std::map Name2Timer;
typedef std::map > Name2Pair;
-}
-
static ManagedStatic NamedTimers;
-
static ManagedStatic NamedGroupedTimers;
static Timer &getNamedRegionTimer(const std::string &Name) {
@@ -252,42 +285,6 @@
// TimerGroup Implementation
//===----------------------------------------------------------------------===//
-
-static void printVal(double Val, double Total, raw_ostream &OS) {
- if (Total < 1e-7) // Avoid dividing by zero...
- OS << " ----- ";
- else {
- OS << " " << format("%7.4f", Val) << " (";
- OS << format("%5.1f", Val*100/Total) << "%)";
- }
-}
-
-void Timer::print(const Timer &Total, raw_ostream &OS) {
- sys::SmartScopedLock L(*TimerLock);
- if (Total.UserTime)
- printVal(UserTime, Total.UserTime, OS);
- if (Total.SystemTime)
- printVal(SystemTime, Total.SystemTime, OS);
- if (Total.getProcessTime())
- printVal(getProcessTime(), Total.getProcessTime(), OS);
- printVal(Elapsed, Total.Elapsed, OS);
-
- OS << " ";
-
- if (Total.MemUsed) {
- OS << format("%9lld", (long long)MemUsed) << " ";
- }
- if (Total.PeakMem) {
- if (PeakMem) {
- OS << format("%9lld", (long long)PeakMem) << " ";
- } else
- OS << " ";
- }
- OS << Name << "\n";
-
- Started = false; // Once printed, don't print again
-}
-
// GetLibSupportInfoOutputFile - Return a file stream to print our output on...
raw_ostream *
llvm::GetLibSupportInfoOutputFile() {
@@ -313,70 +310,71 @@
void TimerGroup::removeTimer() {
sys::SmartScopedLock L(*TimerLock);
- if (--NumTimers == 0 && !TimersToPrint.empty()) { // Print timing report...
- // Sort the timers in descending order by amount of time taken...
- std::sort(TimersToPrint.begin(), TimersToPrint.end(),
- std::greater());
-
- // Figure out how many spaces to indent TimerGroup name...
- unsigned Padding = (80-Name.length())/2;
- if (Padding > 80) Padding = 0; // Don't allow "negative" numbers
-
- raw_ostream *OutStream = GetLibSupportInfoOutputFile();
-
- ++NumTimers;
- { // Scope to contain Total timer... don't allow total timer to drop us to
- // zero timers...
- Timer Total("TOTAL");
-
- for (unsigned i = 0, e = TimersToPrint.size(); i != e; ++i)
- Total.sum(TimersToPrint[i]);
-
- // Print out timing header...
- *OutStream << "===" << std::string(73, '-') << "===\n"
- << std::string(Padding, ' ') << Name << "\n"
- << "===" << std::string(73, '-')
- << "===\n";
-
- // If this is not an collection of ungrouped times, print the total time.
- // Ungrouped timers don't really make sense to add up. We still print the
- // TOTAL line to make the percentages make sense.
- if (this != DefaultTimerGroup) {
- *OutStream << " Total Execution Time: ";
-
- *OutStream << format("%5.4f", Total.getProcessTime()) << " seconds (";
- *OutStream << format("%5.4f", Total.getWallTime()) << " wall clock)\n";
- }
- *OutStream << "\n";
-
- if (Total.UserTime)
- *OutStream << " ---User Time---";
- if (Total.SystemTime)
- *OutStream << " --System Time--";
- if (Total.getProcessTime())
- *OutStream << " --User+System--";
- *OutStream << " ---Wall Time---";
- if (Total.getMemUsed())
- *OutStream << " ---Mem---";
- if (Total.getPeakMem())
- *OutStream << " -PeakMem-";
- *OutStream << " --- Name ---\n";
-
- // Loop through all of the timing data, printing it out...
- for (unsigned i = 0, e = TimersToPrint.size(); i != e; ++i)
- TimersToPrint[i].print(Total, *OutStream);
-
- Total.print(Total, *OutStream);
- *OutStream << '\n';
- OutStream->flush();
- }
- --NumTimers;
+ if (--NumTimers != 0 || TimersToPrint.empty())
+ return; // Don't print timing report.
+
+ // Sort the timers in descending order by amount of time taken.
+ std::sort(TimersToPrint.begin(), TimersToPrint.end(),
+ std::greater());
+
+ // Figure out how many spaces to indent TimerGroup name.
+ unsigned Padding = (80-Name.length())/2;
+ if (Padding > 80) Padding = 0; // Don't allow "negative" numbers
- TimersToPrint.clear();
+ raw_ostream *OutStream = GetLibSupportInfoOutputFile();
- if (OutStream != &errs() && OutStream != &outs() && OutStream != &dbgs())
- delete OutStream; // Close the file...
+ ++NumTimers;
+ { // Scope to contain Total timer... don't allow total timer to drop us to
+ // zero timers...
+ Timer Total("TOTAL");
+
+ for (unsigned i = 0, e = TimersToPrint.size(); i != e; ++i)
+ Total.sum(TimersToPrint[i]);
+
+ // Print out timing header...
+ *OutStream << "===" << std::string(73, '-') << "===\n"
+ << std::string(Padding, ' ') << Name << "\n"
+ << "===" << std::string(73, '-')
+ << "===\n";
+
+ // If this is not an collection of ungrouped times, print the total time.
+ // Ungrouped timers don't really make sense to add up. We still print the
+ // TOTAL line to make the percentages make sense.
+ if (this != DefaultTimerGroup) {
+ *OutStream << " Total Execution Time: ";
+
+ *OutStream << format("%5.4f", Total.getProcessTime()) << " seconds (";
+ *OutStream << format("%5.4f", Total.getWallTime()) << " wall clock)\n";
+ }
+ *OutStream << "\n";
+
+ if (Total.UserTime)
+ *OutStream << " ---User Time---";
+ if (Total.SystemTime)
+ *OutStream << " --System Time--";
+ if (Total.getProcessTime())
+ *OutStream << " --User+System--";
+ *OutStream << " ---Wall Time---";
+ if (Total.getMemUsed())
+ *OutStream << " ---Mem---";
+ if (Total.getPeakMem())
+ *OutStream << " -PeakMem-";
+ *OutStream << " --- Name ---\n";
+
+ // Loop through all of the timing data, printing it out...
+ for (unsigned i = 0, e = TimersToPrint.size(); i != e; ++i)
+ TimersToPrint[i].print(Total, *OutStream);
+
+ Total.print(Total, *OutStream);
+ *OutStream << '\n';
+ OutStream->flush();
}
+ --NumTimers;
+
+ TimersToPrint.clear();
+
+ if (OutStream != &errs() && OutStream != &outs() && OutStream != &dbgs())
+ delete OutStream; // Close the file...
}
void TimerGroup::addTimer() {
From sabre at nondot.org Mon Mar 29 15:38:20 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 29 Mar 2010 20:38:20 -0000
Subject: [llvm-commits] [llvm] r99832 -
/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Message-ID: <20100329203820.8F90D2A6C12C@llvm.org>
Author: lattner
Date: Mon Mar 29 15:38:20 2010
New Revision: 99832
URL: http://llvm.org/viewvc/llvm-project?rev=99832&view=rev
Log:
fix a variety of issues were we'd start DebugTimer but
not stop it by using RAII.
Modified:
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=99832&r1=99831&r2=99832&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Mar 29 15:38:20 2010
@@ -1777,12 +1777,11 @@
void DwarfDebug::beginModule(Module *M, MachineModuleInfo *mmi) {
this->M = M;
- if (TimePassesIsEnabled)
- DebugTimer->startTimer();
-
if (!MAI->doesSupportDebugInformation())
return;
+ TimeRegion Timer(DebugTimer);
+
DebugInfoFinder DbgFinder;
DbgFinder.processModule(*M);
@@ -1830,9 +1829,6 @@
// Emit initial sections
emitInitial();
-
- if (TimePassesIsEnabled)
- DebugTimer->stopTimer();
}
/// endModule - Emit all Dwarf sections that should come after the content.
@@ -1841,8 +1837,7 @@
if (!ModuleCU)
return;
- if (TimePassesIsEnabled)
- DebugTimer->startTimer();
+ TimeRegion Timer(DebugTimer);
// Attach DW_AT_inline attribute with inlined subprogram DIEs.
for (SmallPtrSet::iterator AI = InlinedSubprogramDIEs.begin(),
@@ -1926,9 +1921,6 @@
delete ModuleCU;
ModuleCU = NULL; // Reset for the next Module, if any.
-
- if (TimePassesIsEnabled)
- DebugTimer->stopTimer();
}
/// findAbstractVariable - Find abstract variable, if any, associated with Var.
@@ -2229,12 +2221,10 @@
this->MF = MF;
if (!ShouldEmitDwarfDebug()) return;
-
- if (TimePassesIsEnabled)
- DebugTimer->startTimer();
-
if (!extractScopeInformation())
return;
+
+ TimeRegion Timer(DebugTimer);
collectVariableInfo();
@@ -2258,20 +2248,15 @@
recordSourceLine(Line, Col, DLT.getScope().getNode());
}
- if (TimePassesIsEnabled)
- DebugTimer->stopTimer();
}
/// endFunction - Gather and emit post-function debug information.
///
void DwarfDebug::endFunction(const MachineFunction *MF) {
if (!ShouldEmitDwarfDebug()) return;
-
- if (TimePassesIsEnabled)
- DebugTimer->startTimer();
-
- if (DbgScopeMap.empty())
- return;
+ if (DbgScopeMap.empty()) return;
+
+ TimeRegion Timer(DebugTimer);
if (CurrentFnDbgScope) {
// Define end label for subprogram.
@@ -2309,9 +2294,6 @@
AbstractScopesList.clear();
AbstractVariables.clear();
Lines.clear();
-
- if (TimePassesIsEnabled)
- DebugTimer->stopTimer();
}
/// recordSourceLine - Register a source line with debug info. Returns the
@@ -2321,8 +2303,7 @@
if (!MMI)
return 0;
- if (TimePassesIsEnabled)
- DebugTimer->startTimer();
+ TimeRegion Timer(DebugTimer);
StringRef Dir;
StringRef Fn;
@@ -2347,9 +2328,6 @@
MCSymbol *Label = MMI->getContext().CreateTempSymbol();
Lines.push_back(SrcLineInfo(Line, Col, Src, Label));
- if (TimePassesIsEnabled)
- DebugTimer->stopTimer();
-
Asm->OutStreamer.EmitLabel(Label);
return Label;
}
@@ -2361,15 +2339,8 @@
/// well.
unsigned DwarfDebug::getOrCreateSourceID(const std::string &DirName,
const std::string &FileName) {
- if (TimePassesIsEnabled)
- DebugTimer->startTimer();
-
- unsigned SrcId = GetOrCreateSourceID(DirName.c_str(), FileName.c_str());
-
- if (TimePassesIsEnabled)
- DebugTimer->stopTimer();
-
- return SrcId;
+ TimeRegion Timer(DebugTimer);
+ return GetOrCreateSourceID(DirName.c_str(), FileName.c_str());
}
//===----------------------------------------------------------------------===//
From sabre at nondot.org Mon Mar 29 15:39:38 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 29 Mar 2010 20:39:38 -0000
Subject: [llvm-commits] [llvm] r99833 -
/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
Message-ID: <20100329203938.79A992A6C12C@llvm.org>
Author: lattner
Date: Mon Mar 29 15:39:38 2010
New Revision: 99833
URL: http://llvm.org/viewvc/llvm-project?rev=99833&view=rev
Log:
use RAII for ExceptionTimer too
Modified:
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp?rev=99833&r1=99832&r2=99833&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Mon Mar 29 15:39:38 2010
@@ -885,8 +885,7 @@
if (!shouldEmitMovesModule && !shouldEmitTableModule)
return;
- if (TimePassesIsEnabled)
- ExceptionTimer->startTimer();
+ TimeRegion Timer(ExceptionTimer);
const std::vector Personalities = MMI->getPersonalities();
@@ -896,9 +895,6 @@
for (std::vector::iterator
I = EHFrames.begin(), E = EHFrames.end(); I != E; ++I)
EmitFDE(*I);
-
- if (TimePassesIsEnabled)
- ExceptionTimer->stopTimer();
}
/// BeginFunction - Gather pre-function exception information. Assumes it's
@@ -906,9 +902,7 @@
void DwarfException::BeginFunction(const MachineFunction *MF) {
if (!MMI || !MAI->doesSupportExceptionHandling()) return;
- if (TimePassesIsEnabled)
- ExceptionTimer->startTimer();
-
+ TimeRegion Timer(ExceptionTimer);
this->MF = MF;
shouldEmitTable = shouldEmitMoves = false;
@@ -924,9 +918,6 @@
shouldEmitTableModule |= shouldEmitTable;
shouldEmitMovesModule |= shouldEmitMoves;
-
- if (TimePassesIsEnabled)
- ExceptionTimer->stopTimer();
}
/// EndFunction - Gather and emit post-function exception information.
@@ -934,9 +925,7 @@
void DwarfException::EndFunction() {
if (!shouldEmitMoves && !shouldEmitTable) return;
- if (TimePassesIsEnabled)
- ExceptionTimer->startTimer();
-
+ TimeRegion Timer(ExceptionTimer);
Asm->OutStreamer.EmitLabel(getDWLabel("eh_func_end", SubprogramCount));
// Record if this personality index uses a landing pad.
@@ -961,7 +950,4 @@
!MMI->getLandingPads().empty(),
MMI->getFrameMoves(),
MF->getFunction()));
-
- if (TimePassesIsEnabled)
- ExceptionTimer->stopTimer();
}
From sabre at nondot.org Mon Mar 29 15:40:19 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 29 Mar 2010 20:40:19 -0000
Subject: [llvm-commits] [llvm] r99834 - /llvm/trunk/lib/Support/Timer.cpp
Message-ID: <20100329204019.D4AFE2A6C12C@llvm.org>
Author: lattner
Date: Mon Mar 29 15:40:19 2010
New Revision: 99834
URL: http://llvm.org/viewvc/llvm-project?rev=99834&view=rev
Log:
s/.../.
Modified:
llvm/trunk/lib/Support/Timer.cpp
Modified: llvm/trunk/lib/Support/Timer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=99834&r1=99833&r2=99834&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Timer.cpp (original)
+++ llvm/trunk/lib/Support/Timer.cpp Mon Mar 29 15:40:19 2010
@@ -199,7 +199,7 @@
static void printVal(double Val, double Total, raw_ostream &OS) {
- if (Total < 1e-7) // Avoid dividing by zero...
+ if (Total < 1e-7) // Avoid dividing by zero.
OS << " ----- ";
else {
OS << " " << format("%7.4f", Val) << " (";
@@ -285,7 +285,7 @@
// TimerGroup Implementation
//===----------------------------------------------------------------------===//
-// GetLibSupportInfoOutputFile - Return a file stream to print our output on...
+// GetLibSupportInfoOutputFile - Return a file stream to print our output on.
raw_ostream *
llvm::GetLibSupportInfoOutputFile() {
std::string &LibSupportInfoOutputFilename = getLibSupportInfoOutputFilename();
@@ -324,14 +324,14 @@
raw_ostream *OutStream = GetLibSupportInfoOutputFile();
++NumTimers;
- { // Scope to contain Total timer... don't allow total timer to drop us to
- // zero timers...
+ { // Scope to contain Total timer: don't allow total timer to drop us to
+ // zero timers.
Timer Total("TOTAL");
for (unsigned i = 0, e = TimersToPrint.size(); i != e; ++i)
Total.sum(TimersToPrint[i]);
- // Print out timing header...
+ // Print out timing header.
*OutStream << "===" << std::string(73, '-') << "===\n"
<< std::string(Padding, ' ') << Name << "\n"
<< "===" << std::string(73, '-')
@@ -361,7 +361,7 @@
*OutStream << " -PeakMem-";
*OutStream << " --- Name ---\n";
- // Loop through all of the timing data, printing it out...
+ // Loop through all of the timing data, printing it out.
for (unsigned i = 0, e = TimersToPrint.size(); i != e; ++i)
TimersToPrint[i].print(Total, *OutStream);
@@ -374,7 +374,7 @@
TimersToPrint.clear();
if (OutStream != &errs() && OutStream != &outs() && OutStream != &dbgs())
- delete OutStream; // Close the file...
+ delete OutStream; // Close the file.
}
void TimerGroup::addTimer() {
From echristo at apple.com Mon Mar 29 15:41:51 2010
From: echristo at apple.com (Eric Christopher)
Date: Mon, 29 Mar 2010 20:41:51 -0000
Subject: [llvm-commits] [llvm] r99835 -
/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100329204151.4DA412A6C12C@llvm.org>
Author: echristo
Date: Mon Mar 29 15:41:51 2010
New Revision: 99835
URL: http://llvm.org/viewvc/llvm-project?rev=99835&view=rev
Log:
We'll never match these as instructions, just as intrinsics so remove
the SDNodes.
Modified:
llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=99835&r1=99834&r2=99835&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Mar 29 15:41:51 2010
@@ -69,12 +69,6 @@
def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
-def X86aesimc : SDNode<"X86ISD::AESIMC", SDTIntBinOp>;
-def X86aesenc : SDNode<"X86ISD::AESENC", SDTIntBinOp>;
-def X86aesenclast : SDNode<"X86ISD::AESENCLAST", SDTIntBinOp>;
-def X86aesdec : SDNode<"X86ISD::AESDEC", SDTIntBinOp>;
-def X86aesdeclast : SDNode<"X86ISD::AESDECLAST", SDTIntBinOp>;
-
def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
SDTCisVT<1, v4f32>,
SDTCisVT<2, v4f32>]>;
@@ -3841,25 +3835,25 @@
defm AESDECLAST : SS42I_binop_rm_int<0xDF, "aesdeclast",
int_x86_sse42_aesdeclast>;
-def : Pat<(v2i64 (X86aesimc VR128:$src1, VR128:$src2)),
+def : Pat<(v2i64 (int_x86_sse42_aesimc VR128:$src1, VR128:$src2)),
(AESIMCrr VR128:$src1, VR128:$src2)>;
-def : Pat<(v2i64 (X86aesimc VR128:$src1, (memop addr:$src2))),
+def : Pat<(v2i64 (int_x86_sse42_aesimc VR128:$src1, (memop addr:$src2))),
(AESIMCrm VR128:$src1, addr:$src2)>;
-def : Pat<(v2i64 (X86aesenc VR128:$src1, VR128:$src2)),
+def : Pat<(v2i64 (int_x86_sse42_aesenc VR128:$src1, VR128:$src2)),
(AESENCrr VR128:$src1, VR128:$src2)>;
-def : Pat<(v2i64 (X86aesenc VR128:$src1, (memop addr:$src2))),
+def : Pat<(v2i64 (int_x86_sse42_aesenc VR128:$src1, (memop addr:$src2))),
(AESENCrm VR128:$src1, addr:$src2)>;
-def : Pat<(v2i64 (X86aesenclast VR128:$src1, VR128:$src2)),
+def : Pat<(v2i64 (int_x86_sse42_aesenclast VR128:$src1, VR128:$src2)),
(AESENCLASTrr VR128:$src1, VR128:$src2)>;
-def : Pat<(v2i64 (X86aesenclast VR128:$src1, (memop addr:$src2))),
+def : Pat<(v2i64 (int_x86_sse42_aesenclast VR128:$src1, (memop addr:$src2))),
(AESENCLASTrm VR128:$src1, addr:$src2)>;
-def : Pat<(v2i64 (X86aesdec VR128:$src1, VR128:$src2)),
+def : Pat<(v2i64 (int_x86_sse42_aesdec VR128:$src1, VR128:$src2)),
(AESDECrr VR128:$src1, VR128:$src2)>;
-def : Pat<(v2i64 (X86aesdec VR128:$src1, (memop addr:$src2))),
+def : Pat<(v2i64 (int_x86_sse42_aesdec VR128:$src1, (memop addr:$src2))),
(AESDECrm VR128:$src1, addr:$src2)>;
-def : Pat<(v2i64 (X86aesdeclast VR128:$src1, VR128:$src2)),
+def : Pat<(v2i64 (int_x86_sse42_aesdeclast VR128:$src1, VR128:$src2)),
(AESDECLASTrr VR128:$src1, VR128:$src2)>;
-def : Pat<(v2i64 (X86aesdeclast VR128:$src1, (memop addr:$src2))),
+def : Pat<(v2i64 (int_x86_sse42_aesdeclast VR128:$src1, (memop addr:$src2))),
(AESDECLASTrm VR128:$src1, addr:$src2)>;
def AESKEYGENASSIST128rr : SS42AI<0xDF, MRMSrcReg, (outs),
From evan.cheng at apple.com Mon Mar 29 15:48:30 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 29 Mar 2010 20:48:30 -0000
Subject: [llvm-commits] [llvm] r99836 - in /llvm/trunk:
include/llvm/CodeGen/SelectionDAG.h
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20100329204831.165F32A6C12C@llvm.org>
Author: evancheng
Date: Mon Mar 29 15:48:30 2010
New Revision: 99836
URL: http://llvm.org/viewvc/llvm-project?rev=99836&view=rev
Log:
Pool allocate SDDbgValue nodes.
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=99836&r1=99835&r2=99836&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Mar 29 15:48:30 2010
@@ -34,6 +34,7 @@
class MachineConstantPoolValue;
class MachineFunction;
class MachineModuleInfo;
+class MDNode;
class SDNodeOrdering;
class SDDbgValue;
class TargetLowering;
@@ -767,6 +768,15 @@
SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTs,
const SDValue *Ops, unsigned NumOps);
+ /// getDbgValue - Creates a SDDbgValue node.
+ ///
+ SDDbgValue *getDbgValue(MDNode *MDPtr, SDNode *N, unsigned R, uint64_t Off,
+ DebugLoc DL, unsigned O);
+ SDDbgValue *getDbgValue(MDNode *MDPtr, Value *C, uint64_t Off,
+ DebugLoc DL, unsigned O);
+ SDDbgValue *getDbgValue(MDNode *MDPtr, unsigned FI, uint64_t Off,
+ DebugLoc DL, unsigned O);
+
/// DAGUpdateListener - Clients of various APIs that cause global effects on
/// the DAG can optionally implement this interface. This allows the clients
/// to handle the various sorts of updates that happen.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=99836&r1=99835&r2=99836&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Mar 29 15:48:30 2010
@@ -842,6 +842,7 @@
Root = getEntryNode();
delete Ordering;
Ordering = new SDNodeOrdering();
+ DbgInfo->clear();
delete DbgInfo;
DbgInfo = new SDDbgInfo();
}
@@ -4849,6 +4850,26 @@
return NULL;
}
+/// getDbgValue - Creates a SDDbgValue node.
+///
+SDDbgValue *
+SelectionDAG::getDbgValue(MDNode *MDPtr, SDNode *N, unsigned R, uint64_t Off,
+ DebugLoc DL, unsigned O) {
+ return new (Allocator) SDDbgValue(MDPtr, N, R, Off, DL, O);
+}
+
+SDDbgValue *
+SelectionDAG::getDbgValue(MDNode *MDPtr, Value *C, uint64_t Off,
+ DebugLoc DL, unsigned O) {
+ return new (Allocator) SDDbgValue(MDPtr, C, Off, DL, O);
+}
+
+SDDbgValue *
+SelectionDAG::getDbgValue(MDNode *MDPtr, unsigned FI, uint64_t Off,
+ DebugLoc DL, unsigned O) {
+ return new (Allocator) SDDbgValue(MDPtr, FI, Off, DL, O);
+}
+
namespace {
/// RAUWUpdateListener - Helper for ReplaceAllUsesWith - When the node
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=99836&r1=99835&r2=99836&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Mar 29 15:48:30 2010
@@ -3824,22 +3824,19 @@
// debug info exists.
++SDNodeOrder;
if (isa(V) || isa(V)) {
- SDDbgValue* dv = new SDDbgValue(Variable, V, Offset, dl, SDNodeOrder);
- DAG.AddDbgValue(dv);
+ DAG.AddDbgValue(DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder));
} else {
SDValue &N = NodeMap[V];
- if (N.getNode()) {
- SDDbgValue *dv = new SDDbgValue(Variable, N.getNode(),
- N.getResNo(), Offset, dl, SDNodeOrder);
- DAG.AddDbgValue(dv, N.getNode());
- } else {
+ if (N.getNode())
+ DAG.AddDbgValue(DAG.getDbgValue(Variable, N.getNode(),
+ N.getResNo(), Offset, dl, SDNodeOrder),
+ N.getNode());
+ else
// We may expand this to cover more cases. One case where we have no
// data available is an unreferenced parameter; we need this fallback.
- SDDbgValue* dv = new SDDbgValue(Variable,
+ DAG.AddDbgValue(DAG.getDbgValue(Variable,
UndefValue::get(V->getType()),
- Offset, dl, SDNodeOrder);
- DAG.AddDbgValue(dv);
- }
+ Offset, dl, SDNodeOrder));
}
// Build a debug info table entry.
From evan.cheng at apple.com Mon Mar 29 15:49:23 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 29 Mar 2010 13:49:23 -0700
Subject: [llvm-commits] [llvm] r99469 - in /llvm/trunk:
include/llvm/CodeGen/MachineOperand.h include/llvm/CodeGen/SelectionDAG.h
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
lib/CodeGen/SelectionDAG/InstrEmitter.h
lib/CodeGen/SelectionDAG/SDNodeDbgValue.h l
In-Reply-To: <37F7E1A8-9AB0-4736-9C59-7C304AA2BB3A@apple.com>
References:
<37F7E1A8-9AB0-4736-9C59-7C304AA2BB3A@apple.com>
Message-ID: <51C8EEC7-AA24-4BCA-ADD3-80C8DF3C0A15@apple.com>
Does 99836 fix it?
Evan
On Mar 29, 2010, at 11:38 AM, Evan Cheng wrote:
> Looking.
>
> Evan
>
> On Mar 26, 2010, at 10:16 PM, Jeffrey Yasskin wrote:
>
>> Hey Evan, this change may have introduced the new memory leak in
>> DebugInfo/2010-02-01-DbgValueCrash.ll
>> (http://google1.osuosl.org:8011/builders/llvm-x86_64-linux-vg_leak/builds/7/steps/test-llvm/logs/stdio).
>> The whole valgrind error (run at r99590) is:
>>
>> ==8278== 56 bytes in 1 blocks are definitely lost in loss record 130 of 135
>> ==8278== at 0x4C229C7: operator new(unsigned long) (vg_replace_malloc.c:220)
>> ==8278== by 0xD809F6:
>> llvm::SelectionDAGBuilder::visitIntrinsicCall(llvm::CallInst&,
>> unsigned int) (SelectionDAGBuilder.cpp:3840)
>> ==8278== by 0xD87327:
>> llvm::SelectionDAGBuilder::visitCall(llvm::CallInst&)
>> (SelectionDAGBuilder.cpp:4662)
>> ==8278== by 0xD62E31: llvm::SelectionDAGBuilder::visit(unsigned
>> int, llvm::User&) (Instruction.def:161)
>> ==8278== by 0xD6293D:
>> llvm::SelectionDAGBuilder::visit(llvm::Instruction&)
>> (SelectionDAGBuilder.cpp:617)
>> ==8278== by 0xDA455C:
>> llvm::SelectionDAGISel::SelectBasicBlock(llvm::BasicBlock*,
>> llvm::ilist_iterator,
>> llvm::ilist_iterator, bool&)
>> (SelectionDAGISel.cpp:407)
>> ==8278== by 0xDA7952:
>> llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function&,
>> llvm::MachineFunction&, llvm::MachineModuleInfo*, llvm::DwarfWriter*,
>> llvm::TargetInstrInfo const&) (SelectionDAGISel.cpp:1030)
>> ==8278== by 0xDA41E6:
>> llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&)
>> (SelectionDAGISel.cpp:344)
>> ==8278== by 0xEBE6B6:
>> llvm::MachineFunctionPass::runOnFunction(llvm::Function&)
>> (MachineFunctionPass.cpp:27)
>> ==8278== by 0x11E2A5C:
>> llvm::FPPassManager::runOnFunction(llvm::Function&)
>> (PassManager.cpp:1350)
>> ==8278== by 0x11E2734:
>> llvm::FunctionPassManagerImpl::run(llvm::Function&)
>> (PassManager.cpp:1301)
>> ==8278== by 0x11E23E4:
>> llvm::FunctionPassManager::run(llvm::Function&) (PassManager.cpp:1231)
>> ==8278==
>>
>> Could you take a look? Sorry if you've already fixed this.
>>
>> On Wed, Mar 24, 2010 at 6:38 PM, Evan Cheng wrote:
>>> Author: evancheng
>>> Date: Wed Mar 24 20:38:16 2010
>>> New Revision: 99469
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=99469&view=rev
>>> Log:
>>> Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers.
>>>
>>> Here is a theoretical example that illustrates why the placement is important.
>>>
>>> tmp1 =
>>> store tmp1 -> x
>>> ...
>>> tmp2 = add ...
>>> ...
>>> call
>>> ...
>>> store tmp2 -> x
>>>
>>> Now mem2reg comes along:
>>>
>>> tmp1 =
>>> dbg_value (tmp1 -> x)
>>> ...
>>> tmp2 = add ...
>>> ...
>>> call
>>> ...
>>> dbg_value (tmp2 -> x)
>>>
>>> When the debugger examine the value of x after the add instruction but before the call, it should have the value of tmp1.
>>>
>>> Furthermore, for dbg_value's that reference constants, they should not be emitted at the beginning of the block (since they do not have "producers").
>>>
>>> This patch also cleans up how SDISel manages DbgValue nodes. It allow a SDNode to be referenced by multiple SDDbgValue nodes. When a SDNode is deleted, it uses the information to find the SDDbgValues and invalidate them. They are not deleted until the corresponding SelectionDAG is destroyed.
>>>
>>> Modified:
>>> llvm/trunk/include/llvm/CodeGen/MachineOperand.h
>>> llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>>> llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
>>> llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
>>> llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
>>> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
>>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=99469&r1=99468&r2=99469&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Wed Mar 24 20:38:16 2010
>>> @@ -285,6 +285,11 @@
>>> IsEarlyClobber = Val;
>>> }
>>>
>>> + void setIsDebug(bool Val = true) {
>>> + assert(isReg() && IsDef && "Wrong MachineOperand accessor");
>>> + IsDebug = Val;
>>> + }
>>> +
>>> //===--------------------------------------------------------------------===//
>>> // Accessors for various operand types.
>>> //===--------------------------------------------------------------------===//
>>>
>>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=99469&r1=99468&r2=99469&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Mar 24 20:38:16 2010
>>> @@ -60,42 +60,40 @@
>>>
>>> /// SDDbgInfo - Keeps track of dbg_value information through SDISel. We do
>>> /// not build SDNodes for these so as not to perturb the generated code;
>>> -/// instead the info is kept off to the side in this structure. SDNodes may
>>> -/// have an associated dbg_value entry in DbgValMap. Debug info that is not
>>> -/// associated with any SDNode is held in DbgConstMap. It is possible for
>>> -/// optimizations to change a variable to a constant, in which case the
>>> -/// corresponding debug info is moved from the variable to the constant table
>>> -/// (NYI).
>>> +/// instead the info is kept off to the side in this structure. Each SDNode may
>>> +/// have one or more associated dbg_value entries. This information is kept in
>>> +/// DbgValMap.
>>> class SDDbgInfo {
>>> - DenseMap DbgVblMap;
>>> - SmallVector DbgConstMap;
>>> + SmallVector DbgValues;
>>> + DenseMap > DbgVblMap;
>>>
>>> void operator=(const SDDbgInfo&); // Do not implement.
>>> SDDbgInfo(const SDDbgInfo&); // Do not implement.
>>> public:
>>> SDDbgInfo() {}
>>>
>>> - void add(const SDNode *Node, SDDbgValue *V) {
>>> - DbgVblMap[Node] = V;
>>> + void add(SDDbgValue *V, const SDNode *Node = 0) {
>>> + if (Node)
>>> + DbgVblMap[Node].push_back(V);
>>> + DbgValues.push_back(V);
>>> }
>>> - void add(SDDbgValue *V) { DbgConstMap.push_back(V); }
>>> - void remove(const SDNode *Node) {
>>> - DenseMap::iterator Itr =
>>> - DbgVblMap.find(Node);
>>> - if (Itr != DbgVblMap.end())
>>> - DbgVblMap.erase(Itr);
>>> - }
>>> - // No need to remove a constant.
>>> +
>>> void clear() {
>>> DbgVblMap.clear();
>>> - DbgConstMap.clear();
>>> + DbgValues.clear();
>>> + }
>>> +
>>> + bool empty() const {
>>> + return DbgValues.empty();
>>> }
>>> - SDDbgValue *getSDDbgValue(const SDNode *Node) {
>>> +
>>> + SmallVector &getSDDbgValues(const SDNode *Node) {
>>> return DbgVblMap[Node];
>>> }
>>> - typedef SmallVector::iterator ConstDbgIterator;
>>> - ConstDbgIterator DbgConstBegin() { return DbgConstMap.begin(); }
>>> - ConstDbgIterator DbgConstEnd() { return DbgConstMap.end(); }
>>> +
>>> + typedef SmallVector::iterator DbgIterator;
>>> + DbgIterator DbgBegin() { return DbgValues.begin(); }
>>> + DbgIterator DbgEnd() { return DbgValues.end(); }
>>> };
>>>
>>> enum CombineLevel {
>>> @@ -871,19 +869,21 @@
>>> /// GetOrdering - Get the order for the SDNode.
>>> unsigned GetOrdering(const SDNode *SD) const;
>>>
>>> - /// AssignDbgInfo - Assign debug info to the SDNode.
>>> - void AssignDbgInfo(SDNode *SD, SDDbgValue *db);
>>> + /// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means the
>>> + /// value is produced by SD.
>>> + void AddDbgValue(SDDbgValue *DB, SDNode *SD = 0);
>>>
>>> - /// RememberDbgInfo - Remember debug info with no associated SDNode.
>>> - void RememberDbgInfo(SDDbgValue *db);
>>> + /// GetDbgValues - Get the debug values which reference the given SDNode.
>>> + SmallVector &GetDbgValues(const SDNode* SD) {
>>> + return DbgInfo->getSDDbgValues(SD);
>>> + }
>>>
>>> - /// GetDbgInfo - Get the debug info for the SDNode.
>>> - SDDbgValue *GetDbgInfo(const SDNode* SD);
>>> + /// hasDebugValues - Return true if there are any SDDbgValue nodes associated
>>> + /// with this SelectionDAG.
>>> + bool hasDebugValues() const { return !DbgInfo->empty(); }
>>>
>>> - SDDbgInfo::ConstDbgIterator DbgConstBegin() {
>>> - return DbgInfo->DbgConstBegin();
>>> - }
>>> - SDDbgInfo::ConstDbgIterator DbgConstEnd() { return DbgInfo->DbgConstEnd(); }
>>> + SDDbgInfo::DbgIterator DbgBegin() { return DbgInfo->DbgBegin(); }
>>> + SDDbgInfo::DbgIterator DbgEnd() { return DbgInfo->DbgEnd(); }
>>>
>>> void dump() const;
>>>
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=99469&r1=99468&r2=99469&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Wed Mar 24 20:38:16 2010
>>> @@ -264,7 +264,8 @@
>>> InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
>>> unsigned IIOpNum,
>>> const TargetInstrDesc *II,
>>> - DenseMap &VRBaseMap) {
>>> + DenseMap &VRBaseMap,
>>> + bool IsDebug) {
>>> assert(Op.getValueType() != MVT::Other &&
>>> Op.getValueType() != MVT::Flag &&
>>> "Chain and flag operands should occur at end of operand list!");
>>> @@ -295,7 +296,11 @@
>>> }
>>> }
>>>
>>> - MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
>>> + MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
>>> + false/*isImp*/, false/*isKill*/,
>>> + false/*isDead*/, false/*isUndef*/,
>>> + false/*isEarlyClobber*/,
>>> + 0/*SubReg*/, IsDebug));
>>> }
>>>
>>> /// AddOperand - Add the specified operand to the specified machine instr. II
>>> @@ -305,9 +310,10 @@
>>> void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
>>> unsigned IIOpNum,
>>> const TargetInstrDesc *II,
>>> - DenseMap &VRBaseMap) {
>>> + DenseMap &VRBaseMap,
>>> + bool IsDebug) {
>>> if (Op.isMachineOpcode()) {
>>> - AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
>>> + AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug);
>>> } else if (ConstantSDNode *C = dyn_cast(Op)) {
>>> MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
>>> } else if (ConstantFPSDNode *F = dyn_cast(Op)) {
>>> @@ -356,7 +362,7 @@
>>> assert(Op.getValueType() != MVT::Other &&
>>> Op.getValueType() != MVT::Flag &&
>>> "Chain and flag operands should occur at end of operand list!");
>>> - AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
>>> + AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug);
>>> }
>>> }
>>>
>>> @@ -498,75 +504,48 @@
>>> assert(isNew && "Node emitted out of order - early");
>>> }
>>>
>>> -/// EmitDbgValue - Generate any debug info that refers to this Node. Constant
>>> -/// dbg_value is not handled here.
>>> -void
>>> -InstrEmitter::EmitDbgValue(SDNode *Node,
>>> - DenseMap &VRBaseMap,
>>> - SDDbgValue *sd) {
>>> - if (!Node->getHasDebugValue())
>>> - return;
>>> - if (!sd)
>>> - return;
>>> - assert(sd->getKind() == SDDbgValue::SDNODE);
>>> - unsigned VReg = getVR(SDValue(sd->getSDNode(), sd->getResNo()), VRBaseMap);
>>> - const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
>>> - DebugLoc DL = sd->getDebugLoc();
>>> - MachineInstr *MI;
>>> - if (VReg) {
>>> - MI = BuildMI(*MF, DL, II).addReg(VReg, RegState::Debug).
>>> - addImm(sd->getOffset()).
>>> - addMetadata(sd->getMDPtr());
>>> - } else {
>>> - // Insert an Undef so we can see what we dropped.
>>> - MI = BuildMI(*MF, DL, II).addReg(0U).addImm(sd->getOffset()).
>>> - addMetadata(sd->getMDPtr());
>>> - }
>>> - MBB->insert(InsertPos, MI);
>>> -}
>>> -
>>> -/// EmitDbgValue - Generate debug info that does not refer to a SDNode.
>>> -void
>>> -InstrEmitter::EmitDbgValue(SDDbgValue *sd,
>>> +/// EmitDbgValue - Generate machine instruction for a dbg_value node.
>>> +///
>>> +MachineInstr *InstrEmitter::EmitDbgValue(SDDbgValue *SD,
>>> + MachineBasicBlock *InsertBB,
>>> + DenseMap &VRBaseMap,
>>> DenseMap *EM) {
>>> - if (!sd)
>>> - return;
>>> + uint64_t Offset = SD->getOffset();
>>> + MDNode* MDPtr = SD->getMDPtr();
>>> + DebugLoc DL = SD->getDebugLoc();
>>> +
>>> const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
>>> - uint64_t Offset = sd->getOffset();
>>> - MDNode* mdPtr = sd->getMDPtr();
>>> - SDDbgValue::DbgValueKind kind = sd->getKind();
>>> - DebugLoc DL = sd->getDebugLoc();
>>> - MachineInstr* MI;
>>> - if (kind == SDDbgValue::CONST) {
>>> - Value *V = sd->getConst();
>>> + MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
>>> + if (SD->getKind() == SDDbgValue::SDNODE) {
>>> + AddOperand(&*MIB, SDValue(SD->getSDNode(), SD->getResNo()),
>>> + (*MIB).getNumOperands(), &II, VRBaseMap, true /*IsDebug*/);
>>> + } else if (SD->getKind() == SDDbgValue::CONST) {
>>> + Value *V = SD->getConst();
>>> if (ConstantInt *CI = dyn_cast(V)) {
>>> - MI = BuildMI(*MF, DL, II).addImm(CI->getZExtValue()).
>>> - addImm(Offset).addMetadata(mdPtr);
>>> + MIB.addImm(CI->getSExtValue());
>>> } else if (ConstantFP *CF = dyn_cast(V)) {
>>> - MI = BuildMI(*MF, DL, II).addFPImm(CF).
>>> - addImm(Offset).addMetadata(mdPtr);
>>> + MIB.addFPImm(CF);
>>> } else {
>>> // Could be an Undef. In any case insert an Undef so we can see what we
>>> // dropped.
>>> - MI = BuildMI(*MF, DL, II).addReg(0U).
>>> - addImm(Offset).addMetadata(mdPtr);
>>> + MIB.addReg(0U);
>>> }
>>> - } else if (kind == SDDbgValue::FRAMEIX) {
>>> - unsigned FrameIx = sd->getFrameIx();
>>> + } else if (SD->getKind() == SDDbgValue::FRAMEIX) {
>>> + unsigned FrameIx = SD->getFrameIx();
>>> // Stack address; this needs to be lowered in target-dependent fashion.
>>> // FIXME test that the target supports this somehow; if not emit Undef.
>>> // Create a pseudo for EmitInstrWithCustomInserter's consumption.
>>> - MI = BuildMI(*MF, DL, II).addImm(FrameIx).
>>> - addImm(Offset).addMetadata(mdPtr);
>>> - MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
>>> - InsertPos = MBB->end();
>>> - return;
>>> + MIB.addImm(FrameIx).addImm(Offset).addMetadata(MDPtr);
>>> + abort();
>>> + TLI->EmitInstrWithCustomInserter(&*MIB, InsertBB, EM);
>>> + return 0;
>>> } else {
>>> // Insert an Undef so we can see what we dropped.
>>> - MI = BuildMI(*MF, DL, II).addReg(0U).
>>> - addImm(Offset).addMetadata(mdPtr);
>>> + MIB.addReg(0U);
>>> }
>>> - MBB->insert(InsertPos, MI);
>>> +
>>> + MIB.addImm(Offset).addMetadata(MDPtr);
>>> + return &*MIB;
>>> }
>>>
>>> /// EmitNode - Generate machine code for a node and needed dependencies.
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h?rev=99469&r1=99468&r2=99469&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h Wed Mar 24 20:38:16 2010
>>> @@ -64,7 +64,8 @@
>>> void AddRegisterOperand(MachineInstr *MI, SDValue Op,
>>> unsigned IIOpNum,
>>> const TargetInstrDesc *II,
>>> - DenseMap &VRBaseMap);
>>> + DenseMap &VRBaseMap,
>>> + bool IsDebug = false);
>>>
>>> /// AddOperand - Add the specified operand to the specified machine instr. II
>>> /// specifies the instruction information for the node, and IIOpNum is the
>>> @@ -73,7 +74,8 @@
>>> void AddOperand(MachineInstr *MI, SDValue Op,
>>> unsigned IIOpNum,
>>> const TargetInstrDesc *II,
>>> - DenseMap &VRBaseMap);
>>> + DenseMap &VRBaseMap,
>>> + bool IsDebug = false);
>>>
>>> /// EmitSubregNode - Generate machine code for subreg nodes.
>>> ///
>>> @@ -98,16 +100,12 @@
>>> /// MachineInstr.
>>> static unsigned CountOperands(SDNode *Node);
>>>
>>> - /// EmitDbgValue - Generate any debug info that refers to this Node. Constant
>>> - /// dbg_value is not handled here.
>>> - void EmitDbgValue(SDNode *Node,
>>> - DenseMap &VRBaseMap,
>>> - SDDbgValue* sd);
>>> -
>>> -
>>> - /// EmitDbgValue - Generate a constant DBG_VALUE. No node is involved.
>>> - void EmitDbgValue(SDDbgValue* sd,
>>> - DenseMap *EM);
>>> + /// EmitDbgValue - Generate machine instruction for a dbg_value node.
>>> + ///
>>> + MachineInstr *EmitDbgValue(SDDbgValue *SD,
>>> + MachineBasicBlock *InsertBB,
>>> + DenseMap &VRBaseMap,
>>> + DenseMap *EM);
>>>
>>> /// EmitNode - Generate machine code for a node and needed dependencies.
>>> ///
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h?rev=99469&r1=99468&r2=99469&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h Wed Mar 24 20:38:16 2010
>>> @@ -47,10 +47,12 @@
>>> uint64_t Offset;
>>> DebugLoc DL;
>>> unsigned Order;
>>> + bool Invalid;
>>> public:
>>> // Constructor for non-constants.
>>> SDDbgValue(MDNode *mdP, SDNode *N, unsigned R, uint64_t off, DebugLoc dl,
>>> - unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O) {
>>> + unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
>>> + Invalid(false) {
>>> kind = SDNODE;
>>> u.s.Node = N;
>>> u.s.ResNo = R;
>>> @@ -97,6 +99,12 @@
>>> // Returns the SDNodeOrder. This is the order of the preceding node in the
>>> // input.
>>> unsigned getOrder() { return Order; }
>>> +
>>> + // setIsInvalidated / isInvalidated - Setter / getter of the "Invalidated"
>>> + // property. A SDDbgValue is invalid if the SDNode that produces the value is
>>> + // deleted.
>>> + void setIsInvalidated() { Invalid = true; }
>>> + bool isInvalidated() { return Invalid; }
>>> };
>>>
>>> } // end llvm namespace
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=99469&r1=99468&r2=99469&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Wed Mar 24 20:38:16 2010
>>> @@ -23,6 +23,7 @@
>>> #include "llvm/Target/TargetSubtarget.h"
>>> #include "llvm/ADT/DenseMap.h"
>>> #include "llvm/ADT/SmallPtrSet.h"
>>> +#include "llvm/ADT/SmallSet.h"
>>> #include "llvm/ADT/SmallVector.h"
>>> #include "llvm/ADT/Statistic.h"
>>> #include "llvm/Support/Debug.h"
>>> @@ -407,19 +408,67 @@
>>> }
>>> }
>>>
>>> +namespace {
>>> + struct OrderSorter {
>>> + bool operator()(const std::pair &A,
>>> + const std::pair &B) {
>>> + return A.first < B.first;
>>> + }
>>> + };
>>> +}
>>> +
>>> +// ProcessSourceNode - Process nodes with source order numbers. These are added
>>> +// to a vector which EmitSchedule use to determine how to insert dbg_value
>>> +// instructions in the right order.
>>> +static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
>>> + InstrEmitter &Emitter,
>>> + DenseMap *EM,
>>> + DenseMap &VRBaseMap,
>>> + SmallVector, 32> &Orders,
>>> + SmallSet &Seen) {
>>> + unsigned Order = DAG->GetOrdering(N);
>>> + if (!Order || !Seen.insert(Order))
>>> + return;
>>> +
>>> + MachineBasicBlock *BB = Emitter.getBlock();
>>> + if (BB->empty() || BB->back().isPHI()) {
>>> + // Did not insert any instruction.
>>> + Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
>>> + return;
>>> + }
>>> +
>>> + Orders.push_back(std::make_pair(Order, &BB->back()));
>>> + if (!N->getHasDebugValue())
>>> + return;
>>> + // Opportunistically insert immediate dbg_value uses, i.e. those with source
>>> + // order number right after the N.
>>> + MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
>>> + SmallVector &DVs = DAG->GetDbgValues(N);
>>> + for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
>>> + if (DVs[i]->isInvalidated())
>>> + continue;
>>> + unsigned DVOrder = DVs[i]->getOrder();
>>> + if (DVOrder == ++Order) {
>>> + // FIXME: If the source node with next higher order is scheduled before
>>> + // this could end up generating funky debug info.
>>> + MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], BB, VRBaseMap, EM);
>>> + Orders.push_back(std::make_pair(DVOrder, DbgMI));
>>> + BB->insert(InsertPos, DbgMI);
>>> + DVs[i]->setIsInvalidated();
>>> + }
>>> + }
>>> +}
>>> +
>>> +
>>> /// EmitSchedule - Emit the machine code in scheduled order.
>>> MachineBasicBlock *ScheduleDAGSDNodes::
>>> EmitSchedule(DenseMap *EM) {
>>> InstrEmitter Emitter(BB, InsertPos);
>>> DenseMap VRBaseMap;
>>> DenseMap CopyVRBaseMap;
>>> -
>>> - // For now, any constant debug info nodes go at the beginning.
>>> - for (SDDbgInfo::ConstDbgIterator I = DAG->DbgConstBegin(),
>>> - E = DAG->DbgConstEnd(); I!=E; I++) {
>>> - Emitter.EmitDbgValue(*I, EM);
>>> - delete *I;
>>> - }
>>> + SmallVector, 32> Orders;
>>> + SmallSet Seen;
>>> + bool HasDbg = DAG->hasDebugValues();
>>>
>>> for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
>>> SUnit *SU = Sequence[i];
>>> @@ -442,22 +491,72 @@
>>> N = N->getFlaggedNode())
>>> FlaggedNodes.push_back(N);
>>> while (!FlaggedNodes.empty()) {
>>> + SDNode *N = FlaggedNodes.back();
>>> Emitter.EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,
>>> VRBaseMap, EM);
>>> - if (FlaggedNodes.back()->getHasDebugValue())
>>> - if (SDDbgValue *sd = DAG->GetDbgInfo(FlaggedNodes.back())) {
>>> - Emitter.EmitDbgValue(FlaggedNodes.back(), VRBaseMap, sd);
>>> - delete sd;
>>> - }
>>> + // Remember the the source order of the inserted instruction.
>>> + if (HasDbg)
>>> + ProcessSourceNode(N, DAG, Emitter, EM, VRBaseMap, Orders, Seen);
>>> FlaggedNodes.pop_back();
>>> }
>>> Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
>>> VRBaseMap, EM);
>>> - if (SU->getNode()->getHasDebugValue())
>>> - if (SDDbgValue *sd = DAG->GetDbgInfo(SU->getNode())) {
>>> - Emitter.EmitDbgValue(SU->getNode(), VRBaseMap, sd);
>>> - delete sd;
>>> + // Remember the the source order of the inserted instruction.
>>> + if (HasDbg)
>>> + ProcessSourceNode(SU->getNode(), DAG, Emitter, EM, VRBaseMap, Orders,
>>> + Seen);
>>> + }
>>> +
>>> + // Insert all the dbg_value which have not already been inserted in source
>>> + // order sequence.
>>> + if (HasDbg) {
>>> + MachineBasicBlock::iterator BBBegin = BB->empty() ? BB->end() : BB->begin();
>>> + while (BBBegin != BB->end() && BBBegin->isPHI())
>>> + ++BBBegin;
>>> +
>>> + // Sort the source order instructions and use the order to insert debug
>>> + // values.
>>> + std::sort(Orders.begin(), Orders.end(), OrderSorter());
>>> +
>>> + SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
>>> + SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
>>> + // Now emit the rest according to source order.
>>> + unsigned LastOrder = 0;
>>> + MachineInstr *LastMI = 0;
>>> + for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
>>> + unsigned Order = Orders[i].first;
>>> + MachineInstr *MI = Orders[i].second;
>>> + // Insert all SDDbgValue's whose order(s) are before "Order".
>>> + if (!MI)
>>> + continue;
>>> + MachineBasicBlock *MIBB = MI->getParent();
>>> + for (; DI != DE &&
>>> + (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
>>> + if ((*DI)->isInvalidated())
>>> + continue;
>>> + MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, MIBB, VRBaseMap, EM);
>>> + if (!LastOrder)
>>> + // Insert to start of the BB (after PHIs).
>>> + BB->insert(BBBegin, DbgMI);
>>> + else {
>>> + MachineBasicBlock::iterator Pos = MI;
>>> + MIBB->insert(llvm::next(Pos), DbgMI);
>>> + }
>>> }
>>> + LastOrder = Order;
>>> + LastMI = MI;
>>> + }
>>> + // Add trailing DbgValue's before the terminator. FIXME: May want to add
>>> + // some of them before one or more conditional branches?
>>> + while (DI != DE) {
>>> + MachineBasicBlock *InsertBB = Emitter.getBlock();
>>> + MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator();
>>> + if (!(*DI)->isInvalidated()) {
>>> + MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, InsertBB, VRBaseMap, EM);
>>> + InsertBB->insert(Pos, DbgMI);
>>> + }
>>> + ++DI;
>>> + }
>>> }
>>>
>>> BB = Emitter.getBlock();
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=99469&r1=99468&r2=99469&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Mar 24 20:38:16 2010
>>> @@ -598,8 +598,10 @@
>>> // Remove the ordering of this node.
>>> Ordering->remove(N);
>>>
>>> - // And its entry in the debug info table, if any.
>>> - DbgInfo->remove(N);
>>> + // If any of the SDDbgValue nodes refer to this SDNode, invalidate them.
>>> + SmallVector &DbgVals = DbgInfo->getSDDbgValues(N);
>>> + for (unsigned i = 0, e = DbgVals.size(); i != e; ++i)
>>> + DbgVals[i]->setIsInvalidated();
>>> }
>>>
>>> /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
>>> @@ -811,6 +813,7 @@
>>> SelectionDAG::~SelectionDAG() {
>>> allnodes_clear();
>>> delete Ordering;
>>> + DbgInfo->clear();
>>> delete DbgInfo;
>>> }
>>>
>>> @@ -5241,24 +5244,12 @@
>>> return Ordering->getOrder(SD);
>>> }
>>>
>>> -/// AssignDbgInfo - Assign debug info to the SDNode.
>>> -void SelectionDAG::AssignDbgInfo(SDNode* SD, SDDbgValue* db) {
>>> - assert(SD && "Trying to assign dbg info to a null node!");
>>> - DbgInfo->add(SD, db);
>>> - SD->setHasDebugValue(true);
>>> -}
>>> -
>>> -/// RememberDbgInfo - Remember debug info which is not assigned to an SDNode.
>>> -void SelectionDAG::RememberDbgInfo(SDDbgValue* db) {
>>> - DbgInfo->add(db);
>>> -}
>>> -
>>> -/// GetDbgInfo - Get the debug info, if any, for the SDNode.
>>> -SDDbgValue* SelectionDAG::GetDbgInfo(const SDNode *SD) {
>>> - assert(SD && "Trying to get the order of a null node!");
>>> - if (SD->getHasDebugValue())
>>> - return DbgInfo->getSDDbgValue(SD);
>>> - return 0;
>>> +/// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means the
>>> +/// value is produced by SD.
>>> +void SelectionDAG::AddDbgValue(SDDbgValue *DB, SDNode *SD) {
>>> + DbgInfo->add(DB, SD);
>>> + if (SD)
>>> + SD->setHasDebugValue(true);
>>> }
>>>
>>> //===----------------------------------------------------------------------===//
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=99469&r1=99468&r2=99469&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Mar 24 20:38:16 2010
>>> @@ -3825,20 +3825,20 @@
>>> ++SDNodeOrder;
>>> if (isa(V) || isa(V)) {
>>> SDDbgValue* dv = new SDDbgValue(Variable, V, Offset, dl, SDNodeOrder);
>>> - DAG.RememberDbgInfo(dv);
>>> + DAG.AddDbgValue(dv);
>>> } else {
>>> SDValue &N = NodeMap[V];
>>> if (N.getNode()) {
>>> SDDbgValue *dv = new SDDbgValue(Variable, N.getNode(),
>>> N.getResNo(), Offset, dl, SDNodeOrder);
>>> - DAG.AssignDbgInfo(N.getNode(), dv);
>>> + DAG.AddDbgValue(dv, N.getNode());
>>> } else {
>>> // We may expand this to cover more cases. One case where we have no
>>> // data available is an unreferenced parameter; we need this fallback.
>>> SDDbgValue* dv = new SDDbgValue(Variable,
>>> UndefValue::get(V->getType()),
>>> Offset, dl, SDNodeOrder);
>>> - DAG.RememberDbgInfo(dv);
>>> + DAG.AddDbgValue(dv);
>>> }
>>> }
>>>
>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
From jyasskin at google.com Mon Mar 29 15:53:47 2010
From: jyasskin at google.com (Jeffrey Yasskin)
Date: Mon, 29 Mar 2010 13:53:47 -0700
Subject: [llvm-commits] [llvm] r99469 - in /llvm/trunk:
include/llvm/CodeGen/MachineOperand.h
include/llvm/CodeGen/SelectionDAG.h
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
lib/CodeGen/SelectionDAG/InstrEmitter.h
lib/CodeGen/SelectionDAG/SDNodeDbgValue.h l
In-Reply-To: <51C8EEC7-AA24-4BCA-ADD3-80C8DF3C0A15@apple.com>
References:
<37F7E1A8-9AB0-4736-9C59-7C304AA2BB3A@apple.com>
<51C8EEC7-AA24-4BCA-ADD3-80C8DF3C0A15@apple.com>
Message-ID:
I've started http://google1.osuosl.org:8011/builders/llvm-x86_64-linux-vg_leak/builds/11
to check. Thanks!
On Mon, Mar 29, 2010 at 1:49 PM, Evan Cheng wrote:
> Does 99836 fix it?
>
> Evan
> On Mar 29, 2010, at 11:38 AM, Evan Cheng wrote:
>
>> Looking.
>>
>> Evan
>>
>> On Mar 26, 2010, at 10:16 PM, Jeffrey Yasskin wrote:
>>
>>> Hey Evan, this change may have introduced the new memory leak in
>>> DebugInfo/2010-02-01-DbgValueCrash.ll
>>> (http://google1.osuosl.org:8011/builders/llvm-x86_64-linux-vg_leak/builds/7/steps/test-llvm/logs/stdio).
>>> The whole valgrind error (run at r99590) is:
>>>
>>> ==8278== 56 bytes in 1 blocks are definitely lost in loss record 130 of 135
>>> ==8278== ? ?at 0x4C229C7: operator new(unsigned long) (vg_replace_malloc.c:220)
>>> ==8278== ? ?by 0xD809F6:
>>> llvm::SelectionDAGBuilder::visitIntrinsicCall(llvm::CallInst&,
>>> unsigned int) (SelectionDAGBuilder.cpp:3840)
>>> ==8278== ? ?by 0xD87327:
>>> llvm::SelectionDAGBuilder::visitCall(llvm::CallInst&)
>>> (SelectionDAGBuilder.cpp:4662)
>>> ==8278== ? ?by 0xD62E31: llvm::SelectionDAGBuilder::visit(unsigned
>>> int, llvm::User&) (Instruction.def:161)
>>> ==8278== ? ?by 0xD6293D:
>>> llvm::SelectionDAGBuilder::visit(llvm::Instruction&)
>>> (SelectionDAGBuilder.cpp:617)
>>> ==8278== ? ?by 0xDA455C:
>>> llvm::SelectionDAGISel::SelectBasicBlock(llvm::BasicBlock*,
>>> llvm::ilist_iterator,
>>> llvm::ilist_iterator, bool&)
>>> (SelectionDAGISel.cpp:407)
>>> ==8278== ? ?by 0xDA7952:
>>> llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function&,
>>> llvm::MachineFunction&, llvm::MachineModuleInfo*, llvm::DwarfWriter*,
>>> llvm::TargetInstrInfo const&) (SelectionDAGISel.cpp:1030)
>>> ==8278== ? ?by 0xDA41E6:
>>> llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&)
>>> (SelectionDAGISel.cpp:344)
>>> ==8278== ? ?by 0xEBE6B6:
>>> llvm::MachineFunctionPass::runOnFunction(llvm::Function&)
>>> (MachineFunctionPass.cpp:27)
>>> ==8278== ? ?by 0x11E2A5C:
>>> llvm::FPPassManager::runOnFunction(llvm::Function&)
>>> (PassManager.cpp:1350)
>>> ==8278== ? ?by 0x11E2734:
>>> llvm::FunctionPassManagerImpl::run(llvm::Function&)
>>> (PassManager.cpp:1301)
>>> ==8278== ? ?by 0x11E23E4:
>>> llvm::FunctionPassManager::run(llvm::Function&) (PassManager.cpp:1231)
>>> ==8278==
>>>
>>> Could you take a look? Sorry if you've already fixed this.
>>>
>>> On Wed, Mar 24, 2010 at 6:38 PM, Evan Cheng wrote:
>>>> Author: evancheng
>>>> Date: Wed Mar 24 20:38:16 2010
>>>> New Revision: 99469
>>>>
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=99469&view=rev
>>>> Log:
>>>> Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers.
>>>>
>>>> Here is a theoretical example that illustrates why the placement is important.
>>>>
>>>> tmp1 =
>>>> store tmp1 -> x
>>>> ...
>>>> tmp2 = add ...
>>>> ...
>>>> call
>>>> ...
>>>> store tmp2 -> x
>>>>
>>>> Now mem2reg comes along:
>>>>
>>>> tmp1 =
>>>> dbg_value (tmp1 -> x)
>>>> ...
>>>> tmp2 = add ...
>>>> ...
>>>> call
>>>> ...
>>>> dbg_value (tmp2 -> x)
>>>>
>>>> When the debugger examine the value of x after the add instruction but before the call, it should have the value of tmp1.
>>>>
>>>> Furthermore, for dbg_value's that reference constants, they should not be emitted at the beginning of the block (since they do not have "producers").
>>>>
>>>> This patch also cleans up how SDISel manages DbgValue nodes. It allow a SDNode to be referenced by multiple SDDbgValue nodes. When a SDNode is deleted, it uses the information to find the SDDbgValues and invalidate them. They are not deleted until the corresponding SelectionDAG is destroyed.
>>>>
>>>> Modified:
>>>> ? llvm/trunk/include/llvm/CodeGen/MachineOperand.h
>>>> ? llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
>>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
>>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
>>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
>>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>>>> ? llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
>>>>
>>>> Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=99469&r1=99468&r2=99469&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original)
>>>> +++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Wed Mar 24 20:38:16 2010
>>>> @@ -285,6 +285,11 @@
>>>> ? ?IsEarlyClobber = Val;
>>>> ?}
>>>>
>>>> + ?void setIsDebug(bool Val = true) {
>>>> + ? ?assert(isReg() && IsDef && "Wrong MachineOperand accessor");
>>>> + ? ?IsDebug = Val;
>>>> + ?}
>>>> +
>>>> ?//===--------------------------------------------------------------------===//
>>>> ?// Accessors for various operand types.
>>>> ?//===--------------------------------------------------------------------===//
>>>>
>>>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=99469&r1=99468&r2=99469&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
>>>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Mar 24 20:38:16 2010
>>>> @@ -60,42 +60,40 @@
>>>>
>>>> /// SDDbgInfo - Keeps track of dbg_value information through SDISel. ?We do
>>>> /// not build SDNodes for these so as not to perturb the generated code;
>>>> -/// instead the info is kept off to the side in this structure. ?SDNodes may
>>>> -/// have an associated dbg_value entry in DbgValMap. ?Debug info that is not
>>>> -/// associated with any SDNode is held in DbgConstMap. ?It is possible for
>>>> -/// optimizations to change a variable to a constant, in which case the
>>>> -/// corresponding debug info is moved from the variable to the constant table
>>>> -/// (NYI).
>>>> +/// instead the info is kept off to the side in this structure. Each SDNode may
>>>> +/// have one or more associated dbg_value entries. This information is kept in
>>>> +/// DbgValMap.
>>>> class SDDbgInfo {
>>>> - ?DenseMap DbgVblMap;
>>>> - ?SmallVector DbgConstMap;
>>>> + ?SmallVector DbgValues;
>>>> + ?DenseMap > DbgVblMap;
>>>>
>>>> ?void operator=(const SDDbgInfo&); ? // Do not implement.
>>>> ?SDDbgInfo(const SDDbgInfo&); ? // Do not implement.
>>>> public:
>>>> ?SDDbgInfo() {}
>>>>
>>>> - ?void add(const SDNode *Node, SDDbgValue *V) {
>>>> - ? ?DbgVblMap[Node] = V;
>>>> + ?void add(SDDbgValue *V, const SDNode *Node = 0) {
>>>> + ? ?if (Node)
>>>> + ? ? ?DbgVblMap[Node].push_back(V);
>>>> + ? ?DbgValues.push_back(V);
>>>> ?}
>>>> - ?void add(SDDbgValue *V) { DbgConstMap.push_back(V); }
>>>> - ?void remove(const SDNode *Node) {
>>>> - ? ?DenseMap::iterator Itr =
>>>> - ? ? ? ? ? ? ? ? ? ? ?DbgVblMap.find(Node);
>>>> - ? ?if (Itr != DbgVblMap.end())
>>>> - ? ? ?DbgVblMap.erase(Itr);
>>>> - ?}
>>>> - ?// No need to remove a constant.
>>>> +
>>>> ?void clear() {
>>>> ? ?DbgVblMap.clear();
>>>> - ? ?DbgConstMap.clear();
>>>> + ? ?DbgValues.clear();
>>>> + ?}
>>>> +
>>>> + ?bool empty() const {
>>>> + ? ?return DbgValues.empty();
>>>> ?}
>>>> - ?SDDbgValue *getSDDbgValue(const SDNode *Node) {
>>>> +
>>>> + ?SmallVector &getSDDbgValues(const SDNode *Node) {
>>>> ? ?return DbgVblMap[Node];
>>>> ?}
>>>> - ?typedef SmallVector::iterator ConstDbgIterator;
>>>> - ?ConstDbgIterator DbgConstBegin() { return DbgConstMap.begin(); }
>>>> - ?ConstDbgIterator DbgConstEnd() { return DbgConstMap.end(); }
>>>> +
>>>> + ?typedef SmallVector::iterator DbgIterator;
>>>> + ?DbgIterator DbgBegin() { return DbgValues.begin(); }
>>>> + ?DbgIterator DbgEnd() ? { return DbgValues.end(); }
>>>> };
>>>>
>>>> enum CombineLevel {
>>>> @@ -871,19 +869,21 @@
>>>> ?/// GetOrdering - Get the order for the SDNode.
>>>> ?unsigned GetOrdering(const SDNode *SD) const;
>>>>
>>>> - ?/// AssignDbgInfo - Assign debug info to the SDNode.
>>>> - ?void AssignDbgInfo(SDNode *SD, SDDbgValue *db);
>>>> + ?/// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means the
>>>> + ?/// value is produced by SD.
>>>> + ?void AddDbgValue(SDDbgValue *DB, SDNode *SD = 0);
>>>>
>>>> - ?/// RememberDbgInfo - Remember debug info with no associated SDNode.
>>>> - ?void RememberDbgInfo(SDDbgValue *db);
>>>> + ?/// GetDbgValues - Get the debug values which reference the given SDNode.
>>>> + ?SmallVector &GetDbgValues(const SDNode* SD) {
>>>> + ? ?return DbgInfo->getSDDbgValues(SD);
>>>> + ?}
>>>>
>>>> - ?/// GetDbgInfo - Get the debug info for the SDNode.
>>>> - ?SDDbgValue *GetDbgInfo(const SDNode* SD);
>>>> + ?/// hasDebugValues - Return true if there are any SDDbgValue nodes associated
>>>> + ?/// with this SelectionDAG.
>>>> + ?bool hasDebugValues() const { return !DbgInfo->empty(); }
>>>>
>>>> - ?SDDbgInfo::ConstDbgIterator DbgConstBegin() {
>>>> - ? ?return DbgInfo->DbgConstBegin();
>>>> - ?}
>>>> - ?SDDbgInfo::ConstDbgIterator DbgConstEnd() { return DbgInfo->DbgConstEnd(); }
>>>> + ?SDDbgInfo::DbgIterator DbgBegin() { return DbgInfo->DbgBegin(); }
>>>> + ?SDDbgInfo::DbgIterator DbgEnd() ? { return DbgInfo->DbgEnd(); }
>>>>
>>>> ?void dump() const;
>>>>
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=99469&r1=99468&r2=99469&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Wed Mar 24 20:38:16 2010
>>>> @@ -264,7 +264,8 @@
>>>> InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned IIOpNum,
>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const TargetInstrDesc *II,
>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DenseMap &VRBaseMap) {
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DenseMap &VRBaseMap,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool IsDebug) {
>>>> ?assert(Op.getValueType() != MVT::Other &&
>>>> ? ? ? ? Op.getValueType() != MVT::Flag &&
>>>> ? ? ? ? "Chain and flag operands should occur at end of operand list!");
>>>> @@ -295,7 +296,11 @@
>>>> ? ?}
>>>> ?}
>>>>
>>>> - ?MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
>>>> + ?MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? false/*isImp*/, false/*isKill*/,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? false/*isDead*/, false/*isUndef*/,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? false/*isEarlyClobber*/,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0/*SubReg*/, IsDebug));
>>>> }
>>>>
>>>> /// AddOperand - Add the specified operand to the specified machine instr. ?II
>>>> @@ -305,9 +310,10 @@
>>>> void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned IIOpNum,
>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const TargetInstrDesc *II,
>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DenseMap &VRBaseMap) {
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DenseMap &VRBaseMap,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool IsDebug) {
>>>> ?if (Op.isMachineOpcode()) {
>>>> - ? ?AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
>>>> + ? ?AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug);
>>>> ?} else if (ConstantSDNode *C = dyn_cast(Op)) {
>>>> ? ?MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
>>>> ?} else if (ConstantFPSDNode *F = dyn_cast(Op)) {
>>>> @@ -356,7 +362,7 @@
>>>> ? ?assert(Op.getValueType() != MVT::Other &&
>>>> ? ? ? ? ? Op.getValueType() != MVT::Flag &&
>>>> ? ? ? ? ? "Chain and flag operands should occur at end of operand list!");
>>>> - ? ?AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
>>>> + ? ?AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug);
>>>> ?}
>>>> }
>>>>
>>>> @@ -498,75 +504,48 @@
>>>> ?assert(isNew && "Node emitted out of order - early");
>>>> }
>>>>
>>>> -/// EmitDbgValue - Generate any debug info that refers to this Node. ?Constant
>>>> -/// dbg_value is not handled here.
>>>> -void
>>>> -InstrEmitter::EmitDbgValue(SDNode *Node,
>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? DenseMap &VRBaseMap,
>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? SDDbgValue *sd) {
>>>> - ?if (!Node->getHasDebugValue())
>>>> - ? ?return;
>>>> - ?if (!sd)
>>>> - ? ?return;
>>>> - ?assert(sd->getKind() == SDDbgValue::SDNODE);
>>>> - ?unsigned VReg = getVR(SDValue(sd->getSDNode(), sd->getResNo()), VRBaseMap);
>>>> - ?const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
>>>> - ?DebugLoc DL = sd->getDebugLoc();
>>>> - ?MachineInstr *MI;
>>>> - ?if (VReg) {
>>>> - ? ?MI = BuildMI(*MF, DL, II).addReg(VReg, RegState::Debug).
>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?addImm(sd->getOffset()).
>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?addMetadata(sd->getMDPtr());
>>>> - ?} else {
>>>> - ? ?// Insert an Undef so we can see what we dropped.
>>>> - ? ?MI = BuildMI(*MF, DL, II).addReg(0U).addImm(sd->getOffset()).
>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?addMetadata(sd->getMDPtr());
>>>> - ?}
>>>> - ?MBB->insert(InsertPos, MI);
>>>> -}
>>>> -
>>>> -/// EmitDbgValue - Generate debug info that does not refer to a SDNode.
>>>> -void
>>>> -InstrEmitter::EmitDbgValue(SDDbgValue *sd,
>>>> +/// EmitDbgValue - Generate machine instruction for a dbg_value node.
>>>> +///
>>>> +MachineInstr *InstrEmitter::EmitDbgValue(SDDbgValue *SD,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineBasicBlock *InsertBB,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DenseMap &VRBaseMap,
>>>> ? ? ? ? ? ? ? ? ? ? ? ? DenseMap *EM) {
>>>> - ?if (!sd)
>>>> - ? ?return;
>>>> + ?uint64_t Offset = SD->getOffset();
>>>> + ?MDNode* MDPtr = SD->getMDPtr();
>>>> + ?DebugLoc DL = SD->getDebugLoc();
>>>> +
>>>> ?const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
>>>> - ?uint64_t Offset = sd->getOffset();
>>>> - ?MDNode* mdPtr = sd->getMDPtr();
>>>> - ?SDDbgValue::DbgValueKind kind = sd->getKind();
>>>> - ?DebugLoc DL = sd->getDebugLoc();
>>>> - ?MachineInstr* MI;
>>>> - ?if (kind == SDDbgValue::CONST) {
>>>> - ? ?Value *V = sd->getConst();
>>>> + ?MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
>>>> + ?if (SD->getKind() == SDDbgValue::SDNODE) {
>>>> + ? ?AddOperand(&*MIB, SDValue(SD->getSDNode(), SD->getResNo()),
>>>> + ? ? ? ? ? ? ? (*MIB).getNumOperands(), &II, VRBaseMap, true /*IsDebug*/);
>>>> + ?} else if (SD->getKind() == SDDbgValue::CONST) {
>>>> + ? ?Value *V = SD->getConst();
>>>> ? ?if (ConstantInt *CI = dyn_cast(V)) {
>>>> - ? ? ?MI = BuildMI(*MF, DL, II).addImm(CI->getZExtValue()).
>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? addImm(Offset).addMetadata(mdPtr);
>>>> + ? ? ?MIB.addImm(CI->getSExtValue());
>>>> ? ?} else if (ConstantFP *CF = dyn_cast(V)) {
>>>> - ? ? ?MI = BuildMI(*MF, DL, II).addFPImm(CF).
>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? addImm(Offset).addMetadata(mdPtr);
>>>> + ? ? ?MIB.addFPImm(CF);
>>>> ? ?} else {
>>>> ? ? ?// Could be an Undef. ?In any case insert an Undef so we can see what we
>>>> ? ? ?// dropped.
>>>> - ? ? ?MI = BuildMI(*MF, DL, II).addReg(0U).
>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? addImm(Offset).addMetadata(mdPtr);
>>>> + ? ? ?MIB.addReg(0U);
>>>> ? ?}
>>>> - ?} else if (kind == SDDbgValue::FRAMEIX) {
>>>> - ? ?unsigned FrameIx = sd->getFrameIx();
>>>> + ?} else if (SD->getKind() == SDDbgValue::FRAMEIX) {
>>>> + ? ?unsigned FrameIx = SD->getFrameIx();
>>>> ? ?// Stack address; this needs to be lowered in target-dependent fashion.
>>>> ? ?// FIXME test that the target supports this somehow; if not emit Undef.
>>>> ? ?// Create a pseudo for EmitInstrWithCustomInserter's consumption.
>>>> - ? ?MI = BuildMI(*MF, DL, II).addImm(FrameIx).
>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? addImm(Offset).addMetadata(mdPtr);
>>>> - ? ?MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
>>>> - ? ?InsertPos = MBB->end();
>>>> - ? ?return;
>>>> + ? ?MIB.addImm(FrameIx).addImm(Offset).addMetadata(MDPtr);
>>>> + ? ?abort();
>>>> + ? ?TLI->EmitInstrWithCustomInserter(&*MIB, InsertBB, EM);
>>>> + ? ?return 0;
>>>> ?} else {
>>>> ? ?// Insert an Undef so we can see what we dropped.
>>>> - ? ?MI = BuildMI(*MF, DL, II).addReg(0U).
>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? addImm(Offset).addMetadata(mdPtr);
>>>> + ? ?MIB.addReg(0U);
>>>> ?}
>>>> - ?MBB->insert(InsertPos, MI);
>>>> +
>>>> + ?MIB.addImm(Offset).addMetadata(MDPtr);
>>>> + ?return &*MIB;
>>>> }
>>>>
>>>> /// EmitNode - Generate machine code for a node and needed dependencies.
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h?rev=99469&r1=99468&r2=99469&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h Wed Mar 24 20:38:16 2010
>>>> @@ -64,7 +64,8 @@
>>>> ?void AddRegisterOperand(MachineInstr *MI, SDValue Op,
>>>> ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned IIOpNum,
>>>> ? ? ? ? ? ? ? ? ? ? ? ? ?const TargetInstrDesc *II,
>>>> - ? ? ? ? ? ? ? ? ? ? ? ? ?DenseMap &VRBaseMap);
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ?DenseMap &VRBaseMap,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ?bool IsDebug = false);
>>>>
>>>> ?/// AddOperand - Add the specified operand to the specified machine instr. ?II
>>>> ?/// specifies the instruction information for the node, and IIOpNum is the
>>>> @@ -73,7 +74,8 @@
>>>> ?void AddOperand(MachineInstr *MI, SDValue Op,
>>>> ? ? ? ? ? ? ? ? ?unsigned IIOpNum,
>>>> ? ? ? ? ? ? ? ? ?const TargetInstrDesc *II,
>>>> - ? ? ? ? ? ? ? ? ?DenseMap &VRBaseMap);
>>>> + ? ? ? ? ? ? ? ? ?DenseMap &VRBaseMap,
>>>> + ? ? ? ? ? ? ? ? ?bool IsDebug = false);
>>>>
>>>> ?/// EmitSubregNode - Generate machine code for subreg nodes.
>>>> ?///
>>>> @@ -98,16 +100,12 @@
>>>> ?/// MachineInstr.
>>>> ?static unsigned CountOperands(SDNode *Node);
>>>>
>>>> - ?/// EmitDbgValue - Generate any debug info that refers to this Node. ?Constant
>>>> - ?/// dbg_value is not handled here.
>>>> - ?void EmitDbgValue(SDNode *Node,
>>>> - ? ? ? ? ? ? ? ? ? ?DenseMap &VRBaseMap,
>>>> - ? ? ? ? ? ? ? ? ? ?SDDbgValue* sd);
>>>> -
>>>> -
>>>> - ?/// EmitDbgValue - Generate a constant DBG_VALUE. ?No node is involved.
>>>> - ?void EmitDbgValue(SDDbgValue* sd,
>>>> - ? ? ? ? ? ? ? ?DenseMap *EM);
>>>> + ?/// EmitDbgValue - Generate machine instruction for a dbg_value node.
>>>> + ?///
>>>> + ?MachineInstr *EmitDbgValue(SDDbgValue *SD,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock *InsertBB,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ?DenseMap &VRBaseMap,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ?DenseMap *EM);
>>>>
>>>> ?/// EmitNode - Generate machine code for a node and needed dependencies.
>>>> ?///
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h?rev=99469&r1=99468&r2=99469&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h Wed Mar 24 20:38:16 2010
>>>> @@ -47,10 +47,12 @@
>>>> ?uint64_t Offset;
>>>> ?DebugLoc DL;
>>>> ?unsigned Order;
>>>> + ?bool Invalid;
>>>> public:
>>>> ?// Constructor for non-constants.
>>>> ?SDDbgValue(MDNode *mdP, SDNode *N, unsigned R, uint64_t off, DebugLoc dl,
>>>> - ? ? ? ? ? ? unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O) {
>>>> + ? ? ? ? ? ? unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? Invalid(false) {
>>>> ? ?kind = SDNODE;
>>>> ? ?u.s.Node = N;
>>>> ? ?u.s.ResNo = R;
>>>> @@ -97,6 +99,12 @@
>>>> ?// Returns the SDNodeOrder. ?This is the order of the preceding node in the
>>>> ?// input.
>>>> ?unsigned getOrder() { return Order; }
>>>> +
>>>> + ?// setIsInvalidated / isInvalidated - Setter / getter of the "Invalidated"
>>>> + ?// property. A SDDbgValue is invalid if the SDNode that produces the value is
>>>> + ?// deleted.
>>>> + ?void setIsInvalidated() { Invalid = true; }
>>>> + ?bool isInvalidated() { return Invalid; }
>>>> };
>>>>
>>>> } // end llvm namespace
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=99469&r1=99468&r2=99469&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Wed Mar 24 20:38:16 2010
>>>> @@ -23,6 +23,7 @@
>>>> #include "llvm/Target/TargetSubtarget.h"
>>>> #include "llvm/ADT/DenseMap.h"
>>>> #include "llvm/ADT/SmallPtrSet.h"
>>>> +#include "llvm/ADT/SmallSet.h"
>>>> #include "llvm/ADT/SmallVector.h"
>>>> #include "llvm/ADT/Statistic.h"
>>>> #include "llvm/Support/Debug.h"
>>>> @@ -407,19 +408,67 @@
>>>> ?}
>>>> }
>>>>
>>>> +namespace {
>>>> + ?struct OrderSorter {
>>>> + ? ?bool operator()(const std::pair &A,
>>>> + ? ? ? ? ? ? ? ? ? ?const std::pair &B) {
>>>> + ? ? ?return A.first < B.first;
>>>> + ? ?}
>>>> + ?};
>>>> +}
>>>> +
>>>> +// ProcessSourceNode - Process nodes with source order numbers. These are added
>>>> +// to a vector which EmitSchedule use to determine how to insert dbg_value
>>>> +// instructions in the right order.
>>>> +static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? InstrEmitter &Emitter,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? DenseMap *EM,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? DenseMap &VRBaseMap,
>>>> + ? ? ? ? ? ? ? ? ? ?SmallVector, 32> &Orders,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? SmallSet &Seen) {
>>>> + ?unsigned Order = DAG->GetOrdering(N);
>>>> + ?if (!Order || !Seen.insert(Order))
>>>> + ? ?return;
>>>> +
>>>> + ?MachineBasicBlock *BB = Emitter.getBlock();
>>>> + ?if (BB->empty() || BB->back().isPHI()) {
>>>> + ? ?// Did not insert any instruction.
>>>> + ? ?Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
>>>> + ? ?return;
>>>> + ?}
>>>> +
>>>> + ?Orders.push_back(std::make_pair(Order, &BB->back()));
>>>> + ?if (!N->getHasDebugValue())
>>>> + ? ?return;
>>>> + ?// Opportunistically insert immediate dbg_value uses, i.e. those with source
>>>> + ?// order number right after the N.
>>>> + ?MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
>>>> + ?SmallVector &DVs = DAG->GetDbgValues(N);
>>>> + ?for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
>>>> + ? ?if (DVs[i]->isInvalidated())
>>>> + ? ? ?continue;
>>>> + ? ?unsigned DVOrder = DVs[i]->getOrder();
>>>> + ? ?if (DVOrder == ++Order) {
>>>> + ? ? ?// FIXME: If the source node with next higher order is scheduled before
>>>> + ? ? ?// this could end up generating funky debug info.
>>>> + ? ? ?MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], BB, VRBaseMap, EM);
>>>> + ? ? ?Orders.push_back(std::make_pair(DVOrder, DbgMI));
>>>> + ? ? ?BB->insert(InsertPos, DbgMI);
>>>> + ? ? ?DVs[i]->setIsInvalidated();
>>>> + ? ?}
>>>> + ?}
>>>> +}
>>>> +
>>>> +
>>>> /// EmitSchedule - Emit the machine code in scheduled order.
>>>> MachineBasicBlock *ScheduleDAGSDNodes::
>>>> EmitSchedule(DenseMap *EM) {
>>>> ?InstrEmitter Emitter(BB, InsertPos);
>>>> ?DenseMap VRBaseMap;
>>>> ?DenseMap CopyVRBaseMap;
>>>> -
>>>> - ?// For now, any constant debug info nodes go at the beginning.
>>>> - ?for (SDDbgInfo::ConstDbgIterator I = DAG->DbgConstBegin(),
>>>> - ? ? ? E = DAG->DbgConstEnd(); I!=E; I++) {
>>>> - ? ?Emitter.EmitDbgValue(*I, EM);
>>>> - ? ?delete *I;
>>>> - ?}
>>>> + ?SmallVector, 32> Orders;
>>>> + ?SmallSet Seen;
>>>> + ?bool HasDbg = DAG->hasDebugValues();
>>>>
>>>> ?for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
>>>> ? ?SUnit *SU = Sequence[i];
>>>> @@ -442,22 +491,72 @@
>>>> ? ? ? ? N = N->getFlaggedNode())
>>>> ? ? ?FlaggedNodes.push_back(N);
>>>> ? ?while (!FlaggedNodes.empty()) {
>>>> + ? ? ?SDNode *N = FlaggedNodes.back();
>>>> ? ? ?Emitter.EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,
>>>> ? ? ? ? ? ? ? ? ? ? ? VRBaseMap, EM);
>>>> - ? ? ?if (FlaggedNodes.back()->getHasDebugValue())
>>>> - ? ? ? ?if (SDDbgValue *sd = DAG->GetDbgInfo(FlaggedNodes.back())) {
>>>> - ? ? ? ? ?Emitter.EmitDbgValue(FlaggedNodes.back(), VRBaseMap, sd);
>>>> - ? ? ? ? ?delete sd;
>>>> - ? ? ? ?}
>>>> + ? ? ?// Remember the the source order of the inserted instruction.
>>>> + ? ? ?if (HasDbg)
>>>> + ? ? ? ?ProcessSourceNode(N, DAG, Emitter, EM, VRBaseMap, Orders, Seen);
>>>> ? ? ?FlaggedNodes.pop_back();
>>>> ? ?}
>>>> ? ?Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
>>>> ? ? ? ? ? ? ? ? ? ? VRBaseMap, EM);
>>>> - ? ?if (SU->getNode()->getHasDebugValue())
>>>> - ? ? ?if (SDDbgValue *sd = DAG->GetDbgInfo(SU->getNode())) {
>>>> - ? ? ? ?Emitter.EmitDbgValue(SU->getNode(), VRBaseMap, sd);
>>>> - ? ? ? ?delete sd;
>>>> + ? ?// Remember the the source order of the inserted instruction.
>>>> + ? ?if (HasDbg)
>>>> + ? ? ?ProcessSourceNode(SU->getNode(), DAG, Emitter, EM, VRBaseMap, Orders,
>>>> + ? ? ? ? ? ? ? ? ? ? ? ?Seen);
>>>> + ?}
>>>> +
>>>> + ?// Insert all the dbg_value which have not already been inserted in source
>>>> + ?// order sequence.
>>>> + ?if (HasDbg) {
>>>> + ? ?MachineBasicBlock::iterator BBBegin = BB->empty() ? BB->end() : BB->begin();
>>>> + ? ?while (BBBegin != BB->end() && BBBegin->isPHI())
>>>> + ? ? ?++BBBegin;
>>>> +
>>>> + ? ?// Sort the source order instructions and use the order to insert debug
>>>> + ? ?// values.
>>>> + ? ?std::sort(Orders.begin(), Orders.end(), OrderSorter());
>>>> +
>>>> + ? ?SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
>>>> + ? ?SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
>>>> + ? ?// Now emit the rest according to source order.
>>>> + ? ?unsigned LastOrder = 0;
>>>> + ? ?MachineInstr *LastMI = 0;
>>>> + ? ?for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
>>>> + ? ? ?unsigned Order = Orders[i].first;
>>>> + ? ? ?MachineInstr *MI = Orders[i].second;
>>>> + ? ? ?// Insert all SDDbgValue's whose order(s) are before "Order".
>>>> + ? ? ?if (!MI)
>>>> + ? ? ? ?continue;
>>>> + ? ? ?MachineBasicBlock *MIBB = MI->getParent();
>>>> + ? ? ?for (; DI != DE &&
>>>> + ? ? ? ? ? ? (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
>>>> + ? ? ? ?if ((*DI)->isInvalidated())
>>>> + ? ? ? ? ?continue;
>>>> + ? ? ? ?MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, MIBB, VRBaseMap, EM);
>>>> + ? ? ? ?if (!LastOrder)
>>>> + ? ? ? ? ?// Insert to start of the BB (after PHIs).
>>>> + ? ? ? ? ?BB->insert(BBBegin, DbgMI);
>>>> + ? ? ? ?else {
>>>> + ? ? ? ? ?MachineBasicBlock::iterator Pos = MI;
>>>> + ? ? ? ? ?MIBB->insert(llvm::next(Pos), DbgMI);
>>>> + ? ? ? ?}
>>>> ? ? ?}
>>>> + ? ? ?LastOrder = Order;
>>>> + ? ? ?LastMI = MI;
>>>> + ? ?}
>>>> + ? ?// Add trailing DbgValue's before the terminator. FIXME: May want to add
>>>> + ? ?// some of them before one or more conditional branches?
>>>> + ? ?while (DI != DE) {
>>>> + ? ? ?MachineBasicBlock *InsertBB = Emitter.getBlock();
>>>> + ? ? ?MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator();
>>>> + ? ? ?if (!(*DI)->isInvalidated()) {
>>>> + ? ? ? ?MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, InsertBB, VRBaseMap, EM);
>>>> + ? ? ? ?InsertBB->insert(Pos, DbgMI);
>>>> + ? ? ?}
>>>> + ? ? ?++DI;
>>>> + ? ?}
>>>> ?}
>>>>
>>>> ?BB = Emitter.getBlock();
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=99469&r1=99468&r2=99469&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Mar 24 20:38:16 2010
>>>> @@ -598,8 +598,10 @@
>>>> ?// Remove the ordering of this node.
>>>> ?Ordering->remove(N);
>>>>
>>>> - ?// And its entry in the debug info table, if any.
>>>> - ?DbgInfo->remove(N);
>>>> + ?// If any of the SDDbgValue nodes refer to this SDNode, invalidate them.
>>>> + ?SmallVector &DbgVals = DbgInfo->getSDDbgValues(N);
>>>> + ?for (unsigned i = 0, e = DbgVals.size(); i != e; ++i)
>>>> + ? ?DbgVals[i]->setIsInvalidated();
>>>> }
>>>>
>>>> /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
>>>> @@ -811,6 +813,7 @@
>>>> SelectionDAG::~SelectionDAG() {
>>>> ?allnodes_clear();
>>>> ?delete Ordering;
>>>> + ?DbgInfo->clear();
>>>> ?delete DbgInfo;
>>>> }
>>>>
>>>> @@ -5241,24 +5244,12 @@
>>>> ?return Ordering->getOrder(SD);
>>>> }
>>>>
>>>> -/// AssignDbgInfo - Assign debug info to the SDNode.
>>>> -void SelectionDAG::AssignDbgInfo(SDNode* SD, SDDbgValue* db) {
>>>> - ?assert(SD && "Trying to assign dbg info to a null node!");
>>>> - ?DbgInfo->add(SD, db);
>>>> - ?SD->setHasDebugValue(true);
>>>> -}
>>>> -
>>>> -/// RememberDbgInfo - Remember debug info which is not assigned to an SDNode.
>>>> -void SelectionDAG::RememberDbgInfo(SDDbgValue* db) {
>>>> - ?DbgInfo->add(db);
>>>> -}
>>>> -
>>>> -/// GetDbgInfo - Get the debug info, if any, for the SDNode.
>>>> -SDDbgValue* SelectionDAG::GetDbgInfo(const SDNode *SD) {
>>>> - ?assert(SD && "Trying to get the order of a null node!");
>>>> - ?if (SD->getHasDebugValue())
>>>> - ? ?return DbgInfo->getSDDbgValue(SD);
>>>> - ?return 0;
>>>> +/// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means the
>>>> +/// value is produced by SD.
>>>> +void SelectionDAG::AddDbgValue(SDDbgValue *DB, SDNode *SD) {
>>>> + ?DbgInfo->add(DB, SD);
>>>> + ?if (SD)
>>>> + ? ?SD->setHasDebugValue(true);
>>>> }
>>>>
>>>> //===----------------------------------------------------------------------===//
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=99469&r1=99468&r2=99469&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Mar 24 20:38:16 2010
>>>> @@ -3825,20 +3825,20 @@
>>>> ? ?++SDNodeOrder;
>>>> ? ?if (isa(V) || isa(V)) {
>>>> ? ? ?SDDbgValue* dv = new SDDbgValue(Variable, V, Offset, dl, SDNodeOrder);
>>>> - ? ? ?DAG.RememberDbgInfo(dv);
>>>> + ? ? ?DAG.AddDbgValue(dv);
>>>> ? ?} else {
>>>> ? ? ?SDValue &N = NodeMap[V];
>>>> ? ? ?if (N.getNode()) {
>>>> ? ? ? ?SDDbgValue *dv = new SDDbgValue(Variable, N.getNode(),
>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?N.getResNo(), Offset, dl, SDNodeOrder);
>>>> - ? ? ? ?DAG.AssignDbgInfo(N.getNode(), dv);
>>>> + ? ? ? ?DAG.AddDbgValue(dv, N.getNode());
>>>> ? ? ?} else {
>>>> ? ? ? ?// We may expand this to cover more cases. ?One case where we have no
>>>> ? ? ? ?// data available is an unreferenced parameter; we need this fallback.
>>>> ? ? ? ?SDDbgValue* dv = new SDDbgValue(Variable,
>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?UndefValue::get(V->getType()),
>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Offset, dl, SDNodeOrder);
>>>> - ? ? ? ?DAG.RememberDbgInfo(dv);
>>>> + ? ? ? ?DAG.AddDbgValue(dv);
>>>> ? ? ?}
>>>> ? ?}
>>>>
>>>>
>>>>
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
From benny.kra at googlemail.com Mon Mar 29 16:13:41 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Mon, 29 Mar 2010 21:13:41 -0000
Subject: [llvm-commits] [llvm] r99838 - in /llvm/trunk:
include/llvm/Support/MathExtras.h lib/Target/Blackfin/BlackfinInstrInfo.td
lib/Target/Blackfin/BlackfinRegisterInfo.cpp
lib/Target/CellSPU/SPUISelDAGToDAG.cpp lib/Target/MSIL/MSILWriter.cpp
lib/Target/PowerPC/PPCBranchSelector.cpp
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
lib/Target/PowerPC/PPCRegisterInfo.cpp lib/Target/X86/X86FastISel.cpp
lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20100329211342.390E62A6C12C@llvm.org>
Author: d0k
Date: Mon Mar 29 16:13:41 2010
New Revision: 99838
URL: http://llvm.org/viewvc/llvm-project?rev=99838&view=rev
Log:
Make isInt?? and isUint?? template specializations of the generic versions. This
makes calls a little bit more consistent and allows easy removal of the
specializations in the future. Convert all callers to the templated functions.
Modified:
llvm/trunk/include/llvm/Support/MathExtras.h
llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td
llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/lib/Target/X86/X86FastISel.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/include/llvm/Support/MathExtras.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/MathExtras.h?rev=99838&r1=99837&r2=99838&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/MathExtras.h (original)
+++ llvm/trunk/include/llvm/Support/MathExtras.h Mon Mar 29 16:13:41 2010
@@ -32,35 +32,43 @@
return static_cast(Value);
}
-/// is?Type - these functions produce optimal testing for integer data types.
-inline bool isInt8 (int64_t Value) {
- return static_cast(Value) == Value;
-}
-inline bool isUInt8 (int64_t Value) {
- return static_cast(Value) == Value;
-}
-inline bool isInt16 (int64_t Value) {
- return static_cast(Value) == Value;
-}
-inline bool isUInt16(int64_t Value) {
- return static_cast(Value) == Value;
-}
-inline bool isInt32 (int64_t Value) {
- return static_cast(Value) == Value;
-}
-inline bool isUInt32(int64_t Value) {
- return static_cast(Value) == Value;
-}
-
+/// isInt - Checks if an integer fits into the given bit width.
template
inline bool isInt(int64_t x) {
return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));
}
+// Template specializations to get better code for common cases.
+template<>
+inline bool isInt<8>(int64_t x) {
+ return static_cast(x) == x;
+}
+template<>
+inline bool isInt<16>(int64_t x) {
+ return static_cast(x) == x;
+}
+template<>
+inline bool isInt<32>(int64_t x) {
+ return static_cast(x) == x;
+}
+/// isUInt - Checks if an unsigned integer fits into the given bit width.
template
-inline bool isUint(uint64_t x) {
+inline bool isUInt(uint64_t x) {
return N >= 64 || x < (UINT64_C(1)<
+inline bool isUInt<8>(uint64_t x) {
+ return static_cast(x) == x;
+}
+template<>
+inline bool isUInt<16>(uint64_t x) {
+ return static_cast(x) == x;
+}
+template<>
+inline bool isUInt<32>(uint64_t x) {
+ return static_cast(x) == x;
+}
/// isMask_32 - This function returns true if the argument is a sequence of ones
/// starting at the least significant bit with the remainder zero (32 bit
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td?rev=99838&r1=99837&r2=99838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td Mon Mar 29 16:13:41 2010
@@ -65,23 +65,23 @@
//===----------------------------------------------------------------------===//
def imm3 : PatLeaf<(imm), [{return isInt<3>(N->getSExtValue());}]>;
-def uimm3 : PatLeaf<(imm), [{return isUint<3>(N->getZExtValue());}]>;
-def uimm4 : PatLeaf<(imm), [{return isUint<4>(N->getZExtValue());}]>;
-def uimm5 : PatLeaf<(imm), [{return isUint<5>(N->getZExtValue());}]>;
+def uimm3 : PatLeaf<(imm), [{return isUInt<3>(N->getZExtValue());}]>;
+def uimm4 : PatLeaf<(imm), [{return isUInt<4>(N->getZExtValue());}]>;
+def uimm5 : PatLeaf<(imm), [{return isUInt<5>(N->getZExtValue());}]>;
def uimm5m2 : PatLeaf<(imm), [{
uint64_t value = N->getZExtValue();
- return value % 2 == 0 && isUint<5>(value);
+ return value % 2 == 0 && isUInt<5>(value);
}]>;
def uimm6m4 : PatLeaf<(imm), [{
uint64_t value = N->getZExtValue();
- return value % 4 == 0 && isUint<6>(value);
+ return value % 4 == 0 && isUInt<6>(value);
}]>;
def imm7 : PatLeaf<(imm), [{return isInt<7>(N->getSExtValue());}]>;
def imm16 : PatLeaf<(imm), [{return isInt<16>(N->getSExtValue());}]>;
-def uimm16 : PatLeaf<(imm), [{return isUint<16>(N->getZExtValue());}]>;
+def uimm16 : PatLeaf<(imm), [{return isUInt<16>(N->getZExtValue());}]>;
def ximm16 : PatLeaf<(imm), [{
int64_t value = N->getSExtValue();
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp?rev=99838&r1=99837&r2=99838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp Mon Mar 29 16:13:41 2010
@@ -164,7 +164,7 @@
return;
}
- if (isUint<16>(value)) {
+ if (isUInt<16>(value)) {
BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
return;
}
@@ -255,13 +255,13 @@
assert(FIPos==1 && "Bad frame index operand");
MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
MI.getOperand(FIPos+1).setImm(Offset);
- if (isUint<6>(Offset)) {
+ if (isUInt<6>(Offset)) {
MI.setDesc(TII.get(isStore
? BF::STORE32p_uimm6m4
: BF::LOAD32p_uimm6m4));
return 0;
}
- if (BaseReg == BF::FP && isUint<7>(-Offset)) {
+ if (BaseReg == BF::FP && isUInt<7>(-Offset)) {
MI.setDesc(TII.get(isStore
? BF::STORE32fp_nimm7m4
: BF::LOAD32fp_nimm7m4));
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=99838&r1=99837&r2=99838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Mon Mar 29 16:13:41 2010
@@ -58,7 +58,7 @@
bool
isI32IntU10Immediate(ConstantSDNode *CN)
{
- return isUint<10>(CN->getSExtValue());
+ return isUInt<10>(CN->getSExtValue());
}
//! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
@@ -80,7 +80,7 @@
bool
isI16IntU10Immediate(ConstantSDNode *CN)
{
- return isUint<10>((short) CN->getZExtValue());
+ return isUInt<10>((short) CN->getZExtValue());
}
//! SDNode predicate for i16 sign-extended, 10-bit immediate values
Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=99838&r1=99837&r2=99838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
+++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Mon Mar 29 16:13:41 2010
@@ -424,7 +424,7 @@
case Module::Pointer32:
printSimpleInstruction("ldc.i4",utostr(N).c_str());
// FIXME: Need overflow test?
- if (!isUInt32(N)) {
+ if (!isUInt<32>(N)) {
errs() << "Value = " << utostr(N) << '\n';
llvm_unreachable("32-bit pointer overflowed");
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp?rev=99838&r1=99837&r2=99838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp Mon Mar 29 16:13:41 2010
@@ -130,7 +130,7 @@
}
// If this branch is in range, ignore it.
- if (isInt16(BranchSize)) {
+ if (isInt<16>(BranchSize)) {
MBBStartOffset += 4;
continue;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=99838&r1=99837&r2=99838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Mar 29 16:13:41 2010
@@ -470,11 +470,11 @@
if (CC == ISD::SETEQ || CC == ISD::SETNE) {
if (isInt32Immediate(RHS, Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
- if (isUInt16(Imm))
+ if (isUInt<16>(Imm))
return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
- if (isInt16((int)Imm))
+ if (isInt<16>((int)Imm))
return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
@@ -494,7 +494,7 @@
}
Opc = PPC::CMPLW;
} else if (ISD::isUnsignedIntSetCC(CC)) {
- if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
+ if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLW;
@@ -511,11 +511,11 @@
if (CC == ISD::SETEQ || CC == ISD::SETNE) {
if (isInt64Immediate(RHS.getNode(), Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
- if (isUInt16(Imm))
+ if (isUInt<16>(Imm))
return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
- if (isInt16(Imm))
+ if (isInt<16>(Imm))
return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
@@ -528,7 +528,7 @@
// xoris r0,r3,0x1234
// cmpldi cr0,r0,0x5678
// beq cr0,L6
- if (isUInt32(Imm)) {
+ if (isUInt<32>(Imm)) {
SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
getI64Imm(Imm >> 16)), 0);
return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
@@ -537,7 +537,7 @@
}
Opc = PPC::CMPLD;
} else if (ISD::isUnsignedIntSetCC(CC)) {
- if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
+ if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
getI64Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLD;
@@ -761,12 +761,12 @@
unsigned Shift = 0;
// If it can't be represented as a 32 bit value.
- if (!isInt32(Imm)) {
+ if (!isInt<32>(Imm)) {
Shift = CountTrailingZeros_64(Imm);
int64_t ImmSh = static_cast(Imm) >> Shift;
// If the shifted value fits 32 bits.
- if (isInt32(ImmSh)) {
+ if (isInt<32>(ImmSh)) {
// Go with the shifted value.
Imm = ImmSh;
} else {
@@ -785,7 +785,7 @@
unsigned Hi = (Imm >> 16) & 0xFFFF;
// Simple value.
- if (isInt16(Imm)) {
+ if (isInt<16>(Imm)) {
// Just the Lo bits.
Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
} else if (Lo) {
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=99838&r1=99837&r2=99838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Mar 29 16:13:41 2010
@@ -512,7 +512,7 @@
MachineInstr *MI = I;
DebugLoc dl = MI->getDebugLoc();
- if (isInt16(CalleeAmt)) {
+ if (isInt<16>(CalleeAmt)) {
BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
addImm(CalleeAmt);
} else {
@@ -596,7 +596,7 @@
else
Reg = PPC::R0;
- if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
+ if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
.addReg(PPC::R31)
.addImm(FrameSize);
@@ -798,7 +798,7 @@
// clear can be encoded. This is extremely uncommon, because normally you
// only "std" to a stack slot that is at least 4-byte aligned, but it can
// happen in invalid code.
- if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
+ if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
if (isIXAddr)
Offset >>= 2; // The actual encoded value has the low two bits zero.
MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
@@ -1375,8 +1375,9 @@
if (!isPPC64) {
// PPC32.
if (ALIGN_STACK && MaxAlign > TargetAlign) {
- assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
- assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
+ assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
+ "Invalid alignment!");
+ assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
.addReg(PPC::R1)
@@ -1390,7 +1391,7 @@
.addReg(PPC::R1)
.addReg(PPC::R1)
.addReg(PPC::R0);
- } else if (isInt16(NegFrameSize)) {
+ } else if (isInt<16>(NegFrameSize)) {
BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
.addReg(PPC::R1)
.addImm(NegFrameSize)
@@ -1408,8 +1409,9 @@
}
} else { // PPC64.
if (ALIGN_STACK && MaxAlign > TargetAlign) {
- assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
- assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
+ assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
+ "Invalid alignment!");
+ assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
.addReg(PPC::X1)
@@ -1422,7 +1424,7 @@
.addReg(PPC::X1)
.addReg(PPC::X1)
.addReg(PPC::X0);
- } else if (isInt16(NegFrameSize)) {
+ } else if (isInt<16>(NegFrameSize)) {
BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
.addReg(PPC::X1)
.addImm(NegFrameSize / 4)
@@ -1591,7 +1593,7 @@
// enabled (=> hasFastCall()==true) the fastcc call might contain a tail
// call which invalidates the stack pointer value in SP(0). So we use the
// value of R31 in this case.
- if (FI->hasFastCall() && isInt16(FrameSize)) {
+ if (FI->hasFastCall() && isInt<16>(FrameSize)) {
assert(hasFP(MF) && "Expecting a valid the frame pointer.");
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
.addReg(PPC::R31).addImm(FrameSize);
@@ -1605,7 +1607,7 @@
.addReg(PPC::R1)
.addReg(PPC::R31)
.addReg(PPC::R0);
- } else if (isInt16(FrameSize) &&
+ } else if (isInt<16>(FrameSize) &&
(!ALIGN_STACK || TargetAlign >= MaxAlign) &&
!MFI->hasVarSizedObjects()) {
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
@@ -1615,7 +1617,7 @@
.addImm(0).addReg(PPC::R1);
}
} else {
- if (FI->hasFastCall() && isInt16(FrameSize)) {
+ if (FI->hasFastCall() && isInt<16>(FrameSize)) {
assert(hasFP(MF) && "Expecting a valid the frame pointer.");
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
.addReg(PPC::X31).addImm(FrameSize);
@@ -1629,7 +1631,7 @@
.addReg(PPC::X1)
.addReg(PPC::X31)
.addReg(PPC::X0);
- } else if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
+ } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign &&
!MFI->hasVarSizedObjects()) {
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
.addReg(PPC::X1).addImm(FrameSize);
@@ -1678,7 +1680,7 @@
unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
- if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) {
+ if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
.addReg(StackReg).addImm(CallerAllocatedAmt);
} else {
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=99838&r1=99837&r2=99838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Mon Mar 29 16:13:41 2010
@@ -383,7 +383,7 @@
if (ConstantInt *CI = dyn_cast(U->getOperand(1))) {
uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
// They have to fit in the 32-bit signed displacement field though.
- if (isInt32(Disp)) {
+ if (isInt<32>(Disp)) {
AM.Disp = (uint32_t)Disp;
return X86SelectAddress(U->getOperand(0), AM);
}
@@ -427,7 +427,7 @@
}
}
// Check for displacement overflow.
- if (!isInt32(Disp))
+ if (!isInt<32>(Disp))
break;
// Ok, the GEP indices were covered by constant-offset and scaled-index
// addressing. Update the address state and move on to examining the base.
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=99838&r1=99837&r2=99838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Mar 29 16:13:41 2010
@@ -2424,7 +2424,7 @@
bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
bool hasSymbolicDisplacement) {
// Offset should fit into 32 bit immediate field.
- if (!isInt32(Offset))
+ if (!isInt<32>(Offset))
return false;
// If we don't have a symbolic displacement - we don't have any extra
From sabre at nondot.org Mon Mar 29 16:24:52 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 29 Mar 2010 21:24:52 -0000
Subject: [llvm-commits] [llvm] r99839 - in /llvm/trunk:
include/llvm/Support/Timer.h lib/Support/Timer.cpp
Message-ID: <20100329212452.7FAD02A6C12C@llvm.org>
Author: lattner
Date: Mon Mar 29 16:24:52 2010
New Revision: 99839
URL: http://llvm.org/viewvc/llvm-project?rev=99839&view=rev
Log:
various timer fixes: move operator= out of line,
eliminate the per-timer lock (timers should be
externally locked if needed), the info-output-stream
can never be dbgs(), so drop the check. Make some
stuff private.
Modified:
llvm/trunk/include/llvm/Support/Timer.h
llvm/trunk/lib/Support/Timer.cpp
Modified: llvm/trunk/include/llvm/Support/Timer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Timer.h?rev=99839&r1=99838&r2=99839&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/Timer.h (original)
+++ llvm/trunk/include/llvm/Support/Timer.h Mon Mar 29 16:24:52 2010
@@ -40,54 +40,27 @@
double SystemTime; // System time elapsed
ssize_t MemUsed; // Memory allocated (in bytes)
size_t PeakMem; // Peak memory used
- size_t PeakMemBase; // Temporary for peak calculation...
- std::string Name; // The name of this time variable
+ size_t PeakMemBase; // Temporary for peak memory calculation.
+ std::string Name; // The name of this time variable.
bool Started; // Has this time variable ever been started?
TimerGroup *TG; // The TimerGroup this Timer is in.
- mutable sys::SmartMutex Lock; // Mutex for the contents of this Timer.
public:
explicit Timer(const std::string &N);
Timer(const std::string &N, TimerGroup &tg);
Timer(const Timer &T);
~Timer();
+private:
double getProcessTime() const { return UserTime+SystemTime; }
double getWallTime() const { return Elapsed; }
ssize_t getMemUsed() const { return MemUsed; }
size_t getPeakMem() const { return PeakMem; }
+public:
std::string getName() const { return Name; }
- const Timer &operator=(const Timer &T) {
- if (&T < this) {
- T.Lock.acquire();
- Lock.acquire();
- } else {
- Lock.acquire();
- T.Lock.acquire();
- }
-
- Elapsed = T.Elapsed;
- UserTime = T.UserTime;
- SystemTime = T.SystemTime;
- MemUsed = T.MemUsed;
- PeakMem = T.PeakMem;
- PeakMemBase = T.PeakMemBase;
- Name = T.Name;
- Started = T.Started;
- assert(TG == T.TG && "Can only assign timers in the same TimerGroup!");
-
- if (&T < this) {
- T.Lock.release();
- Lock.release();
- } else {
- Lock.release();
- T.Lock.release();
- }
-
- return *this;
- }
-
- // operator< - Allow sorting...
+ const Timer &operator=(const Timer &T);
+
+ // operator< - Allow sorting.
bool operator<(const Timer &T) const {
// Sort by Wall Time elapsed, as it is the only thing really accurate
return Elapsed < T.Elapsed;
Modified: llvm/trunk/lib/Support/Timer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=99839&r1=99838&r2=99839&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Timer.cpp (original)
+++ llvm/trunk/lib/Support/Timer.cpp Mon Mar 29 16:24:52 2010
@@ -147,7 +147,6 @@
static ManagedStatic > ActiveTimers;
void Timer::startTimer() {
- sys::SmartScopedLock L(*TimerLock);
Started = true;
ActiveTimers->push_back(this);
TimeRecord TR = getTimeRecord(true);
@@ -159,7 +158,6 @@
}
void Timer::stopTimer() {
- sys::SmartScopedLock L(*TimerLock);
TimeRecord TR = getTimeRecord(false);
Elapsed += TR.Elapsed;
UserTime += TR.UserTime;
@@ -184,14 +182,26 @@
PeakMem += T.PeakMem;
}
+const Timer &Timer::operator=(const Timer &T) {
+ Elapsed = T.Elapsed;
+ UserTime = T.UserTime;
+ SystemTime = T.SystemTime;
+ MemUsed = T.MemUsed;
+ PeakMem = T.PeakMem;
+ PeakMemBase = T.PeakMemBase;
+ Name = T.Name;
+ Started = T.Started;
+ assert(TG == T.TG && "Can only assign timers in the same TimerGroup!");
+ return *this;
+}
+
+
/// addPeakMemoryMeasurement - This method should be called whenever memory
/// usage needs to be checked. It adds a peak memory measurement to the
/// currently active timers, which will be printed when the timer group prints
///
void Timer::addPeakMemoryMeasurement() {
- sys::SmartScopedLock L(*TimerLock);
size_t MemUsed = getMemUsage();
-
for (std::vector::iterator I = ActiveTimers->begin(),
E = ActiveTimers->end(); I != E; ++I)
(*I)->PeakMem = std::max((*I)->PeakMem, MemUsed-(*I)->PeakMemBase);
@@ -208,7 +218,6 @@
}
void Timer::print(const Timer &Total, raw_ostream &OS) {
- sys::SmartScopedLock L(*TimerLock);
if (Total.UserTime)
printVal(UserTime, Total.UserTime, OS);
if (Total.SystemTime)
@@ -219,13 +228,13 @@
OS << " ";
- if (Total.MemUsed) {
+ if (Total.MemUsed)
OS << format("%9lld", (long long)MemUsed) << " ";
- }
+
if (Total.PeakMem) {
- if (PeakMem) {
+ if (PeakMem)
OS << format("%9lld", (long long)PeakMem) << " ";
- } else
+ else
OS << " ";
}
OS << Name << "\n";
@@ -286,15 +295,13 @@
//===----------------------------------------------------------------------===//
// GetLibSupportInfoOutputFile - Return a file stream to print our output on.
-raw_ostream *
-llvm::GetLibSupportInfoOutputFile() {
+raw_ostream *llvm::GetLibSupportInfoOutputFile() {
std::string &LibSupportInfoOutputFilename = getLibSupportInfoOutputFilename();
if (LibSupportInfoOutputFilename.empty())
return &errs();
if (LibSupportInfoOutputFilename == "-")
return &outs();
-
std::string Error;
raw_ostream *Result = new raw_fd_ostream(LibSupportInfoOutputFilename.c_str(),
Error, raw_fd_ostream::F_Append);
@@ -373,7 +380,7 @@
TimersToPrint.clear();
- if (OutStream != &errs() && OutStream != &outs() && OutStream != &dbgs())
+ if (OutStream != &errs() && OutStream != &outs())
delete OutStream; // Close the file.
}
From evan.cheng at apple.com Mon Mar 29 16:27:30 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 29 Mar 2010 21:27:30 -0000
Subject: [llvm-commits] [llvm] r99840 - in /llvm/trunk:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
test/CodeGen/Generic/2010-ZeroSizedArg.ll
Message-ID: <20100329212730.C17452A6C12C@llvm.org>
Author: evancheng
Date: Mon Mar 29 16:27:30 2010
New Revision: 99840
URL: http://llvm.org/viewvc/llvm-project?rev=99840&view=rev
Log:
Fix PR4975. Avoid referencing empty vector.
Added:
llvm/trunk/test/CodeGen/Generic/2010-ZeroSizedArg.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=99840&r1=99839&r2=99840&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Mar 29 16:27:30 2010
@@ -6051,8 +6051,10 @@
}
if (!I->use_empty()) {
- SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
- SDB->getCurDebugLoc());
+ SDValue Res;
+ if (!ArgValues.empty())
+ Res = DAG.getMergeValues(&ArgValues[0], NumValues,
+ SDB->getCurDebugLoc());
SDB->setValue(I, Res);
// If this argument is live outside of the entry block, insert a copy from
Added: llvm/trunk/test/CodeGen/Generic/2010-ZeroSizedArg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2010-ZeroSizedArg.ll?rev=99840&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2010-ZeroSizedArg.ll (added)
+++ llvm/trunk/test/CodeGen/Generic/2010-ZeroSizedArg.ll Mon Mar 29 16:27:30 2010
@@ -0,0 +1,17 @@
+; RUN: llc < %s
+; PR4975
+
+%0 = type <{ [0 x i32] }>
+%union.T0 = type { }
+
+ at .str = private constant [1 x i8] c" "
+
+define arm_apcscc void @t(%0) nounwind {
+entry:
+ %arg0 = alloca %union.T0
+ %1 = bitcast %union.T0* %arg0 to %0*
+ store %0 %0, %0* %1, align 1
+ ret void
+}
+
+declare arm_apcscc i32 @printf(i8*, ...)
From sabre at nondot.org Mon Mar 29 16:28:41 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 29 Mar 2010 21:28:41 -0000
Subject: [llvm-commits] [llvm] r99841 - in /llvm/trunk:
include/llvm/Support/Timer.h lib/Support/Timer.cpp
Message-ID: <20100329212841.5A3AA2A6C12C@llvm.org>
Author: lattner
Date: Mon Mar 29 16:28:41 2010
New Revision: 99841
URL: http://llvm.org/viewvc/llvm-project?rev=99841&view=rev
Log:
remove support for per-time peak memory tracking, this
isn't used by anyone and is better exposed as a non-per-timer
thing. Also, stop including System/Mutex.h in Timer.h
Modified:
llvm/trunk/include/llvm/Support/Timer.h
llvm/trunk/lib/Support/Timer.cpp
Modified: llvm/trunk/include/llvm/Support/Timer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Timer.h?rev=99841&r1=99840&r2=99841&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/Timer.h (original)
+++ llvm/trunk/include/llvm/Support/Timer.h Mon Mar 29 16:28:41 2010
@@ -16,7 +16,6 @@
#define LLVM_SUPPORT_TIMER_H
#include "llvm/System/DataTypes.h"
-#include "llvm/System/Mutex.h"
#include
#include
#include
@@ -39,8 +38,6 @@
double UserTime; // User time elapsed
double SystemTime; // System time elapsed
ssize_t MemUsed; // Memory allocated (in bytes)
- size_t PeakMem; // Peak memory used
- size_t PeakMemBase; // Temporary for peak memory calculation.
std::string Name; // The name of this time variable.
bool Started; // Has this time variable ever been started?
TimerGroup *TG; // The TimerGroup this Timer is in.
@@ -54,7 +51,6 @@
double getProcessTime() const { return UserTime+SystemTime; }
double getWallTime() const { return Elapsed; }
ssize_t getMemUsed() const { return MemUsed; }
- size_t getPeakMem() const { return PeakMem; }
public:
std::string getName() const { return Name; }
@@ -77,12 +73,6 @@
///
void stopTimer();
- /// addPeakMemoryMeasurement - This method should be called whenever memory
- /// usage needs to be checked. It adds a peak memory measurement to the
- /// currently active timers, which will be printed when the timer group prints
- ///
- static void addPeakMemoryMeasurement();
-
/// print - Print the current timer to standard error, and reset the "Started"
/// flag.
void print(const Timer &Total, raw_ostream &OS);
Modified: llvm/trunk/lib/Support/Timer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=99841&r1=99840&r2=99841&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Timer.cpp (original)
+++ llvm/trunk/lib/Support/Timer.cpp Mon Mar 29 16:28:41 2010
@@ -11,15 +11,14 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/Support/Debug.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
#include "llvm/Support/ManagedStatic.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/Format.h"
+#include "llvm/System/Mutex.h"
#include "llvm/System/Process.h"
-#include
-#include
#include