From anton at korobeynikov.info Mon May 17 01:40:37 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Mon, 17 May 2010 10:40:37 +0400 Subject: [llvm-commits] Global Merge Pass for ARM In-Reply-To: <00CB9243-E49C-4A8D-B63E-226FC9ADAFD6@apple.com> References: <1274006983.22060.61.camel@aslstation> <00CB9243-E49C-4A8D-B63E-226FC9ADAFD6@apple.com> Message-ID: Hi, Eric > This is pretty cool and simple so far. ?What's the benchmarking look like? In fact the poor results of some numeric codes was the main motivation for this pass. The typical "bad" code is some sort of FIR/IIR filter applications (or something similar in the spirit) which needs to operate on several global memory buffers at once in the tight internal loop. Like in the mentioned toy example the addresses of globals need to be kept in the registers leading to spills & reloads inside hot computation loops. The speedup of such computational kernels might be up to 2x-3x. I didn't see any speed degradation for "normal" code. > At the very least do you mind including the above writeup in a big block comment > on the pass? ?I make no claims about the rest of it, but the pass is pretty > sparse on documentation and much easier to read with the example there. Yes, will add with the final version. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From asl at math.spbu.ru Mon May 17 03:10:57 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 17 May 2010 12:10:57 +0400 Subject: [llvm-commits] [llvm] r103917 - /llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp In-Reply-To: <4E37E15C-26D7-4095-A793-510C744BF1EF@apple.com> References: <20100517011146.A3F04312800A@llvm.org> <4E37E15C-26D7-4095-A793-510C744BF1EF@apple.com> Message-ID: Hi, Evan > Let me know if this is not correct. I don't see why this pass is only run in ARM mode. This looks ok for me. Maybe I was over-conservative :) -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From baldrick at free.fr Mon May 17 04:12:46 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 17 May 2010 11:12:46 +0200 Subject: [llvm-commits] [PATCH] InstCombine: remove malloc+free if malloc's only uses are comparisons to null In-Reply-To: <4BF02485.2050508@iki.fi> References: <4BF02485.2050508@iki.fi> Message-ID: <4BF1088E.30805@free.fr> Hi Matti, > There's one slight weirdness in it whose cleanness I'm not so sure > about: when getting rid of the malloc+free, we want to replace the > remaining uses of the malloc with a constant (trivially folded) non-null > pointer. The only way of getting such a thing I could think of was to > bitcast the enclosing function's address, since that's a GlobalValue and > hence can be handled by ConstantFoldCompareInstruction. It definitely > works, but it seems a bit hacky. why not just directly replace the comparisons with true/false? Also, InstCombineCompares.cpp has a similar transformation in which a malloc which is never freed, but only used in comparisons (for some reason it is limited to only one comparison) is removed. You may want to share some code/logic with that. Ciao, Duncan. From baldrick at free.fr Mon May 17 04:18:09 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 17 May 2010 11:18:09 +0200 Subject: [llvm-commits] [llvm-gcc-4.2] r103918 - /llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp In-Reply-To: <20100517012918.68ED8312800A@llvm.org> References: <20100517012918.68ED8312800A@llvm.org> Message-ID: <4BF109D1.5030203@free.fr> > Fix divide by 8 thinko in palignr128 expansion. It's there in the > mmx version. Testcase? Ciao, Duncan. From xuzhongxing at gmail.com Mon May 17 04:47:55 2010 From: xuzhongxing at gmail.com (Zhongxing Xu) Date: Mon, 17 May 2010 09:47:55 -0000 Subject: [llvm-commits] [llvm] r103936 - in /llvm/trunk: include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/ScheduleDAG.cpp Message-ID: <20100517094755.DEE71312800A@llvm.org> Author: zhongxingxu Date: Mon May 17 04:47:55 2010 New Revision: 103936 URL: http://llvm.org/viewvc/llvm-project?rev=103936&view=rev Log: Remove unused member variable. Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=103936&r1=103935&r2=103936&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Mon May 17 04:47:55 2010 @@ -34,7 +34,6 @@ class SDNode; class TargetInstrInfo; class TargetInstrDesc; - class TargetLowering; class TargetMachine; class TargetRegisterClass; template class GraphWriter; @@ -456,7 +455,6 @@ const TargetMachine &TM; // Target processor const TargetInstrInfo *TII; // Target instruction information const TargetRegisterInfo *TRI; // Target processor register info - const TargetLowering *TLI; // Target lowering info MachineFunction &MF; // Machine function MachineRegisterInfo &MRI; // Virtual/real register map std::vector Sequence; // The schedule. Null SUnit*'s Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp?rev=103936&r1=103935&r2=103936&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Mon May 17 04:47:55 2010 @@ -27,7 +27,6 @@ : TM(mf.getTarget()), TII(TM.getInstrInfo()), TRI(TM.getRegisterInfo()), - TLI(TM.getTargetLowering()), MF(mf), MRI(mf.getRegInfo()), EntrySU(), ExitSU() { } From matti.niemenmaa+llvm at iki.fi Mon May 17 06:07:06 2010 From: matti.niemenmaa+llvm at iki.fi (Matti Niemenmaa) Date: Mon, 17 May 2010 14:07:06 +0300 Subject: [llvm-commits] [PATCH] InstCombine: remove malloc+free if malloc's only uses are comparisons to null In-Reply-To: <4BF1088E.30805@free.fr> References: <4BF02485.2050508@iki.fi> <4BF1088E.30805@free.fr> Message-ID: On 2010-05-17 12:12, Duncan Sands wrote: >> There's one slight weirdness in it whose cleanness I'm not so sure >> about: when getting rid of the malloc+free, we want to replace the >> remaining uses of the malloc with a constant (trivially folded) non-null >> pointer. The only way of getting such a thing I could think of was to >> bitcast the enclosing function's address, since that's a GlobalValue and >> hence can be handled by ConstantFoldCompareInstruction. It definitely >> works, but it seems a bit hacky. > > why not just directly replace the comparisons with true/false? Also, > InstCombineCompares.cpp has a similar transformation in which a malloc > which is never freed, but only used in comparisons (for some reason it > is limited to only one comparison) is removed. You may want to share > some code/logic with that. I did it like that mostly to make the code simpler, since it's then just a single RAUW to get rid of the malloc. I suppose you're right that it's cleaner to replace the icmps themselves, even though it takes some more code. Another issue was that I wasn't sure what to do with comparisons that aren't eq/ne, since the value of null is target-specific. Apparently ConstantFoldCompareInstruction does nothing to them anyway. I think the safest thing to do is to bail on such comparisons and not perform the optimization. I'll amend the patch to only operate on icmp eq/ne. The code in InstCombineCompares.cpp makes me wonder whether we should be operating on the malloc call to begin with? That is, move this 'malloc + [icmps] + [free]' removal from visitFree and InstCombineCompares.cpp to a new InstCombiner::visitMalloc function which would be called like visitFree currently is, from InstCombiner::visitCallInst. From stoklund at 2pi.dk Mon May 17 10:30:32 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 17 May 2010 15:30:32 -0000 Subject: [llvm-commits] [llvm] r103939 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp Message-ID: <20100517153032.CE115312800A@llvm.org> Author: stoklund Date: Mon May 17 10:30:32 2010 New Revision: 103939 URL: http://llvm.org/viewvc/llvm-project?rev=103939&view=rev Log: Extract spill cost calculation to a new method, and use definePhysReg() to clear out aliases when allocating. Clean up allocVirtReg(). Use calcSpillCost() to allow more aggressive hinting. Now the hint is always taken unless blocked by a reserved register. This leads to more coalescing, lower register pressure, and less spilling. Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=103939&r1=103938&r2=103939&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Mon May 17 10:30:32 2010 @@ -118,6 +118,11 @@ // not be erased. bool isBulkSpilling; + enum { + spillClean = 1, + spillDirty = 100, + spillImpossible = ~0u + }; public: virtual const char *getPassName() const { return "Fast Register Allocator"; @@ -144,6 +149,7 @@ void usePhysReg(MachineOperand&); void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState); + unsigned calcSpillCost(unsigned PhysReg) const; void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg); void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint); LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum, @@ -369,6 +375,44 @@ } +// calcSpillCost - Return the cost of spilling clearing out PhysReg and +// aliases so it is free for allocation. +// Returns 0 when PhysReg is free or disabled with all aliases disabled - it +// can be allocated directly. +// Returns spillImpossible when PhysReg or an alias can't be spilled. +unsigned RAFast::calcSpillCost(unsigned PhysReg) const { + switch (unsigned VirtReg = PhysRegState[PhysReg]) { + case regDisabled: + break; + case regFree: + return 0; + case regReserved: + return spillImpossible; + default: + return LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean; + } + + // This is a disabled register, add up const of aliases. + unsigned Cost = 0; + for (const unsigned *AS = TRI->getAliasSet(PhysReg); + unsigned Alias = *AS; ++AS) { + switch (unsigned VirtReg = PhysRegState[Alias]) { + case regDisabled: + break; + case regFree: + ++Cost; + break; + case regReserved: + return spillImpossible; + default: + Cost += LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean; + break; + } + } + return Cost; +} + + /// assignVirtToPhysReg - This method updates local state so that we know /// that PhysReg is the proper container for VirtReg now. The physical /// register must not be used for anything else when this is called. @@ -383,15 +427,12 @@ /// allocVirtReg - Allocate a physical register for VirtReg. void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) { - const unsigned SpillCost = 100; const unsigned VirtReg = LRE.first; assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Can only allocate virtual registers"); const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); - TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF); - TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF); // Ignore invalid hints. if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || @@ -403,107 +444,44 @@ if (Hint) { assert(RC->contains(Hint) && !UsedInInstr.test(Hint) && Allocatable.test(Hint) && "Invalid hint should have been cleared"); - switch(PhysRegState[Hint]) { - case regDisabled: - case regReserved: - break; + switch(calcSpillCost(Hint)) { default: - spillVirtReg(MI, PhysRegState[Hint]); + definePhysReg(MI, Hint, regFree); // Fall through. - case regFree: + case 0: return assignVirtToPhysReg(LRE, Hint); + case spillImpossible: + break; } } + TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF); + TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF); + // First try to find a completely free register. - unsigned BestCost = 0, BestReg = 0; - bool hasDisabled = false; for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { unsigned PhysReg = *I; - switch(PhysRegState[PhysReg]) { - case regDisabled: - hasDisabled = true; - case regReserved: - continue; - case regFree: - if (!UsedInInstr.test(PhysReg)) - return assignVirtToPhysReg(LRE, PhysReg); - continue; - default: - // Grab the first spillable register we meet. - if (!BestReg && !UsedInInstr.test(PhysReg)) - BestReg = PhysReg, BestCost = SpillCost; - continue; - } + if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg)) + return assignVirtToPhysReg(LRE, PhysReg); } DEBUG(dbgs() << "Allocating %reg" << VirtReg << " from " << RC->getName() - << " candidate=" << TRI->getName(BestReg) << "\n"); - - // Try to extend the working set for RC if there were any disabled registers. - if (hasDisabled && (!BestReg || BestCost >= SpillCost)) { - for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { - unsigned PhysReg = *I; - if (PhysRegState[PhysReg] != regDisabled || UsedInInstr.test(PhysReg)) - continue; + << "\n"); - // Calculate the cost of bringing PhysReg into the working set. - unsigned Cost=0; - bool Impossible = false; - for (const unsigned *AS = TRI->getAliasSet(PhysReg); - unsigned Alias = *AS; ++AS) { - if (UsedInInstr.test(Alias)) { - Impossible = true; - break; - } - switch (PhysRegState[Alias]) { - case regDisabled: - break; - case regReserved: - Impossible = true; - break; - case regFree: - Cost++; - break; - default: - Cost += SpillCost; - break; - } - } - if (Impossible) continue; - DEBUG(dbgs() << "- candidate " << TRI->getName(PhysReg) - << " cost=" << Cost << "\n"); - if (!BestReg || Cost < BestCost) { - BestReg = PhysReg; - BestCost = Cost; - if (Cost < SpillCost) break; - } + unsigned BestReg = 0, BestCost = spillImpossible; + for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { + unsigned Cost = calcSpillCost(*I); + if (Cost < BestCost) { + BestReg = *I; + BestCost = Cost; + if (Cost == 0) break; } } if (BestReg) { // BestCost is 0 when all aliases are already disabled. - if (BestCost) { - if (PhysRegState[BestReg] != regDisabled) - spillVirtReg(MI, PhysRegState[BestReg]); - else { - // Make sure all aliases are disabled. - for (const unsigned *AS = TRI->getAliasSet(BestReg); - unsigned Alias = *AS; ++AS) { - switch (PhysRegState[Alias]) { - case regDisabled: - continue; - case regFree: - PhysRegState[Alias] = regDisabled; - break; - default: - spillVirtReg(MI, PhysRegState[Alias]); - PhysRegState[Alias] = regDisabled; - break; - } - } - } - } + if (BestCost) + definePhysReg(MI, BestReg, regFree); return assignVirtToPhysReg(LRE, BestReg); } From stoklund at 2pi.dk Mon May 17 10:30:37 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 17 May 2010 15:30:37 -0000 Subject: [llvm-commits] [llvm] r103940 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp Message-ID: <20100517153037.8A46F3128018@llvm.org> Author: stoklund Date: Mon May 17 10:30:37 2010 New Revision: 103940 URL: http://llvm.org/viewvc/llvm-project?rev=103940&view=rev Log: Minor optimizations. DenseMap::begin() is surprisingly slow on an empty map. Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=103940&r1=103939&r2=103940&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Mon May 17 10:30:37 2010 @@ -267,6 +267,7 @@ /// spillAll - Spill all dirty virtregs without killing them. void RAFast::spillAll(MachineInstr *MI) { + if (LiveVirtRegs.empty()) return; isBulkSpilling = true; for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end(); i != e; ++i) @@ -471,17 +472,15 @@ unsigned BestReg = 0, BestCost = spillImpossible; for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { unsigned Cost = calcSpillCost(*I); - if (Cost < BestCost) { - BestReg = *I; - BestCost = Cost; - if (Cost == 0) break; - } + // Cost is 0 when all aliases are already disabled. + if (Cost == 0) + return assignVirtToPhysReg(LRE, *I); + if (Cost < BestCost) + BestReg = *I, BestCost = Cost; } if (BestReg) { - // BestCost is 0 when all aliases are already disabled. - if (BestCost) - definePhysReg(MI, BestReg, regFree); + definePhysReg(MI, BestReg, regFree); return assignVirtToPhysReg(LRE, BestReg); } From echristo at apple.com Mon May 17 10:33:34 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 17 May 2010 08:33:34 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r103918 - /llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp In-Reply-To: <4BF109D1.5030203@free.fr> References: <20100517012918.68ED8312800A@llvm.org> <4BF109D1.5030203@free.fr> Message-ID: On May 17, 2010, at 2:18 AM, Duncan Sands wrote: >> Fix divide by 8 thinko in palignr128 expansion. It's there in the >> mmx version. > > Testcase? I'll throw one in today. -eric From Edmund.Grimley-Evans at arm.com Mon May 17 10:50:51 2010 From: Edmund.Grimley-Evans at arm.com (Edmund Grimley-Evans) Date: Mon, 17 May 2010 16:50:51 +0100 Subject: [llvm-commits] [PATCH] Test NEON code generation and calling convention Message-ID: <89A528FE6DB0FA44877BB2F05B8467180BACA420@ZIPPY.Emea.Arm.com> Could this file (vadd2.ll) be added in test/CodeGen/ARM/? It broke in r103411 and was fixed again in r103854. It would be nice to keep it working. I'm not sure what if any official rules govern how vector quantities should be passed as arguments and returned. It appears that vectors of less than 64 bits (such as the <2 x i8> in the first example in vadd2.ll) currently get passed in R0-R3 rather than Q0-Q3, which leads to some ugly code. Is this a bug or a feature? -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. -------------- next part -------------- A non-text attachment was scrubbed... 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From criswell at cs.uiuc.edu Mon May 17 12:19:34 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Mon, 17 May 2010 12:19:34 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/downloads.html pubs.html sidebar.incl Message-ID: <201005171719.o4HHJYCI025239@zion.cs.uiuc.edu> Changes in directory llvm-www/safecode: downloads.html updated: 1.5 -> 1.6 pubs.html updated: 1.6 -> 1.7 sidebar.incl updated: 1.3 -> 1.4 --- Log message: Started integrating the SVA web site. --- Diffs of the changes: (+46 -50) downloads.html | 2 + pubs.html | 93 ++++++++++++++++++++++++++------------------------------- sidebar.incl | 1 3 files changed, 46 insertions(+), 50 deletions(-) Index: llvm-www/safecode/downloads.html diff -u llvm-www/safecode/downloads.html:1.5 llvm-www/safecode/downloads.html:1.6 --- llvm-www/safecode/downloads.html:1.5 Mon May 17 12:06:28 2010 +++ llvm-www/safecode/downloads.html Mon May 17 12:19:19 2010 @@ -63,6 +63,8 @@


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    • From stoklund at 2pi.dk Mon May 17 12:18:59 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 17 May 2010 17:18:59 -0000 Subject: [llvm-commits] [llvm] r103946 - in /llvm/trunk: lib/CodeGen/RegAllocFast.cpp test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll Message-ID: <20100517171859.E64F4312800A@llvm.org> Author: stoklund Date: Mon May 17 12:18:59 2010 New Revision: 103946 URL: http://llvm.org/viewvc/llvm-project?rev=103946&view=rev Log: Avoid allocating the same physreg to multiple virtregs in one instruction. While that approach works wonders for register pressure, it tends to break everything. This should unbreak the arm-linux builder and fix a number of miscompilations. Added: llvm/trunk/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=103946&r1=103945&r2=103946&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Mon May 17 12:18:59 2010 @@ -471,6 +471,7 @@ unsigned BestReg = 0, BestCost = spillImpossible; for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { + if (UsedInInstr.test(*I)) continue; unsigned Cost = calcSpillCost(*I); // Cost is 0 when all aliases are already disabled. if (Cost == 0) Added: llvm/trunk/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll?rev=103946&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll Mon May 17 12:18:59 2010 @@ -0,0 +1,105 @@ +; RUN: llc < %s -regalloc=fast -verify-machineinstrs +target triple = "arm-pc-linux-gnu" + +; This test case would accidentally use the same physreg for two virtregs +; because allocVirtReg forgot to check if registers were already used in the +; instruction. +; This caused the RegScavenger to complain, but -verify-machineinstrs also +; catches it. + +%struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 } + + at search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=1] + at bishop_mobility_rr45 = external global [64 x [256 x i32]] ; <[64 x [256 x i32]]*> [#uses=1] + +declare fastcc i32 @FirstOne() + +define fastcc void @Evaluate() { +entry: + br i1 false, label %cond_false186, label %cond_true + +cond_true: ; preds = %entry + ret void + +cond_false186: ; preds = %entry + br i1 false, label %cond_true293, label %bb203 + +bb203: ; preds = %cond_false186 + ret void + +cond_true293: ; preds = %cond_false186 + br i1 false, label %cond_true298, label %cond_next317 + +cond_true298: ; preds = %cond_true293 + br i1 false, label %cond_next518, label %cond_true397.preheader + +cond_next317: ; preds = %cond_true293 + ret void + +cond_true397.preheader: ; preds = %cond_true298 + ret void + +cond_next518: ; preds = %cond_true298 + br i1 false, label %bb1069, label %cond_true522 + +cond_true522: ; preds = %cond_next518 + ret void + +bb1069: ; preds = %cond_next518 + br i1 false, label %cond_next1131, label %bb1096 + +bb1096: ; preds = %bb1069 + ret void + +cond_next1131: ; preds = %bb1069 + br i1 false, label %cond_next1207, label %cond_true1150 + +cond_true1150: ; preds = %cond_next1131 + ret void + +cond_next1207: ; preds = %cond_next1131 + br i1 false, label %cond_next1219, label %cond_true1211 + +cond_true1211: ; preds = %cond_next1207 + ret void + +cond_next1219: ; preds = %cond_next1207 + br i1 false, label %cond_true1223, label %cond_next1283 + +cond_true1223: ; preds = %cond_next1219 + br i1 false, label %cond_true1254, label %cond_true1264 + +cond_true1254: ; preds = %cond_true1223 + br i1 false, label %bb1567, label %cond_true1369.preheader + +cond_true1264: ; preds = %cond_true1223 + ret void + +cond_next1283: ; preds = %cond_next1219 + ret void + +cond_true1369.preheader: ; preds = %cond_true1254 + ret void + +bb1567: ; preds = %cond_true1254 + %tmp1591 = load i64* getelementptr inbounds (%struct.CHESS_POSITION* @search, i32 0, i32 4) ; [#uses=1] + %tmp1572 = tail call fastcc i32 @FirstOne() ; [#uses=1] + %tmp1594 = load i32* undef ; [#uses=1] + %tmp1594.upgrd.5 = trunc i32 %tmp1594 to i8 ; [#uses=1] + %shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; [#uses=1] + %tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6 ; [#uses=1] + %tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32 ; [#uses=1] + %tmp1596 = and i32 %tmp1595.upgrd.7, 255 ; [#uses=1] + %gep.upgrd.8 = zext i32 %tmp1596 to i64 ; [#uses=1] + %tmp1598 = getelementptr [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; [#uses=1] + %tmp1599 = load i32* %tmp1598 ; [#uses=1] + %tmp1602 = sub i32 0, %tmp1599 ; [#uses=1] + br i1 undef, label %cond_next1637, label %cond_true1607 + +cond_true1607: ; preds = %bb1567 + ret void + +cond_next1637: ; preds = %bb1567 + %tmp1662 = sub i32 %tmp1602, 0 ; [#uses=0] + ret void +} From criswell at cs.uiuc.edu Mon May 17 12:22:54 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Mon, 17 May 2010 12:22:54 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/people.html Message-ID: <201005171722.o4HHMs0m025417@zion.cs.uiuc.edu> Changes in directory llvm-www/safecode: people.html updated: 1.5 -> 1.6 --- Log message: Made sure everyone is listed. --- Diffs of the changes: (+4 -0) people.html | 4 ++++ 1 files changed, 4 insertions(+) Index: llvm-www/safecode/people.html diff -u llvm-www/safecode/people.html:1.5 llvm-www/safecode/people.html:1.6 --- llvm-www/safecode/people.html:1.5 Mon May 17 12:06:28 2010 +++ llvm-www/safecode/people.html Mon May 17 12:22:38 2010 @@ -100,6 +100,10 @@
  • Billy Lau
    • + +
  • + Igor Murashkin +
From criswell at cs.uiuc.edu Mon May 17 12:23:14 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Mon, 17 May 2010 12:23:14 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/images/SVA.jpg Message-ID: <201005171723.o4HHNEEu025450@zion.cs.uiuc.edu> Changes in directory llvm-www/safecode/images: SVA.jpg added (r1.1) --- Log message: Adding SVA diagram. --- Diffs of the changes: (+0 -0) SVA.jpg | 0 1 files changed Index: llvm-www/safecode/images/SVA.jpg From criswell at cs.uiuc.edu Mon May 17 12:26:06 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Mon, 17 May 2010 12:26:06 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/sva.html Message-ID: <201005171726.o4HHQ6ks025670@zion.cs.uiuc.edu> Changes in directory llvm-www/safecode: sva.html added (r1.1) --- Log message: SVA page on the SAFECode web site. --- Diffs of the changes: (+98 -0) sva.html | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 98 insertions(+) Index: llvm-www/safecode/sva.html diff -c /dev/null llvm-www/safecode/sva.html:1.1 *** /dev/null Mon May 17 12:26:01 2010 --- llvm-www/safecode/sva.html Mon May 17 12:25:51 2010 *************** *** 0 **** --- 1,98 ---- + + + + + + + + + + + + + + + + SAFECode: Secure Virtual Architecture + + + + + +
+ + + + +
+ + + +
+ +
+ +

Secure Virtual Architecture (SVA)

+
+ +

+ + Secure Virtual Architecture (SVA) is a compiler-based virtual machine + capable of hosting an entire commodity operating system and all its + applications. The virtual machine is unique because it combines a + sophisticated compiler (like high-level language virtual machines such + as JVM or CLI) with a rich run-time system capable of monitoring and + controlling all privileged operations (like Virtual Machine Monitors + such as VMware or Xen). This combination opens up the opportunity to + develop novel and powerful solutions to a wide range of important + software security and reliability problems, including intrusion + prevention, intrusion detection and analysis, OS component isolation, + full system recovery, application data confidentiality, secure + application- and system-level information flow, and many others. The + SVA research group is funded by grants from the National Science + Foundation, Apple Computer, Inc., and the University of Illinois. +

+
+
+ +
+ +
+ + +
+ + + + + + + From criswell at cs.uiuc.edu Mon May 17 12:28:30 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Mon, 17 May 2010 12:28:30 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/links.html Message-ID: <201005171728.o4HHSURR025748@zion.cs.uiuc.edu> Changes in directory llvm-www/safecode: links.html updated: 1.5 -> 1.6 --- Log message: Remove SVA link since the web sites are now merged. --- Diffs of the changes: (+5 -10) links.html | 15 +++++---------- 1 files changed, 5 insertions(+), 10 deletions(-) Index: llvm-www/safecode/links.html diff -u llvm-www/safecode/links.html:1.5 llvm-www/safecode/links.html:1.6 --- llvm-www/safecode/links.html:1.5 Mon May 17 12:06:28 2010 +++ llvm-www/safecode/links.html Mon May 17 12:28:14 2010 @@ -55,22 +55,17 @@
SAFECode is written using the LLVM Compiler Infrastructure. - -
- -
  • - Secure Virtual Architecture Project -
    - The Secure Virtual Architecture (SVA) Project uses the SAFECode - techniques to provide memory safety to the entire software stack, - including the operating system kernel. -
    • +

    +

    +

    +

    +


    From daniel at zuster.org Mon May 17 12:46:23 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 17 May 2010 17:46:23 -0000 Subject: [llvm-commits] [llvm] r103950 - in /llvm/trunk: include/llvm/MC/MCSymbol.h lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/assignment.s Message-ID: <20100517174623.611DC312800A@llvm.org> Author: ddunbar Date: Mon May 17 12:46:23 2010 New Revision: 103950 URL: http://llvm.org/viewvc/llvm-project?rev=103950&view=rev Log: llvm-mc: Support reassignment of variables in one special case, when the variable has not yet been used in an expression. This allows us to support a few cases that show up in real code (mostly because gcc generates it for Objective-C on Darwin), without giving up a reasonable semantic model for assignment. Modified: llvm/trunk/include/llvm/MC/MCSymbol.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/test/MC/AsmParser/assignment.s Modified: llvm/trunk/include/llvm/MC/MCSymbol.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSymbol.h?rev=103950&r1=103949&r2=103950&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSymbol.h (original) +++ llvm/trunk/include/llvm/MC/MCSymbol.h Mon May 17 12:46:23 2010 @@ -52,10 +52,15 @@ /// "Lfoo" or ".foo". unsigned IsTemporary : 1; + /// IsUsedInExpr - True if this symbol has been used in an expression and + /// cannot be redefined. + unsigned IsUsedInExpr : 1; + private: // MCContext creates and uniques these. friend class MCContext; MCSymbol(StringRef name, bool isTemporary) - : Name(name), Section(0), Value(0), IsTemporary(isTemporary) {} + : Name(name), Section(0), Value(0), + IsTemporary(isTemporary), IsUsedInExpr(false) {} MCSymbol(const MCSymbol&); // DO NOT IMPLEMENT void operator=(const MCSymbol&); // DO NOT IMPLEMENT @@ -63,13 +68,15 @@ /// getName - Get the symbol name. StringRef getName() const { return Name; } - /// @name Symbol Type + /// @name Accessors /// @{ /// isTemporary - Check if this is an assembler temporary symbol. - bool isTemporary() const { - return IsTemporary; - } + bool isTemporary() const { return IsTemporary; } + + /// isUsedInExpr - Check if this is an assembler temporary symbol. + bool isUsedInExpr() const { return IsUsedInExpr; } + void setUsedInExpr(bool Value) { IsUsedInExpr = Value; } /// @} /// @name Associated Sections Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=103950&r1=103949&r2=103950&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon May 17 12:46:23 2010 @@ -189,6 +189,9 @@ std::pair Split = getTok().getIdentifier().split('@'); MCSymbol *Sym = CreateSymbol(Split.first); + // Mark the symbol as used in an expression. + Sym->setUsedInExpr(true); + // Lookup the symbol variant if used. MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; if (Split.first.size() != getTok().getIdentifier().size()) @@ -788,7 +791,9 @@ // // FIXME: Diagnostics. Note the location of the definition as a label. // FIXME: Diagnose assignment to protected identifier (e.g., register name). - if (!Sym->isUndefined() && !Sym->isAbsolute()) + if (Sym->isUndefined() && !Sym->isUsedInExpr()) + ; // Allow redefinitions of undefined symbols only used in directives. + else if (!Sym->isUndefined() && !Sym->isAbsolute()) return Error(EqualLoc, "redefinition of '" + Name + "'"); else if (!Sym->isVariable()) return Error(EqualLoc, "invalid assignment to '" + Name + "'"); @@ -800,6 +805,8 @@ // FIXME: Handle '.'. + Sym->setUsedInExpr(true); + // Do the assignment. Out.EmitAssignment(Sym, Value); Modified: llvm/trunk/test/MC/AsmParser/assignment.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/assignment.s?rev=103950&r1=103949&r2=103950&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/assignment.s (original) +++ llvm/trunk/test/MC/AsmParser/assignment.s Mon May 17 12:46:23 2010 @@ -2,6 +2,10 @@ # CHECK: TEST0: # CHECK: a = 0 -TEST0: +TEST0: a = 0 - + +# CHECK: .globl _f1 +# CHECK: _f1 = 0 + .globl _f1 + _f1 = 0 From criswell at cs.uiuc.edu Mon May 17 13:25:34 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Mon, 17 May 2010 13:25:34 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/sva.html Message-ID: <201005171825.o4HIPYCD027465@zion.cs.uiuc.edu> Changes in directory llvm-www/safecode: sva.html updated: 1.1 -> 1.2 --- Log message: Added text about how SVA uses SAFECode and a V-ISA. --- Diffs of the changes: (+17 -2) sva.html | 19 +++++++++++++++++-- 1 files changed, 17 insertions(+), 2 deletions(-) Index: llvm-www/safecode/sva.html diff -u llvm-www/safecode/sva.html:1.1 llvm-www/safecode/sva.html:1.2 --- llvm-www/safecode/sva.html:1.1 Mon May 17 12:25:51 2010 +++ llvm-www/safecode/sva.html Mon May 17 13:25:18 2010 @@ -60,8 +60,23 @@ software security and reliability problems, including intrusion prevention, intrusion detection and analysis, OS component isolation, full system recovery, application data confidentiality, secure - application- and system-level information flow, and many others. The - SVA research group is funded by grants from the National Science + application- and system-level information flow, and many others. +

    + +

    + SVA currently uses techniques employed by the + SAFECode compiler + to provide strong memory safety guarantees to the Linux kernel. All + software in SVA is compiled down to a virtual instruction set; SVA + translates code from the virtual instruction set to the native + processor's instruction set transparently. SVA's virtual instruction + set is the LLVM IR enhanced with + additional instructions + to provide memory safety for low-level software/hardware interactions. +

    + +

    + The SVA research group is funded by grants from the National Science Foundation, Apple Computer, Inc., and the University of Illinois.

    From wendling at apple.com Mon May 17 13:53:15 2010 From: wendling at apple.com (Bill Wendling) Date: Mon, 17 May 2010 11:53:15 -0700 Subject: [llvm-commits] [llvm] r103940 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp In-Reply-To: <20100517153037.8A46F3128018@llvm.org> References: <20100517153037.8A46F3128018@llvm.org> Message-ID: <541CE162-1CBB-4BC7-A7D5-665F47875950@apple.com> On May 17, 2010, at 8:30 AM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Mon May 17 10:30:37 2010 > New Revision: 103940 > > URL: http://llvm.org/viewvc/llvm-project?rev=103940&view=rev > Log: > Minor optimizations. DenseMap::begin() is surprisingly slow on an empty map. > Really?! Is there a good reason, or should that be fixed? -bw From stoklund at 2pi.dk Mon May 17 14:01:58 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 17 May 2010 12:01:58 -0700 Subject: [llvm-commits] [llvm] r103940 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp In-Reply-To: <541CE162-1CBB-4BC7-A7D5-665F47875950@apple.com> References: <20100517153037.8A46F3128018@llvm.org> <541CE162-1CBB-4BC7-A7D5-665F47875950@apple.com> Message-ID: On May 17, 2010, at 11:53 AM, Bill Wendling wrote: > On May 17, 2010, at 8:30 AM, Jakob Stoklund Olesen wrote: > >> Author: stoklund >> Date: Mon May 17 10:30:37 2010 >> New Revision: 103940 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=103940&view=rev >> Log: >> Minor optimizations. DenseMap::begin() is surprisingly slow on an empty map. >> > Really?! Is there a good reason, or should that be fixed? The DenseMap typically holds 64 or more buckets. The iterator constructor skips the empty buckets which is all of them when the map is empty. The scan is really necessary when the map is not empty. Changing begin() to return end() when empty() would avoid this issue: inline iterator begin() { return empty() ? end() : iterator(Buckets, Buckets+NumBuckets); } The fast allocator happens to be iterating over empty maps a lot, but it might be worth fixing in the general case too. From criswell at cs.uiuc.edu Mon May 17 14:25:45 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Mon, 17 May 2010 14:25:45 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/pubs.html Message-ID: <201005171925.o4HJPjJe029272@zion.cs.uiuc.edu> Changes in directory llvm-www/safecode: pubs.html updated: 1.7 -> 1.8 --- Log message: Added related publications per Vikram's request. Changed color of notes indicating that papers won awards. --- Diffs of the changes: (+72 -1) pubs.html | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 72 insertions(+), 1 deletion(-) Index: llvm-www/safecode/pubs.html diff -u llvm-www/safecode/pubs.html:1.7 llvm-www/safecode/pubs.html:1.8 --- llvm-www/safecode/pubs.html:1.7 Mon May 17 12:19:19 2010 +++ llvm-www/safecode/pubs.html Mon May 17 14:25:29 2010 @@ -75,7 +75,9 @@ Proceedings of the Twenty First ACM Symposium on Operating Systems Principles (SOSP '07), Stevenson, WA, October 2007.
    - Received an SOSP 2007 Audience Choice Award. + + Received an SOSP 2007 Audience Choice Award. +
    @@ -182,6 +184,75 @@
    + +
    + +
    +

    Related Publications

    +
    + + +
    +

    From criswell at cs.uiuc.edu Mon May 17 14:42:54 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Mon, 17 May 2010 14:42:54 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/pubs.html Message-ID: <201005171942.o4HJgs6k029773@zion.cs.uiuc.edu> Changes in directory llvm-www/safecode: pubs.html updated: 1.8 -> 1.9 --- Log message: Added Andrew's Recovery Domains paper. --- Diffs of the changes: (+15 -0) pubs.html | 15 +++++++++++++++ 1 files changed, 15 insertions(+) Index: llvm-www/safecode/pubs.html diff -u llvm-www/safecode/pubs.html:1.8 llvm-www/safecode/pubs.html:1.9 --- llvm-www/safecode/pubs.html:1.8 Mon May 17 14:25:29 2010 +++ llvm-www/safecode/pubs.html Mon May 17 14:42:39 2010 @@ -65,6 +65,21 @@
    +
  • + + Recovery Domains: An Organizing Principle for Recoverable Operating + Systems + +
    + Andrew Lenharth, Samuel T. King, and and Vikram Adve +
    + Proceedings of the Fourteenth International Conference on +Architectural Support for Programming Languages and Operating Systems (ASPLOS), + Washington, D.C., March 2009. +
    • + +
    +
  • Secure Virtual Architecture: A Safe Execution Environment for Commodity From clattner at apple.com Mon May 17 14:52:15 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 17 May 2010 12:52:15 -0700 Subject: [llvm-commits] [llvm] r103940 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp In-Reply-To: References: <20100517153037.8A46F3128018@llvm.org> <541CE162-1CBB-4BC7-A7D5-665F47875950@apple.com> Message-ID: <90911873-4625-4D9F-9B61-B51464503DDC@apple.com> On May 17, 2010, at 12:01 PM, Jakob Stoklund Olesen wrote: > > On May 17, 2010, at 11:53 AM, Bill Wendling wrote: > >> On May 17, 2010, at 8:30 AM, Jakob Stoklund Olesen wrote: >> >>> Author: stoklund >>> Date: Mon May 17 10:30:37 2010 >>> New Revision: 103940 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=103940&view=rev >>> Log: >>> Minor optimizations. DenseMap::begin() is surprisingly slow on an empty map. >>> >> Really?! Is there a good reason, or should that be fixed? > > The DenseMap typically holds 64 or more buckets. The iterator constructor skips the empty buckets which is all of them when the map is empty. The scan is really necessary when the map is not empty. > > Changing begin() to return end() when empty() would avoid this issue: > > inline iterator begin() { > return empty() ? end() : iterator(Buckets, Buckets+NumBuckets); > } > > The fast allocator happens to be iterating over empty maps a lot, but it might be worth fixing in the general case too. I think this is a good idea, please do (with a comment). Please also add a comment to your regalloc saying why iterating in densemap order really is deterministic :) -Chris From evan.cheng at apple.com Mon May 17 14:51:20 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 17 May 2010 19:51:20 -0000 Subject: [llvm-commits] [llvm] r103960 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp test/CodeGen/ARM/reg_sequence.ll Message-ID: <20100517195120.84748312800A@llvm.org> Author: evancheng Date: Mon May 17 14:51:20 2010 New Revision: 103960 URL: http://llvm.org/viewvc/llvm-project?rev=103960&view=rev Log: Turn on -neon-reg-sequence by default. Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers! Added: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=103960&r1=103959&r2=103960&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon May 17 14:51:20 2010 @@ -37,7 +37,8 @@ static cl::opt UseRegSeq("neon-reg-sequence", cl::Hidden, - cl::desc("Use reg_sequence to model ld / st of multiple neon regs")); + cl::desc("Use reg_sequence to model ld / st of multiple neon regs"), + cl::init(true)); //===--------------------------------------------------------------------===// /// ARMDAGToDAGISel - ARM specific code to select ARM machine Added: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=103960&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (added) +++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Mon May 17 14:51:20 2010 @@ -0,0 +1,170 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's. + +%struct.int16x8_t = type { <8 x i16> } +%struct.int32x4_t = type { <4 x i32> } +%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } +%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> } +%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> } + +define arm_apcscc void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind { +entry: +; CHECK: t1: +; CHECK: vld1.16 +; CHECK-NOT: vmov d +; CHECK: vmovl.s16 +; CHECK: vshrn.i32 +; CHECK: vshrn.i32 +; CHECK-NOT: vmov d +; CHECK-NEXT: vst1.16 + %0 = getelementptr inbounds %struct.int32x4_t* %vT0ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] + %1 = load <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] + %2 = getelementptr inbounds %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] + %3 = load <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1] + %4 = bitcast i16* %i_ptr to i8* ; [#uses=1] + %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4) ; <<8 x i16>> [#uses=1] + %6 = bitcast <8 x i16> %5 to <2 x double> ; <<2 x double>> [#uses=2] + %7 = extractelement <2 x double> %6, i32 0 ; [#uses=1] + %8 = bitcast double %7 to <4 x i16> ; <<4 x i16>> [#uses=1] + %9 = tail call <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16> %8) ; <<4 x i32>> [#uses=1] + %10 = extractelement <2 x double> %6, i32 1 ; [#uses=1] + %11 = bitcast double %10 to <4 x i16> ; <<4 x i16>> [#uses=1] + %12 = tail call <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16> %11) ; <<4 x i32>> [#uses=1] + %13 = mul <4 x i32> %1, %9 ; <<4 x i32>> [#uses=1] + %14 = mul <4 x i32> %3, %12 ; <<4 x i32>> [#uses=1] + %15 = tail call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %13, <4 x i32> ) ; <<4 x i16>> [#uses=1] + %16 = tail call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %14, <4 x i32> ) ; <<4 x i16>> [#uses=1] + %17 = shufflevector <4 x i16> %15, <4 x i16> %16, <8 x i32> ; <<8 x i16>> [#uses=1] + %18 = bitcast i16* %o_ptr to i8* ; [#uses=1] + tail call void @llvm.arm.neon.vst1.v8i16(i8* %18, <8 x i16> %17) + ret void +} + +define arm_apcscc void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind { +entry: +; CHECK: t2: +; CHECK: vld1.16 +; CHECK-NOT: vmov +; CHECK: vmul.i16 +; CHECK: vld1.16 +; CHECK: vst1.16 +; CHECK-NOT: vmov +; CHECK: vmul.i16 +; CHECK: vst1.16 + %0 = getelementptr inbounds %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] + %1 = load <8 x i16>* %0, align 16 ; <<8 x i16>> [#uses=1] + %2 = getelementptr inbounds %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] + %3 = load <8 x i16>* %2, align 16 ; <<8 x i16>> [#uses=1] + %4 = bitcast i16* %i_ptr to i8* ; [#uses=1] + %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4) ; <<8 x i16>> [#uses=1] + %6 = getelementptr inbounds i16* %i_ptr, i32 8 ; [#uses=1] + %7 = bitcast i16* %6 to i8* ; [#uses=1] + %8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %7) ; <<8 x i16>> [#uses=1] + %9 = mul <8 x i16> %1, %5 ; <<8 x i16>> [#uses=1] + %10 = mul <8 x i16> %3, %8 ; <<8 x i16>> [#uses=1] + %11 = bitcast i16* %o_ptr to i8* ; [#uses=1] + tail call void @llvm.arm.neon.vst1.v8i16(i8* %11, <8 x i16> %9) + %12 = getelementptr inbounds i16* %o_ptr, i32 8 ; [#uses=1] + %13 = bitcast i16* %12 to i8* ; [#uses=1] + tail call void @llvm.arm.neon.vst1.v8i16(i8* %13, <8 x i16> %10) + ret void +} + +define <8 x i8> @t3(i8* %A, i8* %B) nounwind { +; CHECK: t3: +; CHECK: vld3.8 +; CHECK: vmul.i8 +; CHECK-NOT: vmov +; CHECK: vst3.8 + %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1] + %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2 ; <<8 x i8>> [#uses=1] + %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 1 ; <<8 x i8>> [#uses=1] + %tmp5 = sub <8 x i8> %tmp3, %tmp4 + %tmp6 = add <8 x i8> %tmp2, %tmp3 ; <<8 x i8>> [#uses=1] + %tmp7 = mul <8 x i8> %tmp4, %tmp2 + tail call void @llvm.arm.neon.vst3.v8i8(i8* %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7) + ret <8 x i8> %tmp4 +} + +define arm_apcscc void @t4(i32* %in, i32* %out) nounwind { +entry: +; CHECK: t4: +; CHECK: vld2.32 +; CHECK-NOT: vmov +; CHECK: vld2.32 +; CHECK-NOT: vmov +; CHECK: bne + %tmp1 = bitcast i32* %in to i8* ; [#uses=1] + %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp1) ; <%struct.__neon_int32x4x2_t> [#uses=2] + %tmp3 = getelementptr inbounds i32* %in, i32 8 ; [#uses=1] + %tmp4 = bitcast i32* %tmp3 to i8* ; [#uses=1] + %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp4) ; <%struct.__neon_int32x4x2_t> [#uses=2] + %tmp8 = bitcast i32* %out to i8* ; [#uses=1] + br i1 undef, label %return1, label %return2 + +return1: +; CHECK: %return1 +; CHECK-NOT: vmov +; CHECK-NEXT: vadd.i32 +; CHECK-NEXT: vadd.i32 +; CHECK-NEXT: vst2.32 + %tmp52 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1] + %tmp57 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1 ; <<4 x i32>> [#uses=1] + %tmp = extractvalue %struct.__neon_int32x4x2_t %tmp5, 0 ; <<4 x i32>> [#uses=1] + %tmp39 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1] + %tmp6 = add <4 x i32> %tmp52, %tmp ; <<4 x i32>> [#uses=1] + %tmp7 = add <4 x i32> %tmp57, %tmp39 ; <<4 x i32>> [#uses=1] + tail call void @llvm.arm.neon.vst2.v4i32(i8* %tmp8, <4 x i32> %tmp6, <4 x i32> %tmp7) + ret void + +return2: +; CHECK: %return2 +; CHECK: vadd.i32 +; CHECK: vmov q1, q3 +; CHECK-NOT: vmov +; CHECK: vst2.32 {d0, d1, d2, d3} + %tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1] + %tmp101 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1] + %tmp102 = add <4 x i32> %tmp100, %tmp101 ; <<4 x i32>> [#uses=1] + tail call void @llvm.arm.neon.vst2.v4i32(i8* %tmp8, <4 x i32> %tmp102, <4 x i32> %tmp101) + call void @llvm.trap() + unreachable +} + +define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { +; CHECK: t5: +; CHECK: vldmia +; CHECK: vmov q1, q0 +; CHECK-NOT: vmov +; CHECK: vld2.16 {d0[1], d2[1]}, [r0] +; CHECK-NOT: vmov +; CHECK: vadd.i16 + %tmp0 = bitcast i16* %A to i8* ; [#uses=1] + %tmp1 = load <8 x i16>* %B ; <<8 x i16>> [#uses=2] + %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2] + %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 ; <<8 x i16>> [#uses=1] + %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 ; <<8 x i16>> [#uses=1] + %tmp5 = add <8 x i16> %tmp3, %tmp4 ; <<8 x i16>> [#uses=1] + ret <8 x i16> %tmp5 +} + +declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*) nounwind readonly + +declare <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16>) nounwind readnone + +declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone + +declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>) nounwind + +declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>) nounwind + +declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*) nounwind readonly + +declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8*) nounwind readonly + +declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32) nounwind readonly + +declare void @llvm.arm.neon.vst2.v4i32(i8*, <4 x i32>, <4 x i32>) nounwind + +declare void @llvm.trap() nounwind From criswell at cs.uiuc.edu Mon May 17 14:53:36 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Mon, 17 May 2010 14:53:36 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/index.html sva.html Message-ID: <201005171953.o4HJrawd030173@zion.cs.uiuc.edu> Changes in directory llvm-www/safecode: index.html updated: 1.29 -> 1.30 sva.html updated: 1.2 -> 1.3 --- Log message: Moved funding blurb to top page. Added MURI to funding blurb. --- Diffs of the changes: (+7 -5) index.html | 7 +++++++ sva.html | 5 ----- 2 files changed, 7 insertions(+), 5 deletions(-) Index: llvm-www/safecode/index.html diff -u llvm-www/safecode/index.html:1.29 llvm-www/safecode/index.html:1.30 --- llvm-www/safecode/index.html:1.29 Mon May 17 12:06:28 2010 +++ llvm-www/safecode/index.html Mon May 17 14:53:21 2010 @@ -84,6 +84,13 @@

    • + +

    + The SAFECode and SVA research is funded by grants from the National + Science Foundation, the DoD Multi-disciplinary University Research + Initiative (MURI), Apple Computer, Inc., and the University of + Illinois. +

    Index: llvm-www/safecode/sva.html diff -u llvm-www/safecode/sva.html:1.2 llvm-www/safecode/sva.html:1.3 --- llvm-www/safecode/sva.html:1.2 Mon May 17 13:25:18 2010 +++ llvm-www/safecode/sva.html Mon May 17 14:53:21 2010 @@ -74,11 +74,6 @@     additional instructions to provide memory safety for low-level software/hardware interactions.

    - -

    - The SVA research group is funded by grants from the National Science - Foundation, Apple Computer, Inc., and the University of Illinois. -

    From stoklund at 2pi.dk Mon May 17 15:01:22 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 17 May 2010 20:01:22 -0000 Subject: [llvm-commits] [llvm] r103961 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp Message-ID: <20100517200122.A1EC7312800A@llvm.org> Author: stoklund Date: Mon May 17 15:01:22 2010 New Revision: 103961 URL: http://llvm.org/viewvc/llvm-project?rev=103961&view=rev Log: Remove debug option. Add comment on spill order determinism. Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=103961&r1=103960&r2=103961&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Mon May 17 15:01:22 2010 @@ -35,9 +35,6 @@ #include using namespace llvm; -static cl::opt VerifyFastRegalloc("verify-fast-regalloc", cl::Hidden, - cl::desc("Verify machine code before fast regalloc")); - STATISTIC(NumStores, "Number of stores added"); STATISTIC(NumLoads , "Number of loads added"); STATISTIC(NumCopies, "Number of copies coalesced"); @@ -269,8 +266,10 @@ void RAFast::spillAll(MachineInstr *MI) { if (LiveVirtRegs.empty()) return; isBulkSpilling = true; - for (LiveRegMap::iterator i = LiveVirtRegs.begin(), - e = LiveVirtRegs.end(); i != e; ++i) + // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order + // of spilling here is deterministic, if arbitrary. + for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end(); + i != e; ++i) spillVirtReg(MI, i); LiveVirtRegs.clear(); isBulkSpilling = false; @@ -796,8 +795,6 @@ DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n" << "********** Function: " << ((Value*)Fn.getFunction())->getName() << '\n'); - if (VerifyFastRegalloc) - Fn.verify(this, true); MF = &Fn; MRI = &MF->getRegInfo(); TM = &Fn.getTarget(); From stoklund at 2pi.dk Mon May 17 15:01:24 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 17 May 2010 20:01:24 -0000 Subject: [llvm-commits] [llvm] r103962 - /llvm/trunk/include/llvm/ADT/DenseMap.h Message-ID: <20100517200125.065083128018@llvm.org> Author: stoklund Date: Mon May 17 15:01:24 2010 New Revision: 103962 URL: http://llvm.org/viewvc/llvm-project?rev=103962&view=rev Log: Optimize empty DenseMap iteration. Modified: llvm/trunk/include/llvm/ADT/DenseMap.h Modified: llvm/trunk/include/llvm/ADT/DenseMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/DenseMap.h?rev=103962&r1=103961&r2=103962&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/DenseMap.h (original) +++ llvm/trunk/include/llvm/ADT/DenseMap.h Mon May 17 15:01:24 2010 @@ -79,13 +79,14 @@ typedef DenseMapIterator const_iterator; inline iterator begin() { - return iterator(Buckets, Buckets+NumBuckets); + // When the map is empty, avoid the overhead of AdvancePastEmptyBuckets(). + return empty() ? end() : iterator(Buckets, Buckets+NumBuckets); } inline iterator end() { return iterator(Buckets+NumBuckets, Buckets+NumBuckets); } inline const_iterator begin() const { - return const_iterator(Buckets, Buckets+NumBuckets); + return empty() ? end() : const_iterator(Buckets, Buckets+NumBuckets); } inline const_iterator end() const { return const_iterator(Buckets+NumBuckets, Buckets+NumBuckets); From daniel at zuster.org Mon May 17 15:12:31 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 17 May 2010 20:12:31 -0000 Subject: [llvm-commits] [llvm] r103964 - in /llvm/trunk: lib/MC/MCMachOStreamer.cpp test/MC/MachO/symbol-flags.s Message-ID: <20100517201231.748DB312800A@llvm.org> Author: ddunbar Date: Mon May 17 15:12:31 2010 New Revision: 103964 URL: http://llvm.org/viewvc/llvm-project?rev=103964&view=rev Log: MC/Mach-O: Fix some differences in symbol flag handling. - Don't clear weak reference flag, 'as' was only "trying" to do this, it wasn't actually succeeding. - Clear the "lazy bound" bit when we mark something external. This corresponds roughly to the lazy clearing of the bit that 'as' implements in symbol_table_lookup. - The exact meaning of these flags appears pretty loose, since 'as' isn't very consistent. For now we just try to match 'as', we will clean this up one day hopefully. Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp llvm/trunk/test/MC/MachO/symbol-flags.s Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=103964&r1=103963&r2=103964&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Mon May 17 15:12:31 2010 @@ -192,8 +192,14 @@ SD.setFragment(F); SD.setOffset(F->getContents().size()); - // This causes the reference type and weak reference flags to be cleared. - SD.setFlags(SD.getFlags() & ~(SF_WeakReference | SF_ReferenceTypeMask)); + // This causes the reference type flag to be cleared. Darwin 'as' was "trying" + // to clear the weak reference and weak definition bits too, but the + // implementation was buggy. For now we just try to match 'as', for + // diffability. + // + // FIXME: Cleanup this code, these bits should be emitted based on semantic + // properties, not on the order of definition, etc. + SD.setFlags(SD.getFlags() & ~SF_ReferenceTypeMask); Symbol->setSection(*CurSection); } @@ -257,6 +263,13 @@ case MCSA_Global: SD.setExternal(true); + // This effectively clears the undefined lazy bit, in Darwin 'as', although + // it isn't very consistent because it implements this as part of symbol + // lookup. + // + // FIXME: Cleanup this code, these bits should be emitted based on semantic + // properties, not on the order of definition, etc. + SD.setFlags(SD.getFlags() & ~SF_ReferenceTypeUndefinedLazy); break; case MCSA_LazyReference: Modified: llvm/trunk/test/MC/MachO/symbol-flags.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/symbol-flags.s?rev=103964&r1=103963&r2=103964&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/symbol-flags.s (original) +++ llvm/trunk/test/MC/MachO/symbol-flags.s Mon May 17 15:12:31 2010 @@ -5,6 +5,10 @@ sym_ref_def_A: sym_ref_def_C: .reference sym_ref_def_C + .reference sym_ref_def_D + .globl sym_ref_def_D + .globl sym_ref_def_E + .reference sym_ref_def_E .weak_reference sym_weak_ref_A .weak_reference sym_weak_ref_def_A @@ -16,12 +20,22 @@ .globl sym_weak_def_A .weak_definition sym_weak_def_A sym_weak_def_A: +sym_weak_def_B: + .weak_definition sym_weak_def_B + .globl sym_weak_def_B + .weak_definition sym_weak_def_C +sym_weak_def_C: + .globl sym_weak_def_C .lazy_reference sym_lazy_ref_A .lazy_reference sym_lazy_ref_B sym_lazy_ref_B: sym_lazy_ref_C: .lazy_reference sym_lazy_ref_C + .lazy_reference sym_lazy_ref_D + .globl sym_lazy_ref_D + .globl sym_lazy_ref_E + .lazy_reference sym_lazy_ref_E .private_extern sym_private_ext_A .private_extern sym_private_ext_B @@ -30,6 +44,8 @@ .private_extern sym_private_ext_C .private_extern sym_private_ext_D .globl sym_private_ext_D + .globl sym_private_ext_E + .private_extern sym_private_ext_E .no_dead_strip sym_no_dead_strip_A @@ -39,7 +55,7 @@ .desc sym_desc_flags,0x47 sym_desc_flags: - + // CHECK: ('cputype', 7) // CHECK: ('cpusubtype', 3) // CHECK: ('filetype', 1) @@ -73,6 +89,8 @@ // CHECK: ('reserved1', 0) // CHECK: ('reserved2', 0) // CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) // CHECK: # Section 1 // CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -86,19 +104,21 @@ // CHECK: ('reserved1', 0) // CHECK: ('reserved2', 0) // CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 // CHECK: (('command', 2) // CHECK: ('size', 24) // CHECK: ('symoff', 324) -// CHECK: ('nsyms', 16) -// CHECK: ('stroff', 516) -// CHECK: ('strsize', 260) -// CHECK: ('_string_data', '\x00sym_ref_A\x00sym_weak_ref_A\x00sym_weak_def_A\x00sym_lazy_ref_A\x00sym_private_ext_A\x00sym_private_ext_B\x00sym_private_ext_C\x00sym_private_ext_D\x00sym_no_dead_strip_A\x00sym_ref_def_A\x00sym_ref_def_C\x00sym_weak_ref_def_A\x00sym_weak_ref_def_B\x00sym_lazy_ref_B\x00sym_lazy_ref_C\x00sym_desc_flags\x00\x00') +// CHECK: ('nsyms', 23) +// CHECK: ('stroff', 600) +// CHECK: ('strsize', 368) +// CHECK: ('_string_data', '\x00sym_ref_A\x00sym_ref_def_D\x00sym_ref_def_E\x00sym_weak_ref_A\x00sym_weak_def_A\x00sym_weak_def_B\x00sym_weak_def_C\x00sym_lazy_ref_A\x00sym_lazy_ref_D\x00sym_lazy_ref_E\x00sym_private_ext_A\x00sym_private_ext_B\x00sym_private_ext_C\x00sym_private_ext_D\x00sym_private_ext_E\x00sym_no_dead_strip_A\x00sym_ref_def_A\x00sym_ref_def_C\x00sym_weak_ref_def_A\x00sym_weak_ref_def_B\x00sym_lazy_ref_B\x00sym_lazy_ref_C\x00sym_desc_flags\x00\x00\x00\x00') // CHECK: ('_symbols', [ // CHECK: # Symbol 0 -// CHECK: (('n_strx', 148) +// CHECK: (('n_strx', 254) // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 1) // CHECK: ('n_desc', 32) @@ -106,7 +126,7 @@ // CHECK: ('_string', 'sym_ref_def_A') // CHECK: ), // CHECK: # Symbol 1 -// CHECK: (('n_strx', 162) +// CHECK: (('n_strx', 268) // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 1) // CHECK: ('n_desc', 32) @@ -114,15 +134,15 @@ // CHECK: ('_string', 'sym_ref_def_C') // CHECK: ), // CHECK: # Symbol 2 -// CHECK: (('n_strx', 176) +// CHECK: (('n_strx', 282) // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 1) -// CHECK: ('n_desc', 0) +// CHECK: ('n_desc', 64) // CHECK: ('n_value', 0) // CHECK: ('_string', 'sym_weak_ref_def_A') // CHECK: ), // CHECK: # Symbol 3 -// CHECK: (('n_strx', 195) +// CHECK: (('n_strx', 301) // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 1) // CHECK: ('n_desc', 0) @@ -130,7 +150,7 @@ // CHECK: ('_string', 'sym_weak_ref_def_B') // CHECK: ), // CHECK: # Symbol 4 -// CHECK: (('n_strx', 214) +// CHECK: (('n_strx', 320) // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 32) @@ -138,7 +158,7 @@ // CHECK: ('_string', 'sym_lazy_ref_B') // CHECK: ), // CHECK: # Symbol 5 -// CHECK: (('n_strx', 229) +// CHECK: (('n_strx', 335) // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 32) @@ -146,15 +166,15 @@ // CHECK: ('_string', 'sym_lazy_ref_C') // CHECK: ), // CHECK: # Symbol 6 -// CHECK: (('n_strx', 244) +// CHECK: (('n_strx', 350) // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 2) -// CHECK: ('n_desc', 0) +// CHECK: ('n_desc', 64) // CHECK: ('n_value', 0) // CHECK: ('_string', 'sym_desc_flags') // CHECK: ), // CHECK: # Symbol 7 -// CHECK: (('n_strx', 74) +// CHECK: (('n_strx', 162) // CHECK: ('n_type', 0x1f) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 0) @@ -162,7 +182,7 @@ // CHECK: ('_string', 'sym_private_ext_B') // CHECK: ), // CHECK: # Symbol 8 -// CHECK: (('n_strx', 92) +// CHECK: (('n_strx', 180) // CHECK: ('n_type', 0x1f) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 0) @@ -170,7 +190,7 @@ // CHECK: ('_string', 'sym_private_ext_C') // CHECK: ), // CHECK: # Symbol 9 -// CHECK: (('n_strx', 26) +// CHECK: (('n_strx', 54) // CHECK: ('n_type', 0xf) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 128) @@ -178,38 +198,78 @@ // CHECK: ('_string', 'sym_weak_def_A') // CHECK: ), // CHECK: # Symbol 10 -// CHECK: (('n_strx', 41) +// CHECK: (('n_strx', 69) +// CHECK: ('n_type', 0xf) +// CHECK: ('n_sect', 2) +// CHECK: ('n_desc', 128) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'sym_weak_def_B') +// CHECK: ), +// CHECK: # Symbol 11 +// CHECK: (('n_strx', 84) +// CHECK: ('n_type', 0xf) +// CHECK: ('n_sect', 2) +// CHECK: ('n_desc', 128) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'sym_weak_def_C') +// CHECK: ), +// CHECK: # Symbol 12 +// CHECK: (('n_strx', 99) // CHECK: ('n_type', 0x1) // CHECK: ('n_sect', 0) // CHECK: ('n_desc', 33) // CHECK: ('n_value', 0) // CHECK: ('_string', 'sym_lazy_ref_A') // CHECK: ), -// CHECK: # Symbol 11 -// CHECK: (('n_strx', 128) +// CHECK: # Symbol 13 +// CHECK: (('n_strx', 114) +// CHECK: ('n_type', 0x1) +// CHECK: ('n_sect', 0) +// CHECK: ('n_desc', 32) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'sym_lazy_ref_D') +// CHECK: ), +// CHECK: # Symbol 14 +// CHECK: (('n_strx', 129) +// CHECK: ('n_type', 0x1) +// CHECK: ('n_sect', 0) +// CHECK: ('n_desc', 33) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'sym_lazy_ref_E') +// CHECK: ), +// CHECK: # Symbol 15 +// CHECK: (('n_strx', 234) // CHECK: ('n_type', 0x1) // CHECK: ('n_sect', 0) // CHECK: ('n_desc', 32) // CHECK: ('n_value', 0) // CHECK: ('_string', 'sym_no_dead_strip_A') // CHECK: ), -// CHECK: # Symbol 12 -// CHECK: (('n_strx', 56) +// CHECK: # Symbol 16 +// CHECK: (('n_strx', 144) // CHECK: ('n_type', 0x11) // CHECK: ('n_sect', 0) // CHECK: ('n_desc', 0) // CHECK: ('n_value', 0) // CHECK: ('_string', 'sym_private_ext_A') // CHECK: ), -// CHECK: # Symbol 13 -// CHECK: (('n_strx', 110) +// CHECK: # Symbol 17 +// CHECK: (('n_strx', 198) // CHECK: ('n_type', 0x11) // CHECK: ('n_sect', 0) // CHECK: ('n_desc', 0) // CHECK: ('n_value', 0) // CHECK: ('_string', 'sym_private_ext_D') // CHECK: ), -// CHECK: # Symbol 14 +// CHECK: # Symbol 18 +// CHECK: (('n_strx', 216) +// CHECK: ('n_type', 0x11) +// CHECK: ('n_sect', 0) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'sym_private_ext_E') +// CHECK: ), +// CHECK: # Symbol 19 // CHECK: (('n_strx', 1) // CHECK: ('n_type', 0x1) // CHECK: ('n_sect', 0) @@ -217,10 +277,26 @@ // CHECK: ('n_value', 0) // CHECK: ('_string', 'sym_ref_A') // CHECK: ), -// CHECK: # Symbol 15 +// CHECK: # Symbol 20 // CHECK: (('n_strx', 11) // CHECK: ('n_type', 0x1) // CHECK: ('n_sect', 0) +// CHECK: ('n_desc', 32) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'sym_ref_def_D') +// CHECK: ), +// CHECK: # Symbol 21 +// CHECK: (('n_strx', 25) +// CHECK: ('n_type', 0x1) +// CHECK: ('n_sect', 0) +// CHECK: ('n_desc', 32) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'sym_ref_def_E') +// CHECK: ), +// CHECK: # Symbol 22 +// CHECK: (('n_strx', 39) +// CHECK: ('n_type', 0x1) +// CHECK: ('n_sect', 0) // CHECK: ('n_desc', 64) // CHECK: ('n_value', 0) // CHECK: ('_string', 'sym_weak_ref_A') @@ -233,9 +309,9 @@ // CHECK: ('ilocalsym', 0) // CHECK: ('nlocalsym', 7) // CHECK: ('iextdefsym', 7) -// CHECK: ('nextdefsym', 3) -// CHECK: ('iundefsym', 10) -// CHECK: ('nundefsym', 6) +// CHECK: ('nextdefsym', 5) +// CHECK: ('iundefsym', 12) +// CHECK: ('nundefsym', 11) // CHECK: ('tocoff', 0) // CHECK: ('ntoc', 0) // CHECK: ('modtaboff', 0) From baldrick at free.fr Mon May 17 15:20:47 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 17 May 2010 20:20:47 -0000 Subject: [llvm-commits] [dragonegg] r103967 - /dragonegg/trunk/llvm-types.cpp Message-ID: <20100517202047.2AC35312800A@llvm.org> Author: baldrick Date: Mon May 17 15:20:46 2010 New Revision: 103967 URL: http://llvm.org/viewvc/llvm-project?rev=103967&view=rev Log: Port commit 100721 (stoklund) from llvm-gcc: Create larger struct fields for consecutive bitfields. (Again). When creating an LLVM struct type for a struct with bitfields, try to allocate integer fields that are as large as possible, taking the following bitfields into account. For example, this struct: struct S { int a, b; void *c; unsigned d : 8; unsigned e : 8; }; used to be: %struct.S = type { i32, i32, i8*, i8, i8 }, but now it becomes: %struct.S = type { i32, i32, i8*, i16 } This makes it easier for the code generator to shuffle register sized bitfield groups around in fewer registers. It also means that it is harder for SROA to isolate bit fields as scalars. The larger struct fields are only produced when they would be properly aligned and smaller than the natural machine word size. This strategy is similar to what clang will be doing. We will see how it works out. Modified: dragonegg/trunk/llvm-types.cpp Modified: dragonegg/trunk/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-types.cpp?rev=103967&r1=103966&r2=103967&view=diff ============================================================================== --- dragonegg/trunk/llvm-types.cpp (original) +++ dragonegg/trunk/llvm-types.cpp Mon May 17 15:20:46 2010 @@ -1507,7 +1507,8 @@ return getFieldEndOffsetInBytes(ElementOffsetInBytes.size()-1); } - void addNewBitField(uint64_t Size, uint64_t FirstUnallocatedByte); + void addNewBitField(uint64_t Size, uint64_t Extra, + uint64_t FirstUnallocatedByte); void dump() const; }; @@ -1515,22 +1516,43 @@ // Add new element which is a bit field. Size is not the size of bit field, // but size of bits required to determine type of new Field which will be // used to access this bit field. -void StructTypeConversionInfo::addNewBitField(uint64_t Size, +// If possible, allocate a field with room for Size+Extra bits. +void StructTypeConversionInfo::addNewBitField(uint64_t Size, uint64_t Extra, uint64_t FirstUnallocatedByte) { // Figure out the LLVM type that we will use for the new field. // Note, Size is not necessarily size of the new field. It indicates // additional bits required after FirstunallocatedByte to cover new field. - const Type *NewFieldTy; - if (Size <= 8) - NewFieldTy = Type::getInt8Ty(Context); - else if (Size <= 16) - NewFieldTy = Type::getInt16Ty(Context); - else if (Size <= 32) - NewFieldTy = Type::getInt32Ty(Context); - else { - assert(Size <= 64 && "Bitfield too large!"); - NewFieldTy = Type::getInt64Ty(Context); + const Type *NewFieldTy = 0; + + // First try an ABI-aligned field including (some of) the Extra bits. + // This field must satisfy Size <= w && w <= XSize. + uint64_t XSize = Size + Extra; + for (unsigned w = NextPowerOf2(std::min(UINT64_C(64), XSize))/2; + w >= Size && w >= 8; w /= 2) { + if (TD.isIllegalInteger(w)) + continue; + // Would a w-sized integer field be aligned here? + const unsigned a = TD.getABIIntegerTypeAlignment(w); + if (FirstUnallocatedByte & (a-1) || a > getGCCStructAlignmentInBytes()) + continue; + // OK, use w-sized integer. + NewFieldTy = IntegerType::get(Context, w); + break; + } + + // Try an integer field that holds Size bits. + if (!NewFieldTy) { + if (Size <= 8) + NewFieldTy = Type::getInt8Ty(Context); + else if (Size <= 16) + NewFieldTy = Type::getInt16Ty(Context); + else if (Size <= 32) + NewFieldTy = Type::getInt32Ty(Context); + else { + assert(Size <= 64 && "Bitfield too large!"); + NewFieldTy = Type::getInt64Ty(Context); + } } // Check that the alignment of NewFieldTy won't cause a gap in the structure! @@ -1707,7 +1729,34 @@ // LLVM struct such that there are no holes in the struct where the bitfield // is: these holes would make it impossible to statically initialize a global // of this type that has an initializer for the bitfield. - + + // We want the integer-typed fields as large as possible up to the machine + // word size. If there are more bitfields following this one, try to include + // them in the same field. + + // Calculate the total number of bits in the continuous group of bitfields + // following this one. This is the number of bits that addNewBitField should + // try to include. + unsigned ExtraSizeInBits = 0; + tree LastBitField = 0; + for (tree f = TREE_CHAIN(Field); f; f = TREE_CHAIN(f)) { + if (TREE_CODE(f) != FIELD_DECL || + TREE_CODE(DECL_FIELD_OFFSET(f)) != INTEGER_CST) + break; + if (isBitfield(f)) + LastBitField = f; + else { + // We can use all this bits up to the next non-bitfield. + LastBitField = 0; + ExtraSizeInBits = getFieldOffsetInBits(f) - EndBitOffset; + break; + } + } + // Record ended in a bitfield? Use all of the last byte. + if (LastBitField) + ExtraSizeInBits = RoundUpToAlignment(getFieldOffsetInBits(LastBitField) + + TREE_INT_CST_LOW(DECL_SIZE(LastBitField)), 8) - EndBitOffset; + // Compute the number of bits that we need to add to this struct to cover // this field. uint64_t FirstUnallocatedByte = Info.getEndUnallocatedByte(); @@ -1721,7 +1770,7 @@ // This field starts at byte boundry. Need to allocate space // for additional bytes not yet allocated. unsigned NumBitsToAdd = FieldSizeInBits - AvailableBits; - Info.addNewBitField(NumBitsToAdd, FirstUnallocatedByte); + Info.addNewBitField(NumBitsToAdd, ExtraSizeInBits, FirstUnallocatedByte); return; } @@ -1745,7 +1794,7 @@ for (unsigned idx = 0; idx < (prevFieldTypeSizeInBits/8); ++idx) FirstUnallocatedByte--; } - Info.addNewBitField(NumBitsRequired, FirstUnallocatedByte); + Info.addNewBitField(NumBitsRequired, ExtraSizeInBits, FirstUnallocatedByte); // Do this after adding Field. Info.lastFieldStartsAtNonByteBoundry(true); return; @@ -1779,7 +1828,7 @@ } // Now, Field starts at FirstUnallocatedByte and everything is aligned. - Info.addNewBitField(FieldSizeInBits, FirstUnallocatedByte); + Info.addNewBitField(FieldSizeInBits, ExtraSizeInBits, FirstUnallocatedByte); } /// UnionHasOnlyZeroOffsets - Check if a union type has only members with @@ -1857,7 +1906,7 @@ if (isBitfield(UnionField)) { unsigned FieldSizeInBits = TREE_INT_CST_LOW(DECL_SIZE(UnionField)); - Info.addNewBitField(FieldSizeInBits, 0); + Info.addNewBitField(FieldSizeInBits, 0, 0); } else { Info.allFieldsAreNotBitFields(); Info.addElement(UnionTy, 0, Info.getTypeSize(UnionTy)); From bob.wilson at apple.com Mon May 17 15:31:13 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 17 May 2010 20:31:13 -0000 Subject: [llvm-commits] [llvm] r103969 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <20100517203113.9BBEE312800A@llvm.org> Author: bwilson Date: Mon May 17 15:31:13 2010 New Revision: 103969 URL: http://llvm.org/viewvc/llvm-project?rev=103969&view=rev Log: Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests. Obvious in retrospect but not fun to debug. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=103969&r1=103968&r2=103969&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon May 17 15:31:13 2010 @@ -423,7 +423,7 @@ // binutils let isBarrier = 1, isTerminator = 1 in def tTRAP : TI<(outs), (ins), IIC_Br, - ".word 0xdefe ${:comment} trap", [(trap)]>, Encoding16 { + ".short 0xdefe ${:comment} trap", [(trap)]>, Encoding16 { let Inst{15-12} = 0b1101; let Inst{11-8} = 0b1110; } From evan.cheng at apple.com Mon May 17 15:57:12 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 17 May 2010 20:57:12 -0000 Subject: [llvm-commits] [llvm] r103971 - in /llvm/trunk: lib/CodeGen/TwoAddressInstructionPass.cpp test/CodeGen/ARM/reg_sequence.ll Message-ID: <20100517205713.0846F312800A@llvm.org> Author: evancheng Date: Mon May 17 15:57:12 2010 New Revision: 103971 URL: http://llvm.org/viewvc/llvm-project?rev=103971&view=rev Log: Careful with reg_sequence coalescing to not to overwrite sub-register indices. Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=103971&r1=103970&r2=103971&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original) +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Mon May 17 15:57:12 2010 @@ -128,6 +128,8 @@ void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB, SmallPtrSet &Processed); + void CoalesceExtSubRegs(SmallVector &Srcs, unsigned DstReg); + /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part /// of the de-ssa process. This replaces sources of REG_SEQUENCE as /// sub-register references of the register defined by REG_SEQUENCE. @@ -1132,7 +1134,7 @@ } static void UpdateRegSequenceSrcs(unsigned SrcReg, - unsigned DstReg, unsigned SrcIdx, + unsigned DstReg, unsigned SubIdx, MachineRegisterInfo *MRI) { for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg), RE = MRI->reg_end(); RI != RE; ) { @@ -1140,7 +1142,77 @@ ++RI; MO.setReg(DstReg); assert(MO.getSubReg() == 0); - MO.setSubReg(SrcIdx); + MO.setSubReg(SubIdx); + } +} + +/// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are +/// EXTRACT_SUBREG from the same register and to the same virtual register +/// with different sub-register indices, attempt to combine the +/// EXTRACT_SUBREGs and pre-coalesce them. e.g. +/// %reg1026 = VLDMQ %reg1025, 260, pred:14, pred:%reg0 +/// %reg1029:6 = EXTRACT_SUBREG %reg1026, 6 +/// %reg1029:5 = EXTRACT_SUBREG %reg1026, 5 +/// Since D subregs 5, 6 can combine to a Q register, we can coalesce +/// reg1026 to reg1029. +void +TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector &Srcs, + unsigned DstReg) { + SmallSet Seen; + for (unsigned i = 0, e = Srcs.size(); i != e; ++i) { + unsigned SrcReg = Srcs[i]; + if (!Seen.insert(SrcReg)) + continue; + + // If there are no other uses than extract_subreg which feed into + // the reg_sequence, then we might be able to coalesce them. + bool CanCoalesce = true; + SmallVector SubIndices; + for (MachineRegisterInfo::use_nodbg_iterator + UI = MRI->use_nodbg_begin(SrcReg), + UE = MRI->use_nodbg_end(); UI != UE; ++UI) { + MachineInstr *UseMI = &*UI; + if (!UseMI->isExtractSubreg() || + UseMI->getOperand(0).getReg() != DstReg) { + CanCoalesce = false; + break; + } + SubIndices.push_back(UseMI->getOperand(2).getImm()); + } + + if (!CanCoalesce || SubIndices.size() < 2) + continue; + + std::sort(SubIndices.begin(), SubIndices.end()); + unsigned NewSubIdx = 0; + if (TRI->canCombinedSubRegIndex(MRI->getRegClass(SrcReg), SubIndices, + NewSubIdx)) { + bool Proceed = true; + if (NewSubIdx) + for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg), + RE = MRI->reg_end(); RI != RE; ) { + MachineOperand &MO = RI.getOperand(); + ++RI; + // FIXME: If the sub-registers do not combine to the whole + // super-register, i.e. NewSubIdx != 0, and any of the use has a + // sub-register index, then abort the coalescing attempt. + if (MO.getSubReg()) { + Proceed = false; + break; + } + MO.setReg(DstReg); + MO.setSubReg(NewSubIdx); + } + if (Proceed) + for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg), + RE = MRI->reg_end(); RI != RE; ) { + MachineOperand &MO = RI.getOperand(); + ++RI; + MO.setReg(DstReg); + if (NewSubIdx) + MO.setSubReg(NewSubIdx); + } + } } } @@ -1221,50 +1293,15 @@ for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { unsigned SrcReg = MI->getOperand(i).getReg(); - unsigned SrcIdx = MI->getOperand(i+1).getImm(); - UpdateRegSequenceSrcs(SrcReg, DstReg, SrcIdx, MRI); + unsigned SubIdx = MI->getOperand(i+1).getImm(); + UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI); } DEBUG(dbgs() << "Eliminated: " << *MI); MI->eraseFromParent(); // Try coalescing some EXTRACT_SUBREG instructions. - Seen.clear(); - for (unsigned i = 0, e = RealSrcs.size(); i != e; ++i) { - unsigned SrcReg = RealSrcs[i]; - if (!Seen.insert(SrcReg)) - continue; - - // If there are no other uses than extract_subreg which feed into - // the reg_sequence, then we might be able to coalesce them. - bool CanCoalesce = true; - SmallVector SubIndices; - for (MachineRegisterInfo::use_nodbg_iterator - UI = MRI->use_nodbg_begin(SrcReg), - UE = MRI->use_nodbg_end(); UI != UE; ++UI) { - MachineInstr *UseMI = &*UI; - if (!UseMI->isExtractSubreg() || - UseMI->getOperand(0).getReg() != DstReg) { - CanCoalesce = false; - break; - } - SubIndices.push_back(UseMI->getOperand(2).getImm()); - } - - if (!CanCoalesce) - continue; - - // %reg1026 = VLDMQ %reg1025, 260, pred:14, pred:%reg0 - // %reg1029:6 = EXTRACT_SUBREG %reg1026, 6 - // %reg1029:5 = EXTRACT_SUBREG %reg1026, 5 - // Since D subregs 5, 6 can combine to a Q register, we can coalesce - // reg1026 to reg1029. - std::sort(SubIndices.begin(), SubIndices.end()); - unsigned NewSubIdx = 0; - if (TRI->canCombinedSubRegIndex(MRI->getRegClass(SrcReg), SubIndices, - NewSubIdx)) - UpdateRegSequenceSrcs(SrcReg, DstReg, NewSubIdx, MRI); - } + CoalesceExtSubRegs(RealSrcs, DstReg); } RegSequences.clear(); Modified: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=103971&r1=103970&r2=103971&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (original) +++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Mon May 17 15:57:12 2010 @@ -3,6 +3,7 @@ %struct.int16x8_t = type { <8 x i16> } %struct.int32x4_t = type { <4 x i32> } +%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> } %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } %struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> } %struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> } @@ -149,12 +150,51 @@ ret <8 x i16> %tmp5 } +define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { +; CHECK: t6: +; CHECK: vldr.64 +; CHECK: vmov d1, d0 +; CHECK-NEXT: vld2.8 {d0[1], d1[1]} + %tmp1 = load <8 x i8>* %B ; <<8 x i8>> [#uses=2] + %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2] + %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1] + %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 ; <<8 x i8>> [#uses=1] + %tmp5 = add <8 x i8> %tmp3, %tmp4 ; <<8 x i8>> [#uses=1] + ret <8 x i8> %tmp5 +} + +define arm_apcscc void @t7(i32* %iptr, i32* %optr) nounwind { +entry: +; CHECK: t7: +; CHECK: vld2.32 +; CHECK: vst2.32 +; CHECK: vld1.32 {d0, d1}, +; CHECK: vmov q1, q0 +; CHECK-NOT: vmov +; CHECK: vuzp.32 q0, q1 +; CHECK: vst1.32 + %0 = bitcast i32* %iptr to i8* ; [#uses=2] + %1 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %0) ; <%struct.__neon_int32x4x2_t> [#uses=2] + %tmp57 = extractvalue %struct.__neon_int32x4x2_t %1, 0 ; <<4 x i32>> [#uses=1] + %tmp60 = extractvalue %struct.__neon_int32x4x2_t %1, 1 ; <<4 x i32>> [#uses=1] + %2 = bitcast i32* %optr to i8* ; [#uses=2] + tail call void @llvm.arm.neon.vst2.v4i32(i8* %2, <4 x i32> %tmp57, <4 x i32> %tmp60) + %3 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %0) ; <<4 x i32>> [#uses=1] + %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> ; <<4 x i32>> [#uses=1] + tail call void @llvm.arm.neon.vst1.v4i32(i8* %2, <4 x i32> %4) + ret void +} + +declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*) nounwind readonly + declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*) nounwind readonly declare <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16>) nounwind readnone declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone +declare void @llvm.arm.neon.vst1.v4i32(i8*, <4 x i32>) nounwind + declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>) nounwind declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>) nounwind @@ -163,6 +203,8 @@ declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8*) nounwind readonly +declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind readonly + declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32) nounwind readonly declare void @llvm.arm.neon.vst2.v4i32(i8*, <4 x i32>, <4 x i32>) nounwind From echristo at apple.com Mon May 17 16:02:07 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 17 May 2010 21:02:07 -0000 Subject: [llvm-commits] [llvm] r103974 - in /llvm/trunk: include/llvm/CodeGen/TargetLoweringObjectFileImpl.h include/llvm/MC/MCSectionMachO.h lib/CodeGen/TargetLoweringObjectFileImpl.cpp lib/MC/MCSectionMachO.cpp lib/Target/X86/X86AsmBackend.cpp Message-ID: <20100517210208.018D2312800A@llvm.org> Author: echristo Date: Mon May 17 16:02:07 2010 New Revision: 103974 URL: http://llvm.org/viewvc/llvm-project?rev=103974&view=rev Log: Add some section and constant support for darwin TLS. Modified: llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h llvm/trunk/include/llvm/MC/MCSectionMachO.h llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp llvm/trunk/lib/MC/MCSectionMachO.cpp llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Modified: llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h?rev=103974&r1=103973&r2=103974&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h (original) +++ llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h Mon May 17 16:02:07 2010 @@ -84,6 +84,19 @@ class TargetLoweringObjectFileMachO : public TargetLoweringObjectFile { + /// TLSDataSection - Section directive for Thread Local data. + /// + const MCSection *TLSDataSection; // Defaults to ".tdata". + + /// TLSBSSSection - Section directive for Thread Local uninitialized data. + /// + const MCSection *TLSBSSSection; // Defaults to ".tbss". + + /// TLSTLVSection - Section directive for Thread Local structure infomation. + /// Contains the source code name of the variable, visibility and a pointer + /// to the initial value (.tdata or .tbss). + const MCSection *TLSTLVSection; // Defaults to ".tlv". + const MCSection *CStringSection; const MCSection *UStringSection; const MCSection *TextCoalSection; Modified: llvm/trunk/include/llvm/MC/MCSectionMachO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSectionMachO.h?rev=103974&r1=103973&r2=103974&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSectionMachO.h (original) +++ llvm/trunk/include/llvm/MC/MCSectionMachO.h Mon May 17 16:02:07 2010 @@ -87,8 +87,20 @@ /// S_LAZY_DYLIB_SYMBOL_POINTERS - Section with lazy symbol pointers to /// lazy loaded dylibs. S_LAZY_DYLIB_SYMBOL_POINTERS = 0x10U, + /// S_THREAD_LOCAL_REGULAR - Section with .... + S_THREAD_LOCAL_REGULAR = 0x11U, + /// S_THREAD_LOCAL_ZEROFILL - Thread local zerofill section. + S_THREAD_LOCAL_ZEROFILL = 0x12U, + /// S_THREAD_LOCAL_VARIABLES - Section with thread local variable structure + /// data. + S_THREAD_LOCAL_VARIABLES = 0x13U, + /// S_THREAD_LOCAL_VARIABLE_POINTERS - Section with .... + S_THREAD_LOCAL_VARIABLE_POINTERS = 0x14U, + /// S_THREAD_LOCAL_INIT_FUNCTION_POINTERS - Section with thread local + /// variable initialization pointers to functions. + S_THREAD_LOCAL_INIT_FUNCTION_POINTERS = 0x15, - LAST_KNOWN_SECTION_TYPE = S_LAZY_DYLIB_SYMBOL_POINTERS, + LAST_KNOWN_SECTION_TYPE = S_THREAD_LOCAL_INIT_FUNCTION_POINTERS, // Valid section attributes. Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=103974&r1=103973&r2=103974&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Mon May 17 16:02:07 2010 @@ -461,6 +461,20 @@ = getContext().getMachOSection("__DATA", "__data", 0, SectionKind::getDataRel()); + TLSDataSection // .tdata + = getContext().getMachOSection("__DATA", "__thread_data", + MCSectionMachO::S_THREAD_LOCAL_REGULAR, + SectionKind::getDataRel()); + TLSBSSSection // .tbss + = getContext().getMachOSection("__DATA", "__thread_bss", + MCSectionMachO::S_THREAD_LOCAL_ZEROFILL, + SectionKind::getThreadBSS()); + + // TODO: Verify datarel below. + TLSTLVSection // .tlv + = getContext().getMachOSection("__DATA", "__thread_vars", + MCSectionMachO::S_THREAD_LOCAL_VARIABLES, + SectionKind::getDataRel()); CStringSection // .cstring = getContext().getMachOSection("__TEXT", "__cstring", MCSectionMachO::S_CSTRING_LITERALS, @@ -646,7 +660,7 @@ const MCSection *TargetLoweringObjectFileMachO:: SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, - Mangler *Mang, const TargetMachine &TM) const { + Mangler *Mang, const TargetMachine &TM) const { assert(!Kind.isThreadLocal() && "Darwin doesn't support TLS"); if (Kind.isText()) Modified: llvm/trunk/lib/MC/MCSectionMachO.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCSectionMachO.cpp?rev=103974&r1=103973&r2=103974&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCSectionMachO.cpp (original) +++ llvm/trunk/lib/MC/MCSectionMachO.cpp Mon May 17 16:02:07 2010 @@ -34,7 +34,14 @@ { "interposing", "S_INTERPOSING" }, // 0x0D { "16byte_literals", "S_16BYTE_LITERALS" }, // 0x0E { 0, /*FIXME??*/ "S_DTRACE_DOF" }, // 0x0F - { 0, /*FIXME??*/ "S_LAZY_DYLIB_SYMBOL_POINTERS" } // 0x10 + { 0, /*FIXME??*/ "S_LAZY_DYLIB_SYMBOL_POINTERS" }, // 0x10 + { "thread_local_regular", "S_THREAD_LOCAL_REGULAR" }, // 0x11 + { "thread_bss", "S_THREAD_LOCAL_ZEROFILL" }, // 0x12 + { "thread_local_variables", "S_THREAD_LOCAL_VARIABLES" }, // 0x13 + { "thread_local_variable_pointers", + "S_THREAD_LOCAL_VARIABLE_POINTERS" }, // 0x14 + { "thread_local_init_function_pointers", + "S_THREAD_LOCAL_INIT_FUNCTION_POINTERS"}, // 0x15 }; Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=103974&r1=103973&r2=103974&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original) +++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Mon May 17 16:02:07 2010 @@ -222,7 +222,8 @@ bool isVirtualSection(const MCSection &Section) const { const MCSectionMachO &SMO = static_cast(Section); return (SMO.getType() == MCSectionMachO::S_ZEROFILL || - SMO.getType() == MCSectionMachO::S_GB_ZEROFILL); + SMO.getType() == MCSectionMachO::S_GB_ZEROFILL || + SMO.getType() == MCSectionMachO::S_THREAD_LOCAL_ZEROFILL); } }; From stoklund at 2pi.dk Mon May 17 16:02:08 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 17 May 2010 21:02:08 -0000 Subject: [llvm-commits] [llvm] r103975 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp Message-ID: <20100517210208.979183128018@llvm.org> Author: stoklund Date: Mon May 17 16:02:08 2010 New Revision: 103975 URL: http://llvm.org/viewvc/llvm-project?rev=103975&view=rev Log: Pull the UsedInInstr.test() calls into calcSpillCost() and remember aliases. This fixes the miscompilations of MultiSource/Applications/JM/l{en,de}cod. Clang now successfully self hosts in a debug build with the fast register allocator. Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=103975&r1=103974&r2=103975&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Mon May 17 16:02:08 2010 @@ -381,6 +381,8 @@ // can be allocated directly. // Returns spillImpossible when PhysReg or an alias can't be spilled. unsigned RAFast::calcSpillCost(unsigned PhysReg) const { + if (UsedInInstr.test(PhysReg)) + return spillImpossible; switch (unsigned VirtReg = PhysRegState[PhysReg]) { case regDisabled: break; @@ -396,6 +398,8 @@ unsigned Cost = 0; for (const unsigned *AS = TRI->getAliasSet(PhysReg); unsigned Alias = *AS; ++AS) { + if (UsedInInstr.test(Alias)) + return spillImpossible; switch (unsigned VirtReg = PhysRegState[Alias]) { case regDisabled: break; @@ -436,14 +440,11 @@ // Ignore invalid hints. if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || - !RC->contains(Hint) || UsedInInstr.test(Hint) || - !Allocatable.test(Hint))) + !RC->contains(Hint) || !Allocatable.test(Hint))) Hint = 0; // Take hint when possible. if (Hint) { - assert(RC->contains(Hint) && !UsedInInstr.test(Hint) && - Allocatable.test(Hint) && "Invalid hint should have been cleared"); switch(calcSpillCost(Hint)) { default: definePhysReg(MI, Hint, regFree); @@ -470,7 +471,6 @@ unsigned BestReg = 0, BestCost = spillImpossible; for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { - if (UsedInInstr.test(*I)) continue; unsigned Cost = calcSpillCost(*I); // Cost is 0 when all aliases are already disabled. if (Cost == 0) From isanbard at gmail.com Mon May 17 16:06:04 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 May 2010 21:06:04 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r103976 - /llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Message-ID: <20100517210604.B2B51312800A@llvm.org> Author: void Date: Mon May 17 16:06:04 2010 New Revision: 103976 URL: http://llvm.org/viewvc/llvm-project?rev=103976&view=rev Log: Turn on "--disable-non-leaf-fp-elim" if -momit-leaf-frame-pointer is specified. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/i386.h?rev=103976&r1=103975&r2=103976&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/i386.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Mon May 17 16:06:04 2010 @@ -3933,33 +3933,31 @@ (ISDIGIT (*nm) ? reg_names[REG_NUM] : nm); }) /* Propagate code model setting to backend */ -/* - FIXME: (See ) This option was mis-compiling a library. - - if (TARGET_OMIT_LEAF_FRAME_POINTER) - argvec.push_back("--disable-non-leaf-fp-elim"); -*/ -#define LLVM_SET_MACHINE_OPTIONS(argvec) \ - switch (ix86_cmodel) { \ - default: \ - sorry ("code model %<%s%> not supported yet", ix86_cmodel_string); \ - break; \ - case CM_SMALL: \ - case CM_SMALL_PIC: \ - argvec.push_back("--code-model=small"); \ - break; \ - case CM_KERNEL: \ - argvec.push_back("--code-model=kernel"); \ - break; \ - case CM_MEDIUM: \ - case CM_MEDIUM_PIC: \ - argvec.push_back("--code-model=medium"); \ - break; \ - case CM_32: \ - argvec.push_back("--code-model=default"); \ - break; \ - } - +#define LLVM_SET_MACHINE_OPTIONS(argvec) \ + do { \ + switch (ix86_cmodel) { \ + default: \ + sorry ("code model %<%s%> not supported yet", \ + ix86_cmodel_string); \ + break; \ + case CM_SMALL: \ + case CM_SMALL_PIC: \ + argvec.push_back("--code-model=small"); \ + break; \ + case CM_KERNEL: \ + argvec.push_back("--code-model=kernel"); \ + break; \ + case CM_MEDIUM: \ + case CM_MEDIUM_PIC: \ + argvec.push_back("--code-model=medium"); \ + break; \ + case CM_32: \ + argvec.push_back("--code-model=default"); \ + break; \ + } \ + if (TARGET_OMIT_LEAF_FRAME_POINTER) \ + argvec.push_back("--disable-non-leaf-fp-elim"); \ + } while (0) #endif /* ENABLE_LLVM */ /* LLVM LOCAL end */ From daniel at zuster.org Mon May 17 16:20:00 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 17 May 2010 21:20:00 -0000 Subject: [llvm-commits] [llvm] r103979 - in /llvm/trunk: lib/MC/MCMachOStreamer.cpp test/MC/MachO/string-table.s Message-ID: <20100517212000.1F685312800A@llvm.org> Author: ddunbar Date: Mon May 17 16:19:59 2010 New Revision: 103979 URL: http://llvm.org/viewvc/llvm-project?rev=103979&view=rev Log: MC/Mach-O: Reverse order of SymbolData scanning when emitting instructions. - This fixes a string table mismatch with 'as' when two new symbols are defined in a single instruction. Added: llvm/trunk/test/MC/MachO/string-table.s Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=103979&r1=103978&r2=103979&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Mon May 17 16:19:59 2010 @@ -414,7 +414,7 @@ void MCMachOStreamer::EmitInstruction(const MCInst &Inst) { // Scan for values. - for (unsigned i = 0; i != Inst.getNumOperands(); ++i) + for (unsigned i = Inst.getNumOperands(); i--; ) if (Inst.getOperand(i).isExpr()) AddValueSymbols(Inst.getOperand(i).getExpr()); Added: llvm/trunk/test/MC/MachO/string-table.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/string-table.s?rev=103979&view=auto ============================================================================== --- llvm/trunk/test/MC/MachO/string-table.s (added) +++ llvm/trunk/test/MC/MachO/string-table.s Mon May 17 16:19:59 2010 @@ -0,0 +1,100 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + + movl $a, b + +// CHECK: ('cputype', 7) +// CHECK: ('cpusubtype', 3) +// CHECK: ('filetype', 1) +// CHECK: ('num_load_commands', 1) +// CHECK: ('load_commands_size', 228) +// CHECK: ('flag', 0) +// CHECK: ('load_commands', [ +// CHECK: # Load Command 0 +// CHECK: (('command', 1) +// CHECK: ('size', 124) +// CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('vm_addr', 0) +// CHECK: ('vm_size', 10) +// CHECK: ('file_offset', 256) +// CHECK: ('file_size', 10) +// CHECK: ('maxprot', 7) +// CHECK: ('initprot', 7) +// CHECK: ('num_sections', 1) +// CHECK: ('flags', 0) +// CHECK: ('sections', [ +// CHECK: # Section 0 +// CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 10) +// CHECK: ('offset', 256) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 268) +// CHECK: ('num_reloc', 2) +// CHECK: ('flags', 0x80000400) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: # Relocation 0 +// CHECK: (('word-0', 0x6), +// CHECK: ('word-1', 0xc000000)), +// CHECK: # Relocation 1 +// CHECK: (('word-0', 0x2), +// CHECK: ('word-1', 0xc000001)), +// CHECK: ]) +// CHECK: ('_section_data', '\xc7\x05\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 1 +// CHECK: (('command', 2) +// CHECK: ('size', 24) +// CHECK: ('symoff', 284) +// CHECK: ('nsyms', 2) +// CHECK: ('stroff', 308) +// CHECK: ('strsize', 8) +// CHECK: ('_string_data', '\x00a\x00b\x00\x00\x00\x00') +// CHECK: ('_symbols', [ +// CHECK: # Symbol 0 +// CHECK: (('n_strx', 1) +// CHECK: ('n_type', 0x1) +// CHECK: ('n_sect', 0) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'a') +// CHECK: ), +// CHECK: # Symbol 1 +// CHECK: (('n_strx', 3) +// CHECK: ('n_type', 0x1) +// CHECK: ('n_sect', 0) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'b') +// CHECK: ), +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 2 +// CHECK: (('command', 11) +// CHECK: ('size', 80) +// CHECK: ('ilocalsym', 0) +// CHECK: ('nlocalsym', 0) +// CHECK: ('iextdefsym', 0) +// CHECK: ('nextdefsym', 0) +// CHECK: ('iundefsym', 0) +// CHECK: ('nundefsym', 2) +// CHECK: ('tocoff', 0) +// CHECK: ('ntoc', 0) +// CHECK: ('modtaboff', 0) +// CHECK: ('nmodtab', 0) +// CHECK: ('extrefsymoff', 0) +// CHECK: ('nextrefsyms', 0) +// CHECK: ('indirectsymoff', 0) +// CHECK: ('nindirectsyms', 0) +// CHECK: ('extreloff', 0) +// CHECK: ('nextrel', 0) +// CHECK: ('locreloff', 0) +// CHECK: ('nlocrel', 0) +// CHECK: ('_indirect_symbols', [ +// CHECK: ]) +// CHECK: ), +// CHECK: ]) From daniel at zuster.org Mon May 17 16:54:26 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 17 May 2010 21:54:26 -0000 Subject: [llvm-commits] [llvm] r103980 - in /llvm/trunk: include/llvm/MC/MCSection.h include/llvm/MC/MCSectionCOFF.h include/llvm/MC/MCSectionELF.h include/llvm/MC/MCSectionMachO.h lib/MC/MCSectionMachO.cpp lib/Target/PIC16/PIC16Section.h Message-ID: <20100517215426.DE9CF312800A@llvm.org> Author: ddunbar Date: Mon May 17 16:54:26 2010 New Revision: 103980 URL: http://llvm.org/viewvc/llvm-project?rev=103980&view=rev Log: MC: Add dyn_cast support to MCSection. - Of questionable utility, since in general anything which wants to do this should probably be within a target specific hook, which can rely on the sections being of the appropriate type. However, it can be useful for short term hacks. Modified: llvm/trunk/include/llvm/MC/MCSection.h llvm/trunk/include/llvm/MC/MCSectionCOFF.h llvm/trunk/include/llvm/MC/MCSectionELF.h llvm/trunk/include/llvm/MC/MCSectionMachO.h llvm/trunk/lib/MC/MCSectionMachO.cpp llvm/trunk/lib/Target/PIC16/PIC16Section.h Modified: llvm/trunk/include/llvm/MC/MCSection.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSection.h?rev=103980&r1=103979&r2=103980&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSection.h (original) +++ llvm/trunk/include/llvm/MC/MCSection.h Mon May 17 16:54:26 2010 @@ -17,6 +17,7 @@ #include #include "llvm/ADT/StringRef.h" #include "llvm/MC/SectionKind.h" +#include "llvm/Support/Casting.h" namespace llvm { class MCContext; @@ -27,15 +28,27 @@ /// section in the current translation unit. The MCContext class uniques and /// creates these. class MCSection { + public: + enum SectionVariant { + SV_COFF = 0, + SV_ELF, + SV_MachO, + SV_PIC16 + }; + + private: MCSection(const MCSection&); // DO NOT IMPLEMENT void operator=(const MCSection&); // DO NOT IMPLEMENT protected: - MCSection(SectionKind K) : Kind(K) {} + MCSection(SectionVariant V, SectionKind K) : Variant(V), Kind(K) {} + SectionVariant Variant; SectionKind Kind; public: virtual ~MCSection(); SectionKind getKind() const { return Kind; } + + SectionVariant getVariant() const { return Variant; } virtual void PrintSwitchToSection(const MCAsmInfo &MAI, raw_ostream &OS) const = 0; @@ -47,6 +60,8 @@ virtual bool isBaseAddressKnownZero() const { return false; } + + static bool classof(const MCSection *) { return true; } }; } // end namespace llvm Modified: llvm/trunk/include/llvm/MC/MCSectionCOFF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSectionCOFF.h?rev=103980&r1=103979&r2=103980&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSectionCOFF.h (original) +++ llvm/trunk/include/llvm/MC/MCSectionCOFF.h Mon May 17 16:54:26 2010 @@ -35,8 +35,8 @@ friend class MCContext; MCSectionCOFF(StringRef Section, unsigned Characteristics, int Selection, SectionKind K) - : MCSection(K), SectionName(Section), Characteristics(Characteristics), - Selection (Selection) { + : MCSection(SV_COFF, K), SectionName(Section), + Characteristics(Characteristics), Selection (Selection) { assert ((Characteristics & 0x00F00000) == 0 && "alignment must not be set upon section creation"); } @@ -103,6 +103,11 @@ virtual void PrintSwitchToSection(const MCAsmInfo &MAI, raw_ostream &OS) const; + + static bool classof(const MCSection *S) { + return S->getVariant() == SV_COFF; + } + static bool classof(const MCSectionCOFF *) { return true; } }; } // end namespace llvm Modified: llvm/trunk/include/llvm/MC/MCSectionELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSectionELF.h?rev=103980&r1=103979&r2=103980&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSectionELF.h (original) +++ llvm/trunk/include/llvm/MC/MCSectionELF.h Mon May 17 16:54:26 2010 @@ -40,7 +40,7 @@ friend class MCContext; MCSectionELF(StringRef Section, unsigned type, unsigned flags, SectionKind K, bool isExplicit) - : MCSection(K), SectionName(Section), Type(type), Flags(flags), + : MCSection(SV_ELF, K), SectionName(Section), Type(type), Flags(flags), IsExplicit(isExplicit) {} ~MCSectionELF(); public: @@ -178,6 +178,11 @@ virtual bool isBaseAddressKnownZero() const { return (getFlags() & SHF_ALLOC) == 0; } + + static bool classof(const MCSection *S) { + return S->getVariant() == SV_ELF; + } + static bool classof(const MCSectionELF *) { return true; } }; } // end namespace llvm Modified: llvm/trunk/include/llvm/MC/MCSectionMachO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSectionMachO.h?rev=103980&r1=103979&r2=103980&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSectionMachO.h (original) +++ llvm/trunk/include/llvm/MC/MCSectionMachO.h Mon May 17 16:54:26 2010 @@ -165,6 +165,11 @@ virtual void PrintSwitchToSection(const MCAsmInfo &MAI, raw_ostream &OS) const; + + static bool classof(const MCSection *S) { + return S->getVariant() == SV_MachO; + } + static bool classof(const MCSectionMachO *) { return true; } }; } // end namespace llvm Modified: llvm/trunk/lib/MC/MCSectionMachO.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCSectionMachO.cpp?rev=103980&r1=103979&r2=103980&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCSectionMachO.cpp (original) +++ llvm/trunk/lib/MC/MCSectionMachO.cpp Mon May 17 16:54:26 2010 @@ -73,7 +73,7 @@ MCSectionMachO::MCSectionMachO(StringRef Segment, StringRef Section, unsigned TAA, unsigned reserved2, SectionKind K) - : MCSection(K), TypeAndAttributes(TAA), Reserved2(reserved2) { + : MCSection(SV_MachO, K), TypeAndAttributes(TAA), Reserved2(reserved2) { assert(Segment.size() <= 16 && Section.size() <= 16 && "Segment or section string too long"); for (unsigned i = 0; i != 16; ++i) { Modified: llvm/trunk/lib/Target/PIC16/PIC16Section.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16Section.h?rev=103980&r1=103979&r2=103980&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16Section.h (original) +++ llvm/trunk/lib/Target/PIC16/PIC16Section.h Mon May 17 16:54:26 2010 @@ -44,7 +44,8 @@ unsigned Size; PIC16Section(StringRef name, SectionKind K, StringRef addr, int color) - : MCSection(K), Name(name), Address(addr), Color(color), Size(0) { + : MCSection(SV_PIC16, K), Name(name), Address(addr), + Color(color), Size(0) { } public: @@ -86,6 +87,11 @@ /// to a section. virtual void PrintSwitchToSection(const MCAsmInfo &MAI, raw_ostream &OS) const; + + static bool classof(const MCSection *S) { + return S->getVariant() == SV_PIC16; + } + static bool classof(const PIC16Section *) { return true; } }; } // end namespace llvm From daniel at zuster.org Mon May 17 16:54:30 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 17 May 2010 21:54:30 -0000 Subject: [llvm-commits] [llvm] r103981 - in /llvm/trunk: lib/MC/MCParser/AsmParser.cpp test/MC/MachO/x86_32-optimal_nop.s Message-ID: <20100517215430.9BDA93128018@llvm.org> Author: ddunbar Date: Mon May 17 16:54:30 2010 New Revision: 103981 URL: http://llvm.org/viewvc/llvm-project?rev=103981&view=rev Log: MC/Mach-O/x86: Optimal nop sequences should only be used for the .text sections, not all sections in the text segment. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/test/MC/MachO/x86_32-optimal_nop.s Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=103981&r1=103980&r2=103981&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon May 17 16:54:30 2010 @@ -1178,10 +1178,8 @@ Lex(); - if (!HasFillExpr) { - // FIXME: Sometimes fill with nop. + if (!HasFillExpr) FillExpr = 0; - } // Compute alignment in bytes. if (IsPow2) { @@ -1209,14 +1207,21 @@ } } - // FIXME: hard code the parser to use EmitCodeAlignment for text when using - // the TextAlignFillValue. - if(Out.getCurrentSection()->getKind().isText() && - Lexer.getMAI().getTextAlignFillValue() == FillExpr) + // Check whether we should use optimal code alignment for this .align + // directive. + // + // FIXME: This should be using a target hook. + bool UseCodeAlign = false; + if (const MCSectionMachO *S = dyn_cast( + Out.getCurrentSection())) + UseCodeAlign = S->hasAttribute(MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS); + if ((!HasFillExpr || Lexer.getMAI().getTextAlignFillValue() == FillExpr) && + ValueSize == 1 && UseCodeAlign) { Out.EmitCodeAlignment(Alignment, MaxBytesToFill); - else + } else { // FIXME: Target specific behavior about how the "extra" bytes are filled. Out.EmitValueToAlignment(Alignment, FillExpr, ValueSize, MaxBytesToFill); + } return false; } Modified: llvm/trunk/test/MC/MachO/x86_32-optimal_nop.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/x86_32-optimal_nop.s?rev=103981&r1=103980&r2=103981&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/x86_32-optimal_nop.s (original) +++ llvm/trunk/test/MC/MachO/x86_32-optimal_nop.s Mon May 17 16:54:30 2010 @@ -150,24 +150,31 @@ .align 4, 0x90 ret + # Only the .text sections gets optimal nops. + .section __TEXT,__const +f0: + .byte 0 + .align 4, 0x90 + .long 0 + // CHECK: ('cputype', 7) // CHECK: ('cpusubtype', 3) // CHECK: ('filetype', 1) // CHECK: ('num_load_commands', 1) -// CHECK: ('load_commands_size', 124) +// CHECK: ('load_commands_size', 296) // CHECK: ('flag', 0) // CHECK: ('load_commands', [ // CHECK: # Load Command 0 // CHECK: (('command', 1) -// CHECK: ('size', 124) +// CHECK: ('size', 192) // CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('vm_addr', 0) -// CHECK: ('vm_size', 337) -// CHECK: ('file_offset', 152) -// CHECK: ('file_size', 337) +// CHECK: ('vm_size', 372) +// CHECK: ('file_offset', 324) +// CHECK: ('file_size', 372) // CHECK: ('maxprot', 7) // CHECK: ('initprot', 7) -// CHECK: ('num_sections', 1) +// CHECK: ('num_sections', 2) // CHECK: ('flags', 0) // CHECK: ('sections', [ // CHECK: # Section 0 @@ -175,7 +182,7 @@ // CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('address', 0) // CHECK: ('size', 337) -// CHECK: ('offset', 152) +// CHECK: ('offset', 324) // CHECK: ('alignment', 4) // CHECK: ('reloc_offset', 0) // CHECK: ('num_reloc', 0) @@ -186,6 +193,65 @@ // CHECK: ('_relocations', [ // CHECK: ]) // CHECK: ('_section_data', '\xc3\x90\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3f\x90\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\x0f\x1f\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\x0f\x1f@\x00\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\x0f\x1fD\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\xc3f\x0f\x1fD\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\x0f\x1f\x80\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\xc3\xc3\xc3\xc3\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\xc3\xc3\xc3f\x0f\x1f\x84\x00\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\xc3\xc3\xc3f\x0f\x1f\x84\x00\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\xc3\x0f\x1fD\x00\x00f\x0f\x1fD\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3f\x0f\x1fD\x00\x00f\x0f\x1fD\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00 \x00\x00\x00\x00\x00\x00\xc3\xc3\xc3f\x0f\x1fD\x00\x00\x0f\x1f\x80\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\x0f\x1f\x80\x00\x00\x00\x00\x0f\x1f\x80\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\x0f\x1f\x80\x00\x00\x00\x00\x0f\x1f\x84\x00\x00\x00\x00\x00\xc3') +// CHECK: # Section 1 +// CHECK: (('section_name', '__const\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 352) +// CHECK: ('size', 20) +// CHECK: ('offset', 676) +// CHECK: ('alignment', 4) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x0) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: ('_section_data', '\x00\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x00\x00\x00\x00') +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 1 +// CHECK: (('command', 2) +// CHECK: ('size', 24) +// CHECK: ('symoff', 696) +// CHECK: ('nsyms', 1) +// CHECK: ('stroff', 708) +// CHECK: ('strsize', 4) +// CHECK: ('_string_data', '\x00f0\x00') +// CHECK: ('_symbols', [ +// CHECK: # Symbol 0 +// CHECK: (('n_strx', 1) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 2) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 352) +// CHECK: ('_string', 'f0') +// CHECK: ), +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 2 +// CHECK: (('command', 11) +// CHECK: ('size', 80) +// CHECK: ('ilocalsym', 0) +// CHECK: ('nlocalsym', 1) +// CHECK: ('iextdefsym', 1) +// CHECK: ('nextdefsym', 0) +// CHECK: ('iundefsym', 1) +// CHECK: ('nundefsym', 0) +// CHECK: ('tocoff', 0) +// CHECK: ('ntoc', 0) +// CHECK: ('modtaboff', 0) +// CHECK: ('nmodtab', 0) +// CHECK: ('extrefsymoff', 0) +// CHECK: ('nextrefsyms', 0) +// CHECK: ('indirectsymoff', 0) +// CHECK: ('nindirectsyms', 0) +// CHECK: ('extreloff', 0) +// CHECK: ('nextrel', 0) +// CHECK: ('locreloff', 0) +// CHECK: ('nlocrel', 0) +// CHECK: ('_indirect_symbols', [ // CHECK: ]) // CHECK: ), // CHECK: ]) From evan.cheng at apple.com Mon May 17 16:54:51 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 17 May 2010 21:54:51 -0000 Subject: [llvm-commits] [llvm] r103982 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20100517215451.2913D312800A@llvm.org> Author: evancheng Date: Mon May 17 16:54:50 2010 New Revision: 103982 URL: http://llvm.org/viewvc/llvm-project?rev=103982&view=rev Log: vmov of immediates are trivially re-materializable. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=103982&r1=103981&r2=103982&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon May 17 16:54:50 2010 @@ -2862,6 +2862,7 @@ // Note: Some of the cmode bits in the following VMOV instructions need to // be encoded based on the immed values. +let isReMaterializable = 1 in { def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst), (ins h8imm:$SIMM), IIC_VMOVImm, "vmov", "i8", "$dst, $SIMM", "", @@ -2897,6 +2898,7 @@ (ins h64imm:$SIMM), IIC_VMOVImm, "vmov", "i64", "$dst, $SIMM", "", [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>; +} // isReMaterializable // VMOV : Vector Get Lane (move scalar to ARM core register) From evan.cheng at apple.com Mon May 17 17:09:49 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 17 May 2010 22:09:49 -0000 Subject: [llvm-commits] [llvm] r103984 - in /llvm/trunk: lib/CodeGen/TwoAddressInstructionPass.cpp test/CodeGen/ARM/reg_sequence.ll Message-ID: <20100517220949.5FC15312800A@llvm.org> Author: evancheng Date: Mon May 17 17:09:49 2010 New Revision: 103984 URL: http://llvm.org/viewvc/llvm-project?rev=103984&view=rev Log: Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def. Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=103984&r1=103983&r2=103984&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original) +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Mon May 17 17:09:49 2010 @@ -1238,6 +1238,7 @@ llvm_unreachable(0); } + bool IsImpDef = true; SmallVector RealSrcs; SmallSet Seen; for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { @@ -1253,6 +1254,7 @@ DefMI->eraseFromParent(); continue; } + IsImpDef = false; // Remember EXTRACT_SUBREG sources. These might be candidate for // coalescing. @@ -1297,8 +1299,15 @@ UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI); } - DEBUG(dbgs() << "Eliminated: " << *MI); - MI->eraseFromParent(); + if (IsImpDef) { + DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF"); + MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); + for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j) + MI->RemoveOperand(j); + } else { + DEBUG(dbgs() << "Eliminated: " << *MI); + MI->eraseFromParent(); + } // Try coalescing some EXTRACT_SUBREG instructions. CoalesceExtSubRegs(RealSrcs, DstReg); Modified: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=103984&r1=103983&r2=103984&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (original) +++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Mon May 17 17:09:49 2010 @@ -185,6 +185,50 @@ ret void } +; PR7156 +define arm_aapcs_vfpcc i32 @t8() nounwind { +; CHECK: t8: +; CHECK: vrsqrte.f32 q0, q0 +bb.nph55.bb.nph55.split_crit_edge: + br label %bb3 + +bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge + br i1 undef, label %bb5, label %bb3 + +bb5: ; preds = %bb3 + br label %bb.i25 + +bb.i25: ; preds = %bb.i25, %bb5 + %0 = shufflevector <2 x float> undef, <2 x float> undef, <4 x i32> ; <<4 x float>> [#uses=1] + %1 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %0) nounwind ; <<4 x float>> [#uses=1] + %2 = fmul <4 x float> %1, undef ; <<4 x float>> [#uses=1] + %3 = fmul <4 x float> undef, %2 ; <<4 x float>> [#uses=1] + %tmp26.i = bitcast <4 x float> %3 to <2 x double> ; <<2 x double>> [#uses=1] + %4 = extractelement <2 x double> %tmp26.i, i32 0 ; [#uses=1] + %5 = bitcast double %4 to <2 x float> ; <<2 x float>> [#uses=1] + %6 = extractelement <2 x float> %5, i32 1 ; [#uses=1] + store float %6, float* undef, align 4 + br i1 undef, label %bb6, label %bb.i25 + +bb6: ; preds = %bb.i25 + br i1 undef, label %bb7, label %bb14 + +bb7: ; preds = %bb6 + br label %bb.i49 + +bb.i49: ; preds = %bb.i49, %bb7 + br i1 undef, label %bb.i19, label %bb.i49 + +bb.i19: ; preds = %bb.i19, %bb.i49 + br i1 undef, label %exit, label %bb.i19 + +exit: ; preds = %bb.i19 + unreachable + +bb14: ; preds = %bb6 + ret i32 0 +} + declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*) nounwind readonly declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*) nounwind readonly @@ -209,4 +253,6 @@ declare void @llvm.arm.neon.vst2.v4i32(i8*, <4 x i32>, <4 x i32>) nounwind +declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone + declare void @llvm.trap() nounwind From echristo at apple.com Mon May 17 17:53:55 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 17 May 2010 22:53:55 -0000 Subject: [llvm-commits] [llvm] r103985 - in /llvm/trunk: include/llvm/CodeGen/TargetLoweringObjectFileImpl.h include/llvm/MC/MCSectionMachO.h lib/CodeGen/TargetLoweringObjectFileImpl.cpp lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/directive_tbss.s test/MC/AsmParser/directive_tdata.s test/MC/AsmParser/directive_thread_init_func.s test/MC/AsmParser/directive_tlv.s Message-ID: <20100517225355.90D2F312800A@llvm.org> Author: echristo Date: Mon May 17 17:53:55 2010 New Revision: 103985 URL: http://llvm.org/viewvc/llvm-project?rev=103985&view=rev Log: More data/parsing support for tls directives. Add a few more testcases and cleanup comments as well. Added: llvm/trunk/test/MC/AsmParser/directive_tdata.s llvm/trunk/test/MC/AsmParser/directive_thread_init_func.s llvm/trunk/test/MC/AsmParser/directive_tlv.s Modified: llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h llvm/trunk/include/llvm/MC/MCSectionMachO.h llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/test/MC/AsmParser/directive_tbss.s Modified: llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h?rev=103985&r1=103984&r2=103985&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h (original) +++ llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h Mon May 17 17:53:55 2010 @@ -84,19 +84,23 @@ class TargetLoweringObjectFileMachO : public TargetLoweringObjectFile { - /// TLSDataSection - Section directive for Thread Local data. + /// TLSDataSection - Section for thread local data. /// const MCSection *TLSDataSection; // Defaults to ".tdata". - /// TLSBSSSection - Section directive for Thread Local uninitialized data. + /// TLSBSSSection - Section for thread local uninitialized data. /// const MCSection *TLSBSSSection; // Defaults to ".tbss". - /// TLSTLVSection - Section directive for Thread Local structure infomation. + /// TLSTLVSection - Section for thread local structure infomation. /// Contains the source code name of the variable, visibility and a pointer /// to the initial value (.tdata or .tbss). const MCSection *TLSTLVSection; // Defaults to ".tlv". + /// TLSThreadInitSection - Section for thread local data initialization + /// functions. + const MCSection *TLSThreadInitSection; // Defaults to ".thread_init_func". + const MCSection *CStringSection; const MCSection *UStringSection; const MCSection *TextCoalSection; Modified: llvm/trunk/include/llvm/MC/MCSectionMachO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSectionMachO.h?rev=103985&r1=103984&r2=103985&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSectionMachO.h (original) +++ llvm/trunk/include/llvm/MC/MCSectionMachO.h Mon May 17 17:53:55 2010 @@ -98,7 +98,7 @@ S_THREAD_LOCAL_VARIABLE_POINTERS = 0x14U, /// S_THREAD_LOCAL_INIT_FUNCTION_POINTERS - Section with thread local /// variable initialization pointers to functions. - S_THREAD_LOCAL_INIT_FUNCTION_POINTERS = 0x15, + S_THREAD_LOCAL_INIT_FUNCTION_POINTERS = 0x15U, LAST_KNOWN_SECTION_TYPE = S_THREAD_LOCAL_INIT_FUNCTION_POINTERS, Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=103985&r1=103984&r2=103985&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Mon May 17 17:53:55 2010 @@ -475,6 +475,12 @@ = getContext().getMachOSection("__DATA", "__thread_vars", MCSectionMachO::S_THREAD_LOCAL_VARIABLES, SectionKind::getDataRel()); + + TLSThreadInitSection + = getContext().getMachOSection("__DATA", "__thread_init", + MCSectionMachO::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS, + SectionKind::getDataRel()); + CStringSection // .cstring = getContext().getMachOSection("__TEXT", "__cstring", MCSectionMachO::S_CSTRING_LITERALS, Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=103985&r1=103984&r2=103985&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon May 17 17:53:55 2010 @@ -623,6 +623,16 @@ return ParseDirectiveSectionSwitch("__OBJC", "__selector_strs", MCSectionMachO::S_CSTRING_LITERALS); + if (IDVal == ".tdata") + return ParseDirectiveSectionSwitch("__DATA", "__thread_data", + MCSectionMachO::S_THREAD_LOCAL_REGULAR); + if (IDVal == ".tlv") + return ParseDirectiveSectionSwitch("__DATA", "__thread_vars", + MCSectionMachO::S_THREAD_LOCAL_VARIABLES); + if (IDVal == ".thread_init_func") + return ParseDirectiveSectionSwitch("__DATA", "__thread_init", + MCSectionMachO::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS); + // Assembler features if (IDVal == ".set") return ParseDirectiveSet(); Modified: llvm/trunk/test/MC/AsmParser/directive_tbss.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_tbss.s?rev=103985&r1=103984&r2=103985&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_tbss.s (original) +++ llvm/trunk/test/MC/AsmParser/directive_tbss.s Mon May 17 17:53:55 2010 @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple i386-unknown-darwin %s | FileCheck %s +# RUN: llvm-mc -triple x86_64-unknown-darwin %s | FileCheck %s # CHECK: .tbss _a$tlv$init, 4 # CHECK: .tbss _b$tlv$init, 4, 3 Added: llvm/trunk/test/MC/AsmParser/directive_tdata.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_tdata.s?rev=103985&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_tdata.s (added) +++ llvm/trunk/test/MC/AsmParser/directive_tdata.s Mon May 17 17:53:55 2010 @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64-unknown-darwin %s | FileCheck %s + +# CHECK: __DATA,__thread_data,thread_local_regular +# CHECK: _a$tlv$init: +# CHECK: .quad 4 + + .tdata +_a$tlv$init: + .quad 4 Added: llvm/trunk/test/MC/AsmParser/directive_thread_init_func.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_thread_init_func.s?rev=103985&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_thread_init_func.s (added) +++ llvm/trunk/test/MC/AsmParser/directive_thread_init_func.s Mon May 17 17:53:55 2010 @@ -0,0 +1,7 @@ +# RUN: llvm-mc -triple x86_64-unknown-darwin %s | FileCheck %s + +# CHECK: __DATA,__thread_init,thread_local_init_function_pointers +# CHECK: .quad 0 + +.thread_init_func + .quad 0 Added: llvm/trunk/test/MC/AsmParser/directive_tlv.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_tlv.s?rev=103985&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_tlv.s (added) +++ llvm/trunk/test/MC/AsmParser/directive_tlv.s Mon May 17 17:53:55 2010 @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple x86_64-unknown-darwin %s | FileCheck %s + +# CHECK: __DATA,__thread_vars,thread_local_variables +# CHECK: .globl _a +# CHECK: _a: +# CHECK: .quad 0 + + .tlv +.globl _a +_a: + .quad 0 + .quad 0 + .quad 0 From isanbard at gmail.com Mon May 17 18:07:04 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 May 2010 23:07:04 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r103988 - in /llvm-gcc-4.2/trunk/gcc/config/i386: i386.c i386.h Message-ID: <20100517230704.38E17312800A@llvm.org> Author: void Date: Mon May 17 18:07:03 2010 New Revision: 103988 URL: http://llvm.org/viewvc/llvm-project?rev=103988&view=rev Log: Set "flag_omit_frame_pointer" to 3 if -momit-leaf-frame-pointer is specified. This is to make its value unique from any other -fomit-frame-pointer value. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.c llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/i386.c?rev=103988&r1=103987&r2=103988&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/i386.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/i386.c Mon May 17 18:07:03 2010 @@ -2081,7 +2081,7 @@ if (flag_omit_frame_pointer) target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER; else if (TARGET_OMIT_LEAF_FRAME_POINTER) - flag_omit_frame_pointer = 1; + flag_omit_frame_pointer = 3; /* If we're doing fast math, we don't care about comparison order wrt NaNs. This lets us use a shorter comparison sequence. */ Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/i386.h?rev=103988&r1=103987&r2=103988&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/i386.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Mon May 17 18:07:03 2010 @@ -3955,7 +3955,7 @@ argvec.push_back("--code-model=default"); \ break; \ } \ - if (TARGET_OMIT_LEAF_FRAME_POINTER) \ + if (flag_omit_frame_pointer == 3) \ argvec.push_back("--disable-non-leaf-fp-elim"); \ } while (0) #endif /* ENABLE_LLVM */ From enderby at apple.com Mon May 17 18:08:19 2010 From: enderby at apple.com (Kevin Enderby) Date: Mon, 17 May 2010 23:08:19 -0000 Subject: [llvm-commits] [llvm] r103989 - in /llvm/trunk: include/llvm/MC/MCContext.h include/llvm/MC/MCLabel.h lib/MC/CMakeLists.txt lib/MC/MCContext.cpp lib/MC/MCLabel.cpp lib/MC/MCParser/AsmLexer.cpp lib/MC/MCParser/AsmParser.cpp test/MC/MachO/direction_labels.s Message-ID: <20100517230819.C9FF1312800A@llvm.org> Author: enderby Date: Mon May 17 18:08:19 2010 New Revision: 103989 URL: http://llvm.org/viewvc/llvm-project?rev=103989&view=rev Log: Added support in MC for Directional Local Labels. Added: llvm/trunk/include/llvm/MC/MCLabel.h llvm/trunk/lib/MC/MCLabel.cpp llvm/trunk/test/MC/MachO/direction_labels.s Modified: llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/lib/MC/CMakeLists.txt llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/lib/MC/MCParser/AsmLexer.cpp llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=103989&r1=103988&r2=103989&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Mon May 17 18:08:19 2010 @@ -20,6 +20,7 @@ class MCExpr; class MCSection; class MCSymbol; + class MCLabel; class StringRef; class Twine; class MCSectionMachO; @@ -43,6 +44,15 @@ /// NextUniqueID - The next ID to dole out to an unnamed assembler temporary /// symbol. unsigned NextUniqueID; + + /// Instances of directional local labels. + DenseMap Instances; + /// NextInstance() creates the next instance of the directional local label + /// for the LocalLabelVal and adds it to the map if needed. + unsigned NextInstance(int64_t LocalLabelVal); + /// GetInstance() gets the current instance of the directional local label + /// for the LocalLabelVal and adds it to the map if needed. + unsigned GetInstance(int64_t LocalLabelVal); /// Allocator - Allocator object used for creating machine code objects. /// @@ -64,6 +74,14 @@ /// with a unique but unspecified name. MCSymbol *CreateTempSymbol(); + /// CreateDirectionalLocalSymbol - Create the defintion of a directional + /// local symbol for numbered label (used for "1:" defintions). + MCSymbol *CreateDirectionalLocalSymbol(int64_t LocalLabelVal); + + /// GetDirectionalLocalSymbol - Create and return a directional local + /// symbol for numbered label (used for "1b" or 1f" references). + MCSymbol *GetDirectionalLocalSymbol(int64_t LocalLabelVal, int bORf); + /// GetOrCreateSymbol - Lookup the symbol inside with the specified /// @p Name. If it exists, return it. If not, create a forward /// reference and return it. Added: llvm/trunk/include/llvm/MC/MCLabel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCLabel.h?rev=103989&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCLabel.h (added) +++ llvm/trunk/include/llvm/MC/MCLabel.h Mon May 17 18:08:19 2010 @@ -0,0 +1,56 @@ +//===- MCLabel.h - Machine Code Directional Local Labels --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of the MCLabel class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCLABEL_H +#define LLVM_MC_MCLABEL_H + +namespace llvm { + class MCContext; + class raw_ostream; + + /// MCLabel - Instances of this class represent a label name in the MC file, + /// and MCLabel are created and unique'd by the MCContext class. MCLabel + /// should only be constructed for valid instances in the object file. + class MCLabel { + // Instance - the instance number of this Directional Local Label + unsigned Instance; + + private: // MCContext creates and uniques these. + friend class MCContext; + MCLabel(unsigned instance) + : Instance(instance) {} + + MCLabel(const MCLabel&); // DO NOT IMPLEMENT + void operator=(const MCLabel&); // DO NOT IMPLEMENT + public: + /// getInstance - Get the current instance of this Directional Local Label. + unsigned getInstance() const { return Instance; } + + /// incInstance - Increment the current instance of this Directional Local + /// Label. + unsigned incInstance() { return ++Instance; } + + /// print - Print the value to the stream \arg OS. + void print(raw_ostream &OS) const; + + /// dump - Print the value to stderr. + void dump() const; + }; + + inline raw_ostream &operator<<(raw_ostream &OS, const MCLabel &Label) { + Label.print(OS); + return OS; + } +} // end namespace llvm + +#endif Modified: llvm/trunk/lib/MC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/CMakeLists.txt?rev=103989&r1=103988&r2=103989&view=diff ============================================================================== --- llvm/trunk/lib/MC/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/CMakeLists.txt Mon May 17 18:08:19 2010 @@ -10,6 +10,7 @@ MCExpr.cpp MCInst.cpp MCInstPrinter.cpp + MCLabel.cpp MCMachOStreamer.cpp MCNullStreamer.cpp MCObjectWriter.cpp Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=103989&r1=103988&r2=103989&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Mon May 17 18:08:19 2010 @@ -13,6 +13,7 @@ #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCSectionCOFF.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCLabel.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/Twine.h" using namespace llvm; @@ -71,6 +72,50 @@ "tmp" + Twine(NextUniqueID++)); } +unsigned MCContext::NextInstance(int64_t LocalLabelVal) { + unsigned Instance; + MCLabel *Label; + Label = Instances[LocalLabelVal]; + if (Label) { + Instance = Label->incInstance(); + } + else { + Instance = 1; + Label = new MCLabel(Instance); + Instances[LocalLabelVal] = Label; + } + return Instance; +} + +unsigned MCContext::GetInstance(int64_t LocalLabelVal) { + int Instance; + MCLabel *Label; + Label = Instances[LocalLabelVal]; + if (Label) { + Instance = Label->getInstance(); + } + else { + Instance = 0; + Label = new MCLabel(Instance); + Instances[LocalLabelVal] = Label; + } + return Instance; +} + +MCSymbol *MCContext::CreateDirectionalLocalSymbol(int64_t LocalLabelVal) { + return GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix()) + + Twine(LocalLabelVal) + + "\2" + + Twine(NextInstance(LocalLabelVal))); +} +MCSymbol *MCContext::GetDirectionalLocalSymbol(int64_t LocalLabelVal, + int bORf) { + return GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix()) + + Twine(LocalLabelVal) + + "\2" + + Twine(GetInstance(LocalLabelVal) + bORf)); +} + MCSymbol *MCContext::LookupSymbol(StringRef Name) const { return Symbols.lookup(Name); } Added: llvm/trunk/lib/MC/MCLabel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCLabel.cpp?rev=103989&view=auto ============================================================================== --- llvm/trunk/lib/MC/MCLabel.cpp (added) +++ llvm/trunk/lib/MC/MCLabel.cpp Mon May 17 18:08:19 2010 @@ -0,0 +1,21 @@ +//===- lib/MC/MCLabel.cpp - MCLabel implementation ----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCLabel.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" +using namespace llvm; + +void MCLabel::print(raw_ostream &OS) const { + OS << '"' << getInstance() << '"'; +} + +void MCLabel::dump() const { + print(dbgs()); +} Modified: llvm/trunk/lib/MC/MCParser/AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmLexer.cpp?rev=103989&r1=103988&r2=103989&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmLexer.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmLexer.cpp Mon May 17 18:08:19 2010 @@ -132,11 +132,6 @@ /// Decimal integer: [1-9][0-9]* /// TODO: FP literal. AsmToken AsmLexer::LexDigit() { - if (*CurPtr == ':') - return ReturnError(TokStart, "FIXME: local label not implemented"); - if (*CurPtr == 'f' || *CurPtr == 'b') - return ReturnError(TokStart, "FIXME: directional label not implemented"); - // Decimal integer: [1-9][0-9]* if (CurPtr[-1] != '0') { while (isdigit(*CurPtr)) @@ -158,6 +153,13 @@ if (*CurPtr == 'b') { ++CurPtr; + // See if we actually have "0b" as part of something like "jmp 0b\n" + if (CurPtr[0] == '\n') { + --CurPtr; + StringRef Result(TokStart, CurPtr - TokStart); + ++CurPtr; + return AsmToken(AsmToken::Integer, Result, 0); + } const char *NumStart = CurPtr; while (CurPtr[0] == '0' || CurPtr[0] == '1') ++CurPtr; Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=103989&r1=103988&r2=103989&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon May 17 18:08:19 2010 @@ -214,11 +214,28 @@ Res = MCSymbolRefExpr::Create(Sym, Variant, getContext()); return false; } - case AsmToken::Integer: - Res = MCConstantExpr::Create(getTok().getIntVal(), getContext()); + case AsmToken::Integer: { + SMLoc Loc = getTok().getLoc(); + int64_t IntVal = getTok().getIntVal(); + Res = MCConstantExpr::Create(IntVal, getContext()); EndLoc = Lexer.getLoc(); Lex(); // Eat token. + // Look for 'b' or 'f' following an Integer as a directional label + if (Lexer.getKind() == AsmToken::Identifier) { + StringRef IDVal = getTok().getString(); + if (IDVal == "f" || IDVal == "b"){ + MCSymbol *Sym = Ctx.GetDirectionalLocalSymbol(IntVal, + IDVal == "f" ? 1 : 0); + Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, + getContext()); + if(IDVal == "b" && Sym->isUndefined()) + return Error(Loc, "invalid reference to undefined symbol"); + EndLoc = Lexer.getLoc(); + Lex(); // Eat identifier. + } + } return false; + } case AsmToken::Dot: { // This is a '.' reference, which references the current PC. Emit a // temporary label to the streamer and refer to it. @@ -422,7 +439,25 @@ AsmToken ID = getTok(); SMLoc IDLoc = ID.getLoc(); StringRef IDVal; - if (ParseIdentifier(IDVal)) { + int64_t LocalLabelVal = -1; + // GUESS allow an integer followed by a ':' as a directional local label + if (Lexer.is(AsmToken::Integer)) { + LocalLabelVal = getTok().getIntVal(); + if (LocalLabelVal < 0) { + if (!TheCondState.Ignore) + return TokError("unexpected token at start of statement"); + IDVal = ""; + } + else { + IDVal = getTok().getString(); + Lex(); // Consume the integer token to be used as an identifier token. + if (Lexer.getKind() != AsmToken::Colon) { + if (!TheCondState.Ignore) + return TokError("unexpected token at start of statement"); + } + } + } + else if (ParseIdentifier(IDVal)) { if (!TheCondState.Ignore) return TokError("unexpected token at start of statement"); IDVal = ""; @@ -459,7 +494,11 @@ // FIXME: Diagnostics. Note the location of the definition as a label. // FIXME: This doesn't diagnose assignment to a symbol which has been // implicitly marked as external. - MCSymbol *Sym = CreateSymbol(IDVal); + MCSymbol *Sym; + if (LocalLabelVal == -1) + Sym = CreateSymbol(IDVal); + else + Sym = Ctx.CreateDirectionalLocalSymbol(LocalLabelVal); if (!Sym->isUndefined() || Sym->isVariable()) return Error(IDLoc, "invalid symbol redefinition"); Added: llvm/trunk/test/MC/MachO/direction_labels.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/direction_labels.s?rev=103989&view=auto ============================================================================== --- llvm/trunk/test/MC/MachO/direction_labels.s (added) +++ llvm/trunk/test/MC/MachO/direction_labels.s Mon May 17 18:08:19 2010 @@ -0,0 +1,92 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + +direction_labels: +10: nop + jmp 10b + nop + jmp 11f +11: nop + ret + +// CHECK: ('cputype', 7) +// CHECK: ('cpusubtype', 3) +// CHECK: ('filetype', 1) +// CHECK: ('num_load_commands', 1) +// CHECK: ('load_commands_size', 228) +// CHECK: ('flag', 0) +// CHECK: ('load_commands', [ +// CHECK: # Load Command 0 +// CHECK: (('command', 1) +// CHECK: ('size', 124) +// CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('vm_addr', 0) +// CHECK: ('vm_size', 8) +// CHECK: ('file_offset', 256) +// CHECK: ('file_size', 8) +// CHECK: ('maxprot', 7) +// CHECK: ('initprot', 7) +// CHECK: ('num_sections', 1) +// CHECK: ('flags', 0) +// CHECK: ('sections', [ +// CHECK: # Section 0 +// CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 8) +// CHECK: ('offset', 256) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x80000400) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: ('_section_data', '\x90\xeb\xfd\x90\xeb\x00\x90\xc3') +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 1 +// CHECK: (('command', 2) +// CHECK: ('size', 24) +// CHECK: ('symoff', 264) +// CHECK: ('nsyms', 1) +// CHECK: ('stroff', 276) +// CHECK: ('strsize', 20) +// CHECK: ('_string_data', '\x00direction_labels\x00\x00\x00') +// CHECK: ('_symbols', [ +// CHECK: # Symbol 0 +// CHECK: (('n_strx', 1) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', 'direction_labels') +// CHECK: ), +// CHECK: ]) +// CHECK: ), +// CHECK: # Load Command 2 +// CHECK: (('command', 11) +// CHECK: ('size', 80) +// CHECK: ('ilocalsym', 0) +// CHECK: ('nlocalsym', 1) +// CHECK: ('iextdefsym', 1) +// CHECK: ('nextdefsym', 0) +// CHECK: ('iundefsym', 1) +// CHECK: ('nundefsym', 0) +// CHECK: ('tocoff', 0) +// CHECK: ('ntoc', 0) +// CHECK: ('modtaboff', 0) +// CHECK: ('nmodtab', 0) +// CHECK: ('extrefsymoff', 0) +// CHECK: ('nextrefsyms', 0) +// CHECK: ('indirectsymoff', 0) +// CHECK: ('nindirectsyms', 0) +// CHECK: ('extreloff', 0) +// CHECK: ('nextrel', 0) +// CHECK: ('locreloff', 0) +// CHECK: ('nlocrel', 0) +// CHECK: ('_indirect_symbols', [ +// CHECK: ]) +// CHECK: ), +// CHECK: ]) From isanbard at gmail.com Mon May 17 18:09:50 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 May 2010 23:09:50 -0000 Subject: [llvm-commits] [llvm] r103990 - in /llvm/trunk/lib: CodeGen/SelectionDAG/SelectionDAGISel.cpp Target/TargetMachine.cpp Message-ID: <20100517230950.8C5DA312800A@llvm.org> Author: void Date: Mon May 17 18:09:50 2010 New Revision: 103990 URL: http://llvm.org/viewvc/llvm-project?rev=103990&view=rev Log: - Set the "HasCalls" flag after instruction selection is finished. - Change the logic DisableFramePointerElim() to check for the -disable-non-leaf-fp-elim before -disable-fp-elim. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/Target/TargetMachine.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=103990&r1=103989&r2=103990&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon May 17 18:09:50 2010 @@ -233,6 +233,24 @@ } } + // Determine if there are any calls in this machine function. + MachineFrameInfo *MFI = MF->getFrameInfo(); + if (!MFI->hasCalls()) { + for (MachineFunction::const_iterator + I = MF->begin(), E = MF->end(); I != E; ++I) { + const MachineBasicBlock *MBB = I; + for (MachineBasicBlock::const_iterator + II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { + const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); + if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) { + MFI->setHasCalls(true); + goto done; + } + } + } + done:; + } + // Release function-specific state. SDB and CurDAG are already cleared // at this point. FuncInfo->clear(); @@ -606,19 +624,6 @@ delete Scheduler; } - // Determine if there are any calls in this machine function. - MachineFrameInfo *MFI = MF->getFrameInfo(); - if (!MFI->hasCalls()) { - for (MachineBasicBlock::iterator - I = BB->begin(), E = BB->end(); I != E; ++I) { - const TargetInstrDesc &TID = TM.getInstrInfo()->get(I->getOpcode()); - if (I->isInlineAsm() || (TID.isCall() && !TID.isReturn())) { - MFI->setHasCalls(true); - break; - } - } - } - // Free the SelectionDAG state, now that we're finished with it. CurDAG->clear(); @@ -676,6 +681,7 @@ CurDAG->setRoot(Dummy.getValue()); } + DEBUG(errs() << "===== Instruction selection ends:\n"); PostprocessISelDAG(); Modified: llvm/trunk/lib/Target/TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=103990&r1=103989&r2=103990&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/TargetMachine.cpp Mon May 17 18:09:50 2010 @@ -273,13 +273,14 @@ /// DisableFramePointerElim - This returns true if frame pointer elimination /// optimization should be disabled for the given machine function. bool DisableFramePointerElim(const MachineFunction &MF) { - if (NoFramePointerElim) - return true; + // Check to see if we should eliminate non-leaf frame pointers and then + // check to see if we should eliminate all frame pointers. if (NoFramePointerElimNonLeaf) { const MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->hasCalls(); } - return false; + + return NoFramePointerElim; } /// LessPreciseFPMAD - This flag return true when -enable-fp-mad option From evan.cheng at apple.com Mon May 17 18:24:12 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 17 May 2010 23:24:12 -0000 Subject: [llvm-commits] [llvm] r103994 - in /llvm/trunk: lib/CodeGen/TwoAddressInstructionPass.cpp test/CodeGen/ARM/reg_sequence.ll Message-ID: <20100517232412.BEFD4312800A@llvm.org> Author: evancheng Date: Mon May 17 18:24:12 2010 New Revision: 103994 URL: http://llvm.org/viewvc/llvm-project?rev=103994&view=rev Log: Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions. Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=103994&r1=103993&r2=103994&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original) +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Mon May 17 18:24:12 2010 @@ -134,6 +134,7 @@ /// of the de-ssa process. This replaces sources of REG_SEQUENCE as /// sub-register references of the register defined by REG_SEQUENCE. bool EliminateRegSequences(); + public: static char ID; // Pass identification, replacement for typeid TwoAddressInstructionPass() : MachineFunctionPass(&ID) {} @@ -1216,6 +1217,17 @@ } } +static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq, + MachineRegisterInfo *MRI) { + for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg), + UE = MRI->use_end(); UI != UE; ++UI) { + MachineInstr *UseMI = &*UI; + if (UseMI != RegSeq && UseMI->isRegSequence()) + return true; + } + return false; +} + /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part /// of the de-ssa process. This replaces sources of REG_SEQUENCE as /// sub-register references of the register defined by REG_SEQUENCE. e.g. @@ -1261,7 +1273,9 @@ if (DefMI->isExtractSubreg()) RealSrcs.push_back(DefMI->getOperand(1).getReg()); - if (!Seen.insert(SrcReg) || MI->getParent() != DefMI->getParent()) { + if (!Seen.insert(SrcReg) || + MI->getParent() != DefMI->getParent() || + HasOtherRegSequenceUses(SrcReg, MI, MRI)) { // REG_SEQUENCE cannot have duplicated operands, add a copy. // Also add an copy if the source if live-in the block. We don't want // to end up with a partial-redef of a livein, e.g. Modified: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=103994&r1=103993&r2=103994&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (original) +++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Mon May 17 18:24:12 2010 @@ -229,6 +229,41 @@ ret i32 0 } +%0 = type { %1, %1, %1, %1 } +%1 = type { %2 } +%2 = type { <4 x float> } +%3 = type { %0, %1 } + +; PR7157 +define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { +; CHECK: t9: +; CHECK: vldr.64 +; CHECK-NEXT: vstmia r0, {d0,d1} +; CHECK-NEXT: vmov.i8 d1 +; CHECK-NEXT: vstmia r0, {d0,d1} + %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2] + %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> ; <<4 x float>> [#uses=1] + store <4 x float> %4, <4 x float>* undef, align 16 + %5 = shufflevector <2 x float> %3, <2 x float> zeroinitializer, <4 x i32> ; <<4 x float>> [#uses=1] + store <4 x float> %5, <4 x float>* undef, align 16 + br label %8 + +;